1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
199 static const arm_feature_set arm_ext_m =
200 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
201 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
202 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
203 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
204 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
205 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
207 static const arm_feature_set arm_arch_any = ARM_ANY;
208 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
210 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
211 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
213 static const arm_feature_set arm_cext_iwmmxt2 =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
215 static const arm_feature_set arm_cext_iwmmxt =
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
217 static const arm_feature_set arm_cext_xscale =
218 ARM_FEATURE (0, ARM_CEXT_XSCALE);
219 static const arm_feature_set arm_cext_maverick =
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
221 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
222 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
223 static const arm_feature_set fpu_vfp_ext_v1xd =
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
225 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
226 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
227 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
228 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
229 static const arm_feature_set fpu_vfp_ext_d32 =
230 ARM_FEATURE (0, FPU_VFP_EXT_D32);
231 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
233 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
234 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
235 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
236 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static const arm_feature_set fpu_vfp_ext_armv8 =
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
239 static const arm_feature_set fpu_neon_ext_armv8 =
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
241 static const arm_feature_set fpu_crypto_ext_armv8 =
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
337 enum neon_el_type type;
341 #define NEON_MAX_TYPE_ELS 4
345 struct neon_type_el el[NEON_MAX_TYPE_ELS];
349 enum it_instruction_type
354 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
355 if inside, should be the last one. */
356 NEUTRAL_IT_INSN, /* This could be either inside or outside,
357 i.e. BKPT and NOP. */
358 IT_INSN /* The IT insn has been parsed. */
361 /* The maximum number of operands we need. */
362 #define ARM_IT_MAX_OPERANDS 6
367 unsigned long instruction;
371 /* "uncond_value" is set to the value in place of the conditional field in
372 unconditional versions of the instruction, or -1 if nothing is
375 struct neon_type vectype;
376 /* This does not indicate an actual NEON instruction, only that
377 the mnemonic accepts neon-style type suffixes. */
379 /* Set to the opcode if the instruction needs relaxation.
380 Zero if the instruction is not relaxed. */
384 bfd_reloc_code_real_type type;
389 enum it_instruction_type it_insn_type;
395 struct neon_type_el vectype;
396 unsigned present : 1; /* Operand present. */
397 unsigned isreg : 1; /* Operand was a register. */
398 unsigned immisreg : 1; /* .imm field is a second register. */
399 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
400 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
401 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
402 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
403 instructions. This allows us to disambiguate ARM <-> vector insns. */
404 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
405 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
406 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
407 unsigned issingle : 1; /* Operand is VFP single-precision register. */
408 unsigned hasreloc : 1; /* Operand has relocation suffix. */
409 unsigned writeback : 1; /* Operand has trailing ! */
410 unsigned preind : 1; /* Preindexed address. */
411 unsigned postind : 1; /* Postindexed address. */
412 unsigned negative : 1; /* Index register was negated. */
413 unsigned shifted : 1; /* Shift applied to operation. */
414 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
415 } operands[ARM_IT_MAX_OPERANDS];
418 static struct arm_it inst;
420 #define NUM_FLOAT_VALS 8
422 const char * fp_const[] =
424 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
427 /* Number of littlenums required to hold an extended precision number. */
428 #define MAX_LITTLENUMS 6
430 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
440 #define CP_T_X 0x00008000
441 #define CP_T_Y 0x00400000
443 #define CONDS_BIT 0x00100000
444 #define LOAD_BIT 0x00100000
446 #define DOUBLE_LOAD_FLAG 0x00000001
450 const char * template_name;
454 #define COND_ALWAYS 0xE
458 const char * template_name;
462 struct asm_barrier_opt
464 const char * template_name;
466 const arm_feature_set arch;
469 /* The bit that distinguishes CPSR and SPSR. */
470 #define SPSR_BIT (1 << 22)
472 /* The individual PSR flag bits. */
473 #define PSR_c (1 << 16)
474 #define PSR_x (1 << 17)
475 #define PSR_s (1 << 18)
476 #define PSR_f (1 << 19)
481 bfd_reloc_code_real_type reloc;
486 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
487 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
492 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
495 /* Bits for DEFINED field in neon_typed_alias. */
496 #define NTA_HASTYPE 1
497 #define NTA_HASINDEX 2
499 struct neon_typed_alias
501 unsigned char defined;
503 struct neon_type_el eltype;
506 /* ARM register categories. This includes coprocessor numbers and various
507 architecture extensions' registers. */
534 /* Structure for a hash table entry for a register.
535 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
536 information which states whether a vector type or index is specified (for a
537 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
543 unsigned char builtin;
544 struct neon_typed_alias * neon;
547 /* Diagnostics used when we don't get a register of the expected type. */
548 const char * const reg_expected_msgs[] =
550 N_("ARM register expected"),
551 N_("bad or missing co-processor number"),
552 N_("co-processor register expected"),
553 N_("FPA register expected"),
554 N_("VFP single precision register expected"),
555 N_("VFP/Neon double precision register expected"),
556 N_("Neon quad precision register expected"),
557 N_("VFP single or double precision register expected"),
558 N_("Neon double or quad precision register expected"),
559 N_("VFP single, double or Neon quad precision register expected"),
560 N_("VFP system register expected"),
561 N_("Maverick MVF register expected"),
562 N_("Maverick MVD register expected"),
563 N_("Maverick MVFX register expected"),
564 N_("Maverick MVDX register expected"),
565 N_("Maverick MVAX register expected"),
566 N_("Maverick DSPSC register expected"),
567 N_("iWMMXt data register expected"),
568 N_("iWMMXt control register expected"),
569 N_("iWMMXt scalar register expected"),
570 N_("XScale accumulator register expected"),
573 /* Some well known registers that we refer to directly elsewhere. */
579 /* ARM instructions take 4bytes in the object file, Thumb instructions
585 /* Basic string to match. */
586 const char * template_name;
588 /* Parameters to instruction. */
589 unsigned int operands[8];
591 /* Conditional tag - see opcode_lookup. */
592 unsigned int tag : 4;
594 /* Basic instruction code. */
595 unsigned int avalue : 28;
597 /* Thumb-format instruction code. */
600 /* Which architecture variant provides this instruction. */
601 const arm_feature_set * avariant;
602 const arm_feature_set * tvariant;
604 /* Function to call to encode instruction in ARM format. */
605 void (* aencode) (void);
607 /* Function to call to encode instruction in Thumb format. */
608 void (* tencode) (void);
611 /* Defines for various bits that we will want to toggle. */
612 #define INST_IMMEDIATE 0x02000000
613 #define OFFSET_REG 0x02000000
614 #define HWOFFSET_IMM 0x00400000
615 #define SHIFT_BY_REG 0x00000010
616 #define PRE_INDEX 0x01000000
617 #define INDEX_UP 0x00800000
618 #define WRITE_BACK 0x00200000
619 #define LDM_TYPE_2_OR_3 0x00400000
620 #define CPSI_MMOD 0x00020000
622 #define LITERAL_MASK 0xf000f000
623 #define OPCODE_MASK 0xfe1fffff
624 #define V4_STR_BIT 0x00000020
626 #define T2_SUBS_PC_LR 0xf3de8f00
628 #define DATA_OP_SHIFT 21
630 #define T2_OPCODE_MASK 0xfe1fffff
631 #define T2_DATA_OP_SHIFT 21
633 #define A_COND_MASK 0xf0000000
634 #define A_PUSH_POP_OP_MASK 0x0fff0000
636 /* Opcodes for pushing/poping registers to/from the stack. */
637 #define A1_OPCODE_PUSH 0x092d0000
638 #define A2_OPCODE_PUSH 0x052d0004
639 #define A2_OPCODE_POP 0x049d0004
641 /* Codes to distinguish the arithmetic instructions. */
652 #define OPCODE_CMP 10
653 #define OPCODE_CMN 11
654 #define OPCODE_ORR 12
655 #define OPCODE_MOV 13
656 #define OPCODE_BIC 14
657 #define OPCODE_MVN 15
659 #define T2_OPCODE_AND 0
660 #define T2_OPCODE_BIC 1
661 #define T2_OPCODE_ORR 2
662 #define T2_OPCODE_ORN 3
663 #define T2_OPCODE_EOR 4
664 #define T2_OPCODE_ADD 8
665 #define T2_OPCODE_ADC 10
666 #define T2_OPCODE_SBC 11
667 #define T2_OPCODE_SUB 13
668 #define T2_OPCODE_RSB 14
670 #define T_OPCODE_MUL 0x4340
671 #define T_OPCODE_TST 0x4200
672 #define T_OPCODE_CMN 0x42c0
673 #define T_OPCODE_NEG 0x4240
674 #define T_OPCODE_MVN 0x43c0
676 #define T_OPCODE_ADD_R3 0x1800
677 #define T_OPCODE_SUB_R3 0x1a00
678 #define T_OPCODE_ADD_HI 0x4400
679 #define T_OPCODE_ADD_ST 0xb000
680 #define T_OPCODE_SUB_ST 0xb080
681 #define T_OPCODE_ADD_SP 0xa800
682 #define T_OPCODE_ADD_PC 0xa000
683 #define T_OPCODE_ADD_I8 0x3000
684 #define T_OPCODE_SUB_I8 0x3800
685 #define T_OPCODE_ADD_I3 0x1c00
686 #define T_OPCODE_SUB_I3 0x1e00
688 #define T_OPCODE_ASR_R 0x4100
689 #define T_OPCODE_LSL_R 0x4080
690 #define T_OPCODE_LSR_R 0x40c0
691 #define T_OPCODE_ROR_R 0x41c0
692 #define T_OPCODE_ASR_I 0x1000
693 #define T_OPCODE_LSL_I 0x0000
694 #define T_OPCODE_LSR_I 0x0800
696 #define T_OPCODE_MOV_I8 0x2000
697 #define T_OPCODE_CMP_I8 0x2800
698 #define T_OPCODE_CMP_LR 0x4280
699 #define T_OPCODE_MOV_HR 0x4600
700 #define T_OPCODE_CMP_HR 0x4500
702 #define T_OPCODE_LDR_PC 0x4800
703 #define T_OPCODE_LDR_SP 0x9800
704 #define T_OPCODE_STR_SP 0x9000
705 #define T_OPCODE_LDR_IW 0x6800
706 #define T_OPCODE_STR_IW 0x6000
707 #define T_OPCODE_LDR_IH 0x8800
708 #define T_OPCODE_STR_IH 0x8000
709 #define T_OPCODE_LDR_IB 0x7800
710 #define T_OPCODE_STR_IB 0x7000
711 #define T_OPCODE_LDR_RW 0x5800
712 #define T_OPCODE_STR_RW 0x5000
713 #define T_OPCODE_LDR_RH 0x5a00
714 #define T_OPCODE_STR_RH 0x5200
715 #define T_OPCODE_LDR_RB 0x5c00
716 #define T_OPCODE_STR_RB 0x5400
718 #define T_OPCODE_PUSH 0xb400
719 #define T_OPCODE_POP 0xbc00
721 #define T_OPCODE_BRANCH 0xe000
723 #define THUMB_SIZE 2 /* Size of thumb instruction. */
724 #define THUMB_PP_PC_LR 0x0100
725 #define THUMB_LOAD_BIT 0x0800
726 #define THUMB2_LOAD_BIT 0x00100000
728 #define BAD_ARGS _("bad arguments to instruction")
729 #define BAD_SP _("r13 not allowed here")
730 #define BAD_PC _("r15 not allowed here")
731 #define BAD_COND _("instruction cannot be conditional")
732 #define BAD_OVERLAP _("registers may not be the same")
733 #define BAD_HIREG _("lo register required")
734 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
735 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
736 #define BAD_BRANCH _("branch must be last instruction in IT block")
737 #define BAD_NOT_IT _("instruction not allowed in IT block")
738 #define BAD_FPU _("selected FPU does not support instruction")
739 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
740 #define BAD_IT_COND _("incorrect condition in IT block")
741 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
742 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
743 #define BAD_PC_ADDRESSING \
744 _("cannot use register index with PC-relative addressing")
745 #define BAD_PC_WRITEBACK \
746 _("cannot use writeback with PC-relative addressing")
747 #define BAD_RANGE _("branch out of range")
749 static struct hash_control * arm_ops_hsh;
750 static struct hash_control * arm_cond_hsh;
751 static struct hash_control * arm_shift_hsh;
752 static struct hash_control * arm_psr_hsh;
753 static struct hash_control * arm_v7m_psr_hsh;
754 static struct hash_control * arm_reg_hsh;
755 static struct hash_control * arm_reloc_hsh;
756 static struct hash_control * arm_barrier_opt_hsh;
758 /* Stuff needed to resolve the label ambiguity
767 symbolS * last_label_seen;
768 static int label_is_thumb_function_name = FALSE;
770 /* Literal pool structure. Held on a per-section
771 and per-sub-section basis. */
773 #define MAX_LITERAL_POOL_SIZE 1024
774 typedef struct literal_pool
776 expressionS literals [MAX_LITERAL_POOL_SIZE];
777 unsigned int next_free_entry;
783 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
785 struct literal_pool * next;
788 /* Pointer to a linked list of literal pools. */
789 literal_pool * list_of_pools = NULL;
792 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
794 static struct current_it now_it;
798 now_it_compatible (int cond)
800 return (cond & ~1) == (now_it.cc & ~1);
804 conditional_insn (void)
806 return inst.cond != COND_ALWAYS;
809 static int in_it_block (void);
811 static int handle_it_state (void);
813 static void force_automatic_it_block_close (void);
815 static void it_fsm_post_encode (void);
817 #define set_it_insn_type(type) \
820 inst.it_insn_type = type; \
821 if (handle_it_state () == FAIL) \
826 #define set_it_insn_type_nonvoid(type, failret) \
829 inst.it_insn_type = type; \
830 if (handle_it_state () == FAIL) \
835 #define set_it_insn_type_last() \
838 if (inst.cond == COND_ALWAYS) \
839 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
841 set_it_insn_type (INSIDE_IT_LAST_INSN); \
847 /* This array holds the chars that always start a comment. If the
848 pre-processor is disabled, these aren't very useful. */
849 const char comment_chars[] = "@";
851 /* This array holds the chars that only start a comment at the beginning of
852 a line. If the line seems to have the form '# 123 filename'
853 .line and .file directives will appear in the pre-processed output. */
854 /* Note that input_file.c hand checks for '#' at the beginning of the
855 first line of the input file. This is because the compiler outputs
856 #NO_APP at the beginning of its output. */
857 /* Also note that comments like this one will always work. */
858 const char line_comment_chars[] = "#";
860 const char line_separator_chars[] = ";";
862 /* Chars that can be used to separate mant
863 from exp in floating point numbers. */
864 const char EXP_CHARS[] = "eE";
866 /* Chars that mean this number is a floating point constant. */
870 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
872 /* Prefix characters that indicate the start of an immediate
874 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
876 /* Separator character handling. */
878 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
881 skip_past_char (char ** str, char c)
892 #define skip_past_comma(str) skip_past_char (str, ',')
894 /* Arithmetic expressions (possibly involving symbols). */
896 /* Return TRUE if anything in the expression is a bignum. */
899 walk_no_bignums (symbolS * sp)
901 if (symbol_get_value_expression (sp)->X_op == O_big)
904 if (symbol_get_value_expression (sp)->X_add_symbol)
906 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
907 || (symbol_get_value_expression (sp)->X_op_symbol
908 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
914 static int in_my_get_expression = 0;
916 /* Third argument to my_get_expression. */
917 #define GE_NO_PREFIX 0
918 #define GE_IMM_PREFIX 1
919 #define GE_OPT_PREFIX 2
920 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
921 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
922 #define GE_OPT_PREFIX_BIG 3
925 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
930 /* In unified syntax, all prefixes are optional. */
932 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
937 case GE_NO_PREFIX: break;
939 if (!is_immediate_prefix (**str))
941 inst.error = _("immediate expression requires a # prefix");
947 case GE_OPT_PREFIX_BIG:
948 if (is_immediate_prefix (**str))
954 memset (ep, 0, sizeof (expressionS));
956 save_in = input_line_pointer;
957 input_line_pointer = *str;
958 in_my_get_expression = 1;
959 seg = expression (ep);
960 in_my_get_expression = 0;
962 if (ep->X_op == O_illegal || ep->X_op == O_absent)
964 /* We found a bad or missing expression in md_operand(). */
965 *str = input_line_pointer;
966 input_line_pointer = save_in;
967 if (inst.error == NULL)
968 inst.error = (ep->X_op == O_absent
969 ? _("missing expression") :_("bad expression"));
974 if (seg != absolute_section
975 && seg != text_section
976 && seg != data_section
977 && seg != bss_section
978 && seg != undefined_section)
980 inst.error = _("bad segment");
981 *str = input_line_pointer;
982 input_line_pointer = save_in;
989 /* Get rid of any bignums now, so that we don't generate an error for which
990 we can't establish a line number later on. Big numbers are never valid
991 in instructions, which is where this routine is always called. */
992 if (prefix_mode != GE_OPT_PREFIX_BIG
993 && (ep->X_op == O_big
995 && (walk_no_bignums (ep->X_add_symbol)
997 && walk_no_bignums (ep->X_op_symbol))))))
999 inst.error = _("invalid constant");
1000 *str = input_line_pointer;
1001 input_line_pointer = save_in;
1005 *str = input_line_pointer;
1006 input_line_pointer = save_in;
1010 /* Turn a string in input_line_pointer into a floating point constant
1011 of type TYPE, and store the appropriate bytes in *LITP. The number
1012 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1013 returned, or NULL on OK.
1015 Note that fp constants aren't represent in the normal way on the ARM.
1016 In big endian mode, things are as expected. However, in little endian
1017 mode fp constants are big-endian word-wise, and little-endian byte-wise
1018 within the words. For example, (double) 1.1 in big endian mode is
1019 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1020 the byte sequence 99 99 f1 3f 9a 99 99 99.
1022 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1025 md_atof (int type, char * litP, int * sizeP)
1028 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1060 return _("Unrecognized or unsupported floating point constant");
1063 t = atof_ieee (input_line_pointer, type, words);
1065 input_line_pointer = t;
1066 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1068 if (target_big_endian)
1070 for (i = 0; i < prec; i++)
1072 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1073 litP += sizeof (LITTLENUM_TYPE);
1078 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1079 for (i = prec - 1; i >= 0; i--)
1081 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1082 litP += sizeof (LITTLENUM_TYPE);
1085 /* For a 4 byte float the order of elements in `words' is 1 0.
1086 For an 8 byte float the order is 1 0 3 2. */
1087 for (i = 0; i < prec; i += 2)
1089 md_number_to_chars (litP, (valueT) words[i + 1],
1090 sizeof (LITTLENUM_TYPE));
1091 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1092 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1093 litP += 2 * sizeof (LITTLENUM_TYPE);
1100 /* We handle all bad expressions here, so that we can report the faulty
1101 instruction in the error message. */
1103 md_operand (expressionS * exp)
1105 if (in_my_get_expression)
1106 exp->X_op = O_illegal;
1109 /* Immediate values. */
1111 /* Generic immediate-value read function for use in directives.
1112 Accepts anything that 'expression' can fold to a constant.
1113 *val receives the number. */
1116 immediate_for_directive (int *val)
1119 exp.X_op = O_illegal;
1121 if (is_immediate_prefix (*input_line_pointer))
1123 input_line_pointer++;
1127 if (exp.X_op != O_constant)
1129 as_bad (_("expected #constant"));
1130 ignore_rest_of_line ();
1133 *val = exp.X_add_number;
1138 /* Register parsing. */
1140 /* Generic register parser. CCP points to what should be the
1141 beginning of a register name. If it is indeed a valid register
1142 name, advance CCP over it and return the reg_entry structure;
1143 otherwise return NULL. Does not issue diagnostics. */
1145 static struct reg_entry *
1146 arm_reg_parse_multi (char **ccp)
1150 struct reg_entry *reg;
1152 #ifdef REGISTER_PREFIX
1153 if (*start != REGISTER_PREFIX)
1157 #ifdef OPTIONAL_REGISTER_PREFIX
1158 if (*start == OPTIONAL_REGISTER_PREFIX)
1163 if (!ISALPHA (*p) || !is_name_beginner (*p))
1168 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1170 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1180 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1181 enum arm_reg_type type)
1183 /* Alternative syntaxes are accepted for a few register classes. */
1190 /* Generic coprocessor register names are allowed for these. */
1191 if (reg && reg->type == REG_TYPE_CN)
1196 /* For backward compatibility, a bare number is valid here. */
1198 unsigned long processor = strtoul (start, ccp, 10);
1199 if (*ccp != start && processor <= 15)
1203 case REG_TYPE_MMXWC:
1204 /* WC includes WCG. ??? I'm not sure this is true for all
1205 instructions that take WC registers. */
1206 if (reg && reg->type == REG_TYPE_MMXWCG)
1217 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1218 return value is the register number or FAIL. */
1221 arm_reg_parse (char **ccp, enum arm_reg_type type)
1224 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1227 /* Do not allow a scalar (reg+index) to parse as a register. */
1228 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1231 if (reg && reg->type == type)
1234 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1241 /* Parse a Neon type specifier. *STR should point at the leading '.'
1242 character. Does no verification at this stage that the type fits the opcode
1249 Can all be legally parsed by this function.
1251 Fills in neon_type struct pointer with parsed information, and updates STR
1252 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1253 type, FAIL if not. */
1256 parse_neon_type (struct neon_type *type, char **str)
1263 while (type->elems < NEON_MAX_TYPE_ELS)
1265 enum neon_el_type thistype = NT_untyped;
1266 unsigned thissize = -1u;
1273 /* Just a size without an explicit type. */
1277 switch (TOLOWER (*ptr))
1279 case 'i': thistype = NT_integer; break;
1280 case 'f': thistype = NT_float; break;
1281 case 'p': thistype = NT_poly; break;
1282 case 's': thistype = NT_signed; break;
1283 case 'u': thistype = NT_unsigned; break;
1285 thistype = NT_float;
1290 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1296 /* .f is an abbreviation for .f32. */
1297 if (thistype == NT_float && !ISDIGIT (*ptr))
1302 thissize = strtoul (ptr, &ptr, 10);
1304 if (thissize != 8 && thissize != 16 && thissize != 32
1307 as_bad (_("bad size %d in type specifier"), thissize);
1315 type->el[type->elems].type = thistype;
1316 type->el[type->elems].size = thissize;
1321 /* Empty/missing type is not a successful parse. */
1322 if (type->elems == 0)
1330 /* Errors may be set multiple times during parsing or bit encoding
1331 (particularly in the Neon bits), but usually the earliest error which is set
1332 will be the most meaningful. Avoid overwriting it with later (cascading)
1333 errors by calling this function. */
1336 first_error (const char *err)
1342 /* Parse a single type, e.g. ".s32", leading period included. */
1344 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1347 struct neon_type optype;
1351 if (parse_neon_type (&optype, &str) == SUCCESS)
1353 if (optype.elems == 1)
1354 *vectype = optype.el[0];
1357 first_error (_("only one type should be specified for operand"));
1363 first_error (_("vector type expected"));
1375 /* Special meanings for indices (which have a range of 0-7), which will fit into
1378 #define NEON_ALL_LANES 15
1379 #define NEON_INTERLEAVE_LANES 14
1381 /* Parse either a register or a scalar, with an optional type. Return the
1382 register number, and optionally fill in the actual type of the register
1383 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1384 type/index information in *TYPEINFO. */
1387 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1388 enum arm_reg_type *rtype,
1389 struct neon_typed_alias *typeinfo)
1392 struct reg_entry *reg = arm_reg_parse_multi (&str);
1393 struct neon_typed_alias atype;
1394 struct neon_type_el parsetype;
1398 atype.eltype.type = NT_invtype;
1399 atype.eltype.size = -1;
1401 /* Try alternate syntax for some types of register. Note these are mutually
1402 exclusive with the Neon syntax extensions. */
1405 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1413 /* Undo polymorphism when a set of register types may be accepted. */
1414 if ((type == REG_TYPE_NDQ
1415 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1416 || (type == REG_TYPE_VFSD
1417 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1418 || (type == REG_TYPE_NSDQ
1419 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1420 || reg->type == REG_TYPE_NQ))
1421 || (type == REG_TYPE_MMXWC
1422 && (reg->type == REG_TYPE_MMXWCG)))
1423 type = (enum arm_reg_type) reg->type;
1425 if (type != reg->type)
1431 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1433 if ((atype.defined & NTA_HASTYPE) != 0)
1435 first_error (_("can't redefine type for operand"));
1438 atype.defined |= NTA_HASTYPE;
1439 atype.eltype = parsetype;
1442 if (skip_past_char (&str, '[') == SUCCESS)
1444 if (type != REG_TYPE_VFD)
1446 first_error (_("only D registers may be indexed"));
1450 if ((atype.defined & NTA_HASINDEX) != 0)
1452 first_error (_("can't change index for operand"));
1456 atype.defined |= NTA_HASINDEX;
1458 if (skip_past_char (&str, ']') == SUCCESS)
1459 atype.index = NEON_ALL_LANES;
1464 my_get_expression (&exp, &str, GE_NO_PREFIX);
1466 if (exp.X_op != O_constant)
1468 first_error (_("constant expression required"));
1472 if (skip_past_char (&str, ']') == FAIL)
1475 atype.index = exp.X_add_number;
1490 /* Like arm_reg_parse, but allow allow the following extra features:
1491 - If RTYPE is non-zero, return the (possibly restricted) type of the
1492 register (e.g. Neon double or quad reg when either has been requested).
1493 - If this is a Neon vector type with additional type information, fill
1494 in the struct pointed to by VECTYPE (if non-NULL).
1495 This function will fault on encountering a scalar. */
1498 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1499 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1501 struct neon_typed_alias atype;
1503 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1508 /* Do not allow regname(... to parse as a register. */
1512 /* Do not allow a scalar (reg+index) to parse as a register. */
1513 if ((atype.defined & NTA_HASINDEX) != 0)
1515 first_error (_("register operand expected, but got scalar"));
1520 *vectype = atype.eltype;
1527 #define NEON_SCALAR_REG(X) ((X) >> 4)
1528 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1530 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1531 have enough information to be able to do a good job bounds-checking. So, we
1532 just do easy checks here, and do further checks later. */
1535 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1539 struct neon_typed_alias atype;
1541 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1543 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1546 if (atype.index == NEON_ALL_LANES)
1548 first_error (_("scalar must have an index"));
1551 else if (atype.index >= 64 / elsize)
1553 first_error (_("scalar index out of range"));
1558 *type = atype.eltype;
1562 return reg * 16 + atype.index;
1565 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1568 parse_reg_list (char ** strp)
1570 char * str = * strp;
1574 /* We come back here if we get ranges concatenated by '+' or '|'. */
1589 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1591 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1601 first_error (_("bad range in register list"));
1605 for (i = cur_reg + 1; i < reg; i++)
1607 if (range & (1 << i))
1609 (_("Warning: duplicated register (r%d) in register list"),
1617 if (range & (1 << reg))
1618 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1620 else if (reg <= cur_reg)
1621 as_tsktsk (_("Warning: register range not in ascending order"));
1626 while (skip_past_comma (&str) != FAIL
1627 || (in_range = 1, *str++ == '-'));
1632 first_error (_("missing `}'"));
1640 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1643 if (exp.X_op == O_constant)
1645 if (exp.X_add_number
1646 != (exp.X_add_number & 0x0000ffff))
1648 inst.error = _("invalid register mask");
1652 if ((range & exp.X_add_number) != 0)
1654 int regno = range & exp.X_add_number;
1657 regno = (1 << regno) - 1;
1659 (_("Warning: duplicated register (r%d) in register list"),
1663 range |= exp.X_add_number;
1667 if (inst.reloc.type != 0)
1669 inst.error = _("expression too complex");
1673 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1674 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1675 inst.reloc.pc_rel = 0;
1679 if (*str == '|' || *str == '+')
1685 while (another_range);
1691 /* Types of registers in a list. */
1700 /* Parse a VFP register list. If the string is invalid return FAIL.
1701 Otherwise return the number of registers, and set PBASE to the first
1702 register. Parses registers of type ETYPE.
1703 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1704 - Q registers can be used to specify pairs of D registers
1705 - { } can be omitted from around a singleton register list
1706 FIXME: This is not implemented, as it would require backtracking in
1709 This could be done (the meaning isn't really ambiguous), but doesn't
1710 fit in well with the current parsing framework.
1711 - 32 D registers may be used (also true for VFPv3).
1712 FIXME: Types are ignored in these register lists, which is probably a
1716 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1721 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1725 unsigned long mask = 0;
1730 inst.error = _("expecting {");
1739 regtype = REG_TYPE_VFS;
1744 regtype = REG_TYPE_VFD;
1747 case REGLIST_NEON_D:
1748 regtype = REG_TYPE_NDQ;
1752 if (etype != REGLIST_VFP_S)
1754 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1755 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1759 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1762 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1769 base_reg = max_regs;
1773 int setmask = 1, addregs = 1;
1775 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1777 if (new_base == FAIL)
1779 first_error (_(reg_expected_msgs[regtype]));
1783 if (new_base >= max_regs)
1785 first_error (_("register out of range in list"));
1789 /* Note: a value of 2 * n is returned for the register Q<n>. */
1790 if (regtype == REG_TYPE_NQ)
1796 if (new_base < base_reg)
1797 base_reg = new_base;
1799 if (mask & (setmask << new_base))
1801 first_error (_("invalid register list"));
1805 if ((mask >> new_base) != 0 && ! warned)
1807 as_tsktsk (_("register list not in ascending order"));
1811 mask |= setmask << new_base;
1814 if (*str == '-') /* We have the start of a range expression */
1820 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1823 inst.error = gettext (reg_expected_msgs[regtype]);
1827 if (high_range >= max_regs)
1829 first_error (_("register out of range in list"));
1833 if (regtype == REG_TYPE_NQ)
1834 high_range = high_range + 1;
1836 if (high_range <= new_base)
1838 inst.error = _("register range not in ascending order");
1842 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1844 if (mask & (setmask << new_base))
1846 inst.error = _("invalid register list");
1850 mask |= setmask << new_base;
1855 while (skip_past_comma (&str) != FAIL);
1859 /* Sanity check -- should have raised a parse error above. */
1860 if (count == 0 || count > max_regs)
1865 /* Final test -- the registers must be consecutive. */
1867 for (i = 0; i < count; i++)
1869 if ((mask & (1u << i)) == 0)
1871 inst.error = _("non-contiguous register range");
1881 /* True if two alias types are the same. */
1884 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1892 if (a->defined != b->defined)
1895 if ((a->defined & NTA_HASTYPE) != 0
1896 && (a->eltype.type != b->eltype.type
1897 || a->eltype.size != b->eltype.size))
1900 if ((a->defined & NTA_HASINDEX) != 0
1901 && (a->index != b->index))
1907 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1908 The base register is put in *PBASE.
1909 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1911 The register stride (minus one) is put in bit 4 of the return value.
1912 Bits [6:5] encode the list length (minus one).
1913 The type of the list elements is put in *ELTYPE, if non-NULL. */
1915 #define NEON_LANE(X) ((X) & 0xf)
1916 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1917 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1920 parse_neon_el_struct_list (char **str, unsigned *pbase,
1921 struct neon_type_el *eltype)
1928 int leading_brace = 0;
1929 enum arm_reg_type rtype = REG_TYPE_NDQ;
1930 const char *const incr_error = _("register stride must be 1 or 2");
1931 const char *const type_error = _("mismatched element/structure types in list");
1932 struct neon_typed_alias firsttype;
1934 if (skip_past_char (&ptr, '{') == SUCCESS)
1939 struct neon_typed_alias atype;
1940 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1944 first_error (_(reg_expected_msgs[rtype]));
1951 if (rtype == REG_TYPE_NQ)
1957 else if (reg_incr == -1)
1959 reg_incr = getreg - base_reg;
1960 if (reg_incr < 1 || reg_incr > 2)
1962 first_error (_(incr_error));
1966 else if (getreg != base_reg + reg_incr * count)
1968 first_error (_(incr_error));
1972 if (! neon_alias_types_same (&atype, &firsttype))
1974 first_error (_(type_error));
1978 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1982 struct neon_typed_alias htype;
1983 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1985 lane = NEON_INTERLEAVE_LANES;
1986 else if (lane != NEON_INTERLEAVE_LANES)
1988 first_error (_(type_error));
1993 else if (reg_incr != 1)
1995 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1999 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2002 first_error (_(reg_expected_msgs[rtype]));
2005 if (! neon_alias_types_same (&htype, &firsttype))
2007 first_error (_(type_error));
2010 count += hireg + dregs - getreg;
2014 /* If we're using Q registers, we can't use [] or [n] syntax. */
2015 if (rtype == REG_TYPE_NQ)
2021 if ((atype.defined & NTA_HASINDEX) != 0)
2025 else if (lane != atype.index)
2027 first_error (_(type_error));
2031 else if (lane == -1)
2032 lane = NEON_INTERLEAVE_LANES;
2033 else if (lane != NEON_INTERLEAVE_LANES)
2035 first_error (_(type_error));
2040 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2042 /* No lane set by [x]. We must be interleaving structures. */
2044 lane = NEON_INTERLEAVE_LANES;
2047 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2048 || (count > 1 && reg_incr == -1))
2050 first_error (_("error parsing element/structure list"));
2054 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2056 first_error (_("expected }"));
2064 *eltype = firsttype.eltype;
2069 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2072 /* Parse an explicit relocation suffix on an expression. This is
2073 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2074 arm_reloc_hsh contains no entries, so this function can only
2075 succeed if there is no () after the word. Returns -1 on error,
2076 BFD_RELOC_UNUSED if there wasn't any suffix. */
2079 parse_reloc (char **str)
2081 struct reloc_entry *r;
2085 return BFD_RELOC_UNUSED;
2090 while (*q && *q != ')' && *q != ',')
2095 if ((r = (struct reloc_entry *)
2096 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2103 /* Directives: register aliases. */
2105 static struct reg_entry *
2106 insert_reg_alias (char *str, unsigned number, int type)
2108 struct reg_entry *new_reg;
2111 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2113 if (new_reg->builtin)
2114 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2116 /* Only warn about a redefinition if it's not defined as the
2118 else if (new_reg->number != number || new_reg->type != type)
2119 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2124 name = xstrdup (str);
2125 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2127 new_reg->name = name;
2128 new_reg->number = number;
2129 new_reg->type = type;
2130 new_reg->builtin = FALSE;
2131 new_reg->neon = NULL;
2133 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2140 insert_neon_reg_alias (char *str, int number, int type,
2141 struct neon_typed_alias *atype)
2143 struct reg_entry *reg = insert_reg_alias (str, number, type);
2147 first_error (_("attempt to redefine typed alias"));
2153 reg->neon = (struct neon_typed_alias *)
2154 xmalloc (sizeof (struct neon_typed_alias));
2155 *reg->neon = *atype;
2159 /* Look for the .req directive. This is of the form:
2161 new_register_name .req existing_register_name
2163 If we find one, or if it looks sufficiently like one that we want to
2164 handle any error here, return TRUE. Otherwise return FALSE. */
2167 create_register_alias (char * newname, char *p)
2169 struct reg_entry *old;
2170 char *oldname, *nbuf;
2173 /* The input scrubber ensures that whitespace after the mnemonic is
2174 collapsed to single spaces. */
2176 if (strncmp (oldname, " .req ", 6) != 0)
2180 if (*oldname == '\0')
2183 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2186 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2190 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2191 the desired alias name, and p points to its end. If not, then
2192 the desired alias name is in the global original_case_string. */
2193 #ifdef TC_CASE_SENSITIVE
2196 newname = original_case_string;
2197 nlen = strlen (newname);
2200 nbuf = (char *) alloca (nlen + 1);
2201 memcpy (nbuf, newname, nlen);
2204 /* Create aliases under the new name as stated; an all-lowercase
2205 version of the new name; and an all-uppercase version of the new
2207 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2209 for (p = nbuf; *p; p++)
2212 if (strncmp (nbuf, newname, nlen))
2214 /* If this attempt to create an additional alias fails, do not bother
2215 trying to create the all-lower case alias. We will fail and issue
2216 a second, duplicate error message. This situation arises when the
2217 programmer does something like:
2220 The second .req creates the "Foo" alias but then fails to create
2221 the artificial FOO alias because it has already been created by the
2223 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2227 for (p = nbuf; *p; p++)
2230 if (strncmp (nbuf, newname, nlen))
2231 insert_reg_alias (nbuf, old->number, old->type);
2237 /* Create a Neon typed/indexed register alias using directives, e.g.:
2242 These typed registers can be used instead of the types specified after the
2243 Neon mnemonic, so long as all operands given have types. Types can also be
2244 specified directly, e.g.:
2245 vadd d0.s32, d1.s32, d2.s32 */
2248 create_neon_reg_alias (char *newname, char *p)
2250 enum arm_reg_type basetype;
2251 struct reg_entry *basereg;
2252 struct reg_entry mybasereg;
2253 struct neon_type ntype;
2254 struct neon_typed_alias typeinfo;
2255 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2258 typeinfo.defined = 0;
2259 typeinfo.eltype.type = NT_invtype;
2260 typeinfo.eltype.size = -1;
2261 typeinfo.index = -1;
2265 if (strncmp (p, " .dn ", 5) == 0)
2266 basetype = REG_TYPE_VFD;
2267 else if (strncmp (p, " .qn ", 5) == 0)
2268 basetype = REG_TYPE_NQ;
2277 basereg = arm_reg_parse_multi (&p);
2279 if (basereg && basereg->type != basetype)
2281 as_bad (_("bad type for register"));
2285 if (basereg == NULL)
2288 /* Try parsing as an integer. */
2289 my_get_expression (&exp, &p, GE_NO_PREFIX);
2290 if (exp.X_op != O_constant)
2292 as_bad (_("expression must be constant"));
2295 basereg = &mybasereg;
2296 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2302 typeinfo = *basereg->neon;
2304 if (parse_neon_type (&ntype, &p) == SUCCESS)
2306 /* We got a type. */
2307 if (typeinfo.defined & NTA_HASTYPE)
2309 as_bad (_("can't redefine the type of a register alias"));
2313 typeinfo.defined |= NTA_HASTYPE;
2314 if (ntype.elems != 1)
2316 as_bad (_("you must specify a single type only"));
2319 typeinfo.eltype = ntype.el[0];
2322 if (skip_past_char (&p, '[') == SUCCESS)
2325 /* We got a scalar index. */
2327 if (typeinfo.defined & NTA_HASINDEX)
2329 as_bad (_("can't redefine the index of a scalar alias"));
2333 my_get_expression (&exp, &p, GE_NO_PREFIX);
2335 if (exp.X_op != O_constant)
2337 as_bad (_("scalar index must be constant"));
2341 typeinfo.defined |= NTA_HASINDEX;
2342 typeinfo.index = exp.X_add_number;
2344 if (skip_past_char (&p, ']') == FAIL)
2346 as_bad (_("expecting ]"));
2351 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2352 the desired alias name, and p points to its end. If not, then
2353 the desired alias name is in the global original_case_string. */
2354 #ifdef TC_CASE_SENSITIVE
2355 namelen = nameend - newname;
2357 newname = original_case_string;
2358 namelen = strlen (newname);
2361 namebuf = (char *) alloca (namelen + 1);
2362 strncpy (namebuf, newname, namelen);
2363 namebuf[namelen] = '\0';
2365 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2366 typeinfo.defined != 0 ? &typeinfo : NULL);
2368 /* Insert name in all uppercase. */
2369 for (p = namebuf; *p; p++)
2372 if (strncmp (namebuf, newname, namelen))
2373 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2374 typeinfo.defined != 0 ? &typeinfo : NULL);
2376 /* Insert name in all lowercase. */
2377 for (p = namebuf; *p; p++)
2380 if (strncmp (namebuf, newname, namelen))
2381 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2382 typeinfo.defined != 0 ? &typeinfo : NULL);
2387 /* Should never be called, as .req goes between the alias and the
2388 register name, not at the beginning of the line. */
2391 s_req (int a ATTRIBUTE_UNUSED)
2393 as_bad (_("invalid syntax for .req directive"));
2397 s_dn (int a ATTRIBUTE_UNUSED)
2399 as_bad (_("invalid syntax for .dn directive"));
2403 s_qn (int a ATTRIBUTE_UNUSED)
2405 as_bad (_("invalid syntax for .qn directive"));
2408 /* The .unreq directive deletes an alias which was previously defined
2409 by .req. For example:
2415 s_unreq (int a ATTRIBUTE_UNUSED)
2420 name = input_line_pointer;
2422 while (*input_line_pointer != 0
2423 && *input_line_pointer != ' '
2424 && *input_line_pointer != '\n')
2425 ++input_line_pointer;
2427 saved_char = *input_line_pointer;
2428 *input_line_pointer = 0;
2431 as_bad (_("invalid syntax for .unreq directive"));
2434 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2438 as_bad (_("unknown register alias '%s'"), name);
2439 else if (reg->builtin)
2440 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2447 hash_delete (arm_reg_hsh, name, FALSE);
2448 free ((char *) reg->name);
2453 /* Also locate the all upper case and all lower case versions.
2454 Do not complain if we cannot find one or the other as it
2455 was probably deleted above. */
2457 nbuf = strdup (name);
2458 for (p = nbuf; *p; p++)
2460 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2463 hash_delete (arm_reg_hsh, nbuf, FALSE);
2464 free ((char *) reg->name);
2470 for (p = nbuf; *p; p++)
2472 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2475 hash_delete (arm_reg_hsh, nbuf, FALSE);
2476 free ((char *) reg->name);
2486 *input_line_pointer = saved_char;
2487 demand_empty_rest_of_line ();
2490 /* Directives: Instruction set selection. */
2493 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2494 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2495 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2496 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2498 /* Create a new mapping symbol for the transition to STATE. */
2501 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2504 const char * symname;
2511 type = BSF_NO_FLAGS;
2515 type = BSF_NO_FLAGS;
2519 type = BSF_NO_FLAGS;
2525 symbolP = symbol_new (symname, now_seg, value, frag);
2526 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2531 THUMB_SET_FUNC (symbolP, 0);
2532 ARM_SET_THUMB (symbolP, 0);
2533 ARM_SET_INTERWORK (symbolP, support_interwork);
2537 THUMB_SET_FUNC (symbolP, 1);
2538 ARM_SET_THUMB (symbolP, 1);
2539 ARM_SET_INTERWORK (symbolP, support_interwork);
2547 /* Save the mapping symbols for future reference. Also check that
2548 we do not place two mapping symbols at the same offset within a
2549 frag. We'll handle overlap between frags in
2550 check_mapping_symbols.
2552 If .fill or other data filling directive generates zero sized data,
2553 the mapping symbol for the following code will have the same value
2554 as the one generated for the data filling directive. In this case,
2555 we replace the old symbol with the new one at the same address. */
2558 if (frag->tc_frag_data.first_map != NULL)
2560 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2561 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2563 frag->tc_frag_data.first_map = symbolP;
2565 if (frag->tc_frag_data.last_map != NULL)
2567 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2568 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2569 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2571 frag->tc_frag_data.last_map = symbolP;
2574 /* We must sometimes convert a region marked as code to data during
2575 code alignment, if an odd number of bytes have to be padded. The
2576 code mapping symbol is pushed to an aligned address. */
2579 insert_data_mapping_symbol (enum mstate state,
2580 valueT value, fragS *frag, offsetT bytes)
2582 /* If there was already a mapping symbol, remove it. */
2583 if (frag->tc_frag_data.last_map != NULL
2584 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2586 symbolS *symp = frag->tc_frag_data.last_map;
2590 know (frag->tc_frag_data.first_map == symp);
2591 frag->tc_frag_data.first_map = NULL;
2593 frag->tc_frag_data.last_map = NULL;
2594 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2597 make_mapping_symbol (MAP_DATA, value, frag);
2598 make_mapping_symbol (state, value + bytes, frag);
2601 static void mapping_state_2 (enum mstate state, int max_chars);
2603 /* Set the mapping state to STATE. Only call this when about to
2604 emit some STATE bytes to the file. */
2607 mapping_state (enum mstate state)
2609 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2611 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2613 if (mapstate == state)
2614 /* The mapping symbol has already been emitted.
2615 There is nothing else to do. */
2618 if (state == MAP_ARM || state == MAP_THUMB)
2620 All ARM instructions require 4-byte alignment.
2621 (Almost) all Thumb instructions require 2-byte alignment.
2623 When emitting instructions into any section, mark the section
2626 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2627 but themselves require 2-byte alignment; this applies to some
2628 PC- relative forms. However, these cases will invovle implicit
2629 literal pool generation or an explicit .align >=2, both of
2630 which will cause the section to me marked with sufficient
2631 alignment. Thus, we don't handle those cases here. */
2632 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2634 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2635 /* This case will be evaluated later in the next else. */
2637 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2638 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2640 /* Only add the symbol if the offset is > 0:
2641 if we're at the first frag, check it's size > 0;
2642 if we're not at the first frag, then for sure
2643 the offset is > 0. */
2644 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2645 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2648 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2651 mapping_state_2 (state, 0);
2655 /* Same as mapping_state, but MAX_CHARS bytes have already been
2656 allocated. Put the mapping symbol that far back. */
2659 mapping_state_2 (enum mstate state, int max_chars)
2661 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2663 if (!SEG_NORMAL (now_seg))
2666 if (mapstate == state)
2667 /* The mapping symbol has already been emitted.
2668 There is nothing else to do. */
2671 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2672 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2675 #define mapping_state(x) ((void)0)
2676 #define mapping_state_2(x, y) ((void)0)
2679 /* Find the real, Thumb encoded start of a Thumb function. */
2683 find_real_start (symbolS * symbolP)
2686 const char * name = S_GET_NAME (symbolP);
2687 symbolS * new_target;
2689 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2690 #define STUB_NAME ".real_start_of"
2695 /* The compiler may generate BL instructions to local labels because
2696 it needs to perform a branch to a far away location. These labels
2697 do not have a corresponding ".real_start_of" label. We check
2698 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2699 the ".real_start_of" convention for nonlocal branches. */
2700 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2703 real_start = ACONCAT ((STUB_NAME, name, NULL));
2704 new_target = symbol_find (real_start);
2706 if (new_target == NULL)
2708 as_warn (_("Failed to find real start of function: %s\n"), name);
2709 new_target = symbolP;
2717 opcode_select (int width)
2724 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2725 as_bad (_("selected processor does not support THUMB opcodes"));
2728 /* No need to force the alignment, since we will have been
2729 coming from ARM mode, which is word-aligned. */
2730 record_alignment (now_seg, 1);
2737 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2738 as_bad (_("selected processor does not support ARM opcodes"));
2743 frag_align (2, 0, 0);
2745 record_alignment (now_seg, 1);
2750 as_bad (_("invalid instruction size selected (%d)"), width);
2755 s_arm (int ignore ATTRIBUTE_UNUSED)
2758 demand_empty_rest_of_line ();
2762 s_thumb (int ignore ATTRIBUTE_UNUSED)
2765 demand_empty_rest_of_line ();
2769 s_code (int unused ATTRIBUTE_UNUSED)
2773 temp = get_absolute_expression ();
2778 opcode_select (temp);
2782 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2787 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2789 /* If we are not already in thumb mode go into it, EVEN if
2790 the target processor does not support thumb instructions.
2791 This is used by gcc/config/arm/lib1funcs.asm for example
2792 to compile interworking support functions even if the
2793 target processor should not support interworking. */
2797 record_alignment (now_seg, 1);
2800 demand_empty_rest_of_line ();
2804 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2808 /* The following label is the name/address of the start of a Thumb function.
2809 We need to know this for the interworking support. */
2810 label_is_thumb_function_name = TRUE;
2813 /* Perform a .set directive, but also mark the alias as
2814 being a thumb function. */
2817 s_thumb_set (int equiv)
2819 /* XXX the following is a duplicate of the code for s_set() in read.c
2820 We cannot just call that code as we need to get at the symbol that
2827 /* Especial apologies for the random logic:
2828 This just grew, and could be parsed much more simply!
2830 name = input_line_pointer;
2831 delim = get_symbol_end ();
2832 end_name = input_line_pointer;
2835 if (*input_line_pointer != ',')
2838 as_bad (_("expected comma after name \"%s\""), name);
2840 ignore_rest_of_line ();
2844 input_line_pointer++;
2847 if (name[0] == '.' && name[1] == '\0')
2849 /* XXX - this should not happen to .thumb_set. */
2853 if ((symbolP = symbol_find (name)) == NULL
2854 && (symbolP = md_undefined_symbol (name)) == NULL)
2857 /* When doing symbol listings, play games with dummy fragments living
2858 outside the normal fragment chain to record the file and line info
2860 if (listing & LISTING_SYMBOLS)
2862 extern struct list_info_struct * listing_tail;
2863 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2865 memset (dummy_frag, 0, sizeof (fragS));
2866 dummy_frag->fr_type = rs_fill;
2867 dummy_frag->line = listing_tail;
2868 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2869 dummy_frag->fr_symbol = symbolP;
2873 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2876 /* "set" symbols are local unless otherwise specified. */
2877 SF_SET_LOCAL (symbolP);
2878 #endif /* OBJ_COFF */
2879 } /* Make a new symbol. */
2881 symbol_table_insert (symbolP);
2886 && S_IS_DEFINED (symbolP)
2887 && S_GET_SEGMENT (symbolP) != reg_section)
2888 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2890 pseudo_set (symbolP);
2892 demand_empty_rest_of_line ();
2894 /* XXX Now we come to the Thumb specific bit of code. */
2896 THUMB_SET_FUNC (symbolP, 1);
2897 ARM_SET_THUMB (symbolP, 1);
2898 #if defined OBJ_ELF || defined OBJ_COFF
2899 ARM_SET_INTERWORK (symbolP, support_interwork);
2903 /* Directives: Mode selection. */
2905 /* .syntax [unified|divided] - choose the new unified syntax
2906 (same for Arm and Thumb encoding, modulo slight differences in what
2907 can be represented) or the old divergent syntax for each mode. */
2909 s_syntax (int unused ATTRIBUTE_UNUSED)
2913 name = input_line_pointer;
2914 delim = get_symbol_end ();
2916 if (!strcasecmp (name, "unified"))
2917 unified_syntax = TRUE;
2918 else if (!strcasecmp (name, "divided"))
2919 unified_syntax = FALSE;
2922 as_bad (_("unrecognized syntax mode \"%s\""), name);
2925 *input_line_pointer = delim;
2926 demand_empty_rest_of_line ();
2929 /* Directives: sectioning and alignment. */
2931 /* Same as s_align_ptwo but align 0 => align 2. */
2934 s_align (int unused ATTRIBUTE_UNUSED)
2939 long max_alignment = 15;
2941 temp = get_absolute_expression ();
2942 if (temp > max_alignment)
2943 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2946 as_bad (_("alignment negative. 0 assumed."));
2950 if (*input_line_pointer == ',')
2952 input_line_pointer++;
2953 temp_fill = get_absolute_expression ();
2965 /* Only make a frag if we HAVE to. */
2966 if (temp && !need_pass_2)
2968 if (!fill_p && subseg_text_p (now_seg))
2969 frag_align_code (temp, 0);
2971 frag_align (temp, (int) temp_fill, 0);
2973 demand_empty_rest_of_line ();
2975 record_alignment (now_seg, temp);
2979 s_bss (int ignore ATTRIBUTE_UNUSED)
2981 /* We don't support putting frags in the BSS segment, we fake it by
2982 marking in_bss, then looking at s_skip for clues. */
2983 subseg_set (bss_section, 0);
2984 demand_empty_rest_of_line ();
2986 #ifdef md_elf_section_change_hook
2987 md_elf_section_change_hook ();
2992 s_even (int ignore ATTRIBUTE_UNUSED)
2994 /* Never make frag if expect extra pass. */
2996 frag_align (1, 0, 0);
2998 record_alignment (now_seg, 1);
3000 demand_empty_rest_of_line ();
3003 /* Directives: Literal pools. */
3005 static literal_pool *
3006 find_literal_pool (void)
3008 literal_pool * pool;
3010 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3012 if (pool->section == now_seg
3013 && pool->sub_section == now_subseg)
3020 static literal_pool *
3021 find_or_make_literal_pool (void)
3023 /* Next literal pool ID number. */
3024 static unsigned int latest_pool_num = 1;
3025 literal_pool * pool;
3027 pool = find_literal_pool ();
3031 /* Create a new pool. */
3032 pool = (literal_pool *) xmalloc (sizeof (* pool));
3036 pool->next_free_entry = 0;
3037 pool->section = now_seg;
3038 pool->sub_section = now_subseg;
3039 pool->next = list_of_pools;
3040 pool->symbol = NULL;
3042 /* Add it to the list. */
3043 list_of_pools = pool;
3046 /* New pools, and emptied pools, will have a NULL symbol. */
3047 if (pool->symbol == NULL)
3049 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3050 (valueT) 0, &zero_address_frag);
3051 pool->id = latest_pool_num ++;
3058 /* Add the literal in the global 'inst'
3059 structure to the relevant literal pool. */
3062 add_to_lit_pool (void)
3064 literal_pool * pool;
3067 pool = find_or_make_literal_pool ();
3069 /* Check if this literal value is already in the pool. */
3070 for (entry = 0; entry < pool->next_free_entry; entry ++)
3072 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3073 && (inst.reloc.exp.X_op == O_constant)
3074 && (pool->literals[entry].X_add_number
3075 == inst.reloc.exp.X_add_number)
3076 && (pool->literals[entry].X_unsigned
3077 == inst.reloc.exp.X_unsigned))
3080 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3081 && (inst.reloc.exp.X_op == O_symbol)
3082 && (pool->literals[entry].X_add_number
3083 == inst.reloc.exp.X_add_number)
3084 && (pool->literals[entry].X_add_symbol
3085 == inst.reloc.exp.X_add_symbol)
3086 && (pool->literals[entry].X_op_symbol
3087 == inst.reloc.exp.X_op_symbol))
3091 /* Do we need to create a new entry? */
3092 if (entry == pool->next_free_entry)
3094 if (entry >= MAX_LITERAL_POOL_SIZE)
3096 inst.error = _("literal pool overflow");
3100 pool->literals[entry] = inst.reloc.exp;
3102 /* PR ld/12974: Record the location of the first source line to reference
3103 this entry in the literal pool. If it turns out during linking that the
3104 symbol does not exist we will be able to give an accurate line number for
3105 the (first use of the) missing reference. */
3106 if (debug_type == DEBUG_DWARF2)
3107 dwarf2_where (pool->locs + entry);
3109 pool->next_free_entry += 1;
3112 inst.reloc.exp.X_op = O_symbol;
3113 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3114 inst.reloc.exp.X_add_symbol = pool->symbol;
3119 /* Can't use symbol_new here, so have to create a symbol and then at
3120 a later date assign it a value. Thats what these functions do. */
3123 symbol_locate (symbolS * symbolP,
3124 const char * name, /* It is copied, the caller can modify. */
3125 segT segment, /* Segment identifier (SEG_<something>). */
3126 valueT valu, /* Symbol value. */
3127 fragS * frag) /* Associated fragment. */
3129 unsigned int name_length;
3130 char * preserved_copy_of_name;
3132 name_length = strlen (name) + 1; /* +1 for \0. */
3133 obstack_grow (¬es, name, name_length);
3134 preserved_copy_of_name = (char *) obstack_finish (¬es);
3136 #ifdef tc_canonicalize_symbol_name
3137 preserved_copy_of_name =
3138 tc_canonicalize_symbol_name (preserved_copy_of_name);
3141 S_SET_NAME (symbolP, preserved_copy_of_name);
3143 S_SET_SEGMENT (symbolP, segment);
3144 S_SET_VALUE (symbolP, valu);
3145 symbol_clear_list_pointers (symbolP);
3147 symbol_set_frag (symbolP, frag);
3149 /* Link to end of symbol chain. */
3151 extern int symbol_table_frozen;
3153 if (symbol_table_frozen)
3157 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3159 obj_symbol_new_hook (symbolP);
3161 #ifdef tc_symbol_new_hook
3162 tc_symbol_new_hook (symbolP);
3166 verify_symbol_chain (symbol_rootP, symbol_lastP);
3167 #endif /* DEBUG_SYMS */
3172 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3175 literal_pool * pool;
3178 pool = find_literal_pool ();
3180 || pool->symbol == NULL
3181 || pool->next_free_entry == 0)
3184 mapping_state (MAP_DATA);
3186 /* Align pool as you have word accesses.
3187 Only make a frag if we have to. */
3189 frag_align (2, 0, 0);
3191 record_alignment (now_seg, 2);
3193 sprintf (sym_name, "$$lit_\002%x", pool->id);
3195 symbol_locate (pool->symbol, sym_name, now_seg,
3196 (valueT) frag_now_fix (), frag_now);
3197 symbol_table_insert (pool->symbol);
3199 ARM_SET_THUMB (pool->symbol, thumb_mode);
3201 #if defined OBJ_COFF || defined OBJ_ELF
3202 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3205 for (entry = 0; entry < pool->next_free_entry; entry ++)
3208 if (debug_type == DEBUG_DWARF2)
3209 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3211 /* First output the expression in the instruction to the pool. */
3212 emit_expr (&(pool->literals[entry]), 4); /* .word */
3215 /* Mark the pool as empty. */
3216 pool->next_free_entry = 0;
3217 pool->symbol = NULL;
3221 /* Forward declarations for functions below, in the MD interface
3223 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3224 static valueT create_unwind_entry (int);
3225 static void start_unwind_section (const segT, int);
3226 static void add_unwind_opcode (valueT, int);
3227 static void flush_pending_unwind (void);
3229 /* Directives: Data. */
3232 s_arm_elf_cons (int nbytes)
3236 #ifdef md_flush_pending_output
3237 md_flush_pending_output ();
3240 if (is_it_end_of_statement ())
3242 demand_empty_rest_of_line ();
3246 #ifdef md_cons_align
3247 md_cons_align (nbytes);
3250 mapping_state (MAP_DATA);
3254 char *base = input_line_pointer;
3258 if (exp.X_op != O_symbol)
3259 emit_expr (&exp, (unsigned int) nbytes);
3262 char *before_reloc = input_line_pointer;
3263 reloc = parse_reloc (&input_line_pointer);
3266 as_bad (_("unrecognized relocation suffix"));
3267 ignore_rest_of_line ();
3270 else if (reloc == BFD_RELOC_UNUSED)
3271 emit_expr (&exp, (unsigned int) nbytes);
3274 reloc_howto_type *howto = (reloc_howto_type *)
3275 bfd_reloc_type_lookup (stdoutput,
3276 (bfd_reloc_code_real_type) reloc);
3277 int size = bfd_get_reloc_size (howto);
3279 if (reloc == BFD_RELOC_ARM_PLT32)
3281 as_bad (_("(plt) is only valid on branch targets"));
3282 reloc = BFD_RELOC_UNUSED;
3287 as_bad (_("%s relocations do not fit in %d bytes"),
3288 howto->name, nbytes);
3291 /* We've parsed an expression stopping at O_symbol.
3292 But there may be more expression left now that we
3293 have parsed the relocation marker. Parse it again.
3294 XXX Surely there is a cleaner way to do this. */
3295 char *p = input_line_pointer;
3297 char *save_buf = (char *) alloca (input_line_pointer - base);
3298 memcpy (save_buf, base, input_line_pointer - base);
3299 memmove (base + (input_line_pointer - before_reloc),
3300 base, before_reloc - base);
3302 input_line_pointer = base + (input_line_pointer-before_reloc);
3304 memcpy (base, save_buf, p - base);
3306 offset = nbytes - size;
3307 p = frag_more ((int) nbytes);
3308 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3309 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3314 while (*input_line_pointer++ == ',');
3316 /* Put terminator back into stream. */
3317 input_line_pointer --;
3318 demand_empty_rest_of_line ();
3321 /* Emit an expression containing a 32-bit thumb instruction.
3322 Implementation based on put_thumb32_insn. */
3325 emit_thumb32_expr (expressionS * exp)
3327 expressionS exp_high = *exp;
3329 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3330 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3331 exp->X_add_number &= 0xffff;
3332 emit_expr (exp, (unsigned int) THUMB_SIZE);
3335 /* Guess the instruction size based on the opcode. */
3338 thumb_insn_size (int opcode)
3340 if ((unsigned int) opcode < 0xe800u)
3342 else if ((unsigned int) opcode >= 0xe8000000u)
3349 emit_insn (expressionS *exp, int nbytes)
3353 if (exp->X_op == O_constant)
3358 size = thumb_insn_size (exp->X_add_number);
3362 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3364 as_bad (_(".inst.n operand too big. "\
3365 "Use .inst.w instead"));
3370 if (now_it.state == AUTOMATIC_IT_BLOCK)
3371 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3373 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3375 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3376 emit_thumb32_expr (exp);
3378 emit_expr (exp, (unsigned int) size);
3380 it_fsm_post_encode ();
3384 as_bad (_("cannot determine Thumb instruction size. " \
3385 "Use .inst.n/.inst.w instead"));
3388 as_bad (_("constant expression required"));
3393 /* Like s_arm_elf_cons but do not use md_cons_align and
3394 set the mapping state to MAP_ARM/MAP_THUMB. */
3397 s_arm_elf_inst (int nbytes)
3399 if (is_it_end_of_statement ())
3401 demand_empty_rest_of_line ();
3405 /* Calling mapping_state () here will not change ARM/THUMB,
3406 but will ensure not to be in DATA state. */
3409 mapping_state (MAP_THUMB);
3414 as_bad (_("width suffixes are invalid in ARM mode"));
3415 ignore_rest_of_line ();
3421 mapping_state (MAP_ARM);
3430 if (! emit_insn (& exp, nbytes))
3432 ignore_rest_of_line ();
3436 while (*input_line_pointer++ == ',');
3438 /* Put terminator back into stream. */
3439 input_line_pointer --;
3440 demand_empty_rest_of_line ();
3443 /* Parse a .rel31 directive. */
3446 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3453 if (*input_line_pointer == '1')
3454 highbit = 0x80000000;
3455 else if (*input_line_pointer != '0')
3456 as_bad (_("expected 0 or 1"));
3458 input_line_pointer++;
3459 if (*input_line_pointer != ',')
3460 as_bad (_("missing comma"));
3461 input_line_pointer++;
3463 #ifdef md_flush_pending_output
3464 md_flush_pending_output ();
3467 #ifdef md_cons_align
3471 mapping_state (MAP_DATA);
3476 md_number_to_chars (p, highbit, 4);
3477 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3478 BFD_RELOC_ARM_PREL31);
3480 demand_empty_rest_of_line ();
3483 /* Directives: AEABI stack-unwind tables. */
3485 /* Parse an unwind_fnstart directive. Simply records the current location. */
3488 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3490 demand_empty_rest_of_line ();
3491 if (unwind.proc_start)
3493 as_bad (_("duplicate .fnstart directive"));
3497 /* Mark the start of the function. */
3498 unwind.proc_start = expr_build_dot ();
3500 /* Reset the rest of the unwind info. */
3501 unwind.opcode_count = 0;
3502 unwind.table_entry = NULL;
3503 unwind.personality_routine = NULL;
3504 unwind.personality_index = -1;
3505 unwind.frame_size = 0;
3506 unwind.fp_offset = 0;
3507 unwind.fp_reg = REG_SP;
3509 unwind.sp_restored = 0;
3513 /* Parse a handlerdata directive. Creates the exception handling table entry
3514 for the function. */
3517 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3519 demand_empty_rest_of_line ();
3520 if (!unwind.proc_start)
3521 as_bad (MISSING_FNSTART);
3523 if (unwind.table_entry)
3524 as_bad (_("duplicate .handlerdata directive"));
3526 create_unwind_entry (1);
3529 /* Parse an unwind_fnend directive. Generates the index table entry. */
3532 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3537 unsigned int marked_pr_dependency;
3539 demand_empty_rest_of_line ();
3541 if (!unwind.proc_start)
3543 as_bad (_(".fnend directive without .fnstart"));
3547 /* Add eh table entry. */
3548 if (unwind.table_entry == NULL)
3549 val = create_unwind_entry (0);
3553 /* Add index table entry. This is two words. */
3554 start_unwind_section (unwind.saved_seg, 1);
3555 frag_align (2, 0, 0);
3556 record_alignment (now_seg, 2);
3558 ptr = frag_more (8);
3560 where = frag_now_fix () - 8;
3562 /* Self relative offset of the function start. */
3563 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3564 BFD_RELOC_ARM_PREL31);
3566 /* Indicate dependency on EHABI-defined personality routines to the
3567 linker, if it hasn't been done already. */
3568 marked_pr_dependency
3569 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3570 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3571 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3573 static const char *const name[] =
3575 "__aeabi_unwind_cpp_pr0",
3576 "__aeabi_unwind_cpp_pr1",
3577 "__aeabi_unwind_cpp_pr2"
3579 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3580 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3581 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3582 |= 1 << unwind.personality_index;
3586 /* Inline exception table entry. */
3587 md_number_to_chars (ptr + 4, val, 4);
3589 /* Self relative offset of the table entry. */
3590 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3591 BFD_RELOC_ARM_PREL31);
3593 /* Restore the original section. */
3594 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3596 unwind.proc_start = NULL;
3600 /* Parse an unwind_cantunwind directive. */
3603 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3605 demand_empty_rest_of_line ();
3606 if (!unwind.proc_start)
3607 as_bad (MISSING_FNSTART);
3609 if (unwind.personality_routine || unwind.personality_index != -1)
3610 as_bad (_("personality routine specified for cantunwind frame"));
3612 unwind.personality_index = -2;
3616 /* Parse a personalityindex directive. */
3619 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3623 if (!unwind.proc_start)
3624 as_bad (MISSING_FNSTART);
3626 if (unwind.personality_routine || unwind.personality_index != -1)
3627 as_bad (_("duplicate .personalityindex directive"));
3631 if (exp.X_op != O_constant
3632 || exp.X_add_number < 0 || exp.X_add_number > 15)
3634 as_bad (_("bad personality routine number"));
3635 ignore_rest_of_line ();
3639 unwind.personality_index = exp.X_add_number;
3641 demand_empty_rest_of_line ();
3645 /* Parse a personality directive. */
3648 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3652 if (!unwind.proc_start)
3653 as_bad (MISSING_FNSTART);
3655 if (unwind.personality_routine || unwind.personality_index != -1)
3656 as_bad (_("duplicate .personality directive"));
3658 name = input_line_pointer;
3659 c = get_symbol_end ();
3660 p = input_line_pointer;
3661 unwind.personality_routine = symbol_find_or_make (name);
3663 demand_empty_rest_of_line ();
3667 /* Parse a directive saving core registers. */
3670 s_arm_unwind_save_core (void)
3676 range = parse_reg_list (&input_line_pointer);
3679 as_bad (_("expected register list"));
3680 ignore_rest_of_line ();
3684 demand_empty_rest_of_line ();
3686 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3687 into .unwind_save {..., sp...}. We aren't bothered about the value of
3688 ip because it is clobbered by calls. */
3689 if (unwind.sp_restored && unwind.fp_reg == 12
3690 && (range & 0x3000) == 0x1000)
3692 unwind.opcode_count--;
3693 unwind.sp_restored = 0;
3694 range = (range | 0x2000) & ~0x1000;
3695 unwind.pending_offset = 0;
3701 /* See if we can use the short opcodes. These pop a block of up to 8
3702 registers starting with r4, plus maybe r14. */
3703 for (n = 0; n < 8; n++)
3705 /* Break at the first non-saved register. */
3706 if ((range & (1 << (n + 4))) == 0)
3709 /* See if there are any other bits set. */
3710 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3712 /* Use the long form. */
3713 op = 0x8000 | ((range >> 4) & 0xfff);
3714 add_unwind_opcode (op, 2);
3718 /* Use the short form. */
3720 op = 0xa8; /* Pop r14. */
3722 op = 0xa0; /* Do not pop r14. */
3724 add_unwind_opcode (op, 1);
3731 op = 0xb100 | (range & 0xf);
3732 add_unwind_opcode (op, 2);
3735 /* Record the number of bytes pushed. */
3736 for (n = 0; n < 16; n++)
3738 if (range & (1 << n))
3739 unwind.frame_size += 4;
3744 /* Parse a directive saving FPA registers. */
3747 s_arm_unwind_save_fpa (int reg)
3753 /* Get Number of registers to transfer. */
3754 if (skip_past_comma (&input_line_pointer) != FAIL)
3757 exp.X_op = O_illegal;
3759 if (exp.X_op != O_constant)
3761 as_bad (_("expected , <constant>"));
3762 ignore_rest_of_line ();
3766 num_regs = exp.X_add_number;
3768 if (num_regs < 1 || num_regs > 4)
3770 as_bad (_("number of registers must be in the range [1:4]"));
3771 ignore_rest_of_line ();
3775 demand_empty_rest_of_line ();
3780 op = 0xb4 | (num_regs - 1);
3781 add_unwind_opcode (op, 1);
3786 op = 0xc800 | (reg << 4) | (num_regs - 1);
3787 add_unwind_opcode (op, 2);
3789 unwind.frame_size += num_regs * 12;
3793 /* Parse a directive saving VFP registers for ARMv6 and above. */
3796 s_arm_unwind_save_vfp_armv6 (void)
3801 int num_vfpv3_regs = 0;
3802 int num_regs_below_16;
3804 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3807 as_bad (_("expected register list"));
3808 ignore_rest_of_line ();
3812 demand_empty_rest_of_line ();
3814 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3815 than FSTMX/FLDMX-style ones). */
3817 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3819 num_vfpv3_regs = count;
3820 else if (start + count > 16)
3821 num_vfpv3_regs = start + count - 16;
3823 if (num_vfpv3_regs > 0)
3825 int start_offset = start > 16 ? start - 16 : 0;
3826 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3827 add_unwind_opcode (op, 2);
3830 /* Generate opcode for registers numbered in the range 0 .. 15. */
3831 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3832 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3833 if (num_regs_below_16 > 0)
3835 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3836 add_unwind_opcode (op, 2);
3839 unwind.frame_size += count * 8;
3843 /* Parse a directive saving VFP registers for pre-ARMv6. */
3846 s_arm_unwind_save_vfp (void)
3852 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3855 as_bad (_("expected register list"));
3856 ignore_rest_of_line ();
3860 demand_empty_rest_of_line ();
3865 op = 0xb8 | (count - 1);
3866 add_unwind_opcode (op, 1);
3871 op = 0xb300 | (reg << 4) | (count - 1);
3872 add_unwind_opcode (op, 2);
3874 unwind.frame_size += count * 8 + 4;
3878 /* Parse a directive saving iWMMXt data registers. */
3881 s_arm_unwind_save_mmxwr (void)
3889 if (*input_line_pointer == '{')
3890 input_line_pointer++;
3894 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3898 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3903 as_tsktsk (_("register list not in ascending order"));
3906 if (*input_line_pointer == '-')
3908 input_line_pointer++;
3909 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3912 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3915 else if (reg >= hi_reg)
3917 as_bad (_("bad register range"));
3920 for (; reg < hi_reg; reg++)
3924 while (skip_past_comma (&input_line_pointer) != FAIL);
3926 if (*input_line_pointer == '}')
3927 input_line_pointer++;
3929 demand_empty_rest_of_line ();
3931 /* Generate any deferred opcodes because we're going to be looking at
3933 flush_pending_unwind ();
3935 for (i = 0; i < 16; i++)
3937 if (mask & (1 << i))
3938 unwind.frame_size += 8;
3941 /* Attempt to combine with a previous opcode. We do this because gcc
3942 likes to output separate unwind directives for a single block of
3944 if (unwind.opcode_count > 0)
3946 i = unwind.opcodes[unwind.opcode_count - 1];
3947 if ((i & 0xf8) == 0xc0)
3950 /* Only merge if the blocks are contiguous. */
3953 if ((mask & 0xfe00) == (1 << 9))
3955 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3956 unwind.opcode_count--;
3959 else if (i == 6 && unwind.opcode_count >= 2)
3961 i = unwind.opcodes[unwind.opcode_count - 2];
3965 op = 0xffff << (reg - 1);
3967 && ((mask & op) == (1u << (reg - 1))))
3969 op = (1 << (reg + i + 1)) - 1;
3970 op &= ~((1 << reg) - 1);
3972 unwind.opcode_count -= 2;
3979 /* We want to generate opcodes in the order the registers have been
3980 saved, ie. descending order. */
3981 for (reg = 15; reg >= -1; reg--)
3983 /* Save registers in blocks. */
3985 || !(mask & (1 << reg)))
3987 /* We found an unsaved reg. Generate opcodes to save the
3994 op = 0xc0 | (hi_reg - 10);
3995 add_unwind_opcode (op, 1);
4000 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4001 add_unwind_opcode (op, 2);
4010 ignore_rest_of_line ();
4014 s_arm_unwind_save_mmxwcg (void)
4021 if (*input_line_pointer == '{')
4022 input_line_pointer++;
4026 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4030 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4036 as_tsktsk (_("register list not in ascending order"));
4039 if (*input_line_pointer == '-')
4041 input_line_pointer++;
4042 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4045 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4048 else if (reg >= hi_reg)
4050 as_bad (_("bad register range"));
4053 for (; reg < hi_reg; reg++)
4057 while (skip_past_comma (&input_line_pointer) != FAIL);
4059 if (*input_line_pointer == '}')
4060 input_line_pointer++;
4062 demand_empty_rest_of_line ();
4064 /* Generate any deferred opcodes because we're going to be looking at
4066 flush_pending_unwind ();
4068 for (reg = 0; reg < 16; reg++)
4070 if (mask & (1 << reg))
4071 unwind.frame_size += 4;
4074 add_unwind_opcode (op, 2);
4077 ignore_rest_of_line ();
4081 /* Parse an unwind_save directive.
4082 If the argument is non-zero, this is a .vsave directive. */
4085 s_arm_unwind_save (int arch_v6)
4088 struct reg_entry *reg;
4089 bfd_boolean had_brace = FALSE;
4091 if (!unwind.proc_start)
4092 as_bad (MISSING_FNSTART);
4094 /* Figure out what sort of save we have. */
4095 peek = input_line_pointer;
4103 reg = arm_reg_parse_multi (&peek);
4107 as_bad (_("register expected"));
4108 ignore_rest_of_line ();
4117 as_bad (_("FPA .unwind_save does not take a register list"));
4118 ignore_rest_of_line ();
4121 input_line_pointer = peek;
4122 s_arm_unwind_save_fpa (reg->number);
4125 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4128 s_arm_unwind_save_vfp_armv6 ();
4130 s_arm_unwind_save_vfp ();
4132 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4133 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4136 as_bad (_(".unwind_save does not support this kind of register"));
4137 ignore_rest_of_line ();
4142 /* Parse an unwind_movsp directive. */
4145 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4151 if (!unwind.proc_start)
4152 as_bad (MISSING_FNSTART);
4154 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4157 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4158 ignore_rest_of_line ();
4162 /* Optional constant. */
4163 if (skip_past_comma (&input_line_pointer) != FAIL)
4165 if (immediate_for_directive (&offset) == FAIL)
4171 demand_empty_rest_of_line ();
4173 if (reg == REG_SP || reg == REG_PC)
4175 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4179 if (unwind.fp_reg != REG_SP)
4180 as_bad (_("unexpected .unwind_movsp directive"));
4182 /* Generate opcode to restore the value. */
4184 add_unwind_opcode (op, 1);
4186 /* Record the information for later. */
4187 unwind.fp_reg = reg;
4188 unwind.fp_offset = unwind.frame_size - offset;
4189 unwind.sp_restored = 1;
4192 /* Parse an unwind_pad directive. */
4195 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4199 if (!unwind.proc_start)
4200 as_bad (MISSING_FNSTART);
4202 if (immediate_for_directive (&offset) == FAIL)
4207 as_bad (_("stack increment must be multiple of 4"));
4208 ignore_rest_of_line ();
4212 /* Don't generate any opcodes, just record the details for later. */
4213 unwind.frame_size += offset;
4214 unwind.pending_offset += offset;
4216 demand_empty_rest_of_line ();
4219 /* Parse an unwind_setfp directive. */
4222 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4228 if (!unwind.proc_start)
4229 as_bad (MISSING_FNSTART);
4231 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4232 if (skip_past_comma (&input_line_pointer) == FAIL)
4235 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4237 if (fp_reg == FAIL || sp_reg == FAIL)
4239 as_bad (_("expected <reg>, <reg>"));
4240 ignore_rest_of_line ();
4244 /* Optional constant. */
4245 if (skip_past_comma (&input_line_pointer) != FAIL)
4247 if (immediate_for_directive (&offset) == FAIL)
4253 demand_empty_rest_of_line ();
4255 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4257 as_bad (_("register must be either sp or set by a previous"
4258 "unwind_movsp directive"));
4262 /* Don't generate any opcodes, just record the information for later. */
4263 unwind.fp_reg = fp_reg;
4265 if (sp_reg == REG_SP)
4266 unwind.fp_offset = unwind.frame_size - offset;
4268 unwind.fp_offset -= offset;
4271 /* Parse an unwind_raw directive. */
4274 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4277 /* This is an arbitrary limit. */
4278 unsigned char op[16];
4281 if (!unwind.proc_start)
4282 as_bad (MISSING_FNSTART);
4285 if (exp.X_op == O_constant
4286 && skip_past_comma (&input_line_pointer) != FAIL)
4288 unwind.frame_size += exp.X_add_number;
4292 exp.X_op = O_illegal;
4294 if (exp.X_op != O_constant)
4296 as_bad (_("expected <offset>, <opcode>"));
4297 ignore_rest_of_line ();
4303 /* Parse the opcode. */
4308 as_bad (_("unwind opcode too long"));
4309 ignore_rest_of_line ();
4311 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4313 as_bad (_("invalid unwind opcode"));
4314 ignore_rest_of_line ();
4317 op[count++] = exp.X_add_number;
4319 /* Parse the next byte. */
4320 if (skip_past_comma (&input_line_pointer) == FAIL)
4326 /* Add the opcode bytes in reverse order. */
4328 add_unwind_opcode (op[count], 1);
4330 demand_empty_rest_of_line ();
4334 /* Parse a .eabi_attribute directive. */
4337 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4339 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4341 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4342 attributes_set_explicitly[tag] = 1;
4345 /* Emit a tls fix for the symbol. */
4348 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4352 #ifdef md_flush_pending_output
4353 md_flush_pending_output ();
4356 #ifdef md_cons_align
4360 /* Since we're just labelling the code, there's no need to define a
4363 p = obstack_next_free (&frchain_now->frch_obstack);
4364 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4365 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4366 : BFD_RELOC_ARM_TLS_DESCSEQ);
4368 #endif /* OBJ_ELF */
4370 static void s_arm_arch (int);
4371 static void s_arm_object_arch (int);
4372 static void s_arm_cpu (int);
4373 static void s_arm_fpu (int);
4374 static void s_arm_arch_extension (int);
4379 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4386 if (exp.X_op == O_symbol)
4387 exp.X_op = O_secrel;
4389 emit_expr (&exp, 4);
4391 while (*input_line_pointer++ == ',');
4393 input_line_pointer--;
4394 demand_empty_rest_of_line ();
4398 /* This table describes all the machine specific pseudo-ops the assembler
4399 has to support. The fields are:
4400 pseudo-op name without dot
4401 function to call to execute this pseudo-op
4402 Integer arg to pass to the function. */
4404 const pseudo_typeS md_pseudo_table[] =
4406 /* Never called because '.req' does not start a line. */
4407 { "req", s_req, 0 },
4408 /* Following two are likewise never called. */
4411 { "unreq", s_unreq, 0 },
4412 { "bss", s_bss, 0 },
4413 { "align", s_align, 0 },
4414 { "arm", s_arm, 0 },
4415 { "thumb", s_thumb, 0 },
4416 { "code", s_code, 0 },
4417 { "force_thumb", s_force_thumb, 0 },
4418 { "thumb_func", s_thumb_func, 0 },
4419 { "thumb_set", s_thumb_set, 0 },
4420 { "even", s_even, 0 },
4421 { "ltorg", s_ltorg, 0 },
4422 { "pool", s_ltorg, 0 },
4423 { "syntax", s_syntax, 0 },
4424 { "cpu", s_arm_cpu, 0 },
4425 { "arch", s_arm_arch, 0 },
4426 { "object_arch", s_arm_object_arch, 0 },
4427 { "fpu", s_arm_fpu, 0 },
4428 { "arch_extension", s_arm_arch_extension, 0 },
4430 { "word", s_arm_elf_cons, 4 },
4431 { "long", s_arm_elf_cons, 4 },
4432 { "inst.n", s_arm_elf_inst, 2 },
4433 { "inst.w", s_arm_elf_inst, 4 },
4434 { "inst", s_arm_elf_inst, 0 },
4435 { "rel31", s_arm_rel31, 0 },
4436 { "fnstart", s_arm_unwind_fnstart, 0 },
4437 { "fnend", s_arm_unwind_fnend, 0 },
4438 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4439 { "personality", s_arm_unwind_personality, 0 },
4440 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4441 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4442 { "save", s_arm_unwind_save, 0 },
4443 { "vsave", s_arm_unwind_save, 1 },
4444 { "movsp", s_arm_unwind_movsp, 0 },
4445 { "pad", s_arm_unwind_pad, 0 },
4446 { "setfp", s_arm_unwind_setfp, 0 },
4447 { "unwind_raw", s_arm_unwind_raw, 0 },
4448 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4449 { "tlsdescseq", s_arm_tls_descseq, 0 },
4453 /* These are used for dwarf. */
4457 /* These are used for dwarf2. */
4458 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4459 { "loc", dwarf2_directive_loc, 0 },
4460 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4462 { "extend", float_cons, 'x' },
4463 { "ldouble", float_cons, 'x' },
4464 { "packed", float_cons, 'p' },
4466 {"secrel32", pe_directive_secrel, 0},
4471 /* Parser functions used exclusively in instruction operands. */
4473 /* Generic immediate-value read function for use in insn parsing.
4474 STR points to the beginning of the immediate (the leading #);
4475 VAL receives the value; if the value is outside [MIN, MAX]
4476 issue an error. PREFIX_OPT is true if the immediate prefix is
4480 parse_immediate (char **str, int *val, int min, int max,
4481 bfd_boolean prefix_opt)
4484 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4485 if (exp.X_op != O_constant)
4487 inst.error = _("constant expression required");
4491 if (exp.X_add_number < min || exp.X_add_number > max)
4493 inst.error = _("immediate value out of range");
4497 *val = exp.X_add_number;
4501 /* Less-generic immediate-value read function with the possibility of loading a
4502 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4503 instructions. Puts the result directly in inst.operands[i]. */
4506 parse_big_immediate (char **str, int i)
4511 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4513 if (exp.X_op == O_constant)
4515 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4516 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4517 O_constant. We have to be careful not to break compilation for
4518 32-bit X_add_number, though. */
4519 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4521 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4522 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4523 inst.operands[i].regisimm = 1;
4526 else if (exp.X_op == O_big
4527 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4529 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4531 /* Bignums have their least significant bits in
4532 generic_bignum[0]. Make sure we put 32 bits in imm and
4533 32 bits in reg, in a (hopefully) portable way. */
4534 gas_assert (parts != 0);
4536 /* Make sure that the number is not too big.
4537 PR 11972: Bignums can now be sign-extended to the
4538 size of a .octa so check that the out of range bits
4539 are all zero or all one. */
4540 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4542 LITTLENUM_TYPE m = -1;
4544 if (generic_bignum[parts * 2] != 0
4545 && generic_bignum[parts * 2] != m)
4548 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4549 if (generic_bignum[j] != generic_bignum[j-1])
4553 inst.operands[i].imm = 0;
4554 for (j = 0; j < parts; j++, idx++)
4555 inst.operands[i].imm |= generic_bignum[idx]
4556 << (LITTLENUM_NUMBER_OF_BITS * j);
4557 inst.operands[i].reg = 0;
4558 for (j = 0; j < parts; j++, idx++)
4559 inst.operands[i].reg |= generic_bignum[idx]
4560 << (LITTLENUM_NUMBER_OF_BITS * j);
4561 inst.operands[i].regisimm = 1;
4571 /* Returns the pseudo-register number of an FPA immediate constant,
4572 or FAIL if there isn't a valid constant here. */
4575 parse_fpa_immediate (char ** str)
4577 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4583 /* First try and match exact strings, this is to guarantee
4584 that some formats will work even for cross assembly. */
4586 for (i = 0; fp_const[i]; i++)
4588 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4592 *str += strlen (fp_const[i]);
4593 if (is_end_of_line[(unsigned char) **str])
4599 /* Just because we didn't get a match doesn't mean that the constant
4600 isn't valid, just that it is in a format that we don't
4601 automatically recognize. Try parsing it with the standard
4602 expression routines. */
4604 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4606 /* Look for a raw floating point number. */
4607 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4608 && is_end_of_line[(unsigned char) *save_in])
4610 for (i = 0; i < NUM_FLOAT_VALS; i++)
4612 for (j = 0; j < MAX_LITTLENUMS; j++)
4614 if (words[j] != fp_values[i][j])
4618 if (j == MAX_LITTLENUMS)
4626 /* Try and parse a more complex expression, this will probably fail
4627 unless the code uses a floating point prefix (eg "0f"). */
4628 save_in = input_line_pointer;
4629 input_line_pointer = *str;
4630 if (expression (&exp) == absolute_section
4631 && exp.X_op == O_big
4632 && exp.X_add_number < 0)
4634 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4636 if (gen_to_words (words, 5, (long) 15) == 0)
4638 for (i = 0; i < NUM_FLOAT_VALS; i++)
4640 for (j = 0; j < MAX_LITTLENUMS; j++)
4642 if (words[j] != fp_values[i][j])
4646 if (j == MAX_LITTLENUMS)
4648 *str = input_line_pointer;
4649 input_line_pointer = save_in;
4656 *str = input_line_pointer;
4657 input_line_pointer = save_in;
4658 inst.error = _("invalid FPA immediate expression");
4662 /* Returns 1 if a number has "quarter-precision" float format
4663 0baBbbbbbc defgh000 00000000 00000000. */
4666 is_quarter_float (unsigned imm)
4668 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4669 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4672 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4673 0baBbbbbbc defgh000 00000000 00000000.
4674 The zero and minus-zero cases need special handling, since they can't be
4675 encoded in the "quarter-precision" float format, but can nonetheless be
4676 loaded as integer constants. */
4679 parse_qfloat_immediate (char **ccp, int *immed)
4683 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4684 int found_fpchar = 0;
4686 skip_past_char (&str, '#');
4688 /* We must not accidentally parse an integer as a floating-point number. Make
4689 sure that the value we parse is not an integer by checking for special
4690 characters '.' or 'e'.
4691 FIXME: This is a horrible hack, but doing better is tricky because type
4692 information isn't in a very usable state at parse time. */
4694 skip_whitespace (fpnum);
4696 if (strncmp (fpnum, "0x", 2) == 0)
4700 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4701 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4711 if ((str = atof_ieee (str, 's', words)) != NULL)
4713 unsigned fpword = 0;
4716 /* Our FP word must be 32 bits (single-precision FP). */
4717 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4719 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4723 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4736 /* Shift operands. */
4739 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4742 struct asm_shift_name
4745 enum shift_kind kind;
4748 /* Third argument to parse_shift. */
4749 enum parse_shift_mode
4751 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4752 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4753 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4754 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4755 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4758 /* Parse a <shift> specifier on an ARM data processing instruction.
4759 This has three forms:
4761 (LSL|LSR|ASL|ASR|ROR) Rs
4762 (LSL|LSR|ASL|ASR|ROR) #imm
4765 Note that ASL is assimilated to LSL in the instruction encoding, and
4766 RRX to ROR #0 (which cannot be written as such). */
4769 parse_shift (char **str, int i, enum parse_shift_mode mode)
4771 const struct asm_shift_name *shift_name;
4772 enum shift_kind shift;
4777 for (p = *str; ISALPHA (*p); p++)
4782 inst.error = _("shift expression expected");
4786 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4789 if (shift_name == NULL)
4791 inst.error = _("shift expression expected");
4795 shift = shift_name->kind;
4799 case NO_SHIFT_RESTRICT:
4800 case SHIFT_IMMEDIATE: break;
4802 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4803 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4805 inst.error = _("'LSL' or 'ASR' required");
4810 case SHIFT_LSL_IMMEDIATE:
4811 if (shift != SHIFT_LSL)
4813 inst.error = _("'LSL' required");
4818 case SHIFT_ASR_IMMEDIATE:
4819 if (shift != SHIFT_ASR)
4821 inst.error = _("'ASR' required");
4829 if (shift != SHIFT_RRX)
4831 /* Whitespace can appear here if the next thing is a bare digit. */
4832 skip_whitespace (p);
4834 if (mode == NO_SHIFT_RESTRICT
4835 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4837 inst.operands[i].imm = reg;
4838 inst.operands[i].immisreg = 1;
4840 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4843 inst.operands[i].shift_kind = shift;
4844 inst.operands[i].shifted = 1;
4849 /* Parse a <shifter_operand> for an ARM data processing instruction:
4852 #<immediate>, <rotate>
4856 where <shift> is defined by parse_shift above, and <rotate> is a
4857 multiple of 2 between 0 and 30. Validation of immediate operands
4858 is deferred to md_apply_fix. */
4861 parse_shifter_operand (char **str, int i)
4866 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4868 inst.operands[i].reg = value;
4869 inst.operands[i].isreg = 1;
4871 /* parse_shift will override this if appropriate */
4872 inst.reloc.exp.X_op = O_constant;
4873 inst.reloc.exp.X_add_number = 0;
4875 if (skip_past_comma (str) == FAIL)
4878 /* Shift operation on register. */
4879 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4882 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4885 if (skip_past_comma (str) == SUCCESS)
4887 /* #x, y -- ie explicit rotation by Y. */
4888 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4891 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4893 inst.error = _("constant expression expected");
4897 value = exp.X_add_number;
4898 if (value < 0 || value > 30 || value % 2 != 0)
4900 inst.error = _("invalid rotation");
4903 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4905 inst.error = _("invalid constant");
4909 /* Encode as specified. */
4910 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4914 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4915 inst.reloc.pc_rel = 0;
4919 /* Group relocation information. Each entry in the table contains the
4920 textual name of the relocation as may appear in assembler source
4921 and must end with a colon.
4922 Along with this textual name are the relocation codes to be used if
4923 the corresponding instruction is an ALU instruction (ADD or SUB only),
4924 an LDR, an LDRS, or an LDC. */
4926 struct group_reloc_table_entry
4937 /* Varieties of non-ALU group relocation. */
4944 static struct group_reloc_table_entry group_reloc_table[] =
4945 { /* Program counter relative: */
4947 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4952 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4953 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4954 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4955 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4957 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4962 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4963 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4964 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4965 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4967 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4968 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4969 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4970 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4971 /* Section base relative */
4973 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4978 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4979 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4980 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4981 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4983 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4988 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4989 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4990 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4991 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4993 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4994 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4995 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4996 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4998 /* Given the address of a pointer pointing to the textual name of a group
4999 relocation as may appear in assembler source, attempt to find its details
5000 in group_reloc_table. The pointer will be updated to the character after
5001 the trailing colon. On failure, FAIL will be returned; SUCCESS
5002 otherwise. On success, *entry will be updated to point at the relevant
5003 group_reloc_table entry. */
5006 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5009 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5011 int length = strlen (group_reloc_table[i].name);
5013 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5014 && (*str)[length] == ':')
5016 *out = &group_reloc_table[i];
5017 *str += (length + 1);
5025 /* Parse a <shifter_operand> for an ARM data processing instruction
5026 (as for parse_shifter_operand) where group relocations are allowed:
5029 #<immediate>, <rotate>
5030 #:<group_reloc>:<expression>
5034 where <group_reloc> is one of the strings defined in group_reloc_table.
5035 The hashes are optional.
5037 Everything else is as for parse_shifter_operand. */
5039 static parse_operand_result
5040 parse_shifter_operand_group_reloc (char **str, int i)
5042 /* Determine if we have the sequence of characters #: or just :
5043 coming next. If we do, then we check for a group relocation.
5044 If we don't, punt the whole lot to parse_shifter_operand. */
5046 if (((*str)[0] == '#' && (*str)[1] == ':')
5047 || (*str)[0] == ':')
5049 struct group_reloc_table_entry *entry;
5051 if ((*str)[0] == '#')
5056 /* Try to parse a group relocation. Anything else is an error. */
5057 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5059 inst.error = _("unknown group relocation");
5060 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5063 /* We now have the group relocation table entry corresponding to
5064 the name in the assembler source. Next, we parse the expression. */
5065 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5066 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5068 /* Record the relocation type (always the ALU variant here). */
5069 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5070 gas_assert (inst.reloc.type != 0);
5072 return PARSE_OPERAND_SUCCESS;
5075 return parse_shifter_operand (str, i) == SUCCESS
5076 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5078 /* Never reached. */
5081 /* Parse a Neon alignment expression. Information is written to
5082 inst.operands[i]. We assume the initial ':' has been skipped.
5084 align .imm = align << 8, .immisalign=1, .preind=0 */
5085 static parse_operand_result
5086 parse_neon_alignment (char **str, int i)
5091 my_get_expression (&exp, &p, GE_NO_PREFIX);
5093 if (exp.X_op != O_constant)
5095 inst.error = _("alignment must be constant");
5096 return PARSE_OPERAND_FAIL;
5099 inst.operands[i].imm = exp.X_add_number << 8;
5100 inst.operands[i].immisalign = 1;
5101 /* Alignments are not pre-indexes. */
5102 inst.operands[i].preind = 0;
5105 return PARSE_OPERAND_SUCCESS;
5108 /* Parse all forms of an ARM address expression. Information is written
5109 to inst.operands[i] and/or inst.reloc.
5111 Preindexed addressing (.preind=1):
5113 [Rn, #offset] .reg=Rn .reloc.exp=offset
5114 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5115 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5116 .shift_kind=shift .reloc.exp=shift_imm
5118 These three may have a trailing ! which causes .writeback to be set also.
5120 Postindexed addressing (.postind=1, .writeback=1):
5122 [Rn], #offset .reg=Rn .reloc.exp=offset
5123 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5124 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5125 .shift_kind=shift .reloc.exp=shift_imm
5127 Unindexed addressing (.preind=0, .postind=0):
5129 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5133 [Rn]{!} shorthand for [Rn,#0]{!}
5134 =immediate .isreg=0 .reloc.exp=immediate
5135 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5137 It is the caller's responsibility to check for addressing modes not
5138 supported by the instruction, and to set inst.reloc.type. */
5140 static parse_operand_result
5141 parse_address_main (char **str, int i, int group_relocations,
5142 group_reloc_type group_type)
5147 if (skip_past_char (&p, '[') == FAIL)
5149 if (skip_past_char (&p, '=') == FAIL)
5151 /* Bare address - translate to PC-relative offset. */
5152 inst.reloc.pc_rel = 1;
5153 inst.operands[i].reg = REG_PC;
5154 inst.operands[i].isreg = 1;
5155 inst.operands[i].preind = 1;
5157 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5159 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5160 return PARSE_OPERAND_FAIL;
5163 return PARSE_OPERAND_SUCCESS;
5166 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5168 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5169 return PARSE_OPERAND_FAIL;
5171 inst.operands[i].reg = reg;
5172 inst.operands[i].isreg = 1;
5174 if (skip_past_comma (&p) == SUCCESS)
5176 inst.operands[i].preind = 1;
5179 else if (*p == '-') p++, inst.operands[i].negative = 1;
5181 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5183 inst.operands[i].imm = reg;
5184 inst.operands[i].immisreg = 1;
5186 if (skip_past_comma (&p) == SUCCESS)
5187 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5188 return PARSE_OPERAND_FAIL;
5190 else if (skip_past_char (&p, ':') == SUCCESS)
5192 /* FIXME: '@' should be used here, but it's filtered out by generic
5193 code before we get to see it here. This may be subject to
5195 parse_operand_result result = parse_neon_alignment (&p, i);
5197 if (result != PARSE_OPERAND_SUCCESS)
5202 if (inst.operands[i].negative)
5204 inst.operands[i].negative = 0;
5208 if (group_relocations
5209 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5211 struct group_reloc_table_entry *entry;
5213 /* Skip over the #: or : sequence. */
5219 /* Try to parse a group relocation. Anything else is an
5221 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5223 inst.error = _("unknown group relocation");
5224 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5227 /* We now have the group relocation table entry corresponding to
5228 the name in the assembler source. Next, we parse the
5230 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5231 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5233 /* Record the relocation type. */
5237 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5241 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5245 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5252 if (inst.reloc.type == 0)
5254 inst.error = _("this group relocation is not allowed on this instruction");
5255 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5261 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5262 return PARSE_OPERAND_FAIL;
5263 /* If the offset is 0, find out if it's a +0 or -0. */
5264 if (inst.reloc.exp.X_op == O_constant
5265 && inst.reloc.exp.X_add_number == 0)
5267 skip_whitespace (q);
5271 skip_whitespace (q);
5274 inst.operands[i].negative = 1;
5279 else if (skip_past_char (&p, ':') == SUCCESS)
5281 /* FIXME: '@' should be used here, but it's filtered out by generic code
5282 before we get to see it here. This may be subject to change. */
5283 parse_operand_result result = parse_neon_alignment (&p, i);
5285 if (result != PARSE_OPERAND_SUCCESS)
5289 if (skip_past_char (&p, ']') == FAIL)
5291 inst.error = _("']' expected");
5292 return PARSE_OPERAND_FAIL;
5295 if (skip_past_char (&p, '!') == SUCCESS)
5296 inst.operands[i].writeback = 1;
5298 else if (skip_past_comma (&p) == SUCCESS)
5300 if (skip_past_char (&p, '{') == SUCCESS)
5302 /* [Rn], {expr} - unindexed, with option */
5303 if (parse_immediate (&p, &inst.operands[i].imm,
5304 0, 255, TRUE) == FAIL)
5305 return PARSE_OPERAND_FAIL;
5307 if (skip_past_char (&p, '}') == FAIL)
5309 inst.error = _("'}' expected at end of 'option' field");
5310 return PARSE_OPERAND_FAIL;
5312 if (inst.operands[i].preind)
5314 inst.error = _("cannot combine index with option");
5315 return PARSE_OPERAND_FAIL;
5318 return PARSE_OPERAND_SUCCESS;
5322 inst.operands[i].postind = 1;
5323 inst.operands[i].writeback = 1;
5325 if (inst.operands[i].preind)
5327 inst.error = _("cannot combine pre- and post-indexing");
5328 return PARSE_OPERAND_FAIL;
5332 else if (*p == '-') p++, inst.operands[i].negative = 1;
5334 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5336 /* We might be using the immediate for alignment already. If we
5337 are, OR the register number into the low-order bits. */
5338 if (inst.operands[i].immisalign)
5339 inst.operands[i].imm |= reg;
5341 inst.operands[i].imm = reg;
5342 inst.operands[i].immisreg = 1;
5344 if (skip_past_comma (&p) == SUCCESS)
5345 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5346 return PARSE_OPERAND_FAIL;
5351 if (inst.operands[i].negative)
5353 inst.operands[i].negative = 0;
5356 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5357 return PARSE_OPERAND_FAIL;
5358 /* If the offset is 0, find out if it's a +0 or -0. */
5359 if (inst.reloc.exp.X_op == O_constant
5360 && inst.reloc.exp.X_add_number == 0)
5362 skip_whitespace (q);
5366 skip_whitespace (q);
5369 inst.operands[i].negative = 1;
5375 /* If at this point neither .preind nor .postind is set, we have a
5376 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5377 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5379 inst.operands[i].preind = 1;
5380 inst.reloc.exp.X_op = O_constant;
5381 inst.reloc.exp.X_add_number = 0;
5384 return PARSE_OPERAND_SUCCESS;
5388 parse_address (char **str, int i)
5390 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5394 static parse_operand_result
5395 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5397 return parse_address_main (str, i, 1, type);
5400 /* Parse an operand for a MOVW or MOVT instruction. */
5402 parse_half (char **str)
5407 skip_past_char (&p, '#');
5408 if (strncasecmp (p, ":lower16:", 9) == 0)
5409 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5410 else if (strncasecmp (p, ":upper16:", 9) == 0)
5411 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5413 if (inst.reloc.type != BFD_RELOC_UNUSED)
5416 skip_whitespace (p);
5419 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5422 if (inst.reloc.type == BFD_RELOC_UNUSED)
5424 if (inst.reloc.exp.X_op != O_constant)
5426 inst.error = _("constant expression expected");
5429 if (inst.reloc.exp.X_add_number < 0
5430 || inst.reloc.exp.X_add_number > 0xffff)
5432 inst.error = _("immediate value out of range");
5440 /* Miscellaneous. */
5442 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5443 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5445 parse_psr (char **str, bfd_boolean lhs)
5448 unsigned long psr_field;
5449 const struct asm_psr *psr;
5451 bfd_boolean is_apsr = FALSE;
5452 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5454 /* PR gas/12698: If the user has specified -march=all then m_profile will
5455 be TRUE, but we want to ignore it in this case as we are building for any
5456 CPU type, including non-m variants. */
5457 if (selected_cpu.core == arm_arch_any.core)
5460 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5461 feature for ease of use and backwards compatibility. */
5463 if (strncasecmp (p, "SPSR", 4) == 0)
5466 goto unsupported_psr;
5468 psr_field = SPSR_BIT;
5470 else if (strncasecmp (p, "CPSR", 4) == 0)
5473 goto unsupported_psr;
5477 else if (strncasecmp (p, "APSR", 4) == 0)
5479 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5480 and ARMv7-R architecture CPUs. */
5489 while (ISALNUM (*p) || *p == '_');
5491 if (strncasecmp (start, "iapsr", 5) == 0
5492 || strncasecmp (start, "eapsr", 5) == 0
5493 || strncasecmp (start, "xpsr", 4) == 0
5494 || strncasecmp (start, "psr", 3) == 0)
5495 p = start + strcspn (start, "rR") + 1;
5497 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5503 /* If APSR is being written, a bitfield may be specified. Note that
5504 APSR itself is handled above. */
5505 if (psr->field <= 3)
5507 psr_field = psr->field;
5513 /* M-profile MSR instructions have the mask field set to "10", except
5514 *PSR variants which modify APSR, which may use a different mask (and
5515 have been handled already). Do that by setting the PSR_f field
5517 return psr->field | (lhs ? PSR_f : 0);
5520 goto unsupported_psr;
5526 /* A suffix follows. */
5532 while (ISALNUM (*p) || *p == '_');
5536 /* APSR uses a notation for bits, rather than fields. */
5537 unsigned int nzcvq_bits = 0;
5538 unsigned int g_bit = 0;
5541 for (bit = start; bit != p; bit++)
5543 switch (TOLOWER (*bit))
5546 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5550 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5554 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5558 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5562 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5566 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5570 inst.error = _("unexpected bit specified after APSR");
5575 if (nzcvq_bits == 0x1f)
5580 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5582 inst.error = _("selected processor does not "
5583 "support DSP extension");
5590 if ((nzcvq_bits & 0x20) != 0
5591 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5592 || (g_bit & 0x2) != 0)
5594 inst.error = _("bad bitmask specified after APSR");
5600 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5605 psr_field |= psr->field;
5611 goto error; /* Garbage after "[CS]PSR". */
5613 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5614 is deprecated, but allow it anyway. */
5618 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5621 else if (!m_profile)
5622 /* These bits are never right for M-profile devices: don't set them
5623 (only code paths which read/write APSR reach here). */
5624 psr_field |= (PSR_c | PSR_f);
5630 inst.error = _("selected processor does not support requested special "
5631 "purpose register");
5635 inst.error = _("flag for {c}psr instruction expected");
5639 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5640 value suitable for splatting into the AIF field of the instruction. */
5643 parse_cps_flags (char **str)
5652 case '\0': case ',':
5655 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5656 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5657 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5660 inst.error = _("unrecognized CPS flag");
5665 if (saw_a_flag == 0)
5667 inst.error = _("missing CPS flags");
5675 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5676 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5679 parse_endian_specifier (char **str)
5684 if (strncasecmp (s, "BE", 2))
5686 else if (strncasecmp (s, "LE", 2))
5690 inst.error = _("valid endian specifiers are be or le");
5694 if (ISALNUM (s[2]) || s[2] == '_')
5696 inst.error = _("valid endian specifiers are be or le");
5701 return little_endian;
5704 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5705 value suitable for poking into the rotate field of an sxt or sxta
5706 instruction, or FAIL on error. */
5709 parse_ror (char **str)
5714 if (strncasecmp (s, "ROR", 3) == 0)
5718 inst.error = _("missing rotation field after comma");
5722 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5727 case 0: *str = s; return 0x0;
5728 case 8: *str = s; return 0x1;
5729 case 16: *str = s; return 0x2;
5730 case 24: *str = s; return 0x3;
5733 inst.error = _("rotation can only be 0, 8, 16, or 24");
5738 /* Parse a conditional code (from conds[] below). The value returned is in the
5739 range 0 .. 14, or FAIL. */
5741 parse_cond (char **str)
5744 const struct asm_cond *c;
5746 /* Condition codes are always 2 characters, so matching up to
5747 3 characters is sufficient. */
5752 while (ISALPHA (*q) && n < 3)
5754 cond[n] = TOLOWER (*q);
5759 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5762 inst.error = _("condition required");
5770 /* If the given feature available in the selected CPU, mark it as used.
5771 Returns TRUE iff feature is available. */
5773 mark_feature_used (const arm_feature_set *feature)
5775 /* Ensure the option is valid on the current architecture. */
5776 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5779 /* Add the appropriate architecture feature for the barrier option used.
5782 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5784 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5789 /* Parse an option for a barrier instruction. Returns the encoding for the
5792 parse_barrier (char **str)
5795 const struct asm_barrier_opt *o;
5798 while (ISALPHA (*q))
5801 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5806 if (!mark_feature_used (&o->arch))
5813 /* Parse the operands of a table branch instruction. Similar to a memory
5816 parse_tb (char **str)
5821 if (skip_past_char (&p, '[') == FAIL)
5823 inst.error = _("'[' expected");
5827 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5829 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5832 inst.operands[0].reg = reg;
5834 if (skip_past_comma (&p) == FAIL)
5836 inst.error = _("',' expected");
5840 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5842 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5845 inst.operands[0].imm = reg;
5847 if (skip_past_comma (&p) == SUCCESS)
5849 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5851 if (inst.reloc.exp.X_add_number != 1)
5853 inst.error = _("invalid shift");
5856 inst.operands[0].shifted = 1;
5859 if (skip_past_char (&p, ']') == FAIL)
5861 inst.error = _("']' expected");
5868 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5869 information on the types the operands can take and how they are encoded.
5870 Up to four operands may be read; this function handles setting the
5871 ".present" field for each read operand itself.
5872 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5873 else returns FAIL. */
5876 parse_neon_mov (char **str, int *which_operand)
5878 int i = *which_operand, val;
5879 enum arm_reg_type rtype;
5881 struct neon_type_el optype;
5883 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5885 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5886 inst.operands[i].reg = val;
5887 inst.operands[i].isscalar = 1;
5888 inst.operands[i].vectype = optype;
5889 inst.operands[i++].present = 1;
5891 if (skip_past_comma (&ptr) == FAIL)
5894 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5897 inst.operands[i].reg = val;
5898 inst.operands[i].isreg = 1;
5899 inst.operands[i].present = 1;
5901 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5904 /* Cases 0, 1, 2, 3, 5 (D only). */
5905 if (skip_past_comma (&ptr) == FAIL)
5908 inst.operands[i].reg = val;
5909 inst.operands[i].isreg = 1;
5910 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5911 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5912 inst.operands[i].isvec = 1;
5913 inst.operands[i].vectype = optype;
5914 inst.operands[i++].present = 1;
5916 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5918 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5919 Case 13: VMOV <Sd>, <Rm> */
5920 inst.operands[i].reg = val;
5921 inst.operands[i].isreg = 1;
5922 inst.operands[i].present = 1;
5924 if (rtype == REG_TYPE_NQ)
5926 first_error (_("can't use Neon quad register here"));
5929 else if (rtype != REG_TYPE_VFS)
5932 if (skip_past_comma (&ptr) == FAIL)
5934 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5936 inst.operands[i].reg = val;
5937 inst.operands[i].isreg = 1;
5938 inst.operands[i].present = 1;
5941 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5944 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5945 Case 1: VMOV<c><q> <Dd>, <Dm>
5946 Case 8: VMOV.F32 <Sd>, <Sm>
5947 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5949 inst.operands[i].reg = val;
5950 inst.operands[i].isreg = 1;
5951 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5952 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5953 inst.operands[i].isvec = 1;
5954 inst.operands[i].vectype = optype;
5955 inst.operands[i].present = 1;
5957 if (skip_past_comma (&ptr) == SUCCESS)
5962 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5965 inst.operands[i].reg = val;
5966 inst.operands[i].isreg = 1;
5967 inst.operands[i++].present = 1;
5969 if (skip_past_comma (&ptr) == FAIL)
5972 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5975 inst.operands[i].reg = val;
5976 inst.operands[i].isreg = 1;
5977 inst.operands[i].present = 1;
5980 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5981 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5982 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5983 Case 10: VMOV.F32 <Sd>, #<imm>
5984 Case 11: VMOV.F64 <Dd>, #<imm> */
5985 inst.operands[i].immisfloat = 1;
5986 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5987 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5988 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5992 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5996 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5999 inst.operands[i].reg = val;
6000 inst.operands[i].isreg = 1;
6001 inst.operands[i++].present = 1;
6003 if (skip_past_comma (&ptr) == FAIL)
6006 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6008 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6009 inst.operands[i].reg = val;
6010 inst.operands[i].isscalar = 1;
6011 inst.operands[i].present = 1;
6012 inst.operands[i].vectype = optype;
6014 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6016 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6017 inst.operands[i].reg = val;
6018 inst.operands[i].isreg = 1;
6019 inst.operands[i++].present = 1;
6021 if (skip_past_comma (&ptr) == FAIL)
6024 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6027 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6031 inst.operands[i].reg = val;
6032 inst.operands[i].isreg = 1;
6033 inst.operands[i].isvec = 1;
6034 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6035 inst.operands[i].vectype = optype;
6036 inst.operands[i].present = 1;
6038 if (rtype == REG_TYPE_VFS)
6042 if (skip_past_comma (&ptr) == FAIL)
6044 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6047 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6050 inst.operands[i].reg = val;
6051 inst.operands[i].isreg = 1;
6052 inst.operands[i].isvec = 1;
6053 inst.operands[i].issingle = 1;
6054 inst.operands[i].vectype = optype;
6055 inst.operands[i].present = 1;
6058 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6062 inst.operands[i].reg = val;
6063 inst.operands[i].isreg = 1;
6064 inst.operands[i].isvec = 1;
6065 inst.operands[i].issingle = 1;
6066 inst.operands[i].vectype = optype;
6067 inst.operands[i].present = 1;
6072 first_error (_("parse error"));
6076 /* Successfully parsed the operands. Update args. */
6082 first_error (_("expected comma"));
6086 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6090 /* Use this macro when the operand constraints are different
6091 for ARM and THUMB (e.g. ldrd). */
6092 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6093 ((arm_operand) | ((thumb_operand) << 16))
6095 /* Matcher codes for parse_operands. */
6096 enum operand_parse_code
6098 OP_stop, /* end of line */
6100 OP_RR, /* ARM register */
6101 OP_RRnpc, /* ARM register, not r15 */
6102 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6103 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6104 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6105 optional trailing ! */
6106 OP_RRw, /* ARM register, not r15, optional trailing ! */
6107 OP_RCP, /* Coprocessor number */
6108 OP_RCN, /* Coprocessor register */
6109 OP_RF, /* FPA register */
6110 OP_RVS, /* VFP single precision register */
6111 OP_RVD, /* VFP double precision register (0..15) */
6112 OP_RND, /* Neon double precision register (0..31) */
6113 OP_RNQ, /* Neon quad precision register */
6114 OP_RVSD, /* VFP single or double precision register */
6115 OP_RNDQ, /* Neon double or quad precision register */
6116 OP_RNSDQ, /* Neon single, double or quad precision register */
6117 OP_RNSC, /* Neon scalar D[X] */
6118 OP_RVC, /* VFP control register */
6119 OP_RMF, /* Maverick F register */
6120 OP_RMD, /* Maverick D register */
6121 OP_RMFX, /* Maverick FX register */
6122 OP_RMDX, /* Maverick DX register */
6123 OP_RMAX, /* Maverick AX register */
6124 OP_RMDS, /* Maverick DSPSC register */
6125 OP_RIWR, /* iWMMXt wR register */
6126 OP_RIWC, /* iWMMXt wC register */
6127 OP_RIWG, /* iWMMXt wCG register */
6128 OP_RXA, /* XScale accumulator register */
6130 OP_REGLST, /* ARM register list */
6131 OP_VRSLST, /* VFP single-precision register list */
6132 OP_VRDLST, /* VFP double-precision register list */
6133 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6134 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6135 OP_NSTRLST, /* Neon element/structure list */
6137 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6138 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6139 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6140 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6141 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6142 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6143 OP_VMOV, /* Neon VMOV operands. */
6144 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6145 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6146 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6148 OP_I0, /* immediate zero */
6149 OP_I7, /* immediate value 0 .. 7 */
6150 OP_I15, /* 0 .. 15 */
6151 OP_I16, /* 1 .. 16 */
6152 OP_I16z, /* 0 .. 16 */
6153 OP_I31, /* 0 .. 31 */
6154 OP_I31w, /* 0 .. 31, optional trailing ! */
6155 OP_I32, /* 1 .. 32 */
6156 OP_I32z, /* 0 .. 32 */
6157 OP_I63, /* 0 .. 63 */
6158 OP_I63s, /* -64 .. 63 */
6159 OP_I64, /* 1 .. 64 */
6160 OP_I64z, /* 0 .. 64 */
6161 OP_I255, /* 0 .. 255 */
6163 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6164 OP_I7b, /* 0 .. 7 */
6165 OP_I15b, /* 0 .. 15 */
6166 OP_I31b, /* 0 .. 31 */
6168 OP_SH, /* shifter operand */
6169 OP_SHG, /* shifter operand with possible group relocation */
6170 OP_ADDR, /* Memory address expression (any mode) */
6171 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6172 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6173 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6174 OP_EXP, /* arbitrary expression */
6175 OP_EXPi, /* same, with optional immediate prefix */
6176 OP_EXPr, /* same, with optional relocation suffix */
6177 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6179 OP_CPSF, /* CPS flags */
6180 OP_ENDI, /* Endianness specifier */
6181 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6182 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6183 OP_COND, /* conditional code */
6184 OP_TB, /* Table branch. */
6186 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6188 OP_RRnpc_I0, /* ARM register or literal 0 */
6189 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6190 OP_RR_EXi, /* ARM register or expression with imm prefix */
6191 OP_RF_IF, /* FPA register or immediate */
6192 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6193 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6195 /* Optional operands. */
6196 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6197 OP_oI31b, /* 0 .. 31 */
6198 OP_oI32b, /* 1 .. 32 */
6199 OP_oI32z, /* 0 .. 32 */
6200 OP_oIffffb, /* 0 .. 65535 */
6201 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6203 OP_oRR, /* ARM register */
6204 OP_oRRnpc, /* ARM register, not the PC */
6205 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6206 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6207 OP_oRND, /* Optional Neon double precision register */
6208 OP_oRNQ, /* Optional Neon quad precision register */
6209 OP_oRNDQ, /* Optional Neon double or quad precision register */
6210 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6211 OP_oSHll, /* LSL immediate */
6212 OP_oSHar, /* ASR immediate */
6213 OP_oSHllar, /* LSL or ASR immediate */
6214 OP_oROR, /* ROR 0/8/16/24 */
6215 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6217 /* Some pre-defined mixed (ARM/THUMB) operands. */
6218 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6219 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6220 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6222 OP_FIRST_OPTIONAL = OP_oI7b
6225 /* Generic instruction operand parser. This does no encoding and no
6226 semantic validation; it merely squirrels values away in the inst
6227 structure. Returns SUCCESS or FAIL depending on whether the
6228 specified grammar matched. */
6230 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6232 unsigned const int *upat = pattern;
6233 char *backtrack_pos = 0;
6234 const char *backtrack_error = 0;
6235 int i, val = 0, backtrack_index = 0;
6236 enum arm_reg_type rtype;
6237 parse_operand_result result;
6238 unsigned int op_parse_code;
6240 #define po_char_or_fail(chr) \
6243 if (skip_past_char (&str, chr) == FAIL) \
6248 #define po_reg_or_fail(regtype) \
6251 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6252 & inst.operands[i].vectype); \
6255 first_error (_(reg_expected_msgs[regtype])); \
6258 inst.operands[i].reg = val; \
6259 inst.operands[i].isreg = 1; \
6260 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6261 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6262 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6263 || rtype == REG_TYPE_VFD \
6264 || rtype == REG_TYPE_NQ); \
6268 #define po_reg_or_goto(regtype, label) \
6271 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6272 & inst.operands[i].vectype); \
6276 inst.operands[i].reg = val; \
6277 inst.operands[i].isreg = 1; \
6278 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6279 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6280 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6281 || rtype == REG_TYPE_VFD \
6282 || rtype == REG_TYPE_NQ); \
6286 #define po_imm_or_fail(min, max, popt) \
6289 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6291 inst.operands[i].imm = val; \
6295 #define po_scalar_or_goto(elsz, label) \
6298 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6301 inst.operands[i].reg = val; \
6302 inst.operands[i].isscalar = 1; \
6306 #define po_misc_or_fail(expr) \
6314 #define po_misc_or_fail_no_backtrack(expr) \
6318 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6319 backtrack_pos = 0; \
6320 if (result != PARSE_OPERAND_SUCCESS) \
6325 #define po_barrier_or_imm(str) \
6328 val = parse_barrier (&str); \
6331 if (ISALPHA (*str)) \
6338 if ((inst.instruction & 0xf0) == 0x60 \
6341 /* ISB can only take SY as an option. */ \
6342 inst.error = _("invalid barrier type"); \
6349 skip_whitespace (str);
6351 for (i = 0; upat[i] != OP_stop; i++)
6353 op_parse_code = upat[i];
6354 if (op_parse_code >= 1<<16)
6355 op_parse_code = thumb ? (op_parse_code >> 16)
6356 : (op_parse_code & ((1<<16)-1));
6358 if (op_parse_code >= OP_FIRST_OPTIONAL)
6360 /* Remember where we are in case we need to backtrack. */
6361 gas_assert (!backtrack_pos);
6362 backtrack_pos = str;
6363 backtrack_error = inst.error;
6364 backtrack_index = i;
6367 if (i > 0 && (i > 1 || inst.operands[0].present))
6368 po_char_or_fail (',');
6370 switch (op_parse_code)
6378 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6379 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6380 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6381 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6382 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6383 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6385 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6387 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6389 /* Also accept generic coprocessor regs for unknown registers. */
6391 po_reg_or_fail (REG_TYPE_CN);
6393 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6394 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6395 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6396 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6397 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6398 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6399 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6400 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6401 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6402 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6404 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6406 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6407 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6409 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6411 /* Neon scalar. Using an element size of 8 means that some invalid
6412 scalars are accepted here, so deal with those in later code. */
6413 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6417 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6420 po_imm_or_fail (0, 0, TRUE);
6425 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6430 po_scalar_or_goto (8, try_rr);
6433 po_reg_or_fail (REG_TYPE_RN);
6439 po_scalar_or_goto (8, try_nsdq);
6442 po_reg_or_fail (REG_TYPE_NSDQ);
6448 po_scalar_or_goto (8, try_ndq);
6451 po_reg_or_fail (REG_TYPE_NDQ);
6457 po_scalar_or_goto (8, try_vfd);
6460 po_reg_or_fail (REG_TYPE_VFD);
6465 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6466 not careful then bad things might happen. */
6467 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6472 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6475 /* There's a possibility of getting a 64-bit immediate here, so
6476 we need special handling. */
6477 if (parse_big_immediate (&str, i) == FAIL)
6479 inst.error = _("immediate value is out of range");
6487 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6490 po_imm_or_fail (0, 63, TRUE);
6495 po_char_or_fail ('[');
6496 po_reg_or_fail (REG_TYPE_RN);
6497 po_char_or_fail (']');
6503 po_reg_or_fail (REG_TYPE_RN);
6504 if (skip_past_char (&str, '!') == SUCCESS)
6505 inst.operands[i].writeback = 1;
6509 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6510 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6511 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6512 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6513 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6514 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6515 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6516 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6517 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6518 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6519 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6520 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6522 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6524 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6525 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6527 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6528 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6529 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6530 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6532 /* Immediate variants */
6534 po_char_or_fail ('{');
6535 po_imm_or_fail (0, 255, TRUE);
6536 po_char_or_fail ('}');
6540 /* The expression parser chokes on a trailing !, so we have
6541 to find it first and zap it. */
6544 while (*s && *s != ',')
6549 inst.operands[i].writeback = 1;
6551 po_imm_or_fail (0, 31, TRUE);
6559 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6564 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6569 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6571 if (inst.reloc.exp.X_op == O_symbol)
6573 val = parse_reloc (&str);
6576 inst.error = _("unrecognized relocation suffix");
6579 else if (val != BFD_RELOC_UNUSED)
6581 inst.operands[i].imm = val;
6582 inst.operands[i].hasreloc = 1;
6587 /* Operand for MOVW or MOVT. */
6589 po_misc_or_fail (parse_half (&str));
6592 /* Register or expression. */
6593 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6594 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6596 /* Register or immediate. */
6597 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6598 I0: po_imm_or_fail (0, 0, FALSE); break;
6600 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6602 if (!is_immediate_prefix (*str))
6605 val = parse_fpa_immediate (&str);
6608 /* FPA immediates are encoded as registers 8-15.
6609 parse_fpa_immediate has already applied the offset. */
6610 inst.operands[i].reg = val;
6611 inst.operands[i].isreg = 1;
6614 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6615 I32z: po_imm_or_fail (0, 32, FALSE); break;
6617 /* Two kinds of register. */
6620 struct reg_entry *rege = arm_reg_parse_multi (&str);
6622 || (rege->type != REG_TYPE_MMXWR
6623 && rege->type != REG_TYPE_MMXWC
6624 && rege->type != REG_TYPE_MMXWCG))
6626 inst.error = _("iWMMXt data or control register expected");
6629 inst.operands[i].reg = rege->number;
6630 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6636 struct reg_entry *rege = arm_reg_parse_multi (&str);
6638 || (rege->type != REG_TYPE_MMXWC
6639 && rege->type != REG_TYPE_MMXWCG))
6641 inst.error = _("iWMMXt control register expected");
6644 inst.operands[i].reg = rege->number;
6645 inst.operands[i].isreg = 1;
6650 case OP_CPSF: val = parse_cps_flags (&str); break;
6651 case OP_ENDI: val = parse_endian_specifier (&str); break;
6652 case OP_oROR: val = parse_ror (&str); break;
6653 case OP_COND: val = parse_cond (&str); break;
6654 case OP_oBARRIER_I15:
6655 po_barrier_or_imm (str); break;
6657 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6663 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6664 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6666 inst.error = _("Banked registers are not available with this "
6672 val = parse_psr (&str, op_parse_code == OP_wPSR);
6676 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6679 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6681 if (strncasecmp (str, "APSR_", 5) == 0)
6688 case 'c': found = (found & 1) ? 16 : found | 1; break;
6689 case 'n': found = (found & 2) ? 16 : found | 2; break;
6690 case 'z': found = (found & 4) ? 16 : found | 4; break;
6691 case 'v': found = (found & 8) ? 16 : found | 8; break;
6692 default: found = 16;
6696 inst.operands[i].isvec = 1;
6697 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6698 inst.operands[i].reg = REG_PC;
6705 po_misc_or_fail (parse_tb (&str));
6708 /* Register lists. */
6710 val = parse_reg_list (&str);
6713 inst.operands[1].writeback = 1;
6719 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6723 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6727 /* Allow Q registers too. */
6728 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6733 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6735 inst.operands[i].issingle = 1;
6740 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6745 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6746 &inst.operands[i].vectype);
6749 /* Addressing modes */
6751 po_misc_or_fail (parse_address (&str, i));
6755 po_misc_or_fail_no_backtrack (
6756 parse_address_group_reloc (&str, i, GROUP_LDR));
6760 po_misc_or_fail_no_backtrack (
6761 parse_address_group_reloc (&str, i, GROUP_LDRS));
6765 po_misc_or_fail_no_backtrack (
6766 parse_address_group_reloc (&str, i, GROUP_LDC));
6770 po_misc_or_fail (parse_shifter_operand (&str, i));
6774 po_misc_or_fail_no_backtrack (
6775 parse_shifter_operand_group_reloc (&str, i));
6779 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6783 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6787 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6791 as_fatal (_("unhandled operand code %d"), op_parse_code);
6794 /* Various value-based sanity checks and shared operations. We
6795 do not signal immediate failures for the register constraints;
6796 this allows a syntax error to take precedence. */
6797 switch (op_parse_code)
6805 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6806 inst.error = BAD_PC;
6811 if (inst.operands[i].isreg)
6813 if (inst.operands[i].reg == REG_PC)
6814 inst.error = BAD_PC;
6815 else if (inst.operands[i].reg == REG_SP)
6816 inst.error = BAD_SP;
6821 if (inst.operands[i].isreg
6822 && inst.operands[i].reg == REG_PC
6823 && (inst.operands[i].writeback || thumb))
6824 inst.error = BAD_PC;
6833 case OP_oBARRIER_I15:
6842 inst.operands[i].imm = val;
6849 /* If we get here, this operand was successfully parsed. */
6850 inst.operands[i].present = 1;
6854 inst.error = BAD_ARGS;
6859 /* The parse routine should already have set inst.error, but set a
6860 default here just in case. */
6862 inst.error = _("syntax error");
6866 /* Do not backtrack over a trailing optional argument that
6867 absorbed some text. We will only fail again, with the
6868 'garbage following instruction' error message, which is
6869 probably less helpful than the current one. */
6870 if (backtrack_index == i && backtrack_pos != str
6871 && upat[i+1] == OP_stop)
6874 inst.error = _("syntax error");
6878 /* Try again, skipping the optional argument at backtrack_pos. */
6879 str = backtrack_pos;
6880 inst.error = backtrack_error;
6881 inst.operands[backtrack_index].present = 0;
6882 i = backtrack_index;
6886 /* Check that we have parsed all the arguments. */
6887 if (*str != '\0' && !inst.error)
6888 inst.error = _("garbage following instruction");
6890 return inst.error ? FAIL : SUCCESS;
6893 #undef po_char_or_fail
6894 #undef po_reg_or_fail
6895 #undef po_reg_or_goto
6896 #undef po_imm_or_fail
6897 #undef po_scalar_or_fail
6898 #undef po_barrier_or_imm
6900 /* Shorthand macro for instruction encoding functions issuing errors. */
6901 #define constraint(expr, err) \
6912 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6913 instructions are unpredictable if these registers are used. This
6914 is the BadReg predicate in ARM's Thumb-2 documentation. */
6915 #define reject_bad_reg(reg) \
6917 if (reg == REG_SP || reg == REG_PC) \
6919 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6924 /* If REG is R13 (the stack pointer), warn that its use is
6926 #define warn_deprecated_sp(reg) \
6928 if (warn_on_deprecated && reg == REG_SP) \
6929 as_warn (_("use of r13 is deprecated")); \
6932 /* Functions for operand encoding. ARM, then Thumb. */
6934 #define rotate_left(v, n) (v << n | v >> (32 - n))
6936 /* If VAL can be encoded in the immediate field of an ARM instruction,
6937 return the encoded form. Otherwise, return FAIL. */
6940 encode_arm_immediate (unsigned int val)
6944 for (i = 0; i < 32; i += 2)
6945 if ((a = rotate_left (val, i)) <= 0xff)
6946 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6951 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6952 return the encoded form. Otherwise, return FAIL. */
6954 encode_thumb32_immediate (unsigned int val)
6961 for (i = 1; i <= 24; i++)
6964 if ((val & ~(0xff << i)) == 0)
6965 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6969 if (val == ((a << 16) | a))
6971 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6975 if (val == ((a << 16) | a))
6976 return 0x200 | (a >> 8);
6980 /* Encode a VFP SP or DP register number into inst.instruction. */
6983 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6985 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6988 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6991 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6994 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6999 first_error (_("D register out of range for selected VFP version"));
7007 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7011 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7015 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7019 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7023 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7027 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7035 /* Encode a <shift> in an ARM-format instruction. The immediate,
7036 if any, is handled by md_apply_fix. */
7038 encode_arm_shift (int i)
7040 if (inst.operands[i].shift_kind == SHIFT_RRX)
7041 inst.instruction |= SHIFT_ROR << 5;
7044 inst.instruction |= inst.operands[i].shift_kind << 5;
7045 if (inst.operands[i].immisreg)
7047 inst.instruction |= SHIFT_BY_REG;
7048 inst.instruction |= inst.operands[i].imm << 8;
7051 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7056 encode_arm_shifter_operand (int i)
7058 if (inst.operands[i].isreg)
7060 inst.instruction |= inst.operands[i].reg;
7061 encode_arm_shift (i);
7065 inst.instruction |= INST_IMMEDIATE;
7066 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7067 inst.instruction |= inst.operands[i].imm;
7071 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7073 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7076 Generate an error if the operand is not a register. */
7077 constraint (!inst.operands[i].isreg,
7078 _("Instruction does not support =N addresses"));
7080 inst.instruction |= inst.operands[i].reg << 16;
7082 if (inst.operands[i].preind)
7086 inst.error = _("instruction does not accept preindexed addressing");
7089 inst.instruction |= PRE_INDEX;
7090 if (inst.operands[i].writeback)
7091 inst.instruction |= WRITE_BACK;
7094 else if (inst.operands[i].postind)
7096 gas_assert (inst.operands[i].writeback);
7098 inst.instruction |= WRITE_BACK;
7100 else /* unindexed - only for coprocessor */
7102 inst.error = _("instruction does not accept unindexed addressing");
7106 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7107 && (((inst.instruction & 0x000f0000) >> 16)
7108 == ((inst.instruction & 0x0000f000) >> 12)))
7109 as_warn ((inst.instruction & LOAD_BIT)
7110 ? _("destination register same as write-back base")
7111 : _("source register same as write-back base"));
7114 /* inst.operands[i] was set up by parse_address. Encode it into an
7115 ARM-format mode 2 load or store instruction. If is_t is true,
7116 reject forms that cannot be used with a T instruction (i.e. not
7119 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7121 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7123 encode_arm_addr_mode_common (i, is_t);
7125 if (inst.operands[i].immisreg)
7127 constraint ((inst.operands[i].imm == REG_PC
7128 || (is_pc && inst.operands[i].writeback)),
7130 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7131 inst.instruction |= inst.operands[i].imm;
7132 if (!inst.operands[i].negative)
7133 inst.instruction |= INDEX_UP;
7134 if (inst.operands[i].shifted)
7136 if (inst.operands[i].shift_kind == SHIFT_RRX)
7137 inst.instruction |= SHIFT_ROR << 5;
7140 inst.instruction |= inst.operands[i].shift_kind << 5;
7141 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7145 else /* immediate offset in inst.reloc */
7147 if (is_pc && !inst.reloc.pc_rel)
7149 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7151 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7152 cannot use PC in addressing.
7153 PC cannot be used in writeback addressing, either. */
7154 constraint ((is_t || inst.operands[i].writeback),
7157 /* Use of PC in str is deprecated for ARMv7. */
7158 if (warn_on_deprecated
7160 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7161 as_warn (_("use of PC in this instruction is deprecated"));
7164 if (inst.reloc.type == BFD_RELOC_UNUSED)
7166 /* Prefer + for zero encoded value. */
7167 if (!inst.operands[i].negative)
7168 inst.instruction |= INDEX_UP;
7169 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7174 /* inst.operands[i] was set up by parse_address. Encode it into an
7175 ARM-format mode 3 load or store instruction. Reject forms that
7176 cannot be used with such instructions. If is_t is true, reject
7177 forms that cannot be used with a T instruction (i.e. not
7180 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7182 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7184 inst.error = _("instruction does not accept scaled register index");
7188 encode_arm_addr_mode_common (i, is_t);
7190 if (inst.operands[i].immisreg)
7192 constraint ((inst.operands[i].imm == REG_PC
7193 || inst.operands[i].reg == REG_PC),
7195 inst.instruction |= inst.operands[i].imm;
7196 if (!inst.operands[i].negative)
7197 inst.instruction |= INDEX_UP;
7199 else /* immediate offset in inst.reloc */
7201 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7202 && inst.operands[i].writeback),
7204 inst.instruction |= HWOFFSET_IMM;
7205 if (inst.reloc.type == BFD_RELOC_UNUSED)
7207 /* Prefer + for zero encoded value. */
7208 if (!inst.operands[i].negative)
7209 inst.instruction |= INDEX_UP;
7211 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7216 /* inst.operands[i] was set up by parse_address. Encode it into an
7217 ARM-format instruction. Reject all forms which cannot be encoded
7218 into a coprocessor load/store instruction. If wb_ok is false,
7219 reject use of writeback; if unind_ok is false, reject use of
7220 unindexed addressing. If reloc_override is not 0, use it instead
7221 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7222 (in which case it is preserved). */
7225 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7227 inst.instruction |= inst.operands[i].reg << 16;
7229 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7231 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7233 gas_assert (!inst.operands[i].writeback);
7236 inst.error = _("instruction does not support unindexed addressing");
7239 inst.instruction |= inst.operands[i].imm;
7240 inst.instruction |= INDEX_UP;
7244 if (inst.operands[i].preind)
7245 inst.instruction |= PRE_INDEX;
7247 if (inst.operands[i].writeback)
7249 if (inst.operands[i].reg == REG_PC)
7251 inst.error = _("pc may not be used with write-back");
7256 inst.error = _("instruction does not support writeback");
7259 inst.instruction |= WRITE_BACK;
7263 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7264 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7265 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7266 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7269 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7271 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7274 /* Prefer + for zero encoded value. */
7275 if (!inst.operands[i].negative)
7276 inst.instruction |= INDEX_UP;
7281 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7282 Determine whether it can be performed with a move instruction; if
7283 it can, convert inst.instruction to that move instruction and
7284 return TRUE; if it can't, convert inst.instruction to a literal-pool
7285 load and return FALSE. If this is not a valid thing to do in the
7286 current context, set inst.error and return TRUE.
7288 inst.operands[i] describes the destination register. */
7291 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7296 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7300 if ((inst.instruction & tbit) == 0)
7302 inst.error = _("invalid pseudo operation");
7305 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7307 inst.error = _("constant expression expected");
7310 if (inst.reloc.exp.X_op == O_constant)
7314 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7316 /* This can be done with a mov(1) instruction. */
7317 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7318 inst.instruction |= inst.reloc.exp.X_add_number;
7324 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7327 /* This can be done with a mov instruction. */
7328 inst.instruction &= LITERAL_MASK;
7329 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7330 inst.instruction |= value & 0xfff;
7334 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7337 /* This can be done with a mvn instruction. */
7338 inst.instruction &= LITERAL_MASK;
7339 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7340 inst.instruction |= value & 0xfff;
7346 if (add_to_lit_pool () == FAIL)
7348 inst.error = _("literal pool insertion failed");
7351 inst.operands[1].reg = REG_PC;
7352 inst.operands[1].isreg = 1;
7353 inst.operands[1].preind = 1;
7354 inst.reloc.pc_rel = 1;
7355 inst.reloc.type = (thumb_p
7356 ? BFD_RELOC_ARM_THUMB_OFFSET
7358 ? BFD_RELOC_ARM_HWLITERAL
7359 : BFD_RELOC_ARM_LITERAL));
7363 /* Functions for instruction encoding, sorted by sub-architecture.
7364 First some generics; their names are taken from the conventional
7365 bit positions for register arguments in ARM format instructions. */
7375 inst.instruction |= inst.operands[0].reg << 12;
7381 inst.instruction |= inst.operands[0].reg << 12;
7382 inst.instruction |= inst.operands[1].reg;
7388 inst.instruction |= inst.operands[0].reg;
7389 inst.instruction |= inst.operands[1].reg << 16;
7395 inst.instruction |= inst.operands[0].reg << 12;
7396 inst.instruction |= inst.operands[1].reg << 16;
7402 inst.instruction |= inst.operands[0].reg << 16;
7403 inst.instruction |= inst.operands[1].reg << 12;
7407 check_obsolete (const arm_feature_set *feature, const char *msg)
7409 if (ARM_CPU_IS_ANY (cpu_variant))
7411 as_warn ("%s", msg);
7414 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7426 unsigned Rn = inst.operands[2].reg;
7427 /* Enforce restrictions on SWP instruction. */
7428 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7430 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7431 _("Rn must not overlap other operands"));
7433 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7435 if (!check_obsolete (&arm_ext_v8,
7436 _("swp{b} use is obsoleted for ARMv8 and later"))
7437 && warn_on_deprecated
7438 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7439 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7442 inst.instruction |= inst.operands[0].reg << 12;
7443 inst.instruction |= inst.operands[1].reg;
7444 inst.instruction |= Rn << 16;
7450 inst.instruction |= inst.operands[0].reg << 12;
7451 inst.instruction |= inst.operands[1].reg << 16;
7452 inst.instruction |= inst.operands[2].reg;
7458 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7459 constraint (((inst.reloc.exp.X_op != O_constant
7460 && inst.reloc.exp.X_op != O_illegal)
7461 || inst.reloc.exp.X_add_number != 0),
7463 inst.instruction |= inst.operands[0].reg;
7464 inst.instruction |= inst.operands[1].reg << 12;
7465 inst.instruction |= inst.operands[2].reg << 16;
7471 inst.instruction |= inst.operands[0].imm;
7477 inst.instruction |= inst.operands[0].reg << 12;
7478 encode_arm_cp_address (1, TRUE, TRUE, 0);
7481 /* ARM instructions, in alphabetical order by function name (except
7482 that wrapper functions appear immediately after the function they
7485 /* This is a pseudo-op of the form "adr rd, label" to be converted
7486 into a relative address of the form "add rd, pc, #label-.-8". */
7491 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7493 /* Frag hacking will turn this into a sub instruction if the offset turns
7494 out to be negative. */
7495 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7496 inst.reloc.pc_rel = 1;
7497 inst.reloc.exp.X_add_number -= 8;
7500 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7501 into a relative address of the form:
7502 add rd, pc, #low(label-.-8)"
7503 add rd, rd, #high(label-.-8)" */
7508 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7510 /* Frag hacking will turn this into a sub instruction if the offset turns
7511 out to be negative. */
7512 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7513 inst.reloc.pc_rel = 1;
7514 inst.size = INSN_SIZE * 2;
7515 inst.reloc.exp.X_add_number -= 8;
7521 if (!inst.operands[1].present)
7522 inst.operands[1].reg = inst.operands[0].reg;
7523 inst.instruction |= inst.operands[0].reg << 12;
7524 inst.instruction |= inst.operands[1].reg << 16;
7525 encode_arm_shifter_operand (2);
7531 if (inst.operands[0].present)
7533 constraint ((inst.instruction & 0xf0) != 0x40
7534 && inst.operands[0].imm > 0xf
7535 && inst.operands[0].imm < 0x0,
7536 _("bad barrier type"));
7537 inst.instruction |= inst.operands[0].imm;
7540 inst.instruction |= 0xf;
7546 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7547 constraint (msb > 32, _("bit-field extends past end of register"));
7548 /* The instruction encoding stores the LSB and MSB,
7549 not the LSB and width. */
7550 inst.instruction |= inst.operands[0].reg << 12;
7551 inst.instruction |= inst.operands[1].imm << 7;
7552 inst.instruction |= (msb - 1) << 16;
7560 /* #0 in second position is alternative syntax for bfc, which is
7561 the same instruction but with REG_PC in the Rm field. */
7562 if (!inst.operands[1].isreg)
7563 inst.operands[1].reg = REG_PC;
7565 msb = inst.operands[2].imm + inst.operands[3].imm;
7566 constraint (msb > 32, _("bit-field extends past end of register"));
7567 /* The instruction encoding stores the LSB and MSB,
7568 not the LSB and width. */
7569 inst.instruction |= inst.operands[0].reg << 12;
7570 inst.instruction |= inst.operands[1].reg;
7571 inst.instruction |= inst.operands[2].imm << 7;
7572 inst.instruction |= (msb - 1) << 16;
7578 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7579 _("bit-field extends past end of register"));
7580 inst.instruction |= inst.operands[0].reg << 12;
7581 inst.instruction |= inst.operands[1].reg;
7582 inst.instruction |= inst.operands[2].imm << 7;
7583 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7586 /* ARM V5 breakpoint instruction (argument parse)
7587 BKPT <16 bit unsigned immediate>
7588 Instruction is not conditional.
7589 The bit pattern given in insns[] has the COND_ALWAYS condition,
7590 and it is an error if the caller tried to override that. */
7595 /* Top 12 of 16 bits to bits 19:8. */
7596 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7598 /* Bottom 4 of 16 bits to bits 3:0. */
7599 inst.instruction |= inst.operands[0].imm & 0xf;
7603 encode_branch (int default_reloc)
7605 if (inst.operands[0].hasreloc)
7607 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7608 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7609 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7610 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7611 ? BFD_RELOC_ARM_PLT32
7612 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7615 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7616 inst.reloc.pc_rel = 1;
7623 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7624 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7627 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7634 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7636 if (inst.cond == COND_ALWAYS)
7637 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7639 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7643 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7646 /* ARM V5 branch-link-exchange instruction (argument parse)
7647 BLX <target_addr> ie BLX(1)
7648 BLX{<condition>} <Rm> ie BLX(2)
7649 Unfortunately, there are two different opcodes for this mnemonic.
7650 So, the insns[].value is not used, and the code here zaps values
7651 into inst.instruction.
7652 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7657 if (inst.operands[0].isreg)
7659 /* Arg is a register; the opcode provided by insns[] is correct.
7660 It is not illegal to do "blx pc", just useless. */
7661 if (inst.operands[0].reg == REG_PC)
7662 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7664 inst.instruction |= inst.operands[0].reg;
7668 /* Arg is an address; this instruction cannot be executed
7669 conditionally, and the opcode must be adjusted.
7670 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7671 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7672 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7673 inst.instruction = 0xfa000000;
7674 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7681 bfd_boolean want_reloc;
7683 if (inst.operands[0].reg == REG_PC)
7684 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7686 inst.instruction |= inst.operands[0].reg;
7687 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7688 it is for ARMv4t or earlier. */
7689 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7690 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7694 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7699 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7703 /* ARM v5TEJ. Jump to Jazelle code. */
7708 if (inst.operands[0].reg == REG_PC)
7709 as_tsktsk (_("use of r15 in bxj is not really useful"));
7711 inst.instruction |= inst.operands[0].reg;
7714 /* Co-processor data operation:
7715 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7716 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7720 inst.instruction |= inst.operands[0].reg << 8;
7721 inst.instruction |= inst.operands[1].imm << 20;
7722 inst.instruction |= inst.operands[2].reg << 12;
7723 inst.instruction |= inst.operands[3].reg << 16;
7724 inst.instruction |= inst.operands[4].reg;
7725 inst.instruction |= inst.operands[5].imm << 5;
7731 inst.instruction |= inst.operands[0].reg << 16;
7732 encode_arm_shifter_operand (1);
7735 /* Transfer between coprocessor and ARM registers.
7736 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7741 No special properties. */
7743 struct deprecated_coproc_regs_s
7750 arm_feature_set deprecated;
7751 arm_feature_set obsoleted;
7752 const char *dep_msg;
7753 const char *obs_msg;
7756 #define DEPR_ACCESS_V8 \
7757 N_("This coprocessor register access is deprecated in ARMv8")
7759 /* Table of all deprecated coprocessor registers. */
7760 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7762 {15, 0, 7, 10, 5, /* CP15DMB. */
7763 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7764 DEPR_ACCESS_V8, NULL},
7765 {15, 0, 7, 10, 4, /* CP15DSB. */
7766 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7767 DEPR_ACCESS_V8, NULL},
7768 {15, 0, 7, 5, 4, /* CP15ISB. */
7769 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7770 DEPR_ACCESS_V8, NULL},
7771 {14, 6, 1, 0, 0, /* TEEHBR. */
7772 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7773 DEPR_ACCESS_V8, NULL},
7774 {14, 6, 0, 0, 0, /* TEECR. */
7775 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7776 DEPR_ACCESS_V8, NULL},
7779 #undef DEPR_ACCESS_V8
7781 static const size_t deprecated_coproc_reg_count =
7782 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7790 Rd = inst.operands[2].reg;
7793 if (inst.instruction == 0xee000010
7794 || inst.instruction == 0xfe000010)
7796 reject_bad_reg (Rd);
7799 constraint (Rd == REG_SP, BAD_SP);
7804 if (inst.instruction == 0xe000010)
7805 constraint (Rd == REG_PC, BAD_PC);
7808 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7810 const struct deprecated_coproc_regs_s *r =
7811 deprecated_coproc_regs + i;
7813 if (inst.operands[0].reg == r->cp
7814 && inst.operands[1].imm == r->opc1
7815 && inst.operands[3].reg == r->crn
7816 && inst.operands[4].reg == r->crm
7817 && inst.operands[5].imm == r->opc2)
7819 if (!check_obsolete (&r->obsoleted, r->obs_msg)
7820 && warn_on_deprecated
7821 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7822 as_warn ("%s", r->dep_msg);
7826 inst.instruction |= inst.operands[0].reg << 8;
7827 inst.instruction |= inst.operands[1].imm << 21;
7828 inst.instruction |= Rd << 12;
7829 inst.instruction |= inst.operands[3].reg << 16;
7830 inst.instruction |= inst.operands[4].reg;
7831 inst.instruction |= inst.operands[5].imm << 5;
7834 /* Transfer between coprocessor register and pair of ARM registers.
7835 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7840 Two XScale instructions are special cases of these:
7842 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7843 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7845 Result unpredictable if Rd or Rn is R15. */
7852 Rd = inst.operands[2].reg;
7853 Rn = inst.operands[3].reg;
7857 reject_bad_reg (Rd);
7858 reject_bad_reg (Rn);
7862 constraint (Rd == REG_PC, BAD_PC);
7863 constraint (Rn == REG_PC, BAD_PC);
7866 inst.instruction |= inst.operands[0].reg << 8;
7867 inst.instruction |= inst.operands[1].imm << 4;
7868 inst.instruction |= Rd << 12;
7869 inst.instruction |= Rn << 16;
7870 inst.instruction |= inst.operands[4].reg;
7876 inst.instruction |= inst.operands[0].imm << 6;
7877 if (inst.operands[1].present)
7879 inst.instruction |= CPSI_MMOD;
7880 inst.instruction |= inst.operands[1].imm;
7887 inst.instruction |= inst.operands[0].imm;
7893 unsigned Rd, Rn, Rm;
7895 Rd = inst.operands[0].reg;
7896 Rn = (inst.operands[1].present
7897 ? inst.operands[1].reg : Rd);
7898 Rm = inst.operands[2].reg;
7900 constraint ((Rd == REG_PC), BAD_PC);
7901 constraint ((Rn == REG_PC), BAD_PC);
7902 constraint ((Rm == REG_PC), BAD_PC);
7904 inst.instruction |= Rd << 16;
7905 inst.instruction |= Rn << 0;
7906 inst.instruction |= Rm << 8;
7912 /* There is no IT instruction in ARM mode. We
7913 process it to do the validation as if in
7914 thumb mode, just in case the code gets
7915 assembled for thumb using the unified syntax. */
7920 set_it_insn_type (IT_INSN);
7921 now_it.mask = (inst.instruction & 0xf) | 0x10;
7922 now_it.cc = inst.operands[0].imm;
7926 /* If there is only one register in the register list,
7927 then return its register number. Otherwise return -1. */
7929 only_one_reg_in_list (int range)
7931 int i = ffs (range) - 1;
7932 return (i > 15 || range != (1 << i)) ? -1 : i;
7936 encode_ldmstm(int from_push_pop_mnem)
7938 int base_reg = inst.operands[0].reg;
7939 int range = inst.operands[1].imm;
7942 inst.instruction |= base_reg << 16;
7943 inst.instruction |= range;
7945 if (inst.operands[1].writeback)
7946 inst.instruction |= LDM_TYPE_2_OR_3;
7948 if (inst.operands[0].writeback)
7950 inst.instruction |= WRITE_BACK;
7951 /* Check for unpredictable uses of writeback. */
7952 if (inst.instruction & LOAD_BIT)
7954 /* Not allowed in LDM type 2. */
7955 if ((inst.instruction & LDM_TYPE_2_OR_3)
7956 && ((range & (1 << REG_PC)) == 0))
7957 as_warn (_("writeback of base register is UNPREDICTABLE"));
7958 /* Only allowed if base reg not in list for other types. */
7959 else if (range & (1 << base_reg))
7960 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7964 /* Not allowed for type 2. */
7965 if (inst.instruction & LDM_TYPE_2_OR_3)
7966 as_warn (_("writeback of base register is UNPREDICTABLE"));
7967 /* Only allowed if base reg not in list, or first in list. */
7968 else if ((range & (1 << base_reg))
7969 && (range & ((1 << base_reg) - 1)))
7970 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7974 /* If PUSH/POP has only one register, then use the A2 encoding. */
7975 one_reg = only_one_reg_in_list (range);
7976 if (from_push_pop_mnem && one_reg >= 0)
7978 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7980 inst.instruction &= A_COND_MASK;
7981 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7982 inst.instruction |= one_reg << 12;
7989 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
7992 /* ARMv5TE load-consecutive (argument parse)
8001 constraint (inst.operands[0].reg % 2 != 0,
8002 _("first transfer register must be even"));
8003 constraint (inst.operands[1].present
8004 && inst.operands[1].reg != inst.operands[0].reg + 1,
8005 _("can only transfer two consecutive registers"));
8006 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8007 constraint (!inst.operands[2].isreg, _("'[' expected"));
8009 if (!inst.operands[1].present)
8010 inst.operands[1].reg = inst.operands[0].reg + 1;
8012 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8013 register and the first register written; we have to diagnose
8014 overlap between the base and the second register written here. */
8016 if (inst.operands[2].reg == inst.operands[1].reg
8017 && (inst.operands[2].writeback || inst.operands[2].postind))
8018 as_warn (_("base register written back, and overlaps "
8019 "second transfer register"));
8021 if (!(inst.instruction & V4_STR_BIT))
8023 /* For an index-register load, the index register must not overlap the
8024 destination (even if not write-back). */
8025 if (inst.operands[2].immisreg
8026 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8027 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8028 as_warn (_("index register overlaps transfer register"));
8030 inst.instruction |= inst.operands[0].reg << 12;
8031 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8037 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8038 || inst.operands[1].postind || inst.operands[1].writeback
8039 || inst.operands[1].immisreg || inst.operands[1].shifted
8040 || inst.operands[1].negative
8041 /* This can arise if the programmer has written
8043 or if they have mistakenly used a register name as the last
8046 It is very difficult to distinguish between these two cases
8047 because "rX" might actually be a label. ie the register
8048 name has been occluded by a symbol of the same name. So we
8049 just generate a general 'bad addressing mode' type error
8050 message and leave it up to the programmer to discover the
8051 true cause and fix their mistake. */
8052 || (inst.operands[1].reg == REG_PC),
8055 constraint (inst.reloc.exp.X_op != O_constant
8056 || inst.reloc.exp.X_add_number != 0,
8057 _("offset must be zero in ARM encoding"));
8059 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8061 inst.instruction |= inst.operands[0].reg << 12;
8062 inst.instruction |= inst.operands[1].reg << 16;
8063 inst.reloc.type = BFD_RELOC_UNUSED;
8069 constraint (inst.operands[0].reg % 2 != 0,
8070 _("even register required"));
8071 constraint (inst.operands[1].present
8072 && inst.operands[1].reg != inst.operands[0].reg + 1,
8073 _("can only load two consecutive registers"));
8074 /* If op 1 were present and equal to PC, this function wouldn't
8075 have been called in the first place. */
8076 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8078 inst.instruction |= inst.operands[0].reg << 12;
8079 inst.instruction |= inst.operands[2].reg << 16;
8082 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8083 which is not a multiple of four is UNPREDICTABLE. */
8085 check_ldr_r15_aligned (void)
8087 constraint (!(inst.operands[1].immisreg)
8088 && (inst.operands[0].reg == REG_PC
8089 && inst.operands[1].reg == REG_PC
8090 && (inst.reloc.exp.X_add_number & 0x3)),
8091 _("ldr to register 15 must be 4-byte alligned"));
8097 inst.instruction |= inst.operands[0].reg << 12;
8098 if (!inst.operands[1].isreg)
8099 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8101 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8102 check_ldr_r15_aligned ();
8108 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8110 if (inst.operands[1].preind)
8112 constraint (inst.reloc.exp.X_op != O_constant
8113 || inst.reloc.exp.X_add_number != 0,
8114 _("this instruction requires a post-indexed address"));
8116 inst.operands[1].preind = 0;
8117 inst.operands[1].postind = 1;
8118 inst.operands[1].writeback = 1;
8120 inst.instruction |= inst.operands[0].reg << 12;
8121 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8124 /* Halfword and signed-byte load/store operations. */
8129 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8130 inst.instruction |= inst.operands[0].reg << 12;
8131 if (!inst.operands[1].isreg)
8132 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8134 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8140 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8142 if (inst.operands[1].preind)
8144 constraint (inst.reloc.exp.X_op != O_constant
8145 || inst.reloc.exp.X_add_number != 0,
8146 _("this instruction requires a post-indexed address"));
8148 inst.operands[1].preind = 0;
8149 inst.operands[1].postind = 1;
8150 inst.operands[1].writeback = 1;
8152 inst.instruction |= inst.operands[0].reg << 12;
8153 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8156 /* Co-processor register load/store.
8157 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8161 inst.instruction |= inst.operands[0].reg << 8;
8162 inst.instruction |= inst.operands[1].reg << 12;
8163 encode_arm_cp_address (2, TRUE, TRUE, 0);
8169 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8170 if (inst.operands[0].reg == inst.operands[1].reg
8171 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8172 && !(inst.instruction & 0x00400000))
8173 as_tsktsk (_("Rd and Rm should be different in mla"));
8175 inst.instruction |= inst.operands[0].reg << 16;
8176 inst.instruction |= inst.operands[1].reg;
8177 inst.instruction |= inst.operands[2].reg << 8;
8178 inst.instruction |= inst.operands[3].reg << 12;
8184 inst.instruction |= inst.operands[0].reg << 12;
8185 encode_arm_shifter_operand (1);
8188 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8195 top = (inst.instruction & 0x00400000) != 0;
8196 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8197 _(":lower16: not allowed this instruction"));
8198 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8199 _(":upper16: not allowed instruction"));
8200 inst.instruction |= inst.operands[0].reg << 12;
8201 if (inst.reloc.type == BFD_RELOC_UNUSED)
8203 imm = inst.reloc.exp.X_add_number;
8204 /* The value is in two pieces: 0:11, 16:19. */
8205 inst.instruction |= (imm & 0x00000fff);
8206 inst.instruction |= (imm & 0x0000f000) << 4;
8210 static void do_vfp_nsyn_opcode (const char *);
8213 do_vfp_nsyn_mrs (void)
8215 if (inst.operands[0].isvec)
8217 if (inst.operands[1].reg != 1)
8218 first_error (_("operand 1 must be FPSCR"));
8219 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8220 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8221 do_vfp_nsyn_opcode ("fmstat");
8223 else if (inst.operands[1].isvec)
8224 do_vfp_nsyn_opcode ("fmrx");
8232 do_vfp_nsyn_msr (void)
8234 if (inst.operands[0].isvec)
8235 do_vfp_nsyn_opcode ("fmxr");
8245 unsigned Rt = inst.operands[0].reg;
8247 if (thumb_mode && inst.operands[0].reg == REG_SP)
8249 inst.error = BAD_SP;
8253 /* APSR_ sets isvec. All other refs to PC are illegal. */
8254 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8256 inst.error = BAD_PC;
8260 switch (inst.operands[1].reg)
8267 inst.instruction |= (inst.operands[1].reg << 16);
8270 first_error (_("operand 1 must be a VFP extension System Register"));
8273 inst.instruction |= (Rt << 12);
8279 unsigned Rt = inst.operands[1].reg;
8282 reject_bad_reg (Rt);
8283 else if (Rt == REG_PC)
8285 inst.error = BAD_PC;
8289 switch (inst.operands[0].reg)
8294 inst.instruction |= (inst.operands[0].reg << 16);
8297 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8300 inst.instruction |= (Rt << 12);
8308 if (do_vfp_nsyn_mrs () == SUCCESS)
8311 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8312 inst.instruction |= inst.operands[0].reg << 12;
8314 if (inst.operands[1].isreg)
8316 br = inst.operands[1].reg;
8317 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8318 as_bad (_("bad register for mrs"));
8322 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8323 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8325 _("'APSR', 'CPSR' or 'SPSR' expected"));
8326 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8329 inst.instruction |= br;
8332 /* Two possible forms:
8333 "{C|S}PSR_<field>, Rm",
8334 "{C|S}PSR_f, #expression". */
8339 if (do_vfp_nsyn_msr () == SUCCESS)
8342 inst.instruction |= inst.operands[0].imm;
8343 if (inst.operands[1].isreg)
8344 inst.instruction |= inst.operands[1].reg;
8347 inst.instruction |= INST_IMMEDIATE;
8348 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8349 inst.reloc.pc_rel = 0;
8356 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8358 if (!inst.operands[2].present)
8359 inst.operands[2].reg = inst.operands[0].reg;
8360 inst.instruction |= inst.operands[0].reg << 16;
8361 inst.instruction |= inst.operands[1].reg;
8362 inst.instruction |= inst.operands[2].reg << 8;
8364 if (inst.operands[0].reg == inst.operands[1].reg
8365 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8366 as_tsktsk (_("Rd and Rm should be different in mul"));
8369 /* Long Multiply Parser
8370 UMULL RdLo, RdHi, Rm, Rs
8371 SMULL RdLo, RdHi, Rm, Rs
8372 UMLAL RdLo, RdHi, Rm, Rs
8373 SMLAL RdLo, RdHi, Rm, Rs. */
8378 inst.instruction |= inst.operands[0].reg << 12;
8379 inst.instruction |= inst.operands[1].reg << 16;
8380 inst.instruction |= inst.operands[2].reg;
8381 inst.instruction |= inst.operands[3].reg << 8;
8383 /* rdhi and rdlo must be different. */
8384 if (inst.operands[0].reg == inst.operands[1].reg)
8385 as_tsktsk (_("rdhi and rdlo must be different"));
8387 /* rdhi, rdlo and rm must all be different before armv6. */
8388 if ((inst.operands[0].reg == inst.operands[2].reg
8389 || inst.operands[1].reg == inst.operands[2].reg)
8390 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8391 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8397 if (inst.operands[0].present
8398 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8400 /* Architectural NOP hints are CPSR sets with no bits selected. */
8401 inst.instruction &= 0xf0000000;
8402 inst.instruction |= 0x0320f000;
8403 if (inst.operands[0].present)
8404 inst.instruction |= inst.operands[0].imm;
8408 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8409 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8410 Condition defaults to COND_ALWAYS.
8411 Error if Rd, Rn or Rm are R15. */
8416 inst.instruction |= inst.operands[0].reg << 12;
8417 inst.instruction |= inst.operands[1].reg << 16;
8418 inst.instruction |= inst.operands[2].reg;
8419 if (inst.operands[3].present)
8420 encode_arm_shift (3);
8423 /* ARM V6 PKHTB (Argument Parse). */
8428 if (!inst.operands[3].present)
8430 /* If the shift specifier is omitted, turn the instruction
8431 into pkhbt rd, rm, rn. */
8432 inst.instruction &= 0xfff00010;
8433 inst.instruction |= inst.operands[0].reg << 12;
8434 inst.instruction |= inst.operands[1].reg;
8435 inst.instruction |= inst.operands[2].reg << 16;
8439 inst.instruction |= inst.operands[0].reg << 12;
8440 inst.instruction |= inst.operands[1].reg << 16;
8441 inst.instruction |= inst.operands[2].reg;
8442 encode_arm_shift (3);
8446 /* ARMv5TE: Preload-Cache
8447 MP Extensions: Preload for write
8451 Syntactically, like LDR with B=1, W=0, L=1. */
8456 constraint (!inst.operands[0].isreg,
8457 _("'[' expected after PLD mnemonic"));
8458 constraint (inst.operands[0].postind,
8459 _("post-indexed expression used in preload instruction"));
8460 constraint (inst.operands[0].writeback,
8461 _("writeback used in preload instruction"));
8462 constraint (!inst.operands[0].preind,
8463 _("unindexed addressing used in preload instruction"));
8464 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8467 /* ARMv7: PLI <addr_mode> */
8471 constraint (!inst.operands[0].isreg,
8472 _("'[' expected after PLI mnemonic"));
8473 constraint (inst.operands[0].postind,
8474 _("post-indexed expression used in preload instruction"));
8475 constraint (inst.operands[0].writeback,
8476 _("writeback used in preload instruction"));
8477 constraint (!inst.operands[0].preind,
8478 _("unindexed addressing used in preload instruction"));
8479 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8480 inst.instruction &= ~PRE_INDEX;
8486 inst.operands[1] = inst.operands[0];
8487 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8488 inst.operands[0].isreg = 1;
8489 inst.operands[0].writeback = 1;
8490 inst.operands[0].reg = REG_SP;
8491 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8494 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8495 word at the specified address and the following word
8497 Unconditionally executed.
8498 Error if Rn is R15. */
8503 inst.instruction |= inst.operands[0].reg << 16;
8504 if (inst.operands[0].writeback)
8505 inst.instruction |= WRITE_BACK;
8508 /* ARM V6 ssat (argument parse). */
8513 inst.instruction |= inst.operands[0].reg << 12;
8514 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8515 inst.instruction |= inst.operands[2].reg;
8517 if (inst.operands[3].present)
8518 encode_arm_shift (3);
8521 /* ARM V6 usat (argument parse). */
8526 inst.instruction |= inst.operands[0].reg << 12;
8527 inst.instruction |= inst.operands[1].imm << 16;
8528 inst.instruction |= inst.operands[2].reg;
8530 if (inst.operands[3].present)
8531 encode_arm_shift (3);
8534 /* ARM V6 ssat16 (argument parse). */
8539 inst.instruction |= inst.operands[0].reg << 12;
8540 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8541 inst.instruction |= inst.operands[2].reg;
8547 inst.instruction |= inst.operands[0].reg << 12;
8548 inst.instruction |= inst.operands[1].imm << 16;
8549 inst.instruction |= inst.operands[2].reg;
8552 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8553 preserving the other bits.
8555 setend <endian_specifier>, where <endian_specifier> is either
8561 if (warn_on_deprecated
8562 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8563 as_warn (_("setend use is deprecated for ARMv8"));
8565 if (inst.operands[0].imm)
8566 inst.instruction |= 0x200;
8572 unsigned int Rm = (inst.operands[1].present
8573 ? inst.operands[1].reg
8574 : inst.operands[0].reg);
8576 inst.instruction |= inst.operands[0].reg << 12;
8577 inst.instruction |= Rm;
8578 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8580 inst.instruction |= inst.operands[2].reg << 8;
8581 inst.instruction |= SHIFT_BY_REG;
8582 /* PR 12854: Error on extraneous shifts. */
8583 constraint (inst.operands[2].shifted,
8584 _("extraneous shift as part of operand to shift insn"));
8587 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8593 inst.reloc.type = BFD_RELOC_ARM_SMC;
8594 inst.reloc.pc_rel = 0;
8600 inst.reloc.type = BFD_RELOC_ARM_HVC;
8601 inst.reloc.pc_rel = 0;
8607 inst.reloc.type = BFD_RELOC_ARM_SWI;
8608 inst.reloc.pc_rel = 0;
8611 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8612 SMLAxy{cond} Rd,Rm,Rs,Rn
8613 SMLAWy{cond} Rd,Rm,Rs,Rn
8614 Error if any register is R15. */
8619 inst.instruction |= inst.operands[0].reg << 16;
8620 inst.instruction |= inst.operands[1].reg;
8621 inst.instruction |= inst.operands[2].reg << 8;
8622 inst.instruction |= inst.operands[3].reg << 12;
8625 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8626 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8627 Error if any register is R15.
8628 Warning if Rdlo == Rdhi. */
8633 inst.instruction |= inst.operands[0].reg << 12;
8634 inst.instruction |= inst.operands[1].reg << 16;
8635 inst.instruction |= inst.operands[2].reg;
8636 inst.instruction |= inst.operands[3].reg << 8;
8638 if (inst.operands[0].reg == inst.operands[1].reg)
8639 as_tsktsk (_("rdhi and rdlo must be different"));
8642 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8643 SMULxy{cond} Rd,Rm,Rs
8644 Error if any register is R15. */
8649 inst.instruction |= inst.operands[0].reg << 16;
8650 inst.instruction |= inst.operands[1].reg;
8651 inst.instruction |= inst.operands[2].reg << 8;
8654 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8655 the same for both ARM and Thumb-2. */
8662 if (inst.operands[0].present)
8664 reg = inst.operands[0].reg;
8665 constraint (reg != REG_SP, _("SRS base register must be r13"));
8670 inst.instruction |= reg << 16;
8671 inst.instruction |= inst.operands[1].imm;
8672 if (inst.operands[0].writeback || inst.operands[1].writeback)
8673 inst.instruction |= WRITE_BACK;
8676 /* ARM V6 strex (argument parse). */
8681 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8682 || inst.operands[2].postind || inst.operands[2].writeback
8683 || inst.operands[2].immisreg || inst.operands[2].shifted
8684 || inst.operands[2].negative
8685 /* See comment in do_ldrex(). */
8686 || (inst.operands[2].reg == REG_PC),
8689 constraint (inst.operands[0].reg == inst.operands[1].reg
8690 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8692 constraint (inst.reloc.exp.X_op != O_constant
8693 || inst.reloc.exp.X_add_number != 0,
8694 _("offset must be zero in ARM encoding"));
8696 inst.instruction |= inst.operands[0].reg << 12;
8697 inst.instruction |= inst.operands[1].reg;
8698 inst.instruction |= inst.operands[2].reg << 16;
8699 inst.reloc.type = BFD_RELOC_UNUSED;
8705 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8706 || inst.operands[2].postind || inst.operands[2].writeback
8707 || inst.operands[2].immisreg || inst.operands[2].shifted
8708 || inst.operands[2].negative,
8711 constraint (inst.operands[0].reg == inst.operands[1].reg
8712 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8720 constraint (inst.operands[1].reg % 2 != 0,
8721 _("even register required"));
8722 constraint (inst.operands[2].present
8723 && inst.operands[2].reg != inst.operands[1].reg + 1,
8724 _("can only store two consecutive registers"));
8725 /* If op 2 were present and equal to PC, this function wouldn't
8726 have been called in the first place. */
8727 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8729 constraint (inst.operands[0].reg == inst.operands[1].reg
8730 || inst.operands[0].reg == inst.operands[1].reg + 1
8731 || inst.operands[0].reg == inst.operands[3].reg,
8734 inst.instruction |= inst.operands[0].reg << 12;
8735 inst.instruction |= inst.operands[1].reg;
8736 inst.instruction |= inst.operands[3].reg << 16;
8743 constraint (inst.operands[0].reg == inst.operands[1].reg
8744 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8752 constraint (inst.operands[0].reg == inst.operands[1].reg
8753 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8758 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8759 extends it to 32-bits, and adds the result to a value in another
8760 register. You can specify a rotation by 0, 8, 16, or 24 bits
8761 before extracting the 16-bit value.
8762 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8763 Condition defaults to COND_ALWAYS.
8764 Error if any register uses R15. */
8769 inst.instruction |= inst.operands[0].reg << 12;
8770 inst.instruction |= inst.operands[1].reg << 16;
8771 inst.instruction |= inst.operands[2].reg;
8772 inst.instruction |= inst.operands[3].imm << 10;
8777 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8778 Condition defaults to COND_ALWAYS.
8779 Error if any register uses R15. */
8784 inst.instruction |= inst.operands[0].reg << 12;
8785 inst.instruction |= inst.operands[1].reg;
8786 inst.instruction |= inst.operands[2].imm << 10;
8789 /* VFP instructions. In a logical order: SP variant first, monad
8790 before dyad, arithmetic then move then load/store. */
8793 do_vfp_sp_monadic (void)
8795 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8796 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8800 do_vfp_sp_dyadic (void)
8802 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8803 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8804 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8808 do_vfp_sp_compare_z (void)
8810 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8814 do_vfp_dp_sp_cvt (void)
8816 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8817 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8821 do_vfp_sp_dp_cvt (void)
8823 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8824 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8828 do_vfp_reg_from_sp (void)
8830 inst.instruction |= inst.operands[0].reg << 12;
8831 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8835 do_vfp_reg2_from_sp2 (void)
8837 constraint (inst.operands[2].imm != 2,
8838 _("only two consecutive VFP SP registers allowed here"));
8839 inst.instruction |= inst.operands[0].reg << 12;
8840 inst.instruction |= inst.operands[1].reg << 16;
8841 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8845 do_vfp_sp_from_reg (void)
8847 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8848 inst.instruction |= inst.operands[1].reg << 12;
8852 do_vfp_sp2_from_reg2 (void)
8854 constraint (inst.operands[0].imm != 2,
8855 _("only two consecutive VFP SP registers allowed here"));
8856 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8857 inst.instruction |= inst.operands[1].reg << 12;
8858 inst.instruction |= inst.operands[2].reg << 16;
8862 do_vfp_sp_ldst (void)
8864 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8865 encode_arm_cp_address (1, FALSE, TRUE, 0);
8869 do_vfp_dp_ldst (void)
8871 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8872 encode_arm_cp_address (1, FALSE, TRUE, 0);
8877 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8879 if (inst.operands[0].writeback)
8880 inst.instruction |= WRITE_BACK;
8882 constraint (ldstm_type != VFP_LDSTMIA,
8883 _("this addressing mode requires base-register writeback"));
8884 inst.instruction |= inst.operands[0].reg << 16;
8885 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8886 inst.instruction |= inst.operands[1].imm;
8890 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8894 if (inst.operands[0].writeback)
8895 inst.instruction |= WRITE_BACK;
8897 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8898 _("this addressing mode requires base-register writeback"));
8900 inst.instruction |= inst.operands[0].reg << 16;
8901 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8903 count = inst.operands[1].imm << 1;
8904 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8907 inst.instruction |= count;
8911 do_vfp_sp_ldstmia (void)
8913 vfp_sp_ldstm (VFP_LDSTMIA);
8917 do_vfp_sp_ldstmdb (void)
8919 vfp_sp_ldstm (VFP_LDSTMDB);
8923 do_vfp_dp_ldstmia (void)
8925 vfp_dp_ldstm (VFP_LDSTMIA);
8929 do_vfp_dp_ldstmdb (void)
8931 vfp_dp_ldstm (VFP_LDSTMDB);
8935 do_vfp_xp_ldstmia (void)
8937 vfp_dp_ldstm (VFP_LDSTMIAX);
8941 do_vfp_xp_ldstmdb (void)
8943 vfp_dp_ldstm (VFP_LDSTMDBX);
8947 do_vfp_dp_rd_rm (void)
8949 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8950 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8954 do_vfp_dp_rn_rd (void)
8956 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8957 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8961 do_vfp_dp_rd_rn (void)
8963 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8964 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8968 do_vfp_dp_rd_rn_rm (void)
8970 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8971 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8972 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8978 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8982 do_vfp_dp_rm_rd_rn (void)
8984 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8985 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8986 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8989 /* VFPv3 instructions. */
8991 do_vfp_sp_const (void)
8993 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8994 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8995 inst.instruction |= (inst.operands[1].imm & 0x0f);
8999 do_vfp_dp_const (void)
9001 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9002 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9003 inst.instruction |= (inst.operands[1].imm & 0x0f);
9007 vfp_conv (int srcsize)
9009 int immbits = srcsize - inst.operands[1].imm;
9011 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9013 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9014 i.e. immbits must be in range 0 - 16. */
9015 inst.error = _("immediate value out of range, expected range [0, 16]");
9018 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9020 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9021 i.e. immbits must be in range 0 - 31. */
9022 inst.error = _("immediate value out of range, expected range [1, 32]");
9026 inst.instruction |= (immbits & 1) << 5;
9027 inst.instruction |= (immbits >> 1);
9031 do_vfp_sp_conv_16 (void)
9033 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9038 do_vfp_dp_conv_16 (void)
9040 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9045 do_vfp_sp_conv_32 (void)
9047 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9052 do_vfp_dp_conv_32 (void)
9054 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9058 /* FPA instructions. Also in a logical order. */
9063 inst.instruction |= inst.operands[0].reg << 16;
9064 inst.instruction |= inst.operands[1].reg;
9068 do_fpa_ldmstm (void)
9070 inst.instruction |= inst.operands[0].reg << 12;
9071 switch (inst.operands[1].imm)
9073 case 1: inst.instruction |= CP_T_X; break;
9074 case 2: inst.instruction |= CP_T_Y; break;
9075 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9080 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9082 /* The instruction specified "ea" or "fd", so we can only accept
9083 [Rn]{!}. The instruction does not really support stacking or
9084 unstacking, so we have to emulate these by setting appropriate
9085 bits and offsets. */
9086 constraint (inst.reloc.exp.X_op != O_constant
9087 || inst.reloc.exp.X_add_number != 0,
9088 _("this instruction does not support indexing"));
9090 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9091 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9093 if (!(inst.instruction & INDEX_UP))
9094 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9096 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9098 inst.operands[2].preind = 0;
9099 inst.operands[2].postind = 1;
9103 encode_arm_cp_address (2, TRUE, TRUE, 0);
9106 /* iWMMXt instructions: strictly in alphabetical order. */
9109 do_iwmmxt_tandorc (void)
9111 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9115 do_iwmmxt_textrc (void)
9117 inst.instruction |= inst.operands[0].reg << 12;
9118 inst.instruction |= inst.operands[1].imm;
9122 do_iwmmxt_textrm (void)
9124 inst.instruction |= inst.operands[0].reg << 12;
9125 inst.instruction |= inst.operands[1].reg << 16;
9126 inst.instruction |= inst.operands[2].imm;
9130 do_iwmmxt_tinsr (void)
9132 inst.instruction |= inst.operands[0].reg << 16;
9133 inst.instruction |= inst.operands[1].reg << 12;
9134 inst.instruction |= inst.operands[2].imm;
9138 do_iwmmxt_tmia (void)
9140 inst.instruction |= inst.operands[0].reg << 5;
9141 inst.instruction |= inst.operands[1].reg;
9142 inst.instruction |= inst.operands[2].reg << 12;
9146 do_iwmmxt_waligni (void)
9148 inst.instruction |= inst.operands[0].reg << 12;
9149 inst.instruction |= inst.operands[1].reg << 16;
9150 inst.instruction |= inst.operands[2].reg;
9151 inst.instruction |= inst.operands[3].imm << 20;
9155 do_iwmmxt_wmerge (void)
9157 inst.instruction |= inst.operands[0].reg << 12;
9158 inst.instruction |= inst.operands[1].reg << 16;
9159 inst.instruction |= inst.operands[2].reg;
9160 inst.instruction |= inst.operands[3].imm << 21;
9164 do_iwmmxt_wmov (void)
9166 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9167 inst.instruction |= inst.operands[0].reg << 12;
9168 inst.instruction |= inst.operands[1].reg << 16;
9169 inst.instruction |= inst.operands[1].reg;
9173 do_iwmmxt_wldstbh (void)
9176 inst.instruction |= inst.operands[0].reg << 12;
9178 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9180 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9181 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9185 do_iwmmxt_wldstw (void)
9187 /* RIWR_RIWC clears .isreg for a control register. */
9188 if (!inst.operands[0].isreg)
9190 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9191 inst.instruction |= 0xf0000000;
9194 inst.instruction |= inst.operands[0].reg << 12;
9195 encode_arm_cp_address (1, TRUE, TRUE, 0);
9199 do_iwmmxt_wldstd (void)
9201 inst.instruction |= inst.operands[0].reg << 12;
9202 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9203 && inst.operands[1].immisreg)
9205 inst.instruction &= ~0x1a000ff;
9206 inst.instruction |= (0xf << 28);
9207 if (inst.operands[1].preind)
9208 inst.instruction |= PRE_INDEX;
9209 if (!inst.operands[1].negative)
9210 inst.instruction |= INDEX_UP;
9211 if (inst.operands[1].writeback)
9212 inst.instruction |= WRITE_BACK;
9213 inst.instruction |= inst.operands[1].reg << 16;
9214 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9215 inst.instruction |= inst.operands[1].imm;
9218 encode_arm_cp_address (1, TRUE, FALSE, 0);
9222 do_iwmmxt_wshufh (void)
9224 inst.instruction |= inst.operands[0].reg << 12;
9225 inst.instruction |= inst.operands[1].reg << 16;
9226 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9227 inst.instruction |= (inst.operands[2].imm & 0x0f);
9231 do_iwmmxt_wzero (void)
9233 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9234 inst.instruction |= inst.operands[0].reg;
9235 inst.instruction |= inst.operands[0].reg << 12;
9236 inst.instruction |= inst.operands[0].reg << 16;
9240 do_iwmmxt_wrwrwr_or_imm5 (void)
9242 if (inst.operands[2].isreg)
9245 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9246 _("immediate operand requires iWMMXt2"));
9248 if (inst.operands[2].imm == 0)
9250 switch ((inst.instruction >> 20) & 0xf)
9256 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9257 inst.operands[2].imm = 16;
9258 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9264 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9265 inst.operands[2].imm = 32;
9266 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9273 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9275 wrn = (inst.instruction >> 16) & 0xf;
9276 inst.instruction &= 0xff0fff0f;
9277 inst.instruction |= wrn;
9278 /* Bail out here; the instruction is now assembled. */
9283 /* Map 32 -> 0, etc. */
9284 inst.operands[2].imm &= 0x1f;
9285 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9289 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9290 operations first, then control, shift, and load/store. */
9292 /* Insns like "foo X,Y,Z". */
9295 do_mav_triple (void)
9297 inst.instruction |= inst.operands[0].reg << 16;
9298 inst.instruction |= inst.operands[1].reg;
9299 inst.instruction |= inst.operands[2].reg << 12;
9302 /* Insns like "foo W,X,Y,Z".
9303 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9308 inst.instruction |= inst.operands[0].reg << 5;
9309 inst.instruction |= inst.operands[1].reg << 12;
9310 inst.instruction |= inst.operands[2].reg << 16;
9311 inst.instruction |= inst.operands[3].reg;
9314 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9318 inst.instruction |= inst.operands[1].reg << 12;
9321 /* Maverick shift immediate instructions.
9322 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9323 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9328 int imm = inst.operands[2].imm;
9330 inst.instruction |= inst.operands[0].reg << 12;
9331 inst.instruction |= inst.operands[1].reg << 16;
9333 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9334 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9335 Bit 4 should be 0. */
9336 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9338 inst.instruction |= imm;
9341 /* XScale instructions. Also sorted arithmetic before move. */
9343 /* Xscale multiply-accumulate (argument parse)
9346 MIAxycc acc0,Rm,Rs. */
9351 inst.instruction |= inst.operands[1].reg;
9352 inst.instruction |= inst.operands[2].reg << 12;
9355 /* Xscale move-accumulator-register (argument parse)
9357 MARcc acc0,RdLo,RdHi. */
9362 inst.instruction |= inst.operands[1].reg << 12;
9363 inst.instruction |= inst.operands[2].reg << 16;
9366 /* Xscale move-register-accumulator (argument parse)
9368 MRAcc RdLo,RdHi,acc0. */
9373 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9374 inst.instruction |= inst.operands[0].reg << 12;
9375 inst.instruction |= inst.operands[1].reg << 16;
9378 /* Encoding functions relevant only to Thumb. */
9380 /* inst.operands[i] is a shifted-register operand; encode
9381 it into inst.instruction in the format used by Thumb32. */
9384 encode_thumb32_shifted_operand (int i)
9386 unsigned int value = inst.reloc.exp.X_add_number;
9387 unsigned int shift = inst.operands[i].shift_kind;
9389 constraint (inst.operands[i].immisreg,
9390 _("shift by register not allowed in thumb mode"));
9391 inst.instruction |= inst.operands[i].reg;
9392 if (shift == SHIFT_RRX)
9393 inst.instruction |= SHIFT_ROR << 4;
9396 constraint (inst.reloc.exp.X_op != O_constant,
9397 _("expression too complex"));
9399 constraint (value > 32
9400 || (value == 32 && (shift == SHIFT_LSL
9401 || shift == SHIFT_ROR)),
9402 _("shift expression is too large"));
9406 else if (value == 32)
9409 inst.instruction |= shift << 4;
9410 inst.instruction |= (value & 0x1c) << 10;
9411 inst.instruction |= (value & 0x03) << 6;
9416 /* inst.operands[i] was set up by parse_address. Encode it into a
9417 Thumb32 format load or store instruction. Reject forms that cannot
9418 be used with such instructions. If is_t is true, reject forms that
9419 cannot be used with a T instruction; if is_d is true, reject forms
9420 that cannot be used with a D instruction. If it is a store insn,
9424 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9426 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9428 constraint (!inst.operands[i].isreg,
9429 _("Instruction does not support =N addresses"));
9431 inst.instruction |= inst.operands[i].reg << 16;
9432 if (inst.operands[i].immisreg)
9434 constraint (is_pc, BAD_PC_ADDRESSING);
9435 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9436 constraint (inst.operands[i].negative,
9437 _("Thumb does not support negative register indexing"));
9438 constraint (inst.operands[i].postind,
9439 _("Thumb does not support register post-indexing"));
9440 constraint (inst.operands[i].writeback,
9441 _("Thumb does not support register indexing with writeback"));
9442 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9443 _("Thumb supports only LSL in shifted register indexing"));
9445 inst.instruction |= inst.operands[i].imm;
9446 if (inst.operands[i].shifted)
9448 constraint (inst.reloc.exp.X_op != O_constant,
9449 _("expression too complex"));
9450 constraint (inst.reloc.exp.X_add_number < 0
9451 || inst.reloc.exp.X_add_number > 3,
9452 _("shift out of range"));
9453 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9455 inst.reloc.type = BFD_RELOC_UNUSED;
9457 else if (inst.operands[i].preind)
9459 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9460 constraint (is_t && inst.operands[i].writeback,
9461 _("cannot use writeback with this instruction"));
9462 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9463 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9467 inst.instruction |= 0x01000000;
9468 if (inst.operands[i].writeback)
9469 inst.instruction |= 0x00200000;
9473 inst.instruction |= 0x00000c00;
9474 if (inst.operands[i].writeback)
9475 inst.instruction |= 0x00000100;
9477 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9479 else if (inst.operands[i].postind)
9481 gas_assert (inst.operands[i].writeback);
9482 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9483 constraint (is_t, _("cannot use post-indexing with this instruction"));
9486 inst.instruction |= 0x00200000;
9488 inst.instruction |= 0x00000900;
9489 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9491 else /* unindexed - only for coprocessor */
9492 inst.error = _("instruction does not accept unindexed addressing");
9495 /* Table of Thumb instructions which exist in both 16- and 32-bit
9496 encodings (the latter only in post-V6T2 cores). The index is the
9497 value used in the insns table below. When there is more than one
9498 possible 16-bit encoding for the instruction, this table always
9500 Also contains several pseudo-instructions used during relaxation. */
9501 #define T16_32_TAB \
9502 X(_adc, 4140, eb400000), \
9503 X(_adcs, 4140, eb500000), \
9504 X(_add, 1c00, eb000000), \
9505 X(_adds, 1c00, eb100000), \
9506 X(_addi, 0000, f1000000), \
9507 X(_addis, 0000, f1100000), \
9508 X(_add_pc,000f, f20f0000), \
9509 X(_add_sp,000d, f10d0000), \
9510 X(_adr, 000f, f20f0000), \
9511 X(_and, 4000, ea000000), \
9512 X(_ands, 4000, ea100000), \
9513 X(_asr, 1000, fa40f000), \
9514 X(_asrs, 1000, fa50f000), \
9515 X(_b, e000, f000b000), \
9516 X(_bcond, d000, f0008000), \
9517 X(_bic, 4380, ea200000), \
9518 X(_bics, 4380, ea300000), \
9519 X(_cmn, 42c0, eb100f00), \
9520 X(_cmp, 2800, ebb00f00), \
9521 X(_cpsie, b660, f3af8400), \
9522 X(_cpsid, b670, f3af8600), \
9523 X(_cpy, 4600, ea4f0000), \
9524 X(_dec_sp,80dd, f1ad0d00), \
9525 X(_eor, 4040, ea800000), \
9526 X(_eors, 4040, ea900000), \
9527 X(_inc_sp,00dd, f10d0d00), \
9528 X(_ldmia, c800, e8900000), \
9529 X(_ldr, 6800, f8500000), \
9530 X(_ldrb, 7800, f8100000), \
9531 X(_ldrh, 8800, f8300000), \
9532 X(_ldrsb, 5600, f9100000), \
9533 X(_ldrsh, 5e00, f9300000), \
9534 X(_ldr_pc,4800, f85f0000), \
9535 X(_ldr_pc2,4800, f85f0000), \
9536 X(_ldr_sp,9800, f85d0000), \
9537 X(_lsl, 0000, fa00f000), \
9538 X(_lsls, 0000, fa10f000), \
9539 X(_lsr, 0800, fa20f000), \
9540 X(_lsrs, 0800, fa30f000), \
9541 X(_mov, 2000, ea4f0000), \
9542 X(_movs, 2000, ea5f0000), \
9543 X(_mul, 4340, fb00f000), \
9544 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9545 X(_mvn, 43c0, ea6f0000), \
9546 X(_mvns, 43c0, ea7f0000), \
9547 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9548 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9549 X(_orr, 4300, ea400000), \
9550 X(_orrs, 4300, ea500000), \
9551 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9552 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9553 X(_rev, ba00, fa90f080), \
9554 X(_rev16, ba40, fa90f090), \
9555 X(_revsh, bac0, fa90f0b0), \
9556 X(_ror, 41c0, fa60f000), \
9557 X(_rors, 41c0, fa70f000), \
9558 X(_sbc, 4180, eb600000), \
9559 X(_sbcs, 4180, eb700000), \
9560 X(_stmia, c000, e8800000), \
9561 X(_str, 6000, f8400000), \
9562 X(_strb, 7000, f8000000), \
9563 X(_strh, 8000, f8200000), \
9564 X(_str_sp,9000, f84d0000), \
9565 X(_sub, 1e00, eba00000), \
9566 X(_subs, 1e00, ebb00000), \
9567 X(_subi, 8000, f1a00000), \
9568 X(_subis, 8000, f1b00000), \
9569 X(_sxtb, b240, fa4ff080), \
9570 X(_sxth, b200, fa0ff080), \
9571 X(_tst, 4200, ea100f00), \
9572 X(_uxtb, b2c0, fa5ff080), \
9573 X(_uxth, b280, fa1ff080), \
9574 X(_nop, bf00, f3af8000), \
9575 X(_yield, bf10, f3af8001), \
9576 X(_wfe, bf20, f3af8002), \
9577 X(_wfi, bf30, f3af8003), \
9578 X(_sev, bf40, f3af8004), \
9579 X(_sevl, bf50, f3af8005)
9581 /* To catch errors in encoding functions, the codes are all offset by
9582 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9583 as 16-bit instructions. */
9584 #define X(a,b,c) T_MNEM##a
9585 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9588 #define X(a,b,c) 0x##b
9589 static const unsigned short thumb_op16[] = { T16_32_TAB };
9590 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9593 #define X(a,b,c) 0x##c
9594 static const unsigned int thumb_op32[] = { T16_32_TAB };
9595 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9596 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9600 /* Thumb instruction encoders, in alphabetical order. */
9605 do_t_add_sub_w (void)
9609 Rd = inst.operands[0].reg;
9610 Rn = inst.operands[1].reg;
9612 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9613 is the SP-{plus,minus}-immediate form of the instruction. */
9615 constraint (Rd == REG_PC, BAD_PC);
9617 reject_bad_reg (Rd);
9619 inst.instruction |= (Rn << 16) | (Rd << 8);
9620 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9623 /* Parse an add or subtract instruction. We get here with inst.instruction
9624 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9631 Rd = inst.operands[0].reg;
9632 Rs = (inst.operands[1].present
9633 ? inst.operands[1].reg /* Rd, Rs, foo */
9634 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9637 set_it_insn_type_last ();
9645 flags = (inst.instruction == T_MNEM_adds
9646 || inst.instruction == T_MNEM_subs);
9648 narrow = !in_it_block ();
9650 narrow = in_it_block ();
9651 if (!inst.operands[2].isreg)
9655 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9657 add = (inst.instruction == T_MNEM_add
9658 || inst.instruction == T_MNEM_adds);
9660 if (inst.size_req != 4)
9662 /* Attempt to use a narrow opcode, with relaxation if
9664 if (Rd == REG_SP && Rs == REG_SP && !flags)
9665 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9666 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9667 opcode = T_MNEM_add_sp;
9668 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9669 opcode = T_MNEM_add_pc;
9670 else if (Rd <= 7 && Rs <= 7 && narrow)
9673 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9675 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9679 inst.instruction = THUMB_OP16(opcode);
9680 inst.instruction |= (Rd << 4) | Rs;
9681 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9682 if (inst.size_req != 2)
9683 inst.relax = opcode;
9686 constraint (inst.size_req == 2, BAD_HIREG);
9688 if (inst.size_req == 4
9689 || (inst.size_req != 2 && !opcode))
9693 constraint (add, BAD_PC);
9694 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9695 _("only SUBS PC, LR, #const allowed"));
9696 constraint (inst.reloc.exp.X_op != O_constant,
9697 _("expression too complex"));
9698 constraint (inst.reloc.exp.X_add_number < 0
9699 || inst.reloc.exp.X_add_number > 0xff,
9700 _("immediate value out of range"));
9701 inst.instruction = T2_SUBS_PC_LR
9702 | inst.reloc.exp.X_add_number;
9703 inst.reloc.type = BFD_RELOC_UNUSED;
9706 else if (Rs == REG_PC)
9708 /* Always use addw/subw. */
9709 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9710 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9714 inst.instruction = THUMB_OP32 (inst.instruction);
9715 inst.instruction = (inst.instruction & 0xe1ffffff)
9718 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9720 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9722 inst.instruction |= Rd << 8;
9723 inst.instruction |= Rs << 16;
9728 unsigned int value = inst.reloc.exp.X_add_number;
9729 unsigned int shift = inst.operands[2].shift_kind;
9731 Rn = inst.operands[2].reg;
9732 /* See if we can do this with a 16-bit instruction. */
9733 if (!inst.operands[2].shifted && inst.size_req != 4)
9735 if (Rd > 7 || Rs > 7 || Rn > 7)
9740 inst.instruction = ((inst.instruction == T_MNEM_adds
9741 || inst.instruction == T_MNEM_add)
9744 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9748 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9750 /* Thumb-1 cores (except v6-M) require at least one high
9751 register in a narrow non flag setting add. */
9752 if (Rd > 7 || Rn > 7
9753 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9754 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9761 inst.instruction = T_OPCODE_ADD_HI;
9762 inst.instruction |= (Rd & 8) << 4;
9763 inst.instruction |= (Rd & 7);
9764 inst.instruction |= Rn << 3;
9770 constraint (Rd == REG_PC, BAD_PC);
9771 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9772 constraint (Rs == REG_PC, BAD_PC);
9773 reject_bad_reg (Rn);
9775 /* If we get here, it can't be done in 16 bits. */
9776 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9777 _("shift must be constant"));
9778 inst.instruction = THUMB_OP32 (inst.instruction);
9779 inst.instruction |= Rd << 8;
9780 inst.instruction |= Rs << 16;
9781 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9782 _("shift value over 3 not allowed in thumb mode"));
9783 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9784 _("only LSL shift allowed in thumb mode"));
9785 encode_thumb32_shifted_operand (2);
9790 constraint (inst.instruction == T_MNEM_adds
9791 || inst.instruction == T_MNEM_subs,
9794 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9796 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9797 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9800 inst.instruction = (inst.instruction == T_MNEM_add
9802 inst.instruction |= (Rd << 4) | Rs;
9803 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9807 Rn = inst.operands[2].reg;
9808 constraint (inst.operands[2].shifted, _("unshifted register required"));
9810 /* We now have Rd, Rs, and Rn set to registers. */
9811 if (Rd > 7 || Rs > 7 || Rn > 7)
9813 /* Can't do this for SUB. */
9814 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9815 inst.instruction = T_OPCODE_ADD_HI;
9816 inst.instruction |= (Rd & 8) << 4;
9817 inst.instruction |= (Rd & 7);
9819 inst.instruction |= Rn << 3;
9821 inst.instruction |= Rs << 3;
9823 constraint (1, _("dest must overlap one source register"));
9827 inst.instruction = (inst.instruction == T_MNEM_add
9828 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9829 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9839 Rd = inst.operands[0].reg;
9840 reject_bad_reg (Rd);
9842 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9844 /* Defer to section relaxation. */
9845 inst.relax = inst.instruction;
9846 inst.instruction = THUMB_OP16 (inst.instruction);
9847 inst.instruction |= Rd << 4;
9849 else if (unified_syntax && inst.size_req != 2)
9851 /* Generate a 32-bit opcode. */
9852 inst.instruction = THUMB_OP32 (inst.instruction);
9853 inst.instruction |= Rd << 8;
9854 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9855 inst.reloc.pc_rel = 1;
9859 /* Generate a 16-bit opcode. */
9860 inst.instruction = THUMB_OP16 (inst.instruction);
9861 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9862 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9863 inst.reloc.pc_rel = 1;
9865 inst.instruction |= Rd << 4;
9869 /* Arithmetic instructions for which there is just one 16-bit
9870 instruction encoding, and it allows only two low registers.
9871 For maximal compatibility with ARM syntax, we allow three register
9872 operands even when Thumb-32 instructions are not available, as long
9873 as the first two are identical. For instance, both "sbc r0,r1" and
9874 "sbc r0,r0,r1" are allowed. */
9880 Rd = inst.operands[0].reg;
9881 Rs = (inst.operands[1].present
9882 ? inst.operands[1].reg /* Rd, Rs, foo */
9883 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9884 Rn = inst.operands[2].reg;
9886 reject_bad_reg (Rd);
9887 reject_bad_reg (Rs);
9888 if (inst.operands[2].isreg)
9889 reject_bad_reg (Rn);
9893 if (!inst.operands[2].isreg)
9895 /* For an immediate, we always generate a 32-bit opcode;
9896 section relaxation will shrink it later if possible. */
9897 inst.instruction = THUMB_OP32 (inst.instruction);
9898 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9899 inst.instruction |= Rd << 8;
9900 inst.instruction |= Rs << 16;
9901 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9907 /* See if we can do this with a 16-bit instruction. */
9908 if (THUMB_SETS_FLAGS (inst.instruction))
9909 narrow = !in_it_block ();
9911 narrow = in_it_block ();
9913 if (Rd > 7 || Rn > 7 || Rs > 7)
9915 if (inst.operands[2].shifted)
9917 if (inst.size_req == 4)
9923 inst.instruction = THUMB_OP16 (inst.instruction);
9924 inst.instruction |= Rd;
9925 inst.instruction |= Rn << 3;
9929 /* If we get here, it can't be done in 16 bits. */
9930 constraint (inst.operands[2].shifted
9931 && inst.operands[2].immisreg,
9932 _("shift must be constant"));
9933 inst.instruction = THUMB_OP32 (inst.instruction);
9934 inst.instruction |= Rd << 8;
9935 inst.instruction |= Rs << 16;
9936 encode_thumb32_shifted_operand (2);
9941 /* On its face this is a lie - the instruction does set the
9942 flags. However, the only supported mnemonic in this mode
9944 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9946 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9947 _("unshifted register required"));
9948 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9949 constraint (Rd != Rs,
9950 _("dest and source1 must be the same register"));
9952 inst.instruction = THUMB_OP16 (inst.instruction);
9953 inst.instruction |= Rd;
9954 inst.instruction |= Rn << 3;
9958 /* Similarly, but for instructions where the arithmetic operation is
9959 commutative, so we can allow either of them to be different from
9960 the destination operand in a 16-bit instruction. For instance, all
9961 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9968 Rd = inst.operands[0].reg;
9969 Rs = (inst.operands[1].present
9970 ? inst.operands[1].reg /* Rd, Rs, foo */
9971 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9972 Rn = inst.operands[2].reg;
9974 reject_bad_reg (Rd);
9975 reject_bad_reg (Rs);
9976 if (inst.operands[2].isreg)
9977 reject_bad_reg (Rn);
9981 if (!inst.operands[2].isreg)
9983 /* For an immediate, we always generate a 32-bit opcode;
9984 section relaxation will shrink it later if possible. */
9985 inst.instruction = THUMB_OP32 (inst.instruction);
9986 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9987 inst.instruction |= Rd << 8;
9988 inst.instruction |= Rs << 16;
9989 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9995 /* See if we can do this with a 16-bit instruction. */
9996 if (THUMB_SETS_FLAGS (inst.instruction))
9997 narrow = !in_it_block ();
9999 narrow = in_it_block ();
10001 if (Rd > 7 || Rn > 7 || Rs > 7)
10003 if (inst.operands[2].shifted)
10005 if (inst.size_req == 4)
10012 inst.instruction = THUMB_OP16 (inst.instruction);
10013 inst.instruction |= Rd;
10014 inst.instruction |= Rn << 3;
10019 inst.instruction = THUMB_OP16 (inst.instruction);
10020 inst.instruction |= Rd;
10021 inst.instruction |= Rs << 3;
10026 /* If we get here, it can't be done in 16 bits. */
10027 constraint (inst.operands[2].shifted
10028 && inst.operands[2].immisreg,
10029 _("shift must be constant"));
10030 inst.instruction = THUMB_OP32 (inst.instruction);
10031 inst.instruction |= Rd << 8;
10032 inst.instruction |= Rs << 16;
10033 encode_thumb32_shifted_operand (2);
10038 /* On its face this is a lie - the instruction does set the
10039 flags. However, the only supported mnemonic in this mode
10040 says it doesn't. */
10041 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10043 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10044 _("unshifted register required"));
10045 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10047 inst.instruction = THUMB_OP16 (inst.instruction);
10048 inst.instruction |= Rd;
10051 inst.instruction |= Rn << 3;
10053 inst.instruction |= Rs << 3;
10055 constraint (1, _("dest must overlap one source register"));
10060 do_t_barrier (void)
10062 if (inst.operands[0].present)
10064 constraint ((inst.instruction & 0xf0) != 0x40
10065 && inst.operands[0].imm > 0xf
10066 && inst.operands[0].imm < 0x0,
10067 _("bad barrier type"));
10068 inst.instruction |= inst.operands[0].imm;
10071 inst.instruction |= 0xf;
10078 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10079 constraint (msb > 32, _("bit-field extends past end of register"));
10080 /* The instruction encoding stores the LSB and MSB,
10081 not the LSB and width. */
10082 Rd = inst.operands[0].reg;
10083 reject_bad_reg (Rd);
10084 inst.instruction |= Rd << 8;
10085 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10086 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10087 inst.instruction |= msb - 1;
10096 Rd = inst.operands[0].reg;
10097 reject_bad_reg (Rd);
10099 /* #0 in second position is alternative syntax for bfc, which is
10100 the same instruction but with REG_PC in the Rm field. */
10101 if (!inst.operands[1].isreg)
10105 Rn = inst.operands[1].reg;
10106 reject_bad_reg (Rn);
10109 msb = inst.operands[2].imm + inst.operands[3].imm;
10110 constraint (msb > 32, _("bit-field extends past end of register"));
10111 /* The instruction encoding stores the LSB and MSB,
10112 not the LSB and width. */
10113 inst.instruction |= Rd << 8;
10114 inst.instruction |= Rn << 16;
10115 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10116 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10117 inst.instruction |= msb - 1;
10125 Rd = inst.operands[0].reg;
10126 Rn = inst.operands[1].reg;
10128 reject_bad_reg (Rd);
10129 reject_bad_reg (Rn);
10131 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10132 _("bit-field extends past end of register"));
10133 inst.instruction |= Rd << 8;
10134 inst.instruction |= Rn << 16;
10135 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10136 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10137 inst.instruction |= inst.operands[3].imm - 1;
10140 /* ARM V5 Thumb BLX (argument parse)
10141 BLX <target_addr> which is BLX(1)
10142 BLX <Rm> which is BLX(2)
10143 Unfortunately, there are two different opcodes for this mnemonic.
10144 So, the insns[].value is not used, and the code here zaps values
10145 into inst.instruction.
10147 ??? How to take advantage of the additional two bits of displacement
10148 available in Thumb32 mode? Need new relocation? */
10153 set_it_insn_type_last ();
10155 if (inst.operands[0].isreg)
10157 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10158 /* We have a register, so this is BLX(2). */
10159 inst.instruction |= inst.operands[0].reg << 3;
10163 /* No register. This must be BLX(1). */
10164 inst.instruction = 0xf000e800;
10165 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10177 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10179 if (in_it_block ())
10181 /* Conditional branches inside IT blocks are encoded as unconditional
10183 cond = COND_ALWAYS;
10188 if (cond != COND_ALWAYS)
10189 opcode = T_MNEM_bcond;
10191 opcode = inst.instruction;
10194 && (inst.size_req == 4
10195 || (inst.size_req != 2
10196 && (inst.operands[0].hasreloc
10197 || inst.reloc.exp.X_op == O_constant))))
10199 inst.instruction = THUMB_OP32(opcode);
10200 if (cond == COND_ALWAYS)
10201 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10204 gas_assert (cond != 0xF);
10205 inst.instruction |= cond << 22;
10206 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10211 inst.instruction = THUMB_OP16(opcode);
10212 if (cond == COND_ALWAYS)
10213 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10216 inst.instruction |= cond << 8;
10217 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10219 /* Allow section relaxation. */
10220 if (unified_syntax && inst.size_req != 2)
10221 inst.relax = opcode;
10223 inst.reloc.type = reloc;
10224 inst.reloc.pc_rel = 1;
10227 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10228 between the two is the maximum immediate allowed - which is passed in
10231 do_t_bkpt_hlt1 (int range)
10233 constraint (inst.cond != COND_ALWAYS,
10234 _("instruction is always unconditional"));
10235 if (inst.operands[0].present)
10237 constraint (inst.operands[0].imm > range,
10238 _("immediate value out of range"));
10239 inst.instruction |= inst.operands[0].imm;
10242 set_it_insn_type (NEUTRAL_IT_INSN);
10248 do_t_bkpt_hlt1 (63);
10254 do_t_bkpt_hlt1 (255);
10258 do_t_branch23 (void)
10260 set_it_insn_type_last ();
10261 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10263 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10264 this file. We used to simply ignore the PLT reloc type here --
10265 the branch encoding is now needed to deal with TLSCALL relocs.
10266 So if we see a PLT reloc now, put it back to how it used to be to
10267 keep the preexisting behaviour. */
10268 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10269 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10271 #if defined(OBJ_COFF)
10272 /* If the destination of the branch is a defined symbol which does not have
10273 the THUMB_FUNC attribute, then we must be calling a function which has
10274 the (interfacearm) attribute. We look for the Thumb entry point to that
10275 function and change the branch to refer to that function instead. */
10276 if ( inst.reloc.exp.X_op == O_symbol
10277 && inst.reloc.exp.X_add_symbol != NULL
10278 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10279 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10280 inst.reloc.exp.X_add_symbol =
10281 find_real_start (inst.reloc.exp.X_add_symbol);
10288 set_it_insn_type_last ();
10289 inst.instruction |= inst.operands[0].reg << 3;
10290 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10291 should cause the alignment to be checked once it is known. This is
10292 because BX PC only works if the instruction is word aligned. */
10300 set_it_insn_type_last ();
10301 Rm = inst.operands[0].reg;
10302 reject_bad_reg (Rm);
10303 inst.instruction |= Rm << 16;
10312 Rd = inst.operands[0].reg;
10313 Rm = inst.operands[1].reg;
10315 reject_bad_reg (Rd);
10316 reject_bad_reg (Rm);
10318 inst.instruction |= Rd << 8;
10319 inst.instruction |= Rm << 16;
10320 inst.instruction |= Rm;
10326 set_it_insn_type (OUTSIDE_IT_INSN);
10327 inst.instruction |= inst.operands[0].imm;
10333 set_it_insn_type (OUTSIDE_IT_INSN);
10335 && (inst.operands[1].present || inst.size_req == 4)
10336 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10338 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10339 inst.instruction = 0xf3af8000;
10340 inst.instruction |= imod << 9;
10341 inst.instruction |= inst.operands[0].imm << 5;
10342 if (inst.operands[1].present)
10343 inst.instruction |= 0x100 | inst.operands[1].imm;
10347 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10348 && (inst.operands[0].imm & 4),
10349 _("selected processor does not support 'A' form "
10350 "of this instruction"));
10351 constraint (inst.operands[1].present || inst.size_req == 4,
10352 _("Thumb does not support the 2-argument "
10353 "form of this instruction"));
10354 inst.instruction |= inst.operands[0].imm;
10358 /* THUMB CPY instruction (argument parse). */
10363 if (inst.size_req == 4)
10365 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10366 inst.instruction |= inst.operands[0].reg << 8;
10367 inst.instruction |= inst.operands[1].reg;
10371 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10372 inst.instruction |= (inst.operands[0].reg & 0x7);
10373 inst.instruction |= inst.operands[1].reg << 3;
10380 set_it_insn_type (OUTSIDE_IT_INSN);
10381 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10382 inst.instruction |= inst.operands[0].reg;
10383 inst.reloc.pc_rel = 1;
10384 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10390 inst.instruction |= inst.operands[0].imm;
10396 unsigned Rd, Rn, Rm;
10398 Rd = inst.operands[0].reg;
10399 Rn = (inst.operands[1].present
10400 ? inst.operands[1].reg : Rd);
10401 Rm = inst.operands[2].reg;
10403 reject_bad_reg (Rd);
10404 reject_bad_reg (Rn);
10405 reject_bad_reg (Rm);
10407 inst.instruction |= Rd << 8;
10408 inst.instruction |= Rn << 16;
10409 inst.instruction |= Rm;
10415 if (unified_syntax && inst.size_req == 4)
10416 inst.instruction = THUMB_OP32 (inst.instruction);
10418 inst.instruction = THUMB_OP16 (inst.instruction);
10424 unsigned int cond = inst.operands[0].imm;
10426 set_it_insn_type (IT_INSN);
10427 now_it.mask = (inst.instruction & 0xf) | 0x10;
10429 now_it.warn_deprecated = FALSE;
10431 /* If the condition is a negative condition, invert the mask. */
10432 if ((cond & 0x1) == 0x0)
10434 unsigned int mask = inst.instruction & 0x000f;
10436 if ((mask & 0x7) == 0)
10438 /* No conversion needed. */
10439 now_it.block_length = 1;
10441 else if ((mask & 0x3) == 0)
10444 now_it.block_length = 2;
10446 else if ((mask & 0x1) == 0)
10449 now_it.block_length = 3;
10454 now_it.block_length = 4;
10457 inst.instruction &= 0xfff0;
10458 inst.instruction |= mask;
10461 inst.instruction |= cond << 4;
10464 /* Helper function used for both push/pop and ldm/stm. */
10466 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10470 load = (inst.instruction & (1 << 20)) != 0;
10472 if (mask & (1 << 13))
10473 inst.error = _("SP not allowed in register list");
10475 if ((mask & (1 << base)) != 0
10477 inst.error = _("having the base register in the register list when "
10478 "using write back is UNPREDICTABLE");
10482 if (mask & (1 << 15))
10484 if (mask & (1 << 14))
10485 inst.error = _("LR and PC should not both be in register list");
10487 set_it_insn_type_last ();
10492 if (mask & (1 << 15))
10493 inst.error = _("PC not allowed in register list");
10496 if ((mask & (mask - 1)) == 0)
10498 /* Single register transfers implemented as str/ldr. */
10501 if (inst.instruction & (1 << 23))
10502 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10504 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10508 if (inst.instruction & (1 << 23))
10509 inst.instruction = 0x00800000; /* ia -> [base] */
10511 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10514 inst.instruction |= 0xf8400000;
10516 inst.instruction |= 0x00100000;
10518 mask = ffs (mask) - 1;
10521 else if (writeback)
10522 inst.instruction |= WRITE_BACK;
10524 inst.instruction |= mask;
10525 inst.instruction |= base << 16;
10531 /* This really doesn't seem worth it. */
10532 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10533 _("expression too complex"));
10534 constraint (inst.operands[1].writeback,
10535 _("Thumb load/store multiple does not support {reglist}^"));
10537 if (unified_syntax)
10539 bfd_boolean narrow;
10543 /* See if we can use a 16-bit instruction. */
10544 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10545 && inst.size_req != 4
10546 && !(inst.operands[1].imm & ~0xff))
10548 mask = 1 << inst.operands[0].reg;
10550 if (inst.operands[0].reg <= 7)
10552 if (inst.instruction == T_MNEM_stmia
10553 ? inst.operands[0].writeback
10554 : (inst.operands[0].writeback
10555 == !(inst.operands[1].imm & mask)))
10557 if (inst.instruction == T_MNEM_stmia
10558 && (inst.operands[1].imm & mask)
10559 && (inst.operands[1].imm & (mask - 1)))
10560 as_warn (_("value stored for r%d is UNKNOWN"),
10561 inst.operands[0].reg);
10563 inst.instruction = THUMB_OP16 (inst.instruction);
10564 inst.instruction |= inst.operands[0].reg << 8;
10565 inst.instruction |= inst.operands[1].imm;
10568 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10570 /* This means 1 register in reg list one of 3 situations:
10571 1. Instruction is stmia, but without writeback.
10572 2. lmdia without writeback, but with Rn not in
10574 3. ldmia with writeback, but with Rn in reglist.
10575 Case 3 is UNPREDICTABLE behaviour, so we handle
10576 case 1 and 2 which can be converted into a 16-bit
10577 str or ldr. The SP cases are handled below. */
10578 unsigned long opcode;
10579 /* First, record an error for Case 3. */
10580 if (inst.operands[1].imm & mask
10581 && inst.operands[0].writeback)
10583 _("having the base register in the register list when "
10584 "using write back is UNPREDICTABLE");
10586 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10588 inst.instruction = THUMB_OP16 (opcode);
10589 inst.instruction |= inst.operands[0].reg << 3;
10590 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10594 else if (inst.operands[0] .reg == REG_SP)
10596 if (inst.operands[0].writeback)
10599 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10600 ? T_MNEM_push : T_MNEM_pop);
10601 inst.instruction |= inst.operands[1].imm;
10604 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10607 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10608 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10609 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10617 if (inst.instruction < 0xffff)
10618 inst.instruction = THUMB_OP32 (inst.instruction);
10620 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10621 inst.operands[0].writeback);
10626 constraint (inst.operands[0].reg > 7
10627 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10628 constraint (inst.instruction != T_MNEM_ldmia
10629 && inst.instruction != T_MNEM_stmia,
10630 _("Thumb-2 instruction only valid in unified syntax"));
10631 if (inst.instruction == T_MNEM_stmia)
10633 if (!inst.operands[0].writeback)
10634 as_warn (_("this instruction will write back the base register"));
10635 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10636 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10637 as_warn (_("value stored for r%d is UNKNOWN"),
10638 inst.operands[0].reg);
10642 if (!inst.operands[0].writeback
10643 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10644 as_warn (_("this instruction will write back the base register"));
10645 else if (inst.operands[0].writeback
10646 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10647 as_warn (_("this instruction will not write back the base register"));
10650 inst.instruction = THUMB_OP16 (inst.instruction);
10651 inst.instruction |= inst.operands[0].reg << 8;
10652 inst.instruction |= inst.operands[1].imm;
10659 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10660 || inst.operands[1].postind || inst.operands[1].writeback
10661 || inst.operands[1].immisreg || inst.operands[1].shifted
10662 || inst.operands[1].negative,
10665 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10667 inst.instruction |= inst.operands[0].reg << 12;
10668 inst.instruction |= inst.operands[1].reg << 16;
10669 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10675 if (!inst.operands[1].present)
10677 constraint (inst.operands[0].reg == REG_LR,
10678 _("r14 not allowed as first register "
10679 "when second register is omitted"));
10680 inst.operands[1].reg = inst.operands[0].reg + 1;
10682 constraint (inst.operands[0].reg == inst.operands[1].reg,
10685 inst.instruction |= inst.operands[0].reg << 12;
10686 inst.instruction |= inst.operands[1].reg << 8;
10687 inst.instruction |= inst.operands[2].reg << 16;
10693 unsigned long opcode;
10696 if (inst.operands[0].isreg
10697 && !inst.operands[0].preind
10698 && inst.operands[0].reg == REG_PC)
10699 set_it_insn_type_last ();
10701 opcode = inst.instruction;
10702 if (unified_syntax)
10704 if (!inst.operands[1].isreg)
10706 if (opcode <= 0xffff)
10707 inst.instruction = THUMB_OP32 (opcode);
10708 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10711 if (inst.operands[1].isreg
10712 && !inst.operands[1].writeback
10713 && !inst.operands[1].shifted && !inst.operands[1].postind
10714 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10715 && opcode <= 0xffff
10716 && inst.size_req != 4)
10718 /* Insn may have a 16-bit form. */
10719 Rn = inst.operands[1].reg;
10720 if (inst.operands[1].immisreg)
10722 inst.instruction = THUMB_OP16 (opcode);
10724 if (Rn <= 7 && inst.operands[1].imm <= 7)
10726 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10727 reject_bad_reg (inst.operands[1].imm);
10729 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10730 && opcode != T_MNEM_ldrsb)
10731 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10732 || (Rn == REG_SP && opcode == T_MNEM_str))
10739 if (inst.reloc.pc_rel)
10740 opcode = T_MNEM_ldr_pc2;
10742 opcode = T_MNEM_ldr_pc;
10746 if (opcode == T_MNEM_ldr)
10747 opcode = T_MNEM_ldr_sp;
10749 opcode = T_MNEM_str_sp;
10751 inst.instruction = inst.operands[0].reg << 8;
10755 inst.instruction = inst.operands[0].reg;
10756 inst.instruction |= inst.operands[1].reg << 3;
10758 inst.instruction |= THUMB_OP16 (opcode);
10759 if (inst.size_req == 2)
10760 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10762 inst.relax = opcode;
10766 /* Definitely a 32-bit variant. */
10768 /* Warning for Erratum 752419. */
10769 if (opcode == T_MNEM_ldr
10770 && inst.operands[0].reg == REG_SP
10771 && inst.operands[1].writeback == 1
10772 && !inst.operands[1].immisreg)
10774 if (no_cpu_selected ()
10775 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10776 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10777 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10778 as_warn (_("This instruction may be unpredictable "
10779 "if executed on M-profile cores "
10780 "with interrupts enabled."));
10783 /* Do some validations regarding addressing modes. */
10784 if (inst.operands[1].immisreg)
10785 reject_bad_reg (inst.operands[1].imm);
10787 constraint (inst.operands[1].writeback == 1
10788 && inst.operands[0].reg == inst.operands[1].reg,
10791 inst.instruction = THUMB_OP32 (opcode);
10792 inst.instruction |= inst.operands[0].reg << 12;
10793 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10794 check_ldr_r15_aligned ();
10798 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10800 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10802 /* Only [Rn,Rm] is acceptable. */
10803 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10804 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10805 || inst.operands[1].postind || inst.operands[1].shifted
10806 || inst.operands[1].negative,
10807 _("Thumb does not support this addressing mode"));
10808 inst.instruction = THUMB_OP16 (inst.instruction);
10812 inst.instruction = THUMB_OP16 (inst.instruction);
10813 if (!inst.operands[1].isreg)
10814 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10817 constraint (!inst.operands[1].preind
10818 || inst.operands[1].shifted
10819 || inst.operands[1].writeback,
10820 _("Thumb does not support this addressing mode"));
10821 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10823 constraint (inst.instruction & 0x0600,
10824 _("byte or halfword not valid for base register"));
10825 constraint (inst.operands[1].reg == REG_PC
10826 && !(inst.instruction & THUMB_LOAD_BIT),
10827 _("r15 based store not allowed"));
10828 constraint (inst.operands[1].immisreg,
10829 _("invalid base register for register offset"));
10831 if (inst.operands[1].reg == REG_PC)
10832 inst.instruction = T_OPCODE_LDR_PC;
10833 else if (inst.instruction & THUMB_LOAD_BIT)
10834 inst.instruction = T_OPCODE_LDR_SP;
10836 inst.instruction = T_OPCODE_STR_SP;
10838 inst.instruction |= inst.operands[0].reg << 8;
10839 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10843 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10844 if (!inst.operands[1].immisreg)
10846 /* Immediate offset. */
10847 inst.instruction |= inst.operands[0].reg;
10848 inst.instruction |= inst.operands[1].reg << 3;
10849 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10853 /* Register offset. */
10854 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10855 constraint (inst.operands[1].negative,
10856 _("Thumb does not support this addressing mode"));
10859 switch (inst.instruction)
10861 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10862 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10863 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10864 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10865 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10866 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10867 case 0x5600 /* ldrsb */:
10868 case 0x5e00 /* ldrsh */: break;
10872 inst.instruction |= inst.operands[0].reg;
10873 inst.instruction |= inst.operands[1].reg << 3;
10874 inst.instruction |= inst.operands[1].imm << 6;
10880 if (!inst.operands[1].present)
10882 inst.operands[1].reg = inst.operands[0].reg + 1;
10883 constraint (inst.operands[0].reg == REG_LR,
10884 _("r14 not allowed here"));
10885 constraint (inst.operands[0].reg == REG_R12,
10886 _("r12 not allowed here"));
10889 if (inst.operands[2].writeback
10890 && (inst.operands[0].reg == inst.operands[2].reg
10891 || inst.operands[1].reg == inst.operands[2].reg))
10892 as_warn (_("base register written back, and overlaps "
10893 "one of transfer registers"));
10895 inst.instruction |= inst.operands[0].reg << 12;
10896 inst.instruction |= inst.operands[1].reg << 8;
10897 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10903 inst.instruction |= inst.operands[0].reg << 12;
10904 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10910 unsigned Rd, Rn, Rm, Ra;
10912 Rd = inst.operands[0].reg;
10913 Rn = inst.operands[1].reg;
10914 Rm = inst.operands[2].reg;
10915 Ra = inst.operands[3].reg;
10917 reject_bad_reg (Rd);
10918 reject_bad_reg (Rn);
10919 reject_bad_reg (Rm);
10920 reject_bad_reg (Ra);
10922 inst.instruction |= Rd << 8;
10923 inst.instruction |= Rn << 16;
10924 inst.instruction |= Rm;
10925 inst.instruction |= Ra << 12;
10931 unsigned RdLo, RdHi, Rn, Rm;
10933 RdLo = inst.operands[0].reg;
10934 RdHi = inst.operands[1].reg;
10935 Rn = inst.operands[2].reg;
10936 Rm = inst.operands[3].reg;
10938 reject_bad_reg (RdLo);
10939 reject_bad_reg (RdHi);
10940 reject_bad_reg (Rn);
10941 reject_bad_reg (Rm);
10943 inst.instruction |= RdLo << 12;
10944 inst.instruction |= RdHi << 8;
10945 inst.instruction |= Rn << 16;
10946 inst.instruction |= Rm;
10950 do_t_mov_cmp (void)
10954 Rn = inst.operands[0].reg;
10955 Rm = inst.operands[1].reg;
10958 set_it_insn_type_last ();
10960 if (unified_syntax)
10962 int r0off = (inst.instruction == T_MNEM_mov
10963 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10964 unsigned long opcode;
10965 bfd_boolean narrow;
10966 bfd_boolean low_regs;
10968 low_regs = (Rn <= 7 && Rm <= 7);
10969 opcode = inst.instruction;
10970 if (in_it_block ())
10971 narrow = opcode != T_MNEM_movs;
10973 narrow = opcode != T_MNEM_movs || low_regs;
10974 if (inst.size_req == 4
10975 || inst.operands[1].shifted)
10978 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10979 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10980 && !inst.operands[1].shifted
10984 inst.instruction = T2_SUBS_PC_LR;
10988 if (opcode == T_MNEM_cmp)
10990 constraint (Rn == REG_PC, BAD_PC);
10993 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10995 warn_deprecated_sp (Rm);
10996 /* R15 was documented as a valid choice for Rm in ARMv6,
10997 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10998 tools reject R15, so we do too. */
10999 constraint (Rm == REG_PC, BAD_PC);
11002 reject_bad_reg (Rm);
11004 else if (opcode == T_MNEM_mov
11005 || opcode == T_MNEM_movs)
11007 if (inst.operands[1].isreg)
11009 if (opcode == T_MNEM_movs)
11011 reject_bad_reg (Rn);
11012 reject_bad_reg (Rm);
11016 /* This is mov.n. */
11017 if ((Rn == REG_SP || Rn == REG_PC)
11018 && (Rm == REG_SP || Rm == REG_PC))
11020 as_warn (_("Use of r%u as a source register is "
11021 "deprecated when r%u is the destination "
11022 "register."), Rm, Rn);
11027 /* This is mov.w. */
11028 constraint (Rn == REG_PC, BAD_PC);
11029 constraint (Rm == REG_PC, BAD_PC);
11030 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11034 reject_bad_reg (Rn);
11037 if (!inst.operands[1].isreg)
11039 /* Immediate operand. */
11040 if (!in_it_block () && opcode == T_MNEM_mov)
11042 if (low_regs && narrow)
11044 inst.instruction = THUMB_OP16 (opcode);
11045 inst.instruction |= Rn << 8;
11046 if (inst.size_req == 2)
11047 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11049 inst.relax = opcode;
11053 inst.instruction = THUMB_OP32 (inst.instruction);
11054 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11055 inst.instruction |= Rn << r0off;
11056 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11059 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11060 && (inst.instruction == T_MNEM_mov
11061 || inst.instruction == T_MNEM_movs))
11063 /* Register shifts are encoded as separate shift instructions. */
11064 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11066 if (in_it_block ())
11071 if (inst.size_req == 4)
11074 if (!low_regs || inst.operands[1].imm > 7)
11080 switch (inst.operands[1].shift_kind)
11083 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11086 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11089 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11092 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11098 inst.instruction = opcode;
11101 inst.instruction |= Rn;
11102 inst.instruction |= inst.operands[1].imm << 3;
11107 inst.instruction |= CONDS_BIT;
11109 inst.instruction |= Rn << 8;
11110 inst.instruction |= Rm << 16;
11111 inst.instruction |= inst.operands[1].imm;
11116 /* Some mov with immediate shift have narrow variants.
11117 Register shifts are handled above. */
11118 if (low_regs && inst.operands[1].shifted
11119 && (inst.instruction == T_MNEM_mov
11120 || inst.instruction == T_MNEM_movs))
11122 if (in_it_block ())
11123 narrow = (inst.instruction == T_MNEM_mov);
11125 narrow = (inst.instruction == T_MNEM_movs);
11130 switch (inst.operands[1].shift_kind)
11132 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11133 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11134 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11135 default: narrow = FALSE; break;
11141 inst.instruction |= Rn;
11142 inst.instruction |= Rm << 3;
11143 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11147 inst.instruction = THUMB_OP32 (inst.instruction);
11148 inst.instruction |= Rn << r0off;
11149 encode_thumb32_shifted_operand (1);
11153 switch (inst.instruction)
11156 /* In v4t or v5t a move of two lowregs produces unpredictable
11157 results. Don't allow this. */
11160 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11161 "MOV Rd, Rs with two low registers is not "
11162 "permitted on this architecture");
11163 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11167 inst.instruction = T_OPCODE_MOV_HR;
11168 inst.instruction |= (Rn & 0x8) << 4;
11169 inst.instruction |= (Rn & 0x7);
11170 inst.instruction |= Rm << 3;
11174 /* We know we have low registers at this point.
11175 Generate LSLS Rd, Rs, #0. */
11176 inst.instruction = T_OPCODE_LSL_I;
11177 inst.instruction |= Rn;
11178 inst.instruction |= Rm << 3;
11184 inst.instruction = T_OPCODE_CMP_LR;
11185 inst.instruction |= Rn;
11186 inst.instruction |= Rm << 3;
11190 inst.instruction = T_OPCODE_CMP_HR;
11191 inst.instruction |= (Rn & 0x8) << 4;
11192 inst.instruction |= (Rn & 0x7);
11193 inst.instruction |= Rm << 3;
11200 inst.instruction = THUMB_OP16 (inst.instruction);
11202 /* PR 10443: Do not silently ignore shifted operands. */
11203 constraint (inst.operands[1].shifted,
11204 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11206 if (inst.operands[1].isreg)
11208 if (Rn < 8 && Rm < 8)
11210 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11211 since a MOV instruction produces unpredictable results. */
11212 if (inst.instruction == T_OPCODE_MOV_I8)
11213 inst.instruction = T_OPCODE_ADD_I3;
11215 inst.instruction = T_OPCODE_CMP_LR;
11217 inst.instruction |= Rn;
11218 inst.instruction |= Rm << 3;
11222 if (inst.instruction == T_OPCODE_MOV_I8)
11223 inst.instruction = T_OPCODE_MOV_HR;
11225 inst.instruction = T_OPCODE_CMP_HR;
11231 constraint (Rn > 7,
11232 _("only lo regs allowed with immediate"));
11233 inst.instruction |= Rn << 8;
11234 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11245 top = (inst.instruction & 0x00800000) != 0;
11246 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11248 constraint (top, _(":lower16: not allowed this instruction"));
11249 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11251 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11253 constraint (!top, _(":upper16: not allowed this instruction"));
11254 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11257 Rd = inst.operands[0].reg;
11258 reject_bad_reg (Rd);
11260 inst.instruction |= Rd << 8;
11261 if (inst.reloc.type == BFD_RELOC_UNUSED)
11263 imm = inst.reloc.exp.X_add_number;
11264 inst.instruction |= (imm & 0xf000) << 4;
11265 inst.instruction |= (imm & 0x0800) << 15;
11266 inst.instruction |= (imm & 0x0700) << 4;
11267 inst.instruction |= (imm & 0x00ff);
11272 do_t_mvn_tst (void)
11276 Rn = inst.operands[0].reg;
11277 Rm = inst.operands[1].reg;
11279 if (inst.instruction == T_MNEM_cmp
11280 || inst.instruction == T_MNEM_cmn)
11281 constraint (Rn == REG_PC, BAD_PC);
11283 reject_bad_reg (Rn);
11284 reject_bad_reg (Rm);
11286 if (unified_syntax)
11288 int r0off = (inst.instruction == T_MNEM_mvn
11289 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11290 bfd_boolean narrow;
11292 if (inst.size_req == 4
11293 || inst.instruction > 0xffff
11294 || inst.operands[1].shifted
11295 || Rn > 7 || Rm > 7)
11297 else if (inst.instruction == T_MNEM_cmn)
11299 else if (THUMB_SETS_FLAGS (inst.instruction))
11300 narrow = !in_it_block ();
11302 narrow = in_it_block ();
11304 if (!inst.operands[1].isreg)
11306 /* For an immediate, we always generate a 32-bit opcode;
11307 section relaxation will shrink it later if possible. */
11308 if (inst.instruction < 0xffff)
11309 inst.instruction = THUMB_OP32 (inst.instruction);
11310 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11311 inst.instruction |= Rn << r0off;
11312 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11316 /* See if we can do this with a 16-bit instruction. */
11319 inst.instruction = THUMB_OP16 (inst.instruction);
11320 inst.instruction |= Rn;
11321 inst.instruction |= Rm << 3;
11325 constraint (inst.operands[1].shifted
11326 && inst.operands[1].immisreg,
11327 _("shift must be constant"));
11328 if (inst.instruction < 0xffff)
11329 inst.instruction = THUMB_OP32 (inst.instruction);
11330 inst.instruction |= Rn << r0off;
11331 encode_thumb32_shifted_operand (1);
11337 constraint (inst.instruction > 0xffff
11338 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11339 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11340 _("unshifted register required"));
11341 constraint (Rn > 7 || Rm > 7,
11344 inst.instruction = THUMB_OP16 (inst.instruction);
11345 inst.instruction |= Rn;
11346 inst.instruction |= Rm << 3;
11355 if (do_vfp_nsyn_mrs () == SUCCESS)
11358 Rd = inst.operands[0].reg;
11359 reject_bad_reg (Rd);
11360 inst.instruction |= Rd << 8;
11362 if (inst.operands[1].isreg)
11364 unsigned br = inst.operands[1].reg;
11365 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11366 as_bad (_("bad register for mrs"));
11368 inst.instruction |= br & (0xf << 16);
11369 inst.instruction |= (br & 0x300) >> 4;
11370 inst.instruction |= (br & SPSR_BIT) >> 2;
11374 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11376 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11378 /* PR gas/12698: The constraint is only applied for m_profile.
11379 If the user has specified -march=all, we want to ignore it as
11380 we are building for any CPU type, including non-m variants. */
11381 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11382 constraint ((flags != 0) && m_profile, _("selected processor does "
11383 "not support requested special purpose register"));
11386 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11388 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11389 _("'APSR', 'CPSR' or 'SPSR' expected"));
11391 inst.instruction |= (flags & SPSR_BIT) >> 2;
11392 inst.instruction |= inst.operands[1].imm & 0xff;
11393 inst.instruction |= 0xf0000;
11403 if (do_vfp_nsyn_msr () == SUCCESS)
11406 constraint (!inst.operands[1].isreg,
11407 _("Thumb encoding does not support an immediate here"));
11409 if (inst.operands[0].isreg)
11410 flags = (int)(inst.operands[0].reg);
11412 flags = inst.operands[0].imm;
11414 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11416 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11418 /* PR gas/12698: The constraint is only applied for m_profile.
11419 If the user has specified -march=all, we want to ignore it as
11420 we are building for any CPU type, including non-m variants. */
11421 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11422 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11423 && (bits & ~(PSR_s | PSR_f)) != 0)
11424 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11425 && bits != PSR_f)) && m_profile,
11426 _("selected processor does not support requested special "
11427 "purpose register"));
11430 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11431 "requested special purpose register"));
11433 Rn = inst.operands[1].reg;
11434 reject_bad_reg (Rn);
11436 inst.instruction |= (flags & SPSR_BIT) >> 2;
11437 inst.instruction |= (flags & 0xf0000) >> 8;
11438 inst.instruction |= (flags & 0x300) >> 4;
11439 inst.instruction |= (flags & 0xff);
11440 inst.instruction |= Rn << 16;
11446 bfd_boolean narrow;
11447 unsigned Rd, Rn, Rm;
11449 if (!inst.operands[2].present)
11450 inst.operands[2].reg = inst.operands[0].reg;
11452 Rd = inst.operands[0].reg;
11453 Rn = inst.operands[1].reg;
11454 Rm = inst.operands[2].reg;
11456 if (unified_syntax)
11458 if (inst.size_req == 4
11464 else if (inst.instruction == T_MNEM_muls)
11465 narrow = !in_it_block ();
11467 narrow = in_it_block ();
11471 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11472 constraint (Rn > 7 || Rm > 7,
11479 /* 16-bit MULS/Conditional MUL. */
11480 inst.instruction = THUMB_OP16 (inst.instruction);
11481 inst.instruction |= Rd;
11484 inst.instruction |= Rm << 3;
11486 inst.instruction |= Rn << 3;
11488 constraint (1, _("dest must overlap one source register"));
11492 constraint (inst.instruction != T_MNEM_mul,
11493 _("Thumb-2 MUL must not set flags"));
11495 inst.instruction = THUMB_OP32 (inst.instruction);
11496 inst.instruction |= Rd << 8;
11497 inst.instruction |= Rn << 16;
11498 inst.instruction |= Rm << 0;
11500 reject_bad_reg (Rd);
11501 reject_bad_reg (Rn);
11502 reject_bad_reg (Rm);
11509 unsigned RdLo, RdHi, Rn, Rm;
11511 RdLo = inst.operands[0].reg;
11512 RdHi = inst.operands[1].reg;
11513 Rn = inst.operands[2].reg;
11514 Rm = inst.operands[3].reg;
11516 reject_bad_reg (RdLo);
11517 reject_bad_reg (RdHi);
11518 reject_bad_reg (Rn);
11519 reject_bad_reg (Rm);
11521 inst.instruction |= RdLo << 12;
11522 inst.instruction |= RdHi << 8;
11523 inst.instruction |= Rn << 16;
11524 inst.instruction |= Rm;
11527 as_tsktsk (_("rdhi and rdlo must be different"));
11533 set_it_insn_type (NEUTRAL_IT_INSN);
11535 if (unified_syntax)
11537 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11539 inst.instruction = THUMB_OP32 (inst.instruction);
11540 inst.instruction |= inst.operands[0].imm;
11544 /* PR9722: Check for Thumb2 availability before
11545 generating a thumb2 nop instruction. */
11546 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11548 inst.instruction = THUMB_OP16 (inst.instruction);
11549 inst.instruction |= inst.operands[0].imm << 4;
11552 inst.instruction = 0x46c0;
11557 constraint (inst.operands[0].present,
11558 _("Thumb does not support NOP with hints"));
11559 inst.instruction = 0x46c0;
11566 if (unified_syntax)
11568 bfd_boolean narrow;
11570 if (THUMB_SETS_FLAGS (inst.instruction))
11571 narrow = !in_it_block ();
11573 narrow = in_it_block ();
11574 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11576 if (inst.size_req == 4)
11581 inst.instruction = THUMB_OP32 (inst.instruction);
11582 inst.instruction |= inst.operands[0].reg << 8;
11583 inst.instruction |= inst.operands[1].reg << 16;
11587 inst.instruction = THUMB_OP16 (inst.instruction);
11588 inst.instruction |= inst.operands[0].reg;
11589 inst.instruction |= inst.operands[1].reg << 3;
11594 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11596 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11598 inst.instruction = THUMB_OP16 (inst.instruction);
11599 inst.instruction |= inst.operands[0].reg;
11600 inst.instruction |= inst.operands[1].reg << 3;
11609 Rd = inst.operands[0].reg;
11610 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11612 reject_bad_reg (Rd);
11613 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11614 reject_bad_reg (Rn);
11616 inst.instruction |= Rd << 8;
11617 inst.instruction |= Rn << 16;
11619 if (!inst.operands[2].isreg)
11621 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11622 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11628 Rm = inst.operands[2].reg;
11629 reject_bad_reg (Rm);
11631 constraint (inst.operands[2].shifted
11632 && inst.operands[2].immisreg,
11633 _("shift must be constant"));
11634 encode_thumb32_shifted_operand (2);
11641 unsigned Rd, Rn, Rm;
11643 Rd = inst.operands[0].reg;
11644 Rn = inst.operands[1].reg;
11645 Rm = inst.operands[2].reg;
11647 reject_bad_reg (Rd);
11648 reject_bad_reg (Rn);
11649 reject_bad_reg (Rm);
11651 inst.instruction |= Rd << 8;
11652 inst.instruction |= Rn << 16;
11653 inst.instruction |= Rm;
11654 if (inst.operands[3].present)
11656 unsigned int val = inst.reloc.exp.X_add_number;
11657 constraint (inst.reloc.exp.X_op != O_constant,
11658 _("expression too complex"));
11659 inst.instruction |= (val & 0x1c) << 10;
11660 inst.instruction |= (val & 0x03) << 6;
11667 if (!inst.operands[3].present)
11671 inst.instruction &= ~0x00000020;
11673 /* PR 10168. Swap the Rm and Rn registers. */
11674 Rtmp = inst.operands[1].reg;
11675 inst.operands[1].reg = inst.operands[2].reg;
11676 inst.operands[2].reg = Rtmp;
11684 if (inst.operands[0].immisreg)
11685 reject_bad_reg (inst.operands[0].imm);
11687 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11691 do_t_push_pop (void)
11695 constraint (inst.operands[0].writeback,
11696 _("push/pop do not support {reglist}^"));
11697 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11698 _("expression too complex"));
11700 mask = inst.operands[0].imm;
11701 if ((mask & ~0xff) == 0)
11702 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11703 else if ((inst.instruction == T_MNEM_push
11704 && (mask & ~0xff) == 1 << REG_LR)
11705 || (inst.instruction == T_MNEM_pop
11706 && (mask & ~0xff) == 1 << REG_PC))
11708 inst.instruction = THUMB_OP16 (inst.instruction);
11709 inst.instruction |= THUMB_PP_PC_LR;
11710 inst.instruction |= mask & 0xff;
11712 else if (unified_syntax)
11714 inst.instruction = THUMB_OP32 (inst.instruction);
11715 encode_thumb2_ldmstm (13, mask, TRUE);
11719 inst.error = _("invalid register list to push/pop instruction");
11729 Rd = inst.operands[0].reg;
11730 Rm = inst.operands[1].reg;
11732 reject_bad_reg (Rd);
11733 reject_bad_reg (Rm);
11735 inst.instruction |= Rd << 8;
11736 inst.instruction |= Rm << 16;
11737 inst.instruction |= Rm;
11745 Rd = inst.operands[0].reg;
11746 Rm = inst.operands[1].reg;
11748 reject_bad_reg (Rd);
11749 reject_bad_reg (Rm);
11751 if (Rd <= 7 && Rm <= 7
11752 && inst.size_req != 4)
11754 inst.instruction = THUMB_OP16 (inst.instruction);
11755 inst.instruction |= Rd;
11756 inst.instruction |= Rm << 3;
11758 else if (unified_syntax)
11760 inst.instruction = THUMB_OP32 (inst.instruction);
11761 inst.instruction |= Rd << 8;
11762 inst.instruction |= Rm << 16;
11763 inst.instruction |= Rm;
11766 inst.error = BAD_HIREG;
11774 Rd = inst.operands[0].reg;
11775 Rm = inst.operands[1].reg;
11777 reject_bad_reg (Rd);
11778 reject_bad_reg (Rm);
11780 inst.instruction |= Rd << 8;
11781 inst.instruction |= Rm;
11789 Rd = inst.operands[0].reg;
11790 Rs = (inst.operands[1].present
11791 ? inst.operands[1].reg /* Rd, Rs, foo */
11792 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11794 reject_bad_reg (Rd);
11795 reject_bad_reg (Rs);
11796 if (inst.operands[2].isreg)
11797 reject_bad_reg (inst.operands[2].reg);
11799 inst.instruction |= Rd << 8;
11800 inst.instruction |= Rs << 16;
11801 if (!inst.operands[2].isreg)
11803 bfd_boolean narrow;
11805 if ((inst.instruction & 0x00100000) != 0)
11806 narrow = !in_it_block ();
11808 narrow = in_it_block ();
11810 if (Rd > 7 || Rs > 7)
11813 if (inst.size_req == 4 || !unified_syntax)
11816 if (inst.reloc.exp.X_op != O_constant
11817 || inst.reloc.exp.X_add_number != 0)
11820 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11821 relaxation, but it doesn't seem worth the hassle. */
11824 inst.reloc.type = BFD_RELOC_UNUSED;
11825 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11826 inst.instruction |= Rs << 3;
11827 inst.instruction |= Rd;
11831 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11832 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11836 encode_thumb32_shifted_operand (2);
11842 if (warn_on_deprecated
11843 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11844 as_warn (_("setend use is deprecated for ARMv8"));
11846 set_it_insn_type (OUTSIDE_IT_INSN);
11847 if (inst.operands[0].imm)
11848 inst.instruction |= 0x8;
11854 if (!inst.operands[1].present)
11855 inst.operands[1].reg = inst.operands[0].reg;
11857 if (unified_syntax)
11859 bfd_boolean narrow;
11862 switch (inst.instruction)
11865 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11867 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11869 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11871 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11875 if (THUMB_SETS_FLAGS (inst.instruction))
11876 narrow = !in_it_block ();
11878 narrow = in_it_block ();
11879 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11881 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11883 if (inst.operands[2].isreg
11884 && (inst.operands[1].reg != inst.operands[0].reg
11885 || inst.operands[2].reg > 7))
11887 if (inst.size_req == 4)
11890 reject_bad_reg (inst.operands[0].reg);
11891 reject_bad_reg (inst.operands[1].reg);
11895 if (inst.operands[2].isreg)
11897 reject_bad_reg (inst.operands[2].reg);
11898 inst.instruction = THUMB_OP32 (inst.instruction);
11899 inst.instruction |= inst.operands[0].reg << 8;
11900 inst.instruction |= inst.operands[1].reg << 16;
11901 inst.instruction |= inst.operands[2].reg;
11903 /* PR 12854: Error on extraneous shifts. */
11904 constraint (inst.operands[2].shifted,
11905 _("extraneous shift as part of operand to shift insn"));
11909 inst.operands[1].shifted = 1;
11910 inst.operands[1].shift_kind = shift_kind;
11911 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11912 ? T_MNEM_movs : T_MNEM_mov);
11913 inst.instruction |= inst.operands[0].reg << 8;
11914 encode_thumb32_shifted_operand (1);
11915 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11916 inst.reloc.type = BFD_RELOC_UNUSED;
11921 if (inst.operands[2].isreg)
11923 switch (shift_kind)
11925 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11926 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11927 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11928 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11932 inst.instruction |= inst.operands[0].reg;
11933 inst.instruction |= inst.operands[2].reg << 3;
11935 /* PR 12854: Error on extraneous shifts. */
11936 constraint (inst.operands[2].shifted,
11937 _("extraneous shift as part of operand to shift insn"));
11941 switch (shift_kind)
11943 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11944 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11945 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11948 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11949 inst.instruction |= inst.operands[0].reg;
11950 inst.instruction |= inst.operands[1].reg << 3;
11956 constraint (inst.operands[0].reg > 7
11957 || inst.operands[1].reg > 7, BAD_HIREG);
11958 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11960 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11962 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11963 constraint (inst.operands[0].reg != inst.operands[1].reg,
11964 _("source1 and dest must be same register"));
11966 switch (inst.instruction)
11968 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11969 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11970 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11971 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11975 inst.instruction |= inst.operands[0].reg;
11976 inst.instruction |= inst.operands[2].reg << 3;
11978 /* PR 12854: Error on extraneous shifts. */
11979 constraint (inst.operands[2].shifted,
11980 _("extraneous shift as part of operand to shift insn"));
11984 switch (inst.instruction)
11986 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11987 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11988 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11989 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11992 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11993 inst.instruction |= inst.operands[0].reg;
11994 inst.instruction |= inst.operands[1].reg << 3;
12002 unsigned Rd, Rn, Rm;
12004 Rd = inst.operands[0].reg;
12005 Rn = inst.operands[1].reg;
12006 Rm = inst.operands[2].reg;
12008 reject_bad_reg (Rd);
12009 reject_bad_reg (Rn);
12010 reject_bad_reg (Rm);
12012 inst.instruction |= Rd << 8;
12013 inst.instruction |= Rn << 16;
12014 inst.instruction |= Rm;
12020 unsigned Rd, Rn, Rm;
12022 Rd = inst.operands[0].reg;
12023 Rm = inst.operands[1].reg;
12024 Rn = inst.operands[2].reg;
12026 reject_bad_reg (Rd);
12027 reject_bad_reg (Rn);
12028 reject_bad_reg (Rm);
12030 inst.instruction |= Rd << 8;
12031 inst.instruction |= Rn << 16;
12032 inst.instruction |= Rm;
12038 unsigned int value = inst.reloc.exp.X_add_number;
12039 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12040 _("SMC is not permitted on this architecture"));
12041 constraint (inst.reloc.exp.X_op != O_constant,
12042 _("expression too complex"));
12043 inst.reloc.type = BFD_RELOC_UNUSED;
12044 inst.instruction |= (value & 0xf000) >> 12;
12045 inst.instruction |= (value & 0x0ff0);
12046 inst.instruction |= (value & 0x000f) << 16;
12052 unsigned int value = inst.reloc.exp.X_add_number;
12054 inst.reloc.type = BFD_RELOC_UNUSED;
12055 inst.instruction |= (value & 0x0fff);
12056 inst.instruction |= (value & 0xf000) << 4;
12060 do_t_ssat_usat (int bias)
12064 Rd = inst.operands[0].reg;
12065 Rn = inst.operands[2].reg;
12067 reject_bad_reg (Rd);
12068 reject_bad_reg (Rn);
12070 inst.instruction |= Rd << 8;
12071 inst.instruction |= inst.operands[1].imm - bias;
12072 inst.instruction |= Rn << 16;
12074 if (inst.operands[3].present)
12076 offsetT shift_amount = inst.reloc.exp.X_add_number;
12078 inst.reloc.type = BFD_RELOC_UNUSED;
12080 constraint (inst.reloc.exp.X_op != O_constant,
12081 _("expression too complex"));
12083 if (shift_amount != 0)
12085 constraint (shift_amount > 31,
12086 _("shift expression is too large"));
12088 if (inst.operands[3].shift_kind == SHIFT_ASR)
12089 inst.instruction |= 0x00200000; /* sh bit. */
12091 inst.instruction |= (shift_amount & 0x1c) << 10;
12092 inst.instruction |= (shift_amount & 0x03) << 6;
12100 do_t_ssat_usat (1);
12108 Rd = inst.operands[0].reg;
12109 Rn = inst.operands[2].reg;
12111 reject_bad_reg (Rd);
12112 reject_bad_reg (Rn);
12114 inst.instruction |= Rd << 8;
12115 inst.instruction |= inst.operands[1].imm - 1;
12116 inst.instruction |= Rn << 16;
12122 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12123 || inst.operands[2].postind || inst.operands[2].writeback
12124 || inst.operands[2].immisreg || inst.operands[2].shifted
12125 || inst.operands[2].negative,
12128 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12130 inst.instruction |= inst.operands[0].reg << 8;
12131 inst.instruction |= inst.operands[1].reg << 12;
12132 inst.instruction |= inst.operands[2].reg << 16;
12133 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12139 if (!inst.operands[2].present)
12140 inst.operands[2].reg = inst.operands[1].reg + 1;
12142 constraint (inst.operands[0].reg == inst.operands[1].reg
12143 || inst.operands[0].reg == inst.operands[2].reg
12144 || inst.operands[0].reg == inst.operands[3].reg,
12147 inst.instruction |= inst.operands[0].reg;
12148 inst.instruction |= inst.operands[1].reg << 12;
12149 inst.instruction |= inst.operands[2].reg << 8;
12150 inst.instruction |= inst.operands[3].reg << 16;
12156 unsigned Rd, Rn, Rm;
12158 Rd = inst.operands[0].reg;
12159 Rn = inst.operands[1].reg;
12160 Rm = inst.operands[2].reg;
12162 reject_bad_reg (Rd);
12163 reject_bad_reg (Rn);
12164 reject_bad_reg (Rm);
12166 inst.instruction |= Rd << 8;
12167 inst.instruction |= Rn << 16;
12168 inst.instruction |= Rm;
12169 inst.instruction |= inst.operands[3].imm << 4;
12177 Rd = inst.operands[0].reg;
12178 Rm = inst.operands[1].reg;
12180 reject_bad_reg (Rd);
12181 reject_bad_reg (Rm);
12183 if (inst.instruction <= 0xffff
12184 && inst.size_req != 4
12185 && Rd <= 7 && Rm <= 7
12186 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12188 inst.instruction = THUMB_OP16 (inst.instruction);
12189 inst.instruction |= Rd;
12190 inst.instruction |= Rm << 3;
12192 else if (unified_syntax)
12194 if (inst.instruction <= 0xffff)
12195 inst.instruction = THUMB_OP32 (inst.instruction);
12196 inst.instruction |= Rd << 8;
12197 inst.instruction |= Rm;
12198 inst.instruction |= inst.operands[2].imm << 4;
12202 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12203 _("Thumb encoding does not support rotation"));
12204 constraint (1, BAD_HIREG);
12211 /* We have to do the following check manually as ARM_EXT_OS only applies
12213 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12215 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12216 /* This only applies to the v6m howver, not later architectures. */
12217 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12218 as_bad (_("SVC is not permitted on this architecture"));
12219 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12222 inst.reloc.type = BFD_RELOC_ARM_SWI;
12231 half = (inst.instruction & 0x10) != 0;
12232 set_it_insn_type_last ();
12233 constraint (inst.operands[0].immisreg,
12234 _("instruction requires register index"));
12236 Rn = inst.operands[0].reg;
12237 Rm = inst.operands[0].imm;
12239 constraint (Rn == REG_SP, BAD_SP);
12240 reject_bad_reg (Rm);
12242 constraint (!half && inst.operands[0].shifted,
12243 _("instruction does not allow shifted index"));
12244 inst.instruction |= (Rn << 16) | Rm;
12250 do_t_ssat_usat (0);
12258 Rd = inst.operands[0].reg;
12259 Rn = inst.operands[2].reg;
12261 reject_bad_reg (Rd);
12262 reject_bad_reg (Rn);
12264 inst.instruction |= Rd << 8;
12265 inst.instruction |= inst.operands[1].imm;
12266 inst.instruction |= Rn << 16;
12269 /* Neon instruction encoder helpers. */
12271 /* Encodings for the different types for various Neon opcodes. */
12273 /* An "invalid" code for the following tables. */
12276 struct neon_tab_entry
12279 unsigned float_or_poly;
12280 unsigned scalar_or_imm;
12283 /* Map overloaded Neon opcodes to their respective encodings. */
12284 #define NEON_ENC_TAB \
12285 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12286 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12287 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12288 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12289 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12290 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12291 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12292 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12293 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12294 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12295 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12296 /* Register variants of the following two instructions are encoded as
12297 vcge / vcgt with the operands reversed. */ \
12298 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12299 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12300 X(vfma, N_INV, 0x0000c10, N_INV), \
12301 X(vfms, N_INV, 0x0200c10, N_INV), \
12302 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12303 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12304 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12305 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12306 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12307 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12308 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12309 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12310 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12311 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12312 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12313 X(vshl, 0x0000400, N_INV, 0x0800510), \
12314 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12315 X(vand, 0x0000110, N_INV, 0x0800030), \
12316 X(vbic, 0x0100110, N_INV, 0x0800030), \
12317 X(veor, 0x1000110, N_INV, N_INV), \
12318 X(vorn, 0x0300110, N_INV, 0x0800010), \
12319 X(vorr, 0x0200110, N_INV, 0x0800010), \
12320 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12321 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12322 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12323 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12324 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12325 X(vst1, 0x0000000, 0x0800000, N_INV), \
12326 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12327 X(vst2, 0x0000100, 0x0800100, N_INV), \
12328 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12329 X(vst3, 0x0000200, 0x0800200, N_INV), \
12330 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12331 X(vst4, 0x0000300, 0x0800300, N_INV), \
12332 X(vmovn, 0x1b20200, N_INV, N_INV), \
12333 X(vtrn, 0x1b20080, N_INV, N_INV), \
12334 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12335 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12336 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12337 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12338 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12339 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12340 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12341 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12342 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12343 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12344 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12345 X(vseleq, 0xe000a00, N_INV, N_INV), \
12346 X(vselvs, 0xe100a00, N_INV, N_INV), \
12347 X(vselge, 0xe200a00, N_INV, N_INV), \
12348 X(vselgt, 0xe300a00, N_INV, N_INV), \
12349 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12350 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12351 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12352 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12353 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12354 X(aes, 0x3b00300, N_INV, N_INV), \
12355 X(sha3op, 0x2000c00, N_INV, N_INV)
12359 #define X(OPC,I,F,S) N_MNEM_##OPC
12364 static const struct neon_tab_entry neon_enc_tab[] =
12366 #define X(OPC,I,F,S) { (I), (F), (S) }
12371 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12372 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12373 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12374 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12375 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12376 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12377 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12378 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12379 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12380 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12381 #define NEON_ENC_SINGLE_(X) \
12382 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12383 #define NEON_ENC_DOUBLE_(X) \
12384 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12385 #define NEON_ENC_FPV8_(X) \
12386 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12388 #define NEON_ENCODE(type, inst) \
12391 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12392 inst.is_neon = 1; \
12396 #define check_neon_suffixes \
12399 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12401 as_bad (_("invalid neon suffix for non neon instruction")); \
12407 /* Define shapes for instruction operands. The following mnemonic characters
12408 are used in this table:
12410 F - VFP S<n> register
12411 D - Neon D<n> register
12412 Q - Neon Q<n> register
12416 L - D<n> register list
12418 This table is used to generate various data:
12419 - enumerations of the form NS_DDR to be used as arguments to
12421 - a table classifying shapes into single, double, quad, mixed.
12422 - a table used to drive neon_select_shape. */
12424 #define NEON_SHAPE_DEF \
12425 X(3, (D, D, D), DOUBLE), \
12426 X(3, (Q, Q, Q), QUAD), \
12427 X(3, (D, D, I), DOUBLE), \
12428 X(3, (Q, Q, I), QUAD), \
12429 X(3, (D, D, S), DOUBLE), \
12430 X(3, (Q, Q, S), QUAD), \
12431 X(2, (D, D), DOUBLE), \
12432 X(2, (Q, Q), QUAD), \
12433 X(2, (D, S), DOUBLE), \
12434 X(2, (Q, S), QUAD), \
12435 X(2, (D, R), DOUBLE), \
12436 X(2, (Q, R), QUAD), \
12437 X(2, (D, I), DOUBLE), \
12438 X(2, (Q, I), QUAD), \
12439 X(3, (D, L, D), DOUBLE), \
12440 X(2, (D, Q), MIXED), \
12441 X(2, (Q, D), MIXED), \
12442 X(3, (D, Q, I), MIXED), \
12443 X(3, (Q, D, I), MIXED), \
12444 X(3, (Q, D, D), MIXED), \
12445 X(3, (D, Q, Q), MIXED), \
12446 X(3, (Q, Q, D), MIXED), \
12447 X(3, (Q, D, S), MIXED), \
12448 X(3, (D, Q, S), MIXED), \
12449 X(4, (D, D, D, I), DOUBLE), \
12450 X(4, (Q, Q, Q, I), QUAD), \
12451 X(2, (F, F), SINGLE), \
12452 X(3, (F, F, F), SINGLE), \
12453 X(2, (F, I), SINGLE), \
12454 X(2, (F, D), MIXED), \
12455 X(2, (D, F), MIXED), \
12456 X(3, (F, F, I), MIXED), \
12457 X(4, (R, R, F, F), SINGLE), \
12458 X(4, (F, F, R, R), SINGLE), \
12459 X(3, (D, R, R), DOUBLE), \
12460 X(3, (R, R, D), DOUBLE), \
12461 X(2, (S, R), SINGLE), \
12462 X(2, (R, S), SINGLE), \
12463 X(2, (F, R), SINGLE), \
12464 X(2, (R, F), SINGLE)
12466 #define S2(A,B) NS_##A##B
12467 #define S3(A,B,C) NS_##A##B##C
12468 #define S4(A,B,C,D) NS_##A##B##C##D
12470 #define X(N, L, C) S##N L
12483 enum neon_shape_class
12491 #define X(N, L, C) SC_##C
12493 static enum neon_shape_class neon_shape_class[] =
12511 /* Register widths of above. */
12512 static unsigned neon_shape_el_size[] =
12523 struct neon_shape_info
12526 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12529 #define S2(A,B) { SE_##A, SE_##B }
12530 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12531 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12533 #define X(N, L, C) { N, S##N L }
12535 static struct neon_shape_info neon_shape_tab[] =
12545 /* Bit masks used in type checking given instructions.
12546 'N_EQK' means the type must be the same as (or based on in some way) the key
12547 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12548 set, various other bits can be set as well in order to modify the meaning of
12549 the type constraint. */
12551 enum neon_type_mask
12575 N_KEY = 0x1000000, /* Key element (main type specifier). */
12576 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12577 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12578 N_UNT = 0x8000000, /* Must be explicitly untyped. */
12579 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12580 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12581 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12582 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12583 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12584 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12585 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12587 N_MAX_NONSPECIAL = N_P64
12590 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12592 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12593 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12594 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12595 #define N_SUF_32 (N_SU_32 | N_F32)
12596 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12597 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12599 /* Pass this as the first type argument to neon_check_type to ignore types
12601 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12603 /* Select a "shape" for the current instruction (describing register types or
12604 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12605 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12606 function of operand parsing, so this function doesn't need to be called.
12607 Shapes should be listed in order of decreasing length. */
12609 static enum neon_shape
12610 neon_select_shape (enum neon_shape shape, ...)
12613 enum neon_shape first_shape = shape;
12615 /* Fix missing optional operands. FIXME: we don't know at this point how
12616 many arguments we should have, so this makes the assumption that we have
12617 > 1. This is true of all current Neon opcodes, I think, but may not be
12618 true in the future. */
12619 if (!inst.operands[1].present)
12620 inst.operands[1] = inst.operands[0];
12622 va_start (ap, shape);
12624 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12629 for (j = 0; j < neon_shape_tab[shape].els; j++)
12631 if (!inst.operands[j].present)
12637 switch (neon_shape_tab[shape].el[j])
12640 if (!(inst.operands[j].isreg
12641 && inst.operands[j].isvec
12642 && inst.operands[j].issingle
12643 && !inst.operands[j].isquad))
12648 if (!(inst.operands[j].isreg
12649 && inst.operands[j].isvec
12650 && !inst.operands[j].isquad
12651 && !inst.operands[j].issingle))
12656 if (!(inst.operands[j].isreg
12657 && !inst.operands[j].isvec))
12662 if (!(inst.operands[j].isreg
12663 && inst.operands[j].isvec
12664 && inst.operands[j].isquad
12665 && !inst.operands[j].issingle))
12670 if (!(!inst.operands[j].isreg
12671 && !inst.operands[j].isscalar))
12676 if (!(!inst.operands[j].isreg
12677 && inst.operands[j].isscalar))
12687 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12688 /* We've matched all the entries in the shape table, and we don't
12689 have any left over operands which have not been matched. */
12695 if (shape == NS_NULL && first_shape != NS_NULL)
12696 first_error (_("invalid instruction shape"));
12701 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12702 means the Q bit should be set). */
12705 neon_quad (enum neon_shape shape)
12707 return neon_shape_class[shape] == SC_QUAD;
12711 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12714 /* Allow modification to be made to types which are constrained to be
12715 based on the key element, based on bits set alongside N_EQK. */
12716 if ((typebits & N_EQK) != 0)
12718 if ((typebits & N_HLF) != 0)
12720 else if ((typebits & N_DBL) != 0)
12722 if ((typebits & N_SGN) != 0)
12723 *g_type = NT_signed;
12724 else if ((typebits & N_UNS) != 0)
12725 *g_type = NT_unsigned;
12726 else if ((typebits & N_INT) != 0)
12727 *g_type = NT_integer;
12728 else if ((typebits & N_FLT) != 0)
12729 *g_type = NT_float;
12730 else if ((typebits & N_SIZ) != 0)
12731 *g_type = NT_untyped;
12735 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12736 operand type, i.e. the single type specified in a Neon instruction when it
12737 is the only one given. */
12739 static struct neon_type_el
12740 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12742 struct neon_type_el dest = *key;
12744 gas_assert ((thisarg & N_EQK) != 0);
12746 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12751 /* Convert Neon type and size into compact bitmask representation. */
12753 static enum neon_type_mask
12754 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12761 case 8: return N_8;
12762 case 16: return N_16;
12763 case 32: return N_32;
12764 case 64: return N_64;
12772 case 8: return N_I8;
12773 case 16: return N_I16;
12774 case 32: return N_I32;
12775 case 64: return N_I64;
12783 case 16: return N_F16;
12784 case 32: return N_F32;
12785 case 64: return N_F64;
12793 case 8: return N_P8;
12794 case 16: return N_P16;
12795 case 64: return N_P64;
12803 case 8: return N_S8;
12804 case 16: return N_S16;
12805 case 32: return N_S32;
12806 case 64: return N_S64;
12814 case 8: return N_U8;
12815 case 16: return N_U16;
12816 case 32: return N_U32;
12817 case 64: return N_U64;
12828 /* Convert compact Neon bitmask type representation to a type and size. Only
12829 handles the case where a single bit is set in the mask. */
12832 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12833 enum neon_type_mask mask)
12835 if ((mask & N_EQK) != 0)
12838 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12840 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
12842 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12844 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
12849 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12851 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12852 *type = NT_unsigned;
12853 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12854 *type = NT_integer;
12855 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12856 *type = NT_untyped;
12857 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
12859 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
12867 /* Modify a bitmask of allowed types. This is only needed for type
12871 modify_types_allowed (unsigned allowed, unsigned mods)
12874 enum neon_el_type type;
12880 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12882 if (el_type_of_type_chk (&type, &size,
12883 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12885 neon_modify_type_size (mods, &type, &size);
12886 destmask |= type_chk_of_el_type (type, size);
12893 /* Check type and return type classification.
12894 The manual states (paraphrase): If one datatype is given, it indicates the
12896 - the second operand, if there is one
12897 - the operand, if there is no second operand
12898 - the result, if there are no operands.
12899 This isn't quite good enough though, so we use a concept of a "key" datatype
12900 which is set on a per-instruction basis, which is the one which matters when
12901 only one data type is written.
12902 Note: this function has side-effects (e.g. filling in missing operands). All
12903 Neon instructions should call it before performing bit encoding. */
12905 static struct neon_type_el
12906 neon_check_type (unsigned els, enum neon_shape ns, ...)
12909 unsigned i, pass, key_el = 0;
12910 unsigned types[NEON_MAX_TYPE_ELS];
12911 enum neon_el_type k_type = NT_invtype;
12912 unsigned k_size = -1u;
12913 struct neon_type_el badtype = {NT_invtype, -1};
12914 unsigned key_allowed = 0;
12916 /* Optional registers in Neon instructions are always (not) in operand 1.
12917 Fill in the missing operand here, if it was omitted. */
12918 if (els > 1 && !inst.operands[1].present)
12919 inst.operands[1] = inst.operands[0];
12921 /* Suck up all the varargs. */
12923 for (i = 0; i < els; i++)
12925 unsigned thisarg = va_arg (ap, unsigned);
12926 if (thisarg == N_IGNORE_TYPE)
12931 types[i] = thisarg;
12932 if ((thisarg & N_KEY) != 0)
12937 if (inst.vectype.elems > 0)
12938 for (i = 0; i < els; i++)
12939 if (inst.operands[i].vectype.type != NT_invtype)
12941 first_error (_("types specified in both the mnemonic and operands"));
12945 /* Duplicate inst.vectype elements here as necessary.
12946 FIXME: No idea if this is exactly the same as the ARM assembler,
12947 particularly when an insn takes one register and one non-register
12949 if (inst.vectype.elems == 1 && els > 1)
12952 inst.vectype.elems = els;
12953 inst.vectype.el[key_el] = inst.vectype.el[0];
12954 for (j = 0; j < els; j++)
12956 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12959 else if (inst.vectype.elems == 0 && els > 0)
12962 /* No types were given after the mnemonic, so look for types specified
12963 after each operand. We allow some flexibility here; as long as the
12964 "key" operand has a type, we can infer the others. */
12965 for (j = 0; j < els; j++)
12966 if (inst.operands[j].vectype.type != NT_invtype)
12967 inst.vectype.el[j] = inst.operands[j].vectype;
12969 if (inst.operands[key_el].vectype.type != NT_invtype)
12971 for (j = 0; j < els; j++)
12972 if (inst.operands[j].vectype.type == NT_invtype)
12973 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12978 first_error (_("operand types can't be inferred"));
12982 else if (inst.vectype.elems != els)
12984 first_error (_("type specifier has the wrong number of parts"));
12988 for (pass = 0; pass < 2; pass++)
12990 for (i = 0; i < els; i++)
12992 unsigned thisarg = types[i];
12993 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12994 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12995 enum neon_el_type g_type = inst.vectype.el[i].type;
12996 unsigned g_size = inst.vectype.el[i].size;
12998 /* Decay more-specific signed & unsigned types to sign-insensitive
12999 integer types if sign-specific variants are unavailable. */
13000 if ((g_type == NT_signed || g_type == NT_unsigned)
13001 && (types_allowed & N_SU_ALL) == 0)
13002 g_type = NT_integer;
13004 /* If only untyped args are allowed, decay any more specific types to
13005 them. Some instructions only care about signs for some element
13006 sizes, so handle that properly. */
13007 if (((types_allowed & N_UNT) == 0)
13008 && ((g_size == 8 && (types_allowed & N_8) != 0)
13009 || (g_size == 16 && (types_allowed & N_16) != 0)
13010 || (g_size == 32 && (types_allowed & N_32) != 0)
13011 || (g_size == 64 && (types_allowed & N_64) != 0)))
13012 g_type = NT_untyped;
13016 if ((thisarg & N_KEY) != 0)
13020 key_allowed = thisarg & ~N_KEY;
13025 if ((thisarg & N_VFP) != 0)
13027 enum neon_shape_el regshape;
13028 unsigned regwidth, match;
13030 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13033 first_error (_("invalid instruction shape"));
13036 regshape = neon_shape_tab[ns].el[i];
13037 regwidth = neon_shape_el_size[regshape];
13039 /* In VFP mode, operands must match register widths. If we
13040 have a key operand, use its width, else use the width of
13041 the current operand. */
13047 if (regwidth != match)
13049 first_error (_("operand size must match register width"));
13054 if ((thisarg & N_EQK) == 0)
13056 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13058 if ((given_type & types_allowed) == 0)
13060 first_error (_("bad type in Neon instruction"));
13066 enum neon_el_type mod_k_type = k_type;
13067 unsigned mod_k_size = k_size;
13068 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13069 if (g_type != mod_k_type || g_size != mod_k_size)
13071 first_error (_("inconsistent types in Neon instruction"));
13079 return inst.vectype.el[key_el];
13082 /* Neon-style VFP instruction forwarding. */
13084 /* Thumb VFP instructions have 0xE in the condition field. */
13087 do_vfp_cond_or_thumb (void)
13092 inst.instruction |= 0xe0000000;
13094 inst.instruction |= inst.cond << 28;
13097 /* Look up and encode a simple mnemonic, for use as a helper function for the
13098 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13099 etc. It is assumed that operand parsing has already been done, and that the
13100 operands are in the form expected by the given opcode (this isn't necessarily
13101 the same as the form in which they were parsed, hence some massaging must
13102 take place before this function is called).
13103 Checks current arch version against that in the looked-up opcode. */
13106 do_vfp_nsyn_opcode (const char *opname)
13108 const struct asm_opcode *opcode;
13110 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13115 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13116 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13123 inst.instruction = opcode->tvalue;
13124 opcode->tencode ();
13128 inst.instruction = (inst.cond << 28) | opcode->avalue;
13129 opcode->aencode ();
13134 do_vfp_nsyn_add_sub (enum neon_shape rs)
13136 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13141 do_vfp_nsyn_opcode ("fadds");
13143 do_vfp_nsyn_opcode ("fsubs");
13148 do_vfp_nsyn_opcode ("faddd");
13150 do_vfp_nsyn_opcode ("fsubd");
13154 /* Check operand types to see if this is a VFP instruction, and if so call
13158 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13160 enum neon_shape rs;
13161 struct neon_type_el et;
13166 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13167 et = neon_check_type (2, rs,
13168 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13172 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13173 et = neon_check_type (3, rs,
13174 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13181 if (et.type != NT_invtype)
13192 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13194 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13199 do_vfp_nsyn_opcode ("fmacs");
13201 do_vfp_nsyn_opcode ("fnmacs");
13206 do_vfp_nsyn_opcode ("fmacd");
13208 do_vfp_nsyn_opcode ("fnmacd");
13213 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13215 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13220 do_vfp_nsyn_opcode ("ffmas");
13222 do_vfp_nsyn_opcode ("ffnmas");
13227 do_vfp_nsyn_opcode ("ffmad");
13229 do_vfp_nsyn_opcode ("ffnmad");
13234 do_vfp_nsyn_mul (enum neon_shape rs)
13237 do_vfp_nsyn_opcode ("fmuls");
13239 do_vfp_nsyn_opcode ("fmuld");
13243 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13245 int is_neg = (inst.instruction & 0x80) != 0;
13246 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13251 do_vfp_nsyn_opcode ("fnegs");
13253 do_vfp_nsyn_opcode ("fabss");
13258 do_vfp_nsyn_opcode ("fnegd");
13260 do_vfp_nsyn_opcode ("fabsd");
13264 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13265 insns belong to Neon, and are handled elsewhere. */
13268 do_vfp_nsyn_ldm_stm (int is_dbmode)
13270 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13274 do_vfp_nsyn_opcode ("fldmdbs");
13276 do_vfp_nsyn_opcode ("fldmias");
13281 do_vfp_nsyn_opcode ("fstmdbs");
13283 do_vfp_nsyn_opcode ("fstmias");
13288 do_vfp_nsyn_sqrt (void)
13290 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13291 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13294 do_vfp_nsyn_opcode ("fsqrts");
13296 do_vfp_nsyn_opcode ("fsqrtd");
13300 do_vfp_nsyn_div (void)
13302 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13303 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13304 N_F32 | N_F64 | N_KEY | N_VFP);
13307 do_vfp_nsyn_opcode ("fdivs");
13309 do_vfp_nsyn_opcode ("fdivd");
13313 do_vfp_nsyn_nmul (void)
13315 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13316 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13317 N_F32 | N_F64 | N_KEY | N_VFP);
13321 NEON_ENCODE (SINGLE, inst);
13322 do_vfp_sp_dyadic ();
13326 NEON_ENCODE (DOUBLE, inst);
13327 do_vfp_dp_rd_rn_rm ();
13329 do_vfp_cond_or_thumb ();
13333 do_vfp_nsyn_cmp (void)
13335 if (inst.operands[1].isreg)
13337 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13338 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13342 NEON_ENCODE (SINGLE, inst);
13343 do_vfp_sp_monadic ();
13347 NEON_ENCODE (DOUBLE, inst);
13348 do_vfp_dp_rd_rm ();
13353 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13354 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13356 switch (inst.instruction & 0x0fffffff)
13359 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13362 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13370 NEON_ENCODE (SINGLE, inst);
13371 do_vfp_sp_compare_z ();
13375 NEON_ENCODE (DOUBLE, inst);
13379 do_vfp_cond_or_thumb ();
13383 nsyn_insert_sp (void)
13385 inst.operands[1] = inst.operands[0];
13386 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13387 inst.operands[0].reg = REG_SP;
13388 inst.operands[0].isreg = 1;
13389 inst.operands[0].writeback = 1;
13390 inst.operands[0].present = 1;
13394 do_vfp_nsyn_push (void)
13397 if (inst.operands[1].issingle)
13398 do_vfp_nsyn_opcode ("fstmdbs");
13400 do_vfp_nsyn_opcode ("fstmdbd");
13404 do_vfp_nsyn_pop (void)
13407 if (inst.operands[1].issingle)
13408 do_vfp_nsyn_opcode ("fldmias");
13410 do_vfp_nsyn_opcode ("fldmiad");
13413 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13414 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13417 neon_dp_fixup (struct arm_it* insn)
13419 unsigned int i = insn->instruction;
13424 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13435 insn->instruction = i;
13438 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13442 neon_logbits (unsigned x)
13444 return ffs (x) - 4;
13447 #define LOW4(R) ((R) & 0xf)
13448 #define HI1(R) (((R) >> 4) & 1)
13450 /* Encode insns with bit pattern:
13452 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13453 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13455 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13456 different meaning for some instruction. */
13459 neon_three_same (int isquad, int ubit, int size)
13461 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13462 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13463 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13464 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13465 inst.instruction |= LOW4 (inst.operands[2].reg);
13466 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13467 inst.instruction |= (isquad != 0) << 6;
13468 inst.instruction |= (ubit != 0) << 24;
13470 inst.instruction |= neon_logbits (size) << 20;
13472 neon_dp_fixup (&inst);
13475 /* Encode instructions of the form:
13477 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13478 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13480 Don't write size if SIZE == -1. */
13483 neon_two_same (int qbit, int ubit, int size)
13485 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13486 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13487 inst.instruction |= LOW4 (inst.operands[1].reg);
13488 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13489 inst.instruction |= (qbit != 0) << 6;
13490 inst.instruction |= (ubit != 0) << 24;
13493 inst.instruction |= neon_logbits (size) << 18;
13495 neon_dp_fixup (&inst);
13498 /* Neon instruction encoders, in approximate order of appearance. */
13501 do_neon_dyadic_i_su (void)
13503 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13504 struct neon_type_el et = neon_check_type (3, rs,
13505 N_EQK, N_EQK, N_SU_32 | N_KEY);
13506 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13510 do_neon_dyadic_i64_su (void)
13512 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13513 struct neon_type_el et = neon_check_type (3, rs,
13514 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13515 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13519 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13522 unsigned size = et.size >> 3;
13523 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13524 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13525 inst.instruction |= LOW4 (inst.operands[1].reg);
13526 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13527 inst.instruction |= (isquad != 0) << 6;
13528 inst.instruction |= immbits << 16;
13529 inst.instruction |= (size >> 3) << 7;
13530 inst.instruction |= (size & 0x7) << 19;
13532 inst.instruction |= (uval != 0) << 24;
13534 neon_dp_fixup (&inst);
13538 do_neon_shl_imm (void)
13540 if (!inst.operands[2].isreg)
13542 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13543 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13544 NEON_ENCODE (IMMED, inst);
13545 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13549 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13550 struct neon_type_el et = neon_check_type (3, rs,
13551 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13554 /* VSHL/VQSHL 3-register variants have syntax such as:
13556 whereas other 3-register operations encoded by neon_three_same have
13559 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13561 tmp = inst.operands[2].reg;
13562 inst.operands[2].reg = inst.operands[1].reg;
13563 inst.operands[1].reg = tmp;
13564 NEON_ENCODE (INTEGER, inst);
13565 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13570 do_neon_qshl_imm (void)
13572 if (!inst.operands[2].isreg)
13574 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13575 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13577 NEON_ENCODE (IMMED, inst);
13578 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13579 inst.operands[2].imm);
13583 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13584 struct neon_type_el et = neon_check_type (3, rs,
13585 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13588 /* See note in do_neon_shl_imm. */
13589 tmp = inst.operands[2].reg;
13590 inst.operands[2].reg = inst.operands[1].reg;
13591 inst.operands[1].reg = tmp;
13592 NEON_ENCODE (INTEGER, inst);
13593 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13598 do_neon_rshl (void)
13600 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13601 struct neon_type_el et = neon_check_type (3, rs,
13602 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13605 tmp = inst.operands[2].reg;
13606 inst.operands[2].reg = inst.operands[1].reg;
13607 inst.operands[1].reg = tmp;
13608 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13612 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13614 /* Handle .I8 pseudo-instructions. */
13617 /* Unfortunately, this will make everything apart from zero out-of-range.
13618 FIXME is this the intended semantics? There doesn't seem much point in
13619 accepting .I8 if so. */
13620 immediate |= immediate << 8;
13626 if (immediate == (immediate & 0x000000ff))
13628 *immbits = immediate;
13631 else if (immediate == (immediate & 0x0000ff00))
13633 *immbits = immediate >> 8;
13636 else if (immediate == (immediate & 0x00ff0000))
13638 *immbits = immediate >> 16;
13641 else if (immediate == (immediate & 0xff000000))
13643 *immbits = immediate >> 24;
13646 if ((immediate & 0xffff) != (immediate >> 16))
13647 goto bad_immediate;
13648 immediate &= 0xffff;
13651 if (immediate == (immediate & 0x000000ff))
13653 *immbits = immediate;
13656 else if (immediate == (immediate & 0x0000ff00))
13658 *immbits = immediate >> 8;
13663 first_error (_("immediate value out of range"));
13667 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13671 neon_bits_same_in_bytes (unsigned imm)
13673 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13674 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13675 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13676 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13679 /* For immediate of above form, return 0bABCD. */
13682 neon_squash_bits (unsigned imm)
13684 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13685 | ((imm & 0x01000000) >> 21);
13688 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13691 neon_qfloat_bits (unsigned imm)
13693 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13696 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13697 the instruction. *OP is passed as the initial value of the op field, and
13698 may be set to a different value depending on the constant (i.e.
13699 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13700 MVN). If the immediate looks like a repeated pattern then also
13701 try smaller element sizes. */
13704 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13705 unsigned *immbits, int *op, int size,
13706 enum neon_el_type type)
13708 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13710 if (type == NT_float && !float_p)
13713 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13715 if (size != 32 || *op == 1)
13717 *immbits = neon_qfloat_bits (immlo);
13723 if (neon_bits_same_in_bytes (immhi)
13724 && neon_bits_same_in_bytes (immlo))
13728 *immbits = (neon_squash_bits (immhi) << 4)
13729 | neon_squash_bits (immlo);
13734 if (immhi != immlo)
13740 if (immlo == (immlo & 0x000000ff))
13745 else if (immlo == (immlo & 0x0000ff00))
13747 *immbits = immlo >> 8;
13750 else if (immlo == (immlo & 0x00ff0000))
13752 *immbits = immlo >> 16;
13755 else if (immlo == (immlo & 0xff000000))
13757 *immbits = immlo >> 24;
13760 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13762 *immbits = (immlo >> 8) & 0xff;
13765 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13767 *immbits = (immlo >> 16) & 0xff;
13771 if ((immlo & 0xffff) != (immlo >> 16))
13778 if (immlo == (immlo & 0x000000ff))
13783 else if (immlo == (immlo & 0x0000ff00))
13785 *immbits = immlo >> 8;
13789 if ((immlo & 0xff) != (immlo >> 8))
13794 if (immlo == (immlo & 0x000000ff))
13796 /* Don't allow MVN with 8-bit immediate. */
13806 /* Write immediate bits [7:0] to the following locations:
13808 |28/24|23 19|18 16|15 4|3 0|
13809 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13811 This function is used by VMOV/VMVN/VORR/VBIC. */
13814 neon_write_immbits (unsigned immbits)
13816 inst.instruction |= immbits & 0xf;
13817 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13818 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13821 /* Invert low-order SIZE bits of XHI:XLO. */
13824 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13826 unsigned immlo = xlo ? *xlo : 0;
13827 unsigned immhi = xhi ? *xhi : 0;
13832 immlo = (~immlo) & 0xff;
13836 immlo = (~immlo) & 0xffff;
13840 immhi = (~immhi) & 0xffffffff;
13841 /* fall through. */
13844 immlo = (~immlo) & 0xffffffff;
13859 do_neon_logic (void)
13861 if (inst.operands[2].present && inst.operands[2].isreg)
13863 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13864 neon_check_type (3, rs, N_IGNORE_TYPE);
13865 /* U bit and size field were set as part of the bitmask. */
13866 NEON_ENCODE (INTEGER, inst);
13867 neon_three_same (neon_quad (rs), 0, -1);
13871 const int three_ops_form = (inst.operands[2].present
13872 && !inst.operands[2].isreg);
13873 const int immoperand = (three_ops_form ? 2 : 1);
13874 enum neon_shape rs = (three_ops_form
13875 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13876 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13877 struct neon_type_el et = neon_check_type (2, rs,
13878 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13879 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13883 if (et.type == NT_invtype)
13886 if (three_ops_form)
13887 constraint (inst.operands[0].reg != inst.operands[1].reg,
13888 _("first and second operands shall be the same register"));
13890 NEON_ENCODE (IMMED, inst);
13892 immbits = inst.operands[immoperand].imm;
13895 /* .i64 is a pseudo-op, so the immediate must be a repeating
13897 if (immbits != (inst.operands[immoperand].regisimm ?
13898 inst.operands[immoperand].reg : 0))
13900 /* Set immbits to an invalid constant. */
13901 immbits = 0xdeadbeef;
13908 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13912 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13916 /* Pseudo-instruction for VBIC. */
13917 neon_invert_size (&immbits, 0, et.size);
13918 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13922 /* Pseudo-instruction for VORR. */
13923 neon_invert_size (&immbits, 0, et.size);
13924 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13934 inst.instruction |= neon_quad (rs) << 6;
13935 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13936 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13937 inst.instruction |= cmode << 8;
13938 neon_write_immbits (immbits);
13940 neon_dp_fixup (&inst);
13945 do_neon_bitfield (void)
13947 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13948 neon_check_type (3, rs, N_IGNORE_TYPE);
13949 neon_three_same (neon_quad (rs), 0, -1);
13953 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13956 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13957 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13959 if (et.type == NT_float)
13961 NEON_ENCODE (FLOAT, inst);
13962 neon_three_same (neon_quad (rs), 0, -1);
13966 NEON_ENCODE (INTEGER, inst);
13967 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13972 do_neon_dyadic_if_su (void)
13974 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13978 do_neon_dyadic_if_su_d (void)
13980 /* This version only allow D registers, but that constraint is enforced during
13981 operand parsing so we don't need to do anything extra here. */
13982 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13986 do_neon_dyadic_if_i_d (void)
13988 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13989 affected if we specify unsigned args. */
13990 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13993 enum vfp_or_neon_is_neon_bits
13996 NEON_CHECK_ARCH = 2,
13997 NEON_CHECK_ARCH8 = 4
14000 /* Call this function if an instruction which may have belonged to the VFP or
14001 Neon instruction sets, but turned out to be a Neon instruction (due to the
14002 operand types involved, etc.). We have to check and/or fix-up a couple of
14005 - Make sure the user hasn't attempted to make a Neon instruction
14007 - Alter the value in the condition code field if necessary.
14008 - Make sure that the arch supports Neon instructions.
14010 Which of these operations take place depends on bits from enum
14011 vfp_or_neon_is_neon_bits.
14013 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14014 current instruction's condition is COND_ALWAYS, the condition field is
14015 changed to inst.uncond_value. This is necessary because instructions shared
14016 between VFP and Neon may be conditional for the VFP variants only, and the
14017 unconditional Neon version must have, e.g., 0xF in the condition field. */
14020 vfp_or_neon_is_neon (unsigned check)
14022 /* Conditions are always legal in Thumb mode (IT blocks). */
14023 if (!thumb_mode && (check & NEON_CHECK_CC))
14025 if (inst.cond != COND_ALWAYS)
14027 first_error (_(BAD_COND));
14030 if (inst.uncond_value != -1)
14031 inst.instruction |= inst.uncond_value << 28;
14034 if ((check & NEON_CHECK_ARCH)
14035 && !mark_feature_used (&fpu_neon_ext_v1))
14037 first_error (_(BAD_FPU));
14041 if ((check & NEON_CHECK_ARCH8)
14042 && !mark_feature_used (&fpu_neon_ext_armv8))
14044 first_error (_(BAD_FPU));
14052 do_neon_addsub_if_i (void)
14054 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14057 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14060 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14061 affected if we specify unsigned args. */
14062 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14065 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14067 V<op> A,B (A is operand 0, B is operand 2)
14072 so handle that case specially. */
14075 neon_exchange_operands (void)
14077 void *scratch = alloca (sizeof (inst.operands[0]));
14078 if (inst.operands[1].present)
14080 /* Swap operands[1] and operands[2]. */
14081 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14082 inst.operands[1] = inst.operands[2];
14083 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14087 inst.operands[1] = inst.operands[2];
14088 inst.operands[2] = inst.operands[0];
14093 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14095 if (inst.operands[2].isreg)
14098 neon_exchange_operands ();
14099 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14103 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14104 struct neon_type_el et = neon_check_type (2, rs,
14105 N_EQK | N_SIZ, immtypes | N_KEY);
14107 NEON_ENCODE (IMMED, inst);
14108 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14109 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14110 inst.instruction |= LOW4 (inst.operands[1].reg);
14111 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14112 inst.instruction |= neon_quad (rs) << 6;
14113 inst.instruction |= (et.type == NT_float) << 10;
14114 inst.instruction |= neon_logbits (et.size) << 18;
14116 neon_dp_fixup (&inst);
14123 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14127 do_neon_cmp_inv (void)
14129 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14135 neon_compare (N_IF_32, N_IF_32, FALSE);
14138 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14139 scalars, which are encoded in 5 bits, M : Rm.
14140 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14141 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14145 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14147 unsigned regno = NEON_SCALAR_REG (scalar);
14148 unsigned elno = NEON_SCALAR_INDEX (scalar);
14153 if (regno > 7 || elno > 3)
14155 return regno | (elno << 3);
14158 if (regno > 15 || elno > 1)
14160 return regno | (elno << 4);
14164 first_error (_("scalar out of range for multiply instruction"));
14170 /* Encode multiply / multiply-accumulate scalar instructions. */
14173 neon_mul_mac (struct neon_type_el et, int ubit)
14177 /* Give a more helpful error message if we have an invalid type. */
14178 if (et.type == NT_invtype)
14181 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14182 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14183 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14184 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14185 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14186 inst.instruction |= LOW4 (scalar);
14187 inst.instruction |= HI1 (scalar) << 5;
14188 inst.instruction |= (et.type == NT_float) << 8;
14189 inst.instruction |= neon_logbits (et.size) << 20;
14190 inst.instruction |= (ubit != 0) << 24;
14192 neon_dp_fixup (&inst);
14196 do_neon_mac_maybe_scalar (void)
14198 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14201 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14204 if (inst.operands[2].isscalar)
14206 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14207 struct neon_type_el et = neon_check_type (3, rs,
14208 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14209 NEON_ENCODE (SCALAR, inst);
14210 neon_mul_mac (et, neon_quad (rs));
14214 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14215 affected if we specify unsigned args. */
14216 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14221 do_neon_fmac (void)
14223 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14226 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14229 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14235 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14236 struct neon_type_el et = neon_check_type (3, rs,
14237 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14238 neon_three_same (neon_quad (rs), 0, et.size);
14241 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14242 same types as the MAC equivalents. The polynomial type for this instruction
14243 is encoded the same as the integer type. */
14248 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14251 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14254 if (inst.operands[2].isscalar)
14255 do_neon_mac_maybe_scalar ();
14257 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14261 do_neon_qdmulh (void)
14263 if (inst.operands[2].isscalar)
14265 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14266 struct neon_type_el et = neon_check_type (3, rs,
14267 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14268 NEON_ENCODE (SCALAR, inst);
14269 neon_mul_mac (et, neon_quad (rs));
14273 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14274 struct neon_type_el et = neon_check_type (3, rs,
14275 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14276 NEON_ENCODE (INTEGER, inst);
14277 /* The U bit (rounding) comes from bit mask. */
14278 neon_three_same (neon_quad (rs), 0, et.size);
14283 do_neon_fcmp_absolute (void)
14285 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14286 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14287 /* Size field comes from bit mask. */
14288 neon_three_same (neon_quad (rs), 1, -1);
14292 do_neon_fcmp_absolute_inv (void)
14294 neon_exchange_operands ();
14295 do_neon_fcmp_absolute ();
14299 do_neon_step (void)
14301 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14302 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14303 neon_three_same (neon_quad (rs), 0, -1);
14307 do_neon_abs_neg (void)
14309 enum neon_shape rs;
14310 struct neon_type_el et;
14312 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14315 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14318 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14319 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14321 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14322 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14323 inst.instruction |= LOW4 (inst.operands[1].reg);
14324 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14325 inst.instruction |= neon_quad (rs) << 6;
14326 inst.instruction |= (et.type == NT_float) << 10;
14327 inst.instruction |= neon_logbits (et.size) << 18;
14329 neon_dp_fixup (&inst);
14335 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14336 struct neon_type_el et = neon_check_type (2, rs,
14337 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14338 int imm = inst.operands[2].imm;
14339 constraint (imm < 0 || (unsigned)imm >= et.size,
14340 _("immediate out of range for insert"));
14341 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14347 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14348 struct neon_type_el et = neon_check_type (2, rs,
14349 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14350 int imm = inst.operands[2].imm;
14351 constraint (imm < 1 || (unsigned)imm > et.size,
14352 _("immediate out of range for insert"));
14353 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14357 do_neon_qshlu_imm (void)
14359 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14360 struct neon_type_el et = neon_check_type (2, rs,
14361 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14362 int imm = inst.operands[2].imm;
14363 constraint (imm < 0 || (unsigned)imm >= et.size,
14364 _("immediate out of range for shift"));
14365 /* Only encodes the 'U present' variant of the instruction.
14366 In this case, signed types have OP (bit 8) set to 0.
14367 Unsigned types have OP set to 1. */
14368 inst.instruction |= (et.type == NT_unsigned) << 8;
14369 /* The rest of the bits are the same as other immediate shifts. */
14370 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14374 do_neon_qmovn (void)
14376 struct neon_type_el et = neon_check_type (2, NS_DQ,
14377 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14378 /* Saturating move where operands can be signed or unsigned, and the
14379 destination has the same signedness. */
14380 NEON_ENCODE (INTEGER, inst);
14381 if (et.type == NT_unsigned)
14382 inst.instruction |= 0xc0;
14384 inst.instruction |= 0x80;
14385 neon_two_same (0, 1, et.size / 2);
14389 do_neon_qmovun (void)
14391 struct neon_type_el et = neon_check_type (2, NS_DQ,
14392 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14393 /* Saturating move with unsigned results. Operands must be signed. */
14394 NEON_ENCODE (INTEGER, inst);
14395 neon_two_same (0, 1, et.size / 2);
14399 do_neon_rshift_sat_narrow (void)
14401 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14402 or unsigned. If operands are unsigned, results must also be unsigned. */
14403 struct neon_type_el et = neon_check_type (2, NS_DQI,
14404 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14405 int imm = inst.operands[2].imm;
14406 /* This gets the bounds check, size encoding and immediate bits calculation
14410 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14411 VQMOVN.I<size> <Dd>, <Qm>. */
14414 inst.operands[2].present = 0;
14415 inst.instruction = N_MNEM_vqmovn;
14420 constraint (imm < 1 || (unsigned)imm > et.size,
14421 _("immediate out of range"));
14422 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14426 do_neon_rshift_sat_narrow_u (void)
14428 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14429 or unsigned. If operands are unsigned, results must also be unsigned. */
14430 struct neon_type_el et = neon_check_type (2, NS_DQI,
14431 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14432 int imm = inst.operands[2].imm;
14433 /* This gets the bounds check, size encoding and immediate bits calculation
14437 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14438 VQMOVUN.I<size> <Dd>, <Qm>. */
14441 inst.operands[2].present = 0;
14442 inst.instruction = N_MNEM_vqmovun;
14447 constraint (imm < 1 || (unsigned)imm > et.size,
14448 _("immediate out of range"));
14449 /* FIXME: The manual is kind of unclear about what value U should have in
14450 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14452 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14456 do_neon_movn (void)
14458 struct neon_type_el et = neon_check_type (2, NS_DQ,
14459 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14460 NEON_ENCODE (INTEGER, inst);
14461 neon_two_same (0, 1, et.size / 2);
14465 do_neon_rshift_narrow (void)
14467 struct neon_type_el et = neon_check_type (2, NS_DQI,
14468 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14469 int imm = inst.operands[2].imm;
14470 /* This gets the bounds check, size encoding and immediate bits calculation
14474 /* If immediate is zero then we are a pseudo-instruction for
14475 VMOVN.I<size> <Dd>, <Qm> */
14478 inst.operands[2].present = 0;
14479 inst.instruction = N_MNEM_vmovn;
14484 constraint (imm < 1 || (unsigned)imm > et.size,
14485 _("immediate out of range for narrowing operation"));
14486 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14490 do_neon_shll (void)
14492 /* FIXME: Type checking when lengthening. */
14493 struct neon_type_el et = neon_check_type (2, NS_QDI,
14494 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14495 unsigned imm = inst.operands[2].imm;
14497 if (imm == et.size)
14499 /* Maximum shift variant. */
14500 NEON_ENCODE (INTEGER, inst);
14501 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14502 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14503 inst.instruction |= LOW4 (inst.operands[1].reg);
14504 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14505 inst.instruction |= neon_logbits (et.size) << 18;
14507 neon_dp_fixup (&inst);
14511 /* A more-specific type check for non-max versions. */
14512 et = neon_check_type (2, NS_QDI,
14513 N_EQK | N_DBL, N_SU_32 | N_KEY);
14514 NEON_ENCODE (IMMED, inst);
14515 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14519 /* Check the various types for the VCVT instruction, and return which version
14520 the current instruction is. */
14522 #define CVT_FLAVOUR_VAR \
14523 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14524 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14525 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14526 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14527 /* Half-precision conversions. */ \
14528 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14529 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14530 /* VFP instructions. */ \
14531 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14532 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14533 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14534 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14535 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14536 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14537 /* VFP instructions with bitshift. */ \
14538 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14539 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14540 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14541 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14542 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14543 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14544 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14545 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14547 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14548 neon_cvt_flavour_##C,
14550 /* The different types of conversions we can do. */
14551 enum neon_cvt_flavour
14554 neon_cvt_flavour_invalid,
14555 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14560 static enum neon_cvt_flavour
14561 get_neon_cvt_flavour (enum neon_shape rs)
14563 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14564 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14565 if (et.type != NT_invtype) \
14567 inst.error = NULL; \
14568 return (neon_cvt_flavour_##C); \
14571 struct neon_type_el et;
14572 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14573 || rs == NS_FF) ? N_VFP : 0;
14574 /* The instruction versions which take an immediate take one register
14575 argument, which is extended to the width of the full register. Thus the
14576 "source" and "destination" registers must have the same width. Hack that
14577 here by making the size equal to the key (wider, in this case) operand. */
14578 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14582 return neon_cvt_flavour_invalid;
14597 /* Neon-syntax VFP conversions. */
14600 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
14602 const char *opname = 0;
14604 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14606 /* Conversions with immediate bitshift. */
14607 const char *enc[] =
14609 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14615 if (flavour < (int) ARRAY_SIZE (enc))
14617 opname = enc[flavour];
14618 constraint (inst.operands[0].reg != inst.operands[1].reg,
14619 _("operands 0 and 1 must be the same register"));
14620 inst.operands[1] = inst.operands[2];
14621 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14626 /* Conversions without bitshift. */
14627 const char *enc[] =
14629 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14635 if (flavour < (int) ARRAY_SIZE (enc))
14636 opname = enc[flavour];
14640 do_vfp_nsyn_opcode (opname);
14644 do_vfp_nsyn_cvtz (void)
14646 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14647 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14648 const char *enc[] =
14650 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14656 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14657 do_vfp_nsyn_opcode (enc[flavour]);
14661 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
14662 enum neon_cvt_mode mode)
14667 set_it_insn_type (OUTSIDE_IT_INSN);
14671 case neon_cvt_flavour_s32_f64:
14675 case neon_cvt_flavour_s32_f32:
14679 case neon_cvt_flavour_u32_f64:
14683 case neon_cvt_flavour_u32_f32:
14688 first_error (_("invalid instruction shape"));
14694 case neon_cvt_mode_a: rm = 0; break;
14695 case neon_cvt_mode_n: rm = 1; break;
14696 case neon_cvt_mode_p: rm = 2; break;
14697 case neon_cvt_mode_m: rm = 3; break;
14698 default: first_error (_("invalid rounding mode")); return;
14701 NEON_ENCODE (FPV8, inst);
14702 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14703 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
14704 inst.instruction |= sz << 8;
14705 inst.instruction |= op << 7;
14706 inst.instruction |= rm << 16;
14707 inst.instruction |= 0xf0000000;
14708 inst.is_neon = TRUE;
14712 do_neon_cvt_1 (enum neon_cvt_mode mode)
14714 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14715 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14716 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14718 /* PR11109: Handle round-to-zero for VCVT conversions. */
14719 if (mode == neon_cvt_mode_z
14720 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14721 && (flavour == neon_cvt_flavour_s32_f32
14722 || flavour == neon_cvt_flavour_u32_f32
14723 || flavour == neon_cvt_flavour_s32_f64
14724 || flavour == neon_cvt_flavour_u32_f64)
14725 && (rs == NS_FD || rs == NS_FF))
14727 do_vfp_nsyn_cvtz ();
14731 /* VFP rather than Neon conversions. */
14732 if (flavour >= neon_cvt_flavour_first_fp)
14734 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14735 do_vfp_nsyn_cvt (rs, flavour);
14737 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14748 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14750 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14753 /* Fixed-point conversion with #0 immediate is encoded as an
14754 integer conversion. */
14755 if (inst.operands[2].present && inst.operands[2].imm == 0)
14757 immbits = 32 - inst.operands[2].imm;
14758 NEON_ENCODE (IMMED, inst);
14759 if (flavour != neon_cvt_flavour_invalid)
14760 inst.instruction |= enctab[flavour];
14761 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14762 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14763 inst.instruction |= LOW4 (inst.operands[1].reg);
14764 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14765 inst.instruction |= neon_quad (rs) << 6;
14766 inst.instruction |= 1 << 21;
14767 inst.instruction |= immbits << 16;
14769 neon_dp_fixup (&inst);
14775 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
14777 NEON_ENCODE (FLOAT, inst);
14778 set_it_insn_type (OUTSIDE_IT_INSN);
14780 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
14783 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14784 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14785 inst.instruction |= LOW4 (inst.operands[1].reg);
14786 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14787 inst.instruction |= neon_quad (rs) << 6;
14788 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
14789 inst.instruction |= mode << 8;
14791 inst.instruction |= 0xfc000000;
14793 inst.instruction |= 0xf0000000;
14799 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14801 NEON_ENCODE (INTEGER, inst);
14803 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14806 if (flavour != neon_cvt_flavour_invalid)
14807 inst.instruction |= enctab[flavour];
14809 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14810 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14811 inst.instruction |= LOW4 (inst.operands[1].reg);
14812 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14813 inst.instruction |= neon_quad (rs) << 6;
14814 inst.instruction |= 2 << 18;
14816 neon_dp_fixup (&inst);
14821 /* Half-precision conversions for Advanced SIMD -- neon. */
14826 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14828 as_bad (_("operand size must match register width"));
14833 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14835 as_bad (_("operand size must match register width"));
14840 inst.instruction = 0x3b60600;
14842 inst.instruction = 0x3b60700;
14844 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14845 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14846 inst.instruction |= LOW4 (inst.operands[1].reg);
14847 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14848 neon_dp_fixup (&inst);
14852 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14853 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14854 do_vfp_nsyn_cvt (rs, flavour);
14856 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14861 do_neon_cvtr (void)
14863 do_neon_cvt_1 (neon_cvt_mode_x);
14869 do_neon_cvt_1 (neon_cvt_mode_z);
14873 do_neon_cvta (void)
14875 do_neon_cvt_1 (neon_cvt_mode_a);
14879 do_neon_cvtn (void)
14881 do_neon_cvt_1 (neon_cvt_mode_n);
14885 do_neon_cvtp (void)
14887 do_neon_cvt_1 (neon_cvt_mode_p);
14891 do_neon_cvtm (void)
14893 do_neon_cvt_1 (neon_cvt_mode_m);
14897 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
14900 mark_feature_used (&fpu_vfp_ext_armv8);
14902 encode_arm_vfp_reg (inst.operands[0].reg,
14903 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
14904 encode_arm_vfp_reg (inst.operands[1].reg,
14905 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
14906 inst.instruction |= to ? 0x10000 : 0;
14907 inst.instruction |= t ? 0x80 : 0;
14908 inst.instruction |= is_double ? 0x100 : 0;
14909 do_vfp_cond_or_thumb ();
14913 do_neon_cvttb_1 (bfd_boolean t)
14915 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
14919 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
14922 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
14924 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
14927 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
14929 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
14932 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
14934 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
14937 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
14944 do_neon_cvtb (void)
14946 do_neon_cvttb_1 (FALSE);
14951 do_neon_cvtt (void)
14953 do_neon_cvttb_1 (TRUE);
14957 neon_move_immediate (void)
14959 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14960 struct neon_type_el et = neon_check_type (2, rs,
14961 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14962 unsigned immlo, immhi = 0, immbits;
14963 int op, cmode, float_p;
14965 constraint (et.type == NT_invtype,
14966 _("operand size must be specified for immediate VMOV"));
14968 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14969 op = (inst.instruction & (1 << 5)) != 0;
14971 immlo = inst.operands[1].imm;
14972 if (inst.operands[1].regisimm)
14973 immhi = inst.operands[1].reg;
14975 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14976 _("immediate has bits set outside the operand size"));
14978 float_p = inst.operands[1].immisfloat;
14980 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14981 et.size, et.type)) == FAIL)
14983 /* Invert relevant bits only. */
14984 neon_invert_size (&immlo, &immhi, et.size);
14985 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14986 with one or the other; those cases are caught by
14987 neon_cmode_for_move_imm. */
14989 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14990 &op, et.size, et.type)) == FAIL)
14992 first_error (_("immediate out of range"));
14997 inst.instruction &= ~(1 << 5);
14998 inst.instruction |= op << 5;
15000 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15001 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15002 inst.instruction |= neon_quad (rs) << 6;
15003 inst.instruction |= cmode << 8;
15005 neon_write_immbits (immbits);
15011 if (inst.operands[1].isreg)
15013 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15015 NEON_ENCODE (INTEGER, inst);
15016 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15017 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15018 inst.instruction |= LOW4 (inst.operands[1].reg);
15019 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15020 inst.instruction |= neon_quad (rs) << 6;
15024 NEON_ENCODE (IMMED, inst);
15025 neon_move_immediate ();
15028 neon_dp_fixup (&inst);
15031 /* Encode instructions of form:
15033 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15034 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15037 neon_mixed_length (struct neon_type_el et, unsigned size)
15039 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15040 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15041 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15042 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15043 inst.instruction |= LOW4 (inst.operands[2].reg);
15044 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15045 inst.instruction |= (et.type == NT_unsigned) << 24;
15046 inst.instruction |= neon_logbits (size) << 20;
15048 neon_dp_fixup (&inst);
15052 do_neon_dyadic_long (void)
15054 /* FIXME: Type checking for lengthening op. */
15055 struct neon_type_el et = neon_check_type (3, NS_QDD,
15056 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15057 neon_mixed_length (et, et.size);
15061 do_neon_abal (void)
15063 struct neon_type_el et = neon_check_type (3, NS_QDD,
15064 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15065 neon_mixed_length (et, et.size);
15069 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15071 if (inst.operands[2].isscalar)
15073 struct neon_type_el et = neon_check_type (3, NS_QDS,
15074 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
15075 NEON_ENCODE (SCALAR, inst);
15076 neon_mul_mac (et, et.type == NT_unsigned);
15080 struct neon_type_el et = neon_check_type (3, NS_QDD,
15081 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
15082 NEON_ENCODE (INTEGER, inst);
15083 neon_mixed_length (et, et.size);
15088 do_neon_mac_maybe_scalar_long (void)
15090 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15094 do_neon_dyadic_wide (void)
15096 struct neon_type_el et = neon_check_type (3, NS_QQD,
15097 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15098 neon_mixed_length (et, et.size);
15102 do_neon_dyadic_narrow (void)
15104 struct neon_type_el et = neon_check_type (3, NS_QDD,
15105 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
15106 /* Operand sign is unimportant, and the U bit is part of the opcode,
15107 so force the operand type to integer. */
15108 et.type = NT_integer;
15109 neon_mixed_length (et, et.size / 2);
15113 do_neon_mul_sat_scalar_long (void)
15115 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15119 do_neon_vmull (void)
15121 if (inst.operands[2].isscalar)
15122 do_neon_mac_maybe_scalar_long ();
15125 struct neon_type_el et = neon_check_type (3, NS_QDD,
15126 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
15128 if (et.type == NT_poly)
15129 NEON_ENCODE (POLY, inst);
15131 NEON_ENCODE (INTEGER, inst);
15133 /* For polynomial encoding the U bit must be zero, and the size must
15134 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15135 obviously, as 0b10). */
15138 /* Check we're on the correct architecture. */
15139 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15141 _("Instruction form not available on this architecture.");
15146 neon_mixed_length (et, et.size);
15153 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
15154 struct neon_type_el et = neon_check_type (3, rs,
15155 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15156 unsigned imm = (inst.operands[3].imm * et.size) / 8;
15158 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15159 _("shift out of range"));
15160 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15161 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15162 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15163 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15164 inst.instruction |= LOW4 (inst.operands[2].reg);
15165 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15166 inst.instruction |= neon_quad (rs) << 6;
15167 inst.instruction |= imm << 8;
15169 neon_dp_fixup (&inst);
15175 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15176 struct neon_type_el et = neon_check_type (2, rs,
15177 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15178 unsigned op = (inst.instruction >> 7) & 3;
15179 /* N (width of reversed regions) is encoded as part of the bitmask. We
15180 extract it here to check the elements to be reversed are smaller.
15181 Otherwise we'd get a reserved instruction. */
15182 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15183 gas_assert (elsize != 0);
15184 constraint (et.size >= elsize,
15185 _("elements must be smaller than reversal region"));
15186 neon_two_same (neon_quad (rs), 1, et.size);
15192 if (inst.operands[1].isscalar)
15194 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15195 struct neon_type_el et = neon_check_type (2, rs,
15196 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15197 unsigned sizebits = et.size >> 3;
15198 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15199 int logsize = neon_logbits (et.size);
15200 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15202 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15205 NEON_ENCODE (SCALAR, inst);
15206 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15207 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15208 inst.instruction |= LOW4 (dm);
15209 inst.instruction |= HI1 (dm) << 5;
15210 inst.instruction |= neon_quad (rs) << 6;
15211 inst.instruction |= x << 17;
15212 inst.instruction |= sizebits << 16;
15214 neon_dp_fixup (&inst);
15218 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15219 struct neon_type_el et = neon_check_type (2, rs,
15220 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15221 /* Duplicate ARM register to lanes of vector. */
15222 NEON_ENCODE (ARMREG, inst);
15225 case 8: inst.instruction |= 0x400000; break;
15226 case 16: inst.instruction |= 0x000020; break;
15227 case 32: inst.instruction |= 0x000000; break;
15230 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15231 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15232 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15233 inst.instruction |= neon_quad (rs) << 21;
15234 /* The encoding for this instruction is identical for the ARM and Thumb
15235 variants, except for the condition field. */
15236 do_vfp_cond_or_thumb ();
15240 /* VMOV has particularly many variations. It can be one of:
15241 0. VMOV<c><q> <Qd>, <Qm>
15242 1. VMOV<c><q> <Dd>, <Dm>
15243 (Register operations, which are VORR with Rm = Rn.)
15244 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15245 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15247 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15248 (ARM register to scalar.)
15249 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15250 (Two ARM registers to vector.)
15251 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15252 (Scalar to ARM register.)
15253 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15254 (Vector to two ARM registers.)
15255 8. VMOV.F32 <Sd>, <Sm>
15256 9. VMOV.F64 <Dd>, <Dm>
15257 (VFP register moves.)
15258 10. VMOV.F32 <Sd>, #imm
15259 11. VMOV.F64 <Dd>, #imm
15260 (VFP float immediate load.)
15261 12. VMOV <Rd>, <Sm>
15262 (VFP single to ARM reg.)
15263 13. VMOV <Sd>, <Rm>
15264 (ARM reg to VFP single.)
15265 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15266 (Two ARM regs to two VFP singles.)
15267 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15268 (Two VFP singles to two ARM regs.)
15270 These cases can be disambiguated using neon_select_shape, except cases 1/9
15271 and 3/11 which depend on the operand type too.
15273 All the encoded bits are hardcoded by this function.
15275 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15276 Cases 5, 7 may be used with VFPv2 and above.
15278 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15279 can specify a type where it doesn't make sense to, and is ignored). */
15284 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15285 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15287 struct neon_type_el et;
15288 const char *ldconst = 0;
15292 case NS_DD: /* case 1/9. */
15293 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15294 /* It is not an error here if no type is given. */
15296 if (et.type == NT_float && et.size == 64)
15298 do_vfp_nsyn_opcode ("fcpyd");
15301 /* fall through. */
15303 case NS_QQ: /* case 0/1. */
15305 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15307 /* The architecture manual I have doesn't explicitly state which
15308 value the U bit should have for register->register moves, but
15309 the equivalent VORR instruction has U = 0, so do that. */
15310 inst.instruction = 0x0200110;
15311 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15312 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15313 inst.instruction |= LOW4 (inst.operands[1].reg);
15314 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15315 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15316 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15317 inst.instruction |= neon_quad (rs) << 6;
15319 neon_dp_fixup (&inst);
15323 case NS_DI: /* case 3/11. */
15324 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15326 if (et.type == NT_float && et.size == 64)
15328 /* case 11 (fconstd). */
15329 ldconst = "fconstd";
15330 goto encode_fconstd;
15332 /* fall through. */
15334 case NS_QI: /* case 2/3. */
15335 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15337 inst.instruction = 0x0800010;
15338 neon_move_immediate ();
15339 neon_dp_fixup (&inst);
15342 case NS_SR: /* case 4. */
15344 unsigned bcdebits = 0;
15346 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15347 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15349 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15350 logsize = neon_logbits (et.size);
15352 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15354 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15355 && et.size != 32, _(BAD_FPU));
15356 constraint (et.type == NT_invtype, _("bad type for scalar"));
15357 constraint (x >= 64 / et.size, _("scalar index out of range"));
15361 case 8: bcdebits = 0x8; break;
15362 case 16: bcdebits = 0x1; break;
15363 case 32: bcdebits = 0x0; break;
15367 bcdebits |= x << logsize;
15369 inst.instruction = 0xe000b10;
15370 do_vfp_cond_or_thumb ();
15371 inst.instruction |= LOW4 (dn) << 16;
15372 inst.instruction |= HI1 (dn) << 7;
15373 inst.instruction |= inst.operands[1].reg << 12;
15374 inst.instruction |= (bcdebits & 3) << 5;
15375 inst.instruction |= (bcdebits >> 2) << 21;
15379 case NS_DRR: /* case 5 (fmdrr). */
15380 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15383 inst.instruction = 0xc400b10;
15384 do_vfp_cond_or_thumb ();
15385 inst.instruction |= LOW4 (inst.operands[0].reg);
15386 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15387 inst.instruction |= inst.operands[1].reg << 12;
15388 inst.instruction |= inst.operands[2].reg << 16;
15391 case NS_RS: /* case 6. */
15394 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15395 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15396 unsigned abcdebits = 0;
15398 et = neon_check_type (2, NS_NULL,
15399 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15400 logsize = neon_logbits (et.size);
15402 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15404 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15405 && et.size != 32, _(BAD_FPU));
15406 constraint (et.type == NT_invtype, _("bad type for scalar"));
15407 constraint (x >= 64 / et.size, _("scalar index out of range"));
15411 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15412 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15413 case 32: abcdebits = 0x00; break;
15417 abcdebits |= x << logsize;
15418 inst.instruction = 0xe100b10;
15419 do_vfp_cond_or_thumb ();
15420 inst.instruction |= LOW4 (dn) << 16;
15421 inst.instruction |= HI1 (dn) << 7;
15422 inst.instruction |= inst.operands[0].reg << 12;
15423 inst.instruction |= (abcdebits & 3) << 5;
15424 inst.instruction |= (abcdebits >> 2) << 21;
15428 case NS_RRD: /* case 7 (fmrrd). */
15429 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15432 inst.instruction = 0xc500b10;
15433 do_vfp_cond_or_thumb ();
15434 inst.instruction |= inst.operands[0].reg << 12;
15435 inst.instruction |= inst.operands[1].reg << 16;
15436 inst.instruction |= LOW4 (inst.operands[2].reg);
15437 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15440 case NS_FF: /* case 8 (fcpys). */
15441 do_vfp_nsyn_opcode ("fcpys");
15444 case NS_FI: /* case 10 (fconsts). */
15445 ldconst = "fconsts";
15447 if (is_quarter_float (inst.operands[1].imm))
15449 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15450 do_vfp_nsyn_opcode (ldconst);
15453 first_error (_("immediate out of range"));
15456 case NS_RF: /* case 12 (fmrs). */
15457 do_vfp_nsyn_opcode ("fmrs");
15460 case NS_FR: /* case 13 (fmsr). */
15461 do_vfp_nsyn_opcode ("fmsr");
15464 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15465 (one of which is a list), but we have parsed four. Do some fiddling to
15466 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15468 case NS_RRFF: /* case 14 (fmrrs). */
15469 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15470 _("VFP registers must be adjacent"));
15471 inst.operands[2].imm = 2;
15472 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15473 do_vfp_nsyn_opcode ("fmrrs");
15476 case NS_FFRR: /* case 15 (fmsrr). */
15477 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15478 _("VFP registers must be adjacent"));
15479 inst.operands[1] = inst.operands[2];
15480 inst.operands[2] = inst.operands[3];
15481 inst.operands[0].imm = 2;
15482 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15483 do_vfp_nsyn_opcode ("fmsrr");
15492 do_neon_rshift_round_imm (void)
15494 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15495 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15496 int imm = inst.operands[2].imm;
15498 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15501 inst.operands[2].present = 0;
15506 constraint (imm < 1 || (unsigned)imm > et.size,
15507 _("immediate out of range for shift"));
15508 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15513 do_neon_movl (void)
15515 struct neon_type_el et = neon_check_type (2, NS_QD,
15516 N_EQK | N_DBL, N_SU_32 | N_KEY);
15517 unsigned sizebits = et.size >> 3;
15518 inst.instruction |= sizebits << 19;
15519 neon_two_same (0, et.type == NT_unsigned, -1);
15525 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15526 struct neon_type_el et = neon_check_type (2, rs,
15527 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15528 NEON_ENCODE (INTEGER, inst);
15529 neon_two_same (neon_quad (rs), 1, et.size);
15533 do_neon_zip_uzp (void)
15535 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15536 struct neon_type_el et = neon_check_type (2, rs,
15537 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15538 if (rs == NS_DD && et.size == 32)
15540 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15541 inst.instruction = N_MNEM_vtrn;
15545 neon_two_same (neon_quad (rs), 1, et.size);
15549 do_neon_sat_abs_neg (void)
15551 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15552 struct neon_type_el et = neon_check_type (2, rs,
15553 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15554 neon_two_same (neon_quad (rs), 1, et.size);
15558 do_neon_pair_long (void)
15560 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15561 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15562 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15563 inst.instruction |= (et.type == NT_unsigned) << 7;
15564 neon_two_same (neon_quad (rs), 1, et.size);
15568 do_neon_recip_est (void)
15570 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15571 struct neon_type_el et = neon_check_type (2, rs,
15572 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15573 inst.instruction |= (et.type == NT_float) << 8;
15574 neon_two_same (neon_quad (rs), 1, et.size);
15580 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15581 struct neon_type_el et = neon_check_type (2, rs,
15582 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15583 neon_two_same (neon_quad (rs), 1, et.size);
15589 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15590 struct neon_type_el et = neon_check_type (2, rs,
15591 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15592 neon_two_same (neon_quad (rs), 1, et.size);
15598 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15599 struct neon_type_el et = neon_check_type (2, rs,
15600 N_EQK | N_INT, N_8 | N_KEY);
15601 neon_two_same (neon_quad (rs), 1, et.size);
15607 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15608 neon_two_same (neon_quad (rs), 1, -1);
15612 do_neon_tbl_tbx (void)
15614 unsigned listlenbits;
15615 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15617 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15619 first_error (_("bad list length for table lookup"));
15623 listlenbits = inst.operands[1].imm - 1;
15624 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15625 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15626 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15627 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15628 inst.instruction |= LOW4 (inst.operands[2].reg);
15629 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15630 inst.instruction |= listlenbits << 8;
15632 neon_dp_fixup (&inst);
15636 do_neon_ldm_stm (void)
15638 /* P, U and L bits are part of bitmask. */
15639 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15640 unsigned offsetbits = inst.operands[1].imm * 2;
15642 if (inst.operands[1].issingle)
15644 do_vfp_nsyn_ldm_stm (is_dbmode);
15648 constraint (is_dbmode && !inst.operands[0].writeback,
15649 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15651 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15652 _("register list must contain at least 1 and at most 16 "
15655 inst.instruction |= inst.operands[0].reg << 16;
15656 inst.instruction |= inst.operands[0].writeback << 21;
15657 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15658 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15660 inst.instruction |= offsetbits;
15662 do_vfp_cond_or_thumb ();
15666 do_neon_ldr_str (void)
15668 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15670 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15671 And is UNPREDICTABLE in thumb mode. */
15673 && inst.operands[1].reg == REG_PC
15674 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15676 if (!thumb_mode && warn_on_deprecated)
15677 as_warn (_("Use of PC here is deprecated"));
15679 inst.error = _("Use of PC here is UNPREDICTABLE");
15682 if (inst.operands[0].issingle)
15685 do_vfp_nsyn_opcode ("flds");
15687 do_vfp_nsyn_opcode ("fsts");
15692 do_vfp_nsyn_opcode ("fldd");
15694 do_vfp_nsyn_opcode ("fstd");
15698 /* "interleave" version also handles non-interleaving register VLD1/VST1
15702 do_neon_ld_st_interleave (void)
15704 struct neon_type_el et = neon_check_type (1, NS_NULL,
15705 N_8 | N_16 | N_32 | N_64);
15706 unsigned alignbits = 0;
15708 /* The bits in this table go:
15709 0: register stride of one (0) or two (1)
15710 1,2: register list length, minus one (1, 2, 3, 4).
15711 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15712 We use -1 for invalid entries. */
15713 const int typetable[] =
15715 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15716 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15717 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15718 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15722 if (et.type == NT_invtype)
15725 if (inst.operands[1].immisalign)
15726 switch (inst.operands[1].imm >> 8)
15728 case 64: alignbits = 1; break;
15730 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15731 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15732 goto bad_alignment;
15736 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15737 goto bad_alignment;
15742 first_error (_("bad alignment"));
15746 inst.instruction |= alignbits << 4;
15747 inst.instruction |= neon_logbits (et.size) << 6;
15749 /* Bits [4:6] of the immediate in a list specifier encode register stride
15750 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15751 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15752 up the right value for "type" in a table based on this value and the given
15753 list style, then stick it back. */
15754 idx = ((inst.operands[0].imm >> 4) & 7)
15755 | (((inst.instruction >> 8) & 3) << 3);
15757 typebits = typetable[idx];
15759 constraint (typebits == -1, _("bad list type for instruction"));
15761 inst.instruction &= ~0xf00;
15762 inst.instruction |= typebits << 8;
15765 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15766 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15767 otherwise. The variable arguments are a list of pairs of legal (size, align)
15768 values, terminated with -1. */
15771 neon_alignment_bit (int size, int align, int *do_align, ...)
15774 int result = FAIL, thissize, thisalign;
15776 if (!inst.operands[1].immisalign)
15782 va_start (ap, do_align);
15786 thissize = va_arg (ap, int);
15787 if (thissize == -1)
15789 thisalign = va_arg (ap, int);
15791 if (size == thissize && align == thisalign)
15794 while (result != SUCCESS);
15798 if (result == SUCCESS)
15801 first_error (_("unsupported alignment for instruction"));
15807 do_neon_ld_st_lane (void)
15809 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15810 int align_good, do_align = 0;
15811 int logsize = neon_logbits (et.size);
15812 int align = inst.operands[1].imm >> 8;
15813 int n = (inst.instruction >> 8) & 3;
15814 int max_el = 64 / et.size;
15816 if (et.type == NT_invtype)
15819 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15820 _("bad list length"));
15821 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15822 _("scalar index out of range"));
15823 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15825 _("stride of 2 unavailable when element size is 8"));
15829 case 0: /* VLD1 / VST1. */
15830 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15832 if (align_good == FAIL)
15836 unsigned alignbits = 0;
15839 case 16: alignbits = 0x1; break;
15840 case 32: alignbits = 0x3; break;
15843 inst.instruction |= alignbits << 4;
15847 case 1: /* VLD2 / VST2. */
15848 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15850 if (align_good == FAIL)
15853 inst.instruction |= 1 << 4;
15856 case 2: /* VLD3 / VST3. */
15857 constraint (inst.operands[1].immisalign,
15858 _("can't use alignment with this instruction"));
15861 case 3: /* VLD4 / VST4. */
15862 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15863 16, 64, 32, 64, 32, 128, -1);
15864 if (align_good == FAIL)
15868 unsigned alignbits = 0;
15871 case 8: alignbits = 0x1; break;
15872 case 16: alignbits = 0x1; break;
15873 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15876 inst.instruction |= alignbits << 4;
15883 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15884 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15885 inst.instruction |= 1 << (4 + logsize);
15887 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15888 inst.instruction |= logsize << 10;
15891 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15894 do_neon_ld_dup (void)
15896 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15897 int align_good, do_align = 0;
15899 if (et.type == NT_invtype)
15902 switch ((inst.instruction >> 8) & 3)
15904 case 0: /* VLD1. */
15905 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15906 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15907 &do_align, 16, 16, 32, 32, -1);
15908 if (align_good == FAIL)
15910 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15913 case 2: inst.instruction |= 1 << 5; break;
15914 default: first_error (_("bad list length")); return;
15916 inst.instruction |= neon_logbits (et.size) << 6;
15919 case 1: /* VLD2. */
15920 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15921 &do_align, 8, 16, 16, 32, 32, 64, -1);
15922 if (align_good == FAIL)
15924 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15925 _("bad list length"));
15926 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15927 inst.instruction |= 1 << 5;
15928 inst.instruction |= neon_logbits (et.size) << 6;
15931 case 2: /* VLD3. */
15932 constraint (inst.operands[1].immisalign,
15933 _("can't use alignment with this instruction"));
15934 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15935 _("bad list length"));
15936 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15937 inst.instruction |= 1 << 5;
15938 inst.instruction |= neon_logbits (et.size) << 6;
15941 case 3: /* VLD4. */
15943 int align = inst.operands[1].imm >> 8;
15944 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15945 16, 64, 32, 64, 32, 128, -1);
15946 if (align_good == FAIL)
15948 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15949 _("bad list length"));
15950 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15951 inst.instruction |= 1 << 5;
15952 if (et.size == 32 && align == 128)
15953 inst.instruction |= 0x3 << 6;
15955 inst.instruction |= neon_logbits (et.size) << 6;
15962 inst.instruction |= do_align << 4;
15965 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15966 apart from bits [11:4]. */
15969 do_neon_ldx_stx (void)
15971 if (inst.operands[1].isreg)
15972 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15974 switch (NEON_LANE (inst.operands[0].imm))
15976 case NEON_INTERLEAVE_LANES:
15977 NEON_ENCODE (INTERLV, inst);
15978 do_neon_ld_st_interleave ();
15981 case NEON_ALL_LANES:
15982 NEON_ENCODE (DUP, inst);
15987 NEON_ENCODE (LANE, inst);
15988 do_neon_ld_st_lane ();
15991 /* L bit comes from bit mask. */
15992 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15993 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15994 inst.instruction |= inst.operands[1].reg << 16;
15996 if (inst.operands[1].postind)
15998 int postreg = inst.operands[1].imm & 0xf;
15999 constraint (!inst.operands[1].immisreg,
16000 _("post-index must be a register"));
16001 constraint (postreg == 0xd || postreg == 0xf,
16002 _("bad register for post-index"));
16003 inst.instruction |= postreg;
16005 else if (inst.operands[1].writeback)
16007 inst.instruction |= 0xd;
16010 inst.instruction |= 0xf;
16013 inst.instruction |= 0xf9000000;
16015 inst.instruction |= 0xf4000000;
16020 do_vfp_nsyn_fpv8 (enum neon_shape rs)
16022 NEON_ENCODE (FPV8, inst);
16025 do_vfp_sp_dyadic ();
16027 do_vfp_dp_rd_rn_rm ();
16030 inst.instruction |= 0x100;
16032 inst.instruction |= 0xf0000000;
16038 set_it_insn_type (OUTSIDE_IT_INSN);
16040 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16041 first_error (_("invalid instruction shape"));
16047 set_it_insn_type (OUTSIDE_IT_INSN);
16049 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16052 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16055 neon_dyadic_misc (NT_untyped, N_F32, 0);
16059 do_vrint_1 (enum neon_cvt_mode mode)
16061 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16062 struct neon_type_el et;
16067 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16068 if (et.type != NT_invtype)
16070 /* VFP encodings. */
16071 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16072 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16073 set_it_insn_type (OUTSIDE_IT_INSN);
16075 NEON_ENCODE (FPV8, inst);
16077 do_vfp_sp_monadic ();
16079 do_vfp_dp_rd_rm ();
16083 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16084 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16085 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16086 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16087 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16088 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16089 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16093 inst.instruction |= (rs == NS_DD) << 8;
16094 do_vfp_cond_or_thumb ();
16098 /* Neon encodings (or something broken...). */
16100 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16102 if (et.type == NT_invtype)
16105 set_it_insn_type (OUTSIDE_IT_INSN);
16106 NEON_ENCODE (FLOAT, inst);
16108 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16111 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16112 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16113 inst.instruction |= LOW4 (inst.operands[1].reg);
16114 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16115 inst.instruction |= neon_quad (rs) << 6;
16118 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16119 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16120 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16121 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16122 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16123 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16124 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16129 inst.instruction |= 0xfc000000;
16131 inst.instruction |= 0xf0000000;
16138 do_vrint_1 (neon_cvt_mode_x);
16144 do_vrint_1 (neon_cvt_mode_z);
16150 do_vrint_1 (neon_cvt_mode_r);
16156 do_vrint_1 (neon_cvt_mode_a);
16162 do_vrint_1 (neon_cvt_mode_n);
16168 do_vrint_1 (neon_cvt_mode_p);
16174 do_vrint_1 (neon_cvt_mode_m);
16177 /* Crypto v1 instructions. */
16179 do_crypto_2op_1 (unsigned elttype, int op)
16181 set_it_insn_type (OUTSIDE_IT_INSN);
16183 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16189 NEON_ENCODE (INTEGER, inst);
16190 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16191 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16192 inst.instruction |= LOW4 (inst.operands[1].reg);
16193 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16195 inst.instruction |= op << 6;
16198 inst.instruction |= 0xfc000000;
16200 inst.instruction |= 0xf0000000;
16204 do_crypto_3op_1 (int u, int op)
16206 set_it_insn_type (OUTSIDE_IT_INSN);
16208 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16209 N_32 | N_UNT | N_KEY).type == NT_invtype)
16214 NEON_ENCODE (INTEGER, inst);
16215 neon_three_same (1, u, 8 << op);
16221 do_crypto_2op_1 (N_8, 0);
16227 do_crypto_2op_1 (N_8, 1);
16233 do_crypto_2op_1 (N_8, 2);
16239 do_crypto_2op_1 (N_8, 3);
16245 do_crypto_3op_1 (0, 0);
16251 do_crypto_3op_1 (0, 1);
16257 do_crypto_3op_1 (0, 2);
16263 do_crypto_3op_1 (0, 3);
16269 do_crypto_3op_1 (1, 0);
16275 do_crypto_3op_1 (1, 1);
16279 do_sha256su1 (void)
16281 do_crypto_3op_1 (1, 2);
16284 /* Overall per-instruction processing. */
16286 /* We need to be able to fix up arbitrary expressions in some statements.
16287 This is so that we can handle symbols that are an arbitrary distance from
16288 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16289 which returns part of an address in a form which will be valid for
16290 a data instruction. We do this by pushing the expression into a symbol
16291 in the expr_section, and creating a fix for that. */
16294 fix_new_arm (fragS * frag,
16308 /* Create an absolute valued symbol, so we have something to
16309 refer to in the object file. Unfortunately for us, gas's
16310 generic expression parsing will already have folded out
16311 any use of .set foo/.type foo %function that may have
16312 been used to set type information of the target location,
16313 that's being specified symbolically. We have to presume
16314 the user knows what they are doing. */
16318 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16320 symbol = symbol_find_or_make (name);
16321 S_SET_SEGMENT (symbol, absolute_section);
16322 symbol_set_frag (symbol, &zero_address_frag);
16323 S_SET_VALUE (symbol, exp->X_add_number);
16324 exp->X_op = O_symbol;
16325 exp->X_add_symbol = symbol;
16326 exp->X_add_number = 0;
16332 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
16333 (enum bfd_reloc_code_real) reloc);
16337 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
16338 pc_rel, (enum bfd_reloc_code_real) reloc);
16342 /* Mark whether the fix is to a THUMB instruction, or an ARM
16344 new_fix->tc_fix_data = thumb_mode;
16347 /* Create a frg for an instruction requiring relaxation. */
16349 output_relax_insn (void)
16355 /* The size of the instruction is unknown, so tie the debug info to the
16356 start of the instruction. */
16357 dwarf2_emit_insn (0);
16359 switch (inst.reloc.exp.X_op)
16362 sym = inst.reloc.exp.X_add_symbol;
16363 offset = inst.reloc.exp.X_add_number;
16367 offset = inst.reloc.exp.X_add_number;
16370 sym = make_expr_symbol (&inst.reloc.exp);
16374 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16375 inst.relax, sym, offset, NULL/*offset, opcode*/);
16376 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
16379 /* Write a 32-bit thumb instruction to buf. */
16381 put_thumb32_insn (char * buf, unsigned long insn)
16383 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16384 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16388 output_inst (const char * str)
16394 as_bad ("%s -- `%s'", inst.error, str);
16399 output_relax_insn ();
16402 if (inst.size == 0)
16405 to = frag_more (inst.size);
16406 /* PR 9814: Record the thumb mode into the current frag so that we know
16407 what type of NOP padding to use, if necessary. We override any previous
16408 setting so that if the mode has changed then the NOPS that we use will
16409 match the encoding of the last instruction in the frag. */
16410 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
16412 if (thumb_mode && (inst.size > THUMB_SIZE))
16414 gas_assert (inst.size == (2 * THUMB_SIZE));
16415 put_thumb32_insn (to, inst.instruction);
16417 else if (inst.size > INSN_SIZE)
16419 gas_assert (inst.size == (2 * INSN_SIZE));
16420 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16421 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
16424 md_number_to_chars (to, inst.instruction, inst.size);
16426 if (inst.reloc.type != BFD_RELOC_UNUSED)
16427 fix_new_arm (frag_now, to - frag_now->fr_literal,
16428 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16431 dwarf2_emit_insn (inst.size);
16435 output_it_inst (int cond, int mask, char * to)
16437 unsigned long instruction = 0xbf00;
16440 instruction |= mask;
16441 instruction |= cond << 4;
16445 to = frag_more (2);
16447 dwarf2_emit_insn (2);
16451 md_number_to_chars (to, instruction, 2);
16456 /* Tag values used in struct asm_opcode's tag field. */
16459 OT_unconditional, /* Instruction cannot be conditionalized.
16460 The ARM condition field is still 0xE. */
16461 OT_unconditionalF, /* Instruction cannot be conditionalized
16462 and carries 0xF in its ARM condition field. */
16463 OT_csuffix, /* Instruction takes a conditional suffix. */
16464 OT_csuffixF, /* Some forms of the instruction take a conditional
16465 suffix, others place 0xF where the condition field
16467 OT_cinfix3, /* Instruction takes a conditional infix,
16468 beginning at character index 3. (In
16469 unified mode, it becomes a suffix.) */
16470 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16471 tsts, cmps, cmns, and teqs. */
16472 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16473 character index 3, even in unified mode. Used for
16474 legacy instructions where suffix and infix forms
16475 may be ambiguous. */
16476 OT_csuf_or_in3, /* Instruction takes either a conditional
16477 suffix or an infix at character index 3. */
16478 OT_odd_infix_unc, /* This is the unconditional variant of an
16479 instruction that takes a conditional infix
16480 at an unusual position. In unified mode,
16481 this variant will accept a suffix. */
16482 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16483 are the conditional variants of instructions that
16484 take conditional infixes in unusual positions.
16485 The infix appears at character index
16486 (tag - OT_odd_infix_0). These are not accepted
16487 in unified mode. */
16490 /* Subroutine of md_assemble, responsible for looking up the primary
16491 opcode from the mnemonic the user wrote. STR points to the
16492 beginning of the mnemonic.
16494 This is not simply a hash table lookup, because of conditional
16495 variants. Most instructions have conditional variants, which are
16496 expressed with a _conditional affix_ to the mnemonic. If we were
16497 to encode each conditional variant as a literal string in the opcode
16498 table, it would have approximately 20,000 entries.
16500 Most mnemonics take this affix as a suffix, and in unified syntax,
16501 'most' is upgraded to 'all'. However, in the divided syntax, some
16502 instructions take the affix as an infix, notably the s-variants of
16503 the arithmetic instructions. Of those instructions, all but six
16504 have the infix appear after the third character of the mnemonic.
16506 Accordingly, the algorithm for looking up primary opcodes given
16509 1. Look up the identifier in the opcode table.
16510 If we find a match, go to step U.
16512 2. Look up the last two characters of the identifier in the
16513 conditions table. If we find a match, look up the first N-2
16514 characters of the identifier in the opcode table. If we
16515 find a match, go to step CE.
16517 3. Look up the fourth and fifth characters of the identifier in
16518 the conditions table. If we find a match, extract those
16519 characters from the identifier, and look up the remaining
16520 characters in the opcode table. If we find a match, go
16525 U. Examine the tag field of the opcode structure, in case this is
16526 one of the six instructions with its conditional infix in an
16527 unusual place. If it is, the tag tells us where to find the
16528 infix; look it up in the conditions table and set inst.cond
16529 accordingly. Otherwise, this is an unconditional instruction.
16530 Again set inst.cond accordingly. Return the opcode structure.
16532 CE. Examine the tag field to make sure this is an instruction that
16533 should receive a conditional suffix. If it is not, fail.
16534 Otherwise, set inst.cond from the suffix we already looked up,
16535 and return the opcode structure.
16537 CM. Examine the tag field to make sure this is an instruction that
16538 should receive a conditional infix after the third character.
16539 If it is not, fail. Otherwise, undo the edits to the current
16540 line of input and proceed as for case CE. */
16542 static const struct asm_opcode *
16543 opcode_lookup (char **str)
16547 const struct asm_opcode *opcode;
16548 const struct asm_cond *cond;
16551 /* Scan up to the end of the mnemonic, which must end in white space,
16552 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16553 for (base = end = *str; *end != '\0'; end++)
16554 if (*end == ' ' || *end == '.')
16560 /* Handle a possible width suffix and/or Neon type suffix. */
16565 /* The .w and .n suffixes are only valid if the unified syntax is in
16567 if (unified_syntax && end[1] == 'w')
16569 else if (unified_syntax && end[1] == 'n')
16574 inst.vectype.elems = 0;
16576 *str = end + offset;
16578 if (end[offset] == '.')
16580 /* See if we have a Neon type suffix (possible in either unified or
16581 non-unified ARM syntax mode). */
16582 if (parse_neon_type (&inst.vectype, str) == FAIL)
16585 else if (end[offset] != '\0' && end[offset] != ' ')
16591 /* Look for unaffixed or special-case affixed mnemonic. */
16592 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16597 if (opcode->tag < OT_odd_infix_0)
16599 inst.cond = COND_ALWAYS;
16603 if (warn_on_deprecated && unified_syntax)
16604 as_warn (_("conditional infixes are deprecated in unified syntax"));
16605 affix = base + (opcode->tag - OT_odd_infix_0);
16606 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16609 inst.cond = cond->value;
16613 /* Cannot have a conditional suffix on a mnemonic of less than two
16615 if (end - base < 3)
16618 /* Look for suffixed mnemonic. */
16620 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16621 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16623 if (opcode && cond)
16626 switch (opcode->tag)
16628 case OT_cinfix3_legacy:
16629 /* Ignore conditional suffixes matched on infix only mnemonics. */
16633 case OT_cinfix3_deprecated:
16634 case OT_odd_infix_unc:
16635 if (!unified_syntax)
16637 /* else fall through */
16641 case OT_csuf_or_in3:
16642 inst.cond = cond->value;
16645 case OT_unconditional:
16646 case OT_unconditionalF:
16648 inst.cond = cond->value;
16651 /* Delayed diagnostic. */
16652 inst.error = BAD_COND;
16653 inst.cond = COND_ALWAYS;
16662 /* Cannot have a usual-position infix on a mnemonic of less than
16663 six characters (five would be a suffix). */
16664 if (end - base < 6)
16667 /* Look for infixed mnemonic in the usual position. */
16669 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16673 memcpy (save, affix, 2);
16674 memmove (affix, affix + 2, (end - affix) - 2);
16675 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16677 memmove (affix + 2, affix, (end - affix) - 2);
16678 memcpy (affix, save, 2);
16681 && (opcode->tag == OT_cinfix3
16682 || opcode->tag == OT_cinfix3_deprecated
16683 || opcode->tag == OT_csuf_or_in3
16684 || opcode->tag == OT_cinfix3_legacy))
16687 if (warn_on_deprecated && unified_syntax
16688 && (opcode->tag == OT_cinfix3
16689 || opcode->tag == OT_cinfix3_deprecated))
16690 as_warn (_("conditional infixes are deprecated in unified syntax"));
16692 inst.cond = cond->value;
16699 /* This function generates an initial IT instruction, leaving its block
16700 virtually open for the new instructions. Eventually,
16701 the mask will be updated by now_it_add_mask () each time
16702 a new instruction needs to be included in the IT block.
16703 Finally, the block is closed with close_automatic_it_block ().
16704 The block closure can be requested either from md_assemble (),
16705 a tencode (), or due to a label hook. */
16708 new_automatic_it_block (int cond)
16710 now_it.state = AUTOMATIC_IT_BLOCK;
16711 now_it.mask = 0x18;
16713 now_it.block_length = 1;
16714 mapping_state (MAP_THUMB);
16715 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16716 now_it.warn_deprecated = FALSE;
16717 now_it.insn_cond = TRUE;
16720 /* Close an automatic IT block.
16721 See comments in new_automatic_it_block (). */
16724 close_automatic_it_block (void)
16726 now_it.mask = 0x10;
16727 now_it.block_length = 0;
16730 /* Update the mask of the current automatically-generated IT
16731 instruction. See comments in new_automatic_it_block (). */
16734 now_it_add_mask (int cond)
16736 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16737 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16738 | ((bitvalue) << (nbit)))
16739 const int resulting_bit = (cond & 1);
16741 now_it.mask &= 0xf;
16742 now_it.mask = SET_BIT_VALUE (now_it.mask,
16744 (5 - now_it.block_length));
16745 now_it.mask = SET_BIT_VALUE (now_it.mask,
16747 ((5 - now_it.block_length) - 1) );
16748 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16751 #undef SET_BIT_VALUE
16754 /* The IT blocks handling machinery is accessed through the these functions:
16755 it_fsm_pre_encode () from md_assemble ()
16756 set_it_insn_type () optional, from the tencode functions
16757 set_it_insn_type_last () ditto
16758 in_it_block () ditto
16759 it_fsm_post_encode () from md_assemble ()
16760 force_automatic_it_block_close () from label habdling functions
16763 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16764 initializing the IT insn type with a generic initial value depending
16765 on the inst.condition.
16766 2) During the tencode function, two things may happen:
16767 a) The tencode function overrides the IT insn type by
16768 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16769 b) The tencode function queries the IT block state by
16770 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16772 Both set_it_insn_type and in_it_block run the internal FSM state
16773 handling function (handle_it_state), because: a) setting the IT insn
16774 type may incur in an invalid state (exiting the function),
16775 and b) querying the state requires the FSM to be updated.
16776 Specifically we want to avoid creating an IT block for conditional
16777 branches, so it_fsm_pre_encode is actually a guess and we can't
16778 determine whether an IT block is required until the tencode () routine
16779 has decided what type of instruction this actually it.
16780 Because of this, if set_it_insn_type and in_it_block have to be used,
16781 set_it_insn_type has to be called first.
16783 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16784 determines the insn IT type depending on the inst.cond code.
16785 When a tencode () routine encodes an instruction that can be
16786 either outside an IT block, or, in the case of being inside, has to be
16787 the last one, set_it_insn_type_last () will determine the proper
16788 IT instruction type based on the inst.cond code. Otherwise,
16789 set_it_insn_type can be called for overriding that logic or
16790 for covering other cases.
16792 Calling handle_it_state () may not transition the IT block state to
16793 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16794 still queried. Instead, if the FSM determines that the state should
16795 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16796 after the tencode () function: that's what it_fsm_post_encode () does.
16798 Since in_it_block () calls the state handling function to get an
16799 updated state, an error may occur (due to invalid insns combination).
16800 In that case, inst.error is set.
16801 Therefore, inst.error has to be checked after the execution of
16802 the tencode () routine.
16804 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16805 any pending state change (if any) that didn't take place in
16806 handle_it_state () as explained above. */
16809 it_fsm_pre_encode (void)
16811 if (inst.cond != COND_ALWAYS)
16812 inst.it_insn_type = INSIDE_IT_INSN;
16814 inst.it_insn_type = OUTSIDE_IT_INSN;
16816 now_it.state_handled = 0;
16819 /* IT state FSM handling function. */
16822 handle_it_state (void)
16824 now_it.state_handled = 1;
16825 now_it.insn_cond = FALSE;
16827 switch (now_it.state)
16829 case OUTSIDE_IT_BLOCK:
16830 switch (inst.it_insn_type)
16832 case OUTSIDE_IT_INSN:
16835 case INSIDE_IT_INSN:
16836 case INSIDE_IT_LAST_INSN:
16837 if (thumb_mode == 0)
16840 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16841 as_tsktsk (_("Warning: conditional outside an IT block"\
16846 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16847 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16849 /* Automatically generate the IT instruction. */
16850 new_automatic_it_block (inst.cond);
16851 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16852 close_automatic_it_block ();
16856 inst.error = BAD_OUT_IT;
16862 case IF_INSIDE_IT_LAST_INSN:
16863 case NEUTRAL_IT_INSN:
16867 now_it.state = MANUAL_IT_BLOCK;
16868 now_it.block_length = 0;
16873 case AUTOMATIC_IT_BLOCK:
16874 /* Three things may happen now:
16875 a) We should increment current it block size;
16876 b) We should close current it block (closing insn or 4 insns);
16877 c) We should close current it block and start a new one (due
16878 to incompatible conditions or
16879 4 insns-length block reached). */
16881 switch (inst.it_insn_type)
16883 case OUTSIDE_IT_INSN:
16884 /* The closure of the block shall happen immediatelly,
16885 so any in_it_block () call reports the block as closed. */
16886 force_automatic_it_block_close ();
16889 case INSIDE_IT_INSN:
16890 case INSIDE_IT_LAST_INSN:
16891 case IF_INSIDE_IT_LAST_INSN:
16892 now_it.block_length++;
16894 if (now_it.block_length > 4
16895 || !now_it_compatible (inst.cond))
16897 force_automatic_it_block_close ();
16898 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16899 new_automatic_it_block (inst.cond);
16903 now_it.insn_cond = TRUE;
16904 now_it_add_mask (inst.cond);
16907 if (now_it.state == AUTOMATIC_IT_BLOCK
16908 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16909 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16910 close_automatic_it_block ();
16913 case NEUTRAL_IT_INSN:
16914 now_it.block_length++;
16915 now_it.insn_cond = TRUE;
16917 if (now_it.block_length > 4)
16918 force_automatic_it_block_close ();
16920 now_it_add_mask (now_it.cc & 1);
16924 close_automatic_it_block ();
16925 now_it.state = MANUAL_IT_BLOCK;
16930 case MANUAL_IT_BLOCK:
16932 /* Check conditional suffixes. */
16933 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16936 now_it.mask &= 0x1f;
16937 is_last = (now_it.mask == 0x10);
16938 now_it.insn_cond = TRUE;
16940 switch (inst.it_insn_type)
16942 case OUTSIDE_IT_INSN:
16943 inst.error = BAD_NOT_IT;
16946 case INSIDE_IT_INSN:
16947 if (cond != inst.cond)
16949 inst.error = BAD_IT_COND;
16954 case INSIDE_IT_LAST_INSN:
16955 case IF_INSIDE_IT_LAST_INSN:
16956 if (cond != inst.cond)
16958 inst.error = BAD_IT_COND;
16963 inst.error = BAD_BRANCH;
16968 case NEUTRAL_IT_INSN:
16969 /* The BKPT instruction is unconditional even in an IT block. */
16973 inst.error = BAD_IT_IT;
16983 struct depr_insn_mask
16985 unsigned long pattern;
16986 unsigned long mask;
16987 const char* description;
16990 /* List of 16-bit instruction patterns deprecated in an IT block in
16992 static const struct depr_insn_mask depr_it_insns[] = {
16993 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
16994 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
16995 { 0xa000, 0xb800, N_("ADR") },
16996 { 0x4800, 0xf800, N_("Literal loads") },
16997 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
16998 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17003 it_fsm_post_encode (void)
17007 if (!now_it.state_handled)
17008 handle_it_state ();
17010 if (now_it.insn_cond
17011 && !now_it.warn_deprecated
17012 && warn_on_deprecated
17013 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17015 if (inst.instruction >= 0x10000)
17017 as_warn (_("it blocks containing wide Thumb instructions are "
17018 "deprecated in ARMv8"));
17019 now_it.warn_deprecated = TRUE;
17023 const struct depr_insn_mask *p = depr_it_insns;
17025 while (p->mask != 0)
17027 if ((inst.instruction & p->mask) == p->pattern)
17029 as_warn (_("it blocks containing 16-bit Thumb intsructions "
17030 "of the following class are deprecated in ARMv8: "
17031 "%s"), p->description);
17032 now_it.warn_deprecated = TRUE;
17040 if (now_it.block_length > 1)
17042 as_warn (_("it blocks of more than one conditional instruction are "
17043 "deprecated in ARMv8"));
17044 now_it.warn_deprecated = TRUE;
17048 is_last = (now_it.mask == 0x10);
17051 now_it.state = OUTSIDE_IT_BLOCK;
17057 force_automatic_it_block_close (void)
17059 if (now_it.state == AUTOMATIC_IT_BLOCK)
17061 close_automatic_it_block ();
17062 now_it.state = OUTSIDE_IT_BLOCK;
17070 if (!now_it.state_handled)
17071 handle_it_state ();
17073 return now_it.state != OUTSIDE_IT_BLOCK;
17077 md_assemble (char *str)
17080 const struct asm_opcode * opcode;
17082 /* Align the previous label if needed. */
17083 if (last_label_seen != NULL)
17085 symbol_set_frag (last_label_seen, frag_now);
17086 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17087 S_SET_SEGMENT (last_label_seen, now_seg);
17090 memset (&inst, '\0', sizeof (inst));
17091 inst.reloc.type = BFD_RELOC_UNUSED;
17093 opcode = opcode_lookup (&p);
17096 /* It wasn't an instruction, but it might be a register alias of
17097 the form alias .req reg, or a Neon .dn/.qn directive. */
17098 if (! create_register_alias (str, p)
17099 && ! create_neon_reg_alias (str, p))
17100 as_bad (_("bad instruction `%s'"), str);
17105 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
17106 as_warn (_("s suffix on comparison instruction is deprecated"));
17108 /* The value which unconditional instructions should have in place of the
17109 condition field. */
17110 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17114 arm_feature_set variant;
17116 variant = cpu_variant;
17117 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17118 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17119 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
17120 /* Check that this instruction is supported for this CPU. */
17121 if (!opcode->tvariant
17122 || (thumb_mode == 1
17123 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
17125 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
17128 if (inst.cond != COND_ALWAYS && !unified_syntax
17129 && opcode->tencode != do_t_branch)
17131 as_bad (_("Thumb does not support conditional execution"));
17135 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
17137 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
17138 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17139 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17141 /* Two things are addressed here.
17142 1) Implicit require narrow instructions on Thumb-1.
17143 This avoids relaxation accidentally introducing Thumb-2
17145 2) Reject wide instructions in non Thumb-2 cores. */
17146 if (inst.size_req == 0)
17148 else if (inst.size_req == 4)
17150 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
17156 inst.instruction = opcode->tvalue;
17158 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
17160 /* Prepare the it_insn_type for those encodings that don't set
17162 it_fsm_pre_encode ();
17164 opcode->tencode ();
17166 it_fsm_post_encode ();
17169 if (!(inst.error || inst.relax))
17171 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
17172 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17173 if (inst.size_req && inst.size_req != inst.size)
17175 as_bad (_("cannot honor width suffix -- `%s'"), str);
17180 /* Something has gone badly wrong if we try to relax a fixed size
17182 gas_assert (inst.size_req == 0 || !inst.relax);
17184 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17185 *opcode->tvariant);
17186 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17187 set those bits when Thumb-2 32-bit instructions are seen. ie.
17188 anything other than bl/blx and v6-M instructions.
17189 This is overly pessimistic for relaxable instructions. */
17190 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
17192 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17193 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
17194 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17197 check_neon_suffixes;
17201 mapping_state (MAP_THUMB);
17204 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
17208 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17209 is_bx = (opcode->aencode == do_bx);
17211 /* Check that this instruction is supported for this CPU. */
17212 if (!(is_bx && fix_v4bx)
17213 && !(opcode->avariant &&
17214 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
17216 as_bad (_("selected processor does not support ARM mode `%s'"), str);
17221 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17225 inst.instruction = opcode->avalue;
17226 if (opcode->tag == OT_unconditionalF)
17227 inst.instruction |= 0xF << 28;
17229 inst.instruction |= inst.cond << 28;
17230 inst.size = INSN_SIZE;
17231 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
17233 it_fsm_pre_encode ();
17234 opcode->aencode ();
17235 it_fsm_post_encode ();
17237 /* Arm mode bx is marked as both v4T and v5 because it's still required
17238 on a hypothetical non-thumb v5 core. */
17240 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
17242 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17243 *opcode->avariant);
17245 check_neon_suffixes;
17249 mapping_state (MAP_ARM);
17254 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17262 check_it_blocks_finished (void)
17267 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17268 if (seg_info (sect)->tc_segment_info_data.current_it.state
17269 == MANUAL_IT_BLOCK)
17271 as_warn (_("section '%s' finished with an open IT block."),
17275 if (now_it.state == MANUAL_IT_BLOCK)
17276 as_warn (_("file finished with an open IT block."));
17280 /* Various frobbings of labels and their addresses. */
17283 arm_start_line_hook (void)
17285 last_label_seen = NULL;
17289 arm_frob_label (symbolS * sym)
17291 last_label_seen = sym;
17293 ARM_SET_THUMB (sym, thumb_mode);
17295 #if defined OBJ_COFF || defined OBJ_ELF
17296 ARM_SET_INTERWORK (sym, support_interwork);
17299 force_automatic_it_block_close ();
17301 /* Note - do not allow local symbols (.Lxxx) to be labelled
17302 as Thumb functions. This is because these labels, whilst
17303 they exist inside Thumb code, are not the entry points for
17304 possible ARM->Thumb calls. Also, these labels can be used
17305 as part of a computed goto or switch statement. eg gcc
17306 can generate code that looks like this:
17308 ldr r2, [pc, .Laaa]
17318 The first instruction loads the address of the jump table.
17319 The second instruction converts a table index into a byte offset.
17320 The third instruction gets the jump address out of the table.
17321 The fourth instruction performs the jump.
17323 If the address stored at .Laaa is that of a symbol which has the
17324 Thumb_Func bit set, then the linker will arrange for this address
17325 to have the bottom bit set, which in turn would mean that the
17326 address computation performed by the third instruction would end
17327 up with the bottom bit set. Since the ARM is capable of unaligned
17328 word loads, the instruction would then load the incorrect address
17329 out of the jump table, and chaos would ensue. */
17330 if (label_is_thumb_function_name
17331 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17332 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
17334 /* When the address of a Thumb function is taken the bottom
17335 bit of that address should be set. This will allow
17336 interworking between Arm and Thumb functions to work
17339 THUMB_SET_FUNC (sym, 1);
17341 label_is_thumb_function_name = FALSE;
17344 dwarf2_emit_label (sym);
17348 arm_data_in_code (void)
17350 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
17352 *input_line_pointer = '/';
17353 input_line_pointer += 5;
17354 *input_line_pointer = 0;
17362 arm_canonicalize_symbol_name (char * name)
17366 if (thumb_mode && (len = strlen (name)) > 5
17367 && streq (name + len - 5, "/data"))
17368 *(name + len - 5) = 0;
17373 /* Table of all register names defined by default. The user can
17374 define additional names with .req. Note that all register names
17375 should appear in both upper and lowercase variants. Some registers
17376 also have mixed-case names. */
17378 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17379 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17380 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17381 #define REGSET(p,t) \
17382 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17383 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17384 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17385 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17386 #define REGSETH(p,t) \
17387 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17388 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17389 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17390 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17391 #define REGSET2(p,t) \
17392 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17393 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17394 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17395 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17396 #define SPLRBANK(base,bank,t) \
17397 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17398 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17399 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17400 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17401 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17402 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17404 static const struct reg_entry reg_names[] =
17406 /* ARM integer registers. */
17407 REGSET(r, RN), REGSET(R, RN),
17409 /* ATPCS synonyms. */
17410 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17411 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17412 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
17414 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17415 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17416 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
17418 /* Well-known aliases. */
17419 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17420 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17422 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17423 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17425 /* Coprocessor numbers. */
17426 REGSET(p, CP), REGSET(P, CP),
17428 /* Coprocessor register numbers. The "cr" variants are for backward
17430 REGSET(c, CN), REGSET(C, CN),
17431 REGSET(cr, CN), REGSET(CR, CN),
17433 /* ARM banked registers. */
17434 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17435 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17436 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17437 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17438 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17439 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17440 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17442 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17443 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17444 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17445 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17446 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
17447 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
17448 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17449 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17451 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17452 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17453 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17454 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17455 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17456 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17457 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
17458 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
17459 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17461 /* FPA registers. */
17462 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17463 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17465 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17466 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17468 /* VFP SP registers. */
17469 REGSET(s,VFS), REGSET(S,VFS),
17470 REGSETH(s,VFS), REGSETH(S,VFS),
17472 /* VFP DP Registers. */
17473 REGSET(d,VFD), REGSET(D,VFD),
17474 /* Extra Neon DP registers. */
17475 REGSETH(d,VFD), REGSETH(D,VFD),
17477 /* Neon QP registers. */
17478 REGSET2(q,NQ), REGSET2(Q,NQ),
17480 /* VFP control registers. */
17481 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17482 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
17483 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17484 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17485 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17486 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
17488 /* Maverick DSP coprocessor registers. */
17489 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17490 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17492 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17493 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17494 REGDEF(dspsc,0,DSPSC),
17496 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17497 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17498 REGDEF(DSPSC,0,DSPSC),
17500 /* iWMMXt data registers - p0, c0-15. */
17501 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17503 /* iWMMXt control registers - p1, c0-3. */
17504 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17505 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17506 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17507 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17509 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17510 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17511 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17512 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17513 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17515 /* XScale accumulator registers. */
17516 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17522 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17523 within psr_required_here. */
17524 static const struct asm_psr psrs[] =
17526 /* Backward compatibility notation. Note that "all" is no longer
17527 truly all possible PSR bits. */
17528 {"all", PSR_c | PSR_f},
17532 /* Individual flags. */
17538 /* Combinations of flags. */
17539 {"fs", PSR_f | PSR_s},
17540 {"fx", PSR_f | PSR_x},
17541 {"fc", PSR_f | PSR_c},
17542 {"sf", PSR_s | PSR_f},
17543 {"sx", PSR_s | PSR_x},
17544 {"sc", PSR_s | PSR_c},
17545 {"xf", PSR_x | PSR_f},
17546 {"xs", PSR_x | PSR_s},
17547 {"xc", PSR_x | PSR_c},
17548 {"cf", PSR_c | PSR_f},
17549 {"cs", PSR_c | PSR_s},
17550 {"cx", PSR_c | PSR_x},
17551 {"fsx", PSR_f | PSR_s | PSR_x},
17552 {"fsc", PSR_f | PSR_s | PSR_c},
17553 {"fxs", PSR_f | PSR_x | PSR_s},
17554 {"fxc", PSR_f | PSR_x | PSR_c},
17555 {"fcs", PSR_f | PSR_c | PSR_s},
17556 {"fcx", PSR_f | PSR_c | PSR_x},
17557 {"sfx", PSR_s | PSR_f | PSR_x},
17558 {"sfc", PSR_s | PSR_f | PSR_c},
17559 {"sxf", PSR_s | PSR_x | PSR_f},
17560 {"sxc", PSR_s | PSR_x | PSR_c},
17561 {"scf", PSR_s | PSR_c | PSR_f},
17562 {"scx", PSR_s | PSR_c | PSR_x},
17563 {"xfs", PSR_x | PSR_f | PSR_s},
17564 {"xfc", PSR_x | PSR_f | PSR_c},
17565 {"xsf", PSR_x | PSR_s | PSR_f},
17566 {"xsc", PSR_x | PSR_s | PSR_c},
17567 {"xcf", PSR_x | PSR_c | PSR_f},
17568 {"xcs", PSR_x | PSR_c | PSR_s},
17569 {"cfs", PSR_c | PSR_f | PSR_s},
17570 {"cfx", PSR_c | PSR_f | PSR_x},
17571 {"csf", PSR_c | PSR_s | PSR_f},
17572 {"csx", PSR_c | PSR_s | PSR_x},
17573 {"cxf", PSR_c | PSR_x | PSR_f},
17574 {"cxs", PSR_c | PSR_x | PSR_s},
17575 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17576 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17577 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17578 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17579 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17580 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17581 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17582 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17583 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17584 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17585 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17586 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17587 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17588 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17589 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17590 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17591 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17592 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17593 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17594 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17595 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17596 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17597 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17598 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17601 /* Table of V7M psr names. */
17602 static const struct asm_psr v7m_psrs[] =
17604 {"apsr", 0 }, {"APSR", 0 },
17605 {"iapsr", 1 }, {"IAPSR", 1 },
17606 {"eapsr", 2 }, {"EAPSR", 2 },
17607 {"psr", 3 }, {"PSR", 3 },
17608 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17609 {"ipsr", 5 }, {"IPSR", 5 },
17610 {"epsr", 6 }, {"EPSR", 6 },
17611 {"iepsr", 7 }, {"IEPSR", 7 },
17612 {"msp", 8 }, {"MSP", 8 },
17613 {"psp", 9 }, {"PSP", 9 },
17614 {"primask", 16}, {"PRIMASK", 16},
17615 {"basepri", 17}, {"BASEPRI", 17},
17616 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17617 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17618 {"faultmask", 19}, {"FAULTMASK", 19},
17619 {"control", 20}, {"CONTROL", 20}
17622 /* Table of all shift-in-operand names. */
17623 static const struct asm_shift_name shift_names [] =
17625 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17626 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17627 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17628 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17629 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17630 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17633 /* Table of all explicit relocation names. */
17635 static struct reloc_entry reloc_names[] =
17637 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17638 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17639 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17640 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17641 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17642 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17643 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17644 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17645 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17646 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17647 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17648 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17649 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17650 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17651 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17652 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17653 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17654 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17658 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17659 static const struct asm_cond conds[] =
17663 {"cs", 0x2}, {"hs", 0x2},
17664 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17678 #define UL_BARRIER(L,U,CODE,FEAT) \
17679 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17680 { U, CODE, ARM_FEATURE (FEAT, 0) }
17682 static struct asm_barrier_opt barrier_opt_names[] =
17684 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17685 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17686 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17687 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17688 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17689 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17690 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17691 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17692 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17693 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17694 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17695 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17696 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17697 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17698 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17699 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
17704 /* Table of ARM-format instructions. */
17706 /* Macros for gluing together operand strings. N.B. In all cases
17707 other than OPS0, the trailing OP_stop comes from default
17708 zero-initialization of the unspecified elements of the array. */
17709 #define OPS0() { OP_stop, }
17710 #define OPS1(a) { OP_##a, }
17711 #define OPS2(a,b) { OP_##a,OP_##b, }
17712 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17713 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17714 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17715 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17717 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17718 This is useful when mixing operands for ARM and THUMB, i.e. using the
17719 MIX_ARM_THUMB_OPERANDS macro.
17720 In order to use these macros, prefix the number of operands with _
17722 #define OPS_1(a) { a, }
17723 #define OPS_2(a,b) { a,b, }
17724 #define OPS_3(a,b,c) { a,b,c, }
17725 #define OPS_4(a,b,c,d) { a,b,c,d, }
17726 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17727 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17729 /* These macros abstract out the exact format of the mnemonic table and
17730 save some repeated characters. */
17732 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17733 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17734 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17735 THUMB_VARIANT, do_##ae, do_##te }
17737 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17738 a T_MNEM_xyz enumerator. */
17739 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17740 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17741 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17742 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17744 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17745 infix after the third character. */
17746 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17747 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17748 THUMB_VARIANT, do_##ae, do_##te }
17749 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17750 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17751 THUMB_VARIANT, do_##ae, do_##te }
17752 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17753 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17754 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17755 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17756 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17757 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17758 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17759 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17761 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
17762 appear in the condition table. */
17763 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17764 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17765 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17767 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17768 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17769 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17770 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17771 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17772 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17773 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17774 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17775 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17776 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17777 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17778 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17779 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17780 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17781 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17782 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17783 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17784 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17785 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17786 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17788 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17789 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17790 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17791 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17793 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17794 field is still 0xE. Many of the Thumb variants can be executed
17795 conditionally, so this is checked separately. */
17796 #define TUE(mnem, op, top, nops, ops, ae, te) \
17797 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17798 THUMB_VARIANT, do_##ae, do_##te }
17800 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17801 condition code field. */
17802 #define TUF(mnem, op, top, nops, ops, ae, te) \
17803 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17804 THUMB_VARIANT, do_##ae, do_##te }
17806 /* ARM-only variants of all the above. */
17807 #define CE(mnem, op, nops, ops, ae) \
17808 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17810 #define C3(mnem, op, nops, ops, ae) \
17811 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17813 /* Legacy mnemonics that always have conditional infix after the third
17815 #define CL(mnem, op, nops, ops, ae) \
17816 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17817 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17819 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17820 #define cCE(mnem, op, nops, ops, ae) \
17821 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17823 /* Legacy coprocessor instructions where conditional infix and conditional
17824 suffix are ambiguous. For consistency this includes all FPA instructions,
17825 not just the potentially ambiguous ones. */
17826 #define cCL(mnem, op, nops, ops, ae) \
17827 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17828 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17830 /* Coprocessor, takes either a suffix or a position-3 infix
17831 (for an FPA corner case). */
17832 #define C3E(mnem, op, nops, ops, ae) \
17833 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17834 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17836 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17837 { m1 #m2 m3, OPS##nops ops, \
17838 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17839 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17841 #define CM(m1, m2, op, nops, ops, ae) \
17842 xCM_ (m1, , m2, op, nops, ops, ae), \
17843 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17844 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17845 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17846 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17847 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17848 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17849 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17850 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17851 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17852 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17853 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17854 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17855 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17856 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17857 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17858 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17859 xCM_ (m1, le, m2, op, nops, ops, ae), \
17860 xCM_ (m1, al, m2, op, nops, ops, ae)
17862 #define UE(mnem, op, nops, ops, ae) \
17863 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17865 #define UF(mnem, op, nops, ops, ae) \
17866 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17868 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17869 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17870 use the same encoding function for each. */
17871 #define NUF(mnem, op, nops, ops, enc) \
17872 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17873 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17875 /* Neon data processing, version which indirects through neon_enc_tab for
17876 the various overloaded versions of opcodes. */
17877 #define nUF(mnem, op, nops, ops, enc) \
17878 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17879 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17881 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17883 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17884 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17885 THUMB_VARIANT, do_##enc, do_##enc }
17887 #define NCE(mnem, op, nops, ops, enc) \
17888 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17890 #define NCEF(mnem, op, nops, ops, enc) \
17891 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17893 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17894 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17895 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17896 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17898 #define nCE(mnem, op, nops, ops, enc) \
17899 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17901 #define nCEF(mnem, op, nops, ops, enc) \
17902 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17906 static const struct asm_opcode insns[] =
17908 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17909 #define THUMB_VARIANT &arm_ext_v4t
17910 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17911 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17912 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17913 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17914 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17915 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17916 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17917 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17918 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17919 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17920 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17921 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17922 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17923 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17924 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17925 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17927 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17928 for setting PSR flag bits. They are obsolete in V6 and do not
17929 have Thumb equivalents. */
17930 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17931 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17932 CL("tstp", 110f000, 2, (RR, SH), cmp),
17933 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17934 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17935 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17936 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17937 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17938 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17940 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17941 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17942 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17943 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17945 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17946 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17947 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17949 OP_ADDRGLDR),ldst, t_ldst),
17950 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17952 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17953 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17954 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17955 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17956 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17957 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17959 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17960 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17961 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17962 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17965 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17966 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17967 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17969 /* Thumb-compatibility pseudo ops. */
17970 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17971 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17972 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17973 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17974 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17975 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17976 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17977 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17978 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17979 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17980 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17981 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17983 /* These may simplify to neg. */
17984 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17985 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17987 #undef THUMB_VARIANT
17988 #define THUMB_VARIANT & arm_ext_v6
17990 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17992 /* V1 instructions with no Thumb analogue prior to V6T2. */
17993 #undef THUMB_VARIANT
17994 #define THUMB_VARIANT & arm_ext_v6t2
17996 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17997 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17998 CL("teqp", 130f000, 2, (RR, SH), cmp),
18000 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18001 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18002 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18003 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18005 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18006 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18008 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18009 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18011 /* V1 instructions with no Thumb analogue at all. */
18012 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
18013 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18015 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18016 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18017 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18018 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18019 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18020 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18021 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18022 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18025 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18026 #undef THUMB_VARIANT
18027 #define THUMB_VARIANT & arm_ext_v4t
18029 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18030 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18032 #undef THUMB_VARIANT
18033 #define THUMB_VARIANT & arm_ext_v6t2
18035 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18036 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18038 /* Generic coprocessor instructions. */
18039 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18040 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18041 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18042 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18043 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18044 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18045 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
18048 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18050 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18051 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18054 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18055 #undef THUMB_VARIANT
18056 #define THUMB_VARIANT & arm_ext_msr
18058 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18059 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
18062 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18063 #undef THUMB_VARIANT
18064 #define THUMB_VARIANT & arm_ext_v6t2
18066 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18067 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18068 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18069 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18070 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18071 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18072 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18073 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18076 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18077 #undef THUMB_VARIANT
18078 #define THUMB_VARIANT & arm_ext_v4t
18080 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18081 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18082 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18083 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18084 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18085 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18088 #define ARM_VARIANT & arm_ext_v4t_5
18090 /* ARM Architecture 4T. */
18091 /* Note: bx (and blx) are required on V5, even if the processor does
18092 not support Thumb. */
18093 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
18096 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18097 #undef THUMB_VARIANT
18098 #define THUMB_VARIANT & arm_ext_v5t
18100 /* Note: blx has 2 variants; the .value coded here is for
18101 BLX(2). Only this variant has conditional execution. */
18102 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18103 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
18105 #undef THUMB_VARIANT
18106 #define THUMB_VARIANT & arm_ext_v6t2
18108 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18109 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18110 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18111 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18112 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18113 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18114 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18115 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18118 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18119 #undef THUMB_VARIANT
18120 #define THUMB_VARIANT &arm_ext_v5exp
18122 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18123 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18124 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18125 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18127 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18128 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18130 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18131 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18132 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18133 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18135 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18136 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18137 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18138 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18140 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18141 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18143 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18144 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18145 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18146 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18149 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18150 #undef THUMB_VARIANT
18151 #define THUMB_VARIANT &arm_ext_v6t2
18153 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
18154 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18156 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18157 ADDRGLDRS), ldrd, t_ldstd),
18159 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18160 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18163 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18165 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
18168 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18169 #undef THUMB_VARIANT
18170 #define THUMB_VARIANT & arm_ext_v6
18172 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18173 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18174 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18175 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18176 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18177 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18178 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18179 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18180 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18181 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
18183 #undef THUMB_VARIANT
18184 #define THUMB_VARIANT & arm_ext_v6t2
18186 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18187 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18189 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18190 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18192 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18193 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
18195 /* ARM V6 not included in V7M. */
18196 #undef THUMB_VARIANT
18197 #define THUMB_VARIANT & arm_ext_v6_notm
18198 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18199 UF(rfeib, 9900a00, 1, (RRw), rfe),
18200 UF(rfeda, 8100a00, 1, (RRw), rfe),
18201 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18202 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18203 UF(rfefa, 9900a00, 1, (RRw), rfe),
18204 UF(rfeea, 8100a00, 1, (RRw), rfe),
18205 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18206 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18207 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
18208 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
18209 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18211 /* ARM V6 not included in V7M (eg. integer SIMD). */
18212 #undef THUMB_VARIANT
18213 #define THUMB_VARIANT & arm_ext_v6_dsp
18214 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18215 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18216 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18217 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18218 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18219 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18220 /* Old name for QASX. */
18221 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18222 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18223 /* Old name for QSAX. */
18224 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18225 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18226 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18227 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18228 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18229 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18230 /* Old name for SASX. */
18231 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18232 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18233 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18234 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18235 /* Old name for SHASX. */
18236 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18237 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18238 /* Old name for SHSAX. */
18239 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18240 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18241 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18242 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18243 /* Old name for SSAX. */
18244 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18245 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18246 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18247 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18248 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18249 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18250 /* Old name for UASX. */
18251 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18252 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18253 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18254 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18255 /* Old name for UHASX. */
18256 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18257 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18258 /* Old name for UHSAX. */
18259 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18260 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18261 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18262 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18263 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18264 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18265 /* Old name for UQASX. */
18266 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18267 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18268 /* Old name for UQSAX. */
18269 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18270 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18271 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18272 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18273 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18274 /* Old name for USAX. */
18275 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18276 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18277 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18278 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18279 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18280 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18281 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18282 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18283 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18284 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18285 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18286 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18287 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18288 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18289 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18290 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18291 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18292 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18293 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18294 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18295 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18296 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18297 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18298 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18299 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18300 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18301 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18302 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18303 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18304 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18305 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18306 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18307 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18308 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
18311 #define ARM_VARIANT & arm_ext_v6k
18312 #undef THUMB_VARIANT
18313 #define THUMB_VARIANT & arm_ext_v6k
18315 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18316 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18317 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18318 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
18320 #undef THUMB_VARIANT
18321 #define THUMB_VARIANT & arm_ext_v6_notm
18322 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18324 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18325 RRnpcb), strexd, t_strexd),
18327 #undef THUMB_VARIANT
18328 #define THUMB_VARIANT & arm_ext_v6t2
18329 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18331 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18333 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18335 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18337 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
18340 #define ARM_VARIANT & arm_ext_sec
18341 #undef THUMB_VARIANT
18342 #define THUMB_VARIANT & arm_ext_sec
18344 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
18347 #define ARM_VARIANT & arm_ext_virt
18348 #undef THUMB_VARIANT
18349 #define THUMB_VARIANT & arm_ext_virt
18351 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18352 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18355 #define ARM_VARIANT & arm_ext_v6t2
18356 #undef THUMB_VARIANT
18357 #define THUMB_VARIANT & arm_ext_v6t2
18359 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18360 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18361 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18362 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18364 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18365 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18366 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18367 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
18369 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18370 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18371 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18372 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18374 /* Thumb-only instructions. */
18376 #define ARM_VARIANT NULL
18377 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18378 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
18380 /* ARM does not really have an IT instruction, so always allow it.
18381 The opcode is copied from Thumb in order to allow warnings in
18382 -mimplicit-it=[never | arm] modes. */
18384 #define ARM_VARIANT & arm_ext_v1
18386 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18387 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18388 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18389 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18390 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18391 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18392 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18393 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18394 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18395 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18396 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18397 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18398 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18399 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18400 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
18401 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18402 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18403 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
18405 /* Thumb2 only instructions. */
18407 #define ARM_VARIANT NULL
18409 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18410 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18411 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18412 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18413 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18414 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
18416 /* Hardware division instructions. */
18418 #define ARM_VARIANT & arm_ext_adiv
18419 #undef THUMB_VARIANT
18420 #define THUMB_VARIANT & arm_ext_div
18422 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18423 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
18425 /* ARM V6M/V7 instructions. */
18427 #define ARM_VARIANT & arm_ext_barrier
18428 #undef THUMB_VARIANT
18429 #define THUMB_VARIANT & arm_ext_barrier
18431 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
18432 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
18433 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
18435 /* ARM V7 instructions. */
18437 #define ARM_VARIANT & arm_ext_v7
18438 #undef THUMB_VARIANT
18439 #define THUMB_VARIANT & arm_ext_v7
18441 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18442 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
18445 #define ARM_VARIANT & arm_ext_mp
18446 #undef THUMB_VARIANT
18447 #define THUMB_VARIANT & arm_ext_mp
18449 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18451 /* AArchv8 instructions. */
18453 #define ARM_VARIANT & arm_ext_v8
18454 #undef THUMB_VARIANT
18455 #define THUMB_VARIANT & arm_ext_v8
18457 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
18458 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
18459 TCE("ldraex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18460 TCE("ldraexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
18462 TCE("ldraexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18463 TCE("ldraexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18464 TCE("strlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18466 TCE("strlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
18468 TCE("strlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18470 TCE("strlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18472 TCE("ldra", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18473 TCE("ldrab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18474 TCE("ldrah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18475 TCE("strl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18476 TCE("strlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18477 TCE("strlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18479 /* ARMv8 T32 only. */
18481 #define ARM_VARIANT NULL
18482 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18483 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18484 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18486 /* FP for ARMv8. */
18488 #define ARM_VARIANT & fpu_vfp_ext_armv8
18489 #undef THUMB_VARIANT
18490 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18492 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18493 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18494 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18495 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
18496 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18497 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18498 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
18499 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
18500 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
18501 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
18502 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
18503 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
18504 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
18505 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
18506 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
18507 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
18508 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
18510 /* Crypto v1 extensions. */
18512 #define ARM_VARIANT & fpu_crypto_ext_armv8
18513 #undef THUMB_VARIANT
18514 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18516 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
18517 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
18518 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
18519 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
18520 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
18521 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
18522 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
18523 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
18524 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
18525 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
18526 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
18529 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18530 #undef THUMB_VARIANT
18531 #define THUMB_VARIANT NULL
18533 cCE("wfs", e200110, 1, (RR), rd),
18534 cCE("rfs", e300110, 1, (RR), rd),
18535 cCE("wfc", e400110, 1, (RR), rd),
18536 cCE("rfc", e500110, 1, (RR), rd),
18538 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18539 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18540 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18541 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18543 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18544 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18545 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18546 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18548 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18549 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18550 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18551 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18552 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18553 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18554 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18555 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18556 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18557 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18558 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18559 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18561 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18562 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18563 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18564 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18565 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18566 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18567 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18568 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18569 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18570 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18571 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18572 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18574 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18575 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18576 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18577 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18578 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18579 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18580 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18581 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18582 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18583 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18584 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18585 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18587 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18588 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18589 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18590 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18591 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18592 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18593 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18594 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18595 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18596 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18597 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18598 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18600 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18601 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18602 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18603 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18604 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18605 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18606 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18607 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18608 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18609 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18610 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18611 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18613 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18614 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18615 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18616 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18617 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18618 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18619 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18620 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18621 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18622 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18623 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18624 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18626 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18627 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18628 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18629 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18630 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18631 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18632 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18633 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18634 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18635 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18636 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18637 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18639 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18640 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18641 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18642 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18643 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18644 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18645 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18646 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18647 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18648 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18649 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18650 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18652 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18653 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18654 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18655 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18656 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18657 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18658 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18659 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18660 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18661 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18662 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18663 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18665 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18666 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18667 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18668 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18669 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18670 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18671 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18672 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18673 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18674 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18675 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18676 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18678 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18679 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18680 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18681 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18682 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18683 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18684 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18685 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18686 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18687 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18688 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18689 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18691 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18692 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18693 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18694 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18695 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18696 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18697 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18698 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18699 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18700 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18701 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18702 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18704 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18705 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18706 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18707 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18708 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18709 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18710 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18711 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18712 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18713 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18714 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18715 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18717 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18718 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18719 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18720 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18721 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18722 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18723 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18724 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18725 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18726 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18727 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18728 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18730 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18731 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18732 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18733 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18734 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18735 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18736 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18737 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18738 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18739 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18740 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18741 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18743 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18744 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18745 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18746 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18747 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18748 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18749 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18750 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18751 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18752 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18753 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18754 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18756 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18757 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18758 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18759 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18760 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18761 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18762 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18763 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18764 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18765 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18766 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18767 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18769 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18770 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18771 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18772 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18773 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18774 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18775 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18776 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18777 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18778 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18779 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18780 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18782 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18783 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18784 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18785 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18786 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18787 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18788 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18789 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18790 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18791 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18792 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18793 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18795 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18796 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18797 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18798 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18799 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18800 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18801 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18802 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18803 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18804 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18805 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18806 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18808 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18809 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18810 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18811 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18812 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18813 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18814 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18815 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18816 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18817 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18818 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18819 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18821 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18822 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18823 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18824 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18825 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18826 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18827 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18828 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18829 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18830 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18831 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18832 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18834 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18835 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18836 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18837 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18838 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18839 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18840 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18841 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18842 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18843 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18844 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18845 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18847 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18848 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18849 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18850 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18851 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18852 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18853 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18854 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18855 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18856 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18857 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18858 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18860 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18861 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18862 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18863 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18864 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18865 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18866 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18867 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18868 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18869 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18870 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18871 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18873 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18874 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18875 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18876 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18877 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18878 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18879 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18880 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18881 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18882 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18883 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18884 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18886 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18887 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18888 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18889 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18890 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18891 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18892 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18893 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18894 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18895 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18896 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18897 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18899 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18900 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18901 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18902 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18903 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18904 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18905 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18906 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18907 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18908 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18909 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18910 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18912 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18913 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18914 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18915 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18916 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18917 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18918 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18919 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18920 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18921 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18922 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18923 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18925 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18926 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18927 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18928 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18930 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18931 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18932 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18933 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18934 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18935 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18936 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18937 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18938 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18939 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18940 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18941 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18943 /* The implementation of the FIX instruction is broken on some
18944 assemblers, in that it accepts a precision specifier as well as a
18945 rounding specifier, despite the fact that this is meaningless.
18946 To be more compatible, we accept it as well, though of course it
18947 does not set any bits. */
18948 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18949 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18950 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18951 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18952 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18953 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18954 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18955 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18956 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18957 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18958 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18959 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18960 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18962 /* Instructions that were new with the real FPA, call them V2. */
18964 #define ARM_VARIANT & fpu_fpa_ext_v2
18966 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18967 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18968 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18969 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18970 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18971 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18974 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18976 /* Moves and type conversions. */
18977 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18978 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18979 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18980 cCE("fmstat", ef1fa10, 0, (), noargs),
18981 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
18982 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
18983 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18984 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18985 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18986 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18987 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18988 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18989 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18990 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18992 /* Memory operations. */
18993 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18994 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18995 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18996 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18997 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18998 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18999 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19000 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19001 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19002 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19003 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19004 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19005 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19006 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19007 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19008 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19009 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19010 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19012 /* Monadic operations. */
19013 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19014 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19015 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
19017 /* Dyadic operations. */
19018 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19019 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19020 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19021 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19022 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19023 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19024 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19025 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19026 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19029 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19030 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19031 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19032 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
19034 /* Double precision load/store are still present on single precision
19035 implementations. */
19036 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19037 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19038 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19039 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19040 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19041 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19042 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19043 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19044 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19045 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19048 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19050 /* Moves and type conversions. */
19051 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19052 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19053 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19054 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19055 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19056 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19057 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19058 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19059 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19060 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19061 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19062 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19063 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19065 /* Monadic operations. */
19066 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19067 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19068 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19070 /* Dyadic operations. */
19071 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19072 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19073 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19074 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19075 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19076 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19077 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19078 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19079 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19082 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19083 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19084 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19085 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
19088 #define ARM_VARIANT & fpu_vfp_ext_v2
19090 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19091 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19092 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19093 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
19095 /* Instructions which may belong to either the Neon or VFP instruction sets.
19096 Individual encoder functions perform additional architecture checks. */
19098 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19099 #undef THUMB_VARIANT
19100 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19102 /* These mnemonics are unique to VFP. */
19103 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19104 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
19105 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19106 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19107 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19108 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19109 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19110 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19111 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19112 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19114 /* Mnemonics shared by Neon and VFP. */
19115 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19116 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19117 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19119 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19120 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19122 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19123 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19125 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19126 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19127 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19128 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19129 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19130 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19131 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19132 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19134 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
19135 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
19136 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19137 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
19140 /* NOTE: All VMOV encoding is special-cased! */
19141 NCE(vmov, 0, 1, (VMOV), neon_mov),
19142 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19144 #undef THUMB_VARIANT
19145 #define THUMB_VARIANT & fpu_neon_ext_v1
19147 #define ARM_VARIANT & fpu_neon_ext_v1
19149 /* Data processing with three registers of the same length. */
19150 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19151 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19152 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19153 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19154 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19155 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19156 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19157 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19158 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19159 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19160 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19161 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19162 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19163 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19164 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19165 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19166 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19167 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19168 /* If not immediate, fall back to neon_dyadic_i64_su.
19169 shl_imm should accept I8 I16 I32 I64,
19170 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19171 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19172 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19173 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19174 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
19175 /* Logic ops, types optional & ignored. */
19176 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19177 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19178 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19179 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19180 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19181 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19182 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19183 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19184 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19185 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
19186 /* Bitfield ops, untyped. */
19187 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19188 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19189 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19190 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19191 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19192 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19193 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19194 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19195 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19196 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19197 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19198 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19199 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19200 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19201 back to neon_dyadic_if_su. */
19202 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19203 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19204 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19205 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19206 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19207 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19208 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19209 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19210 /* Comparison. Type I8 I16 I32 F32. */
19211 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19212 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
19213 /* As above, D registers only. */
19214 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19215 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19216 /* Int and float variants, signedness unimportant. */
19217 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19218 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19219 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
19220 /* Add/sub take types I8 I16 I32 I64 F32. */
19221 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19222 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19223 /* vtst takes sizes 8, 16, 32. */
19224 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19225 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19226 /* VMUL takes I8 I16 I32 F32 P8. */
19227 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
19228 /* VQD{R}MULH takes S16 S32. */
19229 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19230 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19231 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19232 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19233 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19234 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19235 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19236 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19237 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19238 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19239 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19240 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19241 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19242 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19243 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19244 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19246 /* Two address, int/float. Types S8 S16 S32 F32. */
19247 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
19248 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19250 /* Data processing with two registers and a shift amount. */
19251 /* Right shifts, and variants with rounding.
19252 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19253 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19254 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19255 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19256 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19257 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19258 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19259 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19260 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19261 /* Shift and insert. Sizes accepted 8 16 32 64. */
19262 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19263 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19264 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19265 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19266 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19267 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19268 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19269 /* Right shift immediate, saturating & narrowing, with rounding variants.
19270 Types accepted S16 S32 S64 U16 U32 U64. */
19271 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19272 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19273 /* As above, unsigned. Types accepted S16 S32 S64. */
19274 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19275 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19276 /* Right shift narrowing. Types accepted I16 I32 I64. */
19277 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19278 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19279 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19280 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
19281 /* CVT with optional immediate for fixed-point variant. */
19282 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
19284 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19285 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
19287 /* Data processing, three registers of different lengths. */
19288 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19289 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19290 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19291 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19292 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19293 /* If not scalar, fall back to neon_dyadic_long.
19294 Vector types as above, scalar types S16 S32 U16 U32. */
19295 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19296 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19297 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19298 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19299 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19300 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19301 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19302 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19303 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19304 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19305 /* Saturating doubling multiplies. Types S16 S32. */
19306 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19307 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19308 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19309 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19310 S16 S32 U16 U32. */
19311 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
19313 /* Extract. Size 8. */
19314 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19315 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
19317 /* Two registers, miscellaneous. */
19318 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19319 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19320 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19321 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19322 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19323 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19324 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19325 /* Vector replicate. Sizes 8 16 32. */
19326 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19327 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
19328 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19329 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19330 /* VMOVN. Types I16 I32 I64. */
19331 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
19332 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19333 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
19334 /* VQMOVUN. Types S16 S32 S64. */
19335 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
19336 /* VZIP / VUZP. Sizes 8 16 32. */
19337 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19338 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19339 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19340 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19341 /* VQABS / VQNEG. Types S8 S16 S32. */
19342 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19343 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19344 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19345 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19346 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19347 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19348 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19349 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19350 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19351 /* Reciprocal estimates. Types U32 F32. */
19352 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19353 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19354 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19355 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19356 /* VCLS. Types S8 S16 S32. */
19357 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19358 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19359 /* VCLZ. Types I8 I16 I32. */
19360 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19361 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19362 /* VCNT. Size 8. */
19363 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19364 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19365 /* Two address, untyped. */
19366 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19367 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19368 /* VTRN. Sizes 8 16 32. */
19369 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19370 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
19372 /* Table lookup. Size 8. */
19373 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19374 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19376 #undef THUMB_VARIANT
19377 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19379 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19381 /* Neon element/structure load/store. */
19382 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19383 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19384 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19385 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19386 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19387 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19388 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19389 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19391 #undef THUMB_VARIANT
19392 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
19394 #define ARM_VARIANT &fpu_vfp_ext_v3xd
19395 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19396 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19397 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19398 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19399 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19400 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19401 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19402 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19403 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19405 #undef THUMB_VARIANT
19406 #define THUMB_VARIANT & fpu_vfp_ext_v3
19408 #define ARM_VARIANT & fpu_vfp_ext_v3
19410 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
19411 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19412 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19413 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19414 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19415 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19416 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19417 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19418 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19421 #define ARM_VARIANT &fpu_vfp_ext_fma
19422 #undef THUMB_VARIANT
19423 #define THUMB_VARIANT &fpu_vfp_ext_fma
19424 /* Mnemonics shared by Neon and VFP. These are included in the
19425 VFP FMA variant; NEON and VFP FMA always includes the NEON
19426 FMA instructions. */
19427 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19428 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19429 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19430 the v form should always be used. */
19431 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19432 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19433 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19434 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19435 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19436 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19438 #undef THUMB_VARIANT
19440 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19442 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19443 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19444 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19445 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19446 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19447 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19448 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19449 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
19452 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19454 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19455 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19456 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19457 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19458 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19459 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19460 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19461 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19462 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19463 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19464 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19465 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19466 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19467 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19468 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19469 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19470 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19471 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19472 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19473 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19474 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19475 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19476 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19477 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19478 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19479 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19480 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
19481 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
19482 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
19483 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19484 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19485 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19486 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19487 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19488 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19489 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19490 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19491 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19492 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19493 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19494 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19495 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19496 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19497 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19498 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19499 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19500 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19501 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19502 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19503 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19504 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19505 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19506 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19507 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19508 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19509 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19510 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19511 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19512 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19513 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19514 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19515 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19516 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19517 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19518 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19519 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19520 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19521 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19522 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19523 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19524 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19525 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19526 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19527 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19528 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19529 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19530 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19531 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19532 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19533 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19534 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19535 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19536 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19537 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19538 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19539 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19540 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19541 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19542 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19543 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19544 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19545 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19546 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19547 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19548 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19549 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19550 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19551 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19552 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19553 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19554 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19555 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19556 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19557 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19558 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19559 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19560 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19561 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19562 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19563 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19564 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19565 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19566 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19567 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19568 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19569 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19570 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19571 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19572 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19573 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19574 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19575 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19576 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19577 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19578 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19579 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19580 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19581 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19582 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19583 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19584 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19585 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19586 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19587 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19588 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19589 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19590 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19591 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19592 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19593 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19594 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19595 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19596 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19597 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19598 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19599 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19600 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19601 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19602 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19603 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19604 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19605 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19606 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19607 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19608 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19609 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19610 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19611 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19612 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19613 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19614 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19615 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
19618 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19620 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19621 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19622 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19623 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19624 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19625 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19626 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19627 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19628 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19629 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19630 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19631 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19632 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19633 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19634 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19635 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19636 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19637 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19638 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19639 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19640 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19641 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19642 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19643 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19644 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19645 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19646 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19647 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19648 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19649 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19650 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19651 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19652 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19653 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19654 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19655 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19656 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19657 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19658 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19659 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19660 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19661 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19662 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19663 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19664 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19665 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19666 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19667 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19668 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19669 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19670 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19671 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19672 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19673 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19674 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19675 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19676 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19679 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19681 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19682 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19683 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19684 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19685 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19686 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19687 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19688 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19689 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19690 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19691 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19692 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19693 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19694 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19695 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
19696 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
19697 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
19698 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
19699 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
19700 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
19701 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
19702 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
19703 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
19704 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
19705 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19706 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19707 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19708 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19709 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19710 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
19711 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19712 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19713 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19714 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19715 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
19716 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
19717 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
19718 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
19719 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
19720 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
19721 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19722 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19723 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
19724 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
19725 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19726 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19727 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19728 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19729 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19730 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19731 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19732 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19733 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19734 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19735 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19736 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19737 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19738 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19739 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19740 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19741 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19742 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19743 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19744 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19745 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19746 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19747 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19748 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19749 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19750 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19751 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19752 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19753 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19754 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19755 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19756 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19759 #undef THUMB_VARIANT
19786 /* MD interface: bits in the object file. */
19788 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19789 for use in the a.out file, and stores them in the array pointed to by buf.
19790 This knows about the endian-ness of the target machine and does
19791 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19792 2 (short) and 4 (long) Floating numbers are put out as a series of
19793 LITTLENUMS (shorts, here at least). */
19796 md_number_to_chars (char * buf, valueT val, int n)
19798 if (target_big_endian)
19799 number_to_chars_bigendian (buf, val, n);
19801 number_to_chars_littleendian (buf, val, n);
19805 md_chars_to_number (char * buf, int n)
19808 unsigned char * where = (unsigned char *) buf;
19810 if (target_big_endian)
19815 result |= (*where++ & 255);
19823 result |= (where[n] & 255);
19830 /* MD interface: Sections. */
19832 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19833 that an rs_machine_dependent frag may reach. */
19836 arm_frag_max_var (fragS *fragp)
19838 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19839 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19841 Note that we generate relaxable instructions even for cases that don't
19842 really need it, like an immediate that's a trivial constant. So we're
19843 overestimating the instruction size for some of those cases. Rather
19844 than putting more intelligence here, it would probably be better to
19845 avoid generating a relaxation frag in the first place when it can be
19846 determined up front that a short instruction will suffice. */
19848 gas_assert (fragp->fr_type == rs_machine_dependent);
19852 /* Estimate the size of a frag before relaxing. Assume everything fits in
19856 md_estimate_size_before_relax (fragS * fragp,
19857 segT segtype ATTRIBUTE_UNUSED)
19863 /* Convert a machine dependent frag. */
19866 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19868 unsigned long insn;
19869 unsigned long old_op;
19877 buf = fragp->fr_literal + fragp->fr_fix;
19879 old_op = bfd_get_16(abfd, buf);
19880 if (fragp->fr_symbol)
19882 exp.X_op = O_symbol;
19883 exp.X_add_symbol = fragp->fr_symbol;
19887 exp.X_op = O_constant;
19889 exp.X_add_number = fragp->fr_offset;
19890 opcode = fragp->fr_subtype;
19893 case T_MNEM_ldr_pc:
19894 case T_MNEM_ldr_pc2:
19895 case T_MNEM_ldr_sp:
19896 case T_MNEM_str_sp:
19903 if (fragp->fr_var == 4)
19905 insn = THUMB_OP32 (opcode);
19906 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19908 insn |= (old_op & 0x700) << 4;
19912 insn |= (old_op & 7) << 12;
19913 insn |= (old_op & 0x38) << 13;
19915 insn |= 0x00000c00;
19916 put_thumb32_insn (buf, insn);
19917 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19921 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19923 pc_rel = (opcode == T_MNEM_ldr_pc2);
19926 if (fragp->fr_var == 4)
19928 insn = THUMB_OP32 (opcode);
19929 insn |= (old_op & 0xf0) << 4;
19930 put_thumb32_insn (buf, insn);
19931 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19935 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19936 exp.X_add_number -= 4;
19944 if (fragp->fr_var == 4)
19946 int r0off = (opcode == T_MNEM_mov
19947 || opcode == T_MNEM_movs) ? 0 : 8;
19948 insn = THUMB_OP32 (opcode);
19949 insn = (insn & 0xe1ffffff) | 0x10000000;
19950 insn |= (old_op & 0x700) << r0off;
19951 put_thumb32_insn (buf, insn);
19952 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19956 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19961 if (fragp->fr_var == 4)
19963 insn = THUMB_OP32(opcode);
19964 put_thumb32_insn (buf, insn);
19965 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19968 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19972 if (fragp->fr_var == 4)
19974 insn = THUMB_OP32(opcode);
19975 insn |= (old_op & 0xf00) << 14;
19976 put_thumb32_insn (buf, insn);
19977 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19980 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19983 case T_MNEM_add_sp:
19984 case T_MNEM_add_pc:
19985 case T_MNEM_inc_sp:
19986 case T_MNEM_dec_sp:
19987 if (fragp->fr_var == 4)
19989 /* ??? Choose between add and addw. */
19990 insn = THUMB_OP32 (opcode);
19991 insn |= (old_op & 0xf0) << 4;
19992 put_thumb32_insn (buf, insn);
19993 if (opcode == T_MNEM_add_pc)
19994 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19996 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19999 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20007 if (fragp->fr_var == 4)
20009 insn = THUMB_OP32 (opcode);
20010 insn |= (old_op & 0xf0) << 4;
20011 insn |= (old_op & 0xf) << 16;
20012 put_thumb32_insn (buf, insn);
20013 if (insn & (1 << 20))
20014 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20016 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20019 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20025 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
20026 (enum bfd_reloc_code_real) reloc_type);
20027 fixp->fx_file = fragp->fr_file;
20028 fixp->fx_line = fragp->fr_line;
20029 fragp->fr_fix += fragp->fr_var;
20032 /* Return the size of a relaxable immediate operand instruction.
20033 SHIFT and SIZE specify the form of the allowable immediate. */
20035 relax_immediate (fragS *fragp, int size, int shift)
20041 /* ??? Should be able to do better than this. */
20042 if (fragp->fr_symbol)
20045 low = (1 << shift) - 1;
20046 mask = (1 << (shift + size)) - (1 << shift);
20047 offset = fragp->fr_offset;
20048 /* Force misaligned offsets to 32-bit variant. */
20051 if (offset & ~mask)
20056 /* Get the address of a symbol during relaxation. */
20058 relaxed_symbol_addr (fragS *fragp, long stretch)
20064 sym = fragp->fr_symbol;
20065 sym_frag = symbol_get_frag (sym);
20066 know (S_GET_SEGMENT (sym) != absolute_section
20067 || sym_frag == &zero_address_frag);
20068 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20070 /* If frag has yet to be reached on this pass, assume it will
20071 move by STRETCH just as we did. If this is not so, it will
20072 be because some frag between grows, and that will force
20076 && sym_frag->relax_marker != fragp->relax_marker)
20080 /* Adjust stretch for any alignment frag. Note that if have
20081 been expanding the earlier code, the symbol may be
20082 defined in what appears to be an earlier frag. FIXME:
20083 This doesn't handle the fr_subtype field, which specifies
20084 a maximum number of bytes to skip when doing an
20086 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20088 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20091 stretch = - ((- stretch)
20092 & ~ ((1 << (int) f->fr_offset) - 1));
20094 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20106 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20109 relax_adr (fragS *fragp, asection *sec, long stretch)
20114 /* Assume worst case for symbols not known to be in the same section. */
20115 if (fragp->fr_symbol == NULL
20116 || !S_IS_DEFINED (fragp->fr_symbol)
20117 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20118 || S_IS_WEAK (fragp->fr_symbol))
20121 val = relaxed_symbol_addr (fragp, stretch);
20122 addr = fragp->fr_address + fragp->fr_fix;
20123 addr = (addr + 4) & ~3;
20124 /* Force misaligned targets to 32-bit variant. */
20128 if (val < 0 || val > 1020)
20133 /* Return the size of a relaxable add/sub immediate instruction. */
20135 relax_addsub (fragS *fragp, asection *sec)
20140 buf = fragp->fr_literal + fragp->fr_fix;
20141 op = bfd_get_16(sec->owner, buf);
20142 if ((op & 0xf) == ((op >> 4) & 0xf))
20143 return relax_immediate (fragp, 8, 0);
20145 return relax_immediate (fragp, 3, 0);
20149 /* Return the size of a relaxable branch instruction. BITS is the
20150 size of the offset field in the narrow instruction. */
20153 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
20159 /* Assume worst case for symbols not known to be in the same section. */
20160 if (!S_IS_DEFINED (fragp->fr_symbol)
20161 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20162 || S_IS_WEAK (fragp->fr_symbol))
20166 if (S_IS_DEFINED (fragp->fr_symbol)
20167 && ARM_IS_FUNC (fragp->fr_symbol))
20170 /* PR 12532. Global symbols with default visibility might
20171 be preempted, so do not relax relocations to them. */
20172 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
20173 && (! S_IS_LOCAL (fragp->fr_symbol)))
20177 val = relaxed_symbol_addr (fragp, stretch);
20178 addr = fragp->fr_address + fragp->fr_fix + 4;
20181 /* Offset is a signed value *2 */
20183 if (val >= limit || val < -limit)
20189 /* Relax a machine dependent frag. This returns the amount by which
20190 the current size of the frag should change. */
20193 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
20198 oldsize = fragp->fr_var;
20199 switch (fragp->fr_subtype)
20201 case T_MNEM_ldr_pc2:
20202 newsize = relax_adr (fragp, sec, stretch);
20204 case T_MNEM_ldr_pc:
20205 case T_MNEM_ldr_sp:
20206 case T_MNEM_str_sp:
20207 newsize = relax_immediate (fragp, 8, 2);
20211 newsize = relax_immediate (fragp, 5, 2);
20215 newsize = relax_immediate (fragp, 5, 1);
20219 newsize = relax_immediate (fragp, 5, 0);
20222 newsize = relax_adr (fragp, sec, stretch);
20228 newsize = relax_immediate (fragp, 8, 0);
20231 newsize = relax_branch (fragp, sec, 11, stretch);
20234 newsize = relax_branch (fragp, sec, 8, stretch);
20236 case T_MNEM_add_sp:
20237 case T_MNEM_add_pc:
20238 newsize = relax_immediate (fragp, 8, 2);
20240 case T_MNEM_inc_sp:
20241 case T_MNEM_dec_sp:
20242 newsize = relax_immediate (fragp, 7, 2);
20248 newsize = relax_addsub (fragp, sec);
20254 fragp->fr_var = newsize;
20255 /* Freeze wide instructions that are at or before the same location as
20256 in the previous pass. This avoids infinite loops.
20257 Don't freeze them unconditionally because targets may be artificially
20258 misaligned by the expansion of preceding frags. */
20259 if (stretch <= 0 && newsize > 2)
20261 md_convert_frag (sec->owner, sec, fragp);
20265 return newsize - oldsize;
20268 /* Round up a section size to the appropriate boundary. */
20271 md_section_align (segT segment ATTRIBUTE_UNUSED,
20274 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20275 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20277 /* For a.out, force the section size to be aligned. If we don't do
20278 this, BFD will align it for us, but it will not write out the
20279 final bytes of the section. This may be a bug in BFD, but it is
20280 easier to fix it here since that is how the other a.out targets
20284 align = bfd_get_section_alignment (stdoutput, segment);
20285 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20292 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20293 of an rs_align_code fragment. */
20296 arm_handle_align (fragS * fragP)
20298 static char const arm_noop[2][2][4] =
20301 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20302 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20305 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20306 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20309 static char const thumb_noop[2][2][2] =
20312 {0xc0, 0x46}, /* LE */
20313 {0x46, 0xc0}, /* BE */
20316 {0x00, 0xbf}, /* LE */
20317 {0xbf, 0x00} /* BE */
20320 static char const wide_thumb_noop[2][4] =
20321 { /* Wide Thumb-2 */
20322 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20323 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20326 unsigned bytes, fix, noop_size;
20329 const char *narrow_noop = NULL;
20334 if (fragP->fr_type != rs_align_code)
20337 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20338 p = fragP->fr_literal + fragP->fr_fix;
20341 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20342 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
20344 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
20346 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
20348 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
20350 narrow_noop = thumb_noop[1][target_big_endian];
20351 noop = wide_thumb_noop[target_big_endian];
20354 noop = thumb_noop[0][target_big_endian];
20362 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
20363 [target_big_endian];
20370 fragP->fr_var = noop_size;
20372 if (bytes & (noop_size - 1))
20374 fix = bytes & (noop_size - 1);
20376 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20378 memset (p, 0, fix);
20385 if (bytes & noop_size)
20387 /* Insert a narrow noop. */
20388 memcpy (p, narrow_noop, noop_size);
20390 bytes -= noop_size;
20394 /* Use wide noops for the remainder */
20398 while (bytes >= noop_size)
20400 memcpy (p, noop, noop_size);
20402 bytes -= noop_size;
20406 fragP->fr_fix += fix;
20409 /* Called from md_do_align. Used to create an alignment
20410 frag in a code section. */
20413 arm_frag_align_code (int n, int max)
20417 /* We assume that there will never be a requirement
20418 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20419 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
20424 _("alignments greater than %d bytes not supported in .text sections."),
20425 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20426 as_fatal ("%s", err_msg);
20429 p = frag_var (rs_align_code,
20430 MAX_MEM_FOR_RS_ALIGN_CODE,
20432 (relax_substateT) max,
20439 /* Perform target specific initialisation of a frag.
20440 Note - despite the name this initialisation is not done when the frag
20441 is created, but only when its type is assigned. A frag can be created
20442 and used a long time before its type is set, so beware of assuming that
20443 this initialisationis performed first. */
20447 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20449 /* Record whether this frag is in an ARM or a THUMB area. */
20450 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20453 #else /* OBJ_ELF is defined. */
20455 arm_init_frag (fragS * fragP, int max_chars)
20457 /* If the current ARM vs THUMB mode has not already
20458 been recorded into this frag then do so now. */
20459 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20461 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20463 /* Record a mapping symbol for alignment frags. We will delete this
20464 later if the alignment ends up empty. */
20465 switch (fragP->fr_type)
20468 case rs_align_test:
20470 mapping_state_2 (MAP_DATA, max_chars);
20472 case rs_align_code:
20473 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20481 /* When we change sections we need to issue a new mapping symbol. */
20484 arm_elf_change_section (void)
20486 /* Link an unlinked unwind index table section to the .text section. */
20487 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20488 && elf_linked_to_section (now_seg) == NULL)
20489 elf_linked_to_section (now_seg) = text_section;
20493 arm_elf_section_type (const char * str, size_t len)
20495 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20496 return SHT_ARM_EXIDX;
20501 /* Code to deal with unwinding tables. */
20503 static void add_unwind_adjustsp (offsetT);
20505 /* Generate any deferred unwind frame offset. */
20508 flush_pending_unwind (void)
20512 offset = unwind.pending_offset;
20513 unwind.pending_offset = 0;
20515 add_unwind_adjustsp (offset);
20518 /* Add an opcode to this list for this function. Two-byte opcodes should
20519 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20523 add_unwind_opcode (valueT op, int length)
20525 /* Add any deferred stack adjustment. */
20526 if (unwind.pending_offset)
20527 flush_pending_unwind ();
20529 unwind.sp_restored = 0;
20531 if (unwind.opcode_count + length > unwind.opcode_alloc)
20533 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20534 if (unwind.opcodes)
20535 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
20536 unwind.opcode_alloc);
20538 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
20543 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20545 unwind.opcode_count++;
20549 /* Add unwind opcodes to adjust the stack pointer. */
20552 add_unwind_adjustsp (offsetT offset)
20556 if (offset > 0x200)
20558 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20563 /* Long form: 0xb2, uleb128. */
20564 /* This might not fit in a word so add the individual bytes,
20565 remembering the list is built in reverse order. */
20566 o = (valueT) ((offset - 0x204) >> 2);
20568 add_unwind_opcode (0, 1);
20570 /* Calculate the uleb128 encoding of the offset. */
20574 bytes[n] = o & 0x7f;
20580 /* Add the insn. */
20582 add_unwind_opcode (bytes[n - 1], 1);
20583 add_unwind_opcode (0xb2, 1);
20585 else if (offset > 0x100)
20587 /* Two short opcodes. */
20588 add_unwind_opcode (0x3f, 1);
20589 op = (offset - 0x104) >> 2;
20590 add_unwind_opcode (op, 1);
20592 else if (offset > 0)
20594 /* Short opcode. */
20595 op = (offset - 4) >> 2;
20596 add_unwind_opcode (op, 1);
20598 else if (offset < 0)
20601 while (offset > 0x100)
20603 add_unwind_opcode (0x7f, 1);
20606 op = ((offset - 4) >> 2) | 0x40;
20607 add_unwind_opcode (op, 1);
20611 /* Finish the list of unwind opcodes for this function. */
20613 finish_unwind_opcodes (void)
20617 if (unwind.fp_used)
20619 /* Adjust sp as necessary. */
20620 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20621 flush_pending_unwind ();
20623 /* After restoring sp from the frame pointer. */
20624 op = 0x90 | unwind.fp_reg;
20625 add_unwind_opcode (op, 1);
20628 flush_pending_unwind ();
20632 /* Start an exception table entry. If idx is nonzero this is an index table
20636 start_unwind_section (const segT text_seg, int idx)
20638 const char * text_name;
20639 const char * prefix;
20640 const char * prefix_once;
20641 const char * group_name;
20645 size_t sec_name_len;
20652 prefix = ELF_STRING_ARM_unwind;
20653 prefix_once = ELF_STRING_ARM_unwind_once;
20654 type = SHT_ARM_EXIDX;
20658 prefix = ELF_STRING_ARM_unwind_info;
20659 prefix_once = ELF_STRING_ARM_unwind_info_once;
20660 type = SHT_PROGBITS;
20663 text_name = segment_name (text_seg);
20664 if (streq (text_name, ".text"))
20667 if (strncmp (text_name, ".gnu.linkonce.t.",
20668 strlen (".gnu.linkonce.t.")) == 0)
20670 prefix = prefix_once;
20671 text_name += strlen (".gnu.linkonce.t.");
20674 prefix_len = strlen (prefix);
20675 text_len = strlen (text_name);
20676 sec_name_len = prefix_len + text_len;
20677 sec_name = (char *) xmalloc (sec_name_len + 1);
20678 memcpy (sec_name, prefix, prefix_len);
20679 memcpy (sec_name + prefix_len, text_name, text_len);
20680 sec_name[prefix_len + text_len] = '\0';
20686 /* Handle COMDAT group. */
20687 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20689 group_name = elf_group_name (text_seg);
20690 if (group_name == NULL)
20692 as_bad (_("Group section `%s' has no group signature"),
20693 segment_name (text_seg));
20694 ignore_rest_of_line ();
20697 flags |= SHF_GROUP;
20701 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20703 /* Set the section link for index tables. */
20705 elf_linked_to_section (now_seg) = text_seg;
20709 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20710 personality routine data. Returns zero, or the index table value for
20711 and inline entry. */
20714 create_unwind_entry (int have_data)
20719 /* The current word of data. */
20721 /* The number of bytes left in this word. */
20724 finish_unwind_opcodes ();
20726 /* Remember the current text section. */
20727 unwind.saved_seg = now_seg;
20728 unwind.saved_subseg = now_subseg;
20730 start_unwind_section (now_seg, 0);
20732 if (unwind.personality_routine == NULL)
20734 if (unwind.personality_index == -2)
20737 as_bad (_("handlerdata in cantunwind frame"));
20738 return 1; /* EXIDX_CANTUNWIND. */
20741 /* Use a default personality routine if none is specified. */
20742 if (unwind.personality_index == -1)
20744 if (unwind.opcode_count > 3)
20745 unwind.personality_index = 1;
20747 unwind.personality_index = 0;
20750 /* Space for the personality routine entry. */
20751 if (unwind.personality_index == 0)
20753 if (unwind.opcode_count > 3)
20754 as_bad (_("too many unwind opcodes for personality routine 0"));
20758 /* All the data is inline in the index table. */
20761 while (unwind.opcode_count > 0)
20763 unwind.opcode_count--;
20764 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20768 /* Pad with "finish" opcodes. */
20770 data = (data << 8) | 0xb0;
20777 /* We get two opcodes "free" in the first word. */
20778 size = unwind.opcode_count - 2;
20782 gas_assert (unwind.personality_index == -1);
20784 /* An extra byte is required for the opcode count. */
20785 size = unwind.opcode_count + 1;
20788 size = (size + 3) >> 2;
20790 as_bad (_("too many unwind opcodes"));
20792 frag_align (2, 0, 0);
20793 record_alignment (now_seg, 2);
20794 unwind.table_entry = expr_build_dot ();
20796 /* Allocate the table entry. */
20797 ptr = frag_more ((size << 2) + 4);
20798 /* PR 13449: Zero the table entries in case some of them are not used. */
20799 memset (ptr, 0, (size << 2) + 4);
20800 where = frag_now_fix () - ((size << 2) + 4);
20802 switch (unwind.personality_index)
20805 /* ??? Should this be a PLT generating relocation? */
20806 /* Custom personality routine. */
20807 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20808 BFD_RELOC_ARM_PREL31);
20813 /* Set the first byte to the number of additional words. */
20814 data = size > 0 ? size - 1 : 0;
20818 /* ABI defined personality routines. */
20820 /* Three opcodes bytes are packed into the first word. */
20827 /* The size and first two opcode bytes go in the first word. */
20828 data = ((0x80 + unwind.personality_index) << 8) | size;
20833 /* Should never happen. */
20837 /* Pack the opcodes into words (MSB first), reversing the list at the same
20839 while (unwind.opcode_count > 0)
20843 md_number_to_chars (ptr, data, 4);
20848 unwind.opcode_count--;
20850 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20853 /* Finish off the last word. */
20856 /* Pad with "finish" opcodes. */
20858 data = (data << 8) | 0xb0;
20860 md_number_to_chars (ptr, data, 4);
20865 /* Add an empty descriptor if there is no user-specified data. */
20866 ptr = frag_more (4);
20867 md_number_to_chars (ptr, 0, 4);
20874 /* Initialize the DWARF-2 unwind information for this procedure. */
20877 tc_arm_frame_initial_instructions (void)
20879 cfi_add_CFA_def_cfa (REG_SP, 0);
20881 #endif /* OBJ_ELF */
20883 /* Convert REGNAME to a DWARF-2 register number. */
20886 tc_arm_regname_to_dw2regnum (char *regname)
20888 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20898 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20902 exp.X_op = O_secrel;
20903 exp.X_add_symbol = symbol;
20904 exp.X_add_number = 0;
20905 emit_expr (&exp, size);
20909 /* MD interface: Symbol and relocation handling. */
20911 /* Return the address within the segment that a PC-relative fixup is
20912 relative to. For ARM, PC-relative fixups applied to instructions
20913 are generally relative to the location of the fixup plus 8 bytes.
20914 Thumb branches are offset by 4, and Thumb loads relative to PC
20915 require special handling. */
20918 md_pcrel_from_section (fixS * fixP, segT seg)
20920 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20922 /* If this is pc-relative and we are going to emit a relocation
20923 then we just want to put out any pipeline compensation that the linker
20924 will need. Otherwise we want to use the calculated base.
20925 For WinCE we skip the bias for externals as well, since this
20926 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20928 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20929 || (arm_force_relocation (fixP)
20931 && !S_IS_EXTERNAL (fixP->fx_addsy)
20937 switch (fixP->fx_r_type)
20939 /* PC relative addressing on the Thumb is slightly odd as the
20940 bottom two bits of the PC are forced to zero for the
20941 calculation. This happens *after* application of the
20942 pipeline offset. However, Thumb adrl already adjusts for
20943 this, so we need not do it again. */
20944 case BFD_RELOC_ARM_THUMB_ADD:
20947 case BFD_RELOC_ARM_THUMB_OFFSET:
20948 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20949 case BFD_RELOC_ARM_T32_ADD_PC12:
20950 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20951 return (base + 4) & ~3;
20953 /* Thumb branches are simply offset by +4. */
20954 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20955 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20956 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20957 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20958 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20961 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20963 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20964 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20965 && ARM_IS_FUNC (fixP->fx_addsy)
20966 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20967 base = fixP->fx_where + fixP->fx_frag->fr_address;
20970 /* BLX is like branches above, but forces the low two bits of PC to
20972 case BFD_RELOC_THUMB_PCREL_BLX:
20974 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20975 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20976 && THUMB_IS_FUNC (fixP->fx_addsy)
20977 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20978 base = fixP->fx_where + fixP->fx_frag->fr_address;
20979 return (base + 4) & ~3;
20981 /* ARM mode branches are offset by +8. However, the Windows CE
20982 loader expects the relocation not to take this into account. */
20983 case BFD_RELOC_ARM_PCREL_BLX:
20985 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20986 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20987 && ARM_IS_FUNC (fixP->fx_addsy)
20988 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20989 base = fixP->fx_where + fixP->fx_frag->fr_address;
20992 case BFD_RELOC_ARM_PCREL_CALL:
20994 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20995 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20996 && THUMB_IS_FUNC (fixP->fx_addsy)
20997 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20998 base = fixP->fx_where + fixP->fx_frag->fr_address;
21001 case BFD_RELOC_ARM_PCREL_BRANCH:
21002 case BFD_RELOC_ARM_PCREL_JUMP:
21003 case BFD_RELOC_ARM_PLT32:
21005 /* When handling fixups immediately, because we have already
21006 discovered the value of a symbol, or the address of the frag involved
21007 we must account for the offset by +8, as the OS loader will never see the reloc.
21008 see fixup_segment() in write.c
21009 The S_IS_EXTERNAL test handles the case of global symbols.
21010 Those need the calculated base, not just the pipe compensation the linker will need. */
21012 && fixP->fx_addsy != NULL
21013 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21014 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21022 /* ARM mode loads relative to PC are also offset by +8. Unlike
21023 branches, the Windows CE loader *does* expect the relocation
21024 to take this into account. */
21025 case BFD_RELOC_ARM_OFFSET_IMM:
21026 case BFD_RELOC_ARM_OFFSET_IMM8:
21027 case BFD_RELOC_ARM_HWLITERAL:
21028 case BFD_RELOC_ARM_LITERAL:
21029 case BFD_RELOC_ARM_CP_OFF_IMM:
21033 /* Other PC-relative relocations are un-offset. */
21039 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21040 Otherwise we have no need to default values of symbols. */
21043 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
21046 if (name[0] == '_' && name[1] == 'G'
21047 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21051 if (symbol_find (name))
21052 as_bad (_("GOT already in the symbol table"));
21054 GOT_symbol = symbol_new (name, undefined_section,
21055 (valueT) 0, & zero_address_frag);
21065 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21066 computed as two separate immediate values, added together. We
21067 already know that this value cannot be computed by just one ARM
21070 static unsigned int
21071 validate_immediate_twopart (unsigned int val,
21072 unsigned int * highpart)
21077 for (i = 0; i < 32; i += 2)
21078 if (((a = rotate_left (val, i)) & 0xff) != 0)
21084 * highpart = (a >> 8) | ((i + 24) << 7);
21086 else if (a & 0xff0000)
21088 if (a & 0xff000000)
21090 * highpart = (a >> 16) | ((i + 16) << 7);
21094 gas_assert (a & 0xff000000);
21095 * highpart = (a >> 24) | ((i + 8) << 7);
21098 return (a & 0xff) | (i << 7);
21105 validate_offset_imm (unsigned int val, int hwse)
21107 if ((hwse && val > 255) || val > 4095)
21112 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21113 negative immediate constant by altering the instruction. A bit of
21118 by inverting the second operand, and
21121 by negating the second operand. */
21124 negate_data_op (unsigned long * instruction,
21125 unsigned long value)
21128 unsigned long negated, inverted;
21130 negated = encode_arm_immediate (-value);
21131 inverted = encode_arm_immediate (~value);
21133 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21136 /* First negates. */
21137 case OPCODE_SUB: /* ADD <-> SUB */
21138 new_inst = OPCODE_ADD;
21143 new_inst = OPCODE_SUB;
21147 case OPCODE_CMP: /* CMP <-> CMN */
21148 new_inst = OPCODE_CMN;
21153 new_inst = OPCODE_CMP;
21157 /* Now Inverted ops. */
21158 case OPCODE_MOV: /* MOV <-> MVN */
21159 new_inst = OPCODE_MVN;
21164 new_inst = OPCODE_MOV;
21168 case OPCODE_AND: /* AND <-> BIC */
21169 new_inst = OPCODE_BIC;
21174 new_inst = OPCODE_AND;
21178 case OPCODE_ADC: /* ADC <-> SBC */
21179 new_inst = OPCODE_SBC;
21184 new_inst = OPCODE_ADC;
21188 /* We cannot do anything. */
21193 if (value == (unsigned) FAIL)
21196 *instruction &= OPCODE_MASK;
21197 *instruction |= new_inst << DATA_OP_SHIFT;
21201 /* Like negate_data_op, but for Thumb-2. */
21203 static unsigned int
21204 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
21208 unsigned int negated, inverted;
21210 negated = encode_thumb32_immediate (-value);
21211 inverted = encode_thumb32_immediate (~value);
21213 rd = (*instruction >> 8) & 0xf;
21214 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21217 /* ADD <-> SUB. Includes CMP <-> CMN. */
21218 case T2_OPCODE_SUB:
21219 new_inst = T2_OPCODE_ADD;
21223 case T2_OPCODE_ADD:
21224 new_inst = T2_OPCODE_SUB;
21228 /* ORR <-> ORN. Includes MOV <-> MVN. */
21229 case T2_OPCODE_ORR:
21230 new_inst = T2_OPCODE_ORN;
21234 case T2_OPCODE_ORN:
21235 new_inst = T2_OPCODE_ORR;
21239 /* AND <-> BIC. TST has no inverted equivalent. */
21240 case T2_OPCODE_AND:
21241 new_inst = T2_OPCODE_BIC;
21248 case T2_OPCODE_BIC:
21249 new_inst = T2_OPCODE_AND;
21254 case T2_OPCODE_ADC:
21255 new_inst = T2_OPCODE_SBC;
21259 case T2_OPCODE_SBC:
21260 new_inst = T2_OPCODE_ADC;
21264 /* We cannot do anything. */
21269 if (value == (unsigned int)FAIL)
21272 *instruction &= T2_OPCODE_MASK;
21273 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21277 /* Read a 32-bit thumb instruction from buf. */
21278 static unsigned long
21279 get_thumb32_insn (char * buf)
21281 unsigned long insn;
21282 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21283 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21289 /* We usually want to set the low bit on the address of thumb function
21290 symbols. In particular .word foo - . should have the low bit set.
21291 Generic code tries to fold the difference of two symbols to
21292 a constant. Prevent this and force a relocation when the first symbols
21293 is a thumb function. */
21296 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21298 if (op == O_subtract
21299 && l->X_op == O_symbol
21300 && r->X_op == O_symbol
21301 && THUMB_IS_FUNC (l->X_add_symbol))
21303 l->X_op = O_subtract;
21304 l->X_op_symbol = r->X_add_symbol;
21305 l->X_add_number -= r->X_add_number;
21309 /* Process as normal. */
21313 /* Encode Thumb2 unconditional branches and calls. The encoding
21314 for the 2 are identical for the immediate values. */
21317 encode_thumb2_b_bl_offset (char * buf, offsetT value)
21319 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21322 addressT S, I1, I2, lo, hi;
21324 S = (value >> 24) & 0x01;
21325 I1 = (value >> 23) & 0x01;
21326 I2 = (value >> 22) & 0x01;
21327 hi = (value >> 12) & 0x3ff;
21328 lo = (value >> 1) & 0x7ff;
21329 newval = md_chars_to_number (buf, THUMB_SIZE);
21330 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21331 newval |= (S << 10) | hi;
21332 newval2 &= ~T2I1I2MASK;
21333 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21334 md_number_to_chars (buf, newval, THUMB_SIZE);
21335 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21339 md_apply_fix (fixS * fixP,
21343 offsetT value = * valP;
21345 unsigned int newimm;
21346 unsigned long temp;
21348 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
21350 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
21352 /* Note whether this will delete the relocation. */
21354 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21357 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21358 consistency with the behaviour on 32-bit hosts. Remember value
21360 value &= 0xffffffff;
21361 value ^= 0x80000000;
21362 value -= 0x80000000;
21365 fixP->fx_addnumber = value;
21367 /* Same treatment for fixP->fx_offset. */
21368 fixP->fx_offset &= 0xffffffff;
21369 fixP->fx_offset ^= 0x80000000;
21370 fixP->fx_offset -= 0x80000000;
21372 switch (fixP->fx_r_type)
21374 case BFD_RELOC_NONE:
21375 /* This will need to go in the object file. */
21379 case BFD_RELOC_ARM_IMMEDIATE:
21380 /* We claim that this fixup has been processed here,
21381 even if in fact we generate an error because we do
21382 not have a reloc for it, so tc_gen_reloc will reject it. */
21385 if (fixP->fx_addsy)
21387 const char *msg = 0;
21389 if (! S_IS_DEFINED (fixP->fx_addsy))
21390 msg = _("undefined symbol %s used as an immediate value");
21391 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21392 msg = _("symbol %s is in a different section");
21393 else if (S_IS_WEAK (fixP->fx_addsy))
21394 msg = _("symbol %s is weak and may be overridden later");
21398 as_bad_where (fixP->fx_file, fixP->fx_line,
21399 msg, S_GET_NAME (fixP->fx_addsy));
21404 temp = md_chars_to_number (buf, INSN_SIZE);
21406 /* If the offset is negative, we should use encoding A2 for ADR. */
21407 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21408 newimm = negate_data_op (&temp, value);
21411 newimm = encode_arm_immediate (value);
21413 /* If the instruction will fail, see if we can fix things up by
21414 changing the opcode. */
21415 if (newimm == (unsigned int) FAIL)
21416 newimm = negate_data_op (&temp, value);
21419 if (newimm == (unsigned int) FAIL)
21421 as_bad_where (fixP->fx_file, fixP->fx_line,
21422 _("invalid constant (%lx) after fixup"),
21423 (unsigned long) value);
21427 newimm |= (temp & 0xfffff000);
21428 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21431 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21433 unsigned int highpart = 0;
21434 unsigned int newinsn = 0xe1a00000; /* nop. */
21436 if (fixP->fx_addsy)
21438 const char *msg = 0;
21440 if (! S_IS_DEFINED (fixP->fx_addsy))
21441 msg = _("undefined symbol %s used as an immediate value");
21442 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21443 msg = _("symbol %s is in a different section");
21444 else if (S_IS_WEAK (fixP->fx_addsy))
21445 msg = _("symbol %s is weak and may be overridden later");
21449 as_bad_where (fixP->fx_file, fixP->fx_line,
21450 msg, S_GET_NAME (fixP->fx_addsy));
21455 newimm = encode_arm_immediate (value);
21456 temp = md_chars_to_number (buf, INSN_SIZE);
21458 /* If the instruction will fail, see if we can fix things up by
21459 changing the opcode. */
21460 if (newimm == (unsigned int) FAIL
21461 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21463 /* No ? OK - try using two ADD instructions to generate
21465 newimm = validate_immediate_twopart (value, & highpart);
21467 /* Yes - then make sure that the second instruction is
21469 if (newimm != (unsigned int) FAIL)
21471 /* Still No ? Try using a negated value. */
21472 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21473 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21474 /* Otherwise - give up. */
21477 as_bad_where (fixP->fx_file, fixP->fx_line,
21478 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21483 /* Replace the first operand in the 2nd instruction (which
21484 is the PC) with the destination register. We have
21485 already added in the PC in the first instruction and we
21486 do not want to do it again. */
21487 newinsn &= ~ 0xf0000;
21488 newinsn |= ((newinsn & 0x0f000) << 4);
21491 newimm |= (temp & 0xfffff000);
21492 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21494 highpart |= (newinsn & 0xfffff000);
21495 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21499 case BFD_RELOC_ARM_OFFSET_IMM:
21500 if (!fixP->fx_done && seg->use_rela_p)
21503 case BFD_RELOC_ARM_LITERAL:
21509 if (validate_offset_imm (value, 0) == FAIL)
21511 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21512 as_bad_where (fixP->fx_file, fixP->fx_line,
21513 _("invalid literal constant: pool needs to be closer"));
21515 as_bad_where (fixP->fx_file, fixP->fx_line,
21516 _("bad immediate value for offset (%ld)"),
21521 newval = md_chars_to_number (buf, INSN_SIZE);
21523 newval &= 0xfffff000;
21526 newval &= 0xff7ff000;
21527 newval |= value | (sign ? INDEX_UP : 0);
21529 md_number_to_chars (buf, newval, INSN_SIZE);
21532 case BFD_RELOC_ARM_OFFSET_IMM8:
21533 case BFD_RELOC_ARM_HWLITERAL:
21539 if (validate_offset_imm (value, 1) == FAIL)
21541 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21542 as_bad_where (fixP->fx_file, fixP->fx_line,
21543 _("invalid literal constant: pool needs to be closer"));
21545 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
21550 newval = md_chars_to_number (buf, INSN_SIZE);
21552 newval &= 0xfffff0f0;
21555 newval &= 0xff7ff0f0;
21556 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21558 md_number_to_chars (buf, newval, INSN_SIZE);
21561 case BFD_RELOC_ARM_T32_OFFSET_U8:
21562 if (value < 0 || value > 1020 || value % 4 != 0)
21563 as_bad_where (fixP->fx_file, fixP->fx_line,
21564 _("bad immediate value for offset (%ld)"), (long) value);
21567 newval = md_chars_to_number (buf+2, THUMB_SIZE);
21569 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21572 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21573 /* This is a complicated relocation used for all varieties of Thumb32
21574 load/store instruction with immediate offset:
21576 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21577 *4, optional writeback(W)
21578 (doubleword load/store)
21580 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21581 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21582 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21583 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21584 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21586 Uppercase letters indicate bits that are already encoded at
21587 this point. Lowercase letters are our problem. For the
21588 second block of instructions, the secondary opcode nybble
21589 (bits 8..11) is present, and bit 23 is zero, even if this is
21590 a PC-relative operation. */
21591 newval = md_chars_to_number (buf, THUMB_SIZE);
21593 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
21595 if ((newval & 0xf0000000) == 0xe0000000)
21597 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21599 newval |= (1 << 23);
21602 if (value % 4 != 0)
21604 as_bad_where (fixP->fx_file, fixP->fx_line,
21605 _("offset not a multiple of 4"));
21611 as_bad_where (fixP->fx_file, fixP->fx_line,
21612 _("offset out of range"));
21617 else if ((newval & 0x000f0000) == 0x000f0000)
21619 /* PC-relative, 12-bit offset. */
21621 newval |= (1 << 23);
21626 as_bad_where (fixP->fx_file, fixP->fx_line,
21627 _("offset out of range"));
21632 else if ((newval & 0x00000100) == 0x00000100)
21634 /* Writeback: 8-bit, +/- offset. */
21636 newval |= (1 << 9);
21641 as_bad_where (fixP->fx_file, fixP->fx_line,
21642 _("offset out of range"));
21647 else if ((newval & 0x00000f00) == 0x00000e00)
21649 /* T-instruction: positive 8-bit offset. */
21650 if (value < 0 || value > 0xff)
21652 as_bad_where (fixP->fx_file, fixP->fx_line,
21653 _("offset out of range"));
21661 /* Positive 12-bit or negative 8-bit offset. */
21665 newval |= (1 << 23);
21675 as_bad_where (fixP->fx_file, fixP->fx_line,
21676 _("offset out of range"));
21683 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21684 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21687 case BFD_RELOC_ARM_SHIFT_IMM:
21688 newval = md_chars_to_number (buf, INSN_SIZE);
21689 if (((unsigned long) value) > 32
21691 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21693 as_bad_where (fixP->fx_file, fixP->fx_line,
21694 _("shift expression is too large"));
21699 /* Shifts of zero must be done as lsl. */
21701 else if (value == 32)
21703 newval &= 0xfffff07f;
21704 newval |= (value & 0x1f) << 7;
21705 md_number_to_chars (buf, newval, INSN_SIZE);
21708 case BFD_RELOC_ARM_T32_IMMEDIATE:
21709 case BFD_RELOC_ARM_T32_ADD_IMM:
21710 case BFD_RELOC_ARM_T32_IMM12:
21711 case BFD_RELOC_ARM_T32_ADD_PC12:
21712 /* We claim that this fixup has been processed here,
21713 even if in fact we generate an error because we do
21714 not have a reloc for it, so tc_gen_reloc will reject it. */
21718 && ! S_IS_DEFINED (fixP->fx_addsy))
21720 as_bad_where (fixP->fx_file, fixP->fx_line,
21721 _("undefined symbol %s used as an immediate value"),
21722 S_GET_NAME (fixP->fx_addsy));
21726 newval = md_chars_to_number (buf, THUMB_SIZE);
21728 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21731 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21732 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21734 newimm = encode_thumb32_immediate (value);
21735 if (newimm == (unsigned int) FAIL)
21736 newimm = thumb32_negate_data_op (&newval, value);
21738 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21739 && newimm == (unsigned int) FAIL)
21741 /* Turn add/sum into addw/subw. */
21742 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21743 newval = (newval & 0xfeffffff) | 0x02000000;
21744 /* No flat 12-bit imm encoding for addsw/subsw. */
21745 if ((newval & 0x00100000) == 0)
21747 /* 12 bit immediate for addw/subw. */
21751 newval ^= 0x00a00000;
21754 newimm = (unsigned int) FAIL;
21760 if (newimm == (unsigned int)FAIL)
21762 as_bad_where (fixP->fx_file, fixP->fx_line,
21763 _("invalid constant (%lx) after fixup"),
21764 (unsigned long) value);
21768 newval |= (newimm & 0x800) << 15;
21769 newval |= (newimm & 0x700) << 4;
21770 newval |= (newimm & 0x0ff);
21772 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21773 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21776 case BFD_RELOC_ARM_SMC:
21777 if (((unsigned long) value) > 0xffff)
21778 as_bad_where (fixP->fx_file, fixP->fx_line,
21779 _("invalid smc expression"));
21780 newval = md_chars_to_number (buf, INSN_SIZE);
21781 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21782 md_number_to_chars (buf, newval, INSN_SIZE);
21785 case BFD_RELOC_ARM_HVC:
21786 if (((unsigned long) value) > 0xffff)
21787 as_bad_where (fixP->fx_file, fixP->fx_line,
21788 _("invalid hvc expression"));
21789 newval = md_chars_to_number (buf, INSN_SIZE);
21790 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21791 md_number_to_chars (buf, newval, INSN_SIZE);
21794 case BFD_RELOC_ARM_SWI:
21795 if (fixP->tc_fix_data != 0)
21797 if (((unsigned long) value) > 0xff)
21798 as_bad_where (fixP->fx_file, fixP->fx_line,
21799 _("invalid swi expression"));
21800 newval = md_chars_to_number (buf, THUMB_SIZE);
21802 md_number_to_chars (buf, newval, THUMB_SIZE);
21806 if (((unsigned long) value) > 0x00ffffff)
21807 as_bad_where (fixP->fx_file, fixP->fx_line,
21808 _("invalid swi expression"));
21809 newval = md_chars_to_number (buf, INSN_SIZE);
21811 md_number_to_chars (buf, newval, INSN_SIZE);
21815 case BFD_RELOC_ARM_MULTI:
21816 if (((unsigned long) value) > 0xffff)
21817 as_bad_where (fixP->fx_file, fixP->fx_line,
21818 _("invalid expression in load/store multiple"));
21819 newval = value | md_chars_to_number (buf, INSN_SIZE);
21820 md_number_to_chars (buf, newval, INSN_SIZE);
21824 case BFD_RELOC_ARM_PCREL_CALL:
21826 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21828 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21829 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21830 && THUMB_IS_FUNC (fixP->fx_addsy))
21831 /* Flip the bl to blx. This is a simple flip
21832 bit here because we generate PCREL_CALL for
21833 unconditional bls. */
21835 newval = md_chars_to_number (buf, INSN_SIZE);
21836 newval = newval | 0x10000000;
21837 md_number_to_chars (buf, newval, INSN_SIZE);
21843 goto arm_branch_common;
21845 case BFD_RELOC_ARM_PCREL_JUMP:
21846 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21848 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21849 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21850 && THUMB_IS_FUNC (fixP->fx_addsy))
21852 /* This would map to a bl<cond>, b<cond>,
21853 b<always> to a Thumb function. We
21854 need to force a relocation for this particular
21856 newval = md_chars_to_number (buf, INSN_SIZE);
21860 case BFD_RELOC_ARM_PLT32:
21862 case BFD_RELOC_ARM_PCREL_BRANCH:
21864 goto arm_branch_common;
21866 case BFD_RELOC_ARM_PCREL_BLX:
21869 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21871 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21872 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21873 && ARM_IS_FUNC (fixP->fx_addsy))
21875 /* Flip the blx to a bl and warn. */
21876 const char *name = S_GET_NAME (fixP->fx_addsy);
21877 newval = 0xeb000000;
21878 as_warn_where (fixP->fx_file, fixP->fx_line,
21879 _("blx to '%s' an ARM ISA state function changed to bl"),
21881 md_number_to_chars (buf, newval, INSN_SIZE);
21887 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21888 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21892 /* We are going to store value (shifted right by two) in the
21893 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21894 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21895 also be be clear. */
21897 as_bad_where (fixP->fx_file, fixP->fx_line,
21898 _("misaligned branch destination"));
21899 if ((value & (offsetT)0xfe000000) != (offsetT)0
21900 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21901 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21903 if (fixP->fx_done || !seg->use_rela_p)
21905 newval = md_chars_to_number (buf, INSN_SIZE);
21906 newval |= (value >> 2) & 0x00ffffff;
21907 /* Set the H bit on BLX instructions. */
21911 newval |= 0x01000000;
21913 newval &= ~0x01000000;
21915 md_number_to_chars (buf, newval, INSN_SIZE);
21919 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21920 /* CBZ can only branch forward. */
21922 /* Attempts to use CBZ to branch to the next instruction
21923 (which, strictly speaking, are prohibited) will be turned into
21926 FIXME: It may be better to remove the instruction completely and
21927 perform relaxation. */
21930 newval = md_chars_to_number (buf, THUMB_SIZE);
21931 newval = 0xbf00; /* NOP encoding T1 */
21932 md_number_to_chars (buf, newval, THUMB_SIZE);
21937 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21939 if (fixP->fx_done || !seg->use_rela_p)
21941 newval = md_chars_to_number (buf, THUMB_SIZE);
21942 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21943 md_number_to_chars (buf, newval, THUMB_SIZE);
21948 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21949 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21950 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21952 if (fixP->fx_done || !seg->use_rela_p)
21954 newval = md_chars_to_number (buf, THUMB_SIZE);
21955 newval |= (value & 0x1ff) >> 1;
21956 md_number_to_chars (buf, newval, THUMB_SIZE);
21960 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21961 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21962 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21964 if (fixP->fx_done || !seg->use_rela_p)
21966 newval = md_chars_to_number (buf, THUMB_SIZE);
21967 newval |= (value & 0xfff) >> 1;
21968 md_number_to_chars (buf, newval, THUMB_SIZE);
21972 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21974 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21975 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21976 && ARM_IS_FUNC (fixP->fx_addsy)
21977 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21979 /* Force a relocation for a branch 20 bits wide. */
21982 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21983 as_bad_where (fixP->fx_file, fixP->fx_line,
21984 _("conditional branch out of range"));
21986 if (fixP->fx_done || !seg->use_rela_p)
21989 addressT S, J1, J2, lo, hi;
21991 S = (value & 0x00100000) >> 20;
21992 J2 = (value & 0x00080000) >> 19;
21993 J1 = (value & 0x00040000) >> 18;
21994 hi = (value & 0x0003f000) >> 12;
21995 lo = (value & 0x00000ffe) >> 1;
21997 newval = md_chars_to_number (buf, THUMB_SIZE);
21998 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21999 newval |= (S << 10) | hi;
22000 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22001 md_number_to_chars (buf, newval, THUMB_SIZE);
22002 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22006 case BFD_RELOC_THUMB_PCREL_BLX:
22007 /* If there is a blx from a thumb state function to
22008 another thumb function flip this to a bl and warn
22012 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22013 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22014 && THUMB_IS_FUNC (fixP->fx_addsy))
22016 const char *name = S_GET_NAME (fixP->fx_addsy);
22017 as_warn_where (fixP->fx_file, fixP->fx_line,
22018 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22020 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22021 newval = newval | 0x1000;
22022 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22023 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22028 goto thumb_bl_common;
22030 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22031 /* A bl from Thumb state ISA to an internal ARM state function
22032 is converted to a blx. */
22034 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22035 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22036 && ARM_IS_FUNC (fixP->fx_addsy)
22037 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22039 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22040 newval = newval & ~0x1000;
22041 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22042 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22049 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22050 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22051 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22054 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22055 /* For a BLX instruction, make sure that the relocation is rounded up
22056 to a word boundary. This follows the semantics of the instruction
22057 which specifies that bit 1 of the target address will come from bit
22058 1 of the base address. */
22059 value = (value + 1) & ~ 1;
22061 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22063 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22064 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22065 else if ((value & ~0x1ffffff)
22066 && ((value & ~0x1ffffff) != ~0x1ffffff))
22067 as_bad_where (fixP->fx_file, fixP->fx_line,
22068 _("Thumb2 branch out of range"));
22071 if (fixP->fx_done || !seg->use_rela_p)
22072 encode_thumb2_b_bl_offset (buf, value);
22076 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22077 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22078 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22080 if (fixP->fx_done || !seg->use_rela_p)
22081 encode_thumb2_b_bl_offset (buf, value);
22086 if (fixP->fx_done || !seg->use_rela_p)
22087 md_number_to_chars (buf, value, 1);
22091 if (fixP->fx_done || !seg->use_rela_p)
22092 md_number_to_chars (buf, value, 2);
22096 case BFD_RELOC_ARM_TLS_CALL:
22097 case BFD_RELOC_ARM_THM_TLS_CALL:
22098 case BFD_RELOC_ARM_TLS_DESCSEQ:
22099 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22100 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22103 case BFD_RELOC_ARM_TLS_GOTDESC:
22104 case BFD_RELOC_ARM_TLS_GD32:
22105 case BFD_RELOC_ARM_TLS_LE32:
22106 case BFD_RELOC_ARM_TLS_IE32:
22107 case BFD_RELOC_ARM_TLS_LDM32:
22108 case BFD_RELOC_ARM_TLS_LDO32:
22109 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22112 case BFD_RELOC_ARM_GOT32:
22113 case BFD_RELOC_ARM_GOTOFF:
22114 if (fixP->fx_done || !seg->use_rela_p)
22115 md_number_to_chars (buf, 0, 4);
22118 case BFD_RELOC_ARM_GOT_PREL:
22119 if (fixP->fx_done || !seg->use_rela_p)
22120 md_number_to_chars (buf, value, 4);
22123 case BFD_RELOC_ARM_TARGET2:
22124 /* TARGET2 is not partial-inplace, so we need to write the
22125 addend here for REL targets, because it won't be written out
22126 during reloc processing later. */
22127 if (fixP->fx_done || !seg->use_rela_p)
22128 md_number_to_chars (buf, fixP->fx_offset, 4);
22132 case BFD_RELOC_RVA:
22134 case BFD_RELOC_ARM_TARGET1:
22135 case BFD_RELOC_ARM_ROSEGREL32:
22136 case BFD_RELOC_ARM_SBREL32:
22137 case BFD_RELOC_32_PCREL:
22139 case BFD_RELOC_32_SECREL:
22141 if (fixP->fx_done || !seg->use_rela_p)
22143 /* For WinCE we only do this for pcrel fixups. */
22144 if (fixP->fx_done || fixP->fx_pcrel)
22146 md_number_to_chars (buf, value, 4);
22150 case BFD_RELOC_ARM_PREL31:
22151 if (fixP->fx_done || !seg->use_rela_p)
22153 newval = md_chars_to_number (buf, 4) & 0x80000000;
22154 if ((value ^ (value >> 1)) & 0x40000000)
22156 as_bad_where (fixP->fx_file, fixP->fx_line,
22157 _("rel31 relocation overflow"));
22159 newval |= value & 0x7fffffff;
22160 md_number_to_chars (buf, newval, 4);
22165 case BFD_RELOC_ARM_CP_OFF_IMM:
22166 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22167 if (value < -1023 || value > 1023 || (value & 3))
22168 as_bad_where (fixP->fx_file, fixP->fx_line,
22169 _("co-processor offset out of range"));
22174 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22175 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22176 newval = md_chars_to_number (buf, INSN_SIZE);
22178 newval = get_thumb32_insn (buf);
22180 newval &= 0xffffff00;
22183 newval &= 0xff7fff00;
22184 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22186 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22187 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22188 md_number_to_chars (buf, newval, INSN_SIZE);
22190 put_thumb32_insn (buf, newval);
22193 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
22194 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
22195 if (value < -255 || value > 255)
22196 as_bad_where (fixP->fx_file, fixP->fx_line,
22197 _("co-processor offset out of range"));
22199 goto cp_off_common;
22201 case BFD_RELOC_ARM_THUMB_OFFSET:
22202 newval = md_chars_to_number (buf, THUMB_SIZE);
22203 /* Exactly what ranges, and where the offset is inserted depends
22204 on the type of instruction, we can establish this from the
22206 switch (newval >> 12)
22208 case 4: /* PC load. */
22209 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22210 forced to zero for these loads; md_pcrel_from has already
22211 compensated for this. */
22213 as_bad_where (fixP->fx_file, fixP->fx_line,
22214 _("invalid offset, target not word aligned (0x%08lX)"),
22215 (((unsigned long) fixP->fx_frag->fr_address
22216 + (unsigned long) fixP->fx_where) & ~3)
22217 + (unsigned long) value);
22219 if (value & ~0x3fc)
22220 as_bad_where (fixP->fx_file, fixP->fx_line,
22221 _("invalid offset, value too big (0x%08lX)"),
22224 newval |= value >> 2;
22227 case 9: /* SP load/store. */
22228 if (value & ~0x3fc)
22229 as_bad_where (fixP->fx_file, fixP->fx_line,
22230 _("invalid offset, value too big (0x%08lX)"),
22232 newval |= value >> 2;
22235 case 6: /* Word load/store. */
22237 as_bad_where (fixP->fx_file, fixP->fx_line,
22238 _("invalid offset, value too big (0x%08lX)"),
22240 newval |= value << 4; /* 6 - 2. */
22243 case 7: /* Byte load/store. */
22245 as_bad_where (fixP->fx_file, fixP->fx_line,
22246 _("invalid offset, value too big (0x%08lX)"),
22248 newval |= value << 6;
22251 case 8: /* Halfword load/store. */
22253 as_bad_where (fixP->fx_file, fixP->fx_line,
22254 _("invalid offset, value too big (0x%08lX)"),
22256 newval |= value << 5; /* 6 - 1. */
22260 as_bad_where (fixP->fx_file, fixP->fx_line,
22261 "Unable to process relocation for thumb opcode: %lx",
22262 (unsigned long) newval);
22265 md_number_to_chars (buf, newval, THUMB_SIZE);
22268 case BFD_RELOC_ARM_THUMB_ADD:
22269 /* This is a complicated relocation, since we use it for all of
22270 the following immediate relocations:
22274 9bit ADD/SUB SP word-aligned
22275 10bit ADD PC/SP word-aligned
22277 The type of instruction being processed is encoded in the
22284 newval = md_chars_to_number (buf, THUMB_SIZE);
22286 int rd = (newval >> 4) & 0xf;
22287 int rs = newval & 0xf;
22288 int subtract = !!(newval & 0x8000);
22290 /* Check for HI regs, only very restricted cases allowed:
22291 Adjusting SP, and using PC or SP to get an address. */
22292 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22293 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22294 as_bad_where (fixP->fx_file, fixP->fx_line,
22295 _("invalid Hi register with immediate"));
22297 /* If value is negative, choose the opposite instruction. */
22301 subtract = !subtract;
22303 as_bad_where (fixP->fx_file, fixP->fx_line,
22304 _("immediate value out of range"));
22309 if (value & ~0x1fc)
22310 as_bad_where (fixP->fx_file, fixP->fx_line,
22311 _("invalid immediate for stack address calculation"));
22312 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22313 newval |= value >> 2;
22315 else if (rs == REG_PC || rs == REG_SP)
22317 if (subtract || value & ~0x3fc)
22318 as_bad_where (fixP->fx_file, fixP->fx_line,
22319 _("invalid immediate for address calculation (value = 0x%08lX)"),
22320 (unsigned long) value);
22321 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22323 newval |= value >> 2;
22328 as_bad_where (fixP->fx_file, fixP->fx_line,
22329 _("immediate value out of range"));
22330 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22331 newval |= (rd << 8) | value;
22336 as_bad_where (fixP->fx_file, fixP->fx_line,
22337 _("immediate value out of range"));
22338 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22339 newval |= rd | (rs << 3) | (value << 6);
22342 md_number_to_chars (buf, newval, THUMB_SIZE);
22345 case BFD_RELOC_ARM_THUMB_IMM:
22346 newval = md_chars_to_number (buf, THUMB_SIZE);
22347 if (value < 0 || value > 255)
22348 as_bad_where (fixP->fx_file, fixP->fx_line,
22349 _("invalid immediate: %ld is out of range"),
22352 md_number_to_chars (buf, newval, THUMB_SIZE);
22355 case BFD_RELOC_ARM_THUMB_SHIFT:
22356 /* 5bit shift value (0..32). LSL cannot take 32. */
22357 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22358 temp = newval & 0xf800;
22359 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22360 as_bad_where (fixP->fx_file, fixP->fx_line,
22361 _("invalid shift value: %ld"), (long) value);
22362 /* Shifts of zero must be encoded as LSL. */
22364 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22365 /* Shifts of 32 are encoded as zero. */
22366 else if (value == 32)
22368 newval |= value << 6;
22369 md_number_to_chars (buf, newval, THUMB_SIZE);
22372 case BFD_RELOC_VTABLE_INHERIT:
22373 case BFD_RELOC_VTABLE_ENTRY:
22377 case BFD_RELOC_ARM_MOVW:
22378 case BFD_RELOC_ARM_MOVT:
22379 case BFD_RELOC_ARM_THUMB_MOVW:
22380 case BFD_RELOC_ARM_THUMB_MOVT:
22381 if (fixP->fx_done || !seg->use_rela_p)
22383 /* REL format relocations are limited to a 16-bit addend. */
22384 if (!fixP->fx_done)
22386 if (value < -0x8000 || value > 0x7fff)
22387 as_bad_where (fixP->fx_file, fixP->fx_line,
22388 _("offset out of range"));
22390 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22391 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22396 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22397 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22399 newval = get_thumb32_insn (buf);
22400 newval &= 0xfbf08f00;
22401 newval |= (value & 0xf000) << 4;
22402 newval |= (value & 0x0800) << 15;
22403 newval |= (value & 0x0700) << 4;
22404 newval |= (value & 0x00ff);
22405 put_thumb32_insn (buf, newval);
22409 newval = md_chars_to_number (buf, 4);
22410 newval &= 0xfff0f000;
22411 newval |= value & 0x0fff;
22412 newval |= (value & 0xf000) << 4;
22413 md_number_to_chars (buf, newval, 4);
22418 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22419 case BFD_RELOC_ARM_ALU_PC_G0:
22420 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22421 case BFD_RELOC_ARM_ALU_PC_G1:
22422 case BFD_RELOC_ARM_ALU_PC_G2:
22423 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22424 case BFD_RELOC_ARM_ALU_SB_G0:
22425 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22426 case BFD_RELOC_ARM_ALU_SB_G1:
22427 case BFD_RELOC_ARM_ALU_SB_G2:
22428 gas_assert (!fixP->fx_done);
22429 if (!seg->use_rela_p)
22432 bfd_vma encoded_addend;
22433 bfd_vma addend_abs = abs (value);
22435 /* Check that the absolute value of the addend can be
22436 expressed as an 8-bit constant plus a rotation. */
22437 encoded_addend = encode_arm_immediate (addend_abs);
22438 if (encoded_addend == (unsigned int) FAIL)
22439 as_bad_where (fixP->fx_file, fixP->fx_line,
22440 _("the offset 0x%08lX is not representable"),
22441 (unsigned long) addend_abs);
22443 /* Extract the instruction. */
22444 insn = md_chars_to_number (buf, INSN_SIZE);
22446 /* If the addend is positive, use an ADD instruction.
22447 Otherwise use a SUB. Take care not to destroy the S bit. */
22448 insn &= 0xff1fffff;
22454 /* Place the encoded addend into the first 12 bits of the
22456 insn &= 0xfffff000;
22457 insn |= encoded_addend;
22459 /* Update the instruction. */
22460 md_number_to_chars (buf, insn, INSN_SIZE);
22464 case BFD_RELOC_ARM_LDR_PC_G0:
22465 case BFD_RELOC_ARM_LDR_PC_G1:
22466 case BFD_RELOC_ARM_LDR_PC_G2:
22467 case BFD_RELOC_ARM_LDR_SB_G0:
22468 case BFD_RELOC_ARM_LDR_SB_G1:
22469 case BFD_RELOC_ARM_LDR_SB_G2:
22470 gas_assert (!fixP->fx_done);
22471 if (!seg->use_rela_p)
22474 bfd_vma addend_abs = abs (value);
22476 /* Check that the absolute value of the addend can be
22477 encoded in 12 bits. */
22478 if (addend_abs >= 0x1000)
22479 as_bad_where (fixP->fx_file, fixP->fx_line,
22480 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22481 (unsigned long) addend_abs);
22483 /* Extract the instruction. */
22484 insn = md_chars_to_number (buf, INSN_SIZE);
22486 /* If the addend is negative, clear bit 23 of the instruction.
22487 Otherwise set it. */
22489 insn &= ~(1 << 23);
22493 /* Place the absolute value of the addend into the first 12 bits
22494 of the instruction. */
22495 insn &= 0xfffff000;
22496 insn |= addend_abs;
22498 /* Update the instruction. */
22499 md_number_to_chars (buf, insn, INSN_SIZE);
22503 case BFD_RELOC_ARM_LDRS_PC_G0:
22504 case BFD_RELOC_ARM_LDRS_PC_G1:
22505 case BFD_RELOC_ARM_LDRS_PC_G2:
22506 case BFD_RELOC_ARM_LDRS_SB_G0:
22507 case BFD_RELOC_ARM_LDRS_SB_G1:
22508 case BFD_RELOC_ARM_LDRS_SB_G2:
22509 gas_assert (!fixP->fx_done);
22510 if (!seg->use_rela_p)
22513 bfd_vma addend_abs = abs (value);
22515 /* Check that the absolute value of the addend can be
22516 encoded in 8 bits. */
22517 if (addend_abs >= 0x100)
22518 as_bad_where (fixP->fx_file, fixP->fx_line,
22519 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22520 (unsigned long) addend_abs);
22522 /* Extract the instruction. */
22523 insn = md_chars_to_number (buf, INSN_SIZE);
22525 /* If the addend is negative, clear bit 23 of the instruction.
22526 Otherwise set it. */
22528 insn &= ~(1 << 23);
22532 /* Place the first four bits of the absolute value of the addend
22533 into the first 4 bits of the instruction, and the remaining
22534 four into bits 8 .. 11. */
22535 insn &= 0xfffff0f0;
22536 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22538 /* Update the instruction. */
22539 md_number_to_chars (buf, insn, INSN_SIZE);
22543 case BFD_RELOC_ARM_LDC_PC_G0:
22544 case BFD_RELOC_ARM_LDC_PC_G1:
22545 case BFD_RELOC_ARM_LDC_PC_G2:
22546 case BFD_RELOC_ARM_LDC_SB_G0:
22547 case BFD_RELOC_ARM_LDC_SB_G1:
22548 case BFD_RELOC_ARM_LDC_SB_G2:
22549 gas_assert (!fixP->fx_done);
22550 if (!seg->use_rela_p)
22553 bfd_vma addend_abs = abs (value);
22555 /* Check that the absolute value of the addend is a multiple of
22556 four and, when divided by four, fits in 8 bits. */
22557 if (addend_abs & 0x3)
22558 as_bad_where (fixP->fx_file, fixP->fx_line,
22559 _("bad offset 0x%08lX (must be word-aligned)"),
22560 (unsigned long) addend_abs);
22562 if ((addend_abs >> 2) > 0xff)
22563 as_bad_where (fixP->fx_file, fixP->fx_line,
22564 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22565 (unsigned long) addend_abs);
22567 /* Extract the instruction. */
22568 insn = md_chars_to_number (buf, INSN_SIZE);
22570 /* If the addend is negative, clear bit 23 of the instruction.
22571 Otherwise set it. */
22573 insn &= ~(1 << 23);
22577 /* Place the addend (divided by four) into the first eight
22578 bits of the instruction. */
22579 insn &= 0xfffffff0;
22580 insn |= addend_abs >> 2;
22582 /* Update the instruction. */
22583 md_number_to_chars (buf, insn, INSN_SIZE);
22587 case BFD_RELOC_ARM_V4BX:
22588 /* This will need to go in the object file. */
22592 case BFD_RELOC_UNUSED:
22594 as_bad_where (fixP->fx_file, fixP->fx_line,
22595 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22599 /* Translate internal representation of relocation info to BFD target
22603 tc_gen_reloc (asection *section, fixS *fixp)
22606 bfd_reloc_code_real_type code;
22608 reloc = (arelent *) xmalloc (sizeof (arelent));
22610 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
22611 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22612 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
22614 if (fixp->fx_pcrel)
22616 if (section->use_rela_p)
22617 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22619 fixp->fx_offset = reloc->address;
22621 reloc->addend = fixp->fx_offset;
22623 switch (fixp->fx_r_type)
22626 if (fixp->fx_pcrel)
22628 code = BFD_RELOC_8_PCREL;
22633 if (fixp->fx_pcrel)
22635 code = BFD_RELOC_16_PCREL;
22640 if (fixp->fx_pcrel)
22642 code = BFD_RELOC_32_PCREL;
22646 case BFD_RELOC_ARM_MOVW:
22647 if (fixp->fx_pcrel)
22649 code = BFD_RELOC_ARM_MOVW_PCREL;
22653 case BFD_RELOC_ARM_MOVT:
22654 if (fixp->fx_pcrel)
22656 code = BFD_RELOC_ARM_MOVT_PCREL;
22660 case BFD_RELOC_ARM_THUMB_MOVW:
22661 if (fixp->fx_pcrel)
22663 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22667 case BFD_RELOC_ARM_THUMB_MOVT:
22668 if (fixp->fx_pcrel)
22670 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22674 case BFD_RELOC_NONE:
22675 case BFD_RELOC_ARM_PCREL_BRANCH:
22676 case BFD_RELOC_ARM_PCREL_BLX:
22677 case BFD_RELOC_RVA:
22678 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22679 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22680 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22681 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22682 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22683 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22684 case BFD_RELOC_VTABLE_ENTRY:
22685 case BFD_RELOC_VTABLE_INHERIT:
22687 case BFD_RELOC_32_SECREL:
22689 code = fixp->fx_r_type;
22692 case BFD_RELOC_THUMB_PCREL_BLX:
22694 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22695 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22698 code = BFD_RELOC_THUMB_PCREL_BLX;
22701 case BFD_RELOC_ARM_LITERAL:
22702 case BFD_RELOC_ARM_HWLITERAL:
22703 /* If this is called then the a literal has
22704 been referenced across a section boundary. */
22705 as_bad_where (fixp->fx_file, fixp->fx_line,
22706 _("literal referenced across section boundary"));
22710 case BFD_RELOC_ARM_TLS_CALL:
22711 case BFD_RELOC_ARM_THM_TLS_CALL:
22712 case BFD_RELOC_ARM_TLS_DESCSEQ:
22713 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22714 case BFD_RELOC_ARM_GOT32:
22715 case BFD_RELOC_ARM_GOTOFF:
22716 case BFD_RELOC_ARM_GOT_PREL:
22717 case BFD_RELOC_ARM_PLT32:
22718 case BFD_RELOC_ARM_TARGET1:
22719 case BFD_RELOC_ARM_ROSEGREL32:
22720 case BFD_RELOC_ARM_SBREL32:
22721 case BFD_RELOC_ARM_PREL31:
22722 case BFD_RELOC_ARM_TARGET2:
22723 case BFD_RELOC_ARM_TLS_LE32:
22724 case BFD_RELOC_ARM_TLS_LDO32:
22725 case BFD_RELOC_ARM_PCREL_CALL:
22726 case BFD_RELOC_ARM_PCREL_JUMP:
22727 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22728 case BFD_RELOC_ARM_ALU_PC_G0:
22729 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22730 case BFD_RELOC_ARM_ALU_PC_G1:
22731 case BFD_RELOC_ARM_ALU_PC_G2:
22732 case BFD_RELOC_ARM_LDR_PC_G0:
22733 case BFD_RELOC_ARM_LDR_PC_G1:
22734 case BFD_RELOC_ARM_LDR_PC_G2:
22735 case BFD_RELOC_ARM_LDRS_PC_G0:
22736 case BFD_RELOC_ARM_LDRS_PC_G1:
22737 case BFD_RELOC_ARM_LDRS_PC_G2:
22738 case BFD_RELOC_ARM_LDC_PC_G0:
22739 case BFD_RELOC_ARM_LDC_PC_G1:
22740 case BFD_RELOC_ARM_LDC_PC_G2:
22741 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22742 case BFD_RELOC_ARM_ALU_SB_G0:
22743 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22744 case BFD_RELOC_ARM_ALU_SB_G1:
22745 case BFD_RELOC_ARM_ALU_SB_G2:
22746 case BFD_RELOC_ARM_LDR_SB_G0:
22747 case BFD_RELOC_ARM_LDR_SB_G1:
22748 case BFD_RELOC_ARM_LDR_SB_G2:
22749 case BFD_RELOC_ARM_LDRS_SB_G0:
22750 case BFD_RELOC_ARM_LDRS_SB_G1:
22751 case BFD_RELOC_ARM_LDRS_SB_G2:
22752 case BFD_RELOC_ARM_LDC_SB_G0:
22753 case BFD_RELOC_ARM_LDC_SB_G1:
22754 case BFD_RELOC_ARM_LDC_SB_G2:
22755 case BFD_RELOC_ARM_V4BX:
22756 code = fixp->fx_r_type;
22759 case BFD_RELOC_ARM_TLS_GOTDESC:
22760 case BFD_RELOC_ARM_TLS_GD32:
22761 case BFD_RELOC_ARM_TLS_IE32:
22762 case BFD_RELOC_ARM_TLS_LDM32:
22763 /* BFD will include the symbol's address in the addend.
22764 But we don't want that, so subtract it out again here. */
22765 if (!S_IS_COMMON (fixp->fx_addsy))
22766 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22767 code = fixp->fx_r_type;
22771 case BFD_RELOC_ARM_IMMEDIATE:
22772 as_bad_where (fixp->fx_file, fixp->fx_line,
22773 _("internal relocation (type: IMMEDIATE) not fixed up"));
22776 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22777 as_bad_where (fixp->fx_file, fixp->fx_line,
22778 _("ADRL used for a symbol not defined in the same file"));
22781 case BFD_RELOC_ARM_OFFSET_IMM:
22782 if (section->use_rela_p)
22784 code = fixp->fx_r_type;
22788 if (fixp->fx_addsy != NULL
22789 && !S_IS_DEFINED (fixp->fx_addsy)
22790 && S_IS_LOCAL (fixp->fx_addsy))
22792 as_bad_where (fixp->fx_file, fixp->fx_line,
22793 _("undefined local label `%s'"),
22794 S_GET_NAME (fixp->fx_addsy));
22798 as_bad_where (fixp->fx_file, fixp->fx_line,
22799 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22806 switch (fixp->fx_r_type)
22808 case BFD_RELOC_NONE: type = "NONE"; break;
22809 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22810 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22811 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22812 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22813 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22814 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22815 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22816 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22817 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22818 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22819 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22820 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22821 default: type = _("<unknown>"); break;
22823 as_bad_where (fixp->fx_file, fixp->fx_line,
22824 _("cannot represent %s relocation in this object file format"),
22831 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22833 && fixp->fx_addsy == GOT_symbol)
22835 code = BFD_RELOC_ARM_GOTPC;
22836 reloc->addend = fixp->fx_offset = reloc->address;
22840 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22842 if (reloc->howto == NULL)
22844 as_bad_where (fixp->fx_file, fixp->fx_line,
22845 _("cannot represent %s relocation in this object file format"),
22846 bfd_get_reloc_code_name (code));
22850 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22851 vtable entry to be used in the relocation's section offset. */
22852 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22853 reloc->address = fixp->fx_offset;
22858 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22861 cons_fix_new_arm (fragS * frag,
22866 bfd_reloc_code_real_type type;
22870 FIXME: @@ Should look at CPU word size. */
22874 type = BFD_RELOC_8;
22877 type = BFD_RELOC_16;
22881 type = BFD_RELOC_32;
22884 type = BFD_RELOC_64;
22889 if (exp->X_op == O_secrel)
22891 exp->X_op = O_symbol;
22892 type = BFD_RELOC_32_SECREL;
22896 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22899 #if defined (OBJ_COFF)
22901 arm_validate_fix (fixS * fixP)
22903 /* If the destination of the branch is a defined symbol which does not have
22904 the THUMB_FUNC attribute, then we must be calling a function which has
22905 the (interfacearm) attribute. We look for the Thumb entry point to that
22906 function and change the branch to refer to that function instead. */
22907 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22908 && fixP->fx_addsy != NULL
22909 && S_IS_DEFINED (fixP->fx_addsy)
22910 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22912 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22919 arm_force_relocation (struct fix * fixp)
22921 #if defined (OBJ_COFF) && defined (TE_PE)
22922 if (fixp->fx_r_type == BFD_RELOC_RVA)
22926 /* In case we have a call or a branch to a function in ARM ISA mode from
22927 a thumb function or vice-versa force the relocation. These relocations
22928 are cleared off for some cores that might have blx and simple transformations
22932 switch (fixp->fx_r_type)
22934 case BFD_RELOC_ARM_PCREL_JUMP:
22935 case BFD_RELOC_ARM_PCREL_CALL:
22936 case BFD_RELOC_THUMB_PCREL_BLX:
22937 if (THUMB_IS_FUNC (fixp->fx_addsy))
22941 case BFD_RELOC_ARM_PCREL_BLX:
22942 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22943 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22944 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22945 if (ARM_IS_FUNC (fixp->fx_addsy))
22954 /* Resolve these relocations even if the symbol is extern or weak.
22955 Technically this is probably wrong due to symbol preemption.
22956 In practice these relocations do not have enough range to be useful
22957 at dynamic link time, and some code (e.g. in the Linux kernel)
22958 expects these references to be resolved. */
22959 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22960 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22961 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22962 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22963 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22964 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22965 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22966 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22967 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22968 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22969 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22970 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22971 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22972 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22975 /* Always leave these relocations for the linker. */
22976 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22977 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22978 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22981 /* Always generate relocations against function symbols. */
22982 if (fixp->fx_r_type == BFD_RELOC_32
22984 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22987 return generic_force_reloc (fixp);
22990 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22991 /* Relocations against function names must be left unadjusted,
22992 so that the linker can use this information to generate interworking
22993 stubs. The MIPS version of this function
22994 also prevents relocations that are mips-16 specific, but I do not
22995 know why it does this.
22998 There is one other problem that ought to be addressed here, but
22999 which currently is not: Taking the address of a label (rather
23000 than a function) and then later jumping to that address. Such
23001 addresses also ought to have their bottom bit set (assuming that
23002 they reside in Thumb code), but at the moment they will not. */
23005 arm_fix_adjustable (fixS * fixP)
23007 if (fixP->fx_addsy == NULL)
23010 /* Preserve relocations against symbols with function type. */
23011 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
23014 if (THUMB_IS_FUNC (fixP->fx_addsy)
23015 && fixP->fx_subsy == NULL)
23018 /* We need the symbol name for the VTABLE entries. */
23019 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23020 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23023 /* Don't allow symbols to be discarded on GOT related relocs. */
23024 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23025 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23026 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23027 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23028 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23029 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23030 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23031 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
23032 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23033 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23034 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23035 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23036 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
23037 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
23040 /* Similarly for group relocations. */
23041 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23042 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23043 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23046 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23047 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23048 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23049 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23050 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23051 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23052 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23053 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23054 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
23059 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23064 elf32_arm_target_format (void)
23067 return (target_big_endian
23068 ? "elf32-bigarm-symbian"
23069 : "elf32-littlearm-symbian");
23070 #elif defined (TE_VXWORKS)
23071 return (target_big_endian
23072 ? "elf32-bigarm-vxworks"
23073 : "elf32-littlearm-vxworks");
23074 #elif defined (TE_NACL)
23075 return (target_big_endian
23076 ? "elf32-bigarm-nacl"
23077 : "elf32-littlearm-nacl");
23079 if (target_big_endian)
23080 return "elf32-bigarm";
23082 return "elf32-littlearm";
23087 armelf_frob_symbol (symbolS * symp,
23090 elf_frob_symbol (symp, puntp);
23094 /* MD interface: Finalization. */
23099 literal_pool * pool;
23101 /* Ensure that all the IT blocks are properly closed. */
23102 check_it_blocks_finished ();
23104 for (pool = list_of_pools; pool; pool = pool->next)
23106 /* Put it at the end of the relevant section. */
23107 subseg_set (pool->section, pool->sub_section);
23109 arm_elf_change_section ();
23116 /* Remove any excess mapping symbols generated for alignment frags in
23117 SEC. We may have created a mapping symbol before a zero byte
23118 alignment; remove it if there's a mapping symbol after the
23121 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23122 void *dummy ATTRIBUTE_UNUSED)
23124 segment_info_type *seginfo = seg_info (sec);
23127 if (seginfo == NULL || seginfo->frchainP == NULL)
23130 for (fragp = seginfo->frchainP->frch_root;
23132 fragp = fragp->fr_next)
23134 symbolS *sym = fragp->tc_frag_data.last_map;
23135 fragS *next = fragp->fr_next;
23137 /* Variable-sized frags have been converted to fixed size by
23138 this point. But if this was variable-sized to start with,
23139 there will be a fixed-size frag after it. So don't handle
23141 if (sym == NULL || next == NULL)
23144 if (S_GET_VALUE (sym) < next->fr_address)
23145 /* Not at the end of this frag. */
23147 know (S_GET_VALUE (sym) == next->fr_address);
23151 if (next->tc_frag_data.first_map != NULL)
23153 /* Next frag starts with a mapping symbol. Discard this
23155 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23159 if (next->fr_next == NULL)
23161 /* This mapping symbol is at the end of the section. Discard
23163 know (next->fr_fix == 0 && next->fr_var == 0);
23164 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23168 /* As long as we have empty frags without any mapping symbols,
23170 /* If the next frag is non-empty and does not start with a
23171 mapping symbol, then this mapping symbol is required. */
23172 if (next->fr_address != next->fr_next->fr_address)
23175 next = next->fr_next;
23177 while (next != NULL);
23182 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23186 arm_adjust_symtab (void)
23191 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23193 if (ARM_IS_THUMB (sym))
23195 if (THUMB_IS_FUNC (sym))
23197 /* Mark the symbol as a Thumb function. */
23198 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23199 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23200 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
23202 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23203 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23205 as_bad (_("%s: unexpected function type: %d"),
23206 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23208 else switch (S_GET_STORAGE_CLASS (sym))
23211 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23214 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23217 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23225 if (ARM_IS_INTERWORK (sym))
23226 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
23233 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23235 if (ARM_IS_THUMB (sym))
23237 elf_symbol_type * elf_sym;
23239 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23240 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
23242 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23243 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
23245 /* If it's a .thumb_func, declare it as so,
23246 otherwise tag label as .code 16. */
23247 if (THUMB_IS_FUNC (sym))
23248 elf_sym->internal_elf_sym.st_target_internal
23249 = ST_BRANCH_TO_THUMB;
23250 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23251 elf_sym->internal_elf_sym.st_info =
23252 ELF_ST_INFO (bind, STT_ARM_16BIT);
23257 /* Remove any overlapping mapping symbols generated by alignment frags. */
23258 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
23259 /* Now do generic ELF adjustments. */
23260 elf_adjust_symtab ();
23264 /* MD interface: Initialization. */
23267 set_constant_flonums (void)
23271 for (i = 0; i < NUM_FLOAT_VALS; i++)
23272 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23276 /* Auto-select Thumb mode if it's the only available instruction set for the
23277 given architecture. */
23280 autoselect_thumb_from_cpu_variant (void)
23282 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23283 opcode_select (16);
23292 if ( (arm_ops_hsh = hash_new ()) == NULL
23293 || (arm_cond_hsh = hash_new ()) == NULL
23294 || (arm_shift_hsh = hash_new ()) == NULL
23295 || (arm_psr_hsh = hash_new ()) == NULL
23296 || (arm_v7m_psr_hsh = hash_new ()) == NULL
23297 || (arm_reg_hsh = hash_new ()) == NULL
23298 || (arm_reloc_hsh = hash_new ()) == NULL
23299 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
23300 as_fatal (_("virtual memory exhausted"));
23302 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
23303 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
23304 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
23305 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
23306 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
23307 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
23308 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
23309 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
23310 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
23311 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
23312 (void *) (v7m_psrs + i));
23313 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
23314 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
23316 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23318 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
23319 (void *) (barrier_opt_names + i));
23321 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23323 struct reloc_entry * entry = reloc_names + i;
23325 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23326 /* This makes encode_branch() use the EABI versions of this relocation. */
23327 entry->reloc = BFD_RELOC_UNUSED;
23329 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23333 set_constant_flonums ();
23335 /* Set the cpu variant based on the command-line options. We prefer
23336 -mcpu= over -march= if both are set (as for GCC); and we prefer
23337 -mfpu= over any other way of setting the floating point unit.
23338 Use of legacy options with new options are faulted. */
23341 if (mcpu_cpu_opt || march_cpu_opt)
23342 as_bad (_("use of old and new-style options to set CPU type"));
23344 mcpu_cpu_opt = legacy_cpu;
23346 else if (!mcpu_cpu_opt)
23347 mcpu_cpu_opt = march_cpu_opt;
23352 as_bad (_("use of old and new-style options to set FPU type"));
23354 mfpu_opt = legacy_fpu;
23356 else if (!mfpu_opt)
23358 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23359 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23360 /* Some environments specify a default FPU. If they don't, infer it
23361 from the processor. */
23363 mfpu_opt = mcpu_fpu_opt;
23365 mfpu_opt = march_fpu_opt;
23367 mfpu_opt = &fpu_default;
23373 if (mcpu_cpu_opt != NULL)
23374 mfpu_opt = &fpu_default;
23375 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
23376 mfpu_opt = &fpu_arch_vfp_v2;
23378 mfpu_opt = &fpu_arch_fpa;
23384 mcpu_cpu_opt = &cpu_default;
23385 selected_cpu = cpu_default;
23389 selected_cpu = *mcpu_cpu_opt;
23391 mcpu_cpu_opt = &arm_arch_any;
23394 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23396 autoselect_thumb_from_cpu_variant ();
23398 arm_arch_used = thumb_arch_used = arm_arch_none;
23400 #if defined OBJ_COFF || defined OBJ_ELF
23402 unsigned int flags = 0;
23404 #if defined OBJ_ELF
23405 flags = meabi_flags;
23407 switch (meabi_flags)
23409 case EF_ARM_EABI_UNKNOWN:
23411 /* Set the flags in the private structure. */
23412 if (uses_apcs_26) flags |= F_APCS26;
23413 if (support_interwork) flags |= F_INTERWORK;
23414 if (uses_apcs_float) flags |= F_APCS_FLOAT;
23415 if (pic_code) flags |= F_PIC;
23416 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
23417 flags |= F_SOFT_FLOAT;
23419 switch (mfloat_abi_opt)
23421 case ARM_FLOAT_ABI_SOFT:
23422 case ARM_FLOAT_ABI_SOFTFP:
23423 flags |= F_SOFT_FLOAT;
23426 case ARM_FLOAT_ABI_HARD:
23427 if (flags & F_SOFT_FLOAT)
23428 as_bad (_("hard-float conflicts with specified fpu"));
23432 /* Using pure-endian doubles (even if soft-float). */
23433 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
23434 flags |= F_VFP_FLOAT;
23436 #if defined OBJ_ELF
23437 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
23438 flags |= EF_ARM_MAVERICK_FLOAT;
23441 case EF_ARM_EABI_VER4:
23442 case EF_ARM_EABI_VER5:
23443 /* No additional flags to set. */
23450 bfd_set_private_flags (stdoutput, flags);
23452 /* We have run out flags in the COFF header to encode the
23453 status of ATPCS support, so instead we create a dummy,
23454 empty, debug section called .arm.atpcs. */
23459 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23463 bfd_set_section_flags
23464 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23465 bfd_set_section_size (stdoutput, sec, 0);
23466 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23472 /* Record the CPU type as well. */
23473 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23474 mach = bfd_mach_arm_iWMMXt2;
23475 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
23476 mach = bfd_mach_arm_iWMMXt;
23477 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
23478 mach = bfd_mach_arm_XScale;
23479 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
23480 mach = bfd_mach_arm_ep9312;
23481 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
23482 mach = bfd_mach_arm_5TE;
23483 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
23485 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23486 mach = bfd_mach_arm_5T;
23488 mach = bfd_mach_arm_5;
23490 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
23492 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23493 mach = bfd_mach_arm_4T;
23495 mach = bfd_mach_arm_4;
23497 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
23498 mach = bfd_mach_arm_3M;
23499 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23500 mach = bfd_mach_arm_3;
23501 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23502 mach = bfd_mach_arm_2a;
23503 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23504 mach = bfd_mach_arm_2;
23506 mach = bfd_mach_arm_unknown;
23508 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23511 /* Command line processing. */
23514 Invocation line includes a switch not recognized by the base assembler.
23515 See if it's a processor-specific option.
23517 This routine is somewhat complicated by the need for backwards
23518 compatibility (since older releases of gcc can't be changed).
23519 The new options try to make the interface as compatible as
23522 New options (supported) are:
23524 -mcpu=<cpu name> Assemble for selected processor
23525 -march=<architecture name> Assemble for selected architecture
23526 -mfpu=<fpu architecture> Assemble for selected FPU.
23527 -EB/-mbig-endian Big-endian
23528 -EL/-mlittle-endian Little-endian
23529 -k Generate PIC code
23530 -mthumb Start in Thumb mode
23531 -mthumb-interwork Code supports ARM/Thumb interworking
23533 -m[no-]warn-deprecated Warn about deprecated features
23535 For now we will also provide support for:
23537 -mapcs-32 32-bit Program counter
23538 -mapcs-26 26-bit Program counter
23539 -macps-float Floats passed in FP registers
23540 -mapcs-reentrant Reentrant code
23542 (sometime these will probably be replaced with -mapcs=<list of options>
23543 and -matpcs=<list of options>)
23545 The remaining options are only supported for back-wards compatibility.
23546 Cpu variants, the arm part is optional:
23547 -m[arm]1 Currently not supported.
23548 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23549 -m[arm]3 Arm 3 processor
23550 -m[arm]6[xx], Arm 6 processors
23551 -m[arm]7[xx][t][[d]m] Arm 7 processors
23552 -m[arm]8[10] Arm 8 processors
23553 -m[arm]9[20][tdmi] Arm 9 processors
23554 -mstrongarm[110[0]] StrongARM processors
23555 -mxscale XScale processors
23556 -m[arm]v[2345[t[e]]] Arm architectures
23557 -mall All (except the ARM1)
23559 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23560 -mfpe-old (No float load/store multiples)
23561 -mvfpxd VFP Single precision
23563 -mno-fpu Disable all floating point instructions
23565 The following CPU names are recognized:
23566 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23567 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23568 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23569 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23570 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23571 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23572 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23576 const char * md_shortopts = "m:k";
23578 #ifdef ARM_BI_ENDIAN
23579 #define OPTION_EB (OPTION_MD_BASE + 0)
23580 #define OPTION_EL (OPTION_MD_BASE + 1)
23582 #if TARGET_BYTES_BIG_ENDIAN
23583 #define OPTION_EB (OPTION_MD_BASE + 0)
23585 #define OPTION_EL (OPTION_MD_BASE + 1)
23588 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23590 struct option md_longopts[] =
23593 {"EB", no_argument, NULL, OPTION_EB},
23596 {"EL", no_argument, NULL, OPTION_EL},
23598 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
23599 {NULL, no_argument, NULL, 0}
23602 size_t md_longopts_size = sizeof (md_longopts);
23604 struct arm_option_table
23606 char *option; /* Option name to match. */
23607 char *help; /* Help information. */
23608 int *var; /* Variable to change. */
23609 int value; /* What to change it to. */
23610 char *deprecated; /* If non-null, print this message. */
23613 struct arm_option_table arm_opts[] =
23615 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23616 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23617 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23618 &support_interwork, 1, NULL},
23619 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23620 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23621 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23623 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23624 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23625 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23626 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23629 /* These are recognized by the assembler, but have no affect on code. */
23630 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23631 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
23633 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23634 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23635 &warn_on_deprecated, 0, NULL},
23636 {NULL, NULL, NULL, 0, NULL}
23639 struct arm_legacy_option_table
23641 char *option; /* Option name to match. */
23642 const arm_feature_set **var; /* Variable to change. */
23643 const arm_feature_set value; /* What to change it to. */
23644 char *deprecated; /* If non-null, print this message. */
23647 const struct arm_legacy_option_table arm_legacy_opts[] =
23649 /* DON'T add any new processors to this list -- we want the whole list
23650 to go away... Add them to the processors table instead. */
23651 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23652 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23653 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23654 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23655 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23656 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23657 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23658 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23659 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23660 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23661 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23662 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23663 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23664 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23665 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23666 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23667 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23668 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23669 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23670 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23671 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23672 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23673 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23674 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23675 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23676 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23677 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23678 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23679 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23680 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23681 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23682 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23683 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23684 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23685 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23686 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23687 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23688 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23689 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23690 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23691 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23692 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23693 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23694 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23695 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23696 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23697 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23698 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23699 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23700 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23701 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23702 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23703 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23704 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23705 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23706 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23707 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23708 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23709 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23710 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23711 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23712 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23713 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23714 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23715 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23716 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23717 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23718 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23719 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23720 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23721 N_("use -mcpu=strongarm110")},
23722 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23723 N_("use -mcpu=strongarm1100")},
23724 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23725 N_("use -mcpu=strongarm1110")},
23726 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23727 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23728 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23730 /* Architecture variants -- don't add any more to this list either. */
23731 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23732 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23733 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23734 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23735 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23736 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23737 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23738 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23739 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23740 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23741 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23742 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23743 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23744 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23745 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23746 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23747 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23748 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23750 /* Floating point variants -- don't add any more to this list either. */
23751 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23752 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23753 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23754 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23755 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23757 {NULL, NULL, ARM_ARCH_NONE, NULL}
23760 struct arm_cpu_option_table
23764 const arm_feature_set value;
23765 /* For some CPUs we assume an FPU unless the user explicitly sets
23767 const arm_feature_set default_fpu;
23768 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23770 const char *canonical_name;
23773 /* This list should, at a minimum, contain all the cpu names
23774 recognized by GCC. */
23775 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23776 static const struct arm_cpu_option_table arm_cpus[] =
23778 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23779 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23780 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23781 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23782 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23783 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23784 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23785 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23786 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23787 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23788 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23789 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23790 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23791 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23792 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23793 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23794 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23795 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23796 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23797 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23798 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23799 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23800 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23801 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23802 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23803 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23804 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23805 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23806 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23807 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23808 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23809 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23810 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23811 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23812 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23813 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23814 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23815 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23816 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23817 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23818 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23819 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23820 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23821 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23822 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23823 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23824 /* For V5 or later processors we default to using VFP; but the user
23825 should really set the FPU type explicitly. */
23826 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23827 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23828 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23829 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23830 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23831 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23832 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23833 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23834 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23835 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23836 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23837 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23838 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23839 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23840 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23841 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23842 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23843 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23844 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23845 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23847 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23848 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23849 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23850 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23851 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23852 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23853 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23854 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23855 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23857 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23858 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23859 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23860 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23861 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23862 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23863 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23864 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23865 FPU_NONE, "Cortex-A5"),
23866 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23867 FPU_ARCH_NEON_VFP_V4,
23869 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23870 ARM_FEATURE (0, FPU_VFP_V3
23871 | FPU_NEON_EXT_V1),
23873 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23874 ARM_FEATURE (0, FPU_VFP_V3
23875 | FPU_NEON_EXT_V1),
23877 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23878 FPU_ARCH_NEON_VFP_V4,
23880 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23881 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23883 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23884 FPU_NONE, "Cortex-R5"),
23885 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23886 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23887 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23888 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23889 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
23890 /* ??? XSCALE is really an architecture. */
23891 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23892 /* ??? iwmmxt is not a processor. */
23893 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23894 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23895 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23897 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23900 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23904 struct arm_arch_option_table
23908 const arm_feature_set value;
23909 const arm_feature_set default_fpu;
23912 /* This list should, at a minimum, contain all the architecture names
23913 recognized by GCC. */
23914 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23915 static const struct arm_arch_option_table arm_archs[] =
23917 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23918 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23919 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23920 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
23921 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
23922 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
23923 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
23924 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
23925 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
23926 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
23927 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
23928 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
23929 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
23930 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
23931 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
23932 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
23933 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
23934 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
23935 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
23936 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
23937 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
23938 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
23939 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
23940 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
23941 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
23942 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
23943 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
23944 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
23945 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
23946 /* The official spelling of the ARMv7 profile variants is the dashed form.
23947 Accept the non-dashed form for compatibility with old toolchains. */
23948 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23949 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23950 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23951 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23952 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23953 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23954 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
23955 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
23956 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
23957 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
23958 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
23959 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23961 #undef ARM_ARCH_OPT
23963 /* ISA extensions in the co-processor and main instruction set space. */
23964 struct arm_option_extension_value_table
23968 const arm_feature_set value;
23969 const arm_feature_set allowed_archs;
23972 /* The following table must be in alphabetical order with a NULL last entry.
23974 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23975 static const struct arm_option_extension_value_table arm_extensions[] =
23977 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23978 ARM_FEATURE (ARM_EXT_V8, 0)),
23979 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
23980 ARM_FEATURE (ARM_EXT_V8, 0)),
23981 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23982 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23983 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
23984 ARM_EXT_OPT ("iwmmxt2",
23985 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
23986 ARM_EXT_OPT ("maverick",
23987 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
23988 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
23989 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23990 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
23991 ARM_FEATURE (ARM_EXT_V8, 0)),
23992 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
23993 ARM_FEATURE (ARM_EXT_V6M, 0)),
23994 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23995 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
23996 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
23998 ARM_FEATURE (ARM_EXT_V7A, 0)),
23999 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24000 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24004 /* ISA floating-point and Advanced SIMD extensions. */
24005 struct arm_option_fpu_value_table
24008 const arm_feature_set value;
24011 /* This list should, at a minimum, contain all the fpu names
24012 recognized by GCC. */
24013 static const struct arm_option_fpu_value_table arm_fpus[] =
24015 {"softfpa", FPU_NONE},
24016 {"fpe", FPU_ARCH_FPE},
24017 {"fpe2", FPU_ARCH_FPE},
24018 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24019 {"fpa", FPU_ARCH_FPA},
24020 {"fpa10", FPU_ARCH_FPA},
24021 {"fpa11", FPU_ARCH_FPA},
24022 {"arm7500fe", FPU_ARCH_FPA},
24023 {"softvfp", FPU_ARCH_VFP},
24024 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24025 {"vfp", FPU_ARCH_VFP_V2},
24026 {"vfp9", FPU_ARCH_VFP_V2},
24027 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
24028 {"vfp10", FPU_ARCH_VFP_V2},
24029 {"vfp10-r0", FPU_ARCH_VFP_V1},
24030 {"vfpxd", FPU_ARCH_VFP_V1xD},
24031 {"vfpv2", FPU_ARCH_VFP_V2},
24032 {"vfpv3", FPU_ARCH_VFP_V3},
24033 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
24034 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
24035 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24036 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24037 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
24038 {"arm1020t", FPU_ARCH_VFP_V1},
24039 {"arm1020e", FPU_ARCH_VFP_V2},
24040 {"arm1136jfs", FPU_ARCH_VFP_V2},
24041 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24042 {"maverick", FPU_ARCH_MAVERICK},
24043 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
24044 {"neon-fp16", FPU_ARCH_NEON_FP16},
24045 {"vfpv4", FPU_ARCH_VFP_V4},
24046 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
24047 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
24048 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
24049 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24050 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24051 {"crypto-neon-fp-armv8",
24052 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
24053 {NULL, ARM_ARCH_NONE}
24056 struct arm_option_value_table
24062 static const struct arm_option_value_table arm_float_abis[] =
24064 {"hard", ARM_FLOAT_ABI_HARD},
24065 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24066 {"soft", ARM_FLOAT_ABI_SOFT},
24071 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24072 static const struct arm_option_value_table arm_eabis[] =
24074 {"gnu", EF_ARM_EABI_UNKNOWN},
24075 {"4", EF_ARM_EABI_VER4},
24076 {"5", EF_ARM_EABI_VER5},
24081 struct arm_long_option_table
24083 char * option; /* Substring to match. */
24084 char * help; /* Help information. */
24085 int (* func) (char * subopt); /* Function to decode sub-option. */
24086 char * deprecated; /* If non-null, print this message. */
24090 arm_parse_extension (char *str, const arm_feature_set **opt_p)
24092 arm_feature_set *ext_set = (arm_feature_set *)
24093 xmalloc (sizeof (arm_feature_set));
24095 /* We insist on extensions being specified in alphabetical order, and with
24096 extensions being added before being removed. We achieve this by having
24097 the global ARM_EXTENSIONS table in alphabetical order, and using the
24098 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24099 or removing it (0) and only allowing it to change in the order
24101 const struct arm_option_extension_value_table * opt = NULL;
24102 int adding_value = -1;
24104 /* Copy the feature set, so that we can modify it. */
24105 *ext_set = **opt_p;
24108 while (str != NULL && *str != 0)
24115 as_bad (_("invalid architectural extension"));
24120 ext = strchr (str, '+');
24125 len = strlen (str);
24127 if (len >= 2 && strncmp (str, "no", 2) == 0)
24129 if (adding_value != 0)
24132 opt = arm_extensions;
24140 if (adding_value == -1)
24143 opt = arm_extensions;
24145 else if (adding_value != 1)
24147 as_bad (_("must specify extensions to add before specifying "
24148 "those to remove"));
24155 as_bad (_("missing architectural extension"));
24159 gas_assert (adding_value != -1);
24160 gas_assert (opt != NULL);
24162 /* Scan over the options table trying to find an exact match. */
24163 for (; opt->name != NULL; opt++)
24164 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24166 /* Check we can apply the extension to this architecture. */
24167 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24169 as_bad (_("extension does not apply to the base architecture"));
24173 /* Add or remove the extension. */
24175 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
24177 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
24182 if (opt->name == NULL)
24184 /* Did we fail to find an extension because it wasn't specified in
24185 alphabetical order, or because it does not exist? */
24187 for (opt = arm_extensions; opt->name != NULL; opt++)
24188 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24191 if (opt->name == NULL)
24192 as_bad (_("unknown architectural extension `%s'"), str);
24194 as_bad (_("architectural extensions must be specified in "
24195 "alphabetical order"));
24201 /* We should skip the extension we've just matched the next time
24213 arm_parse_cpu (char *str)
24215 const struct arm_cpu_option_table *opt;
24216 char *ext = strchr (str, '+');
24222 len = strlen (str);
24226 as_bad (_("missing cpu name `%s'"), str);
24230 for (opt = arm_cpus; opt->name != NULL; opt++)
24231 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24233 mcpu_cpu_opt = &opt->value;
24234 mcpu_fpu_opt = &opt->default_fpu;
24235 if (opt->canonical_name)
24236 strcpy (selected_cpu_name, opt->canonical_name);
24241 for (i = 0; i < len; i++)
24242 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24243 selected_cpu_name[i] = 0;
24247 return arm_parse_extension (ext, &mcpu_cpu_opt);
24252 as_bad (_("unknown cpu `%s'"), str);
24257 arm_parse_arch (char *str)
24259 const struct arm_arch_option_table *opt;
24260 char *ext = strchr (str, '+');
24266 len = strlen (str);
24270 as_bad (_("missing architecture name `%s'"), str);
24274 for (opt = arm_archs; opt->name != NULL; opt++)
24275 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24277 march_cpu_opt = &opt->value;
24278 march_fpu_opt = &opt->default_fpu;
24279 strcpy (selected_cpu_name, opt->name);
24282 return arm_parse_extension (ext, &march_cpu_opt);
24287 as_bad (_("unknown architecture `%s'\n"), str);
24292 arm_parse_fpu (char * str)
24294 const struct arm_option_fpu_value_table * opt;
24296 for (opt = arm_fpus; opt->name != NULL; opt++)
24297 if (streq (opt->name, str))
24299 mfpu_opt = &opt->value;
24303 as_bad (_("unknown floating point format `%s'\n"), str);
24308 arm_parse_float_abi (char * str)
24310 const struct arm_option_value_table * opt;
24312 for (opt = arm_float_abis; opt->name != NULL; opt++)
24313 if (streq (opt->name, str))
24315 mfloat_abi_opt = opt->value;
24319 as_bad (_("unknown floating point abi `%s'\n"), str);
24325 arm_parse_eabi (char * str)
24327 const struct arm_option_value_table *opt;
24329 for (opt = arm_eabis; opt->name != NULL; opt++)
24330 if (streq (opt->name, str))
24332 meabi_flags = opt->value;
24335 as_bad (_("unknown EABI `%s'\n"), str);
24341 arm_parse_it_mode (char * str)
24343 bfd_boolean ret = TRUE;
24345 if (streq ("arm", str))
24346 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24347 else if (streq ("thumb", str))
24348 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24349 else if (streq ("always", str))
24350 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24351 else if (streq ("never", str))
24352 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24355 as_bad (_("unknown implicit IT mode `%s', should be "\
24356 "arm, thumb, always, or never."), str);
24363 struct arm_long_option_table arm_long_opts[] =
24365 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24366 arm_parse_cpu, NULL},
24367 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24368 arm_parse_arch, NULL},
24369 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24370 arm_parse_fpu, NULL},
24371 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24372 arm_parse_float_abi, NULL},
24374 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24375 arm_parse_eabi, NULL},
24377 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24378 arm_parse_it_mode, NULL},
24379 {NULL, NULL, 0, NULL}
24383 md_parse_option (int c, char * arg)
24385 struct arm_option_table *opt;
24386 const struct arm_legacy_option_table *fopt;
24387 struct arm_long_option_table *lopt;
24393 target_big_endian = 1;
24399 target_big_endian = 0;
24403 case OPTION_FIX_V4BX:
24408 /* Listing option. Just ignore these, we don't support additional
24413 for (opt = arm_opts; opt->option != NULL; opt++)
24415 if (c == opt->option[0]
24416 && ((arg == NULL && opt->option[1] == 0)
24417 || streq (arg, opt->option + 1)))
24419 /* If the option is deprecated, tell the user. */
24420 if (warn_on_deprecated && opt->deprecated != NULL)
24421 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24422 arg ? arg : "", _(opt->deprecated));
24424 if (opt->var != NULL)
24425 *opt->var = opt->value;
24431 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
24433 if (c == fopt->option[0]
24434 && ((arg == NULL && fopt->option[1] == 0)
24435 || streq (arg, fopt->option + 1)))
24437 /* If the option is deprecated, tell the user. */
24438 if (warn_on_deprecated && fopt->deprecated != NULL)
24439 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24440 arg ? arg : "", _(fopt->deprecated));
24442 if (fopt->var != NULL)
24443 *fopt->var = &fopt->value;
24449 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24451 /* These options are expected to have an argument. */
24452 if (c == lopt->option[0]
24454 && strncmp (arg, lopt->option + 1,
24455 strlen (lopt->option + 1)) == 0)
24457 /* If the option is deprecated, tell the user. */
24458 if (warn_on_deprecated && lopt->deprecated != NULL)
24459 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24460 _(lopt->deprecated));
24462 /* Call the sup-option parser. */
24463 return lopt->func (arg + strlen (lopt->option) - 1);
24474 md_show_usage (FILE * fp)
24476 struct arm_option_table *opt;
24477 struct arm_long_option_table *lopt;
24479 fprintf (fp, _(" ARM-specific assembler options:\n"));
24481 for (opt = arm_opts; opt->option != NULL; opt++)
24482 if (opt->help != NULL)
24483 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
24485 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24486 if (lopt->help != NULL)
24487 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
24491 -EB assemble code for a big-endian cpu\n"));
24496 -EL assemble code for a little-endian cpu\n"));
24500 --fix-v4bx Allow BX in ARMv4 code\n"));
24508 arm_feature_set flags;
24509 } cpu_arch_ver_table;
24511 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24512 least features first. */
24513 static const cpu_arch_ver_table cpu_arch_ver[] =
24519 {4, ARM_ARCH_V5TE},
24520 {5, ARM_ARCH_V5TEJ},
24524 {11, ARM_ARCH_V6M},
24525 {12, ARM_ARCH_V6SM},
24526 {8, ARM_ARCH_V6T2},
24527 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
24528 {10, ARM_ARCH_V7R},
24529 {10, ARM_ARCH_V7M},
24530 {14, ARM_ARCH_V8A},
24534 /* Set an attribute if it has not already been set by the user. */
24536 aeabi_set_attribute_int (int tag, int value)
24539 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24540 || !attributes_set_explicitly[tag])
24541 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24545 aeabi_set_attribute_string (int tag, const char *value)
24548 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24549 || !attributes_set_explicitly[tag])
24550 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24553 /* Set the public EABI object attributes. */
24555 aeabi_set_public_attributes (void)
24560 int fp16_optional = 0;
24561 arm_feature_set flags;
24562 arm_feature_set tmp;
24563 const cpu_arch_ver_table *p;
24565 /* Choose the architecture based on the capabilities of the requested cpu
24566 (if any) and/or the instructions actually used. */
24567 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24568 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24569 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
24571 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24572 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24574 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24575 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24577 /* Allow the user to override the reported architecture. */
24580 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24581 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24584 /* We need to make sure that the attributes do not identify us as v6S-M
24585 when the only v6S-M feature in use is the Operating System Extensions. */
24586 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24587 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
24588 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
24592 for (p = cpu_arch_ver; p->val; p++)
24594 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24597 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24601 /* The table lookup above finds the last architecture to contribute
24602 a new feature. Unfortunately, Tag13 is a subset of the union of
24603 v6T2 and v7-M, so it is never seen as contributing a new feature.
24604 We can not search for the last entry which is entirely used,
24605 because if no CPU is specified we build up only those flags
24606 actually used. Perhaps we should separate out the specified
24607 and implicit cases. Avoid taking this path for -march=all by
24608 checking for contradictory v7-A / v7-M features. */
24610 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24611 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24612 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24615 /* Tag_CPU_name. */
24616 if (selected_cpu_name[0])
24620 q = selected_cpu_name;
24621 if (strncmp (q, "armv", 4) == 0)
24626 for (i = 0; q[i]; i++)
24627 q[i] = TOUPPER (q[i]);
24629 aeabi_set_attribute_string (Tag_CPU_name, q);
24632 /* Tag_CPU_arch. */
24633 aeabi_set_attribute_int (Tag_CPU_arch, arch);
24635 /* Tag_CPU_arch_profile. */
24636 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
24638 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
24640 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
24645 if (profile != '\0')
24646 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
24648 /* Tag_ARM_ISA_use. */
24649 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24651 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
24653 /* Tag_THUMB_ISA_use. */
24654 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24656 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24657 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
24659 /* Tag_VFP_arch. */
24660 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24661 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24662 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
24663 aeabi_set_attribute_int (Tag_VFP_arch,
24664 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24666 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
24669 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24671 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
24673 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24676 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24677 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24678 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24679 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24680 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24682 /* Tag_ABI_HardFP_use. */
24683 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24684 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24685 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24687 /* Tag_WMMX_arch. */
24688 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24689 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24690 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24691 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24693 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24694 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24695 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24696 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24698 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24700 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24704 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24709 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24710 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24711 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24715 We set Tag_DIV_use to two when integer divide instructions have been used
24716 in ARM state, or when Thumb integer divide instructions have been used,
24717 but we have no architecture profile set, nor have we any ARM instructions.
24719 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24722 For new architectures we will have to check these tests. */
24723 gas_assert (arch <= TAG_CPU_ARCH_V8);
24724 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24725 aeabi_set_attribute_int (Tag_DIV_use, 0);
24726 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24727 || (profile == '\0'
24728 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24729 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24730 aeabi_set_attribute_int (Tag_DIV_use, 2);
24732 /* Tag_MP_extension_use. */
24733 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24734 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24736 /* Tag Virtualization_use. */
24737 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24739 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24742 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24745 /* Add the default contents for the .ARM.attributes section. */
24749 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24752 aeabi_set_public_attributes ();
24754 #endif /* OBJ_ELF */
24757 /* Parse a .cpu directive. */
24760 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24762 const struct arm_cpu_option_table *opt;
24766 name = input_line_pointer;
24767 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24768 input_line_pointer++;
24769 saved_char = *input_line_pointer;
24770 *input_line_pointer = 0;
24772 /* Skip the first "all" entry. */
24773 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24774 if (streq (opt->name, name))
24776 mcpu_cpu_opt = &opt->value;
24777 selected_cpu = opt->value;
24778 if (opt->canonical_name)
24779 strcpy (selected_cpu_name, opt->canonical_name);
24783 for (i = 0; opt->name[i]; i++)
24784 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24786 selected_cpu_name[i] = 0;
24788 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24789 *input_line_pointer = saved_char;
24790 demand_empty_rest_of_line ();
24793 as_bad (_("unknown cpu `%s'"), name);
24794 *input_line_pointer = saved_char;
24795 ignore_rest_of_line ();
24799 /* Parse a .arch directive. */
24802 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24804 const struct arm_arch_option_table *opt;
24808 name = input_line_pointer;
24809 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24810 input_line_pointer++;
24811 saved_char = *input_line_pointer;
24812 *input_line_pointer = 0;
24814 /* Skip the first "all" entry. */
24815 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24816 if (streq (opt->name, name))
24818 mcpu_cpu_opt = &opt->value;
24819 selected_cpu = opt->value;
24820 strcpy (selected_cpu_name, opt->name);
24821 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24822 *input_line_pointer = saved_char;
24823 demand_empty_rest_of_line ();
24827 as_bad (_("unknown architecture `%s'\n"), name);
24828 *input_line_pointer = saved_char;
24829 ignore_rest_of_line ();
24833 /* Parse a .object_arch directive. */
24836 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24838 const struct arm_arch_option_table *opt;
24842 name = input_line_pointer;
24843 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24844 input_line_pointer++;
24845 saved_char = *input_line_pointer;
24846 *input_line_pointer = 0;
24848 /* Skip the first "all" entry. */
24849 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24850 if (streq (opt->name, name))
24852 object_arch = &opt->value;
24853 *input_line_pointer = saved_char;
24854 demand_empty_rest_of_line ();
24858 as_bad (_("unknown architecture `%s'\n"), name);
24859 *input_line_pointer = saved_char;
24860 ignore_rest_of_line ();
24863 /* Parse a .arch_extension directive. */
24866 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24868 const struct arm_option_extension_value_table *opt;
24871 int adding_value = 1;
24873 name = input_line_pointer;
24874 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24875 input_line_pointer++;
24876 saved_char = *input_line_pointer;
24877 *input_line_pointer = 0;
24879 if (strlen (name) >= 2
24880 && strncmp (name, "no", 2) == 0)
24886 for (opt = arm_extensions; opt->name != NULL; opt++)
24887 if (streq (opt->name, name))
24889 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
24891 as_bad (_("architectural extension `%s' is not allowed for the "
24892 "current base architecture"), name);
24897 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
24899 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
24901 mcpu_cpu_opt = &selected_cpu;
24902 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24903 *input_line_pointer = saved_char;
24904 demand_empty_rest_of_line ();
24908 if (opt->name == NULL)
24909 as_bad (_("unknown architecture `%s'\n"), name);
24911 *input_line_pointer = saved_char;
24912 ignore_rest_of_line ();
24915 /* Parse a .fpu directive. */
24918 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
24920 const struct arm_option_fpu_value_table *opt;
24924 name = input_line_pointer;
24925 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24926 input_line_pointer++;
24927 saved_char = *input_line_pointer;
24928 *input_line_pointer = 0;
24930 for (opt = arm_fpus; opt->name != NULL; opt++)
24931 if (streq (opt->name, name))
24933 mfpu_opt = &opt->value;
24934 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24935 *input_line_pointer = saved_char;
24936 demand_empty_rest_of_line ();
24940 as_bad (_("unknown floating point format `%s'\n"), name);
24941 *input_line_pointer = saved_char;
24942 ignore_rest_of_line ();
24945 /* Copy symbol information. */
24948 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
24950 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
24954 /* Given a symbolic attribute NAME, return the proper integer value.
24955 Returns -1 if the attribute is not known. */
24958 arm_convert_symbolic_attribute (const char *name)
24960 static const struct
24965 attribute_table[] =
24967 /* When you modify this table you should
24968 also modify the list in doc/c-arm.texi. */
24969 #define T(tag) {#tag, tag}
24970 T (Tag_CPU_raw_name),
24973 T (Tag_CPU_arch_profile),
24974 T (Tag_ARM_ISA_use),
24975 T (Tag_THUMB_ISA_use),
24979 T (Tag_Advanced_SIMD_arch),
24980 T (Tag_PCS_config),
24981 T (Tag_ABI_PCS_R9_use),
24982 T (Tag_ABI_PCS_RW_data),
24983 T (Tag_ABI_PCS_RO_data),
24984 T (Tag_ABI_PCS_GOT_use),
24985 T (Tag_ABI_PCS_wchar_t),
24986 T (Tag_ABI_FP_rounding),
24987 T (Tag_ABI_FP_denormal),
24988 T (Tag_ABI_FP_exceptions),
24989 T (Tag_ABI_FP_user_exceptions),
24990 T (Tag_ABI_FP_number_model),
24991 T (Tag_ABI_align_needed),
24992 T (Tag_ABI_align8_needed),
24993 T (Tag_ABI_align_preserved),
24994 T (Tag_ABI_align8_preserved),
24995 T (Tag_ABI_enum_size),
24996 T (Tag_ABI_HardFP_use),
24997 T (Tag_ABI_VFP_args),
24998 T (Tag_ABI_WMMX_args),
24999 T (Tag_ABI_optimization_goals),
25000 T (Tag_ABI_FP_optimization_goals),
25001 T (Tag_compatibility),
25002 T (Tag_CPU_unaligned_access),
25003 T (Tag_FP_HP_extension),
25004 T (Tag_VFP_HP_extension),
25005 T (Tag_ABI_FP_16bit_format),
25006 T (Tag_MPextension_use),
25008 T (Tag_nodefaults),
25009 T (Tag_also_compatible_with),
25010 T (Tag_conformance),
25012 T (Tag_Virtualization_use),
25013 /* We deliberately do not include Tag_MPextension_use_legacy. */
25021 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
25022 if (streq (name, attribute_table[i].name))
25023 return attribute_table[i].tag;
25029 /* Apply sym value for relocations only in the case that
25030 they are for local symbols and you have the respective
25031 architectural feature for blx and simple switches. */
25033 arm_apply_sym_value (struct fix * fixP)
25036 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
25037 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
25039 switch (fixP->fx_r_type)
25041 case BFD_RELOC_ARM_PCREL_BLX:
25042 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25043 if (ARM_IS_FUNC (fixP->fx_addsy))
25047 case BFD_RELOC_ARM_PCREL_CALL:
25048 case BFD_RELOC_THUMB_PCREL_BLX:
25049 if (THUMB_IS_FUNC (fixP->fx_addsy))
25060 #endif /* OBJ_ELF */