1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 /* Types of processor to assemble for. */
40 #define ARM_1 0x00000001
41 #define ARM_2 0x00000002
42 #define ARM_3 0x00000004
44 #define ARM_6 0x00000008
45 #define ARM_7 ARM_6 /* same core instruction set */
46 #define ARM_8 ARM_6 /* same core instruction set */
47 #define ARM_9 ARM_6 /* same core instruction set */
48 #define ARM_CPU_MASK 0x0000000f
50 /* The following bitmasks control CPU extensions (ARM7 onwards): */
51 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
52 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
53 #define ARM_THUMB 0x00000040 /* allow BX instruction */
54 #define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
55 #define ARM_EXT_V5E 0x00000200 /* "El Segundo" */
57 /* Architectures are the sum of the base and extensions. */
58 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
60 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
61 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP (ARM_ANY - ARM_1)
66 #define ARM_ALL ARM_2UP /* Not arm1 only */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
75 /* Some useful combinations */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
82 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
84 #define CPU_DEFAULT ARM_ALL
89 #define FPU_DEFAULT FPU_ALL
92 #define streq(a, b) (strcmp (a, b) == 0)
93 #define skip_whitespace(str) while (* (str) == ' ') ++ (str)
95 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
96 static int target_oabi = 0;
98 #if defined OBJ_COFF || defined OBJ_ELF
99 /* Flags stored in private area of BFD structure */
100 static boolean uses_apcs_26 = false;
101 static boolean support_interwork = false;
102 static boolean uses_apcs_float = false;
103 static boolean pic_code = false;
106 /* This array holds the chars that always start a comment. If the
107 pre-processor is disabled, these aren't very useful. */
108 CONST char comment_chars[] = "@";
110 /* This array holds the chars that only start a comment at the beginning of
111 a line. If the line seems to have the form '# 123 filename'
112 .line and .file directives will appear in the pre-processed output. */
113 /* Note that input_file.c hand checks for '#' at the beginning of the
114 first line of the input file. This is because the compiler outputs
115 #NO_APP at the beginning of its output. */
116 /* Also note that comments like this one will always work. */
117 CONST char line_comment_chars[] = "#";
120 CONST char line_separator_chars[] = ";";
122 CONST char line_separator_chars[] = "";
125 /* Chars that can be used to separate mant
126 from exp in floating point numbers. */
127 CONST char EXP_CHARS[] = "eE";
129 /* Chars that mean this number is a floating point constant */
133 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
135 /* Prefix characters that indicate the start of an immediate
137 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
140 symbolS * GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
143 CONST int md_reloc_size = 8; /* Size of relocation record */
145 static int thumb_mode = 0; /* 0: assemble for ARM, 1: assemble for Thumb,
146 2: assemble for Thumb even though target cpu
147 does not support thumb instructions. */
148 typedef struct arm_fix
156 unsigned long instruction;
161 bfd_reloc_code_real_type type;
171 CONST char * template;
175 static CONST struct asm_shift shift[] =
191 #define NO_SHIFT_RESTRICT 1
192 #define SHIFT_RESTRICT 0
194 #define NUM_FLOAT_VALS 8
196 CONST char * fp_const[] =
198 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
201 /* Number of littlenums required to hold an extended precision number. */
202 #define MAX_LITTLENUMS 6
204 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
214 #define CP_T_X 0x00008000
215 #define CP_T_Y 0x00400000
216 #define CP_T_Pre 0x01000000
217 #define CP_T_UD 0x00800000
218 #define CP_T_WB 0x00200000
220 #define CONDS_BIT (0x00100000)
221 #define LOAD_BIT (0x00100000)
222 #define TRANS_BIT (0x00200000)
226 CONST char * template;
230 /* This is to save a hash look-up in the common case. */
231 #define COND_ALWAYS 0xe0000000
233 static CONST struct asm_cond conds[] =
237 {"cs", 0x20000000}, {"hs", 0x20000000},
238 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
253 /* Warning: If the top bit of the set_bits is set, then the standard
254 instruction bitmask is ignored, and the new bitmask is taken from
258 CONST char * template; /* Basic flag string */
259 unsigned long set_bits; /* Bits to set */
262 static CONST struct asm_flg s_flag[] =
268 static CONST struct asm_flg ldr_flags[] =
272 {"bt", 0x00400000 | TRANS_BIT},
279 static CONST struct asm_flg str_flags[] =
283 {"bt", 0x00400000 | TRANS_BIT},
288 static CONST struct asm_flg byte_flag[] =
294 static CONST struct asm_flg cmp_flags[] =
301 static CONST struct asm_flg ldm_flags[] =
314 static CONST struct asm_flg stm_flags[] =
327 static CONST struct asm_flg lfm_flags[] =
334 static CONST struct asm_flg sfm_flags[] =
341 static CONST struct asm_flg round_flags[] =
349 /* The implementation of the FIX instruction is broken on some assemblers,
350 in that it accepts a precision specifier as well as a rounding specifier,
351 despite the fact that this is meaningless. To be more compatible, we
352 accept it as well, though of course it does not set any bits. */
353 static CONST struct asm_flg fix_flags[] =
370 static CONST struct asm_flg except_flag[] =
376 static CONST struct asm_flg cplong_flag[] =
384 CONST char * template;
385 unsigned long number;
388 #define PSR_FIELD_MASK 0x000f0000
390 #define PSR_FLAGS 0x00080000
391 #define PSR_CONTROL 0x00010000 /* Undocumented instruction, its use is discouraged by ARM */
392 #define PSR_ALL 0x00090000
401 static CONST struct asm_psr psrs[] =
405 {"cpsr_all", CPSR_ALL},
407 {"spsr_all", SPSR_ALL},
410 {"cpsr_flg", CPSR_FLG},
411 {"spsr_flg", SPSR_FLG},
414 {"cpsr_c", CPSR_CTL},
415 {"cpsr_ctl", CPSR_CTL},
416 {"spsr_c", SPSR_CTL},
417 {"spsr_ctl", SPSR_CTL}
420 /* Functions called by parser. */
421 /* ARM instructions */
422 static void do_arit PARAMS ((char *, unsigned long));
423 static void do_cmp PARAMS ((char *, unsigned long));
424 static void do_mov PARAMS ((char *, unsigned long));
425 static void do_ldst PARAMS ((char *, unsigned long));
426 static void do_ldmstm PARAMS ((char *, unsigned long));
427 static void do_branch PARAMS ((char *, unsigned long));
428 static void do_swi PARAMS ((char *, unsigned long));
429 /* Pseudo Op codes */
430 static void do_adr PARAMS ((char *, unsigned long));
431 static void do_adrl PARAMS ((char *, unsigned long));
432 static void do_nop PARAMS ((char *, unsigned long));
434 static void do_mul PARAMS ((char *, unsigned long));
435 static void do_mla PARAMS ((char *, unsigned long));
437 static void do_swap PARAMS ((char *, unsigned long));
439 static void do_msr PARAMS ((char *, unsigned long));
440 static void do_mrs PARAMS ((char *, unsigned long));
442 static void do_mull PARAMS ((char *, unsigned long));
444 static void do_bx PARAMS ((char *, unsigned long));
447 /* Coprocessor Instructions */
448 static void do_cdp PARAMS ((char *, unsigned long));
449 static void do_lstc PARAMS ((char *, unsigned long));
450 static void do_co_reg PARAMS ((char *, unsigned long));
451 static void do_fp_ctrl PARAMS ((char *, unsigned long));
452 static void do_fp_ldst PARAMS ((char *, unsigned long));
453 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
454 static void do_fp_dyadic PARAMS ((char *, unsigned long));
455 static void do_fp_monadic PARAMS ((char *, unsigned long));
456 static void do_fp_cmp PARAMS ((char *, unsigned long));
457 static void do_fp_from_reg PARAMS ((char *, unsigned long));
458 static void do_fp_to_reg PARAMS ((char *, unsigned long));
460 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
461 static int arm_reg_parse PARAMS ((char **));
462 static int arm_psr_parse PARAMS ((char **));
463 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
464 static int add_to_lit_pool PARAMS ((void));
465 static unsigned validate_immediate PARAMS ((unsigned));
466 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
467 static int validate_offset_imm PARAMS ((unsigned int, int));
468 static void opcode_select PARAMS ((int));
469 static void end_of_line PARAMS ((char *));
470 static int reg_required_here PARAMS ((char **, int));
471 static int psr_required_here PARAMS ((char **, int, int));
472 static int co_proc_number PARAMS ((char **));
473 static int cp_opc_expr PARAMS ((char **, int, int));
474 static int cp_reg_required_here PARAMS ((char **, int));
475 static int fp_reg_required_here PARAMS ((char **, int));
476 static int cp_address_offset PARAMS ((char **));
477 static int cp_address_required_here PARAMS ((char **));
478 static int my_get_float_expression PARAMS ((char **));
479 static int skip_past_comma PARAMS ((char **));
480 static int walk_no_bignums PARAMS ((symbolS *));
481 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
482 static int data_op2 PARAMS ((char **));
483 static int fp_op2 PARAMS ((char **));
484 static long reg_list PARAMS ((char **));
485 static void thumb_load_store PARAMS ((char *, int, int));
486 static int decode_shift PARAMS ((char **, int));
487 static int ldst_extend PARAMS ((char **, int));
488 static void thumb_add_sub PARAMS ((char *, int));
489 static void insert_reg PARAMS ((int));
490 static void thumb_shift PARAMS ((char *, int));
491 static void thumb_mov_compare PARAMS ((char *, int));
492 static void set_constant_flonums PARAMS ((void));
493 static valueT md_chars_to_number PARAMS ((char *, int));
494 static void insert_reg_alias PARAMS ((char *, int));
495 static void output_inst PARAMS ((void));
497 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
500 /* ARM instructions take 4bytes in the object file, Thumb instructions
504 /* LONGEST_INST is the longest basic instruction name without conditions or
505 flags. ARM7M has 4 of length 5. */
507 #define LONGEST_INST 5
512 CONST char * template; /* Basic string to match */
513 unsigned long value; /* Basic instruction code */
515 /* Compulsory suffix that must follow conds. If "", then the
516 instruction is not conditional and must have no suffix. */
517 CONST char * comp_suffix;
519 CONST struct asm_flg * flags; /* Bits to toggle if flag 'n' set */
520 unsigned long variants; /* Which CPU variants this exists for */
521 /* Function to call to parse args */
522 void (* parms) PARAMS ((char *, unsigned long));
525 static CONST struct asm_opcode insns[] =
527 /* ARM Instructions */
528 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
529 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
530 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
531 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
532 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
533 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
534 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
535 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
536 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
537 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
538 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
539 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
540 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
541 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
542 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
543 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
544 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
545 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
546 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
547 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
548 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
550 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
551 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
553 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
554 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
558 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
559 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
560 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
562 /* ARM 2 multiplies */
563 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
564 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
566 /* ARM 3 - swp instructions */
567 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
569 /* ARM 6 Coprocessor instructions */
570 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
571 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
572 /* ScottB: our code uses 0x0128f000 for msr.
573 NickC: but this is wrong because the bits 16 and 19 are handled
574 by the PSR_xxx defines above. */
576 /* ARM 7M long multiplies - need signed/unsigned flags! */
577 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
578 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
579 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
580 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
582 /* ARM THUMB interworking */
583 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
585 /* Floating point instructions */
586 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
587 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
588 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
589 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
590 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
591 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
592 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
593 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
594 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
595 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
596 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
597 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
598 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
599 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
600 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
601 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
602 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
603 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
604 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
605 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
606 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
607 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
608 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
609 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
610 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
611 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
612 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
613 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
614 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
615 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
616 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
617 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
618 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
619 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
620 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
621 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
622 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
623 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
624 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
625 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
626 be an optional suffix, but part of the instruction. To be compatible,
628 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
629 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
630 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
631 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
633 /* Generic copressor instructions. */
634 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
635 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
636 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
637 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
638 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
641 /* Defines for various bits that we will want to toggle. */
642 #define INST_IMMEDIATE 0x02000000
643 #define OFFSET_REG 0x02000000
644 #define HWOFFSET_IMM 0x00400000
645 #define SHIFT_BY_REG 0x00000010
646 #define PRE_INDEX 0x01000000
647 #define INDEX_UP 0x00800000
648 #define WRITE_BACK 0x00200000
649 #define LDM_TYPE_2_OR_3 0x00400000
651 #define LITERAL_MASK 0xf000f000
652 #define COND_MASK 0xf0000000
653 #define OPCODE_MASK 0xfe1fffff
654 #define DATA_OP_SHIFT 21
656 /* Codes to distinguish the arithmetic instructions. */
667 #define OPCODE_CMP 10
668 #define OPCODE_CMN 11
669 #define OPCODE_ORR 12
670 #define OPCODE_MOV 13
671 #define OPCODE_BIC 14
672 #define OPCODE_MVN 15
674 static void do_t_nop PARAMS ((char *));
675 static void do_t_arit PARAMS ((char *));
676 static void do_t_add PARAMS ((char *));
677 static void do_t_asr PARAMS ((char *));
678 static void do_t_branch9 PARAMS ((char *));
679 static void do_t_branch12 PARAMS ((char *));
680 static void do_t_branch23 PARAMS ((char *));
681 static void do_t_bx PARAMS ((char *));
682 static void do_t_compare PARAMS ((char *));
683 static void do_t_ldmstm PARAMS ((char *));
684 static void do_t_ldr PARAMS ((char *));
685 static void do_t_ldrb PARAMS ((char *));
686 static void do_t_ldrh PARAMS ((char *));
687 static void do_t_lds PARAMS ((char *));
688 static void do_t_lsl PARAMS ((char *));
689 static void do_t_lsr PARAMS ((char *));
690 static void do_t_mov PARAMS ((char *));
691 static void do_t_push_pop PARAMS ((char *));
692 static void do_t_str PARAMS ((char *));
693 static void do_t_strb PARAMS ((char *));
694 static void do_t_strh PARAMS ((char *));
695 static void do_t_sub PARAMS ((char *));
696 static void do_t_swi PARAMS ((char *));
697 static void do_t_adr PARAMS ((char *));
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ASR_I 0x1000
721 #define T_OPCODE_LSL_I 0x0000
722 #define T_OPCODE_LSR_I 0x0800
724 #define T_OPCODE_MOV_I8 0x2000
725 #define T_OPCODE_CMP_I8 0x2800
726 #define T_OPCODE_CMP_LR 0x4280
727 #define T_OPCODE_MOV_HR 0x4600
728 #define T_OPCODE_CMP_HR 0x4500
730 #define T_OPCODE_LDR_PC 0x4800
731 #define T_OPCODE_LDR_SP 0x9800
732 #define T_OPCODE_STR_SP 0x9000
733 #define T_OPCODE_LDR_IW 0x6800
734 #define T_OPCODE_STR_IW 0x6000
735 #define T_OPCODE_LDR_IH 0x8800
736 #define T_OPCODE_STR_IH 0x8000
737 #define T_OPCODE_LDR_IB 0x7800
738 #define T_OPCODE_STR_IB 0x7000
739 #define T_OPCODE_LDR_RW 0x5800
740 #define T_OPCODE_STR_RW 0x5000
741 #define T_OPCODE_LDR_RH 0x5a00
742 #define T_OPCODE_STR_RH 0x5200
743 #define T_OPCODE_LDR_RB 0x5c00
744 #define T_OPCODE_STR_RB 0x5400
746 #define T_OPCODE_PUSH 0xb400
747 #define T_OPCODE_POP 0xbc00
749 #define T_OPCODE_BRANCH 0xe7fe
751 static int thumb_reg PARAMS ((char ** str, int hi_lo));
753 #define THUMB_SIZE 2 /* Size of thumb instruction. */
754 #define THUMB_REG_LO 0x1
755 #define THUMB_REG_HI 0x2
756 #define THUMB_REG_ANY 0x3
758 #define THUMB_H1 0x0080
759 #define THUMB_H2 0x0040
766 #define THUMB_COMPARE 1
769 #define THUMB_STORE 1
771 #define THUMB_PP_PC_LR 0x0100
773 /* These three are used for immediate shifts, do not alter. */
775 #define THUMB_HALFWORD 1
780 CONST char * template; /* Basic string to match */
781 unsigned long value; /* Basic instruction code */
783 unsigned long variants; /* Which CPU variants this exists for */
784 void (* parms) PARAMS ((char *)); /* Function to call to parse args */
787 static CONST struct thumb_opcode tinsns[] =
789 {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
790 {"add", 0x0000, 2, ARM_THUMB, do_t_add},
791 {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
792 {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
793 {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
794 {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
795 {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
796 {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
797 {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
798 {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
799 {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
800 {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
801 {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
802 {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
803 {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
804 {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
805 {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
806 {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
807 {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
808 {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
809 {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
810 {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
811 {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
812 {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
813 {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
814 {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
815 {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
816 {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
817 {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
818 {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
819 {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
820 {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
821 {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
822 {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
823 {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
824 {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
825 {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
826 {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
827 {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
828 {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
829 {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
830 {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
831 {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
832 {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
833 {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
834 {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
835 {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
836 {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
837 {"str", 0x0000, 2, ARM_THUMB, do_t_str},
838 {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
839 {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
840 {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
841 {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
842 {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
844 {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
845 {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
854 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
855 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
856 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
862 /* These are the standard names. Users can add aliases with .req */
863 static CONST struct reg_entry reg_table[] =
865 /* Processor Register Numbers. */
866 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
867 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
868 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
869 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
870 /* APCS conventions. */
871 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
872 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
873 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
874 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
875 /* ATPCS additions to APCS conventions. */
876 {"wr", 7}, {"v8", 11},
878 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
879 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
880 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
881 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
882 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
883 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
884 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
885 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
886 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
887 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
888 /* ATPCS additions to float register names. */
889 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
890 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
891 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
892 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
893 /* FIXME: At some point we need to add VFP register names. */
894 /* Array terminator. */
898 #define BAD_ARGS _("Bad arguments to instruction")
899 #define BAD_PC _("r15 not allowed here")
900 #define BAD_FLAGS _("Instruction should not have flags")
901 #define BAD_COND _("Instruction is not conditional")
903 static struct hash_control * arm_ops_hsh = NULL;
904 static struct hash_control * arm_tops_hsh = NULL;
905 static struct hash_control * arm_cond_hsh = NULL;
906 static struct hash_control * arm_shift_hsh = NULL;
907 static struct hash_control * arm_reg_hsh = NULL;
908 static struct hash_control * arm_psr_hsh = NULL;
910 /* This table describes all the machine specific pseudo-ops the assembler
911 has to support. The fields are:
912 pseudo-op name without dot
913 function to call to execute this pseudo-op
914 Integer arg to pass to the function. */
916 static void s_req PARAMS ((int));
917 static void s_align PARAMS ((int));
918 static void s_bss PARAMS ((int));
919 static void s_even PARAMS ((int));
920 static void s_ltorg PARAMS ((int));
921 static void s_arm PARAMS ((int));
922 static void s_thumb PARAMS ((int));
923 static void s_code PARAMS ((int));
924 static void s_force_thumb PARAMS ((int));
925 static void s_thumb_func PARAMS ((int));
926 static void s_thumb_set PARAMS ((int));
927 static void arm_s_text PARAMS ((int));
928 static void arm_s_data PARAMS ((int));
930 static void arm_s_section PARAMS ((int));
931 static void s_arm_elf_cons PARAMS ((int));
934 static int my_get_expression PARAMS ((expressionS *, char **));
936 CONST pseudo_typeS md_pseudo_table[] =
938 { "req", s_req, 0 }, /* Never called becasue '.req' does not start line */
940 { "align", s_align, 0 },
942 { "thumb", s_thumb, 0 },
943 { "code", s_code, 0 },
944 { "force_thumb", s_force_thumb, 0 },
945 { "thumb_func", s_thumb_func, 0 },
946 { "thumb_set", s_thumb_set, 0 },
947 { "even", s_even, 0 },
948 { "ltorg", s_ltorg, 0 },
949 { "pool", s_ltorg, 0 },
950 /* Allow for the effect of section changes. */
951 { "text", arm_s_text, 0 },
952 { "data", arm_s_data, 0 },
954 { "section", arm_s_section, 0 },
955 { "section.s", arm_s_section, 0 },
956 { "sect", arm_s_section, 0 },
957 { "sect.s", arm_s_section, 0 },
958 { "word", s_arm_elf_cons, 4 },
959 { "long", s_arm_elf_cons, 4 },
963 { "extend", float_cons, 'x' },
964 { "ldouble", float_cons, 'x' },
965 { "packed", float_cons, 'p' },
969 /* Stuff needed to resolve the label ambiguity
979 symbolS * last_label_seen;
980 static int label_is_thumb_function_name = false;
984 #define MAX_LITERAL_POOL_SIZE 1024
986 typedef struct literalS
988 struct expressionS exp;
989 struct arm_it * inst;
992 literalT literals[MAX_LITERAL_POOL_SIZE];
993 int next_literal_pool_place = 0; /* Next free entry in the pool */
994 int lit_pool_num = 1; /* Next literal pool number */
995 symbolS * current_poolP = NULL;
1002 if (current_poolP == NULL)
1003 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1004 (valueT) 0, &zero_address_frag);
1006 /* Check if this literal value is already in the pool: */
1007 while (lit_count < next_literal_pool_place)
1009 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1010 && inst.reloc.exp.X_op == O_constant
1011 && literals[lit_count].exp.X_add_number
1012 == inst.reloc.exp.X_add_number
1013 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1018 if (lit_count == next_literal_pool_place) /* new entry */
1020 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1022 inst.error = _("Literal Pool Overflow");
1026 literals[next_literal_pool_place].exp = inst.reloc.exp;
1027 lit_count = next_literal_pool_place++;
1030 inst.reloc.exp.X_op = O_symbol;
1031 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1032 inst.reloc.exp.X_add_symbol = current_poolP;
1037 /* Can't use symbol_new here, so have to create a symbol and then at
1038 a later date assign it a value. Thats what these functions do. */
1040 symbol_locate (symbolP, name, segment, valu, frag)
1042 CONST char * name; /* It is copied, the caller can modify */
1043 segT segment; /* Segment identifier (SEG_<something>) */
1044 valueT valu; /* Symbol value */
1045 fragS * frag; /* Associated fragment */
1047 unsigned int name_length;
1048 char * preserved_copy_of_name;
1050 name_length = strlen (name) + 1; /* +1 for \0 */
1051 obstack_grow (¬es, name, name_length);
1052 preserved_copy_of_name = obstack_finish (¬es);
1053 #ifdef STRIP_UNDERSCORE
1054 if (preserved_copy_of_name[0] == '_')
1055 preserved_copy_of_name++;
1058 #ifdef tc_canonicalize_symbol_name
1059 preserved_copy_of_name =
1060 tc_canonicalize_symbol_name (preserved_copy_of_name);
1063 S_SET_NAME (symbolP, preserved_copy_of_name);
1065 S_SET_SEGMENT (symbolP, segment);
1066 S_SET_VALUE (symbolP, valu);
1067 symbol_clear_list_pointers(symbolP);
1069 symbol_set_frag (symbolP, frag);
1071 /* Link to end of symbol chain. */
1073 extern int symbol_table_frozen;
1074 if (symbol_table_frozen)
1078 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1080 obj_symbol_new_hook (symbolP);
1082 #ifdef tc_symbol_new_hook
1083 tc_symbol_new_hook (symbolP);
1087 verify_symbol_chain (symbol_rootP, symbol_lastP);
1088 #endif /* DEBUG_SYMS */
1091 /* Check that an immediate is valid, and if so,
1092 convert it to the right format. */
1094 validate_immediate (val)
1100 #define rotate_left(v, n) (v << n | v >> (32 - n))
1102 for (i = 0; i < 32; i += 2)
1103 if ((a = rotate_left (val, i)) <= 0xff)
1104 return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
1109 /* Check to see if an immediate can be computed as two seperate immediate
1110 values, added together. We already know that this value cannot be
1111 computed by just one ARM instruction. */
1113 validate_immediate_twopart (val, highpart)
1115 unsigned int * highpart;
1120 for (i = 0; i < 32; i += 2)
1121 if (((a = rotate_left (val, i)) & 0xff) != 0)
1127 * highpart = (a >> 8) | ((i + 24) << 7);
1129 else if (a & 0xff0000)
1134 * highpart = (a >> 16) | ((i + 16) << 7);
1138 assert (a & 0xff000000);
1140 * highpart = (a >> 24) | ((i + 8) << 7);
1143 return (a & 0xff) | (i << 7);
1150 validate_offset_imm (val, hwse)
1154 if ((hwse && val > 255) || val > 4095)
1162 int a ATTRIBUTE_UNUSED;
1164 as_bad (_("Invalid syntax for .req directive."));
1169 int ignore ATTRIBUTE_UNUSED;
1171 /* We don't support putting frags in the BSS segment, we fake it by
1172 marking in_bss, then looking at s_skip for clues?.. */
1173 subseg_set (bss_section, 0);
1174 demand_empty_rest_of_line ();
1179 int ignore ATTRIBUTE_UNUSED;
1181 if (!need_pass_2) /* Never make frag if expect extra pass. */
1182 frag_align (1, 0, 0);
1184 record_alignment (now_seg, 1);
1186 demand_empty_rest_of_line ();
1191 int ignored ATTRIBUTE_UNUSED;
1196 if (current_poolP == NULL)
1199 /* Align pool as you have word accesses */
1200 /* Only make a frag if we have to ... */
1202 frag_align (2, 0, 0);
1204 record_alignment (now_seg, 2);
1206 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1208 symbol_locate (current_poolP, sym_name, now_seg,
1209 (valueT) frag_now_fix (), frag_now);
1210 symbol_table_insert (current_poolP);
1212 ARM_SET_THUMB (current_poolP, thumb_mode);
1214 #if defined OBJ_COFF || defined OBJ_ELF
1215 ARM_SET_INTERWORK (current_poolP, support_interwork);
1218 while (lit_count < next_literal_pool_place)
1219 /* First output the expression in the instruction to the pool. */
1220 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1222 next_literal_pool_place = 0;
1223 current_poolP = NULL;
1227 s_align (unused) /* Same as s_align_ptwo but align 0 => align 2 */
1228 int unused ATTRIBUTE_UNUSED;
1231 register long temp_fill;
1232 long max_alignment = 15;
1234 temp = get_absolute_expression ();
1235 if (temp > max_alignment)
1236 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1239 as_bad (_("Alignment negative. 0 assumed."));
1243 if (*input_line_pointer == ',')
1245 input_line_pointer++;
1246 temp_fill = get_absolute_expression ();
1254 /* Only make a frag if we HAVE to. . . */
1255 if (temp && !need_pass_2)
1256 frag_align (temp, (int) temp_fill, 0);
1257 demand_empty_rest_of_line ();
1259 record_alignment (now_seg, temp);
1263 s_force_thumb (ignore)
1264 int ignore ATTRIBUTE_UNUSED;
1266 /* If we are not already in thumb mode go into it, EVEN if
1267 the target processor does not support thumb instructions.
1268 This is used by gcc/config/arm/lib1funcs.asm for example
1269 to compile interworking support functions even if the
1270 target processor should not support interworking. */
1276 record_alignment (now_seg, 1);
1279 demand_empty_rest_of_line ();
1283 s_thumb_func (ignore)
1284 int ignore ATTRIBUTE_UNUSED;
1286 /* The following label is the name/address of the start of a Thumb function.
1287 We need to know this for the interworking support. */
1289 label_is_thumb_function_name = true;
1291 demand_empty_rest_of_line ();
1294 /* Perform a .set directive, but also mark the alias as
1295 being a thumb function. */
1301 /* XXX the following is a duplicate of the code for s_set() in read.c
1302 We cannot just call that code as we need to get at the symbol that
1304 register char * name;
1305 register char delim;
1306 register char * end_name;
1307 register symbolS * symbolP;
1310 * Especial apologies for the random logic:
1311 * this just grew, and could be parsed much more simply!
1314 name = input_line_pointer;
1315 delim = get_symbol_end ();
1316 end_name = input_line_pointer;
1321 if (*input_line_pointer != ',')
1324 as_bad (_("Expected comma after name \"%s\""), name);
1326 ignore_rest_of_line ();
1330 input_line_pointer++;
1333 if (name[0] == '.' && name[1] == '\0')
1335 /* XXX - this should not happen to .thumb_set */
1339 if ((symbolP = symbol_find (name)) == NULL
1340 && (symbolP = md_undefined_symbol (name)) == NULL)
1343 /* When doing symbol listings, play games with dummy fragments living
1344 outside the normal fragment chain to record the file and line info
1346 if (listing & LISTING_SYMBOLS)
1348 extern struct list_info_struct * listing_tail;
1349 fragS * dummy_frag = (fragS *) xmalloc (sizeof(fragS));
1350 memset (dummy_frag, 0, sizeof(fragS));
1351 dummy_frag->fr_type = rs_fill;
1352 dummy_frag->line = listing_tail;
1353 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1354 dummy_frag->fr_symbol = symbolP;
1358 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1361 /* "set" symbols are local unless otherwise specified. */
1362 SF_SET_LOCAL (symbolP);
1363 #endif /* OBJ_COFF */
1364 } /* make a new symbol */
1366 symbol_table_insert (symbolP);
1371 && S_IS_DEFINED (symbolP)
1372 && S_GET_SEGMENT (symbolP) != reg_section)
1373 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1375 pseudo_set (symbolP);
1377 demand_empty_rest_of_line ();
1379 /* XXX Now we come to the Thumb specific bit of code. */
1381 THUMB_SET_FUNC (symbolP, 1);
1382 ARM_SET_THUMB (symbolP, 1);
1383 #if defined OBJ_ELF || defined OBJ_COFF
1384 ARM_SET_INTERWORK (symbolP, support_interwork);
1388 /* If we change section we must dump the literal pool first. */
1393 if (now_seg != text_section)
1397 obj_elf_text (ignore);
1407 if (flag_readonly_data_in_text)
1409 if (now_seg != text_section)
1412 else if (now_seg != data_section)
1416 obj_elf_data (ignore);
1424 arm_s_section (ignore)
1429 obj_elf_section (ignore);
1434 opcode_select (width)
1442 if (! (cpu_variant & ARM_THUMB))
1443 as_bad (_("selected processor does not support THUMB opcodes"));
1445 /* No need to force the alignment, since we will have been
1446 coming from ARM mode, which is word-aligned. */
1447 record_alignment (now_seg, 1);
1454 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1455 as_bad (_("selected processor does not support ARM opcodes"));
1458 frag_align (2, 0, 0);
1459 record_alignment (now_seg, 1);
1464 as_bad (_("invalid instruction size selected (%d)"), width);
1470 int ignore ATTRIBUTE_UNUSED;
1473 demand_empty_rest_of_line ();
1478 int ignore ATTRIBUTE_UNUSED;
1481 demand_empty_rest_of_line ();
1486 int unused ATTRIBUTE_UNUSED;
1490 temp = get_absolute_expression ();
1495 opcode_select (temp);
1499 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1507 skip_whitespace (str);
1510 inst.error = _("Garbage following instruction");
1514 skip_past_comma (str)
1520 while ((c = *p) == ' ' || c == ',')
1523 if (c == ',' && comma++)
1531 return comma ? SUCCESS : FAIL;
1534 /* A standard register must be given at this point.
1535 Shift is the place to put it in inst.instruction.
1536 Restores input start point on err.
1537 Returns the reg#, or FAIL. */
1539 reg_required_here (str, shift)
1543 static char buff [128]; /* XXX */
1545 char * start = *str;
1547 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1550 inst.instruction |= reg << shift;
1554 /* Restore the start point, we may have got a reg of the wrong class. */
1557 /* In the few cases where we might be able to accept something else
1558 this error can be overridden. */
1559 sprintf (buff, _("Register expected, not '%.100s'"), start);
1566 psr_required_here (str, cpsr, spsr)
1572 char * start = *str;
1573 psr = arm_psr_parse (str);
1575 if (psr == cpsr || psr == spsr)
1578 inst.instruction |= 1 << 22;
1583 /* In the few cases where we might be able to accept something else
1584 this error can be overridden. */
1585 inst.error = _("<psr(f)> expected");
1587 /* Restore the start point. */
1593 co_proc_number (str)
1596 int processor, pchar;
1598 skip_whitespace (* str);
1600 /* The data sheet seems to imply that just a number on its own is valid
1601 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1603 if (**str == 'p' || **str == 'P')
1607 if (pchar >= '0' && pchar <= '9')
1609 processor = pchar - '0';
1610 if (**str >= '0' && **str <= '9')
1612 processor = processor * 10 + *(*str)++ - '0';
1615 inst.error = _("Illegal co-processor number");
1622 inst.error = _("Bad or missing co-processor number");
1626 inst.instruction |= processor << 8;
1631 cp_opc_expr (str, where, length)
1638 skip_whitespace (* str);
1640 memset (&expr, '\0', sizeof (expr));
1642 if (my_get_expression (&expr, str))
1644 if (expr.X_op != O_constant)
1646 inst.error = _("bad or missing expression");
1650 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1652 inst.error = _("immediate co-processor expression too large");
1656 inst.instruction |= expr.X_add_number << where;
1661 cp_reg_required_here (str, where)
1666 char * start = *str;
1668 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1671 inst.instruction |= reg << where;
1675 /* In the few cases where we might be able to accept something else
1676 this error can be overridden. */
1677 inst.error = _("Co-processor register expected");
1679 /* Restore the start point. */
1685 fp_reg_required_here (str, where)
1690 char * start = *str;
1692 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1695 inst.instruction |= reg << where;
1699 /* In the few cases where we might be able to accept something else
1700 this error can be overridden. */
1701 inst.error = _("Floating point register expected");
1703 /* Restore the start point. */
1709 cp_address_offset (str)
1714 skip_whitespace (* str);
1716 if (! is_immediate_prefix (**str))
1718 inst.error = _("immediate expression expected");
1724 if (my_get_expression (& inst.reloc.exp, str))
1727 if (inst.reloc.exp.X_op == O_constant)
1729 offset = inst.reloc.exp.X_add_number;
1733 inst.error = _("co-processor address must be word aligned");
1737 if (offset > 1023 || offset < -1023)
1739 inst.error = _("offset too large");
1744 inst.instruction |= INDEX_UP;
1748 inst.instruction |= offset >> 2;
1751 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1757 cp_address_required_here (str)
1769 skip_whitespace (p);
1771 if ((reg = reg_required_here (& p, 16)) == FAIL)
1774 skip_whitespace (p);
1780 if (skip_past_comma (& p) == SUCCESS)
1783 write_back = WRITE_BACK;
1787 inst.error = _("pc may not be used in post-increment");
1791 if (cp_address_offset (& p) == FAIL)
1795 pre_inc = PRE_INDEX | INDEX_UP;
1799 /* '['Rn, #expr']'[!] */
1801 if (skip_past_comma (& p) == FAIL)
1803 inst.error = _("pre-indexed expression expected");
1807 pre_inc = PRE_INDEX;
1809 if (cp_address_offset (& p) == FAIL)
1812 skip_whitespace (p);
1816 inst.error = _("missing ]");
1820 skip_whitespace (p);
1826 inst.error = _("pc may not be used with write-back");
1831 write_back = WRITE_BACK;
1837 if (my_get_expression (&inst.reloc.exp, &p))
1840 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1841 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
1842 inst.reloc.pc_rel = 1;
1843 inst.instruction |= (REG_PC << 16);
1844 pre_inc = PRE_INDEX;
1847 inst.instruction |= write_back | pre_inc;
1855 unsigned long flags;
1857 /* Do nothing really. */
1858 inst.instruction |= flags; /* This is pointless. */
1866 unsigned long flags;
1868 /* Only one syntax. */
1869 skip_whitespace (str);
1871 if (reg_required_here (&str, 12) == FAIL)
1873 inst.error = BAD_ARGS;
1877 if (skip_past_comma (&str) == FAIL
1878 || psr_required_here (& str, CPSR_ALL, SPSR_ALL) == FAIL)
1880 inst.error = _("<psr> expected");
1884 inst.instruction |= flags;
1889 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression". */
1893 unsigned long flags;
1897 skip_whitespace (str);
1899 if (psr_required_here (&str, CPSR_ALL, SPSR_ALL) == SUCCESS)
1901 inst.instruction |= PSR_ALL;
1903 /* Sytax should be "<psr>, Rm" */
1904 if (skip_past_comma (&str) == FAIL
1905 || (reg = reg_required_here (&str, 0)) == FAIL)
1907 inst.error = BAD_ARGS;
1913 if (psr_required_here (& str, CPSR_FLG, SPSR_FLG) == SUCCESS)
1914 inst.instruction |= PSR_FLAGS;
1915 else if (psr_required_here (& str, CPSR_CTL, SPSR_CTL) == SUCCESS)
1916 inst.instruction |= PSR_CONTROL;
1919 inst.error = BAD_ARGS;
1923 if (skip_past_comma (&str) == FAIL)
1925 inst.error = BAD_ARGS;
1929 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1931 if ((reg = reg_required_here (& str, 0)) != FAIL)
1933 /* Immediate expression. */
1934 else if (is_immediate_prefix (* str))
1939 if (my_get_expression (& inst.reloc.exp, & str))
1941 inst.error = _("Register or shift expression expected");
1945 if (inst.reloc.exp.X_add_symbol)
1947 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
1948 inst.reloc.pc_rel = 0;
1952 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
1953 if (value == (unsigned) FAIL)
1955 inst.error = _("Invalid constant");
1959 inst.instruction |= value;
1962 flags |= INST_IMMEDIATE;
1966 inst.error = _("Error: unrecognised syntax for second argument to msr instruction");
1972 inst.instruction |= flags;
1977 /* Long Multiply Parser
1978 UMULL RdLo, RdHi, Rm, Rs
1979 SMULL RdLo, RdHi, Rm, Rs
1980 UMLAL RdLo, RdHi, Rm, Rs
1981 SMLAL RdLo, RdHi, Rm, Rs
1984 do_mull (str, flags)
1986 unsigned long flags;
1988 int rdlo, rdhi, rm, rs;
1990 /* Only one format "rdlo, rdhi, rm, rs" */
1991 skip_whitespace (str);
1993 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
1995 inst.error = BAD_ARGS;
1999 if (skip_past_comma (&str) == FAIL
2000 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2002 inst.error = BAD_ARGS;
2006 if (skip_past_comma (&str) == FAIL
2007 || (rm = reg_required_here (&str, 0)) == FAIL)
2009 inst.error = BAD_ARGS;
2013 /* rdhi, rdlo and rm must all be different */
2014 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2015 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2017 if (skip_past_comma (&str) == FAIL
2018 || (rs = reg_required_here (&str, 8)) == FAIL)
2020 inst.error = BAD_ARGS;
2024 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2026 inst.error = BAD_PC;
2030 inst.instruction |= flags;
2038 unsigned long flags;
2042 /* Only one format "rd, rm, rs" */
2043 skip_whitespace (str);
2045 if ((rd = reg_required_here (&str, 16)) == FAIL)
2047 inst.error = BAD_ARGS;
2053 inst.error = BAD_PC;
2057 if (skip_past_comma (&str) == FAIL
2058 || (rm = reg_required_here (&str, 0)) == FAIL)
2060 inst.error = BAD_ARGS;
2066 inst.error = BAD_PC;
2071 as_tsktsk (_("rd and rm should be different in mul"));
2073 if (skip_past_comma (&str) == FAIL
2074 || (rm = reg_required_here (&str, 8)) == FAIL)
2076 inst.error = BAD_ARGS;
2082 inst.error = BAD_PC;
2086 inst.instruction |= flags;
2094 unsigned long flags;
2098 /* Only one format "rd, rm, rs, rn" */
2099 skip_whitespace (str);
2101 if ((rd = reg_required_here (&str, 16)) == FAIL)
2103 inst.error = BAD_ARGS;
2109 inst.error = BAD_PC;
2113 if (skip_past_comma (&str) == FAIL
2114 || (rm = reg_required_here (&str, 0)) == FAIL)
2116 inst.error = BAD_ARGS;
2122 inst.error = BAD_PC;
2127 as_tsktsk (_("rd and rm should be different in mla"));
2129 if (skip_past_comma (&str) == FAIL
2130 || (rd = reg_required_here (&str, 8)) == FAIL
2131 || skip_past_comma (&str) == FAIL
2132 || (rm = reg_required_here (&str, 12)) == FAIL)
2134 inst.error = BAD_ARGS;
2138 if (rd == REG_PC || rm == REG_PC)
2140 inst.error = BAD_PC;
2144 inst.instruction |= flags;
2149 /* Returns the index into fp_values of a floating point number, or -1 if
2150 not in the table. */
2152 my_get_float_expression (str)
2155 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2161 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2162 /* Look for a raw floating point number */
2163 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2164 && (is_end_of_line [(int)(*save_in)] || *save_in == '\0'))
2166 for (i = 0; i < NUM_FLOAT_VALS; i++)
2168 for (j = 0; j < MAX_LITTLENUMS; j++)
2170 if (words[j] != fp_values[i][j])
2174 if (j == MAX_LITTLENUMS)
2182 /* Try and parse a more complex expression, this will probably fail
2183 unless the code uses a floating point prefix (eg "0f") */
2184 save_in = input_line_pointer;
2185 input_line_pointer = *str;
2186 if (expression (&exp) == absolute_section
2187 && exp.X_op == O_big
2188 && exp.X_add_number < 0)
2190 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2192 if (gen_to_words (words, 5, (long)15) == 0)
2194 for (i = 0; i < NUM_FLOAT_VALS; i++)
2196 for (j = 0; j < MAX_LITTLENUMS; j++)
2198 if (words[j] != fp_values[i][j])
2202 if (j == MAX_LITTLENUMS)
2204 *str = input_line_pointer;
2205 input_line_pointer = save_in;
2212 *str = input_line_pointer;
2213 input_line_pointer = save_in;
2217 /* Return true if anything in the expression is a bignum */
2219 walk_no_bignums (sp)
2222 if (symbol_get_value_expression (sp)->X_op == O_big)
2225 if (symbol_get_value_expression (sp)->X_add_symbol)
2227 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2228 || (symbol_get_value_expression (sp)->X_op_symbol
2229 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2236 my_get_expression (ep, str)
2243 save_in = input_line_pointer;
2244 input_line_pointer = *str;
2245 seg = expression (ep);
2248 if (seg != absolute_section
2249 && seg != text_section
2250 && seg != data_section
2251 && seg != bss_section
2252 && seg != undefined_section)
2254 inst.error = _("bad_segment");
2255 *str = input_line_pointer;
2256 input_line_pointer = save_in;
2261 /* Get rid of any bignums now, so that we don't generate an error for which
2262 we can't establish a line number later on. Big numbers are never valid
2263 in instructions, which is where this routine is always called. */
2264 if (ep->X_op == O_big
2265 || (ep->X_add_symbol
2266 && (walk_no_bignums (ep->X_add_symbol)
2268 && walk_no_bignums (ep->X_op_symbol)))))
2270 inst.error = _("Invalid constant");
2271 *str = input_line_pointer;
2272 input_line_pointer = save_in;
2276 *str = input_line_pointer;
2277 input_line_pointer = save_in;
2281 /* unrestrict should be one if <shift> <register> is permitted for this
2285 decode_shift (str, unrestrict)
2289 struct asm_shift * shft;
2293 skip_whitespace (* str);
2295 for (p = *str; isalpha (*p); p++)
2300 inst.error = _("Shift expression expected");
2306 shft = (struct asm_shift *) hash_find (arm_shift_hsh, *str);
2310 if (!strncmp (*str, "rrx", 3)
2311 || !strncmp (*str, "RRX", 3))
2314 inst.instruction |= shft->value;
2318 skip_whitespace (p);
2320 if (unrestrict && reg_required_here (&p, 8) != FAIL)
2322 inst.instruction |= shft->value | SHIFT_BY_REG;
2326 else if (is_immediate_prefix (* p))
2330 if (my_get_expression (&inst.reloc.exp, &p))
2333 /* Validate some simple #expressions */
2334 if (inst.reloc.exp.X_op == O_constant)
2336 unsigned num = inst.reloc.exp.X_add_number;
2338 /* Reject operations greater than 32, or lsl #32 */
2339 if (num > 32 || (num == 32 && shft->value == 0))
2341 inst.error = _("Invalid immediate shift");
2345 /* Shifts of zero should be converted to lsl (which is zero)*/
2352 /* Shifts of 32 are encoded as 0, for those shifts that
2357 inst.instruction |= (num << 7) | shft->value;
2362 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2363 inst.reloc.pc_rel = 0;
2364 inst.instruction |= shft->value;
2370 inst.error = unrestrict ? _("shift requires register or #expression")
2371 : _("shift requires #expression");
2377 inst.error = _("Shift expression expected");
2381 /* Do those data_ops which can take a negative immediate constant */
2382 /* by altering the instuction. A bit of a hack really */
2386 by inverting the second operand, and
2389 by negating the second operand.
2392 negate_data_op (instruction, value)
2393 unsigned long * instruction;
2394 unsigned long value;
2397 unsigned long negated, inverted;
2399 negated = validate_immediate (-value);
2400 inverted = validate_immediate (~value);
2402 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2406 case OPCODE_SUB: /* ADD <-> SUB */
2407 new_inst = OPCODE_ADD;
2412 new_inst = OPCODE_SUB;
2416 case OPCODE_CMP: /* CMP <-> CMN */
2417 new_inst = OPCODE_CMN;
2422 new_inst = OPCODE_CMP;
2426 /* Now Inverted ops */
2427 case OPCODE_MOV: /* MOV <-> MVN */
2428 new_inst = OPCODE_MVN;
2433 new_inst = OPCODE_MOV;
2437 case OPCODE_AND: /* AND <-> BIC */
2438 new_inst = OPCODE_BIC;
2443 new_inst = OPCODE_AND;
2447 case OPCODE_ADC: /* ADC <-> SBC */
2448 new_inst = OPCODE_SBC;
2453 new_inst = OPCODE_ADC;
2457 /* We cannot do anything */
2462 if (value == (unsigned) FAIL)
2465 *instruction &= OPCODE_MASK;
2466 *instruction |= new_inst << DATA_OP_SHIFT;
2477 skip_whitespace (* str);
2479 if (reg_required_here (str, 0) != FAIL)
2481 if (skip_past_comma (str) == SUCCESS)
2482 /* Shift operation on register. */
2483 return decode_shift (str, NO_SHIFT_RESTRICT);
2489 /* Immediate expression */
2490 if (is_immediate_prefix (**str))
2495 if (my_get_expression (&inst.reloc.exp, str))
2498 if (inst.reloc.exp.X_add_symbol)
2500 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2501 inst.reloc.pc_rel = 0;
2505 if (skip_past_comma (str) == SUCCESS)
2507 /* #x, y -- ie explicit rotation by Y */
2508 if (my_get_expression (&expr, str))
2511 if (expr.X_op != O_constant)
2513 inst.error = _("Constant expression expected");
2517 /* Rotate must be a multiple of 2 */
2518 if (((unsigned) expr.X_add_number) > 30
2519 || (expr.X_add_number & 1) != 0
2520 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2522 inst.error = _("Invalid constant");
2525 inst.instruction |= INST_IMMEDIATE;
2526 inst.instruction |= inst.reloc.exp.X_add_number;
2527 inst.instruction |= expr.X_add_number << 7;
2531 /* Implicit rotation, select a suitable one */
2532 value = validate_immediate (inst.reloc.exp.X_add_number);
2536 /* Can't be done, perhaps the code reads something like
2537 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2538 if ((value = negate_data_op (&inst.instruction,
2539 inst.reloc.exp.X_add_number))
2542 inst.error = _("Invalid constant");
2547 inst.instruction |= value;
2550 inst.instruction |= INST_IMMEDIATE;
2555 inst.error = _("Register or shift expression expected");
2564 skip_whitespace (* str);
2566 if (fp_reg_required_here (str, 0) != FAIL)
2570 /* Immediate expression */
2571 if (*((*str)++) == '#')
2577 skip_whitespace (* str);
2579 /* First try and match exact strings, this is to guarantee that
2580 some formats will work even for cross assembly */
2582 for (i = 0; fp_const[i]; i++)
2584 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2588 *str += strlen (fp_const[i]);
2589 if (is_end_of_line[(int)**str] || **str == '\0')
2591 inst.instruction |= i + 8;
2598 /* Just because we didn't get a match doesn't mean that the
2599 constant isn't valid, just that it is in a format that we
2600 don't automatically recognize. Try parsing it with
2601 the standard expression routines. */
2602 if ((i = my_get_float_expression (str)) >= 0)
2604 inst.instruction |= i + 8;
2608 inst.error = _("Invalid floating point immediate expression");
2611 inst.error = _("Floating point register or immediate expression expected");
2617 do_arit (str, flags)
2619 unsigned long flags;
2621 skip_whitespace (str);
2623 if (reg_required_here (&str, 12) == FAIL
2624 || skip_past_comma (&str) == FAIL
2625 || reg_required_here (&str, 16) == FAIL
2626 || skip_past_comma (&str) == FAIL
2627 || data_op2 (&str) == FAIL)
2630 inst.error = BAD_ARGS;
2634 inst.instruction |= flags;
2642 unsigned long flags;
2644 /* This is a pseudo-op of the form "adr rd, label" to be converted
2645 into a relative address of the form "add rd, pc, #label-.-8". */
2646 skip_whitespace (str);
2648 if (reg_required_here (&str, 12) == FAIL
2649 || skip_past_comma (&str) == FAIL
2650 || my_get_expression (&inst.reloc.exp, &str))
2653 inst.error = BAD_ARGS;
2657 /* Frag hacking will turn this into a sub instruction if the offset turns
2658 out to be negative. */
2659 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2660 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
2661 inst.reloc.pc_rel = 1;
2662 inst.instruction |= flags;
2668 do_adrl (str, flags)
2670 unsigned long flags;
2672 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2673 into a relative address of the form:
2674 add rd, pc, #low(label-.-8)"
2675 add rd, rd, #high(label-.-8)" */
2677 skip_whitespace (str);
2679 if (reg_required_here (& str, 12) == FAIL
2680 || skip_past_comma (& str) == FAIL
2681 || my_get_expression (& inst.reloc.exp, & str))
2684 inst.error = BAD_ARGS;
2690 /* Frag hacking will turn this into a sub instruction if the offset turns
2691 out to be negative. */
2692 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2693 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2694 inst.reloc.pc_rel = 1;
2695 inst.instruction |= flags;
2696 inst.size = INSN_SIZE * 2;
2704 unsigned long flags;
2706 skip_whitespace (str);
2708 if (reg_required_here (&str, 16) == FAIL)
2711 inst.error = BAD_ARGS;
2715 if (skip_past_comma (&str) == FAIL
2716 || data_op2 (&str) == FAIL)
2719 inst.error = BAD_ARGS;
2723 inst.instruction |= flags;
2724 if ((flags & 0x0000f000) == 0)
2725 inst.instruction |= CONDS_BIT;
2734 unsigned long flags;
2736 skip_whitespace (str);
2738 if (reg_required_here (&str, 12) == FAIL)
2741 inst.error = BAD_ARGS;
2745 if (skip_past_comma (&str) == FAIL
2746 || data_op2 (&str) == FAIL)
2749 inst.error = BAD_ARGS;
2753 inst.instruction |= flags;
2759 ldst_extend (str, hwse)
2770 if (my_get_expression (& inst.reloc.exp, str))
2773 if (inst.reloc.exp.X_op == O_constant)
2775 int value = inst.reloc.exp.X_add_number;
2777 if ((hwse && (value < -255 || value > 255))
2778 || (value < -4095 || value > 4095))
2780 inst.error = _("address offset too large");
2790 /* Halfword and signextension instructions have the
2791 immediate value split across bits 11..8 and bits 3..0 */
2793 inst.instruction |= add | HWOFFSET_IMM | ((value >> 4) << 8) | (value & 0xF);
2795 inst.instruction |= add | value;
2801 inst.instruction |= HWOFFSET_IMM;
2802 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2805 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2806 inst.reloc.pc_rel = 0;
2811 add = 0; /* and fall through */
2813 (*str)++; /* and fall through */
2815 if (reg_required_here (str, 0) == FAIL)
2819 inst.instruction |= add;
2822 inst.instruction |= add | OFFSET_REG;
2823 if (skip_past_comma (str) == SUCCESS)
2824 return decode_shift (str, SHIFT_RESTRICT);
2832 do_ldst (str, flags)
2834 unsigned long flags;
2841 /* This is not ideal, but it is the simplest way of dealing with the
2842 ARM7T halfword instructions (since they use a different
2843 encoding, but the same mnemonic): */
2844 halfword = (flags & 0x80000000) != 0;
2847 /* This is actually a load/store of a halfword, or a
2848 signed-extension load */
2849 if ((cpu_variant & ARM_HALFWORD) == 0)
2852 = _("Processor does not support halfwords or signed bytes");
2856 inst.instruction = (inst.instruction & COND_MASK)
2857 | (flags & ~COND_MASK);
2862 skip_whitespace (str);
2864 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
2867 inst.error = BAD_ARGS;
2871 if (skip_past_comma (& str) == FAIL)
2873 inst.error = _("Address expected");
2883 skip_whitespace (str);
2885 if ((reg = reg_required_here (&str, 16)) == FAIL)
2888 /* Conflicts can occur on stores as well as loads. */
2889 conflict_reg = (conflict_reg == reg);
2891 skip_whitespace (str);
2897 if (skip_past_comma (&str) == SUCCESS)
2899 /* [Rn],... (post inc) */
2900 if (ldst_extend (&str, halfword) == FAIL)
2903 as_warn (_("%s register same as write-back base"),
2904 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2910 inst.instruction |= HWOFFSET_IMM;
2912 skip_whitespace (str);
2917 as_warn (_("%s register same as write-back base"),
2918 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2920 inst.instruction |= WRITE_BACK;
2924 if (! (flags & TRANS_BIT))
2931 if (skip_past_comma (&str) == FAIL)
2933 inst.error = _("pre-indexed expression expected");
2938 if (ldst_extend (&str, halfword) == FAIL)
2941 skip_whitespace (str);
2945 inst.error = _("missing ]");
2949 skip_whitespace (str);
2954 as_warn (_("%s register same as write-back base"),
2955 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2957 inst.instruction |= WRITE_BACK;
2961 else if (*str == '=')
2963 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2966 skip_whitespace (str);
2968 if (my_get_expression (&inst.reloc.exp, &str))
2971 if (inst.reloc.exp.X_op != O_constant
2972 && inst.reloc.exp.X_op != O_symbol)
2974 inst.error = _("Constant expression expected");
2978 if (inst.reloc.exp.X_op == O_constant
2979 && (value = validate_immediate(inst.reloc.exp.X_add_number)) != FAIL)
2981 /* This can be done with a mov instruction */
2982 inst.instruction &= LITERAL_MASK;
2983 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
2984 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
2990 /* Insert into literal pool */
2991 if (add_to_lit_pool () == FAIL)
2994 inst.error = _("literal pool insertion failed");
2998 /* Change the instruction exp to point to the pool */
3001 inst.instruction |= HWOFFSET_IMM;
3002 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
3005 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
3006 inst.reloc.pc_rel = 1;
3007 inst.instruction |= (REG_PC << 16);
3013 if (my_get_expression (&inst.reloc.exp, &str))
3018 inst.instruction |= HWOFFSET_IMM;
3019 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3022 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3024 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
3026 inst.reloc.pc_rel = 1;
3027 inst.instruction |= (REG_PC << 16);
3031 if (pre_inc && (flags & TRANS_BIT))
3032 inst.error = _("Pre-increment instruction with translate");
3034 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3047 /* We come back here if we get ranges concatenated by '+' or '|' */
3062 skip_whitespace (str);
3064 if ((reg = reg_required_here (& str, -1)) == FAIL)
3073 inst.error = _("Bad range in register list");
3077 for (i = cur_reg + 1; i < reg; i++)
3079 if (range & (1 << i))
3081 (_("Warning: Duplicated register (r%d) in register list"),
3089 if (range & (1 << reg))
3090 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3092 else if (reg <= cur_reg)
3093 as_tsktsk (_("Warning: Register range not in ascending order"));
3097 } while (skip_past_comma (&str) != FAIL
3098 || (in_range = 1, *str++ == '-'));
3100 skip_whitespace (str);
3104 inst.error = _("Missing `}'");
3112 if (my_get_expression (&expr, &str))
3115 if (expr.X_op == O_constant)
3117 if (expr.X_add_number
3118 != (expr.X_add_number & 0x0000ffff))
3120 inst.error = _("invalid register mask");
3124 if ((range & expr.X_add_number) != 0)
3126 int regno = range & expr.X_add_number;
3129 regno = (1 << regno) - 1;
3131 (_("Warning: Duplicated register (r%d) in register list"),
3135 range |= expr.X_add_number;
3139 if (inst.reloc.type != 0)
3141 inst.error = _("expression too complex");
3145 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3146 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3147 inst.reloc.pc_rel = 0;
3151 skip_whitespace (str);
3153 if (*str == '|' || *str == '+')
3158 } while (another_range);
3165 do_ldmstm (str, flags)
3167 unsigned long flags;
3172 skip_whitespace (str);
3174 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3177 if (base_reg == REG_PC)
3179 inst.error = _("r15 not allowed as base register");
3183 skip_whitespace (str);
3187 flags |= WRITE_BACK;
3191 if (skip_past_comma (&str) == FAIL
3192 || (range = reg_list (&str)) == FAIL)
3195 inst.error = BAD_ARGS;
3202 flags |= LDM_TYPE_2_OR_3;
3205 inst.instruction |= flags | range;
3213 unsigned long flags;
3215 skip_whitespace (str);
3217 /* Allow optional leading '#'. */
3218 if (is_immediate_prefix (*str))
3221 if (my_get_expression (& inst.reloc.exp, & str))
3224 inst.reloc.type = BFD_RELOC_ARM_SWI;
3225 inst.reloc.pc_rel = 0;
3226 inst.instruction |= flags;
3234 do_swap (str, flags)
3236 unsigned long flags;
3240 skip_whitespace (str);
3242 if ((reg = reg_required_here (&str, 12)) == FAIL)
3247 inst.error = _("r15 not allowed in swap");
3251 if (skip_past_comma (&str) == FAIL
3252 || (reg = reg_required_here (&str, 0)) == FAIL)
3255 inst.error = BAD_ARGS;
3261 inst.error = _("r15 not allowed in swap");
3265 if (skip_past_comma (&str) == FAIL
3268 inst.error = BAD_ARGS;
3272 skip_whitespace (str);
3274 if ((reg = reg_required_here (&str, 16)) == FAIL)
3279 inst.error = BAD_PC;
3283 skip_whitespace (str);
3287 inst.error = _("missing ]");
3291 inst.instruction |= flags;
3297 do_branch (str, flags)
3299 unsigned long flags ATTRIBUTE_UNUSED;
3301 if (my_get_expression (&inst.reloc.exp, &str))
3308 /* ScottB: February 5, 1998 */
3309 /* Check to see of PLT32 reloc required for the instruction. */
3311 /* arm_parse_reloc() works on input_line_pointer.
3312 We actually want to parse the operands to the branch instruction
3313 passed in 'str'. Save the input pointer and restore it later. */
3314 save_in = input_line_pointer;
3315 input_line_pointer = str;
3316 if (inst.reloc.exp.X_op == O_symbol
3318 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3320 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3321 inst.reloc.pc_rel = 0;
3322 /* Modify str to point to after parsed operands, otherwise
3323 end_of_line() will complain about the (PLT) left in str. */
3324 str = input_line_pointer;
3328 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3329 inst.reloc.pc_rel = 1;
3331 input_line_pointer = save_in;
3334 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3335 inst.reloc.pc_rel = 1;
3336 #endif /* OBJ_ELF */
3345 unsigned long flags ATTRIBUTE_UNUSED;
3349 skip_whitespace (str);
3351 if ((reg = reg_required_here (&str, 0)) == FAIL)
3353 inst.error = BAD_ARGS;
3358 inst.error = BAD_PC;
3366 unsigned long flags ATTRIBUTE_UNUSED;
3368 /* Co-processor data operation.
3369 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3370 skip_whitespace (str);
3372 if (co_proc_number (&str) == FAIL)
3375 inst.error = BAD_ARGS;
3379 if (skip_past_comma (&str) == FAIL
3380 || cp_opc_expr (&str, 20,4) == FAIL)
3383 inst.error = BAD_ARGS;
3387 if (skip_past_comma (&str) == FAIL
3388 || cp_reg_required_here (&str, 12) == FAIL)
3391 inst.error = BAD_ARGS;
3395 if (skip_past_comma (&str) == FAIL
3396 || cp_reg_required_here (&str, 16) == FAIL)
3399 inst.error = BAD_ARGS;
3403 if (skip_past_comma (&str) == FAIL
3404 || cp_reg_required_here (&str, 0) == FAIL)
3407 inst.error = BAD_ARGS;
3411 if (skip_past_comma (&str) == SUCCESS)
3413 if (cp_opc_expr (&str, 5, 3) == FAIL)
3416 inst.error = BAD_ARGS;
3426 do_lstc (str, flags)
3428 unsigned long flags;
3430 /* Co-processor register load/store.
3431 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3433 skip_whitespace (str);
3435 if (co_proc_number (&str) == FAIL)
3438 inst.error = BAD_ARGS;
3442 if (skip_past_comma (&str) == FAIL
3443 || cp_reg_required_here (&str, 12) == FAIL)
3446 inst.error = BAD_ARGS;
3450 if (skip_past_comma (&str) == FAIL
3451 || cp_address_required_here (&str) == FAIL)
3454 inst.error = BAD_ARGS;
3458 inst.instruction |= flags;
3464 do_co_reg (str, flags)
3466 unsigned long flags;
3468 /* Co-processor register transfer.
3469 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3471 skip_whitespace (str);
3473 if (co_proc_number (&str) == FAIL)
3476 inst.error = BAD_ARGS;
3480 if (skip_past_comma (&str) == FAIL
3481 || cp_opc_expr (&str, 21, 3) == FAIL)
3484 inst.error = BAD_ARGS;
3488 if (skip_past_comma (&str) == FAIL
3489 || reg_required_here (&str, 12) == FAIL)
3492 inst.error = BAD_ARGS;
3496 if (skip_past_comma (&str) == FAIL
3497 || cp_reg_required_here (&str, 16) == FAIL)
3500 inst.error = BAD_ARGS;
3504 if (skip_past_comma (&str) == FAIL
3505 || cp_reg_required_here (&str, 0) == FAIL)
3508 inst.error = BAD_ARGS;
3512 if (skip_past_comma (&str) == SUCCESS)
3514 if (cp_opc_expr (&str, 5, 3) == FAIL)
3517 inst.error = BAD_ARGS;
3523 inst.error = BAD_COND;
3531 do_fp_ctrl (str, flags)
3533 unsigned long flags ATTRIBUTE_UNUSED;
3535 /* FP control registers.
3536 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3538 skip_whitespace (str);
3540 if (reg_required_here (&str, 12) == FAIL)
3543 inst.error = BAD_ARGS;
3552 do_fp_ldst (str, flags)
3554 unsigned long flags ATTRIBUTE_UNUSED;
3556 skip_whitespace (str);
3558 switch (inst.suffix)
3563 inst.instruction |= CP_T_X;
3566 inst.instruction |= CP_T_Y;
3569 inst.instruction |= CP_T_X | CP_T_Y;
3575 if (fp_reg_required_here (&str, 12) == FAIL)
3578 inst.error = BAD_ARGS;
3582 if (skip_past_comma (&str) == FAIL
3583 || cp_address_required_here (&str) == FAIL)
3586 inst.error = BAD_ARGS;
3594 do_fp_ldmstm (str, flags)
3596 unsigned long flags;
3600 skip_whitespace (str);
3602 if (fp_reg_required_here (&str, 12) == FAIL)
3605 inst.error = BAD_ARGS;
3609 /* Get Number of registers to transfer */
3610 if (skip_past_comma (&str) == FAIL
3611 || my_get_expression (&inst.reloc.exp, &str))
3614 inst.error = _("constant expression expected");
3618 if (inst.reloc.exp.X_op != O_constant)
3620 inst.error = _("Constant value required for number of registers");
3624 num_regs = inst.reloc.exp.X_add_number;
3626 if (num_regs < 1 || num_regs > 4)
3628 inst.error = _("number of registers must be in the range [1:4]");
3635 inst.instruction |= CP_T_X;
3638 inst.instruction |= CP_T_Y;
3641 inst.instruction |= CP_T_Y | CP_T_X;
3655 /* The instruction specified "ea" or "fd", so we can only accept
3656 [Rn]{!}. The instruction does not really support stacking or
3657 unstacking, so we have to emulate these by setting appropriate
3658 bits and offsets. */
3659 if (skip_past_comma (&str) == FAIL
3663 inst.error = BAD_ARGS;
3668 skip_whitespace (str);
3670 if ((reg = reg_required_here (&str, 16)) == FAIL)
3673 skip_whitespace (str);
3677 inst.error = BAD_ARGS;
3688 inst.error = _("R15 not allowed as base register with write-back");
3695 if (flags & CP_T_Pre)
3698 offset = 3 * num_regs;
3704 /* Post-increment */
3708 offset = 3 * num_regs;
3712 /* No write-back, so convert this into a standard pre-increment
3713 instruction -- aesthetically more pleasing. */
3714 flags = CP_T_Pre | CP_T_UD;
3719 inst.instruction |= flags | offset;
3721 else if (skip_past_comma (&str) == FAIL
3722 || cp_address_required_here (&str) == FAIL)
3725 inst.error = BAD_ARGS;
3733 do_fp_dyadic (str, flags)
3735 unsigned long flags;
3737 skip_whitespace (str);
3739 switch (inst.suffix)
3744 inst.instruction |= 0x00000080;
3747 inst.instruction |= 0x00080000;
3753 if (fp_reg_required_here (&str, 12) == FAIL)
3756 inst.error = BAD_ARGS;
3760 if (skip_past_comma (&str) == FAIL
3761 || fp_reg_required_here (&str, 16) == FAIL)
3764 inst.error = BAD_ARGS;
3768 if (skip_past_comma (&str) == FAIL
3769 || fp_op2 (&str) == FAIL)
3772 inst.error = BAD_ARGS;
3776 inst.instruction |= flags;
3782 do_fp_monadic (str, flags)
3784 unsigned long flags;
3786 skip_whitespace (str);
3788 switch (inst.suffix)
3793 inst.instruction |= 0x00000080;
3796 inst.instruction |= 0x00080000;
3802 if (fp_reg_required_here (&str, 12) == FAIL)
3805 inst.error = BAD_ARGS;
3809 if (skip_past_comma (&str) == FAIL
3810 || fp_op2 (&str) == FAIL)
3813 inst.error = BAD_ARGS;
3817 inst.instruction |= flags;
3823 do_fp_cmp (str, flags)
3825 unsigned long flags;
3827 skip_whitespace (str);
3829 if (fp_reg_required_here (&str, 16) == FAIL)
3832 inst.error = BAD_ARGS;
3836 if (skip_past_comma (&str) == FAIL
3837 || fp_op2 (&str) == FAIL)
3840 inst.error = BAD_ARGS;
3844 inst.instruction |= flags;
3850 do_fp_from_reg (str, flags)
3852 unsigned long flags;
3854 skip_whitespace (str);
3856 switch (inst.suffix)
3861 inst.instruction |= 0x00000080;
3864 inst.instruction |= 0x00080000;
3870 if (fp_reg_required_here (&str, 16) == FAIL)
3873 inst.error = BAD_ARGS;
3877 if (skip_past_comma (&str) == FAIL
3878 || reg_required_here (&str, 12) == FAIL)
3881 inst.error = BAD_ARGS;
3885 inst.instruction |= flags;
3891 do_fp_to_reg (str, flags)
3893 unsigned long flags;
3895 skip_whitespace (str);
3897 if (reg_required_here (&str, 12) == FAIL)
3900 if (skip_past_comma (&str) == FAIL
3901 || fp_reg_required_here (&str, 0) == FAIL)
3904 inst.error = BAD_ARGS;
3908 inst.instruction |= flags;
3913 /* Thumb specific routines */
3915 /* Parse and validate that a register is of the right form, this saves
3916 repeated checking of this information in many similar cases.
3917 Unlike the 32-bit case we do not insert the register into the opcode
3918 here, since the position is often unknown until the full instruction
3921 thumb_reg (strp, hi_lo)
3927 if ((reg = reg_required_here (strp, -1)) == FAIL)
3935 inst.error = _("lo register required");
3943 inst.error = _("hi register required");
3955 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3958 thumb_add_sub (str, subtract)
3962 int Rd, Rs, Rn = FAIL;
3964 skip_whitespace (str);
3966 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
3967 || skip_past_comma (&str) == FAIL)
3970 inst.error = BAD_ARGS;
3974 if (is_immediate_prefix (*str))
3978 if (my_get_expression (&inst.reloc.exp, &str))
3983 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3986 if (skip_past_comma (&str) == FAIL)
3988 /* Two operand format, shuffle the registers and pretend there
3993 else if (is_immediate_prefix (*str))
3996 if (my_get_expression (&inst.reloc.exp, &str))
3999 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4003 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4004 for the latter case, EXPR contains the immediate that was found. */
4007 /* All register format. */
4008 if (Rd > 7 || Rs > 7 || Rn > 7)
4012 inst.error = _("dest and source1 must be the same register");
4016 /* Can't do this for SUB */
4019 inst.error = _("subtract valid only on lo regs");
4023 inst.instruction = (T_OPCODE_ADD_HI
4024 | (Rd > 7 ? THUMB_H1 : 0)
4025 | (Rn > 7 ? THUMB_H2 : 0));
4026 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4030 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4031 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4036 /* Immediate expression, now things start to get nasty. */
4038 /* First deal with HI regs, only very restricted cases allowed:
4039 Adjusting SP, and using PC or SP to get an address. */
4040 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4041 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4043 inst.error = _("invalid Hi register with immediate");
4047 if (inst.reloc.exp.X_op != O_constant)
4049 /* Value isn't known yet, all we can do is store all the fragments
4050 we know about in the instruction and let the reloc hacking
4052 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4053 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4057 int offset = inst.reloc.exp.X_add_number;
4067 /* Quick check, in case offset is MIN_INT */
4070 inst.error = _("immediate value out of range");
4079 if (offset & ~0x1fc)
4081 inst.error = _("invalid immediate value for stack adjust");
4084 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4085 inst.instruction |= offset >> 2;
4087 else if (Rs == REG_PC || Rs == REG_SP)
4090 || (offset & ~0x3fc))
4092 inst.error = _("invalid immediate for address calculation");
4095 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4097 inst.instruction |= (Rd << 8) | (offset >> 2);
4103 inst.error = _("immediate value out of range");
4106 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4107 inst.instruction |= (Rd << 8) | offset;
4113 inst.error = _("immediate value out of range");
4116 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4117 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4126 thumb_shift (str, shift)
4130 int Rd, Rs, Rn = FAIL;
4132 skip_whitespace (str);
4134 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4135 || skip_past_comma (&str) == FAIL)
4138 inst.error = BAD_ARGS;
4142 if (is_immediate_prefix (*str))
4144 /* Two operand immediate format, set Rs to Rd. */
4147 if (my_get_expression (&inst.reloc.exp, &str))
4152 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4155 if (skip_past_comma (&str) == FAIL)
4157 /* Two operand format, shuffle the registers and pretend there
4162 else if (is_immediate_prefix (*str))
4165 if (my_get_expression (&inst.reloc.exp, &str))
4168 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4172 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4173 for the latter case, EXPR contains the immediate that was found. */
4179 inst.error = _("source1 and dest must be same register");
4185 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4186 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4187 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4190 inst.instruction |= Rd | (Rn << 3);
4196 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4197 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4198 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4201 if (inst.reloc.exp.X_op != O_constant)
4203 /* Value isn't known yet, create a dummy reloc and let reloc
4204 hacking fix it up */
4206 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4210 unsigned shift_value = inst.reloc.exp.X_add_number;
4212 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4214 inst.error = _("Invalid immediate for shift");
4218 /* Shifts of zero are handled by converting to LSL */
4219 if (shift_value == 0)
4220 inst.instruction = T_OPCODE_LSL_I;
4222 /* Shifts of 32 are encoded as a shift of zero */
4223 if (shift_value == 32)
4226 inst.instruction |= shift_value << 6;
4229 inst.instruction |= Rd | (Rs << 3);
4236 thumb_mov_compare (str, move)
4242 skip_whitespace (str);
4244 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4245 || skip_past_comma (&str) == FAIL)
4248 inst.error = BAD_ARGS;
4252 if (is_immediate_prefix (*str))
4255 if (my_get_expression (&inst.reloc.exp, &str))
4258 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4263 if (Rs < 8 && Rd < 8)
4265 if (move == THUMB_MOVE)
4266 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4267 since a MOV instruction produces unpredictable results */
4268 inst.instruction = T_OPCODE_ADD_I3;
4270 inst.instruction = T_OPCODE_CMP_LR;
4271 inst.instruction |= Rd | (Rs << 3);
4275 if (move == THUMB_MOVE)
4276 inst.instruction = T_OPCODE_MOV_HR;
4278 inst.instruction = T_OPCODE_CMP_HR;
4281 inst.instruction |= THUMB_H1;
4284 inst.instruction |= THUMB_H2;
4286 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4293 inst.error = _("only lo regs allowed with immediate");
4297 if (move == THUMB_MOVE)
4298 inst.instruction = T_OPCODE_MOV_I8;
4300 inst.instruction = T_OPCODE_CMP_I8;
4302 inst.instruction |= Rd << 8;
4304 if (inst.reloc.exp.X_op != O_constant)
4305 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4308 unsigned value = inst.reloc.exp.X_add_number;
4312 inst.error = _("invalid immediate");
4316 inst.instruction |= value;
4324 thumb_load_store (str, load_store, size)
4329 int Rd, Rb, Ro = FAIL;
4331 skip_whitespace (str);
4333 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4334 || skip_past_comma (&str) == FAIL)
4337 inst.error = BAD_ARGS;
4344 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4347 if (skip_past_comma (&str) != FAIL)
4349 if (is_immediate_prefix (*str))
4352 if (my_get_expression (&inst.reloc.exp, &str))
4355 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4360 inst.reloc.exp.X_op = O_constant;
4361 inst.reloc.exp.X_add_number = 0;
4366 inst.error = _("expected ']'");
4371 else if (*str == '=')
4373 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4376 skip_whitespace (str);
4378 if (my_get_expression (& inst.reloc.exp, & str))
4383 if ( inst.reloc.exp.X_op != O_constant
4384 && inst.reloc.exp.X_op != O_symbol)
4386 inst.error = "Constant expression expected";
4390 if (inst.reloc.exp.X_op == O_constant
4391 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4393 /* This can be done with a mov instruction */
4395 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4396 inst.instruction |= inst.reloc.exp.X_add_number;
4400 /* Insert into literal pool */
4401 if (add_to_lit_pool () == FAIL)
4404 inst.error = "literal pool insertion failed";
4408 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4409 inst.reloc.pc_rel = 1;
4410 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4411 inst.reloc.exp.X_add_number += 4; /* Adjust ARM pipeline offset to Thumb */
4417 if (my_get_expression (&inst.reloc.exp, &str))
4420 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4421 inst.reloc.pc_rel = 1;
4422 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset */
4423 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4428 if (Rb == REG_PC || Rb == REG_SP)
4430 if (size != THUMB_WORD)
4432 inst.error = _("byte or halfword not valid for base register");
4435 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4437 inst.error = _("R15 based store not allowed");
4440 else if (Ro != FAIL)
4442 inst.error = _("Invalid base register for register offset");
4447 inst.instruction = T_OPCODE_LDR_PC;
4448 else if (load_store == THUMB_LOAD)
4449 inst.instruction = T_OPCODE_LDR_SP;
4451 inst.instruction = T_OPCODE_STR_SP;
4453 inst.instruction |= Rd << 8;
4454 if (inst.reloc.exp.X_op == O_constant)
4456 unsigned offset = inst.reloc.exp.X_add_number;
4458 if (offset & ~0x3fc)
4460 inst.error = _("invalid offset");
4464 inst.instruction |= offset >> 2;
4467 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4471 inst.error = _("invalid base register in load/store");
4474 else if (Ro == FAIL)
4476 /* Immediate offset */
4477 if (size == THUMB_WORD)
4478 inst.instruction = (load_store == THUMB_LOAD
4479 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4480 else if (size == THUMB_HALFWORD)
4481 inst.instruction = (load_store == THUMB_LOAD
4482 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4484 inst.instruction = (load_store == THUMB_LOAD
4485 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4487 inst.instruction |= Rd | (Rb << 3);
4489 if (inst.reloc.exp.X_op == O_constant)
4491 unsigned offset = inst.reloc.exp.X_add_number;
4493 if (offset & ~(0x1f << size))
4495 inst.error = _("Invalid offset");
4498 inst.instruction |= (offset >> size) << 6;
4501 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4505 /* Register offset */
4506 if (size == THUMB_WORD)
4507 inst.instruction = (load_store == THUMB_LOAD
4508 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4509 else if (size == THUMB_HALFWORD)
4510 inst.instruction = (load_store == THUMB_LOAD
4511 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4513 inst.instruction = (load_store == THUMB_LOAD
4514 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4516 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4531 /* Handle the Format 4 instructions that do not have equivalents in other
4532 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4540 skip_whitespace (str);
4542 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4543 || skip_past_comma (&str) == FAIL
4544 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4546 inst.error = BAD_ARGS;
4550 if (skip_past_comma (&str) != FAIL)
4552 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4553 (It isn't allowed for CMP either, but that isn't handled by this
4555 if (inst.instruction == T_OPCODE_TST
4556 || inst.instruction == T_OPCODE_CMN
4557 || inst.instruction == T_OPCODE_NEG
4558 || inst.instruction == T_OPCODE_MVN)
4560 inst.error = BAD_ARGS;
4564 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4569 inst.error = _("dest and source1 one must be the same register");
4575 if (inst.instruction == T_OPCODE_MUL
4577 as_tsktsk (_("Rs and Rd must be different in MUL"));
4579 inst.instruction |= Rd | (Rs << 3);
4587 thumb_add_sub (str, 0);
4594 thumb_shift (str, THUMB_ASR);
4601 if (my_get_expression (&inst.reloc.exp, &str))
4603 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4604 inst.reloc.pc_rel = 1;
4612 if (my_get_expression (&inst.reloc.exp, &str))
4614 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4615 inst.reloc.pc_rel = 1;
4619 /* Find the real, Thumb encoded start of a Thumb function. */
4622 find_real_start (symbolP)
4626 const char * name = S_GET_NAME (symbolP);
4627 symbolS * new_target;
4629 /* This definiton must agree with the one in gcc/config/arm/thumb.c */
4630 #define STUB_NAME ".real_start_of"
4635 /* Names that start with '.' are local labels, not function entry points.
4636 The compiler may generate BL instructions to these labels because it
4637 needs to perform a branch to a far away location. */
4641 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4642 sprintf (real_start, "%s%s", STUB_NAME, name);
4644 new_target = symbol_find (real_start);
4646 if (new_target == NULL)
4648 as_warn ("Failed to find real start of function: %s\n", name);
4649 new_target = symbolP;
4662 if (my_get_expression (& inst.reloc.exp, & str))
4665 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4666 inst.reloc.pc_rel = 1;
4669 /* If the destination of the branch is a defined symbol which does not have
4670 the THUMB_FUNC attribute, then we must be calling a function which has
4671 the (interfacearm) attribute. We look for the Thumb entry point to that
4672 function and change the branch to refer to that function instead. */
4673 if ( inst.reloc.exp.X_op == O_symbol
4674 && inst.reloc.exp.X_add_symbol != NULL
4675 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4676 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4677 inst.reloc.exp.X_add_symbol = find_real_start (inst.reloc.exp.X_add_symbol);
4686 skip_whitespace (str);
4688 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4691 /* This sets THUMB_H2 from the top bit of reg. */
4692 inst.instruction |= reg << 3;
4694 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4695 should cause the alignment to be checked once it is known. This is
4696 because BX PC only works if the instruction is word aligned. */
4705 thumb_mov_compare (str, THUMB_COMPARE);
4715 skip_whitespace (str);
4717 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4721 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4725 if (skip_past_comma (&str) == FAIL
4726 || (range = reg_list (&str)) == FAIL)
4729 inst.error = BAD_ARGS;
4733 if (inst.reloc.type != BFD_RELOC_NONE)
4735 /* This really doesn't seem worth it. */
4736 inst.reloc.type = BFD_RELOC_NONE;
4737 inst.error = _("Expression too complex");
4743 inst.error = _("only lo-regs valid in load/store multiple");
4747 inst.instruction |= (Rb << 8) | range;
4755 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4762 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
4769 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
4778 skip_whitespace (str);
4780 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4781 || skip_past_comma (&str) == FAIL
4783 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4784 || skip_past_comma (&str) == FAIL
4785 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4789 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4793 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4801 thumb_shift (str, THUMB_LSL);
4808 thumb_shift (str, THUMB_LSR);
4815 thumb_mov_compare (str, THUMB_MOVE);
4824 skip_whitespace (str);
4826 if ((range = reg_list (&str)) == FAIL)
4829 inst.error = BAD_ARGS;
4833 if (inst.reloc.type != BFD_RELOC_NONE)
4835 /* This really doesn't seem worth it. */
4836 inst.reloc.type = BFD_RELOC_NONE;
4837 inst.error = _("Expression too complex");
4843 if ((inst.instruction == T_OPCODE_PUSH
4844 && (range & ~0xff) == 1 << REG_LR)
4845 || (inst.instruction == T_OPCODE_POP
4846 && (range & ~0xff) == 1 << REG_PC))
4848 inst.instruction |= THUMB_PP_PC_LR;
4853 inst.error = _("invalid register list to push/pop instruction");
4858 inst.instruction |= range;
4866 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
4873 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
4880 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
4887 thumb_add_sub (str, 1);
4894 skip_whitespace (str);
4896 if (my_get_expression (&inst.reloc.exp, &str))
4899 inst.reloc.type = BFD_RELOC_ARM_SWI;
4910 /* This is a pseudo-op of the form "adr rd, label" to be converted
4911 into a relative address of the form "add rd, pc, #label-.-4". */
4912 skip_whitespace (str);
4914 /* Store Rd in temporary location inside instruction. */
4915 if ((reg = reg_required_here (&str, 4)) == FAIL
4916 || (reg > 7) /* For Thumb reg must be r0..r7. */
4917 || skip_past_comma (&str) == FAIL
4918 || my_get_expression (&inst.reloc.exp, &str))
4921 inst.error = BAD_ARGS;
4925 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4926 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
4927 inst.reloc.pc_rel = 1;
4928 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
4937 int len = strlen (reg_table[entry].name) + 2;
4938 char * buf = (char *) xmalloc (len);
4939 char * buf2 = (char *) xmalloc (len);
4942 #ifdef REGISTER_PREFIX
4943 buf[i++] = REGISTER_PREFIX;
4946 strcpy (buf + i, reg_table[entry].name);
4948 for (i = 0; buf[i]; i++)
4949 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
4953 hash_insert (arm_reg_hsh, buf, (PTR) ®_table[entry]);
4954 hash_insert (arm_reg_hsh, buf2, (PTR) ®_table[entry]);
4958 insert_reg_alias (str, regnum)
4962 struct reg_entry *new =
4963 (struct reg_entry *)xmalloc (sizeof (struct reg_entry));
4964 char *name = xmalloc (strlen (str) + 1);
4968 new->number = regnum;
4970 hash_insert (arm_reg_hsh, name, (PTR) new);
4974 set_constant_flonums ()
4978 for (i = 0; i < NUM_FLOAT_VALS; i++)
4979 if (atof_ieee ((char *)fp_const[i], 'x', fp_values[i]) == NULL)
4989 if ( (arm_ops_hsh = hash_new ()) == NULL
4990 || (arm_tops_hsh = hash_new ()) == NULL
4991 || (arm_cond_hsh = hash_new ()) == NULL
4992 || (arm_shift_hsh = hash_new ()) == NULL
4993 || (arm_reg_hsh = hash_new ()) == NULL
4994 || (arm_psr_hsh = hash_new ()) == NULL)
4995 as_fatal (_("Virtual memory exhausted"));
4997 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
4998 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
4999 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
5000 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
5001 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5002 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
5003 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
5004 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
5005 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5006 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
5008 for (i = 0; reg_table[i].name; i++)
5011 set_constant_flonums ();
5013 #if defined OBJ_COFF || defined OBJ_ELF
5015 unsigned int flags = 0;
5017 /* Set the flags in the private structure. */
5018 if (uses_apcs_26) flags |= F_APCS26;
5019 if (support_interwork) flags |= F_INTERWORK;
5020 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5021 if (pic_code) flags |= F_PIC;
5022 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
5024 bfd_set_private_flags (stdoutput, flags);
5028 /* Record the CPU type as well. */
5029 switch (cpu_variant & ARM_CPU_MASK)
5032 mach = bfd_mach_arm_2;
5035 case ARM_3: /* Also ARM_250. */
5036 mach = bfd_mach_arm_2a;
5040 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
5041 mach = bfd_mach_arm_4;
5044 case ARM_7: /* Also ARM_6. */
5045 mach = bfd_mach_arm_3;
5049 /* Catch special cases. */
5050 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5052 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5053 mach = bfd_mach_arm_5T;
5054 else if (cpu_variant & ARM_EXT_V5)
5055 mach = bfd_mach_arm_5;
5056 else if (cpu_variant & ARM_THUMB)
5057 mach = bfd_mach_arm_4T;
5058 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5059 mach = bfd_mach_arm_4;
5060 else if (cpu_variant & ARM_LONGMUL)
5061 mach = bfd_mach_arm_3M;
5064 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5067 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5068 for use in the a.out file, and stores them in the array pointed to by buf.
5069 This knows about the endian-ness of the target machine and does
5070 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5071 2 (short) and 4 (long) Floating numbers are put out as a series of
5072 LITTLENUMS (shorts, here at least). */
5074 md_number_to_chars (buf, val, n)
5079 if (target_big_endian)
5080 number_to_chars_bigendian (buf, val, n);
5082 number_to_chars_littleendian (buf, val, n);
5086 md_chars_to_number (buf, n)
5091 unsigned char * where = (unsigned char *) buf;
5093 if (target_big_endian)
5098 result |= (*where++ & 255);
5106 result |= (where[n] & 255);
5113 /* Turn a string in input_line_pointer into a floating point constant
5114 of type TYPE, and store the appropriate bytes in *litP. The number
5115 of LITTLENUMS emitted is stored in *sizeP . An error message is
5116 returned, or NULL on OK.
5118 Note that fp constants aren't represent in the normal way on the ARM.
5119 In big endian mode, things are as expected. However, in little endian
5120 mode fp constants are big-endian word-wise, and little-endian byte-wise
5121 within the words. For example, (double) 1.1 in big endian mode is
5122 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5123 the byte sequence 99 99 f1 3f 9a 99 99 99.
5125 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5128 md_atof (type, litP, sizeP)
5134 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5166 return _("Bad call to MD_ATOF()");
5169 t = atof_ieee (input_line_pointer, type, words);
5171 input_line_pointer = t;
5174 if (target_big_endian)
5176 for (i = 0; i < prec; i++)
5178 md_number_to_chars (litP, (valueT) words[i], 2);
5184 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5185 8 byte float the order is 1 0 3 2. */
5186 for (i = 0; i < prec; i += 2)
5188 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5189 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5197 /* The knowledge of the PC's pipeline offset is built into the insns themselves. */
5199 md_pcrel_from (fixP)
5203 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5204 && fixP->fx_subsy == NULL)
5207 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5209 /* PC relative addressing on the Thumb is slightly odd
5210 as the bottom two bits of the PC are forced to zero
5211 for the calculation. */
5212 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5216 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5217 so we un-adjust here to compensate for the accomodation. */
5218 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
5220 return fixP->fx_where + fixP->fx_frag->fr_address;
5224 /* Round up a section size to the appropriate boundary. */
5226 md_section_align (segment, size)
5227 segT segment ATTRIBUTE_UNUSED;
5233 /* Round all sects to multiple of 4 */
5234 return (size + 3) & ~3;
5238 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. Otherwise
5239 we have no need to default values of symbols. */
5243 md_undefined_symbol (name)
5247 if (name[0] == '_' && name[1] == 'G'
5248 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5252 if (symbol_find (name))
5253 as_bad ("GOT already in the symbol table");
5255 GOT_symbol = symbol_new (name, undefined_section,
5256 (valueT)0, & zero_address_frag);
5266 /* arm_reg_parse () := if it looks like a register, return its token and
5267 advance the pointer. */
5271 register char ** ccp;
5273 char * start = * ccp;
5276 struct reg_entry * reg;
5278 #ifdef REGISTER_PREFIX
5279 if (*start != REGISTER_PREFIX)
5284 #ifdef OPTIONAL_REGISTER_PREFIX
5285 if (*p == OPTIONAL_REGISTER_PREFIX)
5289 if (!isalpha (*p) || !is_name_beginner (*p))
5293 while (isalpha (c) || isdigit (c) || c == '_')
5297 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5311 register char ** ccp;
5313 char * start = * ccp;
5316 CONST struct asm_psr * psr;
5320 while (isalpha (c) || c == '_')
5324 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
5337 md_apply_fix3 (fixP, val, seg)
5342 offsetT value = * val;
5344 unsigned int newimm;
5347 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5348 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5350 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5352 /* Note whether this will delete the relocation. */
5353 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5354 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5357 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5361 /* If this symbol is in a different section then we need to leave it for
5362 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5363 so we have to undo it's effects here. */
5366 if (fixP->fx_addsy != NULL
5367 && S_IS_DEFINED (fixP->fx_addsy)
5368 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5371 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
5375 value += md_pcrel_from (fixP);
5379 fixP->fx_addnumber = value; /* Remember value for emit_reloc. */
5381 switch (fixP->fx_r_type)
5383 case BFD_RELOC_ARM_IMMEDIATE:
5384 newimm = validate_immediate (value);
5385 temp = md_chars_to_number (buf, INSN_SIZE);
5387 /* If the instruction will fail, see if we can fix things up by
5388 changing the opcode. */
5389 if (newimm == (unsigned int) FAIL
5390 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5392 as_bad_where (fixP->fx_file, fixP->fx_line,
5393 _("invalid constant (%lx) after fixup"),
5394 (unsigned long) value);
5398 newimm |= (temp & 0xfffff000);
5399 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5402 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5404 unsigned int highpart = 0;
5405 unsigned int newinsn = 0xe1a00000; /* nop */
5406 newimm = validate_immediate (value);
5407 temp = md_chars_to_number (buf, INSN_SIZE);
5409 /* If the instruction will fail, see if we can fix things up by
5410 changing the opcode. */
5411 if (newimm == (unsigned int) FAIL
5412 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5414 /* No ? OK - try using two ADD instructions to generate the value. */
5415 newimm = validate_immediate_twopart (value, & highpart);
5417 /* Yes - then make sure that the second instruction is also an add. */
5418 if (newimm != (unsigned int) FAIL)
5420 /* Still No ? Try using a negated value. */
5421 else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
5422 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5423 /* Otherwise - give up. */
5426 as_bad_where (fixP->fx_file, fixP->fx_line,
5427 _("Unable to compute ADRL instructions for PC offset of 0x%x"), value);
5431 /* Replace the first operand in the 2nd instruction (which is the PC)
5432 with the destination register. We have already added in the PC in the
5433 first instruction and we do not want to do it again. */
5434 newinsn &= ~ 0xf0000;
5435 newinsn |= ((newinsn & 0x0f000) << 4);
5438 newimm |= (temp & 0xfffff000);
5439 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5441 highpart |= (newinsn & 0xfffff000);
5442 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5446 case BFD_RELOC_ARM_OFFSET_IMM:
5452 if (validate_offset_imm (value, 0) == FAIL)
5454 as_bad_where (fixP->fx_file, fixP->fx_line,
5455 _("bad immediate value for offset (%ld)"), (long) value);
5459 newval = md_chars_to_number (buf, INSN_SIZE);
5460 newval &= 0xff7ff000;
5461 newval |= value | (sign ? INDEX_UP : 0);
5462 md_number_to_chars (buf, newval, INSN_SIZE);
5465 case BFD_RELOC_ARM_OFFSET_IMM8:
5466 case BFD_RELOC_ARM_HWLITERAL:
5472 if (validate_offset_imm (value, 1) == FAIL)
5474 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5475 as_bad_where (fixP->fx_file, fixP->fx_line,
5476 _("invalid literal constant: pool needs to be closer"));
5478 as_bad (_("bad immediate value for half-word offset (%ld)"),
5483 newval = md_chars_to_number (buf, INSN_SIZE);
5484 newval &= 0xff7ff0f0;
5485 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5486 md_number_to_chars (buf, newval, INSN_SIZE);
5489 case BFD_RELOC_ARM_LITERAL:
5495 if (validate_offset_imm (value, 0) == FAIL)
5497 as_bad_where (fixP->fx_file, fixP->fx_line,
5498 _("invalid literal constant: pool needs to be closer"));
5502 newval = md_chars_to_number (buf, INSN_SIZE);
5503 newval &= 0xff7ff000;
5504 newval |= value | (sign ? INDEX_UP : 0);
5505 md_number_to_chars (buf, newval, INSN_SIZE);
5508 case BFD_RELOC_ARM_SHIFT_IMM:
5509 newval = md_chars_to_number (buf, INSN_SIZE);
5510 if (((unsigned long) value) > 32
5512 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5514 as_bad_where (fixP->fx_file, fixP->fx_line,
5515 _("shift expression is too large"));
5520 newval &= ~0x60; /* Shifts of zero must be done as lsl */
5521 else if (value == 32)
5523 newval &= 0xfffff07f;
5524 newval |= (value & 0x1f) << 7;
5525 md_number_to_chars (buf, newval , INSN_SIZE);
5528 case BFD_RELOC_ARM_SWI:
5529 if (arm_data->thumb_mode)
5531 if (((unsigned long) value) > 0xff)
5532 as_bad_where (fixP->fx_file, fixP->fx_line,
5533 _("Invalid swi expression"));
5534 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5536 md_number_to_chars (buf, newval, THUMB_SIZE);
5540 if (((unsigned long) value) > 0x00ffffff)
5541 as_bad_where (fixP->fx_file, fixP->fx_line,
5542 _("Invalid swi expression"));
5543 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5545 md_number_to_chars (buf, newval , INSN_SIZE);
5549 case BFD_RELOC_ARM_MULTI:
5550 if (((unsigned long) value) > 0xffff)
5551 as_bad_where (fixP->fx_file, fixP->fx_line,
5552 _("Invalid expression in load/store multiple"));
5553 newval = value | md_chars_to_number (buf, INSN_SIZE);
5554 md_number_to_chars (buf, newval, INSN_SIZE);
5557 case BFD_RELOC_ARM_PCREL_BRANCH:
5558 newval = md_chars_to_number (buf, INSN_SIZE);
5560 /* Sign-extend a 24-bit number. */
5561 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
5565 value = fixP->fx_offset;
5568 /* We are going to store value (shifted right by two) in the
5569 instruction, in a 24 bit, signed field. Thus we need to check
5570 that none of the top 8 bits of the shifted value (top 7 bits of
5571 the unshifted, unsigned value) are set, or that they are all set. */
5572 if ((value & 0xfe000000UL) != 0
5573 && ((value & 0xfe000000UL) != 0xfe000000UL))
5576 /* Normally we would be stuck at this point, since we cannot store
5577 the absolute address that is the destination of the branch in the
5578 24 bits of the branch instruction. If however, we happen to know
5579 that the destination of the branch is in the same section as the
5580 branch instruciton itself, then we can compute the relocation for
5581 ourselves and not have to bother the linker with it.
5583 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5584 because I have not worked out how to do this for OBJ_COFF or
5587 && fixP->fx_addsy != NULL
5588 && S_IS_DEFINED (fixP->fx_addsy)
5589 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
5591 /* Get pc relative value to go into the branch. */
5594 /* Permit a backward branch provided that enough bits are set.
5595 Allow a forwards branch, provided that enough bits are clear. */
5596 if ((value & 0xfe000000UL) == 0xfe000000UL
5597 || (value & 0xfe000000UL) == 0)
5601 if (! fixP->fx_done)
5603 as_bad_where (fixP->fx_file, fixP->fx_line,
5604 _("gas can't handle same-section branch dest >= 0x04000000"));
5608 value += SEXT24 (newval);
5610 if ((value & 0xff000000UL) != 0
5611 && (fixP->fx_done == 0
5612 || ((value & 0xff000000UL) != 0xff000000UL)))
5613 as_bad_where (fixP->fx_file, fixP->fx_line,
5614 _("out of range branch"));
5616 newval = (value & 0x00ffffff) | (newval & 0xff000000);
5617 md_number_to_chars (buf, newval, INSN_SIZE);
5621 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
5622 newval = md_chars_to_number (buf, THUMB_SIZE);
5624 addressT diff = (newval & 0xff) << 1;
5629 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5630 as_bad_where (fixP->fx_file, fixP->fx_line,
5631 _("Branch out of range"));
5632 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5634 md_number_to_chars (buf, newval, THUMB_SIZE);
5637 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* unconditional branch */
5638 newval = md_chars_to_number (buf, THUMB_SIZE);
5640 addressT diff = (newval & 0x7ff) << 1;
5645 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5646 as_bad_where (fixP->fx_file, fixP->fx_line,
5647 _("Branch out of range"));
5648 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5650 md_number_to_chars (buf, newval, THUMB_SIZE);
5653 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5658 newval = md_chars_to_number (buf, THUMB_SIZE);
5659 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5660 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5661 if (diff & 0x400000)
5664 value = fixP->fx_offset;
5667 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5668 as_bad_where (fixP->fx_file, fixP->fx_line,
5669 _("Branch with link out of range"));
5671 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5672 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5673 md_number_to_chars (buf, newval, THUMB_SIZE);
5674 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5679 if (fixP->fx_done || fixP->fx_pcrel)
5680 md_number_to_chars (buf, value, 1);
5682 else if (!target_oabi)
5684 value = fixP->fx_offset;
5685 md_number_to_chars (buf, value, 1);
5691 if (fixP->fx_done || fixP->fx_pcrel)
5692 md_number_to_chars (buf, value, 2);
5694 else if (!target_oabi)
5696 value = fixP->fx_offset;
5697 md_number_to_chars (buf, value, 2);
5703 case BFD_RELOC_ARM_GOT32:
5704 case BFD_RELOC_ARM_GOTOFF:
5705 md_number_to_chars (buf, 0, 4);
5711 if (fixP->fx_done || fixP->fx_pcrel)
5712 md_number_to_chars (buf, value, 4);
5714 else if (!target_oabi)
5716 value = fixP->fx_offset;
5717 md_number_to_chars (buf, value, 4);
5723 case BFD_RELOC_ARM_PLT32:
5724 /* It appears the instruction is fully prepared at this point. */
5728 case BFD_RELOC_ARM_GOTPC:
5729 md_number_to_chars (buf, value, 4);
5732 case BFD_RELOC_ARM_CP_OFF_IMM:
5734 if (value < -1023 || value > 1023 || (value & 3))
5735 as_bad_where (fixP->fx_file, fixP->fx_line,
5736 _("Illegal value for co-processor offset"));
5739 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5740 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5741 md_number_to_chars (buf, newval , INSN_SIZE);
5744 case BFD_RELOC_ARM_THUMB_OFFSET:
5745 newval = md_chars_to_number (buf, THUMB_SIZE);
5746 /* Exactly what ranges, and where the offset is inserted depends on
5747 the type of instruction, we can establish this from the top 4 bits */
5748 switch (newval >> 12)
5750 case 4: /* PC load */
5751 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5752 forced to zero for these loads, so we will need to round
5753 up the offset if the instruction address is not word
5754 aligned (since the final address produced must be, and
5755 we can only describe word-aligned immediate offsets). */
5757 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
5758 as_bad_where (fixP->fx_file, fixP->fx_line,
5759 _("Invalid offset, target not word aligned (0x%08X)"),
5760 (unsigned int)(fixP->fx_frag->fr_address + fixP->fx_where + value));
5762 if ((value + 2) & ~0x3fe)
5763 as_bad_where (fixP->fx_file, fixP->fx_line,
5764 _("Invalid offset, value too big (0x%08X)"), value);
5766 /* Round up, since pc will be rounded down. */
5767 newval |= (value + 2) >> 2;
5770 case 9: /* SP load/store */
5772 as_bad_where (fixP->fx_file, fixP->fx_line,
5773 _("Invalid offset, value too big (0x%08X)"), value);
5774 newval |= value >> 2;
5777 case 6: /* Word load/store */
5779 as_bad_where (fixP->fx_file, fixP->fx_line,
5780 _("Invalid offset, value too big (0x%08X)"), value);
5781 newval |= value << 4; /* 6 - 2 */
5784 case 7: /* Byte load/store */
5786 as_bad_where (fixP->fx_file, fixP->fx_line,
5787 _("Invalid offset, value too big (0x%08X)"), value);
5788 newval |= value << 6;
5791 case 8: /* Halfword load/store */
5793 as_bad_where (fixP->fx_file, fixP->fx_line,
5794 _("Invalid offset, value too big (0x%08X)"), value);
5795 newval |= value << 5; /* 6 - 1 */
5799 as_bad_where (fixP->fx_file, fixP->fx_line,
5800 "Unable to process relocation for thumb opcode: %lx",
5801 (unsigned long) newval);
5804 md_number_to_chars (buf, newval, THUMB_SIZE);
5807 case BFD_RELOC_ARM_THUMB_ADD:
5808 /* This is a complicated relocation, since we use it for all of
5809 the following immediate relocations:
5812 9bit ADD/SUB SP word-aligned
5813 10bit ADD PC/SP word-aligned
5815 The type of instruction being processed is encoded in the
5821 newval = md_chars_to_number (buf, THUMB_SIZE);
5823 int rd = (newval >> 4) & 0xf;
5824 int rs = newval & 0xf;
5825 int subtract = newval & 0x8000;
5830 as_bad_where (fixP->fx_file, fixP->fx_line,
5831 _("Invalid immediate for stack address calculation"));
5832 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5833 newval |= value >> 2;
5835 else if (rs == REG_PC || rs == REG_SP)
5839 as_bad_where (fixP->fx_file, fixP->fx_line,
5840 _("Invalid immediate for address calculation (value = 0x%08lX)"),
5841 (unsigned long) value);
5842 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
5844 newval |= value >> 2;
5849 as_bad_where (fixP->fx_file, fixP->fx_line,
5850 _("Invalid 8bit immediate"));
5851 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5852 newval |= (rd << 8) | value;
5857 as_bad_where (fixP->fx_file, fixP->fx_line,
5858 _("Invalid 3bit immediate"));
5859 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5860 newval |= rd | (rs << 3) | (value << 6);
5863 md_number_to_chars (buf, newval , THUMB_SIZE);
5866 case BFD_RELOC_ARM_THUMB_IMM:
5867 newval = md_chars_to_number (buf, THUMB_SIZE);
5868 switch (newval >> 11)
5870 case 0x04: /* 8bit immediate MOV */
5871 case 0x05: /* 8bit immediate CMP */
5872 if (value < 0 || value > 255)
5873 as_bad_where (fixP->fx_file, fixP->fx_line,
5874 _("Invalid immediate: %ld is too large"),
5882 md_number_to_chars (buf, newval , THUMB_SIZE);
5885 case BFD_RELOC_ARM_THUMB_SHIFT:
5886 /* 5bit shift value (0..31) */
5887 if (value < 0 || value > 31)
5888 as_bad_where (fixP->fx_file, fixP->fx_line,
5889 _("Illegal Thumb shift value: %ld"), (long) value);
5890 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
5891 newval |= value << 6;
5892 md_number_to_chars (buf, newval , THUMB_SIZE);
5895 case BFD_RELOC_VTABLE_INHERIT:
5896 case BFD_RELOC_VTABLE_ENTRY:
5900 case BFD_RELOC_NONE:
5902 as_bad_where (fixP->fx_file, fixP->fx_line,
5903 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
5909 /* Translate internal representation of relocation info to BFD target
5912 tc_gen_reloc (section, fixp)
5913 asection * section ATTRIBUTE_UNUSED;
5917 bfd_reloc_code_real_type code;
5919 reloc = (arelent *) xmalloc (sizeof (arelent));
5921 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5922 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5923 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5925 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5927 if (fixp->fx_pcrel == 0)
5928 reloc->addend = fixp->fx_offset;
5930 reloc->addend = fixp->fx_offset = reloc->address;
5932 reloc->addend = fixp->fx_offset;
5935 switch (fixp->fx_r_type)
5940 code = BFD_RELOC_8_PCREL;
5947 code = BFD_RELOC_16_PCREL;
5954 code = BFD_RELOC_32_PCREL;
5958 case BFD_RELOC_ARM_PCREL_BRANCH:
5960 case BFD_RELOC_THUMB_PCREL_BRANCH9:
5961 case BFD_RELOC_THUMB_PCREL_BRANCH12:
5962 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5963 case BFD_RELOC_VTABLE_ENTRY:
5964 case BFD_RELOC_VTABLE_INHERIT:
5965 code = fixp->fx_r_type;
5968 case BFD_RELOC_ARM_LITERAL:
5969 case BFD_RELOC_ARM_HWLITERAL:
5970 /* If this is called then the a literal has been referenced across
5971 a section boundary - possibly due to an implicit dump */
5972 as_bad_where (fixp->fx_file, fixp->fx_line,
5973 _("Literal referenced across section boundary (Implicit dump?)"));
5977 case BFD_RELOC_ARM_GOT32:
5978 case BFD_RELOC_ARM_GOTOFF:
5979 case BFD_RELOC_ARM_PLT32:
5980 code = fixp->fx_r_type;
5984 case BFD_RELOC_ARM_IMMEDIATE:
5985 as_bad_where (fixp->fx_file, fixp->fx_line,
5986 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
5990 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5991 as_bad_where (fixp->fx_file, fixp->fx_line,
5992 _("ADRL used for a symbol not defined in the same file"),
5996 case BFD_RELOC_ARM_OFFSET_IMM:
5997 as_bad_where (fixp->fx_file, fixp->fx_line,
5998 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6005 switch (fixp->fx_r_type)
6007 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
6008 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
6009 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
6010 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
6011 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
6012 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
6013 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
6014 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
6015 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
6016 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
6017 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
6018 default: type = _("<unknown>"); break;
6020 as_bad_where (fixp->fx_file, fixp->fx_line,
6021 _("Can not represent %s relocation in this object file format (%d)"),
6022 type, fixp->fx_pcrel);
6028 if (code == BFD_RELOC_32_PCREL
6030 && fixp->fx_addsy == GOT_symbol)
6032 code = BFD_RELOC_ARM_GOTPC;
6033 reloc->addend = fixp->fx_offset = reloc->address;
6037 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6039 if (reloc->howto == NULL)
6041 as_bad_where (fixp->fx_file, fixp->fx_line,
6042 _("Can not represent %s relocation in this object file format"),
6043 bfd_get_reloc_code_name (code));
6047 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6048 vtable entry to be used in the relocation's section offset. */
6049 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6050 reloc->address = fixp->fx_offset;
6056 md_estimate_size_before_relax (fragP, segtype)
6057 fragS * fragP ATTRIBUTE_UNUSED;
6058 segT segtype ATTRIBUTE_UNUSED;
6060 as_fatal (_("md_estimate_size_before_relax\n"));
6065 output_inst PARAMS ((void))
6071 as_bad (inst.error);
6075 to = frag_more (inst.size);
6077 if (thumb_mode && (inst.size > THUMB_SIZE))
6079 assert (inst.size == (2 * THUMB_SIZE));
6080 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6081 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6083 else if (inst.size > INSN_SIZE)
6085 assert (inst.size == (2 * INSN_SIZE));
6086 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6087 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6090 md_number_to_chars (to, inst.instruction, inst.size);
6092 if (inst.reloc.type != BFD_RELOC_NONE)
6093 fix_new_arm (frag_now, to - frag_now->fr_literal,
6094 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6109 /* Align the instruction.
6110 This may not be the right thing to do but ... */
6111 /* arm_align (2, 0); */
6112 listing_prev_line (); /* Defined in listing.h */
6114 /* Align the previous label if needed. */
6115 if (last_label_seen != NULL)
6117 symbol_set_frag (last_label_seen, frag_now);
6118 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6119 S_SET_SEGMENT (last_label_seen, now_seg);
6122 memset (&inst, '\0', sizeof (inst));
6123 inst.reloc.type = BFD_RELOC_NONE;
6125 skip_whitespace (str);
6127 /* Scan up to the end of the op-code, which must end in white space or
6129 for (start = p = str; *p != '\0'; p++)
6135 as_bad (_("No operator -- statement `%s'\n"), str);
6141 CONST struct thumb_opcode * opcode;
6145 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6150 /* Check that this instruction is supported for this CPU. */
6151 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
6153 as_bad (_("selected processor does not support this opcode"));
6157 inst.instruction = opcode->value;
6158 inst.size = opcode->size;
6159 (*opcode->parms)(p);
6166 CONST struct asm_opcode * opcode;
6167 unsigned long cond_code;
6169 inst.size = INSN_SIZE;
6170 /* p now points to the end of the opcode, probably white space, but we
6171 have to break the opcode up in case it contains condionals and flags;
6172 keep trying with progressively smaller basic instructions until one
6173 matches, or we run out of opcode. */
6174 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6175 for (; q != str; q--)
6179 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6182 if (opcode && opcode->template)
6184 unsigned long flag_bits = 0;
6187 /* Check that this instruction is supported for this CPU. */
6188 if ((opcode->variants & cpu_variant) == 0)
6191 inst.instruction = opcode->value;
6192 if (q == p) /* Just a simple opcode. */
6194 if (opcode->comp_suffix)
6196 if (*opcode->comp_suffix != '\0')
6197 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6198 str, opcode->comp_suffix);
6200 /* Not a conditional instruction. */
6201 (*opcode->parms)(q, 0);
6205 /* A conditional instruction with default condition. */
6206 inst.instruction |= COND_ALWAYS;
6207 (*opcode->parms)(q, 0);
6213 /* Not just a simple opcode. Check if extra is a conditional. */
6217 CONST struct asm_cond *cond;
6221 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6225 if (cond->value == 0xf0000000)
6227 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6229 cond_code = cond->value;
6233 cond_code = COND_ALWAYS;
6236 cond_code = COND_ALWAYS;
6238 /* Apply the conditional, or complain it's not allowed. */
6239 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
6241 /* Instruction isn't conditional */
6242 if (cond_code != COND_ALWAYS)
6244 as_bad (_("Opcode `%s' is unconditional\n"), str);
6249 /* Instruction is conditional: set the condition into it. */
6250 inst.instruction |= cond_code;
6253 /* If there is a compulsory suffix, it should come here, before
6254 any optional flags. */
6255 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
6257 CONST char *s = opcode->comp_suffix;
6269 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
6270 opcode->comp_suffix);
6277 /* The remainder, if any should now be flags for the instruction;
6278 Scan these checking each one found with the opcode. */
6282 CONST struct asm_flg *flag = opcode->flags;
6291 for (flagno = 0; flag[flagno].template; flagno++)
6293 if (streq (r, flag[flagno].template))
6295 flag_bits |= flag[flagno].set_bits;
6301 if (! flag[flagno].template)
6308 (*opcode->parms) (p, flag_bits);
6318 /* It wasn't an instruction, but it might be a register alias of the form
6321 skip_whitespace (q);
6326 if (*q && !strncmp (q, ".req ", 4))
6329 char * copy_of_str = str;
6333 skip_whitespace (q);
6335 for (r = q; *r != '\0'; r++)
6345 regnum = arm_reg_parse (& q);
6348 reg = arm_reg_parse (& str);
6353 insert_reg_alias (str, regnum);
6355 as_warn (_("register '%s' does not exist\n"), q);
6357 else if (regnum != FAIL)
6360 as_warn (_("ignoring redefinition of register alias '%s'"),
6363 /* Do not warn about redefinitions to the same alias. */
6366 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6370 as_warn (_("ignoring incomplete .req pseuso op"));
6377 as_bad (_("bad instruction `%s'"), start);
6382 * Invocation line includes a switch not recognized by the base assembler.
6383 * See if it's a processor-specific option. These are:
6384 * Cpu variants, the arm part is optional:
6385 * -m[arm]1 Currently not supported.
6386 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6387 * -m[arm]3 Arm 3 processor
6388 * -m[arm]6[xx], Arm 6 processors
6389 * -m[arm]7[xx][t][[d]m] Arm 7 processors
6390 * -m[arm]8[10] Arm 8 processors
6391 * -m[arm]9[20][tdmi] Arm 9 processors
6392 * -mstrongarm[110[0]] StrongARM processors
6393 * -m[arm]v[2345] Arm architectures
6394 * -mall All (except the ARM1)
6396 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6397 * -mfpe-old (No float load/store multiples)
6398 * -mno-fpu Disable all floating point instructions
6399 * Run-time endian selection:
6400 * -EB big endian cpu
6401 * -EL little endian cpu
6402 * ARM Procedure Calling Standard:
6403 * -mapcs-32 32 bit APCS
6404 * -mapcs-26 26 bit APCS
6405 * -mapcs-float Pass floats in float regs
6406 * -mapcs-reentrant Position independent code
6407 * -mthumb-interwork Code supports Arm/Thumb interworking
6408 * -moabi Old ELF ABI
6411 CONST char * md_shortopts = "m:k";
6412 struct option md_longopts[] =
6414 #ifdef ARM_BI_ENDIAN
6415 #define OPTION_EB (OPTION_MD_BASE + 0)
6416 {"EB", no_argument, NULL, OPTION_EB},
6417 #define OPTION_EL (OPTION_MD_BASE + 1)
6418 {"EL", no_argument, NULL, OPTION_EL},
6420 #define OPTION_OABI (OPTION_MD_BASE +2)
6421 {"oabi", no_argument, NULL, OPTION_OABI},
6424 {NULL, no_argument, NULL, 0}
6426 size_t md_longopts_size = sizeof (md_longopts);
6429 md_parse_option (c, arg)
6437 #ifdef ARM_BI_ENDIAN
6439 target_big_endian = 1;
6442 target_big_endian = 0;
6450 if (streq (str, "fpa10"))
6451 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6452 else if (streq (str, "fpa11"))
6453 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6454 else if (streq (str, "fpe-old"))
6455 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6461 if (streq (str, "no-fpu"))
6462 cpu_variant &= ~FPU_ALL;
6467 if (streq (str, "oabi"))
6473 /* Limit assembler to generating only Thumb instructions: */
6474 if (streq (str, "thumb"))
6476 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6477 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6480 else if (streq (str, "thumb-interwork"))
6482 if ((cpu_variant & ARM_THUMB) == 0)
6483 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
6484 #if defined OBJ_COFF || defined OBJ_ELF
6485 support_interwork = true;
6493 if (streq (str, "all"))
6495 cpu_variant = ARM_ALL | FPU_ALL;
6498 #if defined OBJ_COFF || defined OBJ_ELF
6499 if (! strncmp (str, "apcs-", 5))
6501 /* GCC passes on all command line options starting "-mapcs-..."
6502 to us, so we must parse them here. */
6506 if (streq (str, "32"))
6508 uses_apcs_26 = false;
6511 else if (streq (str, "26"))
6513 uses_apcs_26 = true;
6516 else if (streq (str, "frame"))
6518 /* Stack frames are being generated - does not affect
6522 else if (streq (str, "stack-check"))
6524 /* Stack checking is being performed - does not affect
6525 linkage, but does require that the functions
6526 __rt_stkovf_split_small and __rt_stkovf_split_big be
6527 present in the final link. */
6531 else if (streq (str, "float"))
6533 /* Floating point arguments are being passed in the floating
6534 point registers. This does affect linking, since this
6535 version of the APCS is incompatible with the version that
6536 passes floating points in the integer registers. */
6538 uses_apcs_float = true;
6541 else if (streq (str, "reentrant"))
6543 /* Reentrant code has been generated. This does affect
6544 linking, since there is no point in linking reentrant/
6545 position independent code with absolute position code. */
6550 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6554 /* Strip off optional "arm" */
6555 if (! strncmp (str, "arm", 3))
6561 if (streq (str, "1"))
6562 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6568 if (streq (str, "2"))
6569 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6570 else if (streq (str, "250"))
6571 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6577 if (streq (str, "3"))
6578 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6584 switch (strtol (str, NULL, 10))
6591 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6599 switch (strtol (str, & str, 10)) /* Eat the processor name */
6612 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6618 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6622 cpu_variant |= ARM_LONGMUL;
6625 case 'f': /* fe => fp enabled cpu. */
6631 case 'c': /* Left over from 710c processor name. */
6632 case 'd': /* Debug */
6633 case 'i': /* Embedded ICE */
6634 /* Included for completeness in ARM processor naming. */
6644 if (streq (str, "8") || streq (str, "810"))
6645 cpu_variant = (cpu_variant & ~ARM_ANY)
6646 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6652 if (streq (str, "9"))
6653 cpu_variant = (cpu_variant & ~ARM_ANY)
6654 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6655 else if (streq (str, "920"))
6656 cpu_variant = (cpu_variant & ~ARM_ANY)
6657 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6658 else if (streq (str, "920t"))
6659 cpu_variant = (cpu_variant & ~ARM_ANY)
6660 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6661 else if (streq (str, "9tdmi"))
6662 cpu_variant = (cpu_variant & ~ARM_ANY)
6663 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6670 if (streq (str, "strongarm")
6671 || streq (str, "strongarm110")
6672 || streq (str, "strongarm1100"))
6673 cpu_variant = (cpu_variant & ~ARM_ANY)
6674 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6680 /* Select variant based on architecture rather than processor. */
6687 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6690 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6693 as_bad (_("Invalid architecture variant -m%s"), arg);
6699 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6703 case 'm': cpu_variant |= ARM_LONGMUL; break;
6706 as_bad (_("Invalid architecture variant -m%s"), arg);
6712 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
6716 case 't': cpu_variant |= ARM_THUMB; break;
6719 as_bad (_("Invalid architecture variant -m%s"), arg);
6725 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
6728 case 't': cpu_variant |= ARM_THUMB; break;
6729 case 'e': cpu_variant |= ARM_EXT_V5E; break;
6732 as_bad (_("Invalid architecture variant -m%s"), arg);
6738 as_bad (_("Invalid architecture variant -m%s"), arg);
6745 as_bad (_("Invalid processor variant -m%s"), arg);
6751 #if defined OBJ_ELF || defined OBJ_COFF
6769 ARM Specific Assembler Options:\n\
6770 -m[arm][<processor name>] select processor variant\n\
6771 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
6772 -mthumb only allow Thumb instructions\n\
6773 -mthumb-interwork mark the assembled code as supporting interworking\n\
6774 -mall allow any instruction\n\
6775 -mfpa10, -mfpa11 select floating point architecture\n\
6776 -mfpe-old don't allow floating-point multiple instructions\n\
6777 -mno-fpu don't allow any floating-point instructions.\n\
6778 -k generate PIC code.\n"));
6779 #if defined OBJ_COFF || defined OBJ_ELF
6781 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
6782 -mapcs-float floating point args are passed in FP regs\n\
6783 -mapcs-reentrant the code is position independent/reentrant\n"));
6787 -moabi support the old ELF ABI\n"));
6789 #ifdef ARM_BI_ENDIAN
6791 -EB assemble code for a big endian cpu\n\
6792 -EL assemble code for a little endian cpu\n"));
6796 /* We need to be able to fix up arbitrary expressions in some statements.
6797 This is so that we can handle symbols that are an arbitrary distance from
6798 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6799 which returns part of an address in a form which will be valid for
6800 a data instruction. We do this by pushing the expression into a symbol
6801 in the expr_section, and creating a fix for that. */
6804 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
6813 arm_fix_data * arm_data;
6821 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
6825 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
6830 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6831 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
6832 new_fix->tc_fix_data = (PTR) arm_data;
6833 arm_data->thumb_mode = thumb_mode;
6839 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6841 cons_fix_new_arm (frag, where, size, exp)
6847 bfd_reloc_code_real_type type;
6852 * @@ Should look at CPU word size.
6857 type = BFD_RELOC_16;
6861 type = BFD_RELOC_32;
6864 type = BFD_RELOC_64;
6868 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6871 /* A good place to do this, although this was probably not intended
6872 for this kind of use. We need to dump the literal pool before
6873 references are made to a null symbol pointer. */
6877 if (current_poolP == NULL)
6880 subseg_set (text_section, 0); /* Put it at the end of text section. */
6882 listing_prev_line ();
6886 arm_start_line_hook ()
6888 last_label_seen = NULL;
6892 arm_frob_label (sym)
6895 last_label_seen = sym;
6897 ARM_SET_THUMB (sym, thumb_mode);
6899 #if defined OBJ_COFF || defined OBJ_ELF
6900 ARM_SET_INTERWORK (sym, support_interwork);
6903 if (label_is_thumb_function_name)
6905 /* When the address of a Thumb function is taken the bottom
6906 bit of that address should be set. This will allow
6907 interworking between Arm and Thumb functions to work
6910 THUMB_SET_FUNC (sym, 1);
6912 label_is_thumb_function_name = false;
6916 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6920 arm_adjust_symtab ()
6925 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6927 if (ARM_IS_THUMB (sym))
6929 if (THUMB_IS_FUNC (sym))
6931 /* Mark the symbol as a Thumb function. */
6932 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
6933 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
6934 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
6936 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
6937 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
6939 as_bad (_("%s: unexpected function type: %d"),
6940 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
6942 else switch (S_GET_STORAGE_CLASS (sym))
6945 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
6948 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
6951 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
6953 default: /* do nothing */
6958 if (ARM_IS_INTERWORK (sym))
6959 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
6966 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6968 if (ARM_IS_THUMB (sym))
6970 elf_symbol_type * elf_sym;
6972 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
6973 bind = ELF_ST_BIND (elf_sym);
6975 /* If it's a .thumb_func, declare it as so,
6976 otherwise tag label as .code 16. */
6977 if (THUMB_IS_FUNC (sym))
6978 elf_sym->internal_elf_sym.st_info =
6979 ELF_ST_INFO (bind, STT_ARM_TFUNC);
6981 elf_sym->internal_elf_sym.st_info =
6982 ELF_ST_INFO (bind, STT_ARM_16BIT);
6991 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
6993 *input_line_pointer = '/';
6994 input_line_pointer += 5;
6995 *input_line_pointer = 0;
7003 arm_canonicalize_symbol_name (name)
7008 if (thumb_mode && (len = strlen (name)) > 5
7009 && streq (name + len - 5, "/data"))
7010 *(name + len - 5) = 0;
7016 arm_validate_fix (fixP)
7019 /* If the destination of the branch is a defined symbol which does not have
7020 the THUMB_FUNC attribute, then we must be calling a function which has
7021 the (interfacearm) attribute. We look for the Thumb entry point to that
7022 function and change the branch to refer to that function instead. */
7023 if ( fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
7024 && fixP->fx_addsy != NULL
7025 && S_IS_DEFINED (fixP->fx_addsy)
7026 && ! THUMB_IS_FUNC (fixP->fx_addsy))
7028 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
7036 /* Relocations against Thumb function names must be left unadjusted,
7037 so that the linker can use this information to correctly set the
7038 bottom bit of their addresses. The MIPS version of this function
7039 also prevents relocations that are mips-16 specific, but I do not
7040 know why it does this.
7043 There is one other problem that ought to be addressed here, but
7044 which currently is not: Taking the address of a label (rather
7045 than a function) and then later jumping to that address. Such
7046 addresses also ought to have their bottom bit set (assuming that
7047 they reside in Thumb code), but at the moment they will not. */
7050 arm_fix_adjustable (fixP)
7053 if (fixP->fx_addsy == NULL)
7056 /* Prevent all adjustments to global symbols. */
7057 if (S_IS_EXTERN (fixP->fx_addsy))
7060 if (S_IS_WEAK (fixP->fx_addsy))
7063 if (THUMB_IS_FUNC (fixP->fx_addsy)
7064 && fixP->fx_subsy == NULL)
7067 /* We need the symbol name for the VTABLE entries */
7068 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7069 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7076 elf32_arm_target_format ()
7078 if (target_big_endian)
7080 return "elf32-bigarm-oabi";
7082 return "elf32-bigarm";
7085 return "elf32-littlearm-oabi";
7087 return "elf32-littlearm";
7091 armelf_frob_symbol (symp, puntp)
7095 elf_frob_symbol (symp, puntp);
7099 arm_force_relocation (fixp)
7102 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7103 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7104 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
7105 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
7111 static bfd_reloc_code_real_type
7121 bfd_reloc_code_real_type reloc;
7125 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7126 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7127 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7128 /* ScottB: Jan 30, 1998 */
7129 /* Added support for parsing "var(PLT)" branch instructions */
7130 /* generated by GCC for PLT relocs */
7131 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7132 { NULL, 0, BFD_RELOC_UNUSED }
7136 for (i = 0, ip = input_line_pointer;
7137 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7139 id[i] = tolower (*ip);
7141 for (i = 0; reloc_map[i].str; i++)
7142 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7145 input_line_pointer += reloc_map[i].len;
7147 return reloc_map[i].reloc;
7151 s_arm_elf_cons (nbytes)
7156 #ifdef md_flush_pending_output
7157 md_flush_pending_output ();
7160 if (is_it_end_of_statement ())
7162 demand_empty_rest_of_line ();
7166 #ifdef md_cons_align
7167 md_cons_align (nbytes);
7172 bfd_reloc_code_real_type reloc;
7176 if (exp.X_op == O_symbol
7177 && * input_line_pointer == '('
7178 && (reloc = arm_parse_reloc()) != BFD_RELOC_UNUSED)
7180 reloc_howto_type * howto = bfd_reloc_type_lookup (stdoutput, reloc);
7181 int size = bfd_get_reloc_size (howto);
7184 as_bad ("%s relocations do not fit in %d bytes",
7185 howto->name, nbytes);
7188 register char * p = frag_more ((int) nbytes);
7189 int offset = nbytes - size;
7191 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7196 emit_expr (& exp, (unsigned int) nbytes);
7198 while (*input_line_pointer++ == ',');
7200 input_line_pointer--; /* Put terminator back into stream. */
7201 demand_empty_rest_of_line ();
7204 #endif /* OBJ_ELF */