1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 /* ??? This is currently unused. */
41 #define internalError() \
42 as_fatal (_("ARM Internal Error, line %d, %s"), __LINE__, __FILE__)
44 #define internalError() as_fatal (_("ARM Internal Error"))
47 /* Types of processor to assemble for. */
48 #define ARM_1 0x00000001
49 #define ARM_2 0x00000002
50 #define ARM_3 0x00000004
52 #define ARM_6 0x00000008
53 #define ARM_7 ARM_6 /* same core instruction set */
54 #define ARM_CPU_MASK 0x0000000f
56 /* The following bitmasks control CPU extensions (ARM7 onwards): */
57 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
58 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
59 #define ARM_THUMB 0x00000040 /* allow BX instruction */
61 #define ARM_ARCHv4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP 0x00fffffe
66 #define ARM_ALL ARM_2UP /* Not arm1 only */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
75 /* Some useful combinations */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
82 #define CPU_DEFAULT (ARM_ARCHv4 | ARM_THUMB)
84 #define CPU_DEFAULT ARM_ALL
89 #define FPU_DEFAULT FPU_ALL
92 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
94 #if defined OBJ_COFF || defined OBJ_ELF
95 /* Flags stored in private area of BFD structure */
96 static boolean uses_apcs_26 = false;
97 static boolean support_interwork = false;
98 static boolean uses_apcs_float = false;
99 static boolean pic_code = false;
102 /* This array holds the chars that always start a comment. If the
103 pre-processor is disabled, these aren't very useful */
104 CONST char comment_chars[] = "@";
106 /* This array holds the chars that only start a comment at the beginning of
107 a line. If the line seems to have the form '# 123 filename'
108 .line and .file directives will appear in the pre-processed output */
109 /* Note that input_file.c hand checks for '#' at the beginning of the
110 first line of the input file. This is because the compiler outputs
111 #NO_APP at the beginning of its output. */
112 /* Also note that comments like this one will always work. */
113 CONST char line_comment_chars[] = "#";
115 CONST char line_separator_chars[] = "";
117 /* Chars that can be used to separate mant from exp in floating point nums */
118 CONST char EXP_CHARS[] = "eE";
120 /* Chars that mean this number is a floating point constant */
124 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
126 CONST int md_reloc_size = 8; /* Size of relocation record */
128 static int thumb_mode = 0; /* non-zero if assembling thumb instructions */
130 typedef struct arm_fix
138 unsigned long instruction;
143 bfd_reloc_code_real_type type;
153 CONST char *template;
157 static CONST struct asm_shift shift[] =
173 #define NO_SHIFT_RESTRICT 1
174 #define SHIFT_RESTRICT 0
176 #define NUM_FLOAT_VALS 8
178 CONST char *fp_const[] =
180 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
183 /* Number of littlenums required to hold an extended precision number */
184 #define MAX_LITTLENUMS 6
186 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
196 #define CP_T_X 0x00008000
197 #define CP_T_Y 0x00400000
198 #define CP_T_Pre 0x01000000
199 #define CP_T_UD 0x00800000
200 #define CP_T_WB 0x00200000
202 #define CONDS_BIT (0x00100000)
203 #define LOAD_BIT (0x00100000)
204 #define TRANS_BIT (0x00200000)
208 CONST char *template;
212 /* This is to save a hash look-up in the common case */
213 #define COND_ALWAYS 0xe0000000
215 static CONST struct asm_cond conds[] =
219 {"cs", 0x20000000}, {"hs", 0x20000000},
220 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
235 /* Warning: If the top bit of the set_bits is set, then the standard
236 instruction bitmask is ignored, and the new bitmask is taken from
240 CONST char *template; /* Basic flag string */
241 unsigned long set_bits; /* Bits to set */
244 static CONST struct asm_flg s_flag[] =
250 static CONST struct asm_flg ldr_flags[] =
254 {"bt", 0x00400000 | TRANS_BIT},
261 static CONST struct asm_flg str_flags[] =
265 {"bt", 0x00400000 | TRANS_BIT},
270 static CONST struct asm_flg byte_flag[] =
276 static CONST struct asm_flg cmp_flags[] =
283 static CONST struct asm_flg ldm_flags[] =
296 static CONST struct asm_flg stm_flags[] =
309 static CONST struct asm_flg lfm_flags[] =
316 static CONST struct asm_flg sfm_flags[] =
323 static CONST struct asm_flg round_flags[] =
331 /* The implementation of the FIX instruction is broken on some assemblers,
332 in that it accepts a precision specifier as well as a rounding specifier,
333 despite the fact that this is meaningless. To be more compatible, we
334 accept it as well, though of course it does not set any bits. */
335 static CONST struct asm_flg fix_flags[] =
352 static CONST struct asm_flg except_flag[] =
358 static CONST struct asm_flg cplong_flag[] =
366 CONST char *template;
367 unsigned long number;
370 #define PSR_FIELD_MASK 0x000f0000
372 #define PSR_FLAGS 0x00080000
373 #define PSR_CONTROL 0x00010000 /* Undocumented instruction, its use is discouraged by ARM */
374 #define PSR_ALL 0x00090000
383 static CONST struct asm_psr psrs[] =
387 {"cpsr_all", CPSR_ALL},
389 {"spsr_all", SPSR_ALL},
392 {"cpsr_flg", CPSR_FLG},
393 {"spsr_flg", SPSR_FLG},
396 {"cpsr_c", CPSR_CTL},
397 {"cpsr_ctl", CPSR_CTL},
398 {"spsr_c", SPSR_CTL},
399 {"spsr_ctl", SPSR_CTL}
402 /* Functions called by parser */
403 /* ARM instructions */
404 static void do_arit PARAMS ((char *operands, unsigned long flags));
405 static void do_cmp PARAMS ((char *operands, unsigned long flags));
406 static void do_mov PARAMS ((char *operands, unsigned long flags));
407 static void do_ldst PARAMS ((char *operands, unsigned long flags));
408 static void do_ldmstm PARAMS ((char *operands, unsigned long flags));
409 static void do_branch PARAMS ((char *operands, unsigned long flags));
410 static void do_swi PARAMS ((char *operands, unsigned long flags));
411 /* Pseudo Op codes */
412 static void do_adr PARAMS ((char *operands, unsigned long flags));
413 static void do_nop PARAMS ((char *operands, unsigned long flags));
415 static void do_mul PARAMS ((char *operands, unsigned long flags));
416 static void do_mla PARAMS ((char *operands, unsigned long flags));
418 static void do_swap PARAMS ((char *operands, unsigned long flags));
420 static void do_msr PARAMS ((char *operands, unsigned long flags));
421 static void do_mrs PARAMS ((char *operands, unsigned long flags));
423 static void do_mull PARAMS ((char *operands, unsigned long flags));
425 static void do_bx PARAMS ((char *operands, unsigned long flags));
427 /* Coprocessor Instructions */
428 static void do_cdp PARAMS ((char *operands, unsigned long flags));
429 static void do_lstc PARAMS ((char *operands, unsigned long flags));
430 static void do_co_reg PARAMS ((char *operands, unsigned long flags));
431 static void do_fp_ctrl PARAMS ((char *operands, unsigned long flags));
432 static void do_fp_ldst PARAMS ((char *operands, unsigned long flags));
433 static void do_fp_ldmstm PARAMS ((char *operands, unsigned long flags));
434 static void do_fp_dyadic PARAMS ((char *operands, unsigned long flags));
435 static void do_fp_monadic PARAMS ((char *operands, unsigned long flags));
436 static void do_fp_cmp PARAMS ((char *operands, unsigned long flags));
437 static void do_fp_from_reg PARAMS ((char *operands, unsigned long flags));
438 static void do_fp_to_reg PARAMS ((char *operands, unsigned long flags));
440 static void fix_new_arm PARAMS ((fragS *frag, int where,
441 short int size, expressionS *exp,
442 int pc_rel, int reloc));
443 static int arm_reg_parse PARAMS ((char **ccp));
444 static int arm_psr_parse PARAMS ((char **ccp));
445 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT,
447 static int add_to_lit_pool PARAMS ((void));
448 static unsigned validate_immediate PARAMS ((unsigned));
449 static int validate_offset_imm PARAMS ((int, int));
450 static void opcode_select PARAMS ((int));
451 static void end_of_line PARAMS ((char *));
452 static int reg_required_here PARAMS ((char **, int));
453 static int psr_required_here PARAMS ((char **, int, int));
454 static int co_proc_number PARAMS ((char **));
455 static int cp_opc_expr PARAMS ((char **, int, int));
456 static int cp_reg_required_here PARAMS ((char **, int));
457 static int fp_reg_required_here PARAMS ((char **, int));
458 static int cp_address_offset PARAMS ((char **));
459 static int cp_address_required_here PARAMS ((char **));
460 static int my_get_float_expression PARAMS ((char **));
461 static int skip_past_comma PARAMS ((char **));
462 static int walk_no_bignums PARAMS ((symbolS *));
463 static int negate_data_op PARAMS ((unsigned long *,
465 static int data_op2 PARAMS ((char **));
466 static int fp_op2 PARAMS ((char **));
467 static long reg_list PARAMS ((char **));
468 static void thumb_load_store PARAMS ((char *, int, int));
469 static int decode_shift PARAMS ((char **, int));
470 static int ldst_extend PARAMS ((char **, int));
471 static void thumb_add_sub PARAMS ((char *, int));
472 static void insert_reg PARAMS ((int));
473 static void thumb_shift PARAMS ((char *, int));
474 static void thumb_mov_compare PARAMS ((char *, int));
475 static void set_constant_flonums PARAMS ((void));
476 static valueT md_chars_to_number PARAMS ((char *, int));
477 static void insert_reg_alias PARAMS ((char *, int));
478 static void output_inst PARAMS ((char *));
480 /* ARM instructions take 4bytes in the object file, Thumb instructions
484 /* LONGEST_INST is the longest basic instruction name without conditions or
486 * ARM7M has 4 of length 5
489 #define LONGEST_INST 5
493 CONST char *template; /* Basic string to match */
494 unsigned long value; /* Basic instruction code */
495 CONST char *comp_suffix; /* Compulsory suffix that must follow conds */
496 CONST struct asm_flg *flags; /* Bits to toggle if flag 'n' set */
497 unsigned long variants; /* Which CPU variants this exists for */
498 /* Function to call to parse args */
499 void (*parms) PARAMS ((char *, unsigned long));
502 static CONST struct asm_opcode insns[] =
504 /* ARM Instructions */
505 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
506 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
507 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
508 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
509 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
510 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
511 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
512 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
513 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
514 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
515 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
516 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
517 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
518 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
519 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
520 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
521 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
522 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
523 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
524 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
525 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
526 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
527 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
530 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
531 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
533 /* ARM 2 multiplies */
534 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
535 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
537 /* ARM 3 - swp instructions */
538 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
540 /* ARM 6 Coprocessor instructions */
541 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
542 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
544 /* ARM 7M long multiplies - need signed/unsigned flags! */
545 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
546 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
547 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
548 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
550 /* ARM THUMB interworking */
551 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
553 /* Floating point instructions */
554 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
555 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
556 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
557 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
558 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
559 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
560 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
561 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
562 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
563 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
564 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
565 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
566 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
567 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
568 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
569 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
570 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
571 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
572 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
573 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
574 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
575 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
576 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
577 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
578 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
579 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
580 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
581 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
582 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
583 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
584 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
585 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
586 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
587 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
588 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
589 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
590 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
591 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
592 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
593 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
594 be an optional suffix, but part of the instruction. To be compatible,
596 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
597 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
598 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
599 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
601 /* Generic copressor instructions */
602 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
603 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
604 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
605 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
606 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
609 /* defines for various bits that we will want to toggle */
611 #define INST_IMMEDIATE 0x02000000
612 #define OFFSET_REG 0x02000000
613 #define HWOFFSET_IMM 0x00400000
614 #define SHIFT_BY_REG 0x00000010
615 #define PRE_INDEX 0x01000000
616 #define INDEX_UP 0x00800000
617 #define WRITE_BACK 0x00200000
618 #define MULTI_SET_PSR 0x00400000
620 #define LITERAL_MASK 0xf000f000
621 #define COND_MASK 0xf0000000
622 #define OPCODE_MASK 0xfe1fffff
623 #define DATA_OP_SHIFT 21
625 /* Codes to distinguish the arithmetic instructions */
637 #define OPCODE_CMP 10
638 #define OPCODE_CMN 11
639 #define OPCODE_ORR 12
640 #define OPCODE_MOV 13
641 #define OPCODE_BIC 14
642 #define OPCODE_MVN 15
644 static void do_t_nop PARAMS ((char *operands));
645 static void do_t_arit PARAMS ((char *operands));
646 static void do_t_add PARAMS ((char *operands));
647 static void do_t_asr PARAMS ((char *operands));
648 static void do_t_branch9 PARAMS ((char *operands));
649 static void do_t_branch12 PARAMS ((char *operands));
650 static void do_t_branch23 PARAMS ((char *operands));
651 static void do_t_bx PARAMS ((char *operands));
652 static void do_t_compare PARAMS ((char *operands));
653 static void do_t_ldmstm PARAMS ((char *operands));
654 static void do_t_ldr PARAMS ((char *operands));
655 static void do_t_ldrb PARAMS ((char *operands));
656 static void do_t_ldrh PARAMS ((char *operands));
657 static void do_t_lds PARAMS ((char *operands));
658 static void do_t_lsl PARAMS ((char *operands));
659 static void do_t_lsr PARAMS ((char *operands));
660 static void do_t_mov PARAMS ((char *operands));
661 static void do_t_push_pop PARAMS ((char *operands));
662 static void do_t_str PARAMS ((char *operands));
663 static void do_t_strb PARAMS ((char *operands));
664 static void do_t_strh PARAMS ((char *operands));
665 static void do_t_sub PARAMS ((char *operands));
666 static void do_t_swi PARAMS ((char *operands));
667 static void do_t_adr PARAMS ((char *operands));
669 #define T_OPCODE_MUL 0x4340
670 #define T_OPCODE_TST 0x4200
671 #define T_OPCODE_CMN 0x42c0
672 #define T_OPCODE_NEG 0x4240
673 #define T_OPCODE_MVN 0x43c0
675 #define T_OPCODE_ADD_R3 0x1800
676 #define T_OPCODE_SUB_R3 0x1a00
677 #define T_OPCODE_ADD_HI 0x4400
678 #define T_OPCODE_ADD_ST 0xb000
679 #define T_OPCODE_SUB_ST 0xb080
680 #define T_OPCODE_ADD_SP 0xa800
681 #define T_OPCODE_ADD_PC 0xa000
682 #define T_OPCODE_ADD_I8 0x3000
683 #define T_OPCODE_SUB_I8 0x3800
684 #define T_OPCODE_ADD_I3 0x1c00
685 #define T_OPCODE_SUB_I3 0x1e00
687 #define T_OPCODE_ASR_R 0x4100
688 #define T_OPCODE_LSL_R 0x4080
689 #define T_OPCODE_LSR_R 0x40c0
690 #define T_OPCODE_ASR_I 0x1000
691 #define T_OPCODE_LSL_I 0x0000
692 #define T_OPCODE_LSR_I 0x0800
694 #define T_OPCODE_MOV_I8 0x2000
695 #define T_OPCODE_CMP_I8 0x2800
696 #define T_OPCODE_CMP_LR 0x4280
697 #define T_OPCODE_MOV_HR 0x4600
698 #define T_OPCODE_CMP_HR 0x4500
700 #define T_OPCODE_LDR_PC 0x4800
701 #define T_OPCODE_LDR_SP 0x9800
702 #define T_OPCODE_STR_SP 0x9000
703 #define T_OPCODE_LDR_IW 0x6800
704 #define T_OPCODE_STR_IW 0x6000
705 #define T_OPCODE_LDR_IH 0x8800
706 #define T_OPCODE_STR_IH 0x8000
707 #define T_OPCODE_LDR_IB 0x7800
708 #define T_OPCODE_STR_IB 0x7000
709 #define T_OPCODE_LDR_RW 0x5800
710 #define T_OPCODE_STR_RW 0x5000
711 #define T_OPCODE_LDR_RH 0x5a00
712 #define T_OPCODE_STR_RH 0x5200
713 #define T_OPCODE_LDR_RB 0x5c00
714 #define T_OPCODE_STR_RB 0x5400
716 #define T_OPCODE_PUSH 0xb400
717 #define T_OPCODE_POP 0xbc00
719 #define T_OPCODE_BRANCH 0xe7fe
721 static int thumb_reg PARAMS ((char **str, int hi_lo));
723 #define THUMB_SIZE 2 /* Size of thumb instruction */
724 #define THUMB_REG_LO 0x1
725 #define THUMB_REG_HI 0x2
726 #define THUMB_REG_ANY 0x3
728 #define THUMB_H1 0x0080
729 #define THUMB_H2 0x0040
736 #define THUMB_COMPARE 1
739 #define THUMB_STORE 1
741 #define THUMB_PP_PC_LR 0x0100
743 /* These three are used for immediate shifts, do not alter */
745 #define THUMB_HALFWORD 1
750 CONST char *template; /* Basic string to match */
751 unsigned long value; /* Basic instruction code */
753 /* Function to call to parse args */
754 void (*parms) PARAMS ((char *));
757 static CONST struct thumb_opcode tinsns[] =
759 {"adc", 0x4140, 2, do_t_arit},
760 {"add", 0x0000, 2, do_t_add},
761 {"and", 0x4000, 2, do_t_arit},
762 {"asr", 0x0000, 2, do_t_asr},
763 {"b", T_OPCODE_BRANCH, 2, do_t_branch12},
764 {"beq", 0xd0fe, 2, do_t_branch9},
765 {"bne", 0xd1fe, 2, do_t_branch9},
766 {"bcs", 0xd2fe, 2, do_t_branch9},
767 {"bhs", 0xd2fe, 2, do_t_branch9},
768 {"bcc", 0xd3fe, 2, do_t_branch9},
769 {"bul", 0xd3fe, 2, do_t_branch9},
770 {"blo", 0xd3fe, 2, do_t_branch9},
771 {"bmi", 0xd4fe, 2, do_t_branch9},
772 {"bpl", 0xd5fe, 2, do_t_branch9},
773 {"bvs", 0xd6fe, 2, do_t_branch9},
774 {"bvc", 0xd7fe, 2, do_t_branch9},
775 {"bhi", 0xd8fe, 2, do_t_branch9},
776 {"bls", 0xd9fe, 2, do_t_branch9},
777 {"bge", 0xdafe, 2, do_t_branch9},
778 {"blt", 0xdbfe, 2, do_t_branch9},
779 {"bgt", 0xdcfe, 2, do_t_branch9},
780 {"ble", 0xddfe, 2, do_t_branch9},
781 {"bic", 0x4380, 2, do_t_arit},
782 {"bl", 0xf7fffffe, 4, do_t_branch23},
783 {"bx", 0x4700, 2, do_t_bx},
784 {"cmn", T_OPCODE_CMN, 2, do_t_arit},
785 {"cmp", 0x0000, 2, do_t_compare},
786 {"eor", 0x4040, 2, do_t_arit},
787 {"ldmia", 0xc800, 2, do_t_ldmstm},
788 {"ldr", 0x0000, 2, do_t_ldr},
789 {"ldrb", 0x0000, 2, do_t_ldrb},
790 {"ldrh", 0x0000, 2, do_t_ldrh},
791 {"ldrsb", 0x5600, 2, do_t_lds},
792 {"ldrsh", 0x5e00, 2, do_t_lds},
793 {"ldsb", 0x5600, 2, do_t_lds},
794 {"ldsh", 0x5e00, 2, do_t_lds},
795 {"lsl", 0x0000, 2, do_t_lsl},
796 {"lsr", 0x0000, 2, do_t_lsr},
797 {"mov", 0x0000, 2, do_t_mov},
798 {"mul", T_OPCODE_MUL, 2, do_t_arit},
799 {"mvn", T_OPCODE_MVN, 2, do_t_arit},
800 {"neg", T_OPCODE_NEG, 2, do_t_arit},
801 {"orr", 0x4300, 2, do_t_arit},
802 {"pop", 0xbc00, 2, do_t_push_pop},
803 {"push", 0xb400, 2, do_t_push_pop},
804 {"ror", 0x41c0, 2, do_t_arit},
805 {"sbc", 0x4180, 2, do_t_arit},
806 {"stmia", 0xc000, 2, do_t_ldmstm},
807 {"str", 0x0000, 2, do_t_str},
808 {"strb", 0x0000, 2, do_t_strb},
809 {"strh", 0x0000, 2, do_t_strh},
810 {"swi", 0xdf00, 2, do_t_swi},
811 {"sub", 0x0000, 2, do_t_sub},
812 {"tst", T_OPCODE_TST, 2, do_t_arit},
814 {"adr", 0x0000, 2, do_t_adr},
815 {"nop", 0x46C0, 2, do_t_nop}, /* mov r8,r8 */
824 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
825 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
826 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
832 /* These are the standard names; Users can add aliases with .req */
833 static CONST struct reg_entry reg_table[] =
835 /* Processor Register Numbers */
836 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
837 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
838 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
839 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
840 /* APCS conventions */
841 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
842 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
843 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
844 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
846 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
847 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
848 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
849 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
850 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
851 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
852 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
853 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
854 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
855 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
859 #define bad_args _("Bad arguments to instruction");
860 #define bad_pc _("r15 not allowed here");
862 static struct hash_control *arm_ops_hsh = NULL;
863 static struct hash_control *arm_tops_hsh = NULL;
864 static struct hash_control *arm_cond_hsh = NULL;
865 static struct hash_control *arm_shift_hsh = NULL;
866 static struct hash_control *arm_reg_hsh = NULL;
867 static struct hash_control *arm_psr_hsh = NULL;
869 /* This table describes all the machine specific pseudo-ops the assembler
870 has to support. The fields are:
871 pseudo-op name without dot
872 function to call to execute this pseudo-op
873 Integer arg to pass to the function
876 static void s_req PARAMS ((int));
877 static void s_align PARAMS ((int));
878 static void s_bss PARAMS ((int));
879 static void s_even PARAMS ((int));
880 static void s_ltorg PARAMS ((int));
881 static void s_arm PARAMS ((int));
882 static void s_thumb PARAMS ((int));
883 static void s_code PARAMS ((int));
884 static void s_force_thumb PARAMS ((int));
885 static void s_thumb_func PARAMS ((int));
887 static int my_get_expression PARAMS ((expressionS *, char **));
889 CONST pseudo_typeS md_pseudo_table[] =
891 {"req", s_req, 0}, /* Never called becasue '.req' does not start line */
893 {"align", s_align, 0},
895 {"thumb", s_thumb, 0},
897 {"force_thumb", s_force_thumb, 0},
898 {"thumb_func", s_thumb_func, 0},
900 {"ltorg", s_ltorg, 0},
901 {"pool", s_ltorg, 0},
903 {"extend", float_cons, 'x'},
904 {"ldouble", float_cons, 'x'},
905 {"packed", float_cons, 'p'},
909 /* Stuff needed to resolve the label ambiguity
919 symbolS * last_label_seen;
920 static int label_is_thumb_function_name = false;
924 #define MAX_LITERAL_POOL_SIZE 1024
926 typedef struct literalS
928 struct expressionS exp;
932 literalT literals[MAX_LITERAL_POOL_SIZE];
933 int next_literal_pool_place = 0; /* Next free entry in the pool */
934 int lit_pool_num = 1; /* Next literal pool number */
935 symbolS *current_poolP = NULL;
936 symbolS *symbol_make_empty PARAMS ((void));
943 if (current_poolP == NULL)
944 current_poolP = symbol_make_empty();
946 /* Check if this literal value is already in the pool: */
947 while (lit_count < next_literal_pool_place)
949 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
950 && inst.reloc.exp.X_op == O_constant
951 && literals[lit_count].exp.X_add_number == inst.reloc.exp.X_add_number
952 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
957 if (lit_count == next_literal_pool_place) /* new entry */
959 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
961 inst.error = _("Literal Pool Overflow");
965 literals[next_literal_pool_place].exp = inst.reloc.exp;
966 lit_count = next_literal_pool_place++;
969 inst.reloc.exp.X_op = O_symbol;
970 inst.reloc.exp.X_add_number = (lit_count)*4-8;
971 inst.reloc.exp.X_add_symbol = current_poolP;
976 /* Can't use symbol_new here, so have to create a symbol and then at
977 a later date assign it a value. Thats what these functions do */
979 symbol_locate (symbolP, name, segment, valu, frag)
981 CONST char *name; /* It is copied, the caller can modify */
982 segT segment; /* Segment identifier (SEG_<something>) */
983 valueT valu; /* Symbol value */
984 fragS *frag; /* Associated fragment */
986 unsigned int name_length;
987 char *preserved_copy_of_name;
989 name_length = strlen (name) + 1; /* +1 for \0 */
990 obstack_grow (¬es, name, name_length);
991 preserved_copy_of_name = obstack_finish (¬es);
992 #ifdef STRIP_UNDERSCORE
993 if (preserved_copy_of_name[0] == '_')
994 preserved_copy_of_name++;
997 #ifdef tc_canonicalize_symbol_name
998 preserved_copy_of_name =
999 tc_canonicalize_symbol_name (preserved_copy_of_name);
1002 S_SET_NAME (symbolP, preserved_copy_of_name);
1004 S_SET_SEGMENT (symbolP, segment);
1005 S_SET_VALUE (symbolP, valu);
1006 symbol_clear_list_pointers(symbolP);
1008 symbolP->sy_frag = frag;
1011 * Link to end of symbol chain.
1014 extern int symbol_table_frozen;
1015 if (symbol_table_frozen)
1019 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1021 obj_symbol_new_hook (symbolP);
1023 #ifdef tc_symbol_new_hook
1024 tc_symbol_new_hook (symbolP);
1028 verify_symbol_chain(symbol_rootP, symbol_lastP);
1029 #endif /* DEBUG_SYMS */
1033 symbol_make_empty ()
1037 symbolP = (symbolS *) obstack_alloc (¬es, sizeof (symbolS));
1039 /* symbol must be born in some fixed state. This seems as good as any. */
1040 memset (symbolP, 0, sizeof (symbolS));
1042 symbolP->bsym = bfd_make_empty_symbol (stdoutput);
1043 assert (symbolP->bsym != 0);
1044 symbolP->bsym->udata.p = (PTR) symbolP;
1049 /* Check that an immediate is valid, and if so, convert it to the right format. */
1052 validate_immediate (val)
1058 #define rotate_left(v, n) (v << n | v >> (32 - n))
1060 for (i = 0; i < 32; i += 2)
1061 if ((a = rotate_left (val, i)) <= 0xff)
1062 return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
1067 validate_offset_imm (val, hwse)
1071 if ((hwse && (val < -255 || val > 255))
1072 || (val < -4095 || val > 4095))
1082 as_bad (_("Invalid syntax for .req directive."));
1089 /* We don't support putting frags in the BSS segment, we fake it by
1090 marking in_bss, then looking at s_skip for clues?.. */
1091 subseg_set (bss_section, 0);
1092 demand_empty_rest_of_line ();
1099 if (!need_pass_2) /* Never make frag if expect extra pass. */
1100 frag_align (1, 0, 0);
1101 record_alignment (now_seg, 1);
1102 demand_empty_rest_of_line ();
1112 if (current_poolP == NULL)
1116 as_tsktsk (_("Nothing to put in the pool\n"));
1120 /* Align pool as you have word accesses */
1121 /* Only make a frag if we have to ... */
1123 frag_align (2, 0, 0);
1125 record_alignment (now_seg, 2);
1128 as_tsktsk (_("Inserting implicit pool at change of section"));
1130 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1132 symbol_locate (current_poolP, sym_name, now_seg,
1133 (valueT) frag_now_fix (), frag_now);
1134 symbol_table_insert (current_poolP);
1136 ARM_SET_THUMB (current_poolP, thumb_mode);
1137 #if defined OBJ_COFF || defined OBJ_ELF
1138 ARM_SET_INTERWORK (current_poolP, support_interwork);
1141 while (lit_count < next_literal_pool_place)
1142 /* First output the expression in the instruction to the pool */
1143 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1145 next_literal_pool_place = 0;
1146 current_poolP = NULL;
1149 #if 0 /* not used */
1151 arm_align (power, fill)
1155 /* Only make a frag if we HAVE to ... */
1156 if (power && !need_pass_2)
1157 frag_align (power, fill, 0);
1159 record_alignment (now_seg, power);
1164 s_align (unused) /* Same as s_align_ptwo but align 0 => align 2 */
1168 register long temp_fill;
1169 long max_alignment = 15;
1171 temp = get_absolute_expression ();
1172 if (temp > max_alignment)
1173 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1176 as_bad (_("Alignment negative. 0 assumed."));
1180 if (*input_line_pointer == ',')
1182 input_line_pointer++;
1183 temp_fill = get_absolute_expression ();
1191 /* Only make a frag if we HAVE to. . . */
1192 if (temp && !need_pass_2)
1193 frag_align (temp, (int) temp_fill, 0);
1194 demand_empty_rest_of_line ();
1196 record_alignment (now_seg, temp);
1200 s_force_thumb (ignore)
1203 /* If we are not already in thumb mode go into it, EVEN if
1204 the target processor does not support thumb instructions.
1205 This is used by gcc/config/arm/lib1funcs.asm for example
1206 to compile interworking support functions even if the
1207 target processor should not support interworking. */
1213 record_alignment (now_seg, 1);
1216 demand_empty_rest_of_line ();
1220 s_thumb_func (ignore)
1223 /* The following label is the name/address of the start of a Thumb function.
1224 We need to know this for the interworking support. */
1226 label_is_thumb_function_name = true;
1228 demand_empty_rest_of_line();
1232 opcode_select (width)
1240 if (! (cpu_variant & ARM_THUMB))
1241 as_bad (_("selected processor does not support THUMB opcodes"));
1243 /* No need to force the alignment, since we will have been
1244 coming from ARM mode, which is word-aligned. */
1245 record_alignment (now_seg, 1);
1252 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1253 as_bad (_("selected processor does not support ARM opcodes"));
1256 frag_align (2, 0, 0);
1257 record_alignment (now_seg, 1);
1262 as_bad (_("invalid instruction size selected (%d)"), width);
1271 demand_empty_rest_of_line ();
1279 demand_empty_rest_of_line ();
1288 temp = get_absolute_expression ();
1293 opcode_select(temp);
1297 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1309 inst.error = _("Garbage following instruction");
1313 skip_past_comma (str)
1319 while ((c = *p) == ' ' || c == ',')
1322 if (c == ',' && comma++)
1330 return comma ? SUCCESS : FAIL;
1333 /* A standard register must be given at this point. Shift is the place to
1334 put it in the instruction. */
1337 reg_required_here (str, shift)
1344 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1346 inst.instruction |= reg << shift;
1350 /* In the few cases where we might be able to accept something else
1351 this error can be overridden */
1352 inst.error = _("Register expected");
1354 /* Restore the start point, we may have got a reg of the wrong class. */
1360 psr_required_here (str, cpsr, spsr)
1366 char * start = *str;
1367 psr = arm_psr_parse (str);
1369 if (psr == cpsr || psr == spsr)
1372 inst.instruction |= 1 << 22;
1377 /* In the few cases where we might be able to accept something else
1378 this error can be overridden */
1379 inst.error = _("<psr(f)> expected");
1381 /* Restore the start point. */
1387 co_proc_number (str)
1390 int processor, pchar;
1392 while (**str == ' ')
1395 /* The data sheet seems to imply that just a number on its own is valid
1396 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1398 if (**str == 'p' || **str == 'P')
1402 if (pchar >= '0' && pchar <= '9')
1404 processor = pchar - '0';
1405 if (**str >= '0' && **str <= '9')
1407 processor = processor * 10 + *(*str)++ - '0';
1410 inst.error = _("Illegal co-processor number");
1417 inst.error = _("Bad or missing co-processor number");
1421 inst.instruction |= processor << 8;
1426 cp_opc_expr (str, where, length)
1433 while (**str == ' ')
1436 memset (&expr, '\0', sizeof (expr));
1438 if (my_get_expression (&expr, str))
1440 if (expr.X_op != O_constant)
1442 inst.error = _("bad or missing expression");
1446 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1448 inst.error = _("immediate co-processor expression too large");
1452 inst.instruction |= expr.X_add_number << where;
1457 cp_reg_required_here (str, where)
1464 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1467 inst.instruction |= reg << where;
1471 /* In the few cases where we might be able to accept something else
1472 this error can be overridden */
1473 inst.error = _("Co-processor register expected");
1475 /* Restore the start point */
1481 fp_reg_required_here (str, where)
1488 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1491 inst.instruction |= reg << where;
1495 /* In the few cases where we might be able to accept something else
1496 this error can be overridden */
1497 inst.error = _("Floating point register expected");
1499 /* Restore the start point */
1505 cp_address_offset (str)
1510 while (**str == ' ')
1515 inst.error = _("immediate expression expected");
1520 if (my_get_expression (&inst.reloc.exp, str))
1522 if (inst.reloc.exp.X_op == O_constant)
1524 offset = inst.reloc.exp.X_add_number;
1527 inst.error = _("co-processor address must be word aligned");
1531 if (offset > 1023 || offset < -1023)
1533 inst.error = _("offset too large");
1538 inst.instruction |= INDEX_UP;
1542 inst.instruction |= offset >> 2;
1545 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1551 cp_address_required_here (str)
1566 if ((reg = reg_required_here (&p, 16)) == FAIL)
1568 inst.error = _("Register required");
1578 if (skip_past_comma (&p) == SUCCESS)
1581 write_back = WRITE_BACK;
1584 inst.error = _("pc may not be used in post-increment");
1588 if (cp_address_offset (&p) == FAIL)
1592 pre_inc = PRE_INDEX | INDEX_UP;
1596 /* '['Rn, #expr']'[!] */
1598 if (skip_past_comma (&p) == FAIL)
1600 inst.error = _("pre-indexed expression expected");
1604 pre_inc = PRE_INDEX;
1605 if (cp_address_offset (&p) == FAIL)
1613 inst.error = _("missing ]");
1624 inst.error = _("pc may not be used with write-back");
1629 write_back = WRITE_BACK;
1635 if (my_get_expression (&inst.reloc.exp, &p))
1638 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1639 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
1640 inst.reloc.pc_rel = 1;
1641 inst.instruction |= (REG_PC << 16);
1642 pre_inc = PRE_INDEX;
1645 inst.instruction |= write_back | pre_inc;
1653 unsigned long flags;
1655 /* Do nothing really */
1656 inst.instruction |= flags; /* This is pointless */
1664 unsigned long flags;
1666 /* Only one syntax */
1670 if (reg_required_here (&str, 12) == FAIL)
1672 inst.error = bad_args;
1676 if (skip_past_comma (&str) == FAIL
1677 || psr_required_here (& str, CPSR_ALL, SPSR_ALL) == FAIL)
1679 inst.error = _("<psr> expected");
1683 inst.instruction |= flags;
1688 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression" */
1692 unsigned long flags;
1699 if (psr_required_here (&str, CPSR_ALL, SPSR_ALL) == SUCCESS)
1701 inst.instruction |= PSR_ALL;
1703 /* Sytax should be "<psr>, Rm" */
1704 if (skip_past_comma (&str) == FAIL
1705 || (reg = reg_required_here (&str, 0)) == FAIL)
1707 inst.error = bad_args;
1713 if (psr_required_here (& str, CPSR_FLG, SPSR_FLG) == SUCCESS)
1715 inst.instruction |= PSR_FLAGS;
1717 else if (psr_required_here (& str, CPSR_CTL, SPSR_CTL) == SUCCESS)
1719 inst.instruction |= PSR_CONTROL;
1723 inst.error = bad_args;
1727 if (skip_past_comma (&str) == FAIL)
1729 inst.error = bad_args;
1733 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1735 if ((reg = reg_required_here (&str, 0)) != FAIL)
1737 /* Immediate expression */
1738 else if (*(str++) == '#')
1741 if (my_get_expression (&inst.reloc.exp, &str))
1743 inst.error = _("Register or shift expression expected");
1747 if (inst.reloc.exp.X_add_symbol)
1749 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
1750 inst.reloc.pc_rel = 0;
1754 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
1757 inst.error = _("Invalid constant");
1761 inst.instruction |= value;
1764 flags |= INST_IMMEDIATE;
1768 inst.error = _("Error: unrecognised syntax for second argument to msr instruction");
1774 inst.instruction |= flags;
1779 /* Long Multiply Parser
1780 UMULL RdLo, RdHi, Rm, Rs
1781 SMULL RdLo, RdHi, Rm, Rs
1782 UMLAL RdLo, RdHi, Rm, Rs
1783 SMLAL RdLo, RdHi, Rm, Rs
1786 do_mull (str, flags)
1788 unsigned long flags;
1790 int rdlo, rdhi, rm, rs;
1792 /* only one format "rdlo, rdhi, rm, rs" */
1796 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
1798 inst.error = bad_args;
1802 if (skip_past_comma (&str) == FAIL
1803 || (rdhi = reg_required_here (&str, 16)) == FAIL)
1805 inst.error = bad_args;
1809 if (skip_past_comma (&str) == FAIL
1810 || (rm = reg_required_here (&str, 0)) == FAIL)
1812 inst.error = bad_args;
1816 /* rdhi, rdlo and rm must all be different */
1817 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
1818 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
1820 if (skip_past_comma (&str) == FAIL
1821 || (rs = reg_required_here (&str, 8)) == FAIL)
1823 inst.error = bad_args;
1827 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
1829 inst.error = bad_pc;
1833 inst.instruction |= flags;
1841 unsigned long flags;
1845 /* only one format "rd, rm, rs" */
1849 if ((rd = reg_required_here (&str, 16)) == FAIL)
1851 inst.error = bad_args;
1857 inst.error = bad_pc;
1861 if (skip_past_comma (&str) == FAIL
1862 || (rm = reg_required_here (&str, 0)) == FAIL)
1864 inst.error = bad_args;
1870 inst.error = bad_pc;
1875 as_tsktsk (_("rd and rm should be different in mul"));
1877 if (skip_past_comma (&str) == FAIL
1878 || (rm = reg_required_here (&str, 8)) == FAIL)
1880 inst.error = bad_args;
1886 inst.error = bad_pc;
1890 inst.instruction |= flags;
1898 unsigned long flags;
1902 /* only one format "rd, rm, rs, rn" */
1906 if ((rd = reg_required_here (&str, 16)) == FAIL)
1908 inst.error = bad_args;
1914 inst.error = bad_pc;
1918 if (skip_past_comma (&str) == FAIL
1919 || (rm = reg_required_here (&str, 0)) == FAIL)
1921 inst.error = bad_args;
1927 inst.error = bad_pc;
1932 as_tsktsk (_("rd and rm should be different in mla"));
1934 if (skip_past_comma (&str) == FAIL
1935 || (rd = reg_required_here (&str, 8)) == FAIL
1936 || skip_past_comma (&str) == FAIL
1937 || (rm = reg_required_here (&str, 12)) == FAIL)
1939 inst.error = bad_args;
1943 if (rd == REG_PC || rm == REG_PC)
1945 inst.error = bad_pc;
1949 inst.instruction |= flags;
1954 /* Returns the index into fp_values of a floating point number, or -1 if
1955 not in the table. */
1957 my_get_float_expression (str)
1960 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1965 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
1966 /* Look for a raw floating point number */
1967 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
1968 && (is_end_of_line [(int)(*save_in)] || *save_in == '\0'))
1970 for (i = 0; i < NUM_FLOAT_VALS; i++)
1972 for (j = 0; j < MAX_LITTLENUMS; j++)
1974 if (words[j] != fp_values[i][j])
1978 if (j == MAX_LITTLENUMS)
1986 /* Try and parse a more complex expression, this will probably fail
1987 unless the code uses a floating point prefix (eg "0f") */
1988 save_in = input_line_pointer;
1989 input_line_pointer = *str;
1990 if (expression (&exp) == absolute_section
1991 && exp.X_op == O_big
1992 && exp.X_add_number < 0)
1994 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
1996 if (gen_to_words (words, 5, (long)15) == 0)
1998 for (i = 0; i < NUM_FLOAT_VALS; i++)
2000 for (j = 0; j < MAX_LITTLENUMS; j++)
2002 if (words[j] != fp_values[i][j])
2006 if (j == MAX_LITTLENUMS)
2008 *str = input_line_pointer;
2009 input_line_pointer = save_in;
2016 *str = input_line_pointer;
2017 input_line_pointer = save_in;
2021 /* Return true if anything in the expression is a bignum */
2023 walk_no_bignums (sp)
2026 if (sp->sy_value.X_op == O_big)
2029 if (sp->sy_value.X_add_symbol)
2031 return (walk_no_bignums (sp->sy_value.X_add_symbol)
2032 || (sp->sy_value.X_op_symbol
2033 && walk_no_bignums (sp->sy_value.X_op_symbol)));
2040 my_get_expression (ep, str)
2047 save_in = input_line_pointer;
2048 input_line_pointer = *str;
2049 seg = expression (ep);
2052 if (seg != absolute_section
2053 && seg != text_section
2054 && seg != data_section
2055 && seg != bss_section
2056 && seg != undefined_section)
2058 inst.error = _("bad_segment");
2059 *str = input_line_pointer;
2060 input_line_pointer = save_in;
2065 /* Get rid of any bignums now, so that we don't generate an error for which
2066 we can't establish a line number later on. Big numbers are never valid
2067 in instructions, which is where this routine is always called. */
2068 if (ep->X_op == O_big
2069 || (ep->X_add_symbol
2070 && (walk_no_bignums (ep->X_add_symbol)
2072 && walk_no_bignums (ep->X_op_symbol)))))
2074 inst.error = _("Invalid constant");
2075 *str = input_line_pointer;
2076 input_line_pointer = save_in;
2080 *str = input_line_pointer;
2081 input_line_pointer = save_in;
2085 /* unrestrict should be one if <shift> <register> is permitted for this
2089 decode_shift (str, unrestrict)
2093 struct asm_shift *shft;
2097 while (**str == ' ')
2100 for (p = *str; isalpha (*p); p++)
2105 inst.error = _("Shift expression expected");
2111 shft = (struct asm_shift *) hash_find (arm_shift_hsh, *str);
2115 if (!strncmp (*str, "rrx", 3)
2116 || !strncmp (*str, "RRX", 3))
2119 inst.instruction |= shft->value;
2126 if (unrestrict && reg_required_here (&p, 8) != FAIL)
2128 inst.instruction |= shft->value | SHIFT_BY_REG;
2136 if (my_get_expression (&inst.reloc.exp, &p))
2139 /* Validate some simple #expressions */
2140 if (inst.reloc.exp.X_op == O_constant)
2142 unsigned num = inst.reloc.exp.X_add_number;
2144 /* Reject operations greater than 32, or lsl #32 */
2145 if (num > 32 || (num == 32 && shft->value == 0))
2147 inst.error = _("Invalid immediate shift");
2151 /* Shifts of zero should be converted to lsl (which is zero)*/
2158 /* Shifts of 32 are encoded as 0, for those shifts that
2163 inst.instruction |= (num << 7) | shft->value;
2168 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2169 inst.reloc.pc_rel = 0;
2170 inst.instruction |= shft->value;
2176 inst.error = unrestrict ? _("shift requires register or #expression")
2177 : _("shift requires #expression");
2183 inst.error = _("Shift expression expected");
2187 /* Do those data_ops which can take a negative immediate constant */
2188 /* by altering the instuction. A bit of a hack really */
2192 by inverting the second operand, and
2195 by negating the second operand.
2198 negate_data_op (instruction, value)
2199 unsigned long *instruction;
2200 unsigned long value;
2203 unsigned long negated, inverted;
2205 negated = validate_immediate (-value);
2206 inverted = validate_immediate (~value);
2208 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2212 case OPCODE_SUB: /* ADD <-> SUB */
2213 new_inst = OPCODE_ADD;
2218 new_inst = OPCODE_SUB;
2222 case OPCODE_CMP: /* CMP <-> CMN */
2223 new_inst = OPCODE_CMN;
2228 new_inst = OPCODE_CMP;
2232 /* Now Inverted ops */
2233 case OPCODE_MOV: /* MOV <-> MVN */
2234 new_inst = OPCODE_MVN;
2239 new_inst = OPCODE_MOV;
2243 case OPCODE_AND: /* AND <-> BIC */
2244 new_inst = OPCODE_BIC;
2249 new_inst = OPCODE_AND;
2253 case OPCODE_ADC: /* ADC <-> SBC */
2254 new_inst = OPCODE_SBC;
2259 new_inst = OPCODE_ADC;
2263 /* We cannot do anything */
2271 *instruction &= OPCODE_MASK;
2272 *instruction |= new_inst << DATA_OP_SHIFT;
2283 while (**str == ' ')
2286 if (reg_required_here (str, 0) != FAIL)
2288 if (skip_past_comma (str) == SUCCESS)
2290 /* Shift operation on register */
2291 return decode_shift (str, NO_SHIFT_RESTRICT);
2297 /* Immediate expression */
2298 if (*((*str)++) == '#')
2301 if (my_get_expression (&inst.reloc.exp, str))
2304 if (inst.reloc.exp.X_add_symbol)
2306 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2307 inst.reloc.pc_rel = 0;
2311 if (skip_past_comma (str) == SUCCESS)
2313 /* #x, y -- ie explicit rotation by Y */
2314 if (my_get_expression (&expr, str))
2317 if (expr.X_op != O_constant)
2319 inst.error = _("Constant expression expected");
2323 /* Rotate must be a multiple of 2 */
2324 if (((unsigned) expr.X_add_number) > 30
2325 || (expr.X_add_number & 1) != 0
2326 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2328 inst.error = _("Invalid constant");
2331 inst.instruction |= INST_IMMEDIATE;
2332 inst.instruction |= inst.reloc.exp.X_add_number;
2333 inst.instruction |= expr.X_add_number << 7;
2337 /* Implicit rotation, select a suitable one */
2338 value = validate_immediate (inst.reloc.exp.X_add_number);
2342 /* Can't be done, perhaps the code reads something like
2343 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2344 if ((value = negate_data_op (&inst.instruction,
2345 inst.reloc.exp.X_add_number))
2348 inst.error = _("Invalid constant");
2353 inst.instruction |= value;
2356 inst.instruction |= INST_IMMEDIATE;
2360 inst.error = _("Register or shift expression expected");
2369 while (**str == ' ')
2372 if (fp_reg_required_here (str, 0) != FAIL)
2376 /* Immediate expression */
2377 if (*((*str)++) == '#')
2382 while (**str == ' ')
2385 /* First try and match exact strings, this is to guarantee that
2386 some formats will work even for cross assembly */
2388 for (i = 0; fp_const[i]; i++)
2390 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2394 *str += strlen (fp_const[i]);
2395 if (is_end_of_line[(int)**str] || **str == '\0')
2397 inst.instruction |= i + 8;
2404 /* Just because we didn't get a match doesn't mean that the
2405 constant isn't valid, just that it is in a format that we
2406 don't automatically recognize. Try parsing it with
2407 the standard expression routines. */
2408 if ((i = my_get_float_expression (str)) >= 0)
2410 inst.instruction |= i + 8;
2414 inst.error = _("Invalid floating point immediate expression");
2417 inst.error = _("Floating point register or immediate expression expected");
2423 do_arit (str, flags)
2425 unsigned long flags;
2430 if (reg_required_here (&str, 12) == FAIL
2431 || skip_past_comma (&str) == FAIL
2432 || reg_required_here (&str, 16) == FAIL
2433 || skip_past_comma (&str) == FAIL
2434 || data_op2 (&str) == FAIL)
2437 inst.error = bad_args;
2441 inst.instruction |= flags;
2449 unsigned long flags;
2451 /* This is a pseudo-op of the form "adr rd, label" to be converted
2452 into a relative address of the form "add rd, pc, #label-.-8" */
2457 if (reg_required_here (&str, 12) == FAIL
2458 || skip_past_comma (&str) == FAIL
2459 || my_get_expression (&inst.reloc.exp, &str))
2462 inst.error = bad_args;
2465 /* Frag hacking will turn this into a sub instruction if the offset turns
2466 out to be negative. */
2467 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2468 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2469 inst.reloc.pc_rel = 1;
2470 inst.instruction |= flags;
2478 unsigned long flags;
2483 if (reg_required_here (&str, 16) == FAIL)
2486 inst.error = bad_args;
2490 if (skip_past_comma (&str) == FAIL
2491 || data_op2 (&str) == FAIL)
2494 inst.error = bad_args;
2498 inst.instruction |= flags;
2499 if ((flags & 0x0000f000) == 0)
2500 inst.instruction |= CONDS_BIT;
2509 unsigned long flags;
2514 if (reg_required_here (&str, 12) == FAIL)
2517 inst.error = bad_args;
2521 if (skip_past_comma (&str) == FAIL
2522 || data_op2 (&str) == FAIL)
2525 inst.error = bad_args;
2529 inst.instruction |= flags;
2535 ldst_extend (str, hwse)
2545 if (my_get_expression (&inst.reloc.exp, str))
2548 if (inst.reloc.exp.X_op == O_constant)
2550 int value = inst.reloc.exp.X_add_number;
2552 if ((hwse && (value < -255 || value > 255))
2553 || (value < -4095 || value > 4095))
2555 inst.error = _("address offset too large");
2565 /* Halfword and signextension instructions have the
2566 immediate value split across bits 11..8 and bits 3..0 */
2568 inst.instruction |= add | HWOFFSET_IMM | (value >> 4) << 8 | value & 0xF;
2570 inst.instruction |= add | value;
2576 inst.instruction |= HWOFFSET_IMM;
2577 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2580 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2581 inst.reloc.pc_rel = 0;
2586 add = 0; /* and fall through */
2588 (*str)++; /* and fall through */
2590 if (reg_required_here (str, 0) == FAIL)
2592 inst.error = _("Register expected");
2597 inst.instruction |= add;
2600 inst.instruction |= add | OFFSET_REG;
2601 if (skip_past_comma (str) == SUCCESS)
2602 return decode_shift (str, SHIFT_RESTRICT);
2610 do_ldst (str, flags)
2612 unsigned long flags;
2619 /* This is not ideal, but it is the simplest way of dealing with the
2620 ARM7T halfword instructions (since they use a different
2621 encoding, but the same mnemonic): */
2622 if (halfword = ((flags & 0x80000000) != 0))
2624 /* This is actually a load/store of a halfword, or a
2625 signed-extension load */
2626 if ((cpu_variant & ARM_HALFWORD) == 0)
2629 = _("Processor does not support halfwords or signed bytes");
2633 inst.instruction = (inst.instruction & COND_MASK)
2634 | (flags & ~COND_MASK);
2642 if ((conflict_reg = reg_required_here (&str, 12)) == FAIL)
2645 inst.error = bad_args;
2649 if (skip_past_comma (&str) == FAIL)
2651 inst.error = _("Address expected");
2663 if ((reg = reg_required_here (&str, 16)) == FAIL)
2665 inst.error = _("Register required");
2669 conflict_reg = (((conflict_reg == reg)
2670 && (inst.instruction & LOAD_BIT))
2679 if (skip_past_comma (&str) == SUCCESS)
2681 /* [Rn],... (post inc) */
2682 if (ldst_extend (&str, halfword) == FAIL)
2685 as_warn (_("destination register same as write-back base\n"));
2691 inst.instruction |= HWOFFSET_IMM;
2699 as_warn (_("destination register same as write-back base\n"));
2701 inst.instruction |= WRITE_BACK;
2705 if (! (flags & TRANS_BIT))
2712 if (skip_past_comma (&str) == FAIL)
2714 inst.error = _("pre-indexed expression expected");
2719 if (ldst_extend (&str, halfword) == FAIL)
2727 inst.error = _("missing ]");
2737 as_tsktsk (_("destination register same as write-back base\n"));
2739 inst.instruction |= WRITE_BACK;
2743 else if (*str == '=')
2745 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2751 if (my_get_expression (&inst.reloc.exp, &str))
2754 if (inst.reloc.exp.X_op != O_constant
2755 && inst.reloc.exp.X_op != O_symbol)
2757 inst.error = _("Constant expression expected");
2761 if (inst.reloc.exp.X_op == O_constant
2762 && (value = validate_immediate(inst.reloc.exp.X_add_number)) != FAIL)
2764 /* This can be done with a mov instruction */
2765 inst.instruction &= LITERAL_MASK;
2766 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
2767 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
2773 /* Insert into literal pool */
2774 if (add_to_lit_pool () == FAIL)
2777 inst.error = _("literal pool insertion failed");
2781 /* Change the instruction exp to point to the pool */
2784 inst.instruction |= HWOFFSET_IMM;
2785 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
2788 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
2789 inst.reloc.pc_rel = 1;
2790 inst.instruction |= (REG_PC << 16);
2796 if (my_get_expression (&inst.reloc.exp, &str))
2801 inst.instruction |= HWOFFSET_IMM;
2802 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2805 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2806 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
2807 inst.reloc.pc_rel = 1;
2808 inst.instruction |= (REG_PC << 16);
2812 if (pre_inc && (flags & TRANS_BIT))
2813 inst.error = _("Pre-increment instruction with translate");
2815 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
2828 /* We come back here if we get ranges concatenated by '+' or '|' */
2846 if ((reg = arm_reg_parse (&str)) == FAIL || !int_register (reg))
2848 inst.error = _("Register expected");
2858 inst.error = _("Bad range in register list");
2862 for (i = cur_reg + 1; i < reg; i++)
2864 if (range & (1 << i))
2866 (_("Warning: Duplicated register (r%d) in register list"),
2874 if (range & (1 << reg))
2875 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
2877 else if (reg <= cur_reg)
2878 as_tsktsk (_("Warning: Register range not in ascending order"));
2882 } while (skip_past_comma (&str) != FAIL
2883 || (in_range = 1, *str++ == '-'));
2890 inst.error = _("Missing `}'");
2898 if (my_get_expression (&expr, &str))
2901 if (expr.X_op == O_constant)
2903 if (expr.X_add_number
2904 != (expr.X_add_number & 0x0000ffff))
2906 inst.error = _("invalid register mask");
2910 if ((range & expr.X_add_number) != 0)
2912 int regno = range & expr.X_add_number;
2915 regno = (1 << regno) - 1;
2917 (_("Warning: Duplicated register (r%d) in register list"),
2921 range |= expr.X_add_number;
2925 if (inst.reloc.type != 0)
2927 inst.error = _("expression too complex");
2931 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
2932 inst.reloc.type = BFD_RELOC_ARM_MULTI;
2933 inst.reloc.pc_rel = 0;
2940 if (*str == '|' || *str == '+')
2945 } while (another_range);
2952 do_ldmstm (str, flags)
2954 unsigned long flags;
2962 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
2965 inst.error = bad_args;
2969 if (base_reg == REG_PC)
2971 inst.error = _("r15 not allowed as base register");
2979 flags |= WRITE_BACK;
2983 if (skip_past_comma (&str) == FAIL
2984 || (range = reg_list (&str)) == FAIL)
2987 inst.error = bad_args;
2994 flags |= MULTI_SET_PSR;
2997 inst.instruction |= flags | range;
3005 unsigned long flags;
3007 /* Allow optional leading '#'. */
3013 if (my_get_expression (&inst.reloc.exp, &str))
3016 inst.reloc.type = BFD_RELOC_ARM_SWI;
3017 inst.reloc.pc_rel = 0;
3018 inst.instruction |= flags;
3024 do_swap (str, flags)
3026 unsigned long flags;
3033 if ((reg = reg_required_here (&str, 12)) == FAIL)
3038 inst.error = _("r15 not allowed in swap");
3042 if (skip_past_comma (&str) == FAIL
3043 || (reg = reg_required_here (&str, 0)) == FAIL)
3046 inst.error = bad_args;
3052 inst.error = _("r15 not allowed in swap");
3056 if (skip_past_comma (&str) == FAIL
3059 inst.error = bad_args;
3066 if ((reg = reg_required_here (&str, 16)) == FAIL)
3071 inst.error = bad_pc;
3080 inst.error = _("missing ]");
3084 inst.instruction |= flags;
3090 do_branch (str, flags)
3092 unsigned long flags;
3094 if (my_get_expression (&inst.reloc.exp, &str))
3096 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3097 inst.reloc.pc_rel = 1;
3105 unsigned long flags;
3112 if ((reg = reg_required_here (&str, 0)) == FAIL)
3116 as_tsktsk (_("Use of r15 in bx has undefined behaviour"));
3125 unsigned long flags;
3127 /* Co-processor data operation.
3128 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3132 if (co_proc_number (&str) == FAIL)
3135 inst.error = bad_args;
3139 if (skip_past_comma (&str) == FAIL
3140 || cp_opc_expr (&str, 20,4) == FAIL)
3143 inst.error = bad_args;
3147 if (skip_past_comma (&str) == FAIL
3148 || cp_reg_required_here (&str, 12) == FAIL)
3151 inst.error = bad_args;
3155 if (skip_past_comma (&str) == FAIL
3156 || cp_reg_required_here (&str, 16) == FAIL)
3159 inst.error = bad_args;
3163 if (skip_past_comma (&str) == FAIL
3164 || cp_reg_required_here (&str, 0) == FAIL)
3167 inst.error = bad_args;
3171 if (skip_past_comma (&str) == SUCCESS)
3173 if (cp_opc_expr (&str, 5, 3) == FAIL)
3176 inst.error = bad_args;
3186 do_lstc (str, flags)
3188 unsigned long flags;
3190 /* Co-processor register load/store.
3191 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3196 if (co_proc_number (&str) == FAIL)
3199 inst.error = bad_args;
3203 if (skip_past_comma (&str) == FAIL
3204 || cp_reg_required_here (&str, 12) == FAIL)
3207 inst.error = bad_args;
3211 if (skip_past_comma (&str) == FAIL
3212 || cp_address_required_here (&str) == FAIL)
3215 inst.error = bad_args;
3219 inst.instruction |= flags;
3225 do_co_reg (str, flags)
3227 unsigned long flags;
3229 /* Co-processor register transfer.
3230 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3235 if (co_proc_number (&str) == FAIL)
3238 inst.error = bad_args;
3242 if (skip_past_comma (&str) == FAIL
3243 || cp_opc_expr (&str, 21, 3) == FAIL)
3246 inst.error = bad_args;
3250 if (skip_past_comma (&str) == FAIL
3251 || reg_required_here (&str, 12) == FAIL)
3254 inst.error = bad_args;
3258 if (skip_past_comma (&str) == FAIL
3259 || cp_reg_required_here (&str, 16) == FAIL)
3262 inst.error = bad_args;
3266 if (skip_past_comma (&str) == FAIL
3267 || cp_reg_required_here (&str, 0) == FAIL)
3270 inst.error = bad_args;
3274 if (skip_past_comma (&str) == SUCCESS)
3276 if (cp_opc_expr (&str, 5, 3) == FAIL)
3279 inst.error = bad_args;
3289 do_fp_ctrl (str, flags)
3291 unsigned long flags;
3293 /* FP control registers.
3294 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3299 if (reg_required_here (&str, 12) == FAIL)
3302 inst.error = bad_args;
3311 do_fp_ldst (str, flags)
3313 unsigned long flags;
3318 switch (inst.suffix)
3323 inst.instruction |= CP_T_X;
3326 inst.instruction |= CP_T_Y;
3329 inst.instruction |= CP_T_X | CP_T_Y;
3335 if (fp_reg_required_here (&str, 12) == FAIL)
3338 inst.error = bad_args;
3342 if (skip_past_comma (&str) == FAIL
3343 || cp_address_required_here (&str) == FAIL)
3346 inst.error = bad_args;
3354 do_fp_ldmstm (str, flags)
3356 unsigned long flags;
3363 if (fp_reg_required_here (&str, 12) == FAIL)
3366 inst.error = bad_args;
3370 /* Get Number of registers to transfer */
3371 if (skip_past_comma (&str) == FAIL
3372 || my_get_expression (&inst.reloc.exp, &str))
3375 inst.error = _("constant expression expected");
3379 if (inst.reloc.exp.X_op != O_constant)
3381 inst.error = _("Constant value required for number of registers");
3385 num_regs = inst.reloc.exp.X_add_number;
3387 if (num_regs < 1 || num_regs > 4)
3389 inst.error = _("number of registers must be in the range [1:4]");
3396 inst.instruction |= CP_T_X;
3399 inst.instruction |= CP_T_Y;
3402 inst.instruction |= CP_T_Y | CP_T_X;
3416 /* The instruction specified "ea" or "fd", so we can only accept
3417 [Rn]{!}. The instruction does not really support stacking or
3418 unstacking, so we have to emulate these by setting appropriate
3419 bits and offsets. */
3420 if (skip_past_comma (&str) == FAIL
3424 inst.error = bad_args;
3432 if ((reg = reg_required_here (&str, 16)) == FAIL)
3434 inst.error = _("Register required");
3443 inst.error = bad_args;
3454 inst.error = _("R15 not allowed as base register with write-back");
3461 if (flags & CP_T_Pre)
3464 offset = 3 * num_regs;
3470 /* Post-increment */
3474 offset = 3 * num_regs;
3478 /* No write-back, so convert this into a standard pre-increment
3479 instruction -- aesthetically more pleasing. */
3480 flags = CP_T_Pre | CP_T_UD;
3485 inst.instruction |= flags | offset;
3487 else if (skip_past_comma (&str) == FAIL
3488 || cp_address_required_here (&str) == FAIL)
3491 inst.error = bad_args;
3499 do_fp_dyadic (str, flags)
3501 unsigned long flags;
3506 switch (inst.suffix)
3511 inst.instruction |= 0x00000080;
3514 inst.instruction |= 0x00080000;
3520 if (fp_reg_required_here (&str, 12) == FAIL)
3523 inst.error = bad_args;
3527 if (skip_past_comma (&str) == FAIL
3528 || fp_reg_required_here (&str, 16) == FAIL)
3531 inst.error = bad_args;
3535 if (skip_past_comma (&str) == FAIL
3536 || fp_op2 (&str) == FAIL)
3539 inst.error = bad_args;
3543 inst.instruction |= flags;
3549 do_fp_monadic (str, flags)
3551 unsigned long flags;
3556 switch (inst.suffix)
3561 inst.instruction |= 0x00000080;
3564 inst.instruction |= 0x00080000;
3570 if (fp_reg_required_here (&str, 12) == FAIL)
3573 inst.error = bad_args;
3577 if (skip_past_comma (&str) == FAIL
3578 || fp_op2 (&str) == FAIL)
3581 inst.error = bad_args;
3585 inst.instruction |= flags;
3591 do_fp_cmp (str, flags)
3593 unsigned long flags;
3598 if (fp_reg_required_here (&str, 16) == FAIL)
3601 inst.error = bad_args;
3605 if (skip_past_comma (&str) == FAIL
3606 || fp_op2 (&str) == FAIL)
3609 inst.error = bad_args;
3613 inst.instruction |= flags;
3619 do_fp_from_reg (str, flags)
3621 unsigned long flags;
3626 switch (inst.suffix)
3631 inst.instruction |= 0x00000080;
3634 inst.instruction |= 0x00080000;
3640 if (fp_reg_required_here (&str, 16) == FAIL)
3643 inst.error = bad_args;
3647 if (skip_past_comma (&str) == FAIL
3648 || reg_required_here (&str, 12) == FAIL)
3651 inst.error = bad_args;
3655 inst.instruction |= flags;
3661 do_fp_to_reg (str, flags)
3663 unsigned long flags;
3668 if (reg_required_here (&str, 12) == FAIL)
3671 inst.error = bad_args;
3675 if (skip_past_comma (&str) == FAIL
3676 || fp_reg_required_here (&str, 0) == FAIL)
3679 inst.error = bad_args;
3683 inst.instruction |= flags;
3688 /* Thumb specific routines */
3690 /* Parse and validate that a register is of the right form, this saves
3691 repeated checking of this information in many similar cases.
3692 Unlike the 32-bit case we do not insert the register into the opcode
3693 here, since the position is often unknown until the full instruction
3696 thumb_reg (strp, hi_lo)
3702 if ((reg = arm_reg_parse (strp)) == FAIL || ! int_register (reg))
3704 inst.error = _("Register expected");
3713 inst.error = _("lo register required");
3721 inst.error = _("hi register required");
3733 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3736 thumb_add_sub (str, subtract)
3740 int Rd, Rs, Rn = FAIL;
3745 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
3746 || skip_past_comma (&str) == FAIL)
3749 inst.error = bad_args;
3757 if (my_get_expression (&inst.reloc.exp, &str))
3762 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3765 if (skip_past_comma (&str) == FAIL)
3767 /* Two operand format, shuffle the registers and pretend there
3772 else if (*str == '#')
3775 if (my_get_expression (&inst.reloc.exp, &str))
3778 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3782 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
3783 for the latter case, EXPR contains the immediate that was found. */
3786 /* All register format. */
3787 if (Rd > 7 || Rs > 7 || Rn > 7)
3791 inst.error = _("dest and source1 must be the same register");
3795 /* Can't do this for SUB */
3798 inst.error = _("subtract valid only on lo regs");
3802 inst.instruction = (T_OPCODE_ADD_HI
3803 | (Rd > 7 ? THUMB_H1 : 0)
3804 | (Rn > 7 ? THUMB_H2 : 0));
3805 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
3809 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
3810 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
3815 /* Immediate expression, now things start to get nasty. */
3817 /* First deal with HI regs, only very restricted cases allowed:
3818 Adjusting SP, and using PC or SP to get an address. */
3819 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
3820 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
3822 inst.error = _("invalid Hi register with immediate");
3826 if (inst.reloc.exp.X_op != O_constant)
3828 /* Value isn't known yet, all we can do is store all the fragments
3829 we know about in the instruction and let the reloc hacking
3831 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
3832 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
3836 int offset = inst.reloc.exp.X_add_number;
3846 /* Quick check, in case offset is MIN_INT */
3849 inst.error = _("immediate value out of range");
3858 if (offset & ~0x1fc)
3860 inst.error = _("invalid immediate value for stack adjust");
3863 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
3864 inst.instruction |= offset >> 2;
3866 else if (Rs == REG_PC || Rs == REG_SP)
3869 || (offset & ~0x3fc))
3871 inst.error = _("invalid immediate for address calculation");
3874 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
3876 inst.instruction |= (Rd << 8) | (offset >> 2);
3882 inst.error = _("immediate value out of range");
3885 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
3886 inst.instruction |= (Rd << 8) | offset;
3892 inst.error = _("immediate value out of range");
3895 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
3896 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
3904 thumb_shift (str, shift)
3908 int Rd, Rs, Rn = FAIL;
3913 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
3914 || skip_past_comma (&str) == FAIL)
3917 inst.error = bad_args;
3923 /* Two operand immediate format, set Rs to Rd. */
3926 if (my_get_expression (&inst.reloc.exp, &str))
3931 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
3934 if (skip_past_comma (&str) == FAIL)
3936 /* Two operand format, shuffle the registers and pretend there
3941 else if (*str == '#')
3944 if (my_get_expression (&inst.reloc.exp, &str))
3947 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
3951 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
3952 for the latter case, EXPR contains the immediate that was found. */
3958 inst.error = _("source1 and dest must be same register");
3964 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
3965 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
3966 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
3969 inst.instruction |= Rd | (Rn << 3);
3975 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
3976 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
3977 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
3980 if (inst.reloc.exp.X_op != O_constant)
3982 /* Value isn't known yet, create a dummy reloc and let reloc
3983 hacking fix it up */
3985 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
3989 unsigned shift_value = inst.reloc.exp.X_add_number;
3991 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
3993 inst.error = _("Invalid immediate for shift");
3997 /* Shifts of zero are handled by converting to LSL */
3998 if (shift_value == 0)
3999 inst.instruction = T_OPCODE_LSL_I;
4001 /* Shifts of 32 are encoded as a shift of zero */
4002 if (shift_value == 32)
4005 inst.instruction |= shift_value << 6;
4008 inst.instruction |= Rd | (Rs << 3);
4014 thumb_mov_compare (str, move)
4023 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4024 || skip_past_comma (&str) == FAIL)
4027 inst.error = bad_args;
4034 if (my_get_expression (&inst.reloc.exp, &str))
4037 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4042 if (Rs < 8 && Rd < 8)
4044 if (move == THUMB_MOVE)
4045 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4046 since a MOV instruction produces unpredictable results */
4047 inst.instruction = T_OPCODE_ADD_I3;
4049 inst.instruction = T_OPCODE_CMP_LR;
4050 inst.instruction |= Rd | (Rs << 3);
4054 if (move == THUMB_MOVE)
4055 inst.instruction = T_OPCODE_MOV_HR;
4057 inst.instruction = T_OPCODE_CMP_HR;
4060 inst.instruction |= THUMB_H1;
4063 inst.instruction |= THUMB_H2;
4065 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4072 inst.error = _("only lo regs allowed with immediate");
4076 if (move == THUMB_MOVE)
4077 inst.instruction = T_OPCODE_MOV_I8;
4079 inst.instruction = T_OPCODE_CMP_I8;
4081 inst.instruction |= Rd << 8;
4083 if (inst.reloc.exp.X_op != O_constant)
4084 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4087 unsigned value = inst.reloc.exp.X_add_number;
4091 inst.error = _("invalid immediate");
4095 inst.instruction |= value;
4103 thumb_load_store (str, load_store, size)
4108 int Rd, Rb, Ro = FAIL;
4113 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4114 || skip_past_comma (&str) == FAIL)
4117 inst.error = bad_args;
4124 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4127 if (skip_past_comma (&str) != FAIL)
4132 if (my_get_expression (&inst.reloc.exp, &str))
4135 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4140 inst.reloc.exp.X_op = O_constant;
4141 inst.reloc.exp.X_add_number = 0;
4146 inst.error = _("expected ']'");
4151 else if (*str == '=')
4153 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4159 if (my_get_expression (& inst.reloc.exp, & str))
4164 if ( inst.reloc.exp.X_op != O_constant
4165 && inst.reloc.exp.X_op != O_symbol)
4167 inst.error = "Constant expression expected";
4171 if (inst.reloc.exp.X_op == O_constant
4172 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4174 /* This can be done with a mov instruction */
4176 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4177 inst.instruction |= inst.reloc.exp.X_add_number;
4181 /* Insert into literal pool */
4182 if (add_to_lit_pool () == FAIL)
4185 inst.error = "literal pool insertion failed";
4189 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4190 inst.reloc.pc_rel = 1;
4191 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4192 inst.reloc.exp.X_add_number += 4; /* Adjust ARM pipeline offset to Thumb */
4198 if (my_get_expression (&inst.reloc.exp, &str))
4201 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4202 inst.reloc.pc_rel = 1;
4203 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset */
4204 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4209 if (Rb == REG_PC || Rb == REG_SP)
4211 if (size != THUMB_WORD)
4213 inst.error = _("byte or halfword not valid for base register");
4216 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4218 inst.error = _("R15 based store not allowed");
4221 else if (Ro != FAIL)
4223 inst.error = _("Invalid base register for register offset");
4228 inst.instruction = T_OPCODE_LDR_PC;
4229 else if (load_store == THUMB_LOAD)
4230 inst.instruction = T_OPCODE_LDR_SP;
4232 inst.instruction = T_OPCODE_STR_SP;
4234 inst.instruction |= Rd << 8;
4235 if (inst.reloc.exp.X_op == O_constant)
4237 unsigned offset = inst.reloc.exp.X_add_number;
4239 if (offset & ~0x3fc)
4241 inst.error = _("invalid offset");
4245 inst.instruction |= offset >> 2;
4248 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4252 inst.error = _("invalid base register in load/store");
4255 else if (Ro == FAIL)
4257 /* Immediate offset */
4258 if (size == THUMB_WORD)
4259 inst.instruction = (load_store == THUMB_LOAD
4260 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4261 else if (size == THUMB_HALFWORD)
4262 inst.instruction = (load_store == THUMB_LOAD
4263 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4265 inst.instruction = (load_store == THUMB_LOAD
4266 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4268 inst.instruction |= Rd | (Rb << 3);
4270 if (inst.reloc.exp.X_op == O_constant)
4272 unsigned offset = inst.reloc.exp.X_add_number;
4274 if (offset & ~(0x1f << size))
4276 inst.error = _("Invalid offset");
4279 inst.instruction |= (offset >> size) << 6;
4282 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4286 /* Register offset */
4287 if (size == THUMB_WORD)
4288 inst.instruction = (load_store == THUMB_LOAD
4289 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4290 else if (size == THUMB_HALFWORD)
4291 inst.instruction = (load_store == THUMB_LOAD
4292 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4294 inst.instruction = (load_store == THUMB_LOAD
4295 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4297 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4312 /* Handle the Format 4 instructions that do not have equivalents in other
4313 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4324 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4327 if (skip_past_comma (&str) == FAIL
4328 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4331 inst.error = bad_args;
4335 if (skip_past_comma (&str) != FAIL)
4337 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4338 (It isn't allowed for CMP either, but that isn't handled by this
4340 if (inst.instruction == T_OPCODE_TST
4341 || inst.instruction == T_OPCODE_CMN
4342 || inst.instruction == T_OPCODE_NEG
4343 || inst.instruction == T_OPCODE_MVN)
4345 inst.error = bad_args;
4349 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4354 inst.error = _("dest and source1 one must be the same register");
4360 if (inst.instruction == T_OPCODE_MUL
4362 as_tsktsk (_("Rs and Rd must be different in MUL"));
4364 inst.instruction |= Rd | (Rs << 3);
4372 thumb_add_sub (str, 0);
4379 thumb_shift (str, THUMB_ASR);
4386 if (my_get_expression (&inst.reloc.exp, &str))
4388 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4389 inst.reloc.pc_rel = 1;
4397 if (my_get_expression (&inst.reloc.exp, &str))
4399 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4400 inst.reloc.pc_rel = 1;
4404 /* Find the real, Thumb encoded start of a Thumb function. */
4407 find_real_start (symbolP)
4411 const char * name = S_GET_NAME (symbolP);
4412 symbolS * new_target;
4414 /* This definitonmust agree with the one in gcc/config/arm/thumb.c */
4415 #define STUB_NAME ".real_start_of"
4420 /* Names that start with '.' are local labels, not function entry points.
4421 The compiler may generate BL instructions to these labels because it
4422 needs to perform a branch to a far away location. */
4426 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4427 sprintf (real_start, "%s%s", STUB_NAME, name);
4429 new_target = symbol_find (real_start);
4431 if (new_target == NULL)
4433 as_warn ("Failed to find real start of function: %s\n", name);
4434 new_target = symbolP;
4447 if (my_get_expression (&inst.reloc.exp, &str))
4449 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4450 inst.reloc.pc_rel = 1;
4453 /* If the destination of the branch is a defined symbol which does not have
4454 the THUMB_FUNC attribute, then we must be calling a function which has
4455 the (interfacearm) attribute. We look for the Thumb entry point to that
4456 function and change the branch to refer to that function instead. */
4457 if ( inst.reloc.exp.X_op == O_symbol
4458 && inst.reloc.exp.X_add_symbol != NULL
4459 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4460 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4461 inst.reloc.exp.X_add_symbol = find_real_start (inst.reloc.exp.X_add_symbol);
4473 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4476 /* This sets THUMB_H2 from the top bit of reg. */
4477 inst.instruction |= reg << 3;
4479 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4480 should cause the alignment to be checked once it is known. This is
4481 because BX PC only works if the instruction is word aligned. */
4490 thumb_mov_compare (str, THUMB_COMPARE);
4503 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4507 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4511 if (skip_past_comma (&str) == FAIL
4512 || (range = reg_list (&str)) == FAIL)
4515 inst.error = bad_args;
4519 if (inst.reloc.type != BFD_RELOC_NONE)
4521 /* This really doesn't seem worth it. */
4522 inst.reloc.type = BFD_RELOC_NONE;
4523 inst.error = _("Expression too complex");
4529 inst.error = _("only lo-regs valid in load/store multiple");
4533 inst.instruction |= (Rb << 8) | range;
4541 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4548 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
4555 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
4567 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4568 || skip_past_comma (&str) == FAIL
4570 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4571 || skip_past_comma (&str) == FAIL
4572 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4576 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4580 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4588 thumb_shift (str, THUMB_LSL);
4595 thumb_shift (str, THUMB_LSR);
4602 thumb_mov_compare (str, THUMB_MOVE);
4614 if ((range = reg_list (&str)) == FAIL)
4617 inst.error = bad_args;
4621 if (inst.reloc.type != BFD_RELOC_NONE)
4623 /* This really doesn't seem worth it. */
4624 inst.reloc.type = BFD_RELOC_NONE;
4625 inst.error = _("Expression too complex");
4631 if ((inst.instruction == T_OPCODE_PUSH
4632 && (range & ~0xff) == 1 << REG_LR)
4633 || (inst.instruction == T_OPCODE_POP
4634 && (range & ~0xff) == 1 << REG_PC))
4636 inst.instruction |= THUMB_PP_PC_LR;
4641 inst.error = _("invalid register list to push/pop instruction");
4646 inst.instruction |= range;
4654 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
4661 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
4668 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
4675 thumb_add_sub (str, 1);
4685 if (my_get_expression (&inst.reloc.exp, &str))
4688 inst.reloc.type = BFD_RELOC_ARM_SWI;
4697 /* This is a pseudo-op of the form "adr rd, label" to be converted
4698 into a relative address of the form "add rd, pc, #label-.-4" */
4702 if (reg_required_here (&str, 4) == FAIL /* Store Rd in temporary location inside instruction. */
4703 || skip_past_comma (&str) == FAIL
4704 || my_get_expression (&inst.reloc.exp, &str))
4707 inst.error = bad_args;
4711 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4712 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust */
4713 inst.reloc.pc_rel = 1;
4714 inst.instruction |= REG_PC; /* Rd is already placed into the instruction */
4722 int len = strlen (reg_table[entry].name) + 2;
4723 char *buf = (char *) xmalloc (len);
4724 char *buf2 = (char *) xmalloc (len);
4727 #ifdef REGISTER_PREFIX
4728 buf[i++] = REGISTER_PREFIX;
4731 strcpy (buf + i, reg_table[entry].name);
4733 for (i = 0; buf[i]; i++)
4734 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
4738 hash_insert (arm_reg_hsh, buf, (PTR) ®_table[entry]);
4739 hash_insert (arm_reg_hsh, buf2, (PTR) ®_table[entry]);
4743 insert_reg_alias (str, regnum)
4747 struct reg_entry *new =
4748 (struct reg_entry *)xmalloc (sizeof (struct reg_entry));
4749 char *name = xmalloc (strlen (str) + 1);
4753 new->number = regnum;
4755 hash_insert (arm_reg_hsh, name, (PTR) new);
4759 set_constant_flonums ()
4763 for (i = 0; i < NUM_FLOAT_VALS; i++)
4764 if (atof_ieee ((char *)fp_const[i], 'x', fp_values[i]) == NULL)
4773 if ((arm_ops_hsh = hash_new ()) == NULL
4774 || (arm_tops_hsh = hash_new ()) == NULL
4775 || (arm_cond_hsh = hash_new ()) == NULL
4776 || (arm_shift_hsh = hash_new ()) == NULL
4777 || (arm_reg_hsh = hash_new ()) == NULL
4778 || (arm_psr_hsh = hash_new ()) == NULL)
4779 as_fatal (_("Virtual memory exhausted"));
4781 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
4782 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
4783 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
4784 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
4785 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
4786 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
4787 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
4788 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
4789 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
4790 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
4792 for (i = 0; reg_table[i].name; i++)
4795 set_constant_flonums ();
4797 #if defined OBJ_COFF || defined OBJ_ELF
4799 unsigned int flags = 0;
4801 /* Set the flags in the private structure */
4802 if (uses_apcs_26) flags |= F_APCS26;
4803 if (support_interwork) flags |= F_INTERWORK;
4804 if (uses_apcs_float) flags |= F_APCS_FLOAT;
4805 if (pic_code) flags |= F_PIC;
4807 bfd_set_private_flags (stdoutput, flags);
4814 /* Record the CPU type as well */
4815 switch (cpu_variant & ARM_CPU_MASK)
4818 mach = bfd_mach_arm_2;
4821 case ARM_3: /* also ARM_250 */
4822 mach = bfd_mach_arm_2a;
4826 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined */
4827 mach = bfd_mach_arm_4;
4830 case ARM_7: /* also ARM_6 */
4831 mach = bfd_mach_arm_3;
4835 /* Catch special cases */
4836 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
4838 if (cpu_variant & ARM_THUMB)
4839 mach = bfd_mach_arm_4T;
4840 else if ((cpu_variant & ARM_ARCHv4) == ARM_ARCHv4)
4841 mach = bfd_mach_arm_4;
4842 else if (cpu_variant & ARM_LONGMUL)
4843 mach = bfd_mach_arm_3M;
4846 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
4850 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
4851 for use in the a.out file, and stores them in the array pointed to by buf.
4852 This knows about the endian-ness of the target machine and does
4853 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
4854 2 (short) and 4 (long) Floating numbers are put out as a series of
4855 LITTLENUMS (shorts, here at least)
4858 md_number_to_chars (buf, val, n)
4863 if (target_big_endian)
4864 number_to_chars_bigendian (buf, val, n);
4866 number_to_chars_littleendian (buf, val, n);
4870 md_chars_to_number (buf, n)
4875 unsigned char *where = (unsigned char *) buf;
4877 if (target_big_endian)
4882 result |= (*where++ & 255);
4890 result |= (where[n] & 255);
4897 /* Turn a string in input_line_pointer into a floating point constant
4898 of type TYPE, and store the appropriate bytes in *litP. The number
4899 of LITTLENUMS emitted is stored in *sizeP . An error message is
4900 returned, or NULL on OK.
4902 Note that fp constants aren't represent in the normal way on the ARM.
4903 In big endian mode, things are as expected. However, in little endian
4904 mode fp constants are big-endian word-wise, and little-endian byte-wise
4905 within the words. For example, (double) 1.1 in big endian mode is
4906 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
4907 the byte sequence 99 99 f1 3f 9a 99 99 99.
4909 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
4912 md_atof (type, litP, sizeP)
4918 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4950 return _("Bad call to MD_ATOF()");
4953 t = atof_ieee (input_line_pointer, type, words);
4955 input_line_pointer = t;
4958 if (target_big_endian)
4960 for (i = 0; i < prec; i++)
4962 md_number_to_chars (litP, (valueT) words[i], 2);
4968 /* For a 4 byte float the order of elements in `words' is 1 0. For an
4969 8 byte float the order is 1 0 3 2. */
4970 for (i = 0; i < prec; i += 2)
4972 md_number_to_chars (litP, (valueT) words[i + 1], 2);
4973 md_number_to_chars (litP + 2, (valueT) words[i], 2);
4981 /* We have already put the pipeline compensation in the instruction */
4984 md_pcrel_from (fixP)
4988 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
4989 && fixP->fx_subsy == NULL)
4990 return 0; /* HACK */
4992 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
4994 /* PC relative addressing on the Thumb is slightly odd
4995 as the bottom two bits of the PC are forced to zero
4996 for the calculation */
4997 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5000 return fixP->fx_where + fixP->fx_frag->fr_address;
5003 /* Round up a section size to the appropriate boundary. */
5005 md_section_align (segment, size)
5009 /* start-sanitize-armelf */
5011 /* Don't align the dwarf2 debug sections */
5012 if (!strncmp(segment->name,".debug",5))
5015 /* end-sanitize-armelf */
5016 /* Round all sects to multiple of 4 */
5017 return (size + 3) & ~3;
5020 /* We have no need to default values of symbols. */
5024 md_undefined_symbol (name)
5030 /* arm_reg_parse () := if it looks like a register, return its token and
5031 advance the pointer. */
5035 register char **ccp;
5040 struct reg_entry *reg;
5042 #ifdef REGISTER_PREFIX
5043 if (*start != REGISTER_PREFIX)
5048 #ifdef OPTIONAL_REGISTER_PREFIX
5049 if (*p == OPTIONAL_REGISTER_PREFIX)
5053 if (!isalpha (*p) || !is_name_beginner (*p))
5057 while (isalpha (c) || isdigit (c) || c == '_')
5061 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5075 register char **ccp;
5079 CONST struct asm_psr *psr;
5083 while (isalpha (c) || c == '_')
5087 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
5100 md_apply_fix3 (fixP, val, seg)
5105 offsetT value = *val;
5107 unsigned int newimm;
5110 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5111 arm_fix_data *arm_data = (arm_fix_data *) fixP->tc_fix_data;
5113 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5115 /* Note whether this will delete the relocation. */
5116 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5117 if ((fixP->fx_addsy == 0 || fixP->fx_addsy->sy_value.X_op == O_constant)
5120 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5124 /* If this symbol is in a different section then we need to leave it for
5125 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5126 so we have to undo it's effects here. */
5129 if (fixP->fx_addsy != NULL
5130 && S_IS_DEFINED (fixP->fx_addsy)
5131 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5133 if (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH)
5136 value += md_pcrel_from (fixP);
5140 fixP->fx_addnumber = value; /* Remember value for emit_reloc */
5142 switch (fixP->fx_r_type)
5144 case BFD_RELOC_ARM_IMMEDIATE:
5145 newimm = validate_immediate (value);
5146 temp = md_chars_to_number (buf, INSN_SIZE);
5148 /* If the instruction will fail, see if we can fix things up by
5149 changing the opcode. */
5150 if (newimm == (unsigned int) FAIL
5151 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5153 as_bad_where (fixP->fx_file, fixP->fx_line,
5154 _("invalid constant after fixup\n"));
5158 newimm |= (temp & 0xfffff000);
5159 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5162 case BFD_RELOC_ARM_OFFSET_IMM:
5164 if ((value = validate_offset_imm (value, 0)) == FAIL)
5166 as_bad (_("bad immediate value for offset (%d)"), val);
5172 newval = md_chars_to_number (buf, INSN_SIZE);
5173 newval &= 0xff7ff000;
5174 newval |= value | (sign ? INDEX_UP : 0);
5175 md_number_to_chars (buf, newval, INSN_SIZE);
5178 case BFD_RELOC_ARM_OFFSET_IMM8:
5179 case BFD_RELOC_ARM_HWLITERAL:
5181 if ((value = validate_offset_imm (value, 1)) == FAIL)
5183 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5184 as_bad_where (fixP->fx_file, fixP->fx_line,
5185 _("invalid literal constant: pool needs to be closer\n"));
5187 as_bad (_("bad immediate value for offset (%d)"), value);
5194 newval = md_chars_to_number (buf, INSN_SIZE);
5195 newval &= 0xff7ff0f0;
5196 newval |= ((value >> 4) << 8) | value & 0xf | (sign ? INDEX_UP : 0);
5197 md_number_to_chars (buf, newval, INSN_SIZE);
5200 case BFD_RELOC_ARM_LITERAL:
5205 if ((value = validate_offset_imm (value, 0)) == FAIL)
5207 as_bad_where (fixP->fx_file, fixP->fx_line,
5208 _("invalid literal constant: pool needs to be closer\n"));
5212 newval = md_chars_to_number (buf, INSN_SIZE);
5213 newval &= 0xff7ff000;
5214 newval |= value | (sign ? INDEX_UP : 0);
5215 md_number_to_chars (buf, newval, INSN_SIZE);
5218 case BFD_RELOC_ARM_SHIFT_IMM:
5219 newval = md_chars_to_number (buf, INSN_SIZE);
5220 if (((unsigned long) value) > 32
5222 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5224 as_bad_where (fixP->fx_file, fixP->fx_line,
5225 _("shift expression is too large"));
5230 newval &= ~0x60; /* Shifts of zero must be done as lsl */
5231 else if (value == 32)
5233 newval &= 0xfffff07f;
5234 newval |= (value & 0x1f) << 7;
5235 md_number_to_chars (buf, newval , INSN_SIZE);
5238 case BFD_RELOC_ARM_SWI:
5239 if (arm_data->thumb_mode)
5241 if (((unsigned long) value) > 0xff)
5242 as_bad_where (fixP->fx_file, fixP->fx_line,
5243 _("Invalid swi expression"));
5244 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5246 md_number_to_chars (buf, newval, THUMB_SIZE);
5250 if (((unsigned long) value) > 0x00ffffff)
5251 as_bad_where (fixP->fx_file, fixP->fx_line,
5252 _("Invalid swi expression"));
5253 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5255 md_number_to_chars (buf, newval , INSN_SIZE);
5259 case BFD_RELOC_ARM_MULTI:
5260 if (((unsigned long) value) > 0xffff)
5261 as_bad_where (fixP->fx_file, fixP->fx_line,
5262 _("Invalid expression in load/store multiple"));
5263 newval = value | md_chars_to_number (buf, INSN_SIZE);
5264 md_number_to_chars (buf, newval, INSN_SIZE);
5267 case BFD_RELOC_ARM_PCREL_BRANCH:
5268 value = (value >> 2) & 0x00ffffff;
5269 newval = md_chars_to_number (buf, INSN_SIZE);
5270 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5271 newval = value | (newval & 0xff000000);
5272 md_number_to_chars (buf, newval, INSN_SIZE);
5275 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
5276 newval = md_chars_to_number (buf, THUMB_SIZE);
5278 addressT diff = (newval & 0xff) << 1;
5283 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5284 as_bad_where (fixP->fx_file, fixP->fx_line,
5285 _("Branch out of range"));
5286 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5288 md_number_to_chars (buf, newval, THUMB_SIZE);
5291 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* unconditional branch */
5292 newval = md_chars_to_number (buf, THUMB_SIZE);
5294 addressT diff = (newval & 0x7ff) << 1;
5299 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5300 as_bad_where (fixP->fx_file, fixP->fx_line,
5301 _("Branch out of range"));
5302 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5304 md_number_to_chars (buf, newval, THUMB_SIZE);
5307 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5312 newval = md_chars_to_number (buf, THUMB_SIZE);
5313 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5314 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5315 if (diff & 0x400000)
5318 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5319 as_bad_where (fixP->fx_file, fixP->fx_line,
5320 _("Branch with link out of range"));
5322 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5323 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5324 md_number_to_chars (buf, newval, THUMB_SIZE);
5325 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5330 if (fixP->fx_done || fixP->fx_pcrel)
5331 md_number_to_chars (buf, value, 1);
5335 if (fixP->fx_done || fixP->fx_pcrel)
5336 md_number_to_chars (buf, value, 2);
5341 if (fixP->fx_done || fixP->fx_pcrel)
5342 md_number_to_chars (buf, value, 4);
5345 case BFD_RELOC_ARM_CP_OFF_IMM:
5347 if (value < -1023 || value > 1023 || (value & 3))
5348 as_bad_where (fixP->fx_file, fixP->fx_line,
5349 _("Illegal value for co-processor offset"));
5352 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5353 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5354 md_number_to_chars (buf, newval , INSN_SIZE);
5357 case BFD_RELOC_ARM_THUMB_OFFSET:
5358 newval = md_chars_to_number (buf, THUMB_SIZE);
5359 /* Exactly what ranges, and where the offset is inserted depends on
5360 the type of instruction, we can establish this from the top 4 bits */
5361 switch (newval >> 12)
5363 case 4: /* PC load */
5364 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5365 forced to zero for these loads, so we will need to round
5366 up the offset if the instruction address is not word
5367 aligned (since the final address produced must be, and
5368 we can only describe word-aligned immediate offsets). */
5370 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
5371 as_bad_where (fixP->fx_file, fixP->fx_line,
5372 _("Invalid offset, target not word aligned (0x%08X)"),
5373 (unsigned int)(fixP->fx_frag->fr_address + fixP->fx_where + value));
5375 if ((value + 2) & ~0x3fe)
5376 as_bad_where (fixP->fx_file, fixP->fx_line,
5377 _("Invalid offset"));
5379 /* Round up, since pc will be rounded down. */
5380 newval |= (value + 2) >> 2;
5383 case 9: /* SP load/store */
5385 as_bad_where (fixP->fx_file, fixP->fx_line,
5386 _("Invalid offset"));
5387 newval |= value >> 2;
5390 case 6: /* Word load/store */
5392 as_bad_where (fixP->fx_file, fixP->fx_line,
5393 _("Invalid offset"));
5394 newval |= value << 4; /* 6 - 2 */
5397 case 7: /* Byte load/store */
5399 as_bad_where (fixP->fx_file, fixP->fx_line,
5400 _("Invalid offset"));
5401 newval |= value << 6;
5404 case 8: /* Halfword load/store */
5406 as_bad_where (fixP->fx_file, fixP->fx_line,
5407 _("Invalid offset"));
5408 newval |= value << 5; /* 6 - 1 */
5412 as_bad_where (fixP->fx_file, fixP->fx_line,
5413 "Unable to process relocation for thumb opcode: %x", newval);
5416 md_number_to_chars (buf, newval, THUMB_SIZE);
5419 case BFD_RELOC_ARM_THUMB_ADD:
5420 /* This is a complicated relocation, since we use it for all of
5421 the following immediate relocations:
5424 9bit ADD/SUB SP word-aligned
5425 10bit ADD PC/SP word-aligned
5427 The type of instruction being processed is encoded in the
5433 newval = md_chars_to_number (buf, THUMB_SIZE);
5435 int rd = (newval >> 4) & 0xf;
5436 int rs = newval & 0xf;
5437 int subtract = newval & 0x8000;
5442 as_bad_where (fixP->fx_file, fixP->fx_line,
5443 _("Invalid immediate for stack address calculation"));
5444 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5445 newval |= value >> 2;
5447 else if (rs == REG_PC || rs == REG_SP)
5451 as_bad_where (fixP->fx_file, fixP->fx_line,
5452 _("Invalid immediate for address calculation (value = 0x%08X)"), value);
5453 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
5455 newval |= value >> 2;
5460 as_bad_where (fixP->fx_file, fixP->fx_line,
5461 _("Invalid 8bit immediate"));
5462 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5463 newval |= (rd << 8) | value;
5468 as_bad_where (fixP->fx_file, fixP->fx_line,
5469 _("Invalid 3bit immediate"));
5470 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5471 newval |= rd | (rs << 3) | (value << 6);
5474 md_number_to_chars (buf, newval , THUMB_SIZE);
5477 case BFD_RELOC_ARM_THUMB_IMM:
5478 newval = md_chars_to_number (buf, THUMB_SIZE);
5479 switch (newval >> 11)
5481 case 0x04: /* 8bit immediate MOV */
5482 case 0x05: /* 8bit immediate CMP */
5483 if (value < 0 || value > 255)
5484 as_bad_where (fixP->fx_file, fixP->fx_line,
5485 _("Invalid immediate: %d is too large"), value);
5492 md_number_to_chars (buf, newval , THUMB_SIZE);
5495 case BFD_RELOC_ARM_THUMB_SHIFT:
5496 /* 5bit shift value (0..31) */
5497 if (value < 0 || value > 31)
5498 as_bad_where (fixP->fx_file, fixP->fx_line,
5499 _("Illegal Thumb shift value: %d"), value);
5500 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
5501 newval |= value << 6;
5502 md_number_to_chars (buf, newval , THUMB_SIZE);
5505 case BFD_RELOC_NONE:
5507 as_bad_where (fixP->fx_file, fixP->fx_line,
5508 _("Bad relocation fixup type (%d)\n"), fixP->fx_r_type);
5514 /* Translate internal representation of relocation info to BFD target
5517 tc_gen_reloc (section, fixp)
5522 bfd_reloc_code_real_type code;
5524 reloc = (arelent *) xmalloc (sizeof (arelent));
5526 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
5527 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5529 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5531 if (fixp->fx_pcrel == 0)
5532 reloc->addend = fixp->fx_offset;
5534 reloc->addend = fixp->fx_offset = reloc->address;
5536 reloc->addend = fixp->fx_offset;
5539 switch (fixp->fx_r_type)
5544 code = BFD_RELOC_8_PCREL;
5551 code = BFD_RELOC_16_PCREL;
5558 code = BFD_RELOC_32_PCREL;
5562 case BFD_RELOC_ARM_PCREL_BRANCH:
5564 case BFD_RELOC_THUMB_PCREL_BRANCH9:
5565 case BFD_RELOC_THUMB_PCREL_BRANCH12:
5566 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5567 code = fixp->fx_r_type;
5570 case BFD_RELOC_ARM_LITERAL:
5571 case BFD_RELOC_ARM_HWLITERAL:
5572 /* If this is called then the a literal has been referenced across
5573 a section boundry - possibly due to an implicit dump */
5574 as_bad_where (fixp->fx_file, fixp->fx_line,
5575 _("Literal referenced across section boundry (Implicit dump?)"));
5578 case BFD_RELOC_ARM_IMMEDIATE:
5579 as_bad_where (fixp->fx_file, fixp->fx_line,
5580 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
5584 case BFD_RELOC_ARM_OFFSET_IMM:
5585 as_bad_where (fixp->fx_file, fixp->fx_line,
5586 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
5593 switch (fixp->fx_r_type)
5595 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
5596 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
5597 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
5598 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
5599 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
5600 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
5601 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
5602 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
5603 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
5604 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
5605 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
5606 default: type = "<unknown>"; break;
5608 as_bad_where (fixp->fx_file, fixp->fx_line,
5609 _("Can not represent %s relocation in this object file format (%d)"),
5610 type, fixp->fx_pcrel);
5615 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
5617 if (reloc->howto == NULL)
5619 as_bad_where (fixp->fx_file, fixp->fx_line,
5620 _("Can not represent %s relocation in this object file format"),
5621 bfd_get_reloc_code_name (code));
5629 md_estimate_size_before_relax (fragP, segtype)
5633 as_fatal (_("md_estimate_size_before_relax\n"));
5645 as_bad (inst.error);
5649 to = frag_more (inst.size);
5650 if (thumb_mode && (inst.size > THUMB_SIZE))
5652 assert (inst.size == (2 * THUMB_SIZE));
5653 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
5654 md_number_to_chars (to + 2, inst.instruction, THUMB_SIZE);
5657 md_number_to_chars (to, inst.instruction, inst.size);
5659 if (inst.reloc.type != BFD_RELOC_NONE)
5660 fix_new_arm (frag_now, to - frag_now->fr_literal,
5661 inst.size, &inst.reloc.exp, inst.reloc.pc_rel,
5672 char *p, *q, *start;
5674 /* Align the instruction */
5675 /* this may not be the right thing to do but ... */
5676 /* arm_align (2, 0); */
5677 listing_prev_line (); /* Defined in listing.h */
5679 /* Align the previous label if needed */
5680 if (last_label_seen != NULL)
5682 last_label_seen->sy_frag = frag_now;
5683 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
5684 S_SET_SEGMENT (last_label_seen, now_seg);
5687 memset (&inst, '\0', sizeof (inst));
5688 inst.reloc.type = BFD_RELOC_NONE;
5691 str++; /* Skip leading white space */
5693 /* scan up to the end of the op-code, which must end in white space or
5695 for (start = p = str; *p != '\0'; p++)
5701 as_bad (_("No operator -- statement `%s'\n"), str);
5707 CONST struct thumb_opcode *opcode;
5711 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
5715 inst.instruction = opcode->value;
5716 inst.size = opcode->size;
5717 (*opcode->parms)(p);
5718 output_inst (start);
5724 CONST struct asm_opcode *opcode;
5726 inst.size = INSN_SIZE;
5727 /* p now points to the end of the opcode, probably white space, but we
5728 have to break the opcode up in case it contains condionals and flags;
5729 keep trying with progressively smaller basic instructions until one
5730 matches, or we run out of opcode. */
5731 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
5732 for (; q != str; q--)
5736 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
5738 if (opcode && opcode->template)
5740 unsigned long flag_bits = 0;
5743 /* Check that this instruction is supported for this CPU */
5744 if ((opcode->variants & cpu_variant) == 0)
5747 inst.instruction = opcode->value;
5748 if (q == p) /* Just a simple opcode */
5750 if (opcode->comp_suffix != 0)
5751 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
5752 opcode->comp_suffix);
5755 inst.instruction |= COND_ALWAYS;
5756 (*opcode->parms)(q, 0);
5758 output_inst (start);
5762 /* Now check for a conditional */
5766 CONST struct asm_cond *cond;
5770 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
5774 if (cond->value == 0xf0000000)
5776 _("Warning: Use of the 'nv' conditional is deprecated\n"));
5778 inst.instruction |= cond->value;
5782 inst.instruction |= COND_ALWAYS;
5785 inst.instruction |= COND_ALWAYS;
5787 /* if there is a compulsory suffix, it should come here, before
5788 any optional flags. */
5789 if (opcode->comp_suffix)
5791 CONST char *s = opcode->comp_suffix;
5803 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
5804 opcode->comp_suffix);
5811 /* The remainder, if any should now be flags for the instruction;
5812 Scan these checking each one found with the opcode. */
5816 CONST struct asm_flg *flag = opcode->flags;
5825 for (flagno = 0; flag[flagno].template; flagno++)
5827 if (! strcmp (r, flag[flagno].template))
5829 flag_bits |= flag[flagno].set_bits;
5835 if (! flag[flagno].template)
5842 (*opcode->parms) (p, flag_bits);
5843 output_inst (start);
5852 /* It wasn't an instruction, but it might be a register alias of the form
5862 if (*q && !strncmp (q, ".req ", 4))
5865 char * copy_of_str = str;
5872 for (r = q; *r != '\0'; r++)
5882 regnum = arm_reg_parse (& q);
5885 reg = arm_reg_parse (& str);
5891 insert_reg_alias (str, regnum);
5895 as_warn (_("register '%s' does not exist\n"), q);
5898 else if (regnum != FAIL)
5901 as_warn (_("ignoring redefinition of register alias '%s'"), copy_of_str );
5903 /* Do not warn abpout redefinitions to the same alias. */
5906 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
5910 as_warn (_("ignoring incomplete .req pseuso op"));
5917 as_bad (_("bad instruction `%s'"), start);
5922 * Invocation line includes a switch not recognized by the base assembler.
5923 * See if it's a processor-specific option. These are:
5924 * Cpu variants, the arm part is optional:
5925 * -m[arm]1 Currently not supported.
5926 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
5927 * -m[arm]3 Arm 3 processor
5928 * -m[arm]6, Arm 6 processors
5929 * -m[arm]7[t][[d]m] Arm 7 processors
5930 * -mall All (except the ARM1)
5932 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
5933 * -mfpe-old (No float load/store multiples)
5934 * -mno-fpu Disable all floating point instructions
5935 * Run-time endian selection:
5936 * -EB big endian cpu
5937 * -EL little endian cpu
5938 * ARM Procedure Calling Standard:
5939 * -mapcs-32 32 bit APCS
5940 * -mapcs-26 26 bit APCS
5941 * -mapcs-float Pass floats in float regs
5942 * -mapcs-reentrant Position independent code
5943 * -mthumb-interwork Code supports Arm/Thumb interworking
5946 CONST char *md_shortopts = "m:";
5947 struct option md_longopts[] =
5949 #ifdef ARM_BI_ENDIAN
5950 #define OPTION_EB (OPTION_MD_BASE + 0)
5951 {"EB", no_argument, NULL, OPTION_EB},
5952 #define OPTION_EL (OPTION_MD_BASE + 1)
5953 {"EL", no_argument, NULL, OPTION_EL},
5955 {NULL, no_argument, NULL, 0}
5957 size_t md_longopts_size = sizeof (md_longopts);
5960 md_parse_option (c, arg)
5968 #ifdef ARM_BI_ENDIAN
5970 target_big_endian = 1;
5973 target_big_endian = 0;
5981 if (! strcmp (str, "fpa10"))
5982 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
5983 else if (! strcmp (str, "fpa11"))
5984 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
5985 else if (! strcmp (str, "fpe-old"))
5986 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
5992 if (! strcmp (str, "no-fpu"))
5993 cpu_variant &= ~FPU_ALL;
5997 /* Limit assembler to generating only Thumb instructions: */
5998 if (! strcmp (str, "thumb"))
6000 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6001 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6004 else if (! strcmp (str, "thumb-interwork"))
6006 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB | ARM_ARCHv4;
6007 #if defined OBJ_COFF || defined OBJ_ELF
6008 support_interwork = true;
6016 if (! strcmp (str, "all"))
6018 cpu_variant = ARM_ALL | FPU_ALL;
6021 #if defined OBJ_COFF || defined OBJ_ELF
6022 if (! strncmp (str, "apcs-", 5))
6024 /* GCC passes on all command line options starting "-mapcs-..."
6025 to us, so we must parse them here. */
6029 if (! strcmp (str, "32"))
6031 uses_apcs_26 = false;
6034 else if (! strcmp (str, "26"))
6036 uses_apcs_26 = true;
6039 else if (! strcmp (str, "frame"))
6041 /* Stack frames are being generated - does not affect
6045 else if (! strcmp (str, "stack-check"))
6047 /* Stack checking is being performed - does not affect
6048 linkage, but does require that the functions
6049 __rt_stkovf_split_small and __rt_stkovf_split_big be
6050 present in the final link. */
6054 else if (! strcmp (str, "float"))
6056 /* Floating point arguments are being passed in the floating
6057 point registers. This does affect linking, since this
6058 version of the APCS is incompatible with the version that
6059 passes floating points in the integer registers. */
6061 uses_apcs_float = true;
6064 else if (! strcmp (str, "reentrant"))
6066 /* Reentrant code has been generated. This does affect
6067 linking, since there is no point in linking reentrant/
6068 position independent code with absolute position code. */
6073 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6077 /* Strip off optional "arm" */
6078 if (! strncmp (str, "arm", 3))
6084 if (! strcmp (str, "1"))
6085 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6091 if (! strcmp (str, "2"))
6092 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6093 else if (! strcmp (str, "250"))
6094 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6100 if (! strcmp (str, "3"))
6101 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6107 if (! strcmp (str, "strongarm") || ! strcmp (str, "strongarm110"))
6108 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCHv4 | ARM_LONGMUL;
6114 if (! strcmp (str, "8"))
6115 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCHv4 | ARM_LONGMUL;
6121 if (! strcmp (str, "6"))
6122 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6128 str++; /* eat the '7' */
6129 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6135 cpu_variant |= (ARM_THUMB | ARM_ARCHv4);
6139 cpu_variant |= ARM_LONGMUL;
6142 case 'f': /* fe => fp enabled cpu. */
6148 case 'c': /* Unknown */
6149 case 'd': /* debug */
6150 case 'i': /* embedded ice */
6151 /* Included for completeness in ARM processor naming. */
6161 /* Select variant based on architecture rather than processor */
6167 case 'a': cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3; break;
6168 case 0: cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2; break;
6169 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6174 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6178 case 'm': cpu_variant |= ARM_LONGMUL; break;
6180 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6185 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCHv4;
6189 case 't': cpu_variant |= ARM_THUMB; break;
6191 default: as_bad (_("Invalid architecture variant -m%s"), arg); break;
6196 as_bad (_("Invalid architecture variant -m%s"), arg);
6203 as_bad (_("Invalid processor variant -m%s"), arg);
6222 -m[arm][<processor name>] select processor variant\n\
6223 -m[arm]v[2|2a|3|3m|4|4t] select architecture variant\n\
6224 -mthumb only allow Thumb instructions\n\
6225 -mthumb-interwork mark the assembled code as supporting interworking\n\
6226 -mall allow any instruction\n\
6227 -mfpa10, -mfpa11 select floating point architecture\n\
6228 -mfpe-old don't allow floating-point multiple instructions\n\
6229 -mno-fpu don't allow any floating-point instructions.\n"));
6230 #if defined OBJ_COFF || defined OBJ_ELF
6233 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard is in use\n"));
6236 -mapcs-float floating point args are passed in floating point regs\n"));
6239 -mapcs-reentrant position independent/reentrant code has been generated\n"));
6241 #ifdef ARM_BI_ENDIAN
6244 -EB assemble code for a big endian cpu\n\
6245 -EL assemble code for a little endian cpu\n"));
6249 /* We need to be able to fix up arbitrary expressions in some statements.
6250 This is so that we can handle symbols that are an arbitrary distance from
6251 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6252 which returns part of an address in a form which will be valid for
6253 a data instruction. We do this by pushing the expression into a symbol
6254 in the expr_section, and creating a fix for that. */
6257 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
6266 arm_fix_data *arm_data;
6274 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
6278 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
6283 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6284 arm_data = (arm_fix_data *) obstack_alloc (¬es, sizeof (arm_fix_data));
6285 new_fix->tc_fix_data = (PTR) arm_data;
6286 arm_data->thumb_mode = thumb_mode;
6291 /* A good place to do this, although this was probably not intended
6292 * for this kind of use. We need to dump the literal pool before
6293 * references are made to a null symbol pointer. */
6297 if (current_poolP != NULL)
6299 subseg_set (text_section, 0); /* Put it at the end of text section */
6301 listing_prev_line ();
6306 arm_start_line_hook ()
6308 last_label_seen = NULL;
6312 arm_frob_label (sym)
6315 last_label_seen = sym;
6316 ARM_SET_THUMB (sym, thumb_mode);
6317 #if defined OBJ_COFF || defined OBJ_ELF
6318 ARM_SET_INTERWORK (sym, support_interwork);
6321 if (label_is_thumb_function_name)
6323 /* When the address of a Thumb function is taken the bottom
6324 bit of that address should be set. This will allow
6325 interworking between Arm and Thumb functions to work
6328 THUMB_SET_FUNC (sym, 1);
6330 label_is_thumb_function_name = false;
6334 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6338 arm_adjust_symtab ()
6340 #if defined OBJ_COFF
6343 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6345 if (ARM_IS_THUMB (sym))
6347 if (THUMB_IS_FUNC (sym))
6349 /* Mark the symbol as a Thumb function. */
6350 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
6351 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
6352 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
6353 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
6354 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
6356 as_bad (_("%s: unexpected function type: %d"), S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
6358 else switch (S_GET_STORAGE_CLASS (sym))
6361 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
6364 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
6367 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
6369 default: /* do nothing */
6374 if (ARM_IS_INTERWORK (sym))
6375 coffsymbol(sym->bsym)->native->u.syment.n_flags = 0xFF;
6383 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
6385 *input_line_pointer = '/';
6386 input_line_pointer += 5;
6387 *input_line_pointer = 0;
6394 arm_canonicalize_symbol_name (name)
6399 if (thumb_mode && (len = strlen (name)) > 5
6400 && ! strcmp (name + len - 5, "/data"))
6402 *(name + len - 5) = 0;
6409 arm_validate_fix (fixP)
6412 /* If the destination of the branch is a defined symbol which does not have
6413 the THUMB_FUNC attribute, then we must be calling a function which has
6414 the (interfacearm) attribute. We look for the Thumb entry point to that
6415 function and change the branch to refer to that function instead. */
6416 if ( fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
6417 && fixP->fx_addsy != NULL
6418 && S_IS_DEFINED (fixP->fx_addsy)
6419 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6421 fixP->fx_addsy = find_real_start (fixP->fx_addsy);