1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
35 /* ??? This is currently unused. */
37 #define internalError() \
38 as_fatal ("ARM Internal Error, line %d, %s", __LINE__, __FILE__)
40 #define internalError() as_fatal ("ARM Internal Error")
43 /* Types of processor to assemble for. */
44 #define ARM_1 0x00000001
45 #define ARM_2 0x00000002
46 #define ARM_3 0x00000004
48 #define ARM_6 0x00000008
49 #define ARM_7 ARM_6 /* same core instruction set */
50 #define ARM_CPU_MASK 0x0000000f
52 /* The following bitmasks control CPU extensions (ARM7 onwards): */
53 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
54 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
55 #define ARM_THUMB 0x00000040 /* allow BX instruction */
57 #define ARM_ARCHv4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 /* Some useful combinations: */
60 #define ARM_ANY 0x00ffffff
61 #define ARM_2UP 0x00fffffe
62 #define ARM_ALL ARM_2UP /* Not arm1 only */
63 #define ARM_3UP 0x00fffffc
64 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
66 #define FPU_CORE 0x80000000
67 #define FPU_FPA10 0x40000000
68 #define FPU_FPA11 0x40000000
71 /* Some useful combinations */
72 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
73 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
78 #define CPU_DEFAULT (ARM_ARCHv4 | ARM_THUMB)
80 #define CPU_DEFAULT ARM_ALL
85 #define FPU_DEFAULT FPU_ALL
88 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
91 /* Flags stored in private area of BFD COFF structure */
92 static boolean uses_apcs_26 = false;
93 static boolean support_interwork = false;
94 static boolean uses_apcs_float = false;
95 static boolean pic_code = false;
98 /* This array holds the chars that always start a comment. If the
99 pre-processor is disabled, these aren't very useful */
100 CONST char comment_chars[] = "@";
102 /* This array holds the chars that only start a comment at the beginning of
103 a line. If the line seems to have the form '# 123 filename'
104 .line and .file directives will appear in the pre-processed output */
105 /* Note that input_file.c hand checks for '#' at the beginning of the
106 first line of the input file. This is because the compiler outputs
107 #NO_APP at the beginning of its output. */
108 /* Also note that comments like this one will always work. */
109 CONST char line_comment_chars[] = "#";
111 CONST char line_separator_chars[] = "";
113 /* Chars that can be used to separate mant from exp in floating point nums */
114 CONST char EXP_CHARS[] = "eE";
116 /* Chars that mean this number is a floating point constant */
120 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
122 CONST int md_reloc_size = 8; /* Size of relocation record */
124 static int thumb_mode = 0; /* non-zero if assembling thumb instructions */
126 typedef struct arm_fix
134 unsigned long instruction;
139 bfd_reloc_code_real_type type;
149 CONST char *template;
153 static CONST struct asm_shift shift[] =
169 #define NO_SHIFT_RESTRICT 1
170 #define SHIFT_RESTRICT 0
172 #define NUM_FLOAT_VALS 8
174 CONST char *fp_const[] =
176 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
179 /* Number of littlenums required to hold an extended precision number */
180 #define MAX_LITTLENUMS 6
182 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
192 #define CP_T_X 0x00008000
193 #define CP_T_Y 0x00400000
194 #define CP_T_Pre 0x01000000
195 #define CP_T_UD 0x00800000
196 #define CP_T_WB 0x00200000
198 #define CONDS_BIT (0x00100000)
199 #define LOAD_BIT (0x00100000)
200 #define TRANS_BIT (0x00200000)
204 CONST char *template;
208 /* This is to save a hash look-up in the common case */
209 #define COND_ALWAYS 0xe0000000
211 static CONST struct asm_cond conds[] =
215 {"cs", 0x20000000}, {"hs", 0x20000000},
216 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
231 /* Warning: If the top bit of the set_bits is set, then the standard
232 instruction bitmask is ignored, and the new bitmask is taken from
236 CONST char *template; /* Basic flag string */
237 unsigned long set_bits; /* Bits to set */
240 static CONST struct asm_flg s_flag[] =
246 static CONST struct asm_flg ldr_flags[] =
250 {"bt", 0x00400000 | TRANS_BIT},
257 static CONST struct asm_flg str_flags[] =
261 {"bt", 0x00400000 | TRANS_BIT},
266 static CONST struct asm_flg byte_flag[] =
272 static CONST struct asm_flg cmp_flags[] =
279 static CONST struct asm_flg ldm_flags[] =
292 static CONST struct asm_flg stm_flags[] =
305 static CONST struct asm_flg lfm_flags[] =
312 static CONST struct asm_flg sfm_flags[] =
319 static CONST struct asm_flg round_flags[] =
327 /* The implementation of the FIX instruction is broken on some assemblers,
328 in that it accepts a precision specifier as well as a rounding specifier,
329 despite the fact that this is meaningless. To be more compatible, we
330 accept it as well, though of course it does not set any bits. */
331 static CONST struct asm_flg fix_flags[] =
348 static CONST struct asm_flg except_flag[] =
354 static CONST struct asm_flg cplong_flag[] =
362 CONST char *template;
363 unsigned long number;
366 #define PSR_ALL 0x00010000
368 static CONST struct asm_psr psrs[] =
381 /* Functions called by parser */
382 /* ARM instructions */
383 static void do_arit PARAMS ((char *operands, unsigned long flags));
384 static void do_cmp PARAMS ((char *operands, unsigned long flags));
385 static void do_mov PARAMS ((char *operands, unsigned long flags));
386 static void do_ldst PARAMS ((char *operands, unsigned long flags));
387 static void do_ldmstm PARAMS ((char *operands, unsigned long flags));
388 static void do_branch PARAMS ((char *operands, unsigned long flags));
389 static void do_swi PARAMS ((char *operands, unsigned long flags));
390 /* Pseudo Op codes */
391 static void do_adr PARAMS ((char *operands, unsigned long flags));
392 static void do_nop PARAMS ((char *operands, unsigned long flags));
394 static void do_mul PARAMS ((char *operands, unsigned long flags));
395 static void do_mla PARAMS ((char *operands, unsigned long flags));
397 static void do_swap PARAMS ((char *operands, unsigned long flags));
399 static void do_msr PARAMS ((char *operands, unsigned long flags));
400 static void do_mrs PARAMS ((char *operands, unsigned long flags));
402 static void do_mull PARAMS ((char *operands, unsigned long flags));
404 static void do_bx PARAMS ((char *operands, unsigned long flags));
406 /* Coprocessor Instructions */
407 static void do_cdp PARAMS ((char *operands, unsigned long flags));
408 static void do_lstc PARAMS ((char *operands, unsigned long flags));
409 static void do_co_reg PARAMS ((char *operands, unsigned long flags));
410 static void do_fp_ctrl PARAMS ((char *operands, unsigned long flags));
411 static void do_fp_ldst PARAMS ((char *operands, unsigned long flags));
412 static void do_fp_ldmstm PARAMS ((char *operands, unsigned long flags));
413 static void do_fp_dyadic PARAMS ((char *operands, unsigned long flags));
414 static void do_fp_monadic PARAMS ((char *operands, unsigned long flags));
415 static void do_fp_cmp PARAMS ((char *operands, unsigned long flags));
416 static void do_fp_from_reg PARAMS ((char *operands, unsigned long flags));
417 static void do_fp_to_reg PARAMS ((char *operands, unsigned long flags));
419 static void fix_new_arm PARAMS ((fragS *frag, int where,
420 short int size, expressionS *exp,
421 int pc_rel, int reloc));
422 static int arm_reg_parse PARAMS ((char **ccp));
423 static int arm_psr_parse PARAMS ((char **ccp));
424 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT,
426 static int add_to_lit_pool PARAMS ((void));
427 static unsigned validate_immediate PARAMS ((unsigned));
428 static int validate_offset_imm PARAMS ((int, int));
429 static void opcode_select PARAMS ((int));
430 static void end_of_line PARAMS ((char *));
431 static int reg_required_here PARAMS ((char **, int));
432 static int psr_required_here PARAMS ((char **, int));
433 static int psrf_required_here PARAMS ((char **, int));
434 static int co_proc_number PARAMS ((char **));
435 static int cp_opc_expr PARAMS ((char **, int, int));
436 static int cp_reg_required_here PARAMS ((char **, int));
437 static int fp_reg_required_here PARAMS ((char **, int));
438 static int cp_address_offset PARAMS ((char **));
439 static int cp_address_required_here PARAMS ((char **));
440 static int my_get_float_expression PARAMS ((char **));
441 static int skip_past_comma PARAMS ((char **));
442 static int walk_no_bignums PARAMS ((symbolS *));
443 static int negate_data_op PARAMS ((unsigned long *,
445 static int data_op2 PARAMS ((char **));
446 static int fp_op2 PARAMS ((char **));
447 static long reg_list PARAMS ((char **));
448 static void thumb_load_store PARAMS ((char *, int, int));
449 static int decode_shift PARAMS ((char **, int));
450 static int ldst_extend PARAMS ((char **, int));
451 static void thumb_add_sub PARAMS ((char *, int));
452 static void insert_reg PARAMS ((int));
453 static void thumb_shift PARAMS ((char *, int));
454 static void thumb_mov_compare PARAMS ((char *, int));
455 static void set_constant_flonums PARAMS ((void));
456 static valueT md_chars_to_number PARAMS ((char *, int));
457 static void insert_reg_alias PARAMS ((char *, int));
458 static void output_inst PARAMS ((char *));
460 /* ARM instructions take 4bytes in the object file, Thumb instructions
464 /* LONGEST_INST is the longest basic instruction name without conditions or
466 * ARM7M has 4 of length 5
469 #define LONGEST_INST 5
473 CONST char *template; /* Basic string to match */
474 unsigned long value; /* Basic instruction code */
475 CONST char *comp_suffix; /* Compulsory suffix that must follow conds */
476 CONST struct asm_flg *flags; /* Bits to toggle if flag 'n' set */
477 unsigned long variants; /* Which CPU variants this exists for */
478 /* Function to call to parse args */
479 void (*parms) PARAMS ((char *, unsigned long));
482 static CONST struct asm_opcode insns[] =
484 /* ARM Instructions */
485 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
486 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
487 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
488 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
489 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
490 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
491 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
492 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
493 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
494 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
495 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
496 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
497 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
498 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
499 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
500 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
501 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
502 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
503 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
504 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
505 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
506 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
507 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
510 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
511 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
513 /* ARM 2 multiplies */
514 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
515 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
517 /* ARM 3 - swp instructions */
518 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
520 /* ARM 6 Coprocessor instructions */
521 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
522 {"msr", 0x0128f000, NULL, NULL, ARM_6UP, do_msr},
524 /* ARM 7M long multiplies - need signed/unsigned flags! */
525 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
526 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
527 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
528 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
530 /* ARM THUMB interworking */
531 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
533 /* Floating point instructions */
534 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
535 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
536 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
537 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
538 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
539 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
540 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
541 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
542 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
543 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
544 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
545 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
546 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
547 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
548 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
549 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
550 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
551 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
552 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
553 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
554 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
555 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
556 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
557 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
558 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
559 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
560 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
561 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
562 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
563 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
564 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
565 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
566 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
567 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
568 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
569 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
570 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
571 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
572 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
573 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
574 be an optional suffix, but part of the instruction. To be compatible,
576 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
577 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
578 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
579 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
581 /* Generic copressor instructions */
582 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
583 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
584 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
585 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
586 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
589 /* defines for various bits that we will want to toggle */
591 #define INST_IMMEDIATE 0x02000000
592 #define OFFSET_REG 0x02000000
593 #define HWOFFSET_IMM 0x00400000
594 #define SHIFT_BY_REG 0x00000010
595 #define PRE_INDEX 0x01000000
596 #define INDEX_UP 0x00800000
597 #define WRITE_BACK 0x00200000
598 #define MULTI_SET_PSR 0x00400000
600 #define LITERAL_MASK 0xf000f000
601 #define COND_MASK 0xf0000000
602 #define OPCODE_MASK 0xfe1fffff
603 #define DATA_OP_SHIFT 21
605 /* Codes to distinguish the arithmetic instructions */
617 #define OPCODE_CMP 10
618 #define OPCODE_CMN 11
619 #define OPCODE_ORR 12
620 #define OPCODE_MOV 13
621 #define OPCODE_BIC 14
622 #define OPCODE_MVN 15
624 static void do_t_nop PARAMS ((char *operands));
625 static void do_t_arit PARAMS ((char *operands));
626 static void do_t_add PARAMS ((char *operands));
627 static void do_t_asr PARAMS ((char *operands));
628 static void do_t_branch9 PARAMS ((char *operands));
629 static void do_t_branch12 PARAMS ((char *operands));
630 static void do_t_branch23 PARAMS ((char *operands));
631 static void do_t_bx PARAMS ((char *operands));
632 static void do_t_compare PARAMS ((char *operands));
633 static void do_t_ldmstm PARAMS ((char *operands));
634 static void do_t_ldr PARAMS ((char *operands));
635 static void do_t_ldrb PARAMS ((char *operands));
636 static void do_t_ldrh PARAMS ((char *operands));
637 static void do_t_lds PARAMS ((char *operands));
638 static void do_t_lsl PARAMS ((char *operands));
639 static void do_t_lsr PARAMS ((char *operands));
640 static void do_t_mov PARAMS ((char *operands));
641 static void do_t_push_pop PARAMS ((char *operands));
642 static void do_t_str PARAMS ((char *operands));
643 static void do_t_strb PARAMS ((char *operands));
644 static void do_t_strh PARAMS ((char *operands));
645 static void do_t_sub PARAMS ((char *operands));
646 static void do_t_swi PARAMS ((char *operands));
647 static void do_t_adr PARAMS ((char *operands));
649 #define T_OPCODE_MUL 0x4340
650 #define T_OPCODE_TST 0x4200
651 #define T_OPCODE_CMN 0x42c0
652 #define T_OPCODE_NEG 0x4240
653 #define T_OPCODE_MVN 0x43c0
655 #define T_OPCODE_ADD_R3 0x1800
656 #define T_OPCODE_SUB_R3 0x1a00
657 #define T_OPCODE_ADD_HI 0x4400
658 #define T_OPCODE_ADD_ST 0xb000
659 #define T_OPCODE_SUB_ST 0xb080
660 #define T_OPCODE_ADD_SP 0xa800
661 #define T_OPCODE_ADD_PC 0xa000
662 #define T_OPCODE_ADD_I8 0x3000
663 #define T_OPCODE_SUB_I8 0x3800
664 #define T_OPCODE_ADD_I3 0x1c00
665 #define T_OPCODE_SUB_I3 0x1e00
667 #define T_OPCODE_ASR_R 0x4100
668 #define T_OPCODE_LSL_R 0x4080
669 #define T_OPCODE_LSR_R 0x40c0
670 #define T_OPCODE_ASR_I 0x1000
671 #define T_OPCODE_LSL_I 0x0000
672 #define T_OPCODE_LSR_I 0x0800
674 #define T_OPCODE_MOV_I8 0x2000
675 #define T_OPCODE_CMP_I8 0x2800
676 #define T_OPCODE_CMP_LR 0x4280
677 #define T_OPCODE_MOV_HR 0x4600
678 #define T_OPCODE_CMP_HR 0x4500
680 #define T_OPCODE_LDR_PC 0x4800
681 #define T_OPCODE_LDR_SP 0x9800
682 #define T_OPCODE_STR_SP 0x9000
683 #define T_OPCODE_LDR_IW 0x6800
684 #define T_OPCODE_STR_IW 0x6000
685 #define T_OPCODE_LDR_IH 0x8800
686 #define T_OPCODE_STR_IH 0x8000
687 #define T_OPCODE_LDR_IB 0x7800
688 #define T_OPCODE_STR_IB 0x7000
689 #define T_OPCODE_LDR_RW 0x5800
690 #define T_OPCODE_STR_RW 0x5000
691 #define T_OPCODE_LDR_RH 0x5a00
692 #define T_OPCODE_STR_RH 0x5200
693 #define T_OPCODE_LDR_RB 0x5c00
694 #define T_OPCODE_STR_RB 0x5400
696 #define T_OPCODE_PUSH 0xb400
697 #define T_OPCODE_POP 0xbc00
699 #define T_OPCODE_BRANCH 0xe7fe
701 static int thumb_reg PARAMS ((char **str, int hi_lo));
703 #define THUMB_SIZE 2 /* Size of thumb instruction */
704 #define THUMB_REG_LO 0x1
705 #define THUMB_REG_HI 0x2
706 #define THUMB_REG_ANY 0x3
708 #define THUMB_H1 0x0080
709 #define THUMB_H2 0x0040
716 #define THUMB_COMPARE 1
719 #define THUMB_STORE 1
721 #define THUMB_PP_PC_LR 0x0100
723 /* These three are used for immediate shifts, do not alter */
725 #define THUMB_HALFWORD 1
730 CONST char *template; /* Basic string to match */
731 unsigned long value; /* Basic instruction code */
733 /* Function to call to parse args */
734 void (*parms) PARAMS ((char *));
737 static CONST struct thumb_opcode tinsns[] =
739 {"adc", 0x4140, 2, do_t_arit},
740 {"add", 0x0000, 2, do_t_add},
741 {"and", 0x4000, 2, do_t_arit},
742 {"asr", 0x0000, 2, do_t_asr},
743 {"b", T_OPCODE_BRANCH, 2, do_t_branch12},
744 {"beq", 0xd0fe, 2, do_t_branch9},
745 {"bne", 0xd1fe, 2, do_t_branch9},
746 {"bcs", 0xd2fe, 2, do_t_branch9},
747 {"bhs", 0xd2fe, 2, do_t_branch9},
748 {"bcc", 0xd3fe, 2, do_t_branch9},
749 {"bul", 0xd3fe, 2, do_t_branch9},
750 {"blo", 0xd3fe, 2, do_t_branch9},
751 {"bmi", 0xd4fe, 2, do_t_branch9},
752 {"bpl", 0xd5fe, 2, do_t_branch9},
753 {"bvs", 0xd6fe, 2, do_t_branch9},
754 {"bvc", 0xd7fe, 2, do_t_branch9},
755 {"bhi", 0xd8fe, 2, do_t_branch9},
756 {"bls", 0xd9fe, 2, do_t_branch9},
757 {"bge", 0xdafe, 2, do_t_branch9},
758 {"blt", 0xdbfe, 2, do_t_branch9},
759 {"bgt", 0xdcfe, 2, do_t_branch9},
760 {"ble", 0xddfe, 2, do_t_branch9},
761 {"bic", 0x4380, 2, do_t_arit},
762 {"bl", 0xf7fffffe, 4, do_t_branch23},
763 {"bx", 0x4700, 2, do_t_bx},
764 {"cmn", T_OPCODE_CMN, 2, do_t_arit},
765 {"cmp", 0x0000, 2, do_t_compare},
766 {"eor", 0x4040, 2, do_t_arit},
767 {"ldmia", 0xc800, 2, do_t_ldmstm},
768 {"ldr", 0x0000, 2, do_t_ldr},
769 {"ldrb", 0x0000, 2, do_t_ldrb},
770 {"ldrh", 0x0000, 2, do_t_ldrh},
771 {"ldrsb", 0x5600, 2, do_t_lds},
772 {"ldrsh", 0x5e00, 2, do_t_lds},
773 {"ldsb", 0x5600, 2, do_t_lds},
774 {"ldsh", 0x5e00, 2, do_t_lds},
775 {"lsl", 0x0000, 2, do_t_lsl},
776 {"lsr", 0x0000, 2, do_t_lsr},
777 {"mov", 0x0000, 2, do_t_mov},
778 {"mul", T_OPCODE_MUL, 2, do_t_arit},
779 {"mvn", T_OPCODE_MVN, 2, do_t_arit},
780 {"neg", T_OPCODE_NEG, 2, do_t_arit},
781 {"orr", 0x4300, 2, do_t_arit},
782 {"pop", 0xbc00, 2, do_t_push_pop},
783 {"push", 0xb400, 2, do_t_push_pop},
784 {"ror", 0x41c0, 2, do_t_arit},
785 {"sbc", 0x4180, 2, do_t_arit},
786 {"stmia", 0xc000, 2, do_t_ldmstm},
787 {"str", 0x0000, 2, do_t_str},
788 {"strb", 0x0000, 2, do_t_strb},
789 {"strh", 0x0000, 2, do_t_strh},
790 {"swi", 0xdf00, 2, do_t_swi},
791 {"sub", 0x0000, 2, do_t_sub},
792 {"tst", T_OPCODE_TST, 2, do_t_arit},
794 {"adr", 0x0000, 2, do_t_adr},
795 {"nop", 0x46C0, 2, do_t_nop}, /* mov r8,r8 */
804 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
805 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
806 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
812 /* These are the standard names; Users can add aliases with .req */
813 static CONST struct reg_entry reg_table[] =
815 /* Processor Register Numbers */
816 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
817 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
818 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
819 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
820 /* APCS conventions */
821 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
822 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
823 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
824 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
826 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
827 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
828 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
829 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
830 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
831 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
832 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
833 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
834 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
835 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
839 static CONST char *bad_args = "Bad arguments to instruction";
840 static CONST char *bad_pc = "r15 not allowed here";
842 static struct hash_control *arm_ops_hsh = NULL;
843 static struct hash_control *arm_tops_hsh = NULL;
844 static struct hash_control *arm_cond_hsh = NULL;
845 static struct hash_control *arm_shift_hsh = NULL;
846 static struct hash_control *arm_reg_hsh = NULL;
847 static struct hash_control *arm_psr_hsh = NULL;
849 /* This table describes all the machine specific pseudo-ops the assembler
850 has to support. The fields are:
851 pseudo-op name without dot
852 function to call to execute this pseudo-op
853 Integer arg to pass to the function
856 static void s_req PARAMS ((int));
857 static void s_align PARAMS ((int));
858 static void s_bss PARAMS ((int));
859 static void s_even PARAMS ((int));
860 static void s_ltorg PARAMS ((int));
861 static void s_arm PARAMS ((int));
862 static void s_thumb PARAMS ((int));
863 static void s_code PARAMS ((int));
864 static void s_force_thumb PARAMS ((int));
865 static void s_thumb_func PARAMS ((int));
867 static int my_get_expression PARAMS ((expressionS *, char **));
869 CONST pseudo_typeS md_pseudo_table[] =
871 {"req", s_req, 0}, /* Never called becasue '.req' does not start line */
873 {"align", s_align, 0},
875 {"thumb", s_thumb, 0},
877 {"force_thumb", s_force_thumb, 0},
878 {"thumb_func", s_thumb_func, 0},
880 {"ltorg", s_ltorg, 0},
881 {"pool", s_ltorg, 0},
883 {"extend", float_cons, 'x'},
884 {"ldouble", float_cons, 'x'},
885 {"packed", float_cons, 'p'},
889 /* Stuff needed to resolve the label ambiguity
899 symbolS * last_label_seen;
900 static int label_is_thumb_function_name = false;
904 #define MAX_LITERAL_POOL_SIZE 1024
906 typedef struct literalS
908 struct expressionS exp;
912 literalT literals[MAX_LITERAL_POOL_SIZE];
913 int next_literal_pool_place = 0; /* Next free entry in the pool */
914 int lit_pool_num = 1; /* Next literal pool number */
915 symbolS *current_poolP = NULL;
916 symbolS *symbol_make_empty PARAMS ((void));
923 if (current_poolP == NULL)
924 current_poolP = symbol_make_empty();
926 /* Check if this literal value is already in the pool: */
927 while (lit_count < next_literal_pool_place)
929 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
930 && inst.reloc.exp.X_op == O_constant
931 && literals[lit_count].exp.X_add_number == inst.reloc.exp.X_add_number
932 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
937 if (lit_count == next_literal_pool_place) /* new entry */
939 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
941 inst.error = "Literal Pool Overflow";
945 literals[next_literal_pool_place].exp = inst.reloc.exp;
946 lit_count = next_literal_pool_place++;
949 inst.reloc.exp.X_op = O_symbol;
950 inst.reloc.exp.X_add_number = (lit_count)*4-8;
951 inst.reloc.exp.X_add_symbol = current_poolP;
956 /* Can't use symbol_new here, so have to create a symbol and then at
957 a later date assign it a value. Thats what these functions do */
959 symbol_locate (symbolP, name, segment, valu, frag)
961 CONST char *name; /* It is copied, the caller can modify */
962 segT segment; /* Segment identifier (SEG_<something>) */
963 valueT valu; /* Symbol value */
964 fragS *frag; /* Associated fragment */
966 unsigned int name_length;
967 char *preserved_copy_of_name;
969 name_length = strlen (name) + 1; /* +1 for \0 */
970 obstack_grow (¬es, name, name_length);
971 preserved_copy_of_name = obstack_finish (¬es);
972 #ifdef STRIP_UNDERSCORE
973 if (preserved_copy_of_name[0] == '_')
974 preserved_copy_of_name++;
977 #ifdef tc_canonicalize_symbol_name
978 preserved_copy_of_name =
979 tc_canonicalize_symbol_name (preserved_copy_of_name);
982 S_SET_NAME (symbolP, preserved_copy_of_name);
984 S_SET_SEGMENT (symbolP, segment);
985 S_SET_VALUE (symbolP, valu);
986 symbol_clear_list_pointers(symbolP);
988 symbolP->sy_frag = frag;
991 * Link to end of symbol chain.
994 extern int symbol_table_frozen;
995 if (symbol_table_frozen)
999 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1001 obj_symbol_new_hook (symbolP);
1003 #ifdef tc_symbol_new_hook
1004 tc_symbol_new_hook (symbolP);
1008 verify_symbol_chain(symbol_rootP, symbol_lastP);
1009 #endif /* DEBUG_SYMS */
1013 symbol_make_empty ()
1017 symbolP = (symbolS *) obstack_alloc (¬es, sizeof (symbolS));
1019 /* symbol must be born in some fixed state. This seems as good as any. */
1020 memset (symbolP, 0, sizeof (symbolS));
1022 symbolP->bsym = bfd_make_empty_symbol (stdoutput);
1023 assert (symbolP->bsym != 0);
1024 symbolP->bsym->udata.p = (PTR) symbolP;
1029 /* Check that an immediate is valid, and if so, convert it to the right format. */
1032 validate_immediate (val)
1038 #define rotate_left(v, n) (v << n | v >> (32 - n))
1040 for (i = 0; i < 32; i += 2)
1041 if ((a = rotate_left (val, i)) <= 0xff)
1042 return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
1047 validate_offset_imm (val, hwse)
1051 if ((hwse && (val < -255 || val > 255))
1052 || (val < -4095 || val > 4095))
1062 as_bad ("Invalid syntax for .req directive.");
1069 /* We don't support putting frags in the BSS segment, we fake it by
1070 marking in_bss, then looking at s_skip for clues?.. */
1071 subseg_set (bss_section, 0);
1072 demand_empty_rest_of_line ();
1079 if (!need_pass_2) /* Never make frag if expect extra pass. */
1080 frag_align (1, 0, 0);
1081 record_alignment (now_seg, 1);
1082 demand_empty_rest_of_line ();
1092 if (current_poolP == NULL)
1096 as_tsktsk ("Nothing to put in the pool\n");
1100 /* Align pool as you have word accesses */
1101 /* Only make a frag if we have to ... */
1103 frag_align (2, 0, 0);
1105 record_alignment (now_seg, 2);
1108 as_tsktsk ("Inserting implicit pool at change of section");
1110 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1112 symbol_locate (current_poolP, sym_name, now_seg,
1113 (valueT) frag_now_fix (), frag_now);
1114 symbol_table_insert (current_poolP);
1116 ARM_SET_THUMB (current_poolP, thumb_mode);
1117 ARM_SET_INTERWORK (current_poolP, support_interwork);
1119 while (lit_count < next_literal_pool_place)
1120 /* First output the expression in the instruction to the pool */
1121 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1123 next_literal_pool_place = 0;
1124 current_poolP = NULL;
1127 #if 0 /* not used */
1129 arm_align (power, fill)
1133 /* Only make a frag if we HAVE to ... */
1134 if (power && !need_pass_2)
1135 frag_align (power, fill, 0);
1137 record_alignment (now_seg, power);
1142 s_align (unused) /* Same as s_align_ptwo but align 0 => align 2 */
1146 register long temp_fill;
1147 long max_alignment = 15;
1149 temp = get_absolute_expression ();
1150 if (temp > max_alignment)
1151 as_bad ("Alignment too large: %d. assumed.", temp = max_alignment);
1154 as_bad ("Alignment negative. 0 assumed.");
1158 if (*input_line_pointer == ',')
1160 input_line_pointer++;
1161 temp_fill = get_absolute_expression ();
1169 /* Only make a frag if we HAVE to. . . */
1170 if (temp && !need_pass_2)
1171 frag_align (temp, (int) temp_fill, 0);
1172 demand_empty_rest_of_line ();
1174 record_alignment (now_seg, temp);
1178 s_force_thumb (ignore)
1181 /* If we are not already in thumb mode go into it, EVEN if
1182 the target processor does not support thumb instructions.
1183 This is used by gcc/config/arm/lib1funcs.asm for example
1184 to compile interworking support functions even if the
1185 target processor should not support interworking. */
1191 record_alignment (now_seg, 1);
1194 demand_empty_rest_of_line ();
1198 s_thumb_func (ignore)
1201 /* The following label is the name/address of the start of a Thumb function.
1202 We need to know this for the interworking support. */
1204 label_is_thumb_function_name = true;
1206 demand_empty_rest_of_line();
1210 opcode_select (width)
1218 if (! (cpu_variant & ARM_THUMB))
1219 as_bad ("selected processor does not support THUMB opcodes");
1221 /* No need to force the alignment, since we will have been
1222 coming from ARM mode, which is word-aligned. */
1223 record_alignment (now_seg, 1);
1230 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1231 as_bad ("selected processor does not support ARM opcodes");
1234 frag_align (2, 0, 0);
1235 record_alignment (now_seg, 1);
1240 as_bad ("invalid instruction size selected (%d)", width);
1249 demand_empty_rest_of_line ();
1257 demand_empty_rest_of_line ();
1266 temp = get_absolute_expression ();
1271 opcode_select(temp);
1275 as_bad ("invalid operand to .code directive (%d) (expecting 16 or 32)", temp);
1287 inst.error = "Garbage following instruction";
1291 skip_past_comma (str)
1297 while ((c = *p) == ' ' || c == ',')
1300 if (c == ',' && comma++)
1308 return comma ? SUCCESS : FAIL;
1311 /* A standard register must be given at this point. Shift is the place to
1312 put it in the instruction. */
1315 reg_required_here (str, shift)
1322 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1324 inst.instruction |= reg << shift;
1328 /* In the few cases where we might be able to accept something else
1329 this error can be overridden */
1330 inst.error = "Register expected";
1332 /* Restore the start point, we may have got a reg of the wrong class. */
1338 psr_required_here (str, shift)
1345 if ((psr = arm_psr_parse (str)) != FAIL && psr < 2)
1348 inst.instruction |= 1 << shift; /* Should be bit 22 */
1352 /* In the few cases where we might be able to accept something else
1353 this error can be overridden */
1354 inst.error = "<psr> expected";
1356 /* Restore the start point. */
1362 psrf_required_here (str, shift)
1369 if ((psrf = arm_psr_parse (str)) != FAIL && psrf > 1)
1371 if (psrf == 1 || psrf == 3)
1372 inst.instruction |= 1 << shift; /* Should be bit 22 */
1376 /* In the few cases where we might be able to accept something else
1377 this error can be overridden */
1378 inst.error = "<psrf> expected";
1380 /* Restore the start point. */
1386 co_proc_number (str)
1389 int processor, pchar;
1391 while (**str == ' ')
1394 /* The data sheet seems to imply that just a number on its own is valid
1395 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1397 if (**str == 'p' || **str == 'P')
1401 if (pchar >= '0' && pchar <= '9')
1403 processor = pchar - '0';
1404 if (**str >= '0' && **str <= '9')
1406 processor = processor * 10 + *(*str)++ - '0';
1409 inst.error = "Illegal co-processor number";
1416 inst.error = "Bad or missing co-processor number";
1420 inst.instruction |= processor << 8;
1425 cp_opc_expr (str, where, length)
1432 while (**str == ' ')
1435 memset (&expr, '\0', sizeof (expr));
1437 if (my_get_expression (&expr, str))
1439 if (expr.X_op != O_constant)
1441 inst.error = "bad or missing expression";
1445 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1447 inst.error = "immediate co-processor expression too large";
1451 inst.instruction |= expr.X_add_number << where;
1456 cp_reg_required_here (str, where)
1463 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1466 inst.instruction |= reg << where;
1470 /* In the few cases where we might be able to accept something else
1471 this error can be overridden */
1472 inst.error = "Co-processor register expected";
1474 /* Restore the start point */
1480 fp_reg_required_here (str, where)
1487 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1490 inst.instruction |= reg << where;
1494 /* In the few cases where we might be able to accept something else
1495 this error can be overridden */
1496 inst.error = "Floating point register expected";
1498 /* Restore the start point */
1504 cp_address_offset (str)
1509 while (**str == ' ')
1514 inst.error = "immediate expression expected";
1519 if (my_get_expression (&inst.reloc.exp, str))
1521 if (inst.reloc.exp.X_op == O_constant)
1523 offset = inst.reloc.exp.X_add_number;
1526 inst.error = "co-processor address must be word aligned";
1530 if (offset > 1023 || offset < -1023)
1532 inst.error = "offset too large";
1537 inst.instruction |= INDEX_UP;
1541 inst.instruction |= offset >> 2;
1544 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1550 cp_address_required_here (str)
1565 if ((reg = reg_required_here (&p, 16)) == FAIL)
1567 inst.error = "Register required";
1577 if (skip_past_comma (&p) == SUCCESS)
1580 write_back = WRITE_BACK;
1583 inst.error = "pc may not be used in post-increment";
1587 if (cp_address_offset (&p) == FAIL)
1591 pre_inc = PRE_INDEX | INDEX_UP;
1595 /* '['Rn, #expr']'[!] */
1597 if (skip_past_comma (&p) == FAIL)
1599 inst.error = "pre-indexed expression expected";
1603 pre_inc = PRE_INDEX;
1604 if (cp_address_offset (&p) == FAIL)
1612 inst.error = "missing ]";
1623 inst.error = "pc may not be used with write-back";
1628 write_back = WRITE_BACK;
1634 if (my_get_expression (&inst.reloc.exp, &p))
1637 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1638 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
1639 inst.reloc.pc_rel = 1;
1640 inst.instruction |= (REG_PC << 16);
1641 pre_inc = PRE_INDEX;
1644 inst.instruction |= write_back | pre_inc;
1652 unsigned long flags;
1654 /* Do nothing really */
1655 inst.instruction |= flags; /* This is pointless */
1663 unsigned long flags;
1665 /* Only one syntax */
1669 if (reg_required_here (&str, 12) == FAIL)
1671 inst.error = bad_args;
1675 if (skip_past_comma (&str) == FAIL
1676 || psr_required_here (&str, 22) == FAIL)
1678 inst.error = "<psr> expected";
1682 inst.instruction |= flags;
1690 unsigned long flags;
1693 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression" */
1698 if ((psr = psr_required_here (&str, 22)) != FAIL)
1700 inst.instruction |= PSR_ALL;
1701 /* Sytax should be "<psr>, Rm" */
1702 if (skip_past_comma (&str) == FAIL
1703 || (reg = reg_required_here (&str, 0)) == FAIL)
1705 inst.error = bad_args;
1709 else if ((psrf = psrf_required_here (&str, 22)) != FAIL)
1710 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1712 if (skip_past_comma (&str) == FAIL)
1714 inst.error = bad_args;
1717 if ((reg = reg_required_here (&str, 0)) != FAIL)
1719 /* Immediate expression */
1720 else if (*(str++) == '#')
1723 if (my_get_expression (&inst.reloc.exp, &str))
1725 inst.error = "Register or shift expression expected";
1729 if (inst.reloc.exp.X_add_symbol)
1731 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
1732 inst.reloc.pc_rel = 0;
1736 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
1739 inst.error = "Invalid constant";
1743 inst.instruction |= value;
1746 flags |= INST_IMMEDIATE;
1750 inst.error = "Error: the other";
1756 inst.error = bad_args;
1761 inst.instruction |= flags;
1766 /* Long Multiply Parser
1767 UMULL RdLo, RdHi, Rm, Rs
1768 SMULL RdLo, RdHi, Rm, Rs
1769 UMLAL RdLo, RdHi, Rm, Rs
1770 SMLAL RdLo, RdHi, Rm, Rs
1773 do_mull (str, flags)
1775 unsigned long flags;
1777 int rdlo, rdhi, rm, rs;
1779 /* only one format "rdlo, rdhi, rm, rs" */
1783 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
1785 inst.error = bad_args;
1789 if (skip_past_comma (&str) == FAIL
1790 || (rdhi = reg_required_here (&str, 16)) == FAIL)
1792 inst.error = bad_args;
1796 if (skip_past_comma (&str) == FAIL
1797 || (rm = reg_required_here (&str, 0)) == FAIL)
1799 inst.error = bad_args;
1803 /* rdhi, rdlo and rm must all be different */
1804 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
1805 as_tsktsk ("rdhi, rdlo and rm must all be different");
1807 if (skip_past_comma (&str) == FAIL
1808 || (rs = reg_required_here (&str, 8)) == FAIL)
1810 inst.error = bad_args;
1814 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
1816 inst.error = bad_pc;
1820 inst.instruction |= flags;
1828 unsigned long flags;
1832 /* only one format "rd, rm, rs" */
1836 if ((rd = reg_required_here (&str, 16)) == FAIL)
1838 inst.error = bad_args;
1844 inst.error = bad_pc;
1848 if (skip_past_comma (&str) == FAIL
1849 || (rm = reg_required_here (&str, 0)) == FAIL)
1851 inst.error = bad_args;
1857 inst.error = bad_pc;
1862 as_tsktsk ("rd and rm should be different in mul");
1864 if (skip_past_comma (&str) == FAIL
1865 || (rm = reg_required_here (&str, 8)) == FAIL)
1867 inst.error = bad_args;
1873 inst.error = bad_pc;
1877 inst.instruction |= flags;
1885 unsigned long flags;
1889 /* only one format "rd, rm, rs, rn" */
1893 if ((rd = reg_required_here (&str, 16)) == FAIL)
1895 inst.error = bad_args;
1901 inst.error = bad_pc;
1905 if (skip_past_comma (&str) == FAIL
1906 || (rm = reg_required_here (&str, 0)) == FAIL)
1908 inst.error = bad_args;
1914 inst.error = bad_pc;
1919 as_tsktsk ("rd and rm should be different in mla");
1921 if (skip_past_comma (&str) == FAIL
1922 || (rd = reg_required_here (&str, 8)) == FAIL
1923 || skip_past_comma (&str) == FAIL
1924 || (rm = reg_required_here (&str, 12)) == FAIL)
1926 inst.error = bad_args;
1930 if (rd == REG_PC || rm == REG_PC)
1932 inst.error = bad_pc;
1936 inst.instruction |= flags;
1941 /* Returns the index into fp_values of a floating point number, or -1 if
1942 not in the table. */
1944 my_get_float_expression (str)
1947 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1952 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
1953 /* Look for a raw floating point number */
1954 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
1955 && (is_end_of_line [(int)(*save_in)] || *save_in == '\0'))
1957 for (i = 0; i < NUM_FLOAT_VALS; i++)
1959 for (j = 0; j < MAX_LITTLENUMS; j++)
1961 if (words[j] != fp_values[i][j])
1965 if (j == MAX_LITTLENUMS)
1973 /* Try and parse a more complex expression, this will probably fail
1974 unless the code uses a floating point prefix (eg "0f") */
1975 save_in = input_line_pointer;
1976 input_line_pointer = *str;
1977 if (expression (&exp) == absolute_section
1978 && exp.X_op == O_big
1979 && exp.X_add_number < 0)
1981 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
1983 if (gen_to_words (words, 5, (long)15) == 0)
1985 for (i = 0; i < NUM_FLOAT_VALS; i++)
1987 for (j = 0; j < MAX_LITTLENUMS; j++)
1989 if (words[j] != fp_values[i][j])
1993 if (j == MAX_LITTLENUMS)
1995 *str = input_line_pointer;
1996 input_line_pointer = save_in;
2003 *str = input_line_pointer;
2004 input_line_pointer = save_in;
2008 /* Return true if anything in the expression is a bignum */
2010 walk_no_bignums (sp)
2013 if (sp->sy_value.X_op == O_big)
2016 if (sp->sy_value.X_add_symbol)
2018 return (walk_no_bignums (sp->sy_value.X_add_symbol)
2019 || (sp->sy_value.X_op_symbol
2020 && walk_no_bignums (sp->sy_value.X_op_symbol)));
2027 my_get_expression (ep, str)
2034 save_in = input_line_pointer;
2035 input_line_pointer = *str;
2036 seg = expression (ep);
2039 if (seg != absolute_section
2040 && seg != text_section
2041 && seg != data_section
2042 && seg != bss_section
2043 && seg != undefined_section)
2045 inst.error = "bad_segment";
2046 *str = input_line_pointer;
2047 input_line_pointer = save_in;
2052 /* Get rid of any bignums now, so that we don't generate an error for which
2053 we can't establish a line number later on. Big numbers are never valid
2054 in instructions, which is where this routine is always called. */
2055 if (ep->X_op == O_big
2056 || (ep->X_add_symbol
2057 && (walk_no_bignums (ep->X_add_symbol)
2059 && walk_no_bignums (ep->X_op_symbol)))))
2061 inst.error = "Invalid constant";
2062 *str = input_line_pointer;
2063 input_line_pointer = save_in;
2067 *str = input_line_pointer;
2068 input_line_pointer = save_in;
2072 /* unrestrict should be one if <shift> <register> is permitted for this
2076 decode_shift (str, unrestrict)
2080 struct asm_shift *shft;
2084 while (**str == ' ')
2087 for (p = *str; isalpha (*p); p++)
2092 inst.error = "Shift expression expected";
2098 shft = (struct asm_shift *) hash_find (arm_shift_hsh, *str);
2102 if (!strcmp (*str, "rrx")
2103 || !strcmp (*str, "RRX"))
2106 inst.instruction |= shft->value;
2113 if (unrestrict && reg_required_here (&p, 8) != FAIL)
2115 inst.instruction |= shft->value | SHIFT_BY_REG;
2123 if (my_get_expression (&inst.reloc.exp, &p))
2126 /* Validate some simple #expressions */
2127 if (inst.reloc.exp.X_op == O_constant)
2129 unsigned num = inst.reloc.exp.X_add_number;
2131 /* Reject operations greater than 32, or lsl #32 */
2132 if (num > 32 || (num == 32 && shft->value == 0))
2134 inst.error = "Invalid immediate shift";
2138 /* Shifts of zero should be converted to lsl (which is zero)*/
2145 /* Shifts of 32 are encoded as 0, for those shifts that
2150 inst.instruction |= (num << 7) | shft->value;
2155 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2156 inst.reloc.pc_rel = 0;
2157 inst.instruction |= shft->value;
2163 inst.error = unrestrict ? "shift requires register or #expression"
2164 : "shift requires #expression";
2170 inst.error = "Shift expression expected";
2174 /* Do those data_ops which can take a negative immediate constant */
2175 /* by altering the instuction. A bit of a hack really */
2179 by inverting the second operand, and
2182 by negating the second operand.
2185 negate_data_op (instruction, value)
2186 unsigned long *instruction;
2187 unsigned long value;
2190 unsigned long negated, inverted;
2192 negated = validate_immediate (-value);
2193 inverted = validate_immediate (~value);
2195 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2199 case OPCODE_SUB: /* ADD <-> SUB */
2200 new_inst = OPCODE_ADD;
2205 new_inst = OPCODE_SUB;
2209 case OPCODE_CMP: /* CMP <-> CMN */
2210 new_inst = OPCODE_CMN;
2215 new_inst = OPCODE_CMP;
2219 /* Now Inverted ops */
2220 case OPCODE_MOV: /* MOV <-> MVN */
2221 new_inst = OPCODE_MVN;
2226 new_inst = OPCODE_MOV;
2230 case OPCODE_AND: /* AND <-> BIC */
2231 new_inst = OPCODE_BIC;
2236 new_inst = OPCODE_AND;
2240 case OPCODE_ADC: /* ADC <-> SBC */
2241 new_inst = OPCODE_SBC;
2246 new_inst = OPCODE_ADC;
2250 /* We cannot do anything */
2258 *instruction &= OPCODE_MASK;
2259 *instruction |= new_inst << DATA_OP_SHIFT;
2270 while (**str == ' ')
2273 if (reg_required_here (str, 0) != FAIL)
2275 if (skip_past_comma (str) == SUCCESS)
2277 /* Shift operation on register */
2278 return decode_shift (str, NO_SHIFT_RESTRICT);
2284 /* Immediate expression */
2285 if (*((*str)++) == '#')
2288 if (my_get_expression (&inst.reloc.exp, str))
2291 if (inst.reloc.exp.X_add_symbol)
2293 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2294 inst.reloc.pc_rel = 0;
2298 if (skip_past_comma (str) == SUCCESS)
2300 /* #x, y -- ie explicit rotation by Y */
2301 if (my_get_expression (&expr, str))
2304 if (expr.X_op != O_constant)
2306 inst.error = "Constant expression expected";
2310 /* Rotate must be a multiple of 2 */
2311 if (((unsigned) expr.X_add_number) > 30
2312 || (expr.X_add_number & 1) != 0
2313 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2315 inst.error = "Invalid constant";
2318 inst.instruction |= INST_IMMEDIATE;
2319 inst.instruction |= inst.reloc.exp.X_add_number;
2320 inst.instruction |= expr.X_add_number << 7;
2324 /* Implicit rotation, select a suitable one */
2325 value = validate_immediate (inst.reloc.exp.X_add_number);
2329 /* Can't be done, perhaps the code reads something like
2330 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2331 if ((value = negate_data_op (&inst.instruction,
2332 inst.reloc.exp.X_add_number))
2335 inst.error = "Invalid constant";
2340 inst.instruction |= value;
2343 inst.instruction |= INST_IMMEDIATE;
2347 inst.error = "Register or shift expression expected";
2356 while (**str == ' ')
2359 if (fp_reg_required_here (str, 0) != FAIL)
2363 /* Immediate expression */
2364 if (*((*str)++) == '#')
2369 while (**str == ' ')
2372 /* First try and match exact strings, this is to guarantee that
2373 some formats will work even for cross assembly */
2375 for (i = 0; fp_const[i]; i++)
2377 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2381 *str += strlen (fp_const[i]);
2382 if (is_end_of_line[(int)**str] || **str == '\0')
2384 inst.instruction |= i + 8;
2391 /* Just because we didn't get a match doesn't mean that the
2392 constant isn't valid, just that it is in a format that we
2393 don't automatically recognize. Try parsing it with
2394 the standard expression routines. */
2395 if ((i = my_get_float_expression (str)) >= 0)
2397 inst.instruction |= i + 8;
2401 inst.error = "Invalid floating point immediate expression";
2404 inst.error = "Floating point register or immediate expression expected";
2410 do_arit (str, flags)
2412 unsigned long flags;
2417 if (reg_required_here (&str, 12) == FAIL
2418 || skip_past_comma (&str) == FAIL
2419 || reg_required_here (&str, 16) == FAIL
2420 || skip_past_comma (&str) == FAIL
2421 || data_op2 (&str) == FAIL)
2424 inst.error = bad_args;
2428 inst.instruction |= flags;
2436 unsigned long flags;
2438 /* This is a pseudo-op of the form "adr rd, label" to be converted
2439 into a relative address of the form "add rd, pc, #label-.-8" */
2444 if (reg_required_here (&str, 12) == FAIL
2445 || skip_past_comma (&str) == FAIL
2446 || my_get_expression (&inst.reloc.exp, &str))
2449 inst.error = bad_args;
2452 /* Frag hacking will turn this into a sub instruction if the offset turns
2453 out to be negative. */
2454 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2455 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2456 inst.reloc.pc_rel = 1;
2457 inst.instruction |= flags;
2465 unsigned long flags;
2470 if (reg_required_here (&str, 16) == FAIL)
2473 inst.error = bad_args;
2477 if (skip_past_comma (&str) == FAIL
2478 || data_op2 (&str) == FAIL)
2481 inst.error = bad_args;
2485 inst.instruction |= flags;
2486 if ((flags & 0x0000f000) == 0)
2487 inst.instruction |= CONDS_BIT;
2496 unsigned long flags;
2501 if (reg_required_here (&str, 12) == FAIL)
2504 inst.error = bad_args;
2508 if (skip_past_comma (&str) == FAIL
2509 || data_op2 (&str) == FAIL)
2512 inst.error = bad_args;
2516 inst.instruction |= flags;
2522 ldst_extend (str, hwse)
2532 if (my_get_expression (&inst.reloc.exp, str))
2535 if (inst.reloc.exp.X_op == O_constant)
2537 int value = inst.reloc.exp.X_add_number;
2539 if ((hwse && (value < -255 || value > 255))
2540 || (value < -4095 || value > 4095))
2542 inst.error = "address offset too large";
2552 /* Halfword and signextension instructions have the
2553 immediate value split across bits 11..8 and bits 3..0 */
2555 inst.instruction |= add | HWOFFSET_IMM | (value >> 4) << 8 | value & 0xF;
2557 inst.instruction |= add | value;
2563 inst.instruction |= HWOFFSET_IMM;
2564 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2567 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2568 inst.reloc.pc_rel = 0;
2573 add = 0; /* and fall through */
2575 (*str)++; /* and fall through */
2577 if (reg_required_here (str, 0) == FAIL)
2579 inst.error = "Register expected";
2584 inst.instruction |= add;
2587 inst.instruction |= add | OFFSET_REG;
2588 if (skip_past_comma (str) == SUCCESS)
2589 return decode_shift (str, SHIFT_RESTRICT);
2597 do_ldst (str, flags)
2599 unsigned long flags;
2606 /* This is not ideal, but it is the simplest way of dealing with the
2607 ARM7T halfword instructions (since they use a different
2608 encoding, but the same mnemonic): */
2609 if (halfword = ((flags & 0x80000000) != 0))
2611 /* This is actually a load/store of a halfword, or a
2612 signed-extension load */
2613 if ((cpu_variant & ARM_HALFWORD) == 0)
2616 = "Processor does not support halfwords or signed bytes";
2620 inst.instruction = (inst.instruction & COND_MASK)
2621 | (flags & ~COND_MASK);
2629 if ((conflict_reg = reg_required_here (&str, 12)) == FAIL)
2632 inst.error = bad_args;
2636 if (skip_past_comma (&str) == FAIL)
2638 inst.error = "Address expected";
2650 if ((reg = reg_required_here (&str, 16)) == FAIL)
2652 inst.error = "Register required";
2656 conflict_reg = (((conflict_reg == reg)
2657 && (inst.instruction & LOAD_BIT))
2666 if (skip_past_comma (&str) == SUCCESS)
2668 /* [Rn],... (post inc) */
2669 if (ldst_extend (&str, halfword) == FAIL)
2672 as_warn ("destination register same as write-back base\n");
2678 inst.instruction |= HWOFFSET_IMM;
2686 as_warn ("destination register same as write-back base\n");
2688 inst.instruction |= WRITE_BACK;
2692 if (! (flags & TRANS_BIT))
2699 if (skip_past_comma (&str) == FAIL)
2701 inst.error = "pre-indexed expression expected";
2706 if (ldst_extend (&str, halfword) == FAIL)
2714 inst.error = "missing ]";
2724 as_tsktsk ("destination register same as write-back base\n");
2726 inst.instruction |= WRITE_BACK;
2730 else if (*str == '=')
2732 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2738 if (my_get_expression (&inst.reloc.exp, &str))
2741 if (inst.reloc.exp.X_op != O_constant
2742 && inst.reloc.exp.X_op != O_symbol)
2744 inst.error = "Constant expression expected";
2748 if (inst.reloc.exp.X_op == O_constant
2749 && (value = validate_immediate(inst.reloc.exp.X_add_number)) != FAIL)
2751 /* This can be done with a mov instruction */
2752 inst.instruction &= LITERAL_MASK;
2753 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
2754 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
2760 /* Insert into literal pool */
2761 if (add_to_lit_pool () == FAIL)
2764 inst.error = "literal pool insertion failed";
2768 /* Change the instruction exp to point to the pool */
2771 inst.instruction |= HWOFFSET_IMM;
2772 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
2775 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
2776 inst.reloc.pc_rel = 1;
2777 inst.instruction |= (REG_PC << 16);
2783 if (my_get_expression (&inst.reloc.exp, &str))
2788 inst.instruction |= HWOFFSET_IMM;
2789 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2792 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2793 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
2794 inst.reloc.pc_rel = 1;
2795 inst.instruction |= (REG_PC << 16);
2799 if (pre_inc && (flags & TRANS_BIT))
2800 inst.error = "Pre-increment instruction with translate";
2802 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
2815 /* We come back here if we get ranges concatenated by '+' or '|' */
2833 if ((reg = arm_reg_parse (&str)) == FAIL || !int_register (reg))
2835 inst.error = "Register expected";
2845 inst.error = "Bad range in register list";
2849 for (i = cur_reg + 1; i < reg; i++)
2851 if (range & (1 << i))
2853 ("Warning: Duplicated register (r%d) in register list",
2861 if (range & (1 << reg))
2862 as_tsktsk ("Warning: Duplicated register (r%d) in register list",
2864 else if (reg <= cur_reg)
2865 as_tsktsk ("Warning: Register range not in ascending order");
2869 } while (skip_past_comma (&str) != FAIL
2870 || (in_range = 1, *str++ == '-'));
2877 inst.error = "Missing `}'";
2885 if (my_get_expression (&expr, &str))
2888 if (expr.X_op == O_constant)
2890 if (expr.X_add_number
2891 != (expr.X_add_number & 0x0000ffff))
2893 inst.error = "invalid register mask";
2897 if ((range & expr.X_add_number) != 0)
2899 int regno = range & expr.X_add_number;
2902 regno = (1 << regno) - 1;
2904 ("Warning: Duplicated register (r%d) in register list",
2908 range |= expr.X_add_number;
2912 if (inst.reloc.type != 0)
2914 inst.error = "expression too complex";
2918 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
2919 inst.reloc.type = BFD_RELOC_ARM_MULTI;
2920 inst.reloc.pc_rel = 0;
2927 if (*str == '|' || *str == '+')
2932 } while (another_range);
2939 do_ldmstm (str, flags)
2941 unsigned long flags;
2949 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
2952 inst.error = bad_args;
2956 if (base_reg == REG_PC)
2958 inst.error = "r15 not allowed as base register";
2966 flags |= WRITE_BACK;
2970 if (skip_past_comma (&str) == FAIL
2971 || (range = reg_list (&str)) == FAIL)
2974 inst.error = bad_args;
2981 flags |= MULTI_SET_PSR;
2984 inst.instruction |= flags | range;
2992 unsigned long flags;
2994 /* Allow optional leading '#'. */
3000 if (my_get_expression (&inst.reloc.exp, &str))
3003 inst.reloc.type = BFD_RELOC_ARM_SWI;
3004 inst.reloc.pc_rel = 0;
3005 inst.instruction |= flags;
3011 do_swap (str, flags)
3013 unsigned long flags;
3020 if ((reg = reg_required_here (&str, 12)) == FAIL)
3025 inst.error = "r15 not allowed in swap";
3029 if (skip_past_comma (&str) == FAIL
3030 || (reg = reg_required_here (&str, 0)) == FAIL)
3033 inst.error = bad_args;
3039 inst.error = "r15 not allowed in swap";
3043 if (skip_past_comma (&str) == FAIL
3046 inst.error = bad_args;
3053 if ((reg = reg_required_here (&str, 16)) == FAIL)
3058 inst.error = bad_pc;
3067 inst.error = "missing ]";
3071 inst.instruction |= flags;
3077 do_branch (str, flags)
3079 unsigned long flags;
3081 if (my_get_expression (&inst.reloc.exp, &str))
3083 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3084 inst.reloc.pc_rel = 1;
3092 unsigned long flags;
3099 if ((reg = reg_required_here (&str, 0)) == FAIL)
3103 as_tsktsk ("Use of r15 in bx has undefined behaviour");
3112 unsigned long flags;
3114 /* Co-processor data operation.
3115 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3119 if (co_proc_number (&str) == FAIL)
3122 inst.error = bad_args;
3126 if (skip_past_comma (&str) == FAIL
3127 || cp_opc_expr (&str, 20,4) == FAIL)
3130 inst.error = bad_args;
3134 if (skip_past_comma (&str) == FAIL
3135 || cp_reg_required_here (&str, 12) == FAIL)
3138 inst.error = bad_args;
3142 if (skip_past_comma (&str) == FAIL
3143 || cp_reg_required_here (&str, 16) == FAIL)
3146 inst.error = bad_args;
3150 if (skip_past_comma (&str) == FAIL
3151 || cp_reg_required_here (&str, 0) == FAIL)
3154 inst.error = bad_args;
3158 if (skip_past_comma (&str) == SUCCESS)
3160 if (cp_opc_expr (&str, 5, 3) == FAIL)
3163 inst.error = bad_args;
3173 do_lstc (str, flags)
3175 unsigned long flags;
3177 /* Co-processor register load/store.
3178 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3183 if (co_proc_number (&str) == FAIL)
3186 inst.error = bad_args;
3190 if (skip_past_comma (&str) == FAIL
3191 || cp_reg_required_here (&str, 12) == FAIL)
3194 inst.error = bad_args;
3198 if (skip_past_comma (&str) == FAIL
3199 || cp_address_required_here (&str) == FAIL)
3202 inst.error = bad_args;
3206 inst.instruction |= flags;
3212 do_co_reg (str, flags)
3214 unsigned long flags;
3216 /* Co-processor register transfer.
3217 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3222 if (co_proc_number (&str) == FAIL)
3225 inst.error = bad_args;
3229 if (skip_past_comma (&str) == FAIL
3230 || cp_opc_expr (&str, 21, 3) == FAIL)
3233 inst.error = bad_args;
3237 if (skip_past_comma (&str) == FAIL
3238 || reg_required_here (&str, 12) == FAIL)
3241 inst.error = bad_args;
3245 if (skip_past_comma (&str) == FAIL
3246 || cp_reg_required_here (&str, 16) == FAIL)
3249 inst.error = bad_args;
3253 if (skip_past_comma (&str) == FAIL
3254 || cp_reg_required_here (&str, 0) == FAIL)
3257 inst.error = bad_args;
3261 if (skip_past_comma (&str) == SUCCESS)
3263 if (cp_opc_expr (&str, 5, 3) == FAIL)
3266 inst.error = bad_args;
3276 do_fp_ctrl (str, flags)
3278 unsigned long flags;
3280 /* FP control registers.
3281 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3286 if (reg_required_here (&str, 12) == FAIL)
3289 inst.error = bad_args;
3298 do_fp_ldst (str, flags)
3300 unsigned long flags;
3305 switch (inst.suffix)
3310 inst.instruction |= CP_T_X;
3313 inst.instruction |= CP_T_Y;
3316 inst.instruction |= CP_T_X | CP_T_Y;
3322 if (fp_reg_required_here (&str, 12) == FAIL)
3325 inst.error = bad_args;
3329 if (skip_past_comma (&str) == FAIL
3330 || cp_address_required_here (&str) == FAIL)
3333 inst.error = bad_args;
3341 do_fp_ldmstm (str, flags)
3343 unsigned long flags;
3350 if (fp_reg_required_here (&str, 12) == FAIL)
3353 inst.error = bad_args;
3357 /* Get Number of registers to transfer */
3358 if (skip_past_comma (&str) == FAIL
3359 || my_get_expression (&inst.reloc.exp, &str))
3362 inst.error = "constant expression expected";
3366 if (inst.reloc.exp.X_op != O_constant)
3368 inst.error = "Constant value required for number of registers";
3372 num_regs = inst.reloc.exp.X_add_number;
3374 if (num_regs < 1 || num_regs > 4)
3376 inst.error = "number of registers must be in the range [1:4]";
3383 inst.instruction |= CP_T_X;
3386 inst.instruction |= CP_T_Y;
3389 inst.instruction |= CP_T_Y | CP_T_X;
3403 /* The instruction specified "ea" or "fd", so we can only accept
3404 [Rn]{!}. The instruction does not really support stacking or
3405 unstacking, so we have to emulate these by setting appropriate
3406 bits and offsets. */
3407 if (skip_past_comma (&str) == FAIL
3411 inst.error = bad_args;
3419 if ((reg = reg_required_here (&str, 16)) == FAIL)
3421 inst.error = "Register required";
3430 inst.error = bad_args;
3441 inst.error = "R15 not allowed as base register with write-back";
3448 if (flags & CP_T_Pre)
3451 offset = 3 * num_regs;
3457 /* Post-increment */
3461 offset = 3 * num_regs;
3465 /* No write-back, so convert this into a standard pre-increment
3466 instruction -- aesthetically more pleasing. */
3467 flags = CP_T_Pre | CP_T_UD;
3472 inst.instruction |= flags | offset;
3474 else if (skip_past_comma (&str) == FAIL
3475 || cp_address_required_here (&str) == FAIL)
3478 inst.error = bad_args;
3486 do_fp_dyadic (str, flags)
3488 unsigned long flags;
3493 switch (inst.suffix)
3498 inst.instruction |= 0x00000080;
3501 inst.instruction |= 0x00080000;
3507 if (fp_reg_required_here (&str, 12) == FAIL)
3510 inst.error = bad_args;
3514 if (skip_past_comma (&str) == FAIL
3515 || fp_reg_required_here (&str, 16) == FAIL)
3518 inst.error = bad_args;
3522 if (skip_past_comma (&str) == FAIL
3523 || fp_op2 (&str) == FAIL)
3526 inst.error = bad_args;
3530 inst.instruction |= flags;
3536 do_fp_monadic (str, flags)
3538 unsigned long flags;
3543 switch (inst.suffix)
3548 inst.instruction |= 0x00000080;
3551 inst.instruction |= 0x00080000;
3557 if (fp_reg_required_here (&str, 12) == FAIL)
3560 inst.error = bad_args;
3564 if (skip_past_comma (&str) == FAIL
3565 || fp_op2 (&str) == FAIL)
3568 inst.error = bad_args;
3572 inst.instruction |= flags;
3578 do_fp_cmp (str, flags)
3580 unsigned long flags;
3585 if (fp_reg_required_here (&str, 16) == FAIL)
3588 inst.error = bad_args;
3592 if (skip_past_comma (&str) == FAIL
3593 || fp_op2 (&str) == FAIL)
3596 inst.error = bad_args;
3600 inst.instruction |= flags;
3606 do_fp_from_reg (str, flags)
3608 unsigned long flags;
3613 switch (inst.suffix)
3618 inst.instruction |= 0x00000080;
3621 inst.instruction |= 0x00080000;
3627 if (fp_reg_required_here (&str, 16) == FAIL)
3630 inst.error = bad_args;
3634 if (skip_past_comma (&str) == FAIL
3635 || reg_required_here (&str, 12) == FAIL)
3638 inst.error = bad_args;
3642 inst.instruction |= flags;
3648 do_fp_to_reg (str, flags)
3650 unsigned long flags;
3655 if (reg_required_here (&str, 12) == FAIL)
3658 inst.error = bad_args;
3662 if (skip_past_comma (&str) == FAIL
3663 || fp_reg_required_here (&str, 0) == FAIL)
3666 inst.error = bad_args;
3670 inst.instruction |= flags;
3675 /* Thumb specific routines */
3677 /* Parse and validate that a register is of the right form, this saves
3678 repeated checking of this information in many similar cases.
3679 Unlike the 32-bit case we do not insert the register into the opcode
3680 here, since the position is often unknown until the full instruction
3683 thumb_reg (strp, hi_lo)
3689 if ((reg = arm_reg_parse (strp)) == FAIL || ! int_register (reg))
3691 inst.error = "Register expected";
3700 inst.error = "lo register required";
3708 inst.error = "hi register required";
3720 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3723 thumb_add_sub (str, subtract)
3727 int Rd, Rs, Rn = FAIL;
3732 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
3733 || skip_past_comma (&str) == FAIL)
3736 inst.error = bad_args;
3744 if (my_get_expression (&inst.reloc.exp, &str))
3749 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3752 if (skip_past_comma (&str) == FAIL)
3754 /* Two operand format, shuffle the registers and pretend there
3759 else if (*str == '#')
3762 if (my_get_expression (&inst.reloc.exp, &str))
3765 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3769 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
3770 for the latter case, EXPR contains the immediate that was found. */
3773 /* All register format. */
3774 if (Rd > 7 || Rs > 7 || Rn > 7)
3778 inst.error = "dest and source1 must be the same register";
3782 /* Can't do this for SUB */
3785 inst.error = "subtract valid only on lo regs";
3789 inst.instruction = (T_OPCODE_ADD_HI
3790 | (Rd > 7 ? THUMB_H1 : 0)
3791 | (Rn > 7 ? THUMB_H2 : 0));
3792 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
3796 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
3797 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
3802 /* Immediate expression, now things start to get nasty. */
3804 /* First deal with HI regs, only very restricted cases allowed:
3805 Adjusting SP, and using PC or SP to get an address. */
3806 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
3807 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
3809 inst.error = "invalid Hi register with immediate";
3813 if (inst.reloc.exp.X_op != O_constant)
3815 /* Value isn't known yet, all we can do is store all the fragments
3816 we know about in the instruction and let the reloc hacking
3818 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
3819 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
3823 int offset = inst.reloc.exp.X_add_number;
3833 /* Quick check, in case offset is MIN_INT */
3836 inst.error = "immediate value out of range";
3845 if (offset & ~0x1fc)
3847 inst.error = "invalid immediate value for stack adjust";
3850 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
3851 inst.instruction |= offset >> 2;
3853 else if (Rs == REG_PC || Rs == REG_SP)
3856 || (offset & ~0x3fc))
3858 inst.error = "invalid immediate for address calculation";
3861 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
3863 inst.instruction |= (Rd << 8) | (offset >> 2);
3869 inst.error = "immediate value out of range";
3872 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
3873 inst.instruction |= (Rd << 8) | offset;
3879 inst.error = "immediate value out of range";
3882 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
3883 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
3891 thumb_shift (str, shift)
3895 int Rd, Rs, Rn = FAIL;
3900 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
3901 || skip_past_comma (&str) == FAIL)
3904 inst.error = bad_args;
3910 /* Two operand immediate format, set Rs to Rd. */
3913 if (my_get_expression (&inst.reloc.exp, &str))
3918 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
3921 if (skip_past_comma (&str) == FAIL)
3923 /* Two operand format, shuffle the registers and pretend there
3928 else if (*str == '#')
3931 if (my_get_expression (&inst.reloc.exp, &str))
3934 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
3938 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
3939 for the latter case, EXPR contains the immediate that was found. */
3945 inst.error = "source1 and dest must be same register";
3951 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
3952 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
3953 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
3956 inst.instruction |= Rd | (Rn << 3);
3962 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
3963 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
3964 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
3967 if (inst.reloc.exp.X_op != O_constant)
3969 /* Value isn't known yet, create a dummy reloc and let reloc
3970 hacking fix it up */
3972 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
3976 unsigned shift_value = inst.reloc.exp.X_add_number;
3978 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
3980 inst.error = "Invalid immediate for shift";
3984 /* Shifts of zero are handled by converting to LSL */
3985 if (shift_value == 0)
3986 inst.instruction = T_OPCODE_LSL_I;
3988 /* Shifts of 32 are encoded as a shift of zero */
3989 if (shift_value == 32)
3992 inst.instruction |= shift_value << 6;
3995 inst.instruction |= Rd | (Rs << 3);
4001 thumb_mov_compare (str, move)
4010 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4011 || skip_past_comma (&str) == FAIL)
4014 inst.error = bad_args;
4021 if (my_get_expression (&inst.reloc.exp, &str))
4024 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4029 if (Rs < 8 && Rd < 8)
4031 if (move == THUMB_MOVE)
4032 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4033 since a MOV instruction produces unpredictable results */
4034 inst.instruction = T_OPCODE_ADD_I3;
4036 inst.instruction = T_OPCODE_CMP_LR;
4037 inst.instruction |= Rd | (Rs << 3);
4041 if (move == THUMB_MOVE)
4042 inst.instruction = T_OPCODE_MOV_HR;
4044 inst.instruction = T_OPCODE_CMP_HR;
4047 inst.instruction |= THUMB_H1;
4050 inst.instruction |= THUMB_H2;
4052 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4059 inst.error = "only lo regs allowed with immediate";
4063 if (move == THUMB_MOVE)
4064 inst.instruction = T_OPCODE_MOV_I8;
4066 inst.instruction = T_OPCODE_CMP_I8;
4068 inst.instruction |= Rd << 8;
4070 if (inst.reloc.exp.X_op != O_constant)
4071 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4074 unsigned value = inst.reloc.exp.X_add_number;
4078 inst.error = "invalid immediate";
4082 inst.instruction |= value;
4090 thumb_load_store (str, load_store, size)
4095 int Rd, Rb, Ro = FAIL;
4100 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4101 || skip_past_comma (&str) == FAIL)
4104 inst.error = bad_args;
4111 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4114 if (skip_past_comma (&str) != FAIL)
4119 if (my_get_expression (&inst.reloc.exp, &str))
4122 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4127 inst.reloc.exp.X_op = O_constant;
4128 inst.reloc.exp.X_add_number = 0;
4133 inst.error = "expected ']'";
4138 else if (*str == '=')
4140 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4146 if (my_get_expression (& inst.reloc.exp, & str))
4151 if ( inst.reloc.exp.X_op != O_constant
4152 && inst.reloc.exp.X_op != O_symbol)
4154 inst.error = "Constant expression expected";
4158 if (inst.reloc.exp.X_op == O_constant
4159 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4161 /* This can be done with a mov instruction */
4163 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4164 inst.instruction |= inst.reloc.exp.X_add_number;
4168 /* Insert into literal pool */
4169 if (add_to_lit_pool () == FAIL)
4172 inst.error = "literal pool insertion failed";
4176 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4177 inst.reloc.pc_rel = 1;
4178 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4179 inst.reloc.exp.X_add_number += 4; /* Adjust ARM pipeline offset to Thumb */
4185 if (my_get_expression (&inst.reloc.exp, &str))
4188 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4189 inst.reloc.pc_rel = 1;
4190 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset */
4191 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4196 if (Rb == REG_PC || Rb == REG_SP)
4198 if (size != THUMB_WORD)
4200 inst.error = "byte or halfword not valid for base register";
4203 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4205 inst.error = "R15 based store not allowed";
4208 else if (Ro != FAIL)
4210 inst.error = "Invalid base register for register offset";
4215 inst.instruction = T_OPCODE_LDR_PC;
4216 else if (load_store == THUMB_LOAD)
4217 inst.instruction = T_OPCODE_LDR_SP;
4219 inst.instruction = T_OPCODE_STR_SP;
4221 inst.instruction |= Rd << 8;
4222 if (inst.reloc.exp.X_op == O_constant)
4224 unsigned offset = inst.reloc.exp.X_add_number;
4226 if (offset & ~0x3fc)
4228 inst.error = "invalid offset";
4232 inst.instruction |= offset >> 2;
4235 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4239 inst.error = "invalid base register in load/store";
4242 else if (Ro == FAIL)
4244 /* Immediate offset */
4245 if (size == THUMB_WORD)
4246 inst.instruction = (load_store == THUMB_LOAD
4247 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4248 else if (size == THUMB_HALFWORD)
4249 inst.instruction = (load_store == THUMB_LOAD
4250 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4252 inst.instruction = (load_store == THUMB_LOAD
4253 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4255 inst.instruction |= Rd | (Rb << 3);
4257 if (inst.reloc.exp.X_op == O_constant)
4259 unsigned offset = inst.reloc.exp.X_add_number;
4261 if (offset & ~(0x1f << size))
4263 inst.error = "Invalid offset";
4266 inst.instruction |= (offset >> size) << 6;
4269 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4273 /* Register offset */
4274 if (size == THUMB_WORD)
4275 inst.instruction = (load_store == THUMB_LOAD
4276 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4277 else if (size == THUMB_HALFWORD)
4278 inst.instruction = (load_store == THUMB_LOAD
4279 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4281 inst.instruction = (load_store == THUMB_LOAD
4282 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4284 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4299 /* Handle the Format 4 instructions that do not have equivalents in other
4300 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4311 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4314 if (skip_past_comma (&str) == FAIL
4315 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4318 inst.error = bad_args;
4322 if (skip_past_comma (&str) != FAIL)
4324 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4325 (It isn't allowed for CMP either, but that isn't handled by this
4327 if (inst.instruction == T_OPCODE_TST
4328 || inst.instruction == T_OPCODE_CMN
4329 || inst.instruction == T_OPCODE_NEG
4330 || inst.instruction == T_OPCODE_MVN)
4332 inst.error = bad_args;
4336 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4341 inst.error = "dest and source1 one must be the same register";
4347 if (inst.instruction == T_OPCODE_MUL
4349 as_tsktsk ("Rs and Rd must be different in MUL");
4351 inst.instruction |= Rd | (Rs << 3);
4359 thumb_add_sub (str, 0);
4366 thumb_shift (str, THUMB_ASR);
4373 if (my_get_expression (&inst.reloc.exp, &str))
4375 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4376 inst.reloc.pc_rel = 1;
4384 if (my_get_expression (&inst.reloc.exp, &str))
4386 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4387 inst.reloc.pc_rel = 1;
4395 if (my_get_expression (&inst.reloc.exp, &str))
4397 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4398 inst.reloc.pc_rel = 1;
4411 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4414 /* This sets THUMB_H2 from the top bit of reg. */
4415 inst.instruction |= reg << 3;
4417 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4418 should cause the alignment to be checked once it is known. This is
4419 because BX PC only works if the instruction is word aligned. */
4428 thumb_mov_compare (str, THUMB_COMPARE);
4441 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4445 as_warn ("Inserted missing '!': load/store multiple always writes back base register");
4449 if (skip_past_comma (&str) == FAIL
4450 || (range = reg_list (&str)) == FAIL)
4453 inst.error = bad_args;
4457 if (inst.reloc.type != BFD_RELOC_NONE)
4459 /* This really doesn't seem worth it. */
4460 inst.reloc.type = BFD_RELOC_NONE;
4461 inst.error = "Expression too complex";
4467 inst.error = "only lo-regs valid in load/store multiple";
4471 inst.instruction |= (Rb << 8) | range;
4479 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4486 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
4493 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
4505 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4506 || skip_past_comma (&str) == FAIL
4508 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4509 || skip_past_comma (&str) == FAIL
4510 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4514 inst.error = "Syntax: ldrs[b] Rd, [Rb, Ro]";
4518 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4526 thumb_shift (str, THUMB_LSL);
4533 thumb_shift (str, THUMB_LSR);
4540 thumb_mov_compare (str, THUMB_MOVE);
4552 if ((range = reg_list (&str)) == FAIL)
4555 inst.error = bad_args;
4559 if (inst.reloc.type != BFD_RELOC_NONE)
4561 /* This really doesn't seem worth it. */
4562 inst.reloc.type = BFD_RELOC_NONE;
4563 inst.error = "Expression too complex";
4569 if ((inst.instruction == T_OPCODE_PUSH
4570 && (range & ~0xff) == 1 << REG_LR)
4571 || (inst.instruction == T_OPCODE_POP
4572 && (range & ~0xff) == 1 << REG_PC))
4574 inst.instruction |= THUMB_PP_PC_LR;
4579 inst.error = "invalid register list to push/pop instruction";
4584 inst.instruction |= range;
4592 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
4599 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
4606 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
4613 thumb_add_sub (str, 1);
4623 if (my_get_expression (&inst.reloc.exp, &str))
4626 inst.reloc.type = BFD_RELOC_ARM_SWI;
4635 /* This is a pseudo-op of the form "adr rd, label" to be converted
4636 into a relative address of the form "add rd, pc, #label-.-4" */
4640 if (reg_required_here (&str, 4) == FAIL /* Store Rd in temporary location inside instruction. */
4641 || skip_past_comma (&str) == FAIL
4642 || my_get_expression (&inst.reloc.exp, &str))
4645 inst.error = bad_args;
4649 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4650 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust */
4651 inst.reloc.pc_rel = 1;
4652 inst.instruction |= REG_PC; /* Rd is already placed into the instruction */
4660 int len = strlen (reg_table[entry].name) + 2;
4661 char *buf = (char *) xmalloc (len);
4662 char *buf2 = (char *) xmalloc (len);
4665 #ifdef REGISTER_PREFIX
4666 buf[i++] = REGISTER_PREFIX;
4669 strcpy (buf + i, reg_table[entry].name);
4671 for (i = 0; buf[i]; i++)
4672 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
4676 hash_insert (arm_reg_hsh, buf, (PTR) ®_table[entry]);
4677 hash_insert (arm_reg_hsh, buf2, (PTR) ®_table[entry]);
4681 insert_reg_alias (str, regnum)
4685 struct reg_entry *new =
4686 (struct reg_entry *)xmalloc (sizeof (struct reg_entry));
4687 char *name = xmalloc (strlen (str) + 1);
4691 new->number = regnum;
4693 hash_insert (arm_reg_hsh, name, (PTR) new);
4697 set_constant_flonums ()
4701 for (i = 0; i < NUM_FLOAT_VALS; i++)
4702 if (atof_ieee ((char *)fp_const[i], 'x', fp_values[i]) == NULL)
4711 if ((arm_ops_hsh = hash_new ()) == NULL
4712 || (arm_tops_hsh = hash_new ()) == NULL
4713 || (arm_cond_hsh = hash_new ()) == NULL
4714 || (arm_shift_hsh = hash_new ()) == NULL
4715 || (arm_reg_hsh = hash_new ()) == NULL
4716 || (arm_psr_hsh = hash_new ()) == NULL)
4717 as_fatal ("Virtual memory exhausted");
4719 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
4720 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
4721 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
4722 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
4723 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
4724 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
4725 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
4726 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
4727 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
4728 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
4730 for (i = 0; reg_table[i].name; i++)
4733 set_constant_flonums ();
4737 unsigned int flags = 0;
4739 /* Set the flags in the private structure */
4740 if (uses_apcs_26) flags |= F_APCS26;
4741 if (support_interwork) flags |= F_INTERWORK;
4742 if (uses_apcs_float) flags |= F_APCS_FLOAT;
4743 if (pic_code) flags |= F_PIC;
4745 bfd_set_private_flags (stdoutput, flags);
4752 /* Record the CPU type as well */
4753 switch (cpu_variant & ARM_CPU_MASK)
4756 mach = bfd_mach_arm_2;
4759 case ARM_3: /* also ARM_250 */
4760 mach = bfd_mach_arm_2a;
4764 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined */
4765 mach = bfd_mach_arm_4;
4768 case ARM_7: /* also ARM_6 */
4769 mach = bfd_mach_arm_3;
4773 /* Catch special cases */
4774 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
4776 if (cpu_variant & ARM_THUMB)
4777 mach = bfd_mach_arm_4T;
4778 else if ((cpu_variant & ARM_ARCHv4) == ARM_ARCHv4)
4779 mach = bfd_mach_arm_4;
4780 else if (cpu_variant & ARM_LONGMUL)
4781 mach = bfd_mach_arm_3M;
4784 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
4788 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
4789 for use in the a.out file, and stores them in the array pointed to by buf.
4790 This knows about the endian-ness of the target machine and does
4791 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
4792 2 (short) and 4 (long) Floating numbers are put out as a series of
4793 LITTLENUMS (shorts, here at least)
4796 md_number_to_chars (buf, val, n)
4801 if (target_big_endian)
4802 number_to_chars_bigendian (buf, val, n);
4804 number_to_chars_littleendian (buf, val, n);
4808 md_chars_to_number (buf, n)
4813 unsigned char *where = (unsigned char *) buf;
4815 if (target_big_endian)
4820 result |= (*where++ & 255);
4828 result |= (where[n] & 255);
4835 /* Turn a string in input_line_pointer into a floating point constant
4836 of type TYPE, and store the appropriate bytes in *litP. The number
4837 of LITTLENUMS emitted is stored in *sizeP . An error message is
4838 returned, or NULL on OK.
4840 Note that fp constants aren't represent in the normal way on the ARM.
4841 In big endian mode, things are as expected. However, in little endian
4842 mode fp constants are big-endian word-wise, and little-endian byte-wise
4843 within the words. For example, (double) 1.1 in big endian mode is
4844 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
4845 the byte sequence 99 99 f1 3f 9a 99 99 99.
4847 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
4850 md_atof (type, litP, sizeP)
4856 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4888 return "Bad call to MD_ATOF()";
4891 t = atof_ieee (input_line_pointer, type, words);
4893 input_line_pointer = t;
4896 if (target_big_endian)
4898 for (i = 0; i < prec; i++)
4900 md_number_to_chars (litP, (valueT) words[i], 2);
4906 /* For a 4 byte float the order of elements in `words' is 1 0. For an
4907 8 byte float the order is 1 0 3 2. */
4908 for (i = 0; i < prec; i += 2)
4910 md_number_to_chars (litP, (valueT) words[i + 1], 2);
4911 md_number_to_chars (litP + 2, (valueT) words[i], 2);
4919 /* We have already put the pipeline compensation in the instruction */
4922 md_pcrel_from (fixP)
4925 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
4926 && fixP->fx_subsy == NULL)
4927 return 0; /* HACK */
4929 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
4931 /* PC relative addressing on the Thumb is slightly odd
4932 as the bottom two bits of the PC are forced to zero
4933 for the calculation */
4934 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
4937 return fixP->fx_where + fixP->fx_frag->fr_address;
4940 /* Round up a section size to the appropriate boundary. */
4942 md_section_align (segment, size)
4946 /* Round all sects to multiple of 4 */
4947 return (size + 3) & ~3;
4950 /* We have no need to default values of symbols. */
4954 md_undefined_symbol (name)
4960 /* arm_reg_parse () := if it looks like a register, return its token and
4961 advance the pointer. */
4965 register char **ccp;
4970 struct reg_entry *reg;
4972 #ifdef REGISTER_PREFIX
4973 if (*start != REGISTER_PREFIX)
4978 #ifdef OPTIONAL_REGISTER_PREFIX
4979 if (*p == OPTIONAL_REGISTER_PREFIX)
4983 if (!isalpha (*p) || !is_name_beginner (*p))
4987 while (isalpha (c) || isdigit (c) || c == '_')
4991 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5005 register char **ccp;
5009 CONST struct asm_psr *psr;
5013 while (isalpha (c) || c == '_')
5017 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
5030 md_apply_fix3 (fixP, val, seg)
5035 offsetT value = *val;
5039 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5040 arm_fix_data *arm_data = (arm_fix_data *) fixP->tc_fix_data;
5042 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5044 /* Note whether this will delete the relocation. */
5045 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5046 if ((fixP->fx_addsy == 0 || fixP->fx_addsy->sy_value.X_op == O_constant)
5049 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5053 /* If this symbol is in a different section then we need to leave it for
5054 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5055 so we have to undo it's effects here. */
5058 if (S_IS_DEFINED (fixP->fx_addsy)
5059 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5061 if (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH)
5064 value += md_pcrel_from (fixP);
5068 fixP->fx_addnumber = value; /* Remember value for emit_reloc */
5070 switch (fixP->fx_r_type)
5072 case BFD_RELOC_ARM_IMMEDIATE:
5073 newval = validate_immediate (value);
5074 temp = md_chars_to_number (buf, INSN_SIZE);
5076 /* If the instruction will fail, see if we can fix things up by
5077 changing the opcode. */
5079 && (newval = negate_data_op (&temp, value)) == FAIL)
5081 as_bad_where (fixP->fx_file, fixP->fx_line,
5082 "invalid constant after fixup\n");
5086 newval |= (temp & 0xfffff000);
5087 md_number_to_chars (buf, newval, INSN_SIZE);
5090 case BFD_RELOC_ARM_OFFSET_IMM:
5092 if ((value = validate_offset_imm (value, 0)) == FAIL)
5094 as_bad ("bad immediate value for offset (%d)", val);
5100 newval = md_chars_to_number (buf, INSN_SIZE);
5101 newval &= 0xff7ff000;
5102 newval |= value | (sign ? INDEX_UP : 0);
5103 md_number_to_chars (buf, newval, INSN_SIZE);
5106 case BFD_RELOC_ARM_OFFSET_IMM8:
5107 case BFD_RELOC_ARM_HWLITERAL:
5109 if ((value = validate_offset_imm (value, 1)) == FAIL)
5111 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5112 as_bad_where (fixP->fx_file, fixP->fx_line,
5113 "invalid literal constant: pool needs to be closer\n");
5115 as_bad ("bad immediate value for offset (%d)", value);
5122 newval = md_chars_to_number (buf, INSN_SIZE);
5123 newval &= 0xff7ff0f0;
5124 newval |= ((value >> 4) << 8) | value & 0xf | (sign ? INDEX_UP : 0);
5125 md_number_to_chars (buf, newval, INSN_SIZE);
5128 case BFD_RELOC_ARM_LITERAL:
5133 if ((value = validate_offset_imm (value, 0)) == FAIL)
5135 as_bad_where (fixP->fx_file, fixP->fx_line,
5136 "invalid literal constant: pool needs to be closer\n");
5140 newval = md_chars_to_number (buf, INSN_SIZE);
5141 newval &= 0xff7ff000;
5142 newval |= value | (sign ? INDEX_UP : 0);
5143 md_number_to_chars (buf, newval, INSN_SIZE);
5146 case BFD_RELOC_ARM_SHIFT_IMM:
5147 newval = md_chars_to_number (buf, INSN_SIZE);
5148 if (((unsigned long) value) > 32
5150 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5152 as_bad_where (fixP->fx_file, fixP->fx_line,
5153 "shift expression is too large");
5158 newval &= ~0x60; /* Shifts of zero must be done as lsl */
5159 else if (value == 32)
5161 newval &= 0xfffff07f;
5162 newval |= (value & 0x1f) << 7;
5163 md_number_to_chars (buf, newval , INSN_SIZE);
5166 case BFD_RELOC_ARM_SWI:
5167 if (arm_data->thumb_mode)
5169 if (((unsigned long) value) > 0xff)
5170 as_bad_where (fixP->fx_file, fixP->fx_line,
5171 "Invalid swi expression");
5172 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5174 md_number_to_chars (buf, newval, THUMB_SIZE);
5178 if (((unsigned long) value) > 0x00ffffff)
5179 as_bad_where (fixP->fx_file, fixP->fx_line,
5180 "Invalid swi expression");
5181 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5183 md_number_to_chars (buf, newval , INSN_SIZE);
5187 case BFD_RELOC_ARM_MULTI:
5188 if (((unsigned long) value) > 0xffff)
5189 as_bad_where (fixP->fx_file, fixP->fx_line,
5190 "Invalid expression in load/store multiple");
5191 newval = value | md_chars_to_number (buf, INSN_SIZE);
5192 md_number_to_chars (buf, newval, INSN_SIZE);
5195 case BFD_RELOC_ARM_PCREL_BRANCH:
5196 value = (value >> 2) & 0x00ffffff;
5197 newval = md_chars_to_number (buf, INSN_SIZE);
5198 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5199 newval = value | (newval & 0xff000000);
5200 md_number_to_chars (buf, newval, INSN_SIZE);
5203 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
5204 newval = md_chars_to_number (buf, THUMB_SIZE);
5206 addressT diff = (newval & 0xff) << 1;
5211 if ((value & 0x100) && ((value & ~0xff) != ~0xff))
5212 as_bad_where (fixP->fx_file, fixP->fx_line,
5213 "Branch out of range");
5214 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5216 md_number_to_chars (buf, newval, THUMB_SIZE);
5219 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* unconditional branch */
5220 newval = md_chars_to_number (buf, THUMB_SIZE);
5222 addressT diff = (newval & 0x7ff) << 1;
5227 if ((value & 0x800) && ((value & ~0x7ff) != ~0x7ff))
5228 as_bad_where (fixP->fx_file, fixP->fx_line,
5229 "Branch out of range");
5230 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5232 md_number_to_chars (buf, newval, THUMB_SIZE);
5235 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5236 newval = md_chars_to_number (buf, THUMB_SIZE);
5241 newval2 = md_chars_to_number (buf + 2, THUMB_SIZE);
5242 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5243 if (diff & 0x400000)
5246 if ((value & 0x400000) && ((value & ~0x3fffff) != ~0x3fffff))
5247 as_bad_where (fixP->fx_file, fixP->fx_line,
5248 "Branch with link out of range");
5250 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5251 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5252 md_number_to_chars (buf, newval, THUMB_SIZE);
5253 md_number_to_chars (buf + 2, newval2, THUMB_SIZE);
5258 if (fixP->fx_done || fixP->fx_pcrel)
5259 md_number_to_chars (buf, value, 1);
5263 if (fixP->fx_done || fixP->fx_pcrel)
5264 md_number_to_chars (buf, value, 2);
5269 if (fixP->fx_done || fixP->fx_pcrel)
5270 md_number_to_chars (buf, value, 4);
5273 case BFD_RELOC_ARM_CP_OFF_IMM:
5275 if (value < -1023 || value > 1023 || (value & 3))
5276 as_bad_where (fixP->fx_file, fixP->fx_line,
5277 "Illegal value for co-processor offset");
5280 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5281 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5282 md_number_to_chars (buf, newval , INSN_SIZE);
5285 case BFD_RELOC_ARM_THUMB_OFFSET:
5286 newval = md_chars_to_number (buf, THUMB_SIZE);
5287 /* Exactly what ranges, and where the offset is inserted depends on
5288 the type of instruction, we can establish this from the top 4 bits */
5289 switch (newval >> 12)
5291 case 4: /* PC load */
5292 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5293 forced to zero for these loads, so we will need to round
5294 up the offset if the instruction address is not word
5295 aligned (since the final address produced must be, and
5296 we can only describe word-aligned immediate offsets). */
5298 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
5299 as_bad_where (fixP->fx_file, fixP->fx_line,
5300 "Invalid offset, target not word aligned (0x%08X)",
5301 (unsigned int)(fixP->fx_frag->fr_address + fixP->fx_where + value));
5303 if ((value + 2) & ~0x3fe)
5304 as_bad_where (fixP->fx_file, fixP->fx_line,
5307 /* Round up, since pc will be rounded down. */
5308 newval |= (value + 2) >> 2;
5311 case 9: /* SP load/store */
5313 as_bad_where (fixP->fx_file, fixP->fx_line,
5315 newval |= value >> 2;
5318 case 6: /* Word load/store */
5320 as_bad_where (fixP->fx_file, fixP->fx_line,
5322 newval |= value << 4; /* 6 - 2 */
5325 case 7: /* Byte load/store */
5327 as_bad_where (fixP->fx_file, fixP->fx_line,
5329 newval |= value << 6;
5332 case 8: /* Halfword load/store */
5334 as_bad_where (fixP->fx_file, fixP->fx_line,
5336 newval |= value << 5; /* 6 - 1 */
5340 as_bad_where (fixP->fx_file, fixP->fx_line,
5341 "Unable to process relocation for thumb opcode: %x", newval);
5344 md_number_to_chars (buf, newval, THUMB_SIZE);
5347 case BFD_RELOC_ARM_THUMB_ADD:
5348 /* This is a complicated relocation, since we use it for all of
5349 the following immediate relocations:
5352 9bit ADD/SUB SP word-aligned
5353 10bit ADD PC/SP word-aligned
5355 The type of instruction being processed is encoded in the
5361 newval = md_chars_to_number (buf, THUMB_SIZE);
5363 int rd = (newval >> 4) & 0xf;
5364 int rs = newval & 0xf;
5365 int subtract = newval & 0x8000;
5370 as_bad_where (fixP->fx_file, fixP->fx_line,
5371 "Invalid immediate for stack address calculation");
5372 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5373 newval |= value >> 2;
5375 else if (rs == REG_PC || rs == REG_SP)
5379 as_bad_where (fixP->fx_file, fixP->fx_line,
5380 "Invalid immediate for address calculation (value = 0x%08X)", value);
5381 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
5383 newval |= value >> 2;
5388 as_bad_where (fixP->fx_file, fixP->fx_line,
5389 "Invalid 8bit immediate");
5390 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5391 newval |= (rd << 8) | value;
5396 as_bad_where (fixP->fx_file, fixP->fx_line,
5397 "Invalid 3bit immediate");
5398 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5399 newval |= rd | (rs << 3) | (value << 6);
5402 md_number_to_chars (buf, newval , THUMB_SIZE);
5405 case BFD_RELOC_ARM_THUMB_IMM:
5406 newval = md_chars_to_number (buf, THUMB_SIZE);
5407 switch (newval >> 11)
5409 case 0x04: /* 8bit immediate MOV */
5410 case 0x05: /* 8bit immediate CMP */
5411 if (value < 0 || value > 255)
5412 as_bad_where (fixP->fx_file, fixP->fx_line,
5413 "Invalid immediate: %d is too large", value);
5420 md_number_to_chars (buf, newval , THUMB_SIZE);
5423 case BFD_RELOC_ARM_THUMB_SHIFT:
5424 /* 5bit shift value (0..31) */
5425 if (value < 0 || value > 31)
5426 as_bad_where (fixP->fx_file, fixP->fx_line,
5427 "Illegal Thumb shift value: %d", value);
5428 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
5429 newval |= value << 6;
5430 md_number_to_chars (buf, newval , THUMB_SIZE);
5433 case BFD_RELOC_NONE:
5435 as_bad_where (fixP->fx_file, fixP->fx_line,
5436 "Bad relocation fixup type (%d)\n", fixP->fx_r_type);
5442 /* Translate internal representation of relocation info to BFD target
5445 tc_gen_reloc (section, fixp)
5450 bfd_reloc_code_real_type code;
5452 reloc = (arelent *) xmalloc (sizeof (arelent));
5454 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
5455 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5457 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5458 if (fixp->fx_pcrel == 0)
5459 reloc->addend = fixp->fx_offset;
5461 reloc->addend = fixp->fx_offset = reloc->address;
5463 switch (fixp->fx_r_type)
5468 code = BFD_RELOC_8_PCREL;
5475 code = BFD_RELOC_16_PCREL;
5482 code = BFD_RELOC_32_PCREL;
5486 case BFD_RELOC_ARM_PCREL_BRANCH:
5488 case BFD_RELOC_THUMB_PCREL_BRANCH9:
5489 case BFD_RELOC_THUMB_PCREL_BRANCH12:
5490 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5491 code = fixp->fx_r_type;
5494 case BFD_RELOC_ARM_LITERAL:
5495 case BFD_RELOC_ARM_HWLITERAL:
5496 /* If this is called then the a literal has been referenced across
5497 a section boundry - possibly due to an implicit dump */
5498 as_bad_where (fixp->fx_file, fixp->fx_line,
5499 "Literal referenced across section boundry (Implicit dump?)");
5505 switch (fixp->fx_r_type)
5507 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
5508 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
5509 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
5510 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
5511 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
5512 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
5513 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
5514 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
5515 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
5516 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
5517 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
5518 default: type = "<unknown>"; break;
5520 as_bad_where (fixp->fx_file, fixp->fx_line,
5521 "Can not represent %s relocation in this object file format (%d)",
5522 type, fixp->fx_pcrel);
5527 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
5529 if (reloc->howto == NULL)
5531 as_bad_where (fixp->fx_file, fixp->fx_line,
5532 "Can not represent %s relocation in this object file format",
5533 bfd_get_reloc_code_name (code));
5540 CONST int md_short_jump_size = 4;
5541 CONST int md_long_jump_size = 4;
5543 /* These should never be called on the arm */
5545 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5547 addressT from_addr, to_addr;
5551 as_fatal ("md_create_long_jump\n");
5555 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5557 addressT from_addr, to_addr;
5561 as_fatal ("md_create_short_jump\n");
5565 md_estimate_size_before_relax (fragP, segtype)
5569 as_fatal ("md_estimate_size_before_relax\n");
5581 as_bad (inst.error);
5585 to = frag_more (inst.size);
5586 if (thumb_mode && (inst.size > THUMB_SIZE))
5588 assert (inst.size == (2 * THUMB_SIZE));
5589 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
5590 md_number_to_chars (to + 2, inst.instruction, THUMB_SIZE);
5593 md_number_to_chars (to, inst.instruction, inst.size);
5595 if (inst.reloc.type != BFD_RELOC_NONE)
5596 fix_new_arm (frag_now, to - frag_now->fr_literal,
5597 inst.size, &inst.reloc.exp, inst.reloc.pc_rel,
5608 char *p, *q, *start;
5610 /* Align the instruction */
5611 /* this may not be the right thing to do but ... */
5612 /* arm_align (2, 0); */
5613 listing_prev_line (); /* Defined in listing.h */
5615 /* Align the previous label if needed */
5616 if (last_label_seen != NULL)
5618 last_label_seen->sy_frag = frag_now;
5619 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
5620 S_SET_SEGMENT (last_label_seen, now_seg);
5623 memset (&inst, '\0', sizeof (inst));
5624 inst.reloc.type = BFD_RELOC_NONE;
5627 str++; /* Skip leading white space */
5629 /* scan up to the end of the op-code, which must end in white space or
5631 for (start = p = str; *p != '\0'; p++)
5637 as_bad ("No operator -- statement `%s'\n", str);
5643 CONST struct thumb_opcode *opcode;
5647 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
5651 inst.instruction = opcode->value;
5652 inst.size = opcode->size;
5653 (*opcode->parms)(p);
5654 output_inst (start);
5660 CONST struct asm_opcode *opcode;
5662 inst.size = INSN_SIZE;
5663 /* p now points to the end of the opcode, probably white space, but we
5664 have to break the opcode up in case it contains condionals and flags;
5665 keep trying with progressively smaller basic instructions until one
5666 matches, or we run out of opcode. */
5667 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
5668 for (; q != str; q--)
5672 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
5674 if (opcode && opcode->template)
5676 unsigned long flag_bits = 0;
5679 /* Check that this instruction is supported for this CPU */
5680 if ((opcode->variants & cpu_variant) == 0)
5683 inst.instruction = opcode->value;
5684 if (q == p) /* Just a simple opcode */
5686 if (opcode->comp_suffix != 0)
5687 as_bad ("Opcode `%s' must have suffix from <%s>\n", str,
5688 opcode->comp_suffix);
5691 inst.instruction |= COND_ALWAYS;
5692 (*opcode->parms)(q, 0);
5694 output_inst (start);
5698 /* Now check for a conditional */
5702 CONST struct asm_cond *cond;
5706 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
5710 if (cond->value == 0xf0000000)
5712 "Warning: Use of the 'nv' conditional is deprecated\n");
5714 inst.instruction |= cond->value;
5718 inst.instruction |= COND_ALWAYS;
5721 inst.instruction |= COND_ALWAYS;
5723 /* if there is a compulsory suffix, it should come here, before
5724 any optional flags. */
5725 if (opcode->comp_suffix)
5727 CONST char *s = opcode->comp_suffix;
5739 as_bad ("Opcode `%s' must have suffix from <%s>\n", str,
5740 opcode->comp_suffix);
5747 /* The remainder, if any should now be flags for the instruction;
5748 Scan these checking each one found with the opcode. */
5752 CONST struct asm_flg *flag = opcode->flags;
5761 for (flagno = 0; flag[flagno].template; flagno++)
5763 if (! strcmp (r, flag[flagno].template))
5765 flag_bits |= flag[flagno].set_bits;
5771 if (! flag[flagno].template)
5778 (*opcode->parms) (p, flag_bits);
5779 output_inst (start);
5788 /* It wasn't an instruction, but it might be a register alias of the form
5798 if (*q && !strncmp (q, ".req ", 4))
5801 char * copy_of_str = str;
5808 for (r = q; *r != '\0'; r++)
5818 regnum = arm_reg_parse (& q);
5821 reg = arm_reg_parse (& str);
5827 insert_reg_alias (str, regnum);
5831 as_warn ("register '%s' does not exist\n", q);
5834 else if (regnum != FAIL)
5837 as_warn ("ignoring redefinition of register alias '%s'", copy_of_str );
5839 /* Do not warn abpout redefinitions to the same alias. */
5842 as_warn ("ignoring redefinition of register alias '%s' to non-existant register '%s'",
5846 as_warn ("ignoring incomplete .req pseuso op");
5853 as_bad ("bad instruction `%s'", start);
5858 * Invocation line includes a switch not recognized by the base assembler.
5859 * See if it's a processor-specific option. These are:
5860 * Cpu variants, the arm part is optional:
5861 * -m[arm]1 Currently not supported.
5862 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
5863 * -m[arm]3 Arm 3 processor
5864 * -m[arm]6, Arm 6 processors
5865 * -m[arm]7[t][[d]m] Arm 7 processors
5866 * -mall All (except the ARM1)
5868 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
5869 * -mfpe-old (No float load/store multiples)
5870 * -mno-fpu Disable all floating point instructions
5871 * Run-time endian selection:
5872 * -EB big endian cpu
5873 * -EL little endian cpu
5874 * ARM Procedure Calling Standard:
5875 * -mapcs-32 32 bit APCS
5876 * -mapcs-26 26 bit APCS
5877 * -mapcs-float Pass floats in float regs
5878 * -mapcs-reentrant Position independent code
5879 * -mthumb-interwork Code supports Arm/Thumb interworking
5882 CONST char *md_shortopts = "m:";
5883 struct option md_longopts[] =
5885 #ifdef ARM_BI_ENDIAN
5886 #define OPTION_EB (OPTION_MD_BASE + 0)
5887 {"EB", no_argument, NULL, OPTION_EB},
5888 #define OPTION_EL (OPTION_MD_BASE + 1)
5889 {"EL", no_argument, NULL, OPTION_EL},
5891 {NULL, no_argument, NULL, 0}
5893 size_t md_longopts_size = sizeof (md_longopts);
5896 md_parse_option (c, arg)
5904 #ifdef ARM_BI_ENDIAN
5906 target_big_endian = 1;
5909 target_big_endian = 0;
5917 if (! strcmp (str, "fpa10"))
5918 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
5919 else if (! strcmp (str, "fpa11"))
5920 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
5921 else if (! strcmp (str, "fpe-old"))
5922 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
5928 if (! strcmp (str, "no-fpu"))
5929 cpu_variant &= ~FPU_ALL;
5933 /* Limit assembler to generating only Thumb instructions: */
5934 if (! strcmp (str, "thumb"))
5936 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
5937 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
5940 else if (! strcmp (str, "thumb-interwork"))
5942 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB | ARM_ARCHv4;
5944 support_interwork = true;
5952 if (! strcmp (str, "all"))
5954 cpu_variant = ARM_ALL | FPU_ALL;
5958 if (! strncmp (str, "apcs-", 5))
5960 /* GCC passes on all command line options starting "-mapcs-..."
5961 to us, so we must parse them here. */
5965 if (! strcmp (str, "32"))
5967 uses_apcs_26 = false;
5970 else if (! strcmp (str, "26"))
5972 uses_apcs_26 = true;
5975 else if (! strcmp (str, "frame"))
5977 /* Stack frames are being generated - does not affect
5981 else if (! strcmp (str, "stack-check"))
5983 /* Stack checking is being performed - does not affect
5984 linkage, but does require that the functions
5985 __rt_stkovf_split_small and __rt_stkovf_split_big be
5986 present in the final link. */
5990 else if (! strcmp (str, "float"))
5992 /* Floating point arguments are being passed in the floating
5993 point registers. This does affect linking, since this
5994 version of the APCS is incompatible with the version that
5995 passes floating points in the integer registers. */
5997 uses_apcs_float = true;
6000 else if (! strcmp (str, "reentrant"))
6002 /* Reentrant code has been generated. This does affect
6003 linking, since there is no point in linking reentrant/
6004 position independent code with absolute position code. */
6009 as_bad ("Unrecognised APCS switch -m%s", arg);
6013 /* Strip off optional "arm" */
6014 if (! strncmp (str, "arm", 3))
6020 if (! strcmp (str, "1"))
6021 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6027 if (! strcmp (str, "2"))
6028 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6029 else if (! strcmp (str, "250"))
6030 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6036 if (! strcmp (str, "3"))
6037 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6043 if (! strcmp (str, "strongarm") || ! strcmp (str, "strongarm110"))
6044 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCHv4 | ARM_LONGMUL;
6050 if (! strcmp (str, "8"))
6051 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCHv4 | ARM_LONGMUL;
6057 if (! strcmp (str, "6"))
6058 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6064 str++; /* eat the '7' */
6065 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6071 cpu_variant |= (ARM_THUMB | ARM_ARCHv4);
6075 cpu_variant |= ARM_LONGMUL;
6078 case 'f': /* fe => fp enabled cpu. */
6084 case 'c': /* Unknown */
6085 case 'd': /* debug */
6086 case 'i': /* embedded ice */
6087 /* Included for completeness in ARM processor naming. */
6097 /* Select variant based on architecture rather than processor */
6103 case 'a': cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3; break;
6104 case 0: cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2; break;
6105 default: as_bad ("Invalid architecture variant -m%s", arg); break;
6110 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6114 case 'm': cpu_variant |= ARM_LONGMUL; break;
6116 default: as_bad ("Invalid architecture variant -m%s", arg); break;
6121 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCHv4;
6125 case 't': cpu_variant |= ARM_THUMB; break;
6127 default: as_bad ("Invalid architecture variant -m%s", arg); break;
6132 as_bad ("Invalid architecture variant -m%s", arg);
6139 as_bad ("Invalid processor variant -m%s", arg);
6157 "-m[arm][<processor name>] select processor variant\n\
6158 -m[arm]v[2|2a|3|3m|4|4t] select architecture variant\n\
6159 -mthumb\t\t\tonly allow Thumb instructions\n\
6160 -mthumb-interwork\tmark the assembled code as supporting interworking\n\
6161 -mall\t\t\tallow any instruction\n\
6162 -mfpa10, -mfpa11\tselect floating point architecture\n\
6163 -mfpe-old\t\tdon't allow floating-point multiple instructions\n\
6164 -mno-fpu\t\tdon't allow any floating-point instructions.\n");
6167 "-mapcs-32, -mapcs-26\tspecify which ARM Procedure Calling Standard is in use\n");
6169 "-mapcs-float\t\tfloating point args are passed in floating point regs\n");
6171 "-mapcs-reentrant\tposition independent/reentrant code has been generated\n");
6173 #ifdef ARM_BI_ENDIAN
6175 "-EB\t\t\tassemble code for a big endian cpu\n\
6176 -EL\t\t\tassemble code for a little endian cpu\n");
6180 /* We need to be able to fix up arbitrary expressions in some statements.
6181 This is so that we can handle symbols that are an arbitrary distance from
6182 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6183 which returns part of an address in a form which will be valid for
6184 a data instruction. We do this by pushing the expression into a symbol
6185 in the expr_section, and creating a fix for that. */
6188 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
6197 arm_fix_data *arm_data;
6205 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
6209 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
6214 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6215 arm_data = (arm_fix_data *) obstack_alloc (¬es, sizeof (arm_fix_data));
6216 new_fix->tc_fix_data = (PTR) arm_data;
6217 arm_data->thumb_mode = thumb_mode;
6222 /* A good place to do this, although this was probably not intended
6223 * for this kind of use. We need to dump the literal pool before
6224 * references are made to a null symbol pointer. */
6226 arm_after_pass_hook ()
6228 if (current_poolP != NULL)
6230 subseg_set (text_section, 0); /* Put it at the end of text section */
6232 listing_prev_line ();
6237 arm_start_line_hook ()
6239 last_label_seen = NULL;
6243 arm_frob_label (sym)
6246 last_label_seen = sym;
6247 ARM_SET_THUMB (sym, thumb_mode);
6248 ARM_SET_INTERWORK (sym, support_interwork);
6250 if (label_is_thumb_function_name)
6252 /* When the address of a Thumb function is taken the bottom
6253 bit of that address should be set. This will allow
6254 interworking between Arm and Thumb functions to work
6257 THUMB_SET_FUNC (sym, 1);
6259 label_is_thumb_function_name = false;
6263 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6267 arm_adjust_symtab ()
6272 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6274 if (ARM_IS_THUMB (sym))
6276 if (THUMB_IS_FUNC (sym))
6278 /* Mark the symbol as a Thumb function. */
6279 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
6280 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
6281 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
6282 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
6283 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
6285 as_bad ("%s: unexpected function type: %d", S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
6287 else switch (S_GET_STORAGE_CLASS (sym))
6290 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
6293 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
6296 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
6298 default: /* do nothing */
6303 if (ARM_IS_INTERWORK (sym))
6305 coffsymbol(sym->bsym)->native->u.syment.n_flags = 0xFF;
6314 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
6316 *input_line_pointer = '/';
6317 input_line_pointer += 5;
6318 *input_line_pointer = 0;
6325 arm_canonicalize_symbol_name (name)
6330 if (thumb_mode && (len = strlen (name)) > 5
6331 && ! strcmp (name + len - 5, "/data"))
6333 *(name + len - 5) = 0;