1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
40 #include "opcode/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
60 symbolS * table_entry;
61 symbolS * personality_routine;
62 int personality_index;
63 /* The segment containing the function. */
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes;
70 /* The number of bytes pushed to the stack. */
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
80 /* Nonzero if an unwind_setfp directive has been seen. */
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored:1;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency = 0;
100 /* Types of processor to assemble for. */
101 #define ARM_1 ARM_ARCH_V1
102 #define ARM_2 ARM_ARCH_V2
103 #define ARM_3 ARM_ARCH_V2S
104 #define ARM_250 ARM_ARCH_V2S
105 #define ARM_6 ARM_ARCH_V3
106 #define ARM_7 ARM_ARCH_V3
107 #define ARM_8 ARM_ARCH_V4
108 #define ARM_9 ARM_ARCH_V4T
109 #define ARM_STRONG ARM_ARCH_V4
110 #define ARM_CPU_MASK 0x0000000f /* XXX? */
113 #if defined __XSCALE__
114 #define CPU_DEFAULT (ARM_ARCH_XSCALE)
116 #if defined __thumb__
117 #define CPU_DEFAULT (ARM_ARCH_V5T)
124 # define FPU_DEFAULT FPU_ARCH_FPA
125 # elif defined (TE_NetBSD)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
129 /* Legacy a.out format. */
130 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
132 # elif defined (TE_VXWORKS)
133 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
135 /* For backwards compatibility, default to FPA. */
136 # define FPU_DEFAULT FPU_ARCH_FPA
138 #endif /* ifndef FPU_DEFAULT */
140 #define streq(a, b) (strcmp (a, b) == 0)
142 static unsigned long cpu_variant;
143 static unsigned long arm_arch_used;
144 static unsigned long thumb_arch_used;
146 /* Flags stored in private area of BFD structure. */
147 static int uses_apcs_26 = FALSE;
148 static int atpcs = FALSE;
149 static int support_interwork = FALSE;
150 static int uses_apcs_float = FALSE;
151 static int pic_code = FALSE;
153 /* Variables that we set while parsing command-line options. Once all
154 options have been read we re-process these values to set the real
156 static int legacy_cpu = -1;
157 static int legacy_fpu = -1;
159 static int mcpu_cpu_opt = -1;
160 static int mcpu_fpu_opt = -1;
161 static int march_cpu_opt = -1;
162 static int march_fpu_opt = -1;
163 static int mfpu_opt = -1;
164 static int mfloat_abi_opt = -1;
165 /* Record user cpu selection for object attributes.
166 Zero if no default or user specified CPU. */
167 static int selected_cpu = -1;
168 /* Must be long enough to hold any of the names in arm_cpus. */
169 static char selected_cpu_name[16];
172 static int meabi_flags = EABI_DEFAULT;
174 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
179 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
180 symbolS * GOT_symbol;
183 /* 0: assemble for ARM,
184 1: assemble for Thumb,
185 2: assemble for Thumb even though target CPU does not support thumb
187 static int thumb_mode = 0;
189 /* If unified_syntax is true, we are processing the new unified
190 ARM/Thumb syntax. Important differences from the old ARM mode:
192 - Immediate operands do not require a # prefix.
193 - Conditional affixes always appear at the end of the
194 instruction. (For backward compatibility, those instructions
195 that formerly had them in the middle, continue to accept them
197 - The IT instruction may appear, and if it does is validated
198 against subsequent conditional affixes. It does not generate
201 Important differences from the old Thumb mode:
203 - Immediate operands do not require a # prefix.
204 - Most of the V6T2 instructions are only available in unified mode.
205 - The .N and .W suffixes are recognized and honored (it is an error
206 if they cannot be honored).
207 - All instructions set the flags if and only if they have an 's' affix.
208 - Conditional affixes may be used. They are validated against
209 preceding IT instructions. Unlike ARM mode, you cannot use a
210 conditional affix except in the scope of an IT instruction. */
212 static bfd_boolean unified_syntax = FALSE;
217 unsigned long instruction;
221 /* Set to the opcode if the instruction needs relaxation.
222 Zero if the instruction is not relaxed. */
226 bfd_reloc_code_real_type type;
235 unsigned present : 1; /* Operand present. */
236 unsigned isreg : 1; /* Operand was a register. */
237 unsigned immisreg : 1; /* .imm field is a second register. */
238 unsigned hasreloc : 1; /* Operand has relocation suffix. */
239 unsigned writeback : 1; /* Operand has trailing ! */
240 unsigned preind : 1; /* Preindexed address. */
241 unsigned postind : 1; /* Postindexed address. */
242 unsigned negative : 1; /* Index register was negated. */
243 unsigned shifted : 1; /* Shift applied to operation. */
244 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
248 static struct arm_it inst;
250 #define NUM_FLOAT_VALS 8
252 const char * fp_const[] =
254 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
257 /* Number of littlenums required to hold an extended precision number. */
258 #define MAX_LITTLENUMS 6
260 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
270 #define CP_T_X 0x00008000
271 #define CP_T_Y 0x00400000
273 #define CONDS_BIT 0x00100000
274 #define LOAD_BIT 0x00100000
276 #define DOUBLE_LOAD_FLAG 0x00000001
280 const char * template;
284 #define COND_ALWAYS 0xE
288 const char *template;
292 /* The bit that distinguishes CPSR and SPSR. */
293 #define SPSR_BIT (1 << 22)
295 /* The individual PSR flag bits. */
296 #define PSR_c (1 << 16)
297 #define PSR_x (1 << 17)
298 #define PSR_s (1 << 18)
299 #define PSR_f (1 << 19)
304 bfd_reloc_code_real_type reloc;
309 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
314 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
317 /* ARM register categories. This includes coprocessor numbers and various
318 architecture extensions' registers. */
340 /* Structure for a hash table entry for a register. */
344 unsigned char number;
346 unsigned char builtin;
349 /* Diagnostics used when we don't get a register of the expected type. */
350 const char *const reg_expected_msgs[] =
352 N_("ARM register expected"),
353 N_("bad or missing co-processor number"),
354 N_("co-processor register expected"),
355 N_("FPA register expected"),
356 N_("VFP single precision register expected"),
357 N_("VFP double precision register expected"),
358 N_("VFP system register expected"),
359 N_("Maverick MVF register expected"),
360 N_("Maverick MVD register expected"),
361 N_("Maverick MVFX register expected"),
362 N_("Maverick MVDX register expected"),
363 N_("Maverick MVAX register expected"),
364 N_("Maverick DSPSC register expected"),
365 N_("iWMMXt data register expected"),
366 N_("iWMMXt control register expected"),
367 N_("iWMMXt scalar register expected"),
368 N_("XScale accumulator register expected"),
371 /* Some well known registers that we refer to directly elsewhere. */
376 /* ARM instructions take 4bytes in the object file, Thumb instructions
382 /* Basic string to match. */
383 const char *template;
385 /* Parameters to instruction. */
386 unsigned char operands[8];
388 /* Conditional tag - see opcode_lookup. */
389 unsigned int tag : 4;
391 /* Basic instruction code. */
392 unsigned int avalue : 28;
394 /* Thumb-format instruction code. */
397 /* Which architecture variant provides this instruction. */
398 unsigned long avariant;
399 unsigned long tvariant;
401 /* Function to call to encode instruction in ARM format. */
402 void (* aencode) (void);
404 /* Function to call to encode instruction in Thumb format. */
405 void (* tencode) (void);
408 /* Defines for various bits that we will want to toggle. */
409 #define INST_IMMEDIATE 0x02000000
410 #define OFFSET_REG 0x02000000
411 #define HWOFFSET_IMM 0x00400000
412 #define SHIFT_BY_REG 0x00000010
413 #define PRE_INDEX 0x01000000
414 #define INDEX_UP 0x00800000
415 #define WRITE_BACK 0x00200000
416 #define LDM_TYPE_2_OR_3 0x00400000
418 #define LITERAL_MASK 0xf000f000
419 #define OPCODE_MASK 0xfe1fffff
420 #define V4_STR_BIT 0x00000020
422 #define DATA_OP_SHIFT 21
424 /* Codes to distinguish the arithmetic instructions. */
435 #define OPCODE_CMP 10
436 #define OPCODE_CMN 11
437 #define OPCODE_ORR 12
438 #define OPCODE_MOV 13
439 #define OPCODE_BIC 14
440 #define OPCODE_MVN 15
442 #define T_OPCODE_MUL 0x4340
443 #define T_OPCODE_TST 0x4200
444 #define T_OPCODE_CMN 0x42c0
445 #define T_OPCODE_NEG 0x4240
446 #define T_OPCODE_MVN 0x43c0
448 #define T_OPCODE_ADD_R3 0x1800
449 #define T_OPCODE_SUB_R3 0x1a00
450 #define T_OPCODE_ADD_HI 0x4400
451 #define T_OPCODE_ADD_ST 0xb000
452 #define T_OPCODE_SUB_ST 0xb080
453 #define T_OPCODE_ADD_SP 0xa800
454 #define T_OPCODE_ADD_PC 0xa000
455 #define T_OPCODE_ADD_I8 0x3000
456 #define T_OPCODE_SUB_I8 0x3800
457 #define T_OPCODE_ADD_I3 0x1c00
458 #define T_OPCODE_SUB_I3 0x1e00
460 #define T_OPCODE_ASR_R 0x4100
461 #define T_OPCODE_LSL_R 0x4080
462 #define T_OPCODE_LSR_R 0x40c0
463 #define T_OPCODE_ROR_R 0x41c0
464 #define T_OPCODE_ASR_I 0x1000
465 #define T_OPCODE_LSL_I 0x0000
466 #define T_OPCODE_LSR_I 0x0800
468 #define T_OPCODE_MOV_I8 0x2000
469 #define T_OPCODE_CMP_I8 0x2800
470 #define T_OPCODE_CMP_LR 0x4280
471 #define T_OPCODE_MOV_HR 0x4600
472 #define T_OPCODE_CMP_HR 0x4500
474 #define T_OPCODE_LDR_PC 0x4800
475 #define T_OPCODE_LDR_SP 0x9800
476 #define T_OPCODE_STR_SP 0x9000
477 #define T_OPCODE_LDR_IW 0x6800
478 #define T_OPCODE_STR_IW 0x6000
479 #define T_OPCODE_LDR_IH 0x8800
480 #define T_OPCODE_STR_IH 0x8000
481 #define T_OPCODE_LDR_IB 0x7800
482 #define T_OPCODE_STR_IB 0x7000
483 #define T_OPCODE_LDR_RW 0x5800
484 #define T_OPCODE_STR_RW 0x5000
485 #define T_OPCODE_LDR_RH 0x5a00
486 #define T_OPCODE_STR_RH 0x5200
487 #define T_OPCODE_LDR_RB 0x5c00
488 #define T_OPCODE_STR_RB 0x5400
490 #define T_OPCODE_PUSH 0xb400
491 #define T_OPCODE_POP 0xbc00
493 #define T_OPCODE_BRANCH 0xe000
495 #define THUMB_SIZE 2 /* Size of thumb instruction. */
496 #define THUMB_PP_PC_LR 0x0100
497 #define THUMB_LOAD_BIT 0x0800
499 #define BAD_ARGS _("bad arguments to instruction")
500 #define BAD_PC _("r15 not allowed here")
501 #define BAD_COND _("instruction cannot be conditional")
502 #define BAD_OVERLAP _("registers may not be the same")
503 #define BAD_HIREG _("lo register required")
504 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
505 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
507 static struct hash_control *arm_ops_hsh;
508 static struct hash_control *arm_cond_hsh;
509 static struct hash_control *arm_shift_hsh;
510 static struct hash_control *arm_psr_hsh;
511 static struct hash_control *arm_reg_hsh;
512 static struct hash_control *arm_reloc_hsh;
514 /* Stuff needed to resolve the label ambiguity
524 symbolS * last_label_seen;
525 static int label_is_thumb_function_name = FALSE;
527 /* Literal pool structure. Held on a per-section
528 and per-sub-section basis. */
530 #define MAX_LITERAL_POOL_SIZE 1024
531 typedef struct literal_pool
533 expressionS literals [MAX_LITERAL_POOL_SIZE];
534 unsigned int next_free_entry;
539 struct literal_pool * next;
542 /* Pointer to a linked list of literal pools. */
543 literal_pool * list_of_pools = NULL;
545 /* State variables for IT block handling. */
546 static bfd_boolean current_it_mask = 0;
547 static int current_cc;
552 /* This array holds the chars that always start a comment. If the
553 pre-processor is disabled, these aren't very useful. */
554 const char comment_chars[] = "@";
556 /* This array holds the chars that only start a comment at the beginning of
557 a line. If the line seems to have the form '# 123 filename'
558 .line and .file directives will appear in the pre-processed output. */
559 /* Note that input_file.c hand checks for '#' at the beginning of the
560 first line of the input file. This is because the compiler outputs
561 #NO_APP at the beginning of its output. */
562 /* Also note that comments like this one will always work. */
563 const char line_comment_chars[] = "#";
565 const char line_separator_chars[] = ";";
567 /* Chars that can be used to separate mant
568 from exp in floating point numbers. */
569 const char EXP_CHARS[] = "eE";
571 /* Chars that mean this number is a floating point constant. */
575 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
577 /* Prefix characters that indicate the start of an immediate
579 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
581 /* Separator character handling. */
583 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
586 skip_past_char (char ** str, char c)
596 #define skip_past_comma(str) skip_past_char (str, ',')
598 /* Arithmetic expressions (possibly involving symbols). */
600 /* Return TRUE if anything in the expression is a bignum. */
603 walk_no_bignums (symbolS * sp)
605 if (symbol_get_value_expression (sp)->X_op == O_big)
608 if (symbol_get_value_expression (sp)->X_add_symbol)
610 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
611 || (symbol_get_value_expression (sp)->X_op_symbol
612 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
618 static int in_my_get_expression = 0;
620 /* Third argument to my_get_expression. */
621 #define GE_NO_PREFIX 0
622 #define GE_IMM_PREFIX 1
623 #define GE_OPT_PREFIX 2
626 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
631 /* In unified syntax, all prefixes are optional. */
633 prefix_mode = GE_OPT_PREFIX;
637 case GE_NO_PREFIX: break;
639 if (!is_immediate_prefix (**str))
641 inst.error = _("immediate expression requires a # prefix");
647 if (is_immediate_prefix (**str))
653 memset (ep, 0, sizeof (expressionS));
655 save_in = input_line_pointer;
656 input_line_pointer = *str;
657 in_my_get_expression = 1;
658 seg = expression (ep);
659 in_my_get_expression = 0;
661 if (ep->X_op == O_illegal)
663 /* We found a bad expression in md_operand(). */
664 *str = input_line_pointer;
665 input_line_pointer = save_in;
666 if (inst.error == NULL)
667 inst.error = _("bad expression");
672 if (seg != absolute_section
673 && seg != text_section
674 && seg != data_section
675 && seg != bss_section
676 && seg != undefined_section)
678 inst.error = _("bad segment");
679 *str = input_line_pointer;
680 input_line_pointer = save_in;
685 /* Get rid of any bignums now, so that we don't generate an error for which
686 we can't establish a line number later on. Big numbers are never valid
687 in instructions, which is where this routine is always called. */
688 if (ep->X_op == O_big
690 && (walk_no_bignums (ep->X_add_symbol)
692 && walk_no_bignums (ep->X_op_symbol)))))
694 inst.error = _("invalid constant");
695 *str = input_line_pointer;
696 input_line_pointer = save_in;
700 *str = input_line_pointer;
701 input_line_pointer = save_in;
705 /* Turn a string in input_line_pointer into a floating point constant
706 of type TYPE, and store the appropriate bytes in *LITP. The number
707 of LITTLENUMS emitted is stored in *SIZEP. An error message is
708 returned, or NULL on OK.
710 Note that fp constants aren't represent in the normal way on the ARM.
711 In big endian mode, things are as expected. However, in little endian
712 mode fp constants are big-endian word-wise, and little-endian byte-wise
713 within the words. For example, (double) 1.1 in big endian mode is
714 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
715 the byte sequence 99 99 f1 3f 9a 99 99 99.
717 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
720 md_atof (int type, char * litP, int * sizeP)
723 LITTLENUM_TYPE words[MAX_LITTLENUMS];
755 return _("bad call to MD_ATOF()");
758 t = atof_ieee (input_line_pointer, type, words);
760 input_line_pointer = t;
763 if (target_big_endian)
765 for (i = 0; i < prec; i++)
767 md_number_to_chars (litP, (valueT) words[i], 2);
773 if (cpu_variant & FPU_ARCH_VFP)
774 for (i = prec - 1; i >= 0; i--)
776 md_number_to_chars (litP, (valueT) words[i], 2);
780 /* For a 4 byte float the order of elements in `words' is 1 0.
781 For an 8 byte float the order is 1 0 3 2. */
782 for (i = 0; i < prec; i += 2)
784 md_number_to_chars (litP, (valueT) words[i + 1], 2);
785 md_number_to_chars (litP + 2, (valueT) words[i], 2);
793 /* We handle all bad expressions here, so that we can report the faulty
794 instruction in the error message. */
796 md_operand (expressionS * expr)
798 if (in_my_get_expression)
799 expr->X_op = O_illegal;
802 /* Immediate values. */
804 /* Generic immediate-value read function for use in directives.
805 Accepts anything that 'expression' can fold to a constant.
806 *val receives the number. */
809 immediate_for_directive (int *val)
812 exp.X_op = O_illegal;
814 if (is_immediate_prefix (*input_line_pointer))
816 input_line_pointer++;
820 if (exp.X_op != O_constant)
822 as_bad (_("expected #constant"));
823 ignore_rest_of_line ();
826 *val = exp.X_add_number;
831 /* Register parsing. */
833 /* Generic register parser. CCP points to what should be the
834 beginning of a register name. If it is indeed a valid register
835 name, advance CCP over it and return the reg_entry structure;
836 otherwise return NULL. Does not issue diagnostics. */
838 static struct reg_entry *
839 arm_reg_parse_multi (char **ccp)
843 struct reg_entry *reg;
845 #ifdef REGISTER_PREFIX
846 if (*start != REGISTER_PREFIX)
850 #ifdef OPTIONAL_REGISTER_PREFIX
851 if (*start == OPTIONAL_REGISTER_PREFIX)
856 if (!ISALPHA (*p) || !is_name_beginner (*p))
861 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
863 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
872 /* As above, but the register must be of type TYPE, and the return
873 value is the register number or FAIL. */
876 arm_reg_parse (char **ccp, enum arm_reg_type type)
879 struct reg_entry *reg = arm_reg_parse_multi (ccp);
881 if (reg && reg->type == type)
884 /* Alternative syntaxes are accepted for a few register classes. */
891 /* Generic coprocessor register names are allowed for these. */
892 if (reg->type == REG_TYPE_CN)
897 /* For backward compatibility, a bare number is valid here. */
899 unsigned long processor = strtoul (start, ccp, 10);
900 if (*ccp != start && processor <= 15)
905 /* WC includes WCG. ??? I'm not sure this is true for all
906 instructions that take WC registers. */
907 if (reg->type == REG_TYPE_MMXWCG)
919 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
921 parse_reg_list (char ** strp)
927 /* We come back here if we get ranges concatenated by '+' or '|'. */
942 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
944 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
954 inst.error = _("bad range in register list");
958 for (i = cur_reg + 1; i < reg; i++)
960 if (range & (1 << i))
962 (_("Warning: duplicated register (r%d) in register list"),
970 if (range & (1 << reg))
971 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
973 else if (reg <= cur_reg)
974 as_tsktsk (_("Warning: register range not in ascending order"));
979 while (skip_past_comma (&str) != FAIL
980 || (in_range = 1, *str++ == '-'));
985 inst.error = _("missing `}'");
993 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
996 if (expr.X_op == O_constant)
998 if (expr.X_add_number
999 != (expr.X_add_number & 0x0000ffff))
1001 inst.error = _("invalid register mask");
1005 if ((range & expr.X_add_number) != 0)
1007 int regno = range & expr.X_add_number;
1010 regno = (1 << regno) - 1;
1012 (_("Warning: duplicated register (r%d) in register list"),
1016 range |= expr.X_add_number;
1020 if (inst.reloc.type != 0)
1022 inst.error = _("expression too complex");
1026 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1027 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1028 inst.reloc.pc_rel = 0;
1032 if (*str == '|' || *str == '+')
1038 while (another_range);
1044 /* Parse a VFP register list. If the string is invalid return FAIL.
1045 Otherwise return the number of registers, and set PBASE to the first
1046 register. Double precision registers are matched if DP is nonzero. */
1049 parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
1057 unsigned long mask = 0;
1067 regtype = REG_TYPE_VFD;
1072 regtype = REG_TYPE_VFS;
1076 base_reg = max_regs;
1080 new_base = arm_reg_parse (str, regtype);
1081 if (new_base == FAIL)
1083 inst.error = gettext (reg_expected_msgs[regtype]);
1087 if (new_base < base_reg)
1088 base_reg = new_base;
1090 if (mask & (1 << new_base))
1092 inst.error = _("invalid register list");
1096 if ((mask >> new_base) != 0 && ! warned)
1098 as_tsktsk (_("register list not in ascending order"));
1102 mask |= 1 << new_base;
1105 if (**str == '-') /* We have the start of a range expression */
1111 if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
1113 inst.error = gettext (reg_expected_msgs[regtype]);
1117 if (high_range <= new_base)
1119 inst.error = _("register range not in ascending order");
1123 for (new_base++; new_base <= high_range; new_base++)
1125 if (mask & (1 << new_base))
1127 inst.error = _("invalid register list");
1131 mask |= 1 << new_base;
1136 while (skip_past_comma (str) != FAIL);
1140 /* Sanity check -- should have raised a parse error above. */
1141 if (count == 0 || count > max_regs)
1146 /* Final test -- the registers must be consecutive. */
1148 for (i = 0; i < count; i++)
1150 if ((mask & (1u << i)) == 0)
1152 inst.error = _("non-contiguous register range");
1160 /* Parse an explicit relocation suffix on an expression. This is
1161 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1162 arm_reloc_hsh contains no entries, so this function can only
1163 succeed if there is no () after the word. Returns -1 on error,
1164 BFD_RELOC_UNUSED if there wasn't any suffix. */
1166 parse_reloc (char **str)
1168 struct reloc_entry *r;
1172 return BFD_RELOC_UNUSED;
1177 while (*q && *q != ')' && *q != ',')
1182 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1189 /* Directives: register aliases. */
1192 insert_reg_alias (char *str, int number, int type)
1194 struct reg_entry *new;
1197 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1200 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1202 /* Only warn about a redefinition if it's not defined as the
1204 else if (new->number != number || new->type != type)
1205 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1210 name = xstrdup (str);
1211 new = xmalloc (sizeof (struct reg_entry));
1214 new->number = number;
1216 new->builtin = FALSE;
1218 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1222 /* Look for the .req directive. This is of the form:
1224 new_register_name .req existing_register_name
1226 If we find one, or if it looks sufficiently like one that we want to
1227 handle any error here, return non-zero. Otherwise return zero. */
1230 create_register_alias (char * newname, char *p)
1232 struct reg_entry *old;
1233 char *oldname, *nbuf;
1236 /* The input scrubber ensures that whitespace after the mnemonic is
1237 collapsed to single spaces. */
1239 if (strncmp (oldname, " .req ", 6) != 0)
1243 if (*oldname == '\0')
1246 old = hash_find (arm_reg_hsh, oldname);
1249 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1253 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1254 the desired alias name, and p points to its end. If not, then
1255 the desired alias name is in the global original_case_string. */
1256 #ifdef TC_CASE_SENSITIVE
1259 newname = original_case_string;
1260 nlen = strlen (newname);
1263 nbuf = alloca (nlen + 1);
1264 memcpy (nbuf, newname, nlen);
1267 /* Create aliases under the new name as stated; an all-lowercase
1268 version of the new name; and an all-uppercase version of the new
1270 insert_reg_alias (nbuf, old->number, old->type);
1272 for (p = nbuf; *p; p++)
1275 if (strncmp (nbuf, newname, nlen))
1276 insert_reg_alias (nbuf, old->number, old->type);
1278 for (p = nbuf; *p; p++)
1281 if (strncmp (nbuf, newname, nlen))
1282 insert_reg_alias (nbuf, old->number, old->type);
1287 /* Should never be called, as .req goes between the alias and the
1288 register name, not at the beginning of the line. */
1290 s_req (int a ATTRIBUTE_UNUSED)
1292 as_bad (_("invalid syntax for .req directive"));
1295 /* The .unreq directive deletes an alias which was previously defined
1296 by .req. For example:
1302 s_unreq (int a ATTRIBUTE_UNUSED)
1307 name = input_line_pointer;
1309 while (*input_line_pointer != 0
1310 && *input_line_pointer != ' '
1311 && *input_line_pointer != '\n')
1312 ++input_line_pointer;
1314 saved_char = *input_line_pointer;
1315 *input_line_pointer = 0;
1318 as_bad (_("invalid syntax for .unreq directive"));
1321 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
1324 as_bad (_("unknown register alias '%s'"), name);
1325 else if (reg->builtin)
1326 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1330 hash_delete (arm_reg_hsh, name);
1331 free ((char *) reg->name);
1336 *input_line_pointer = saved_char;
1337 demand_empty_rest_of_line ();
1340 /* Directives: Instruction set selection. */
1343 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1344 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1345 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1346 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1348 static enum mstate mapstate = MAP_UNDEFINED;
1351 mapping_state (enum mstate state)
1354 const char * symname;
1357 if (mapstate == state)
1358 /* The mapping symbol has already been emitted.
1359 There is nothing else to do. */
1368 type = BSF_NO_FLAGS;
1372 type = BSF_NO_FLAGS;
1376 type = BSF_NO_FLAGS;
1384 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1386 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
1387 symbol_table_insert (symbolP);
1388 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1393 THUMB_SET_FUNC (symbolP, 0);
1394 ARM_SET_THUMB (symbolP, 0);
1395 ARM_SET_INTERWORK (symbolP, support_interwork);
1399 THUMB_SET_FUNC (symbolP, 1);
1400 ARM_SET_THUMB (symbolP, 1);
1401 ARM_SET_INTERWORK (symbolP, support_interwork);
1410 #define mapping_state(x) /* nothing */
1413 /* Find the real, Thumb encoded start of a Thumb function. */
1416 find_real_start (symbolS * symbolP)
1419 const char * name = S_GET_NAME (symbolP);
1420 symbolS * new_target;
1422 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1423 #define STUB_NAME ".real_start_of"
1428 /* The compiler may generate BL instructions to local labels because
1429 it needs to perform a branch to a far away location. These labels
1430 do not have a corresponding ".real_start_of" label. We check
1431 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1432 the ".real_start_of" convention for nonlocal branches. */
1433 if (S_IS_LOCAL (symbolP) || name[0] == '.')
1436 real_start = ACONCAT ((STUB_NAME, name, NULL));
1437 new_target = symbol_find (real_start);
1439 if (new_target == NULL)
1441 as_warn ("Failed to find real start of function: %s\n", name);
1442 new_target = symbolP;
1449 opcode_select (int width)
1456 if (! (cpu_variant & ARM_EXT_V4T))
1457 as_bad (_("selected processor does not support THUMB opcodes"));
1460 /* No need to force the alignment, since we will have been
1461 coming from ARM mode, which is word-aligned. */
1462 record_alignment (now_seg, 1);
1464 mapping_state (MAP_THUMB);
1470 if ((cpu_variant & ARM_ALL) == ARM_EXT_V4T)
1471 as_bad (_("selected processor does not support ARM opcodes"));
1476 frag_align (2, 0, 0);
1478 record_alignment (now_seg, 1);
1480 mapping_state (MAP_ARM);
1484 as_bad (_("invalid instruction size selected (%d)"), width);
1489 s_arm (int ignore ATTRIBUTE_UNUSED)
1492 demand_empty_rest_of_line ();
1496 s_thumb (int ignore ATTRIBUTE_UNUSED)
1499 demand_empty_rest_of_line ();
1503 s_code (int unused ATTRIBUTE_UNUSED)
1507 temp = get_absolute_expression ();
1512 opcode_select (temp);
1516 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1521 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
1523 /* If we are not already in thumb mode go into it, EVEN if
1524 the target processor does not support thumb instructions.
1525 This is used by gcc/config/arm/lib1funcs.asm for example
1526 to compile interworking support functions even if the
1527 target processor should not support interworking. */
1531 record_alignment (now_seg, 1);
1534 demand_empty_rest_of_line ();
1538 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
1542 /* The following label is the name/address of the start of a Thumb function.
1543 We need to know this for the interworking support. */
1544 label_is_thumb_function_name = TRUE;
1547 /* Perform a .set directive, but also mark the alias as
1548 being a thumb function. */
1551 s_thumb_set (int equiv)
1553 /* XXX the following is a duplicate of the code for s_set() in read.c
1554 We cannot just call that code as we need to get at the symbol that
1561 /* Especial apologies for the random logic:
1562 This just grew, and could be parsed much more simply!
1564 name = input_line_pointer;
1565 delim = get_symbol_end ();
1566 end_name = input_line_pointer;
1569 if (*input_line_pointer != ',')
1572 as_bad (_("expected comma after name \"%s\""), name);
1574 ignore_rest_of_line ();
1578 input_line_pointer++;
1581 if (name[0] == '.' && name[1] == '\0')
1583 /* XXX - this should not happen to .thumb_set. */
1587 if ((symbolP = symbol_find (name)) == NULL
1588 && (symbolP = md_undefined_symbol (name)) == NULL)
1591 /* When doing symbol listings, play games with dummy fragments living
1592 outside the normal fragment chain to record the file and line info
1594 if (listing & LISTING_SYMBOLS)
1596 extern struct list_info_struct * listing_tail;
1597 fragS * dummy_frag = xmalloc (sizeof (fragS));
1599 memset (dummy_frag, 0, sizeof (fragS));
1600 dummy_frag->fr_type = rs_fill;
1601 dummy_frag->line = listing_tail;
1602 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1603 dummy_frag->fr_symbol = symbolP;
1607 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1610 /* "set" symbols are local unless otherwise specified. */
1611 SF_SET_LOCAL (symbolP);
1612 #endif /* OBJ_COFF */
1613 } /* Make a new symbol. */
1615 symbol_table_insert (symbolP);
1620 && S_IS_DEFINED (symbolP)
1621 && S_GET_SEGMENT (symbolP) != reg_section)
1622 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1624 pseudo_set (symbolP);
1626 demand_empty_rest_of_line ();
1628 /* XXX Now we come to the Thumb specific bit of code. */
1630 THUMB_SET_FUNC (symbolP, 1);
1631 ARM_SET_THUMB (symbolP, 1);
1632 #if defined OBJ_ELF || defined OBJ_COFF
1633 ARM_SET_INTERWORK (symbolP, support_interwork);
1637 /* Directives: Mode selection. */
1639 /* .syntax [unified|divided] - choose the new unified syntax
1640 (same for Arm and Thumb encoding, modulo slight differences in what
1641 can be represented) or the old divergent syntax for each mode. */
1643 s_syntax (int unused ATTRIBUTE_UNUSED)
1647 name = input_line_pointer;
1648 delim = get_symbol_end ();
1650 if (!strcasecmp (name, "unified"))
1651 unified_syntax = TRUE;
1652 else if (!strcasecmp (name, "divided"))
1653 unified_syntax = FALSE;
1656 as_bad (_("unrecognized syntax mode \"%s\""), name);
1659 *input_line_pointer = delim;
1660 demand_empty_rest_of_line ();
1663 /* Directives: sectioning and alignment. */
1665 /* Same as s_align_ptwo but align 0 => align 2. */
1668 s_align (int unused ATTRIBUTE_UNUSED)
1672 long max_alignment = 15;
1674 temp = get_absolute_expression ();
1675 if (temp > max_alignment)
1676 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
1679 as_bad (_("alignment negative. 0 assumed."));
1683 if (*input_line_pointer == ',')
1685 input_line_pointer++;
1686 temp_fill = get_absolute_expression ();
1694 /* Only make a frag if we HAVE to. */
1695 if (temp && !need_pass_2)
1696 frag_align (temp, (int) temp_fill, 0);
1697 demand_empty_rest_of_line ();
1699 record_alignment (now_seg, temp);
1703 s_bss (int ignore ATTRIBUTE_UNUSED)
1705 /* We don't support putting frags in the BSS segment, we fake it by
1706 marking in_bss, then looking at s_skip for clues. */
1707 subseg_set (bss_section, 0);
1708 demand_empty_rest_of_line ();
1709 mapping_state (MAP_DATA);
1713 s_even (int ignore ATTRIBUTE_UNUSED)
1715 /* Never make frag if expect extra pass. */
1717 frag_align (1, 0, 0);
1719 record_alignment (now_seg, 1);
1721 demand_empty_rest_of_line ();
1724 /* Directives: Literal pools. */
1726 static literal_pool *
1727 find_literal_pool (void)
1729 literal_pool * pool;
1731 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1733 if (pool->section == now_seg
1734 && pool->sub_section == now_subseg)
1741 static literal_pool *
1742 find_or_make_literal_pool (void)
1744 /* Next literal pool ID number. */
1745 static unsigned int latest_pool_num = 1;
1746 literal_pool * pool;
1748 pool = find_literal_pool ();
1752 /* Create a new pool. */
1753 pool = xmalloc (sizeof (* pool));
1757 pool->next_free_entry = 0;
1758 pool->section = now_seg;
1759 pool->sub_section = now_subseg;
1760 pool->next = list_of_pools;
1761 pool->symbol = NULL;
1763 /* Add it to the list. */
1764 list_of_pools = pool;
1767 /* New pools, and emptied pools, will have a NULL symbol. */
1768 if (pool->symbol == NULL)
1770 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1771 (valueT) 0, &zero_address_frag);
1772 pool->id = latest_pool_num ++;
1779 /* Add the literal in the global 'inst'
1780 structure to the relevent literal pool. */
1783 add_to_lit_pool (void)
1785 literal_pool * pool;
1788 pool = find_or_make_literal_pool ();
1790 /* Check if this literal value is already in the pool. */
1791 for (entry = 0; entry < pool->next_free_entry; entry ++)
1793 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1794 && (inst.reloc.exp.X_op == O_constant)
1795 && (pool->literals[entry].X_add_number
1796 == inst.reloc.exp.X_add_number)
1797 && (pool->literals[entry].X_unsigned
1798 == inst.reloc.exp.X_unsigned))
1801 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1802 && (inst.reloc.exp.X_op == O_symbol)
1803 && (pool->literals[entry].X_add_number
1804 == inst.reloc.exp.X_add_number)
1805 && (pool->literals[entry].X_add_symbol
1806 == inst.reloc.exp.X_add_symbol)
1807 && (pool->literals[entry].X_op_symbol
1808 == inst.reloc.exp.X_op_symbol))
1812 /* Do we need to create a new entry? */
1813 if (entry == pool->next_free_entry)
1815 if (entry >= MAX_LITERAL_POOL_SIZE)
1817 inst.error = _("literal pool overflow");
1821 pool->literals[entry] = inst.reloc.exp;
1822 pool->next_free_entry += 1;
1825 inst.reloc.exp.X_op = O_symbol;
1826 inst.reloc.exp.X_add_number = ((int) entry) * 4;
1827 inst.reloc.exp.X_add_symbol = pool->symbol;
1832 /* Can't use symbol_new here, so have to create a symbol and then at
1833 a later date assign it a value. Thats what these functions do. */
1836 symbol_locate (symbolS * symbolP,
1837 const char * name, /* It is copied, the caller can modify. */
1838 segT segment, /* Segment identifier (SEG_<something>). */
1839 valueT valu, /* Symbol value. */
1840 fragS * frag) /* Associated fragment. */
1842 unsigned int name_length;
1843 char * preserved_copy_of_name;
1845 name_length = strlen (name) + 1; /* +1 for \0. */
1846 obstack_grow (¬es, name, name_length);
1847 preserved_copy_of_name = obstack_finish (¬es);
1849 #ifdef tc_canonicalize_symbol_name
1850 preserved_copy_of_name =
1851 tc_canonicalize_symbol_name (preserved_copy_of_name);
1854 S_SET_NAME (symbolP, preserved_copy_of_name);
1856 S_SET_SEGMENT (symbolP, segment);
1857 S_SET_VALUE (symbolP, valu);
1858 symbol_clear_list_pointers (symbolP);
1860 symbol_set_frag (symbolP, frag);
1862 /* Link to end of symbol chain. */
1864 extern int symbol_table_frozen;
1866 if (symbol_table_frozen)
1870 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1872 obj_symbol_new_hook (symbolP);
1874 #ifdef tc_symbol_new_hook
1875 tc_symbol_new_hook (symbolP);
1879 verify_symbol_chain (symbol_rootP, symbol_lastP);
1880 #endif /* DEBUG_SYMS */
1885 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1888 literal_pool * pool;
1891 pool = find_literal_pool ();
1893 || pool->symbol == NULL
1894 || pool->next_free_entry == 0)
1897 mapping_state (MAP_DATA);
1899 /* Align pool as you have word accesses.
1900 Only make a frag if we have to. */
1902 frag_align (2, 0, 0);
1904 record_alignment (now_seg, 2);
1906 sprintf (sym_name, "$$lit_\002%x", pool->id);
1908 symbol_locate (pool->symbol, sym_name, now_seg,
1909 (valueT) frag_now_fix (), frag_now);
1910 symbol_table_insert (pool->symbol);
1912 ARM_SET_THUMB (pool->symbol, thumb_mode);
1914 #if defined OBJ_COFF || defined OBJ_ELF
1915 ARM_SET_INTERWORK (pool->symbol, support_interwork);
1918 for (entry = 0; entry < pool->next_free_entry; entry ++)
1919 /* First output the expression in the instruction to the pool. */
1920 emit_expr (&(pool->literals[entry]), 4); /* .word */
1922 /* Mark the pool as empty. */
1923 pool->next_free_entry = 0;
1924 pool->symbol = NULL;
1928 /* Forward declarations for functions below, in the MD interface
1930 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
1931 static valueT create_unwind_entry (int);
1932 static void start_unwind_section (const segT, int);
1933 static void add_unwind_opcode (valueT, int);
1934 static void flush_pending_unwind (void);
1936 /* Directives: Data. */
1939 s_arm_elf_cons (int nbytes)
1943 #ifdef md_flush_pending_output
1944 md_flush_pending_output ();
1947 if (is_it_end_of_statement ())
1949 demand_empty_rest_of_line ();
1953 #ifdef md_cons_align
1954 md_cons_align (nbytes);
1957 mapping_state (MAP_DATA);
1961 char *base = input_line_pointer;
1965 if (exp.X_op != O_symbol)
1966 emit_expr (&exp, (unsigned int) nbytes);
1969 char *before_reloc = input_line_pointer;
1970 reloc = parse_reloc (&input_line_pointer);
1973 as_bad (_("unrecognized relocation suffix"));
1974 ignore_rest_of_line ();
1977 else if (reloc == BFD_RELOC_UNUSED)
1978 emit_expr (&exp, (unsigned int) nbytes);
1981 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
1982 int size = bfd_get_reloc_size (howto);
1984 if (reloc == BFD_RELOC_ARM_PLT32)
1986 as_bad (_("(plt) is only valid on branch targets"));
1987 reloc = BFD_RELOC_UNUSED;
1992 as_bad (_("%s relocations do not fit in %d bytes"),
1993 howto->name, nbytes);
1996 /* We've parsed an expression stopping at O_symbol.
1997 But there may be more expression left now that we
1998 have parsed the relocation marker. Parse it again.
1999 XXX Surely there is a cleaner way to do this. */
2000 char *p = input_line_pointer;
2002 char *save_buf = alloca (input_line_pointer - base);
2003 memcpy (save_buf, base, input_line_pointer - base);
2004 memmove (base + (input_line_pointer - before_reloc),
2005 base, before_reloc - base);
2007 input_line_pointer = base + (input_line_pointer-before_reloc);
2009 memcpy (base, save_buf, p - base);
2011 offset = nbytes - size;
2012 p = frag_more ((int) nbytes);
2013 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2014 size, &exp, 0, reloc);
2019 while (*input_line_pointer++ == ',');
2021 /* Put terminator back into stream. */
2022 input_line_pointer --;
2023 demand_empty_rest_of_line ();
2027 /* Parse a .rel31 directive. */
2030 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2037 if (*input_line_pointer == '1')
2038 highbit = 0x80000000;
2039 else if (*input_line_pointer != '0')
2040 as_bad (_("expected 0 or 1"));
2042 input_line_pointer++;
2043 if (*input_line_pointer != ',')
2044 as_bad (_("missing comma"));
2045 input_line_pointer++;
2047 #ifdef md_flush_pending_output
2048 md_flush_pending_output ();
2051 #ifdef md_cons_align
2055 mapping_state (MAP_DATA);
2060 md_number_to_chars (p, highbit, 4);
2061 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
2062 BFD_RELOC_ARM_PREL31);
2064 demand_empty_rest_of_line ();
2067 /* Directives: AEABI stack-unwind tables. */
2069 /* Parse an unwind_fnstart directive. Simply records the current location. */
2072 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
2074 demand_empty_rest_of_line ();
2075 /* Mark the start of the function. */
2076 unwind.proc_start = expr_build_dot ();
2078 /* Reset the rest of the unwind info. */
2079 unwind.opcode_count = 0;
2080 unwind.table_entry = NULL;
2081 unwind.personality_routine = NULL;
2082 unwind.personality_index = -1;
2083 unwind.frame_size = 0;
2084 unwind.fp_offset = 0;
2087 unwind.sp_restored = 0;
2091 /* Parse a handlerdata directive. Creates the exception handling table entry
2092 for the function. */
2095 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
2097 demand_empty_rest_of_line ();
2098 if (unwind.table_entry)
2099 as_bad (_("dupicate .handlerdata directive"));
2101 create_unwind_entry (1);
2104 /* Parse an unwind_fnend directive. Generates the index table entry. */
2107 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
2113 demand_empty_rest_of_line ();
2115 /* Add eh table entry. */
2116 if (unwind.table_entry == NULL)
2117 val = create_unwind_entry (0);
2121 /* Add index table entry. This is two words. */
2122 start_unwind_section (unwind.saved_seg, 1);
2123 frag_align (2, 0, 0);
2124 record_alignment (now_seg, 2);
2126 ptr = frag_more (8);
2127 where = frag_now_fix () - 8;
2129 /* Self relative offset of the function start. */
2130 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
2131 BFD_RELOC_ARM_PREL31);
2133 /* Indicate dependency on EHABI-defined personality routines to the
2134 linker, if it hasn't been done already. */
2135 if (unwind.personality_index >= 0 && unwind.personality_index < 3
2136 && !(marked_pr_dependency & (1 << unwind.personality_index)))
2138 static const char *const name[] = {
2139 "__aeabi_unwind_cpp_pr0",
2140 "__aeabi_unwind_cpp_pr1",
2141 "__aeabi_unwind_cpp_pr2"
2143 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
2144 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
2145 marked_pr_dependency |= 1 << unwind.personality_index;
2146 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
2147 = marked_pr_dependency;
2151 /* Inline exception table entry. */
2152 md_number_to_chars (ptr + 4, val, 4);
2154 /* Self relative offset of the table entry. */
2155 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
2156 BFD_RELOC_ARM_PREL31);
2158 /* Restore the original section. */
2159 subseg_set (unwind.saved_seg, unwind.saved_subseg);
2163 /* Parse an unwind_cantunwind directive. */
2166 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
2168 demand_empty_rest_of_line ();
2169 if (unwind.personality_routine || unwind.personality_index != -1)
2170 as_bad (_("personality routine specified for cantunwind frame"));
2172 unwind.personality_index = -2;
2176 /* Parse a personalityindex directive. */
2179 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
2183 if (unwind.personality_routine || unwind.personality_index != -1)
2184 as_bad (_("duplicate .personalityindex directive"));
2188 if (exp.X_op != O_constant
2189 || exp.X_add_number < 0 || exp.X_add_number > 15)
2191 as_bad (_("bad personality routine number"));
2192 ignore_rest_of_line ();
2196 unwind.personality_index = exp.X_add_number;
2198 demand_empty_rest_of_line ();
2202 /* Parse a personality directive. */
2205 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
2209 if (unwind.personality_routine || unwind.personality_index != -1)
2210 as_bad (_("duplicate .personality directive"));
2212 name = input_line_pointer;
2213 c = get_symbol_end ();
2214 p = input_line_pointer;
2215 unwind.personality_routine = symbol_find_or_make (name);
2217 demand_empty_rest_of_line ();
2221 /* Parse a directive saving core registers. */
2224 s_arm_unwind_save_core (void)
2230 range = parse_reg_list (&input_line_pointer);
2233 as_bad (_("expected register list"));
2234 ignore_rest_of_line ();
2238 demand_empty_rest_of_line ();
2240 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2241 into .unwind_save {..., sp...}. We aren't bothered about the value of
2242 ip because it is clobbered by calls. */
2243 if (unwind.sp_restored && unwind.fp_reg == 12
2244 && (range & 0x3000) == 0x1000)
2246 unwind.opcode_count--;
2247 unwind.sp_restored = 0;
2248 range = (range | 0x2000) & ~0x1000;
2249 unwind.pending_offset = 0;
2255 /* See if we can use the short opcodes. These pop a block of up to 8
2256 registers starting with r4, plus maybe r14. */
2257 for (n = 0; n < 8; n++)
2259 /* Break at the first non-saved register. */
2260 if ((range & (1 << (n + 4))) == 0)
2263 /* See if there are any other bits set. */
2264 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
2266 /* Use the long form. */
2267 op = 0x8000 | ((range >> 4) & 0xfff);
2268 add_unwind_opcode (op, 2);
2272 /* Use the short form. */
2274 op = 0xa8; /* Pop r14. */
2276 op = 0xa0; /* Do not pop r14. */
2278 add_unwind_opcode (op, 1);
2285 op = 0xb100 | (range & 0xf);
2286 add_unwind_opcode (op, 2);
2289 /* Record the number of bytes pushed. */
2290 for (n = 0; n < 16; n++)
2292 if (range & (1 << n))
2293 unwind.frame_size += 4;
2298 /* Parse a directive saving FPA registers. */
2301 s_arm_unwind_save_fpa (int reg)
2307 /* Get Number of registers to transfer. */
2308 if (skip_past_comma (&input_line_pointer) != FAIL)
2311 exp.X_op = O_illegal;
2313 if (exp.X_op != O_constant)
2315 as_bad (_("expected , <constant>"));
2316 ignore_rest_of_line ();
2320 num_regs = exp.X_add_number;
2322 if (num_regs < 1 || num_regs > 4)
2324 as_bad (_("number of registers must be in the range [1:4]"));
2325 ignore_rest_of_line ();
2329 demand_empty_rest_of_line ();
2334 op = 0xb4 | (num_regs - 1);
2335 add_unwind_opcode (op, 1);
2340 op = 0xc800 | (reg << 4) | (num_regs - 1);
2341 add_unwind_opcode (op, 2);
2343 unwind.frame_size += num_regs * 12;
2347 /* Parse a directive saving VFP registers. */
2350 s_arm_unwind_save_vfp (void)
2356 count = parse_vfp_reg_list (&input_line_pointer, ®, 1);
2359 as_bad (_("expected register list"));
2360 ignore_rest_of_line ();
2364 demand_empty_rest_of_line ();
2369 op = 0xb8 | (count - 1);
2370 add_unwind_opcode (op, 1);
2375 op = 0xb300 | (reg << 4) | (count - 1);
2376 add_unwind_opcode (op, 2);
2378 unwind.frame_size += count * 8 + 4;
2382 /* Parse a directive saving iWMMXt data registers. */
2385 s_arm_unwind_save_mmxwr (void)
2393 if (*input_line_pointer == '{')
2394 input_line_pointer++;
2398 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2402 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2407 as_tsktsk (_("register list not in ascending order"));
2410 if (*input_line_pointer == '-')
2412 input_line_pointer++;
2413 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2416 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2419 else if (reg >= hi_reg)
2421 as_bad (_("bad register range"));
2424 for (; reg < hi_reg; reg++)
2428 while (skip_past_comma (&input_line_pointer) != FAIL);
2430 if (*input_line_pointer == '}')
2431 input_line_pointer++;
2433 demand_empty_rest_of_line ();
2435 /* Generate any deferred opcodes becuuse we're going to be looking at
2437 flush_pending_unwind ();
2439 for (i = 0; i < 16; i++)
2441 if (mask & (1 << i))
2442 unwind.frame_size += 8;
2445 /* Attempt to combine with a previous opcode. We do this because gcc
2446 likes to output separate unwind directives for a single block of
2448 if (unwind.opcode_count > 0)
2450 i = unwind.opcodes[unwind.opcode_count - 1];
2451 if ((i & 0xf8) == 0xc0)
2454 /* Only merge if the blocks are contiguous. */
2457 if ((mask & 0xfe00) == (1 << 9))
2459 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
2460 unwind.opcode_count--;
2463 else if (i == 6 && unwind.opcode_count >= 2)
2465 i = unwind.opcodes[unwind.opcode_count - 2];
2469 op = 0xffff << (reg - 1);
2471 || ((mask & op) == (1u << (reg - 1))))
2473 op = (1 << (reg + i + 1)) - 1;
2474 op &= ~((1 << reg) - 1);
2476 unwind.opcode_count -= 2;
2483 /* We want to generate opcodes in the order the registers have been
2484 saved, ie. descending order. */
2485 for (reg = 15; reg >= -1; reg--)
2487 /* Save registers in blocks. */
2489 || !(mask & (1 << reg)))
2491 /* We found an unsaved reg. Generate opcodes to save the
2492 preceeding block. */
2498 op = 0xc0 | (hi_reg - 10);
2499 add_unwind_opcode (op, 1);
2504 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
2505 add_unwind_opcode (op, 2);
2514 ignore_rest_of_line ();
2518 s_arm_unwind_save_mmxwcg (void)
2525 if (*input_line_pointer == '{')
2526 input_line_pointer++;
2530 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2534 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2540 as_tsktsk (_("register list not in ascending order"));
2543 if (*input_line_pointer == '-')
2545 input_line_pointer++;
2546 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2549 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2552 else if (reg >= hi_reg)
2554 as_bad (_("bad register range"));
2557 for (; reg < hi_reg; reg++)
2561 while (skip_past_comma (&input_line_pointer) != FAIL);
2563 if (*input_line_pointer == '}')
2564 input_line_pointer++;
2566 demand_empty_rest_of_line ();
2568 /* Generate any deferred opcodes becuuse we're going to be looking at
2570 flush_pending_unwind ();
2572 for (reg = 0; reg < 16; reg++)
2574 if (mask & (1 << reg))
2575 unwind.frame_size += 4;
2578 add_unwind_opcode (op, 2);
2581 ignore_rest_of_line ();
2585 /* Parse an unwind_save directive. */
2588 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
2591 struct reg_entry *reg;
2592 bfd_boolean had_brace = FALSE;
2594 /* Figure out what sort of save we have. */
2595 peek = input_line_pointer;
2603 reg = arm_reg_parse_multi (&peek);
2607 as_bad (_("register expected"));
2608 ignore_rest_of_line ();
2617 as_bad (_("FPA .unwind_save does not take a register list"));
2618 ignore_rest_of_line ();
2621 s_arm_unwind_save_fpa (reg->number);
2624 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
2625 case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
2626 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
2627 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
2630 as_bad (_(".unwind_save does not support this kind of register"));
2631 ignore_rest_of_line ();
2636 /* Parse an unwind_movsp directive. */
2639 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
2644 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2647 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
2648 ignore_rest_of_line ();
2651 demand_empty_rest_of_line ();
2653 if (reg == REG_SP || reg == REG_PC)
2655 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2659 if (unwind.fp_reg != REG_SP)
2660 as_bad (_("unexpected .unwind_movsp directive"));
2662 /* Generate opcode to restore the value. */
2664 add_unwind_opcode (op, 1);
2666 /* Record the information for later. */
2667 unwind.fp_reg = reg;
2668 unwind.fp_offset = unwind.frame_size;
2669 unwind.sp_restored = 1;
2672 /* Parse an unwind_pad directive. */
2675 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
2679 if (immediate_for_directive (&offset) == FAIL)
2684 as_bad (_("stack increment must be multiple of 4"));
2685 ignore_rest_of_line ();
2689 /* Don't generate any opcodes, just record the details for later. */
2690 unwind.frame_size += offset;
2691 unwind.pending_offset += offset;
2693 demand_empty_rest_of_line ();
2696 /* Parse an unwind_setfp directive. */
2699 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
2705 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2706 if (skip_past_comma (&input_line_pointer) == FAIL)
2709 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2711 if (fp_reg == FAIL || sp_reg == FAIL)
2713 as_bad (_("expected <reg>, <reg>"));
2714 ignore_rest_of_line ();
2718 /* Optional constant. */
2719 if (skip_past_comma (&input_line_pointer) != FAIL)
2721 if (immediate_for_directive (&offset) == FAIL)
2727 demand_empty_rest_of_line ();
2729 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
2731 as_bad (_("register must be either sp or set by a previous"
2732 "unwind_movsp directive"));
2736 /* Don't generate any opcodes, just record the information for later. */
2737 unwind.fp_reg = fp_reg;
2740 unwind.fp_offset = unwind.frame_size - offset;
2742 unwind.fp_offset -= offset;
2745 /* Parse an unwind_raw directive. */
2748 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
2751 /* This is an arbitary limit. */
2752 unsigned char op[16];
2756 if (exp.X_op == O_constant
2757 && skip_past_comma (&input_line_pointer) != FAIL)
2759 unwind.frame_size += exp.X_add_number;
2763 exp.X_op = O_illegal;
2765 if (exp.X_op != O_constant)
2767 as_bad (_("expected <offset>, <opcode>"));
2768 ignore_rest_of_line ();
2774 /* Parse the opcode. */
2779 as_bad (_("unwind opcode too long"));
2780 ignore_rest_of_line ();
2782 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
2784 as_bad (_("invalid unwind opcode"));
2785 ignore_rest_of_line ();
2788 op[count++] = exp.X_add_number;
2790 /* Parse the next byte. */
2791 if (skip_past_comma (&input_line_pointer) == FAIL)
2797 /* Add the opcode bytes in reverse order. */
2799 add_unwind_opcode (op[count], 1);
2801 demand_empty_rest_of_line ();
2805 /* Parse a .eabi_attribute directive. */
2808 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
2811 bfd_boolean is_string;
2818 if (exp.X_op != O_constant)
2821 tag = exp.X_add_number;
2822 if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0))
2827 if (skip_past_comma (&input_line_pointer) == FAIL)
2829 if (tag == 32 || !is_string)
2832 if (exp.X_op != O_constant)
2834 as_bad (_("expected numeric constant"));
2835 ignore_rest_of_line ();
2838 i = exp.X_add_number;
2840 if (tag == Tag_compatibility
2841 && skip_past_comma (&input_line_pointer) == FAIL)
2843 as_bad (_("expected comma"));
2844 ignore_rest_of_line ();
2849 skip_whitespace(input_line_pointer);
2850 if (*input_line_pointer != '"')
2852 input_line_pointer++;
2853 s = input_line_pointer;
2854 while (*input_line_pointer && *input_line_pointer != '"')
2855 input_line_pointer++;
2856 if (*input_line_pointer != '"')
2858 saved_char = *input_line_pointer;
2859 *input_line_pointer = 0;
2867 if (tag == Tag_compatibility)
2868 elf32_arm_add_eabi_attr_compat (stdoutput, i, s);
2870 elf32_arm_add_eabi_attr_string (stdoutput, tag, s);
2872 elf32_arm_add_eabi_attr_int (stdoutput, tag, i);
2876 *input_line_pointer = saved_char;
2877 input_line_pointer++;
2879 demand_empty_rest_of_line ();
2882 as_bad (_("bad string constant"));
2883 ignore_rest_of_line ();
2886 as_bad (_("expected <tag> , <value>"));
2887 ignore_rest_of_line ();
2890 static void s_arm_arch (int);
2891 static void s_arm_cpu (int);
2892 static void s_arm_fpu (int);
2893 #endif /* OBJ_ELF */
2895 /* This table describes all the machine specific pseudo-ops the assembler
2896 has to support. The fields are:
2897 pseudo-op name without dot
2898 function to call to execute this pseudo-op
2899 Integer arg to pass to the function. */
2901 const pseudo_typeS md_pseudo_table[] =
2903 /* Never called because '.req' does not start a line. */
2904 { "req", s_req, 0 },
2905 { "unreq", s_unreq, 0 },
2906 { "bss", s_bss, 0 },
2907 { "align", s_align, 0 },
2908 { "arm", s_arm, 0 },
2909 { "thumb", s_thumb, 0 },
2910 { "code", s_code, 0 },
2911 { "force_thumb", s_force_thumb, 0 },
2912 { "thumb_func", s_thumb_func, 0 },
2913 { "thumb_set", s_thumb_set, 0 },
2914 { "even", s_even, 0 },
2915 { "ltorg", s_ltorg, 0 },
2916 { "pool", s_ltorg, 0 },
2917 { "syntax", s_syntax, 0 },
2919 { "word", s_arm_elf_cons, 4 },
2920 { "long", s_arm_elf_cons, 4 },
2921 { "rel31", s_arm_rel31, 0 },
2922 { "fnstart", s_arm_unwind_fnstart, 0 },
2923 { "fnend", s_arm_unwind_fnend, 0 },
2924 { "cantunwind", s_arm_unwind_cantunwind, 0 },
2925 { "personality", s_arm_unwind_personality, 0 },
2926 { "personalityindex", s_arm_unwind_personalityindex, 0 },
2927 { "handlerdata", s_arm_unwind_handlerdata, 0 },
2928 { "save", s_arm_unwind_save, 0 },
2929 { "movsp", s_arm_unwind_movsp, 0 },
2930 { "pad", s_arm_unwind_pad, 0 },
2931 { "setfp", s_arm_unwind_setfp, 0 },
2932 { "unwind_raw", s_arm_unwind_raw, 0 },
2933 { "cpu", s_arm_cpu, 0 },
2934 { "arch", s_arm_arch, 0 },
2935 { "fpu", s_arm_fpu, 0 },
2936 { "eabi_attribute", s_arm_eabi_attribute, 0 },
2940 { "extend", float_cons, 'x' },
2941 { "ldouble", float_cons, 'x' },
2942 { "packed", float_cons, 'p' },
2946 /* Parser functions used exclusively in instruction operands. */
2948 /* Generic immediate-value read function for use in insn parsing.
2949 STR points to the beginning of the immediate (the leading #);
2950 VAL receives the value; if the value is outside [MIN, MAX]
2951 issue an error. PREFIX_OPT is true if the immediate prefix is
2955 parse_immediate (char **str, int *val, int min, int max,
2956 bfd_boolean prefix_opt)
2959 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
2960 if (exp.X_op != O_constant)
2962 inst.error = _("constant expression required");
2966 if (exp.X_add_number < min || exp.X_add_number > max)
2968 inst.error = _("immediate value out of range");
2972 *val = exp.X_add_number;
2976 /* Returns the pseudo-register number of an FPA immediate constant,
2977 or FAIL if there isn't a valid constant here. */
2980 parse_fpa_immediate (char ** str)
2982 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2988 /* First try and match exact strings, this is to guarantee
2989 that some formats will work even for cross assembly. */
2991 for (i = 0; fp_const[i]; i++)
2993 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2997 *str += strlen (fp_const[i]);
2998 if (is_end_of_line[(unsigned char) **str])
3004 /* Just because we didn't get a match doesn't mean that the constant
3005 isn't valid, just that it is in a format that we don't
3006 automatically recognize. Try parsing it with the standard
3007 expression routines. */
3009 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
3011 /* Look for a raw floating point number. */
3012 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
3013 && is_end_of_line[(unsigned char) *save_in])
3015 for (i = 0; i < NUM_FLOAT_VALS; i++)
3017 for (j = 0; j < MAX_LITTLENUMS; j++)
3019 if (words[j] != fp_values[i][j])
3023 if (j == MAX_LITTLENUMS)
3031 /* Try and parse a more complex expression, this will probably fail
3032 unless the code uses a floating point prefix (eg "0f"). */
3033 save_in = input_line_pointer;
3034 input_line_pointer = *str;
3035 if (expression (&exp) == absolute_section
3036 && exp.X_op == O_big
3037 && exp.X_add_number < 0)
3039 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3041 if (gen_to_words (words, 5, (long) 15) == 0)
3043 for (i = 0; i < NUM_FLOAT_VALS; i++)
3045 for (j = 0; j < MAX_LITTLENUMS; j++)
3047 if (words[j] != fp_values[i][j])
3051 if (j == MAX_LITTLENUMS)
3053 *str = input_line_pointer;
3054 input_line_pointer = save_in;
3061 *str = input_line_pointer;
3062 input_line_pointer = save_in;
3063 inst.error = _("invalid FPA immediate expression");
3067 /* Shift operands. */
3070 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
3073 struct asm_shift_name
3076 enum shift_kind kind;
3079 /* Third argument to parse_shift. */
3080 enum parse_shift_mode
3082 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
3083 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
3084 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
3085 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
3086 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
3089 /* Parse a <shift> specifier on an ARM data processing instruction.
3090 This has three forms:
3092 (LSL|LSR|ASL|ASR|ROR) Rs
3093 (LSL|LSR|ASL|ASR|ROR) #imm
3096 Note that ASL is assimilated to LSL in the instruction encoding, and
3097 RRX to ROR #0 (which cannot be written as such). */
3100 parse_shift (char **str, int i, enum parse_shift_mode mode)
3102 const struct asm_shift_name *shift_name;
3103 enum shift_kind shift;
3108 for (p = *str; ISALPHA (*p); p++)
3113 inst.error = _("shift expression expected");
3117 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
3119 if (shift_name == NULL)
3121 inst.error = _("shift expression expected");
3125 shift = shift_name->kind;
3129 case NO_SHIFT_RESTRICT:
3130 case SHIFT_IMMEDIATE: break;
3132 case SHIFT_LSL_OR_ASR_IMMEDIATE:
3133 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
3135 inst.error = _("'LSL' or 'ASR' required");
3140 case SHIFT_LSL_IMMEDIATE:
3141 if (shift != SHIFT_LSL)
3143 inst.error = _("'LSL' required");
3148 case SHIFT_ASR_IMMEDIATE:
3149 if (shift != SHIFT_ASR)
3151 inst.error = _("'ASR' required");
3159 if (shift != SHIFT_RRX)
3161 /* Whitespace can appear here if the next thing is a bare digit. */
3162 skip_whitespace (p);
3164 if (mode == NO_SHIFT_RESTRICT
3165 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3167 inst.operands[i].imm = reg;
3168 inst.operands[i].immisreg = 1;
3170 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3173 inst.operands[i].shift_kind = shift;
3174 inst.operands[i].shifted = 1;
3179 /* Parse a <shifter_operand> for an ARM data processing instruction:
3182 #<immediate>, <rotate>
3186 where <shift> is defined by parse_shift above, and <rotate> is a
3187 multiple of 2 between 0 and 30. Validation of immediate operands
3188 is deferred to md_apply_fix. */
3191 parse_shifter_operand (char **str, int i)
3196 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
3198 inst.operands[i].reg = value;
3199 inst.operands[i].isreg = 1;
3201 /* parse_shift will override this if appropriate */
3202 inst.reloc.exp.X_op = O_constant;
3203 inst.reloc.exp.X_add_number = 0;
3205 if (skip_past_comma (str) == FAIL)
3208 /* Shift operation on register. */
3209 return parse_shift (str, i, NO_SHIFT_RESTRICT);
3212 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
3215 if (skip_past_comma (str) == SUCCESS)
3217 /* #x, y -- ie explicit rotation by Y. */
3218 if (my_get_expression (&expr, str, GE_NO_PREFIX))
3221 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
3223 inst.error = _("constant expression expected");
3227 value = expr.X_add_number;
3228 if (value < 0 || value > 30 || value % 2 != 0)
3230 inst.error = _("invalid rotation");
3233 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
3235 inst.error = _("invalid constant");
3239 /* Convert to decoded value. md_apply_fix will put it back. */
3240 inst.reloc.exp.X_add_number
3241 = (((inst.reloc.exp.X_add_number << (32 - value))
3242 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
3245 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3246 inst.reloc.pc_rel = 0;
3250 /* Parse all forms of an ARM address expression. Information is written
3251 to inst.operands[i] and/or inst.reloc.
3253 Preindexed addressing (.preind=1):
3255 [Rn, #offset] .reg=Rn .reloc.exp=offset
3256 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3257 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3258 .shift_kind=shift .reloc.exp=shift_imm
3260 These three may have a trailing ! which causes .writeback to be set also.
3262 Postindexed addressing (.postind=1, .writeback=1):
3264 [Rn], #offset .reg=Rn .reloc.exp=offset
3265 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3266 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3267 .shift_kind=shift .reloc.exp=shift_imm
3269 Unindexed addressing (.preind=0, .postind=0):
3271 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3275 [Rn]{!} shorthand for [Rn,#0]{!}
3276 =immediate .isreg=0 .reloc.exp=immediate
3277 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3279 It is the caller's responsibility to check for addressing modes not
3280 supported by the instruction, and to set inst.reloc.type. */
3283 parse_address (char **str, int i)
3288 if (skip_past_char (&p, '[') == FAIL)
3290 if (skip_past_char (&p, '=') == FAIL)
3292 /* bare address - translate to PC-relative offset */
3293 inst.reloc.pc_rel = 1;
3294 inst.operands[i].reg = REG_PC;
3295 inst.operands[i].isreg = 1;
3296 inst.operands[i].preind = 1;
3298 /* else a load-constant pseudo op, no special treatment needed here */
3300 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
3307 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3309 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3312 inst.operands[i].reg = reg;
3313 inst.operands[i].isreg = 1;
3315 if (skip_past_comma (&p) == SUCCESS)
3317 inst.operands[i].preind = 1;
3320 else if (*p == '-') p++, inst.operands[i].negative = 1;
3322 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3324 inst.operands[i].imm = reg;
3325 inst.operands[i].immisreg = 1;
3327 if (skip_past_comma (&p) == SUCCESS)
3328 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3333 if (inst.operands[i].negative)
3335 inst.operands[i].negative = 0;
3338 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3343 if (skip_past_char (&p, ']') == FAIL)
3345 inst.error = _("']' expected");
3349 if (skip_past_char (&p, '!') == SUCCESS)
3350 inst.operands[i].writeback = 1;
3352 else if (skip_past_comma (&p) == SUCCESS)
3354 if (skip_past_char (&p, '{') == SUCCESS)
3356 /* [Rn], {expr} - unindexed, with option */
3357 if (parse_immediate (&p, &inst.operands[i].imm,
3358 0, 255, TRUE) == FAIL)
3361 if (skip_past_char (&p, '}') == FAIL)
3363 inst.error = _("'}' expected at end of 'option' field");
3366 if (inst.operands[i].preind)
3368 inst.error = _("cannot combine index with option");
3376 inst.operands[i].postind = 1;
3377 inst.operands[i].writeback = 1;
3379 if (inst.operands[i].preind)
3381 inst.error = _("cannot combine pre- and post-indexing");
3386 else if (*p == '-') p++, inst.operands[i].negative = 1;
3388 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3390 inst.operands[i].imm = reg;
3391 inst.operands[i].immisreg = 1;
3393 if (skip_past_comma (&p) == SUCCESS)
3394 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3399 if (inst.operands[i].negative)
3401 inst.operands[i].negative = 0;
3404 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3410 /* If at this point neither .preind nor .postind is set, we have a
3411 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3412 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
3414 inst.operands[i].preind = 1;
3415 inst.reloc.exp.X_op = O_constant;
3416 inst.reloc.exp.X_add_number = 0;
3422 /* Miscellaneous. */
3424 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3425 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3427 parse_psr (char **str)
3430 unsigned long psr_field;
3432 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3433 feature for ease of use and backwards compatibility. */
3435 if (*p == 's' || *p == 'S')
3436 psr_field = SPSR_BIT;
3437 else if (*p == 'c' || *p == 'C')
3443 if (strncasecmp (p, "PSR", 3) != 0)
3449 /* A suffix follows. */
3450 const struct asm_psr *psr;
3458 while (ISALNUM (*p) || *p == '_');
3460 psr = hash_find_n (arm_psr_hsh, start, p - start);
3464 psr_field |= psr->field;
3469 goto error; /* Garbage after "[CS]PSR". */
3471 psr_field |= (PSR_c | PSR_f);
3477 inst.error = _("flag for {c}psr instruction expected");
3481 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3482 value suitable for splatting into the AIF field of the instruction. */
3485 parse_cps_flags (char **str)
3494 case '\0': case ',':
3497 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
3498 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
3499 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
3502 inst.error = _("unrecognized CPS flag");
3507 if (saw_a_flag == 0)
3509 inst.error = _("missing CPS flags");
3517 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3518 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3521 parse_endian_specifier (char **str)
3526 if (strncasecmp (s, "BE", 2))
3528 else if (strncasecmp (s, "LE", 2))
3532 inst.error = _("valid endian specifiers are be or le");
3536 if (ISALNUM (s[2]) || s[2] == '_')
3538 inst.error = _("valid endian specifiers are be or le");
3543 return little_endian;
3546 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3547 value suitable for poking into the rotate field of an sxt or sxta
3548 instruction, or FAIL on error. */
3551 parse_ror (char **str)
3556 if (strncasecmp (s, "ROR", 3) == 0)
3560 inst.error = _("missing rotation field after comma");
3564 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
3569 case 0: *str = s; return 0x0;
3570 case 8: *str = s; return 0x1;
3571 case 16: *str = s; return 0x2;
3572 case 24: *str = s; return 0x3;
3575 inst.error = _("rotation can only be 0, 8, 16, or 24");
3580 /* Parse a conditional code (from conds[] below). The value returned is in the
3581 range 0 .. 14, or FAIL. */
3583 parse_cond (char **str)
3586 const struct asm_cond *c;
3589 while (ISALPHA (*q))
3592 c = hash_find_n (arm_cond_hsh, p, q - p);
3595 inst.error = _("condition required");
3603 /* Parse the operands of a table branch instruction. Similar to a memory
3606 parse_tb (char **str)
3611 if (skip_past_char (&p, '[') == FAIL)
3614 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3616 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3619 inst.operands[0].reg = reg;
3621 if (skip_past_comma (&p) == FAIL)
3624 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3626 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3629 inst.operands[0].imm = reg;
3631 if (skip_past_comma (&p) == SUCCESS)
3633 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
3635 if (inst.reloc.exp.X_add_number != 1)
3637 inst.error = _("invalid shift");
3640 inst.operands[0].shifted = 1;
3643 if (skip_past_char (&p, ']') == FAIL)
3645 inst.error = _("']' expected");
3652 /* Matcher codes for parse_operands. */
3653 enum operand_parse_code
3655 OP_stop, /* end of line */
3657 OP_RR, /* ARM register */
3658 OP_RRnpc, /* ARM register, not r15 */
3659 OP_RRnpcb, /* ARM register, not r15, in square brackets */
3660 OP_RRw, /* ARM register, not r15, optional trailing ! */
3661 OP_RCP, /* Coprocessor number */
3662 OP_RCN, /* Coprocessor register */
3663 OP_RF, /* FPA register */
3664 OP_RVS, /* VFP single precision register */
3665 OP_RVD, /* VFP double precision register */
3666 OP_RVC, /* VFP control register */
3667 OP_RMF, /* Maverick F register */
3668 OP_RMD, /* Maverick D register */
3669 OP_RMFX, /* Maverick FX register */
3670 OP_RMDX, /* Maverick DX register */
3671 OP_RMAX, /* Maverick AX register */
3672 OP_RMDS, /* Maverick DSPSC register */
3673 OP_RIWR, /* iWMMXt wR register */
3674 OP_RIWC, /* iWMMXt wC register */
3675 OP_RIWG, /* iWMMXt wCG register */
3676 OP_RXA, /* XScale accumulator register */
3678 OP_REGLST, /* ARM register list */
3679 OP_VRSLST, /* VFP single-precision register list */
3680 OP_VRDLST, /* VFP double-precision register list */
3682 OP_I7, /* immediate value 0 .. 7 */
3683 OP_I15, /* 0 .. 15 */
3684 OP_I16, /* 1 .. 16 */
3685 OP_I31, /* 0 .. 31 */
3686 OP_I31w, /* 0 .. 31, optional trailing ! */
3687 OP_I32, /* 1 .. 32 */
3688 OP_I63s, /* -64 .. 63 */
3689 OP_I255, /* 0 .. 255 */
3690 OP_Iffff, /* 0 .. 65535 */
3692 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
3693 OP_I7b, /* 0 .. 7 */
3694 OP_I15b, /* 0 .. 15 */
3695 OP_I31b, /* 0 .. 31 */
3697 OP_SH, /* shifter operand */
3698 OP_ADDR, /* Memory address expression (any mode) */
3699 OP_EXP, /* arbitrary expression */
3700 OP_EXPi, /* same, with optional immediate prefix */
3701 OP_EXPr, /* same, with optional relocation suffix */
3703 OP_CPSF, /* CPS flags */
3704 OP_ENDI, /* Endianness specifier */
3705 OP_PSR, /* CPSR/SPSR mask for msr */
3706 OP_COND, /* conditional code */
3707 OP_TB, /* Table branch. */
3709 OP_RRnpc_I0, /* ARM register or literal 0 */
3710 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
3711 OP_RR_EXi, /* ARM register or expression with imm prefix */
3712 OP_RF_IF, /* FPA register or immediate */
3713 OP_RIWR_RIWC, /* iWMMXt R or C reg */
3715 /* Optional operands. */
3716 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
3717 OP_oI31b, /* 0 .. 31 */
3718 OP_oIffffb, /* 0 .. 65535 */
3719 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
3721 OP_oRR, /* ARM register */
3722 OP_oRRnpc, /* ARM register, not the PC */
3723 OP_oSHll, /* LSL immediate */
3724 OP_oSHar, /* ASR immediate */
3725 OP_oSHllar, /* LSL or ASR immediate */
3726 OP_oROR, /* ROR 0/8/16/24 */
3728 OP_FIRST_OPTIONAL = OP_oI7b
3731 /* Generic instruction operand parser. This does no encoding and no
3732 semantic validation; it merely squirrels values away in the inst
3733 structure. Returns SUCCESS or FAIL depending on whether the
3734 specified grammar matched. */
3736 parse_operands (char *str, const unsigned char *pattern)
3738 unsigned const char *upat = pattern;
3739 char *backtrack_pos = 0;
3740 const char *backtrack_error = 0;
3741 int i, val, backtrack_index = 0;
3743 #define po_char_or_fail(chr) do { \
3744 if (skip_past_char (&str, chr) == FAIL) \
3748 #define po_reg_or_fail(regtype) do { \
3749 val = arm_reg_parse (&str, regtype); \
3752 inst.error = _(reg_expected_msgs[regtype]); \
3755 inst.operands[i].reg = val; \
3756 inst.operands[i].isreg = 1; \
3759 #define po_reg_or_goto(regtype, label) do { \
3760 val = arm_reg_parse (&str, regtype); \
3764 inst.operands[i].reg = val; \
3765 inst.operands[i].isreg = 1; \
3768 #define po_imm_or_fail(min, max, popt) do { \
3769 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3771 inst.operands[i].imm = val; \
3774 #define po_misc_or_fail(expr) do { \
3779 skip_whitespace (str);
3781 for (i = 0; upat[i] != OP_stop; i++)
3783 if (upat[i] >= OP_FIRST_OPTIONAL)
3785 /* Remember where we are in case we need to backtrack. */
3786 assert (!backtrack_pos);
3787 backtrack_pos = str;
3788 backtrack_error = inst.error;
3789 backtrack_index = i;
3793 po_char_or_fail (',');
3801 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
3802 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
3803 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
3804 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
3805 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
3806 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
3807 case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
3808 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
3809 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
3810 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
3811 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
3812 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
3813 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
3814 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
3815 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
3816 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
3817 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
3820 po_char_or_fail ('[');
3821 po_reg_or_fail (REG_TYPE_RN);
3822 po_char_or_fail (']');
3826 po_reg_or_fail (REG_TYPE_RN);
3827 if (skip_past_char (&str, '!') == SUCCESS)
3828 inst.operands[i].writeback = 1;
3832 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
3833 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
3834 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
3835 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
3836 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
3837 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
3838 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
3839 case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
3841 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
3843 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
3844 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
3846 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
3847 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
3849 /* Immediate variants */
3851 po_char_or_fail ('{');
3852 po_imm_or_fail (0, 255, TRUE);
3853 po_char_or_fail ('}');
3857 /* The expression parser chokes on a trailing !, so we have
3858 to find it first and zap it. */
3861 while (*s && *s != ',')
3866 inst.operands[i].writeback = 1;
3868 po_imm_or_fail (0, 31, TRUE);
3876 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3881 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3886 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3888 if (inst.reloc.exp.X_op == O_symbol)
3890 val = parse_reloc (&str);
3893 inst.error = _("unrecognized relocation suffix");
3896 else if (val != BFD_RELOC_UNUSED)
3898 inst.operands[i].imm = val;
3899 inst.operands[i].hasreloc = 1;
3904 /* Register or expression */
3905 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
3906 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
3908 /* Register or immediate */
3909 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
3910 I0: po_imm_or_fail (0, 0, FALSE); break;
3912 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
3914 if (!is_immediate_prefix (*str))
3917 val = parse_fpa_immediate (&str);
3920 /* FPA immediates are encoded as registers 8-15.
3921 parse_fpa_immediate has already applied the offset. */
3922 inst.operands[i].reg = val;
3923 inst.operands[i].isreg = 1;
3926 /* Two kinds of register */
3929 struct reg_entry *rege = arm_reg_parse_multi (&str);
3930 if (rege->type != REG_TYPE_MMXWR
3931 && rege->type != REG_TYPE_MMXWC
3932 && rege->type != REG_TYPE_MMXWCG)
3934 inst.error = _("iWMMXt data or control register expected");
3937 inst.operands[i].reg = rege->number;
3938 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
3943 case OP_CPSF: val = parse_cps_flags (&str); break;
3944 case OP_ENDI: val = parse_endian_specifier (&str); break;
3945 case OP_oROR: val = parse_ror (&str); break;
3946 case OP_PSR: val = parse_psr (&str); break;
3947 case OP_COND: val = parse_cond (&str); break;
3950 po_misc_or_fail (parse_tb (&str));
3953 /* Register lists */
3955 val = parse_reg_list (&str);
3958 inst.operands[1].writeback = 1;
3964 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
3968 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
3971 /* Addressing modes */
3973 po_misc_or_fail (parse_address (&str, i));
3977 po_misc_or_fail (parse_shifter_operand (&str, i));
3981 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
3985 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
3989 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
3993 as_fatal ("unhandled operand code %d", upat[i]);
3996 /* Various value-based sanity checks and shared operations. We
3997 do not signal immediate failures for the register constraints;
3998 this allows a syntax error to take precedence. */
4006 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
4007 inst.error = BAD_PC;
4020 inst.operands[i].imm = val;
4027 /* If we get here, this operand was successfully parsed. */
4028 inst.operands[i].present = 1;
4032 inst.error = BAD_ARGS;
4038 /* Do not backtrack over a trailing optional argument that
4039 absorbed some text. We will only fail again, with the
4040 'garbage following instruction' error message, which is
4041 probably less helpful than the current one. */
4042 if (backtrack_index == i && backtrack_pos != str
4043 && upat[i+1] == OP_stop)
4046 /* Try again, skipping the optional argument at backtrack_pos. */
4047 str = backtrack_pos;
4048 inst.error = backtrack_error;
4049 inst.operands[backtrack_index].present = 0;
4050 i = backtrack_index;
4054 /* Check that we have parsed all the arguments. */
4055 if (*str != '\0' && !inst.error)
4056 inst.error = _("garbage following instruction");
4058 return inst.error ? FAIL : SUCCESS;
4061 #undef po_char_or_fail
4062 #undef po_reg_or_fail
4063 #undef po_reg_or_goto
4064 #undef po_imm_or_fail
4066 /* Shorthand macro for instruction encoding functions issuing errors. */
4067 #define constraint(expr, err) do { \
4075 /* Functions for operand encoding. ARM, then Thumb. */
4077 #define rotate_left(v, n) (v << n | v >> (32 - n))
4079 /* If VAL can be encoded in the immediate field of an ARM instruction,
4080 return the encoded form. Otherwise, return FAIL. */
4083 encode_arm_immediate (unsigned int val)
4087 for (i = 0; i < 32; i += 2)
4088 if ((a = rotate_left (val, i)) <= 0xff)
4089 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
4094 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
4095 return the encoded form. Otherwise, return FAIL. */
4097 encode_thumb32_immediate (unsigned int val)
4104 for (i = 1; i <= 24; i++)
4107 if ((val & ~(0xff << i)) == 0)
4108 return ((val >> i) & 0x7f) | ((32 - i) << 7);
4112 if (val == ((a << 16) | a))
4114 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
4118 if (val == ((a << 16) | a))
4119 return 0x200 | (a >> 8);
4123 /* Encode a VFP SP register number into inst.instruction. */
4126 encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
4131 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
4135 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
4139 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
4147 /* Encode a <shift> in an ARM-format instruction. The immediate,
4148 if any, is handled by md_apply_fix. */
4150 encode_arm_shift (int i)
4152 if (inst.operands[i].shift_kind == SHIFT_RRX)
4153 inst.instruction |= SHIFT_ROR << 5;
4156 inst.instruction |= inst.operands[i].shift_kind << 5;
4157 if (inst.operands[i].immisreg)
4159 inst.instruction |= SHIFT_BY_REG;
4160 inst.instruction |= inst.operands[i].imm << 8;
4163 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4168 encode_arm_shifter_operand (int i)
4170 if (inst.operands[i].isreg)
4172 inst.instruction |= inst.operands[i].reg;
4173 encode_arm_shift (i);
4176 inst.instruction |= INST_IMMEDIATE;
4179 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4181 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
4183 assert (inst.operands[i].isreg);
4184 inst.instruction |= inst.operands[i].reg << 16;
4186 if (inst.operands[i].preind)
4190 inst.error = _("instruction does not accept preindexed addressing");
4193 inst.instruction |= PRE_INDEX;
4194 if (inst.operands[i].writeback)
4195 inst.instruction |= WRITE_BACK;
4198 else if (inst.operands[i].postind)
4200 assert (inst.operands[i].writeback);
4202 inst.instruction |= WRITE_BACK;
4204 else /* unindexed - only for coprocessor */
4206 inst.error = _("instruction does not accept unindexed addressing");
4210 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
4211 && (((inst.instruction & 0x000f0000) >> 16)
4212 == ((inst.instruction & 0x0000f000) >> 12)))
4213 as_warn ((inst.instruction & LOAD_BIT)
4214 ? _("destination register same as write-back base")
4215 : _("source register same as write-back base"));
4218 /* inst.operands[i] was set up by parse_address. Encode it into an
4219 ARM-format mode 2 load or store instruction. If is_t is true,
4220 reject forms that cannot be used with a T instruction (i.e. not
4223 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
4225 encode_arm_addr_mode_common (i, is_t);
4227 if (inst.operands[i].immisreg)
4229 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
4230 inst.instruction |= inst.operands[i].imm;
4231 if (!inst.operands[i].negative)
4232 inst.instruction |= INDEX_UP;
4233 if (inst.operands[i].shifted)
4235 if (inst.operands[i].shift_kind == SHIFT_RRX)
4236 inst.instruction |= SHIFT_ROR << 5;
4239 inst.instruction |= inst.operands[i].shift_kind << 5;
4240 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4244 else /* immediate offset in inst.reloc */
4246 if (inst.reloc.type == BFD_RELOC_UNUSED)
4247 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4251 /* inst.operands[i] was set up by parse_address. Encode it into an
4252 ARM-format mode 3 load or store instruction. Reject forms that
4253 cannot be used with such instructions. If is_t is true, reject
4254 forms that cannot be used with a T instruction (i.e. not
4257 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
4259 if (inst.operands[i].immisreg && inst.operands[i].shifted)
4261 inst.error = _("instruction does not accept scaled register index");
4265 encode_arm_addr_mode_common (i, is_t);
4267 if (inst.operands[i].immisreg)
4269 inst.instruction |= inst.operands[i].imm;
4270 if (!inst.operands[i].negative)
4271 inst.instruction |= INDEX_UP;
4273 else /* immediate offset in inst.reloc */
4275 inst.instruction |= HWOFFSET_IMM;
4276 if (inst.reloc.type == BFD_RELOC_UNUSED)
4277 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4281 /* inst.operands[i] was set up by parse_address. Encode it into an
4282 ARM-format instruction. Reject all forms which cannot be encoded
4283 into a coprocessor load/store instruction. If wb_ok is false,
4284 reject use of writeback; if unind_ok is false, reject use of
4285 unindexed addressing. If reloc_override is not 0, use it instead
4286 of BFD_ARM_CP_OFF_IMM. */
4289 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
4291 inst.instruction |= inst.operands[i].reg << 16;
4293 assert (!(inst.operands[i].preind && inst.operands[i].postind));
4295 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
4297 assert (!inst.operands[i].writeback);
4300 inst.error = _("instruction does not support unindexed addressing");
4303 inst.instruction |= inst.operands[i].imm;
4304 inst.instruction |= INDEX_UP;
4308 if (inst.operands[i].preind)
4309 inst.instruction |= PRE_INDEX;
4311 if (inst.operands[i].writeback)
4313 if (inst.operands[i].reg == REG_PC)
4315 inst.error = _("pc may not be used with write-back");
4320 inst.error = _("instruction does not support writeback");
4323 inst.instruction |= WRITE_BACK;
4327 inst.reloc.type = reloc_override;
4328 else if (thumb_mode)
4329 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
4331 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
4335 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4336 Determine whether it can be performed with a move instruction; if
4337 it can, convert inst.instruction to that move instruction and
4338 return 1; if it can't, convert inst.instruction to a literal-pool
4339 load and return 0. If this is not a valid thing to do in the
4340 current context, set inst.error and return 1.
4342 inst.operands[i] describes the destination register. */
4345 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
4347 if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0)
4349 inst.error = _("invalid pseudo operation");
4352 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
4354 inst.error = _("constant expression expected");
4357 if (inst.reloc.exp.X_op == O_constant)
4361 if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
4363 /* This can be done with a mov(1) instruction. */
4364 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
4365 inst.instruction |= inst.reloc.exp.X_add_number;
4371 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
4374 /* This can be done with a mov instruction. */
4375 inst.instruction &= LITERAL_MASK;
4376 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4377 inst.instruction |= value & 0xfff;
4381 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
4384 /* This can be done with a mvn instruction. */
4385 inst.instruction &= LITERAL_MASK;
4386 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4387 inst.instruction |= value & 0xfff;
4393 if (add_to_lit_pool () == FAIL)
4395 inst.error = _("literal pool insertion failed");
4398 inst.operands[1].reg = REG_PC;
4399 inst.operands[1].isreg = 1;
4400 inst.operands[1].preind = 1;
4401 inst.reloc.pc_rel = 1;
4402 inst.reloc.type = (thumb_p
4403 ? BFD_RELOC_ARM_THUMB_OFFSET
4405 ? BFD_RELOC_ARM_HWLITERAL
4406 : BFD_RELOC_ARM_LITERAL));
4410 /* Functions for instruction encoding, sorted by subarchitecture.
4411 First some generics; their names are taken from the conventional
4412 bit positions for register arguments in ARM format instructions. */
4422 inst.instruction |= inst.operands[0].reg << 12;
4428 inst.instruction |= inst.operands[0].reg << 12;
4429 inst.instruction |= inst.operands[1].reg;
4435 inst.instruction |= inst.operands[0].reg << 12;
4436 inst.instruction |= inst.operands[1].reg << 16;
4442 inst.instruction |= inst.operands[0].reg << 16;
4443 inst.instruction |= inst.operands[1].reg << 12;
4449 unsigned Rn = inst.operands[2].reg;
4450 /* Enforce resutrictions on SWP instruction. */
4451 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
4452 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
4453 _("Rn must not overlap other operands"));
4454 inst.instruction |= inst.operands[0].reg << 12;
4455 inst.instruction |= inst.operands[1].reg;
4456 inst.instruction |= Rn << 16;
4462 inst.instruction |= inst.operands[0].reg << 12;
4463 inst.instruction |= inst.operands[1].reg << 16;
4464 inst.instruction |= inst.operands[2].reg;
4470 inst.instruction |= inst.operands[0].reg;
4471 inst.instruction |= inst.operands[1].reg << 12;
4472 inst.instruction |= inst.operands[2].reg << 16;
4478 inst.instruction |= inst.operands[0].imm;
4484 inst.instruction |= inst.operands[0].reg << 12;
4485 encode_arm_cp_address (1, TRUE, TRUE, 0);
4488 /* ARM instructions, in alphabetical order by function name (except
4489 that wrapper functions appear immediately after the function they
4492 /* This is a pseudo-op of the form "adr rd, label" to be converted
4493 into a relative address of the form "add rd, pc, #label-.-8". */
4498 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4500 /* Frag hacking will turn this into a sub instruction if the offset turns
4501 out to be negative. */
4502 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4503 inst.reloc.pc_rel = 1;
4504 inst.reloc.exp.X_add_number -= 8;
4507 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4508 into a relative address of the form:
4509 add rd, pc, #low(label-.-8)"
4510 add rd, rd, #high(label-.-8)" */
4515 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4517 /* Frag hacking will turn this into a sub instruction if the offset turns
4518 out to be negative. */
4519 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4520 inst.reloc.pc_rel = 1;
4521 inst.size = INSN_SIZE * 2;
4522 inst.reloc.exp.X_add_number -= 8;
4528 if (!inst.operands[1].present)
4529 inst.operands[1].reg = inst.operands[0].reg;
4530 inst.instruction |= inst.operands[0].reg << 12;
4531 inst.instruction |= inst.operands[1].reg << 16;
4532 encode_arm_shifter_operand (2);
4538 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
4539 constraint (msb > 32, _("bit-field extends past end of register"));
4540 /* The instruction encoding stores the LSB and MSB,
4541 not the LSB and width. */
4542 inst.instruction |= inst.operands[0].reg << 12;
4543 inst.instruction |= inst.operands[1].imm << 7;
4544 inst.instruction |= (msb - 1) << 16;
4552 /* #0 in second position is alternative syntax for bfc, which is
4553 the same instruction but with REG_PC in the Rm field. */
4554 if (!inst.operands[1].isreg)
4555 inst.operands[1].reg = REG_PC;
4557 msb = inst.operands[2].imm + inst.operands[3].imm;
4558 constraint (msb > 32, _("bit-field extends past end of register"));
4559 /* The instruction encoding stores the LSB and MSB,
4560 not the LSB and width. */
4561 inst.instruction |= inst.operands[0].reg << 12;
4562 inst.instruction |= inst.operands[1].reg;
4563 inst.instruction |= inst.operands[2].imm << 7;
4564 inst.instruction |= (msb - 1) << 16;
4570 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
4571 _("bit-field extends past end of register"));
4572 inst.instruction |= inst.operands[0].reg << 12;
4573 inst.instruction |= inst.operands[1].reg;
4574 inst.instruction |= inst.operands[2].imm << 7;
4575 inst.instruction |= (inst.operands[3].imm - 1) << 16;
4578 /* ARM V5 breakpoint instruction (argument parse)
4579 BKPT <16 bit unsigned immediate>
4580 Instruction is not conditional.
4581 The bit pattern given in insns[] has the COND_ALWAYS condition,
4582 and it is an error if the caller tried to override that. */
4587 /* Top 12 of 16 bits to bits 19:8. */
4588 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
4590 /* Bottom 4 of 16 bits to bits 3:0. */
4591 inst.instruction |= inst.operands[0].imm & 0xf;
4595 encode_branch (int default_reloc)
4597 if (inst.operands[0].hasreloc)
4599 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
4600 _("the only suffix valid here is '(plt)'"));
4601 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4605 inst.reloc.type = default_reloc;
4607 inst.reloc.pc_rel = 1;
4614 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4615 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
4618 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4625 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4627 if (inst.cond == COND_ALWAYS)
4628 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
4630 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
4634 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4637 /* ARM V5 branch-link-exchange instruction (argument parse)
4638 BLX <target_addr> ie BLX(1)
4639 BLX{<condition>} <Rm> ie BLX(2)
4640 Unfortunately, there are two different opcodes for this mnemonic.
4641 So, the insns[].value is not used, and the code here zaps values
4642 into inst.instruction.
4643 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4648 if (inst.operands[0].isreg)
4650 /* Arg is a register; the opcode provided by insns[] is correct.
4651 It is not illegal to do "blx pc", just useless. */
4652 if (inst.operands[0].reg == REG_PC)
4653 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4655 inst.instruction |= inst.operands[0].reg;
4659 /* Arg is an address; this instruction cannot be executed
4660 conditionally, and the opcode must be adjusted. */
4661 constraint (inst.cond != COND_ALWAYS, BAD_COND);
4662 inst.instruction = 0xfa000000;
4664 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4665 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
4668 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
4675 if (inst.operands[0].reg == REG_PC)
4676 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4678 inst.instruction |= inst.operands[0].reg;
4682 /* ARM v5TEJ. Jump to Jazelle code. */
4687 if (inst.operands[0].reg == REG_PC)
4688 as_tsktsk (_("use of r15 in bxj is not really useful"));
4690 inst.instruction |= inst.operands[0].reg;
4693 /* Co-processor data operation:
4694 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4695 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4699 inst.instruction |= inst.operands[0].reg << 8;
4700 inst.instruction |= inst.operands[1].imm << 20;
4701 inst.instruction |= inst.operands[2].reg << 12;
4702 inst.instruction |= inst.operands[3].reg << 16;
4703 inst.instruction |= inst.operands[4].reg;
4704 inst.instruction |= inst.operands[5].imm << 5;
4710 inst.instruction |= inst.operands[0].reg << 16;
4711 encode_arm_shifter_operand (1);
4714 /* Transfer between coprocessor and ARM registers.
4715 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4720 No special properties. */
4725 inst.instruction |= inst.operands[0].reg << 8;
4726 inst.instruction |= inst.operands[1].imm << 21;
4727 inst.instruction |= inst.operands[2].reg << 12;
4728 inst.instruction |= inst.operands[3].reg << 16;
4729 inst.instruction |= inst.operands[4].reg;
4730 inst.instruction |= inst.operands[5].imm << 5;
4733 /* Transfer between coprocessor register and pair of ARM registers.
4734 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4739 Two XScale instructions are special cases of these:
4741 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4742 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4744 Result unpredicatable if Rd or Rn is R15. */
4749 inst.instruction |= inst.operands[0].reg << 8;
4750 inst.instruction |= inst.operands[1].imm << 4;
4751 inst.instruction |= inst.operands[2].reg << 12;
4752 inst.instruction |= inst.operands[3].reg << 16;
4753 inst.instruction |= inst.operands[4].reg;
4759 inst.instruction |= inst.operands[0].imm << 6;
4760 inst.instruction |= inst.operands[1].imm;
4766 /* There is no IT instruction in ARM mode. We
4767 process it but do not generate code for it. */
4774 int base_reg = inst.operands[0].reg;
4775 int range = inst.operands[1].imm;
4777 inst.instruction |= base_reg << 16;
4778 inst.instruction |= range;
4780 if (inst.operands[1].writeback)
4781 inst.instruction |= LDM_TYPE_2_OR_3;
4783 if (inst.operands[0].writeback)
4785 inst.instruction |= WRITE_BACK;
4786 /* Check for unpredictable uses of writeback. */
4787 if (inst.instruction & LOAD_BIT)
4789 /* Not allowed in LDM type 2. */
4790 if ((inst.instruction & LDM_TYPE_2_OR_3)
4791 && ((range & (1 << REG_PC)) == 0))
4792 as_warn (_("writeback of base register is UNPREDICTABLE"));
4793 /* Only allowed if base reg not in list for other types. */
4794 else if (range & (1 << base_reg))
4795 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4799 /* Not allowed for type 2. */
4800 if (inst.instruction & LDM_TYPE_2_OR_3)
4801 as_warn (_("writeback of base register is UNPREDICTABLE"));
4802 /* Only allowed if base reg not in list, or first in list. */
4803 else if ((range & (1 << base_reg))
4804 && (range & ((1 << base_reg) - 1)))
4805 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4810 /* ARMv5TE load-consecutive (argument parse)
4819 constraint (inst.operands[0].reg % 2 != 0,
4820 _("first destination register must be even"));
4821 constraint (inst.operands[1].present
4822 && inst.operands[1].reg != inst.operands[0].reg + 1,
4823 _("can only load two consecutive registers"));
4824 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4825 constraint (!inst.operands[2].isreg, _("'[' expected"));
4827 if (!inst.operands[1].present)
4828 inst.operands[1].reg = inst.operands[0].reg + 1;
4830 if (inst.instruction & LOAD_BIT)
4832 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4833 register and the first register written; we have to diagnose
4834 overlap between the base and the second register written here. */
4836 if (inst.operands[2].reg == inst.operands[1].reg
4837 && (inst.operands[2].writeback || inst.operands[2].postind))
4838 as_warn (_("base register written back, and overlaps "
4839 "second destination register"));
4841 /* For an index-register load, the index register must not overlap the
4842 destination (even if not write-back). */
4843 else if (inst.operands[2].immisreg
4844 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
4845 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
4846 as_warn (_("index register overlaps destination register"));
4849 inst.instruction |= inst.operands[0].reg << 12;
4850 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
4856 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
4857 || inst.operands[1].postind || inst.operands[1].writeback
4858 || inst.operands[1].immisreg || inst.operands[1].shifted
4859 || inst.operands[1].negative
4860 /* This can arise if the programmer has written
4862 or if they have mistakenly used a register name as the last
4865 It is very difficult to distinguish between these two cases
4866 because "rX" might actually be a label. ie the register
4867 name has been occluded by a symbol of the same name. So we
4868 just generate a general 'bad addressing mode' type error
4869 message and leave it up to the programmer to discover the
4870 true cause and fix their mistake. */
4871 || (inst.operands[1].reg == REG_PC),
4874 constraint (inst.reloc.exp.X_op != O_constant
4875 || inst.reloc.exp.X_add_number != 0,
4876 _("offset must be zero in ARM encoding"));
4878 inst.instruction |= inst.operands[0].reg << 12;
4879 inst.instruction |= inst.operands[1].reg << 16;
4880 inst.reloc.type = BFD_RELOC_UNUSED;
4886 constraint (inst.operands[0].reg % 2 != 0,
4887 _("even register required"));
4888 constraint (inst.operands[1].present
4889 && inst.operands[1].reg != inst.operands[0].reg + 1,
4890 _("can only load two consecutive registers"));
4891 /* If op 1 were present and equal to PC, this function wouldn't
4892 have been called in the first place. */
4893 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4895 inst.instruction |= inst.operands[0].reg << 12;
4896 inst.instruction |= inst.operands[2].reg << 16;
4902 inst.instruction |= inst.operands[0].reg << 12;
4903 if (!inst.operands[1].isreg)
4904 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
4906 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
4912 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4914 if (inst.operands[1].preind)
4916 constraint (inst.reloc.exp.X_op != O_constant ||
4917 inst.reloc.exp.X_add_number != 0,
4918 _("this instruction requires a post-indexed address"));
4920 inst.operands[1].preind = 0;
4921 inst.operands[1].postind = 1;
4922 inst.operands[1].writeback = 1;
4924 inst.instruction |= inst.operands[0].reg << 12;
4925 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
4928 /* Halfword and signed-byte load/store operations. */
4933 inst.instruction |= inst.operands[0].reg << 12;
4934 if (!inst.operands[1].isreg)
4935 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
4937 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
4943 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4945 if (inst.operands[1].preind)
4947 constraint (inst.reloc.exp.X_op != O_constant ||
4948 inst.reloc.exp.X_add_number != 0,
4949 _("this instruction requires a post-indexed address"));
4951 inst.operands[1].preind = 0;
4952 inst.operands[1].postind = 1;
4953 inst.operands[1].writeback = 1;
4955 inst.instruction |= inst.operands[0].reg << 12;
4956 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
4959 /* Co-processor register load/store.
4960 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
4964 inst.instruction |= inst.operands[0].reg << 8;
4965 inst.instruction |= inst.operands[1].reg << 12;
4966 encode_arm_cp_address (2, TRUE, TRUE, 0);
4972 /* This restriction does not apply to mls (nor to mla in v6, but
4973 that's hard to detect at present). */
4974 if (inst.operands[0].reg == inst.operands[1].reg
4975 && !(inst.instruction & 0x00400000))
4976 as_tsktsk (_("rd and rm should be different in mla"));
4978 inst.instruction |= inst.operands[0].reg << 16;
4979 inst.instruction |= inst.operands[1].reg;
4980 inst.instruction |= inst.operands[2].reg << 8;
4981 inst.instruction |= inst.operands[3].reg << 12;
4988 inst.instruction |= inst.operands[0].reg << 12;
4989 encode_arm_shifter_operand (1);
4992 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
4996 inst.instruction |= inst.operands[0].reg << 12;
4997 /* The value is in two pieces: 0:11, 16:19. */
4998 inst.instruction |= (inst.operands[1].imm & 0x00000fff);
4999 inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
5005 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
5006 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
5008 _("'CPSR' or 'SPSR' expected"));
5009 inst.instruction |= inst.operands[0].reg << 12;
5010 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
5013 /* Two possible forms:
5014 "{C|S}PSR_<field>, Rm",
5015 "{C|S}PSR_f, #expression". */
5020 inst.instruction |= inst.operands[0].imm;
5021 if (inst.operands[1].isreg)
5022 inst.instruction |= inst.operands[1].reg;
5025 inst.instruction |= INST_IMMEDIATE;
5026 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5027 inst.reloc.pc_rel = 0;
5034 if (!inst.operands[2].present)
5035 inst.operands[2].reg = inst.operands[0].reg;
5036 inst.instruction |= inst.operands[0].reg << 16;
5037 inst.instruction |= inst.operands[1].reg;
5038 inst.instruction |= inst.operands[2].reg << 8;
5040 if (inst.operands[0].reg == inst.operands[1].reg)
5041 as_tsktsk (_("rd and rm should be different in mul"));
5044 /* Long Multiply Parser
5045 UMULL RdLo, RdHi, Rm, Rs
5046 SMULL RdLo, RdHi, Rm, Rs
5047 UMLAL RdLo, RdHi, Rm, Rs
5048 SMLAL RdLo, RdHi, Rm, Rs. */
5053 inst.instruction |= inst.operands[0].reg << 12;
5054 inst.instruction |= inst.operands[1].reg << 16;
5055 inst.instruction |= inst.operands[2].reg;
5056 inst.instruction |= inst.operands[3].reg << 8;
5058 /* rdhi, rdlo and rm must all be different. */
5059 if (inst.operands[0].reg == inst.operands[1].reg
5060 || inst.operands[0].reg == inst.operands[2].reg
5061 || inst.operands[1].reg == inst.operands[2].reg)
5062 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
5068 if (inst.operands[0].present)
5070 /* Architectural NOP hints are CPSR sets with no bits selected. */
5071 inst.instruction &= 0xf0000000;
5072 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
5076 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
5077 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
5078 Condition defaults to COND_ALWAYS.
5079 Error if Rd, Rn or Rm are R15. */
5084 inst.instruction |= inst.operands[0].reg << 12;
5085 inst.instruction |= inst.operands[1].reg << 16;
5086 inst.instruction |= inst.operands[2].reg;
5087 if (inst.operands[3].present)
5088 encode_arm_shift (3);
5091 /* ARM V6 PKHTB (Argument Parse). */
5096 if (!inst.operands[3].present)
5098 /* If the shift specifier is omitted, turn the instruction
5099 into pkhbt rd, rm, rn. */
5100 inst.instruction &= 0xfff00010;
5101 inst.instruction |= inst.operands[0].reg << 12;
5102 inst.instruction |= inst.operands[1].reg;
5103 inst.instruction |= inst.operands[2].reg << 16;
5107 inst.instruction |= inst.operands[0].reg << 12;
5108 inst.instruction |= inst.operands[1].reg << 16;
5109 inst.instruction |= inst.operands[2].reg;
5110 encode_arm_shift (3);
5114 /* ARMv5TE: Preload-Cache
5118 Syntactically, like LDR with B=1, W=0, L=1. */
5123 constraint (!inst.operands[0].isreg,
5124 _("'[' expected after PLD mnemonic"));
5125 constraint (inst.operands[0].postind,
5126 _("post-indexed expression used in preload instruction"));
5127 constraint (inst.operands[0].writeback,
5128 _("writeback used in preload instruction"));
5129 constraint (!inst.operands[0].preind,
5130 _("unindexed addressing used in preload instruction"));
5131 inst.instruction |= inst.operands[0].reg;
5132 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
5138 inst.operands[1] = inst.operands[0];
5139 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
5140 inst.operands[0].isreg = 1;
5141 inst.operands[0].writeback = 1;
5142 inst.operands[0].reg = REG_SP;
5146 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
5147 word at the specified address and the following word
5149 Unconditionally executed.
5150 Error if Rn is R15. */
5155 inst.instruction |= inst.operands[0].reg << 16;
5156 if (inst.operands[0].writeback)
5157 inst.instruction |= WRITE_BACK;
5160 /* ARM V6 ssat (argument parse). */
5165 inst.instruction |= inst.operands[0].reg << 12;
5166 inst.instruction |= (inst.operands[1].imm - 1) << 16;
5167 inst.instruction |= inst.operands[2].reg;
5169 if (inst.operands[3].present)
5170 encode_arm_shift (3);
5173 /* ARM V6 usat (argument parse). */
5178 inst.instruction |= inst.operands[0].reg << 12;
5179 inst.instruction |= inst.operands[1].imm << 16;
5180 inst.instruction |= inst.operands[2].reg;
5182 if (inst.operands[3].present)
5183 encode_arm_shift (3);
5186 /* ARM V6 ssat16 (argument parse). */
5191 inst.instruction |= inst.operands[0].reg << 12;
5192 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
5193 inst.instruction |= inst.operands[2].reg;
5199 inst.instruction |= inst.operands[0].reg << 12;
5200 inst.instruction |= inst.operands[1].imm << 16;
5201 inst.instruction |= inst.operands[2].reg;
5204 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5205 preserving the other bits.
5207 setend <endian_specifier>, where <endian_specifier> is either
5213 if (inst.operands[0].imm)
5214 inst.instruction |= 0x200;
5220 unsigned int Rm = (inst.operands[1].present
5221 ? inst.operands[1].reg
5222 : inst.operands[0].reg);
5224 inst.instruction |= inst.operands[0].reg << 12;
5225 inst.instruction |= Rm;
5226 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
5228 constraint (inst.operands[0].reg != Rm,
5229 _("source1 and dest must be same register"));
5230 inst.instruction |= inst.operands[2].reg << 8;
5231 inst.instruction |= SHIFT_BY_REG;
5234 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
5240 inst.reloc.type = BFD_RELOC_ARM_SMC;
5241 inst.reloc.pc_rel = 0;
5247 inst.reloc.type = BFD_RELOC_ARM_SWI;
5248 inst.reloc.pc_rel = 0;
5251 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5252 SMLAxy{cond} Rd,Rm,Rs,Rn
5253 SMLAWy{cond} Rd,Rm,Rs,Rn
5254 Error if any register is R15. */
5259 inst.instruction |= inst.operands[0].reg << 16;
5260 inst.instruction |= inst.operands[1].reg;
5261 inst.instruction |= inst.operands[2].reg << 8;
5262 inst.instruction |= inst.operands[3].reg << 12;
5265 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5266 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5267 Error if any register is R15.
5268 Warning if Rdlo == Rdhi. */
5273 inst.instruction |= inst.operands[0].reg << 12;
5274 inst.instruction |= inst.operands[1].reg << 16;
5275 inst.instruction |= inst.operands[2].reg;
5276 inst.instruction |= inst.operands[3].reg << 8;
5278 if (inst.operands[0].reg == inst.operands[1].reg)
5279 as_tsktsk (_("rdhi and rdlo must be different"));
5282 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5283 SMULxy{cond} Rd,Rm,Rs
5284 Error if any register is R15. */
5289 inst.instruction |= inst.operands[0].reg << 16;
5290 inst.instruction |= inst.operands[1].reg;
5291 inst.instruction |= inst.operands[2].reg << 8;
5294 /* ARM V6 srs (argument parse). */
5299 inst.instruction |= inst.operands[0].imm;
5300 if (inst.operands[0].writeback)
5301 inst.instruction |= WRITE_BACK;
5304 /* ARM V6 strex (argument parse). */
5309 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
5310 || inst.operands[2].postind || inst.operands[2].writeback
5311 || inst.operands[2].immisreg || inst.operands[2].shifted
5312 || inst.operands[2].negative
5313 /* See comment in do_ldrex(). */
5314 || (inst.operands[2].reg == REG_PC),
5317 constraint (inst.operands[0].reg == inst.operands[1].reg
5318 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
5320 constraint (inst.reloc.exp.X_op != O_constant
5321 || inst.reloc.exp.X_add_number != 0,
5322 _("offset must be zero in ARM encoding"));
5324 inst.instruction |= inst.operands[0].reg << 12;
5325 inst.instruction |= inst.operands[1].reg;
5326 inst.instruction |= inst.operands[2].reg << 16;
5327 inst.reloc.type = BFD_RELOC_UNUSED;
5333 constraint (inst.operands[1].reg % 2 != 0,
5334 _("even register required"));
5335 constraint (inst.operands[2].present
5336 && inst.operands[2].reg != inst.operands[1].reg + 1,
5337 _("can only store two consecutive registers"));
5338 /* If op 2 were present and equal to PC, this function wouldn't
5339 have been called in the first place. */
5340 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
5342 constraint (inst.operands[0].reg == inst.operands[1].reg
5343 || inst.operands[0].reg == inst.operands[1].reg + 1
5344 || inst.operands[0].reg == inst.operands[3].reg,
5347 inst.instruction |= inst.operands[0].reg << 12;
5348 inst.instruction |= inst.operands[1].reg;
5349 inst.instruction |= inst.operands[3].reg << 16;
5352 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5353 extends it to 32-bits, and adds the result to a value in another
5354 register. You can specify a rotation by 0, 8, 16, or 24 bits
5355 before extracting the 16-bit value.
5356 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5357 Condition defaults to COND_ALWAYS.
5358 Error if any register uses R15. */
5363 inst.instruction |= inst.operands[0].reg << 12;
5364 inst.instruction |= inst.operands[1].reg << 16;
5365 inst.instruction |= inst.operands[2].reg;
5366 inst.instruction |= inst.operands[3].imm << 10;
5371 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5372 Condition defaults to COND_ALWAYS.
5373 Error if any register uses R15. */
5378 inst.instruction |= inst.operands[0].reg << 12;
5379 inst.instruction |= inst.operands[1].reg;
5380 inst.instruction |= inst.operands[2].imm << 10;
5383 /* VFP instructions. In a logical order: SP variant first, monad
5384 before dyad, arithmetic then move then load/store. */
5387 do_vfp_sp_monadic (void)
5389 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5390 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5394 do_vfp_sp_dyadic (void)
5396 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5397 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5398 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5402 do_vfp_sp_compare_z (void)
5404 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5408 do_vfp_dp_sp_cvt (void)
5410 inst.instruction |= inst.operands[0].reg << 12;
5411 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5415 do_vfp_sp_dp_cvt (void)
5417 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5418 inst.instruction |= inst.operands[1].reg;
5422 do_vfp_reg_from_sp (void)
5424 inst.instruction |= inst.operands[0].reg << 12;
5425 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5429 do_vfp_reg2_from_sp2 (void)
5431 constraint (inst.operands[2].imm != 2,
5432 _("only two consecutive VFP SP registers allowed here"));
5433 inst.instruction |= inst.operands[0].reg << 12;
5434 inst.instruction |= inst.operands[1].reg << 16;
5435 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5439 do_vfp_sp_from_reg (void)
5441 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
5442 inst.instruction |= inst.operands[1].reg << 12;
5446 do_vfp_sp2_from_reg2 (void)
5448 constraint (inst.operands[0].imm != 2,
5449 _("only two consecutive VFP SP registers allowed here"));
5450 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
5451 inst.instruction |= inst.operands[1].reg << 12;
5452 inst.instruction |= inst.operands[2].reg << 16;
5456 do_vfp_sp_ldst (void)
5458 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5459 encode_arm_cp_address (1, FALSE, TRUE, 0);
5463 do_vfp_dp_ldst (void)
5465 inst.instruction |= inst.operands[0].reg << 12;
5466 encode_arm_cp_address (1, FALSE, TRUE, 0);
5471 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
5473 if (inst.operands[0].writeback)
5474 inst.instruction |= WRITE_BACK;
5476 constraint (ldstm_type != VFP_LDSTMIA,
5477 _("this addressing mode requires base-register writeback"));
5478 inst.instruction |= inst.operands[0].reg << 16;
5479 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
5480 inst.instruction |= inst.operands[1].imm;
5484 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
5488 if (inst.operands[0].writeback)
5489 inst.instruction |= WRITE_BACK;
5491 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
5492 _("this addressing mode requires base-register writeback"));
5494 inst.instruction |= inst.operands[0].reg << 16;
5495 inst.instruction |= inst.operands[1].reg << 12;
5497 count = inst.operands[1].imm << 1;
5498 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
5501 inst.instruction |= count;
5505 do_vfp_sp_ldstmia (void)
5507 vfp_sp_ldstm (VFP_LDSTMIA);
5511 do_vfp_sp_ldstmdb (void)
5513 vfp_sp_ldstm (VFP_LDSTMDB);
5517 do_vfp_dp_ldstmia (void)
5519 vfp_dp_ldstm (VFP_LDSTMIA);
5523 do_vfp_dp_ldstmdb (void)
5525 vfp_dp_ldstm (VFP_LDSTMDB);
5529 do_vfp_xp_ldstmia (void)
5531 vfp_dp_ldstm (VFP_LDSTMIAX);
5535 do_vfp_xp_ldstmdb (void)
5537 vfp_dp_ldstm (VFP_LDSTMDBX);
5540 /* FPA instructions. Also in a logical order. */
5545 inst.instruction |= inst.operands[0].reg << 16;
5546 inst.instruction |= inst.operands[1].reg;
5550 do_fpa_ldmstm (void)
5552 inst.instruction |= inst.operands[0].reg << 12;
5553 switch (inst.operands[1].imm)
5555 case 1: inst.instruction |= CP_T_X; break;
5556 case 2: inst.instruction |= CP_T_Y; break;
5557 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
5562 if (inst.instruction & (PRE_INDEX | INDEX_UP))
5564 /* The instruction specified "ea" or "fd", so we can only accept
5565 [Rn]{!}. The instruction does not really support stacking or
5566 unstacking, so we have to emulate these by setting appropriate
5567 bits and offsets. */
5568 constraint (inst.reloc.exp.X_op != O_constant
5569 || inst.reloc.exp.X_add_number != 0,
5570 _("this instruction does not support indexing"));
5572 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
5573 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
5575 if (!(inst.instruction & INDEX_UP))
5576 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
5578 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
5580 inst.operands[2].preind = 0;
5581 inst.operands[2].postind = 1;
5585 encode_arm_cp_address (2, TRUE, TRUE, 0);
5588 /* iWMMXt instructions: strictly in alphabetical order. */
5591 do_iwmmxt_tandorc (void)
5593 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
5597 do_iwmmxt_textrc (void)
5599 inst.instruction |= inst.operands[0].reg << 12;
5600 inst.instruction |= inst.operands[1].imm;
5604 do_iwmmxt_textrm (void)
5606 inst.instruction |= inst.operands[0].reg << 12;
5607 inst.instruction |= inst.operands[1].reg << 16;
5608 inst.instruction |= inst.operands[2].imm;
5612 do_iwmmxt_tinsr (void)
5614 inst.instruction |= inst.operands[0].reg << 16;
5615 inst.instruction |= inst.operands[1].reg << 12;
5616 inst.instruction |= inst.operands[2].imm;
5620 do_iwmmxt_tmia (void)
5622 inst.instruction |= inst.operands[0].reg << 5;
5623 inst.instruction |= inst.operands[1].reg;
5624 inst.instruction |= inst.operands[2].reg << 12;
5628 do_iwmmxt_waligni (void)
5630 inst.instruction |= inst.operands[0].reg << 12;
5631 inst.instruction |= inst.operands[1].reg << 16;
5632 inst.instruction |= inst.operands[2].reg;
5633 inst.instruction |= inst.operands[3].imm << 20;
5637 do_iwmmxt_wmov (void)
5639 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5640 inst.instruction |= inst.operands[0].reg << 12;
5641 inst.instruction |= inst.operands[1].reg << 16;
5642 inst.instruction |= inst.operands[1].reg;
5646 do_iwmmxt_wldstbh (void)
5649 inst.instruction |= inst.operands[0].reg << 12;
5650 inst.reloc.exp.X_add_number *= 4;
5652 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
5654 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
5655 encode_arm_cp_address (1, TRUE, FALSE, reloc);
5659 do_iwmmxt_wldstw (void)
5661 /* RIWR_RIWC clears .isreg for a control register. */
5662 if (!inst.operands[0].isreg)
5664 constraint (inst.cond != COND_ALWAYS, BAD_COND);
5665 inst.instruction |= 0xf0000000;
5668 inst.instruction |= inst.operands[0].reg << 12;
5669 encode_arm_cp_address (1, TRUE, TRUE, 0);
5673 do_iwmmxt_wldstd (void)
5675 inst.instruction |= inst.operands[0].reg << 12;
5676 encode_arm_cp_address (1, TRUE, FALSE, 0);
5680 do_iwmmxt_wshufh (void)
5682 inst.instruction |= inst.operands[0].reg << 12;
5683 inst.instruction |= inst.operands[1].reg << 16;
5684 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
5685 inst.instruction |= (inst.operands[2].imm & 0x0f);
5689 do_iwmmxt_wzero (void)
5691 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5692 inst.instruction |= inst.operands[0].reg;
5693 inst.instruction |= inst.operands[0].reg << 12;
5694 inst.instruction |= inst.operands[0].reg << 16;
5697 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5698 operations first, then control, shift, and load/store. */
5700 /* Insns like "foo X,Y,Z". */
5703 do_mav_triple (void)
5705 inst.instruction |= inst.operands[0].reg << 16;
5706 inst.instruction |= inst.operands[1].reg;
5707 inst.instruction |= inst.operands[2].reg << 12;
5710 /* Insns like "foo W,X,Y,Z".
5711 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5716 inst.instruction |= inst.operands[0].reg << 5;
5717 inst.instruction |= inst.operands[1].reg << 12;
5718 inst.instruction |= inst.operands[2].reg << 16;
5719 inst.instruction |= inst.operands[3].reg;
5722 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5726 inst.instruction |= inst.operands[1].reg << 12;
5729 /* Maverick shift immediate instructions.
5730 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5731 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5736 int imm = inst.operands[2].imm;
5738 inst.instruction |= inst.operands[0].reg << 12;
5739 inst.instruction |= inst.operands[1].reg << 16;
5741 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5742 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5743 Bit 4 should be 0. */
5744 imm = (imm & 0xf) | ((imm & 0x70) << 1);
5746 inst.instruction |= imm;
5749 /* XScale instructions. Also sorted arithmetic before move. */
5751 /* Xscale multiply-accumulate (argument parse)
5754 MIAxycc acc0,Rm,Rs. */
5759 inst.instruction |= inst.operands[1].reg;
5760 inst.instruction |= inst.operands[2].reg << 12;
5763 /* Xscale move-accumulator-register (argument parse)
5765 MARcc acc0,RdLo,RdHi. */
5770 inst.instruction |= inst.operands[1].reg << 12;
5771 inst.instruction |= inst.operands[2].reg << 16;
5774 /* Xscale move-register-accumulator (argument parse)
5776 MRAcc RdLo,RdHi,acc0. */
5781 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
5782 inst.instruction |= inst.operands[0].reg << 12;
5783 inst.instruction |= inst.operands[1].reg << 16;
5786 /* Encoding functions relevant only to Thumb. */
5788 /* inst.operands[i] is a shifted-register operand; encode
5789 it into inst.instruction in the format used by Thumb32. */
5792 encode_thumb32_shifted_operand (int i)
5794 unsigned int value = inst.reloc.exp.X_add_number;
5795 unsigned int shift = inst.operands[i].shift_kind;
5797 constraint (inst.operands[i].immisreg,
5798 _("shift by register not allowed in thumb mode"));
5799 inst.instruction |= inst.operands[i].reg;
5800 if (shift == SHIFT_RRX)
5801 inst.instruction |= SHIFT_ROR << 4;
5804 constraint (inst.reloc.exp.X_op != O_constant,
5805 _("expression too complex"));
5807 constraint (value > 32
5808 || (value == 32 && (shift == SHIFT_LSL
5809 || shift == SHIFT_ROR)),
5810 _("shift expression is too large"));
5814 else if (value == 32)
5817 inst.instruction |= shift << 4;
5818 inst.instruction |= (value & 0x1c) << 10;
5819 inst.instruction |= (value & 0x03) << 6;
5824 /* inst.operands[i] was set up by parse_address. Encode it into a
5825 Thumb32 format load or store instruction. Reject forms that cannot
5826 be used with such instructions. If is_t is true, reject forms that
5827 cannot be used with a T instruction; if is_d is true, reject forms
5828 that cannot be used with a D instruction. */
5831 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
5833 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
5835 constraint (!inst.operands[i].isreg,
5836 _("Thumb does not support the ldr =N pseudo-operation"));
5838 inst.instruction |= inst.operands[i].reg << 16;
5839 if (inst.operands[i].immisreg)
5841 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
5842 constraint (is_t || is_d, _("cannot use register index with this instruction"));
5843 constraint (inst.operands[i].negative,
5844 _("Thumb does not support negative register indexing"));
5845 constraint (inst.operands[i].postind,
5846 _("Thumb does not support register post-indexing"));
5847 constraint (inst.operands[i].writeback,
5848 _("Thumb does not support register indexing with writeback"));
5849 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
5850 _("Thumb supports only LSL in shifted register indexing"));
5852 inst.instruction |= inst.operands[1].imm;
5853 if (inst.operands[i].shifted)
5855 constraint (inst.reloc.exp.X_op != O_constant,
5856 _("expression too complex"));
5857 constraint (inst.reloc.exp.X_add_number < 0
5858 || inst.reloc.exp.X_add_number > 3,
5859 _("shift out of range"));
5860 inst.instruction |= inst.reloc.exp.X_add_number << 4;
5862 inst.reloc.type = BFD_RELOC_UNUSED;
5864 else if (inst.operands[i].preind)
5866 constraint (is_pc && inst.operands[i].writeback,
5867 _("cannot use writeback with PC-relative addressing"));
5868 constraint (is_t && inst.operands[1].writeback,
5869 _("cannot use writeback with this instruction"));
5873 inst.instruction |= 0x01000000;
5874 if (inst.operands[i].writeback)
5875 inst.instruction |= 0x00200000;
5879 inst.instruction |= 0x00000c00;
5880 if (inst.operands[i].writeback)
5881 inst.instruction |= 0x00000100;
5883 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5885 else if (inst.operands[i].postind)
5887 assert (inst.operands[i].writeback);
5888 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
5889 constraint (is_t, _("cannot use post-indexing with this instruction"));
5892 inst.instruction |= 0x00200000;
5894 inst.instruction |= 0x00000900;
5895 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5897 else /* unindexed - only for coprocessor */
5898 inst.error = _("instruction does not accept unindexed addressing");
5901 /* Table of Thumb instructions which exist in both 16- and 32-bit
5902 encodings (the latter only in post-V6T2 cores). The index is the
5903 value used in the insns table below. When there is more than one
5904 possible 16-bit encoding for the instruction, this table always
5906 Also contains several pseudo-instructions used during relaxation. */
5907 #define T16_32_TAB \
5908 X(adc, 4140, eb400000), \
5909 X(adcs, 4140, eb500000), \
5910 X(add, 1c00, eb000000), \
5911 X(adds, 1c00, eb100000), \
5912 X(addi, 0000, f1000000), \
5913 X(addis, 0000, f1100000), \
5914 X(add_pc,000f, f20f0000), \
5915 X(add_sp,000d, f10d0000), \
5916 X(adr, 000f, f20f0000), \
5917 X(and, 4000, ea000000), \
5918 X(ands, 4000, ea100000), \
5919 X(asr, 1000, fa40f000), \
5920 X(asrs, 1000, fa50f000), \
5921 X(b, e000, f000b000), \
5922 X(bcond, d000, f0008000), \
5923 X(bic, 4380, ea200000), \
5924 X(bics, 4380, ea300000), \
5925 X(cmn, 42c0, eb100f00), \
5926 X(cmp, 2800, ebb00f00), \
5927 X(cpsie, b660, f3af8400), \
5928 X(cpsid, b670, f3af8600), \
5929 X(cpy, 4600, ea4f0000), \
5930 X(dec_sp,80dd, f1bd0d00), \
5931 X(eor, 4040, ea800000), \
5932 X(eors, 4040, ea900000), \
5933 X(inc_sp,00dd, f10d0d00), \
5934 X(ldmia, c800, e8900000), \
5935 X(ldr, 6800, f8500000), \
5936 X(ldrb, 7800, f8100000), \
5937 X(ldrh, 8800, f8300000), \
5938 X(ldrsb, 5600, f9100000), \
5939 X(ldrsh, 5e00, f9300000), \
5940 X(ldr_pc,4800, f85f0000), \
5941 X(ldr_pc2,4800, f85f0000), \
5942 X(ldr_sp,9800, f85d0000), \
5943 X(lsl, 0000, fa00f000), \
5944 X(lsls, 0000, fa10f000), \
5945 X(lsr, 0800, fa20f000), \
5946 X(lsrs, 0800, fa30f000), \
5947 X(mov, 2000, ea4f0000), \
5948 X(movs, 2000, ea5f0000), \
5949 X(mul, 4340, fb00f000), \
5950 X(muls, 4340, ffffffff), /* no 32b muls */ \
5951 X(mvn, 43c0, ea6f0000), \
5952 X(mvns, 43c0, ea7f0000), \
5953 X(neg, 4240, f1c00000), /* rsb #0 */ \
5954 X(negs, 4240, f1d00000), /* rsbs #0 */ \
5955 X(orr, 4300, ea400000), \
5956 X(orrs, 4300, ea500000), \
5957 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
5958 X(push, b400, e92d0000), /* stmdb sp!,... */ \
5959 X(rev, ba00, fa90f080), \
5960 X(rev16, ba40, fa90f090), \
5961 X(revsh, bac0, fa90f0b0), \
5962 X(ror, 41c0, fa60f000), \
5963 X(rors, 41c0, fa70f000), \
5964 X(sbc, 4180, eb600000), \
5965 X(sbcs, 4180, eb700000), \
5966 X(stmia, c000, e8800000), \
5967 X(str, 6000, f8400000), \
5968 X(strb, 7000, f8000000), \
5969 X(strh, 8000, f8200000), \
5970 X(str_sp,9000, f84d0000), \
5971 X(sub, 1e00, eba00000), \
5972 X(subs, 1e00, ebb00000), \
5973 X(subi, 8000, f1a00000), \
5974 X(subis, 8000, f1b00000), \
5975 X(sxtb, b240, fa4ff080), \
5976 X(sxth, b200, fa0ff080), \
5977 X(tst, 4200, ea100f00), \
5978 X(uxtb, b2c0, fa5ff080), \
5979 X(uxth, b280, fa1ff080), \
5980 X(nop, bf00, f3af8000), \
5981 X(yield, bf10, f3af8001), \
5982 X(wfe, bf20, f3af8002), \
5983 X(wfi, bf30, f3af8003), \
5984 X(sev, bf40, f3af9004), /* typo, 8004? */
5986 /* To catch errors in encoding functions, the codes are all offset by
5987 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
5988 as 16-bit instructions. */
5989 #define X(a,b,c) T_MNEM_##a
5990 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
5993 #define X(a,b,c) 0x##b
5994 static const unsigned short thumb_op16[] = { T16_32_TAB };
5995 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
5998 #define X(a,b,c) 0x##c
5999 static const unsigned int thumb_op32[] = { T16_32_TAB };
6000 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
6001 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
6005 /* Thumb instruction encoders, in alphabetical order. */
6009 do_t_add_sub_w (void)
6013 Rd = inst.operands[0].reg;
6014 Rn = inst.operands[1].reg;
6016 constraint (Rd == 15, _("PC not allowed as destination"));
6017 inst.instruction |= (Rn << 16) | (Rd << 8);
6018 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
6021 /* Parse an add or subtract instruction. We get here with inst.instruction
6022 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
6029 Rd = inst.operands[0].reg;
6030 Rs = (inst.operands[1].present
6031 ? inst.operands[1].reg /* Rd, Rs, foo */
6032 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6040 flags = (inst.instruction == T_MNEM_adds
6041 || inst.instruction == T_MNEM_subs);
6043 narrow = (current_it_mask == 0);
6045 narrow = (current_it_mask != 0);
6046 if (!inst.operands[2].isreg)
6049 if (inst.size_req != 4)
6053 add = (inst.instruction == T_MNEM_add
6054 || inst.instruction == T_MNEM_adds);
6055 /* Attempt to use a narrow opcode, with relaxation if
6057 if (Rd == REG_SP && Rs == REG_SP && !flags)
6058 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
6059 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
6060 opcode = T_MNEM_add_sp;
6061 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
6062 opcode = T_MNEM_add_pc;
6063 else if (Rd <= 7 && Rs <= 7 && narrow)
6066 opcode = add ? T_MNEM_addis : T_MNEM_subis;
6068 opcode = add ? T_MNEM_addi : T_MNEM_subi;
6072 inst.instruction = THUMB_OP16(opcode);
6073 inst.instruction |= (Rd << 4) | Rs;
6074 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6075 if (inst.size_req != 2)
6076 inst.relax = opcode;
6079 constraint (inst.size_req == 2, BAD_HIREG);
6081 if (inst.size_req == 4
6082 || (inst.size_req != 2 && !opcode))
6084 /* ??? Convert large immediates to addw/subw. */
6085 inst.instruction = THUMB_OP32 (inst.instruction);
6086 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6087 inst.instruction |= inst.operands[0].reg << 8;
6088 inst.instruction |= inst.operands[1].reg << 16;
6089 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6094 Rn = inst.operands[2].reg;
6095 /* See if we can do this with a 16-bit instruction. */
6096 if (!inst.operands[2].shifted && inst.size_req != 4)
6098 if (Rd > 7 || Rs > 7 || Rn > 7)
6103 inst.instruction = ((inst.instruction == T_MNEM_adds
6104 || inst.instruction == T_MNEM_add)
6107 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
6111 if (inst.instruction == T_MNEM_add)
6115 inst.instruction = T_OPCODE_ADD_HI;
6116 inst.instruction |= (Rd & 8) << 4;
6117 inst.instruction |= (Rd & 7);
6118 inst.instruction |= Rn << 3;
6121 /* ... because addition is commutative! */
6124 inst.instruction = T_OPCODE_ADD_HI;
6125 inst.instruction |= (Rd & 8) << 4;
6126 inst.instruction |= (Rd & 7);
6127 inst.instruction |= Rs << 3;
6132 /* If we get here, it can't be done in 16 bits. */
6133 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
6134 _("shift must be constant"));
6135 inst.instruction = THUMB_OP32 (inst.instruction);
6136 inst.instruction |= Rd << 8;
6137 inst.instruction |= Rs << 16;
6138 encode_thumb32_shifted_operand (2);
6143 constraint (inst.instruction == T_MNEM_adds
6144 || inst.instruction == T_MNEM_subs,
6147 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
6149 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
6150 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
6153 inst.instruction = (inst.instruction == T_MNEM_add
6155 inst.instruction |= (Rd << 4) | Rs;
6156 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6160 Rn = inst.operands[2].reg;
6161 constraint (inst.operands[2].shifted, _("unshifted register required"));
6163 /* We now have Rd, Rs, and Rn set to registers. */
6164 if (Rd > 7 || Rs > 7 || Rn > 7)
6166 /* Can't do this for SUB. */
6167 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
6168 inst.instruction = T_OPCODE_ADD_HI;
6169 inst.instruction |= (Rd & 8) << 4;
6170 inst.instruction |= (Rd & 7);
6172 inst.instruction |= Rn << 3;
6174 inst.instruction |= Rs << 3;
6176 constraint (1, _("dest must overlap one source register"));
6180 inst.instruction = (inst.instruction == T_MNEM_add
6181 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
6182 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
6190 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
6192 /* Defer to section relaxation. */
6193 inst.relax = inst.instruction;
6194 inst.instruction = THUMB_OP16 (inst.instruction);
6195 inst.instruction |= inst.operands[0].reg << 4;
6197 else if (unified_syntax && inst.size_req != 2)
6199 /* Generate a 32-bit opcode. */
6200 inst.instruction = THUMB_OP32 (inst.instruction);
6201 inst.instruction |= inst.operands[0].reg << 8;
6202 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
6203 inst.reloc.pc_rel = 1;
6207 /* Generate a 16-bit opcode. */
6208 inst.instruction = THUMB_OP16 (inst.instruction);
6209 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6210 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
6211 inst.reloc.pc_rel = 1;
6213 inst.instruction |= inst.operands[0].reg << 4;
6217 /* Arithmetic instructions for which there is just one 16-bit
6218 instruction encoding, and it allows only two low registers.
6219 For maximal compatibility with ARM syntax, we allow three register
6220 operands even when Thumb-32 instructions are not available, as long
6221 as the first two are identical. For instance, both "sbc r0,r1" and
6222 "sbc r0,r0,r1" are allowed. */
6228 Rd = inst.operands[0].reg;
6229 Rs = (inst.operands[1].present
6230 ? inst.operands[1].reg /* Rd, Rs, foo */
6231 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6232 Rn = inst.operands[2].reg;
6236 if (!inst.operands[2].isreg)
6238 /* For an immediate, we always generate a 32-bit opcode;
6239 section relaxation will shrink it later if possible. */
6240 inst.instruction = THUMB_OP32 (inst.instruction);
6241 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6242 inst.instruction |= Rd << 8;
6243 inst.instruction |= Rs << 16;
6244 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6250 /* See if we can do this with a 16-bit instruction. */
6251 if (THUMB_SETS_FLAGS (inst.instruction))
6252 narrow = current_it_mask == 0;
6254 narrow = current_it_mask != 0;
6256 if (Rd > 7 || Rn > 7 || Rs > 7)
6258 if (inst.operands[2].shifted)
6260 if (inst.size_req == 4)
6266 inst.instruction = THUMB_OP16 (inst.instruction);
6267 inst.instruction |= Rd;
6268 inst.instruction |= Rn << 3;
6272 /* If we get here, it can't be done in 16 bits. */
6273 constraint (inst.operands[2].shifted
6274 && inst.operands[2].immisreg,
6275 _("shift must be constant"));
6276 inst.instruction = THUMB_OP32 (inst.instruction);
6277 inst.instruction |= Rd << 8;
6278 inst.instruction |= Rs << 16;
6279 encode_thumb32_shifted_operand (2);
6284 /* On its face this is a lie - the instruction does set the
6285 flags. However, the only supported mnemonic in this mode
6287 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6289 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6290 _("unshifted register required"));
6291 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6292 constraint (Rd != Rs,
6293 _("dest and source1 must be the same register"));
6295 inst.instruction = THUMB_OP16 (inst.instruction);
6296 inst.instruction |= Rd;
6297 inst.instruction |= Rn << 3;
6301 /* Similarly, but for instructions where the arithmetic operation is
6302 commutative, so we can allow either of them to be different from
6303 the destination operand in a 16-bit instruction. For instance, all
6304 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6311 Rd = inst.operands[0].reg;
6312 Rs = (inst.operands[1].present
6313 ? inst.operands[1].reg /* Rd, Rs, foo */
6314 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6315 Rn = inst.operands[2].reg;
6319 if (!inst.operands[2].isreg)
6321 /* For an immediate, we always generate a 32-bit opcode;
6322 section relaxation will shrink it later if possible. */
6323 inst.instruction = THUMB_OP32 (inst.instruction);
6324 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6325 inst.instruction |= Rd << 8;
6326 inst.instruction |= Rs << 16;
6327 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6333 /* See if we can do this with a 16-bit instruction. */
6334 if (THUMB_SETS_FLAGS (inst.instruction))
6335 narrow = current_it_mask == 0;
6337 narrow = current_it_mask != 0;
6339 if (Rd > 7 || Rn > 7 || Rs > 7)
6341 if (inst.operands[2].shifted)
6343 if (inst.size_req == 4)
6350 inst.instruction = THUMB_OP16 (inst.instruction);
6351 inst.instruction |= Rd;
6352 inst.instruction |= Rn << 3;
6357 inst.instruction = THUMB_OP16 (inst.instruction);
6358 inst.instruction |= Rd;
6359 inst.instruction |= Rs << 3;
6364 /* If we get here, it can't be done in 16 bits. */
6365 constraint (inst.operands[2].shifted
6366 && inst.operands[2].immisreg,
6367 _("shift must be constant"));
6368 inst.instruction = THUMB_OP32 (inst.instruction);
6369 inst.instruction |= Rd << 8;
6370 inst.instruction |= Rs << 16;
6371 encode_thumb32_shifted_operand (2);
6376 /* On its face this is a lie - the instruction does set the
6377 flags. However, the only supported mnemonic in this mode
6379 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6381 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6382 _("unshifted register required"));
6383 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6385 inst.instruction = THUMB_OP16 (inst.instruction);
6386 inst.instruction |= Rd;
6389 inst.instruction |= Rn << 3;
6391 inst.instruction |= Rs << 3;
6393 constraint (1, _("dest must overlap one source register"));
6400 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6401 constraint (msb > 32, _("bit-field extends past end of register"));
6402 /* The instruction encoding stores the LSB and MSB,
6403 not the LSB and width. */
6404 inst.instruction |= inst.operands[0].reg << 8;
6405 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
6406 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
6407 inst.instruction |= msb - 1;
6415 /* #0 in second position is alternative syntax for bfc, which is
6416 the same instruction but with REG_PC in the Rm field. */
6417 if (!inst.operands[1].isreg)
6418 inst.operands[1].reg = REG_PC;
6420 msb = inst.operands[2].imm + inst.operands[3].imm;
6421 constraint (msb > 32, _("bit-field extends past end of register"));
6422 /* The instruction encoding stores the LSB and MSB,
6423 not the LSB and width. */
6424 inst.instruction |= inst.operands[0].reg << 8;
6425 inst.instruction |= inst.operands[1].reg << 16;
6426 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6427 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6428 inst.instruction |= msb - 1;
6434 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6435 _("bit-field extends past end of register"));
6436 inst.instruction |= inst.operands[0].reg << 8;
6437 inst.instruction |= inst.operands[1].reg << 16;
6438 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6439 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6440 inst.instruction |= inst.operands[3].imm - 1;
6443 /* ARM V5 Thumb BLX (argument parse)
6444 BLX <target_addr> which is BLX(1)
6445 BLX <Rm> which is BLX(2)
6446 Unfortunately, there are two different opcodes for this mnemonic.
6447 So, the insns[].value is not used, and the code here zaps values
6448 into inst.instruction.
6450 ??? How to take advantage of the additional two bits of displacement
6451 available in Thumb32 mode? Need new relocation? */
6456 if (inst.operands[0].isreg)
6457 /* We have a register, so this is BLX(2). */
6458 inst.instruction |= inst.operands[0].reg << 3;
6461 /* No register. This must be BLX(1). */
6462 inst.instruction = 0xf000e800;
6464 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6465 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6468 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
6469 inst.reloc.pc_rel = 1;
6477 if (inst.cond != COND_ALWAYS)
6478 opcode = T_MNEM_bcond;
6480 opcode = inst.instruction;
6482 if (unified_syntax && inst.size_req == 4)
6484 inst.instruction = THUMB_OP32(opcode);
6485 if (inst.cond == COND_ALWAYS)
6486 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
6489 assert (inst.cond != 0xF);
6490 inst.instruction |= inst.cond << 22;
6491 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
6496 inst.instruction = THUMB_OP16(opcode);
6497 if (inst.cond == COND_ALWAYS)
6498 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6501 inst.instruction |= inst.cond << 8;
6502 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6504 /* Allow section relaxation. */
6505 if (unified_syntax && inst.size_req != 2)
6506 inst.relax = opcode;
6509 inst.reloc.pc_rel = 1;
6515 if (inst.operands[0].present)
6517 constraint (inst.operands[0].imm > 255,
6518 _("immediate value out of range"));
6519 inst.instruction |= inst.operands[0].imm;
6524 do_t_branch23 (void)
6526 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6527 inst.reloc.pc_rel = 1;
6529 /* If the destination of the branch is a defined symbol which does not have
6530 the THUMB_FUNC attribute, then we must be calling a function which has
6531 the (interfacearm) attribute. We look for the Thumb entry point to that
6532 function and change the branch to refer to that function instead. */
6533 if ( inst.reloc.exp.X_op == O_symbol
6534 && inst.reloc.exp.X_add_symbol != NULL
6535 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6536 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6537 inst.reloc.exp.X_add_symbol =
6538 find_real_start (inst.reloc.exp.X_add_symbol);
6544 inst.instruction |= inst.operands[0].reg << 3;
6545 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6546 should cause the alignment to be checked once it is known. This is
6547 because BX PC only works if the instruction is word aligned. */
6553 if (inst.operands[0].reg == REG_PC)
6554 as_tsktsk (_("use of r15 in bxj is not really useful"));
6556 inst.instruction |= inst.operands[0].reg << 16;
6562 inst.instruction |= inst.operands[0].reg << 8;
6563 inst.instruction |= inst.operands[1].reg << 16;
6564 inst.instruction |= inst.operands[1].reg;
6571 && (inst.operands[1].present || inst.size_req == 4))
6573 unsigned int imod = (inst.instruction & 0x0030) >> 4;
6574 inst.instruction = 0xf3af8000;
6575 inst.instruction |= imod << 9;
6576 inst.instruction |= inst.operands[0].imm << 5;
6577 if (inst.operands[1].present)
6578 inst.instruction |= 0x100 | inst.operands[1].imm;
6582 constraint (inst.operands[1].present,
6583 _("Thumb does not support the 2-argument "
6584 "form of this instruction"));
6585 inst.instruction |= inst.operands[0].imm;
6589 /* THUMB CPY instruction (argument parse). */
6594 if (inst.size_req == 4)
6596 inst.instruction = THUMB_OP32 (T_MNEM_mov);
6597 inst.instruction |= inst.operands[0].reg << 8;
6598 inst.instruction |= inst.operands[1].reg;
6602 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6603 inst.instruction |= (inst.operands[0].reg & 0x7);
6604 inst.instruction |= inst.operands[1].reg << 3;
6611 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6612 inst.instruction |= inst.operands[0].reg;
6613 inst.reloc.pc_rel = 1;
6614 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
6620 if (unified_syntax && inst.size_req == 4)
6621 inst.instruction = THUMB_OP32 (inst.instruction);
6623 inst.instruction = THUMB_OP16 (inst.instruction);
6629 unsigned int cond = inst.operands[0].imm;
6631 current_it_mask = (inst.instruction & 0xf) | 0x10;
6634 /* If the condition is a negative condition, invert the mask. */
6635 if ((cond & 0x1) == 0x0)
6637 unsigned int mask = inst.instruction & 0x000f;
6639 if ((mask & 0x7) == 0)
6640 /* no conversion needed */;
6641 else if ((mask & 0x3) == 0)
6643 else if ((mask & 0x1) == 0)
6648 inst.instruction &= 0xfff0;
6649 inst.instruction |= mask;
6652 inst.instruction |= cond << 4;
6658 /* This really doesn't seem worth it. */
6659 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6660 _("expression too complex"));
6661 constraint (inst.operands[1].writeback,
6662 _("Thumb load/store multiple does not support {reglist}^"));
6666 /* See if we can use a 16-bit instruction. */
6667 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
6668 && inst.size_req != 4
6669 && inst.operands[0].reg <= 7
6670 && !(inst.operands[1].imm & ~0xff)
6671 && (inst.instruction == T_MNEM_stmia
6672 ? inst.operands[0].writeback
6673 : (inst.operands[0].writeback
6674 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
6676 if (inst.instruction == T_MNEM_stmia
6677 && (inst.operands[1].imm & (1 << inst.operands[0].reg))
6678 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6679 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6680 inst.operands[0].reg);
6682 inst.instruction = THUMB_OP16 (inst.instruction);
6683 inst.instruction |= inst.operands[0].reg << 8;
6684 inst.instruction |= inst.operands[1].imm;
6688 if (inst.operands[1].imm & (1 << 13))
6689 as_warn (_("SP should not be in register list"));
6690 if (inst.instruction == T_MNEM_stmia)
6692 if (inst.operands[1].imm & (1 << 15))
6693 as_warn (_("PC should not be in register list"));
6694 if (inst.operands[1].imm & (1 << inst.operands[0].reg))
6695 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6696 inst.operands[0].reg);
6700 if (inst.operands[1].imm & (1 << 14)
6701 && inst.operands[1].imm & (1 << 15))
6702 as_warn (_("LR and PC should not both be in register list"));
6703 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6704 && inst.operands[0].writeback)
6705 as_warn (_("base register should not be in register list "
6706 "when written back"));
6708 if (inst.instruction < 0xffff)
6709 inst.instruction = THUMB_OP32 (inst.instruction);
6710 inst.instruction |= inst.operands[0].reg << 16;
6711 inst.instruction |= inst.operands[1].imm;
6712 if (inst.operands[0].writeback)
6713 inst.instruction |= WRITE_BACK;
6718 constraint (inst.operands[0].reg > 7
6719 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
6720 if (inst.instruction == T_MNEM_stmia)
6722 if (!inst.operands[0].writeback)
6723 as_warn (_("this instruction will write back the base register"));
6724 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6725 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6726 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6727 inst.operands[0].reg);
6731 if (!inst.operands[0].writeback
6732 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
6733 as_warn (_("this instruction will write back the base register"));
6734 else if (inst.operands[0].writeback
6735 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
6736 as_warn (_("this instruction will not write back the base register"));
6739 inst.instruction = THUMB_OP16 (inst.instruction);
6740 inst.instruction |= inst.operands[0].reg << 8;
6741 inst.instruction |= inst.operands[1].imm;
6748 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6749 || inst.operands[1].postind || inst.operands[1].writeback
6750 || inst.operands[1].immisreg || inst.operands[1].shifted
6751 || inst.operands[1].negative,
6754 inst.instruction |= inst.operands[0].reg << 12;
6755 inst.instruction |= inst.operands[1].reg << 16;
6756 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
6762 if (!inst.operands[1].present)
6764 constraint (inst.operands[0].reg == REG_LR,
6765 _("r14 not allowed as first register "
6766 "when second register is omitted"));
6767 inst.operands[1].reg = inst.operands[0].reg + 1;
6769 constraint (inst.operands[0].reg == inst.operands[1].reg,
6772 inst.instruction |= inst.operands[0].reg << 12;
6773 inst.instruction |= inst.operands[1].reg << 8;
6774 inst.instruction |= inst.operands[2].reg << 16;
6780 unsigned long opcode;
6783 opcode = inst.instruction;
6786 if (inst.operands[1].isreg
6787 && !inst.operands[1].writeback
6788 && !inst.operands[1].shifted && !inst.operands[1].postind
6789 && !inst.operands[1].negative && inst.operands[0].reg <= 7
6791 && inst.size_req != 4)
6793 /* Insn may have a 16-bit form. */
6794 Rn = inst.operands[1].reg;
6795 if (inst.operands[1].immisreg)
6797 inst.instruction = THUMB_OP16 (opcode);
6799 if (Rn <= 7 && inst.operands[1].imm <= 7)
6802 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
6803 && opcode != T_MNEM_ldrsb)
6804 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
6805 || (Rn == REG_SP && opcode == T_MNEM_str))
6812 if (inst.reloc.pc_rel)
6813 opcode = T_MNEM_ldr_pc2;
6815 opcode = T_MNEM_ldr_pc;
6819 if (opcode == T_MNEM_ldr)
6820 opcode = T_MNEM_ldr_sp;
6822 opcode = T_MNEM_str_sp;
6824 inst.instruction = inst.operands[0].reg << 8;
6828 inst.instruction = inst.operands[0].reg;
6829 inst.instruction |= inst.operands[1].reg << 3;
6831 inst.instruction |= THUMB_OP16 (opcode);
6832 if (inst.size_req == 2)
6833 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6835 inst.relax = opcode;
6839 /* Definitely a 32-bit variant. */
6840 inst.instruction = THUMB_OP32 (opcode);
6841 inst.instruction |= inst.operands[0].reg << 12;
6842 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
6846 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6848 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
6850 /* Only [Rn,Rm] is acceptable. */
6851 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
6852 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
6853 || inst.operands[1].postind || inst.operands[1].shifted
6854 || inst.operands[1].negative,
6855 _("Thumb does not support this addressing mode"));
6856 inst.instruction = THUMB_OP16 (inst.instruction);
6860 inst.instruction = THUMB_OP16 (inst.instruction);
6861 if (!inst.operands[1].isreg)
6862 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
6865 constraint (!inst.operands[1].preind
6866 || inst.operands[1].shifted
6867 || inst.operands[1].writeback,
6868 _("Thumb does not support this addressing mode"));
6869 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
6871 constraint (inst.instruction & 0x0600,
6872 _("byte or halfword not valid for base register"));
6873 constraint (inst.operands[1].reg == REG_PC
6874 && !(inst.instruction & THUMB_LOAD_BIT),
6875 _("r15 based store not allowed"));
6876 constraint (inst.operands[1].immisreg,
6877 _("invalid base register for register offset"));
6879 if (inst.operands[1].reg == REG_PC)
6880 inst.instruction = T_OPCODE_LDR_PC;
6881 else if (inst.instruction & THUMB_LOAD_BIT)
6882 inst.instruction = T_OPCODE_LDR_SP;
6884 inst.instruction = T_OPCODE_STR_SP;
6886 inst.instruction |= inst.operands[0].reg << 8;
6887 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6891 constraint (inst.operands[1].reg > 7, BAD_HIREG);
6892 if (!inst.operands[1].immisreg)
6894 /* Immediate offset. */
6895 inst.instruction |= inst.operands[0].reg;
6896 inst.instruction |= inst.operands[1].reg << 3;
6897 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6901 /* Register offset. */
6902 constraint (inst.operands[1].imm > 7, BAD_HIREG);
6903 constraint (inst.operands[1].negative,
6904 _("Thumb does not support this addressing mode"));
6907 switch (inst.instruction)
6909 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
6910 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
6911 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
6912 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
6913 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
6914 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
6915 case 0x5600 /* ldrsb */:
6916 case 0x5e00 /* ldrsh */: break;
6920 inst.instruction |= inst.operands[0].reg;
6921 inst.instruction |= inst.operands[1].reg << 3;
6922 inst.instruction |= inst.operands[1].imm << 6;
6928 if (!inst.operands[1].present)
6930 inst.operands[1].reg = inst.operands[0].reg + 1;
6931 constraint (inst.operands[0].reg == REG_LR,
6932 _("r14 not allowed here"));
6934 inst.instruction |= inst.operands[0].reg << 12;
6935 inst.instruction |= inst.operands[1].reg << 8;
6936 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
6943 inst.instruction |= inst.operands[0].reg << 12;
6944 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
6950 inst.instruction |= inst.operands[0].reg << 8;
6951 inst.instruction |= inst.operands[1].reg << 16;
6952 inst.instruction |= inst.operands[2].reg;
6953 inst.instruction |= inst.operands[3].reg << 12;
6959 inst.instruction |= inst.operands[0].reg << 12;
6960 inst.instruction |= inst.operands[1].reg << 8;
6961 inst.instruction |= inst.operands[2].reg << 16;
6962 inst.instruction |= inst.operands[3].reg;
6970 int r0off = (inst.instruction == T_MNEM_mov
6971 || inst.instruction == T_MNEM_movs) ? 8 : 16;
6972 unsigned long opcode;
6974 bfd_boolean low_regs;
6976 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
6977 opcode = inst.instruction;
6978 if (current_it_mask)
6979 narrow = opcode != T_MNEM_movs;
6981 narrow = opcode != T_MNEM_movs || low_regs;
6982 if (inst.size_req == 4
6983 || inst.operands[1].shifted)
6986 if (!inst.operands[1].isreg)
6988 /* Immediate operand. */
6989 if (current_it_mask == 0 && opcode == T_MNEM_mov)
6991 if (low_regs && narrow)
6993 inst.instruction = THUMB_OP16 (opcode);
6994 inst.instruction |= inst.operands[0].reg << 8;
6995 if (inst.size_req == 2)
6996 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
6998 inst.relax = opcode;
7002 inst.instruction = THUMB_OP32 (inst.instruction);
7003 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7004 inst.instruction |= inst.operands[0].reg << r0off;
7005 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7010 inst.instruction = THUMB_OP32 (inst.instruction);
7011 inst.instruction |= inst.operands[0].reg << r0off;
7012 encode_thumb32_shifted_operand (1);
7015 switch (inst.instruction)
7018 inst.instruction = T_OPCODE_MOV_HR;
7019 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
7020 inst.instruction |= (inst.operands[0].reg & 0x7);
7021 inst.instruction |= inst.operands[1].reg << 3;
7025 /* We know we have low registers at this point.
7026 Generate ADD Rd, Rs, #0. */
7027 inst.instruction = T_OPCODE_ADD_I3;
7028 inst.instruction |= inst.operands[0].reg;
7029 inst.instruction |= inst.operands[1].reg << 3;
7035 inst.instruction = T_OPCODE_CMP_LR;
7036 inst.instruction |= inst.operands[0].reg;
7037 inst.instruction |= inst.operands[1].reg << 3;
7041 inst.instruction = T_OPCODE_CMP_HR;
7042 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
7043 inst.instruction |= (inst.operands[0].reg & 0x7);
7044 inst.instruction |= inst.operands[1].reg << 3;
7051 inst.instruction = THUMB_OP16 (inst.instruction);
7052 if (inst.operands[1].isreg)
7054 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
7056 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
7057 since a MOV instruction produces unpredictable results. */
7058 if (inst.instruction == T_OPCODE_MOV_I8)
7059 inst.instruction = T_OPCODE_ADD_I3;
7061 inst.instruction = T_OPCODE_CMP_LR;
7063 inst.instruction |= inst.operands[0].reg;
7064 inst.instruction |= inst.operands[1].reg << 3;
7068 if (inst.instruction == T_OPCODE_MOV_I8)
7069 inst.instruction = T_OPCODE_MOV_HR;
7071 inst.instruction = T_OPCODE_CMP_HR;
7077 constraint (inst.operands[0].reg > 7,
7078 _("only lo regs allowed with immediate"));
7079 inst.instruction |= inst.operands[0].reg << 8;
7080 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
7087 inst.instruction |= inst.operands[0].reg << 8;
7088 inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
7089 inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
7090 inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
7091 inst.instruction |= (inst.operands[1].imm & 0x00ff);
7099 int r0off = (inst.instruction == T_MNEM_mvn
7100 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
7103 if (inst.size_req == 4
7104 || inst.instruction > 0xffff
7105 || inst.operands[1].shifted
7106 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7108 else if (inst.instruction == T_MNEM_cmn)
7110 else if (THUMB_SETS_FLAGS (inst.instruction))
7111 narrow = (current_it_mask == 0);
7113 narrow = (current_it_mask != 0);
7115 if (!inst.operands[1].isreg)
7117 /* For an immediate, we always generate a 32-bit opcode;
7118 section relaxation will shrink it later if possible. */
7119 if (inst.instruction < 0xffff)
7120 inst.instruction = THUMB_OP32 (inst.instruction);
7121 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7122 inst.instruction |= inst.operands[0].reg << r0off;
7123 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7127 /* See if we can do this with a 16-bit instruction. */
7130 inst.instruction = THUMB_OP16 (inst.instruction);
7131 inst.instruction |= inst.operands[0].reg;
7132 inst.instruction |= inst.operands[1].reg << 3;
7136 constraint (inst.operands[1].shifted
7137 && inst.operands[1].immisreg,
7138 _("shift must be constant"));
7139 if (inst.instruction < 0xffff)
7140 inst.instruction = THUMB_OP32 (inst.instruction);
7141 inst.instruction |= inst.operands[0].reg << r0off;
7142 encode_thumb32_shifted_operand (1);
7148 constraint (inst.instruction > 0xffff
7149 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
7150 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
7151 _("unshifted register required"));
7152 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7155 inst.instruction = THUMB_OP16 (inst.instruction);
7156 inst.instruction |= inst.operands[0].reg;
7157 inst.instruction |= inst.operands[1].reg << 3;
7164 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7165 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7167 _("'CPSR' or 'SPSR' expected"));
7168 inst.instruction |= inst.operands[0].reg << 8;
7169 inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2;
7175 constraint (!inst.operands[1].isreg,
7176 _("Thumb encoding does not support an immediate here"));
7177 inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2;
7178 inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8;
7179 inst.instruction |= inst.operands[1].reg << 16;
7185 if (!inst.operands[2].present)
7186 inst.operands[2].reg = inst.operands[0].reg;
7188 /* There is no 32-bit MULS and no 16-bit MUL. */
7189 if (unified_syntax && inst.instruction == T_MNEM_mul)
7191 inst.instruction = THUMB_OP32 (inst.instruction);
7192 inst.instruction |= inst.operands[0].reg << 8;
7193 inst.instruction |= inst.operands[1].reg << 16;
7194 inst.instruction |= inst.operands[2].reg << 0;
7198 constraint (!unified_syntax
7199 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
7200 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7203 inst.instruction = THUMB_OP16 (inst.instruction);
7204 inst.instruction |= inst.operands[0].reg;
7206 if (inst.operands[0].reg == inst.operands[1].reg)
7207 inst.instruction |= inst.operands[2].reg << 3;
7208 else if (inst.operands[0].reg == inst.operands[2].reg)
7209 inst.instruction |= inst.operands[1].reg << 3;
7211 constraint (1, _("dest must overlap one source register"));
7218 inst.instruction |= inst.operands[0].reg << 12;
7219 inst.instruction |= inst.operands[1].reg << 8;
7220 inst.instruction |= inst.operands[2].reg << 16;
7221 inst.instruction |= inst.operands[3].reg;
7223 if (inst.operands[0].reg == inst.operands[1].reg)
7224 as_tsktsk (_("rdhi and rdlo must be different"));
7232 if (inst.size_req == 4 || inst.operands[0].imm > 15)
7234 inst.instruction = THUMB_OP32 (inst.instruction);
7235 inst.instruction |= inst.operands[0].imm;
7239 inst.instruction = THUMB_OP16 (inst.instruction);
7240 inst.instruction |= inst.operands[0].imm << 4;
7245 constraint (inst.operands[0].present,
7246 _("Thumb does not support NOP with hints"));
7247 inst.instruction = 0x46c0;
7258 if (THUMB_SETS_FLAGS (inst.instruction))
7259 narrow = (current_it_mask == 0);
7261 narrow = (current_it_mask != 0);
7262 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7264 if (inst.size_req == 4)
7269 inst.instruction = THUMB_OP32 (inst.instruction);
7270 inst.instruction |= inst.operands[0].reg << 8;
7271 inst.instruction |= inst.operands[1].reg << 16;
7275 inst.instruction = THUMB_OP16 (inst.instruction);
7276 inst.instruction |= inst.operands[0].reg;
7277 inst.instruction |= inst.operands[1].reg << 3;
7282 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7284 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7286 inst.instruction = THUMB_OP16 (inst.instruction);
7287 inst.instruction |= inst.operands[0].reg;
7288 inst.instruction |= inst.operands[1].reg << 3;
7295 inst.instruction |= inst.operands[0].reg << 8;
7296 inst.instruction |= inst.operands[1].reg << 16;
7297 inst.instruction |= inst.operands[2].reg;
7298 if (inst.operands[3].present)
7300 unsigned int val = inst.reloc.exp.X_add_number;
7301 constraint (inst.reloc.exp.X_op != O_constant,
7302 _("expression too complex"));
7303 inst.instruction |= (val & 0x1c) << 10;
7304 inst.instruction |= (val & 0x03) << 6;
7311 if (!inst.operands[3].present)
7312 inst.instruction &= ~0x00000020;
7319 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
7323 do_t_push_pop (void)
7327 constraint (inst.operands[0].writeback,
7328 _("push/pop do not support {reglist}^"));
7329 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
7330 _("expression too complex"));
7332 mask = inst.operands[0].imm;
7333 if ((mask & ~0xff) == 0)
7334 inst.instruction = THUMB_OP16 (inst.instruction);
7335 else if ((inst.instruction == T_MNEM_push
7336 && (mask & ~0xff) == 1 << REG_LR)
7337 || (inst.instruction == T_MNEM_pop
7338 && (mask & ~0xff) == 1 << REG_PC))
7340 inst.instruction = THUMB_OP16 (inst.instruction);
7341 inst.instruction |= THUMB_PP_PC_LR;
7344 else if (unified_syntax)
7346 if (mask & (1 << 13))
7347 inst.error = _("SP not allowed in register list");
7348 if (inst.instruction == T_MNEM_push)
7350 if (mask & (1 << 15))
7351 inst.error = _("PC not allowed in register list");
7355 if (mask & (1 << 14)
7356 && mask & (1 << 15))
7357 inst.error = _("LR and PC should not both be in register list");
7359 if ((mask & (mask - 1)) == 0)
7361 /* Single register push/pop implemented as str/ldr. */
7362 if (inst.instruction == T_MNEM_push)
7363 inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
7365 inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
7366 mask = ffs(mask) - 1;
7370 inst.instruction = THUMB_OP32 (inst.instruction);
7374 inst.error = _("invalid register list to push/pop instruction");
7378 inst.instruction |= mask;
7384 inst.instruction |= inst.operands[0].reg << 8;
7385 inst.instruction |= inst.operands[1].reg << 16;
7391 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7392 && inst.size_req != 4)
7394 inst.instruction = THUMB_OP16 (inst.instruction);
7395 inst.instruction |= inst.operands[0].reg;
7396 inst.instruction |= inst.operands[1].reg << 3;
7398 else if (unified_syntax)
7400 inst.instruction = THUMB_OP32 (inst.instruction);
7401 inst.instruction |= inst.operands[0].reg << 8;
7402 inst.instruction |= inst.operands[1].reg << 16;
7403 inst.instruction |= inst.operands[1].reg;
7406 inst.error = BAD_HIREG;
7414 Rd = inst.operands[0].reg;
7415 Rs = (inst.operands[1].present
7416 ? inst.operands[1].reg /* Rd, Rs, foo */
7417 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
7419 inst.instruction |= Rd << 8;
7420 inst.instruction |= Rs << 16;
7421 if (!inst.operands[2].isreg)
7423 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7424 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7427 encode_thumb32_shifted_operand (2);
7433 if (inst.operands[0].imm)
7434 inst.instruction |= 0x8;
7440 if (!inst.operands[1].present)
7441 inst.operands[1].reg = inst.operands[0].reg;
7448 switch (inst.instruction)
7451 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
7453 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
7455 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
7457 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
7461 if (THUMB_SETS_FLAGS (inst.instruction))
7462 narrow = (current_it_mask == 0);
7464 narrow = (current_it_mask != 0);
7465 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7467 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
7469 if (inst.operands[2].isreg
7470 && (inst.operands[1].reg != inst.operands[0].reg
7471 || inst.operands[2].reg > 7))
7473 if (inst.size_req == 4)
7478 if (inst.operands[2].isreg)
7480 inst.instruction = THUMB_OP32 (inst.instruction);
7481 inst.instruction |= inst.operands[0].reg << 8;
7482 inst.instruction |= inst.operands[1].reg << 16;
7483 inst.instruction |= inst.operands[2].reg;
7487 inst.operands[1].shifted = 1;
7488 inst.operands[1].shift_kind = shift_kind;
7489 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
7490 ? T_MNEM_movs : T_MNEM_mov);
7491 inst.instruction |= inst.operands[0].reg << 8;
7492 encode_thumb32_shifted_operand (1);
7493 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7494 inst.reloc.type = BFD_RELOC_UNUSED;
7499 if (inst.operands[2].isreg)
7503 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
7504 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
7505 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
7506 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
7510 inst.instruction |= inst.operands[0].reg;
7511 inst.instruction |= inst.operands[2].reg << 3;
7517 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
7518 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
7519 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
7522 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7523 inst.instruction |= inst.operands[0].reg;
7524 inst.instruction |= inst.operands[1].reg << 3;
7530 constraint (inst.operands[0].reg > 7
7531 || inst.operands[1].reg > 7, BAD_HIREG);
7532 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7534 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
7536 constraint (inst.operands[2].reg > 7, BAD_HIREG);
7537 constraint (inst.operands[0].reg != inst.operands[1].reg,
7538 _("source1 and dest must be same register"));
7540 switch (inst.instruction)
7542 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
7543 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
7544 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
7545 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
7549 inst.instruction |= inst.operands[0].reg;
7550 inst.instruction |= inst.operands[2].reg << 3;
7554 switch (inst.instruction)
7556 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
7557 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
7558 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
7559 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
7562 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7563 inst.instruction |= inst.operands[0].reg;
7564 inst.instruction |= inst.operands[1].reg << 3;
7572 inst.instruction |= inst.operands[0].reg << 8;
7573 inst.instruction |= inst.operands[1].reg << 16;
7574 inst.instruction |= inst.operands[2].reg;
7580 unsigned int value = inst.reloc.exp.X_add_number;
7581 constraint (inst.reloc.exp.X_op != O_constant,
7582 _("expression too complex"));
7583 inst.reloc.type = BFD_RELOC_UNUSED;
7584 inst.instruction |= (value & 0xf000) >> 12;
7585 inst.instruction |= (value & 0x0ff0);
7586 inst.instruction |= (value & 0x000f) << 16;
7592 inst.instruction |= inst.operands[0].reg << 8;
7593 inst.instruction |= inst.operands[1].imm - 1;
7594 inst.instruction |= inst.operands[2].reg << 16;
7596 if (inst.operands[3].present)
7598 constraint (inst.reloc.exp.X_op != O_constant,
7599 _("expression too complex"));
7601 if (inst.reloc.exp.X_add_number != 0)
7603 if (inst.operands[3].shift_kind == SHIFT_ASR)
7604 inst.instruction |= 0x00200000; /* sh bit */
7605 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7606 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7608 inst.reloc.type = BFD_RELOC_UNUSED;
7615 inst.instruction |= inst.operands[0].reg << 8;
7616 inst.instruction |= inst.operands[1].imm - 1;
7617 inst.instruction |= inst.operands[2].reg << 16;
7623 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7624 || inst.operands[2].postind || inst.operands[2].writeback
7625 || inst.operands[2].immisreg || inst.operands[2].shifted
7626 || inst.operands[2].negative,
7629 inst.instruction |= inst.operands[0].reg << 8;
7630 inst.instruction |= inst.operands[1].reg << 12;
7631 inst.instruction |= inst.operands[2].reg << 16;
7632 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
7638 if (!inst.operands[2].present)
7639 inst.operands[2].reg = inst.operands[1].reg + 1;
7641 constraint (inst.operands[0].reg == inst.operands[1].reg
7642 || inst.operands[0].reg == inst.operands[2].reg
7643 || inst.operands[0].reg == inst.operands[3].reg
7644 || inst.operands[1].reg == inst.operands[2].reg,
7647 inst.instruction |= inst.operands[0].reg;
7648 inst.instruction |= inst.operands[1].reg << 12;
7649 inst.instruction |= inst.operands[2].reg << 8;
7650 inst.instruction |= inst.operands[3].reg << 16;
7656 inst.instruction |= inst.operands[0].reg << 8;
7657 inst.instruction |= inst.operands[1].reg << 16;
7658 inst.instruction |= inst.operands[2].reg;
7659 inst.instruction |= inst.operands[3].imm << 4;
7665 if (inst.instruction <= 0xffff && inst.size_req != 4
7666 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7667 && (!inst.operands[2].present || inst.operands[2].imm == 0))
7669 inst.instruction = THUMB_OP16 (inst.instruction);
7670 inst.instruction |= inst.operands[0].reg;
7671 inst.instruction |= inst.operands[1].reg << 3;
7673 else if (unified_syntax)
7675 if (inst.instruction <= 0xffff)
7676 inst.instruction = THUMB_OP32 (inst.instruction);
7677 inst.instruction |= inst.operands[0].reg << 8;
7678 inst.instruction |= inst.operands[1].reg;
7679 inst.instruction |= inst.operands[2].imm << 4;
7683 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
7684 _("Thumb encoding does not support rotation"));
7685 constraint (1, BAD_HIREG);
7692 inst.reloc.type = BFD_RELOC_ARM_SWI;
7700 half = (inst.instruction & 0x10) != 0;
7701 constraint (inst.operands[0].imm == 15,
7702 _("PC is not a valid index register"));
7703 constraint (!half && inst.operands[0].shifted,
7704 _("instruction does not allow shifted index"));
7705 constraint (half && !inst.operands[0].shifted,
7706 _("instruction requires shifted index"));
7707 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
7713 inst.instruction |= inst.operands[0].reg << 8;
7714 inst.instruction |= inst.operands[1].imm;
7715 inst.instruction |= inst.operands[2].reg << 16;
7717 if (inst.operands[3].present)
7719 constraint (inst.reloc.exp.X_op != O_constant,
7720 _("expression too complex"));
7721 if (inst.reloc.exp.X_add_number != 0)
7723 if (inst.operands[3].shift_kind == SHIFT_ASR)
7724 inst.instruction |= 0x00200000; /* sh bit */
7726 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7727 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7729 inst.reloc.type = BFD_RELOC_UNUSED;
7736 inst.instruction |= inst.operands[0].reg << 8;
7737 inst.instruction |= inst.operands[1].imm;
7738 inst.instruction |= inst.operands[2].reg << 16;
7741 /* Overall per-instruction processing. */
7743 /* We need to be able to fix up arbitrary expressions in some statements.
7744 This is so that we can handle symbols that are an arbitrary distance from
7745 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7746 which returns part of an address in a form which will be valid for
7747 a data instruction. We do this by pushing the expression into a symbol
7748 in the expr_section, and creating a fix for that. */
7751 fix_new_arm (fragS * frag,
7766 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7770 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7775 /* Mark whether the fix is to a THUMB instruction, or an ARM
7777 new_fix->tc_fix_data = thumb_mode;
7780 /* Create a frg for an instruction requiring relaxation. */
7782 output_relax_insn (void)
7788 switch (inst.reloc.exp.X_op)
7791 sym = inst.reloc.exp.X_add_symbol;
7792 offset = inst.reloc.exp.X_add_number;
7796 offset = inst.reloc.exp.X_add_number;
7799 sym = make_expr_symbol (&inst.reloc.exp);
7803 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
7804 inst.relax, sym, offset, NULL/*offset, opcode*/);
7805 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
7808 dwarf2_emit_insn (INSN_SIZE);
7812 /* Write a 32-bit thumb instruction to buf. */
7814 put_thumb32_insn (char * buf, unsigned long insn)
7816 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
7817 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
7821 output_inst (const char * str)
7827 as_bad ("%s -- `%s'", inst.error, str);
7831 output_relax_insn();
7837 to = frag_more (inst.size);
7839 if (thumb_mode && (inst.size > THUMB_SIZE))
7841 assert (inst.size == (2 * THUMB_SIZE));
7842 put_thumb32_insn (to, inst.instruction);
7844 else if (inst.size > INSN_SIZE)
7846 assert (inst.size == (2 * INSN_SIZE));
7847 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7848 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
7851 md_number_to_chars (to, inst.instruction, inst.size);
7853 if (inst.reloc.type != BFD_RELOC_UNUSED)
7854 fix_new_arm (frag_now, to - frag_now->fr_literal,
7855 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7859 dwarf2_emit_insn (inst.size);
7863 /* Tag values used in struct asm_opcode's tag field. */
7866 OT_unconditional, /* Instruction cannot be conditionalized.
7867 The ARM condition field is still 0xE. */
7868 OT_unconditionalF, /* Instruction cannot be conditionalized
7869 and carries 0xF in its ARM condition field. */
7870 OT_csuffix, /* Instruction takes a conditional suffix. */
7871 OT_cinfix3, /* Instruction takes a conditional infix,
7872 beginning at character index 3. (In
7873 unified mode, it becomes a suffix.) */
7874 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
7875 character index 3, even in unified mode. Used for
7876 legacy instructions where suffix and infix forms
7877 may be ambiguous. */
7878 OT_csuf_or_in3, /* Instruction takes either a conditional
7879 suffix or an infix at character index 3. */
7880 OT_odd_infix_unc, /* This is the unconditional variant of an
7881 instruction that takes a conditional infix
7882 at an unusual position. In unified mode,
7883 this variant will accept a suffix. */
7884 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
7885 are the conditional variants of instructions that
7886 take conditional infixes in unusual positions.
7887 The infix appears at character index
7888 (tag - OT_odd_infix_0). These are not accepted
7892 /* Subroutine of md_assemble, responsible for looking up the primary
7893 opcode from the mnemonic the user wrote. STR points to the
7894 beginning of the mnemonic.
7896 This is not simply a hash table lookup, because of conditional
7897 variants. Most instructions have conditional variants, which are
7898 expressed with a _conditional affix_ to the mnemonic. If we were
7899 to encode each conditional variant as a literal string in the opcode
7900 table, it would have approximately 20,000 entries.
7902 Most mnemonics take this affix as a suffix, and in unified syntax,
7903 'most' is upgraded to 'all'. However, in the divided syntax, some
7904 instructions take the affix as an infix, notably the s-variants of
7905 the arithmetic instructions. Of those instructions, all but six
7906 have the infix appear after the third character of the mnemonic.
7908 Accordingly, the algorithm for looking up primary opcodes given
7911 1. Look up the identifier in the opcode table.
7912 If we find a match, go to step U.
7914 2. Look up the last two characters of the identifier in the
7915 conditions table. If we find a match, look up the first N-2
7916 characters of the identifier in the opcode table. If we
7917 find a match, go to step CE.
7919 3. Look up the fourth and fifth characters of the identifier in
7920 the conditions table. If we find a match, extract those
7921 characters from the identifier, and look up the remaining
7922 characters in the opcode table. If we find a match, go
7927 U. Examine the tag field of the opcode structure, in case this is
7928 one of the six instructions with its conditional infix in an
7929 unusual place. If it is, the tag tells us where to find the
7930 infix; look it up in the conditions table and set inst.cond
7931 accordingly. Otherwise, this is an unconditional instruction.
7932 Again set inst.cond accordingly. Return the opcode structure.
7934 CE. Examine the tag field to make sure this is an instruction that
7935 should receive a conditional suffix. If it is not, fail.
7936 Otherwise, set inst.cond from the suffix we already looked up,
7937 and return the opcode structure.
7939 CM. Examine the tag field to make sure this is an instruction that
7940 should receive a conditional infix after the third character.
7941 If it is not, fail. Otherwise, undo the edits to the current
7942 line of input and proceed as for case CE. */
7944 static const struct asm_opcode *
7945 opcode_lookup (char **str)
7949 const struct asm_opcode *opcode;
7950 const struct asm_cond *cond;
7953 /* Scan up to the end of the mnemonic, which must end in white space,
7954 '.' (in unified mode only), or end of string. */
7955 for (base = end = *str; *end != '\0'; end++)
7956 if (*end == ' ' || (unified_syntax && *end == '.'))
7962 /* Handle a possible width suffix. */
7965 if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
7967 else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
7977 /* Look for unaffixed or special-case affixed mnemonic. */
7978 opcode = hash_find_n (arm_ops_hsh, base, end - base);
7982 if (opcode->tag < OT_odd_infix_0)
7984 inst.cond = COND_ALWAYS;
7989 as_warn (_("conditional infixes are deprecated in unified syntax"));
7990 affix = base + (opcode->tag - OT_odd_infix_0);
7991 cond = hash_find_n (arm_cond_hsh, affix, 2);
7994 inst.cond = cond->value;
7998 /* Cannot have a conditional suffix on a mnemonic of less than two
8003 /* Look for suffixed mnemonic. */
8005 cond = hash_find_n (arm_cond_hsh, affix, 2);
8006 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
8010 switch (opcode->tag)
8012 case OT_cinfix3_legacy:
8013 /* Ignore conditional suffixes matched on infix only mnemonics. */
8017 case OT_odd_infix_unc:
8018 if (!unified_syntax)
8020 /* else fall through */
8023 case OT_csuf_or_in3:
8024 inst.cond = cond->value;
8027 case OT_unconditional:
8028 case OT_unconditionalF:
8029 /* delayed diagnostic */
8030 inst.error = BAD_COND;
8031 inst.cond = COND_ALWAYS;
8039 /* Cannot have a usual-position infix on a mnemonic of less than
8040 six characters (five would be a suffix). */
8044 /* Look for infixed mnemonic in the usual position. */
8046 cond = hash_find_n (arm_cond_hsh, affix, 2);
8050 memcpy (save, affix, 2);
8051 memmove (affix, affix + 2, (end - affix) - 2);
8052 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
8053 memmove (affix + 2, affix, (end - affix) - 2);
8054 memcpy (affix, save, 2);
8056 if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3
8057 || opcode->tag == OT_cinfix3_legacy))
8060 if (unified_syntax && opcode->tag == OT_cinfix3)
8061 as_warn (_("conditional infixes are deprecated in unified syntax"));
8063 inst.cond = cond->value;
8071 md_assemble (char *str)
8074 const struct asm_opcode * opcode;
8076 /* Align the previous label if needed. */
8077 if (last_label_seen != NULL)
8079 symbol_set_frag (last_label_seen, frag_now);
8080 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
8081 S_SET_SEGMENT (last_label_seen, now_seg);
8084 memset (&inst, '\0', sizeof (inst));
8085 inst.reloc.type = BFD_RELOC_UNUSED;
8087 opcode = opcode_lookup (&p);
8090 /* It wasn't an instruction, but it might be a register alias of
8091 the form alias .req reg. */
8092 if (!create_register_alias (str, p))
8093 as_bad (_("bad instruction `%s'"), str);
8100 unsigned long variant;
8102 variant = cpu_variant;
8103 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
8104 if ((variant & ARM_EXT_V6T2) == 0)
8106 /* Check that this instruction is supported for this CPU. */
8107 if (thumb_mode == 1 && (opcode->tvariant & variant) == 0)
8109 as_bad (_("selected processor does not support `%s'"), str);
8112 if (inst.cond != COND_ALWAYS && !unified_syntax
8113 && opcode->tencode != do_t_branch)
8115 as_bad (_("Thumb does not support conditional execution"));
8119 /* Check conditional suffixes. */
8120 if (current_it_mask)
8123 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
8124 if (cond != inst.cond)
8126 as_bad (_("incorrect condition in IT block"));
8129 current_it_mask <<= 1;
8130 current_it_mask &= 0x1f;
8132 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
8134 as_bad (_("thumb conditional instrunction not in IT block"));
8138 mapping_state (MAP_THUMB);
8139 inst.instruction = opcode->tvalue;
8141 if (!parse_operands (p, opcode->operands))
8144 /* Clear current_it_mask at the end of an IT block. */
8145 if (current_it_mask == 0x10)
8146 current_it_mask = 0;
8148 if (!(inst.error || inst.relax))
8150 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
8151 inst.size = (inst.instruction > 0xffff ? 4 : 2);
8152 if (inst.size_req && inst.size_req != inst.size)
8154 as_bad (_("cannot honor width suffix -- `%s'"), str);
8158 thumb_arch_used |= opcode->tvariant;
8159 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
8160 set those bits when Thumb-2 32-bit instuctions are seen. ie.
8161 anything other than bl/blx.
8162 This is overly pessimistic for relaxable instructions. */
8163 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
8165 thumb_arch_used |= ARM_EXT_V6T2;
8169 /* Check that this instruction is supported for this CPU. */
8170 if ((opcode->avariant & cpu_variant) == 0)
8172 as_bad (_("selected processor does not support `%s'"), str);
8177 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
8181 mapping_state (MAP_ARM);
8182 inst.instruction = opcode->avalue;
8183 if (opcode->tag == OT_unconditionalF)
8184 inst.instruction |= 0xF << 28;
8186 inst.instruction |= inst.cond << 28;
8187 inst.size = INSN_SIZE;
8188 if (!parse_operands (p, opcode->operands))
8190 /* Arm mode bx is marked as both v4T and v5 because it's still required
8191 on a hypothetical non-thumb v5 core. */
8192 if (opcode->avariant == (ARM_EXT_V4T | ARM_EXT_V5))
8193 arm_arch_used |= ARM_EXT_V4T;
8195 arm_arch_used |= opcode->avariant;
8200 /* Various frobbings of labels and their addresses. */
8203 arm_start_line_hook (void)
8205 last_label_seen = NULL;
8209 arm_frob_label (symbolS * sym)
8211 last_label_seen = sym;
8213 ARM_SET_THUMB (sym, thumb_mode);
8215 #if defined OBJ_COFF || defined OBJ_ELF
8216 ARM_SET_INTERWORK (sym, support_interwork);
8219 /* Note - do not allow local symbols (.Lxxx) to be labeled
8220 as Thumb functions. This is because these labels, whilst
8221 they exist inside Thumb code, are not the entry points for
8222 possible ARM->Thumb calls. Also, these labels can be used
8223 as part of a computed goto or switch statement. eg gcc
8224 can generate code that looks like this:
8236 The first instruction loads the address of the jump table.
8237 The second instruction converts a table index into a byte offset.
8238 The third instruction gets the jump address out of the table.
8239 The fourth instruction performs the jump.
8241 If the address stored at .Laaa is that of a symbol which has the
8242 Thumb_Func bit set, then the linker will arrange for this address
8243 to have the bottom bit set, which in turn would mean that the
8244 address computation performed by the third instruction would end
8245 up with the bottom bit set. Since the ARM is capable of unaligned
8246 word loads, the instruction would then load the incorrect address
8247 out of the jump table, and chaos would ensue. */
8248 if (label_is_thumb_function_name
8249 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
8250 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
8252 /* When the address of a Thumb function is taken the bottom
8253 bit of that address should be set. This will allow
8254 interworking between Arm and Thumb functions to work
8257 THUMB_SET_FUNC (sym, 1);
8259 label_is_thumb_function_name = FALSE;
8263 dwarf2_emit_label (sym);
8268 arm_data_in_code (void)
8270 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
8272 *input_line_pointer = '/';
8273 input_line_pointer += 5;
8274 *input_line_pointer = 0;
8282 arm_canonicalize_symbol_name (char * name)
8286 if (thumb_mode && (len = strlen (name)) > 5
8287 && streq (name + len - 5, "/data"))
8288 *(name + len - 5) = 0;
8293 /* Table of all register names defined by default. The user can
8294 define additional names with .req. Note that all register names
8295 should appear in both upper and lowercase variants. Some registers
8296 also have mixed-case names. */
8298 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
8299 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8300 #define REGSET(p,t) \
8301 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8302 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8303 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8304 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8306 static const struct reg_entry reg_names[] =
8308 /* ARM integer registers. */
8309 REGSET(r, RN), REGSET(R, RN),
8311 /* ATPCS synonyms. */
8312 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
8313 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
8314 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
8316 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
8317 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
8318 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
8320 /* Well-known aliases. */
8321 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
8322 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
8324 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
8325 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
8327 /* Coprocessor numbers. */
8328 REGSET(p, CP), REGSET(P, CP),
8330 /* Coprocessor register numbers. The "cr" variants are for backward
8332 REGSET(c, CN), REGSET(C, CN),
8333 REGSET(cr, CN), REGSET(CR, CN),
8335 /* FPA registers. */
8336 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
8337 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
8339 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
8340 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
8342 /* VFP SP registers. */
8344 REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
8345 REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
8346 REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
8347 REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
8350 REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
8351 REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
8352 REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
8353 REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
8355 /* VFP DP Registers. */
8356 REGSET(d,VFD), REGSET(D,VFS),
8358 /* VFP control registers. */
8359 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
8360 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
8362 /* Maverick DSP coprocessor registers. */
8363 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
8364 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
8366 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
8367 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
8368 REGDEF(dspsc,0,DSPSC),
8370 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
8371 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
8372 REGDEF(DSPSC,0,DSPSC),
8374 /* iWMMXt data registers - p0, c0-15. */
8375 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
8377 /* iWMMXt control registers - p1, c0-3. */
8378 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
8379 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
8380 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
8381 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
8383 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
8384 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
8385 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
8386 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
8387 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
8389 /* XScale accumulator registers. */
8390 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
8396 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
8397 within psr_required_here. */
8398 static const struct asm_psr psrs[] =
8400 /* Backward compatibility notation. Note that "all" is no longer
8401 truly all possible PSR bits. */
8402 {"all", PSR_c | PSR_f},
8406 /* Individual flags. */
8411 /* Combinations of flags. */
8412 {"fs", PSR_f | PSR_s},
8413 {"fx", PSR_f | PSR_x},
8414 {"fc", PSR_f | PSR_c},
8415 {"sf", PSR_s | PSR_f},
8416 {"sx", PSR_s | PSR_x},
8417 {"sc", PSR_s | PSR_c},
8418 {"xf", PSR_x | PSR_f},
8419 {"xs", PSR_x | PSR_s},
8420 {"xc", PSR_x | PSR_c},
8421 {"cf", PSR_c | PSR_f},
8422 {"cs", PSR_c | PSR_s},
8423 {"cx", PSR_c | PSR_x},
8424 {"fsx", PSR_f | PSR_s | PSR_x},
8425 {"fsc", PSR_f | PSR_s | PSR_c},
8426 {"fxs", PSR_f | PSR_x | PSR_s},
8427 {"fxc", PSR_f | PSR_x | PSR_c},
8428 {"fcs", PSR_f | PSR_c | PSR_s},
8429 {"fcx", PSR_f | PSR_c | PSR_x},
8430 {"sfx", PSR_s | PSR_f | PSR_x},
8431 {"sfc", PSR_s | PSR_f | PSR_c},
8432 {"sxf", PSR_s | PSR_x | PSR_f},
8433 {"sxc", PSR_s | PSR_x | PSR_c},
8434 {"scf", PSR_s | PSR_c | PSR_f},
8435 {"scx", PSR_s | PSR_c | PSR_x},
8436 {"xfs", PSR_x | PSR_f | PSR_s},
8437 {"xfc", PSR_x | PSR_f | PSR_c},
8438 {"xsf", PSR_x | PSR_s | PSR_f},
8439 {"xsc", PSR_x | PSR_s | PSR_c},
8440 {"xcf", PSR_x | PSR_c | PSR_f},
8441 {"xcs", PSR_x | PSR_c | PSR_s},
8442 {"cfs", PSR_c | PSR_f | PSR_s},
8443 {"cfx", PSR_c | PSR_f | PSR_x},
8444 {"csf", PSR_c | PSR_s | PSR_f},
8445 {"csx", PSR_c | PSR_s | PSR_x},
8446 {"cxf", PSR_c | PSR_x | PSR_f},
8447 {"cxs", PSR_c | PSR_x | PSR_s},
8448 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
8449 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
8450 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
8451 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
8452 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
8453 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
8454 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
8455 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
8456 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
8457 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
8458 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
8459 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
8460 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
8461 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
8462 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
8463 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
8464 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
8465 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
8466 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
8467 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
8468 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
8469 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
8470 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
8471 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
8474 /* Table of all shift-in-operand names. */
8475 static const struct asm_shift_name shift_names [] =
8477 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
8478 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
8479 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
8480 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
8481 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
8482 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
8485 /* Table of all explicit relocation names. */
8487 static struct reloc_entry reloc_names[] =
8489 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
8490 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
8491 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
8492 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
8493 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
8494 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
8495 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
8496 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
8497 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
8498 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
8499 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
8503 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
8504 static const struct asm_cond conds[] =
8508 {"cs", 0x2}, {"hs", 0x2},
8509 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8523 /* Table of ARM-format instructions. */
8525 /* Macros for gluing together operand strings. N.B. In all cases
8526 other than OPS0, the trailing OP_stop comes from default
8527 zero-initialization of the unspecified elements of the array. */
8528 #define OPS0() { OP_stop, }
8529 #define OPS1(a) { OP_##a, }
8530 #define OPS2(a,b) { OP_##a,OP_##b, }
8531 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8532 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8533 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8534 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8536 /* These macros abstract out the exact format of the mnemonic table and
8537 save some repeated characters. */
8539 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8540 #define TxCE(mnem, op, top, nops, ops, ae, te) \
8541 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
8542 THUMB_VARIANT, do_##ae, do_##te }
8544 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8545 a T_MNEM_xyz enumerator. */
8546 #define TCE(mnem, aop, top, nops, ops, ae, te) \
8547 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8548 #define tCE(mnem, aop, top, nops, ops, ae, te) \
8549 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8551 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8552 infix after the third character. */
8553 #define TxC3(mnem, op, top, nops, ops, ae, te) \
8554 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
8555 THUMB_VARIANT, do_##ae, do_##te }
8556 #define TC3(mnem, aop, top, nops, ops, ae, te) \
8557 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8558 #define tC3(mnem, aop, top, nops, ops, ae, te) \
8559 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8561 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8562 appear in the condition table. */
8563 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8564 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8565 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
8567 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8568 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8569 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8570 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8571 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8572 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8573 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8574 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8575 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8576 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8577 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8578 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8579 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8580 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8581 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8582 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8583 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8584 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8585 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8586 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8588 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8589 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8590 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8591 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8593 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8594 field is still 0xE. */
8595 #define TUE(mnem, op, top, nops, ops, ae, te) \
8596 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8597 THUMB_VARIANT, do_##ae, do_##te }
8599 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8600 condition code field. */
8601 #define TUF(mnem, op, top, nops, ops, ae, te) \
8602 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8603 THUMB_VARIANT, do_##ae, do_##te }
8605 /* ARM-only variants of all the above. */
8606 #define CE(mnem, op, nops, ops, ae) \
8607 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8609 #define C3(mnem, op, nops, ops, ae) \
8610 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8612 /* Legacy mnemonics that always have conditional infix after the third
8614 #define CL(mnem, op, nops, ops, ae) \
8615 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8616 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8618 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
8619 #define cCE(mnem, op, nops, ops, ae) \
8620 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8622 /* Legacy coprocessor instructions where conditional infix and conditional
8623 suffix are ambiguous. For consistency this includes all FPA instructions,
8624 not just the potentially ambiguous ones. */
8625 #define cCL(mnem, op, nops, ops, ae) \
8626 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8627 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8629 /* Coprocessor, takes either a suffix or a position-3 infix
8630 (for an FPA corner case). */
8631 #define C3E(mnem, op, nops, ops, ae) \
8632 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
8633 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8635 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8636 { #m1 #m2 #m3, OPS##nops ops, \
8637 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8638 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8640 #define CM(m1, m2, op, nops, ops, ae) \
8641 xCM_(m1, , m2, op, nops, ops, ae), \
8642 xCM_(m1, eq, m2, op, nops, ops, ae), \
8643 xCM_(m1, ne, m2, op, nops, ops, ae), \
8644 xCM_(m1, cs, m2, op, nops, ops, ae), \
8645 xCM_(m1, hs, m2, op, nops, ops, ae), \
8646 xCM_(m1, cc, m2, op, nops, ops, ae), \
8647 xCM_(m1, ul, m2, op, nops, ops, ae), \
8648 xCM_(m1, lo, m2, op, nops, ops, ae), \
8649 xCM_(m1, mi, m2, op, nops, ops, ae), \
8650 xCM_(m1, pl, m2, op, nops, ops, ae), \
8651 xCM_(m1, vs, m2, op, nops, ops, ae), \
8652 xCM_(m1, vc, m2, op, nops, ops, ae), \
8653 xCM_(m1, hi, m2, op, nops, ops, ae), \
8654 xCM_(m1, ls, m2, op, nops, ops, ae), \
8655 xCM_(m1, ge, m2, op, nops, ops, ae), \
8656 xCM_(m1, lt, m2, op, nops, ops, ae), \
8657 xCM_(m1, gt, m2, op, nops, ops, ae), \
8658 xCM_(m1, le, m2, op, nops, ops, ae), \
8659 xCM_(m1, al, m2, op, nops, ops, ae)
8661 #define UE(mnem, op, nops, ops, ae) \
8662 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8664 #define UF(mnem, op, nops, ops, ae) \
8665 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8669 /* Thumb-only, unconditional. */
8670 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8672 static const struct asm_opcode insns[] =
8674 #define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
8675 #define THUMB_VARIANT ARM_EXT_V4T
8676 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
8677 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
8678 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
8679 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
8680 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
8681 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
8682 tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
8683 tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
8684 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
8685 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
8686 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
8687 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
8688 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
8689 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
8690 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
8691 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
8693 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8694 for setting PSR flag bits. They are obsolete in V6 and do not
8695 have Thumb equivalents. */
8696 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8697 tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8698 CL(tstp, 110f000, 2, (RR, SH), cmp),
8699 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8700 tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8701 CL(cmpp, 150f000, 2, (RR, SH), cmp),
8702 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8703 tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8704 CL(cmnp, 170f000, 2, (RR, SH), cmp),
8706 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
8707 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
8708 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
8709 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
8711 tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
8712 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
8713 tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
8714 tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
8716 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8717 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8718 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8719 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8721 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
8722 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
8723 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23),
8726 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
8727 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
8728 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
8730 /* Thumb-compatibility pseudo ops. */
8731 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
8732 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
8733 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
8734 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
8735 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
8736 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
8737 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
8738 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
8739 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
8740 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
8741 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
8742 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
8744 #undef THUMB_VARIANT
8745 #define THUMB_VARIANT ARM_EXT_V6
8746 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
8748 /* V1 instructions with no Thumb analogue prior to V6T2. */
8749 #undef THUMB_VARIANT
8750 #define THUMB_VARIANT ARM_EXT_V6T2
8751 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
8752 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
8753 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8754 TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8755 CL(teqp, 130f000, 2, (RR, SH), cmp),
8757 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
8758 TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt),
8759 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
8760 TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt),
8762 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8763 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8765 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8766 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8768 /* V1 instructions with no Thumb analogue at all. */
8769 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
8770 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
8772 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
8773 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
8774 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
8775 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
8776 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
8777 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
8778 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
8779 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
8782 #define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
8783 #undef THUMB_VARIANT
8784 #define THUMB_VARIANT ARM_EXT_V4T
8785 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8786 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8788 #undef THUMB_VARIANT
8789 #define THUMB_VARIANT ARM_EXT_V6T2
8790 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8791 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
8793 /* Generic coprocessor instructions. */
8794 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8795 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8796 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8797 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8798 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8799 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8800 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8803 #define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
8804 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8805 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8808 #define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
8809 TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs),
8810 TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
8813 #define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
8814 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8815 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8816 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8817 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8818 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8819 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8820 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8821 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8824 #define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
8825 #undef THUMB_VARIANT
8826 #define THUMB_VARIANT ARM_EXT_V4T
8827 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
8828 tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
8829 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8830 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8831 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8832 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8835 #define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
8836 /* ARM Architecture 4T. */
8837 /* Note: bx (and blx) are required on V5, even if the processor does
8838 not support Thumb. */
8839 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
8842 #define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
8843 #undef THUMB_VARIANT
8844 #define THUMB_VARIANT ARM_EXT_V5T
8845 /* Note: blx has 2 variants; the .value coded here is for
8846 BLX(2). Only this variant has conditional execution. */
8847 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
8848 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
8850 #undef THUMB_VARIANT
8851 #define THUMB_VARIANT ARM_EXT_V6T2
8852 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
8853 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8854 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8855 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8856 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8857 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8858 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8859 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8862 #define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
8863 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8864 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8865 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8866 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8868 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8869 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8871 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8872 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8873 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8874 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8876 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8877 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8878 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8879 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8881 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8882 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8884 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8885 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8886 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8887 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8890 #define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
8891 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
8892 TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8893 TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8895 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8896 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8899 #define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
8900 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
8903 #define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
8904 #undef THUMB_VARIANT
8905 #define THUMB_VARIANT ARM_EXT_V6
8906 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
8907 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
8908 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8909 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8910 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8911 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8912 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8913 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8914 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8915 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
8917 #undef THUMB_VARIANT
8918 #define THUMB_VARIANT ARM_EXT_V6T2
8919 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0),
8920 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
8921 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8922 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8923 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
8924 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
8925 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8926 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8927 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8928 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8929 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8930 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8931 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8932 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8933 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8934 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8935 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8936 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8937 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8938 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8939 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8940 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8941 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8942 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8943 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8944 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8945 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8946 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8947 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8948 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8949 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8950 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8951 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8952 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8953 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8954 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8955 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8956 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8957 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8958 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8959 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8960 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8961 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8962 UF(rfeib, 9900a00, 1, (RRw), rfe),
8963 UF(rfeda, 8100a00, 1, (RRw), rfe),
8964 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8965 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8966 UF(rfefa, 9900a00, 1, (RRw), rfe),
8967 UF(rfeea, 8100a00, 1, (RRw), rfe),
8968 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8969 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8970 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8971 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8972 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8973 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8974 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8975 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8976 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8977 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8978 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8979 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8980 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8981 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8982 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8983 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8984 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8985 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8986 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8987 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8988 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8989 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8990 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8991 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8992 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8993 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8994 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8995 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8996 TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs),
8997 UF(srsib, 9cd0500, 1, (I31w), srs),
8998 UF(srsda, 84d0500, 1, (I31w), srs),
8999 TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs),
9000 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
9001 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
9002 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
9003 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
9004 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9005 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9006 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
9007 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
9010 #define ARM_VARIANT ARM_EXT_V6K
9011 #undef THUMB_VARIANT
9012 #define THUMB_VARIANT ARM_EXT_V6K
9013 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
9014 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
9015 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
9016 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
9018 #undef THUMB_VARIANT
9019 #define THUMB_VARIANT ARM_EXT_V6T2
9020 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
9021 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
9022 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
9023 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
9024 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
9025 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
9026 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
9029 #define ARM_VARIANT ARM_EXT_V6Z
9030 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
9033 #define ARM_VARIANT ARM_EXT_V6T2
9034 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
9035 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
9036 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
9037 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
9039 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
9040 TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16),
9041 TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16),
9042 TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
9044 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9045 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9046 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9047 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9049 UT(cbnz, b900, 2, (RR, EXP), t_czb),
9050 UT(cbz, b100, 2, (RR, EXP), t_czb),
9051 /* ARM does not really have an IT instruction. */
9052 TUE(it, 0, bf08, 1, (COND), it, t_it),
9053 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
9054 TUE(ite, 0, bf04, 1, (COND), it, t_it),
9055 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
9056 TUE(itet, 0, bf06, 1, (COND), it, t_it),
9057 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
9058 TUE(itee, 0, bf02, 1, (COND), it, t_it),
9059 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
9060 TUE(itett, 0, bf07, 1, (COND), it, t_it),
9061 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
9062 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
9063 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
9064 TUE(itete, 0, bf05, 1, (COND), it, t_it),
9065 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
9066 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
9068 /* Thumb2 only instructions. */
9070 #define ARM_VARIANT 0
9072 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
9073 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
9074 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
9075 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
9078 #define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
9079 cCE(wfs, e200110, 1, (RR), rd),
9080 cCE(rfs, e300110, 1, (RR), rd),
9081 cCE(wfc, e400110, 1, (RR), rd),
9082 cCE(rfc, e500110, 1, (RR), rd),
9084 cCL(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
9085 cCL(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
9086 cCL(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
9087 cCL(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
9089 cCL(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
9090 cCL(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
9091 cCL(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
9092 cCL(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
9094 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
9095 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
9096 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
9097 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
9098 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
9099 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
9100 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
9101 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
9102 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
9103 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
9104 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
9105 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
9107 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
9108 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
9109 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
9110 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
9111 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
9112 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
9113 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
9114 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
9115 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
9116 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
9117 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
9118 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
9120 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
9121 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
9122 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
9123 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
9124 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
9125 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
9126 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
9127 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
9128 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
9129 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
9130 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
9131 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
9133 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
9134 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
9135 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
9136 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
9137 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
9138 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
9139 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
9140 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
9141 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
9142 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
9143 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
9144 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
9146 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
9147 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
9148 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
9149 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
9150 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
9151 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
9152 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
9153 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
9154 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
9155 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
9156 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
9157 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
9159 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
9160 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
9161 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
9162 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
9163 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
9164 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
9165 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
9166 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
9167 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
9168 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
9169 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
9170 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
9172 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
9173 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
9174 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
9175 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
9176 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
9177 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
9178 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
9179 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
9180 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
9181 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
9182 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
9183 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
9185 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
9186 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
9187 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
9188 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
9189 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
9190 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
9191 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
9192 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
9193 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
9194 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
9195 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
9196 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
9198 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
9199 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
9200 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
9201 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
9202 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
9203 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
9204 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
9205 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
9206 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
9207 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
9208 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
9209 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
9211 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
9212 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
9213 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
9214 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
9215 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
9216 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
9217 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
9218 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
9219 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
9220 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
9221 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
9222 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
9224 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
9225 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
9226 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
9227 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
9228 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
9229 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
9230 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
9231 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
9232 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
9233 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
9234 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
9235 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
9237 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
9238 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
9239 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
9240 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
9241 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
9242 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
9243 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
9244 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
9245 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
9246 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
9247 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
9248 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
9250 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
9251 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
9252 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
9253 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
9254 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
9255 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
9256 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
9257 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
9258 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
9259 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
9260 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
9261 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
9263 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
9264 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
9265 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
9266 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
9267 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
9268 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
9269 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
9270 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
9271 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
9272 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
9273 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
9274 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
9276 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
9277 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
9278 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
9279 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
9280 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
9281 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
9282 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
9283 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
9284 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
9285 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
9286 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
9287 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
9289 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
9290 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
9291 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
9292 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
9293 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
9294 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
9295 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
9296 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
9297 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
9298 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
9299 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
9300 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
9302 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
9303 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
9304 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
9305 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
9306 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
9307 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9308 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9309 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9310 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
9311 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
9312 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
9313 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
9315 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
9316 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
9317 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
9318 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
9319 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
9320 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9321 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9322 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9323 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
9324 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
9325 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
9326 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
9328 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
9329 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
9330 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
9331 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
9332 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
9333 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9334 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9335 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9336 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
9337 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
9338 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
9339 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
9341 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
9342 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
9343 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
9344 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
9345 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
9346 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9347 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9348 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9349 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
9350 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
9351 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
9352 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
9354 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
9355 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
9356 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
9357 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
9358 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
9359 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9360 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9361 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9362 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
9363 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
9364 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
9365 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
9367 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
9368 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
9369 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
9370 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
9371 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
9372 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9373 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9374 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9375 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
9376 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
9377 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
9378 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
9380 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
9381 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
9382 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
9383 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
9384 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
9385 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9386 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9387 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9388 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
9389 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
9390 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
9391 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
9393 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
9394 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
9395 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
9396 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
9397 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
9398 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9399 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9400 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9401 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
9402 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
9403 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
9404 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
9406 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
9407 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
9408 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
9409 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
9410 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
9411 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9412 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9413 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9414 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
9415 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
9416 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
9417 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
9419 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
9420 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
9421 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
9422 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
9423 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
9424 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9425 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9426 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9427 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
9428 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
9429 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
9430 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
9432 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9433 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9434 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9435 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9436 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9437 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9438 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9439 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9440 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9441 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9442 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9443 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9445 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9446 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9447 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9448 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9449 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9450 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9451 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9452 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9453 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9454 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9455 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9456 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9458 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9459 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9460 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9461 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9462 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9463 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9464 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9465 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9466 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9467 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9468 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9469 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9471 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
9472 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
9473 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
9474 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
9476 cCL(flts, e000110, 2, (RF, RR), rn_rd),
9477 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
9478 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
9479 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
9480 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
9481 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
9482 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
9483 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
9484 cCL(flte, e080110, 2, (RF, RR), rn_rd),
9485 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
9486 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
9487 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
9489 /* The implementation of the FIX instruction is broken on some
9490 assemblers, in that it accepts a precision specifier as well as a
9491 rounding specifier, despite the fact that this is meaningless.
9492 To be more compatible, we accept it as well, though of course it
9493 does not set any bits. */
9494 cCE(fix, e100110, 2, (RR, RF), rd_rm),
9495 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
9496 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
9497 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
9498 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
9499 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
9500 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
9501 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
9502 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
9503 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
9504 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
9505 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
9506 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
9508 /* Instructions that were new with the real FPA, call them V2. */
9510 #define ARM_VARIANT FPU_FPA_EXT_V2
9511 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9512 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9513 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9514 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9515 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9516 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9519 #define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
9520 /* Moves and type conversions. */
9521 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
9522 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
9523 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
9524 cCE(fmstat, ef1fa10, 0, (), noargs),
9525 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
9526 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
9527 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
9528 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9529 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
9530 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9531 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
9532 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
9534 /* Memory operations. */
9535 cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
9536 cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
9537 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9538 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9539 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9540 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9541 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9542 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9543 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9544 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9545 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9546 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9547 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9548 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9549 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9550 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9551 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9552 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9554 /* Monadic operations. */
9555 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
9556 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
9557 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
9559 /* Dyadic operations. */
9560 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9561 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9562 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9563 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9564 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9565 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9566 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9567 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9568 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9571 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
9572 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
9573 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
9574 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
9577 #define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
9578 /* Moves and type conversions. */
9579 cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
9580 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9581 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9582 cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
9583 cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
9584 cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
9585 cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
9586 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9587 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
9588 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9589 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9590 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9591 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9593 /* Memory operations. */
9594 cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
9595 cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
9596 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9597 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9598 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9599 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9600 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9601 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9602 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9603 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9605 /* Monadic operations. */
9606 cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
9607 cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
9608 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
9610 /* Dyadic operations. */
9611 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9612 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9613 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9614 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9615 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9616 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9617 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9618 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9619 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9622 cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
9623 cCE(fcmpzd, eb50b40, 1, (RVD), rd),
9624 cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
9625 cCE(fcmpezd, eb50bc0, 1, (RVD), rd),
9628 #define ARM_VARIANT FPU_VFP_EXT_V2
9629 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
9630 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
9631 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
9632 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
9635 #define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
9636 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9637 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9638 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9639 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9640 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9641 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9642 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
9643 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
9646 #define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
9647 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
9648 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
9649 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
9650 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
9651 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
9652 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
9653 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
9654 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
9655 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
9656 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9657 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9658 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9659 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9660 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9661 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9662 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9663 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9664 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9665 cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
9666 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
9667 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9668 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9669 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9670 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9671 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9672 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9673 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
9674 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
9675 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
9676 cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
9677 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
9678 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
9679 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
9680 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
9681 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
9682 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
9683 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
9684 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9685 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9686 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9687 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9688 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9689 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9690 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9691 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9692 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9693 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
9694 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9695 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9696 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9697 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9698 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9699 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9700 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9701 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9702 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9703 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9704 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9705 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9706 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9707 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9708 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9709 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9710 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9711 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9712 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9713 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9714 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9715 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9716 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9717 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9718 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9719 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9720 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9721 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9722 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9723 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9724 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9725 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9726 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9727 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9728 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9729 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9730 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9731 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9732 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9733 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9734 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9735 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
9736 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9737 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9738 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9739 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9740 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9741 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9742 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9743 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9744 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9745 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9746 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9747 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9748 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9749 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9750 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9751 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9752 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9753 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9754 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9755 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9756 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9757 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
9758 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9759 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9760 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9761 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9762 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9763 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9764 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9765 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9766 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9767 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9768 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9769 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9770 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9771 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9772 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9773 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9774 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9775 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9776 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9777 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9778 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9779 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9780 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9781 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9782 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9783 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9784 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9785 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9786 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9787 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9788 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9789 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
9790 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
9791 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
9792 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
9793 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
9794 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
9795 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9796 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9797 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9798 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
9799 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
9800 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
9801 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
9802 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
9803 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
9804 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9805 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9806 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9807 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9808 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
9811 #define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
9812 cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
9813 cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
9814 cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
9815 cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
9816 cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
9817 cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
9818 cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
9819 cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
9820 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
9821 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
9822 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
9823 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
9824 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
9825 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
9826 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
9827 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
9828 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
9829 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
9830 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
9831 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
9832 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
9833 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
9834 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
9835 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
9836 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
9837 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
9838 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
9839 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
9840 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
9841 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
9842 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
9843 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
9844 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
9845 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
9846 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
9847 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
9848 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
9849 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
9850 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
9851 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
9852 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
9853 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
9854 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
9855 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
9856 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
9857 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
9858 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
9859 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
9860 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
9861 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
9862 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
9863 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
9864 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
9865 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
9866 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
9867 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
9868 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
9869 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
9870 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
9871 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
9872 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
9873 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
9874 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
9875 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
9876 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9877 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9878 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9879 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9880 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9881 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9882 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9883 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9884 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9885 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9886 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9887 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9890 #undef THUMB_VARIANT
9913 /* MD interface: bits in the object file. */
9915 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9916 for use in the a.out file, and stores them in the array pointed to by buf.
9917 This knows about the endian-ness of the target machine and does
9918 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9919 2 (short) and 4 (long) Floating numbers are put out as a series of
9920 LITTLENUMS (shorts, here at least). */
9923 md_number_to_chars (char * buf, valueT val, int n)
9925 if (target_big_endian)
9926 number_to_chars_bigendian (buf, val, n);
9928 number_to_chars_littleendian (buf, val, n);
9932 md_chars_to_number (char * buf, int n)
9935 unsigned char * where = (unsigned char *) buf;
9937 if (target_big_endian)
9942 result |= (*where++ & 255);
9950 result |= (where[n] & 255);
9957 /* MD interface: Sections. */
9959 /* Estimate the size of a frag before relaxing. Assume everything fits in
9963 md_estimate_size_before_relax (fragS * fragp,
9964 segT segtype ATTRIBUTE_UNUSED)
9970 /* Convert a machine dependent frag. */
9973 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
9976 unsigned long old_op;
9984 buf = fragp->fr_literal + fragp->fr_fix;
9986 old_op = bfd_get_16(abfd, buf);
9987 if (fragp->fr_symbol) {
9988 exp.X_op = O_symbol;
9989 exp.X_add_symbol = fragp->fr_symbol;
9991 exp.X_op = O_constant;
9993 exp.X_add_number = fragp->fr_offset;
9994 opcode = fragp->fr_subtype;
9998 case T_MNEM_ldr_pc2:
10000 case T_MNEM_str_sp:
10007 if (fragp->fr_var == 4)
10009 insn = THUMB_OP32(opcode);
10010 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
10012 insn |= (old_op & 0x700) << 4;
10016 insn |= (old_op & 7) << 12;
10017 insn |= (old_op & 0x38) << 13;
10019 insn |= 0x00000c00;
10020 put_thumb32_insn (buf, insn);
10021 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10025 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
10027 pc_rel = (opcode == T_MNEM_ldr_pc2);
10030 if (fragp->fr_var == 4)
10032 insn = THUMB_OP32 (opcode);
10033 insn |= (old_op & 0xf0) << 4;
10034 put_thumb32_insn (buf, insn);
10035 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
10039 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10040 exp.X_add_number -= 4;
10048 if (fragp->fr_var == 4)
10050 int r0off = (opcode == T_MNEM_mov
10051 || opcode == T_MNEM_movs) ? 0 : 8;
10052 insn = THUMB_OP32 (opcode);
10053 insn = (insn & 0xe1ffffff) | 0x10000000;
10054 insn |= (old_op & 0x700) << r0off;
10055 put_thumb32_insn (buf, insn);
10056 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10060 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
10065 if (fragp->fr_var == 4)
10067 insn = THUMB_OP32(opcode);
10068 put_thumb32_insn (buf, insn);
10069 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
10072 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
10076 if (fragp->fr_var == 4)
10078 insn = THUMB_OP32(opcode);
10079 insn |= (old_op & 0xf00) << 14;
10080 put_thumb32_insn (buf, insn);
10081 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
10084 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
10087 case T_MNEM_add_sp:
10088 case T_MNEM_add_pc:
10089 case T_MNEM_inc_sp:
10090 case T_MNEM_dec_sp:
10091 if (fragp->fr_var == 4)
10093 /* ??? Choose between add and addw. */
10094 insn = THUMB_OP32 (opcode);
10095 insn |= (old_op & 0xf0) << 4;
10096 put_thumb32_insn (buf, insn);
10097 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10100 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10108 if (fragp->fr_var == 4)
10110 insn = THUMB_OP32 (opcode);
10111 insn |= (old_op & 0xf0) << 4;
10112 insn |= (old_op & 0xf) << 16;
10113 put_thumb32_insn (buf, insn);
10114 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10117 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10123 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
10125 fixp->fx_file = fragp->fr_file;
10126 fixp->fx_line = fragp->fr_line;
10127 fragp->fr_fix += fragp->fr_var;
10130 /* Return the size of a relaxable immediate operand instruction.
10131 SHIFT and SIZE specify the form of the allowable immediate. */
10133 relax_immediate (fragS *fragp, int size, int shift)
10139 /* ??? Should be able to do better than this. */
10140 if (fragp->fr_symbol)
10143 low = (1 << shift) - 1;
10144 mask = (1 << (shift + size)) - (1 << shift);
10145 offset = fragp->fr_offset;
10146 /* Force misaligned offsets to 32-bit variant. */
10149 if (offset & ~mask)
10154 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
10157 relax_adr (fragS *fragp, asection *sec)
10162 /* Assume worst case for symbols not known to be in the same section. */
10163 if (!S_IS_DEFINED(fragp->fr_symbol)
10164 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10167 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10168 addr = fragp->fr_address + fragp->fr_fix;
10169 addr = (addr + 4) & ~3;
10170 /* Fix the insn as the 4-byte version if the target address is not
10171 sufficiently aligned. This is prevents an infinite loop when two
10172 instructions have contradictory range/alignment requirements. */
10176 if (val < 0 || val > 1020)
10181 /* Return the size of a relaxable add/sub immediate instruction. */
10183 relax_addsub (fragS *fragp, asection *sec)
10188 buf = fragp->fr_literal + fragp->fr_fix;
10189 op = bfd_get_16(sec->owner, buf);
10190 if ((op & 0xf) == ((op >> 4) & 0xf))
10191 return relax_immediate (fragp, 8, 0);
10193 return relax_immediate (fragp, 3, 0);
10197 /* Return the size of a relaxable branch instruction. BITS is the
10198 size of the offset field in the narrow instruction. */
10201 relax_branch (fragS *fragp, asection *sec, int bits)
10207 /* Assume worst case for symbols not known to be in the same section. */
10208 if (!S_IS_DEFINED(fragp->fr_symbol)
10209 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10212 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10213 addr = fragp->fr_address + fragp->fr_fix + 4;
10216 /* Offset is a signed value *2 */
10218 if (val >= limit || val < -limit)
10224 /* Relax a machine dependent frag. This returns the amount by which
10225 the current size of the frag should change. */
10228 arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
10233 oldsize = fragp->fr_var;
10234 switch (fragp->fr_subtype)
10236 case T_MNEM_ldr_pc2:
10237 newsize = relax_adr(fragp, sec);
10239 case T_MNEM_ldr_pc:
10240 case T_MNEM_ldr_sp:
10241 case T_MNEM_str_sp:
10242 newsize = relax_immediate(fragp, 8, 2);
10246 newsize = relax_immediate(fragp, 5, 2);
10250 newsize = relax_immediate(fragp, 5, 1);
10254 newsize = relax_immediate(fragp, 5, 0);
10257 newsize = relax_adr(fragp, sec);
10263 newsize = relax_immediate(fragp, 8, 0);
10266 newsize = relax_branch(fragp, sec, 11);
10269 newsize = relax_branch(fragp, sec, 8);
10271 case T_MNEM_add_sp:
10272 case T_MNEM_add_pc:
10273 newsize = relax_immediate (fragp, 8, 2);
10275 case T_MNEM_inc_sp:
10276 case T_MNEM_dec_sp:
10277 newsize = relax_immediate (fragp, 7, 2);
10283 newsize = relax_addsub (fragp, sec);
10290 fragp->fr_var = -newsize;
10291 md_convert_frag (sec->owner, sec, fragp);
10293 return -(newsize + oldsize);
10295 fragp->fr_var = newsize;
10296 return newsize - oldsize;
10299 /* Round up a section size to the appropriate boundary. */
10302 md_section_align (segT segment ATTRIBUTE_UNUSED,
10308 /* Round all sects to multiple of 4. */
10309 return (size + 3) & ~3;
10313 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10314 of an rs_align_code fragment. */
10317 arm_handle_align (fragS * fragP)
10319 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
10320 static char const thumb_noop[2] = { 0xc0, 0x46 };
10321 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
10322 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
10324 int bytes, fix, noop_size;
10328 if (fragP->fr_type != rs_align_code)
10331 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
10332 p = fragP->fr_literal + fragP->fr_fix;
10335 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
10336 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
10338 if (fragP->tc_frag_data)
10340 if (target_big_endian)
10341 noop = thumb_bigend_noop;
10344 noop_size = sizeof (thumb_noop);
10348 if (target_big_endian)
10349 noop = arm_bigend_noop;
10352 noop_size = sizeof (arm_noop);
10355 if (bytes & (noop_size - 1))
10357 fix = bytes & (noop_size - 1);
10358 memset (p, 0, fix);
10363 while (bytes >= noop_size)
10365 memcpy (p, noop, noop_size);
10367 bytes -= noop_size;
10371 fragP->fr_fix += fix;
10372 fragP->fr_var = noop_size;
10375 /* Called from md_do_align. Used to create an alignment
10376 frag in a code section. */
10379 arm_frag_align_code (int n, int max)
10383 /* We assume that there will never be a requirement
10384 to support alignments greater than 32 bytes. */
10385 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
10386 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
10388 p = frag_var (rs_align_code,
10389 MAX_MEM_FOR_RS_ALIGN_CODE,
10391 (relax_substateT) max,
10398 /* Perform target specific initialisation of a frag. */
10401 arm_init_frag (fragS * fragP)
10403 /* Record whether this frag is in an ARM or a THUMB area. */
10404 fragP->tc_frag_data = thumb_mode;
10408 /* When we change sections we need to issue a new mapping symbol. */
10411 arm_elf_change_section (void)
10414 segment_info_type *seginfo;
10416 /* Link an unlinked unwind index table section to the .text section. */
10417 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
10418 && elf_linked_to_section (now_seg) == NULL)
10419 elf_linked_to_section (now_seg) = text_section;
10421 if (!SEG_NORMAL (now_seg))
10424 flags = bfd_get_section_flags (stdoutput, now_seg);
10426 /* We can ignore sections that only contain debug info. */
10427 if ((flags & SEC_ALLOC) == 0)
10430 seginfo = seg_info (now_seg);
10431 mapstate = seginfo->tc_segment_info_data.mapstate;
10432 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
10436 arm_elf_section_type (const char * str, size_t len)
10438 if (len == 5 && strncmp (str, "exidx", 5) == 0)
10439 return SHT_ARM_EXIDX;
10444 /* Code to deal with unwinding tables. */
10446 static void add_unwind_adjustsp (offsetT);
10448 /* Cenerate and deferred unwind frame offset. */
10451 flush_pending_unwind (void)
10455 offset = unwind.pending_offset;
10456 unwind.pending_offset = 0;
10458 add_unwind_adjustsp (offset);
10461 /* Add an opcode to this list for this function. Two-byte opcodes should
10462 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
10466 add_unwind_opcode (valueT op, int length)
10468 /* Add any deferred stack adjustment. */
10469 if (unwind.pending_offset)
10470 flush_pending_unwind ();
10472 unwind.sp_restored = 0;
10474 if (unwind.opcode_count + length > unwind.opcode_alloc)
10476 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
10477 if (unwind.opcodes)
10478 unwind.opcodes = xrealloc (unwind.opcodes,
10479 unwind.opcode_alloc);
10481 unwind.opcodes = xmalloc (unwind.opcode_alloc);
10486 unwind.opcodes[unwind.opcode_count] = op & 0xff;
10488 unwind.opcode_count++;
10492 /* Add unwind opcodes to adjust the stack pointer. */
10495 add_unwind_adjustsp (offsetT offset)
10499 if (offset > 0x200)
10501 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
10506 /* Long form: 0xb2, uleb128. */
10507 /* This might not fit in a word so add the individual bytes,
10508 remembering the list is built in reverse order. */
10509 o = (valueT) ((offset - 0x204) >> 2);
10511 add_unwind_opcode (0, 1);
10513 /* Calculate the uleb128 encoding of the offset. */
10517 bytes[n] = o & 0x7f;
10523 /* Add the insn. */
10525 add_unwind_opcode (bytes[n - 1], 1);
10526 add_unwind_opcode (0xb2, 1);
10528 else if (offset > 0x100)
10530 /* Two short opcodes. */
10531 add_unwind_opcode (0x3f, 1);
10532 op = (offset - 0x104) >> 2;
10533 add_unwind_opcode (op, 1);
10535 else if (offset > 0)
10537 /* Short opcode. */
10538 op = (offset - 4) >> 2;
10539 add_unwind_opcode (op, 1);
10541 else if (offset < 0)
10544 while (offset > 0x100)
10546 add_unwind_opcode (0x7f, 1);
10549 op = ((offset - 4) >> 2) | 0x40;
10550 add_unwind_opcode (op, 1);
10554 /* Finish the list of unwind opcodes for this function. */
10556 finish_unwind_opcodes (void)
10560 if (unwind.fp_used)
10562 /* Adjust sp as neccessary. */
10563 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
10564 flush_pending_unwind ();
10566 /* After restoring sp from the frame pointer. */
10567 op = 0x90 | unwind.fp_reg;
10568 add_unwind_opcode (op, 1);
10571 flush_pending_unwind ();
10575 /* Start an exception table entry. If idx is nonzero this is an index table
10579 start_unwind_section (const segT text_seg, int idx)
10581 const char * text_name;
10582 const char * prefix;
10583 const char * prefix_once;
10584 const char * group_name;
10588 size_t sec_name_len;
10595 prefix = ELF_STRING_ARM_unwind;
10596 prefix_once = ELF_STRING_ARM_unwind_once;
10597 type = SHT_ARM_EXIDX;
10601 prefix = ELF_STRING_ARM_unwind_info;
10602 prefix_once = ELF_STRING_ARM_unwind_info_once;
10603 type = SHT_PROGBITS;
10606 text_name = segment_name (text_seg);
10607 if (streq (text_name, ".text"))
10610 if (strncmp (text_name, ".gnu.linkonce.t.",
10611 strlen (".gnu.linkonce.t.")) == 0)
10613 prefix = prefix_once;
10614 text_name += strlen (".gnu.linkonce.t.");
10617 prefix_len = strlen (prefix);
10618 text_len = strlen (text_name);
10619 sec_name_len = prefix_len + text_len;
10620 sec_name = xmalloc (sec_name_len + 1);
10621 memcpy (sec_name, prefix, prefix_len);
10622 memcpy (sec_name + prefix_len, text_name, text_len);
10623 sec_name[prefix_len + text_len] = '\0';
10629 /* Handle COMDAT group. */
10630 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
10632 group_name = elf_group_name (text_seg);
10633 if (group_name == NULL)
10635 as_bad ("Group section `%s' has no group signature",
10636 segment_name (text_seg));
10637 ignore_rest_of_line ();
10640 flags |= SHF_GROUP;
10644 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
10646 /* Set the setion link for index tables. */
10648 elf_linked_to_section (now_seg) = text_seg;
10652 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
10653 personality routine data. Returns zero, or the index table value for
10654 and inline entry. */
10657 create_unwind_entry (int have_data)
10662 /* The current word of data. */
10664 /* The number of bytes left in this word. */
10667 finish_unwind_opcodes ();
10669 /* Remember the current text section. */
10670 unwind.saved_seg = now_seg;
10671 unwind.saved_subseg = now_subseg;
10673 start_unwind_section (now_seg, 0);
10675 if (unwind.personality_routine == NULL)
10677 if (unwind.personality_index == -2)
10680 as_bad (_("handerdata in cantunwind frame"));
10681 return 1; /* EXIDX_CANTUNWIND. */
10684 /* Use a default personality routine if none is specified. */
10685 if (unwind.personality_index == -1)
10687 if (unwind.opcode_count > 3)
10688 unwind.personality_index = 1;
10690 unwind.personality_index = 0;
10693 /* Space for the personality routine entry. */
10694 if (unwind.personality_index == 0)
10696 if (unwind.opcode_count > 3)
10697 as_bad (_("too many unwind opcodes for personality routine 0"));
10701 /* All the data is inline in the index table. */
10704 while (unwind.opcode_count > 0)
10706 unwind.opcode_count--;
10707 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
10711 /* Pad with "finish" opcodes. */
10713 data = (data << 8) | 0xb0;
10720 /* We get two opcodes "free" in the first word. */
10721 size = unwind.opcode_count - 2;
10724 /* An extra byte is required for the opcode count. */
10725 size = unwind.opcode_count + 1;
10727 size = (size + 3) >> 2;
10729 as_bad (_("too many unwind opcodes"));
10731 frag_align (2, 0, 0);
10732 record_alignment (now_seg, 2);
10733 unwind.table_entry = expr_build_dot ();
10735 /* Allocate the table entry. */
10736 ptr = frag_more ((size << 2) + 4);
10737 where = frag_now_fix () - ((size << 2) + 4);
10739 switch (unwind.personality_index)
10742 /* ??? Should this be a PLT generating relocation? */
10743 /* Custom personality routine. */
10744 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
10745 BFD_RELOC_ARM_PREL31);
10750 /* Set the first byte to the number of additional words. */
10755 /* ABI defined personality routines. */
10757 /* Three opcodes bytes are packed into the first word. */
10764 /* The size and first two opcode bytes go in the first word. */
10765 data = ((0x80 + unwind.personality_index) << 8) | size;
10770 /* Should never happen. */
10774 /* Pack the opcodes into words (MSB first), reversing the list at the same
10776 while (unwind.opcode_count > 0)
10780 md_number_to_chars (ptr, data, 4);
10785 unwind.opcode_count--;
10787 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
10790 /* Finish off the last word. */
10793 /* Pad with "finish" opcodes. */
10795 data = (data << 8) | 0xb0;
10797 md_number_to_chars (ptr, data, 4);
10802 /* Add an empty descriptor if there is no user-specified data. */
10803 ptr = frag_more (4);
10804 md_number_to_chars (ptr, 0, 4);
10810 /* Convert REGNAME to a DWARF-2 register number. */
10813 tc_arm_regname_to_dw2regnum (const char *regname)
10815 int reg = arm_reg_parse ((char **) ®name, REG_TYPE_RN);
10823 /* Initialize the DWARF-2 unwind information for this procedure. */
10826 tc_arm_frame_initial_instructions (void)
10828 cfi_add_CFA_def_cfa (REG_SP, 0);
10830 #endif /* OBJ_ELF */
10833 /* MD interface: Symbol and relocation handling. */
10835 /* Return the address within the segment that a PC-relative fixup is
10836 relative to. For ARM, PC-relative fixups applied to instructions
10837 are generally relative to the location of the fixup plus 8 bytes.
10838 Thumb branches are offset by 4, and Thumb loads relative to PC
10839 require special handling. */
10842 md_pcrel_from_section (fixS * fixP, segT seg)
10844 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
10846 /* If this is pc-relative and we are going to emit a relocation
10847 then we just want to put out any pipeline compensation that the linker
10848 will need. Otherwise we want to use the calculated base. */
10850 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
10851 || arm_force_relocation (fixP)))
10854 switch (fixP->fx_r_type)
10856 /* PC relative addressing on the Thumb is slightly odd as the
10857 bottom two bits of the PC are forced to zero for the
10858 calculation. This happens *after* application of the
10859 pipeline offset. However, Thumb adrl already adjusts for
10860 this, so we need not do it again. */
10861 case BFD_RELOC_ARM_THUMB_ADD:
10864 case BFD_RELOC_ARM_THUMB_OFFSET:
10865 case BFD_RELOC_ARM_T32_OFFSET_IMM:
10866 case BFD_RELOC_ARM_T32_ADD_PC12:
10867 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
10868 return (base + 4) & ~3;
10870 /* Thumb branches are simply offset by +4. */
10871 case BFD_RELOC_THUMB_PCREL_BRANCH7:
10872 case BFD_RELOC_THUMB_PCREL_BRANCH9:
10873 case BFD_RELOC_THUMB_PCREL_BRANCH12:
10874 case BFD_RELOC_THUMB_PCREL_BRANCH20:
10875 case BFD_RELOC_THUMB_PCREL_BRANCH23:
10876 case BFD_RELOC_THUMB_PCREL_BRANCH25:
10877 case BFD_RELOC_THUMB_PCREL_BLX:
10880 /* ARM mode branches are offset by +8. However, the Windows CE
10881 loader expects the relocation not to take this into account. */
10882 case BFD_RELOC_ARM_PCREL_BRANCH:
10883 case BFD_RELOC_ARM_PCREL_CALL:
10884 case BFD_RELOC_ARM_PCREL_JUMP:
10885 case BFD_RELOC_ARM_PCREL_BLX:
10886 case BFD_RELOC_ARM_PLT32:
10893 /* ARM mode loads relative to PC are also offset by +8. Unlike
10894 branches, the Windows CE loader *does* expect the relocation
10895 to take this into account. */
10896 case BFD_RELOC_ARM_OFFSET_IMM:
10897 case BFD_RELOC_ARM_OFFSET_IMM8:
10898 case BFD_RELOC_ARM_HWLITERAL:
10899 case BFD_RELOC_ARM_LITERAL:
10900 case BFD_RELOC_ARM_CP_OFF_IMM:
10904 /* Other PC-relative relocations are un-offset. */
10910 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
10911 Otherwise we have no need to default values of symbols. */
10914 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
10917 if (name[0] == '_' && name[1] == 'G'
10918 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
10922 if (symbol_find (name))
10923 as_bad ("GOT already in the symbol table");
10925 GOT_symbol = symbol_new (name, undefined_section,
10926 (valueT) 0, & zero_address_frag);
10936 /* Subroutine of md_apply_fix. Check to see if an immediate can be
10937 computed as two separate immediate values, added together. We
10938 already know that this value cannot be computed by just one ARM
10941 static unsigned int
10942 validate_immediate_twopart (unsigned int val,
10943 unsigned int * highpart)
10948 for (i = 0; i < 32; i += 2)
10949 if (((a = rotate_left (val, i)) & 0xff) != 0)
10955 * highpart = (a >> 8) | ((i + 24) << 7);
10957 else if (a & 0xff0000)
10959 if (a & 0xff000000)
10961 * highpart = (a >> 16) | ((i + 16) << 7);
10965 assert (a & 0xff000000);
10966 * highpart = (a >> 24) | ((i + 8) << 7);
10969 return (a & 0xff) | (i << 7);
10976 validate_offset_imm (unsigned int val, int hwse)
10978 if ((hwse && val > 255) || val > 4095)
10983 /* Subroutine of md_apply_fix. Do those data_ops which can take a
10984 negative immediate constant by altering the instruction. A bit of
10989 by inverting the second operand, and
10992 by negating the second operand. */
10995 negate_data_op (unsigned long * instruction,
10996 unsigned long value)
10999 unsigned long negated, inverted;
11001 negated = encode_arm_immediate (-value);
11002 inverted = encode_arm_immediate (~value);
11004 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
11007 /* First negates. */
11008 case OPCODE_SUB: /* ADD <-> SUB */
11009 new_inst = OPCODE_ADD;
11014 new_inst = OPCODE_SUB;
11018 case OPCODE_CMP: /* CMP <-> CMN */
11019 new_inst = OPCODE_CMN;
11024 new_inst = OPCODE_CMP;
11028 /* Now Inverted ops. */
11029 case OPCODE_MOV: /* MOV <-> MVN */
11030 new_inst = OPCODE_MVN;
11035 new_inst = OPCODE_MOV;
11039 case OPCODE_AND: /* AND <-> BIC */
11040 new_inst = OPCODE_BIC;
11045 new_inst = OPCODE_AND;
11049 case OPCODE_ADC: /* ADC <-> SBC */
11050 new_inst = OPCODE_SBC;
11055 new_inst = OPCODE_ADC;
11059 /* We cannot do anything. */
11064 if (value == (unsigned) FAIL)
11067 *instruction &= OPCODE_MASK;
11068 *instruction |= new_inst << DATA_OP_SHIFT;
11072 /* Read a 32-bit thumb instruction from buf. */
11073 static unsigned long
11074 get_thumb32_insn (char * buf)
11076 unsigned long insn;
11077 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
11078 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11084 md_apply_fix (fixS * fixP,
11088 offsetT value = * valP;
11090 unsigned int newimm;
11091 unsigned long temp;
11093 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
11095 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
11097 /* Note whether this will delete the relocation. */
11098 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
11101 /* On a 64-bit host, silently truncate 'value' to 32 bits for
11102 consistency with the behavior on 32-bit hosts. Remember value
11104 value &= 0xffffffff;
11105 value ^= 0x80000000;
11106 value -= 0x80000000;
11109 fixP->fx_addnumber = value;
11111 /* Same treatment for fixP->fx_offset. */
11112 fixP->fx_offset &= 0xffffffff;
11113 fixP->fx_offset ^= 0x80000000;
11114 fixP->fx_offset -= 0x80000000;
11116 switch (fixP->fx_r_type)
11118 case BFD_RELOC_NONE:
11119 /* This will need to go in the object file. */
11123 case BFD_RELOC_ARM_IMMEDIATE:
11124 /* We claim that this fixup has been processed here,
11125 even if in fact we generate an error because we do
11126 not have a reloc for it, so tc_gen_reloc will reject it. */
11130 && ! S_IS_DEFINED (fixP->fx_addsy))
11132 as_bad_where (fixP->fx_file, fixP->fx_line,
11133 _("undefined symbol %s used as an immediate value"),
11134 S_GET_NAME (fixP->fx_addsy));
11138 newimm = encode_arm_immediate (value);
11139 temp = md_chars_to_number (buf, INSN_SIZE);
11141 /* If the instruction will fail, see if we can fix things up by
11142 changing the opcode. */
11143 if (newimm == (unsigned int) FAIL
11144 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
11146 as_bad_where (fixP->fx_file, fixP->fx_line,
11147 _("invalid constant (%lx) after fixup"),
11148 (unsigned long) value);
11152 newimm |= (temp & 0xfffff000);
11153 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
11156 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
11158 unsigned int highpart = 0;
11159 unsigned int newinsn = 0xe1a00000; /* nop. */
11161 newimm = encode_arm_immediate (value);
11162 temp = md_chars_to_number (buf, INSN_SIZE);
11164 /* If the instruction will fail, see if we can fix things up by
11165 changing the opcode. */
11166 if (newimm == (unsigned int) FAIL
11167 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
11169 /* No ? OK - try using two ADD instructions to generate
11171 newimm = validate_immediate_twopart (value, & highpart);
11173 /* Yes - then make sure that the second instruction is
11175 if (newimm != (unsigned int) FAIL)
11177 /* Still No ? Try using a negated value. */
11178 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
11179 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
11180 /* Otherwise - give up. */
11183 as_bad_where (fixP->fx_file, fixP->fx_line,
11184 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
11189 /* Replace the first operand in the 2nd instruction (which
11190 is the PC) with the destination register. We have
11191 already added in the PC in the first instruction and we
11192 do not want to do it again. */
11193 newinsn &= ~ 0xf0000;
11194 newinsn |= ((newinsn & 0x0f000) << 4);
11197 newimm |= (temp & 0xfffff000);
11198 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
11200 highpart |= (newinsn & 0xfffff000);
11201 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
11205 case BFD_RELOC_ARM_OFFSET_IMM:
11206 case BFD_RELOC_ARM_LITERAL:
11212 if (validate_offset_imm (value, 0) == FAIL)
11214 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
11215 as_bad_where (fixP->fx_file, fixP->fx_line,
11216 _("invalid literal constant: pool needs to be closer"));
11218 as_bad_where (fixP->fx_file, fixP->fx_line,
11219 _("bad immediate value for offset (%ld)"),
11224 newval = md_chars_to_number (buf, INSN_SIZE);
11225 newval &= 0xff7ff000;
11226 newval |= value | (sign ? INDEX_UP : 0);
11227 md_number_to_chars (buf, newval, INSN_SIZE);
11230 case BFD_RELOC_ARM_OFFSET_IMM8:
11231 case BFD_RELOC_ARM_HWLITERAL:
11237 if (validate_offset_imm (value, 1) == FAIL)
11239 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
11240 as_bad_where (fixP->fx_file, fixP->fx_line,
11241 _("invalid literal constant: pool needs to be closer"));
11243 as_bad (_("bad immediate value for half-word offset (%ld)"),
11248 newval = md_chars_to_number (buf, INSN_SIZE);
11249 newval &= 0xff7ff0f0;
11250 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
11251 md_number_to_chars (buf, newval, INSN_SIZE);
11254 case BFD_RELOC_ARM_T32_OFFSET_U8:
11255 if (value < 0 || value > 1020 || value % 4 != 0)
11256 as_bad_where (fixP->fx_file, fixP->fx_line,
11257 _("bad immediate value for offset (%ld)"), (long) value);
11260 newval = md_chars_to_number (buf+2, THUMB_SIZE);
11262 md_number_to_chars (buf+2, newval, THUMB_SIZE);
11265 case BFD_RELOC_ARM_T32_OFFSET_IMM:
11266 /* This is a complicated relocation used for all varieties of Thumb32
11267 load/store instruction with immediate offset:
11269 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
11270 *4, optional writeback(W)
11271 (doubleword load/store)
11273 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
11274 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
11275 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
11276 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
11277 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
11279 Uppercase letters indicate bits that are already encoded at
11280 this point. Lowercase letters are our problem. For the
11281 second block of instructions, the secondary opcode nybble
11282 (bits 8..11) is present, and bit 23 is zero, even if this is
11283 a PC-relative operation. */
11284 newval = md_chars_to_number (buf, THUMB_SIZE);
11286 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
11288 if ((newval & 0xf0000000) == 0xe0000000)
11290 /* Doubleword load/store: 8-bit offset, scaled by 4. */
11292 newval |= (1 << 23);
11295 if (value % 4 != 0)
11297 as_bad_where (fixP->fx_file, fixP->fx_line,
11298 _("offset not a multiple of 4"));
11304 as_bad_where (fixP->fx_file, fixP->fx_line,
11305 _("offset out of range"));
11310 else if ((newval & 0x000f0000) == 0x000f0000)
11312 /* PC-relative, 12-bit offset. */
11314 newval |= (1 << 23);
11317 if (value >= 0xfff)
11319 as_bad_where (fixP->fx_file, fixP->fx_line,
11320 _("offset out of range"));
11325 else if ((newval & 0x00000100) == 0x00000100)
11327 /* Writeback: 8-bit, +/- offset. */
11329 newval |= (1 << 9);
11334 as_bad_where (fixP->fx_file, fixP->fx_line,
11335 _("offset out of range"));
11340 else if ((newval & 0x00000f00) == 0x00000e00)
11342 /* T-instruction: positive 8-bit offset. */
11343 if (value < 0 || value >= 0xff)
11345 as_bad_where (fixP->fx_file, fixP->fx_line,
11346 _("offset out of range"));
11354 /* Positive 12-bit or negative 8-bit offset. */
11358 newval |= (1 << 23);
11368 as_bad_where (fixP->fx_file, fixP->fx_line,
11369 _("offset out of range"));
11376 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
11377 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
11380 case BFD_RELOC_ARM_SHIFT_IMM:
11381 newval = md_chars_to_number (buf, INSN_SIZE);
11382 if (((unsigned long) value) > 32
11384 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
11386 as_bad_where (fixP->fx_file, fixP->fx_line,
11387 _("shift expression is too large"));
11392 /* Shifts of zero must be done as lsl. */
11394 else if (value == 32)
11396 newval &= 0xfffff07f;
11397 newval |= (value & 0x1f) << 7;
11398 md_number_to_chars (buf, newval, INSN_SIZE);
11401 case BFD_RELOC_ARM_T32_IMMEDIATE:
11402 case BFD_RELOC_ARM_T32_IMM12:
11403 case BFD_RELOC_ARM_T32_ADD_PC12:
11404 /* We claim that this fixup has been processed here,
11405 even if in fact we generate an error because we do
11406 not have a reloc for it, so tc_gen_reloc will reject it. */
11410 && ! S_IS_DEFINED (fixP->fx_addsy))
11412 as_bad_where (fixP->fx_file, fixP->fx_line,
11413 _("undefined symbol %s used as an immediate value"),
11414 S_GET_NAME (fixP->fx_addsy));
11418 newval = md_chars_to_number (buf, THUMB_SIZE);
11420 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
11422 /* FUTURE: Implement analogue of negate_data_op for T32. */
11423 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
11424 newimm = encode_thumb32_immediate (value);
11427 /* 12 bit immediate for addw/subw. */
11431 newval ^= 0x00a00000;
11434 newimm = (unsigned int) FAIL;
11439 if (newimm == (unsigned int)FAIL)
11441 as_bad_where (fixP->fx_file, fixP->fx_line,
11442 _("invalid constant (%lx) after fixup"),
11443 (unsigned long) value);
11447 newval |= (newimm & 0x800) << 15;
11448 newval |= (newimm & 0x700) << 4;
11449 newval |= (newimm & 0x0ff);
11451 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
11452 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
11455 case BFD_RELOC_ARM_SMC:
11456 if (((unsigned long) value) > 0xffff)
11457 as_bad_where (fixP->fx_file, fixP->fx_line,
11458 _("invalid smc expression"));
11459 newval = md_chars_to_number (buf, INSN_SIZE);
11460 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
11461 md_number_to_chars (buf, newval, INSN_SIZE);
11464 case BFD_RELOC_ARM_SWI:
11465 if (fixP->tc_fix_data != 0)
11467 if (((unsigned long) value) > 0xff)
11468 as_bad_where (fixP->fx_file, fixP->fx_line,
11469 _("invalid swi expression"));
11470 newval = md_chars_to_number (buf, THUMB_SIZE);
11472 md_number_to_chars (buf, newval, THUMB_SIZE);
11476 if (((unsigned long) value) > 0x00ffffff)
11477 as_bad_where (fixP->fx_file, fixP->fx_line,
11478 _("invalid swi expression"));
11479 newval = md_chars_to_number (buf, INSN_SIZE);
11481 md_number_to_chars (buf, newval, INSN_SIZE);
11485 case BFD_RELOC_ARM_MULTI:
11486 if (((unsigned long) value) > 0xffff)
11487 as_bad_where (fixP->fx_file, fixP->fx_line,
11488 _("invalid expression in load/store multiple"));
11489 newval = value | md_chars_to_number (buf, INSN_SIZE);
11490 md_number_to_chars (buf, newval, INSN_SIZE);
11494 case BFD_RELOC_ARM_PCREL_CALL:
11495 newval = md_chars_to_number (buf, INSN_SIZE);
11496 if ((newval & 0xf0000000) == 0xf0000000)
11500 goto arm_branch_common;
11502 case BFD_RELOC_ARM_PCREL_JUMP:
11503 case BFD_RELOC_ARM_PLT32:
11505 case BFD_RELOC_ARM_PCREL_BRANCH:
11507 goto arm_branch_common;
11509 case BFD_RELOC_ARM_PCREL_BLX:
11512 /* We are going to store value (shifted right by two) in the
11513 instruction, in a 24 bit, signed field. Bits 26 through 32 either
11514 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
11515 also be be clear. */
11517 as_bad_where (fixP->fx_file, fixP->fx_line,
11518 _("misaligned branch destination"));
11519 if ((value & (offsetT)0xfe000000) != (offsetT)0
11520 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
11521 as_bad_where (fixP->fx_file, fixP->fx_line,
11522 _("branch out of range"));
11524 if (fixP->fx_done || !seg->use_rela_p)
11526 newval = md_chars_to_number (buf, INSN_SIZE);
11527 newval |= (value >> 2) & 0x00ffffff;
11528 md_number_to_chars (buf, newval, INSN_SIZE);
11532 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
11533 /* CZB can only branch forward. */
11535 as_bad_where (fixP->fx_file, fixP->fx_line,
11536 _("branch out of range"));
11538 if (fixP->fx_done || !seg->use_rela_p)
11540 newval = md_chars_to_number (buf, THUMB_SIZE);
11541 newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3);
11542 md_number_to_chars (buf, newval, THUMB_SIZE);
11546 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
11547 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
11548 as_bad_where (fixP->fx_file, fixP->fx_line,
11549 _("branch out of range"));
11551 if (fixP->fx_done || !seg->use_rela_p)
11553 newval = md_chars_to_number (buf, THUMB_SIZE);
11554 newval |= (value & 0x1ff) >> 1;
11555 md_number_to_chars (buf, newval, THUMB_SIZE);
11559 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
11560 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
11561 as_bad_where (fixP->fx_file, fixP->fx_line,
11562 _("branch out of range"));
11564 if (fixP->fx_done || !seg->use_rela_p)
11566 newval = md_chars_to_number (buf, THUMB_SIZE);
11567 newval |= (value & 0xfff) >> 1;
11568 md_number_to_chars (buf, newval, THUMB_SIZE);
11572 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11573 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
11574 as_bad_where (fixP->fx_file, fixP->fx_line,
11575 _("conditional branch out of range"));
11577 if (fixP->fx_done || !seg->use_rela_p)
11580 addressT S, J1, J2, lo, hi;
11582 S = (value & 0x00100000) >> 20;
11583 J2 = (value & 0x00080000) >> 19;
11584 J1 = (value & 0x00040000) >> 18;
11585 hi = (value & 0x0003f000) >> 12;
11586 lo = (value & 0x00000ffe) >> 1;
11588 newval = md_chars_to_number (buf, THUMB_SIZE);
11589 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11590 newval |= (S << 10) | hi;
11591 newval2 |= (J1 << 13) | (J2 << 11) | lo;
11592 md_number_to_chars (buf, newval, THUMB_SIZE);
11593 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11597 case BFD_RELOC_THUMB_PCREL_BLX:
11598 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11599 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
11600 as_bad_where (fixP->fx_file, fixP->fx_line,
11601 _("branch out of range"));
11603 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
11604 /* For a BLX instruction, make sure that the relocation is rounded up
11605 to a word boundary. This follows the semantics of the instruction
11606 which specifies that bit 1 of the target address will come from bit
11607 1 of the base address. */
11608 value = (value + 1) & ~ 1;
11610 if (fixP->fx_done || !seg->use_rela_p)
11614 newval = md_chars_to_number (buf, THUMB_SIZE);
11615 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11616 newval |= (value & 0x7fffff) >> 12;
11617 newval2 |= (value & 0xfff) >> 1;
11618 md_number_to_chars (buf, newval, THUMB_SIZE);
11619 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11623 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11624 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
11625 as_bad_where (fixP->fx_file, fixP->fx_line,
11626 _("branch out of range"));
11628 if (fixP->fx_done || !seg->use_rela_p)
11631 addressT S, I1, I2, lo, hi;
11633 S = (value & 0x01000000) >> 24;
11634 I1 = (value & 0x00800000) >> 23;
11635 I2 = (value & 0x00400000) >> 22;
11636 hi = (value & 0x003ff000) >> 12;
11637 lo = (value & 0x00000ffe) >> 1;
11642 newval = md_chars_to_number (buf, THUMB_SIZE);
11643 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11644 newval |= (S << 10) | hi;
11645 newval2 |= (I1 << 13) | (I2 << 11) | lo;
11646 md_number_to_chars (buf, newval, THUMB_SIZE);
11647 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11652 if (fixP->fx_done || !seg->use_rela_p)
11653 md_number_to_chars (buf, value, 1);
11657 if (fixP->fx_done || !seg->use_rela_p)
11658 md_number_to_chars (buf, value, 2);
11662 case BFD_RELOC_ARM_TLS_GD32:
11663 case BFD_RELOC_ARM_TLS_LE32:
11664 case BFD_RELOC_ARM_TLS_IE32:
11665 case BFD_RELOC_ARM_TLS_LDM32:
11666 case BFD_RELOC_ARM_TLS_LDO32:
11667 S_SET_THREAD_LOCAL (fixP->fx_addsy);
11670 case BFD_RELOC_ARM_GOT32:
11671 case BFD_RELOC_ARM_GOTOFF:
11672 case BFD_RELOC_ARM_TARGET2:
11673 if (fixP->fx_done || !seg->use_rela_p)
11674 md_number_to_chars (buf, 0, 4);
11678 case BFD_RELOC_RVA:
11680 case BFD_RELOC_ARM_TARGET1:
11681 case BFD_RELOC_ARM_ROSEGREL32:
11682 case BFD_RELOC_ARM_SBREL32:
11683 case BFD_RELOC_32_PCREL:
11684 if (fixP->fx_done || !seg->use_rela_p)
11685 md_number_to_chars (buf, value, 4);
11689 case BFD_RELOC_ARM_PREL31:
11690 if (fixP->fx_done || !seg->use_rela_p)
11692 newval = md_chars_to_number (buf, 4) & 0x80000000;
11693 if ((value ^ (value >> 1)) & 0x40000000)
11695 as_bad_where (fixP->fx_file, fixP->fx_line,
11696 _("rel31 relocation overflow"));
11698 newval |= value & 0x7fffffff;
11699 md_number_to_chars (buf, newval, 4);
11704 case BFD_RELOC_ARM_CP_OFF_IMM:
11705 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
11706 if (value < -1023 || value > 1023 || (value & 3))
11707 as_bad_where (fixP->fx_file, fixP->fx_line,
11708 _("co-processor offset out of range"));
11713 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
11714 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
11715 newval = md_chars_to_number (buf, INSN_SIZE);
11717 newval = get_thumb32_insn (buf);
11718 newval &= 0xff7fff00;
11719 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
11721 newval &= ~WRITE_BACK;
11722 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
11723 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
11724 md_number_to_chars (buf, newval, INSN_SIZE);
11726 put_thumb32_insn (buf, newval);
11729 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
11730 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
11731 if (value < -255 || value > 255)
11732 as_bad_where (fixP->fx_file, fixP->fx_line,
11733 _("co-processor offset out of range"));
11734 goto cp_off_common;
11736 case BFD_RELOC_ARM_THUMB_OFFSET:
11737 newval = md_chars_to_number (buf, THUMB_SIZE);
11738 /* Exactly what ranges, and where the offset is inserted depends
11739 on the type of instruction, we can establish this from the
11741 switch (newval >> 12)
11743 case 4: /* PC load. */
11744 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
11745 forced to zero for these loads; md_pcrel_from has already
11746 compensated for this. */
11748 as_bad_where (fixP->fx_file, fixP->fx_line,
11749 _("invalid offset, target not word aligned (0x%08lX)"),
11750 (((unsigned int) fixP->fx_frag->fr_address
11751 + (unsigned int) fixP->fx_where) & ~3) + value);
11753 if (value & ~0x3fc)
11754 as_bad_where (fixP->fx_file, fixP->fx_line,
11755 _("invalid offset, value too big (0x%08lX)"),
11758 newval |= value >> 2;
11761 case 9: /* SP load/store. */
11762 if (value & ~0x3fc)
11763 as_bad_where (fixP->fx_file, fixP->fx_line,
11764 _("invalid offset, value too big (0x%08lX)"),
11766 newval |= value >> 2;
11769 case 6: /* Word load/store. */
11771 as_bad_where (fixP->fx_file, fixP->fx_line,
11772 _("invalid offset, value too big (0x%08lX)"),
11774 newval |= value << 4; /* 6 - 2. */
11777 case 7: /* Byte load/store. */
11779 as_bad_where (fixP->fx_file, fixP->fx_line,
11780 _("invalid offset, value too big (0x%08lX)"),
11782 newval |= value << 6;
11785 case 8: /* Halfword load/store. */
11787 as_bad_where (fixP->fx_file, fixP->fx_line,
11788 _("invalid offset, value too big (0x%08lX)"),
11790 newval |= value << 5; /* 6 - 1. */
11794 as_bad_where (fixP->fx_file, fixP->fx_line,
11795 "Unable to process relocation for thumb opcode: %lx",
11796 (unsigned long) newval);
11799 md_number_to_chars (buf, newval, THUMB_SIZE);
11802 case BFD_RELOC_ARM_THUMB_ADD:
11803 /* This is a complicated relocation, since we use it for all of
11804 the following immediate relocations:
11808 9bit ADD/SUB SP word-aligned
11809 10bit ADD PC/SP word-aligned
11811 The type of instruction being processed is encoded in the
11818 newval = md_chars_to_number (buf, THUMB_SIZE);
11820 int rd = (newval >> 4) & 0xf;
11821 int rs = newval & 0xf;
11822 int subtract = !!(newval & 0x8000);
11824 /* Check for HI regs, only very restricted cases allowed:
11825 Adjusting SP, and using PC or SP to get an address. */
11826 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
11827 || (rs > 7 && rs != REG_SP && rs != REG_PC))
11828 as_bad_where (fixP->fx_file, fixP->fx_line,
11829 _("invalid Hi register with immediate"));
11831 /* If value is negative, choose the opposite instruction. */
11835 subtract = !subtract;
11837 as_bad_where (fixP->fx_file, fixP->fx_line,
11838 _("immediate value out of range"));
11843 if (value & ~0x1fc)
11844 as_bad_where (fixP->fx_file, fixP->fx_line,
11845 _("invalid immediate for stack address calculation"));
11846 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
11847 newval |= value >> 2;
11849 else if (rs == REG_PC || rs == REG_SP)
11851 if (subtract || value & ~0x3fc)
11852 as_bad_where (fixP->fx_file, fixP->fx_line,
11853 _("invalid immediate for address calculation (value = 0x%08lX)"),
11854 (unsigned long) value);
11855 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
11857 newval |= value >> 2;
11862 as_bad_where (fixP->fx_file, fixP->fx_line,
11863 _("immediate value out of range"));
11864 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
11865 newval |= (rd << 8) | value;
11870 as_bad_where (fixP->fx_file, fixP->fx_line,
11871 _("immediate value out of range"));
11872 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
11873 newval |= rd | (rs << 3) | (value << 6);
11876 md_number_to_chars (buf, newval, THUMB_SIZE);
11879 case BFD_RELOC_ARM_THUMB_IMM:
11880 newval = md_chars_to_number (buf, THUMB_SIZE);
11881 if (value < 0 || value > 255)
11882 as_bad_where (fixP->fx_file, fixP->fx_line,
11883 _("invalid immediate: %ld is too large"),
11886 md_number_to_chars (buf, newval, THUMB_SIZE);
11889 case BFD_RELOC_ARM_THUMB_SHIFT:
11890 /* 5bit shift value (0..32). LSL cannot take 32. */
11891 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
11892 temp = newval & 0xf800;
11893 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
11894 as_bad_where (fixP->fx_file, fixP->fx_line,
11895 _("invalid shift value: %ld"), (long) value);
11896 /* Shifts of zero must be encoded as LSL. */
11898 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
11899 /* Shifts of 32 are encoded as zero. */
11900 else if (value == 32)
11902 newval |= value << 6;
11903 md_number_to_chars (buf, newval, THUMB_SIZE);
11906 case BFD_RELOC_VTABLE_INHERIT:
11907 case BFD_RELOC_VTABLE_ENTRY:
11911 case BFD_RELOC_UNUSED:
11913 as_bad_where (fixP->fx_file, fixP->fx_line,
11914 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
11918 /* Translate internal representation of relocation info to BFD target
11922 tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
11926 bfd_reloc_code_real_type code;
11928 reloc = xmalloc (sizeof (arelent));
11930 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
11931 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11932 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
11934 if (fixp->fx_pcrel)
11935 fixp->fx_offset = reloc->address;
11936 reloc->addend = fixp->fx_offset;
11938 switch (fixp->fx_r_type)
11941 if (fixp->fx_pcrel)
11943 code = BFD_RELOC_8_PCREL;
11948 if (fixp->fx_pcrel)
11950 code = BFD_RELOC_16_PCREL;
11955 if (fixp->fx_pcrel)
11957 code = BFD_RELOC_32_PCREL;
11961 case BFD_RELOC_NONE:
11962 case BFD_RELOC_ARM_PCREL_BRANCH:
11963 case BFD_RELOC_ARM_PCREL_BLX:
11964 case BFD_RELOC_RVA:
11965 case BFD_RELOC_THUMB_PCREL_BRANCH7:
11966 case BFD_RELOC_THUMB_PCREL_BRANCH9:
11967 case BFD_RELOC_THUMB_PCREL_BRANCH12:
11968 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11969 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11970 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11971 case BFD_RELOC_THUMB_PCREL_BLX:
11972 case BFD_RELOC_VTABLE_ENTRY:
11973 case BFD_RELOC_VTABLE_INHERIT:
11974 code = fixp->fx_r_type;
11977 case BFD_RELOC_ARM_LITERAL:
11978 case BFD_RELOC_ARM_HWLITERAL:
11979 /* If this is called then the a literal has
11980 been referenced across a section boundary. */
11981 as_bad_where (fixp->fx_file, fixp->fx_line,
11982 _("literal referenced across section boundary"));
11986 case BFD_RELOC_ARM_GOT32:
11987 case BFD_RELOC_ARM_GOTOFF:
11988 case BFD_RELOC_ARM_PLT32:
11989 case BFD_RELOC_ARM_TARGET1:
11990 case BFD_RELOC_ARM_ROSEGREL32:
11991 case BFD_RELOC_ARM_SBREL32:
11992 case BFD_RELOC_ARM_PREL31:
11993 case BFD_RELOC_ARM_TARGET2:
11994 case BFD_RELOC_ARM_TLS_LE32:
11995 case BFD_RELOC_ARM_TLS_LDO32:
11996 case BFD_RELOC_ARM_PCREL_CALL:
11997 case BFD_RELOC_ARM_PCREL_JUMP:
11998 code = fixp->fx_r_type;
12001 case BFD_RELOC_ARM_TLS_GD32:
12002 case BFD_RELOC_ARM_TLS_IE32:
12003 case BFD_RELOC_ARM_TLS_LDM32:
12004 /* BFD will include the symbol's address in the addend.
12005 But we don't want that, so subtract it out again here. */
12006 if (!S_IS_COMMON (fixp->fx_addsy))
12007 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
12008 code = fixp->fx_r_type;
12012 case BFD_RELOC_ARM_IMMEDIATE:
12013 as_bad_where (fixp->fx_file, fixp->fx_line,
12014 _("internal relocation (type: IMMEDIATE) not fixed up"));
12017 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
12018 as_bad_where (fixp->fx_file, fixp->fx_line,
12019 _("ADRL used for a symbol not defined in the same file"));
12022 case BFD_RELOC_ARM_OFFSET_IMM:
12023 if (fixp->fx_addsy != NULL
12024 && !S_IS_DEFINED (fixp->fx_addsy)
12025 && S_IS_LOCAL (fixp->fx_addsy))
12027 as_bad_where (fixp->fx_file, fixp->fx_line,
12028 _("undefined local label `%s'"),
12029 S_GET_NAME (fixp->fx_addsy));
12033 as_bad_where (fixp->fx_file, fixp->fx_line,
12034 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
12041 switch (fixp->fx_r_type)
12043 case BFD_RELOC_NONE: type = "NONE"; break;
12044 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
12045 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
12046 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
12047 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
12048 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
12049 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
12050 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
12051 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
12052 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
12053 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
12054 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
12055 default: type = _("<unknown>"); break;
12057 as_bad_where (fixp->fx_file, fixp->fx_line,
12058 _("cannot represent %s relocation in this object file format"),
12065 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
12067 && fixp->fx_addsy == GOT_symbol)
12069 code = BFD_RELOC_ARM_GOTPC;
12070 reloc->addend = fixp->fx_offset = reloc->address;
12074 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12076 if (reloc->howto == NULL)
12078 as_bad_where (fixp->fx_file, fixp->fx_line,
12079 _("cannot represent %s relocation in this object file format"),
12080 bfd_get_reloc_code_name (code));
12084 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
12085 vtable entry to be used in the relocation's section offset. */
12086 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12087 reloc->address = fixp->fx_offset;
12092 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
12095 cons_fix_new_arm (fragS * frag,
12100 bfd_reloc_code_real_type type;
12104 FIXME: @@ Should look at CPU word size. */
12108 type = BFD_RELOC_8;
12111 type = BFD_RELOC_16;
12115 type = BFD_RELOC_32;
12118 type = BFD_RELOC_64;
12122 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
12125 #if defined OBJ_COFF || defined OBJ_ELF
12127 arm_validate_fix (fixS * fixP)
12129 /* If the destination of the branch is a defined symbol which does not have
12130 the THUMB_FUNC attribute, then we must be calling a function which has
12131 the (interfacearm) attribute. We look for the Thumb entry point to that
12132 function and change the branch to refer to that function instead. */
12133 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
12134 && fixP->fx_addsy != NULL
12135 && S_IS_DEFINED (fixP->fx_addsy)
12136 && ! THUMB_IS_FUNC (fixP->fx_addsy))
12138 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
12144 arm_force_relocation (struct fix * fixp)
12146 #if defined (OBJ_COFF) && defined (TE_PE)
12147 if (fixp->fx_r_type == BFD_RELOC_RVA)
12151 /* Resolve these relocations even if the symbol is extern or weak. */
12152 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
12153 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
12154 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
12155 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
12156 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
12157 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
12160 return generic_force_reloc (fixp);
12164 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
12165 local labels from being added to the output symbol table when they
12166 are used with the ADRL pseudo op. The ADRL relocation should always
12167 be resolved before the binbary is emitted, so it is safe to say that
12168 it is adjustable. */
12171 arm_fix_adjustable (fixS * fixP)
12173 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
12180 /* Relocations against Thumb function names must be left unadjusted,
12181 so that the linker can use this information to correctly set the
12182 bottom bit of their addresses. The MIPS version of this function
12183 also prevents relocations that are mips-16 specific, but I do not
12184 know why it does this.
12187 There is one other problem that ought to be addressed here, but
12188 which currently is not: Taking the address of a label (rather
12189 than a function) and then later jumping to that address. Such
12190 addresses also ought to have their bottom bit set (assuming that
12191 they reside in Thumb code), but at the moment they will not. */
12194 arm_fix_adjustable (fixS * fixP)
12196 if (fixP->fx_addsy == NULL)
12199 if (THUMB_IS_FUNC (fixP->fx_addsy)
12200 && fixP->fx_subsy == NULL)
12203 /* We need the symbol name for the VTABLE entries. */
12204 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12205 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12208 /* Don't allow symbols to be discarded on GOT related relocs. */
12209 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
12210 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
12211 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
12212 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
12213 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
12214 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
12215 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
12216 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
12217 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
12224 elf32_arm_target_format (void)
12227 return (target_big_endian
12228 ? "elf32-bigarm-symbian"
12229 : "elf32-littlearm-symbian");
12230 #elif defined (TE_VXWORKS)
12231 return (target_big_endian
12232 ? "elf32-bigarm-vxworks"
12233 : "elf32-littlearm-vxworks");
12235 if (target_big_endian)
12236 return "elf32-bigarm";
12238 return "elf32-littlearm";
12243 armelf_frob_symbol (symbolS * symp,
12246 elf_frob_symbol (symp, puntp);
12250 /* MD interface: Finalization. */
12252 /* A good place to do this, although this was probably not intended
12253 for this kind of use. We need to dump the literal pool before
12254 references are made to a null symbol pointer. */
12259 literal_pool * pool;
12261 for (pool = list_of_pools; pool; pool = pool->next)
12263 /* Put it at the end of the relevent section. */
12264 subseg_set (pool->section, pool->sub_section);
12266 arm_elf_change_section ();
12272 /* Adjust the symbol table. This marks Thumb symbols as distinct from
12276 arm_adjust_symtab (void)
12281 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12283 if (ARM_IS_THUMB (sym))
12285 if (THUMB_IS_FUNC (sym))
12287 /* Mark the symbol as a Thumb function. */
12288 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
12289 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
12290 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
12292 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
12293 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
12295 as_bad (_("%s: unexpected function type: %d"),
12296 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
12298 else switch (S_GET_STORAGE_CLASS (sym))
12301 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
12304 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
12307 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
12315 if (ARM_IS_INTERWORK (sym))
12316 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
12323 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12325 if (ARM_IS_THUMB (sym))
12327 elf_symbol_type * elf_sym;
12329 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
12330 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
12332 if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
12334 /* If it's a .thumb_func, declare it as so,
12335 otherwise tag label as .code 16. */
12336 if (THUMB_IS_FUNC (sym))
12337 elf_sym->internal_elf_sym.st_info =
12338 ELF_ST_INFO (bind, STT_ARM_TFUNC);
12340 elf_sym->internal_elf_sym.st_info =
12341 ELF_ST_INFO (bind, STT_ARM_16BIT);
12348 /* MD interface: Initialization. */
12351 set_constant_flonums (void)
12355 for (i = 0; i < NUM_FLOAT_VALS; i++)
12356 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
12366 if ( (arm_ops_hsh = hash_new ()) == NULL
12367 || (arm_cond_hsh = hash_new ()) == NULL
12368 || (arm_shift_hsh = hash_new ()) == NULL
12369 || (arm_psr_hsh = hash_new ()) == NULL
12370 || (arm_reg_hsh = hash_new ()) == NULL
12371 || (arm_reloc_hsh = hash_new ()) == NULL)
12372 as_fatal (_("virtual memory exhausted"));
12374 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
12375 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
12376 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
12377 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
12378 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
12379 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
12380 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
12381 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
12382 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
12383 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
12385 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
12386 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
12389 set_constant_flonums ();
12391 /* Set the cpu variant based on the command-line options. We prefer
12392 -mcpu= over -march= if both are set (as for GCC); and we prefer
12393 -mfpu= over any other way of setting the floating point unit.
12394 Use of legacy options with new options are faulted. */
12395 if (legacy_cpu != -1)
12397 if (mcpu_cpu_opt != -1 || march_cpu_opt != -1)
12398 as_bad (_("use of old and new-style options to set CPU type"));
12400 mcpu_cpu_opt = legacy_cpu;
12402 else if (mcpu_cpu_opt == -1)
12403 mcpu_cpu_opt = march_cpu_opt;
12405 if (legacy_fpu != -1)
12407 if (mfpu_opt != -1)
12408 as_bad (_("use of old and new-style options to set FPU type"));
12410 mfpu_opt = legacy_fpu;
12412 else if (mfpu_opt == -1)
12414 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
12415 /* Some environments specify a default FPU. If they don't, infer it
12416 from the processor. */
12417 if (mcpu_fpu_opt != -1)
12418 mfpu_opt = mcpu_fpu_opt;
12420 mfpu_opt = march_fpu_opt;
12422 mfpu_opt = FPU_DEFAULT;
12426 if (mfpu_opt == -1)
12428 if (mcpu_cpu_opt == -1)
12429 mfpu_opt = FPU_DEFAULT;
12430 else if (mcpu_cpu_opt & ARM_EXT_V5)
12431 mfpu_opt = FPU_ARCH_VFP_V2;
12433 mfpu_opt = FPU_ARCH_FPA;
12437 if (mcpu_cpu_opt == -1)
12438 selected_cpu = mcpu_cpu_opt = CPU_DEFAULT;
12440 if (mcpu_cpu_opt == -1)
12442 mcpu_cpu_opt = ARM_ANY;
12446 selected_cpu = mcpu_cpu_opt;
12449 cpu_variant = mcpu_cpu_opt | mfpu_opt;
12451 arm_arch_used = thumb_arch_used = 0;
12453 #if defined OBJ_COFF || defined OBJ_ELF
12455 unsigned int flags = 0;
12457 #if defined OBJ_ELF
12458 flags = meabi_flags;
12460 switch (meabi_flags)
12462 case EF_ARM_EABI_UNKNOWN:
12464 /* Set the flags in the private structure. */
12465 if (uses_apcs_26) flags |= F_APCS26;
12466 if (support_interwork) flags |= F_INTERWORK;
12467 if (uses_apcs_float) flags |= F_APCS_FLOAT;
12468 if (pic_code) flags |= F_PIC;
12469 if ((cpu_variant & FPU_ANY) == FPU_NONE
12470 || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
12471 flags |= F_SOFT_FLOAT;
12473 switch (mfloat_abi_opt)
12475 case ARM_FLOAT_ABI_SOFT:
12476 case ARM_FLOAT_ABI_SOFTFP:
12477 flags |= F_SOFT_FLOAT;
12480 case ARM_FLOAT_ABI_HARD:
12481 if (flags & F_SOFT_FLOAT)
12482 as_bad (_("hard-float conflicts with specified fpu"));
12486 /* Using VFP conventions (even if soft-float). */
12487 if (cpu_variant & FPU_VFP_EXT_NONE)
12488 flags |= F_VFP_FLOAT;
12490 #if defined OBJ_ELF
12491 if (cpu_variant & FPU_ARCH_MAVERICK)
12492 flags |= EF_ARM_MAVERICK_FLOAT;
12495 case EF_ARM_EABI_VER4:
12496 /* No additional flags to set. */
12503 bfd_set_private_flags (stdoutput, flags);
12505 /* We have run out flags in the COFF header to encode the
12506 status of ATPCS support, so instead we create a dummy,
12507 empty, debug section called .arm.atpcs. */
12512 sec = bfd_make_section (stdoutput, ".arm.atpcs");
12516 bfd_set_section_flags
12517 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
12518 bfd_set_section_size (stdoutput, sec, 0);
12519 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
12525 /* Record the CPU type as well. */
12526 switch (cpu_variant & ARM_CPU_MASK)
12529 mach = bfd_mach_arm_2;
12532 case ARM_3: /* Also ARM_250. */
12533 mach = bfd_mach_arm_2a;
12536 case ARM_6: /* Also ARM_7. */
12537 mach = bfd_mach_arm_3;
12541 mach = bfd_mach_arm_unknown;
12545 /* Catch special cases. */
12546 if (cpu_variant & ARM_CEXT_IWMMXT)
12547 mach = bfd_mach_arm_iWMMXt;
12548 else if (cpu_variant & ARM_CEXT_XSCALE)
12549 mach = bfd_mach_arm_XScale;
12550 else if (cpu_variant & ARM_CEXT_MAVERICK)
12551 mach = bfd_mach_arm_ep9312;
12552 else if (cpu_variant & ARM_EXT_V5E)
12553 mach = bfd_mach_arm_5TE;
12554 else if (cpu_variant & ARM_EXT_V5)
12556 if (cpu_variant & ARM_EXT_V4T)
12557 mach = bfd_mach_arm_5T;
12559 mach = bfd_mach_arm_5;
12561 else if (cpu_variant & ARM_EXT_V4)
12563 if (cpu_variant & ARM_EXT_V4T)
12564 mach = bfd_mach_arm_4T;
12566 mach = bfd_mach_arm_4;
12568 else if (cpu_variant & ARM_EXT_V3M)
12569 mach = bfd_mach_arm_3M;
12571 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
12574 /* Command line processing. */
12577 Invocation line includes a switch not recognized by the base assembler.
12578 See if it's a processor-specific option.
12580 This routine is somewhat complicated by the need for backwards
12581 compatibility (since older releases of gcc can't be changed).
12582 The new options try to make the interface as compatible as
12585 New options (supported) are:
12587 -mcpu=<cpu name> Assemble for selected processor
12588 -march=<architecture name> Assemble for selected architecture
12589 -mfpu=<fpu architecture> Assemble for selected FPU.
12590 -EB/-mbig-endian Big-endian
12591 -EL/-mlittle-endian Little-endian
12592 -k Generate PIC code
12593 -mthumb Start in Thumb mode
12594 -mthumb-interwork Code supports ARM/Thumb interworking
12596 For now we will also provide support for:
12598 -mapcs-32 32-bit Program counter
12599 -mapcs-26 26-bit Program counter
12600 -macps-float Floats passed in FP registers
12601 -mapcs-reentrant Reentrant code
12603 (sometime these will probably be replaced with -mapcs=<list of options>
12604 and -matpcs=<list of options>)
12606 The remaining options are only supported for back-wards compatibility.
12607 Cpu variants, the arm part is optional:
12608 -m[arm]1 Currently not supported.
12609 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
12610 -m[arm]3 Arm 3 processor
12611 -m[arm]6[xx], Arm 6 processors
12612 -m[arm]7[xx][t][[d]m] Arm 7 processors
12613 -m[arm]8[10] Arm 8 processors
12614 -m[arm]9[20][tdmi] Arm 9 processors
12615 -mstrongarm[110[0]] StrongARM processors
12616 -mxscale XScale processors
12617 -m[arm]v[2345[t[e]]] Arm architectures
12618 -mall All (except the ARM1)
12620 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
12621 -mfpe-old (No float load/store multiples)
12622 -mvfpxd VFP Single precision
12624 -mno-fpu Disable all floating point instructions
12626 The following CPU names are recognized:
12627 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
12628 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
12629 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
12630 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
12631 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
12632 arm10t arm10e, arm1020t, arm1020e, arm10200e,
12633 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
12637 const char * md_shortopts = "m:k";
12639 #ifdef ARM_BI_ENDIAN
12640 #define OPTION_EB (OPTION_MD_BASE + 0)
12641 #define OPTION_EL (OPTION_MD_BASE + 1)
12643 #if TARGET_BYTES_BIG_ENDIAN
12644 #define OPTION_EB (OPTION_MD_BASE + 0)
12646 #define OPTION_EL (OPTION_MD_BASE + 1)
12650 struct option md_longopts[] =
12653 {"EB", no_argument, NULL, OPTION_EB},
12656 {"EL", no_argument, NULL, OPTION_EL},
12658 {NULL, no_argument, NULL, 0}
12661 size_t md_longopts_size = sizeof (md_longopts);
12663 struct arm_option_table
12665 char *option; /* Option name to match. */
12666 char *help; /* Help information. */
12667 int *var; /* Variable to change. */
12668 int value; /* What to change it to. */
12669 char *deprecated; /* If non-null, print this message. */
12672 struct arm_option_table arm_opts[] =
12674 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
12675 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
12676 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
12677 &support_interwork, 1, NULL},
12678 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
12679 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
12680 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
12682 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
12683 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
12684 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
12685 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
12688 /* These are recognized by the assembler, but have no affect on code. */
12689 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
12690 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
12692 /* DON'T add any new processors to this list -- we want the whole list
12693 to go away... Add them to the processors table instead. */
12694 {"marm1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
12695 {"m1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
12696 {"marm2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
12697 {"m2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
12698 {"marm250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
12699 {"m250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
12700 {"marm3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
12701 {"m3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
12702 {"marm6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
12703 {"m6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
12704 {"marm600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
12705 {"m600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
12706 {"marm610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
12707 {"m610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
12708 {"marm620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
12709 {"m620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
12710 {"marm7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
12711 {"m7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
12712 {"marm70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
12713 {"m70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
12714 {"marm700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
12715 {"m700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
12716 {"marm700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
12717 {"m700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
12718 {"marm710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
12719 {"m710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
12720 {"marm710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
12721 {"m710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
12722 {"marm720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
12723 {"m720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
12724 {"marm7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
12725 {"m7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
12726 {"marm7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
12727 {"m7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
12728 {"marm7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
12729 {"m7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
12730 {"marm7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
12731 {"m7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
12732 {"marm7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
12733 {"m7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
12734 {"marm7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
12735 {"m7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
12736 {"marm7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
12737 {"m7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
12738 {"marm7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
12739 {"m7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
12740 {"marm7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12741 {"m7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12742 {"marm7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12743 {"m7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12744 {"marm710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
12745 {"m710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
12746 {"marm720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
12747 {"m720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
12748 {"marm740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
12749 {"m740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
12750 {"marm8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
12751 {"m8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
12752 {"marm810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
12753 {"m810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
12754 {"marm9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
12755 {"m9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
12756 {"marm9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
12757 {"m9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
12758 {"marm920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
12759 {"m920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
12760 {"marm940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
12761 {"m940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
12762 {"mstrongarm", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
12763 {"mstrongarm110", NULL, &legacy_cpu, ARM_ARCH_V4,
12764 N_("use -mcpu=strongarm110")},
12765 {"mstrongarm1100", NULL, &legacy_cpu, ARM_ARCH_V4,
12766 N_("use -mcpu=strongarm1100")},
12767 {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4,
12768 N_("use -mcpu=strongarm1110")},
12769 {"mxscale", NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
12770 {"miwmmxt", NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
12771 {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
12773 /* Architecture variants -- don't add any more to this list either. */
12774 {"mv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
12775 {"marmv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
12776 {"mv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
12777 {"marmv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
12778 {"mv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
12779 {"marmv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
12780 {"mv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
12781 {"marmv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
12782 {"mv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
12783 {"marmv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
12784 {"mv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
12785 {"marmv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
12786 {"mv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
12787 {"marmv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
12788 {"mv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
12789 {"marmv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
12790 {"mv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
12791 {"marmv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
12793 /* Floating point variants -- don't add any more to this list either. */
12794 {"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
12795 {"mfpa10", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
12796 {"mfpa11", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
12797 {"mno-fpu", NULL, &legacy_fpu, 0,
12798 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
12800 {NULL, NULL, NULL, 0, NULL}
12803 struct arm_cpu_option_table
12807 /* For some CPUs we assume an FPU unless the user explicitly sets
12810 /* The canonical name of the CPU, or NULL to use NAME converted to upper
12812 const char *canonical_name;
12815 /* This list should, at a minimum, contain all the cpu names
12816 recognized by GCC. */
12817 static struct arm_cpu_option_table arm_cpus[] =
12819 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
12820 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
12821 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
12822 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
12823 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
12824 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12825 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12826 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12827 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12828 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12829 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12830 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
12831 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12832 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
12833 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12834 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
12835 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12836 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12837 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12838 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12839 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12840 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12841 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12842 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12843 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12844 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12845 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12846 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12847 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12848 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12849 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12850 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12851 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12852 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12853 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12854 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12855 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12856 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12857 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12858 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
12859 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12860 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12861 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12862 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12863 /* For V5 or later processors we default to using VFP; but the user
12864 should really set the FPU type explicitly. */
12865 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
12866 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
12867 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
12868 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
12869 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
12870 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
12871 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
12872 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
12873 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
12874 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
12875 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
12876 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
12877 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
12878 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
12879 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
12880 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
12881 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
12882 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
12883 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
12884 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
12885 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
12886 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
12887 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
12888 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
12889 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
12890 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
12891 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
12892 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
12893 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
12894 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
12895 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
12896 /* ??? XSCALE is really an architecture. */
12897 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
12898 /* ??? iwmmxt is not a processor. */
12899 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
12900 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
12902 {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK, "ARM920T"},
12906 struct arm_arch_option_table
12913 /* This list should, at a minimum, contain all the architecture names
12914 recognized by GCC. */
12915 static struct arm_arch_option_table arm_archs[] =
12917 {"all", ARM_ANY, FPU_ARCH_FPA},
12918 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
12919 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
12920 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
12921 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
12922 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
12923 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
12924 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
12925 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
12926 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12927 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
12928 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
12929 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
12930 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
12931 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
12932 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
12933 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
12934 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
12935 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
12936 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
12937 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
12938 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
12939 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
12940 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
12941 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
12942 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
12943 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
12944 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
12948 /* ISA extensions in the co-processor space. */
12949 struct arm_option_value_table
12955 static struct arm_option_value_table arm_extensions[] =
12957 {"maverick", ARM_CEXT_MAVERICK},
12958 {"xscale", ARM_CEXT_XSCALE},
12959 {"iwmmxt", ARM_CEXT_IWMMXT},
12963 /* This list should, at a minimum, contain all the fpu names
12964 recognized by GCC. */
12965 static struct arm_option_value_table arm_fpus[] =
12967 {"softfpa", FPU_NONE},
12968 {"fpe", FPU_ARCH_FPE},
12969 {"fpe2", FPU_ARCH_FPE},
12970 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
12971 {"fpa", FPU_ARCH_FPA},
12972 {"fpa10", FPU_ARCH_FPA},
12973 {"fpa11", FPU_ARCH_FPA},
12974 {"arm7500fe", FPU_ARCH_FPA},
12975 {"softvfp", FPU_ARCH_VFP},
12976 {"softvfp+vfp", FPU_ARCH_VFP_V2},
12977 {"vfp", FPU_ARCH_VFP_V2},
12978 {"vfp9", FPU_ARCH_VFP_V2},
12979 {"vfp10", FPU_ARCH_VFP_V2},
12980 {"vfp10-r0", FPU_ARCH_VFP_V1},
12981 {"vfpxd", FPU_ARCH_VFP_V1xD},
12982 {"arm1020t", FPU_ARCH_VFP_V1},
12983 {"arm1020e", FPU_ARCH_VFP_V2},
12984 {"arm1136jfs", FPU_ARCH_VFP_V2},
12985 {"arm1136jf-s", FPU_ARCH_VFP_V2},
12986 {"maverick", FPU_ARCH_MAVERICK},
12990 static struct arm_option_value_table arm_float_abis[] =
12992 {"hard", ARM_FLOAT_ABI_HARD},
12993 {"softfp", ARM_FLOAT_ABI_SOFTFP},
12994 {"soft", ARM_FLOAT_ABI_SOFT},
12999 /* We only know how to output GNU and ver 4 (AAELF) formats. */
13000 static struct arm_option_value_table arm_eabis[] =
13002 {"gnu", EF_ARM_EABI_UNKNOWN},
13003 {"4", EF_ARM_EABI_VER4},
13008 struct arm_long_option_table
13010 char * option; /* Substring to match. */
13011 char * help; /* Help information. */
13012 int (* func) (char * subopt); /* Function to decode sub-option. */
13013 char * deprecated; /* If non-null, print this message. */
13017 arm_parse_extension (char * str, int * opt_p)
13019 while (str != NULL && *str != 0)
13021 struct arm_option_value_table * opt;
13027 as_bad (_("invalid architectural extension"));
13032 ext = strchr (str, '+');
13035 optlen = ext - str;
13037 optlen = strlen (str);
13041 as_bad (_("missing architectural extension"));
13045 for (opt = arm_extensions; opt->name != NULL; opt++)
13046 if (strncmp (opt->name, str, optlen) == 0)
13048 *opt_p |= opt->value;
13052 if (opt->name == NULL)
13054 as_bad (_("unknown architectural extnsion `%s'"), str);
13065 arm_parse_cpu (char * str)
13067 struct arm_cpu_option_table * opt;
13068 char * ext = strchr (str, '+');
13072 optlen = ext - str;
13074 optlen = strlen (str);
13078 as_bad (_("missing cpu name `%s'"), str);
13082 for (opt = arm_cpus; opt->name != NULL; opt++)
13083 if (strncmp (opt->name, str, optlen) == 0)
13085 mcpu_cpu_opt = opt->value;
13086 mcpu_fpu_opt = opt->default_fpu;
13087 if (opt->canonical_name)
13088 strcpy(selected_cpu_name, opt->canonical_name);
13092 for (i = 0; i < optlen; i++)
13093 selected_cpu_name[i] = TOUPPER (opt->name[i]);
13094 selected_cpu_name[i] = 0;
13098 return arm_parse_extension (ext, &mcpu_cpu_opt);
13103 as_bad (_("unknown cpu `%s'"), str);
13108 arm_parse_arch (char * str)
13110 struct arm_arch_option_table *opt;
13111 char *ext = strchr (str, '+');
13115 optlen = ext - str;
13117 optlen = strlen (str);
13121 as_bad (_("missing architecture name `%s'"), str);
13125 for (opt = arm_archs; opt->name != NULL; opt++)
13126 if (streq (opt->name, str))
13128 march_cpu_opt = opt->value;
13129 march_fpu_opt = opt->default_fpu;
13130 strcpy(selected_cpu_name, opt->name);
13133 return arm_parse_extension (ext, &march_cpu_opt);
13138 as_bad (_("unknown architecture `%s'\n"), str);
13143 arm_parse_fpu (char * str)
13145 struct arm_option_value_table * opt;
13147 for (opt = arm_fpus; opt->name != NULL; opt++)
13148 if (streq (opt->name, str))
13150 mfpu_opt = opt->value;
13154 as_bad (_("unknown floating point format `%s'\n"), str);
13159 arm_parse_float_abi (char * str)
13161 struct arm_option_value_table * opt;
13163 for (opt = arm_float_abis; opt->name != NULL; opt++)
13164 if (streq (opt->name, str))
13166 mfloat_abi_opt = opt->value;
13170 as_bad (_("unknown floating point abi `%s'\n"), str);
13176 arm_parse_eabi (char * str)
13178 struct arm_option_value_table *opt;
13180 for (opt = arm_eabis; opt->name != NULL; opt++)
13181 if (streq (opt->name, str))
13183 meabi_flags = opt->value;
13186 as_bad (_("unknown EABI `%s'\n"), str);
13191 struct arm_long_option_table arm_long_opts[] =
13193 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
13194 arm_parse_cpu, NULL},
13195 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
13196 arm_parse_arch, NULL},
13197 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
13198 arm_parse_fpu, NULL},
13199 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
13200 arm_parse_float_abi, NULL},
13202 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
13203 arm_parse_eabi, NULL},
13205 {NULL, NULL, 0, NULL}
13209 md_parse_option (int c, char * arg)
13211 struct arm_option_table *opt;
13212 struct arm_long_option_table *lopt;
13218 target_big_endian = 1;
13224 target_big_endian = 0;
13229 /* Listing option. Just ignore these, we don't support additional
13234 for (opt = arm_opts; opt->option != NULL; opt++)
13236 if (c == opt->option[0]
13237 && ((arg == NULL && opt->option[1] == 0)
13238 || streq (arg, opt->option + 1)))
13240 #if WARN_DEPRECATED
13241 /* If the option is deprecated, tell the user. */
13242 if (opt->deprecated != NULL)
13243 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
13244 arg ? arg : "", _(opt->deprecated));
13247 if (opt->var != NULL)
13248 *opt->var = opt->value;
13254 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13256 /* These options are expected to have an argument. */
13257 if (c == lopt->option[0]
13259 && strncmp (arg, lopt->option + 1,
13260 strlen (lopt->option + 1)) == 0)
13262 #if WARN_DEPRECATED
13263 /* If the option is deprecated, tell the user. */
13264 if (lopt->deprecated != NULL)
13265 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
13266 _(lopt->deprecated));
13269 /* Call the sup-option parser. */
13270 return lopt->func (arg + strlen (lopt->option) - 1);
13281 md_show_usage (FILE * fp)
13283 struct arm_option_table *opt;
13284 struct arm_long_option_table *lopt;
13286 fprintf (fp, _(" ARM-specific assembler options:\n"));
13288 for (opt = arm_opts; opt->option != NULL; opt++)
13289 if (opt->help != NULL)
13290 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
13292 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13293 if (lopt->help != NULL)
13294 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
13298 -EB assemble code for a big-endian cpu\n"));
13303 -EL assemble code for a little-endian cpu\n"));
13309 /* Set the public EABI object attributes. */
13311 aeabi_set_public_attributes (void)
13316 /* Choose the architecture based on the capabilities of the requested cpu
13317 (if any) and/or the instructions actually used. */
13318 flags = selected_cpu | mfpu_opt | arm_arch_used | thumb_arch_used;
13319 if (flags & ARM_EXT_V6T2)
13321 else if (flags & ARM_EXT_V6Z)
13323 else if (flags & ARM_EXT_V6K)
13325 else if (flags & ARM_EXT_V6)
13327 else if (flags & ARM_EXT_V5E)
13329 else if (flags & (ARM_EXT_V5 | ARM_EXT_V5T))
13331 else if (flags & ARM_EXT_V4T)
13333 else if (flags & ARM_EXT_V4)
13338 /* Tag_CPU_name. */
13339 if (selected_cpu_name[0])
13343 p = selected_cpu_name;
13344 if (strncmp(p, "armv", 4) == 0)
13349 for (i = 0; p[i]; i++)
13350 p[i] = TOUPPER (p[i]);
13352 elf32_arm_add_eabi_attr_string (stdoutput, 5, p);
13354 /* Tag_CPU_arch. */
13355 elf32_arm_add_eabi_attr_int (stdoutput, 6, arch);
13356 /* Tag_ARM_ISA_use. */
13358 elf32_arm_add_eabi_attr_int (stdoutput, 8, 1);
13359 /* Tag_THUMB_ISA_use. */
13360 if (thumb_arch_used)
13361 elf32_arm_add_eabi_attr_int (stdoutput, 9,
13362 (thumb_arch_used & ARM_EXT_V6T2) ? 2 : 1);
13363 /* Tag_VFP_arch. */
13364 if ((arm_arch_used | thumb_arch_used) & FPU_ARCH_VFP_V2)
13365 elf32_arm_add_eabi_attr_int (stdoutput, 10, 2);
13366 else if ((arm_arch_used | thumb_arch_used) & FPU_ARCH_VFP_V1)
13367 elf32_arm_add_eabi_attr_int (stdoutput, 10, 1);
13368 /* Tag_WMMX_arch. */
13369 if ((arm_arch_used | thumb_arch_used) & ARM_CEXT_IWMMXT)
13370 elf32_arm_add_eabi_attr_int (stdoutput, 11, 1);
13373 /* Add the .ARM.attributes section. */
13382 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
13385 aeabi_set_public_attributes ();
13386 size = elf32_arm_eabi_attr_size (stdoutput);
13387 s = subseg_new (".ARM.attributes", 0);
13388 bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
13389 addr = frag_now_fix ();
13390 p = frag_more (size);
13391 elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size);
13395 /* Parse a .cpu directive. */
13398 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
13400 struct arm_cpu_option_table *opt;
13404 name = input_line_pointer;
13405 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13406 input_line_pointer++;
13407 saved_char = *input_line_pointer;
13408 *input_line_pointer = 0;
13410 /* Skip the first "all" entry. */
13411 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
13412 if (streq (opt->name, name))
13414 mcpu_cpu_opt = opt->value;
13415 selected_cpu = mcpu_cpu_opt;
13416 if (opt->canonical_name)
13417 strcpy(selected_cpu_name, opt->canonical_name);
13421 for (i = 0; opt->name[i]; i++)
13422 selected_cpu_name[i] = TOUPPER (opt->name[i]);
13423 selected_cpu_name[i] = 0;
13425 cpu_variant = mcpu_cpu_opt | mfpu_opt;
13426 *input_line_pointer = saved_char;
13427 demand_empty_rest_of_line ();
13430 as_bad (_("unknown cpu `%s'"), name);
13431 *input_line_pointer = saved_char;
13432 ignore_rest_of_line ();
13436 /* Parse a .arch directive. */
13439 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
13441 struct arm_arch_option_table *opt;
13445 name = input_line_pointer;
13446 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13447 input_line_pointer++;
13448 saved_char = *input_line_pointer;
13449 *input_line_pointer = 0;
13451 /* Skip the first "all" entry. */
13452 for (opt = arm_archs + 1; opt->name != NULL; opt++)
13453 if (streq (opt->name, name))
13455 mcpu_cpu_opt = opt->value;
13456 selected_cpu = mcpu_cpu_opt;
13457 strcpy(selected_cpu_name, opt->name);
13458 cpu_variant = mcpu_cpu_opt | mfpu_opt;
13459 *input_line_pointer = saved_char;
13460 demand_empty_rest_of_line ();
13464 as_bad (_("unknown architecture `%s'\n"), name);
13465 *input_line_pointer = saved_char;
13466 ignore_rest_of_line ();
13470 /* Parse a .fpu directive. */
13473 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
13475 struct arm_option_value_table *opt;
13479 name = input_line_pointer;
13480 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13481 input_line_pointer++;
13482 saved_char = *input_line_pointer;
13483 *input_line_pointer = 0;
13485 for (opt = arm_fpus; opt->name != NULL; opt++)
13486 if (streq (opt->name, name))
13488 mfpu_opt = opt->value;
13489 cpu_variant = mcpu_cpu_opt | mfpu_opt;
13490 *input_line_pointer = saved_char;
13491 demand_empty_rest_of_line ();
13495 as_bad (_("unknown floating point format `%s'\n"), name);
13496 *input_line_pointer = saved_char;
13497 ignore_rest_of_line ();
13499 #endif /* OBJ_ELF */