1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
40 #include "opcode/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
60 symbolS * table_entry;
61 symbolS * personality_routine;
62 int personality_index;
63 /* The segment containing the function. */
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes;
70 /* The number of bytes pushed to the stack. */
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
80 /* Nonzero if an unwind_setfp directive has been seen. */
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored:1;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency = 0;
100 /* Types of processor to assemble for. */
101 #define ARM_1 ARM_ARCH_V1
102 #define ARM_2 ARM_ARCH_V2
103 #define ARM_3 ARM_ARCH_V2S
104 #define ARM_250 ARM_ARCH_V2S
105 #define ARM_6 ARM_ARCH_V3
106 #define ARM_7 ARM_ARCH_V3
107 #define ARM_8 ARM_ARCH_V4
108 #define ARM_9 ARM_ARCH_V4T
109 #define ARM_STRONG ARM_ARCH_V4
110 #define ARM_CPU_MASK 0x0000000f /* XXX? */
113 #if defined __XSCALE__
114 #define CPU_DEFAULT (ARM_ARCH_XSCALE)
116 #if defined __thumb__
117 #define CPU_DEFAULT (ARM_ARCH_V5T)
119 #define CPU_DEFAULT ARM_ANY
126 # define FPU_DEFAULT FPU_ARCH_FPA
127 # elif defined (TE_NetBSD)
129 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
131 /* Legacy a.out format. */
132 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
134 # elif defined (TE_VXWORKS)
135 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
137 /* For backwards compatibility, default to FPA. */
138 # define FPU_DEFAULT FPU_ARCH_FPA
140 #endif /* ifndef FPU_DEFAULT */
142 #define streq(a, b) (strcmp (a, b) == 0)
144 static unsigned long cpu_variant;
146 /* Flags stored in private area of BFD structure. */
147 static int uses_apcs_26 = FALSE;
148 static int atpcs = FALSE;
149 static int support_interwork = FALSE;
150 static int uses_apcs_float = FALSE;
151 static int pic_code = FALSE;
153 /* Variables that we set while parsing command-line options. Once all
154 options have been read we re-process these values to set the real
156 static int legacy_cpu = -1;
157 static int legacy_fpu = -1;
159 static int mcpu_cpu_opt = -1;
160 static int mcpu_fpu_opt = -1;
161 static int march_cpu_opt = -1;
162 static int march_fpu_opt = -1;
163 static int mfpu_opt = -1;
164 static int mfloat_abi_opt = -1;
167 static int meabi_flags = EABI_DEFAULT;
169 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
174 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
175 symbolS * GOT_symbol;
178 /* Size of relocation record. */
179 const int md_reloc_size = 8;
181 /* 0: assemble for ARM,
182 1: assemble for Thumb,
183 2: assemble for Thumb even though target CPU does not support thumb
185 static int thumb_mode = 0;
187 /* If unified_syntax is true, we are processing the new unified
188 ARM/Thumb syntax. Important differences from the old ARM mode:
190 - Immediate operands do not require a # prefix.
191 - Conditional affixes always appear at the end of the
192 instruction. (For backward compatibility, those instructions
193 that formerly had them in the middle, continue to accept them
195 - The IT instruction may appear, and if it does is validated
196 against subsequent conditional affixes. It does not generate
199 Important differences from the old Thumb mode:
201 - Immediate operands do not require a # prefix.
202 - Most of the V6T2 instructions are only available in unified mode.
203 - The .N and .W suffixes are recognized and honored (it is an error
204 if they cannot be honored).
205 - All instructions set the flags if and only if they have an 's' affix.
206 - Conditional affixes may be used. They are validated against
207 preceding IT instructions. Unlike ARM mode, you cannot use a
208 conditional affix except in the scope of an IT instruction. */
210 static bfd_boolean unified_syntax = FALSE;
215 unsigned long instruction;
221 bfd_reloc_code_real_type type;
230 unsigned present : 1; /* operand present */
231 unsigned isreg : 1; /* operand was a register */
232 unsigned immisreg : 1; /* .imm field is a second register */
233 unsigned hasreloc : 1; /* operand has relocation suffix */
234 unsigned writeback : 1; /* operand has trailing ! */
235 unsigned preind : 1; /* preindexed address */
236 unsigned postind : 1; /* postindexed address */
237 unsigned negative : 1; /* index register was negated */
238 unsigned shifted : 1; /* shift applied to operation */
239 unsigned shift_kind : 3; /* shift operation (enum shift_kind) */
243 static struct arm_it inst;
245 #define NUM_FLOAT_VALS 8
247 const char * fp_const[] =
249 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
252 /* Number of littlenums required to hold an extended precision number. */
253 #define MAX_LITTLENUMS 6
255 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
265 #define CP_T_X 0x00008000
266 #define CP_T_Y 0x00400000
268 #define CONDS_BIT 0x00100000
269 #define LOAD_BIT 0x00100000
271 #define DOUBLE_LOAD_FLAG 0x00000001
275 const char * template;
279 #define COND_ALWAYS 0xE
283 const char *template;
287 /* The bit that distinguishes CPSR and SPSR. */
288 #define SPSR_BIT (1 << 22)
290 /* The individual PSR flag bits. */
291 #define PSR_c (1 << 16)
292 #define PSR_x (1 << 17)
293 #define PSR_s (1 << 18)
294 #define PSR_f (1 << 19)
299 bfd_reloc_code_real_type reloc;
304 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
309 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
312 /* ARM register categories. This includes coprocessor numbers and various
313 architecture extensions' registers. */
335 /* Structure for a hash table entry for a register. */
339 unsigned char number;
341 unsigned char builtin;
344 /* Diagnostics used when we don't get a register of the expected type. */
345 const char *const reg_expected_msgs[] =
347 N_("ARM register expected"),
348 N_("bad or missing co-processor number"),
349 N_("co-processor register expected"),
350 N_("FPA register expected"),
351 N_("VFP single precision register expected"),
352 N_("VFP double precision register expected"),
353 N_("VFP system register expected"),
354 N_("Maverick MVF register expected"),
355 N_("Maverick MVD register expected"),
356 N_("Maverick MVFX register expected"),
357 N_("Maverick MVDX register expected"),
358 N_("Maverick MVAX register expected"),
359 N_("Maverick DSPSC register expected"),
360 N_("iWMMXt data register expected"),
361 N_("iWMMXt control register expected"),
362 N_("iWMMXt scalar register expected"),
363 N_("XScale accumulator register expected"),
366 /* Some well known registers that we refer to directly elsewhere. */
371 /* ARM instructions take 4bytes in the object file, Thumb instructions
377 /* Basic string to match. */
378 const char *template;
380 /* Parameters to instruction. */
381 unsigned char operands[8];
383 /* Conditional tag - see opcode_lookup. */
384 unsigned int tag : 4;
386 /* Basic instruction code. */
387 unsigned int avalue : 28;
389 /* Thumb-format instruction code. */
392 /* Which architecture variant provides this instruction. */
393 unsigned long avariant;
394 unsigned long tvariant;
396 /* Function to call to encode instruction in ARM format. */
397 void (* aencode) (void);
399 /* Function to call to encode instruction in Thumb format. */
400 void (* tencode) (void);
403 /* Defines for various bits that we will want to toggle. */
404 #define INST_IMMEDIATE 0x02000000
405 #define OFFSET_REG 0x02000000
406 #define HWOFFSET_IMM 0x00400000
407 #define SHIFT_BY_REG 0x00000010
408 #define PRE_INDEX 0x01000000
409 #define INDEX_UP 0x00800000
410 #define WRITE_BACK 0x00200000
411 #define LDM_TYPE_2_OR_3 0x00400000
413 #define LITERAL_MASK 0xf000f000
414 #define OPCODE_MASK 0xfe1fffff
415 #define V4_STR_BIT 0x00000020
417 #define DATA_OP_SHIFT 21
419 /* Codes to distinguish the arithmetic instructions. */
430 #define OPCODE_CMP 10
431 #define OPCODE_CMN 11
432 #define OPCODE_ORR 12
433 #define OPCODE_MOV 13
434 #define OPCODE_BIC 14
435 #define OPCODE_MVN 15
437 #define T_OPCODE_MUL 0x4340
438 #define T_OPCODE_TST 0x4200
439 #define T_OPCODE_CMN 0x42c0
440 #define T_OPCODE_NEG 0x4240
441 #define T_OPCODE_MVN 0x43c0
443 #define T_OPCODE_ADD_R3 0x1800
444 #define T_OPCODE_SUB_R3 0x1a00
445 #define T_OPCODE_ADD_HI 0x4400
446 #define T_OPCODE_ADD_ST 0xb000
447 #define T_OPCODE_SUB_ST 0xb080
448 #define T_OPCODE_ADD_SP 0xa800
449 #define T_OPCODE_ADD_PC 0xa000
450 #define T_OPCODE_ADD_I8 0x3000
451 #define T_OPCODE_SUB_I8 0x3800
452 #define T_OPCODE_ADD_I3 0x1c00
453 #define T_OPCODE_SUB_I3 0x1e00
455 #define T_OPCODE_ASR_R 0x4100
456 #define T_OPCODE_LSL_R 0x4080
457 #define T_OPCODE_LSR_R 0x40c0
458 #define T_OPCODE_ROR_R 0x41c0
459 #define T_OPCODE_ASR_I 0x1000
460 #define T_OPCODE_LSL_I 0x0000
461 #define T_OPCODE_LSR_I 0x0800
463 #define T_OPCODE_MOV_I8 0x2000
464 #define T_OPCODE_CMP_I8 0x2800
465 #define T_OPCODE_CMP_LR 0x4280
466 #define T_OPCODE_MOV_HR 0x4600
467 #define T_OPCODE_CMP_HR 0x4500
469 #define T_OPCODE_LDR_PC 0x4800
470 #define T_OPCODE_LDR_SP 0x9800
471 #define T_OPCODE_STR_SP 0x9000
472 #define T_OPCODE_LDR_IW 0x6800
473 #define T_OPCODE_STR_IW 0x6000
474 #define T_OPCODE_LDR_IH 0x8800
475 #define T_OPCODE_STR_IH 0x8000
476 #define T_OPCODE_LDR_IB 0x7800
477 #define T_OPCODE_STR_IB 0x7000
478 #define T_OPCODE_LDR_RW 0x5800
479 #define T_OPCODE_STR_RW 0x5000
480 #define T_OPCODE_LDR_RH 0x5a00
481 #define T_OPCODE_STR_RH 0x5200
482 #define T_OPCODE_LDR_RB 0x5c00
483 #define T_OPCODE_STR_RB 0x5400
485 #define T_OPCODE_PUSH 0xb400
486 #define T_OPCODE_POP 0xbc00
488 #define T_OPCODE_BRANCH 0xe7fe
490 #define THUMB_SIZE 2 /* Size of thumb instruction. */
491 #define THUMB_PP_PC_LR 0x0100
492 #define THUMB_LOAD_BIT 0x0800
494 #define BAD_ARGS _("bad arguments to instruction")
495 #define BAD_PC _("r15 not allowed here")
496 #define BAD_COND _("instruction cannot be conditional")
497 #define BAD_OVERLAP _("registers may not be the same")
498 #define BAD_HIREG _("lo register required")
499 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
501 static struct hash_control *arm_ops_hsh;
502 static struct hash_control *arm_cond_hsh;
503 static struct hash_control *arm_shift_hsh;
504 static struct hash_control *arm_psr_hsh;
505 static struct hash_control *arm_reg_hsh;
506 static struct hash_control *arm_reloc_hsh;
508 /* Stuff needed to resolve the label ambiguity
518 symbolS * last_label_seen;
519 static int label_is_thumb_function_name = FALSE;
521 /* Literal pool structure. Held on a per-section
522 and per-sub-section basis. */
524 #define MAX_LITERAL_POOL_SIZE 1024
525 typedef struct literal_pool
527 expressionS literals [MAX_LITERAL_POOL_SIZE];
528 unsigned int next_free_entry;
533 struct literal_pool * next;
536 /* Pointer to a linked list of literal pools. */
537 literal_pool * list_of_pools = NULL;
541 /* This array holds the chars that always start a comment. If the
542 pre-processor is disabled, these aren't very useful. */
543 const char comment_chars[] = "@";
545 /* This array holds the chars that only start a comment at the beginning of
546 a line. If the line seems to have the form '# 123 filename'
547 .line and .file directives will appear in the pre-processed output. */
548 /* Note that input_file.c hand checks for '#' at the beginning of the
549 first line of the input file. This is because the compiler outputs
550 #NO_APP at the beginning of its output. */
551 /* Also note that comments like this one will always work. */
552 const char line_comment_chars[] = "#";
554 const char line_separator_chars[] = ";";
556 /* Chars that can be used to separate mant
557 from exp in floating point numbers. */
558 const char EXP_CHARS[] = "eE";
560 /* Chars that mean this number is a floating point constant. */
564 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
566 /* Prefix characters that indicate the start of an immediate
568 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
570 /* Separator character handling. */
572 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
575 skip_past_char (char ** str, char c)
585 #define skip_past_comma(str) skip_past_char (str, ',')
587 /* Arithmetic expressions (possibly involving symbols). */
589 /* Return TRUE if anything in the expression is a bignum. */
592 walk_no_bignums (symbolS * sp)
594 if (symbol_get_value_expression (sp)->X_op == O_big)
597 if (symbol_get_value_expression (sp)->X_add_symbol)
599 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
600 || (symbol_get_value_expression (sp)->X_op_symbol
601 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
607 static int in_my_get_expression = 0;
609 /* Third argument to my_get_expression. */
610 #define GE_NO_PREFIX 0
611 #define GE_IMM_PREFIX 1
612 #define GE_OPT_PREFIX 2
615 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
620 /* In unified syntax, all prefixes are optional. */
622 prefix_mode = GE_OPT_PREFIX;
626 case GE_NO_PREFIX: break;
628 if (!is_immediate_prefix (**str))
630 inst.error = _("immediate expression requires a # prefix");
636 if (is_immediate_prefix (**str))
642 memset (ep, 0, sizeof (expressionS));
644 save_in = input_line_pointer;
645 input_line_pointer = *str;
646 in_my_get_expression = 1;
647 seg = expression (ep);
648 in_my_get_expression = 0;
650 if (ep->X_op == O_illegal)
652 /* We found a bad expression in md_operand(). */
653 *str = input_line_pointer;
654 input_line_pointer = save_in;
655 if (inst.error == NULL)
656 inst.error = _("bad expression");
661 if (seg != absolute_section
662 && seg != text_section
663 && seg != data_section
664 && seg != bss_section
665 && seg != undefined_section)
667 inst.error = _("bad segment");
668 *str = input_line_pointer;
669 input_line_pointer = save_in;
674 /* Get rid of any bignums now, so that we don't generate an error for which
675 we can't establish a line number later on. Big numbers are never valid
676 in instructions, which is where this routine is always called. */
677 if (ep->X_op == O_big
679 && (walk_no_bignums (ep->X_add_symbol)
681 && walk_no_bignums (ep->X_op_symbol)))))
683 inst.error = _("invalid constant");
684 *str = input_line_pointer;
685 input_line_pointer = save_in;
689 *str = input_line_pointer;
690 input_line_pointer = save_in;
694 /* Turn a string in input_line_pointer into a floating point constant
695 of type TYPE, and store the appropriate bytes in *LITP. The number
696 of LITTLENUMS emitted is stored in *SIZEP. An error message is
697 returned, or NULL on OK.
699 Note that fp constants aren't represent in the normal way on the ARM.
700 In big endian mode, things are as expected. However, in little endian
701 mode fp constants are big-endian word-wise, and little-endian byte-wise
702 within the words. For example, (double) 1.1 in big endian mode is
703 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
704 the byte sequence 99 99 f1 3f 9a 99 99 99.
706 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
709 md_atof (int type, char * litP, int * sizeP)
712 LITTLENUM_TYPE words[MAX_LITTLENUMS];
744 return _("bad call to MD_ATOF()");
747 t = atof_ieee (input_line_pointer, type, words);
749 input_line_pointer = t;
752 if (target_big_endian)
754 for (i = 0; i < prec; i++)
756 md_number_to_chars (litP, (valueT) words[i], 2);
762 if (cpu_variant & FPU_ARCH_VFP)
763 for (i = prec - 1; i >= 0; i--)
765 md_number_to_chars (litP, (valueT) words[i], 2);
769 /* For a 4 byte float the order of elements in `words' is 1 0.
770 For an 8 byte float the order is 1 0 3 2. */
771 for (i = 0; i < prec; i += 2)
773 md_number_to_chars (litP, (valueT) words[i + 1], 2);
774 md_number_to_chars (litP + 2, (valueT) words[i], 2);
782 /* We handle all bad expressions here, so that we can report the faulty
783 instruction in the error message. */
785 md_operand (expressionS * expr)
787 if (in_my_get_expression)
788 expr->X_op = O_illegal;
791 /* Immediate values. */
793 /* Generic immediate-value read function for use in directives.
794 Accepts anything that 'expression' can fold to a constant.
795 *val receives the number. */
798 immediate_for_directive (int *val)
801 exp.X_op = O_illegal;
803 if (is_immediate_prefix (*input_line_pointer))
805 input_line_pointer++;
809 if (exp.X_op != O_constant)
811 as_bad (_("expected #constant"));
812 ignore_rest_of_line ();
815 *val = exp.X_add_number;
820 /* Register parsing. */
822 /* Generic register parser. CCP points to what should be the
823 beginning of a register name. If it is indeed a valid register
824 name, advance CCP over it and return the reg_entry structure;
825 otherwise return NULL. Does not issue diagnostics. */
827 static struct reg_entry *
828 arm_reg_parse_multi (char **ccp)
832 struct reg_entry *reg;
834 #ifdef REGISTER_PREFIX
835 if (*start != REGISTER_PREFIX)
839 #ifdef OPTIONAL_REGISTER_PREFIX
840 if (*start == OPTIONAL_REGISTER_PREFIX)
845 if (!ISALPHA (*p) || !is_name_beginner (*p))
850 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
852 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
861 /* As above, but the register must be of type TYPE, and the return
862 value is the register number or NULL. */
865 arm_reg_parse (char **ccp, enum arm_reg_type type)
868 struct reg_entry *reg = arm_reg_parse_multi (ccp);
870 if (reg && reg->type == type)
873 /* Alternative syntaxes are accepted for a few register classes. */
880 /* Generic coprocessor register names are allowed for these. */
881 if (reg->type == REG_TYPE_CN)
886 /* For backward compatibility, a bare number is valid here. */
888 unsigned long processor = strtoul (start, ccp, 10);
889 if (*ccp != start && processor <= 15)
894 /* WC includes WCG. ??? I'm not sure this is true for all
895 instructions that take WC registers. */
896 if (reg->type == REG_TYPE_MMXWCG)
908 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
910 parse_reg_list (char ** strp)
916 /* We come back here if we get ranges concatenated by '+' or '|'. */
931 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
933 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
943 inst.error = _("bad range in register list");
947 for (i = cur_reg + 1; i < reg; i++)
949 if (range & (1 << i))
951 (_("Warning: duplicated register (r%d) in register list"),
959 if (range & (1 << reg))
960 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
962 else if (reg <= cur_reg)
963 as_tsktsk (_("Warning: register range not in ascending order"));
968 while (skip_past_comma (&str) != FAIL
969 || (in_range = 1, *str++ == '-'));
974 inst.error = _("missing `}'");
982 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
985 if (expr.X_op == O_constant)
987 if (expr.X_add_number
988 != (expr.X_add_number & 0x0000ffff))
990 inst.error = _("invalid register mask");
994 if ((range & expr.X_add_number) != 0)
996 int regno = range & expr.X_add_number;
999 regno = (1 << regno) - 1;
1001 (_("Warning: duplicated register (r%d) in register list"),
1005 range |= expr.X_add_number;
1009 if (inst.reloc.type != 0)
1011 inst.error = _("expression too complex");
1015 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1016 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1017 inst.reloc.pc_rel = 0;
1021 if (*str == '|' || *str == '+')
1027 while (another_range);
1033 /* Parse a VFP register list. If the string is invalid return FAIL.
1034 Otherwise return the number of registers, and set PBASE to the first
1035 register. Double precision registers are matched if DP is nonzero. */
1038 parse_vfp_reg_list (char **str, int *pbase, int dp)
1046 unsigned long mask = 0;
1056 regtype = REG_TYPE_VFD;
1061 regtype = REG_TYPE_VFS;
1065 base_reg = max_regs;
1069 new_base = arm_reg_parse (str, regtype);
1070 if (new_base == FAIL)
1072 inst.error = gettext (reg_expected_msgs[regtype]);
1076 if (new_base < base_reg)
1077 base_reg = new_base;
1079 if (mask & (1 << new_base))
1081 inst.error = _("invalid register list");
1085 if ((mask >> new_base) != 0 && ! warned)
1087 as_tsktsk (_("register list not in ascending order"));
1091 mask |= 1 << new_base;
1094 if (**str == '-') /* We have the start of a range expression */
1100 if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
1102 inst.error = gettext (reg_expected_msgs[regtype]);
1106 if (high_range <= new_base)
1108 inst.error = _("register range not in ascending order");
1112 for (new_base++; new_base <= high_range; new_base++)
1114 if (mask & (1 << new_base))
1116 inst.error = _("invalid register list");
1120 mask |= 1 << new_base;
1125 while (skip_past_comma (str) != FAIL);
1129 /* Sanity check -- should have raised a parse error above. */
1130 if (count == 0 || count > max_regs)
1135 /* Final test -- the registers must be consecutive. */
1137 for (i = 0; i < count; i++)
1139 if ((mask & (1u << i)) == 0)
1141 inst.error = _("non-contiguous register range");
1149 /* Parse an explicit relocation suffix on an expression. This is
1150 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1151 arm_reloc_hsh contains no entries, so this function can only
1152 succeed if there is no () after the word. Returns -1 on error,
1153 BFD_RELOC_UNUSED if there wasn't any suffix. */
1155 parse_reloc (char **str)
1157 struct reloc_entry *r;
1161 return BFD_RELOC_UNUSED;
1166 while (*q && *q != ')' && *q != ',')
1171 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1178 /* Directives: register aliases. */
1181 insert_reg_alias (char *str, int number, int type)
1183 struct reg_entry *new;
1186 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1189 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1191 /* Only warn about a redefinition if it's not defined as the
1193 else if (new->number != number || new->type != type)
1194 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1199 name = xstrdup (str);
1200 new = xmalloc (sizeof (struct reg_entry));
1203 new->number = number;
1205 new->builtin = FALSE;
1207 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1211 /* Look for the .req directive. This is of the form:
1213 new_register_name .req existing_register_name
1215 If we find one, or if it looks sufficiently like one that we want to
1216 handle any error here, return non-zero. Otherwise return zero. */
1219 create_register_alias (char * newname, char *p)
1221 struct reg_entry *old;
1222 char *oldname, *nbuf;
1225 /* The input scrubber ensures that whitespace after the mnemonic is
1226 collapsed to single spaces. */
1228 if (strncmp (oldname, " .req ", 6) != 0)
1232 if (*oldname == '\0')
1235 old = hash_find (arm_reg_hsh, oldname);
1238 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1242 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1243 the desired alias name, and p points to its end. If not, then
1244 the desired alias name is in the global original_case_string. */
1245 #ifdef TC_CASE_SENSITIVE
1248 newname = original_case_string;
1249 nlen = strlen (newname);
1252 nbuf = alloca (nlen + 1);
1253 memcpy (nbuf, newname, nlen);
1256 /* Create aliases under the new name as stated; an all-lowercase
1257 version of the new name; and an all-uppercase version of the new
1259 insert_reg_alias (nbuf, old->number, old->type);
1261 for (p = nbuf; *p; p++)
1264 if (strncmp (nbuf, newname, nlen))
1265 insert_reg_alias (nbuf, old->number, old->type);
1267 for (p = nbuf; *p; p++)
1270 if (strncmp (nbuf, newname, nlen))
1271 insert_reg_alias (nbuf, old->number, old->type);
1276 /* Should never be called, as .req goes between the alias and the
1277 register name, not at the beginning of the line. */
1279 s_req (int a ATTRIBUTE_UNUSED)
1281 as_bad (_("invalid syntax for .req directive"));
1284 /* The .unreq directive deletes an alias which was previously defined
1285 by .req. For example:
1291 s_unreq (int a ATTRIBUTE_UNUSED)
1296 name = input_line_pointer;
1298 while (*input_line_pointer != 0
1299 && *input_line_pointer != ' '
1300 && *input_line_pointer != '\n')
1301 ++input_line_pointer;
1303 saved_char = *input_line_pointer;
1304 *input_line_pointer = 0;
1307 as_bad (_("invalid syntax for .unreq directive"));
1310 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
1313 as_bad (_("unknown register alias '%s'"), name);
1314 else if (reg->builtin)
1315 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1319 hash_delete (arm_reg_hsh, name);
1320 free ((char *) reg->name);
1325 *input_line_pointer = saved_char;
1326 demand_empty_rest_of_line ();
1329 /* Directives: Instruction set selection. */
1332 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1333 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1334 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1335 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1337 static enum mstate mapstate = MAP_UNDEFINED;
1340 mapping_state (enum mstate state)
1343 const char * symname;
1346 if (mapstate == state)
1347 /* The mapping symbol has already been emitted.
1348 There is nothing else to do. */
1357 type = BSF_NO_FLAGS;
1361 type = BSF_NO_FLAGS;
1365 type = BSF_NO_FLAGS;
1373 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1375 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
1376 symbol_table_insert (symbolP);
1377 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1382 THUMB_SET_FUNC (symbolP, 0);
1383 ARM_SET_THUMB (symbolP, 0);
1384 ARM_SET_INTERWORK (symbolP, support_interwork);
1388 THUMB_SET_FUNC (symbolP, 1);
1389 ARM_SET_THUMB (symbolP, 1);
1390 ARM_SET_INTERWORK (symbolP, support_interwork);
1399 #define mapping_state(x) /* nothing */
1402 /* Find the real, Thumb encoded start of a Thumb function. */
1405 find_real_start (symbolS * symbolP)
1408 const char * name = S_GET_NAME (symbolP);
1409 symbolS * new_target;
1411 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1412 #define STUB_NAME ".real_start_of"
1417 /* The compiler may generate BL instructions to local labels because
1418 it needs to perform a branch to a far away location. These labels
1419 do not have a corresponding ".real_start_of" label. We check
1420 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1421 the ".real_start_of" convention for nonlocal branches. */
1422 if (S_IS_LOCAL (symbolP) || name[0] == '.')
1425 real_start = ACONCAT ((STUB_NAME, name, NULL));
1426 new_target = symbol_find (real_start);
1428 if (new_target == NULL)
1430 as_warn ("Failed to find real start of function: %s\n", name);
1431 new_target = symbolP;
1438 opcode_select (int width)
1445 if (! (cpu_variant & ARM_EXT_V4T))
1446 as_bad (_("selected processor does not support THUMB opcodes"));
1449 /* No need to force the alignment, since we will have been
1450 coming from ARM mode, which is word-aligned. */
1451 record_alignment (now_seg, 1);
1453 mapping_state (MAP_THUMB);
1459 if ((cpu_variant & ARM_ALL) == ARM_EXT_V4T)
1460 as_bad (_("selected processor does not support ARM opcodes"));
1465 frag_align (2, 0, 0);
1467 record_alignment (now_seg, 1);
1469 mapping_state (MAP_ARM);
1473 as_bad (_("invalid instruction size selected (%d)"), width);
1478 s_arm (int ignore ATTRIBUTE_UNUSED)
1481 demand_empty_rest_of_line ();
1485 s_thumb (int ignore ATTRIBUTE_UNUSED)
1488 demand_empty_rest_of_line ();
1492 s_code (int unused ATTRIBUTE_UNUSED)
1496 temp = get_absolute_expression ();
1501 opcode_select (temp);
1505 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1510 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
1512 /* If we are not already in thumb mode go into it, EVEN if
1513 the target processor does not support thumb instructions.
1514 This is used by gcc/config/arm/lib1funcs.asm for example
1515 to compile interworking support functions even if the
1516 target processor should not support interworking. */
1520 record_alignment (now_seg, 1);
1523 demand_empty_rest_of_line ();
1527 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
1531 /* The following label is the name/address of the start of a Thumb function.
1532 We need to know this for the interworking support. */
1533 label_is_thumb_function_name = TRUE;
1536 /* Perform a .set directive, but also mark the alias as
1537 being a thumb function. */
1540 s_thumb_set (int equiv)
1542 /* XXX the following is a duplicate of the code for s_set() in read.c
1543 We cannot just call that code as we need to get at the symbol that
1550 /* Especial apologies for the random logic:
1551 This just grew, and could be parsed much more simply!
1553 name = input_line_pointer;
1554 delim = get_symbol_end ();
1555 end_name = input_line_pointer;
1558 if (*input_line_pointer != ',')
1561 as_bad (_("expected comma after name \"%s\""), name);
1563 ignore_rest_of_line ();
1567 input_line_pointer++;
1570 if (name[0] == '.' && name[1] == '\0')
1572 /* XXX - this should not happen to .thumb_set. */
1576 if ((symbolP = symbol_find (name)) == NULL
1577 && (symbolP = md_undefined_symbol (name)) == NULL)
1580 /* When doing symbol listings, play games with dummy fragments living
1581 outside the normal fragment chain to record the file and line info
1583 if (listing & LISTING_SYMBOLS)
1585 extern struct list_info_struct * listing_tail;
1586 fragS * dummy_frag = xmalloc (sizeof (fragS));
1588 memset (dummy_frag, 0, sizeof (fragS));
1589 dummy_frag->fr_type = rs_fill;
1590 dummy_frag->line = listing_tail;
1591 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1592 dummy_frag->fr_symbol = symbolP;
1596 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1599 /* "set" symbols are local unless otherwise specified. */
1600 SF_SET_LOCAL (symbolP);
1601 #endif /* OBJ_COFF */
1602 } /* Make a new symbol. */
1604 symbol_table_insert (symbolP);
1609 && S_IS_DEFINED (symbolP)
1610 && S_GET_SEGMENT (symbolP) != reg_section)
1611 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1613 pseudo_set (symbolP);
1615 demand_empty_rest_of_line ();
1617 /* XXX Now we come to the Thumb specific bit of code. */
1619 THUMB_SET_FUNC (symbolP, 1);
1620 ARM_SET_THUMB (symbolP, 1);
1621 #if defined OBJ_ELF || defined OBJ_COFF
1622 ARM_SET_INTERWORK (symbolP, support_interwork);
1626 /* Directives: Mode selection. */
1628 /* .syntax [unified|divided] - choose the new unified syntax
1629 (same for Arm and Thumb encoding, modulo slight differences in what
1630 can be represented) or the old divergent syntax for each mode. */
1632 s_syntax (int unused ATTRIBUTE_UNUSED)
1636 name = input_line_pointer;
1637 delim = get_symbol_end ();
1639 if (!strcasecmp (name, "unified"))
1640 unified_syntax = TRUE;
1641 else if (!strcasecmp (name, "divided"))
1642 unified_syntax = FALSE;
1645 as_bad (_("unrecognized syntax mode \"%s\""), name);
1648 *input_line_pointer = delim;
1649 demand_empty_rest_of_line ();
1652 /* Directives: sectioning and alignment. */
1654 /* Same as s_align_ptwo but align 0 => align 2. */
1657 s_align (int unused ATTRIBUTE_UNUSED)
1661 long max_alignment = 15;
1663 temp = get_absolute_expression ();
1664 if (temp > max_alignment)
1665 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
1668 as_bad (_("alignment negative. 0 assumed."));
1672 if (*input_line_pointer == ',')
1674 input_line_pointer++;
1675 temp_fill = get_absolute_expression ();
1683 /* Only make a frag if we HAVE to. */
1684 if (temp && !need_pass_2)
1685 frag_align (temp, (int) temp_fill, 0);
1686 demand_empty_rest_of_line ();
1688 record_alignment (now_seg, temp);
1692 s_bss (int ignore ATTRIBUTE_UNUSED)
1694 /* We don't support putting frags in the BSS segment, we fake it by
1695 marking in_bss, then looking at s_skip for clues. */
1696 subseg_set (bss_section, 0);
1697 demand_empty_rest_of_line ();
1698 mapping_state (MAP_DATA);
1702 s_even (int ignore ATTRIBUTE_UNUSED)
1704 /* Never make frag if expect extra pass. */
1706 frag_align (1, 0, 0);
1708 record_alignment (now_seg, 1);
1710 demand_empty_rest_of_line ();
1713 /* Directives: Literal pools. */
1715 static literal_pool *
1716 find_literal_pool (void)
1718 literal_pool * pool;
1720 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1722 if (pool->section == now_seg
1723 && pool->sub_section == now_subseg)
1730 static literal_pool *
1731 find_or_make_literal_pool (void)
1733 /* Next literal pool ID number. */
1734 static unsigned int latest_pool_num = 1;
1735 literal_pool * pool;
1737 pool = find_literal_pool ();
1741 /* Create a new pool. */
1742 pool = xmalloc (sizeof (* pool));
1746 pool->next_free_entry = 0;
1747 pool->section = now_seg;
1748 pool->sub_section = now_subseg;
1749 pool->next = list_of_pools;
1750 pool->symbol = NULL;
1752 /* Add it to the list. */
1753 list_of_pools = pool;
1756 /* New pools, and emptied pools, will have a NULL symbol. */
1757 if (pool->symbol == NULL)
1759 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1760 (valueT) 0, &zero_address_frag);
1761 pool->id = latest_pool_num ++;
1768 /* Add the literal in the global 'inst'
1769 structure to the relevent literal pool. */
1772 add_to_lit_pool (void)
1774 literal_pool * pool;
1777 pool = find_or_make_literal_pool ();
1779 /* Check if this literal value is already in the pool. */
1780 for (entry = 0; entry < pool->next_free_entry; entry ++)
1782 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1783 && (inst.reloc.exp.X_op == O_constant)
1784 && (pool->literals[entry].X_add_number
1785 == inst.reloc.exp.X_add_number)
1786 && (pool->literals[entry].X_unsigned
1787 == inst.reloc.exp.X_unsigned))
1790 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1791 && (inst.reloc.exp.X_op == O_symbol)
1792 && (pool->literals[entry].X_add_number
1793 == inst.reloc.exp.X_add_number)
1794 && (pool->literals[entry].X_add_symbol
1795 == inst.reloc.exp.X_add_symbol)
1796 && (pool->literals[entry].X_op_symbol
1797 == inst.reloc.exp.X_op_symbol))
1801 /* Do we need to create a new entry? */
1802 if (entry == pool->next_free_entry)
1804 if (entry >= MAX_LITERAL_POOL_SIZE)
1806 inst.error = _("literal pool overflow");
1810 pool->literals[entry] = inst.reloc.exp;
1811 pool->next_free_entry += 1;
1814 inst.reloc.exp.X_op = O_symbol;
1815 inst.reloc.exp.X_add_number = ((int) entry) * 4;
1816 inst.reloc.exp.X_add_symbol = pool->symbol;
1821 /* Can't use symbol_new here, so have to create a symbol and then at
1822 a later date assign it a value. Thats what these functions do. */
1825 symbol_locate (symbolS * symbolP,
1826 const char * name, /* It is copied, the caller can modify. */
1827 segT segment, /* Segment identifier (SEG_<something>). */
1828 valueT valu, /* Symbol value. */
1829 fragS * frag) /* Associated fragment. */
1831 unsigned int name_length;
1832 char * preserved_copy_of_name;
1834 name_length = strlen (name) + 1; /* +1 for \0. */
1835 obstack_grow (¬es, name, name_length);
1836 preserved_copy_of_name = obstack_finish (¬es);
1838 #ifdef tc_canonicalize_symbol_name
1839 preserved_copy_of_name =
1840 tc_canonicalize_symbol_name (preserved_copy_of_name);
1843 S_SET_NAME (symbolP, preserved_copy_of_name);
1845 S_SET_SEGMENT (symbolP, segment);
1846 S_SET_VALUE (symbolP, valu);
1847 symbol_clear_list_pointers (symbolP);
1849 symbol_set_frag (symbolP, frag);
1851 /* Link to end of symbol chain. */
1853 extern int symbol_table_frozen;
1855 if (symbol_table_frozen)
1859 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1861 obj_symbol_new_hook (symbolP);
1863 #ifdef tc_symbol_new_hook
1864 tc_symbol_new_hook (symbolP);
1868 verify_symbol_chain (symbol_rootP, symbol_lastP);
1869 #endif /* DEBUG_SYMS */
1874 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1877 literal_pool * pool;
1880 pool = find_literal_pool ();
1882 || pool->symbol == NULL
1883 || pool->next_free_entry == 0)
1886 mapping_state (MAP_DATA);
1888 /* Align pool as you have word accesses.
1889 Only make a frag if we have to. */
1891 frag_align (2, 0, 0);
1893 record_alignment (now_seg, 2);
1895 sprintf (sym_name, "$$lit_\002%x", pool->id);
1897 symbol_locate (pool->symbol, sym_name, now_seg,
1898 (valueT) frag_now_fix (), frag_now);
1899 symbol_table_insert (pool->symbol);
1901 ARM_SET_THUMB (pool->symbol, thumb_mode);
1903 #if defined OBJ_COFF || defined OBJ_ELF
1904 ARM_SET_INTERWORK (pool->symbol, support_interwork);
1907 for (entry = 0; entry < pool->next_free_entry; entry ++)
1908 /* First output the expression in the instruction to the pool. */
1909 emit_expr (&(pool->literals[entry]), 4); /* .word */
1911 /* Mark the pool as empty. */
1912 pool->next_free_entry = 0;
1913 pool->symbol = NULL;
1917 /* Forward declarations for functions below, in the MD interface
1919 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
1920 static valueT create_unwind_entry (int);
1921 static void start_unwind_section (const segT, int);
1922 static void add_unwind_opcode (valueT, int);
1923 static void flush_pending_unwind (void);
1925 /* Directives: Data. */
1928 s_arm_elf_cons (int nbytes)
1932 #ifdef md_flush_pending_output
1933 md_flush_pending_output ();
1936 if (is_it_end_of_statement ())
1938 demand_empty_rest_of_line ();
1942 #ifdef md_cons_align
1943 md_cons_align (nbytes);
1946 mapping_state (MAP_DATA);
1950 char *base = input_line_pointer;
1954 if (exp.X_op != O_symbol)
1955 emit_expr (&exp, (unsigned int) nbytes);
1958 char *before_reloc = input_line_pointer;
1959 reloc = parse_reloc (&input_line_pointer);
1962 as_bad (_("unrecognized relocation suffix"));
1963 ignore_rest_of_line ();
1966 else if (reloc == BFD_RELOC_UNUSED)
1967 emit_expr (&exp, (unsigned int) nbytes);
1970 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
1971 int size = bfd_get_reloc_size (howto);
1974 as_bad ("%s relocations do not fit in %d bytes",
1975 howto->name, nbytes);
1978 /* We've parsed an expression stopping at O_symbol.
1979 But there may be more expression left now that we
1980 have parsed the relocation marker. Parse it again.
1981 XXX Surely there is a cleaner way to do this. */
1982 char *p = input_line_pointer;
1984 char *save_buf = alloca (input_line_pointer - base);
1985 memcpy (save_buf, base, input_line_pointer - base);
1986 memmove (base + (input_line_pointer - before_reloc),
1987 base, before_reloc - base);
1989 input_line_pointer = base + (input_line_pointer-before_reloc);
1991 memcpy (base, save_buf, p - base);
1993 offset = nbytes - size;
1994 p = frag_more ((int) nbytes);
1995 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
1996 size, &exp, 0, reloc);
2001 while (*input_line_pointer++ == ',');
2003 /* Put terminator back into stream. */
2004 input_line_pointer --;
2005 demand_empty_rest_of_line ();
2009 /* Parse a .rel31 directive. */
2012 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2019 if (*input_line_pointer == '1')
2020 highbit = 0x80000000;
2021 else if (*input_line_pointer != '0')
2022 as_bad (_("expected 0 or 1"));
2024 input_line_pointer++;
2025 if (*input_line_pointer != ',')
2026 as_bad (_("missing comma"));
2027 input_line_pointer++;
2029 #ifdef md_flush_pending_output
2030 md_flush_pending_output ();
2033 #ifdef md_cons_align
2037 mapping_state (MAP_DATA);
2042 md_number_to_chars (p, highbit, 4);
2043 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
2044 BFD_RELOC_ARM_PREL31);
2046 demand_empty_rest_of_line ();
2049 /* Directives: AEABI stack-unwind tables. */
2051 /* Parse an unwind_fnstart directive. Simply records the current location. */
2054 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
2056 demand_empty_rest_of_line ();
2057 /* Mark the start of the function. */
2058 unwind.proc_start = expr_build_dot ();
2060 /* Reset the rest of the unwind info. */
2061 unwind.opcode_count = 0;
2062 unwind.table_entry = NULL;
2063 unwind.personality_routine = NULL;
2064 unwind.personality_index = -1;
2065 unwind.frame_size = 0;
2066 unwind.fp_offset = 0;
2069 unwind.sp_restored = 0;
2073 /* Parse a handlerdata directive. Creates the exception handling table entry
2074 for the function. */
2077 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
2079 demand_empty_rest_of_line ();
2080 if (unwind.table_entry)
2081 as_bad (_("dupicate .handlerdata directive"));
2083 create_unwind_entry (1);
2086 /* Parse an unwind_fnend directive. Generates the index table entry. */
2089 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
2095 demand_empty_rest_of_line ();
2097 /* Add eh table entry. */
2098 if (unwind.table_entry == NULL)
2099 val = create_unwind_entry (0);
2103 /* Add index table entry. This is two words. */
2104 start_unwind_section (unwind.saved_seg, 1);
2105 frag_align (2, 0, 0);
2106 record_alignment (now_seg, 2);
2108 ptr = frag_more (8);
2109 where = frag_now_fix () - 8;
2111 /* Self relative offset of the function start. */
2112 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
2113 BFD_RELOC_ARM_PREL31);
2115 /* Indicate dependency on EHABI-defined personality routines to the
2116 linker, if it hasn't been done already. */
2117 if (unwind.personality_index >= 0 && unwind.personality_index < 3
2118 && !(marked_pr_dependency & (1 << unwind.personality_index)))
2120 static const char *const name[] = {
2121 "__aeabi_unwind_cpp_pr0",
2122 "__aeabi_unwind_cpp_pr1",
2123 "__aeabi_unwind_cpp_pr2"
2125 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
2126 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
2127 marked_pr_dependency |= 1 << unwind.personality_index;
2128 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
2129 = marked_pr_dependency;
2133 /* Inline exception table entry. */
2134 md_number_to_chars (ptr + 4, val, 4);
2136 /* Self relative offset of the table entry. */
2137 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
2138 BFD_RELOC_ARM_PREL31);
2140 /* Restore the original section. */
2141 subseg_set (unwind.saved_seg, unwind.saved_subseg);
2145 /* Parse an unwind_cantunwind directive. */
2148 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
2150 demand_empty_rest_of_line ();
2151 if (unwind.personality_routine || unwind.personality_index != -1)
2152 as_bad (_("personality routine specified for cantunwind frame"));
2154 unwind.personality_index = -2;
2158 /* Parse a personalityindex directive. */
2161 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
2165 if (unwind.personality_routine || unwind.personality_index != -1)
2166 as_bad (_("duplicate .personalityindex directive"));
2170 if (exp.X_op != O_constant
2171 || exp.X_add_number < 0 || exp.X_add_number > 15)
2173 as_bad (_("bad personality routine number"));
2174 ignore_rest_of_line ();
2178 unwind.personality_index = exp.X_add_number;
2180 demand_empty_rest_of_line ();
2184 /* Parse a personality directive. */
2187 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
2191 if (unwind.personality_routine || unwind.personality_index != -1)
2192 as_bad (_("duplicate .personality directive"));
2194 name = input_line_pointer;
2195 c = get_symbol_end ();
2196 p = input_line_pointer;
2197 unwind.personality_routine = symbol_find_or_make (name);
2199 demand_empty_rest_of_line ();
2203 /* Parse a directive saving core registers. */
2206 s_arm_unwind_save_core (void)
2212 range = parse_reg_list (&input_line_pointer);
2215 as_bad (_("expected register list"));
2216 ignore_rest_of_line ();
2220 demand_empty_rest_of_line ();
2222 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2223 into .unwind_save {..., sp...}. We aren't bothered about the value of
2224 ip because it is clobbered by calls. */
2225 if (unwind.sp_restored && unwind.fp_reg == 12
2226 && (range & 0x3000) == 0x1000)
2228 unwind.opcode_count--;
2229 unwind.sp_restored = 0;
2230 range = (range | 0x2000) & ~0x1000;
2231 unwind.pending_offset = 0;
2234 /* See if we can use the short opcodes. These pop a block of upto 8
2235 registers starting with r4, plus maybe r14. */
2236 for (n = 0; n < 8; n++)
2238 /* Break at the first non-saved register. */
2239 if ((range & (1 << (n + 4))) == 0)
2242 /* See if there are any other bits set. */
2243 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
2245 /* Use the long form. */
2246 op = 0x8000 | ((range >> 4) & 0xfff);
2247 add_unwind_opcode (op, 2);
2251 /* Use the short form. */
2253 op = 0xa8; /* Pop r14. */
2255 op = 0xa0; /* Do not pop r14. */
2257 add_unwind_opcode (op, 1);
2263 op = 0xb100 | (range & 0xf);
2264 add_unwind_opcode (op, 2);
2267 /* Record the number of bytes pushed. */
2268 for (n = 0; n < 16; n++)
2270 if (range & (1 << n))
2271 unwind.frame_size += 4;
2276 /* Parse a directive saving FPA registers. */
2279 s_arm_unwind_save_fpa (int reg)
2285 /* Get Number of registers to transfer. */
2286 if (skip_past_comma (&input_line_pointer) != FAIL)
2289 exp.X_op = O_illegal;
2291 if (exp.X_op != O_constant)
2293 as_bad (_("expected , <constant>"));
2294 ignore_rest_of_line ();
2298 num_regs = exp.X_add_number;
2300 if (num_regs < 1 || num_regs > 4)
2302 as_bad (_("number of registers must be in the range [1:4]"));
2303 ignore_rest_of_line ();
2307 demand_empty_rest_of_line ();
2312 op = 0xb4 | (num_regs - 1);
2313 add_unwind_opcode (op, 1);
2318 op = 0xc800 | (reg << 4) | (num_regs - 1);
2319 add_unwind_opcode (op, 2);
2321 unwind.frame_size += num_regs * 12;
2325 /* Parse a directive saving VFP registers. */
2328 s_arm_unwind_save_vfp (void)
2334 count = parse_vfp_reg_list (&input_line_pointer, ®, 1);
2337 as_bad (_("expected register list"));
2338 ignore_rest_of_line ();
2342 demand_empty_rest_of_line ();
2347 op = 0xb8 | (count - 1);
2348 add_unwind_opcode (op, 1);
2353 op = 0xb300 | (reg << 4) | (count - 1);
2354 add_unwind_opcode (op, 2);
2356 unwind.frame_size += count * 8 + 4;
2360 /* Parse a directive saving iWMMXt data registers. */
2363 s_arm_unwind_save_mmxwr (void)
2371 if (*input_line_pointer == '{')
2372 input_line_pointer++;
2376 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2380 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2385 as_tsktsk (_("register list not in ascending order"));
2388 if (*input_line_pointer == '-')
2390 input_line_pointer++;
2391 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2394 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2397 else if (reg >= hi_reg)
2399 as_bad (_("bad register range"));
2402 for (; reg < hi_reg; reg++)
2406 while (skip_past_comma (&input_line_pointer) != FAIL);
2408 if (*input_line_pointer == '}')
2409 input_line_pointer++;
2411 demand_empty_rest_of_line ();
2413 /* Generate any deferred opcodes becuuse we're going to be looking at
2415 flush_pending_unwind ();
2417 for (i = 0; i < 16; i++)
2419 if (mask & (1 << i))
2420 unwind.frame_size += 8;
2423 /* Attempt to combine with a previous opcode. We do this because gcc
2424 likes to output separate unwind directives for a single block of
2426 if (unwind.opcode_count > 0)
2428 i = unwind.opcodes[unwind.opcode_count - 1];
2429 if ((i & 0xf8) == 0xc0)
2432 /* Only merge if the blocks are contiguous. */
2435 if ((mask & 0xfe00) == (1 << 9))
2437 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
2438 unwind.opcode_count--;
2441 else if (i == 6 && unwind.opcode_count >= 2)
2443 i = unwind.opcodes[unwind.opcode_count - 2];
2447 op = 0xffff << (reg - 1);
2449 || ((mask & op) == (1u << (reg - 1))))
2451 op = (1 << (reg + i + 1)) - 1;
2452 op &= ~((1 << reg) - 1);
2454 unwind.opcode_count -= 2;
2461 /* We want to generate opcodes in the order the registers have been
2462 saved, ie. descending order. */
2463 for (reg = 15; reg >= -1; reg--)
2465 /* Save registers in blocks. */
2467 || !(mask & (1 << reg)))
2469 /* We found an unsaved reg. Generate opcodes to save the
2470 preceeding block. */
2476 op = 0xc0 | (hi_reg - 10);
2477 add_unwind_opcode (op, 1);
2482 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
2483 add_unwind_opcode (op, 2);
2492 ignore_rest_of_line ();
2496 s_arm_unwind_save_mmxwcg (void)
2503 if (*input_line_pointer == '{')
2504 input_line_pointer++;
2508 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2512 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2518 as_tsktsk (_("register list not in ascending order"));
2521 if (*input_line_pointer == '-')
2523 input_line_pointer++;
2524 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2527 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2530 else if (reg >= hi_reg)
2532 as_bad (_("bad register range"));
2535 for (; reg < hi_reg; reg++)
2539 while (skip_past_comma (&input_line_pointer) != FAIL);
2541 if (*input_line_pointer == '}')
2542 input_line_pointer++;
2544 demand_empty_rest_of_line ();
2546 /* Generate any deferred opcodes becuuse we're going to be looking at
2548 flush_pending_unwind ();
2550 for (reg = 0; reg < 16; reg++)
2552 if (mask & (1 << reg))
2553 unwind.frame_size += 4;
2556 add_unwind_opcode (op, 2);
2559 ignore_rest_of_line ();
2563 /* Parse an unwind_save directive. */
2566 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
2569 struct reg_entry *reg;
2570 bfd_boolean had_brace = FALSE;
2572 /* Figure out what sort of save we have. */
2573 peek = input_line_pointer;
2581 reg = arm_reg_parse_multi (&peek);
2585 as_bad (_("register expected"));
2586 ignore_rest_of_line ();
2595 as_bad (_("FPA .unwind_save does not take a register list"));
2596 ignore_rest_of_line ();
2599 s_arm_unwind_save_fpa (reg->number);
2602 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
2603 case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
2604 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
2605 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
2608 as_bad (_(".unwind_save does not support this kind of register"));
2609 ignore_rest_of_line ();
2614 /* Parse an unwind_movsp directive. */
2617 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
2622 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2625 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
2626 ignore_rest_of_line ();
2629 demand_empty_rest_of_line ();
2631 if (reg == REG_SP || reg == REG_PC)
2633 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2637 if (unwind.fp_reg != REG_SP)
2638 as_bad (_("unexpected .unwind_movsp directive"));
2640 /* Generate opcode to restore the value. */
2642 add_unwind_opcode (op, 1);
2644 /* Record the information for later. */
2645 unwind.fp_reg = reg;
2646 unwind.fp_offset = unwind.frame_size;
2647 unwind.sp_restored = 1;
2650 /* Parse an unwind_pad directive. */
2653 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
2657 if (immediate_for_directive (&offset) == FAIL)
2662 as_bad (_("stack increment must be multiple of 4"));
2663 ignore_rest_of_line ();
2667 /* Don't generate any opcodes, just record the details for later. */
2668 unwind.frame_size += offset;
2669 unwind.pending_offset += offset;
2671 demand_empty_rest_of_line ();
2674 /* Parse an unwind_setfp directive. */
2677 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
2683 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2684 if (skip_past_comma (&input_line_pointer) == FAIL)
2687 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2689 if (fp_reg == FAIL || sp_reg == FAIL)
2691 as_bad (_("expected <reg>, <reg>"));
2692 ignore_rest_of_line ();
2696 /* Optional constant. */
2697 if (skip_past_comma (&input_line_pointer) != FAIL)
2699 if (immediate_for_directive (&offset) == FAIL)
2705 demand_empty_rest_of_line ();
2707 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
2709 as_bad (_("register must be either sp or set by a previous"
2710 "unwind_movsp directive"));
2714 /* Don't generate any opcodes, just record the information for later. */
2715 unwind.fp_reg = fp_reg;
2718 unwind.fp_offset = unwind.frame_size - offset;
2720 unwind.fp_offset -= offset;
2723 /* Parse an unwind_raw directive. */
2726 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
2729 /* This is an arbitary limit. */
2730 unsigned char op[16];
2734 if (exp.X_op == O_constant
2735 && skip_past_comma (&input_line_pointer) != FAIL)
2737 unwind.frame_size += exp.X_add_number;
2741 exp.X_op = O_illegal;
2743 if (exp.X_op != O_constant)
2745 as_bad (_("expected <offset>, <opcode>"));
2746 ignore_rest_of_line ();
2752 /* Parse the opcode. */
2757 as_bad (_("unwind opcode too long"));
2758 ignore_rest_of_line ();
2760 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
2762 as_bad (_("invalid unwind opcode"));
2763 ignore_rest_of_line ();
2766 op[count++] = exp.X_add_number;
2768 /* Parse the next byte. */
2769 if (skip_past_comma (&input_line_pointer) == FAIL)
2775 /* Add the opcode bytes in reverse order. */
2777 add_unwind_opcode (op[count], 1);
2779 demand_empty_rest_of_line ();
2781 #endif /* OBJ_ELF */
2783 /* This table describes all the machine specific pseudo-ops the assembler
2784 has to support. The fields are:
2785 pseudo-op name without dot
2786 function to call to execute this pseudo-op
2787 Integer arg to pass to the function. */
2789 const pseudo_typeS md_pseudo_table[] =
2791 /* Never called because '.req' does not start a line. */
2792 { "req", s_req, 0 },
2793 { "unreq", s_unreq, 0 },
2794 { "bss", s_bss, 0 },
2795 { "align", s_align, 0 },
2796 { "arm", s_arm, 0 },
2797 { "thumb", s_thumb, 0 },
2798 { "code", s_code, 0 },
2799 { "force_thumb", s_force_thumb, 0 },
2800 { "thumb_func", s_thumb_func, 0 },
2801 { "thumb_set", s_thumb_set, 0 },
2802 { "even", s_even, 0 },
2803 { "ltorg", s_ltorg, 0 },
2804 { "pool", s_ltorg, 0 },
2805 { "syntax", s_syntax, 0 },
2807 { "word", s_arm_elf_cons, 4 },
2808 { "long", s_arm_elf_cons, 4 },
2809 { "rel31", s_arm_rel31, 0 },
2810 { "fnstart", s_arm_unwind_fnstart, 0 },
2811 { "fnend", s_arm_unwind_fnend, 0 },
2812 { "cantunwind", s_arm_unwind_cantunwind, 0 },
2813 { "personality", s_arm_unwind_personality, 0 },
2814 { "personalityindex", s_arm_unwind_personalityindex, 0 },
2815 { "handlerdata", s_arm_unwind_handlerdata, 0 },
2816 { "save", s_arm_unwind_save, 0 },
2817 { "movsp", s_arm_unwind_movsp, 0 },
2818 { "pad", s_arm_unwind_pad, 0 },
2819 { "setfp", s_arm_unwind_setfp, 0 },
2820 { "unwind_raw", s_arm_unwind_raw, 0 },
2824 { "extend", float_cons, 'x' },
2825 { "ldouble", float_cons, 'x' },
2826 { "packed", float_cons, 'p' },
2830 /* Parser functions used exclusively in instruction operands. */
2832 /* Generic immediate-value read function for use in insn parsing.
2833 STR points to the beginning of the immediate (the leading #);
2834 VAL receives the value; if the value is outside [MIN, MAX]
2835 issue an error. PREFIX_OPT is true if the immediate prefix is
2839 parse_immediate (char **str, int *val, int min, int max,
2840 bfd_boolean prefix_opt)
2843 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
2844 if (exp.X_op != O_constant)
2846 inst.error = _("constant expression required");
2850 if (exp.X_add_number < min || exp.X_add_number > max)
2852 inst.error = _("immediate value out of range");
2856 *val = exp.X_add_number;
2860 /* Returns the pseudo-register number of an FPA immediate constant,
2861 or FAIL if there isn't a valid constant here. */
2864 parse_fpa_immediate (char ** str)
2866 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2872 /* First try and match exact strings, this is to guarantee
2873 that some formats will work even for cross assembly. */
2875 for (i = 0; fp_const[i]; i++)
2877 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2881 *str += strlen (fp_const[i]);
2882 if (is_end_of_line[(unsigned char) **str])
2888 /* Just because we didn't get a match doesn't mean that the constant
2889 isn't valid, just that it is in a format that we don't
2890 automatically recognize. Try parsing it with the standard
2891 expression routines. */
2893 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2895 /* Look for a raw floating point number. */
2896 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2897 && is_end_of_line[(unsigned char) *save_in])
2899 for (i = 0; i < NUM_FLOAT_VALS; i++)
2901 for (j = 0; j < MAX_LITTLENUMS; j++)
2903 if (words[j] != fp_values[i][j])
2907 if (j == MAX_LITTLENUMS)
2915 /* Try and parse a more complex expression, this will probably fail
2916 unless the code uses a floating point prefix (eg "0f"). */
2917 save_in = input_line_pointer;
2918 input_line_pointer = *str;
2919 if (expression (&exp) == absolute_section
2920 && exp.X_op == O_big
2921 && exp.X_add_number < 0)
2923 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2925 if (gen_to_words (words, 5, (long) 15) == 0)
2927 for (i = 0; i < NUM_FLOAT_VALS; i++)
2929 for (j = 0; j < MAX_LITTLENUMS; j++)
2931 if (words[j] != fp_values[i][j])
2935 if (j == MAX_LITTLENUMS)
2937 *str = input_line_pointer;
2938 input_line_pointer = save_in;
2945 *str = input_line_pointer;
2946 input_line_pointer = save_in;
2947 inst.error = _("invalid FPA immediate expression");
2951 /* Shift operands. */
2954 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
2957 struct asm_shift_name
2960 enum shift_kind kind;
2963 /* Third argument to parse_shift. */
2964 enum parse_shift_mode
2966 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
2967 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
2968 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
2969 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
2970 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
2973 /* Parse a <shift> specifier on an ARM data processing instruction.
2974 This has three forms:
2976 (LSL|LSR|ASL|ASR|ROR) Rs
2977 (LSL|LSR|ASL|ASR|ROR) #imm
2980 Note that ASL is assimilated to LSL in the instruction encoding, and
2981 RRX to ROR #0 (which cannot be written as such). */
2984 parse_shift (char **str, int i, enum parse_shift_mode mode)
2986 const struct asm_shift_name *shift_name;
2987 enum shift_kind shift;
2992 for (p = *str; ISALPHA (*p); p++)
2997 inst.error = _("shift expression expected");
3001 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
3003 if (shift_name == NULL)
3005 inst.error = _("shift expression expected");
3009 shift = shift_name->kind;
3013 case NO_SHIFT_RESTRICT:
3014 case SHIFT_IMMEDIATE: break;
3016 case SHIFT_LSL_OR_ASR_IMMEDIATE:
3017 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
3019 inst.error = _("'LSL' or 'ASR' required");
3024 case SHIFT_LSL_IMMEDIATE:
3025 if (shift != SHIFT_LSL)
3027 inst.error = _("'LSL' required");
3032 case SHIFT_ASR_IMMEDIATE:
3033 if (shift != SHIFT_ASR)
3035 inst.error = _("'ASR' required");
3043 if (shift != SHIFT_RRX)
3045 /* Whitespace can appear here if the next thing is a bare digit. */
3046 skip_whitespace (p);
3048 if (mode == NO_SHIFT_RESTRICT
3049 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3051 inst.operands[i].imm = reg;
3052 inst.operands[i].immisreg = 1;
3054 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3057 inst.operands[i].shift_kind = shift;
3058 inst.operands[i].shifted = 1;
3063 /* Parse a <shifter_operand> for an ARM data processing instruction:
3066 #<immediate>, <rotate>
3070 where <shift> is defined by parse_shift above, and <rotate> is a
3071 multiple of 2 between 0 and 30. Validation of immediate operands
3072 is deferred to md_apply_fix. */
3075 parse_shifter_operand (char **str, int i)
3080 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
3082 inst.operands[i].reg = value;
3083 inst.operands[i].isreg = 1;
3085 /* parse_shift will override this if appropriate */
3086 inst.reloc.exp.X_op = O_constant;
3087 inst.reloc.exp.X_add_number = 0;
3089 if (skip_past_comma (str) == FAIL)
3092 /* Shift operation on register. */
3093 return parse_shift (str, i, NO_SHIFT_RESTRICT);
3096 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
3099 if (skip_past_comma (str) == SUCCESS)
3101 /* #x, y -- ie explicit rotation by Y. */
3102 if (my_get_expression (&expr, str, GE_NO_PREFIX))
3105 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
3107 inst.error = _("constant expression expected");
3111 value = expr.X_add_number;
3112 if (value < 0 || value > 30 || value % 2 != 0)
3114 inst.error = _("invalid rotation");
3117 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
3119 inst.error = _("invalid constant");
3123 /* Convert to decoded value. md_apply_fix will put it back. */
3124 inst.reloc.exp.X_add_number
3125 = (((inst.reloc.exp.X_add_number << (32 - value))
3126 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
3129 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3130 inst.reloc.pc_rel = 0;
3134 /* Parse all forms of an ARM address expression. Information is written
3135 to inst.operands[i] and/or inst.reloc.
3137 Preindexed addressing (.preind=1):
3139 [Rn, #offset] .reg=Rn .reloc.exp=offset
3140 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3141 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3142 .shift_kind=shift .reloc.exp=shift_imm
3144 These three may have a trailing ! which causes .writeback to be set also.
3146 Postindexed addressing (.postind=1, .writeback=1):
3148 [Rn], #offset .reg=Rn .reloc.exp=offset
3149 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3150 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3151 .shift_kind=shift .reloc.exp=shift_imm
3153 Unindexed addressing (.preind=0, .postind=0):
3155 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3159 [Rn]{!} shorthand for [Rn,#0]{!}
3160 =immediate .isreg=0 .reloc.exp=immediate
3161 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3163 It is the caller's responsibility to check for addressing modes not
3164 supported by the instruction, and to set inst.reloc.type. */
3167 parse_address (char **str, int i)
3172 if (skip_past_char (&p, '[') == FAIL)
3174 if (skip_past_char (&p, '=') == FAIL)
3176 /* bare address - translate to PC-relative offset */
3177 inst.reloc.pc_rel = 1;
3178 inst.operands[i].reg = REG_PC;
3179 inst.operands[i].isreg = 1;
3180 inst.operands[i].preind = 1;
3182 /* else a load-constant pseudo op, no special treatment needed here */
3184 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
3191 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3193 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3196 inst.operands[i].reg = reg;
3197 inst.operands[i].isreg = 1;
3199 if (skip_past_comma (&p) == SUCCESS)
3201 inst.operands[i].preind = 1;
3204 else if (*p == '-') p++, inst.operands[i].negative = 1;
3206 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3208 inst.operands[i].imm = reg;
3209 inst.operands[i].immisreg = 1;
3211 if (skip_past_comma (&p) == SUCCESS)
3212 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3217 if (inst.operands[i].negative)
3219 inst.operands[i].negative = 0;
3222 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3227 if (skip_past_char (&p, ']') == FAIL)
3229 inst.error = _("']' expected");
3233 if (skip_past_char (&p, '!') == SUCCESS)
3234 inst.operands[i].writeback = 1;
3236 else if (skip_past_comma (&p) == SUCCESS)
3238 if (skip_past_char (&p, '{') == SUCCESS)
3240 /* [Rn], {expr} - unindexed, with option */
3241 if (parse_immediate (&p, &inst.operands[i].imm,
3242 0, 255, TRUE) == FAIL)
3245 if (skip_past_char (&p, '}') == FAIL)
3247 inst.error = _("'}' expected at end of 'option' field");
3250 if (inst.operands[i].preind)
3252 inst.error = _("cannot combine index with option");
3260 inst.operands[i].postind = 1;
3261 inst.operands[i].writeback = 1;
3263 if (inst.operands[i].preind)
3265 inst.error = _("cannot combine pre- and post-indexing");
3270 else if (*p == '-') p++, inst.operands[i].negative = 1;
3272 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3274 inst.operands[i].imm = reg;
3275 inst.operands[i].immisreg = 1;
3277 if (skip_past_comma (&p) == SUCCESS)
3278 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3283 if (inst.operands[i].negative)
3285 inst.operands[i].negative = 0;
3288 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3294 /* If at this point neither .preind nor .postind is set, we have a
3295 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3296 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
3298 inst.operands[i].preind = 1;
3299 inst.reloc.exp.X_op = O_constant;
3300 inst.reloc.exp.X_add_number = 0;
3306 /* Miscellaneous. */
3308 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3309 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3311 parse_psr (char **str)
3314 unsigned long psr_field;
3316 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3317 feature for ease of use and backwards compatibility. */
3319 if (*p == 's' || *p == 'S')
3320 psr_field = SPSR_BIT;
3321 else if (*p == 'c' || *p == 'C')
3327 if (strncasecmp (p, "PSR", 3) != 0)
3333 /* A suffix follows. */
3334 const struct asm_psr *psr;
3342 while (ISALNUM (*p) || *p == '_');
3344 psr = hash_find_n (arm_psr_hsh, start, p - start);
3348 psr_field |= psr->field;
3353 goto error; /* Garbage after "[CS]PSR". */
3355 psr_field |= (PSR_c | PSR_f);
3361 inst.error = _("flag for {c}psr instruction expected");
3365 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3366 value suitable for splatting into the AIF field of the instruction. */
3369 parse_cps_flags (char **str)
3378 case '\0': case ',':
3381 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
3382 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
3383 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
3386 inst.error = _("unrecognized CPS flag");
3391 if (saw_a_flag == 0)
3393 inst.error = _("missing CPS flags");
3401 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3402 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3405 parse_endian_specifier (char **str)
3410 if (strncasecmp (s, "BE", 2))
3412 else if (strncasecmp (s, "LE", 2))
3416 inst.error = _("valid endian specifiers are be or le");
3420 if (ISALNUM (s[2]) || s[2] == '_')
3422 inst.error = _("valid endian specifiers are be or le");
3427 return little_endian;
3430 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3431 value suitable for poking into the rotate field of an sxt or sxta
3432 instruction, or FAIL on error. */
3435 parse_ror (char **str)
3440 if (strncasecmp (s, "ROR", 3) == 0)
3444 inst.error = _("missing rotation field after comma");
3448 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
3453 case 0: *str = s; return 0x0;
3454 case 8: *str = s; return 0x1;
3455 case 16: *str = s; return 0x2;
3456 case 24: *str = s; return 0x3;
3459 inst.error = _("rotation can only be 0, 8, 16, or 24");
3464 /* Parse a conditional code (from conds[] below). The value returned is in the
3465 range 0 .. 14, or FAIL. */
3467 parse_cond (char **str)
3470 const struct asm_cond *c;
3473 while (ISALPHA (*q))
3476 c = hash_find_n (arm_cond_hsh, p, q - p);
3479 inst.error = _("condition required");
3487 /* Matcher codes for parse_operands. */
3488 enum operand_parse_code
3490 OP_stop, /* end of line */
3492 OP_RR, /* ARM register */
3493 OP_RRnpc, /* ARM register, not r15 */
3494 OP_RRnpcb, /* ARM register, not r15, in square brackets */
3495 OP_RRw, /* ARM register, not r15, optional trailing ! */
3496 OP_RCP, /* Coprocessor number */
3497 OP_RCN, /* Coprocessor register */
3498 OP_RF, /* FPA register */
3499 OP_RVS, /* VFP single precision register */
3500 OP_RVD, /* VFP double precision register */
3501 OP_RVC, /* VFP control register */
3502 OP_RMF, /* Maverick F register */
3503 OP_RMD, /* Maverick D register */
3504 OP_RMFX, /* Maverick FX register */
3505 OP_RMDX, /* Maverick DX register */
3506 OP_RMAX, /* Maverick AX register */
3507 OP_RMDS, /* Maverick DSPSC register */
3508 OP_RIWR, /* iWMMXt wR register */
3509 OP_RIWC, /* iWMMXt wC register */
3510 OP_RIWG, /* iWMMXt wCG register */
3511 OP_RXA, /* XScale accumulator register */
3513 OP_REGLST, /* ARM register list */
3514 OP_VRSLST, /* VFP single-precision register list */
3515 OP_VRDLST, /* VFP double-precision register list */
3517 OP_I7, /* immediate value 0 .. 7 */
3518 OP_I15, /* 0 .. 15 */
3519 OP_I16, /* 1 .. 16 */
3520 OP_I31, /* 0 .. 31 */
3521 OP_I31w, /* 0 .. 31, optional trailing ! */
3522 OP_I32, /* 1 .. 32 */
3523 OP_I63s, /* -64 .. 63 */
3524 OP_I255, /* 0 .. 255 */
3525 OP_Iffff, /* 0 .. 65535 */
3527 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
3528 OP_I7b, /* 0 .. 7 */
3529 OP_I15b, /* 0 .. 15 */
3530 OP_I31b, /* 0 .. 31 */
3532 OP_SH, /* shifter operand */
3533 OP_ADDR, /* Memory address expression (any mode) */
3534 OP_EXP, /* arbitrary expression */
3535 OP_EXPi, /* same, with optional immediate prefix */
3536 OP_EXPr, /* same, with optional relocation suffix */
3538 OP_CPSF, /* CPS flags */
3539 OP_ENDI, /* Endianness specifier */
3540 OP_PSR, /* CPSR/SPSR mask for msr */
3541 OP_COND, /* conditional code */
3543 OP_RRnpc_I0, /* ARM register or literal 0 */
3544 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
3545 OP_RR_EXi, /* ARM register or expression with imm prefix */
3546 OP_RF_IF, /* FPA register or immediate */
3547 OP_RIWR_RIWC, /* iWMMXt R or C reg */
3549 /* Optional operands. */
3550 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
3551 OP_oI31b, /* 0 .. 31 */
3552 OP_oIffffb, /* 0 .. 65535 */
3553 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
3555 OP_oRR, /* ARM register */
3556 OP_oRRnpc, /* ARM register, not the PC */
3557 OP_oSHll, /* LSL immediate */
3558 OP_oSHar, /* ASR immediate */
3559 OP_oSHllar, /* LSL or ASR immediate */
3560 OP_oROR, /* ROR 0/8/16/24 */
3562 OP_FIRST_OPTIONAL = OP_oI7b
3565 /* Generic instruction operand parser. This does no encoding and no
3566 semantic validation; it merely squirrels values away in the inst
3567 structure. Returns SUCCESS or FAIL depending on whether the
3568 specified grammar matched. */
3570 parse_operands (char *str, const char *pattern)
3572 unsigned const char *upat = pattern;
3573 char *backtrack_pos = 0;
3574 const char *backtrack_error = 0;
3575 int i, val, backtrack_index = 0;
3577 #define po_char_or_fail(chr) do { \
3578 if (skip_past_char (&str, chr) == FAIL) \
3582 #define po_reg_or_fail(regtype) do { \
3583 val = arm_reg_parse (&str, regtype); \
3586 inst.error = _(reg_expected_msgs[regtype]); \
3589 inst.operands[i].reg = val; \
3590 inst.operands[i].isreg = 1; \
3593 #define po_reg_or_goto(regtype, label) do { \
3594 val = arm_reg_parse (&str, regtype); \
3598 inst.operands[i].reg = val; \
3599 inst.operands[i].isreg = 1; \
3602 #define po_imm_or_fail(min, max, popt) do { \
3603 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3605 inst.operands[i].imm = val; \
3608 #define po_misc_or_fail(expr) do { \
3613 skip_whitespace (str);
3615 for (i = 0; upat[i] != OP_stop; i++)
3617 if (upat[i] >= OP_FIRST_OPTIONAL)
3619 /* Remember where we are in case we need to backtrack. */
3620 assert (!backtrack_pos);
3621 backtrack_pos = str;
3622 backtrack_error = inst.error;
3623 backtrack_index = i;
3627 po_char_or_fail (',');
3635 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
3636 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
3637 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
3638 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
3639 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
3640 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
3641 case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
3642 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
3643 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
3644 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
3645 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
3646 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
3647 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
3648 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
3649 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
3650 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
3651 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
3654 po_char_or_fail ('[');
3655 po_reg_or_fail (REG_TYPE_RN);
3656 po_char_or_fail (']');
3660 po_reg_or_fail (REG_TYPE_RN);
3661 if (skip_past_char (&str, '!') == SUCCESS)
3662 inst.operands[i].writeback = 1;
3666 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
3667 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
3668 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
3669 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
3670 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
3671 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
3672 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
3673 case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
3675 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
3677 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
3678 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
3680 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
3681 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
3683 /* Immediate variants */
3685 po_char_or_fail ('{');
3686 po_imm_or_fail (0, 255, TRUE);
3687 po_char_or_fail ('}');
3691 /* The expression parser chokes on a trailing !, so we have
3692 to find it first and zap it. */
3695 while (*s && *s != ',')
3700 inst.operands[i].writeback = 1;
3702 po_imm_or_fail (0, 31, TRUE);
3710 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3715 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3720 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3722 if (inst.reloc.exp.X_op == O_symbol)
3724 val = parse_reloc (&str);
3727 inst.error = _("unrecognized relocation suffix");
3730 else if (val != BFD_RELOC_UNUSED)
3732 inst.operands[i].imm = val;
3733 inst.operands[i].hasreloc = 1;
3738 /* Register or expression */
3739 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
3740 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
3742 /* Register or immediate */
3743 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
3744 I0: po_imm_or_fail (0, 0, FALSE); break;
3746 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
3748 if (!is_immediate_prefix (*str))
3751 val = parse_fpa_immediate (&str);
3754 /* FPA immediates are encoded as registers 8-15.
3755 parse_fpa_immediate has already applied the offset. */
3756 inst.operands[i].reg = val;
3757 inst.operands[i].isreg = 1;
3760 /* Two kinds of register */
3763 struct reg_entry *rege = arm_reg_parse_multi (&str);
3764 if (rege->type != REG_TYPE_MMXWR
3765 && rege->type != REG_TYPE_MMXWC
3766 && rege->type != REG_TYPE_MMXWCG)
3768 inst.error = _("iWMMXt data or control register expected");
3771 inst.operands[i].reg = rege->number;
3772 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
3777 case OP_CPSF: val = parse_cps_flags (&str); break;
3778 case OP_ENDI: val = parse_endian_specifier (&str); break;
3779 case OP_oROR: val = parse_ror (&str); break;
3780 case OP_PSR: val = parse_psr (&str); break;
3781 case OP_COND: val = parse_cond (&str); break;
3783 /* Register lists */
3785 val = parse_reg_list (&str);
3788 inst.operands[1].writeback = 1;
3794 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
3798 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
3801 /* Addressing modes */
3803 po_misc_or_fail (parse_address (&str, i));
3807 po_misc_or_fail (parse_shifter_operand (&str, i));
3811 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
3815 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
3819 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
3823 as_fatal ("unhandled operand code %d", upat[i]);
3826 /* Various value-based sanity checks and shared operations. We
3827 do not signal immediate failures for the register constraints;
3828 this allows a syntax error to take precedence. */
3836 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
3837 inst.error = BAD_PC;
3850 inst.operands[i].imm = val;
3857 /* If we get here, this operand was successfully parsed. */
3858 inst.operands[i].present = 1;
3862 inst.error = BAD_ARGS;
3868 /* Do not backtrack over a trailing optional argument that
3869 absorbed some text. We will only fail again, with the
3870 'garbage following instruction' error message, which is
3871 probably less helpful than the current one. */
3872 if (backtrack_index == i && backtrack_pos != str
3873 && upat[i+1] == OP_stop)
3876 /* Try again, skipping the optional argument at backtrack_pos. */
3877 str = backtrack_pos;
3878 inst.error = backtrack_error;
3879 inst.operands[backtrack_index].present = 0;
3880 i = backtrack_index;
3884 /* Check that we have parsed all the arguments. */
3885 if (*str != '\0' && !inst.error)
3886 inst.error = _("garbage following instruction");
3888 return inst.error ? FAIL : SUCCESS;
3891 #undef po_char_or_fail
3892 #undef po_reg_or_fail
3893 #undef po_reg_or_goto
3894 #undef po_imm_or_fail
3896 /* Shorthand macro for instruction encoding functions issuing errors. */
3897 #define constraint(expr, err) do { \
3905 /* Functions for operand encoding. ARM, then Thumb. */
3907 #define rotate_left(v, n) (v << n | v >> (32 - n))
3909 /* If VAL can be encoded in the immediate field of an ARM instruction,
3910 return the encoded form. Otherwise, return FAIL. */
3913 encode_arm_immediate (unsigned int val)
3917 for (i = 0; i < 32; i += 2)
3918 if ((a = rotate_left (val, i)) <= 0xff)
3919 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
3924 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
3925 return the encoded form. Otherwise, return FAIL. */
3927 encode_thumb32_immediate (unsigned int val)
3934 for (i = 0; i < 32; i++)
3936 a = rotate_left (val, i);
3937 if (a >= 128 && a <= 255)
3938 return (a & 0x7f) | (i << 7);
3942 if (val == ((a << 16) | a))
3944 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
3948 if (val == ((a << 16) | a))
3949 return 0x200 | (a >> 8);
3953 /* Encode a VFP SP register number into inst.instruction. */
3956 encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
3961 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
3965 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
3969 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
3977 /* Encode a <shift> in an ARM-format instruction. The immediate,
3978 if any, is handled by md_apply_fix. */
3980 encode_arm_shift (int i)
3982 if (inst.operands[i].shift_kind == SHIFT_RRX)
3983 inst.instruction |= SHIFT_ROR << 5;
3986 inst.instruction |= inst.operands[i].shift_kind << 5;
3987 if (inst.operands[i].immisreg)
3989 inst.instruction |= SHIFT_BY_REG;
3990 inst.instruction |= inst.operands[i].imm << 8;
3993 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
3998 encode_arm_shifter_operand (int i)
4000 if (inst.operands[i].isreg)
4002 inst.instruction |= inst.operands[i].reg;
4003 encode_arm_shift (i);
4006 inst.instruction |= INST_IMMEDIATE;
4009 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4011 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
4013 assert (inst.operands[i].isreg);
4014 inst.instruction |= inst.operands[i].reg << 16;
4016 if (inst.operands[i].preind)
4020 inst.error = _("instruction does not accept preindexed addressing");
4023 inst.instruction |= PRE_INDEX;
4024 if (inst.operands[i].writeback)
4025 inst.instruction |= WRITE_BACK;
4028 else if (inst.operands[i].postind)
4030 assert (inst.operands[i].writeback);
4032 inst.instruction |= WRITE_BACK;
4034 else /* unindexed - only for coprocessor */
4036 inst.error = _("instruction does not accept unindexed addressing");
4040 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
4041 && (((inst.instruction & 0x000f0000) >> 16)
4042 == ((inst.instruction & 0x0000f000) >> 12)))
4043 as_warn ((inst.instruction & LOAD_BIT)
4044 ? _("destination register same as write-back base")
4045 : _("source register same as write-back base"));
4048 /* inst.operands[i] was set up by parse_address. Encode it into an
4049 ARM-format mode 2 load or store instruction. If is_t is true,
4050 reject forms that cannot be used with a T instruction (i.e. not
4053 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
4055 encode_arm_addr_mode_common (i, is_t);
4057 if (inst.operands[i].immisreg)
4059 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
4060 inst.instruction |= inst.operands[i].imm;
4061 if (!inst.operands[i].negative)
4062 inst.instruction |= INDEX_UP;
4063 if (inst.operands[i].shifted)
4065 if (inst.operands[i].shift_kind == SHIFT_RRX)
4066 inst.instruction |= SHIFT_ROR << 5;
4069 inst.instruction |= inst.operands[i].shift_kind << 5;
4070 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4074 else /* immediate offset in inst.reloc */
4076 if (inst.reloc.type == BFD_RELOC_UNUSED)
4077 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4078 if (inst.reloc.pc_rel)
4079 inst.reloc.exp.X_add_number -= 8; /* pipeline offset */
4083 /* inst.operands[i] was set up by parse_address. Encode it into an
4084 ARM-format mode 3 load or store instruction. Reject forms that
4085 cannot be used with such instructions. If is_t is true, reject
4086 forms that cannot be used with a T instruction (i.e. not
4089 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
4091 if (inst.operands[i].immisreg && inst.operands[i].shifted)
4093 inst.error = _("instruction does not accept scaled register index");
4097 encode_arm_addr_mode_common (i, is_t);
4099 if (inst.operands[i].immisreg)
4101 inst.instruction |= inst.operands[i].imm;
4102 if (!inst.operands[i].negative)
4103 inst.instruction |= INDEX_UP;
4105 else /* immediate offset in inst.reloc */
4107 inst.instruction |= HWOFFSET_IMM;
4108 if (inst.reloc.type == BFD_RELOC_UNUSED)
4109 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4110 if (inst.reloc.pc_rel)
4111 inst.reloc.exp.X_add_number -= 8; /* pipeline offset */
4115 /* inst.operands[i] was set up by parse_address. Encode it into an
4116 ARM-format instruction. Reject all forms which cannot be encoded
4117 into a coprocessor load/store instruction. If wb_ok is false,
4118 reject use of writeback; if unind_ok is false, reject use of
4119 unindexed addressing. If reloc_override is not 0, use it instead
4120 of BFD_ARM_CP_OFF_IMM. */
4123 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
4125 inst.instruction |= inst.operands[i].reg << 16;
4127 assert (!(inst.operands[i].preind && inst.operands[i].postind));
4129 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
4131 assert (!inst.operands[i].writeback);
4134 inst.error = _("instruction does not support unindexed addressing");
4137 inst.instruction |= inst.operands[i].imm;
4138 inst.instruction |= INDEX_UP;
4142 if (inst.operands[i].preind)
4143 inst.instruction |= PRE_INDEX;
4145 if (inst.operands[i].writeback)
4147 if (inst.operands[i].reg == REG_PC)
4149 inst.error = _("pc may not be used with write-back");
4154 inst.error = _("instruction does not support writeback");
4157 inst.instruction |= WRITE_BACK;
4161 inst.reloc.type = reloc_override;
4163 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
4164 if (inst.reloc.pc_rel)
4165 inst.reloc.exp.X_add_number -= 8;
4169 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4170 Determine whether it can be performed with a move instruction; if
4171 it can, convert inst.instruction to that move instruction and
4172 return 1; if it can't, convert inst.instruction to a literal-pool
4173 load and return 0. If this is not a valid thing to do in the
4174 current context, set inst.error and return 1.
4176 inst.operands[i] describes the destination register. */
4179 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
4181 if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0)
4183 inst.error = _("invalid pseudo operation");
4186 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
4188 inst.error = _("constant expression expected");
4191 if (inst.reloc.exp.X_op == O_constant)
4195 if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
4197 /* This can be done with a mov(1) instruction. */
4198 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
4199 inst.instruction |= inst.reloc.exp.X_add_number;
4205 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
4208 /* This can be done with a mov instruction. */
4209 inst.instruction &= LITERAL_MASK;
4210 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4211 inst.instruction |= value & 0xfff;
4215 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
4218 /* This can be done with a mvn instruction. */
4219 inst.instruction &= LITERAL_MASK;
4220 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4221 inst.instruction |= value & 0xfff;
4227 if (add_to_lit_pool () == FAIL)
4229 inst.error = _("literal pool insertion failed");
4232 inst.operands[1].reg = REG_PC;
4233 inst.operands[1].isreg = 1;
4234 inst.operands[1].preind = 1;
4235 inst.reloc.pc_rel = 1;
4236 inst.reloc.type = (thumb_p
4237 ? BFD_RELOC_ARM_THUMB_OFFSET
4239 ? BFD_RELOC_ARM_HWLITERAL
4240 : BFD_RELOC_ARM_LITERAL));
4244 /* Functions for instruction encoding, sorted by subarchitecture.
4245 First some generics; their names are taken from the conventional
4246 bit positions for register arguments in ARM format instructions. */
4256 inst.instruction |= inst.operands[0].reg << 12;
4262 inst.instruction |= inst.operands[0].reg << 12;
4263 inst.instruction |= inst.operands[1].reg;
4269 inst.instruction |= inst.operands[0].reg << 12;
4270 inst.instruction |= inst.operands[1].reg << 16;
4276 inst.instruction |= inst.operands[0].reg << 16;
4277 inst.instruction |= inst.operands[1].reg << 12;
4283 inst.instruction |= inst.operands[0].reg << 12;
4284 inst.instruction |= inst.operands[1].reg;
4285 inst.instruction |= inst.operands[2].reg << 16;
4291 inst.instruction |= inst.operands[0].reg << 12;
4292 inst.instruction |= inst.operands[1].reg << 16;
4293 inst.instruction |= inst.operands[2].reg;
4299 inst.instruction |= inst.operands[0].reg;
4300 inst.instruction |= inst.operands[1].reg << 12;
4301 inst.instruction |= inst.operands[2].reg << 16;
4307 inst.instruction |= inst.operands[0].imm;
4313 inst.instruction |= inst.operands[0].reg << 12;
4314 encode_arm_cp_address (1, TRUE, TRUE, 0);
4317 /* ARM instructions, in alphabetical order by function name (except
4318 that wrapper functions appear immediately after the function they
4321 /* This is a pseudo-op of the form "adr rd, label" to be converted
4322 into a relative address of the form "add rd, pc, #label-.-8". */
4327 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4329 /* Frag hacking will turn this into a sub instruction if the offset turns
4330 out to be negative. */
4331 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4333 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
4335 inst.reloc.pc_rel = 1;
4338 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4339 into a relative address of the form:
4340 add rd, pc, #low(label-.-8)"
4341 add rd, rd, #high(label-.-8)" */
4346 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4348 /* Frag hacking will turn this into a sub instruction if the offset turns
4349 out to be negative. */
4350 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4352 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
4354 inst.reloc.pc_rel = 1;
4355 inst.size = INSN_SIZE * 2;
4361 if (!inst.operands[1].present)
4362 inst.operands[1].reg = inst.operands[0].reg;
4363 inst.instruction |= inst.operands[0].reg << 12;
4364 inst.instruction |= inst.operands[1].reg << 16;
4365 encode_arm_shifter_operand (2);
4371 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
4372 constraint (msb > 32, _("bit-field extends past end of register"));
4373 /* The instruction encoding stores the LSB and MSB,
4374 not the LSB and width. */
4375 inst.instruction |= inst.operands[0].reg << 12;
4376 inst.instruction |= inst.operands[1].imm << 7;
4377 inst.instruction |= (msb - 1) << 16;
4385 /* #0 in second position is alternative syntax for bfc, which is
4386 the same instruction but with REG_PC in the Rm field. */
4387 if (!inst.operands[1].isreg)
4388 inst.operands[1].reg = REG_PC;
4390 msb = inst.operands[2].imm + inst.operands[3].imm;
4391 constraint (msb > 32, _("bit-field extends past end of register"));
4392 /* The instruction encoding stores the LSB and MSB,
4393 not the LSB and width. */
4394 inst.instruction |= inst.operands[0].reg << 12;
4395 inst.instruction |= inst.operands[1].reg;
4396 inst.instruction |= inst.operands[2].imm << 7;
4397 inst.instruction |= (msb - 1) << 16;
4403 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
4404 _("bit-field extends past end of register"));
4405 inst.instruction |= inst.operands[0].reg << 12;
4406 inst.instruction |= inst.operands[1].reg;
4407 inst.instruction |= inst.operands[2].imm << 7;
4408 inst.instruction |= (inst.operands[3].imm - 1) << 16;
4411 /* ARM V5 breakpoint instruction (argument parse)
4412 BKPT <16 bit unsigned immediate>
4413 Instruction is not conditional.
4414 The bit pattern given in insns[] has the COND_ALWAYS condition,
4415 and it is an error if the caller tried to override that. */
4420 /* Top 12 of 16 bits to bits 19:8. */
4421 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
4423 /* Bottom 4 of 16 bits to bits 3:0. */
4424 inst.instruction |= inst.operands[0].imm & 0xf;
4428 encode_branch (int default_reloc)
4430 if (inst.operands[0].hasreloc)
4432 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
4433 _("the only suffix valid here is '(plt)'"));
4434 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4435 inst.reloc.pc_rel = 0;
4439 inst.reloc.type = default_reloc;
4440 inst.reloc.pc_rel = 1;
4447 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4450 /* ARM V5 branch-link-exchange instruction (argument parse)
4451 BLX <target_addr> ie BLX(1)
4452 BLX{<condition>} <Rm> ie BLX(2)
4453 Unfortunately, there are two different opcodes for this mnemonic.
4454 So, the insns[].value is not used, and the code here zaps values
4455 into inst.instruction.
4456 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4461 if (inst.operands[0].isreg)
4463 /* Arg is a register; the opcode provided by insns[] is correct.
4464 It is not illegal to do "blx pc", just useless. */
4465 if (inst.operands[0].reg == REG_PC)
4466 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4468 inst.instruction |= inst.operands[0].reg;
4472 /* Arg is an address; this instruction cannot be executed
4473 conditionally, and the opcode must be adjusted. */
4474 constraint (inst.cond != COND_ALWAYS, BAD_COND);
4475 inst.instruction = 0xfafffffe;
4476 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
4483 if (inst.operands[0].reg == REG_PC)
4484 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4486 inst.instruction |= inst.operands[0].reg;
4490 /* ARM v5TEJ. Jump to Jazelle code. */
4495 if (inst.operands[0].reg == REG_PC)
4496 as_tsktsk (_("use of r15 in bxj is not really useful"));
4498 inst.instruction |= inst.operands[0].reg;
4501 /* Co-processor data operation:
4502 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4503 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4507 inst.instruction |= inst.operands[0].reg << 8;
4508 inst.instruction |= inst.operands[1].imm << 20;
4509 inst.instruction |= inst.operands[2].reg << 12;
4510 inst.instruction |= inst.operands[3].reg << 16;
4511 inst.instruction |= inst.operands[4].reg;
4512 inst.instruction |= inst.operands[5].imm << 5;
4518 inst.instruction |= inst.operands[0].reg << 16;
4519 encode_arm_shifter_operand (1);
4522 /* Transfer between coprocessor and ARM registers.
4523 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4528 No special properties. */
4533 inst.instruction |= inst.operands[0].reg << 8;
4534 inst.instruction |= inst.operands[1].imm << 21;
4535 inst.instruction |= inst.operands[2].reg << 12;
4536 inst.instruction |= inst.operands[3].reg << 16;
4537 inst.instruction |= inst.operands[4].reg;
4538 inst.instruction |= inst.operands[5].imm << 5;
4541 /* Transfer between coprocessor register and pair of ARM registers.
4542 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4547 Two XScale instructions are special cases of these:
4549 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4550 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4552 Result unpredicatable if Rd or Rn is R15. */
4557 inst.instruction |= inst.operands[0].reg << 8;
4558 inst.instruction |= inst.operands[1].imm << 4;
4559 inst.instruction |= inst.operands[2].reg << 12;
4560 inst.instruction |= inst.operands[3].reg << 16;
4561 inst.instruction |= inst.operands[4].reg;
4567 inst.instruction |= inst.operands[0].imm << 6;
4568 inst.instruction |= inst.operands[1].imm;
4574 /* There is no IT instruction in ARM mode. We
4575 process it but do not generate code for it. */
4582 int base_reg = inst.operands[0].reg;
4583 int range = inst.operands[1].imm;
4585 inst.instruction |= base_reg << 16;
4586 inst.instruction |= range;
4588 if (inst.operands[1].writeback)
4589 inst.instruction |= LDM_TYPE_2_OR_3;
4591 if (inst.operands[0].writeback)
4593 inst.instruction |= WRITE_BACK;
4594 /* Check for unpredictable uses of writeback. */
4595 if (inst.instruction & LOAD_BIT)
4597 /* Not allowed in LDM type 2. */
4598 if ((inst.instruction & LDM_TYPE_2_OR_3)
4599 && ((range & (1 << REG_PC)) == 0))
4600 as_warn (_("writeback of base register is UNPREDICTABLE"));
4601 /* Only allowed if base reg not in list for other types. */
4602 else if (range & (1 << base_reg))
4603 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4607 /* Not allowed for type 2. */
4608 if (inst.instruction & LDM_TYPE_2_OR_3)
4609 as_warn (_("writeback of base register is UNPREDICTABLE"));
4610 /* Only allowed if base reg not in list, or first in list. */
4611 else if ((range & (1 << base_reg))
4612 && (range & ((1 << base_reg) - 1)))
4613 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4618 /* ARMv5TE load-consecutive (argument parse)
4627 constraint (inst.operands[0].reg % 2 != 0,
4628 _("first destination register must be even"));
4629 constraint (inst.operands[1].present
4630 && inst.operands[1].reg != inst.operands[0].reg + 1,
4631 _("can only load two consecutive registers"));
4632 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4633 constraint (!inst.operands[2].isreg, _("'[' expected"));
4635 if (!inst.operands[1].present)
4636 inst.operands[1].reg = inst.operands[0].reg + 1;
4638 if (inst.instruction & LOAD_BIT)
4640 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4641 register and the first register written; we have to diagnose
4642 overlap between the base and the second register written here. */
4644 if (inst.operands[2].reg == inst.operands[1].reg
4645 && (inst.operands[2].writeback || inst.operands[2].postind))
4646 as_warn (_("base register written back, and overlaps "
4647 "second destination register"));
4649 /* For an index-register load, the index register must not overlap the
4650 destination (even if not write-back). */
4651 else if (inst.operands[2].immisreg
4652 && (inst.operands[2].imm == inst.operands[0].reg
4653 || inst.operands[2].imm == inst.operands[1].reg))
4654 as_warn (_("index register overlaps destination register"));
4657 inst.instruction |= inst.operands[0].reg << 12;
4658 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
4664 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
4665 || inst.operands[1].postind || inst.operands[1].writeback
4666 || inst.operands[1].immisreg || inst.operands[1].shifted
4667 || inst.operands[1].negative,
4668 _("instruction does not accept this addressing mode"));
4670 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
4672 constraint (inst.reloc.exp.X_op != O_constant
4673 || inst.reloc.exp.X_add_number != 0,
4674 _("offset must be zero in ARM encoding"));
4676 inst.instruction |= inst.operands[0].reg << 12;
4677 inst.instruction |= inst.operands[1].reg << 16;
4678 inst.reloc.type = BFD_RELOC_UNUSED;
4684 constraint (inst.operands[0].reg % 2 != 0,
4685 _("even register required"));
4686 constraint (inst.operands[1].present
4687 && inst.operands[1].reg != inst.operands[0].reg + 1,
4688 _("can only load two consecutive registers"));
4689 /* If op 1 were present and equal to PC, this function wouldn't
4690 have been called in the first place. */
4691 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4693 inst.instruction |= inst.operands[0].reg << 12;
4694 inst.instruction |= inst.operands[2].reg << 16;
4700 inst.instruction |= inst.operands[0].reg << 12;
4701 if (!inst.operands[1].isreg)
4702 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
4704 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
4710 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4712 if (inst.operands[1].preind)
4714 constraint (inst.reloc.exp.X_op != O_constant ||
4715 inst.reloc.exp.X_add_number != 0,
4716 _("this instruction requires a post-indexed address"));
4718 inst.operands[1].preind = 0;
4719 inst.operands[1].postind = 1;
4720 inst.operands[1].writeback = 1;
4722 inst.instruction |= inst.operands[0].reg << 12;
4723 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
4726 /* Halfword and signed-byte load/store operations. */
4731 inst.instruction |= inst.operands[0].reg << 12;
4732 if (!inst.operands[1].isreg)
4733 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
4735 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
4741 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4743 if (inst.operands[1].preind)
4745 constraint (inst.reloc.exp.X_op != O_constant ||
4746 inst.reloc.exp.X_add_number != 0,
4747 _("this instruction requires a post-indexed address"));
4749 inst.operands[1].preind = 0;
4750 inst.operands[1].postind = 1;
4751 inst.operands[1].writeback = 1;
4753 inst.instruction |= inst.operands[0].reg << 12;
4754 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
4757 /* Co-processor register load/store.
4758 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
4762 inst.instruction |= inst.operands[0].reg << 8;
4763 inst.instruction |= inst.operands[1].reg << 12;
4764 encode_arm_cp_address (2, TRUE, TRUE, 0);
4770 /* This restriction does not apply to mls (nor to mla in v6, but
4771 that's hard to detect at present). */
4772 if (inst.operands[0].reg == inst.operands[1].reg
4773 && !(inst.instruction & 0x00400000))
4774 as_tsktsk (_("rd and rm should be different in mla"));
4776 inst.instruction |= inst.operands[0].reg << 16;
4777 inst.instruction |= inst.operands[1].reg;
4778 inst.instruction |= inst.operands[2].reg << 8;
4779 inst.instruction |= inst.operands[3].reg << 12;
4786 inst.instruction |= inst.operands[0].reg << 12;
4787 encode_arm_shifter_operand (1);
4790 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
4794 inst.instruction |= inst.operands[0].reg << 12;
4795 /* The value is in two pieces: 0:11, 16:19. */
4796 inst.instruction |= (inst.operands[1].imm & 0x00000fff);
4797 inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
4803 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
4804 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
4806 _("'CPSR' or 'SPSR' expected"));
4807 inst.instruction |= inst.operands[0].reg << 12;
4808 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
4811 /* Two possible forms:
4812 "{C|S}PSR_<field>, Rm",
4813 "{C|S}PSR_f, #expression". */
4818 inst.instruction |= inst.operands[0].imm;
4819 if (inst.operands[1].isreg)
4820 inst.instruction |= inst.operands[1].reg;
4823 inst.instruction |= INST_IMMEDIATE;
4824 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4825 inst.reloc.pc_rel = 0;
4832 if (!inst.operands[2].present)
4833 inst.operands[2].reg = inst.operands[0].reg;
4834 inst.instruction |= inst.operands[0].reg << 16;
4835 inst.instruction |= inst.operands[1].reg;
4836 inst.instruction |= inst.operands[2].reg << 8;
4838 if (inst.operands[0].reg == inst.operands[1].reg)
4839 as_tsktsk (_("rd and rm should be different in mul"));
4842 /* Long Multiply Parser
4843 UMULL RdLo, RdHi, Rm, Rs
4844 SMULL RdLo, RdHi, Rm, Rs
4845 UMLAL RdLo, RdHi, Rm, Rs
4846 SMLAL RdLo, RdHi, Rm, Rs. */
4851 inst.instruction |= inst.operands[0].reg << 12;
4852 inst.instruction |= inst.operands[1].reg << 16;
4853 inst.instruction |= inst.operands[2].reg;
4854 inst.instruction |= inst.operands[3].reg << 8;
4856 /* rdhi, rdlo and rm must all be different. */
4857 if (inst.operands[0].reg == inst.operands[1].reg
4858 || inst.operands[0].reg == inst.operands[2].reg
4859 || inst.operands[1].reg == inst.operands[2].reg)
4860 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
4866 if (inst.operands[0].present)
4868 /* Architectural NOP hints are CPSR sets with no bits selected. */
4869 inst.instruction &= 0xf0000000;
4870 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
4874 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
4875 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
4876 Condition defaults to COND_ALWAYS.
4877 Error if Rd, Rn or Rm are R15. */
4882 inst.instruction |= inst.operands[0].reg << 12;
4883 inst.instruction |= inst.operands[1].reg << 16;
4884 inst.instruction |= inst.operands[2].reg;
4885 if (inst.operands[3].present)
4886 encode_arm_shift (3);
4889 /* ARM V6 PKHTB (Argument Parse). */
4894 if (!inst.operands[3].present)
4896 /* If the shift specifier is omitted, turn the instruction
4897 into pkhbt rd, rm, rn. */
4898 inst.instruction &= 0xfff00010;
4899 inst.instruction |= inst.operands[0].reg << 12;
4900 inst.instruction |= inst.operands[1].reg;
4901 inst.instruction |= inst.operands[2].reg << 16;
4905 inst.instruction |= inst.operands[0].reg << 12;
4906 inst.instruction |= inst.operands[1].reg << 16;
4907 inst.instruction |= inst.operands[2].reg;
4908 encode_arm_shift (3);
4912 /* ARMv5TE: Preload-Cache
4916 Syntactically, like LDR with B=1, W=0, L=1. */
4921 constraint (!inst.operands[0].isreg,
4922 _("'[' expected after PLD mnemonic"));
4923 constraint (inst.operands[0].postind,
4924 _("post-indexed expression used in preload instruction"));
4925 constraint (inst.operands[0].writeback,
4926 _("writeback used in preload instruction"));
4927 constraint (!inst.operands[0].preind,
4928 _("unindexed addressing used in preload instruction"));
4929 inst.instruction |= inst.operands[0].reg;
4930 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
4936 inst.operands[1] = inst.operands[0];
4937 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
4938 inst.operands[0].isreg = 1;
4939 inst.operands[0].writeback = 1;
4940 inst.operands[0].reg = REG_SP;
4944 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
4945 word at the specified address and the following word
4947 Unconditionally executed.
4948 Error if Rn is R15. */
4953 inst.instruction |= inst.operands[0].reg << 16;
4954 if (inst.operands[0].writeback)
4955 inst.instruction |= WRITE_BACK;
4958 /* ARM V6 ssat (argument parse). */
4963 inst.instruction |= inst.operands[0].reg << 12;
4964 inst.instruction |= (inst.operands[1].imm - 1) << 16;
4965 inst.instruction |= inst.operands[2].reg;
4967 if (inst.operands[3].present)
4968 encode_arm_shift (3);
4971 /* ARM V6 usat (argument parse). */
4976 inst.instruction |= inst.operands[0].reg << 12;
4977 inst.instruction |= inst.operands[1].imm << 16;
4978 inst.instruction |= inst.operands[2].reg;
4980 if (inst.operands[3].present)
4981 encode_arm_shift (3);
4984 /* ARM V6 ssat16 (argument parse). */
4989 inst.instruction |= inst.operands[0].reg << 12;
4990 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
4991 inst.instruction |= inst.operands[2].reg;
4997 inst.instruction |= inst.operands[0].reg << 12;
4998 inst.instruction |= inst.operands[1].imm << 16;
4999 inst.instruction |= inst.operands[2].reg;
5002 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5003 preserving the other bits.
5005 setend <endian_specifier>, where <endian_specifier> is either
5011 if (inst.operands[0].imm)
5012 inst.instruction |= 0x200;
5018 unsigned int Rm = (inst.operands[1].present
5019 ? inst.operands[1].reg
5020 : inst.operands[0].reg);
5022 inst.instruction |= inst.operands[0].reg << 12;
5023 inst.instruction |= Rm;
5024 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
5026 constraint (inst.operands[0].reg != Rm,
5027 _("source1 and dest must be same register"));
5028 inst.instruction |= inst.operands[2].reg << 8;
5029 inst.instruction |= SHIFT_BY_REG;
5032 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
5038 inst.reloc.type = BFD_RELOC_ARM_SMI;
5039 inst.reloc.pc_rel = 0;
5045 inst.reloc.type = BFD_RELOC_ARM_SWI;
5046 inst.reloc.pc_rel = 0;
5049 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5050 SMLAxy{cond} Rd,Rm,Rs,Rn
5051 SMLAWy{cond} Rd,Rm,Rs,Rn
5052 Error if any register is R15. */
5057 inst.instruction |= inst.operands[0].reg << 16;
5058 inst.instruction |= inst.operands[1].reg;
5059 inst.instruction |= inst.operands[2].reg << 8;
5060 inst.instruction |= inst.operands[3].reg << 12;
5063 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5064 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5065 Error if any register is R15.
5066 Warning if Rdlo == Rdhi. */
5071 inst.instruction |= inst.operands[0].reg << 12;
5072 inst.instruction |= inst.operands[1].reg << 16;
5073 inst.instruction |= inst.operands[2].reg;
5074 inst.instruction |= inst.operands[3].reg << 8;
5076 if (inst.operands[0].reg == inst.operands[1].reg)
5077 as_tsktsk (_("rdhi and rdlo must be different"));
5080 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5081 SMULxy{cond} Rd,Rm,Rs
5082 Error if any register is R15. */
5087 inst.instruction |= inst.operands[0].reg << 16;
5088 inst.instruction |= inst.operands[1].reg;
5089 inst.instruction |= inst.operands[2].reg << 8;
5092 /* ARM V6 srs (argument parse). */
5097 inst.instruction |= inst.operands[0].imm;
5098 if (inst.operands[0].writeback)
5099 inst.instruction |= WRITE_BACK;
5102 /* ARM V6 strex (argument parse). */
5107 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
5108 || inst.operands[2].postind || inst.operands[2].writeback
5109 || inst.operands[2].immisreg || inst.operands[2].shifted
5110 || inst.operands[2].negative,
5111 _("instruction does not accept this addressing mode"));
5113 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
5115 constraint (inst.operands[0].reg == inst.operands[1].reg
5116 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
5118 constraint (inst.reloc.exp.X_op != O_constant
5119 || inst.reloc.exp.X_add_number != 0,
5120 _("offset must be zero in ARM encoding"));
5122 inst.instruction |= inst.operands[0].reg << 12;
5123 inst.instruction |= inst.operands[1].reg;
5124 inst.instruction |= inst.operands[2].reg << 16;
5125 inst.reloc.type = BFD_RELOC_UNUSED;
5131 constraint (inst.operands[1].reg % 2 != 0,
5132 _("even register required"));
5133 constraint (inst.operands[2].present
5134 && inst.operands[2].reg != inst.operands[1].reg + 1,
5135 _("can only store two consecutive registers"));
5136 /* If op 2 were present and equal to PC, this function wouldn't
5137 have been called in the first place. */
5138 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
5140 constraint (inst.operands[0].reg == inst.operands[1].reg
5141 || inst.operands[0].reg == inst.operands[1].reg + 1
5142 || inst.operands[0].reg == inst.operands[3].reg,
5145 inst.instruction |= inst.operands[0].reg << 12;
5146 inst.instruction |= inst.operands[1].reg;
5147 inst.instruction |= inst.operands[3].reg << 16;
5150 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5151 extends it to 32-bits, and adds the result to a value in another
5152 register. You can specify a rotation by 0, 8, 16, or 24 bits
5153 before extracting the 16-bit value.
5154 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5155 Condition defaults to COND_ALWAYS.
5156 Error if any register uses R15. */
5161 inst.instruction |= inst.operands[0].reg << 12;
5162 inst.instruction |= inst.operands[1].reg << 16;
5163 inst.instruction |= inst.operands[2].reg;
5164 inst.instruction |= inst.operands[3].imm << 10;
5169 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5170 Condition defaults to COND_ALWAYS.
5171 Error if any register uses R15. */
5176 inst.instruction |= inst.operands[0].reg << 12;
5177 inst.instruction |= inst.operands[1].reg;
5178 inst.instruction |= inst.operands[2].imm << 10;
5181 /* VFP instructions. In a logical order: SP variant first, monad
5182 before dyad, arithmetic then move then load/store. */
5185 do_vfp_sp_monadic (void)
5187 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5188 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5192 do_vfp_sp_dyadic (void)
5194 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5195 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5196 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5200 do_vfp_sp_compare_z (void)
5202 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5206 do_vfp_dp_sp_cvt (void)
5208 inst.instruction |= inst.operands[0].reg << 12;
5209 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5213 do_vfp_sp_dp_cvt (void)
5215 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5216 inst.instruction |= inst.operands[1].reg;
5220 do_vfp_reg_from_sp (void)
5222 inst.instruction |= inst.operands[0].reg << 12;
5223 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5227 do_vfp_reg2_from_sp2 (void)
5229 constraint (inst.operands[2].imm != 2,
5230 _("only two consecutive VFP SP registers allowed here"));
5231 inst.instruction |= inst.operands[0].reg << 12;
5232 inst.instruction |= inst.operands[1].reg << 16;
5233 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5237 do_vfp_sp_from_reg (void)
5239 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
5240 inst.instruction |= inst.operands[1].reg << 12;
5244 do_vfp_sp2_from_reg2 (void)
5246 constraint (inst.operands[0].imm != 2,
5247 _("only two consecutive VFP SP registers allowed here"));
5248 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
5249 inst.instruction |= inst.operands[1].reg << 12;
5250 inst.instruction |= inst.operands[2].reg << 16;
5254 do_vfp_sp_ldst (void)
5256 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5257 encode_arm_cp_address (1, FALSE, TRUE, 0);
5261 do_vfp_dp_ldst (void)
5263 inst.instruction |= inst.operands[0].reg << 12;
5264 encode_arm_cp_address (1, FALSE, TRUE, 0);
5269 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
5271 if (inst.operands[0].writeback)
5272 inst.instruction |= WRITE_BACK;
5274 constraint (ldstm_type != VFP_LDSTMIA,
5275 _("this addressing mode requires base-register writeback"));
5276 inst.instruction |= inst.operands[0].reg << 16;
5277 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
5278 inst.instruction |= inst.operands[1].imm;
5282 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
5286 if (inst.operands[0].writeback)
5287 inst.instruction |= WRITE_BACK;
5289 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
5290 _("this addressing mode requires base-register writeback"));
5292 inst.instruction |= inst.operands[0].reg << 16;
5293 inst.instruction |= inst.operands[1].reg << 12;
5295 count = inst.operands[1].imm << 1;
5296 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
5299 inst.instruction |= count;
5303 do_vfp_sp_ldstmia (void)
5305 vfp_sp_ldstm (VFP_LDSTMIA);
5309 do_vfp_sp_ldstmdb (void)
5311 vfp_sp_ldstm (VFP_LDSTMDB);
5315 do_vfp_dp_ldstmia (void)
5317 vfp_dp_ldstm (VFP_LDSTMIA);
5321 do_vfp_dp_ldstmdb (void)
5323 vfp_dp_ldstm (VFP_LDSTMDB);
5327 do_vfp_xp_ldstmia (void)
5329 vfp_dp_ldstm (VFP_LDSTMIAX);
5333 do_vfp_xp_ldstmdb (void)
5335 vfp_dp_ldstm (VFP_LDSTMDBX);
5338 /* FPA instructions. Also in a logical order. */
5343 inst.instruction |= inst.operands[0].reg << 16;
5344 inst.instruction |= inst.operands[1].reg;
5348 do_fpa_ldmstm (void)
5350 inst.instruction |= inst.operands[0].reg << 12;
5351 switch (inst.operands[1].imm)
5353 case 1: inst.instruction |= CP_T_X; break;
5354 case 2: inst.instruction |= CP_T_Y; break;
5355 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
5360 if (inst.instruction & (PRE_INDEX | INDEX_UP))
5362 /* The instruction specified "ea" or "fd", so we can only accept
5363 [Rn]{!}. The instruction does not really support stacking or
5364 unstacking, so we have to emulate these by setting appropriate
5365 bits and offsets. */
5366 constraint (inst.reloc.exp.X_op != O_constant
5367 || inst.reloc.exp.X_add_number != 0,
5368 _("this instruction does not support indexing"));
5370 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
5371 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
5373 if (!(inst.instruction & INDEX_UP))
5374 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
5376 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
5378 inst.operands[2].preind = 0;
5379 inst.operands[2].postind = 1;
5383 encode_arm_cp_address (2, TRUE, TRUE, 0);
5386 /* iWMMXt instructions: strictly in alphabetical order. */
5389 do_iwmmxt_tandorc (void)
5391 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
5395 do_iwmmxt_textrc (void)
5397 inst.instruction |= inst.operands[0].reg << 12;
5398 inst.instruction |= inst.operands[1].imm;
5402 do_iwmmxt_textrm (void)
5404 inst.instruction |= inst.operands[0].reg << 12;
5405 inst.instruction |= inst.operands[1].reg << 16;
5406 inst.instruction |= inst.operands[2].imm;
5410 do_iwmmxt_tinsr (void)
5412 inst.instruction |= inst.operands[0].reg << 16;
5413 inst.instruction |= inst.operands[1].reg << 12;
5414 inst.instruction |= inst.operands[2].imm;
5418 do_iwmmxt_tmia (void)
5420 inst.instruction |= inst.operands[0].reg << 5;
5421 inst.instruction |= inst.operands[1].reg;
5422 inst.instruction |= inst.operands[2].reg << 12;
5426 do_iwmmxt_waligni (void)
5428 inst.instruction |= inst.operands[0].reg << 12;
5429 inst.instruction |= inst.operands[1].reg << 16;
5430 inst.instruction |= inst.operands[2].reg;
5431 inst.instruction |= inst.operands[3].imm << 20;
5435 do_iwmmxt_wmov (void)
5437 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5438 inst.instruction |= inst.operands[0].reg << 12;
5439 inst.instruction |= inst.operands[1].reg << 16;
5440 inst.instruction |= inst.operands[1].reg;
5444 do_iwmmxt_wldstbh (void)
5446 inst.instruction |= inst.operands[0].reg << 12;
5447 inst.reloc.exp.X_add_number *= 4;
5448 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
5452 do_iwmmxt_wldstw (void)
5454 /* RIWR_RIWC clears .isreg for a control register. */
5455 if (!inst.operands[0].isreg)
5457 constraint (inst.cond != COND_ALWAYS, BAD_COND);
5458 inst.instruction |= 0xf0000000;
5461 inst.instruction |= inst.operands[0].reg << 12;
5462 encode_arm_cp_address (1, TRUE, TRUE, 0);
5466 do_iwmmxt_wldstd (void)
5468 inst.instruction |= inst.operands[0].reg << 12;
5469 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
5473 do_iwmmxt_wshufh (void)
5475 inst.instruction |= inst.operands[0].reg << 12;
5476 inst.instruction |= inst.operands[1].reg << 16;
5477 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
5478 inst.instruction |= (inst.operands[2].imm & 0x0f);
5482 do_iwmmxt_wzero (void)
5484 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5485 inst.instruction |= inst.operands[0].reg;
5486 inst.instruction |= inst.operands[0].reg << 12;
5487 inst.instruction |= inst.operands[0].reg << 16;
5490 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5491 operations first, then control, shift, and load/store. */
5493 /* Insns like "foo X,Y,Z". */
5496 do_mav_triple (void)
5498 inst.instruction |= inst.operands[0].reg << 16;
5499 inst.instruction |= inst.operands[1].reg;
5500 inst.instruction |= inst.operands[2].reg << 12;
5503 /* Insns like "foo W,X,Y,Z".
5504 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5509 inst.instruction |= inst.operands[0].reg << 5;
5510 inst.instruction |= inst.operands[1].reg << 12;
5511 inst.instruction |= inst.operands[2].reg << 16;
5512 inst.instruction |= inst.operands[3].reg;
5515 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5519 inst.instruction |= inst.operands[1].reg << 12;
5522 /* Maverick shift immediate instructions.
5523 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5524 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5529 int imm = inst.operands[2].imm;
5531 inst.instruction |= inst.operands[0].reg << 12;
5532 inst.instruction |= inst.operands[1].reg << 16;
5534 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5535 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5536 Bit 4 should be 0. */
5537 imm = (imm & 0xf) | ((imm & 0x70) << 1);
5539 inst.instruction |= imm;
5542 /* XScale instructions. Also sorted arithmetic before move. */
5544 /* Xscale multiply-accumulate (argument parse)
5547 MIAxycc acc0,Rm,Rs. */
5552 inst.instruction |= inst.operands[1].reg;
5553 inst.instruction |= inst.operands[2].reg << 12;
5556 /* Xscale move-accumulator-register (argument parse)
5558 MARcc acc0,RdLo,RdHi. */
5563 inst.instruction |= inst.operands[1].reg << 12;
5564 inst.instruction |= inst.operands[2].reg << 16;
5567 /* Xscale move-register-accumulator (argument parse)
5569 MRAcc RdLo,RdHi,acc0. */
5574 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
5575 inst.instruction |= inst.operands[0].reg << 12;
5576 inst.instruction |= inst.operands[1].reg << 16;
5579 /* Encoding functions relevant only to Thumb. */
5581 /* inst.operands[i] is a shifted-register operand; encode
5582 it into inst.instruction in the format used by Thumb32. */
5585 encode_thumb32_shifted_operand (int i)
5587 unsigned int value = inst.reloc.exp.X_add_number;
5588 unsigned int shift = inst.operands[i].shift_kind;
5590 inst.instruction |= inst.operands[i].reg;
5591 if (shift == SHIFT_RRX)
5592 inst.instruction |= SHIFT_ROR << 4;
5595 constraint (inst.reloc.exp.X_op != O_constant,
5596 _("expression too complex"));
5598 constraint (value > 32
5599 || (value == 32 && (shift == SHIFT_LSL
5600 || shift == SHIFT_ROR)),
5601 _("shift expression is too large"));
5605 else if (value == 32)
5608 inst.instruction |= shift << 4;
5609 inst.instruction |= (value & 0x1c) << 10;
5610 inst.instruction |= (value & 0x03) << 6;
5615 /* inst.operands[i] was set up by parse_address. Encode it into a
5616 Thumb32 format load or store instruction. Reject forms that cannot
5617 be used with such instructions. If is_t is true, reject forms that
5618 cannot be used with a T instruction; if is_d is true, reject forms
5619 that cannot be used with a D instruction. */
5622 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
5624 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
5626 constraint (!inst.operands[i].isreg,
5627 _("Thumb does not support the ldr =N pseudo-operation"));
5629 inst.instruction |= inst.operands[i].reg << 16;
5630 if (inst.operands[i].immisreg)
5632 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
5633 constraint (is_t || is_d, _("cannot use register index with this instruction"));
5634 constraint (inst.operands[i].negative,
5635 _("Thumb does not support negative register indexing"));
5636 constraint (inst.operands[i].postind,
5637 _("Thumb does not support register post-indexing"));
5638 constraint (inst.operands[i].writeback,
5639 _("Thumb does not support register indexing with writeback"));
5640 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
5641 _("Thumb supports only LSL in shifted register indexing"));
5643 inst.instruction |= inst.operands[1].imm;
5644 if (inst.operands[i].shifted)
5646 constraint (inst.reloc.exp.X_op != O_constant,
5647 _("expression too complex"));
5648 constraint (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 3,
5649 _("shift out of range"));
5650 inst.instruction |= inst.reloc.exp.X_op << 4;
5652 inst.reloc.type = BFD_RELOC_UNUSED;
5654 else if (inst.operands[i].preind)
5656 constraint (is_pc && inst.operands[i].writeback,
5657 _("cannot use writeback with PC-relative addressing"));
5658 constraint (is_t && inst.operands[1].writeback,
5659 _("cannot use writeback with this instruction"));
5663 inst.instruction |= 0x01000000;
5664 if (inst.operands[i].writeback)
5665 inst.instruction |= 0x00200000;
5669 inst.instruction |= 0x00000c00;
5670 if (inst.operands[i].writeback)
5671 inst.instruction |= 0x00000100;
5673 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5674 inst.reloc.pc_rel = is_pc;
5676 else if (inst.operands[i].postind)
5678 assert (inst.operands[i].writeback);
5679 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
5680 constraint (is_t, _("cannot use post-indexing with this instruction"));
5683 inst.instruction |= 0x00200000;
5685 inst.instruction |= 0x00000900;
5686 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5688 else /* unindexed - only for coprocessor */
5689 inst.error = _("instruction does not accept unindexed addressing");
5692 /* Table of Thumb instructions which exist in both 16- and 32-bit
5693 encodings (the latter only in post-V6T2 cores). The index is the
5694 value used in the insns table below. When there is more than one
5695 possible 16-bit encoding for the instruction, this table always
5696 holds variant (1). */
5697 #define T16_32_TAB \
5698 X(adc, 4140, eb400000), \
5699 X(adcs, 4140, eb500000), \
5700 X(add, 1c00, eb000000), \
5701 X(adds, 1c00, eb100000), \
5702 X(and, 4000, ea000000), \
5703 X(ands, 4000, ea100000), \
5704 X(asr, 1000, fa40f000), \
5705 X(asrs, 1000, fa50f000), \
5706 X(bic, 4380, ea200000), \
5707 X(bics, 4380, ea300000), \
5708 X(cmn, 42c0, eb100f00), \
5709 X(cmp, 2800, ebb00f00), \
5710 X(cpsie, b660, f3af8400), \
5711 X(cpsid, b670, f3af8600), \
5712 X(cpy, 4600, ea4f0000), \
5713 X(eor, 4040, ea800000), \
5714 X(eors, 4040, ea900000), \
5715 X(ldmia, c800, e8900000), \
5716 X(ldr, 6800, f8500000), \
5717 X(ldrb, 7800, f8100000), \
5718 X(ldrh, 8800, f8300000), \
5719 X(ldrsb, 5600, f9100000), \
5720 X(ldrsh, 5e00, f9300000), \
5721 X(lsl, 0000, fa00f000), \
5722 X(lsls, 0000, fa10f000), \
5723 X(lsr, 0800, fa20f000), \
5724 X(lsrs, 0800, fa30f000), \
5725 X(mov, 2000, ea4f0000), \
5726 X(movs, 2000, ea5f0000), \
5727 X(mul, 4340, fb00f000), \
5728 X(muls, 4340, ffffffff), /* no 32b muls */ \
5729 X(mvn, 43c0, ea6f0000), \
5730 X(mvns, 43c0, ea7f0000), \
5731 X(neg, 4240, f1c00000), /* rsb #0 */ \
5732 X(negs, 4240, f1d00000), /* rsbs #0 */ \
5733 X(orr, 4300, ea400000), \
5734 X(orrs, 4300, ea500000), \
5735 X(pop, bc00, e8ad0000), /* ldmia sp!,... */ \
5736 X(push, b400, e8bd0000), /* stmia sp!,... */ \
5737 X(rev, ba00, fa90f080), \
5738 X(rev16, ba40, fa90f090), \
5739 X(revsh, bac0, fa90f0b0), \
5740 X(ror, 41c0, fa60f000), \
5741 X(rors, 41c0, fa70f000), \
5742 X(sbc, 4180, eb600000), \
5743 X(sbcs, 4180, eb700000), \
5744 X(stmia, c000, e8800000), \
5745 X(str, 6000, f8400000), \
5746 X(strb, 7000, f8000000), \
5747 X(strh, 8000, f8200000), \
5748 X(sub, 1e00, eba00000), \
5749 X(subs, 1e00, ebb00000), \
5750 X(sxtb, b240, fa4ff080), \
5751 X(sxth, b200, fa0ff080), \
5752 X(tst, 4200, ea100f00), \
5753 X(uxtb, b2c0, fa5ff080), \
5754 X(uxth, b280, fa1ff080), \
5755 X(nop, bf00, f3af8000), \
5756 X(yield, bf10, f3af8001), \
5757 X(wfe, bf20, f3af8002), \
5758 X(wfi, bf30, f3af8003), \
5759 X(sev, bf40, f3af9004), /* typo, 8004? */
5761 /* To catch errors in encoding functions, the codes are all offset by
5762 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
5763 as 16-bit instructions. */
5764 #define X(a,b,c) T_MNEM_##a
5765 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
5768 #define X(a,b,c) 0x##b
5769 static const unsigned short thumb_op16[] = { T16_32_TAB };
5770 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
5773 #define X(a,b,c) 0x##c
5774 static const unsigned int thumb_op32[] = { T16_32_TAB };
5775 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
5776 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
5780 /* Thumb instruction encoders, in alphabetical order. */
5782 /* Parse an add or subtract instruction. We get here with inst.instruction
5783 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
5790 Rd = inst.operands[0].reg;
5791 Rs = (inst.operands[1].present
5792 ? inst.operands[1].reg /* Rd, Rs, foo */
5793 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
5797 if (!inst.operands[2].isreg)
5799 /* For an immediate, we always generate a 32-bit opcode;
5800 section relaxation will shrink it later if possible. */
5801 inst.instruction = THUMB_OP32 (inst.instruction);
5802 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
5803 inst.instruction |= inst.operands[0].reg << 8;
5804 inst.instruction |= inst.operands[1].reg << 16;
5805 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
5809 Rn = inst.operands[2].reg;
5810 /* See if we can do this with a 16-bit instruction. */
5811 if (!inst.operands[2].shifted && inst.size_req != 4)
5813 if (Rd <= 7 && Rn <= 7 && Rn <= 7
5814 && (inst.instruction == T_MNEM_adds
5815 || inst.instruction == T_MNEM_subs))
5817 inst.instruction = (inst.instruction == T_MNEM_adds
5820 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5824 if (inst.instruction == T_MNEM_add)
5828 inst.instruction = T_OPCODE_ADD_HI;
5829 inst.instruction |= (Rd & 8) << 4;
5830 inst.instruction |= (Rd & 7);
5831 inst.instruction |= Rn << 3;
5834 /* ... because addition is commutative! */
5837 inst.instruction = T_OPCODE_ADD_HI;
5838 inst.instruction |= (Rd & 8) << 4;
5839 inst.instruction |= (Rd & 7);
5840 inst.instruction |= Rs << 3;
5845 /* If we get here, it can't be done in 16 bits. */
5846 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
5847 _("shift must be constant"));
5848 inst.instruction = THUMB_OP32 (inst.instruction);
5849 inst.instruction |= Rd << 8;
5850 inst.instruction |= Rs << 16;
5851 encode_thumb32_shifted_operand (2);
5856 constraint (inst.instruction == T_MNEM_adds
5857 || inst.instruction == T_MNEM_subs,
5860 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
5862 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
5863 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
5866 inst.instruction = (inst.instruction == T_MNEM_add
5868 inst.instruction |= (Rd << 4) | Rs;
5869 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5873 Rn = inst.operands[2].reg;
5874 constraint (inst.operands[2].shifted, _("unshifted register required"));
5876 /* We now have Rd, Rs, and Rn set to registers. */
5877 if (Rd > 7 || Rs > 7 || Rn > 7)
5879 /* Can't do this for SUB. */
5880 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
5881 inst.instruction = T_OPCODE_ADD_HI;
5882 inst.instruction |= (Rd & 8) << 4;
5883 inst.instruction |= (Rd & 7);
5885 inst.instruction |= Rn << 3;
5887 inst.instruction |= Rs << 3;
5889 constraint (1, _("dest must overlap one source register"));
5893 inst.instruction = (inst.instruction == T_MNEM_add
5894 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
5895 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5903 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5904 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
5905 inst.reloc.pc_rel = 1;
5907 inst.instruction |= inst.operands[0].reg << 4;
5910 /* Arithmetic instructions for which there is just one 16-bit
5911 instruction encoding, and it allows only two low registers.
5912 For maximal compatibility with ARM syntax, we allow three register
5913 operands even when Thumb-32 instructions are not available, as long
5914 as the first two are identical. For instance, both "sbc r0,r1" and
5915 "sbc r0,r0,r1" are allowed. */
5921 Rd = inst.operands[0].reg;
5922 Rs = (inst.operands[1].present
5923 ? inst.operands[1].reg /* Rd, Rs, foo */
5924 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
5925 Rn = inst.operands[2].reg;
5929 if (!inst.operands[2].isreg)
5931 /* For an immediate, we always generate a 32-bit opcode;
5932 section relaxation will shrink it later if possible. */
5933 inst.instruction = THUMB_OP32 (inst.instruction);
5934 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
5935 inst.instruction |= Rd << 8;
5936 inst.instruction |= Rs << 16;
5937 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
5941 /* See if we can do this with a 16-bit instruction. */
5942 if (THUMB_SETS_FLAGS (inst.instruction)
5943 && !inst.operands[2].shifted
5944 && inst.size_req != 4
5947 inst.instruction = THUMB_OP16 (inst.instruction);
5948 inst.instruction |= Rd;
5949 inst.instruction |= Rn << 3;
5953 /* If we get here, it can't be done in 16 bits. */
5954 constraint (inst.operands[2].shifted
5955 && inst.operands[2].immisreg,
5956 _("shift must be constant"));
5957 inst.instruction = THUMB_OP32 (inst.instruction);
5958 inst.instruction |= Rd << 8;
5959 inst.instruction |= Rs << 16;
5960 encode_thumb32_shifted_operand (2);
5965 /* On its face this is a lie - the instruction does set the
5966 flags. However, the only supported mnemonic in this mode
5968 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
5970 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
5971 _("unshifted register required"));
5972 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
5973 constraint (Rd != Rs,
5974 _("dest and source1 must be the same register"));
5976 inst.instruction = THUMB_OP16 (inst.instruction);
5977 inst.instruction |= Rd;
5978 inst.instruction |= Rn << 3;
5982 /* Similarly, but for instructions where the arithmetic operation is
5983 commutative, so we can allow either of them to be different from
5984 the destination operand in a 16-bit instruction. For instance, all
5985 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
5992 Rd = inst.operands[0].reg;
5993 Rs = (inst.operands[1].present
5994 ? inst.operands[1].reg /* Rd, Rs, foo */
5995 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
5996 Rn = inst.operands[2].reg;
6000 if (!inst.operands[2].isreg)
6002 /* For an immediate, we always generate a 32-bit opcode;
6003 section relaxation will shrink it later if possible. */
6004 inst.instruction = THUMB_OP32 (inst.instruction);
6005 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6006 inst.instruction |= Rd << 8;
6007 inst.instruction |= Rs << 16;
6008 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6012 /* See if we can do this with a 16-bit instruction. */
6013 if (THUMB_SETS_FLAGS (inst.instruction)
6014 && !inst.operands[2].shifted
6015 && inst.size_req != 4)
6019 inst.instruction = THUMB_OP16 (inst.instruction);
6020 inst.instruction |= Rd;
6021 inst.instruction |= Rn << 3;
6026 inst.instruction = THUMB_OP16 (inst.instruction);
6027 inst.instruction |= Rd;
6028 inst.instruction |= Rs << 3;
6033 /* If we get here, it can't be done in 16 bits. */
6034 constraint (inst.operands[2].shifted
6035 && inst.operands[2].immisreg,
6036 _("shift must be constant"));
6037 inst.instruction = THUMB_OP32 (inst.instruction);
6038 inst.instruction |= Rd << 8;
6039 inst.instruction |= Rs << 16;
6040 encode_thumb32_shifted_operand (2);
6045 /* On its face this is a lie - the instruction does set the
6046 flags. However, the only supported mnemonic in this mode
6048 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6050 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6051 _("unshifted register required"));
6052 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6054 inst.instruction = THUMB_OP16 (inst.instruction);
6055 inst.instruction |= Rd;
6058 inst.instruction |= Rn << 3;
6060 inst.instruction |= Rs << 3;
6062 constraint (1, _("dest must overlap one source register"));
6069 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6070 constraint (msb > 32, _("bit-field extends past end of register"));
6071 /* The instruction encoding stores the LSB and MSB,
6072 not the LSB and width. */
6073 inst.instruction |= inst.operands[0].reg << 8;
6074 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
6075 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
6076 inst.instruction |= msb - 1;
6084 /* #0 in second position is alternative syntax for bfc, which is
6085 the same instruction but with REG_PC in the Rm field. */
6086 if (!inst.operands[1].isreg)
6087 inst.operands[1].reg = REG_PC;
6089 msb = inst.operands[2].imm + inst.operands[3].imm;
6090 constraint (msb > 32, _("bit-field extends past end of register"));
6091 /* The instruction encoding stores the LSB and MSB,
6092 not the LSB and width. */
6093 inst.instruction |= inst.operands[0].reg << 8;
6094 inst.instruction |= inst.operands[1].reg << 16;
6095 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6096 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6097 inst.instruction |= msb - 1;
6103 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6104 _("bit-field extends past end of register"));
6105 inst.instruction |= inst.operands[0].reg << 8;
6106 inst.instruction |= inst.operands[1].reg << 16;
6107 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6108 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6109 inst.instruction |= inst.operands[3].imm - 1;
6112 /* ARM V5 Thumb BLX (argument parse)
6113 BLX <target_addr> which is BLX(1)
6114 BLX <Rm> which is BLX(2)
6115 Unfortunately, there are two different opcodes for this mnemonic.
6116 So, the insns[].value is not used, and the code here zaps values
6117 into inst.instruction.
6119 ??? How to take advantage of the additional two bits of displacement
6120 available in Thumb32 mode? Need new relocation? */
6125 if (inst.operands[0].isreg)
6126 /* We have a register, so this is BLX(2). */
6127 inst.instruction |= inst.operands[0].reg << 3;
6130 /* No register. This must be BLX(1). */
6131 inst.instruction = 0xf7ffeffe;
6132 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
6133 inst.reloc.pc_rel = 1;
6140 if (unified_syntax && inst.size_req != 2)
6142 if (inst.cond == COND_ALWAYS)
6144 inst.instruction = 0xf7ffbffe;
6145 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
6149 assert (inst.cond != 0xF);
6150 inst.instruction = (inst.cond << 22) | 0xf43faffe;
6151 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
6156 if (inst.cond == COND_ALWAYS)
6157 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6160 inst.instruction = 0xd0fe | (inst.cond << 8);
6161 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6165 inst.reloc.pc_rel = 1;
6171 if (inst.operands[0].present)
6173 constraint (inst.operands[0].imm > 255,
6174 _("immediate value out of range"));
6175 inst.instruction |= inst.operands[0].imm;
6180 do_t_branch23 (void)
6182 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6183 inst.reloc.pc_rel = 1;
6185 /* If the destination of the branch is a defined symbol which does not have
6186 the THUMB_FUNC attribute, then we must be calling a function which has
6187 the (interfacearm) attribute. We look for the Thumb entry point to that
6188 function and change the branch to refer to that function instead. */
6189 if ( inst.reloc.exp.X_op == O_symbol
6190 && inst.reloc.exp.X_add_symbol != NULL
6191 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6192 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6193 inst.reloc.exp.X_add_symbol =
6194 find_real_start (inst.reloc.exp.X_add_symbol);
6200 inst.instruction |= inst.operands[0].reg << 3;
6201 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6202 should cause the alignment to be checked once it is known. This is
6203 because BX PC only works if the instruction is word aligned. */
6209 if (inst.operands[0].reg == REG_PC)
6210 as_tsktsk (_("use of r15 in bxj is not really useful"));
6212 inst.instruction |= inst.operands[0].reg << 16;
6218 inst.instruction |= inst.operands[0].reg << 8;
6219 inst.instruction |= inst.operands[1].reg << 16;
6220 inst.instruction |= inst.operands[1].reg;
6227 && (inst.operands[1].present || inst.size_req == 4))
6229 unsigned int imod = (inst.instruction & 0x0030) >> 4;
6230 inst.instruction = 0xf3af8000;
6231 inst.instruction |= imod << 9;
6232 inst.instruction |= inst.operands[0].imm << 5;
6233 if (inst.operands[1].present)
6234 inst.instruction |= 0x100 | inst.operands[1].imm;
6238 constraint (inst.operands[1].present,
6239 _("Thumb does not support the 2-argument "
6240 "form of this instruction"));
6241 inst.instruction |= inst.operands[0].imm;
6245 /* THUMB CPY instruction (argument parse). */
6250 if (inst.size_req == 4)
6252 inst.instruction = THUMB_OP32 (T_MNEM_mov);
6253 inst.instruction |= inst.operands[0].reg << 8;
6254 inst.instruction |= inst.operands[1].reg;
6258 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6259 inst.instruction |= (inst.operands[0].reg & 0x7);
6260 inst.instruction |= inst.operands[1].reg << 3;
6267 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6268 inst.instruction |= inst.operands[0].reg;
6269 inst.reloc.pc_rel = 1;
6270 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
6276 if (unified_syntax && inst.size_req == 4)
6277 inst.instruction = THUMB_OP32 (inst.instruction);
6279 inst.instruction = THUMB_OP16 (inst.instruction);
6285 unsigned int cond = inst.operands[0].imm;
6286 if ((cond & 0x1) == 0x0)
6288 unsigned int mask = inst.instruction & 0x000f;
6289 inst.instruction &= 0xfff0;
6291 if ((mask & 0x7) == 0)
6292 /* no conversion needed */;
6293 else if ((mask & 0x3) == 0)
6294 mask = (~(mask & 0x8) & 0x8) | 0x4;
6295 else if ((mask & 1) == 0)
6296 mask = (~(mask & 0xC) & 0xC) | 0x2;
6298 mask = (~(mask & 0xE) & 0xE) | 0x1;
6300 inst.instruction |= (mask & 0xF);
6303 inst.instruction |= cond << 4;
6309 /* This really doesn't seem worth it. */
6310 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6311 _("expression too complex"));
6312 constraint (inst.operands[1].writeback,
6313 _("Thumb load/store multiple does not support {reglist}^"));
6317 /* See if we can use a 16-bit instruction. */
6318 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
6319 && inst.size_req != 4
6320 && inst.operands[0].reg <= 7
6321 && !(inst.operands[1].imm & ~0xff)
6322 && (inst.instruction == T_MNEM_stmia
6323 ? inst.operands[0].writeback
6324 : (inst.operands[0].writeback
6325 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
6327 if (inst.instruction == T_MNEM_stmia
6328 && (inst.operands[1].imm & (1 << inst.operands[0].reg))
6329 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6330 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6331 inst.operands[0].reg);
6333 inst.instruction = THUMB_OP16 (inst.instruction);
6334 inst.instruction |= inst.operands[0].reg << 8;
6335 inst.instruction |= inst.operands[1].imm;
6339 if (inst.operands[1].imm & (1 << 13))
6340 as_warn (_("SP should not be in register list"));
6341 if (inst.instruction == T_MNEM_stmia)
6343 if (inst.operands[1].imm & (1 << 15))
6344 as_warn (_("PC should not be in register list"));
6345 if (inst.operands[1].imm & (1 << inst.operands[0].reg))
6346 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6347 inst.operands[0].reg);
6351 if (inst.operands[1].imm & (1 << 14)
6352 && inst.operands[1].imm & (1 << 15))
6353 as_warn (_("LR and PC should not both be in register list"));
6354 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6355 && inst.operands[0].writeback)
6356 as_warn (_("base register should not be in register list "
6357 "when written back"));
6359 if (inst.instruction < 0xffff)
6360 inst.instruction = THUMB_OP32 (inst.instruction);
6361 inst.instruction |= inst.operands[0].reg << 16;
6362 inst.instruction |= inst.operands[1].imm;
6363 if (inst.operands[0].writeback)
6364 inst.instruction |= WRITE_BACK;
6369 constraint (inst.operands[0].reg > 7
6370 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
6371 if (inst.instruction == T_MNEM_stmia)
6373 if (!inst.operands[0].writeback)
6374 as_warn (_("this instruction will write back the base register"));
6375 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6376 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6377 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6378 inst.operands[0].reg);
6382 if (!inst.operands[0].writeback
6383 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
6384 as_warn (_("this instruction will write back the base register"));
6385 else if (inst.operands[0].writeback
6386 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
6387 as_warn (_("this instruction will not write back the base register"));
6390 inst.instruction = THUMB_OP16 (inst.instruction);
6391 inst.instruction |= inst.operands[0].reg << 8;
6392 inst.instruction |= inst.operands[1].imm;
6399 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6400 || inst.operands[1].postind || inst.operands[1].writeback
6401 || inst.operands[1].immisreg || inst.operands[1].shifted
6402 || inst.operands[1].negative,
6403 _("instruction does not accept this addressing mode"));
6405 inst.instruction |= inst.operands[0].reg << 12;
6406 inst.instruction |= inst.operands[1].reg << 16;
6407 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
6413 if (!inst.operands[1].present)
6415 constraint (inst.operands[0].reg == REG_LR,
6416 _("r14 not allowed as first register "
6417 "when second register is omitted"));
6418 inst.operands[1].reg = inst.operands[0].reg + 1;
6420 constraint (inst.operands[0].reg == inst.operands[1].reg,
6423 inst.instruction |= inst.operands[0].reg << 12;
6424 inst.instruction |= inst.operands[1].reg << 8;
6425 inst.instruction |= inst.operands[2].reg << 16;
6433 /* Generation of 16-bit instructions for anything other than
6434 Rd, [Rn, Ri] is deferred to section relaxation time. */
6435 if (inst.operands[1].isreg && inst.operands[1].immisreg
6436 && !inst.operands[1].shifted && !inst.operands[1].postind
6437 && !inst.operands[1].negative && inst.operands[0].reg <= 7
6438 && inst.operands[1].reg <= 7 && inst.operands[1].imm <= 7
6439 && inst.instruction <= 0xffff)
6441 inst.instruction = THUMB_OP16 (inst.instruction);
6445 inst.instruction = THUMB_OP32 (inst.instruction);
6446 inst.instruction |= inst.operands[0].reg << 12;
6447 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
6451 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6453 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
6455 /* Only [Rn,Rm] is acceptable. */
6456 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
6457 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
6458 || inst.operands[1].postind || inst.operands[1].shifted
6459 || inst.operands[1].negative,
6460 _("Thumb does not support this addressing mode"));
6461 inst.instruction = THUMB_OP16 (inst.instruction);
6465 inst.instruction = THUMB_OP16 (inst.instruction);
6466 if (!inst.operands[1].isreg)
6467 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
6470 constraint (!inst.operands[1].preind
6471 || inst.operands[1].shifted
6472 || inst.operands[1].writeback,
6473 _("Thumb does not support this addressing mode"));
6474 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
6476 constraint (inst.instruction & 0x0600,
6477 _("byte or halfword not valid for base register"));
6478 constraint (inst.operands[1].reg == REG_PC
6479 && !(inst.instruction & THUMB_LOAD_BIT),
6480 _("r15 based store not allowed"));
6481 constraint (inst.operands[1].immisreg,
6482 _("invalid base register for register offset"));
6484 if (inst.operands[1].reg == REG_PC)
6485 inst.instruction = T_OPCODE_LDR_PC;
6486 else if (inst.instruction & THUMB_LOAD_BIT)
6487 inst.instruction = T_OPCODE_LDR_SP;
6489 inst.instruction = T_OPCODE_STR_SP;
6491 inst.instruction |= inst.operands[0].reg << 8;
6492 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6496 constraint (inst.operands[1].reg > 7, BAD_HIREG);
6497 if (!inst.operands[1].immisreg)
6499 /* Immediate offset. */
6500 inst.instruction |= inst.operands[0].reg;
6501 inst.instruction |= inst.operands[1].reg << 3;
6502 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6506 /* Register offset. */
6507 constraint (inst.operands[1].imm > 7, BAD_HIREG);
6508 constraint (inst.operands[1].negative,
6509 _("Thumb does not support this addressing mode"));
6512 switch (inst.instruction)
6514 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
6515 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
6516 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
6517 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
6518 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
6519 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
6520 case 0x5600 /* ldrsb */:
6521 case 0x5e00 /* ldrsh */: break;
6525 inst.instruction |= inst.operands[0].reg;
6526 inst.instruction |= inst.operands[1].reg << 3;
6527 inst.instruction |= inst.operands[1].imm << 6;
6533 if (!inst.operands[1].present)
6535 inst.operands[1].reg = inst.operands[0].reg + 1;
6536 constraint (inst.operands[0].reg == REG_LR,
6537 _("r14 not allowed here"));
6539 inst.instruction |= inst.operands[0].reg << 12;
6540 inst.instruction |= inst.operands[1].reg << 8;
6541 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
6548 inst.instruction |= inst.operands[0].reg << 12;
6549 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
6555 inst.instruction |= inst.operands[0].reg << 8;
6556 inst.instruction |= inst.operands[1].reg << 16;
6557 inst.instruction |= inst.operands[2].reg;
6558 inst.instruction |= inst.operands[3].reg << 12;
6564 inst.instruction |= inst.operands[0].reg << 12;
6565 inst.instruction |= inst.operands[1].reg << 8;
6566 inst.instruction |= inst.operands[2].reg << 16;
6567 inst.instruction |= inst.operands[3].reg;
6575 int r0off = (inst.instruction == T_MNEM_mov
6576 || inst.instruction == T_MNEM_movs) ? 8 : 16;
6577 if (!inst.operands[1].isreg)
6579 /* For an immediate, we always generate a 32-bit opcode;
6580 section relaxation will shrink it later if possible. */
6581 inst.instruction = THUMB_OP32 (inst.instruction);
6582 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6583 inst.instruction |= inst.operands[0].reg << r0off;
6584 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6586 else if (inst.size_req == 4
6587 || inst.operands[1].shifted
6588 || (inst.instruction == T_MNEM_movs
6589 && (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)))
6591 inst.instruction = THUMB_OP32 (inst.instruction);
6592 inst.instruction |= inst.operands[0].reg << r0off;
6593 encode_thumb32_shifted_operand (1);
6596 switch (inst.instruction)
6599 inst.instruction = T_OPCODE_MOV_HR;
6600 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6601 inst.instruction |= (inst.operands[0].reg & 0x7);
6602 inst.instruction |= inst.operands[1].reg << 3;
6606 /* We know we have low registers at this point.
6607 Generate ADD Rd, Rs, #0. */
6608 inst.instruction = T_OPCODE_ADD_I3;
6609 inst.instruction |= inst.operands[0].reg;
6610 inst.instruction |= inst.operands[1].reg << 3;
6614 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7)
6616 inst.instruction = T_OPCODE_CMP_LR;
6617 inst.instruction |= inst.operands[0].reg;
6618 inst.instruction |= inst.operands[1].reg << 3;
6622 inst.instruction = T_OPCODE_CMP_HR;
6623 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6624 inst.instruction |= (inst.operands[0].reg & 0x7);
6625 inst.instruction |= inst.operands[1].reg << 3;
6632 inst.instruction = THUMB_OP16 (inst.instruction);
6633 if (inst.operands[1].isreg)
6635 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
6637 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
6638 since a MOV instruction produces unpredictable results. */
6639 if (inst.instruction == T_OPCODE_MOV_I8)
6640 inst.instruction = T_OPCODE_ADD_I3;
6642 inst.instruction = T_OPCODE_CMP_LR;
6644 inst.instruction |= inst.operands[0].reg;
6645 inst.instruction |= inst.operands[1].reg << 3;
6649 if (inst.instruction == T_OPCODE_MOV_I8)
6650 inst.instruction = T_OPCODE_MOV_HR;
6652 inst.instruction = T_OPCODE_CMP_HR;
6658 constraint (inst.operands[0].reg > 7,
6659 _("only lo regs allowed with immediate"));
6660 inst.instruction |= inst.operands[0].reg << 8;
6661 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
6668 inst.instruction |= inst.operands[0].reg << 8;
6669 inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
6670 inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
6671 inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
6672 inst.instruction |= (inst.operands[1].imm & 0x00ff);
6680 int r0off = (inst.instruction == T_MNEM_mvn
6681 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
6682 if (!inst.operands[1].isreg)
6684 /* For an immediate, we always generate a 32-bit opcode;
6685 section relaxation will shrink it later if possible. */
6686 if (inst.instruction < 0xffff)
6687 inst.instruction = THUMB_OP32 (inst.instruction);
6688 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6689 inst.instruction |= inst.operands[0].reg << r0off;
6690 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6694 /* See if we can do this with a 16-bit instruction. */
6695 if (inst.instruction < 0xffff
6696 && THUMB_SETS_FLAGS (inst.instruction)
6697 && !inst.operands[1].shifted
6698 && inst.operands[0].reg <= 7
6699 && inst.operands[1].reg <= 7
6700 && inst.size_req != 4)
6702 inst.instruction = THUMB_OP16 (inst.instruction);
6703 inst.instruction |= inst.operands[0].reg;
6704 inst.instruction |= inst.operands[1].reg << 3;
6708 constraint (inst.operands[1].shifted
6709 && inst.operands[1].immisreg,
6710 _("shift must be constant"));
6711 if (inst.instruction < 0xffff)
6712 inst.instruction = THUMB_OP32 (inst.instruction);
6713 inst.instruction |= inst.operands[0].reg << r0off;
6714 encode_thumb32_shifted_operand (1);
6720 constraint (inst.instruction > 0xffff
6721 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
6722 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
6723 _("unshifted register required"));
6724 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6727 inst.instruction = THUMB_OP16 (inst.instruction);
6728 inst.instruction |= inst.operands[0].reg;
6729 inst.instruction |= inst.operands[1].reg << 3;
6736 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
6737 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
6739 _("'CPSR' or 'SPSR' expected"));
6740 inst.instruction |= inst.operands[0].reg << 8;
6741 inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2;
6747 constraint (!inst.operands[1].isreg,
6748 _("Thumb encoding does not support an immediate here"));
6749 inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2;
6750 inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8;
6751 inst.instruction |= inst.operands[1].reg << 16;
6757 if (!inst.operands[2].present)
6758 inst.operands[2].reg = inst.operands[0].reg;
6760 /* There is no 32-bit MULS and no 16-bit MUL. */
6761 if (unified_syntax && inst.instruction == T_MNEM_mul)
6763 inst.instruction = THUMB_OP32 (inst.instruction);
6764 inst.instruction |= inst.operands[0].reg << 8;
6765 inst.instruction |= inst.operands[1].reg << 16;
6766 inst.instruction |= inst.operands[2].reg << 0;
6770 constraint (!unified_syntax
6771 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
6772 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6775 inst.instruction = THUMB_OP16 (inst.instruction);
6776 inst.instruction |= inst.operands[0].reg;
6778 if (inst.operands[0].reg == inst.operands[1].reg)
6779 inst.instruction |= inst.operands[2].reg << 3;
6780 else if (inst.operands[0].reg == inst.operands[2].reg)
6781 inst.instruction |= inst.operands[1].reg << 3;
6783 constraint (1, _("dest must overlap one source register"));
6790 inst.instruction |= inst.operands[0].reg << 12;
6791 inst.instruction |= inst.operands[1].reg << 8;
6792 inst.instruction |= inst.operands[2].reg << 16;
6793 inst.instruction |= inst.operands[3].reg;
6795 if (inst.operands[0].reg == inst.operands[1].reg)
6796 as_tsktsk (_("rdhi and rdlo must be different"));
6804 if (inst.size_req == 4 || inst.operands[0].imm > 15)
6806 inst.instruction = THUMB_OP32 (inst.instruction);
6807 inst.instruction |= inst.operands[0].imm;
6811 inst.instruction = THUMB_OP16 (inst.instruction);
6812 inst.instruction |= inst.operands[0].imm << 4;
6817 constraint (inst.operands[0].present,
6818 _("Thumb does not support NOP with hints"));
6819 inst.instruction = 0x46c0;
6828 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7
6829 || !THUMB_SETS_FLAGS (inst.instruction)
6830 || inst.size_req == 4)
6832 inst.instruction = THUMB_OP32 (inst.instruction);
6833 inst.instruction |= inst.operands[0].reg << 8;
6834 inst.instruction |= inst.operands[1].reg << 16;
6838 inst.instruction = THUMB_OP16 (inst.instruction);
6839 inst.instruction |= inst.operands[0].reg;
6840 inst.instruction |= inst.operands[1].reg << 3;
6845 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6847 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6849 inst.instruction = THUMB_OP16 (inst.instruction);
6850 inst.instruction |= inst.operands[0].reg;
6851 inst.instruction |= inst.operands[1].reg << 3;
6858 inst.instruction |= inst.operands[0].reg << 8;
6859 inst.instruction |= inst.operands[1].reg << 16;
6860 inst.instruction |= inst.operands[2].reg;
6861 if (inst.operands[3].present)
6863 unsigned int val = inst.reloc.exp.X_add_number;
6864 constraint (inst.reloc.exp.X_op != O_constant,
6865 _("expression too complex"));
6866 inst.instruction |= (val & 0x1c) << 10;
6867 inst.instruction |= (val & 0x03) << 6;
6874 if (!inst.operands[3].present)
6875 inst.instruction &= ~0x00000020;
6882 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
6886 do_t_push_pop (void)
6888 constraint (inst.operands[0].writeback,
6889 _("push/pop do not support {reglist}^"));
6890 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6891 _("expression too complex"));
6893 if ((inst.operands[0].imm & ~0xff) == 0)
6894 inst.instruction = THUMB_OP16 (inst.instruction);
6895 else if ((inst.instruction == T_MNEM_push
6896 && (inst.operands[0].imm & ~0xff) == 1 << REG_LR)
6897 || (inst.instruction == T_MNEM_pop
6898 && (inst.operands[0].imm & ~0xff) == 1 << REG_PC))
6900 inst.instruction = THUMB_OP16 (inst.instruction);
6901 inst.instruction |= THUMB_PP_PC_LR;
6902 inst.operands[0].imm &= 0xff;
6904 else if (unified_syntax)
6906 if (inst.operands[1].imm & (1 << 13))
6907 as_warn (_("SP should not be in register list"));
6908 if (inst.instruction == T_MNEM_push)
6910 if (inst.operands[1].imm & (1 << 15))
6911 as_warn (_("PC should not be in register list"));
6915 if (inst.operands[1].imm & (1 << 14)
6916 && inst.operands[1].imm & (1 << 15))
6917 as_warn (_("LR and PC should not both be in register list"));
6920 inst.instruction = THUMB_OP32 (inst.instruction);
6924 inst.error = _("invalid register list to push/pop instruction");
6928 inst.instruction |= inst.operands[0].imm;
6934 inst.instruction |= inst.operands[0].reg << 8;
6935 inst.instruction |= inst.operands[1].reg << 16;
6941 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
6942 && inst.size_req != 4)
6944 inst.instruction = THUMB_OP16 (inst.instruction);
6945 inst.instruction |= inst.operands[0].reg;
6946 inst.instruction |= inst.operands[1].reg << 3;
6948 else if (unified_syntax)
6950 inst.instruction = THUMB_OP32 (inst.instruction);
6951 inst.instruction |= inst.operands[0].reg << 8;
6952 inst.instruction |= inst.operands[1].reg << 16;
6953 inst.instruction |= inst.operands[1].reg;
6956 inst.error = BAD_HIREG;
6964 Rd = inst.operands[0].reg;
6965 Rs = (inst.operands[1].present
6966 ? inst.operands[1].reg /* Rd, Rs, foo */
6967 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6969 inst.instruction |= Rd << 8;
6970 inst.instruction |= Rs << 16;
6971 if (!inst.operands[2].isreg)
6973 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6974 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6977 encode_thumb32_shifted_operand (2);
6983 if (inst.operands[0].imm)
6984 inst.instruction |= 0x8;
6990 if (!inst.operands[1].present)
6991 inst.operands[1].reg = inst.operands[0].reg;
6995 if (inst.operands[0].reg > 7
6996 || inst.operands[1].reg > 7
6997 || !THUMB_SETS_FLAGS (inst.instruction)
6998 || (!inst.operands[2].isreg && inst.instruction == T_MNEM_rors)
6999 || (inst.operands[2].isreg && inst.operands[1].reg != inst.operands[0].reg)
7000 || inst.size_req == 4)
7002 if (inst.operands[2].isreg)
7004 inst.instruction = THUMB_OP32 (inst.instruction);
7005 inst.instruction |= inst.operands[0].reg << 8;
7006 inst.instruction |= inst.operands[1].reg << 16;
7007 inst.instruction |= inst.operands[2].reg;
7011 inst.operands[1].shifted = 1;
7012 switch (inst.instruction)
7015 case T_MNEM_asrs: inst.operands[1].shift_kind = SHIFT_ASR; break;
7017 case T_MNEM_lsls: inst.operands[1].shift_kind = SHIFT_LSL; break;
7019 case T_MNEM_lsrs: inst.operands[1].shift_kind = SHIFT_LSR; break;
7021 case T_MNEM_rors: inst.operands[1].shift_kind = SHIFT_ROR; break;
7025 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
7026 ? T_MNEM_movs : T_MNEM_mov);
7027 inst.instruction |= inst.operands[0].reg << 8;
7028 encode_thumb32_shifted_operand (1);
7029 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7030 inst.reloc.type = BFD_RELOC_UNUSED;
7035 if (inst.operands[2].isreg)
7037 switch (inst.instruction)
7039 case T_MNEM_asrs: inst.instruction = T_OPCODE_ASR_R; break;
7040 case T_MNEM_lsls: inst.instruction = T_OPCODE_LSL_R; break;
7041 case T_MNEM_lsrs: inst.instruction = T_OPCODE_LSR_R; break;
7042 case T_MNEM_rors: inst.instruction = T_OPCODE_ROR_R; break;
7046 inst.instruction |= inst.operands[0].reg;
7047 inst.instruction |= inst.operands[2].reg << 3;
7051 switch (inst.instruction)
7053 case T_MNEM_asrs: inst.instruction = T_OPCODE_ASR_I; break;
7054 case T_MNEM_lsls: inst.instruction = T_OPCODE_LSL_I; break;
7055 case T_MNEM_lsrs: inst.instruction = T_OPCODE_LSR_I; break;
7058 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7059 inst.instruction |= inst.operands[0].reg;
7060 inst.instruction |= inst.operands[1].reg << 3;
7066 constraint (inst.operands[0].reg > 7
7067 || inst.operands[1].reg > 7, BAD_HIREG);
7068 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7070 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
7072 constraint (inst.operands[2].reg > 7, BAD_HIREG);
7073 constraint (inst.operands[0].reg != inst.operands[1].reg,
7074 _("source1 and dest must be same register"));
7076 switch (inst.instruction)
7078 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
7079 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
7080 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
7081 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
7085 inst.instruction |= inst.operands[0].reg;
7086 inst.instruction |= inst.operands[2].reg << 3;
7090 switch (inst.instruction)
7092 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
7093 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
7094 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
7095 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
7098 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7099 inst.instruction |= inst.operands[0].reg;
7100 inst.instruction |= inst.operands[1].reg << 3;
7108 inst.instruction |= inst.operands[0].reg << 8;
7109 inst.instruction |= inst.operands[1].reg << 16;
7110 inst.instruction |= inst.operands[2].reg;
7116 unsigned int value = inst.reloc.exp.X_add_number;
7117 constraint (inst.reloc.exp.X_op != O_constant,
7118 _("expression too complex"));
7119 inst.reloc.type = BFD_RELOC_UNUSED;
7120 inst.instruction |= (value & 0xf000) >> 12;
7121 inst.instruction |= (value & 0x0ff0);
7122 inst.instruction |= (value & 0x000f) << 16;
7128 inst.instruction |= inst.operands[0].reg << 8;
7129 inst.instruction |= inst.operands[1].imm - 1;
7130 inst.instruction |= inst.operands[2].reg << 16;
7132 if (inst.operands[3].present)
7134 constraint (inst.reloc.exp.X_op != O_constant,
7135 _("expression too complex"));
7137 if (inst.reloc.exp.X_add_number != 0)
7139 if (inst.operands[3].shift_kind == SHIFT_ASR)
7140 inst.instruction |= 0x00200000; /* sh bit */
7141 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7142 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7144 inst.reloc.type = BFD_RELOC_UNUSED;
7151 inst.instruction |= inst.operands[0].reg << 8;
7152 inst.instruction |= inst.operands[1].imm - 1;
7153 inst.instruction |= inst.operands[2].reg << 16;
7159 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7160 || inst.operands[2].postind || inst.operands[2].writeback
7161 || inst.operands[2].immisreg || inst.operands[2].shifted
7162 || inst.operands[2].negative,
7163 _("instruction does not accept this addressing mode"));
7165 inst.instruction |= inst.operands[0].reg << 8;
7166 inst.instruction |= inst.operands[1].reg << 12;
7167 inst.instruction |= inst.operands[2].reg << 16;
7168 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
7174 if (!inst.operands[2].present)
7175 inst.operands[2].reg = inst.operands[1].reg + 1;
7177 constraint (inst.operands[0].reg == inst.operands[1].reg
7178 || inst.operands[0].reg == inst.operands[2].reg
7179 || inst.operands[0].reg == inst.operands[3].reg
7180 || inst.operands[1].reg == inst.operands[2].reg,
7183 inst.instruction |= inst.operands[0].reg;
7184 inst.instruction |= inst.operands[1].reg << 12;
7185 inst.instruction |= inst.operands[2].reg << 8;
7186 inst.instruction |= inst.operands[3].reg << 16;
7192 inst.instruction |= inst.operands[0].reg << 8;
7193 inst.instruction |= inst.operands[1].reg << 16;
7194 inst.instruction |= inst.operands[2].reg;
7195 inst.instruction |= inst.operands[3].imm << 4;
7201 if (inst.instruction <= 0xffff && inst.size_req != 4
7202 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7203 && (!inst.operands[2].present || inst.operands[2].imm == 0))
7205 inst.instruction = THUMB_OP16 (inst.instruction);
7206 inst.instruction |= inst.operands[0].reg;
7207 inst.instruction |= inst.operands[1].reg << 3;
7209 else if (unified_syntax)
7211 if (inst.instruction <= 0xffff)
7212 inst.instruction = THUMB_OP32 (inst.instruction);
7213 inst.instruction |= inst.operands[0].reg << 8;
7214 inst.instruction |= inst.operands[1].reg;
7215 inst.instruction |= inst.operands[2].imm << 4;
7219 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
7220 _("Thumb encoding does not support rotation"));
7221 constraint (1, BAD_HIREG);
7228 inst.reloc.type = BFD_RELOC_ARM_SWI;
7234 inst.instruction |= inst.operands[0].reg << 8;
7235 inst.instruction |= inst.operands[1].imm;
7236 inst.instruction |= inst.operands[2].reg << 16;
7238 if (inst.operands[3].present)
7240 constraint (inst.reloc.exp.X_op != O_constant,
7241 _("expression too complex"));
7242 if (inst.reloc.exp.X_add_number != 0)
7244 if (inst.operands[3].shift_kind == SHIFT_ASR)
7245 inst.instruction |= 0x00200000; /* sh bit */
7247 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7248 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7250 inst.reloc.type = BFD_RELOC_UNUSED;
7257 inst.instruction |= inst.operands[0].reg << 8;
7258 inst.instruction |= inst.operands[1].imm;
7259 inst.instruction |= inst.operands[2].reg << 16;
7262 /* Overall per-instruction processing. */
7264 /* We need to be able to fix up arbitrary expressions in some statements.
7265 This is so that we can handle symbols that are an arbitrary distance from
7266 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7267 which returns part of an address in a form which will be valid for
7268 a data instruction. We do this by pushing the expression into a symbol
7269 in the expr_section, and creating a fix for that. */
7272 fix_new_arm (fragS * frag,
7287 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7291 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7296 /* Mark whether the fix is to a THUMB instruction, or an ARM
7298 new_fix->tc_fix_data = thumb_mode;
7302 output_inst (const char * str)
7308 as_bad ("%s -- `%s'", inst.error, str);
7314 to = frag_more (inst.size);
7316 if (thumb_mode && (inst.size > THUMB_SIZE))
7318 assert (inst.size == (2 * THUMB_SIZE));
7319 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
7320 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
7322 else if (inst.size > INSN_SIZE)
7324 assert (inst.size == (2 * INSN_SIZE));
7325 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7326 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
7329 md_number_to_chars (to, inst.instruction, inst.size);
7331 if (inst.reloc.type != BFD_RELOC_UNUSED)
7332 fix_new_arm (frag_now, to - frag_now->fr_literal,
7333 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7337 dwarf2_emit_insn (inst.size);
7341 /* Tag values used in struct asm_opcode's tag field. */
7344 OT_unconditional, /* Instruction cannot be conditionalized.
7345 The ARM condition field is still 0xE. */
7346 OT_unconditionalF, /* Instruction cannot be conditionalized
7347 and carries 0xF in its ARM condition field. */
7348 OT_csuffix, /* Instruction takes a conditional suffix. */
7349 OT_cinfix3, /* Instruction takes a conditional infix,
7350 beginning at character index 3. (In
7351 unified mode, it becomes a suffix.) */
7352 OT_csuf_or_in3, /* Instruction takes either a conditional
7353 suffix or an infix at character index 3.
7354 (In unified mode, a suffix only. */
7355 OT_odd_infix_unc, /* This is the unconditional variant of an
7356 instruction that takes a conditional infix
7357 at an unusual position. In unified mode,
7358 this variant will accept a suffix. */
7359 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
7360 are the conditional variants of instructions that
7361 take conditional infixes in unusual positions.
7362 The infix appears at character index
7363 (tag - OT_odd_infix_0). These are not accepted
7367 /* Subroutine of md_assemble, responsible for looking up the primary
7368 opcode from the mnemonic the user wrote. STR points to the
7369 beginning of the mnemonic.
7371 This is not simply a hash table lookup, because of conditional
7372 variants. Most instructions have conditional variants, which are
7373 expressed with a _conditional affix_ to the mnemonic. If we were
7374 to encode each conditional variant as a literal string in the opcode
7375 table, it would have approximately 20,000 entries.
7377 Most mnemonics take this affix as a suffix, and in unified syntax,
7378 'most' is upgraded to 'all'. However, in the divided syntax, some
7379 instructions take the affix as an infix, notably the s-variants of
7380 the arithmetic instructions. Of those instructions, all but six
7381 have the infix appear after the third character of the mnemonic.
7383 Accordingly, the algorithm for looking up primary opcodes given
7386 1. Look up the identifier in the opcode table.
7387 If we find a match, go to step U.
7389 2. Look up the last two characters of the identifier in the
7390 conditions table. If we find a match, look up the first N-2
7391 characters of the identifier in the opcode table. If we
7392 find a match, go to step CE.
7394 3. Look up the fourth and fifth characters of the identifier in
7395 the conditions table. If we find a match, extract those
7396 characters from the identifier, and look up the remaining
7397 characters in the opcode table. If we find a match, go
7402 U. Examine the tag field of the opcode structure, in case this is
7403 one of the six instructions with its conditional infix in an
7404 unusual place. If it is, the tag tells us where to find the
7405 infix; look it up in the conditions table and set inst.cond
7406 accordingly. Otherwise, this is an unconditional instruction.
7407 Again set inst.cond accordingly. Return the opcode structure.
7409 CE. Examine the tag field to make sure this is an instruction that
7410 should receive a conditional suffix. If it is not, fail.
7411 Otherwise, set inst.cond from the suffix we already looked up,
7412 and return the opcode structure.
7414 CM. Examine the tag field to make sure this is an instruction that
7415 should receive a conditional infix after the third character.
7416 If it is not, fail. Otherwise, undo the edits to the current
7417 line of input and proceed as for case CE. */
7419 static const struct asm_opcode *
7420 opcode_lookup (char **str)
7424 const struct asm_opcode *opcode;
7425 const struct asm_cond *cond;
7427 /* Scan up to the end of the mnemonic, which must end in white space,
7428 '.' (in unified mode only), or end of string. */
7429 for (base = end = *str; *end != '\0'; end++)
7430 if (*end == ' ' || (unified_syntax && *end == '.'))
7436 /* Handle a possible width suffix. */
7439 if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
7441 else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
7451 /* Look for unaffixed or special-case affixed mnemonic. */
7452 opcode = hash_find_n (arm_ops_hsh, base, end - base);
7456 if (opcode->tag < OT_odd_infix_0)
7458 inst.cond = COND_ALWAYS;
7463 as_warn (_("conditional infixes are deprecated in unified syntax"));
7464 affix = base + (opcode->tag - OT_odd_infix_0);
7465 cond = hash_find_n (arm_cond_hsh, affix, 2);
7468 inst.cond = cond->value;
7472 /* Cannot have a conditional suffix on a mnemonic of less than two
7477 /* Look for suffixed mnemonic. */
7479 cond = hash_find_n (arm_cond_hsh, affix, 2);
7480 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
7484 switch (opcode->tag)
7487 case OT_odd_infix_unc:
7488 if (!unified_syntax)
7490 /* else fall through */
7493 case OT_csuf_or_in3:
7494 inst.cond = cond->value;
7497 case OT_unconditional:
7498 case OT_unconditionalF:
7499 /* delayed diagnostic */
7500 inst.error = BAD_COND;
7501 inst.cond = COND_ALWAYS;
7509 /* Cannot have a usual-position infix on a mnemonic of less than
7510 six characters (five would be a suffix). */
7514 /* Look for infixed mnemonic in the usual position. */
7516 cond = hash_find_n (arm_cond_hsh, affix, 2);
7520 memcpy (save, affix, 2);
7521 memmove (affix, affix + 2, (end - affix) - 2);
7522 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
7523 memmove (affix + 2, affix, (end - affix) - 2);
7524 memcpy (affix, save, 2);
7526 if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3))
7530 as_warn (_("conditional infixes are deprecated in unified syntax"));
7532 inst.cond = cond->value;
7540 md_assemble (char *str)
7543 const struct asm_opcode * opcode;
7545 /* Align the previous label if needed. */
7546 if (last_label_seen != NULL)
7548 symbol_set_frag (last_label_seen, frag_now);
7549 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
7550 S_SET_SEGMENT (last_label_seen, now_seg);
7553 memset (&inst, '\0', sizeof (inst));
7554 inst.reloc.type = BFD_RELOC_UNUSED;
7556 opcode = opcode_lookup (&p);
7559 /* It wasn't an instruction, but it might be a register alias of
7560 the form alias .req reg. */
7561 if (!create_register_alias (str, p))
7562 as_bad (_("bad instruction `%s'"), str);
7569 /* Check that this instruction is supported for this CPU. */
7570 if (thumb_mode == 1 && (opcode->tvariant & cpu_variant) == 0)
7572 as_bad (_("selected processor does not support `%s'"), str);
7575 if (inst.cond != COND_ALWAYS && !unified_syntax
7576 && opcode->tencode != do_t_branch)
7578 as_bad (_("Thumb does not support conditional execution"));
7582 mapping_state (MAP_THUMB);
7583 inst.instruction = opcode->tvalue;
7585 if (!parse_operands (p, opcode->operands))
7590 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
7591 inst.size = (inst.instruction > 0xffff ? 4 : 2);
7592 if (inst.size_req && inst.size_req != inst.size)
7594 as_bad (_("cannot honor width suffix -- `%s'"), str);
7601 /* Check that this instruction is supported for this CPU. */
7602 if ((opcode->avariant & cpu_variant) == 0)
7604 as_bad (_("selected processor does not support `%s'"), str);
7609 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
7613 mapping_state (MAP_ARM);
7614 inst.instruction = opcode->avalue;
7615 if (opcode->tag == OT_unconditionalF)
7616 inst.instruction |= 0xF << 28;
7618 inst.instruction |= inst.cond << 28;
7619 inst.size = INSN_SIZE;
7620 if (!parse_operands (p, opcode->operands))
7626 /* Various frobbings of labels and their addresses. */
7629 arm_start_line_hook (void)
7631 last_label_seen = NULL;
7635 arm_frob_label (symbolS * sym)
7637 last_label_seen = sym;
7639 ARM_SET_THUMB (sym, thumb_mode);
7641 #if defined OBJ_COFF || defined OBJ_ELF
7642 ARM_SET_INTERWORK (sym, support_interwork);
7645 /* Note - do not allow local symbols (.Lxxx) to be labeled
7646 as Thumb functions. This is because these labels, whilst
7647 they exist inside Thumb code, are not the entry points for
7648 possible ARM->Thumb calls. Also, these labels can be used
7649 as part of a computed goto or switch statement. eg gcc
7650 can generate code that looks like this:
7662 The first instruction loads the address of the jump table.
7663 The second instruction converts a table index into a byte offset.
7664 The third instruction gets the jump address out of the table.
7665 The fourth instruction performs the jump.
7667 If the address stored at .Laaa is that of a symbol which has the
7668 Thumb_Func bit set, then the linker will arrange for this address
7669 to have the bottom bit set, which in turn would mean that the
7670 address computation performed by the third instruction would end
7671 up with the bottom bit set. Since the ARM is capable of unaligned
7672 word loads, the instruction would then load the incorrect address
7673 out of the jump table, and chaos would ensue. */
7674 if (label_is_thumb_function_name
7675 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
7676 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
7678 /* When the address of a Thumb function is taken the bottom
7679 bit of that address should be set. This will allow
7680 interworking between Arm and Thumb functions to work
7683 THUMB_SET_FUNC (sym, 1);
7685 label_is_thumb_function_name = FALSE;
7690 arm_data_in_code (void)
7692 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7694 *input_line_pointer = '/';
7695 input_line_pointer += 5;
7696 *input_line_pointer = 0;
7704 arm_canonicalize_symbol_name (char * name)
7708 if (thumb_mode && (len = strlen (name)) > 5
7709 && streq (name + len - 5, "/data"))
7710 *(name + len - 5) = 0;
7715 /* Table of all register names defined by default. The user can
7716 define additional names with .req. Note that all register names
7717 should appear in both upper and lowercase variants. Some registers
7718 also have mixed-case names. */
7720 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7721 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7722 #define REGSET(p,t) \
7723 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7724 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7725 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7726 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7728 static const struct reg_entry reg_names[] =
7730 /* ARM integer registers. */
7731 REGSET(r, RN), REGSET(R, RN),
7733 /* ATPCS synonyms. */
7734 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
7735 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
7736 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7738 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
7739 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
7740 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7742 /* Well-known aliases. */
7743 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
7744 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
7746 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
7747 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
7749 /* Coprocessor numbers. */
7750 REGSET(p, CP), REGSET(P, CP),
7752 /* Coprocessor register numbers. The "cr" variants are for backward
7754 REGSET(c, CN), REGSET(C, CN),
7755 REGSET(cr, CN), REGSET(CR, CN),
7757 /* FPA registers. */
7758 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
7759 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
7761 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
7762 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
7764 /* VFP SP registers. */
7766 REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
7767 REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
7768 REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
7769 REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
7772 REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
7773 REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
7774 REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
7775 REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
7777 /* VFP DP Registers. */
7778 REGSET(d,VFD), REGSET(D,VFS),
7780 /* VFP control registers. */
7781 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
7782 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
7784 /* Maverick DSP coprocessor registers. */
7785 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
7786 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
7788 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
7789 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
7790 REGDEF(dspsc,0,DSPSC),
7792 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
7793 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
7794 REGDEF(DSPSC,0,DSPSC),
7796 /* iWMMXt data registers - p0, c0-15. */
7797 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
7799 /* iWMMXt control registers - p1, c0-3. */
7800 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
7801 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
7802 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
7803 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
7805 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
7806 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
7807 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
7808 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
7809 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
7811 /* XScale accumulator registers. */
7812 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
7818 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
7819 within psr_required_here. */
7820 static const struct asm_psr psrs[] =
7822 /* Backward compatibility notation. Note that "all" is no longer
7823 truly all possible PSR bits. */
7824 {"all", PSR_c | PSR_f},
7828 /* Individual flags. */
7833 /* Combinations of flags. */
7834 {"fs", PSR_f | PSR_s},
7835 {"fx", PSR_f | PSR_x},
7836 {"fc", PSR_f | PSR_c},
7837 {"sf", PSR_s | PSR_f},
7838 {"sx", PSR_s | PSR_x},
7839 {"sc", PSR_s | PSR_c},
7840 {"xf", PSR_x | PSR_f},
7841 {"xs", PSR_x | PSR_s},
7842 {"xc", PSR_x | PSR_c},
7843 {"cf", PSR_c | PSR_f},
7844 {"cs", PSR_c | PSR_s},
7845 {"cx", PSR_c | PSR_x},
7846 {"fsx", PSR_f | PSR_s | PSR_x},
7847 {"fsc", PSR_f | PSR_s | PSR_c},
7848 {"fxs", PSR_f | PSR_x | PSR_s},
7849 {"fxc", PSR_f | PSR_x | PSR_c},
7850 {"fcs", PSR_f | PSR_c | PSR_s},
7851 {"fcx", PSR_f | PSR_c | PSR_x},
7852 {"sfx", PSR_s | PSR_f | PSR_x},
7853 {"sfc", PSR_s | PSR_f | PSR_c},
7854 {"sxf", PSR_s | PSR_x | PSR_f},
7855 {"sxc", PSR_s | PSR_x | PSR_c},
7856 {"scf", PSR_s | PSR_c | PSR_f},
7857 {"scx", PSR_s | PSR_c | PSR_x},
7858 {"xfs", PSR_x | PSR_f | PSR_s},
7859 {"xfc", PSR_x | PSR_f | PSR_c},
7860 {"xsf", PSR_x | PSR_s | PSR_f},
7861 {"xsc", PSR_x | PSR_s | PSR_c},
7862 {"xcf", PSR_x | PSR_c | PSR_f},
7863 {"xcs", PSR_x | PSR_c | PSR_s},
7864 {"cfs", PSR_c | PSR_f | PSR_s},
7865 {"cfx", PSR_c | PSR_f | PSR_x},
7866 {"csf", PSR_c | PSR_s | PSR_f},
7867 {"csx", PSR_c | PSR_s | PSR_x},
7868 {"cxf", PSR_c | PSR_x | PSR_f},
7869 {"cxs", PSR_c | PSR_x | PSR_s},
7870 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
7871 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
7872 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
7873 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
7874 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
7875 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
7876 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
7877 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
7878 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
7879 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
7880 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
7881 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
7882 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
7883 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
7884 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
7885 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
7886 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
7887 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
7888 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
7889 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
7890 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
7891 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
7892 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
7893 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
7896 /* Table of all shift-in-operand names. */
7897 static const struct asm_shift_name shift_names [] =
7899 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
7900 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
7901 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
7902 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
7903 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
7904 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
7907 /* Table of all explicit relocation names. */
7909 static struct reloc_entry reloc_names[] =
7911 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
7912 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
7913 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
7914 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
7915 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
7916 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
7917 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
7918 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
7919 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
7920 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
7921 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
7925 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
7926 static const struct asm_cond conds[] =
7930 {"cs", 0x2}, {"hs", 0x2},
7931 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
7945 /* Table of ARM-format instructions. */
7947 /* Macros for gluing together operand strings. N.B. In all cases
7948 other than OPS0, the trailing OP_stop comes from default
7949 zero-initialization of the unspecified elements of the array. */
7950 #define OPS0() { OP_stop, }
7951 #define OPS1(a) { OP_##a, }
7952 #define OPS2(a,b) { OP_##a,OP_##b, }
7953 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
7954 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
7955 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
7956 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
7958 /* These macros abstract out the exact format of the mnemonic table and
7959 save some repeated characters. */
7961 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
7962 #define TxCE(mnem, op, top, nops, ops, ae, te) \
7963 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
7964 THUMB_VARIANT, do_##ae, do_##te }
7966 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
7967 a T_MNEM_xyz enumerator. */
7968 #define TCE(mnem, aop, top, nops, ops, ae, te) \
7969 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
7970 #define tCE(mnem, aop, top, nops, ops, ae, te) \
7971 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
7973 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
7974 infix after the third character. */
7975 #define TxC3(mnem, op, top, nops, ops, ae, te) \
7976 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
7977 THUMB_VARIANT, do_##ae, do_##te }
7978 #define TC3(mnem, aop, top, nops, ops, ae, te) \
7979 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
7980 #define tC3(mnem, aop, top, nops, ops, ae, te) \
7981 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
7983 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
7984 appear in the condition table. */
7985 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
7986 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
7987 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
7989 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
7990 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
7991 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
7992 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
7993 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
7994 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
7995 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
7996 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
7997 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
7998 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
7999 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8000 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8001 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8002 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8003 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8004 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8005 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8006 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8007 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8008 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8010 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8011 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8012 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8013 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8015 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8016 field is still 0xE. */
8017 #define TUE(mnem, op, top, nops, ops, ae, te) \
8018 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8019 THUMB_VARIANT, do_##ae, do_##te }
8021 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8022 condition code field. */
8023 #define TUF(mnem, op, top, nops, ops, ae, te) \
8024 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8025 THUMB_VARIANT, do_##ae, do_##te }
8027 /* ARM-only variants of all the above. */
8028 #define CE(mnem, op, nops, ops, ae) \
8029 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8031 #define C3(mnem, op, nops, ops, ae) \
8032 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8034 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8035 { #m1 #m2 #m3, OPS##nops ops, \
8036 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8037 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8039 #define CM(m1, m2, op, nops, ops, ae) \
8040 xCM_(m1, , m2, op, nops, ops, ae), \
8041 xCM_(m1, eq, m2, op, nops, ops, ae), \
8042 xCM_(m1, ne, m2, op, nops, ops, ae), \
8043 xCM_(m1, cs, m2, op, nops, ops, ae), \
8044 xCM_(m1, hs, m2, op, nops, ops, ae), \
8045 xCM_(m1, cc, m2, op, nops, ops, ae), \
8046 xCM_(m1, ul, m2, op, nops, ops, ae), \
8047 xCM_(m1, lo, m2, op, nops, ops, ae), \
8048 xCM_(m1, mi, m2, op, nops, ops, ae), \
8049 xCM_(m1, pl, m2, op, nops, ops, ae), \
8050 xCM_(m1, vs, m2, op, nops, ops, ae), \
8051 xCM_(m1, vc, m2, op, nops, ops, ae), \
8052 xCM_(m1, hi, m2, op, nops, ops, ae), \
8053 xCM_(m1, ls, m2, op, nops, ops, ae), \
8054 xCM_(m1, ge, m2, op, nops, ops, ae), \
8055 xCM_(m1, lt, m2, op, nops, ops, ae), \
8056 xCM_(m1, gt, m2, op, nops, ops, ae), \
8057 xCM_(m1, le, m2, op, nops, ops, ae), \
8058 xCM_(m1, al, m2, op, nops, ops, ae)
8060 #define UE(mnem, op, nops, ops, ae) \
8061 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8063 #define UF(mnem, op, nops, ops, ae) \
8064 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8068 /* Thumb-only, unconditional. */
8069 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8071 /* ARM-only, takes either a suffix or a position-3 infix
8072 (for an FPA corner case). */
8073 #define C3E(mnem, op, nops, ops, ae) \
8074 { #mnem, OPS##nops ops, OT_csuf_or_in3, 0x##op, 0, ARM_VARIANT, 0, do_##ae, 0 }
8076 static const struct asm_opcode insns[] =
8078 #define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
8079 #define THUMB_VARIANT ARM_EXT_V4T
8080 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
8081 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
8082 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
8083 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
8084 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
8085 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
8086 tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
8087 tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
8088 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
8089 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
8090 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
8091 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
8092 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
8093 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
8094 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
8095 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
8097 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8098 for setting PSR flag bits. They are obsolete in V6 and do not
8099 have Thumb equivalents. */
8100 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8101 tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8102 C3(tstp, 110f000, 2, (RR, SH), cmp),
8103 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8104 tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8105 C3(cmpp, 150f000, 2, (RR, SH), cmp),
8106 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8107 tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8108 C3(cmnp, 170f000, 2, (RR, SH), cmp),
8110 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
8111 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
8112 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
8113 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
8115 tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
8116 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
8117 tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
8118 tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
8120 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8121 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8122 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8123 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8125 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
8127 /* XXX This is the wrong place to do this. Think multi-arch. */
8128 TCE(b, a000000, e7fe, 1, (EXPr), branch, t_branch),
8129 TCE(bl, b000000, f7fffffe, 1, (EXPr), branch, t_branch23),
8131 TCE(b, afffffe, e7fe, 1, (EXPr), branch, t_branch),
8132 TCE(bl, bfffffe, f7fffffe, 1, (EXPr), branch, t_branch23),
8136 TCE(adr, 28f0000, 000f, 2, (RR, EXP), adr, t_adr),
8137 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
8138 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
8140 /* Thumb-compatibility pseudo ops. */
8141 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
8142 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
8143 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
8144 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
8145 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
8146 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
8147 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
8148 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
8149 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
8150 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
8151 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
8152 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
8154 #undef THUMB_VARIANT
8155 #define THUMB_VARIANT ARM_EXT_V6
8156 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
8158 /* V1 instructions with no Thumb analogue prior to V6T2. */
8159 #undef THUMB_VARIANT
8160 #define THUMB_VARIANT ARM_EXT_V6T2
8161 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
8162 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
8163 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8164 TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8165 C3(teqp, 130f000, 2, (RR, SH), cmp),
8167 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
8168 TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt),
8169 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
8170 TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt),
8172 TC3(stmdb, 9000000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8173 TC3(stmfd, 9000000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8175 TC3(ldmdb, 9100000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8176 TC3(ldmea, 9100000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8178 /* V1 instructions with no Thumb analogue at all. */
8179 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
8180 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
8182 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
8183 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
8184 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
8185 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
8186 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
8187 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
8188 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
8189 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
8192 #define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
8193 #undef THUMB_VARIANT
8194 #define THUMB_VARIANT ARM_EXT_V4T
8195 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8196 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8198 #undef THUMB_VARIANT
8199 #define THUMB_VARIANT ARM_EXT_V6T2
8200 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8201 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
8203 /* Generic coprocessor instructions. */
8204 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8205 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8206 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8207 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8208 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8209 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8210 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8213 #define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
8214 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8215 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8218 #define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
8219 TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs),
8220 TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
8223 #define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
8224 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8225 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8226 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8227 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8228 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8229 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8230 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8231 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8234 #define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
8235 #undef THUMB_VARIANT
8236 #define THUMB_VARIANT ARM_EXT_V4T
8237 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
8238 tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
8239 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8240 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8241 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8242 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8245 #define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
8246 /* ARM Architecture 4T. */
8247 /* Note: bx (and blx) are required on V5, even if the processor does
8248 not support Thumb. */
8249 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
8252 #define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
8253 #undef THUMB_VARIANT
8254 #define THUMB_VARIANT ARM_EXT_V5T
8255 /* Note: blx has 2 variants; the .value coded here is for
8256 BLX(2). Only this variant has conditional execution. */
8257 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
8258 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
8260 #undef THUMB_VARIANT
8261 #define THUMB_VARIANT ARM_EXT_V6T2
8262 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
8263 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8264 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8265 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8266 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8267 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8268 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8269 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8272 #define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
8273 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8274 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8275 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8276 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8278 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8279 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8281 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8282 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8283 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8284 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8286 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8287 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8288 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8289 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8291 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8292 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8294 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8295 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8296 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8297 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8300 #define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
8301 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
8302 TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8303 TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8305 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8306 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8309 #define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
8310 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
8313 #define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
8314 #undef THUMB_VARIANT
8315 #define THUMB_VARIANT ARM_EXT_V6
8316 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
8317 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
8318 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8319 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8320 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8321 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8322 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8323 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8324 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8325 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
8327 #undef THUMB_VARIANT
8328 #define THUMB_VARIANT ARM_EXT_V6T2
8329 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0),
8330 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
8331 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8332 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8333 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
8334 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
8335 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8336 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8337 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8338 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8339 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8340 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8341 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8342 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8343 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8344 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8345 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8346 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8347 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8348 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8349 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8350 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8351 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8352 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8353 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8354 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8355 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8356 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8357 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8358 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8359 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8360 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8361 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8362 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8363 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8364 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8365 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8366 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8367 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8368 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8369 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8370 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8371 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8372 UF(rfeib, 9900a00, 1, (RRw), rfe),
8373 UF(rfeda, 8100a00, 1, (RRw), rfe),
8374 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8375 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8376 UF(rfefa, 9900a00, 1, (RRw), rfe),
8377 UF(rfeea, 8100a00, 1, (RRw), rfe),
8378 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8379 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8380 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8381 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8382 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8383 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8384 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8385 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8386 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8387 TCE(sel, 68000b0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8388 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8389 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8390 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8391 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8392 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8393 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8394 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8395 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8396 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8397 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8398 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8399 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8400 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8401 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8402 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8403 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8404 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8405 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8406 TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs),
8407 UF(srsib, 9cd0500, 1, (I31w), srs),
8408 UF(srsda, 84d0500, 1, (I31w), srs),
8409 TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs),
8410 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
8411 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
8412 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
8413 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
8414 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8415 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8416 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
8417 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
8420 #define ARM_VARIANT ARM_EXT_V6K
8421 #undef THUMB_VARIANT
8422 #define THUMB_VARIANT ARM_EXT_V6K
8423 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
8424 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
8425 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
8426 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
8428 #undef THUMB_VARIANT
8429 #define THUMB_VARIANT ARM_EXT_V6T2
8430 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
8431 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
8432 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
8433 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
8434 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
8435 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
8436 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
8439 #define ARM_VARIANT ARM_EXT_V6Z
8440 TCE(smi, 1600070, f7f08000, 1, (EXPi), smi, t_smi),
8443 #define ARM_VARIANT ARM_EXT_V6T2
8444 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
8445 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
8446 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
8447 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
8449 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8450 TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16),
8451 TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16),
8452 TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
8454 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8455 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8456 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8457 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8459 UT(cbnz, b900, 2, (RR, EXP), t_czb),
8460 UT(cbz, b100, 2, (RR, EXP), t_czb),
8461 /* ARM does not really have an IT instruction. */
8462 TUE(it, 0, bf08, 1, (COND), it, t_it),
8463 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
8464 TUE(ite, 0, bf04, 1, (COND), it, t_it),
8465 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
8466 TUE(itet, 0, bf06, 1, (COND), it, t_it),
8467 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
8468 TUE(itee, 0, bf02, 1, (COND), it, t_it),
8469 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
8470 TUE(itett, 0, bf07, 1, (COND), it, t_it),
8471 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
8472 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
8473 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
8474 TUE(itete, 0, bf05, 1, (COND), it, t_it),
8475 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
8476 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
8479 #define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
8480 CE(wfs, e200110, 1, (RR), rd),
8481 CE(rfs, e300110, 1, (RR), rd),
8482 CE(wfc, e400110, 1, (RR), rd),
8483 CE(rfc, e500110, 1, (RR), rd),
8485 C3(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
8486 C3(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
8487 C3(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
8488 C3(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
8490 C3(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
8491 C3(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
8492 C3(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
8493 C3(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
8495 C3(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
8496 C3(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
8497 C3(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
8498 C3(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
8499 C3(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
8500 C3(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
8501 C3(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
8502 C3(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
8503 C3(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
8504 C3(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
8505 C3(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
8506 C3(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
8508 C3(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
8509 C3(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
8510 C3(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
8511 C3(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
8512 C3(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
8513 C3(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
8514 C3(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
8515 C3(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
8516 C3(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
8517 C3(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
8518 C3(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
8519 C3(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
8521 C3(abss, e208100, 2, (RF, RF_IF), rd_rm),
8522 C3(abssp, e208120, 2, (RF, RF_IF), rd_rm),
8523 C3(abssm, e208140, 2, (RF, RF_IF), rd_rm),
8524 C3(abssz, e208160, 2, (RF, RF_IF), rd_rm),
8525 C3(absd, e208180, 2, (RF, RF_IF), rd_rm),
8526 C3(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
8527 C3(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
8528 C3(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
8529 C3(abse, e288100, 2, (RF, RF_IF), rd_rm),
8530 C3(absep, e288120, 2, (RF, RF_IF), rd_rm),
8531 C3(absem, e288140, 2, (RF, RF_IF), rd_rm),
8532 C3(absez, e288160, 2, (RF, RF_IF), rd_rm),
8534 C3(rnds, e308100, 2, (RF, RF_IF), rd_rm),
8535 C3(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
8536 C3(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
8537 C3(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
8538 C3(rndd, e308180, 2, (RF, RF_IF), rd_rm),
8539 C3(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
8540 C3(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
8541 C3(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
8542 C3(rnde, e388100, 2, (RF, RF_IF), rd_rm),
8543 C3(rndep, e388120, 2, (RF, RF_IF), rd_rm),
8544 C3(rndem, e388140, 2, (RF, RF_IF), rd_rm),
8545 C3(rndez, e388160, 2, (RF, RF_IF), rd_rm),
8547 C3(sqts, e408100, 2, (RF, RF_IF), rd_rm),
8548 C3(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
8549 C3(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
8550 C3(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
8551 C3(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
8552 C3(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
8553 C3(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
8554 C3(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
8555 C3(sqte, e488100, 2, (RF, RF_IF), rd_rm),
8556 C3(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
8557 C3(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
8558 C3(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
8560 C3(logs, e508100, 2, (RF, RF_IF), rd_rm),
8561 C3(logsp, e508120, 2, (RF, RF_IF), rd_rm),
8562 C3(logsm, e508140, 2, (RF, RF_IF), rd_rm),
8563 C3(logsz, e508160, 2, (RF, RF_IF), rd_rm),
8564 C3(logd, e508180, 2, (RF, RF_IF), rd_rm),
8565 C3(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
8566 C3(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
8567 C3(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
8568 C3(loge, e588100, 2, (RF, RF_IF), rd_rm),
8569 C3(logep, e588120, 2, (RF, RF_IF), rd_rm),
8570 C3(logem, e588140, 2, (RF, RF_IF), rd_rm),
8571 C3(logez, e588160, 2, (RF, RF_IF), rd_rm),
8573 C3(lgns, e608100, 2, (RF, RF_IF), rd_rm),
8574 C3(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
8575 C3(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
8576 C3(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
8577 C3(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
8578 C3(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
8579 C3(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
8580 C3(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
8581 C3(lgne, e688100, 2, (RF, RF_IF), rd_rm),
8582 C3(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
8583 C3(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
8584 C3(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
8586 C3(exps, e708100, 2, (RF, RF_IF), rd_rm),
8587 C3(expsp, e708120, 2, (RF, RF_IF), rd_rm),
8588 C3(expsm, e708140, 2, (RF, RF_IF), rd_rm),
8589 C3(expsz, e708160, 2, (RF, RF_IF), rd_rm),
8590 C3(expd, e708180, 2, (RF, RF_IF), rd_rm),
8591 C3(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
8592 C3(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
8593 C3(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
8594 C3(expe, e788100, 2, (RF, RF_IF), rd_rm),
8595 C3(expep, e788120, 2, (RF, RF_IF), rd_rm),
8596 C3(expem, e788140, 2, (RF, RF_IF), rd_rm),
8597 C3(expdz, e788160, 2, (RF, RF_IF), rd_rm),
8599 C3(sins, e808100, 2, (RF, RF_IF), rd_rm),
8600 C3(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
8601 C3(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
8602 C3(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
8603 C3(sind, e808180, 2, (RF, RF_IF), rd_rm),
8604 C3(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
8605 C3(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
8606 C3(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
8607 C3(sine, e888100, 2, (RF, RF_IF), rd_rm),
8608 C3(sinep, e888120, 2, (RF, RF_IF), rd_rm),
8609 C3(sinem, e888140, 2, (RF, RF_IF), rd_rm),
8610 C3(sinez, e888160, 2, (RF, RF_IF), rd_rm),
8612 C3(coss, e908100, 2, (RF, RF_IF), rd_rm),
8613 C3(cossp, e908120, 2, (RF, RF_IF), rd_rm),
8614 C3(cossm, e908140, 2, (RF, RF_IF), rd_rm),
8615 C3(cossz, e908160, 2, (RF, RF_IF), rd_rm),
8616 C3(cosd, e908180, 2, (RF, RF_IF), rd_rm),
8617 C3(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
8618 C3(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
8619 C3(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
8620 C3(cose, e988100, 2, (RF, RF_IF), rd_rm),
8621 C3(cosep, e988120, 2, (RF, RF_IF), rd_rm),
8622 C3(cosem, e988140, 2, (RF, RF_IF), rd_rm),
8623 C3(cosez, e988160, 2, (RF, RF_IF), rd_rm),
8625 C3(tans, ea08100, 2, (RF, RF_IF), rd_rm),
8626 C3(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
8627 C3(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
8628 C3(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
8629 C3(tand, ea08180, 2, (RF, RF_IF), rd_rm),
8630 C3(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
8631 C3(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
8632 C3(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
8633 C3(tane, ea88100, 2, (RF, RF_IF), rd_rm),
8634 C3(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
8635 C3(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
8636 C3(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
8638 C3(asns, eb08100, 2, (RF, RF_IF), rd_rm),
8639 C3(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
8640 C3(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
8641 C3(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
8642 C3(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
8643 C3(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
8644 C3(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
8645 C3(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
8646 C3(asne, eb88100, 2, (RF, RF_IF), rd_rm),
8647 C3(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
8648 C3(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
8649 C3(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
8651 C3(acss, ec08100, 2, (RF, RF_IF), rd_rm),
8652 C3(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
8653 C3(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
8654 C3(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
8655 C3(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
8656 C3(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
8657 C3(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
8658 C3(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
8659 C3(acse, ec88100, 2, (RF, RF_IF), rd_rm),
8660 C3(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
8661 C3(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
8662 C3(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
8664 C3(atns, ed08100, 2, (RF, RF_IF), rd_rm),
8665 C3(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
8666 C3(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
8667 C3(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
8668 C3(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
8669 C3(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
8670 C3(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
8671 C3(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
8672 C3(atne, ed88100, 2, (RF, RF_IF), rd_rm),
8673 C3(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
8674 C3(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
8675 C3(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
8677 C3(urds, ee08100, 2, (RF, RF_IF), rd_rm),
8678 C3(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
8679 C3(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
8680 C3(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
8681 C3(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
8682 C3(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
8683 C3(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
8684 C3(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
8685 C3(urde, ee88100, 2, (RF, RF_IF), rd_rm),
8686 C3(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
8687 C3(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
8688 C3(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
8690 C3(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
8691 C3(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
8692 C3(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
8693 C3(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
8694 C3(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
8695 C3(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
8696 C3(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
8697 C3(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
8698 C3(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
8699 C3(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
8700 C3(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
8701 C3(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
8703 C3(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
8704 C3(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
8705 C3(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
8706 C3(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
8707 C3(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
8708 C3(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8709 C3(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8710 C3(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8711 C3(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
8712 C3(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
8713 C3(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
8714 C3(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
8716 C3(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
8717 C3(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
8718 C3(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
8719 C3(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
8720 C3(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
8721 C3(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8722 C3(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8723 C3(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8724 C3(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
8725 C3(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
8726 C3(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
8727 C3(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
8729 C3(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
8730 C3(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
8731 C3(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
8732 C3(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
8733 C3(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
8734 C3(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8735 C3(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8736 C3(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8737 C3(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
8738 C3(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
8739 C3(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
8740 C3(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
8742 C3(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
8743 C3(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
8744 C3(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
8745 C3(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
8746 C3(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
8747 C3(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8748 C3(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8749 C3(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8750 C3(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
8751 C3(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
8752 C3(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
8753 C3(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
8755 C3(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
8756 C3(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
8757 C3(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
8758 C3(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
8759 C3(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
8760 C3(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8761 C3(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8762 C3(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8763 C3(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
8764 C3(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
8765 C3(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
8766 C3(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
8768 C3(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
8769 C3(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
8770 C3(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
8771 C3(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
8772 C3(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
8773 C3(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8774 C3(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8775 C3(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8776 C3(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
8777 C3(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
8778 C3(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
8779 C3(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
8781 C3(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
8782 C3(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
8783 C3(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
8784 C3(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
8785 C3(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
8786 C3(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8787 C3(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8788 C3(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8789 C3(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
8790 C3(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
8791 C3(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
8792 C3(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
8794 C3(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
8795 C3(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
8796 C3(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
8797 C3(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
8798 C3(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
8799 C3(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8800 C3(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8801 C3(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8802 C3(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
8803 C3(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
8804 C3(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
8805 C3(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
8807 C3(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
8808 C3(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
8809 C3(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
8810 C3(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
8811 C3(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
8812 C3(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8813 C3(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8814 C3(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8815 C3(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
8816 C3(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
8817 C3(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
8818 C3(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
8820 C3(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
8821 C3(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
8822 C3(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
8823 C3(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
8824 C3(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
8825 C3(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8826 C3(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8827 C3(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8828 C3(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
8829 C3(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
8830 C3(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
8831 C3(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
8833 C3(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
8834 C3(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
8835 C3(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
8836 C3(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
8837 C3(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
8838 C3(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8839 C3(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8840 C3(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8841 C3(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
8842 C3(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
8843 C3(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
8844 C3(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8846 C3(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
8847 C3(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
8848 C3(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
8849 C3(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
8850 C3(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
8851 C3(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8852 C3(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8853 C3(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8854 C3(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
8855 C3(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
8856 C3(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
8857 C3(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8859 C3(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
8860 C3(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
8861 C3(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
8862 C3(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
8863 C3(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
8864 C3(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8865 C3(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8866 C3(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8867 C3(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
8868 C3(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
8869 C3(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
8870 C3(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8872 CE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
8873 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
8874 CE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
8875 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
8877 C3(flts, e000110, 2, (RF, RR), rn_rd),
8878 C3(fltsp, e000130, 2, (RF, RR), rn_rd),
8879 C3(fltsm, e000150, 2, (RF, RR), rn_rd),
8880 C3(fltsz, e000170, 2, (RF, RR), rn_rd),
8881 C3(fltd, e000190, 2, (RF, RR), rn_rd),
8882 C3(fltdp, e0001b0, 2, (RF, RR), rn_rd),
8883 C3(fltdm, e0001d0, 2, (RF, RR), rn_rd),
8884 C3(fltdz, e0001f0, 2, (RF, RR), rn_rd),
8885 C3(flte, e080110, 2, (RF, RR), rn_rd),
8886 C3(fltep, e080130, 2, (RF, RR), rn_rd),
8887 C3(fltem, e080150, 2, (RF, RR), rn_rd),
8888 C3(fltez, e080170, 2, (RF, RR), rn_rd),
8890 /* The implementation of the FIX instruction is broken on some
8891 assemblers, in that it accepts a precision specifier as well as a
8892 rounding specifier, despite the fact that this is meaningless.
8893 To be more compatible, we accept it as well, though of course it
8894 does not set any bits. */
8895 CE(fix, e100110, 2, (RR, RF), rd_rm),
8896 C3(fixp, e100130, 2, (RR, RF), rd_rm),
8897 C3(fixm, e100150, 2, (RR, RF), rd_rm),
8898 C3(fixz, e100170, 2, (RR, RF), rd_rm),
8899 C3(fixsp, e100130, 2, (RR, RF), rd_rm),
8900 C3(fixsm, e100150, 2, (RR, RF), rd_rm),
8901 C3(fixsz, e100170, 2, (RR, RF), rd_rm),
8902 C3(fixdp, e100130, 2, (RR, RF), rd_rm),
8903 C3(fixdm, e100150, 2, (RR, RF), rd_rm),
8904 C3(fixdz, e100170, 2, (RR, RF), rd_rm),
8905 C3(fixep, e100130, 2, (RR, RF), rd_rm),
8906 C3(fixem, e100150, 2, (RR, RF), rd_rm),
8907 C3(fixez, e100170, 2, (RR, RF), rd_rm),
8909 /* Instructions that were new with the real FPA, call them V2. */
8911 #define ARM_VARIANT FPU_FPA_EXT_V2
8912 CE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8913 C3(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8914 C3(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8915 CE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8916 C3(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8917 C3(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8920 #define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
8921 /* Moves and type conversions. */
8922 CE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
8923 CE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
8924 CE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
8925 CE(fmstat, ef1fa10, 0, (), noargs),
8926 CE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
8927 CE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
8928 CE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
8929 CE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
8930 CE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
8931 CE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
8932 CE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
8933 CE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
8935 /* Memory operations. */
8936 CE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
8937 CE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
8938 CE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
8939 CE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
8940 CE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
8941 CE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
8942 CE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
8943 CE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
8944 CE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
8945 CE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
8946 CE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
8947 CE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
8948 CE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
8949 CE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
8950 CE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
8951 CE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
8952 CE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
8953 CE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
8955 /* Monadic operations. */
8956 CE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
8957 CE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
8958 CE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
8960 /* Dyadic operations. */
8961 CE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8962 CE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8963 CE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8964 CE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8965 CE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8966 CE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8967 CE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8968 CE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8969 CE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8972 CE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
8973 CE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
8974 CE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
8975 CE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
8978 #define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
8979 /* Moves and type conversions. */
8980 CE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
8981 CE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
8982 CE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
8983 CE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
8984 CE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
8985 CE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
8986 CE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
8987 CE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
8988 CE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
8989 CE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
8990 CE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
8991 CE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
8992 CE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
8994 /* Memory operations. */
8995 CE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
8996 CE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
8997 CE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
8998 CE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
8999 CE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9000 CE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9001 CE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9002 CE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9003 CE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9004 CE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9006 /* Monadic operations. */
9007 CE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
9008 CE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
9009 CE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
9011 /* Dyadic operations. */
9012 CE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9013 CE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9014 CE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9015 CE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9016 CE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9017 CE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9018 CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9019 CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9020 CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9023 CE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
9024 CE(fcmpzd, eb50b40, 1, (RVD), rd),
9025 CE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
9026 CE(fcmpezd, eb50bc0, 1, (RVD), rd),
9029 #define ARM_VARIANT FPU_VFP_EXT_V2
9030 CE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
9031 CE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
9032 CE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
9033 CE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
9036 #define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
9037 CE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9038 CE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9039 CE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9040 CE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9041 CE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9042 CE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9043 CE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
9044 CE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
9047 #define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
9048 CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
9049 CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
9050 CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
9051 CE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
9052 CE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
9053 CE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
9054 CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
9055 CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
9056 CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
9057 CE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9058 CE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9059 CE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9060 CE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9061 CE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9062 CE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9063 CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9064 CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9065 CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9066 CE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
9067 CE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
9068 CE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9069 CE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9070 CE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9071 CE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9072 CE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9073 CE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9074 CE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
9075 CE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
9076 CE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
9077 CE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
9078 CE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
9079 CE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
9080 CE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
9081 CE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
9082 CE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
9083 CE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
9084 CE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
9085 CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9086 CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9087 CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9088 CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9089 CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9090 CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9091 CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9092 CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9093 CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9094 CE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
9095 CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9096 CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9097 CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9098 CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9099 CE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9100 CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9101 CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9102 CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9103 CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9104 CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9105 CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9106 CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9107 CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9108 CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9109 CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9110 CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9111 CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9112 CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9113 CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9114 CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9115 CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9116 CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9117 CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9118 CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9119 CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9120 CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9121 CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9122 CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9123 CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9124 CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9125 CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9126 CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9127 CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9128 CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9129 CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9130 CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9131 CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9132 CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9133 CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9134 CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9135 CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9136 CE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
9137 CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9138 CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9139 CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9140 CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9141 CE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9142 CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9143 CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9144 CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9145 CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9146 CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9147 CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9148 CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9149 CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9150 CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9151 CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9152 CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9153 CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9154 CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9155 CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9156 CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9157 CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9158 CE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
9159 CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9160 CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9161 CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9162 CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9163 CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9164 CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9165 CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9166 CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9167 CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9168 CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9169 CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9170 CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9171 CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9172 CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9173 CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9174 CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9175 CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9176 CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9177 CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9178 CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9179 CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9180 CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9181 CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9182 CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9183 CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9184 CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9185 CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9186 CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9187 CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9188 CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9189 CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9190 CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
9191 CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
9192 CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
9193 CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
9194 CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
9195 CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
9196 CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9197 CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9198 CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9199 CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
9200 CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
9201 CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
9202 CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
9203 CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
9204 CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
9205 CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9206 CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9207 CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9208 CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9209 CE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
9212 #define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
9213 CE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
9214 CE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
9215 CE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
9216 CE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
9217 CE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
9218 CE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
9219 CE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
9220 CE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
9221 CE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
9222 CE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
9223 CE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
9224 CE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
9225 CE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
9226 CE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
9227 CE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
9228 CE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
9229 CE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
9230 CE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
9231 CE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
9232 CE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
9233 CE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
9234 CE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
9235 CE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
9236 CE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
9237 CE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
9238 CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
9239 CE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
9240 CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
9241 CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
9242 CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
9243 CE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
9244 CE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
9245 CE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
9246 CE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
9247 CE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
9248 CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
9249 CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
9250 CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
9251 CE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
9252 CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
9253 CE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
9254 CE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
9255 CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
9256 CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
9257 CE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
9258 CE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
9259 CE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
9260 CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
9261 CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
9262 CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
9263 CE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
9264 CE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
9265 CE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
9266 CE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
9267 CE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
9268 CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
9269 CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
9270 CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
9271 CE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
9272 CE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
9273 CE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
9274 CE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
9275 CE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
9276 CE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
9277 CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9278 CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9279 CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9280 CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9281 CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9282 CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9283 CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9284 CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9285 CE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9286 CE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9287 CE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9288 CE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9291 #undef THUMB_VARIANT
9311 /* MD interface: bits in the object file. */
9313 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9314 for use in the a.out file, and stores them in the array pointed to by buf.
9315 This knows about the endian-ness of the target machine and does
9316 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9317 2 (short) and 4 (long) Floating numbers are put out as a series of
9318 LITTLENUMS (shorts, here at least). */
9321 md_number_to_chars (char * buf, valueT val, int n)
9323 if (target_big_endian)
9324 number_to_chars_bigendian (buf, val, n);
9326 number_to_chars_littleendian (buf, val, n);
9330 md_chars_to_number (char * buf, int n)
9333 unsigned char * where = (unsigned char *) buf;
9335 if (target_big_endian)
9340 result |= (*where++ & 255);
9348 result |= (where[n] & 255);
9355 /* MD interface: Sections. */
9358 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
9359 segT segtype ATTRIBUTE_UNUSED)
9361 as_fatal (_("md_estimate_size_before_relax\n"));
9365 /* Round up a section size to the appropriate boundary. */
9368 md_section_align (segT segment ATTRIBUTE_UNUSED,
9374 /* Round all sects to multiple of 4. */
9375 return (size + 3) & ~3;
9379 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
9380 of an rs_align_code fragment. */
9383 arm_handle_align (fragS * fragP)
9385 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
9386 static char const thumb_noop[2] = { 0xc0, 0x46 };
9387 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
9388 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
9390 int bytes, fix, noop_size;
9394 if (fragP->fr_type != rs_align_code)
9397 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
9398 p = fragP->fr_literal + fragP->fr_fix;
9401 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
9402 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
9404 if (fragP->tc_frag_data)
9406 if (target_big_endian)
9407 noop = thumb_bigend_noop;
9410 noop_size = sizeof (thumb_noop);
9414 if (target_big_endian)
9415 noop = arm_bigend_noop;
9418 noop_size = sizeof (arm_noop);
9421 if (bytes & (noop_size - 1))
9423 fix = bytes & (noop_size - 1);
9429 while (bytes >= noop_size)
9431 memcpy (p, noop, noop_size);
9437 fragP->fr_fix += fix;
9438 fragP->fr_var = noop_size;
9441 /* Called from md_do_align. Used to create an alignment
9442 frag in a code section. */
9445 arm_frag_align_code (int n, int max)
9449 /* We assume that there will never be a requirement
9450 to support alignments greater than 32 bytes. */
9451 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
9452 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
9454 p = frag_var (rs_align_code,
9455 MAX_MEM_FOR_RS_ALIGN_CODE,
9457 (relax_substateT) max,
9464 /* Perform target specific initialisation of a frag. */
9467 arm_init_frag (fragS * fragP)
9469 /* Record whether this frag is in an ARM or a THUMB area. */
9470 fragP->tc_frag_data = thumb_mode;
9474 /* When we change sections we need to issue a new mapping symbol. */
9477 arm_elf_change_section (void)
9480 segment_info_type *seginfo;
9482 /* Link an unlinked unwind index table section to the .text section. */
9483 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
9484 && elf_linked_to_section (now_seg) == NULL)
9485 elf_linked_to_section (now_seg) = text_section;
9487 if (!SEG_NORMAL (now_seg))
9490 flags = bfd_get_section_flags (stdoutput, now_seg);
9492 /* We can ignore sections that only contain debug info. */
9493 if ((flags & SEC_ALLOC) == 0)
9496 seginfo = seg_info (now_seg);
9497 mapstate = seginfo->tc_segment_info_data.mapstate;
9498 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
9502 arm_elf_section_type (const char * str, size_t len)
9504 if (len == 5 && strncmp (str, "exidx", 5) == 0)
9505 return SHT_ARM_EXIDX;
9510 /* Code to deal with unwinding tables. */
9512 static void add_unwind_adjustsp (offsetT);
9514 /* Cenerate and deferred unwind frame offset. */
9517 flush_pending_unwind (void)
9521 offset = unwind.pending_offset;
9522 unwind.pending_offset = 0;
9524 add_unwind_adjustsp (offset);
9527 /* Add an opcode to this list for this function. Two-byte opcodes should
9528 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
9532 add_unwind_opcode (valueT op, int length)
9534 /* Add any deferred stack adjustment. */
9535 if (unwind.pending_offset)
9536 flush_pending_unwind ();
9538 unwind.sp_restored = 0;
9540 if (unwind.opcode_count + length > unwind.opcode_alloc)
9542 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
9544 unwind.opcodes = xrealloc (unwind.opcodes,
9545 unwind.opcode_alloc);
9547 unwind.opcodes = xmalloc (unwind.opcode_alloc);
9552 unwind.opcodes[unwind.opcode_count] = op & 0xff;
9554 unwind.opcode_count++;
9558 /* Add unwind opcodes to adjust the stack pointer. */
9561 add_unwind_adjustsp (offsetT offset)
9567 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
9572 /* Long form: 0xb2, uleb128. */
9573 /* This might not fit in a word so add the individual bytes,
9574 remembering the list is built in reverse order. */
9575 o = (valueT) ((offset - 0x204) >> 2);
9577 add_unwind_opcode (0, 1);
9579 /* Calculate the uleb128 encoding of the offset. */
9583 bytes[n] = o & 0x7f;
9591 add_unwind_opcode (bytes[n - 1], 1);
9592 add_unwind_opcode (0xb2, 1);
9594 else if (offset > 0x100)
9596 /* Two short opcodes. */
9597 add_unwind_opcode (0x3f, 1);
9598 op = (offset - 0x104) >> 2;
9599 add_unwind_opcode (op, 1);
9601 else if (offset > 0)
9604 op = (offset - 4) >> 2;
9605 add_unwind_opcode (op, 1);
9607 else if (offset < 0)
9610 while (offset > 0x100)
9612 add_unwind_opcode (0x7f, 1);
9615 op = ((offset - 4) >> 2) | 0x40;
9616 add_unwind_opcode (op, 1);
9620 /* Finish the list of unwind opcodes for this function. */
9622 finish_unwind_opcodes (void)
9628 /* Adjust sp as neccessary. */
9629 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
9630 flush_pending_unwind ();
9632 /* After restoring sp from the frame pointer. */
9633 op = 0x90 | unwind.fp_reg;
9634 add_unwind_opcode (op, 1);
9637 flush_pending_unwind ();
9641 /* Start an exception table entry. If idx is nonzero this is an index table
9645 start_unwind_section (const segT text_seg, int idx)
9647 const char * text_name;
9648 const char * prefix;
9649 const char * prefix_once;
9650 const char * group_name;
9654 size_t sec_name_len;
9661 prefix = ELF_STRING_ARM_unwind;
9662 prefix_once = ELF_STRING_ARM_unwind_once;
9663 type = SHT_ARM_EXIDX;
9667 prefix = ELF_STRING_ARM_unwind_info;
9668 prefix_once = ELF_STRING_ARM_unwind_info_once;
9669 type = SHT_PROGBITS;
9672 text_name = segment_name (text_seg);
9673 if (streq (text_name, ".text"))
9676 if (strncmp (text_name, ".gnu.linkonce.t.",
9677 strlen (".gnu.linkonce.t.")) == 0)
9679 prefix = prefix_once;
9680 text_name += strlen (".gnu.linkonce.t.");
9683 prefix_len = strlen (prefix);
9684 text_len = strlen (text_name);
9685 sec_name_len = prefix_len + text_len;
9686 sec_name = xmalloc (sec_name_len + 1);
9687 memcpy (sec_name, prefix, prefix_len);
9688 memcpy (sec_name + prefix_len, text_name, text_len);
9689 sec_name[prefix_len + text_len] = '\0';
9695 /* Handle COMDAT group. */
9696 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
9698 group_name = elf_group_name (text_seg);
9699 if (group_name == NULL)
9701 as_bad ("Group section `%s' has no group signature",
9702 segment_name (text_seg));
9703 ignore_rest_of_line ();
9710 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
9712 /* Set the setion link for index tables. */
9714 elf_linked_to_section (now_seg) = text_seg;
9718 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
9719 personality routine data. Returns zero, or the index table value for
9720 and inline entry. */
9723 create_unwind_entry (int have_data)
9728 /* The current word of data. */
9730 /* The number of bytes left in this word. */
9733 finish_unwind_opcodes ();
9735 /* Remember the current text section. */
9736 unwind.saved_seg = now_seg;
9737 unwind.saved_subseg = now_subseg;
9739 start_unwind_section (now_seg, 0);
9741 if (unwind.personality_routine == NULL)
9743 if (unwind.personality_index == -2)
9746 as_bad (_("handerdata in cantunwind frame"));
9747 return 1; /* EXIDX_CANTUNWIND. */
9750 /* Use a default personality routine if none is specified. */
9751 if (unwind.personality_index == -1)
9753 if (unwind.opcode_count > 3)
9754 unwind.personality_index = 1;
9756 unwind.personality_index = 0;
9759 /* Space for the personality routine entry. */
9760 if (unwind.personality_index == 0)
9762 if (unwind.opcode_count > 3)
9763 as_bad (_("too many unwind opcodes for personality routine 0"));
9767 /* All the data is inline in the index table. */
9770 while (unwind.opcode_count > 0)
9772 unwind.opcode_count--;
9773 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
9777 /* Pad with "finish" opcodes. */
9779 data = (data << 8) | 0xb0;
9786 /* We get two opcodes "free" in the first word. */
9787 size = unwind.opcode_count - 2;
9790 /* An extra byte is required for the opcode count. */
9791 size = unwind.opcode_count + 1;
9793 size = (size + 3) >> 2;
9795 as_bad (_("too many unwind opcodes"));
9797 frag_align (2, 0, 0);
9798 record_alignment (now_seg, 2);
9799 unwind.table_entry = expr_build_dot ();
9801 /* Allocate the table entry. */
9802 ptr = frag_more ((size << 2) + 4);
9803 where = frag_now_fix () - ((size << 2) + 4);
9805 switch (unwind.personality_index)
9808 /* ??? Should this be a PLT generating relocation? */
9809 /* Custom personality routine. */
9810 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
9811 BFD_RELOC_ARM_PREL31);
9816 /* Set the first byte to the number of additional words. */
9821 /* ABI defined personality routines. */
9823 /* Three opcodes bytes are packed into the first word. */
9830 /* The size and first two opcode bytes go in the first word. */
9831 data = ((0x80 + unwind.personality_index) << 8) | size;
9836 /* Should never happen. */
9840 /* Pack the opcodes into words (MSB first), reversing the list at the same
9842 while (unwind.opcode_count > 0)
9846 md_number_to_chars (ptr, data, 4);
9851 unwind.opcode_count--;
9853 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
9856 /* Finish off the last word. */
9859 /* Pad with "finish" opcodes. */
9861 data = (data << 8) | 0xb0;
9863 md_number_to_chars (ptr, data, 4);
9868 /* Add an empty descriptor if there is no user-specified data. */
9869 ptr = frag_more (4);
9870 md_number_to_chars (ptr, 0, 4);
9876 /* Convert REGNAME to a DWARF-2 register number. */
9879 tc_arm_regname_to_dw2regnum (const char *regname)
9881 int reg = arm_reg_parse ((char **) ®name, REG_TYPE_RN);
9889 /* Initialize the DWARF-2 unwind information for this procedure. */
9892 tc_arm_frame_initial_instructions (void)
9894 cfi_add_CFA_def_cfa (REG_SP, 0);
9896 #endif /* OBJ_ELF */
9899 /* MD interface: Symbol and relocation handling. */
9901 /* The knowledge of the PC's pipeline offset is built into the insns
9905 md_pcrel_from (fixS * fixP)
9908 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
9909 && fixP->fx_subsy == NULL)
9912 /* PC relative addressing on the Thumb is slightly odd as the bottom
9913 two bits of the PC are forced to zero for the calculation. This
9914 happens *after* application of the pipeline offset. However,
9915 Thumb adrl already adjusts for this, so we need not do it again. */
9916 switch (fixP->fx_r_type)
9918 case BFD_RELOC_ARM_THUMB_ADD:
9919 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
9921 case BFD_RELOC_ARM_THUMB_OFFSET:
9922 case BFD_RELOC_ARM_T32_OFFSET_IMM:
9923 return (fixP->fx_where + fixP->fx_frag->fr_address + 4) & ~3;
9930 /* The pattern was adjusted to accommodate CE's off-by-one fixups,
9931 so we un-adjust here to compensate for the accommodation. */
9932 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
9934 return fixP->fx_where + fixP->fx_frag->fr_address;
9938 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
9939 Otherwise we have no need to default values of symbols. */
9942 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
9945 if (name[0] == '_' && name[1] == 'G'
9946 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
9950 if (symbol_find (name))
9951 as_bad ("GOT already in the symbol table");
9953 GOT_symbol = symbol_new (name, undefined_section,
9954 (valueT) 0, & zero_address_frag);
9964 /* Subroutine of md_apply_fix. Check to see if an immediate can be
9965 computed as two separate immediate values, added together. We
9966 already know that this value cannot be computed by just one ARM
9970 validate_immediate_twopart (unsigned int val,
9971 unsigned int * highpart)
9976 for (i = 0; i < 32; i += 2)
9977 if (((a = rotate_left (val, i)) & 0xff) != 0)
9983 * highpart = (a >> 8) | ((i + 24) << 7);
9985 else if (a & 0xff0000)
9989 * highpart = (a >> 16) | ((i + 16) << 7);
9993 assert (a & 0xff000000);
9994 * highpart = (a >> 24) | ((i + 8) << 7);
9997 return (a & 0xff) | (i << 7);
10004 validate_offset_imm (unsigned int val, int hwse)
10006 if ((hwse && val > 255) || val > 4095)
10011 /* Subroutine of md_apply_fix. Do those data_ops which can take a
10012 negative immediate constant by altering the instruction. A bit of
10017 by inverting the second operand, and
10020 by negating the second operand. */
10023 negate_data_op (unsigned long * instruction,
10024 unsigned long value)
10027 unsigned long negated, inverted;
10029 negated = encode_arm_immediate (-value);
10030 inverted = encode_arm_immediate (~value);
10032 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
10035 /* First negates. */
10036 case OPCODE_SUB: /* ADD <-> SUB */
10037 new_inst = OPCODE_ADD;
10042 new_inst = OPCODE_SUB;
10046 case OPCODE_CMP: /* CMP <-> CMN */
10047 new_inst = OPCODE_CMN;
10052 new_inst = OPCODE_CMP;
10056 /* Now Inverted ops. */
10057 case OPCODE_MOV: /* MOV <-> MVN */
10058 new_inst = OPCODE_MVN;
10063 new_inst = OPCODE_MOV;
10067 case OPCODE_AND: /* AND <-> BIC */
10068 new_inst = OPCODE_BIC;
10073 new_inst = OPCODE_AND;
10077 case OPCODE_ADC: /* ADC <-> SBC */
10078 new_inst = OPCODE_SBC;
10083 new_inst = OPCODE_ADC;
10087 /* We cannot do anything. */
10092 if (value == (unsigned) FAIL)
10095 *instruction &= OPCODE_MASK;
10096 *instruction |= new_inst << DATA_OP_SHIFT;
10101 md_apply_fix (fixS * fixP,
10105 offsetT value = * valP;
10107 unsigned int newimm;
10108 unsigned long temp;
10110 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
10112 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
10114 /* Note whether this will delete the relocation. */
10115 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
10118 /* If this symbol is in a different section then we need to leave it for
10119 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
10120 so we have to undo its effects here. */
10121 if (fixP->fx_pcrel)
10123 if (fixP->fx_addsy != NULL
10124 && S_IS_DEFINED (fixP->fx_addsy)
10125 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
10126 value += md_pcrel_from (fixP);
10129 /* On a 64-bit host, silently truncate 'value' to 32 bits for
10130 consistency with the behavior on 32-bit hosts. Remember value
10132 value &= 0xffffffff;
10133 value ^= 0x80000000;
10134 value -= 0x80000000;
10137 fixP->fx_addnumber = value;
10139 /* Same treatment for fixP->fx_offset. */
10140 fixP->fx_offset &= 0xffffffff;
10141 fixP->fx_offset ^= 0x80000000;
10142 fixP->fx_offset -= 0x80000000;
10144 switch (fixP->fx_r_type)
10146 case BFD_RELOC_NONE:
10147 /* This will need to go in the object file. */
10151 case BFD_RELOC_ARM_IMMEDIATE:
10152 /* We claim that this fixup has been processed here,
10153 even if in fact we generate an error because we do
10154 not have a reloc for it, so tc_gen_reloc will reject it. */
10158 && ! S_IS_DEFINED (fixP->fx_addsy))
10160 as_bad_where (fixP->fx_file, fixP->fx_line,
10161 _("undefined symbol %s used as an immediate value"),
10162 S_GET_NAME (fixP->fx_addsy));
10166 newimm = encode_arm_immediate (value);
10167 temp = md_chars_to_number (buf, INSN_SIZE);
10169 /* If the instruction will fail, see if we can fix things up by
10170 changing the opcode. */
10171 if (newimm == (unsigned int) FAIL
10172 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
10174 as_bad_where (fixP->fx_file, fixP->fx_line,
10175 _("invalid constant (%lx) after fixup"),
10176 (unsigned long) value);
10180 newimm |= (temp & 0xfffff000);
10181 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
10184 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
10186 unsigned int highpart = 0;
10187 unsigned int newinsn = 0xe1a00000; /* nop. */
10189 newimm = encode_arm_immediate (value);
10190 temp = md_chars_to_number (buf, INSN_SIZE);
10192 /* If the instruction will fail, see if we can fix things up by
10193 changing the opcode. */
10194 if (newimm == (unsigned int) FAIL
10195 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
10197 /* No ? OK - try using two ADD instructions to generate
10199 newimm = validate_immediate_twopart (value, & highpart);
10201 /* Yes - then make sure that the second instruction is
10203 if (newimm != (unsigned int) FAIL)
10205 /* Still No ? Try using a negated value. */
10206 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
10207 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
10208 /* Otherwise - give up. */
10211 as_bad_where (fixP->fx_file, fixP->fx_line,
10212 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
10217 /* Replace the first operand in the 2nd instruction (which
10218 is the PC) with the destination register. We have
10219 already added in the PC in the first instruction and we
10220 do not want to do it again. */
10221 newinsn &= ~ 0xf0000;
10222 newinsn |= ((newinsn & 0x0f000) << 4);
10225 newimm |= (temp & 0xfffff000);
10226 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
10228 highpart |= (newinsn & 0xfffff000);
10229 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
10233 case BFD_RELOC_ARM_OFFSET_IMM:
10234 case BFD_RELOC_ARM_LITERAL:
10240 if (validate_offset_imm (value, 0) == FAIL)
10242 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
10243 as_bad_where (fixP->fx_file, fixP->fx_line,
10244 _("invalid literal constant: pool needs to be closer"));
10246 as_bad_where (fixP->fx_file, fixP->fx_line,
10247 _("bad immediate value for offset (%ld)"),
10252 newval = md_chars_to_number (buf, INSN_SIZE);
10253 newval &= 0xff7ff000;
10254 newval |= value | (sign ? INDEX_UP : 0);
10255 md_number_to_chars (buf, newval, INSN_SIZE);
10258 case BFD_RELOC_ARM_OFFSET_IMM8:
10259 case BFD_RELOC_ARM_HWLITERAL:
10265 if (validate_offset_imm (value, 1) == FAIL)
10267 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
10268 as_bad_where (fixP->fx_file, fixP->fx_line,
10269 _("invalid literal constant: pool needs to be closer"));
10271 as_bad (_("bad immediate value for half-word offset (%ld)"),
10276 newval = md_chars_to_number (buf, INSN_SIZE);
10277 newval &= 0xff7ff0f0;
10278 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
10279 md_number_to_chars (buf, newval, INSN_SIZE);
10282 case BFD_RELOC_ARM_T32_OFFSET_U8:
10283 if (value < 0 || value > 1020 || value % 4 != 0)
10284 as_bad_where (fixP->fx_file, fixP->fx_line,
10285 _("bad immediate value for offset (%ld)"), (long) value);
10288 newval = md_chars_to_number (buf+2, THUMB_SIZE);
10291 md_number_to_chars (buf+2, newval, THUMB_SIZE);
10294 case BFD_RELOC_ARM_T32_OFFSET_IMM:
10295 /* This is a complicated relocation used for all varieties of Thumb32
10296 load/store instruction with immediate offset:
10298 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
10299 *4, optional writeback(W)
10300 (doubleword load/store)
10302 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
10303 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
10304 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
10305 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
10306 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
10308 Uppercase letters indicate bits that are already encoded at
10309 this point. Lowercase letters are our problem. For the
10310 second block of instructions, the secondary opcode nybble
10311 (bits 8..11) is present, and bit 23 is zero, even if this is
10312 a PC-relative operation. */
10313 newval = md_chars_to_number (buf, THUMB_SIZE);
10315 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
10317 if ((newval & 0xf0000000) == 0xe0000000)
10319 /* Doubleword load/store: 8-bit offset, scaled by 4. */
10321 newval |= (1 << 23);
10324 if (value % 4 != 0)
10326 as_bad_where (fixP->fx_file, fixP->fx_line,
10327 _("offset not a multiple of 4"));
10333 as_bad_where (fixP->fx_file, fixP->fx_line,
10334 _("offset out of range"));
10339 else if ((newval & 0x000f0000) == 0x000f0000)
10341 /* PC-relative, 12-bit offset. */
10343 newval |= (1 << 23);
10346 if (value >= 0xfff)
10348 as_bad_where (fixP->fx_file, fixP->fx_line,
10349 _("offset out of range"));
10354 else if ((newval & 0x00000100) == 0x00000100)
10356 /* Writeback: 8-bit, +/- offset. */
10358 newval |= (1 << 9);
10363 as_bad_where (fixP->fx_file, fixP->fx_line,
10364 _("offset out of range"));
10369 else if ((newval & 0x00000f00) == 0x00000e00)
10371 /* T-instruction: positive 8-bit offset. */
10372 if (value < 0 || value >= 0xff)
10374 as_bad_where (fixP->fx_file, fixP->fx_line,
10375 _("offset out of range"));
10383 /* Positive 12-bit or negative 8-bit offset. */
10387 newval |= (1 << 23);
10397 as_bad_where (fixP->fx_file, fixP->fx_line,
10398 _("offset out of range"));
10405 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
10406 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
10409 case BFD_RELOC_ARM_SHIFT_IMM:
10410 newval = md_chars_to_number (buf, INSN_SIZE);
10411 if (((unsigned long) value) > 32
10413 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
10415 as_bad_where (fixP->fx_file, fixP->fx_line,
10416 _("shift expression is too large"));
10421 /* Shifts of zero must be done as lsl. */
10423 else if (value == 32)
10425 newval &= 0xfffff07f;
10426 newval |= (value & 0x1f) << 7;
10427 md_number_to_chars (buf, newval, INSN_SIZE);
10430 case BFD_RELOC_ARM_T32_IMMEDIATE:
10431 /* We claim that this fixup has been processed here,
10432 even if in fact we generate an error because we do
10433 not have a reloc for it, so tc_gen_reloc will reject it. */
10437 && ! S_IS_DEFINED (fixP->fx_addsy))
10439 as_bad_where (fixP->fx_file, fixP->fx_line,
10440 _("undefined symbol %s used as an immediate value"),
10441 S_GET_NAME (fixP->fx_addsy));
10445 newval = md_chars_to_number (buf, THUMB_SIZE);
10447 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
10449 newimm = encode_thumb32_immediate (value);
10451 /* FUTURE: Implement analogue of negate_data_op for T32. */
10452 if (newimm == (unsigned int)FAIL)
10454 as_bad_where (fixP->fx_file, fixP->fx_line,
10455 _("invalid constant (%lx) after fixup"),
10456 (unsigned long) value);
10460 newval &= 0xfbff8f00;
10461 newval |= (newimm & 0x800) << 15;
10462 newval |= (newimm & 0x700) << 4;
10463 newval |= (newimm & 0x0ff);
10465 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
10466 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
10469 case BFD_RELOC_ARM_SMI:
10470 if (((unsigned long) value) > 0xffff)
10471 as_bad_where (fixP->fx_file, fixP->fx_line,
10472 _("invalid smi expression"));
10473 newval = md_chars_to_number (buf, INSN_SIZE) & 0xfff000f0;
10474 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
10475 md_number_to_chars (buf, newval, INSN_SIZE);
10478 case BFD_RELOC_ARM_SWI:
10479 if (fixP->tc_fix_data != 0)
10481 if (((unsigned long) value) > 0xff)
10482 as_bad_where (fixP->fx_file, fixP->fx_line,
10483 _("invalid swi expression"));
10484 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
10486 md_number_to_chars (buf, newval, THUMB_SIZE);
10490 if (((unsigned long) value) > 0x00ffffff)
10491 as_bad_where (fixP->fx_file, fixP->fx_line,
10492 _("invalid swi expression"));
10493 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
10495 md_number_to_chars (buf, newval, INSN_SIZE);
10499 case BFD_RELOC_ARM_MULTI:
10500 if (((unsigned long) value) > 0xffff)
10501 as_bad_where (fixP->fx_file, fixP->fx_line,
10502 _("invalid expression in load/store multiple"));
10503 newval = value | md_chars_to_number (buf, INSN_SIZE);
10504 md_number_to_chars (buf, newval, INSN_SIZE);
10507 case BFD_RELOC_ARM_PCREL_BRANCH:
10508 newval = md_chars_to_number (buf, INSN_SIZE);
10510 /* Sign-extend a 24-bit number. */
10511 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
10514 if (!fixP->fx_done)
10515 value = fixP->fx_offset;
10518 /* We are going to store value (shifted right by two) in the
10519 instruction, in a 24 bit, signed field Thus we need to check
10520 that none of the top 8 bits of the shifted value (top 7 bits of
10521 the unshifted, unsigned value) are set, or that they are all set. */
10522 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
10523 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
10526 /* Normally we would be stuck at this point, since we cannot store
10527 the absolute address that is the destination of the branch in the
10528 24 bits of the branch instruction. If however, we happen to know
10529 that the destination of the branch is in the same section as the
10530 branch instruction itself, then we can compute the relocation for
10531 ourselves and not have to bother the linker with it.
10533 FIXME: The test for OBJ_ELF is only here because I have not
10534 worked out how to do this for OBJ_COFF. */
10535 if (fixP->fx_addsy != NULL
10536 && S_IS_DEFINED (fixP->fx_addsy)
10537 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
10539 /* Get pc relative value to go into the branch. */
10542 /* Permit a backward branch provided that enough bits
10543 are set. Allow a forwards branch, provided that
10544 enough bits are clear. */
10545 if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
10546 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
10550 if (! fixP->fx_done)
10552 as_bad_where (fixP->fx_file, fixP->fx_line,
10553 _("GAS can't handle same-section branch dest >= 0x04000000"));
10557 value += SEXT24 (newval);
10559 if ( (value & ~ ((offsetT) 0xffffff)) != 0
10560 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
10561 as_bad_where (fixP->fx_file, fixP->fx_line,
10562 _("out of range branch"));
10564 if (seg->use_rela_p && !fixP->fx_done)
10566 /* Must unshift the value before storing it in the addend. */
10569 fixP->fx_offset = value;
10571 fixP->fx_addnumber = value;
10572 newval = newval & 0xff000000;
10575 newval = (value & 0x00ffffff) | (newval & 0xff000000);
10576 md_number_to_chars (buf, newval, INSN_SIZE);
10579 case BFD_RELOC_ARM_PCREL_BLX:
10582 newval = md_chars_to_number (buf, INSN_SIZE);
10585 if (!fixP->fx_done)
10586 value = fixP->fx_offset;
10588 hbit = (value >> 1) & 1;
10589 value = (value >> 2) & 0x00ffffff;
10590 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
10592 if (seg->use_rela_p && !fixP->fx_done)
10594 /* Must sign-extend and unshift the value before storing
10595 it in the addend. */
10596 value = SEXT24 (value);
10597 value = (value << 2) | hbit;
10599 fixP->fx_offset = value;
10601 fixP->fx_addnumber = value;
10602 newval = newval & 0xfe000000;
10605 newval = value | (newval & 0xfe000000) | (hbit << 24);
10606 md_number_to_chars (buf, newval, INSN_SIZE);
10610 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
10611 newval = md_chars_to_number (buf, THUMB_SIZE);
10613 addressT diff = ((newval & 0x00f8) >> 2) | (newval & 0x0200) >> 3;
10614 /* This one does not have the offset encoded in the pattern. */
10615 value = value + diff - 4;
10616 /* CZB can only branch forward. */
10618 as_bad_where (fixP->fx_file, fixP->fx_line,
10619 _("branch out of range"));
10622 if (seg->use_rela_p && !fixP->fx_done)
10625 fixP->fx_offset = value;
10627 fixP->fx_addnumber = value;
10630 newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3);
10632 md_number_to_chars (buf, newval, THUMB_SIZE);
10635 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
10636 newval = md_chars_to_number (buf, THUMB_SIZE);
10638 addressT diff = (newval & 0xff) << 1;
10643 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
10644 as_bad_where (fixP->fx_file, fixP->fx_line,
10645 _("branch out of range"));
10646 if (seg->use_rela_p && !fixP->fx_done)
10649 fixP->fx_offset = value;
10651 fixP->fx_addnumber = value;
10652 newval = newval & 0xff00;
10655 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
10657 md_number_to_chars (buf, newval, THUMB_SIZE);
10660 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
10661 newval = md_chars_to_number (buf, THUMB_SIZE);
10663 addressT diff = (newval & 0x7ff) << 1;
10668 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
10669 as_bad_where (fixP->fx_file, fixP->fx_line,
10670 _("branch out of range"));
10671 if (seg->use_rela_p && !fixP->fx_done)
10674 fixP->fx_offset = value;
10676 fixP->fx_addnumber = value;
10677 newval = newval & 0xf800;
10680 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
10682 md_number_to_chars (buf, newval, THUMB_SIZE);
10685 case BFD_RELOC_THUMB_PCREL_BRANCH20:
10688 addressT diff, S, J1, J2, lo, hi;
10690 newval = md_chars_to_number (buf, THUMB_SIZE);
10691 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10693 S = !(newval & 0x0400); /* flipped - 0=negative */
10694 hi = (newval & 0x003f);
10695 J1 = (newval2 & 0x2000) >> 13;
10696 J2 = (newval2 & 0x0800) >> 11;
10697 lo = (newval2 & 0x07ff);
10699 diff = ((S << 20) | (J2 << 19) | (J1 << 18) | (hi << 12) | (lo << 1));
10700 diff -= (1 << 20); /* sign extend */
10703 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
10704 as_bad_where (fixP->fx_file, fixP->fx_line,
10705 _("conditional branch out of range"));
10707 newval = newval & 0xfbc0;
10708 newval2 = newval2 & 0xd000;
10709 if (seg->use_rela_p && !fixP->fx_done)
10712 fixP->fx_offset = value;
10714 fixP->fx_addnumber = value;
10718 S = (value & 0x00100000) >> 20;
10719 J2 = (value & 0x00080000) >> 19;
10720 J1 = (value & 0x00040000) >> 18;
10721 hi = (value & 0x0003f000) >> 12;
10722 lo = (value & 0x00000ffe) >> 1;
10724 newval = newval | (S << 10) | hi;
10725 newval2 = newval2 | (J1 << 13) | (J2 << 11) | lo;
10728 md_number_to_chars (buf, newval, THUMB_SIZE);
10729 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10733 case BFD_RELOC_THUMB_PCREL_BLX:
10734 case BFD_RELOC_THUMB_PCREL_BRANCH23:
10739 newval = md_chars_to_number (buf, THUMB_SIZE);
10740 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10741 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
10742 if (diff & 0x400000)
10745 if (!fixP->fx_done)
10746 value = fixP->fx_offset;
10750 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
10751 as_bad_where (fixP->fx_file, fixP->fx_line,
10752 _("branch with link out of range"));
10754 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
10755 /* For a BLX instruction, make sure that the relocation is rounded up
10756 to a word boundary. This follows the semantics of the instruction
10757 which specifies that bit 1 of the target address will come from bit
10758 1 of the base address. */
10759 value = (value + 1) & ~ 1;
10761 if (seg->use_rela_p && !fixP->fx_done)
10764 fixP->fx_offset = value;
10766 fixP->fx_addnumber = value;
10767 newval = newval & 0xf800;
10768 newval2 = newval2 & 0xf800;
10772 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
10773 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
10775 md_number_to_chars (buf, newval, THUMB_SIZE);
10776 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10781 if (seg->use_rela_p && !fixP->fx_done)
10783 if (fixP->fx_done || fixP->fx_pcrel)
10784 md_number_to_chars (buf, value, 1);
10788 value = fixP->fx_offset;
10789 md_number_to_chars (buf, value, 1);
10794 case BFD_RELOC_THUMB_PCREL_BRANCH25:
10797 addressT diff, S, I1, I2, lo, hi;
10799 newval = md_chars_to_number (buf, THUMB_SIZE);
10800 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10802 S = (newval & 0x0400) >> 10;
10803 hi = (newval & 0x03ff);
10804 I1 = (newval2 & 0x2000) >> 13;
10805 I2 = (newval2 & 0x0800) >> 11;
10806 lo = (newval2 & 0x07ff);
10812 diff = ((S << 24) | (I1 << 23) | (I2 << 22) | (hi << 12) | (lo << 1));
10813 diff -= (1 << 24); /* sign extend */
10816 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
10817 as_bad_where (fixP->fx_file, fixP->fx_line,
10818 _("branch out of range"));
10820 newval = newval & 0xf800;
10821 newval2 = newval2 & 0xd000;
10822 if (seg->use_rela_p && !fixP->fx_done)
10825 fixP->fx_offset = value;
10827 fixP->fx_addnumber = value;
10831 S = (value & 0x01000000) >> 24;
10832 I1 = (value & 0x00800000) >> 23;
10833 I2 = (value & 0x00400000) >> 22;
10834 hi = (value & 0x003ff000) >> 12;
10835 lo = (value & 0x00000ffe) >> 1;
10840 newval = newval | (S << 10) | hi;
10841 newval2 = newval2 | (I1 << 13) | (I2 << 11) | lo;
10843 md_number_to_chars (buf, newval, THUMB_SIZE);
10844 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10849 if (seg->use_rela_p && !fixP->fx_done)
10851 if (fixP->fx_done || fixP->fx_pcrel)
10852 md_number_to_chars (buf, value, 2);
10856 value = fixP->fx_offset;
10857 md_number_to_chars (buf, value, 2);
10863 case BFD_RELOC_ARM_TLS_GD32:
10864 case BFD_RELOC_ARM_TLS_LE32:
10865 case BFD_RELOC_ARM_TLS_IE32:
10866 case BFD_RELOC_ARM_TLS_LDM32:
10867 case BFD_RELOC_ARM_TLS_LDO32:
10868 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10871 case BFD_RELOC_ARM_GOT32:
10872 case BFD_RELOC_ARM_GOTOFF:
10873 case BFD_RELOC_ARM_TARGET2:
10874 if (seg->use_rela_p && !fixP->fx_done)
10876 md_number_to_chars (buf, 0, 4);
10880 case BFD_RELOC_RVA:
10882 case BFD_RELOC_ARM_TARGET1:
10883 case BFD_RELOC_ARM_ROSEGREL32:
10884 case BFD_RELOC_ARM_SBREL32:
10885 case BFD_RELOC_32_PCREL:
10886 if (seg->use_rela_p && !fixP->fx_done)
10888 if (fixP->fx_done || fixP->fx_pcrel)
10889 md_number_to_chars (buf, value, 4);
10893 value = fixP->fx_offset;
10894 md_number_to_chars (buf, value, 4);
10900 case BFD_RELOC_ARM_PREL31:
10901 if (fixP->fx_done || fixP->fx_pcrel)
10903 newval = md_chars_to_number (buf, 4) & 0x80000000;
10904 if ((value ^ (value >> 1)) & 0x40000000)
10906 as_bad_where (fixP->fx_file, fixP->fx_line,
10907 _("rel31 relocation overflow"));
10909 newval |= value & 0x7fffffff;
10910 md_number_to_chars (buf, newval, 4);
10914 case BFD_RELOC_ARM_PLT32:
10915 /* It appears the instruction is fully prepared at this point. */
10919 case BFD_RELOC_ARM_CP_OFF_IMM:
10920 if (value < -1023 || value > 1023 || (value & 3))
10921 as_bad_where (fixP->fx_file, fixP->fx_line,
10922 _("co-processor offset out of range"));
10927 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
10928 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
10930 newval &= ~WRITE_BACK;
10931 md_number_to_chars (buf, newval, INSN_SIZE);
10934 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
10935 if (value < -255 || value > 255)
10936 as_bad_where (fixP->fx_file, fixP->fx_line,
10937 _("co-processor offset out of range"));
10938 goto cp_off_common;
10940 case BFD_RELOC_ARM_THUMB_OFFSET:
10941 newval = md_chars_to_number (buf, THUMB_SIZE);
10942 /* Exactly what ranges, and where the offset is inserted depends
10943 on the type of instruction, we can establish this from the
10945 switch (newval >> 12)
10947 case 4: /* PC load. */
10948 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
10949 forced to zero for these loads; md_pcrel_from has already
10950 compensated for this. */
10952 as_bad_where (fixP->fx_file, fixP->fx_line,
10953 _("invalid offset, target not word aligned (0x%08lX)"),
10954 (((unsigned int) fixP->fx_frag->fr_address
10955 + (unsigned int) fixP->fx_where) & ~3) + value);
10957 if (value & ~0x3fc)
10958 as_bad_where (fixP->fx_file, fixP->fx_line,
10959 _("invalid offset, value too big (0x%08lX)"),
10962 newval |= value >> 2;
10965 case 9: /* SP load/store. */
10966 if (value & ~0x3fc)
10967 as_bad_where (fixP->fx_file, fixP->fx_line,
10968 _("invalid offset, value too big (0x%08lX)"),
10970 newval |= value >> 2;
10973 case 6: /* Word load/store. */
10975 as_bad_where (fixP->fx_file, fixP->fx_line,
10976 _("invalid offset, value too big (0x%08lX)"),
10978 newval |= value << 4; /* 6 - 2. */
10981 case 7: /* Byte load/store. */
10983 as_bad_where (fixP->fx_file, fixP->fx_line,
10984 _("invalid offset, value too big (0x%08lX)"),
10986 newval |= value << 6;
10989 case 8: /* Halfword load/store. */
10991 as_bad_where (fixP->fx_file, fixP->fx_line,
10992 _("invalid offset, value too big (0x%08lX)"),
10994 newval |= value << 5; /* 6 - 1. */
10998 as_bad_where (fixP->fx_file, fixP->fx_line,
10999 "Unable to process relocation for thumb opcode: %lx",
11000 (unsigned long) newval);
11003 md_number_to_chars (buf, newval, THUMB_SIZE);
11006 case BFD_RELOC_ARM_THUMB_ADD:
11007 /* This is a complicated relocation, since we use it for all of
11008 the following immediate relocations:
11012 9bit ADD/SUB SP word-aligned
11013 10bit ADD PC/SP word-aligned
11015 The type of instruction being processed is encoded in the
11022 newval = md_chars_to_number (buf, THUMB_SIZE);
11024 int rd = (newval >> 4) & 0xf;
11025 int rs = newval & 0xf;
11026 int subtract = !!(newval & 0x8000);
11028 /* Check for HI regs, only very restricted cases allowed:
11029 Adjusting SP, and using PC or SP to get an address. */
11030 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
11031 || (rs > 7 && rs != REG_SP && rs != REG_PC))
11032 as_bad_where (fixP->fx_file, fixP->fx_line,
11033 _("invalid Hi register with immediate"));
11035 /* If value is negative, choose the opposite instruction. */
11039 subtract = !subtract;
11041 as_bad_where (fixP->fx_file, fixP->fx_line,
11042 _("immediate value out of range"));
11047 if (value & ~0x1fc)
11048 as_bad_where (fixP->fx_file, fixP->fx_line,
11049 _("invalid immediate for stack address calculation"));
11050 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
11051 newval |= value >> 2;
11053 else if (rs == REG_PC || rs == REG_SP)
11055 if (subtract || value & ~0x3fc)
11056 as_bad_where (fixP->fx_file, fixP->fx_line,
11057 _("invalid immediate for address calculation (value = 0x%08lX)"),
11058 (unsigned long) value);
11059 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
11061 newval |= value >> 2;
11066 as_bad_where (fixP->fx_file, fixP->fx_line,
11067 _("immediate value out of range"));
11068 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
11069 newval |= (rd << 8) | value;
11074 as_bad_where (fixP->fx_file, fixP->fx_line,
11075 _("immediate value out of range"));
11076 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
11077 newval |= rd | (rs << 3) | (value << 6);
11080 md_number_to_chars (buf, newval, THUMB_SIZE);
11083 case BFD_RELOC_ARM_THUMB_IMM:
11084 newval = md_chars_to_number (buf, THUMB_SIZE);
11085 if (value < 0 || value > 255)
11086 as_bad_where (fixP->fx_file, fixP->fx_line,
11087 _("invalid immediate: %ld is too large"),
11090 md_number_to_chars (buf, newval, THUMB_SIZE);
11093 case BFD_RELOC_ARM_THUMB_SHIFT:
11094 /* 5bit shift value (0..32). LSL cannot take 32. */
11095 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
11096 temp = newval & 0xf800;
11097 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
11098 as_bad_where (fixP->fx_file, fixP->fx_line,
11099 _("invalid shift value: %ld"), (long) value);
11100 /* Shifts of zero must be encoded as LSL. */
11102 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
11103 /* Shifts of 32 are encoded as zero. */
11104 else if (value == 32)
11106 newval |= value << 6;
11107 md_number_to_chars (buf, newval, THUMB_SIZE);
11110 case BFD_RELOC_VTABLE_INHERIT:
11111 case BFD_RELOC_VTABLE_ENTRY:
11115 case BFD_RELOC_UNUSED:
11117 as_bad_where (fixP->fx_file, fixP->fx_line,
11118 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
11122 /* Translate internal representation of relocation info to BFD target
11126 tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
11130 bfd_reloc_code_real_type code;
11132 reloc = xmalloc (sizeof (arelent));
11134 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
11135 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11136 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
11138 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
11140 if (fixp->fx_pcrel == 0)
11141 reloc->addend = fixp->fx_offset;
11143 reloc->addend = fixp->fx_offset = reloc->address;
11144 #else /* OBJ_ELF */
11145 reloc->addend = fixp->fx_offset;
11148 switch (fixp->fx_r_type)
11151 if (fixp->fx_pcrel)
11153 code = BFD_RELOC_8_PCREL;
11158 if (fixp->fx_pcrel)
11160 code = BFD_RELOC_16_PCREL;
11165 if (fixp->fx_pcrel)
11167 code = BFD_RELOC_32_PCREL;
11171 case BFD_RELOC_NONE:
11172 case BFD_RELOC_ARM_PCREL_BRANCH:
11173 case BFD_RELOC_ARM_PCREL_BLX:
11174 case BFD_RELOC_RVA:
11175 case BFD_RELOC_THUMB_PCREL_BRANCH7:
11176 case BFD_RELOC_THUMB_PCREL_BRANCH9:
11177 case BFD_RELOC_THUMB_PCREL_BRANCH12:
11178 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11179 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11180 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11181 case BFD_RELOC_THUMB_PCREL_BLX:
11182 case BFD_RELOC_VTABLE_ENTRY:
11183 case BFD_RELOC_VTABLE_INHERIT:
11184 code = fixp->fx_r_type;
11187 case BFD_RELOC_ARM_LITERAL:
11188 case BFD_RELOC_ARM_HWLITERAL:
11189 /* If this is called then the a literal has
11190 been referenced across a section boundary. */
11191 as_bad_where (fixp->fx_file, fixp->fx_line,
11192 _("literal referenced across section boundary"));
11196 case BFD_RELOC_ARM_GOT32:
11197 case BFD_RELOC_ARM_GOTOFF:
11198 case BFD_RELOC_ARM_PLT32:
11199 case BFD_RELOC_ARM_TARGET1:
11200 case BFD_RELOC_ARM_ROSEGREL32:
11201 case BFD_RELOC_ARM_SBREL32:
11202 case BFD_RELOC_ARM_PREL31:
11203 case BFD_RELOC_ARM_TARGET2:
11204 case BFD_RELOC_ARM_TLS_LE32:
11205 case BFD_RELOC_ARM_TLS_LDO32:
11206 code = fixp->fx_r_type;
11209 case BFD_RELOC_ARM_TLS_GD32:
11210 case BFD_RELOC_ARM_TLS_IE32:
11211 case BFD_RELOC_ARM_TLS_LDM32:
11212 /* BFD will include the symbol's address in the addend.
11213 But we don't want that, so subtract it out again here. */
11214 if (!S_IS_COMMON (fixp->fx_addsy))
11215 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
11216 code = fixp->fx_r_type;
11220 case BFD_RELOC_ARM_IMMEDIATE:
11221 as_bad_where (fixp->fx_file, fixp->fx_line,
11222 _("internal relocation (type: IMMEDIATE) not fixed up"));
11225 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
11226 as_bad_where (fixp->fx_file, fixp->fx_line,
11227 _("ADRL used for a symbol not defined in the same file"));
11230 case BFD_RELOC_ARM_OFFSET_IMM:
11231 if (fixp->fx_addsy != NULL
11232 && !S_IS_DEFINED (fixp->fx_addsy)
11233 && S_IS_LOCAL (fixp->fx_addsy))
11235 as_bad_where (fixp->fx_file, fixp->fx_line,
11236 _("undefined local label `%s'"),
11237 S_GET_NAME (fixp->fx_addsy));
11241 as_bad_where (fixp->fx_file, fixp->fx_line,
11242 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
11249 switch (fixp->fx_r_type)
11251 case BFD_RELOC_NONE: type = "NONE"; break;
11252 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
11253 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
11254 case BFD_RELOC_ARM_SMI: type = "SMI"; break;
11255 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
11256 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
11257 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
11258 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
11259 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
11260 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
11261 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
11262 default: type = _("<unknown>"); break;
11264 as_bad_where (fixp->fx_file, fixp->fx_line,
11265 _("cannot represent %s relocation in this object file format"),
11272 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
11274 && fixp->fx_addsy == GOT_symbol)
11276 code = BFD_RELOC_ARM_GOTPC;
11277 reloc->addend = fixp->fx_offset = reloc->address;
11281 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
11283 if (reloc->howto == NULL)
11285 as_bad_where (fixp->fx_file, fixp->fx_line,
11286 _("cannot represent %s relocation in this object file format"),
11287 bfd_get_reloc_code_name (code));
11291 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
11292 vtable entry to be used in the relocation's section offset. */
11293 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11294 reloc->address = fixp->fx_offset;
11299 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
11302 cons_fix_new_arm (fragS * frag,
11307 bfd_reloc_code_real_type type;
11311 FIXME: @@ Should look at CPU word size. */
11315 type = BFD_RELOC_8;
11318 type = BFD_RELOC_16;
11322 type = BFD_RELOC_32;
11325 type = BFD_RELOC_64;
11329 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
11332 #if defined OBJ_COFF || defined OBJ_ELF
11334 arm_validate_fix (fixS * fixP)
11336 /* If the destination of the branch is a defined symbol which does not have
11337 the THUMB_FUNC attribute, then we must be calling a function which has
11338 the (interfacearm) attribute. We look for the Thumb entry point to that
11339 function and change the branch to refer to that function instead. */
11340 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
11341 && fixP->fx_addsy != NULL
11342 && S_IS_DEFINED (fixP->fx_addsy)
11343 && ! THUMB_IS_FUNC (fixP->fx_addsy))
11345 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
11351 arm_force_relocation (struct fix * fixp)
11353 #if defined (OBJ_COFF) && defined (TE_PE)
11354 if (fixp->fx_r_type == BFD_RELOC_RVA)
11358 /* Resolve these relocations even if the symbol is extern or weak. */
11359 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
11360 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
11361 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
11364 return generic_force_reloc (fixp);
11368 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
11369 local labels from being added to the output symbol table when they
11370 are used with the ADRL pseudo op. The ADRL relocation should always
11371 be resolved before the binbary is emitted, so it is safe to say that
11372 it is adjustable. */
11375 arm_fix_adjustable (fixS * fixP)
11377 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
11384 /* Relocations against Thumb function names must be left unadjusted,
11385 so that the linker can use this information to correctly set the
11386 bottom bit of their addresses. The MIPS version of this function
11387 also prevents relocations that are mips-16 specific, but I do not
11388 know why it does this.
11391 There is one other problem that ought to be addressed here, but
11392 which currently is not: Taking the address of a label (rather
11393 than a function) and then later jumping to that address. Such
11394 addresses also ought to have their bottom bit set (assuming that
11395 they reside in Thumb code), but at the moment they will not. */
11398 arm_fix_adjustable (fixS * fixP)
11400 if (fixP->fx_addsy == NULL)
11403 if (THUMB_IS_FUNC (fixP->fx_addsy)
11404 && fixP->fx_subsy == NULL)
11407 /* We need the symbol name for the VTABLE entries. */
11408 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11409 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11412 /* Don't allow symbols to be discarded on GOT related relocs. */
11413 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
11414 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
11415 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
11416 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
11417 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
11418 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
11419 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
11420 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
11421 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
11428 elf32_arm_target_format (void)
11431 return (target_big_endian
11432 ? "elf32-bigarm-symbian"
11433 : "elf32-littlearm-symbian");
11434 #elif defined (TE_VXWORKS)
11435 return (target_big_endian
11436 ? "elf32-bigarm-vxworks"
11437 : "elf32-littlearm-vxworks");
11439 if (target_big_endian)
11440 return "elf32-bigarm";
11442 return "elf32-littlearm";
11447 armelf_frob_symbol (symbolS * symp,
11450 elf_frob_symbol (symp, puntp);
11454 /* MD interface: Finalization. */
11456 /* A good place to do this, although this was probably not intended
11457 for this kind of use. We need to dump the literal pool before
11458 references are made to a null symbol pointer. */
11463 literal_pool * pool;
11465 for (pool = list_of_pools; pool; pool = pool->next)
11467 /* Put it at the end of the relevent section. */
11468 subseg_set (pool->section, pool->sub_section);
11470 arm_elf_change_section ();
11476 /* Adjust the symbol table. This marks Thumb symbols as distinct from
11480 arm_adjust_symtab (void)
11485 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
11487 if (ARM_IS_THUMB (sym))
11489 if (THUMB_IS_FUNC (sym))
11491 /* Mark the symbol as a Thumb function. */
11492 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
11493 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
11494 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
11496 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
11497 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
11499 as_bad (_("%s: unexpected function type: %d"),
11500 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
11502 else switch (S_GET_STORAGE_CLASS (sym))
11505 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
11508 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
11511 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
11519 if (ARM_IS_INTERWORK (sym))
11520 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
11527 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
11529 if (ARM_IS_THUMB (sym))
11531 elf_symbol_type * elf_sym;
11533 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
11534 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
11536 if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
11538 /* If it's a .thumb_func, declare it as so,
11539 otherwise tag label as .code 16. */
11540 if (THUMB_IS_FUNC (sym))
11541 elf_sym->internal_elf_sym.st_info =
11542 ELF_ST_INFO (bind, STT_ARM_TFUNC);
11544 elf_sym->internal_elf_sym.st_info =
11545 ELF_ST_INFO (bind, STT_ARM_16BIT);
11552 /* MD interface: Initialization. */
11555 set_constant_flonums (void)
11559 for (i = 0; i < NUM_FLOAT_VALS; i++)
11560 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
11570 if ( (arm_ops_hsh = hash_new ()) == NULL
11571 || (arm_cond_hsh = hash_new ()) == NULL
11572 || (arm_shift_hsh = hash_new ()) == NULL
11573 || (arm_psr_hsh = hash_new ()) == NULL
11574 || (arm_reg_hsh = hash_new ()) == NULL
11575 || (arm_reloc_hsh = hash_new ()) == NULL)
11576 as_fatal (_("virtual memory exhausted"));
11578 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
11579 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
11580 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
11581 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
11582 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
11583 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
11584 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
11585 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
11586 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
11587 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
11589 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
11590 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
11593 set_constant_flonums ();
11595 /* Set the cpu variant based on the command-line options. We prefer
11596 -mcpu= over -march= if both are set (as for GCC); and we prefer
11597 -mfpu= over any other way of setting the floating point unit.
11598 Use of legacy options with new options are faulted. */
11599 if (legacy_cpu != -1)
11601 if (mcpu_cpu_opt != -1 || march_cpu_opt != -1)
11602 as_bad (_("use of old and new-style options to set CPU type"));
11604 mcpu_cpu_opt = legacy_cpu;
11606 else if (mcpu_cpu_opt == -1)
11607 mcpu_cpu_opt = march_cpu_opt;
11609 if (legacy_fpu != -1)
11611 if (mfpu_opt != -1)
11612 as_bad (_("use of old and new-style options to set FPU type"));
11614 mfpu_opt = legacy_fpu;
11616 else if (mfpu_opt == -1)
11618 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
11619 /* Some environments specify a default FPU. If they don't, infer it
11620 from the processor. */
11621 if (mcpu_fpu_opt != -1)
11622 mfpu_opt = mcpu_fpu_opt;
11624 mfpu_opt = march_fpu_opt;
11626 mfpu_opt = FPU_DEFAULT;
11630 if (mfpu_opt == -1)
11632 if (mcpu_cpu_opt == -1)
11633 mfpu_opt = FPU_DEFAULT;
11634 else if (mcpu_cpu_opt & ARM_EXT_V5)
11635 mfpu_opt = FPU_ARCH_VFP_V2;
11637 mfpu_opt = FPU_ARCH_FPA;
11640 if (mcpu_cpu_opt == -1)
11641 mcpu_cpu_opt = CPU_DEFAULT;
11643 cpu_variant = mcpu_cpu_opt | mfpu_opt;
11645 #if defined OBJ_COFF || defined OBJ_ELF
11647 unsigned int flags = 0;
11649 #if defined OBJ_ELF
11650 flags = meabi_flags;
11652 switch (meabi_flags)
11654 case EF_ARM_EABI_UNKNOWN:
11656 /* Set the flags in the private structure. */
11657 if (uses_apcs_26) flags |= F_APCS26;
11658 if (support_interwork) flags |= F_INTERWORK;
11659 if (uses_apcs_float) flags |= F_APCS_FLOAT;
11660 if (pic_code) flags |= F_PIC;
11661 if ((cpu_variant & FPU_ANY) == FPU_NONE
11662 || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
11663 flags |= F_SOFT_FLOAT;
11665 switch (mfloat_abi_opt)
11667 case ARM_FLOAT_ABI_SOFT:
11668 case ARM_FLOAT_ABI_SOFTFP:
11669 flags |= F_SOFT_FLOAT;
11672 case ARM_FLOAT_ABI_HARD:
11673 if (flags & F_SOFT_FLOAT)
11674 as_bad (_("hard-float conflicts with specified fpu"));
11678 /* Using VFP conventions (even if soft-float). */
11679 if (cpu_variant & FPU_VFP_EXT_NONE)
11680 flags |= F_VFP_FLOAT;
11682 #if defined OBJ_ELF
11683 if (cpu_variant & FPU_ARCH_MAVERICK)
11684 flags |= EF_ARM_MAVERICK_FLOAT;
11687 case EF_ARM_EABI_VER4:
11688 /* No additional flags to set. */
11695 bfd_set_private_flags (stdoutput, flags);
11697 /* We have run out flags in the COFF header to encode the
11698 status of ATPCS support, so instead we create a dummy,
11699 empty, debug section called .arm.atpcs. */
11704 sec = bfd_make_section (stdoutput, ".arm.atpcs");
11708 bfd_set_section_flags
11709 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
11710 bfd_set_section_size (stdoutput, sec, 0);
11711 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
11717 /* Record the CPU type as well. */
11718 switch (cpu_variant & ARM_CPU_MASK)
11721 mach = bfd_mach_arm_2;
11724 case ARM_3: /* Also ARM_250. */
11725 mach = bfd_mach_arm_2a;
11728 case ARM_6: /* Also ARM_7. */
11729 mach = bfd_mach_arm_3;
11733 mach = bfd_mach_arm_unknown;
11737 /* Catch special cases. */
11738 if (cpu_variant & ARM_CEXT_IWMMXT)
11739 mach = bfd_mach_arm_iWMMXt;
11740 else if (cpu_variant & ARM_CEXT_XSCALE)
11741 mach = bfd_mach_arm_XScale;
11742 else if (cpu_variant & ARM_CEXT_MAVERICK)
11743 mach = bfd_mach_arm_ep9312;
11744 else if (cpu_variant & ARM_EXT_V5E)
11745 mach = bfd_mach_arm_5TE;
11746 else if (cpu_variant & ARM_EXT_V5)
11748 if (cpu_variant & ARM_EXT_V4T)
11749 mach = bfd_mach_arm_5T;
11751 mach = bfd_mach_arm_5;
11753 else if (cpu_variant & ARM_EXT_V4)
11755 if (cpu_variant & ARM_EXT_V4T)
11756 mach = bfd_mach_arm_4T;
11758 mach = bfd_mach_arm_4;
11760 else if (cpu_variant & ARM_EXT_V3M)
11761 mach = bfd_mach_arm_3M;
11763 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
11766 /* Command line processing. */
11769 Invocation line includes a switch not recognized by the base assembler.
11770 See if it's a processor-specific option.
11772 This routine is somewhat complicated by the need for backwards
11773 compatibility (since older releases of gcc can't be changed).
11774 The new options try to make the interface as compatible as
11777 New options (supported) are:
11779 -mcpu=<cpu name> Assemble for selected processor
11780 -march=<architecture name> Assemble for selected architecture
11781 -mfpu=<fpu architecture> Assemble for selected FPU.
11782 -EB/-mbig-endian Big-endian
11783 -EL/-mlittle-endian Little-endian
11784 -k Generate PIC code
11785 -mthumb Start in Thumb mode
11786 -mthumb-interwork Code supports ARM/Thumb interworking
11788 For now we will also provide support for:
11790 -mapcs-32 32-bit Program counter
11791 -mapcs-26 26-bit Program counter
11792 -macps-float Floats passed in FP registers
11793 -mapcs-reentrant Reentrant code
11795 (sometime these will probably be replaced with -mapcs=<list of options>
11796 and -matpcs=<list of options>)
11798 The remaining options are only supported for back-wards compatibility.
11799 Cpu variants, the arm part is optional:
11800 -m[arm]1 Currently not supported.
11801 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
11802 -m[arm]3 Arm 3 processor
11803 -m[arm]6[xx], Arm 6 processors
11804 -m[arm]7[xx][t][[d]m] Arm 7 processors
11805 -m[arm]8[10] Arm 8 processors
11806 -m[arm]9[20][tdmi] Arm 9 processors
11807 -mstrongarm[110[0]] StrongARM processors
11808 -mxscale XScale processors
11809 -m[arm]v[2345[t[e]]] Arm architectures
11810 -mall All (except the ARM1)
11812 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
11813 -mfpe-old (No float load/store multiples)
11814 -mvfpxd VFP Single precision
11816 -mno-fpu Disable all floating point instructions
11818 The following CPU names are recognized:
11819 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
11820 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
11821 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
11822 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
11823 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
11824 arm10t arm10e, arm1020t, arm1020e, arm10200e,
11825 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
11829 const char * md_shortopts = "m:k";
11831 #ifdef ARM_BI_ENDIAN
11832 #define OPTION_EB (OPTION_MD_BASE + 0)
11833 #define OPTION_EL (OPTION_MD_BASE + 1)
11835 #if TARGET_BYTES_BIG_ENDIAN
11836 #define OPTION_EB (OPTION_MD_BASE + 0)
11838 #define OPTION_EL (OPTION_MD_BASE + 1)
11842 struct option md_longopts[] =
11845 {"EB", no_argument, NULL, OPTION_EB},
11848 {"EL", no_argument, NULL, OPTION_EL},
11850 {NULL, no_argument, NULL, 0}
11853 size_t md_longopts_size = sizeof (md_longopts);
11855 struct arm_option_table
11857 char *option; /* Option name to match. */
11858 char *help; /* Help information. */
11859 int *var; /* Variable to change. */
11860 int value; /* What to change it to. */
11861 char *deprecated; /* If non-null, print this message. */
11864 struct arm_option_table arm_opts[] =
11866 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
11867 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
11868 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
11869 &support_interwork, 1, NULL},
11870 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
11871 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
11872 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
11874 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
11875 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
11876 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
11877 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
11880 /* These are recognized by the assembler, but have no affect on code. */
11881 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
11882 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
11884 /* DON'T add any new processors to this list -- we want the whole list
11885 to go away... Add them to the processors table instead. */
11886 {"marm1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
11887 {"m1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
11888 {"marm2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
11889 {"m2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
11890 {"marm250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
11891 {"m250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
11892 {"marm3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
11893 {"m3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
11894 {"marm6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
11895 {"m6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
11896 {"marm600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
11897 {"m600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
11898 {"marm610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
11899 {"m610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
11900 {"marm620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
11901 {"m620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
11902 {"marm7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
11903 {"m7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
11904 {"marm70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
11905 {"m70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
11906 {"marm700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
11907 {"m700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
11908 {"marm700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
11909 {"m700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
11910 {"marm710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
11911 {"m710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
11912 {"marm710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
11913 {"m710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
11914 {"marm720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
11915 {"m720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
11916 {"marm7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
11917 {"m7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
11918 {"marm7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
11919 {"m7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
11920 {"marm7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
11921 {"m7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
11922 {"marm7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
11923 {"m7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
11924 {"marm7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
11925 {"m7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
11926 {"marm7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
11927 {"m7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
11928 {"marm7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
11929 {"m7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
11930 {"marm7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
11931 {"m7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
11932 {"marm7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11933 {"m7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11934 {"marm7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11935 {"m7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11936 {"marm710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
11937 {"m710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
11938 {"marm720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
11939 {"m720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
11940 {"marm740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
11941 {"m740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
11942 {"marm8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
11943 {"m8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
11944 {"marm810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
11945 {"m810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
11946 {"marm9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
11947 {"m9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
11948 {"marm9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
11949 {"m9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
11950 {"marm920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
11951 {"m920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
11952 {"marm940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
11953 {"m940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
11954 {"mstrongarm", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
11955 {"mstrongarm110", NULL, &legacy_cpu, ARM_ARCH_V4,
11956 N_("use -mcpu=strongarm110")},
11957 {"mstrongarm1100", NULL, &legacy_cpu, ARM_ARCH_V4,
11958 N_("use -mcpu=strongarm1100")},
11959 {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4,
11960 N_("use -mcpu=strongarm1110")},
11961 {"mxscale", NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
11962 {"miwmmxt", NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
11963 {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
11965 /* Architecture variants -- don't add any more to this list either. */
11966 {"mv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
11967 {"marmv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
11968 {"mv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
11969 {"marmv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
11970 {"mv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
11971 {"marmv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
11972 {"mv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
11973 {"marmv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
11974 {"mv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
11975 {"marmv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
11976 {"mv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
11977 {"marmv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
11978 {"mv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
11979 {"marmv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
11980 {"mv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
11981 {"marmv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
11982 {"mv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
11983 {"marmv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
11985 /* Floating point variants -- don't add any more to this list either. */
11986 {"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
11987 {"mfpa10", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
11988 {"mfpa11", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
11989 {"mno-fpu", NULL, &legacy_fpu, 0,
11990 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
11992 {NULL, NULL, NULL, 0, NULL}
11995 struct arm_cpu_option_table
11999 /* For some CPUs we assume an FPU unless the user explicitly sets
12004 /* This list should, at a minimum, contain all the cpu names
12005 recognized by GCC. */
12006 static struct arm_cpu_option_table arm_cpus[] =
12008 {"all", ARM_ANY, FPU_ARCH_FPA},
12009 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA},
12010 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA},
12011 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA},
12012 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA},
12013 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA},
12014 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA},
12015 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA},
12016 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA},
12017 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA},
12018 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA},
12019 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA},
12020 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA},
12021 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA},
12022 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA},
12023 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA},
12024 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA},
12025 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA},
12026 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA},
12027 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA},
12028 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12029 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA},
12030 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12031 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12032 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA},
12033 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA},
12034 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA},
12035 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA},
12036 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12037 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
12038 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA},
12039 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA},
12040 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA},
12041 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA},
12042 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA},
12043 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA},
12044 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA},
12045 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA},
12046 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA},
12047 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA},
12048 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12049 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12050 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12051 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
12052 /* For V5 or later processors we default to using VFP; but the user
12053 should really set the FPU type explicitly. */
12054 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12055 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12056 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12057 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12058 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12059 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12060 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12061 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12062 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12063 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
12064 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12065 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12066 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
12067 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12068 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12069 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12070 {"arm1136js", ARM_ARCH_V6, FPU_NONE},
12071 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE},
12072 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
12073 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
12074 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2},
12075 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE},
12076 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE},
12077 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2},
12078 /* ??? XSCALE is really an architecture. */
12079 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
12080 /* ??? iwmmxt is not a processor. */
12081 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2},
12082 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
12084 {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK},
12088 struct arm_arch_option_table
12095 /* This list should, at a minimum, contain all the architecture names
12096 recognized by GCC. */
12097 static struct arm_arch_option_table arm_archs[] =
12099 {"all", ARM_ANY, FPU_ARCH_FPA},
12100 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
12101 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
12102 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
12103 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
12104 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
12105 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
12106 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
12107 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
12108 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12109 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
12110 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
12111 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
12112 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
12113 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
12114 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
12115 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
12116 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
12117 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
12118 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
12119 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
12120 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
12121 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
12122 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
12123 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
12124 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
12125 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
12126 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
12130 /* ISA extensions in the co-processor space. */
12131 struct arm_option_value_table
12137 static struct arm_option_value_table arm_extensions[] =
12139 {"maverick", ARM_CEXT_MAVERICK},
12140 {"xscale", ARM_CEXT_XSCALE},
12141 {"iwmmxt", ARM_CEXT_IWMMXT},
12145 /* This list should, at a minimum, contain all the fpu names
12146 recognized by GCC. */
12147 static struct arm_option_value_table arm_fpus[] =
12149 {"softfpa", FPU_NONE},
12150 {"fpe", FPU_ARCH_FPE},
12151 {"fpe2", FPU_ARCH_FPE},
12152 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
12153 {"fpa", FPU_ARCH_FPA},
12154 {"fpa10", FPU_ARCH_FPA},
12155 {"fpa11", FPU_ARCH_FPA},
12156 {"arm7500fe", FPU_ARCH_FPA},
12157 {"softvfp", FPU_ARCH_VFP},
12158 {"softvfp+vfp", FPU_ARCH_VFP_V2},
12159 {"vfp", FPU_ARCH_VFP_V2},
12160 {"vfp9", FPU_ARCH_VFP_V2},
12161 {"vfp10", FPU_ARCH_VFP_V2},
12162 {"vfp10-r0", FPU_ARCH_VFP_V1},
12163 {"vfpxd", FPU_ARCH_VFP_V1xD},
12164 {"arm1020t", FPU_ARCH_VFP_V1},
12165 {"arm1020e", FPU_ARCH_VFP_V2},
12166 {"arm1136jfs", FPU_ARCH_VFP_V2},
12167 {"arm1136jf-s", FPU_ARCH_VFP_V2},
12168 {"maverick", FPU_ARCH_MAVERICK},
12172 static struct arm_option_value_table arm_float_abis[] =
12174 {"hard", ARM_FLOAT_ABI_HARD},
12175 {"softfp", ARM_FLOAT_ABI_SOFTFP},
12176 {"soft", ARM_FLOAT_ABI_SOFT},
12181 /* We only know how to output GNU and ver 4 (AAELF) formats. */
12182 static struct arm_option_value_table arm_eabis[] =
12184 {"gnu", EF_ARM_EABI_UNKNOWN},
12185 {"4", EF_ARM_EABI_VER4},
12190 struct arm_long_option_table
12192 char * option; /* Substring to match. */
12193 char * help; /* Help information. */
12194 int (* func) (char * subopt); /* Function to decode sub-option. */
12195 char * deprecated; /* If non-null, print this message. */
12199 arm_parse_extension (char * str, int * opt_p)
12201 while (str != NULL && *str != 0)
12203 struct arm_option_value_table * opt;
12209 as_bad (_("invalid architectural extension"));
12214 ext = strchr (str, '+');
12217 optlen = ext - str;
12219 optlen = strlen (str);
12223 as_bad (_("missing architectural extension"));
12227 for (opt = arm_extensions; opt->name != NULL; opt++)
12228 if (strncmp (opt->name, str, optlen) == 0)
12230 *opt_p |= opt->value;
12234 if (opt->name == NULL)
12236 as_bad (_("unknown architectural extnsion `%s'"), str);
12247 arm_parse_cpu (char * str)
12249 struct arm_cpu_option_table * opt;
12250 char * ext = strchr (str, '+');
12254 optlen = ext - str;
12256 optlen = strlen (str);
12260 as_bad (_("missing cpu name `%s'"), str);
12264 for (opt = arm_cpus; opt->name != NULL; opt++)
12265 if (strncmp (opt->name, str, optlen) == 0)
12267 mcpu_cpu_opt = opt->value;
12268 mcpu_fpu_opt = opt->default_fpu;
12271 return arm_parse_extension (ext, &mcpu_cpu_opt);
12276 as_bad (_("unknown cpu `%s'"), str);
12281 arm_parse_arch (char * str)
12283 struct arm_arch_option_table *opt;
12284 char *ext = strchr (str, '+');
12288 optlen = ext - str;
12290 optlen = strlen (str);
12294 as_bad (_("missing architecture name `%s'"), str);
12299 for (opt = arm_archs; opt->name != NULL; opt++)
12300 if (streq (opt->name, str))
12302 march_cpu_opt = opt->value;
12303 march_fpu_opt = opt->default_fpu;
12306 return arm_parse_extension (ext, &march_cpu_opt);
12311 as_bad (_("unknown architecture `%s'\n"), str);
12316 arm_parse_fpu (char * str)
12318 struct arm_option_value_table * opt;
12320 for (opt = arm_fpus; opt->name != NULL; opt++)
12321 if (streq (opt->name, str))
12323 mfpu_opt = opt->value;
12327 as_bad (_("unknown floating point format `%s'\n"), str);
12332 arm_parse_float_abi (char * str)
12334 struct arm_option_value_table * opt;
12336 for (opt = arm_float_abis; opt->name != NULL; opt++)
12337 if (streq (opt->name, str))
12339 mfloat_abi_opt = opt->value;
12343 as_bad (_("unknown floating point abi `%s'\n"), str);
12349 arm_parse_eabi (char * str)
12351 struct arm_option_value_table *opt;
12353 for (opt = arm_eabis; opt->name != NULL; opt++)
12354 if (streq (opt->name, str))
12356 meabi_flags = opt->value;
12359 as_bad (_("unknown EABI `%s'\n"), str);
12364 struct arm_long_option_table arm_long_opts[] =
12366 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
12367 arm_parse_cpu, NULL},
12368 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
12369 arm_parse_arch, NULL},
12370 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
12371 arm_parse_fpu, NULL},
12372 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
12373 arm_parse_float_abi, NULL},
12375 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
12376 arm_parse_eabi, NULL},
12378 {NULL, NULL, 0, NULL}
12382 md_parse_option (int c, char * arg)
12384 struct arm_option_table *opt;
12385 struct arm_long_option_table *lopt;
12391 target_big_endian = 1;
12397 target_big_endian = 0;
12402 /* Listing option. Just ignore these, we don't support additional
12407 for (opt = arm_opts; opt->option != NULL; opt++)
12409 if (c == opt->option[0]
12410 && ((arg == NULL && opt->option[1] == 0)
12411 || streq (arg, opt->option + 1)))
12413 #if WARN_DEPRECATED
12414 /* If the option is deprecated, tell the user. */
12415 if (opt->deprecated != NULL)
12416 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
12417 arg ? arg : "", _(opt->deprecated));
12420 if (opt->var != NULL)
12421 *opt->var = opt->value;
12427 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
12429 /* These options are expected to have an argument. */
12430 if (c == lopt->option[0]
12432 && strncmp (arg, lopt->option + 1,
12433 strlen (lopt->option + 1)) == 0)
12435 #if WARN_DEPRECATED
12436 /* If the option is deprecated, tell the user. */
12437 if (lopt->deprecated != NULL)
12438 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
12439 _(lopt->deprecated));
12442 /* Call the sup-option parser. */
12443 return lopt->func (arg + strlen (lopt->option) - 1);
12454 md_show_usage (FILE * fp)
12456 struct arm_option_table *opt;
12457 struct arm_long_option_table *lopt;
12459 fprintf (fp, _(" ARM-specific assembler options:\n"));
12461 for (opt = arm_opts; opt->option != NULL; opt++)
12462 if (opt->help != NULL)
12463 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
12465 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
12466 if (lopt->help != NULL)
12467 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
12471 -EB assemble code for a big-endian cpu\n"));
12476 -EL assemble code for a little-endian cpu\n"));