1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
199 static const arm_feature_set arm_ext_m =
200 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
201 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
202 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
203 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
204 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
205 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
207 static const arm_feature_set arm_arch_any = ARM_ANY;
208 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
210 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
211 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
213 static const arm_feature_set arm_cext_iwmmxt2 =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
215 static const arm_feature_set arm_cext_iwmmxt =
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
217 static const arm_feature_set arm_cext_xscale =
218 ARM_FEATURE (0, ARM_CEXT_XSCALE);
219 static const arm_feature_set arm_cext_maverick =
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
221 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
222 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
223 static const arm_feature_set fpu_vfp_ext_v1xd =
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
225 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
226 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
227 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
228 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
229 static const arm_feature_set fpu_vfp_ext_d32 =
230 ARM_FEATURE (0, FPU_VFP_EXT_D32);
231 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
233 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
234 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
235 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
236 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static const arm_feature_set fpu_vfp_ext_armv8 =
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
239 static const arm_feature_set fpu_neon_ext_armv8 =
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
241 static const arm_feature_set fpu_crypto_ext_armv8 =
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
337 enum neon_el_type type;
341 #define NEON_MAX_TYPE_ELS 4
345 struct neon_type_el el[NEON_MAX_TYPE_ELS];
349 enum it_instruction_type
354 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
355 if inside, should be the last one. */
356 NEUTRAL_IT_INSN, /* This could be either inside or outside,
357 i.e. BKPT and NOP. */
358 IT_INSN /* The IT insn has been parsed. */
361 /* The maximum number of operands we need. */
362 #define ARM_IT_MAX_OPERANDS 6
367 unsigned long instruction;
371 /* "uncond_value" is set to the value in place of the conditional field in
372 unconditional versions of the instruction, or -1 if nothing is
375 struct neon_type vectype;
376 /* This does not indicate an actual NEON instruction, only that
377 the mnemonic accepts neon-style type suffixes. */
379 /* Set to the opcode if the instruction needs relaxation.
380 Zero if the instruction is not relaxed. */
384 bfd_reloc_code_real_type type;
389 enum it_instruction_type it_insn_type;
395 struct neon_type_el vectype;
396 unsigned present : 1; /* Operand present. */
397 unsigned isreg : 1; /* Operand was a register. */
398 unsigned immisreg : 1; /* .imm field is a second register. */
399 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
400 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
401 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
402 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
403 instructions. This allows us to disambiguate ARM <-> vector insns. */
404 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
405 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
406 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
407 unsigned issingle : 1; /* Operand is VFP single-precision register. */
408 unsigned hasreloc : 1; /* Operand has relocation suffix. */
409 unsigned writeback : 1; /* Operand has trailing ! */
410 unsigned preind : 1; /* Preindexed address. */
411 unsigned postind : 1; /* Postindexed address. */
412 unsigned negative : 1; /* Index register was negated. */
413 unsigned shifted : 1; /* Shift applied to operation. */
414 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
415 } operands[ARM_IT_MAX_OPERANDS];
418 static struct arm_it inst;
420 #define NUM_FLOAT_VALS 8
422 const char * fp_const[] =
424 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
427 /* Number of littlenums required to hold an extended precision number. */
428 #define MAX_LITTLENUMS 6
430 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
440 #define CP_T_X 0x00008000
441 #define CP_T_Y 0x00400000
443 #define CONDS_BIT 0x00100000
444 #define LOAD_BIT 0x00100000
446 #define DOUBLE_LOAD_FLAG 0x00000001
450 const char * template_name;
454 #define COND_ALWAYS 0xE
458 const char * template_name;
462 struct asm_barrier_opt
464 const char * template_name;
466 const arm_feature_set arch;
469 /* The bit that distinguishes CPSR and SPSR. */
470 #define SPSR_BIT (1 << 22)
472 /* The individual PSR flag bits. */
473 #define PSR_c (1 << 16)
474 #define PSR_x (1 << 17)
475 #define PSR_s (1 << 18)
476 #define PSR_f (1 << 19)
481 bfd_reloc_code_real_type reloc;
486 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
487 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
492 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
495 /* Bits for DEFINED field in neon_typed_alias. */
496 #define NTA_HASTYPE 1
497 #define NTA_HASINDEX 2
499 struct neon_typed_alias
501 unsigned char defined;
503 struct neon_type_el eltype;
506 /* ARM register categories. This includes coprocessor numbers and various
507 architecture extensions' registers. */
534 /* Structure for a hash table entry for a register.
535 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
536 information which states whether a vector type or index is specified (for a
537 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
543 unsigned char builtin;
544 struct neon_typed_alias * neon;
547 /* Diagnostics used when we don't get a register of the expected type. */
548 const char * const reg_expected_msgs[] =
550 N_("ARM register expected"),
551 N_("bad or missing co-processor number"),
552 N_("co-processor register expected"),
553 N_("FPA register expected"),
554 N_("VFP single precision register expected"),
555 N_("VFP/Neon double precision register expected"),
556 N_("Neon quad precision register expected"),
557 N_("VFP single or double precision register expected"),
558 N_("Neon double or quad precision register expected"),
559 N_("VFP single, double or Neon quad precision register expected"),
560 N_("VFP system register expected"),
561 N_("Maverick MVF register expected"),
562 N_("Maverick MVD register expected"),
563 N_("Maverick MVFX register expected"),
564 N_("Maverick MVDX register expected"),
565 N_("Maverick MVAX register expected"),
566 N_("Maverick DSPSC register expected"),
567 N_("iWMMXt data register expected"),
568 N_("iWMMXt control register expected"),
569 N_("iWMMXt scalar register expected"),
570 N_("XScale accumulator register expected"),
573 /* Some well known registers that we refer to directly elsewhere. */
579 /* ARM instructions take 4bytes in the object file, Thumb instructions
585 /* Basic string to match. */
586 const char * template_name;
588 /* Parameters to instruction. */
589 unsigned int operands[8];
591 /* Conditional tag - see opcode_lookup. */
592 unsigned int tag : 4;
594 /* Basic instruction code. */
595 unsigned int avalue : 28;
597 /* Thumb-format instruction code. */
600 /* Which architecture variant provides this instruction. */
601 const arm_feature_set * avariant;
602 const arm_feature_set * tvariant;
604 /* Function to call to encode instruction in ARM format. */
605 void (* aencode) (void);
607 /* Function to call to encode instruction in Thumb format. */
608 void (* tencode) (void);
611 /* Defines for various bits that we will want to toggle. */
612 #define INST_IMMEDIATE 0x02000000
613 #define OFFSET_REG 0x02000000
614 #define HWOFFSET_IMM 0x00400000
615 #define SHIFT_BY_REG 0x00000010
616 #define PRE_INDEX 0x01000000
617 #define INDEX_UP 0x00800000
618 #define WRITE_BACK 0x00200000
619 #define LDM_TYPE_2_OR_3 0x00400000
620 #define CPSI_MMOD 0x00020000
622 #define LITERAL_MASK 0xf000f000
623 #define OPCODE_MASK 0xfe1fffff
624 #define V4_STR_BIT 0x00000020
626 #define T2_SUBS_PC_LR 0xf3de8f00
628 #define DATA_OP_SHIFT 21
630 #define T2_OPCODE_MASK 0xfe1fffff
631 #define T2_DATA_OP_SHIFT 21
633 #define A_COND_MASK 0xf0000000
634 #define A_PUSH_POP_OP_MASK 0x0fff0000
636 /* Opcodes for pushing/poping registers to/from the stack. */
637 #define A1_OPCODE_PUSH 0x092d0000
638 #define A2_OPCODE_PUSH 0x052d0004
639 #define A2_OPCODE_POP 0x049d0004
641 /* Codes to distinguish the arithmetic instructions. */
652 #define OPCODE_CMP 10
653 #define OPCODE_CMN 11
654 #define OPCODE_ORR 12
655 #define OPCODE_MOV 13
656 #define OPCODE_BIC 14
657 #define OPCODE_MVN 15
659 #define T2_OPCODE_AND 0
660 #define T2_OPCODE_BIC 1
661 #define T2_OPCODE_ORR 2
662 #define T2_OPCODE_ORN 3
663 #define T2_OPCODE_EOR 4
664 #define T2_OPCODE_ADD 8
665 #define T2_OPCODE_ADC 10
666 #define T2_OPCODE_SBC 11
667 #define T2_OPCODE_SUB 13
668 #define T2_OPCODE_RSB 14
670 #define T_OPCODE_MUL 0x4340
671 #define T_OPCODE_TST 0x4200
672 #define T_OPCODE_CMN 0x42c0
673 #define T_OPCODE_NEG 0x4240
674 #define T_OPCODE_MVN 0x43c0
676 #define T_OPCODE_ADD_R3 0x1800
677 #define T_OPCODE_SUB_R3 0x1a00
678 #define T_OPCODE_ADD_HI 0x4400
679 #define T_OPCODE_ADD_ST 0xb000
680 #define T_OPCODE_SUB_ST 0xb080
681 #define T_OPCODE_ADD_SP 0xa800
682 #define T_OPCODE_ADD_PC 0xa000
683 #define T_OPCODE_ADD_I8 0x3000
684 #define T_OPCODE_SUB_I8 0x3800
685 #define T_OPCODE_ADD_I3 0x1c00
686 #define T_OPCODE_SUB_I3 0x1e00
688 #define T_OPCODE_ASR_R 0x4100
689 #define T_OPCODE_LSL_R 0x4080
690 #define T_OPCODE_LSR_R 0x40c0
691 #define T_OPCODE_ROR_R 0x41c0
692 #define T_OPCODE_ASR_I 0x1000
693 #define T_OPCODE_LSL_I 0x0000
694 #define T_OPCODE_LSR_I 0x0800
696 #define T_OPCODE_MOV_I8 0x2000
697 #define T_OPCODE_CMP_I8 0x2800
698 #define T_OPCODE_CMP_LR 0x4280
699 #define T_OPCODE_MOV_HR 0x4600
700 #define T_OPCODE_CMP_HR 0x4500
702 #define T_OPCODE_LDR_PC 0x4800
703 #define T_OPCODE_LDR_SP 0x9800
704 #define T_OPCODE_STR_SP 0x9000
705 #define T_OPCODE_LDR_IW 0x6800
706 #define T_OPCODE_STR_IW 0x6000
707 #define T_OPCODE_LDR_IH 0x8800
708 #define T_OPCODE_STR_IH 0x8000
709 #define T_OPCODE_LDR_IB 0x7800
710 #define T_OPCODE_STR_IB 0x7000
711 #define T_OPCODE_LDR_RW 0x5800
712 #define T_OPCODE_STR_RW 0x5000
713 #define T_OPCODE_LDR_RH 0x5a00
714 #define T_OPCODE_STR_RH 0x5200
715 #define T_OPCODE_LDR_RB 0x5c00
716 #define T_OPCODE_STR_RB 0x5400
718 #define T_OPCODE_PUSH 0xb400
719 #define T_OPCODE_POP 0xbc00
721 #define T_OPCODE_BRANCH 0xe000
723 #define THUMB_SIZE 2 /* Size of thumb instruction. */
724 #define THUMB_PP_PC_LR 0x0100
725 #define THUMB_LOAD_BIT 0x0800
726 #define THUMB2_LOAD_BIT 0x00100000
728 #define BAD_ARGS _("bad arguments to instruction")
729 #define BAD_SP _("r13 not allowed here")
730 #define BAD_PC _("r15 not allowed here")
731 #define BAD_COND _("instruction cannot be conditional")
732 #define BAD_OVERLAP _("registers may not be the same")
733 #define BAD_HIREG _("lo register required")
734 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
735 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
736 #define BAD_BRANCH _("branch must be last instruction in IT block")
737 #define BAD_NOT_IT _("instruction not allowed in IT block")
738 #define BAD_FPU _("selected FPU does not support instruction")
739 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
740 #define BAD_IT_COND _("incorrect condition in IT block")
741 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
742 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
743 #define BAD_PC_ADDRESSING \
744 _("cannot use register index with PC-relative addressing")
745 #define BAD_PC_WRITEBACK \
746 _("cannot use writeback with PC-relative addressing")
747 #define BAD_RANGE _("branch out of range")
749 static struct hash_control * arm_ops_hsh;
750 static struct hash_control * arm_cond_hsh;
751 static struct hash_control * arm_shift_hsh;
752 static struct hash_control * arm_psr_hsh;
753 static struct hash_control * arm_v7m_psr_hsh;
754 static struct hash_control * arm_reg_hsh;
755 static struct hash_control * arm_reloc_hsh;
756 static struct hash_control * arm_barrier_opt_hsh;
758 /* Stuff needed to resolve the label ambiguity
767 symbolS * last_label_seen;
768 static int label_is_thumb_function_name = FALSE;
770 /* Literal pool structure. Held on a per-section
771 and per-sub-section basis. */
773 #define MAX_LITERAL_POOL_SIZE 1024
774 typedef struct literal_pool
776 expressionS literals [MAX_LITERAL_POOL_SIZE];
777 unsigned int next_free_entry;
783 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
785 struct literal_pool * next;
788 /* Pointer to a linked list of literal pools. */
789 literal_pool * list_of_pools = NULL;
792 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
794 static struct current_it now_it;
798 now_it_compatible (int cond)
800 return (cond & ~1) == (now_it.cc & ~1);
804 conditional_insn (void)
806 return inst.cond != COND_ALWAYS;
809 static int in_it_block (void);
811 static int handle_it_state (void);
813 static void force_automatic_it_block_close (void);
815 static void it_fsm_post_encode (void);
817 #define set_it_insn_type(type) \
820 inst.it_insn_type = type; \
821 if (handle_it_state () == FAIL) \
826 #define set_it_insn_type_nonvoid(type, failret) \
829 inst.it_insn_type = type; \
830 if (handle_it_state () == FAIL) \
835 #define set_it_insn_type_last() \
838 if (inst.cond == COND_ALWAYS) \
839 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
841 set_it_insn_type (INSIDE_IT_LAST_INSN); \
847 /* This array holds the chars that always start a comment. If the
848 pre-processor is disabled, these aren't very useful. */
849 const char comment_chars[] = "@";
851 /* This array holds the chars that only start a comment at the beginning of
852 a line. If the line seems to have the form '# 123 filename'
853 .line and .file directives will appear in the pre-processed output. */
854 /* Note that input_file.c hand checks for '#' at the beginning of the
855 first line of the input file. This is because the compiler outputs
856 #NO_APP at the beginning of its output. */
857 /* Also note that comments like this one will always work. */
858 const char line_comment_chars[] = "#";
860 const char line_separator_chars[] = ";";
862 /* Chars that can be used to separate mant
863 from exp in floating point numbers. */
864 const char EXP_CHARS[] = "eE";
866 /* Chars that mean this number is a floating point constant. */
870 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
872 /* Prefix characters that indicate the start of an immediate
874 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
876 /* Separator character handling. */
878 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
881 skip_past_char (char ** str, char c)
892 #define skip_past_comma(str) skip_past_char (str, ',')
894 /* Arithmetic expressions (possibly involving symbols). */
896 /* Return TRUE if anything in the expression is a bignum. */
899 walk_no_bignums (symbolS * sp)
901 if (symbol_get_value_expression (sp)->X_op == O_big)
904 if (symbol_get_value_expression (sp)->X_add_symbol)
906 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
907 || (symbol_get_value_expression (sp)->X_op_symbol
908 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
914 static int in_my_get_expression = 0;
916 /* Third argument to my_get_expression. */
917 #define GE_NO_PREFIX 0
918 #define GE_IMM_PREFIX 1
919 #define GE_OPT_PREFIX 2
920 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
921 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
922 #define GE_OPT_PREFIX_BIG 3
925 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
930 /* In unified syntax, all prefixes are optional. */
932 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
937 case GE_NO_PREFIX: break;
939 if (!is_immediate_prefix (**str))
941 inst.error = _("immediate expression requires a # prefix");
947 case GE_OPT_PREFIX_BIG:
948 if (is_immediate_prefix (**str))
954 memset (ep, 0, sizeof (expressionS));
956 save_in = input_line_pointer;
957 input_line_pointer = *str;
958 in_my_get_expression = 1;
959 seg = expression (ep);
960 in_my_get_expression = 0;
962 if (ep->X_op == O_illegal || ep->X_op == O_absent)
964 /* We found a bad or missing expression in md_operand(). */
965 *str = input_line_pointer;
966 input_line_pointer = save_in;
967 if (inst.error == NULL)
968 inst.error = (ep->X_op == O_absent
969 ? _("missing expression") :_("bad expression"));
974 if (seg != absolute_section
975 && seg != text_section
976 && seg != data_section
977 && seg != bss_section
978 && seg != undefined_section)
980 inst.error = _("bad segment");
981 *str = input_line_pointer;
982 input_line_pointer = save_in;
989 /* Get rid of any bignums now, so that we don't generate an error for which
990 we can't establish a line number later on. Big numbers are never valid
991 in instructions, which is where this routine is always called. */
992 if (prefix_mode != GE_OPT_PREFIX_BIG
993 && (ep->X_op == O_big
995 && (walk_no_bignums (ep->X_add_symbol)
997 && walk_no_bignums (ep->X_op_symbol))))))
999 inst.error = _("invalid constant");
1000 *str = input_line_pointer;
1001 input_line_pointer = save_in;
1005 *str = input_line_pointer;
1006 input_line_pointer = save_in;
1010 /* Turn a string in input_line_pointer into a floating point constant
1011 of type TYPE, and store the appropriate bytes in *LITP. The number
1012 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1013 returned, or NULL on OK.
1015 Note that fp constants aren't represent in the normal way on the ARM.
1016 In big endian mode, things are as expected. However, in little endian
1017 mode fp constants are big-endian word-wise, and little-endian byte-wise
1018 within the words. For example, (double) 1.1 in big endian mode is
1019 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1020 the byte sequence 99 99 f1 3f 9a 99 99 99.
1022 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1025 md_atof (int type, char * litP, int * sizeP)
1028 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1060 return _("Unrecognized or unsupported floating point constant");
1063 t = atof_ieee (input_line_pointer, type, words);
1065 input_line_pointer = t;
1066 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1068 if (target_big_endian)
1070 for (i = 0; i < prec; i++)
1072 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1073 litP += sizeof (LITTLENUM_TYPE);
1078 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1079 for (i = prec - 1; i >= 0; i--)
1081 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1082 litP += sizeof (LITTLENUM_TYPE);
1085 /* For a 4 byte float the order of elements in `words' is 1 0.
1086 For an 8 byte float the order is 1 0 3 2. */
1087 for (i = 0; i < prec; i += 2)
1089 md_number_to_chars (litP, (valueT) words[i + 1],
1090 sizeof (LITTLENUM_TYPE));
1091 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1092 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1093 litP += 2 * sizeof (LITTLENUM_TYPE);
1100 /* We handle all bad expressions here, so that we can report the faulty
1101 instruction in the error message. */
1103 md_operand (expressionS * exp)
1105 if (in_my_get_expression)
1106 exp->X_op = O_illegal;
1109 /* Immediate values. */
1111 /* Generic immediate-value read function for use in directives.
1112 Accepts anything that 'expression' can fold to a constant.
1113 *val receives the number. */
1116 immediate_for_directive (int *val)
1119 exp.X_op = O_illegal;
1121 if (is_immediate_prefix (*input_line_pointer))
1123 input_line_pointer++;
1127 if (exp.X_op != O_constant)
1129 as_bad (_("expected #constant"));
1130 ignore_rest_of_line ();
1133 *val = exp.X_add_number;
1138 /* Register parsing. */
1140 /* Generic register parser. CCP points to what should be the
1141 beginning of a register name. If it is indeed a valid register
1142 name, advance CCP over it and return the reg_entry structure;
1143 otherwise return NULL. Does not issue diagnostics. */
1145 static struct reg_entry *
1146 arm_reg_parse_multi (char **ccp)
1150 struct reg_entry *reg;
1152 #ifdef REGISTER_PREFIX
1153 if (*start != REGISTER_PREFIX)
1157 #ifdef OPTIONAL_REGISTER_PREFIX
1158 if (*start == OPTIONAL_REGISTER_PREFIX)
1163 if (!ISALPHA (*p) || !is_name_beginner (*p))
1168 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1170 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1180 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1181 enum arm_reg_type type)
1183 /* Alternative syntaxes are accepted for a few register classes. */
1190 /* Generic coprocessor register names are allowed for these. */
1191 if (reg && reg->type == REG_TYPE_CN)
1196 /* For backward compatibility, a bare number is valid here. */
1198 unsigned long processor = strtoul (start, ccp, 10);
1199 if (*ccp != start && processor <= 15)
1203 case REG_TYPE_MMXWC:
1204 /* WC includes WCG. ??? I'm not sure this is true for all
1205 instructions that take WC registers. */
1206 if (reg && reg->type == REG_TYPE_MMXWCG)
1217 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1218 return value is the register number or FAIL. */
1221 arm_reg_parse (char **ccp, enum arm_reg_type type)
1224 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1227 /* Do not allow a scalar (reg+index) to parse as a register. */
1228 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1231 if (reg && reg->type == type)
1234 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1241 /* Parse a Neon type specifier. *STR should point at the leading '.'
1242 character. Does no verification at this stage that the type fits the opcode
1249 Can all be legally parsed by this function.
1251 Fills in neon_type struct pointer with parsed information, and updates STR
1252 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1253 type, FAIL if not. */
1256 parse_neon_type (struct neon_type *type, char **str)
1263 while (type->elems < NEON_MAX_TYPE_ELS)
1265 enum neon_el_type thistype = NT_untyped;
1266 unsigned thissize = -1u;
1273 /* Just a size without an explicit type. */
1277 switch (TOLOWER (*ptr))
1279 case 'i': thistype = NT_integer; break;
1280 case 'f': thistype = NT_float; break;
1281 case 'p': thistype = NT_poly; break;
1282 case 's': thistype = NT_signed; break;
1283 case 'u': thistype = NT_unsigned; break;
1285 thistype = NT_float;
1290 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1296 /* .f is an abbreviation for .f32. */
1297 if (thistype == NT_float && !ISDIGIT (*ptr))
1302 thissize = strtoul (ptr, &ptr, 10);
1304 if (thissize != 8 && thissize != 16 && thissize != 32
1307 as_bad (_("bad size %d in type specifier"), thissize);
1315 type->el[type->elems].type = thistype;
1316 type->el[type->elems].size = thissize;
1321 /* Empty/missing type is not a successful parse. */
1322 if (type->elems == 0)
1330 /* Errors may be set multiple times during parsing or bit encoding
1331 (particularly in the Neon bits), but usually the earliest error which is set
1332 will be the most meaningful. Avoid overwriting it with later (cascading)
1333 errors by calling this function. */
1336 first_error (const char *err)
1342 /* Parse a single type, e.g. ".s32", leading period included. */
1344 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1347 struct neon_type optype;
1351 if (parse_neon_type (&optype, &str) == SUCCESS)
1353 if (optype.elems == 1)
1354 *vectype = optype.el[0];
1357 first_error (_("only one type should be specified for operand"));
1363 first_error (_("vector type expected"));
1375 /* Special meanings for indices (which have a range of 0-7), which will fit into
1378 #define NEON_ALL_LANES 15
1379 #define NEON_INTERLEAVE_LANES 14
1381 /* Parse either a register or a scalar, with an optional type. Return the
1382 register number, and optionally fill in the actual type of the register
1383 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1384 type/index information in *TYPEINFO. */
1387 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1388 enum arm_reg_type *rtype,
1389 struct neon_typed_alias *typeinfo)
1392 struct reg_entry *reg = arm_reg_parse_multi (&str);
1393 struct neon_typed_alias atype;
1394 struct neon_type_el parsetype;
1398 atype.eltype.type = NT_invtype;
1399 atype.eltype.size = -1;
1401 /* Try alternate syntax for some types of register. Note these are mutually
1402 exclusive with the Neon syntax extensions. */
1405 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1413 /* Undo polymorphism when a set of register types may be accepted. */
1414 if ((type == REG_TYPE_NDQ
1415 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1416 || (type == REG_TYPE_VFSD
1417 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1418 || (type == REG_TYPE_NSDQ
1419 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1420 || reg->type == REG_TYPE_NQ))
1421 || (type == REG_TYPE_MMXWC
1422 && (reg->type == REG_TYPE_MMXWCG)))
1423 type = (enum arm_reg_type) reg->type;
1425 if (type != reg->type)
1431 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1433 if ((atype.defined & NTA_HASTYPE) != 0)
1435 first_error (_("can't redefine type for operand"));
1438 atype.defined |= NTA_HASTYPE;
1439 atype.eltype = parsetype;
1442 if (skip_past_char (&str, '[') == SUCCESS)
1444 if (type != REG_TYPE_VFD)
1446 first_error (_("only D registers may be indexed"));
1450 if ((atype.defined & NTA_HASINDEX) != 0)
1452 first_error (_("can't change index for operand"));
1456 atype.defined |= NTA_HASINDEX;
1458 if (skip_past_char (&str, ']') == SUCCESS)
1459 atype.index = NEON_ALL_LANES;
1464 my_get_expression (&exp, &str, GE_NO_PREFIX);
1466 if (exp.X_op != O_constant)
1468 first_error (_("constant expression required"));
1472 if (skip_past_char (&str, ']') == FAIL)
1475 atype.index = exp.X_add_number;
1490 /* Like arm_reg_parse, but allow allow the following extra features:
1491 - If RTYPE is non-zero, return the (possibly restricted) type of the
1492 register (e.g. Neon double or quad reg when either has been requested).
1493 - If this is a Neon vector type with additional type information, fill
1494 in the struct pointed to by VECTYPE (if non-NULL).
1495 This function will fault on encountering a scalar. */
1498 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1499 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1501 struct neon_typed_alias atype;
1503 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1508 /* Do not allow regname(... to parse as a register. */
1512 /* Do not allow a scalar (reg+index) to parse as a register. */
1513 if ((atype.defined & NTA_HASINDEX) != 0)
1515 first_error (_("register operand expected, but got scalar"));
1520 *vectype = atype.eltype;
1527 #define NEON_SCALAR_REG(X) ((X) >> 4)
1528 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1530 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1531 have enough information to be able to do a good job bounds-checking. So, we
1532 just do easy checks here, and do further checks later. */
1535 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1539 struct neon_typed_alias atype;
1541 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1543 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1546 if (atype.index == NEON_ALL_LANES)
1548 first_error (_("scalar must have an index"));
1551 else if (atype.index >= 64 / elsize)
1553 first_error (_("scalar index out of range"));
1558 *type = atype.eltype;
1562 return reg * 16 + atype.index;
1565 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1568 parse_reg_list (char ** strp)
1570 char * str = * strp;
1574 /* We come back here if we get ranges concatenated by '+' or '|'. */
1589 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1591 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1601 first_error (_("bad range in register list"));
1605 for (i = cur_reg + 1; i < reg; i++)
1607 if (range & (1 << i))
1609 (_("Warning: duplicated register (r%d) in register list"),
1617 if (range & (1 << reg))
1618 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1620 else if (reg <= cur_reg)
1621 as_tsktsk (_("Warning: register range not in ascending order"));
1626 while (skip_past_comma (&str) != FAIL
1627 || (in_range = 1, *str++ == '-'));
1632 first_error (_("missing `}'"));
1640 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1643 if (exp.X_op == O_constant)
1645 if (exp.X_add_number
1646 != (exp.X_add_number & 0x0000ffff))
1648 inst.error = _("invalid register mask");
1652 if ((range & exp.X_add_number) != 0)
1654 int regno = range & exp.X_add_number;
1657 regno = (1 << regno) - 1;
1659 (_("Warning: duplicated register (r%d) in register list"),
1663 range |= exp.X_add_number;
1667 if (inst.reloc.type != 0)
1669 inst.error = _("expression too complex");
1673 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1674 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1675 inst.reloc.pc_rel = 0;
1679 if (*str == '|' || *str == '+')
1685 while (another_range);
1691 /* Types of registers in a list. */
1700 /* Parse a VFP register list. If the string is invalid return FAIL.
1701 Otherwise return the number of registers, and set PBASE to the first
1702 register. Parses registers of type ETYPE.
1703 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1704 - Q registers can be used to specify pairs of D registers
1705 - { } can be omitted from around a singleton register list
1706 FIXME: This is not implemented, as it would require backtracking in
1709 This could be done (the meaning isn't really ambiguous), but doesn't
1710 fit in well with the current parsing framework.
1711 - 32 D registers may be used (also true for VFPv3).
1712 FIXME: Types are ignored in these register lists, which is probably a
1716 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1721 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1725 unsigned long mask = 0;
1730 inst.error = _("expecting {");
1739 regtype = REG_TYPE_VFS;
1744 regtype = REG_TYPE_VFD;
1747 case REGLIST_NEON_D:
1748 regtype = REG_TYPE_NDQ;
1752 if (etype != REGLIST_VFP_S)
1754 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1755 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1759 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1762 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1769 base_reg = max_regs;
1773 int setmask = 1, addregs = 1;
1775 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1777 if (new_base == FAIL)
1779 first_error (_(reg_expected_msgs[regtype]));
1783 if (new_base >= max_regs)
1785 first_error (_("register out of range in list"));
1789 /* Note: a value of 2 * n is returned for the register Q<n>. */
1790 if (regtype == REG_TYPE_NQ)
1796 if (new_base < base_reg)
1797 base_reg = new_base;
1799 if (mask & (setmask << new_base))
1801 first_error (_("invalid register list"));
1805 if ((mask >> new_base) != 0 && ! warned)
1807 as_tsktsk (_("register list not in ascending order"));
1811 mask |= setmask << new_base;
1814 if (*str == '-') /* We have the start of a range expression */
1820 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1823 inst.error = gettext (reg_expected_msgs[regtype]);
1827 if (high_range >= max_regs)
1829 first_error (_("register out of range in list"));
1833 if (regtype == REG_TYPE_NQ)
1834 high_range = high_range + 1;
1836 if (high_range <= new_base)
1838 inst.error = _("register range not in ascending order");
1842 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1844 if (mask & (setmask << new_base))
1846 inst.error = _("invalid register list");
1850 mask |= setmask << new_base;
1855 while (skip_past_comma (&str) != FAIL);
1859 /* Sanity check -- should have raised a parse error above. */
1860 if (count == 0 || count > max_regs)
1865 /* Final test -- the registers must be consecutive. */
1867 for (i = 0; i < count; i++)
1869 if ((mask & (1u << i)) == 0)
1871 inst.error = _("non-contiguous register range");
1881 /* True if two alias types are the same. */
1884 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1892 if (a->defined != b->defined)
1895 if ((a->defined & NTA_HASTYPE) != 0
1896 && (a->eltype.type != b->eltype.type
1897 || a->eltype.size != b->eltype.size))
1900 if ((a->defined & NTA_HASINDEX) != 0
1901 && (a->index != b->index))
1907 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1908 The base register is put in *PBASE.
1909 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1911 The register stride (minus one) is put in bit 4 of the return value.
1912 Bits [6:5] encode the list length (minus one).
1913 The type of the list elements is put in *ELTYPE, if non-NULL. */
1915 #define NEON_LANE(X) ((X) & 0xf)
1916 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1917 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1920 parse_neon_el_struct_list (char **str, unsigned *pbase,
1921 struct neon_type_el *eltype)
1928 int leading_brace = 0;
1929 enum arm_reg_type rtype = REG_TYPE_NDQ;
1930 const char *const incr_error = _("register stride must be 1 or 2");
1931 const char *const type_error = _("mismatched element/structure types in list");
1932 struct neon_typed_alias firsttype;
1934 if (skip_past_char (&ptr, '{') == SUCCESS)
1939 struct neon_typed_alias atype;
1940 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1944 first_error (_(reg_expected_msgs[rtype]));
1951 if (rtype == REG_TYPE_NQ)
1957 else if (reg_incr == -1)
1959 reg_incr = getreg - base_reg;
1960 if (reg_incr < 1 || reg_incr > 2)
1962 first_error (_(incr_error));
1966 else if (getreg != base_reg + reg_incr * count)
1968 first_error (_(incr_error));
1972 if (! neon_alias_types_same (&atype, &firsttype))
1974 first_error (_(type_error));
1978 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1982 struct neon_typed_alias htype;
1983 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1985 lane = NEON_INTERLEAVE_LANES;
1986 else if (lane != NEON_INTERLEAVE_LANES)
1988 first_error (_(type_error));
1993 else if (reg_incr != 1)
1995 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1999 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2002 first_error (_(reg_expected_msgs[rtype]));
2005 if (! neon_alias_types_same (&htype, &firsttype))
2007 first_error (_(type_error));
2010 count += hireg + dregs - getreg;
2014 /* If we're using Q registers, we can't use [] or [n] syntax. */
2015 if (rtype == REG_TYPE_NQ)
2021 if ((atype.defined & NTA_HASINDEX) != 0)
2025 else if (lane != atype.index)
2027 first_error (_(type_error));
2031 else if (lane == -1)
2032 lane = NEON_INTERLEAVE_LANES;
2033 else if (lane != NEON_INTERLEAVE_LANES)
2035 first_error (_(type_error));
2040 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2042 /* No lane set by [x]. We must be interleaving structures. */
2044 lane = NEON_INTERLEAVE_LANES;
2047 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2048 || (count > 1 && reg_incr == -1))
2050 first_error (_("error parsing element/structure list"));
2054 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2056 first_error (_("expected }"));
2064 *eltype = firsttype.eltype;
2069 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2072 /* Parse an explicit relocation suffix on an expression. This is
2073 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2074 arm_reloc_hsh contains no entries, so this function can only
2075 succeed if there is no () after the word. Returns -1 on error,
2076 BFD_RELOC_UNUSED if there wasn't any suffix. */
2079 parse_reloc (char **str)
2081 struct reloc_entry *r;
2085 return BFD_RELOC_UNUSED;
2090 while (*q && *q != ')' && *q != ',')
2095 if ((r = (struct reloc_entry *)
2096 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2103 /* Directives: register aliases. */
2105 static struct reg_entry *
2106 insert_reg_alias (char *str, unsigned number, int type)
2108 struct reg_entry *new_reg;
2111 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2113 if (new_reg->builtin)
2114 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2116 /* Only warn about a redefinition if it's not defined as the
2118 else if (new_reg->number != number || new_reg->type != type)
2119 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2124 name = xstrdup (str);
2125 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2127 new_reg->name = name;
2128 new_reg->number = number;
2129 new_reg->type = type;
2130 new_reg->builtin = FALSE;
2131 new_reg->neon = NULL;
2133 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2140 insert_neon_reg_alias (char *str, int number, int type,
2141 struct neon_typed_alias *atype)
2143 struct reg_entry *reg = insert_reg_alias (str, number, type);
2147 first_error (_("attempt to redefine typed alias"));
2153 reg->neon = (struct neon_typed_alias *)
2154 xmalloc (sizeof (struct neon_typed_alias));
2155 *reg->neon = *atype;
2159 /* Look for the .req directive. This is of the form:
2161 new_register_name .req existing_register_name
2163 If we find one, or if it looks sufficiently like one that we want to
2164 handle any error here, return TRUE. Otherwise return FALSE. */
2167 create_register_alias (char * newname, char *p)
2169 struct reg_entry *old;
2170 char *oldname, *nbuf;
2173 /* The input scrubber ensures that whitespace after the mnemonic is
2174 collapsed to single spaces. */
2176 if (strncmp (oldname, " .req ", 6) != 0)
2180 if (*oldname == '\0')
2183 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2186 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2190 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2191 the desired alias name, and p points to its end. If not, then
2192 the desired alias name is in the global original_case_string. */
2193 #ifdef TC_CASE_SENSITIVE
2196 newname = original_case_string;
2197 nlen = strlen (newname);
2200 nbuf = (char *) alloca (nlen + 1);
2201 memcpy (nbuf, newname, nlen);
2204 /* Create aliases under the new name as stated; an all-lowercase
2205 version of the new name; and an all-uppercase version of the new
2207 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2209 for (p = nbuf; *p; p++)
2212 if (strncmp (nbuf, newname, nlen))
2214 /* If this attempt to create an additional alias fails, do not bother
2215 trying to create the all-lower case alias. We will fail and issue
2216 a second, duplicate error message. This situation arises when the
2217 programmer does something like:
2220 The second .req creates the "Foo" alias but then fails to create
2221 the artificial FOO alias because it has already been created by the
2223 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2227 for (p = nbuf; *p; p++)
2230 if (strncmp (nbuf, newname, nlen))
2231 insert_reg_alias (nbuf, old->number, old->type);
2237 /* Create a Neon typed/indexed register alias using directives, e.g.:
2242 These typed registers can be used instead of the types specified after the
2243 Neon mnemonic, so long as all operands given have types. Types can also be
2244 specified directly, e.g.:
2245 vadd d0.s32, d1.s32, d2.s32 */
2248 create_neon_reg_alias (char *newname, char *p)
2250 enum arm_reg_type basetype;
2251 struct reg_entry *basereg;
2252 struct reg_entry mybasereg;
2253 struct neon_type ntype;
2254 struct neon_typed_alias typeinfo;
2255 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2258 typeinfo.defined = 0;
2259 typeinfo.eltype.type = NT_invtype;
2260 typeinfo.eltype.size = -1;
2261 typeinfo.index = -1;
2265 if (strncmp (p, " .dn ", 5) == 0)
2266 basetype = REG_TYPE_VFD;
2267 else if (strncmp (p, " .qn ", 5) == 0)
2268 basetype = REG_TYPE_NQ;
2277 basereg = arm_reg_parse_multi (&p);
2279 if (basereg && basereg->type != basetype)
2281 as_bad (_("bad type for register"));
2285 if (basereg == NULL)
2288 /* Try parsing as an integer. */
2289 my_get_expression (&exp, &p, GE_NO_PREFIX);
2290 if (exp.X_op != O_constant)
2292 as_bad (_("expression must be constant"));
2295 basereg = &mybasereg;
2296 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2302 typeinfo = *basereg->neon;
2304 if (parse_neon_type (&ntype, &p) == SUCCESS)
2306 /* We got a type. */
2307 if (typeinfo.defined & NTA_HASTYPE)
2309 as_bad (_("can't redefine the type of a register alias"));
2313 typeinfo.defined |= NTA_HASTYPE;
2314 if (ntype.elems != 1)
2316 as_bad (_("you must specify a single type only"));
2319 typeinfo.eltype = ntype.el[0];
2322 if (skip_past_char (&p, '[') == SUCCESS)
2325 /* We got a scalar index. */
2327 if (typeinfo.defined & NTA_HASINDEX)
2329 as_bad (_("can't redefine the index of a scalar alias"));
2333 my_get_expression (&exp, &p, GE_NO_PREFIX);
2335 if (exp.X_op != O_constant)
2337 as_bad (_("scalar index must be constant"));
2341 typeinfo.defined |= NTA_HASINDEX;
2342 typeinfo.index = exp.X_add_number;
2344 if (skip_past_char (&p, ']') == FAIL)
2346 as_bad (_("expecting ]"));
2351 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2352 the desired alias name, and p points to its end. If not, then
2353 the desired alias name is in the global original_case_string. */
2354 #ifdef TC_CASE_SENSITIVE
2355 namelen = nameend - newname;
2357 newname = original_case_string;
2358 namelen = strlen (newname);
2361 namebuf = (char *) alloca (namelen + 1);
2362 strncpy (namebuf, newname, namelen);
2363 namebuf[namelen] = '\0';
2365 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2366 typeinfo.defined != 0 ? &typeinfo : NULL);
2368 /* Insert name in all uppercase. */
2369 for (p = namebuf; *p; p++)
2372 if (strncmp (namebuf, newname, namelen))
2373 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2374 typeinfo.defined != 0 ? &typeinfo : NULL);
2376 /* Insert name in all lowercase. */
2377 for (p = namebuf; *p; p++)
2380 if (strncmp (namebuf, newname, namelen))
2381 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2382 typeinfo.defined != 0 ? &typeinfo : NULL);
2387 /* Should never be called, as .req goes between the alias and the
2388 register name, not at the beginning of the line. */
2391 s_req (int a ATTRIBUTE_UNUSED)
2393 as_bad (_("invalid syntax for .req directive"));
2397 s_dn (int a ATTRIBUTE_UNUSED)
2399 as_bad (_("invalid syntax for .dn directive"));
2403 s_qn (int a ATTRIBUTE_UNUSED)
2405 as_bad (_("invalid syntax for .qn directive"));
2408 /* The .unreq directive deletes an alias which was previously defined
2409 by .req. For example:
2415 s_unreq (int a ATTRIBUTE_UNUSED)
2420 name = input_line_pointer;
2422 while (*input_line_pointer != 0
2423 && *input_line_pointer != ' '
2424 && *input_line_pointer != '\n')
2425 ++input_line_pointer;
2427 saved_char = *input_line_pointer;
2428 *input_line_pointer = 0;
2431 as_bad (_("invalid syntax for .unreq directive"));
2434 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2438 as_bad (_("unknown register alias '%s'"), name);
2439 else if (reg->builtin)
2440 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2447 hash_delete (arm_reg_hsh, name, FALSE);
2448 free ((char *) reg->name);
2453 /* Also locate the all upper case and all lower case versions.
2454 Do not complain if we cannot find one or the other as it
2455 was probably deleted above. */
2457 nbuf = strdup (name);
2458 for (p = nbuf; *p; p++)
2460 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2463 hash_delete (arm_reg_hsh, nbuf, FALSE);
2464 free ((char *) reg->name);
2470 for (p = nbuf; *p; p++)
2472 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2475 hash_delete (arm_reg_hsh, nbuf, FALSE);
2476 free ((char *) reg->name);
2486 *input_line_pointer = saved_char;
2487 demand_empty_rest_of_line ();
2490 /* Directives: Instruction set selection. */
2493 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2494 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2495 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2496 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2498 /* Create a new mapping symbol for the transition to STATE. */
2501 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2504 const char * symname;
2511 type = BSF_NO_FLAGS;
2515 type = BSF_NO_FLAGS;
2519 type = BSF_NO_FLAGS;
2525 symbolP = symbol_new (symname, now_seg, value, frag);
2526 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2531 THUMB_SET_FUNC (symbolP, 0);
2532 ARM_SET_THUMB (symbolP, 0);
2533 ARM_SET_INTERWORK (symbolP, support_interwork);
2537 THUMB_SET_FUNC (symbolP, 1);
2538 ARM_SET_THUMB (symbolP, 1);
2539 ARM_SET_INTERWORK (symbolP, support_interwork);
2547 /* Save the mapping symbols for future reference. Also check that
2548 we do not place two mapping symbols at the same offset within a
2549 frag. We'll handle overlap between frags in
2550 check_mapping_symbols.
2552 If .fill or other data filling directive generates zero sized data,
2553 the mapping symbol for the following code will have the same value
2554 as the one generated for the data filling directive. In this case,
2555 we replace the old symbol with the new one at the same address. */
2558 if (frag->tc_frag_data.first_map != NULL)
2560 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2561 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2563 frag->tc_frag_data.first_map = symbolP;
2565 if (frag->tc_frag_data.last_map != NULL)
2567 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2568 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2569 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2571 frag->tc_frag_data.last_map = symbolP;
2574 /* We must sometimes convert a region marked as code to data during
2575 code alignment, if an odd number of bytes have to be padded. The
2576 code mapping symbol is pushed to an aligned address. */
2579 insert_data_mapping_symbol (enum mstate state,
2580 valueT value, fragS *frag, offsetT bytes)
2582 /* If there was already a mapping symbol, remove it. */
2583 if (frag->tc_frag_data.last_map != NULL
2584 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2586 symbolS *symp = frag->tc_frag_data.last_map;
2590 know (frag->tc_frag_data.first_map == symp);
2591 frag->tc_frag_data.first_map = NULL;
2593 frag->tc_frag_data.last_map = NULL;
2594 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2597 make_mapping_symbol (MAP_DATA, value, frag);
2598 make_mapping_symbol (state, value + bytes, frag);
2601 static void mapping_state_2 (enum mstate state, int max_chars);
2603 /* Set the mapping state to STATE. Only call this when about to
2604 emit some STATE bytes to the file. */
2607 mapping_state (enum mstate state)
2609 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2611 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2613 if (mapstate == state)
2614 /* The mapping symbol has already been emitted.
2615 There is nothing else to do. */
2618 if (state == MAP_ARM || state == MAP_THUMB)
2620 All ARM instructions require 4-byte alignment.
2621 (Almost) all Thumb instructions require 2-byte alignment.
2623 When emitting instructions into any section, mark the section
2626 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2627 but themselves require 2-byte alignment; this applies to some
2628 PC- relative forms. However, these cases will invovle implicit
2629 literal pool generation or an explicit .align >=2, both of
2630 which will cause the section to me marked with sufficient
2631 alignment. Thus, we don't handle those cases here. */
2632 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2634 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2635 /* This case will be evaluated later in the next else. */
2637 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2638 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2640 /* Only add the symbol if the offset is > 0:
2641 if we're at the first frag, check it's size > 0;
2642 if we're not at the first frag, then for sure
2643 the offset is > 0. */
2644 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2645 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2648 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2651 mapping_state_2 (state, 0);
2655 /* Same as mapping_state, but MAX_CHARS bytes have already been
2656 allocated. Put the mapping symbol that far back. */
2659 mapping_state_2 (enum mstate state, int max_chars)
2661 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2663 if (!SEG_NORMAL (now_seg))
2666 if (mapstate == state)
2667 /* The mapping symbol has already been emitted.
2668 There is nothing else to do. */
2671 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2672 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2675 #define mapping_state(x) ((void)0)
2676 #define mapping_state_2(x, y) ((void)0)
2679 /* Find the real, Thumb encoded start of a Thumb function. */
2683 find_real_start (symbolS * symbolP)
2686 const char * name = S_GET_NAME (symbolP);
2687 symbolS * new_target;
2689 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2690 #define STUB_NAME ".real_start_of"
2695 /* The compiler may generate BL instructions to local labels because
2696 it needs to perform a branch to a far away location. These labels
2697 do not have a corresponding ".real_start_of" label. We check
2698 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2699 the ".real_start_of" convention for nonlocal branches. */
2700 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2703 real_start = ACONCAT ((STUB_NAME, name, NULL));
2704 new_target = symbol_find (real_start);
2706 if (new_target == NULL)
2708 as_warn (_("Failed to find real start of function: %s\n"), name);
2709 new_target = symbolP;
2717 opcode_select (int width)
2724 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2725 as_bad (_("selected processor does not support THUMB opcodes"));
2728 /* No need to force the alignment, since we will have been
2729 coming from ARM mode, which is word-aligned. */
2730 record_alignment (now_seg, 1);
2737 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2738 as_bad (_("selected processor does not support ARM opcodes"));
2743 frag_align (2, 0, 0);
2745 record_alignment (now_seg, 1);
2750 as_bad (_("invalid instruction size selected (%d)"), width);
2755 s_arm (int ignore ATTRIBUTE_UNUSED)
2758 demand_empty_rest_of_line ();
2762 s_thumb (int ignore ATTRIBUTE_UNUSED)
2765 demand_empty_rest_of_line ();
2769 s_code (int unused ATTRIBUTE_UNUSED)
2773 temp = get_absolute_expression ();
2778 opcode_select (temp);
2782 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2787 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2789 /* If we are not already in thumb mode go into it, EVEN if
2790 the target processor does not support thumb instructions.
2791 This is used by gcc/config/arm/lib1funcs.asm for example
2792 to compile interworking support functions even if the
2793 target processor should not support interworking. */
2797 record_alignment (now_seg, 1);
2800 demand_empty_rest_of_line ();
2804 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2808 /* The following label is the name/address of the start of a Thumb function.
2809 We need to know this for the interworking support. */
2810 label_is_thumb_function_name = TRUE;
2813 /* Perform a .set directive, but also mark the alias as
2814 being a thumb function. */
2817 s_thumb_set (int equiv)
2819 /* XXX the following is a duplicate of the code for s_set() in read.c
2820 We cannot just call that code as we need to get at the symbol that
2827 /* Especial apologies for the random logic:
2828 This just grew, and could be parsed much more simply!
2830 name = input_line_pointer;
2831 delim = get_symbol_end ();
2832 end_name = input_line_pointer;
2835 if (*input_line_pointer != ',')
2838 as_bad (_("expected comma after name \"%s\""), name);
2840 ignore_rest_of_line ();
2844 input_line_pointer++;
2847 if (name[0] == '.' && name[1] == '\0')
2849 /* XXX - this should not happen to .thumb_set. */
2853 if ((symbolP = symbol_find (name)) == NULL
2854 && (symbolP = md_undefined_symbol (name)) == NULL)
2857 /* When doing symbol listings, play games with dummy fragments living
2858 outside the normal fragment chain to record the file and line info
2860 if (listing & LISTING_SYMBOLS)
2862 extern struct list_info_struct * listing_tail;
2863 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2865 memset (dummy_frag, 0, sizeof (fragS));
2866 dummy_frag->fr_type = rs_fill;
2867 dummy_frag->line = listing_tail;
2868 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2869 dummy_frag->fr_symbol = symbolP;
2873 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2876 /* "set" symbols are local unless otherwise specified. */
2877 SF_SET_LOCAL (symbolP);
2878 #endif /* OBJ_COFF */
2879 } /* Make a new symbol. */
2881 symbol_table_insert (symbolP);
2886 && S_IS_DEFINED (symbolP)
2887 && S_GET_SEGMENT (symbolP) != reg_section)
2888 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2890 pseudo_set (symbolP);
2892 demand_empty_rest_of_line ();
2894 /* XXX Now we come to the Thumb specific bit of code. */
2896 THUMB_SET_FUNC (symbolP, 1);
2897 ARM_SET_THUMB (symbolP, 1);
2898 #if defined OBJ_ELF || defined OBJ_COFF
2899 ARM_SET_INTERWORK (symbolP, support_interwork);
2903 /* Directives: Mode selection. */
2905 /* .syntax [unified|divided] - choose the new unified syntax
2906 (same for Arm and Thumb encoding, modulo slight differences in what
2907 can be represented) or the old divergent syntax for each mode. */
2909 s_syntax (int unused ATTRIBUTE_UNUSED)
2913 name = input_line_pointer;
2914 delim = get_symbol_end ();
2916 if (!strcasecmp (name, "unified"))
2917 unified_syntax = TRUE;
2918 else if (!strcasecmp (name, "divided"))
2919 unified_syntax = FALSE;
2922 as_bad (_("unrecognized syntax mode \"%s\""), name);
2925 *input_line_pointer = delim;
2926 demand_empty_rest_of_line ();
2929 /* Directives: sectioning and alignment. */
2931 /* Same as s_align_ptwo but align 0 => align 2. */
2934 s_align (int unused ATTRIBUTE_UNUSED)
2939 long max_alignment = 15;
2941 temp = get_absolute_expression ();
2942 if (temp > max_alignment)
2943 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2946 as_bad (_("alignment negative. 0 assumed."));
2950 if (*input_line_pointer == ',')
2952 input_line_pointer++;
2953 temp_fill = get_absolute_expression ();
2965 /* Only make a frag if we HAVE to. */
2966 if (temp && !need_pass_2)
2968 if (!fill_p && subseg_text_p (now_seg))
2969 frag_align_code (temp, 0);
2971 frag_align (temp, (int) temp_fill, 0);
2973 demand_empty_rest_of_line ();
2975 record_alignment (now_seg, temp);
2979 s_bss (int ignore ATTRIBUTE_UNUSED)
2981 /* We don't support putting frags in the BSS segment, we fake it by
2982 marking in_bss, then looking at s_skip for clues. */
2983 subseg_set (bss_section, 0);
2984 demand_empty_rest_of_line ();
2986 #ifdef md_elf_section_change_hook
2987 md_elf_section_change_hook ();
2992 s_even (int ignore ATTRIBUTE_UNUSED)
2994 /* Never make frag if expect extra pass. */
2996 frag_align (1, 0, 0);
2998 record_alignment (now_seg, 1);
3000 demand_empty_rest_of_line ();
3003 /* Directives: Literal pools. */
3005 static literal_pool *
3006 find_literal_pool (void)
3008 literal_pool * pool;
3010 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3012 if (pool->section == now_seg
3013 && pool->sub_section == now_subseg)
3020 static literal_pool *
3021 find_or_make_literal_pool (void)
3023 /* Next literal pool ID number. */
3024 static unsigned int latest_pool_num = 1;
3025 literal_pool * pool;
3027 pool = find_literal_pool ();
3031 /* Create a new pool. */
3032 pool = (literal_pool *) xmalloc (sizeof (* pool));
3036 pool->next_free_entry = 0;
3037 pool->section = now_seg;
3038 pool->sub_section = now_subseg;
3039 pool->next = list_of_pools;
3040 pool->symbol = NULL;
3042 /* Add it to the list. */
3043 list_of_pools = pool;
3046 /* New pools, and emptied pools, will have a NULL symbol. */
3047 if (pool->symbol == NULL)
3049 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3050 (valueT) 0, &zero_address_frag);
3051 pool->id = latest_pool_num ++;
3058 /* Add the literal in the global 'inst'
3059 structure to the relevant literal pool. */
3062 add_to_lit_pool (void)
3064 literal_pool * pool;
3067 pool = find_or_make_literal_pool ();
3069 /* Check if this literal value is already in the pool. */
3070 for (entry = 0; entry < pool->next_free_entry; entry ++)
3072 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3073 && (inst.reloc.exp.X_op == O_constant)
3074 && (pool->literals[entry].X_add_number
3075 == inst.reloc.exp.X_add_number)
3076 && (pool->literals[entry].X_unsigned
3077 == inst.reloc.exp.X_unsigned))
3080 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3081 && (inst.reloc.exp.X_op == O_symbol)
3082 && (pool->literals[entry].X_add_number
3083 == inst.reloc.exp.X_add_number)
3084 && (pool->literals[entry].X_add_symbol
3085 == inst.reloc.exp.X_add_symbol)
3086 && (pool->literals[entry].X_op_symbol
3087 == inst.reloc.exp.X_op_symbol))
3091 /* Do we need to create a new entry? */
3092 if (entry == pool->next_free_entry)
3094 if (entry >= MAX_LITERAL_POOL_SIZE)
3096 inst.error = _("literal pool overflow");
3100 pool->literals[entry] = inst.reloc.exp;
3102 /* PR ld/12974: Record the location of the first source line to reference
3103 this entry in the literal pool. If it turns out during linking that the
3104 symbol does not exist we will be able to give an accurate line number for
3105 the (first use of the) missing reference. */
3106 if (debug_type == DEBUG_DWARF2)
3107 dwarf2_where (pool->locs + entry);
3109 pool->next_free_entry += 1;
3112 inst.reloc.exp.X_op = O_symbol;
3113 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3114 inst.reloc.exp.X_add_symbol = pool->symbol;
3119 /* Can't use symbol_new here, so have to create a symbol and then at
3120 a later date assign it a value. Thats what these functions do. */
3123 symbol_locate (symbolS * symbolP,
3124 const char * name, /* It is copied, the caller can modify. */
3125 segT segment, /* Segment identifier (SEG_<something>). */
3126 valueT valu, /* Symbol value. */
3127 fragS * frag) /* Associated fragment. */
3129 unsigned int name_length;
3130 char * preserved_copy_of_name;
3132 name_length = strlen (name) + 1; /* +1 for \0. */
3133 obstack_grow (¬es, name, name_length);
3134 preserved_copy_of_name = (char *) obstack_finish (¬es);
3136 #ifdef tc_canonicalize_symbol_name
3137 preserved_copy_of_name =
3138 tc_canonicalize_symbol_name (preserved_copy_of_name);
3141 S_SET_NAME (symbolP, preserved_copy_of_name);
3143 S_SET_SEGMENT (symbolP, segment);
3144 S_SET_VALUE (symbolP, valu);
3145 symbol_clear_list_pointers (symbolP);
3147 symbol_set_frag (symbolP, frag);
3149 /* Link to end of symbol chain. */
3151 extern int symbol_table_frozen;
3153 if (symbol_table_frozen)
3157 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3159 obj_symbol_new_hook (symbolP);
3161 #ifdef tc_symbol_new_hook
3162 tc_symbol_new_hook (symbolP);
3166 verify_symbol_chain (symbol_rootP, symbol_lastP);
3167 #endif /* DEBUG_SYMS */
3172 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3175 literal_pool * pool;
3178 pool = find_literal_pool ();
3180 || pool->symbol == NULL
3181 || pool->next_free_entry == 0)
3184 mapping_state (MAP_DATA);
3186 /* Align pool as you have word accesses.
3187 Only make a frag if we have to. */
3189 frag_align (2, 0, 0);
3191 record_alignment (now_seg, 2);
3193 sprintf (sym_name, "$$lit_\002%x", pool->id);
3195 symbol_locate (pool->symbol, sym_name, now_seg,
3196 (valueT) frag_now_fix (), frag_now);
3197 symbol_table_insert (pool->symbol);
3199 ARM_SET_THUMB (pool->symbol, thumb_mode);
3201 #if defined OBJ_COFF || defined OBJ_ELF
3202 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3205 for (entry = 0; entry < pool->next_free_entry; entry ++)
3208 if (debug_type == DEBUG_DWARF2)
3209 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3211 /* First output the expression in the instruction to the pool. */
3212 emit_expr (&(pool->literals[entry]), 4); /* .word */
3215 /* Mark the pool as empty. */
3216 pool->next_free_entry = 0;
3217 pool->symbol = NULL;
3221 /* Forward declarations for functions below, in the MD interface
3223 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3224 static valueT create_unwind_entry (int);
3225 static void start_unwind_section (const segT, int);
3226 static void add_unwind_opcode (valueT, int);
3227 static void flush_pending_unwind (void);
3229 /* Directives: Data. */
3232 s_arm_elf_cons (int nbytes)
3236 #ifdef md_flush_pending_output
3237 md_flush_pending_output ();
3240 if (is_it_end_of_statement ())
3242 demand_empty_rest_of_line ();
3246 #ifdef md_cons_align
3247 md_cons_align (nbytes);
3250 mapping_state (MAP_DATA);
3254 char *base = input_line_pointer;
3258 if (exp.X_op != O_symbol)
3259 emit_expr (&exp, (unsigned int) nbytes);
3262 char *before_reloc = input_line_pointer;
3263 reloc = parse_reloc (&input_line_pointer);
3266 as_bad (_("unrecognized relocation suffix"));
3267 ignore_rest_of_line ();
3270 else if (reloc == BFD_RELOC_UNUSED)
3271 emit_expr (&exp, (unsigned int) nbytes);
3274 reloc_howto_type *howto = (reloc_howto_type *)
3275 bfd_reloc_type_lookup (stdoutput,
3276 (bfd_reloc_code_real_type) reloc);
3277 int size = bfd_get_reloc_size (howto);
3279 if (reloc == BFD_RELOC_ARM_PLT32)
3281 as_bad (_("(plt) is only valid on branch targets"));
3282 reloc = BFD_RELOC_UNUSED;
3287 as_bad (_("%s relocations do not fit in %d bytes"),
3288 howto->name, nbytes);
3291 /* We've parsed an expression stopping at O_symbol.
3292 But there may be more expression left now that we
3293 have parsed the relocation marker. Parse it again.
3294 XXX Surely there is a cleaner way to do this. */
3295 char *p = input_line_pointer;
3297 char *save_buf = (char *) alloca (input_line_pointer - base);
3298 memcpy (save_buf, base, input_line_pointer - base);
3299 memmove (base + (input_line_pointer - before_reloc),
3300 base, before_reloc - base);
3302 input_line_pointer = base + (input_line_pointer-before_reloc);
3304 memcpy (base, save_buf, p - base);
3306 offset = nbytes - size;
3307 p = frag_more ((int) nbytes);
3308 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3309 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3314 while (*input_line_pointer++ == ',');
3316 /* Put terminator back into stream. */
3317 input_line_pointer --;
3318 demand_empty_rest_of_line ();
3321 /* Emit an expression containing a 32-bit thumb instruction.
3322 Implementation based on put_thumb32_insn. */
3325 emit_thumb32_expr (expressionS * exp)
3327 expressionS exp_high = *exp;
3329 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3330 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3331 exp->X_add_number &= 0xffff;
3332 emit_expr (exp, (unsigned int) THUMB_SIZE);
3335 /* Guess the instruction size based on the opcode. */
3338 thumb_insn_size (int opcode)
3340 if ((unsigned int) opcode < 0xe800u)
3342 else if ((unsigned int) opcode >= 0xe8000000u)
3349 emit_insn (expressionS *exp, int nbytes)
3353 if (exp->X_op == O_constant)
3358 size = thumb_insn_size (exp->X_add_number);
3362 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3364 as_bad (_(".inst.n operand too big. "\
3365 "Use .inst.w instead"));
3370 if (now_it.state == AUTOMATIC_IT_BLOCK)
3371 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3373 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3375 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3376 emit_thumb32_expr (exp);
3378 emit_expr (exp, (unsigned int) size);
3380 it_fsm_post_encode ();
3384 as_bad (_("cannot determine Thumb instruction size. " \
3385 "Use .inst.n/.inst.w instead"));
3388 as_bad (_("constant expression required"));
3393 /* Like s_arm_elf_cons but do not use md_cons_align and
3394 set the mapping state to MAP_ARM/MAP_THUMB. */
3397 s_arm_elf_inst (int nbytes)
3399 if (is_it_end_of_statement ())
3401 demand_empty_rest_of_line ();
3405 /* Calling mapping_state () here will not change ARM/THUMB,
3406 but will ensure not to be in DATA state. */
3409 mapping_state (MAP_THUMB);
3414 as_bad (_("width suffixes are invalid in ARM mode"));
3415 ignore_rest_of_line ();
3421 mapping_state (MAP_ARM);
3430 if (! emit_insn (& exp, nbytes))
3432 ignore_rest_of_line ();
3436 while (*input_line_pointer++ == ',');
3438 /* Put terminator back into stream. */
3439 input_line_pointer --;
3440 demand_empty_rest_of_line ();
3443 /* Parse a .rel31 directive. */
3446 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3453 if (*input_line_pointer == '1')
3454 highbit = 0x80000000;
3455 else if (*input_line_pointer != '0')
3456 as_bad (_("expected 0 or 1"));
3458 input_line_pointer++;
3459 if (*input_line_pointer != ',')
3460 as_bad (_("missing comma"));
3461 input_line_pointer++;
3463 #ifdef md_flush_pending_output
3464 md_flush_pending_output ();
3467 #ifdef md_cons_align
3471 mapping_state (MAP_DATA);
3476 md_number_to_chars (p, highbit, 4);
3477 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3478 BFD_RELOC_ARM_PREL31);
3480 demand_empty_rest_of_line ();
3483 /* Directives: AEABI stack-unwind tables. */
3485 /* Parse an unwind_fnstart directive. Simply records the current location. */
3488 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3490 demand_empty_rest_of_line ();
3491 if (unwind.proc_start)
3493 as_bad (_("duplicate .fnstart directive"));
3497 /* Mark the start of the function. */
3498 unwind.proc_start = expr_build_dot ();
3500 /* Reset the rest of the unwind info. */
3501 unwind.opcode_count = 0;
3502 unwind.table_entry = NULL;
3503 unwind.personality_routine = NULL;
3504 unwind.personality_index = -1;
3505 unwind.frame_size = 0;
3506 unwind.fp_offset = 0;
3507 unwind.fp_reg = REG_SP;
3509 unwind.sp_restored = 0;
3513 /* Parse a handlerdata directive. Creates the exception handling table entry
3514 for the function. */
3517 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3519 demand_empty_rest_of_line ();
3520 if (!unwind.proc_start)
3521 as_bad (MISSING_FNSTART);
3523 if (unwind.table_entry)
3524 as_bad (_("duplicate .handlerdata directive"));
3526 create_unwind_entry (1);
3529 /* Parse an unwind_fnend directive. Generates the index table entry. */
3532 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3537 unsigned int marked_pr_dependency;
3539 demand_empty_rest_of_line ();
3541 if (!unwind.proc_start)
3543 as_bad (_(".fnend directive without .fnstart"));
3547 /* Add eh table entry. */
3548 if (unwind.table_entry == NULL)
3549 val = create_unwind_entry (0);
3553 /* Add index table entry. This is two words. */
3554 start_unwind_section (unwind.saved_seg, 1);
3555 frag_align (2, 0, 0);
3556 record_alignment (now_seg, 2);
3558 ptr = frag_more (8);
3560 where = frag_now_fix () - 8;
3562 /* Self relative offset of the function start. */
3563 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3564 BFD_RELOC_ARM_PREL31);
3566 /* Indicate dependency on EHABI-defined personality routines to the
3567 linker, if it hasn't been done already. */
3568 marked_pr_dependency
3569 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3570 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3571 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3573 static const char *const name[] =
3575 "__aeabi_unwind_cpp_pr0",
3576 "__aeabi_unwind_cpp_pr1",
3577 "__aeabi_unwind_cpp_pr2"
3579 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3580 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3581 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3582 |= 1 << unwind.personality_index;
3586 /* Inline exception table entry. */
3587 md_number_to_chars (ptr + 4, val, 4);
3589 /* Self relative offset of the table entry. */
3590 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3591 BFD_RELOC_ARM_PREL31);
3593 /* Restore the original section. */
3594 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3596 unwind.proc_start = NULL;
3600 /* Parse an unwind_cantunwind directive. */
3603 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3605 demand_empty_rest_of_line ();
3606 if (!unwind.proc_start)
3607 as_bad (MISSING_FNSTART);
3609 if (unwind.personality_routine || unwind.personality_index != -1)
3610 as_bad (_("personality routine specified for cantunwind frame"));
3612 unwind.personality_index = -2;
3616 /* Parse a personalityindex directive. */
3619 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3623 if (!unwind.proc_start)
3624 as_bad (MISSING_FNSTART);
3626 if (unwind.personality_routine || unwind.personality_index != -1)
3627 as_bad (_("duplicate .personalityindex directive"));
3631 if (exp.X_op != O_constant
3632 || exp.X_add_number < 0 || exp.X_add_number > 15)
3634 as_bad (_("bad personality routine number"));
3635 ignore_rest_of_line ();
3639 unwind.personality_index = exp.X_add_number;
3641 demand_empty_rest_of_line ();
3645 /* Parse a personality directive. */
3648 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3652 if (!unwind.proc_start)
3653 as_bad (MISSING_FNSTART);
3655 if (unwind.personality_routine || unwind.personality_index != -1)
3656 as_bad (_("duplicate .personality directive"));
3658 name = input_line_pointer;
3659 c = get_symbol_end ();
3660 p = input_line_pointer;
3661 unwind.personality_routine = symbol_find_or_make (name);
3663 demand_empty_rest_of_line ();
3667 /* Parse a directive saving core registers. */
3670 s_arm_unwind_save_core (void)
3676 range = parse_reg_list (&input_line_pointer);
3679 as_bad (_("expected register list"));
3680 ignore_rest_of_line ();
3684 demand_empty_rest_of_line ();
3686 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3687 into .unwind_save {..., sp...}. We aren't bothered about the value of
3688 ip because it is clobbered by calls. */
3689 if (unwind.sp_restored && unwind.fp_reg == 12
3690 && (range & 0x3000) == 0x1000)
3692 unwind.opcode_count--;
3693 unwind.sp_restored = 0;
3694 range = (range | 0x2000) & ~0x1000;
3695 unwind.pending_offset = 0;
3701 /* See if we can use the short opcodes. These pop a block of up to 8
3702 registers starting with r4, plus maybe r14. */
3703 for (n = 0; n < 8; n++)
3705 /* Break at the first non-saved register. */
3706 if ((range & (1 << (n + 4))) == 0)
3709 /* See if there are any other bits set. */
3710 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3712 /* Use the long form. */
3713 op = 0x8000 | ((range >> 4) & 0xfff);
3714 add_unwind_opcode (op, 2);
3718 /* Use the short form. */
3720 op = 0xa8; /* Pop r14. */
3722 op = 0xa0; /* Do not pop r14. */
3724 add_unwind_opcode (op, 1);
3731 op = 0xb100 | (range & 0xf);
3732 add_unwind_opcode (op, 2);
3735 /* Record the number of bytes pushed. */
3736 for (n = 0; n < 16; n++)
3738 if (range & (1 << n))
3739 unwind.frame_size += 4;
3744 /* Parse a directive saving FPA registers. */
3747 s_arm_unwind_save_fpa (int reg)
3753 /* Get Number of registers to transfer. */
3754 if (skip_past_comma (&input_line_pointer) != FAIL)
3757 exp.X_op = O_illegal;
3759 if (exp.X_op != O_constant)
3761 as_bad (_("expected , <constant>"));
3762 ignore_rest_of_line ();
3766 num_regs = exp.X_add_number;
3768 if (num_regs < 1 || num_regs > 4)
3770 as_bad (_("number of registers must be in the range [1:4]"));
3771 ignore_rest_of_line ();
3775 demand_empty_rest_of_line ();
3780 op = 0xb4 | (num_regs - 1);
3781 add_unwind_opcode (op, 1);
3786 op = 0xc800 | (reg << 4) | (num_regs - 1);
3787 add_unwind_opcode (op, 2);
3789 unwind.frame_size += num_regs * 12;
3793 /* Parse a directive saving VFP registers for ARMv6 and above. */
3796 s_arm_unwind_save_vfp_armv6 (void)
3801 int num_vfpv3_regs = 0;
3802 int num_regs_below_16;
3804 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3807 as_bad (_("expected register list"));
3808 ignore_rest_of_line ();
3812 demand_empty_rest_of_line ();
3814 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3815 than FSTMX/FLDMX-style ones). */
3817 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3819 num_vfpv3_regs = count;
3820 else if (start + count > 16)
3821 num_vfpv3_regs = start + count - 16;
3823 if (num_vfpv3_regs > 0)
3825 int start_offset = start > 16 ? start - 16 : 0;
3826 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3827 add_unwind_opcode (op, 2);
3830 /* Generate opcode for registers numbered in the range 0 .. 15. */
3831 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3832 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3833 if (num_regs_below_16 > 0)
3835 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3836 add_unwind_opcode (op, 2);
3839 unwind.frame_size += count * 8;
3843 /* Parse a directive saving VFP registers for pre-ARMv6. */
3846 s_arm_unwind_save_vfp (void)
3852 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3855 as_bad (_("expected register list"));
3856 ignore_rest_of_line ();
3860 demand_empty_rest_of_line ();
3865 op = 0xb8 | (count - 1);
3866 add_unwind_opcode (op, 1);
3871 op = 0xb300 | (reg << 4) | (count - 1);
3872 add_unwind_opcode (op, 2);
3874 unwind.frame_size += count * 8 + 4;
3878 /* Parse a directive saving iWMMXt data registers. */
3881 s_arm_unwind_save_mmxwr (void)
3889 if (*input_line_pointer == '{')
3890 input_line_pointer++;
3894 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3898 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3903 as_tsktsk (_("register list not in ascending order"));
3906 if (*input_line_pointer == '-')
3908 input_line_pointer++;
3909 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3912 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3915 else if (reg >= hi_reg)
3917 as_bad (_("bad register range"));
3920 for (; reg < hi_reg; reg++)
3924 while (skip_past_comma (&input_line_pointer) != FAIL);
3926 if (*input_line_pointer == '}')
3927 input_line_pointer++;
3929 demand_empty_rest_of_line ();
3931 /* Generate any deferred opcodes because we're going to be looking at
3933 flush_pending_unwind ();
3935 for (i = 0; i < 16; i++)
3937 if (mask & (1 << i))
3938 unwind.frame_size += 8;
3941 /* Attempt to combine with a previous opcode. We do this because gcc
3942 likes to output separate unwind directives for a single block of
3944 if (unwind.opcode_count > 0)
3946 i = unwind.opcodes[unwind.opcode_count - 1];
3947 if ((i & 0xf8) == 0xc0)
3950 /* Only merge if the blocks are contiguous. */
3953 if ((mask & 0xfe00) == (1 << 9))
3955 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3956 unwind.opcode_count--;
3959 else if (i == 6 && unwind.opcode_count >= 2)
3961 i = unwind.opcodes[unwind.opcode_count - 2];
3965 op = 0xffff << (reg - 1);
3967 && ((mask & op) == (1u << (reg - 1))))
3969 op = (1 << (reg + i + 1)) - 1;
3970 op &= ~((1 << reg) - 1);
3972 unwind.opcode_count -= 2;
3979 /* We want to generate opcodes in the order the registers have been
3980 saved, ie. descending order. */
3981 for (reg = 15; reg >= -1; reg--)
3983 /* Save registers in blocks. */
3985 || !(mask & (1 << reg)))
3987 /* We found an unsaved reg. Generate opcodes to save the
3994 op = 0xc0 | (hi_reg - 10);
3995 add_unwind_opcode (op, 1);
4000 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4001 add_unwind_opcode (op, 2);
4010 ignore_rest_of_line ();
4014 s_arm_unwind_save_mmxwcg (void)
4021 if (*input_line_pointer == '{')
4022 input_line_pointer++;
4026 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4030 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4036 as_tsktsk (_("register list not in ascending order"));
4039 if (*input_line_pointer == '-')
4041 input_line_pointer++;
4042 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4045 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4048 else if (reg >= hi_reg)
4050 as_bad (_("bad register range"));
4053 for (; reg < hi_reg; reg++)
4057 while (skip_past_comma (&input_line_pointer) != FAIL);
4059 if (*input_line_pointer == '}')
4060 input_line_pointer++;
4062 demand_empty_rest_of_line ();
4064 /* Generate any deferred opcodes because we're going to be looking at
4066 flush_pending_unwind ();
4068 for (reg = 0; reg < 16; reg++)
4070 if (mask & (1 << reg))
4071 unwind.frame_size += 4;
4074 add_unwind_opcode (op, 2);
4077 ignore_rest_of_line ();
4081 /* Parse an unwind_save directive.
4082 If the argument is non-zero, this is a .vsave directive. */
4085 s_arm_unwind_save (int arch_v6)
4088 struct reg_entry *reg;
4089 bfd_boolean had_brace = FALSE;
4091 if (!unwind.proc_start)
4092 as_bad (MISSING_FNSTART);
4094 /* Figure out what sort of save we have. */
4095 peek = input_line_pointer;
4103 reg = arm_reg_parse_multi (&peek);
4107 as_bad (_("register expected"));
4108 ignore_rest_of_line ();
4117 as_bad (_("FPA .unwind_save does not take a register list"));
4118 ignore_rest_of_line ();
4121 input_line_pointer = peek;
4122 s_arm_unwind_save_fpa (reg->number);
4125 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4128 s_arm_unwind_save_vfp_armv6 ();
4130 s_arm_unwind_save_vfp ();
4132 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4133 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4136 as_bad (_(".unwind_save does not support this kind of register"));
4137 ignore_rest_of_line ();
4142 /* Parse an unwind_movsp directive. */
4145 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4151 if (!unwind.proc_start)
4152 as_bad (MISSING_FNSTART);
4154 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4157 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4158 ignore_rest_of_line ();
4162 /* Optional constant. */
4163 if (skip_past_comma (&input_line_pointer) != FAIL)
4165 if (immediate_for_directive (&offset) == FAIL)
4171 demand_empty_rest_of_line ();
4173 if (reg == REG_SP || reg == REG_PC)
4175 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4179 if (unwind.fp_reg != REG_SP)
4180 as_bad (_("unexpected .unwind_movsp directive"));
4182 /* Generate opcode to restore the value. */
4184 add_unwind_opcode (op, 1);
4186 /* Record the information for later. */
4187 unwind.fp_reg = reg;
4188 unwind.fp_offset = unwind.frame_size - offset;
4189 unwind.sp_restored = 1;
4192 /* Parse an unwind_pad directive. */
4195 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4199 if (!unwind.proc_start)
4200 as_bad (MISSING_FNSTART);
4202 if (immediate_for_directive (&offset) == FAIL)
4207 as_bad (_("stack increment must be multiple of 4"));
4208 ignore_rest_of_line ();
4212 /* Don't generate any opcodes, just record the details for later. */
4213 unwind.frame_size += offset;
4214 unwind.pending_offset += offset;
4216 demand_empty_rest_of_line ();
4219 /* Parse an unwind_setfp directive. */
4222 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4228 if (!unwind.proc_start)
4229 as_bad (MISSING_FNSTART);
4231 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4232 if (skip_past_comma (&input_line_pointer) == FAIL)
4235 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4237 if (fp_reg == FAIL || sp_reg == FAIL)
4239 as_bad (_("expected <reg>, <reg>"));
4240 ignore_rest_of_line ();
4244 /* Optional constant. */
4245 if (skip_past_comma (&input_line_pointer) != FAIL)
4247 if (immediate_for_directive (&offset) == FAIL)
4253 demand_empty_rest_of_line ();
4255 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4257 as_bad (_("register must be either sp or set by a previous"
4258 "unwind_movsp directive"));
4262 /* Don't generate any opcodes, just record the information for later. */
4263 unwind.fp_reg = fp_reg;
4265 if (sp_reg == REG_SP)
4266 unwind.fp_offset = unwind.frame_size - offset;
4268 unwind.fp_offset -= offset;
4271 /* Parse an unwind_raw directive. */
4274 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4277 /* This is an arbitrary limit. */
4278 unsigned char op[16];
4281 if (!unwind.proc_start)
4282 as_bad (MISSING_FNSTART);
4285 if (exp.X_op == O_constant
4286 && skip_past_comma (&input_line_pointer) != FAIL)
4288 unwind.frame_size += exp.X_add_number;
4292 exp.X_op = O_illegal;
4294 if (exp.X_op != O_constant)
4296 as_bad (_("expected <offset>, <opcode>"));
4297 ignore_rest_of_line ();
4303 /* Parse the opcode. */
4308 as_bad (_("unwind opcode too long"));
4309 ignore_rest_of_line ();
4311 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4313 as_bad (_("invalid unwind opcode"));
4314 ignore_rest_of_line ();
4317 op[count++] = exp.X_add_number;
4319 /* Parse the next byte. */
4320 if (skip_past_comma (&input_line_pointer) == FAIL)
4326 /* Add the opcode bytes in reverse order. */
4328 add_unwind_opcode (op[count], 1);
4330 demand_empty_rest_of_line ();
4334 /* Parse a .eabi_attribute directive. */
4337 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4339 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4341 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4342 attributes_set_explicitly[tag] = 1;
4345 /* Emit a tls fix for the symbol. */
4348 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4352 #ifdef md_flush_pending_output
4353 md_flush_pending_output ();
4356 #ifdef md_cons_align
4360 /* Since we're just labelling the code, there's no need to define a
4363 p = obstack_next_free (&frchain_now->frch_obstack);
4364 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4365 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4366 : BFD_RELOC_ARM_TLS_DESCSEQ);
4368 #endif /* OBJ_ELF */
4370 static void s_arm_arch (int);
4371 static void s_arm_object_arch (int);
4372 static void s_arm_cpu (int);
4373 static void s_arm_fpu (int);
4374 static void s_arm_arch_extension (int);
4379 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4386 if (exp.X_op == O_symbol)
4387 exp.X_op = O_secrel;
4389 emit_expr (&exp, 4);
4391 while (*input_line_pointer++ == ',');
4393 input_line_pointer--;
4394 demand_empty_rest_of_line ();
4398 /* This table describes all the machine specific pseudo-ops the assembler
4399 has to support. The fields are:
4400 pseudo-op name without dot
4401 function to call to execute this pseudo-op
4402 Integer arg to pass to the function. */
4404 const pseudo_typeS md_pseudo_table[] =
4406 /* Never called because '.req' does not start a line. */
4407 { "req", s_req, 0 },
4408 /* Following two are likewise never called. */
4411 { "unreq", s_unreq, 0 },
4412 { "bss", s_bss, 0 },
4413 { "align", s_align, 0 },
4414 { "arm", s_arm, 0 },
4415 { "thumb", s_thumb, 0 },
4416 { "code", s_code, 0 },
4417 { "force_thumb", s_force_thumb, 0 },
4418 { "thumb_func", s_thumb_func, 0 },
4419 { "thumb_set", s_thumb_set, 0 },
4420 { "even", s_even, 0 },
4421 { "ltorg", s_ltorg, 0 },
4422 { "pool", s_ltorg, 0 },
4423 { "syntax", s_syntax, 0 },
4424 { "cpu", s_arm_cpu, 0 },
4425 { "arch", s_arm_arch, 0 },
4426 { "object_arch", s_arm_object_arch, 0 },
4427 { "fpu", s_arm_fpu, 0 },
4428 { "arch_extension", s_arm_arch_extension, 0 },
4430 { "word", s_arm_elf_cons, 4 },
4431 { "long", s_arm_elf_cons, 4 },
4432 { "inst.n", s_arm_elf_inst, 2 },
4433 { "inst.w", s_arm_elf_inst, 4 },
4434 { "inst", s_arm_elf_inst, 0 },
4435 { "rel31", s_arm_rel31, 0 },
4436 { "fnstart", s_arm_unwind_fnstart, 0 },
4437 { "fnend", s_arm_unwind_fnend, 0 },
4438 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4439 { "personality", s_arm_unwind_personality, 0 },
4440 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4441 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4442 { "save", s_arm_unwind_save, 0 },
4443 { "vsave", s_arm_unwind_save, 1 },
4444 { "movsp", s_arm_unwind_movsp, 0 },
4445 { "pad", s_arm_unwind_pad, 0 },
4446 { "setfp", s_arm_unwind_setfp, 0 },
4447 { "unwind_raw", s_arm_unwind_raw, 0 },
4448 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4449 { "tlsdescseq", s_arm_tls_descseq, 0 },
4453 /* These are used for dwarf. */
4457 /* These are used for dwarf2. */
4458 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4459 { "loc", dwarf2_directive_loc, 0 },
4460 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4462 { "extend", float_cons, 'x' },
4463 { "ldouble", float_cons, 'x' },
4464 { "packed", float_cons, 'p' },
4466 {"secrel32", pe_directive_secrel, 0},
4471 /* Parser functions used exclusively in instruction operands. */
4473 /* Generic immediate-value read function for use in insn parsing.
4474 STR points to the beginning of the immediate (the leading #);
4475 VAL receives the value; if the value is outside [MIN, MAX]
4476 issue an error. PREFIX_OPT is true if the immediate prefix is
4480 parse_immediate (char **str, int *val, int min, int max,
4481 bfd_boolean prefix_opt)
4484 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4485 if (exp.X_op != O_constant)
4487 inst.error = _("constant expression required");
4491 if (exp.X_add_number < min || exp.X_add_number > max)
4493 inst.error = _("immediate value out of range");
4497 *val = exp.X_add_number;
4501 /* Less-generic immediate-value read function with the possibility of loading a
4502 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4503 instructions. Puts the result directly in inst.operands[i]. */
4506 parse_big_immediate (char **str, int i)
4511 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4513 if (exp.X_op == O_constant)
4515 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4516 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4517 O_constant. We have to be careful not to break compilation for
4518 32-bit X_add_number, though. */
4519 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4521 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4522 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4523 inst.operands[i].regisimm = 1;
4526 else if (exp.X_op == O_big
4527 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4529 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4531 /* Bignums have their least significant bits in
4532 generic_bignum[0]. Make sure we put 32 bits in imm and
4533 32 bits in reg, in a (hopefully) portable way. */
4534 gas_assert (parts != 0);
4536 /* Make sure that the number is not too big.
4537 PR 11972: Bignums can now be sign-extended to the
4538 size of a .octa so check that the out of range bits
4539 are all zero or all one. */
4540 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4542 LITTLENUM_TYPE m = -1;
4544 if (generic_bignum[parts * 2] != 0
4545 && generic_bignum[parts * 2] != m)
4548 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4549 if (generic_bignum[j] != generic_bignum[j-1])
4553 inst.operands[i].imm = 0;
4554 for (j = 0; j < parts; j++, idx++)
4555 inst.operands[i].imm |= generic_bignum[idx]
4556 << (LITTLENUM_NUMBER_OF_BITS * j);
4557 inst.operands[i].reg = 0;
4558 for (j = 0; j < parts; j++, idx++)
4559 inst.operands[i].reg |= generic_bignum[idx]
4560 << (LITTLENUM_NUMBER_OF_BITS * j);
4561 inst.operands[i].regisimm = 1;
4571 /* Returns the pseudo-register number of an FPA immediate constant,
4572 or FAIL if there isn't a valid constant here. */
4575 parse_fpa_immediate (char ** str)
4577 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4583 /* First try and match exact strings, this is to guarantee
4584 that some formats will work even for cross assembly. */
4586 for (i = 0; fp_const[i]; i++)
4588 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4592 *str += strlen (fp_const[i]);
4593 if (is_end_of_line[(unsigned char) **str])
4599 /* Just because we didn't get a match doesn't mean that the constant
4600 isn't valid, just that it is in a format that we don't
4601 automatically recognize. Try parsing it with the standard
4602 expression routines. */
4604 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4606 /* Look for a raw floating point number. */
4607 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4608 && is_end_of_line[(unsigned char) *save_in])
4610 for (i = 0; i < NUM_FLOAT_VALS; i++)
4612 for (j = 0; j < MAX_LITTLENUMS; j++)
4614 if (words[j] != fp_values[i][j])
4618 if (j == MAX_LITTLENUMS)
4626 /* Try and parse a more complex expression, this will probably fail
4627 unless the code uses a floating point prefix (eg "0f"). */
4628 save_in = input_line_pointer;
4629 input_line_pointer = *str;
4630 if (expression (&exp) == absolute_section
4631 && exp.X_op == O_big
4632 && exp.X_add_number < 0)
4634 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4636 if (gen_to_words (words, 5, (long) 15) == 0)
4638 for (i = 0; i < NUM_FLOAT_VALS; i++)
4640 for (j = 0; j < MAX_LITTLENUMS; j++)
4642 if (words[j] != fp_values[i][j])
4646 if (j == MAX_LITTLENUMS)
4648 *str = input_line_pointer;
4649 input_line_pointer = save_in;
4656 *str = input_line_pointer;
4657 input_line_pointer = save_in;
4658 inst.error = _("invalid FPA immediate expression");
4662 /* Returns 1 if a number has "quarter-precision" float format
4663 0baBbbbbbc defgh000 00000000 00000000. */
4666 is_quarter_float (unsigned imm)
4668 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4669 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4672 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4673 0baBbbbbbc defgh000 00000000 00000000.
4674 The zero and minus-zero cases need special handling, since they can't be
4675 encoded in the "quarter-precision" float format, but can nonetheless be
4676 loaded as integer constants. */
4679 parse_qfloat_immediate (char **ccp, int *immed)
4683 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4684 int found_fpchar = 0;
4686 skip_past_char (&str, '#');
4688 /* We must not accidentally parse an integer as a floating-point number. Make
4689 sure that the value we parse is not an integer by checking for special
4690 characters '.' or 'e'.
4691 FIXME: This is a horrible hack, but doing better is tricky because type
4692 information isn't in a very usable state at parse time. */
4694 skip_whitespace (fpnum);
4696 if (strncmp (fpnum, "0x", 2) == 0)
4700 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4701 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4711 if ((str = atof_ieee (str, 's', words)) != NULL)
4713 unsigned fpword = 0;
4716 /* Our FP word must be 32 bits (single-precision FP). */
4717 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4719 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4723 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4736 /* Shift operands. */
4739 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4742 struct asm_shift_name
4745 enum shift_kind kind;
4748 /* Third argument to parse_shift. */
4749 enum parse_shift_mode
4751 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4752 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4753 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4754 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4755 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4758 /* Parse a <shift> specifier on an ARM data processing instruction.
4759 This has three forms:
4761 (LSL|LSR|ASL|ASR|ROR) Rs
4762 (LSL|LSR|ASL|ASR|ROR) #imm
4765 Note that ASL is assimilated to LSL in the instruction encoding, and
4766 RRX to ROR #0 (which cannot be written as such). */
4769 parse_shift (char **str, int i, enum parse_shift_mode mode)
4771 const struct asm_shift_name *shift_name;
4772 enum shift_kind shift;
4777 for (p = *str; ISALPHA (*p); p++)
4782 inst.error = _("shift expression expected");
4786 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4789 if (shift_name == NULL)
4791 inst.error = _("shift expression expected");
4795 shift = shift_name->kind;
4799 case NO_SHIFT_RESTRICT:
4800 case SHIFT_IMMEDIATE: break;
4802 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4803 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4805 inst.error = _("'LSL' or 'ASR' required");
4810 case SHIFT_LSL_IMMEDIATE:
4811 if (shift != SHIFT_LSL)
4813 inst.error = _("'LSL' required");
4818 case SHIFT_ASR_IMMEDIATE:
4819 if (shift != SHIFT_ASR)
4821 inst.error = _("'ASR' required");
4829 if (shift != SHIFT_RRX)
4831 /* Whitespace can appear here if the next thing is a bare digit. */
4832 skip_whitespace (p);
4834 if (mode == NO_SHIFT_RESTRICT
4835 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4837 inst.operands[i].imm = reg;
4838 inst.operands[i].immisreg = 1;
4840 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4843 inst.operands[i].shift_kind = shift;
4844 inst.operands[i].shifted = 1;
4849 /* Parse a <shifter_operand> for an ARM data processing instruction:
4852 #<immediate>, <rotate>
4856 where <shift> is defined by parse_shift above, and <rotate> is a
4857 multiple of 2 between 0 and 30. Validation of immediate operands
4858 is deferred to md_apply_fix. */
4861 parse_shifter_operand (char **str, int i)
4866 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4868 inst.operands[i].reg = value;
4869 inst.operands[i].isreg = 1;
4871 /* parse_shift will override this if appropriate */
4872 inst.reloc.exp.X_op = O_constant;
4873 inst.reloc.exp.X_add_number = 0;
4875 if (skip_past_comma (str) == FAIL)
4878 /* Shift operation on register. */
4879 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4882 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4885 if (skip_past_comma (str) == SUCCESS)
4887 /* #x, y -- ie explicit rotation by Y. */
4888 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4891 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4893 inst.error = _("constant expression expected");
4897 value = exp.X_add_number;
4898 if (value < 0 || value > 30 || value % 2 != 0)
4900 inst.error = _("invalid rotation");
4903 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4905 inst.error = _("invalid constant");
4909 /* Encode as specified. */
4910 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4914 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4915 inst.reloc.pc_rel = 0;
4919 /* Group relocation information. Each entry in the table contains the
4920 textual name of the relocation as may appear in assembler source
4921 and must end with a colon.
4922 Along with this textual name are the relocation codes to be used if
4923 the corresponding instruction is an ALU instruction (ADD or SUB only),
4924 an LDR, an LDRS, or an LDC. */
4926 struct group_reloc_table_entry
4937 /* Varieties of non-ALU group relocation. */
4944 static struct group_reloc_table_entry group_reloc_table[] =
4945 { /* Program counter relative: */
4947 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4952 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4953 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4954 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4955 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4957 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4962 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4963 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4964 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4965 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4967 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4968 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4969 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4970 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4971 /* Section base relative */
4973 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4978 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4979 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4980 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4981 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4983 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4988 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4989 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4990 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4991 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4993 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4994 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4995 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4996 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4998 /* Given the address of a pointer pointing to the textual name of a group
4999 relocation as may appear in assembler source, attempt to find its details
5000 in group_reloc_table. The pointer will be updated to the character after
5001 the trailing colon. On failure, FAIL will be returned; SUCCESS
5002 otherwise. On success, *entry will be updated to point at the relevant
5003 group_reloc_table entry. */
5006 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5009 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5011 int length = strlen (group_reloc_table[i].name);
5013 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5014 && (*str)[length] == ':')
5016 *out = &group_reloc_table[i];
5017 *str += (length + 1);
5025 /* Parse a <shifter_operand> for an ARM data processing instruction
5026 (as for parse_shifter_operand) where group relocations are allowed:
5029 #<immediate>, <rotate>
5030 #:<group_reloc>:<expression>
5034 where <group_reloc> is one of the strings defined in group_reloc_table.
5035 The hashes are optional.
5037 Everything else is as for parse_shifter_operand. */
5039 static parse_operand_result
5040 parse_shifter_operand_group_reloc (char **str, int i)
5042 /* Determine if we have the sequence of characters #: or just :
5043 coming next. If we do, then we check for a group relocation.
5044 If we don't, punt the whole lot to parse_shifter_operand. */
5046 if (((*str)[0] == '#' && (*str)[1] == ':')
5047 || (*str)[0] == ':')
5049 struct group_reloc_table_entry *entry;
5051 if ((*str)[0] == '#')
5056 /* Try to parse a group relocation. Anything else is an error. */
5057 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5059 inst.error = _("unknown group relocation");
5060 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5063 /* We now have the group relocation table entry corresponding to
5064 the name in the assembler source. Next, we parse the expression. */
5065 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5066 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5068 /* Record the relocation type (always the ALU variant here). */
5069 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5070 gas_assert (inst.reloc.type != 0);
5072 return PARSE_OPERAND_SUCCESS;
5075 return parse_shifter_operand (str, i) == SUCCESS
5076 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5078 /* Never reached. */
5081 /* Parse a Neon alignment expression. Information is written to
5082 inst.operands[i]. We assume the initial ':' has been skipped.
5084 align .imm = align << 8, .immisalign=1, .preind=0 */
5085 static parse_operand_result
5086 parse_neon_alignment (char **str, int i)
5091 my_get_expression (&exp, &p, GE_NO_PREFIX);
5093 if (exp.X_op != O_constant)
5095 inst.error = _("alignment must be constant");
5096 return PARSE_OPERAND_FAIL;
5099 inst.operands[i].imm = exp.X_add_number << 8;
5100 inst.operands[i].immisalign = 1;
5101 /* Alignments are not pre-indexes. */
5102 inst.operands[i].preind = 0;
5105 return PARSE_OPERAND_SUCCESS;
5108 /* Parse all forms of an ARM address expression. Information is written
5109 to inst.operands[i] and/or inst.reloc.
5111 Preindexed addressing (.preind=1):
5113 [Rn, #offset] .reg=Rn .reloc.exp=offset
5114 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5115 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5116 .shift_kind=shift .reloc.exp=shift_imm
5118 These three may have a trailing ! which causes .writeback to be set also.
5120 Postindexed addressing (.postind=1, .writeback=1):
5122 [Rn], #offset .reg=Rn .reloc.exp=offset
5123 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5124 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5125 .shift_kind=shift .reloc.exp=shift_imm
5127 Unindexed addressing (.preind=0, .postind=0):
5129 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5133 [Rn]{!} shorthand for [Rn,#0]{!}
5134 =immediate .isreg=0 .reloc.exp=immediate
5135 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5137 It is the caller's responsibility to check for addressing modes not
5138 supported by the instruction, and to set inst.reloc.type. */
5140 static parse_operand_result
5141 parse_address_main (char **str, int i, int group_relocations,
5142 group_reloc_type group_type)
5147 if (skip_past_char (&p, '[') == FAIL)
5149 if (skip_past_char (&p, '=') == FAIL)
5151 /* Bare address - translate to PC-relative offset. */
5152 inst.reloc.pc_rel = 1;
5153 inst.operands[i].reg = REG_PC;
5154 inst.operands[i].isreg = 1;
5155 inst.operands[i].preind = 1;
5157 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5159 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5160 return PARSE_OPERAND_FAIL;
5163 return PARSE_OPERAND_SUCCESS;
5166 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5168 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5169 return PARSE_OPERAND_FAIL;
5171 inst.operands[i].reg = reg;
5172 inst.operands[i].isreg = 1;
5174 if (skip_past_comma (&p) == SUCCESS)
5176 inst.operands[i].preind = 1;
5179 else if (*p == '-') p++, inst.operands[i].negative = 1;
5181 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5183 inst.operands[i].imm = reg;
5184 inst.operands[i].immisreg = 1;
5186 if (skip_past_comma (&p) == SUCCESS)
5187 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5188 return PARSE_OPERAND_FAIL;
5190 else if (skip_past_char (&p, ':') == SUCCESS)
5192 /* FIXME: '@' should be used here, but it's filtered out by generic
5193 code before we get to see it here. This may be subject to
5195 parse_operand_result result = parse_neon_alignment (&p, i);
5197 if (result != PARSE_OPERAND_SUCCESS)
5202 if (inst.operands[i].negative)
5204 inst.operands[i].negative = 0;
5208 if (group_relocations
5209 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5211 struct group_reloc_table_entry *entry;
5213 /* Skip over the #: or : sequence. */
5219 /* Try to parse a group relocation. Anything else is an
5221 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5223 inst.error = _("unknown group relocation");
5224 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5227 /* We now have the group relocation table entry corresponding to
5228 the name in the assembler source. Next, we parse the
5230 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5231 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5233 /* Record the relocation type. */
5237 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5241 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5245 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5252 if (inst.reloc.type == 0)
5254 inst.error = _("this group relocation is not allowed on this instruction");
5255 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5261 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5262 return PARSE_OPERAND_FAIL;
5263 /* If the offset is 0, find out if it's a +0 or -0. */
5264 if (inst.reloc.exp.X_op == O_constant
5265 && inst.reloc.exp.X_add_number == 0)
5267 skip_whitespace (q);
5271 skip_whitespace (q);
5274 inst.operands[i].negative = 1;
5279 else if (skip_past_char (&p, ':') == SUCCESS)
5281 /* FIXME: '@' should be used here, but it's filtered out by generic code
5282 before we get to see it here. This may be subject to change. */
5283 parse_operand_result result = parse_neon_alignment (&p, i);
5285 if (result != PARSE_OPERAND_SUCCESS)
5289 if (skip_past_char (&p, ']') == FAIL)
5291 inst.error = _("']' expected");
5292 return PARSE_OPERAND_FAIL;
5295 if (skip_past_char (&p, '!') == SUCCESS)
5296 inst.operands[i].writeback = 1;
5298 else if (skip_past_comma (&p) == SUCCESS)
5300 if (skip_past_char (&p, '{') == SUCCESS)
5302 /* [Rn], {expr} - unindexed, with option */
5303 if (parse_immediate (&p, &inst.operands[i].imm,
5304 0, 255, TRUE) == FAIL)
5305 return PARSE_OPERAND_FAIL;
5307 if (skip_past_char (&p, '}') == FAIL)
5309 inst.error = _("'}' expected at end of 'option' field");
5310 return PARSE_OPERAND_FAIL;
5312 if (inst.operands[i].preind)
5314 inst.error = _("cannot combine index with option");
5315 return PARSE_OPERAND_FAIL;
5318 return PARSE_OPERAND_SUCCESS;
5322 inst.operands[i].postind = 1;
5323 inst.operands[i].writeback = 1;
5325 if (inst.operands[i].preind)
5327 inst.error = _("cannot combine pre- and post-indexing");
5328 return PARSE_OPERAND_FAIL;
5332 else if (*p == '-') p++, inst.operands[i].negative = 1;
5334 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5336 /* We might be using the immediate for alignment already. If we
5337 are, OR the register number into the low-order bits. */
5338 if (inst.operands[i].immisalign)
5339 inst.operands[i].imm |= reg;
5341 inst.operands[i].imm = reg;
5342 inst.operands[i].immisreg = 1;
5344 if (skip_past_comma (&p) == SUCCESS)
5345 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5346 return PARSE_OPERAND_FAIL;
5351 if (inst.operands[i].negative)
5353 inst.operands[i].negative = 0;
5356 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5357 return PARSE_OPERAND_FAIL;
5358 /* If the offset is 0, find out if it's a +0 or -0. */
5359 if (inst.reloc.exp.X_op == O_constant
5360 && inst.reloc.exp.X_add_number == 0)
5362 skip_whitespace (q);
5366 skip_whitespace (q);
5369 inst.operands[i].negative = 1;
5375 /* If at this point neither .preind nor .postind is set, we have a
5376 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5377 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5379 inst.operands[i].preind = 1;
5380 inst.reloc.exp.X_op = O_constant;
5381 inst.reloc.exp.X_add_number = 0;
5384 return PARSE_OPERAND_SUCCESS;
5388 parse_address (char **str, int i)
5390 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5394 static parse_operand_result
5395 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5397 return parse_address_main (str, i, 1, type);
5400 /* Parse an operand for a MOVW or MOVT instruction. */
5402 parse_half (char **str)
5407 skip_past_char (&p, '#');
5408 if (strncasecmp (p, ":lower16:", 9) == 0)
5409 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5410 else if (strncasecmp (p, ":upper16:", 9) == 0)
5411 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5413 if (inst.reloc.type != BFD_RELOC_UNUSED)
5416 skip_whitespace (p);
5419 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5422 if (inst.reloc.type == BFD_RELOC_UNUSED)
5424 if (inst.reloc.exp.X_op != O_constant)
5426 inst.error = _("constant expression expected");
5429 if (inst.reloc.exp.X_add_number < 0
5430 || inst.reloc.exp.X_add_number > 0xffff)
5432 inst.error = _("immediate value out of range");
5440 /* Miscellaneous. */
5442 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5443 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5445 parse_psr (char **str, bfd_boolean lhs)
5448 unsigned long psr_field;
5449 const struct asm_psr *psr;
5451 bfd_boolean is_apsr = FALSE;
5452 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5454 /* PR gas/12698: If the user has specified -march=all then m_profile will
5455 be TRUE, but we want to ignore it in this case as we are building for any
5456 CPU type, including non-m variants. */
5457 if (selected_cpu.core == arm_arch_any.core)
5460 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5461 feature for ease of use and backwards compatibility. */
5463 if (strncasecmp (p, "SPSR", 4) == 0)
5466 goto unsupported_psr;
5468 psr_field = SPSR_BIT;
5470 else if (strncasecmp (p, "CPSR", 4) == 0)
5473 goto unsupported_psr;
5477 else if (strncasecmp (p, "APSR", 4) == 0)
5479 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5480 and ARMv7-R architecture CPUs. */
5489 while (ISALNUM (*p) || *p == '_');
5491 if (strncasecmp (start, "iapsr", 5) == 0
5492 || strncasecmp (start, "eapsr", 5) == 0
5493 || strncasecmp (start, "xpsr", 4) == 0
5494 || strncasecmp (start, "psr", 3) == 0)
5495 p = start + strcspn (start, "rR") + 1;
5497 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5503 /* If APSR is being written, a bitfield may be specified. Note that
5504 APSR itself is handled above. */
5505 if (psr->field <= 3)
5507 psr_field = psr->field;
5513 /* M-profile MSR instructions have the mask field set to "10", except
5514 *PSR variants which modify APSR, which may use a different mask (and
5515 have been handled already). Do that by setting the PSR_f field
5517 return psr->field | (lhs ? PSR_f : 0);
5520 goto unsupported_psr;
5526 /* A suffix follows. */
5532 while (ISALNUM (*p) || *p == '_');
5536 /* APSR uses a notation for bits, rather than fields. */
5537 unsigned int nzcvq_bits = 0;
5538 unsigned int g_bit = 0;
5541 for (bit = start; bit != p; bit++)
5543 switch (TOLOWER (*bit))
5546 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5550 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5554 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5558 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5562 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5566 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5570 inst.error = _("unexpected bit specified after APSR");
5575 if (nzcvq_bits == 0x1f)
5580 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5582 inst.error = _("selected processor does not "
5583 "support DSP extension");
5590 if ((nzcvq_bits & 0x20) != 0
5591 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5592 || (g_bit & 0x2) != 0)
5594 inst.error = _("bad bitmask specified after APSR");
5600 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5605 psr_field |= psr->field;
5611 goto error; /* Garbage after "[CS]PSR". */
5613 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5614 is deprecated, but allow it anyway. */
5618 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5621 else if (!m_profile)
5622 /* These bits are never right for M-profile devices: don't set them
5623 (only code paths which read/write APSR reach here). */
5624 psr_field |= (PSR_c | PSR_f);
5630 inst.error = _("selected processor does not support requested special "
5631 "purpose register");
5635 inst.error = _("flag for {c}psr instruction expected");
5639 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5640 value suitable for splatting into the AIF field of the instruction. */
5643 parse_cps_flags (char **str)
5652 case '\0': case ',':
5655 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5656 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5657 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5660 inst.error = _("unrecognized CPS flag");
5665 if (saw_a_flag == 0)
5667 inst.error = _("missing CPS flags");
5675 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5676 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5679 parse_endian_specifier (char **str)
5684 if (strncasecmp (s, "BE", 2))
5686 else if (strncasecmp (s, "LE", 2))
5690 inst.error = _("valid endian specifiers are be or le");
5694 if (ISALNUM (s[2]) || s[2] == '_')
5696 inst.error = _("valid endian specifiers are be or le");
5701 return little_endian;
5704 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5705 value suitable for poking into the rotate field of an sxt or sxta
5706 instruction, or FAIL on error. */
5709 parse_ror (char **str)
5714 if (strncasecmp (s, "ROR", 3) == 0)
5718 inst.error = _("missing rotation field after comma");
5722 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5727 case 0: *str = s; return 0x0;
5728 case 8: *str = s; return 0x1;
5729 case 16: *str = s; return 0x2;
5730 case 24: *str = s; return 0x3;
5733 inst.error = _("rotation can only be 0, 8, 16, or 24");
5738 /* Parse a conditional code (from conds[] below). The value returned is in the
5739 range 0 .. 14, or FAIL. */
5741 parse_cond (char **str)
5744 const struct asm_cond *c;
5746 /* Condition codes are always 2 characters, so matching up to
5747 3 characters is sufficient. */
5752 while (ISALPHA (*q) && n < 3)
5754 cond[n] = TOLOWER (*q);
5759 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5762 inst.error = _("condition required");
5770 /* If the given feature available in the selected CPU, mark it as used.
5771 Returns TRUE iff feature is available. */
5773 mark_feature_used (const arm_feature_set *feature)
5775 /* Ensure the option is valid on the current architecture. */
5776 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5779 /* Add the appropriate architecture feature for the barrier option used.
5782 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5784 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5789 /* Parse an option for a barrier instruction. Returns the encoding for the
5792 parse_barrier (char **str)
5795 const struct asm_barrier_opt *o;
5798 while (ISALPHA (*q))
5801 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5806 if (!mark_feature_used (&o->arch))
5813 /* Parse the operands of a table branch instruction. Similar to a memory
5816 parse_tb (char **str)
5821 if (skip_past_char (&p, '[') == FAIL)
5823 inst.error = _("'[' expected");
5827 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5829 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5832 inst.operands[0].reg = reg;
5834 if (skip_past_comma (&p) == FAIL)
5836 inst.error = _("',' expected");
5840 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5842 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5845 inst.operands[0].imm = reg;
5847 if (skip_past_comma (&p) == SUCCESS)
5849 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5851 if (inst.reloc.exp.X_add_number != 1)
5853 inst.error = _("invalid shift");
5856 inst.operands[0].shifted = 1;
5859 if (skip_past_char (&p, ']') == FAIL)
5861 inst.error = _("']' expected");
5868 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5869 information on the types the operands can take and how they are encoded.
5870 Up to four operands may be read; this function handles setting the
5871 ".present" field for each read operand itself.
5872 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5873 else returns FAIL. */
5876 parse_neon_mov (char **str, int *which_operand)
5878 int i = *which_operand, val;
5879 enum arm_reg_type rtype;
5881 struct neon_type_el optype;
5883 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5885 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5886 inst.operands[i].reg = val;
5887 inst.operands[i].isscalar = 1;
5888 inst.operands[i].vectype = optype;
5889 inst.operands[i++].present = 1;
5891 if (skip_past_comma (&ptr) == FAIL)
5894 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5897 inst.operands[i].reg = val;
5898 inst.operands[i].isreg = 1;
5899 inst.operands[i].present = 1;
5901 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5904 /* Cases 0, 1, 2, 3, 5 (D only). */
5905 if (skip_past_comma (&ptr) == FAIL)
5908 inst.operands[i].reg = val;
5909 inst.operands[i].isreg = 1;
5910 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5911 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5912 inst.operands[i].isvec = 1;
5913 inst.operands[i].vectype = optype;
5914 inst.operands[i++].present = 1;
5916 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5918 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5919 Case 13: VMOV <Sd>, <Rm> */
5920 inst.operands[i].reg = val;
5921 inst.operands[i].isreg = 1;
5922 inst.operands[i].present = 1;
5924 if (rtype == REG_TYPE_NQ)
5926 first_error (_("can't use Neon quad register here"));
5929 else if (rtype != REG_TYPE_VFS)
5932 if (skip_past_comma (&ptr) == FAIL)
5934 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5936 inst.operands[i].reg = val;
5937 inst.operands[i].isreg = 1;
5938 inst.operands[i].present = 1;
5941 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5944 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5945 Case 1: VMOV<c><q> <Dd>, <Dm>
5946 Case 8: VMOV.F32 <Sd>, <Sm>
5947 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5949 inst.operands[i].reg = val;
5950 inst.operands[i].isreg = 1;
5951 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5952 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5953 inst.operands[i].isvec = 1;
5954 inst.operands[i].vectype = optype;
5955 inst.operands[i].present = 1;
5957 if (skip_past_comma (&ptr) == SUCCESS)
5962 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5965 inst.operands[i].reg = val;
5966 inst.operands[i].isreg = 1;
5967 inst.operands[i++].present = 1;
5969 if (skip_past_comma (&ptr) == FAIL)
5972 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5975 inst.operands[i].reg = val;
5976 inst.operands[i].isreg = 1;
5977 inst.operands[i].present = 1;
5980 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5981 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5982 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5983 Case 10: VMOV.F32 <Sd>, #<imm>
5984 Case 11: VMOV.F64 <Dd>, #<imm> */
5985 inst.operands[i].immisfloat = 1;
5986 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5987 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5988 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5992 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5996 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5999 inst.operands[i].reg = val;
6000 inst.operands[i].isreg = 1;
6001 inst.operands[i++].present = 1;
6003 if (skip_past_comma (&ptr) == FAIL)
6006 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6008 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6009 inst.operands[i].reg = val;
6010 inst.operands[i].isscalar = 1;
6011 inst.operands[i].present = 1;
6012 inst.operands[i].vectype = optype;
6014 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6016 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6017 inst.operands[i].reg = val;
6018 inst.operands[i].isreg = 1;
6019 inst.operands[i++].present = 1;
6021 if (skip_past_comma (&ptr) == FAIL)
6024 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6027 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6031 inst.operands[i].reg = val;
6032 inst.operands[i].isreg = 1;
6033 inst.operands[i].isvec = 1;
6034 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6035 inst.operands[i].vectype = optype;
6036 inst.operands[i].present = 1;
6038 if (rtype == REG_TYPE_VFS)
6042 if (skip_past_comma (&ptr) == FAIL)
6044 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6047 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6050 inst.operands[i].reg = val;
6051 inst.operands[i].isreg = 1;
6052 inst.operands[i].isvec = 1;
6053 inst.operands[i].issingle = 1;
6054 inst.operands[i].vectype = optype;
6055 inst.operands[i].present = 1;
6058 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6062 inst.operands[i].reg = val;
6063 inst.operands[i].isreg = 1;
6064 inst.operands[i].isvec = 1;
6065 inst.operands[i].issingle = 1;
6066 inst.operands[i].vectype = optype;
6067 inst.operands[i].present = 1;
6072 first_error (_("parse error"));
6076 /* Successfully parsed the operands. Update args. */
6082 first_error (_("expected comma"));
6086 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6090 /* Use this macro when the operand constraints are different
6091 for ARM and THUMB (e.g. ldrd). */
6092 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6093 ((arm_operand) | ((thumb_operand) << 16))
6095 /* Matcher codes for parse_operands. */
6096 enum operand_parse_code
6098 OP_stop, /* end of line */
6100 OP_RR, /* ARM register */
6101 OP_RRnpc, /* ARM register, not r15 */
6102 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6103 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6104 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6105 optional trailing ! */
6106 OP_RRw, /* ARM register, not r15, optional trailing ! */
6107 OP_RCP, /* Coprocessor number */
6108 OP_RCN, /* Coprocessor register */
6109 OP_RF, /* FPA register */
6110 OP_RVS, /* VFP single precision register */
6111 OP_RVD, /* VFP double precision register (0..15) */
6112 OP_RND, /* Neon double precision register (0..31) */
6113 OP_RNQ, /* Neon quad precision register */
6114 OP_RVSD, /* VFP single or double precision register */
6115 OP_RNDQ, /* Neon double or quad precision register */
6116 OP_RNSDQ, /* Neon single, double or quad precision register */
6117 OP_RNSC, /* Neon scalar D[X] */
6118 OP_RVC, /* VFP control register */
6119 OP_RMF, /* Maverick F register */
6120 OP_RMD, /* Maverick D register */
6121 OP_RMFX, /* Maverick FX register */
6122 OP_RMDX, /* Maverick DX register */
6123 OP_RMAX, /* Maverick AX register */
6124 OP_RMDS, /* Maverick DSPSC register */
6125 OP_RIWR, /* iWMMXt wR register */
6126 OP_RIWC, /* iWMMXt wC register */
6127 OP_RIWG, /* iWMMXt wCG register */
6128 OP_RXA, /* XScale accumulator register */
6130 OP_REGLST, /* ARM register list */
6131 OP_VRSLST, /* VFP single-precision register list */
6132 OP_VRDLST, /* VFP double-precision register list */
6133 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6134 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6135 OP_NSTRLST, /* Neon element/structure list */
6137 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6138 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6139 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6140 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6141 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6142 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6143 OP_VMOV, /* Neon VMOV operands. */
6144 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6145 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6146 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6148 OP_I0, /* immediate zero */
6149 OP_I7, /* immediate value 0 .. 7 */
6150 OP_I15, /* 0 .. 15 */
6151 OP_I16, /* 1 .. 16 */
6152 OP_I16z, /* 0 .. 16 */
6153 OP_I31, /* 0 .. 31 */
6154 OP_I31w, /* 0 .. 31, optional trailing ! */
6155 OP_I32, /* 1 .. 32 */
6156 OP_I32z, /* 0 .. 32 */
6157 OP_I63, /* 0 .. 63 */
6158 OP_I63s, /* -64 .. 63 */
6159 OP_I64, /* 1 .. 64 */
6160 OP_I64z, /* 0 .. 64 */
6161 OP_I255, /* 0 .. 255 */
6163 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6164 OP_I7b, /* 0 .. 7 */
6165 OP_I15b, /* 0 .. 15 */
6166 OP_I31b, /* 0 .. 31 */
6168 OP_SH, /* shifter operand */
6169 OP_SHG, /* shifter operand with possible group relocation */
6170 OP_ADDR, /* Memory address expression (any mode) */
6171 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6172 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6173 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6174 OP_EXP, /* arbitrary expression */
6175 OP_EXPi, /* same, with optional immediate prefix */
6176 OP_EXPr, /* same, with optional relocation suffix */
6177 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6179 OP_CPSF, /* CPS flags */
6180 OP_ENDI, /* Endianness specifier */
6181 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6182 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6183 OP_COND, /* conditional code */
6184 OP_TB, /* Table branch. */
6186 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6188 OP_RRnpc_I0, /* ARM register or literal 0 */
6189 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6190 OP_RR_EXi, /* ARM register or expression with imm prefix */
6191 OP_RF_IF, /* FPA register or immediate */
6192 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6193 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6195 /* Optional operands. */
6196 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6197 OP_oI31b, /* 0 .. 31 */
6198 OP_oI32b, /* 1 .. 32 */
6199 OP_oI32z, /* 0 .. 32 */
6200 OP_oIffffb, /* 0 .. 65535 */
6201 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6203 OP_oRR, /* ARM register */
6204 OP_oRRnpc, /* ARM register, not the PC */
6205 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6206 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6207 OP_oRND, /* Optional Neon double precision register */
6208 OP_oRNQ, /* Optional Neon quad precision register */
6209 OP_oRNDQ, /* Optional Neon double or quad precision register */
6210 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6211 OP_oSHll, /* LSL immediate */
6212 OP_oSHar, /* ASR immediate */
6213 OP_oSHllar, /* LSL or ASR immediate */
6214 OP_oROR, /* ROR 0/8/16/24 */
6215 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6217 /* Some pre-defined mixed (ARM/THUMB) operands. */
6218 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6219 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6220 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6222 OP_FIRST_OPTIONAL = OP_oI7b
6225 /* Generic instruction operand parser. This does no encoding and no
6226 semantic validation; it merely squirrels values away in the inst
6227 structure. Returns SUCCESS or FAIL depending on whether the
6228 specified grammar matched. */
6230 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6232 unsigned const int *upat = pattern;
6233 char *backtrack_pos = 0;
6234 const char *backtrack_error = 0;
6235 int i, val = 0, backtrack_index = 0;
6236 enum arm_reg_type rtype;
6237 parse_operand_result result;
6238 unsigned int op_parse_code;
6240 #define po_char_or_fail(chr) \
6243 if (skip_past_char (&str, chr) == FAIL) \
6248 #define po_reg_or_fail(regtype) \
6251 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6252 & inst.operands[i].vectype); \
6255 first_error (_(reg_expected_msgs[regtype])); \
6258 inst.operands[i].reg = val; \
6259 inst.operands[i].isreg = 1; \
6260 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6261 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6262 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6263 || rtype == REG_TYPE_VFD \
6264 || rtype == REG_TYPE_NQ); \
6268 #define po_reg_or_goto(regtype, label) \
6271 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6272 & inst.operands[i].vectype); \
6276 inst.operands[i].reg = val; \
6277 inst.operands[i].isreg = 1; \
6278 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6279 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6280 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6281 || rtype == REG_TYPE_VFD \
6282 || rtype == REG_TYPE_NQ); \
6286 #define po_imm_or_fail(min, max, popt) \
6289 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6291 inst.operands[i].imm = val; \
6295 #define po_scalar_or_goto(elsz, label) \
6298 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6301 inst.operands[i].reg = val; \
6302 inst.operands[i].isscalar = 1; \
6306 #define po_misc_or_fail(expr) \
6314 #define po_misc_or_fail_no_backtrack(expr) \
6318 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6319 backtrack_pos = 0; \
6320 if (result != PARSE_OPERAND_SUCCESS) \
6325 #define po_barrier_or_imm(str) \
6328 val = parse_barrier (&str); \
6331 if (ISALPHA (*str)) \
6338 if ((inst.instruction & 0xf0) == 0x60 \
6341 /* ISB can only take SY as an option. */ \
6342 inst.error = _("invalid barrier type"); \
6349 skip_whitespace (str);
6351 for (i = 0; upat[i] != OP_stop; i++)
6353 op_parse_code = upat[i];
6354 if (op_parse_code >= 1<<16)
6355 op_parse_code = thumb ? (op_parse_code >> 16)
6356 : (op_parse_code & ((1<<16)-1));
6358 if (op_parse_code >= OP_FIRST_OPTIONAL)
6360 /* Remember where we are in case we need to backtrack. */
6361 gas_assert (!backtrack_pos);
6362 backtrack_pos = str;
6363 backtrack_error = inst.error;
6364 backtrack_index = i;
6367 if (i > 0 && (i > 1 || inst.operands[0].present))
6368 po_char_or_fail (',');
6370 switch (op_parse_code)
6378 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6379 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6380 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6381 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6382 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6383 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6385 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6387 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6389 /* Also accept generic coprocessor regs for unknown registers. */
6391 po_reg_or_fail (REG_TYPE_CN);
6393 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6394 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6395 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6396 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6397 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6398 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6399 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6400 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6401 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6402 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6404 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6406 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6407 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6409 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6411 /* Neon scalar. Using an element size of 8 means that some invalid
6412 scalars are accepted here, so deal with those in later code. */
6413 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6417 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6420 po_imm_or_fail (0, 0, TRUE);
6425 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6430 po_scalar_or_goto (8, try_rr);
6433 po_reg_or_fail (REG_TYPE_RN);
6439 po_scalar_or_goto (8, try_nsdq);
6442 po_reg_or_fail (REG_TYPE_NSDQ);
6448 po_scalar_or_goto (8, try_ndq);
6451 po_reg_or_fail (REG_TYPE_NDQ);
6457 po_scalar_or_goto (8, try_vfd);
6460 po_reg_or_fail (REG_TYPE_VFD);
6465 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6466 not careful then bad things might happen. */
6467 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6472 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6475 /* There's a possibility of getting a 64-bit immediate here, so
6476 we need special handling. */
6477 if (parse_big_immediate (&str, i) == FAIL)
6479 inst.error = _("immediate value is out of range");
6487 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6490 po_imm_or_fail (0, 63, TRUE);
6495 po_char_or_fail ('[');
6496 po_reg_or_fail (REG_TYPE_RN);
6497 po_char_or_fail (']');
6503 po_reg_or_fail (REG_TYPE_RN);
6504 if (skip_past_char (&str, '!') == SUCCESS)
6505 inst.operands[i].writeback = 1;
6509 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6510 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6511 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6512 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6513 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6514 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6515 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6516 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6517 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6518 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6519 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6520 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6522 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6524 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6525 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6527 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6528 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6529 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6530 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6532 /* Immediate variants */
6534 po_char_or_fail ('{');
6535 po_imm_or_fail (0, 255, TRUE);
6536 po_char_or_fail ('}');
6540 /* The expression parser chokes on a trailing !, so we have
6541 to find it first and zap it. */
6544 while (*s && *s != ',')
6549 inst.operands[i].writeback = 1;
6551 po_imm_or_fail (0, 31, TRUE);
6559 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6564 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6569 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6571 if (inst.reloc.exp.X_op == O_symbol)
6573 val = parse_reloc (&str);
6576 inst.error = _("unrecognized relocation suffix");
6579 else if (val != BFD_RELOC_UNUSED)
6581 inst.operands[i].imm = val;
6582 inst.operands[i].hasreloc = 1;
6587 /* Operand for MOVW or MOVT. */
6589 po_misc_or_fail (parse_half (&str));
6592 /* Register or expression. */
6593 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6594 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6596 /* Register or immediate. */
6597 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6598 I0: po_imm_or_fail (0, 0, FALSE); break;
6600 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6602 if (!is_immediate_prefix (*str))
6605 val = parse_fpa_immediate (&str);
6608 /* FPA immediates are encoded as registers 8-15.
6609 parse_fpa_immediate has already applied the offset. */
6610 inst.operands[i].reg = val;
6611 inst.operands[i].isreg = 1;
6614 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6615 I32z: po_imm_or_fail (0, 32, FALSE); break;
6617 /* Two kinds of register. */
6620 struct reg_entry *rege = arm_reg_parse_multi (&str);
6622 || (rege->type != REG_TYPE_MMXWR
6623 && rege->type != REG_TYPE_MMXWC
6624 && rege->type != REG_TYPE_MMXWCG))
6626 inst.error = _("iWMMXt data or control register expected");
6629 inst.operands[i].reg = rege->number;
6630 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6636 struct reg_entry *rege = arm_reg_parse_multi (&str);
6638 || (rege->type != REG_TYPE_MMXWC
6639 && rege->type != REG_TYPE_MMXWCG))
6641 inst.error = _("iWMMXt control register expected");
6644 inst.operands[i].reg = rege->number;
6645 inst.operands[i].isreg = 1;
6650 case OP_CPSF: val = parse_cps_flags (&str); break;
6651 case OP_ENDI: val = parse_endian_specifier (&str); break;
6652 case OP_oROR: val = parse_ror (&str); break;
6653 case OP_COND: val = parse_cond (&str); break;
6654 case OP_oBARRIER_I15:
6655 po_barrier_or_imm (str); break;
6657 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6663 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6664 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6666 inst.error = _("Banked registers are not available with this "
6672 val = parse_psr (&str, op_parse_code == OP_wPSR);
6676 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6679 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6681 if (strncasecmp (str, "APSR_", 5) == 0)
6688 case 'c': found = (found & 1) ? 16 : found | 1; break;
6689 case 'n': found = (found & 2) ? 16 : found | 2; break;
6690 case 'z': found = (found & 4) ? 16 : found | 4; break;
6691 case 'v': found = (found & 8) ? 16 : found | 8; break;
6692 default: found = 16;
6696 inst.operands[i].isvec = 1;
6697 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6698 inst.operands[i].reg = REG_PC;
6705 po_misc_or_fail (parse_tb (&str));
6708 /* Register lists. */
6710 val = parse_reg_list (&str);
6713 inst.operands[1].writeback = 1;
6719 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6723 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6727 /* Allow Q registers too. */
6728 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6733 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6735 inst.operands[i].issingle = 1;
6740 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6745 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6746 &inst.operands[i].vectype);
6749 /* Addressing modes */
6751 po_misc_or_fail (parse_address (&str, i));
6755 po_misc_or_fail_no_backtrack (
6756 parse_address_group_reloc (&str, i, GROUP_LDR));
6760 po_misc_or_fail_no_backtrack (
6761 parse_address_group_reloc (&str, i, GROUP_LDRS));
6765 po_misc_or_fail_no_backtrack (
6766 parse_address_group_reloc (&str, i, GROUP_LDC));
6770 po_misc_or_fail (parse_shifter_operand (&str, i));
6774 po_misc_or_fail_no_backtrack (
6775 parse_shifter_operand_group_reloc (&str, i));
6779 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6783 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6787 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6791 as_fatal (_("unhandled operand code %d"), op_parse_code);
6794 /* Various value-based sanity checks and shared operations. We
6795 do not signal immediate failures for the register constraints;
6796 this allows a syntax error to take precedence. */
6797 switch (op_parse_code)
6805 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6806 inst.error = BAD_PC;
6811 if (inst.operands[i].isreg)
6813 if (inst.operands[i].reg == REG_PC)
6814 inst.error = BAD_PC;
6815 else if (inst.operands[i].reg == REG_SP)
6816 inst.error = BAD_SP;
6821 if (inst.operands[i].isreg
6822 && inst.operands[i].reg == REG_PC
6823 && (inst.operands[i].writeback || thumb))
6824 inst.error = BAD_PC;
6833 case OP_oBARRIER_I15:
6842 inst.operands[i].imm = val;
6849 /* If we get here, this operand was successfully parsed. */
6850 inst.operands[i].present = 1;
6854 inst.error = BAD_ARGS;
6859 /* The parse routine should already have set inst.error, but set a
6860 default here just in case. */
6862 inst.error = _("syntax error");
6866 /* Do not backtrack over a trailing optional argument that
6867 absorbed some text. We will only fail again, with the
6868 'garbage following instruction' error message, which is
6869 probably less helpful than the current one. */
6870 if (backtrack_index == i && backtrack_pos != str
6871 && upat[i+1] == OP_stop)
6874 inst.error = _("syntax error");
6878 /* Try again, skipping the optional argument at backtrack_pos. */
6879 str = backtrack_pos;
6880 inst.error = backtrack_error;
6881 inst.operands[backtrack_index].present = 0;
6882 i = backtrack_index;
6886 /* Check that we have parsed all the arguments. */
6887 if (*str != '\0' && !inst.error)
6888 inst.error = _("garbage following instruction");
6890 return inst.error ? FAIL : SUCCESS;
6893 #undef po_char_or_fail
6894 #undef po_reg_or_fail
6895 #undef po_reg_or_goto
6896 #undef po_imm_or_fail
6897 #undef po_scalar_or_fail
6898 #undef po_barrier_or_imm
6900 /* Shorthand macro for instruction encoding functions issuing errors. */
6901 #define constraint(expr, err) \
6912 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6913 instructions are unpredictable if these registers are used. This
6914 is the BadReg predicate in ARM's Thumb-2 documentation. */
6915 #define reject_bad_reg(reg) \
6917 if (reg == REG_SP || reg == REG_PC) \
6919 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6924 /* If REG is R13 (the stack pointer), warn that its use is
6926 #define warn_deprecated_sp(reg) \
6928 if (warn_on_deprecated && reg == REG_SP) \
6929 as_warn (_("use of r13 is deprecated")); \
6932 /* Functions for operand encoding. ARM, then Thumb. */
6934 #define rotate_left(v, n) (v << n | v >> (32 - n))
6936 /* If VAL can be encoded in the immediate field of an ARM instruction,
6937 return the encoded form. Otherwise, return FAIL. */
6940 encode_arm_immediate (unsigned int val)
6944 for (i = 0; i < 32; i += 2)
6945 if ((a = rotate_left (val, i)) <= 0xff)
6946 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6951 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6952 return the encoded form. Otherwise, return FAIL. */
6954 encode_thumb32_immediate (unsigned int val)
6961 for (i = 1; i <= 24; i++)
6964 if ((val & ~(0xff << i)) == 0)
6965 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6969 if (val == ((a << 16) | a))
6971 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6975 if (val == ((a << 16) | a))
6976 return 0x200 | (a >> 8);
6980 /* Encode a VFP SP or DP register number into inst.instruction. */
6983 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6985 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6988 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6991 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6994 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6999 first_error (_("D register out of range for selected VFP version"));
7007 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7011 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7015 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7019 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7023 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7027 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7035 /* Encode a <shift> in an ARM-format instruction. The immediate,
7036 if any, is handled by md_apply_fix. */
7038 encode_arm_shift (int i)
7040 if (inst.operands[i].shift_kind == SHIFT_RRX)
7041 inst.instruction |= SHIFT_ROR << 5;
7044 inst.instruction |= inst.operands[i].shift_kind << 5;
7045 if (inst.operands[i].immisreg)
7047 inst.instruction |= SHIFT_BY_REG;
7048 inst.instruction |= inst.operands[i].imm << 8;
7051 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7056 encode_arm_shifter_operand (int i)
7058 if (inst.operands[i].isreg)
7060 inst.instruction |= inst.operands[i].reg;
7061 encode_arm_shift (i);
7065 inst.instruction |= INST_IMMEDIATE;
7066 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7067 inst.instruction |= inst.operands[i].imm;
7071 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7073 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7076 Generate an error if the operand is not a register. */
7077 constraint (!inst.operands[i].isreg,
7078 _("Instruction does not support =N addresses"));
7080 inst.instruction |= inst.operands[i].reg << 16;
7082 if (inst.operands[i].preind)
7086 inst.error = _("instruction does not accept preindexed addressing");
7089 inst.instruction |= PRE_INDEX;
7090 if (inst.operands[i].writeback)
7091 inst.instruction |= WRITE_BACK;
7094 else if (inst.operands[i].postind)
7096 gas_assert (inst.operands[i].writeback);
7098 inst.instruction |= WRITE_BACK;
7100 else /* unindexed - only for coprocessor */
7102 inst.error = _("instruction does not accept unindexed addressing");
7106 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7107 && (((inst.instruction & 0x000f0000) >> 16)
7108 == ((inst.instruction & 0x0000f000) >> 12)))
7109 as_warn ((inst.instruction & LOAD_BIT)
7110 ? _("destination register same as write-back base")
7111 : _("source register same as write-back base"));
7114 /* inst.operands[i] was set up by parse_address. Encode it into an
7115 ARM-format mode 2 load or store instruction. If is_t is true,
7116 reject forms that cannot be used with a T instruction (i.e. not
7119 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7121 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7123 encode_arm_addr_mode_common (i, is_t);
7125 if (inst.operands[i].immisreg)
7127 constraint ((inst.operands[i].imm == REG_PC
7128 || (is_pc && inst.operands[i].writeback)),
7130 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7131 inst.instruction |= inst.operands[i].imm;
7132 if (!inst.operands[i].negative)
7133 inst.instruction |= INDEX_UP;
7134 if (inst.operands[i].shifted)
7136 if (inst.operands[i].shift_kind == SHIFT_RRX)
7137 inst.instruction |= SHIFT_ROR << 5;
7140 inst.instruction |= inst.operands[i].shift_kind << 5;
7141 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7145 else /* immediate offset in inst.reloc */
7147 if (is_pc && !inst.reloc.pc_rel)
7149 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7151 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7152 cannot use PC in addressing.
7153 PC cannot be used in writeback addressing, either. */
7154 constraint ((is_t || inst.operands[i].writeback),
7157 /* Use of PC in str is deprecated for ARMv7. */
7158 if (warn_on_deprecated
7160 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7161 as_warn (_("use of PC in this instruction is deprecated"));
7164 if (inst.reloc.type == BFD_RELOC_UNUSED)
7166 /* Prefer + for zero encoded value. */
7167 if (!inst.operands[i].negative)
7168 inst.instruction |= INDEX_UP;
7169 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7174 /* inst.operands[i] was set up by parse_address. Encode it into an
7175 ARM-format mode 3 load or store instruction. Reject forms that
7176 cannot be used with such instructions. If is_t is true, reject
7177 forms that cannot be used with a T instruction (i.e. not
7180 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7182 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7184 inst.error = _("instruction does not accept scaled register index");
7188 encode_arm_addr_mode_common (i, is_t);
7190 if (inst.operands[i].immisreg)
7192 constraint ((inst.operands[i].imm == REG_PC
7193 || inst.operands[i].reg == REG_PC),
7195 inst.instruction |= inst.operands[i].imm;
7196 if (!inst.operands[i].negative)
7197 inst.instruction |= INDEX_UP;
7199 else /* immediate offset in inst.reloc */
7201 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7202 && inst.operands[i].writeback),
7204 inst.instruction |= HWOFFSET_IMM;
7205 if (inst.reloc.type == BFD_RELOC_UNUSED)
7207 /* Prefer + for zero encoded value. */
7208 if (!inst.operands[i].negative)
7209 inst.instruction |= INDEX_UP;
7211 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7216 /* inst.operands[i] was set up by parse_address. Encode it into an
7217 ARM-format instruction. Reject all forms which cannot be encoded
7218 into a coprocessor load/store instruction. If wb_ok is false,
7219 reject use of writeback; if unind_ok is false, reject use of
7220 unindexed addressing. If reloc_override is not 0, use it instead
7221 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7222 (in which case it is preserved). */
7225 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7227 inst.instruction |= inst.operands[i].reg << 16;
7229 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7231 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7233 gas_assert (!inst.operands[i].writeback);
7236 inst.error = _("instruction does not support unindexed addressing");
7239 inst.instruction |= inst.operands[i].imm;
7240 inst.instruction |= INDEX_UP;
7244 if (inst.operands[i].preind)
7245 inst.instruction |= PRE_INDEX;
7247 if (inst.operands[i].writeback)
7249 if (inst.operands[i].reg == REG_PC)
7251 inst.error = _("pc may not be used with write-back");
7256 inst.error = _("instruction does not support writeback");
7259 inst.instruction |= WRITE_BACK;
7263 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7264 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7265 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7266 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7269 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7271 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7274 /* Prefer + for zero encoded value. */
7275 if (!inst.operands[i].negative)
7276 inst.instruction |= INDEX_UP;
7281 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7282 Determine whether it can be performed with a move instruction; if
7283 it can, convert inst.instruction to that move instruction and
7284 return TRUE; if it can't, convert inst.instruction to a literal-pool
7285 load and return FALSE. If this is not a valid thing to do in the
7286 current context, set inst.error and return TRUE.
7288 inst.operands[i] describes the destination register. */
7291 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7296 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7300 if ((inst.instruction & tbit) == 0)
7302 inst.error = _("invalid pseudo operation");
7305 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7307 inst.error = _("constant expression expected");
7310 if (inst.reloc.exp.X_op == O_constant)
7314 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7316 /* This can be done with a mov(1) instruction. */
7317 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7318 inst.instruction |= inst.reloc.exp.X_add_number;
7324 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7327 /* This can be done with a mov instruction. */
7328 inst.instruction &= LITERAL_MASK;
7329 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7330 inst.instruction |= value & 0xfff;
7334 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7337 /* This can be done with a mvn instruction. */
7338 inst.instruction &= LITERAL_MASK;
7339 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7340 inst.instruction |= value & 0xfff;
7346 if (add_to_lit_pool () == FAIL)
7348 inst.error = _("literal pool insertion failed");
7351 inst.operands[1].reg = REG_PC;
7352 inst.operands[1].isreg = 1;
7353 inst.operands[1].preind = 1;
7354 inst.reloc.pc_rel = 1;
7355 inst.reloc.type = (thumb_p
7356 ? BFD_RELOC_ARM_THUMB_OFFSET
7358 ? BFD_RELOC_ARM_HWLITERAL
7359 : BFD_RELOC_ARM_LITERAL));
7363 /* Functions for instruction encoding, sorted by sub-architecture.
7364 First some generics; their names are taken from the conventional
7365 bit positions for register arguments in ARM format instructions. */
7375 inst.instruction |= inst.operands[0].reg << 12;
7381 inst.instruction |= inst.operands[0].reg << 12;
7382 inst.instruction |= inst.operands[1].reg;
7388 inst.instruction |= inst.operands[0].reg;
7389 inst.instruction |= inst.operands[1].reg << 16;
7395 inst.instruction |= inst.operands[0].reg << 12;
7396 inst.instruction |= inst.operands[1].reg << 16;
7402 inst.instruction |= inst.operands[0].reg << 16;
7403 inst.instruction |= inst.operands[1].reg << 12;
7407 check_obsolete (const arm_feature_set *feature, const char *msg)
7409 if (ARM_CPU_IS_ANY (cpu_variant))
7411 as_warn ("%s", msg);
7414 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7426 unsigned Rn = inst.operands[2].reg;
7427 /* Enforce restrictions on SWP instruction. */
7428 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7430 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7431 _("Rn must not overlap other operands"));
7433 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7435 if (!check_obsolete (&arm_ext_v8,
7436 _("swp{b} use is obsoleted for ARMv8 and later"))
7437 && warn_on_deprecated
7438 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7439 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7442 inst.instruction |= inst.operands[0].reg << 12;
7443 inst.instruction |= inst.operands[1].reg;
7444 inst.instruction |= Rn << 16;
7450 inst.instruction |= inst.operands[0].reg << 12;
7451 inst.instruction |= inst.operands[1].reg << 16;
7452 inst.instruction |= inst.operands[2].reg;
7458 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7459 constraint (((inst.reloc.exp.X_op != O_constant
7460 && inst.reloc.exp.X_op != O_illegal)
7461 || inst.reloc.exp.X_add_number != 0),
7463 inst.instruction |= inst.operands[0].reg;
7464 inst.instruction |= inst.operands[1].reg << 12;
7465 inst.instruction |= inst.operands[2].reg << 16;
7471 inst.instruction |= inst.operands[0].imm;
7477 inst.instruction |= inst.operands[0].reg << 12;
7478 encode_arm_cp_address (1, TRUE, TRUE, 0);
7481 /* ARM instructions, in alphabetical order by function name (except
7482 that wrapper functions appear immediately after the function they
7485 /* This is a pseudo-op of the form "adr rd, label" to be converted
7486 into a relative address of the form "add rd, pc, #label-.-8". */
7491 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7493 /* Frag hacking will turn this into a sub instruction if the offset turns
7494 out to be negative. */
7495 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7496 inst.reloc.pc_rel = 1;
7497 inst.reloc.exp.X_add_number -= 8;
7500 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7501 into a relative address of the form:
7502 add rd, pc, #low(label-.-8)"
7503 add rd, rd, #high(label-.-8)" */
7508 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7510 /* Frag hacking will turn this into a sub instruction if the offset turns
7511 out to be negative. */
7512 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7513 inst.reloc.pc_rel = 1;
7514 inst.size = INSN_SIZE * 2;
7515 inst.reloc.exp.X_add_number -= 8;
7521 if (!inst.operands[1].present)
7522 inst.operands[1].reg = inst.operands[0].reg;
7523 inst.instruction |= inst.operands[0].reg << 12;
7524 inst.instruction |= inst.operands[1].reg << 16;
7525 encode_arm_shifter_operand (2);
7531 if (inst.operands[0].present)
7533 constraint ((inst.instruction & 0xf0) != 0x40
7534 && inst.operands[0].imm > 0xf
7535 && inst.operands[0].imm < 0x0,
7536 _("bad barrier type"));
7537 inst.instruction |= inst.operands[0].imm;
7540 inst.instruction |= 0xf;
7546 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7547 constraint (msb > 32, _("bit-field extends past end of register"));
7548 /* The instruction encoding stores the LSB and MSB,
7549 not the LSB and width. */
7550 inst.instruction |= inst.operands[0].reg << 12;
7551 inst.instruction |= inst.operands[1].imm << 7;
7552 inst.instruction |= (msb - 1) << 16;
7560 /* #0 in second position is alternative syntax for bfc, which is
7561 the same instruction but with REG_PC in the Rm field. */
7562 if (!inst.operands[1].isreg)
7563 inst.operands[1].reg = REG_PC;
7565 msb = inst.operands[2].imm + inst.operands[3].imm;
7566 constraint (msb > 32, _("bit-field extends past end of register"));
7567 /* The instruction encoding stores the LSB and MSB,
7568 not the LSB and width. */
7569 inst.instruction |= inst.operands[0].reg << 12;
7570 inst.instruction |= inst.operands[1].reg;
7571 inst.instruction |= inst.operands[2].imm << 7;
7572 inst.instruction |= (msb - 1) << 16;
7578 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7579 _("bit-field extends past end of register"));
7580 inst.instruction |= inst.operands[0].reg << 12;
7581 inst.instruction |= inst.operands[1].reg;
7582 inst.instruction |= inst.operands[2].imm << 7;
7583 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7586 /* ARM V5 breakpoint instruction (argument parse)
7587 BKPT <16 bit unsigned immediate>
7588 Instruction is not conditional.
7589 The bit pattern given in insns[] has the COND_ALWAYS condition,
7590 and it is an error if the caller tried to override that. */
7595 /* Top 12 of 16 bits to bits 19:8. */
7596 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7598 /* Bottom 4 of 16 bits to bits 3:0. */
7599 inst.instruction |= inst.operands[0].imm & 0xf;
7603 encode_branch (int default_reloc)
7605 if (inst.operands[0].hasreloc)
7607 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7608 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7609 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7610 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7611 ? BFD_RELOC_ARM_PLT32
7612 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7615 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7616 inst.reloc.pc_rel = 1;
7623 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7624 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7627 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7634 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7636 if (inst.cond == COND_ALWAYS)
7637 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7639 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7643 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7646 /* ARM V5 branch-link-exchange instruction (argument parse)
7647 BLX <target_addr> ie BLX(1)
7648 BLX{<condition>} <Rm> ie BLX(2)
7649 Unfortunately, there are two different opcodes for this mnemonic.
7650 So, the insns[].value is not used, and the code here zaps values
7651 into inst.instruction.
7652 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7657 if (inst.operands[0].isreg)
7659 /* Arg is a register; the opcode provided by insns[] is correct.
7660 It is not illegal to do "blx pc", just useless. */
7661 if (inst.operands[0].reg == REG_PC)
7662 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7664 inst.instruction |= inst.operands[0].reg;
7668 /* Arg is an address; this instruction cannot be executed
7669 conditionally, and the opcode must be adjusted.
7670 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7671 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7672 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7673 inst.instruction = 0xfa000000;
7674 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7681 bfd_boolean want_reloc;
7683 if (inst.operands[0].reg == REG_PC)
7684 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7686 inst.instruction |= inst.operands[0].reg;
7687 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7688 it is for ARMv4t or earlier. */
7689 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7690 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7694 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7699 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7703 /* ARM v5TEJ. Jump to Jazelle code. */
7708 if (inst.operands[0].reg == REG_PC)
7709 as_tsktsk (_("use of r15 in bxj is not really useful"));
7711 inst.instruction |= inst.operands[0].reg;
7714 /* Co-processor data operation:
7715 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7716 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7720 inst.instruction |= inst.operands[0].reg << 8;
7721 inst.instruction |= inst.operands[1].imm << 20;
7722 inst.instruction |= inst.operands[2].reg << 12;
7723 inst.instruction |= inst.operands[3].reg << 16;
7724 inst.instruction |= inst.operands[4].reg;
7725 inst.instruction |= inst.operands[5].imm << 5;
7731 inst.instruction |= inst.operands[0].reg << 16;
7732 encode_arm_shifter_operand (1);
7735 /* Transfer between coprocessor and ARM registers.
7736 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7741 No special properties. */
7743 struct deprecated_coproc_regs_s
7750 arm_feature_set deprecated;
7751 arm_feature_set obsoleted;
7752 const char *dep_msg;
7753 const char *obs_msg;
7756 #define DEPR_ACCESS_V8 \
7757 N_("This coprocessor register access is deprecated in ARMv8")
7759 /* Table of all deprecated coprocessor registers. */
7760 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7762 {15, 0, 7, 10, 5, /* CP15DMB. */
7763 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7764 DEPR_ACCESS_V8, NULL},
7765 {15, 0, 7, 10, 4, /* CP15DSB. */
7766 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7767 DEPR_ACCESS_V8, NULL},
7768 {15, 0, 7, 5, 4, /* CP15ISB. */
7769 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7770 DEPR_ACCESS_V8, NULL},
7771 {14, 6, 1, 0, 0, /* TEEHBR. */
7772 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7773 DEPR_ACCESS_V8, NULL},
7774 {14, 6, 0, 0, 0, /* TEECR. */
7775 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7776 DEPR_ACCESS_V8, NULL},
7779 #undef DEPR_ACCESS_V8
7781 static const size_t deprecated_coproc_reg_count =
7782 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7790 Rd = inst.operands[2].reg;
7793 if (inst.instruction == 0xee000010
7794 || inst.instruction == 0xfe000010)
7796 reject_bad_reg (Rd);
7799 constraint (Rd == REG_SP, BAD_SP);
7804 if (inst.instruction == 0xe000010)
7805 constraint (Rd == REG_PC, BAD_PC);
7808 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7810 const struct deprecated_coproc_regs_s *r =
7811 deprecated_coproc_regs + i;
7813 if (inst.operands[0].reg == r->cp
7814 && inst.operands[1].imm == r->opc1
7815 && inst.operands[3].reg == r->crn
7816 && inst.operands[4].reg == r->crm
7817 && inst.operands[5].imm == r->opc2)
7819 if (!check_obsolete (&r->obsoleted, r->obs_msg)
7820 && warn_on_deprecated
7821 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7822 as_warn ("%s", r->dep_msg);
7826 inst.instruction |= inst.operands[0].reg << 8;
7827 inst.instruction |= inst.operands[1].imm << 21;
7828 inst.instruction |= Rd << 12;
7829 inst.instruction |= inst.operands[3].reg << 16;
7830 inst.instruction |= inst.operands[4].reg;
7831 inst.instruction |= inst.operands[5].imm << 5;
7834 /* Transfer between coprocessor register and pair of ARM registers.
7835 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7840 Two XScale instructions are special cases of these:
7842 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7843 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7845 Result unpredictable if Rd or Rn is R15. */
7852 Rd = inst.operands[2].reg;
7853 Rn = inst.operands[3].reg;
7857 reject_bad_reg (Rd);
7858 reject_bad_reg (Rn);
7862 constraint (Rd == REG_PC, BAD_PC);
7863 constraint (Rn == REG_PC, BAD_PC);
7866 inst.instruction |= inst.operands[0].reg << 8;
7867 inst.instruction |= inst.operands[1].imm << 4;
7868 inst.instruction |= Rd << 12;
7869 inst.instruction |= Rn << 16;
7870 inst.instruction |= inst.operands[4].reg;
7876 inst.instruction |= inst.operands[0].imm << 6;
7877 if (inst.operands[1].present)
7879 inst.instruction |= CPSI_MMOD;
7880 inst.instruction |= inst.operands[1].imm;
7887 inst.instruction |= inst.operands[0].imm;
7893 unsigned Rd, Rn, Rm;
7895 Rd = inst.operands[0].reg;
7896 Rn = (inst.operands[1].present
7897 ? inst.operands[1].reg : Rd);
7898 Rm = inst.operands[2].reg;
7900 constraint ((Rd == REG_PC), BAD_PC);
7901 constraint ((Rn == REG_PC), BAD_PC);
7902 constraint ((Rm == REG_PC), BAD_PC);
7904 inst.instruction |= Rd << 16;
7905 inst.instruction |= Rn << 0;
7906 inst.instruction |= Rm << 8;
7912 /* There is no IT instruction in ARM mode. We
7913 process it to do the validation as if in
7914 thumb mode, just in case the code gets
7915 assembled for thumb using the unified syntax. */
7920 set_it_insn_type (IT_INSN);
7921 now_it.mask = (inst.instruction & 0xf) | 0x10;
7922 now_it.cc = inst.operands[0].imm;
7926 /* If there is only one register in the register list,
7927 then return its register number. Otherwise return -1. */
7929 only_one_reg_in_list (int range)
7931 int i = ffs (range) - 1;
7932 return (i > 15 || range != (1 << i)) ? -1 : i;
7936 encode_ldmstm(int from_push_pop_mnem)
7938 int base_reg = inst.operands[0].reg;
7939 int range = inst.operands[1].imm;
7942 inst.instruction |= base_reg << 16;
7943 inst.instruction |= range;
7945 if (inst.operands[1].writeback)
7946 inst.instruction |= LDM_TYPE_2_OR_3;
7948 if (inst.operands[0].writeback)
7950 inst.instruction |= WRITE_BACK;
7951 /* Check for unpredictable uses of writeback. */
7952 if (inst.instruction & LOAD_BIT)
7954 /* Not allowed in LDM type 2. */
7955 if ((inst.instruction & LDM_TYPE_2_OR_3)
7956 && ((range & (1 << REG_PC)) == 0))
7957 as_warn (_("writeback of base register is UNPREDICTABLE"));
7958 /* Only allowed if base reg not in list for other types. */
7959 else if (range & (1 << base_reg))
7960 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7964 /* Not allowed for type 2. */
7965 if (inst.instruction & LDM_TYPE_2_OR_3)
7966 as_warn (_("writeback of base register is UNPREDICTABLE"));
7967 /* Only allowed if base reg not in list, or first in list. */
7968 else if ((range & (1 << base_reg))
7969 && (range & ((1 << base_reg) - 1)))
7970 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7974 /* If PUSH/POP has only one register, then use the A2 encoding. */
7975 one_reg = only_one_reg_in_list (range);
7976 if (from_push_pop_mnem && one_reg >= 0)
7978 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7980 inst.instruction &= A_COND_MASK;
7981 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7982 inst.instruction |= one_reg << 12;
7989 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
7992 /* ARMv5TE load-consecutive (argument parse)
8001 constraint (inst.operands[0].reg % 2 != 0,
8002 _("first transfer register must be even"));
8003 constraint (inst.operands[1].present
8004 && inst.operands[1].reg != inst.operands[0].reg + 1,
8005 _("can only transfer two consecutive registers"));
8006 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8007 constraint (!inst.operands[2].isreg, _("'[' expected"));
8009 if (!inst.operands[1].present)
8010 inst.operands[1].reg = inst.operands[0].reg + 1;
8012 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8013 register and the first register written; we have to diagnose
8014 overlap between the base and the second register written here. */
8016 if (inst.operands[2].reg == inst.operands[1].reg
8017 && (inst.operands[2].writeback || inst.operands[2].postind))
8018 as_warn (_("base register written back, and overlaps "
8019 "second transfer register"));
8021 if (!(inst.instruction & V4_STR_BIT))
8023 /* For an index-register load, the index register must not overlap the
8024 destination (even if not write-back). */
8025 if (inst.operands[2].immisreg
8026 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8027 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8028 as_warn (_("index register overlaps transfer register"));
8030 inst.instruction |= inst.operands[0].reg << 12;
8031 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8037 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8038 || inst.operands[1].postind || inst.operands[1].writeback
8039 || inst.operands[1].immisreg || inst.operands[1].shifted
8040 || inst.operands[1].negative
8041 /* This can arise if the programmer has written
8043 or if they have mistakenly used a register name as the last
8046 It is very difficult to distinguish between these two cases
8047 because "rX" might actually be a label. ie the register
8048 name has been occluded by a symbol of the same name. So we
8049 just generate a general 'bad addressing mode' type error
8050 message and leave it up to the programmer to discover the
8051 true cause and fix their mistake. */
8052 || (inst.operands[1].reg == REG_PC),
8055 constraint (inst.reloc.exp.X_op != O_constant
8056 || inst.reloc.exp.X_add_number != 0,
8057 _("offset must be zero in ARM encoding"));
8059 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8061 inst.instruction |= inst.operands[0].reg << 12;
8062 inst.instruction |= inst.operands[1].reg << 16;
8063 inst.reloc.type = BFD_RELOC_UNUSED;
8069 constraint (inst.operands[0].reg % 2 != 0,
8070 _("even register required"));
8071 constraint (inst.operands[1].present
8072 && inst.operands[1].reg != inst.operands[0].reg + 1,
8073 _("can only load two consecutive registers"));
8074 /* If op 1 were present and equal to PC, this function wouldn't
8075 have been called in the first place. */
8076 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8078 inst.instruction |= inst.operands[0].reg << 12;
8079 inst.instruction |= inst.operands[2].reg << 16;
8082 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8083 which is not a multiple of four is UNPREDICTABLE. */
8085 check_ldr_r15_aligned (void)
8087 constraint (!(inst.operands[1].immisreg)
8088 && (inst.operands[0].reg == REG_PC
8089 && inst.operands[1].reg == REG_PC
8090 && (inst.reloc.exp.X_add_number & 0x3)),
8091 _("ldr to register 15 must be 4-byte alligned"));
8097 inst.instruction |= inst.operands[0].reg << 12;
8098 if (!inst.operands[1].isreg)
8099 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8101 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8102 check_ldr_r15_aligned ();
8108 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8110 if (inst.operands[1].preind)
8112 constraint (inst.reloc.exp.X_op != O_constant
8113 || inst.reloc.exp.X_add_number != 0,
8114 _("this instruction requires a post-indexed address"));
8116 inst.operands[1].preind = 0;
8117 inst.operands[1].postind = 1;
8118 inst.operands[1].writeback = 1;
8120 inst.instruction |= inst.operands[0].reg << 12;
8121 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8124 /* Halfword and signed-byte load/store operations. */
8129 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8130 inst.instruction |= inst.operands[0].reg << 12;
8131 if (!inst.operands[1].isreg)
8132 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8134 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8140 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8142 if (inst.operands[1].preind)
8144 constraint (inst.reloc.exp.X_op != O_constant
8145 || inst.reloc.exp.X_add_number != 0,
8146 _("this instruction requires a post-indexed address"));
8148 inst.operands[1].preind = 0;
8149 inst.operands[1].postind = 1;
8150 inst.operands[1].writeback = 1;
8152 inst.instruction |= inst.operands[0].reg << 12;
8153 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8156 /* Co-processor register load/store.
8157 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8161 inst.instruction |= inst.operands[0].reg << 8;
8162 inst.instruction |= inst.operands[1].reg << 12;
8163 encode_arm_cp_address (2, TRUE, TRUE, 0);
8169 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8170 if (inst.operands[0].reg == inst.operands[1].reg
8171 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8172 && !(inst.instruction & 0x00400000))
8173 as_tsktsk (_("Rd and Rm should be different in mla"));
8175 inst.instruction |= inst.operands[0].reg << 16;
8176 inst.instruction |= inst.operands[1].reg;
8177 inst.instruction |= inst.operands[2].reg << 8;
8178 inst.instruction |= inst.operands[3].reg << 12;
8184 inst.instruction |= inst.operands[0].reg << 12;
8185 encode_arm_shifter_operand (1);
8188 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8195 top = (inst.instruction & 0x00400000) != 0;
8196 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8197 _(":lower16: not allowed this instruction"));
8198 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8199 _(":upper16: not allowed instruction"));
8200 inst.instruction |= inst.operands[0].reg << 12;
8201 if (inst.reloc.type == BFD_RELOC_UNUSED)
8203 imm = inst.reloc.exp.X_add_number;
8204 /* The value is in two pieces: 0:11, 16:19. */
8205 inst.instruction |= (imm & 0x00000fff);
8206 inst.instruction |= (imm & 0x0000f000) << 4;
8210 static void do_vfp_nsyn_opcode (const char *);
8213 do_vfp_nsyn_mrs (void)
8215 if (inst.operands[0].isvec)
8217 if (inst.operands[1].reg != 1)
8218 first_error (_("operand 1 must be FPSCR"));
8219 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8220 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8221 do_vfp_nsyn_opcode ("fmstat");
8223 else if (inst.operands[1].isvec)
8224 do_vfp_nsyn_opcode ("fmrx");
8232 do_vfp_nsyn_msr (void)
8234 if (inst.operands[0].isvec)
8235 do_vfp_nsyn_opcode ("fmxr");
8245 unsigned Rt = inst.operands[0].reg;
8247 if (thumb_mode && inst.operands[0].reg == REG_SP)
8249 inst.error = BAD_SP;
8253 /* APSR_ sets isvec. All other refs to PC are illegal. */
8254 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8256 inst.error = BAD_PC;
8260 switch (inst.operands[1].reg)
8267 inst.instruction |= (inst.operands[1].reg << 16);
8270 first_error (_("operand 1 must be a VFP extension System Register"));
8273 inst.instruction |= (Rt << 12);
8279 unsigned Rt = inst.operands[1].reg;
8282 reject_bad_reg (Rt);
8283 else if (Rt == REG_PC)
8285 inst.error = BAD_PC;
8289 switch (inst.operands[0].reg)
8294 inst.instruction |= (inst.operands[0].reg << 16);
8297 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8300 inst.instruction |= (Rt << 12);
8308 if (do_vfp_nsyn_mrs () == SUCCESS)
8311 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8312 inst.instruction |= inst.operands[0].reg << 12;
8314 if (inst.operands[1].isreg)
8316 br = inst.operands[1].reg;
8317 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8318 as_bad (_("bad register for mrs"));
8322 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8323 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8325 _("'APSR', 'CPSR' or 'SPSR' expected"));
8326 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8329 inst.instruction |= br;
8332 /* Two possible forms:
8333 "{C|S}PSR_<field>, Rm",
8334 "{C|S}PSR_f, #expression". */
8339 if (do_vfp_nsyn_msr () == SUCCESS)
8342 inst.instruction |= inst.operands[0].imm;
8343 if (inst.operands[1].isreg)
8344 inst.instruction |= inst.operands[1].reg;
8347 inst.instruction |= INST_IMMEDIATE;
8348 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8349 inst.reloc.pc_rel = 0;
8356 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8358 if (!inst.operands[2].present)
8359 inst.operands[2].reg = inst.operands[0].reg;
8360 inst.instruction |= inst.operands[0].reg << 16;
8361 inst.instruction |= inst.operands[1].reg;
8362 inst.instruction |= inst.operands[2].reg << 8;
8364 if (inst.operands[0].reg == inst.operands[1].reg
8365 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8366 as_tsktsk (_("Rd and Rm should be different in mul"));
8369 /* Long Multiply Parser
8370 UMULL RdLo, RdHi, Rm, Rs
8371 SMULL RdLo, RdHi, Rm, Rs
8372 UMLAL RdLo, RdHi, Rm, Rs
8373 SMLAL RdLo, RdHi, Rm, Rs. */
8378 inst.instruction |= inst.operands[0].reg << 12;
8379 inst.instruction |= inst.operands[1].reg << 16;
8380 inst.instruction |= inst.operands[2].reg;
8381 inst.instruction |= inst.operands[3].reg << 8;
8383 /* rdhi and rdlo must be different. */
8384 if (inst.operands[0].reg == inst.operands[1].reg)
8385 as_tsktsk (_("rdhi and rdlo must be different"));
8387 /* rdhi, rdlo and rm must all be different before armv6. */
8388 if ((inst.operands[0].reg == inst.operands[2].reg
8389 || inst.operands[1].reg == inst.operands[2].reg)
8390 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8391 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8397 if (inst.operands[0].present
8398 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8400 /* Architectural NOP hints are CPSR sets with no bits selected. */
8401 inst.instruction &= 0xf0000000;
8402 inst.instruction |= 0x0320f000;
8403 if (inst.operands[0].present)
8404 inst.instruction |= inst.operands[0].imm;
8408 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8409 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8410 Condition defaults to COND_ALWAYS.
8411 Error if Rd, Rn or Rm are R15. */
8416 inst.instruction |= inst.operands[0].reg << 12;
8417 inst.instruction |= inst.operands[1].reg << 16;
8418 inst.instruction |= inst.operands[2].reg;
8419 if (inst.operands[3].present)
8420 encode_arm_shift (3);
8423 /* ARM V6 PKHTB (Argument Parse). */
8428 if (!inst.operands[3].present)
8430 /* If the shift specifier is omitted, turn the instruction
8431 into pkhbt rd, rm, rn. */
8432 inst.instruction &= 0xfff00010;
8433 inst.instruction |= inst.operands[0].reg << 12;
8434 inst.instruction |= inst.operands[1].reg;
8435 inst.instruction |= inst.operands[2].reg << 16;
8439 inst.instruction |= inst.operands[0].reg << 12;
8440 inst.instruction |= inst.operands[1].reg << 16;
8441 inst.instruction |= inst.operands[2].reg;
8442 encode_arm_shift (3);
8446 /* ARMv5TE: Preload-Cache
8447 MP Extensions: Preload for write
8451 Syntactically, like LDR with B=1, W=0, L=1. */
8456 constraint (!inst.operands[0].isreg,
8457 _("'[' expected after PLD mnemonic"));
8458 constraint (inst.operands[0].postind,
8459 _("post-indexed expression used in preload instruction"));
8460 constraint (inst.operands[0].writeback,
8461 _("writeback used in preload instruction"));
8462 constraint (!inst.operands[0].preind,
8463 _("unindexed addressing used in preload instruction"));
8464 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8467 /* ARMv7: PLI <addr_mode> */
8471 constraint (!inst.operands[0].isreg,
8472 _("'[' expected after PLI mnemonic"));
8473 constraint (inst.operands[0].postind,
8474 _("post-indexed expression used in preload instruction"));
8475 constraint (inst.operands[0].writeback,
8476 _("writeback used in preload instruction"));
8477 constraint (!inst.operands[0].preind,
8478 _("unindexed addressing used in preload instruction"));
8479 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8480 inst.instruction &= ~PRE_INDEX;
8486 inst.operands[1] = inst.operands[0];
8487 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8488 inst.operands[0].isreg = 1;
8489 inst.operands[0].writeback = 1;
8490 inst.operands[0].reg = REG_SP;
8491 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8494 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8495 word at the specified address and the following word
8497 Unconditionally executed.
8498 Error if Rn is R15. */
8503 inst.instruction |= inst.operands[0].reg << 16;
8504 if (inst.operands[0].writeback)
8505 inst.instruction |= WRITE_BACK;
8508 /* ARM V6 ssat (argument parse). */
8513 inst.instruction |= inst.operands[0].reg << 12;
8514 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8515 inst.instruction |= inst.operands[2].reg;
8517 if (inst.operands[3].present)
8518 encode_arm_shift (3);
8521 /* ARM V6 usat (argument parse). */
8526 inst.instruction |= inst.operands[0].reg << 12;
8527 inst.instruction |= inst.operands[1].imm << 16;
8528 inst.instruction |= inst.operands[2].reg;
8530 if (inst.operands[3].present)
8531 encode_arm_shift (3);
8534 /* ARM V6 ssat16 (argument parse). */
8539 inst.instruction |= inst.operands[0].reg << 12;
8540 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8541 inst.instruction |= inst.operands[2].reg;
8547 inst.instruction |= inst.operands[0].reg << 12;
8548 inst.instruction |= inst.operands[1].imm << 16;
8549 inst.instruction |= inst.operands[2].reg;
8552 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8553 preserving the other bits.
8555 setend <endian_specifier>, where <endian_specifier> is either
8561 if (warn_on_deprecated
8562 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8563 as_warn (_("setend use is deprecated for ARMv8"));
8565 if (inst.operands[0].imm)
8566 inst.instruction |= 0x200;
8572 unsigned int Rm = (inst.operands[1].present
8573 ? inst.operands[1].reg
8574 : inst.operands[0].reg);
8576 inst.instruction |= inst.operands[0].reg << 12;
8577 inst.instruction |= Rm;
8578 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8580 inst.instruction |= inst.operands[2].reg << 8;
8581 inst.instruction |= SHIFT_BY_REG;
8582 /* PR 12854: Error on extraneous shifts. */
8583 constraint (inst.operands[2].shifted,
8584 _("extraneous shift as part of operand to shift insn"));
8587 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8593 inst.reloc.type = BFD_RELOC_ARM_SMC;
8594 inst.reloc.pc_rel = 0;
8600 inst.reloc.type = BFD_RELOC_ARM_HVC;
8601 inst.reloc.pc_rel = 0;
8607 inst.reloc.type = BFD_RELOC_ARM_SWI;
8608 inst.reloc.pc_rel = 0;
8611 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8612 SMLAxy{cond} Rd,Rm,Rs,Rn
8613 SMLAWy{cond} Rd,Rm,Rs,Rn
8614 Error if any register is R15. */
8619 inst.instruction |= inst.operands[0].reg << 16;
8620 inst.instruction |= inst.operands[1].reg;
8621 inst.instruction |= inst.operands[2].reg << 8;
8622 inst.instruction |= inst.operands[3].reg << 12;
8625 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8626 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8627 Error if any register is R15.
8628 Warning if Rdlo == Rdhi. */
8633 inst.instruction |= inst.operands[0].reg << 12;
8634 inst.instruction |= inst.operands[1].reg << 16;
8635 inst.instruction |= inst.operands[2].reg;
8636 inst.instruction |= inst.operands[3].reg << 8;
8638 if (inst.operands[0].reg == inst.operands[1].reg)
8639 as_tsktsk (_("rdhi and rdlo must be different"));
8642 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8643 SMULxy{cond} Rd,Rm,Rs
8644 Error if any register is R15. */
8649 inst.instruction |= inst.operands[0].reg << 16;
8650 inst.instruction |= inst.operands[1].reg;
8651 inst.instruction |= inst.operands[2].reg << 8;
8654 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8655 the same for both ARM and Thumb-2. */
8662 if (inst.operands[0].present)
8664 reg = inst.operands[0].reg;
8665 constraint (reg != REG_SP, _("SRS base register must be r13"));
8670 inst.instruction |= reg << 16;
8671 inst.instruction |= inst.operands[1].imm;
8672 if (inst.operands[0].writeback || inst.operands[1].writeback)
8673 inst.instruction |= WRITE_BACK;
8676 /* ARM V6 strex (argument parse). */
8681 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8682 || inst.operands[2].postind || inst.operands[2].writeback
8683 || inst.operands[2].immisreg || inst.operands[2].shifted
8684 || inst.operands[2].negative
8685 /* See comment in do_ldrex(). */
8686 || (inst.operands[2].reg == REG_PC),
8689 constraint (inst.operands[0].reg == inst.operands[1].reg
8690 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8692 constraint (inst.reloc.exp.X_op != O_constant
8693 || inst.reloc.exp.X_add_number != 0,
8694 _("offset must be zero in ARM encoding"));
8696 inst.instruction |= inst.operands[0].reg << 12;
8697 inst.instruction |= inst.operands[1].reg;
8698 inst.instruction |= inst.operands[2].reg << 16;
8699 inst.reloc.type = BFD_RELOC_UNUSED;
8705 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8706 || inst.operands[2].postind || inst.operands[2].writeback
8707 || inst.operands[2].immisreg || inst.operands[2].shifted
8708 || inst.operands[2].negative,
8711 constraint (inst.operands[0].reg == inst.operands[1].reg
8712 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8720 constraint (inst.operands[1].reg % 2 != 0,
8721 _("even register required"));
8722 constraint (inst.operands[2].present
8723 && inst.operands[2].reg != inst.operands[1].reg + 1,
8724 _("can only store two consecutive registers"));
8725 /* If op 2 were present and equal to PC, this function wouldn't
8726 have been called in the first place. */
8727 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8729 constraint (inst.operands[0].reg == inst.operands[1].reg
8730 || inst.operands[0].reg == inst.operands[1].reg + 1
8731 || inst.operands[0].reg == inst.operands[3].reg,
8734 inst.instruction |= inst.operands[0].reg << 12;
8735 inst.instruction |= inst.operands[1].reg;
8736 inst.instruction |= inst.operands[3].reg << 16;
8743 constraint (inst.operands[0].reg == inst.operands[1].reg
8744 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8752 constraint (inst.operands[0].reg == inst.operands[1].reg
8753 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8758 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8759 extends it to 32-bits, and adds the result to a value in another
8760 register. You can specify a rotation by 0, 8, 16, or 24 bits
8761 before extracting the 16-bit value.
8762 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8763 Condition defaults to COND_ALWAYS.
8764 Error if any register uses R15. */
8769 inst.instruction |= inst.operands[0].reg << 12;
8770 inst.instruction |= inst.operands[1].reg << 16;
8771 inst.instruction |= inst.operands[2].reg;
8772 inst.instruction |= inst.operands[3].imm << 10;
8777 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8778 Condition defaults to COND_ALWAYS.
8779 Error if any register uses R15. */
8784 inst.instruction |= inst.operands[0].reg << 12;
8785 inst.instruction |= inst.operands[1].reg;
8786 inst.instruction |= inst.operands[2].imm << 10;
8789 /* VFP instructions. In a logical order: SP variant first, monad
8790 before dyad, arithmetic then move then load/store. */
8793 do_vfp_sp_monadic (void)
8795 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8796 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8800 do_vfp_sp_dyadic (void)
8802 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8803 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8804 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8808 do_vfp_sp_compare_z (void)
8810 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8814 do_vfp_dp_sp_cvt (void)
8816 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8817 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8821 do_vfp_sp_dp_cvt (void)
8823 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8824 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8828 do_vfp_reg_from_sp (void)
8830 inst.instruction |= inst.operands[0].reg << 12;
8831 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8835 do_vfp_reg2_from_sp2 (void)
8837 constraint (inst.operands[2].imm != 2,
8838 _("only two consecutive VFP SP registers allowed here"));
8839 inst.instruction |= inst.operands[0].reg << 12;
8840 inst.instruction |= inst.operands[1].reg << 16;
8841 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8845 do_vfp_sp_from_reg (void)
8847 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8848 inst.instruction |= inst.operands[1].reg << 12;
8852 do_vfp_sp2_from_reg2 (void)
8854 constraint (inst.operands[0].imm != 2,
8855 _("only two consecutive VFP SP registers allowed here"));
8856 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8857 inst.instruction |= inst.operands[1].reg << 12;
8858 inst.instruction |= inst.operands[2].reg << 16;
8862 do_vfp_sp_ldst (void)
8864 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8865 encode_arm_cp_address (1, FALSE, TRUE, 0);
8869 do_vfp_dp_ldst (void)
8871 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8872 encode_arm_cp_address (1, FALSE, TRUE, 0);
8877 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8879 if (inst.operands[0].writeback)
8880 inst.instruction |= WRITE_BACK;
8882 constraint (ldstm_type != VFP_LDSTMIA,
8883 _("this addressing mode requires base-register writeback"));
8884 inst.instruction |= inst.operands[0].reg << 16;
8885 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8886 inst.instruction |= inst.operands[1].imm;
8890 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8894 if (inst.operands[0].writeback)
8895 inst.instruction |= WRITE_BACK;
8897 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8898 _("this addressing mode requires base-register writeback"));
8900 inst.instruction |= inst.operands[0].reg << 16;
8901 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8903 count = inst.operands[1].imm << 1;
8904 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8907 inst.instruction |= count;
8911 do_vfp_sp_ldstmia (void)
8913 vfp_sp_ldstm (VFP_LDSTMIA);
8917 do_vfp_sp_ldstmdb (void)
8919 vfp_sp_ldstm (VFP_LDSTMDB);
8923 do_vfp_dp_ldstmia (void)
8925 vfp_dp_ldstm (VFP_LDSTMIA);
8929 do_vfp_dp_ldstmdb (void)
8931 vfp_dp_ldstm (VFP_LDSTMDB);
8935 do_vfp_xp_ldstmia (void)
8937 vfp_dp_ldstm (VFP_LDSTMIAX);
8941 do_vfp_xp_ldstmdb (void)
8943 vfp_dp_ldstm (VFP_LDSTMDBX);
8947 do_vfp_dp_rd_rm (void)
8949 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8950 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8954 do_vfp_dp_rn_rd (void)
8956 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8957 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8961 do_vfp_dp_rd_rn (void)
8963 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8964 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8968 do_vfp_dp_rd_rn_rm (void)
8970 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8971 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8972 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8978 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8982 do_vfp_dp_rm_rd_rn (void)
8984 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8985 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8986 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8989 /* VFPv3 instructions. */
8991 do_vfp_sp_const (void)
8993 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8994 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8995 inst.instruction |= (inst.operands[1].imm & 0x0f);
8999 do_vfp_dp_const (void)
9001 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9002 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9003 inst.instruction |= (inst.operands[1].imm & 0x0f);
9007 vfp_conv (int srcsize)
9009 int immbits = srcsize - inst.operands[1].imm;
9011 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9013 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9014 i.e. immbits must be in range 0 - 16. */
9015 inst.error = _("immediate value out of range, expected range [0, 16]");
9018 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9020 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9021 i.e. immbits must be in range 0 - 31. */
9022 inst.error = _("immediate value out of range, expected range [1, 32]");
9026 inst.instruction |= (immbits & 1) << 5;
9027 inst.instruction |= (immbits >> 1);
9031 do_vfp_sp_conv_16 (void)
9033 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9038 do_vfp_dp_conv_16 (void)
9040 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9045 do_vfp_sp_conv_32 (void)
9047 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9052 do_vfp_dp_conv_32 (void)
9054 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9058 /* FPA instructions. Also in a logical order. */
9063 inst.instruction |= inst.operands[0].reg << 16;
9064 inst.instruction |= inst.operands[1].reg;
9068 do_fpa_ldmstm (void)
9070 inst.instruction |= inst.operands[0].reg << 12;
9071 switch (inst.operands[1].imm)
9073 case 1: inst.instruction |= CP_T_X; break;
9074 case 2: inst.instruction |= CP_T_Y; break;
9075 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9080 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9082 /* The instruction specified "ea" or "fd", so we can only accept
9083 [Rn]{!}. The instruction does not really support stacking or
9084 unstacking, so we have to emulate these by setting appropriate
9085 bits and offsets. */
9086 constraint (inst.reloc.exp.X_op != O_constant
9087 || inst.reloc.exp.X_add_number != 0,
9088 _("this instruction does not support indexing"));
9090 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9091 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9093 if (!(inst.instruction & INDEX_UP))
9094 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9096 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9098 inst.operands[2].preind = 0;
9099 inst.operands[2].postind = 1;
9103 encode_arm_cp_address (2, TRUE, TRUE, 0);
9106 /* iWMMXt instructions: strictly in alphabetical order. */
9109 do_iwmmxt_tandorc (void)
9111 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9115 do_iwmmxt_textrc (void)
9117 inst.instruction |= inst.operands[0].reg << 12;
9118 inst.instruction |= inst.operands[1].imm;
9122 do_iwmmxt_textrm (void)
9124 inst.instruction |= inst.operands[0].reg << 12;
9125 inst.instruction |= inst.operands[1].reg << 16;
9126 inst.instruction |= inst.operands[2].imm;
9130 do_iwmmxt_tinsr (void)
9132 inst.instruction |= inst.operands[0].reg << 16;
9133 inst.instruction |= inst.operands[1].reg << 12;
9134 inst.instruction |= inst.operands[2].imm;
9138 do_iwmmxt_tmia (void)
9140 inst.instruction |= inst.operands[0].reg << 5;
9141 inst.instruction |= inst.operands[1].reg;
9142 inst.instruction |= inst.operands[2].reg << 12;
9146 do_iwmmxt_waligni (void)
9148 inst.instruction |= inst.operands[0].reg << 12;
9149 inst.instruction |= inst.operands[1].reg << 16;
9150 inst.instruction |= inst.operands[2].reg;
9151 inst.instruction |= inst.operands[3].imm << 20;
9155 do_iwmmxt_wmerge (void)
9157 inst.instruction |= inst.operands[0].reg << 12;
9158 inst.instruction |= inst.operands[1].reg << 16;
9159 inst.instruction |= inst.operands[2].reg;
9160 inst.instruction |= inst.operands[3].imm << 21;
9164 do_iwmmxt_wmov (void)
9166 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9167 inst.instruction |= inst.operands[0].reg << 12;
9168 inst.instruction |= inst.operands[1].reg << 16;
9169 inst.instruction |= inst.operands[1].reg;
9173 do_iwmmxt_wldstbh (void)
9176 inst.instruction |= inst.operands[0].reg << 12;
9178 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9180 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9181 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9185 do_iwmmxt_wldstw (void)
9187 /* RIWR_RIWC clears .isreg for a control register. */
9188 if (!inst.operands[0].isreg)
9190 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9191 inst.instruction |= 0xf0000000;
9194 inst.instruction |= inst.operands[0].reg << 12;
9195 encode_arm_cp_address (1, TRUE, TRUE, 0);
9199 do_iwmmxt_wldstd (void)
9201 inst.instruction |= inst.operands[0].reg << 12;
9202 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9203 && inst.operands[1].immisreg)
9205 inst.instruction &= ~0x1a000ff;
9206 inst.instruction |= (0xf << 28);
9207 if (inst.operands[1].preind)
9208 inst.instruction |= PRE_INDEX;
9209 if (!inst.operands[1].negative)
9210 inst.instruction |= INDEX_UP;
9211 if (inst.operands[1].writeback)
9212 inst.instruction |= WRITE_BACK;
9213 inst.instruction |= inst.operands[1].reg << 16;
9214 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9215 inst.instruction |= inst.operands[1].imm;
9218 encode_arm_cp_address (1, TRUE, FALSE, 0);
9222 do_iwmmxt_wshufh (void)
9224 inst.instruction |= inst.operands[0].reg << 12;
9225 inst.instruction |= inst.operands[1].reg << 16;
9226 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9227 inst.instruction |= (inst.operands[2].imm & 0x0f);
9231 do_iwmmxt_wzero (void)
9233 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9234 inst.instruction |= inst.operands[0].reg;
9235 inst.instruction |= inst.operands[0].reg << 12;
9236 inst.instruction |= inst.operands[0].reg << 16;
9240 do_iwmmxt_wrwrwr_or_imm5 (void)
9242 if (inst.operands[2].isreg)
9245 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9246 _("immediate operand requires iWMMXt2"));
9248 if (inst.operands[2].imm == 0)
9250 switch ((inst.instruction >> 20) & 0xf)
9256 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9257 inst.operands[2].imm = 16;
9258 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9264 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9265 inst.operands[2].imm = 32;
9266 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9273 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9275 wrn = (inst.instruction >> 16) & 0xf;
9276 inst.instruction &= 0xff0fff0f;
9277 inst.instruction |= wrn;
9278 /* Bail out here; the instruction is now assembled. */
9283 /* Map 32 -> 0, etc. */
9284 inst.operands[2].imm &= 0x1f;
9285 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9289 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9290 operations first, then control, shift, and load/store. */
9292 /* Insns like "foo X,Y,Z". */
9295 do_mav_triple (void)
9297 inst.instruction |= inst.operands[0].reg << 16;
9298 inst.instruction |= inst.operands[1].reg;
9299 inst.instruction |= inst.operands[2].reg << 12;
9302 /* Insns like "foo W,X,Y,Z".
9303 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9308 inst.instruction |= inst.operands[0].reg << 5;
9309 inst.instruction |= inst.operands[1].reg << 12;
9310 inst.instruction |= inst.operands[2].reg << 16;
9311 inst.instruction |= inst.operands[3].reg;
9314 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9318 inst.instruction |= inst.operands[1].reg << 12;
9321 /* Maverick shift immediate instructions.
9322 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9323 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9328 int imm = inst.operands[2].imm;
9330 inst.instruction |= inst.operands[0].reg << 12;
9331 inst.instruction |= inst.operands[1].reg << 16;
9333 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9334 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9335 Bit 4 should be 0. */
9336 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9338 inst.instruction |= imm;
9341 /* XScale instructions. Also sorted arithmetic before move. */
9343 /* Xscale multiply-accumulate (argument parse)
9346 MIAxycc acc0,Rm,Rs. */
9351 inst.instruction |= inst.operands[1].reg;
9352 inst.instruction |= inst.operands[2].reg << 12;
9355 /* Xscale move-accumulator-register (argument parse)
9357 MARcc acc0,RdLo,RdHi. */
9362 inst.instruction |= inst.operands[1].reg << 12;
9363 inst.instruction |= inst.operands[2].reg << 16;
9366 /* Xscale move-register-accumulator (argument parse)
9368 MRAcc RdLo,RdHi,acc0. */
9373 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9374 inst.instruction |= inst.operands[0].reg << 12;
9375 inst.instruction |= inst.operands[1].reg << 16;
9378 /* Encoding functions relevant only to Thumb. */
9380 /* inst.operands[i] is a shifted-register operand; encode
9381 it into inst.instruction in the format used by Thumb32. */
9384 encode_thumb32_shifted_operand (int i)
9386 unsigned int value = inst.reloc.exp.X_add_number;
9387 unsigned int shift = inst.operands[i].shift_kind;
9389 constraint (inst.operands[i].immisreg,
9390 _("shift by register not allowed in thumb mode"));
9391 inst.instruction |= inst.operands[i].reg;
9392 if (shift == SHIFT_RRX)
9393 inst.instruction |= SHIFT_ROR << 4;
9396 constraint (inst.reloc.exp.X_op != O_constant,
9397 _("expression too complex"));
9399 constraint (value > 32
9400 || (value == 32 && (shift == SHIFT_LSL
9401 || shift == SHIFT_ROR)),
9402 _("shift expression is too large"));
9406 else if (value == 32)
9409 inst.instruction |= shift << 4;
9410 inst.instruction |= (value & 0x1c) << 10;
9411 inst.instruction |= (value & 0x03) << 6;
9416 /* inst.operands[i] was set up by parse_address. Encode it into a
9417 Thumb32 format load or store instruction. Reject forms that cannot
9418 be used with such instructions. If is_t is true, reject forms that
9419 cannot be used with a T instruction; if is_d is true, reject forms
9420 that cannot be used with a D instruction. If it is a store insn,
9424 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9426 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9428 constraint (!inst.operands[i].isreg,
9429 _("Instruction does not support =N addresses"));
9431 inst.instruction |= inst.operands[i].reg << 16;
9432 if (inst.operands[i].immisreg)
9434 constraint (is_pc, BAD_PC_ADDRESSING);
9435 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9436 constraint (inst.operands[i].negative,
9437 _("Thumb does not support negative register indexing"));
9438 constraint (inst.operands[i].postind,
9439 _("Thumb does not support register post-indexing"));
9440 constraint (inst.operands[i].writeback,
9441 _("Thumb does not support register indexing with writeback"));
9442 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9443 _("Thumb supports only LSL in shifted register indexing"));
9445 inst.instruction |= inst.operands[i].imm;
9446 if (inst.operands[i].shifted)
9448 constraint (inst.reloc.exp.X_op != O_constant,
9449 _("expression too complex"));
9450 constraint (inst.reloc.exp.X_add_number < 0
9451 || inst.reloc.exp.X_add_number > 3,
9452 _("shift out of range"));
9453 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9455 inst.reloc.type = BFD_RELOC_UNUSED;
9457 else if (inst.operands[i].preind)
9459 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9460 constraint (is_t && inst.operands[i].writeback,
9461 _("cannot use writeback with this instruction"));
9462 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9463 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9467 inst.instruction |= 0x01000000;
9468 if (inst.operands[i].writeback)
9469 inst.instruction |= 0x00200000;
9473 inst.instruction |= 0x00000c00;
9474 if (inst.operands[i].writeback)
9475 inst.instruction |= 0x00000100;
9477 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9479 else if (inst.operands[i].postind)
9481 gas_assert (inst.operands[i].writeback);
9482 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9483 constraint (is_t, _("cannot use post-indexing with this instruction"));
9486 inst.instruction |= 0x00200000;
9488 inst.instruction |= 0x00000900;
9489 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9491 else /* unindexed - only for coprocessor */
9492 inst.error = _("instruction does not accept unindexed addressing");
9495 /* Table of Thumb instructions which exist in both 16- and 32-bit
9496 encodings (the latter only in post-V6T2 cores). The index is the
9497 value used in the insns table below. When there is more than one
9498 possible 16-bit encoding for the instruction, this table always
9500 Also contains several pseudo-instructions used during relaxation. */
9501 #define T16_32_TAB \
9502 X(_adc, 4140, eb400000), \
9503 X(_adcs, 4140, eb500000), \
9504 X(_add, 1c00, eb000000), \
9505 X(_adds, 1c00, eb100000), \
9506 X(_addi, 0000, f1000000), \
9507 X(_addis, 0000, f1100000), \
9508 X(_add_pc,000f, f20f0000), \
9509 X(_add_sp,000d, f10d0000), \
9510 X(_adr, 000f, f20f0000), \
9511 X(_and, 4000, ea000000), \
9512 X(_ands, 4000, ea100000), \
9513 X(_asr, 1000, fa40f000), \
9514 X(_asrs, 1000, fa50f000), \
9515 X(_b, e000, f000b000), \
9516 X(_bcond, d000, f0008000), \
9517 X(_bic, 4380, ea200000), \
9518 X(_bics, 4380, ea300000), \
9519 X(_cmn, 42c0, eb100f00), \
9520 X(_cmp, 2800, ebb00f00), \
9521 X(_cpsie, b660, f3af8400), \
9522 X(_cpsid, b670, f3af8600), \
9523 X(_cpy, 4600, ea4f0000), \
9524 X(_dec_sp,80dd, f1ad0d00), \
9525 X(_eor, 4040, ea800000), \
9526 X(_eors, 4040, ea900000), \
9527 X(_inc_sp,00dd, f10d0d00), \
9528 X(_ldmia, c800, e8900000), \
9529 X(_ldr, 6800, f8500000), \
9530 X(_ldrb, 7800, f8100000), \
9531 X(_ldrh, 8800, f8300000), \
9532 X(_ldrsb, 5600, f9100000), \
9533 X(_ldrsh, 5e00, f9300000), \
9534 X(_ldr_pc,4800, f85f0000), \
9535 X(_ldr_pc2,4800, f85f0000), \
9536 X(_ldr_sp,9800, f85d0000), \
9537 X(_lsl, 0000, fa00f000), \
9538 X(_lsls, 0000, fa10f000), \
9539 X(_lsr, 0800, fa20f000), \
9540 X(_lsrs, 0800, fa30f000), \
9541 X(_mov, 2000, ea4f0000), \
9542 X(_movs, 2000, ea5f0000), \
9543 X(_mul, 4340, fb00f000), \
9544 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9545 X(_mvn, 43c0, ea6f0000), \
9546 X(_mvns, 43c0, ea7f0000), \
9547 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9548 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9549 X(_orr, 4300, ea400000), \
9550 X(_orrs, 4300, ea500000), \
9551 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9552 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9553 X(_rev, ba00, fa90f080), \
9554 X(_rev16, ba40, fa90f090), \
9555 X(_revsh, bac0, fa90f0b0), \
9556 X(_ror, 41c0, fa60f000), \
9557 X(_rors, 41c0, fa70f000), \
9558 X(_sbc, 4180, eb600000), \
9559 X(_sbcs, 4180, eb700000), \
9560 X(_stmia, c000, e8800000), \
9561 X(_str, 6000, f8400000), \
9562 X(_strb, 7000, f8000000), \
9563 X(_strh, 8000, f8200000), \
9564 X(_str_sp,9000, f84d0000), \
9565 X(_sub, 1e00, eba00000), \
9566 X(_subs, 1e00, ebb00000), \
9567 X(_subi, 8000, f1a00000), \
9568 X(_subis, 8000, f1b00000), \
9569 X(_sxtb, b240, fa4ff080), \
9570 X(_sxth, b200, fa0ff080), \
9571 X(_tst, 4200, ea100f00), \
9572 X(_uxtb, b2c0, fa5ff080), \
9573 X(_uxth, b280, fa1ff080), \
9574 X(_nop, bf00, f3af8000), \
9575 X(_yield, bf10, f3af8001), \
9576 X(_wfe, bf20, f3af8002), \
9577 X(_wfi, bf30, f3af8003), \
9578 X(_sev, bf40, f3af8004), \
9579 X(_sevl, bf50, f3af8005)
9581 /* To catch errors in encoding functions, the codes are all offset by
9582 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9583 as 16-bit instructions. */
9584 #define X(a,b,c) T_MNEM##a
9585 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9588 #define X(a,b,c) 0x##b
9589 static const unsigned short thumb_op16[] = { T16_32_TAB };
9590 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9593 #define X(a,b,c) 0x##c
9594 static const unsigned int thumb_op32[] = { T16_32_TAB };
9595 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9596 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9600 /* Thumb instruction encoders, in alphabetical order. */
9605 do_t_add_sub_w (void)
9609 Rd = inst.operands[0].reg;
9610 Rn = inst.operands[1].reg;
9612 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9613 is the SP-{plus,minus}-immediate form of the instruction. */
9615 constraint (Rd == REG_PC, BAD_PC);
9617 reject_bad_reg (Rd);
9619 inst.instruction |= (Rn << 16) | (Rd << 8);
9620 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9623 /* Parse an add or subtract instruction. We get here with inst.instruction
9624 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9631 Rd = inst.operands[0].reg;
9632 Rs = (inst.operands[1].present
9633 ? inst.operands[1].reg /* Rd, Rs, foo */
9634 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9637 set_it_insn_type_last ();
9645 flags = (inst.instruction == T_MNEM_adds
9646 || inst.instruction == T_MNEM_subs);
9648 narrow = !in_it_block ();
9650 narrow = in_it_block ();
9651 if (!inst.operands[2].isreg)
9655 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9657 add = (inst.instruction == T_MNEM_add
9658 || inst.instruction == T_MNEM_adds);
9660 if (inst.size_req != 4)
9662 /* Attempt to use a narrow opcode, with relaxation if
9664 if (Rd == REG_SP && Rs == REG_SP && !flags)
9665 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9666 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9667 opcode = T_MNEM_add_sp;
9668 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9669 opcode = T_MNEM_add_pc;
9670 else if (Rd <= 7 && Rs <= 7 && narrow)
9673 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9675 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9679 inst.instruction = THUMB_OP16(opcode);
9680 inst.instruction |= (Rd << 4) | Rs;
9681 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9682 if (inst.size_req != 2)
9683 inst.relax = opcode;
9686 constraint (inst.size_req == 2, BAD_HIREG);
9688 if (inst.size_req == 4
9689 || (inst.size_req != 2 && !opcode))
9693 constraint (add, BAD_PC);
9694 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9695 _("only SUBS PC, LR, #const allowed"));
9696 constraint (inst.reloc.exp.X_op != O_constant,
9697 _("expression too complex"));
9698 constraint (inst.reloc.exp.X_add_number < 0
9699 || inst.reloc.exp.X_add_number > 0xff,
9700 _("immediate value out of range"));
9701 inst.instruction = T2_SUBS_PC_LR
9702 | inst.reloc.exp.X_add_number;
9703 inst.reloc.type = BFD_RELOC_UNUSED;
9706 else if (Rs == REG_PC)
9708 /* Always use addw/subw. */
9709 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9710 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9714 inst.instruction = THUMB_OP32 (inst.instruction);
9715 inst.instruction = (inst.instruction & 0xe1ffffff)
9718 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9720 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9722 inst.instruction |= Rd << 8;
9723 inst.instruction |= Rs << 16;
9728 unsigned int value = inst.reloc.exp.X_add_number;
9729 unsigned int shift = inst.operands[2].shift_kind;
9731 Rn = inst.operands[2].reg;
9732 /* See if we can do this with a 16-bit instruction. */
9733 if (!inst.operands[2].shifted && inst.size_req != 4)
9735 if (Rd > 7 || Rs > 7 || Rn > 7)
9740 inst.instruction = ((inst.instruction == T_MNEM_adds
9741 || inst.instruction == T_MNEM_add)
9744 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9748 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9750 /* Thumb-1 cores (except v6-M) require at least one high
9751 register in a narrow non flag setting add. */
9752 if (Rd > 7 || Rn > 7
9753 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9754 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9761 inst.instruction = T_OPCODE_ADD_HI;
9762 inst.instruction |= (Rd & 8) << 4;
9763 inst.instruction |= (Rd & 7);
9764 inst.instruction |= Rn << 3;
9770 constraint (Rd == REG_PC, BAD_PC);
9771 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9772 constraint (Rs == REG_PC, BAD_PC);
9773 reject_bad_reg (Rn);
9775 /* If we get here, it can't be done in 16 bits. */
9776 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9777 _("shift must be constant"));
9778 inst.instruction = THUMB_OP32 (inst.instruction);
9779 inst.instruction |= Rd << 8;
9780 inst.instruction |= Rs << 16;
9781 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9782 _("shift value over 3 not allowed in thumb mode"));
9783 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9784 _("only LSL shift allowed in thumb mode"));
9785 encode_thumb32_shifted_operand (2);
9790 constraint (inst.instruction == T_MNEM_adds
9791 || inst.instruction == T_MNEM_subs,
9794 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9796 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9797 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9800 inst.instruction = (inst.instruction == T_MNEM_add
9802 inst.instruction |= (Rd << 4) | Rs;
9803 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9807 Rn = inst.operands[2].reg;
9808 constraint (inst.operands[2].shifted, _("unshifted register required"));
9810 /* We now have Rd, Rs, and Rn set to registers. */
9811 if (Rd > 7 || Rs > 7 || Rn > 7)
9813 /* Can't do this for SUB. */
9814 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9815 inst.instruction = T_OPCODE_ADD_HI;
9816 inst.instruction |= (Rd & 8) << 4;
9817 inst.instruction |= (Rd & 7);
9819 inst.instruction |= Rn << 3;
9821 inst.instruction |= Rs << 3;
9823 constraint (1, _("dest must overlap one source register"));
9827 inst.instruction = (inst.instruction == T_MNEM_add
9828 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9829 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9839 Rd = inst.operands[0].reg;
9840 reject_bad_reg (Rd);
9842 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9844 /* Defer to section relaxation. */
9845 inst.relax = inst.instruction;
9846 inst.instruction = THUMB_OP16 (inst.instruction);
9847 inst.instruction |= Rd << 4;
9849 else if (unified_syntax && inst.size_req != 2)
9851 /* Generate a 32-bit opcode. */
9852 inst.instruction = THUMB_OP32 (inst.instruction);
9853 inst.instruction |= Rd << 8;
9854 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9855 inst.reloc.pc_rel = 1;
9859 /* Generate a 16-bit opcode. */
9860 inst.instruction = THUMB_OP16 (inst.instruction);
9861 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9862 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9863 inst.reloc.pc_rel = 1;
9865 inst.instruction |= Rd << 4;
9869 /* Arithmetic instructions for which there is just one 16-bit
9870 instruction encoding, and it allows only two low registers.
9871 For maximal compatibility with ARM syntax, we allow three register
9872 operands even when Thumb-32 instructions are not available, as long
9873 as the first two are identical. For instance, both "sbc r0,r1" and
9874 "sbc r0,r0,r1" are allowed. */
9880 Rd = inst.operands[0].reg;
9881 Rs = (inst.operands[1].present
9882 ? inst.operands[1].reg /* Rd, Rs, foo */
9883 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9884 Rn = inst.operands[2].reg;
9886 reject_bad_reg (Rd);
9887 reject_bad_reg (Rs);
9888 if (inst.operands[2].isreg)
9889 reject_bad_reg (Rn);
9893 if (!inst.operands[2].isreg)
9895 /* For an immediate, we always generate a 32-bit opcode;
9896 section relaxation will shrink it later if possible. */
9897 inst.instruction = THUMB_OP32 (inst.instruction);
9898 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9899 inst.instruction |= Rd << 8;
9900 inst.instruction |= Rs << 16;
9901 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9907 /* See if we can do this with a 16-bit instruction. */
9908 if (THUMB_SETS_FLAGS (inst.instruction))
9909 narrow = !in_it_block ();
9911 narrow = in_it_block ();
9913 if (Rd > 7 || Rn > 7 || Rs > 7)
9915 if (inst.operands[2].shifted)
9917 if (inst.size_req == 4)
9923 inst.instruction = THUMB_OP16 (inst.instruction);
9924 inst.instruction |= Rd;
9925 inst.instruction |= Rn << 3;
9929 /* If we get here, it can't be done in 16 bits. */
9930 constraint (inst.operands[2].shifted
9931 && inst.operands[2].immisreg,
9932 _("shift must be constant"));
9933 inst.instruction = THUMB_OP32 (inst.instruction);
9934 inst.instruction |= Rd << 8;
9935 inst.instruction |= Rs << 16;
9936 encode_thumb32_shifted_operand (2);
9941 /* On its face this is a lie - the instruction does set the
9942 flags. However, the only supported mnemonic in this mode
9944 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9946 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9947 _("unshifted register required"));
9948 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9949 constraint (Rd != Rs,
9950 _("dest and source1 must be the same register"));
9952 inst.instruction = THUMB_OP16 (inst.instruction);
9953 inst.instruction |= Rd;
9954 inst.instruction |= Rn << 3;
9958 /* Similarly, but for instructions where the arithmetic operation is
9959 commutative, so we can allow either of them to be different from
9960 the destination operand in a 16-bit instruction. For instance, all
9961 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9968 Rd = inst.operands[0].reg;
9969 Rs = (inst.operands[1].present
9970 ? inst.operands[1].reg /* Rd, Rs, foo */
9971 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9972 Rn = inst.operands[2].reg;
9974 reject_bad_reg (Rd);
9975 reject_bad_reg (Rs);
9976 if (inst.operands[2].isreg)
9977 reject_bad_reg (Rn);
9981 if (!inst.operands[2].isreg)
9983 /* For an immediate, we always generate a 32-bit opcode;
9984 section relaxation will shrink it later if possible. */
9985 inst.instruction = THUMB_OP32 (inst.instruction);
9986 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9987 inst.instruction |= Rd << 8;
9988 inst.instruction |= Rs << 16;
9989 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9995 /* See if we can do this with a 16-bit instruction. */
9996 if (THUMB_SETS_FLAGS (inst.instruction))
9997 narrow = !in_it_block ();
9999 narrow = in_it_block ();
10001 if (Rd > 7 || Rn > 7 || Rs > 7)
10003 if (inst.operands[2].shifted)
10005 if (inst.size_req == 4)
10012 inst.instruction = THUMB_OP16 (inst.instruction);
10013 inst.instruction |= Rd;
10014 inst.instruction |= Rn << 3;
10019 inst.instruction = THUMB_OP16 (inst.instruction);
10020 inst.instruction |= Rd;
10021 inst.instruction |= Rs << 3;
10026 /* If we get here, it can't be done in 16 bits. */
10027 constraint (inst.operands[2].shifted
10028 && inst.operands[2].immisreg,
10029 _("shift must be constant"));
10030 inst.instruction = THUMB_OP32 (inst.instruction);
10031 inst.instruction |= Rd << 8;
10032 inst.instruction |= Rs << 16;
10033 encode_thumb32_shifted_operand (2);
10038 /* On its face this is a lie - the instruction does set the
10039 flags. However, the only supported mnemonic in this mode
10040 says it doesn't. */
10041 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10043 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10044 _("unshifted register required"));
10045 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10047 inst.instruction = THUMB_OP16 (inst.instruction);
10048 inst.instruction |= Rd;
10051 inst.instruction |= Rn << 3;
10053 inst.instruction |= Rs << 3;
10055 constraint (1, _("dest must overlap one source register"));
10060 do_t_barrier (void)
10062 if (inst.operands[0].present)
10064 constraint ((inst.instruction & 0xf0) != 0x40
10065 && inst.operands[0].imm > 0xf
10066 && inst.operands[0].imm < 0x0,
10067 _("bad barrier type"));
10068 inst.instruction |= inst.operands[0].imm;
10071 inst.instruction |= 0xf;
10078 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10079 constraint (msb > 32, _("bit-field extends past end of register"));
10080 /* The instruction encoding stores the LSB and MSB,
10081 not the LSB and width. */
10082 Rd = inst.operands[0].reg;
10083 reject_bad_reg (Rd);
10084 inst.instruction |= Rd << 8;
10085 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10086 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10087 inst.instruction |= msb - 1;
10096 Rd = inst.operands[0].reg;
10097 reject_bad_reg (Rd);
10099 /* #0 in second position is alternative syntax for bfc, which is
10100 the same instruction but with REG_PC in the Rm field. */
10101 if (!inst.operands[1].isreg)
10105 Rn = inst.operands[1].reg;
10106 reject_bad_reg (Rn);
10109 msb = inst.operands[2].imm + inst.operands[3].imm;
10110 constraint (msb > 32, _("bit-field extends past end of register"));
10111 /* The instruction encoding stores the LSB and MSB,
10112 not the LSB and width. */
10113 inst.instruction |= Rd << 8;
10114 inst.instruction |= Rn << 16;
10115 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10116 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10117 inst.instruction |= msb - 1;
10125 Rd = inst.operands[0].reg;
10126 Rn = inst.operands[1].reg;
10128 reject_bad_reg (Rd);
10129 reject_bad_reg (Rn);
10131 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10132 _("bit-field extends past end of register"));
10133 inst.instruction |= Rd << 8;
10134 inst.instruction |= Rn << 16;
10135 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10136 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10137 inst.instruction |= inst.operands[3].imm - 1;
10140 /* ARM V5 Thumb BLX (argument parse)
10141 BLX <target_addr> which is BLX(1)
10142 BLX <Rm> which is BLX(2)
10143 Unfortunately, there are two different opcodes for this mnemonic.
10144 So, the insns[].value is not used, and the code here zaps values
10145 into inst.instruction.
10147 ??? How to take advantage of the additional two bits of displacement
10148 available in Thumb32 mode? Need new relocation? */
10153 set_it_insn_type_last ();
10155 if (inst.operands[0].isreg)
10157 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10158 /* We have a register, so this is BLX(2). */
10159 inst.instruction |= inst.operands[0].reg << 3;
10163 /* No register. This must be BLX(1). */
10164 inst.instruction = 0xf000e800;
10165 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10177 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10179 if (in_it_block ())
10181 /* Conditional branches inside IT blocks are encoded as unconditional
10183 cond = COND_ALWAYS;
10188 if (cond != COND_ALWAYS)
10189 opcode = T_MNEM_bcond;
10191 opcode = inst.instruction;
10194 && (inst.size_req == 4
10195 || (inst.size_req != 2
10196 && (inst.operands[0].hasreloc
10197 || inst.reloc.exp.X_op == O_constant))))
10199 inst.instruction = THUMB_OP32(opcode);
10200 if (cond == COND_ALWAYS)
10201 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10204 gas_assert (cond != 0xF);
10205 inst.instruction |= cond << 22;
10206 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10211 inst.instruction = THUMB_OP16(opcode);
10212 if (cond == COND_ALWAYS)
10213 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10216 inst.instruction |= cond << 8;
10217 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10219 /* Allow section relaxation. */
10220 if (unified_syntax && inst.size_req != 2)
10221 inst.relax = opcode;
10223 inst.reloc.type = reloc;
10224 inst.reloc.pc_rel = 1;
10227 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10228 between the two is the maximum immediate allowed - which is passed in
10231 do_t_bkpt_hlt1 (int range)
10233 constraint (inst.cond != COND_ALWAYS,
10234 _("instruction is always unconditional"));
10235 if (inst.operands[0].present)
10237 constraint (inst.operands[0].imm > range,
10238 _("immediate value out of range"));
10239 inst.instruction |= inst.operands[0].imm;
10242 set_it_insn_type (NEUTRAL_IT_INSN);
10248 do_t_bkpt_hlt1 (63);
10254 do_t_bkpt_hlt1 (255);
10258 do_t_branch23 (void)
10260 set_it_insn_type_last ();
10261 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10263 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10264 this file. We used to simply ignore the PLT reloc type here --
10265 the branch encoding is now needed to deal with TLSCALL relocs.
10266 So if we see a PLT reloc now, put it back to how it used to be to
10267 keep the preexisting behaviour. */
10268 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10269 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10271 #if defined(OBJ_COFF)
10272 /* If the destination of the branch is a defined symbol which does not have
10273 the THUMB_FUNC attribute, then we must be calling a function which has
10274 the (interfacearm) attribute. We look for the Thumb entry point to that
10275 function and change the branch to refer to that function instead. */
10276 if ( inst.reloc.exp.X_op == O_symbol
10277 && inst.reloc.exp.X_add_symbol != NULL
10278 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10279 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10280 inst.reloc.exp.X_add_symbol =
10281 find_real_start (inst.reloc.exp.X_add_symbol);
10288 set_it_insn_type_last ();
10289 inst.instruction |= inst.operands[0].reg << 3;
10290 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10291 should cause the alignment to be checked once it is known. This is
10292 because BX PC only works if the instruction is word aligned. */
10300 set_it_insn_type_last ();
10301 Rm = inst.operands[0].reg;
10302 reject_bad_reg (Rm);
10303 inst.instruction |= Rm << 16;
10312 Rd = inst.operands[0].reg;
10313 Rm = inst.operands[1].reg;
10315 reject_bad_reg (Rd);
10316 reject_bad_reg (Rm);
10318 inst.instruction |= Rd << 8;
10319 inst.instruction |= Rm << 16;
10320 inst.instruction |= Rm;
10326 set_it_insn_type (OUTSIDE_IT_INSN);
10327 inst.instruction |= inst.operands[0].imm;
10333 set_it_insn_type (OUTSIDE_IT_INSN);
10335 && (inst.operands[1].present || inst.size_req == 4)
10336 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10338 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10339 inst.instruction = 0xf3af8000;
10340 inst.instruction |= imod << 9;
10341 inst.instruction |= inst.operands[0].imm << 5;
10342 if (inst.operands[1].present)
10343 inst.instruction |= 0x100 | inst.operands[1].imm;
10347 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10348 && (inst.operands[0].imm & 4),
10349 _("selected processor does not support 'A' form "
10350 "of this instruction"));
10351 constraint (inst.operands[1].present || inst.size_req == 4,
10352 _("Thumb does not support the 2-argument "
10353 "form of this instruction"));
10354 inst.instruction |= inst.operands[0].imm;
10358 /* THUMB CPY instruction (argument parse). */
10363 if (inst.size_req == 4)
10365 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10366 inst.instruction |= inst.operands[0].reg << 8;
10367 inst.instruction |= inst.operands[1].reg;
10371 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10372 inst.instruction |= (inst.operands[0].reg & 0x7);
10373 inst.instruction |= inst.operands[1].reg << 3;
10380 set_it_insn_type (OUTSIDE_IT_INSN);
10381 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10382 inst.instruction |= inst.operands[0].reg;
10383 inst.reloc.pc_rel = 1;
10384 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10390 inst.instruction |= inst.operands[0].imm;
10396 unsigned Rd, Rn, Rm;
10398 Rd = inst.operands[0].reg;
10399 Rn = (inst.operands[1].present
10400 ? inst.operands[1].reg : Rd);
10401 Rm = inst.operands[2].reg;
10403 reject_bad_reg (Rd);
10404 reject_bad_reg (Rn);
10405 reject_bad_reg (Rm);
10407 inst.instruction |= Rd << 8;
10408 inst.instruction |= Rn << 16;
10409 inst.instruction |= Rm;
10415 if (unified_syntax && inst.size_req == 4)
10416 inst.instruction = THUMB_OP32 (inst.instruction);
10418 inst.instruction = THUMB_OP16 (inst.instruction);
10424 unsigned int cond = inst.operands[0].imm;
10426 set_it_insn_type (IT_INSN);
10427 now_it.mask = (inst.instruction & 0xf) | 0x10;
10429 now_it.warn_deprecated = FALSE;
10431 /* If the condition is a negative condition, invert the mask. */
10432 if ((cond & 0x1) == 0x0)
10434 unsigned int mask = inst.instruction & 0x000f;
10436 if ((mask & 0x7) == 0)
10438 /* No conversion needed. */
10439 now_it.block_length = 1;
10441 else if ((mask & 0x3) == 0)
10444 now_it.block_length = 2;
10446 else if ((mask & 0x1) == 0)
10449 now_it.block_length = 3;
10454 now_it.block_length = 4;
10457 inst.instruction &= 0xfff0;
10458 inst.instruction |= mask;
10461 inst.instruction |= cond << 4;
10464 /* Helper function used for both push/pop and ldm/stm. */
10466 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10470 load = (inst.instruction & (1 << 20)) != 0;
10472 if (mask & (1 << 13))
10473 inst.error = _("SP not allowed in register list");
10475 if ((mask & (1 << base)) != 0
10477 inst.error = _("having the base register in the register list when "
10478 "using write back is UNPREDICTABLE");
10482 if (mask & (1 << 15))
10484 if (mask & (1 << 14))
10485 inst.error = _("LR and PC should not both be in register list");
10487 set_it_insn_type_last ();
10492 if (mask & (1 << 15))
10493 inst.error = _("PC not allowed in register list");
10496 if ((mask & (mask - 1)) == 0)
10498 /* Single register transfers implemented as str/ldr. */
10501 if (inst.instruction & (1 << 23))
10502 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10504 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10508 if (inst.instruction & (1 << 23))
10509 inst.instruction = 0x00800000; /* ia -> [base] */
10511 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10514 inst.instruction |= 0xf8400000;
10516 inst.instruction |= 0x00100000;
10518 mask = ffs (mask) - 1;
10521 else if (writeback)
10522 inst.instruction |= WRITE_BACK;
10524 inst.instruction |= mask;
10525 inst.instruction |= base << 16;
10531 /* This really doesn't seem worth it. */
10532 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10533 _("expression too complex"));
10534 constraint (inst.operands[1].writeback,
10535 _("Thumb load/store multiple does not support {reglist}^"));
10537 if (unified_syntax)
10539 bfd_boolean narrow;
10543 /* See if we can use a 16-bit instruction. */
10544 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10545 && inst.size_req != 4
10546 && !(inst.operands[1].imm & ~0xff))
10548 mask = 1 << inst.operands[0].reg;
10550 if (inst.operands[0].reg <= 7)
10552 if (inst.instruction == T_MNEM_stmia
10553 ? inst.operands[0].writeback
10554 : (inst.operands[0].writeback
10555 == !(inst.operands[1].imm & mask)))
10557 if (inst.instruction == T_MNEM_stmia
10558 && (inst.operands[1].imm & mask)
10559 && (inst.operands[1].imm & (mask - 1)))
10560 as_warn (_("value stored for r%d is UNKNOWN"),
10561 inst.operands[0].reg);
10563 inst.instruction = THUMB_OP16 (inst.instruction);
10564 inst.instruction |= inst.operands[0].reg << 8;
10565 inst.instruction |= inst.operands[1].imm;
10568 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10570 /* This means 1 register in reg list one of 3 situations:
10571 1. Instruction is stmia, but without writeback.
10572 2. lmdia without writeback, but with Rn not in
10574 3. ldmia with writeback, but with Rn in reglist.
10575 Case 3 is UNPREDICTABLE behaviour, so we handle
10576 case 1 and 2 which can be converted into a 16-bit
10577 str or ldr. The SP cases are handled below. */
10578 unsigned long opcode;
10579 /* First, record an error for Case 3. */
10580 if (inst.operands[1].imm & mask
10581 && inst.operands[0].writeback)
10583 _("having the base register in the register list when "
10584 "using write back is UNPREDICTABLE");
10586 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10588 inst.instruction = THUMB_OP16 (opcode);
10589 inst.instruction |= inst.operands[0].reg << 3;
10590 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10594 else if (inst.operands[0] .reg == REG_SP)
10596 if (inst.operands[0].writeback)
10599 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10600 ? T_MNEM_push : T_MNEM_pop);
10601 inst.instruction |= inst.operands[1].imm;
10604 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10607 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10608 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10609 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10617 if (inst.instruction < 0xffff)
10618 inst.instruction = THUMB_OP32 (inst.instruction);
10620 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10621 inst.operands[0].writeback);
10626 constraint (inst.operands[0].reg > 7
10627 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10628 constraint (inst.instruction != T_MNEM_ldmia
10629 && inst.instruction != T_MNEM_stmia,
10630 _("Thumb-2 instruction only valid in unified syntax"));
10631 if (inst.instruction == T_MNEM_stmia)
10633 if (!inst.operands[0].writeback)
10634 as_warn (_("this instruction will write back the base register"));
10635 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10636 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10637 as_warn (_("value stored for r%d is UNKNOWN"),
10638 inst.operands[0].reg);
10642 if (!inst.operands[0].writeback
10643 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10644 as_warn (_("this instruction will write back the base register"));
10645 else if (inst.operands[0].writeback
10646 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10647 as_warn (_("this instruction will not write back the base register"));
10650 inst.instruction = THUMB_OP16 (inst.instruction);
10651 inst.instruction |= inst.operands[0].reg << 8;
10652 inst.instruction |= inst.operands[1].imm;
10659 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10660 || inst.operands[1].postind || inst.operands[1].writeback
10661 || inst.operands[1].immisreg || inst.operands[1].shifted
10662 || inst.operands[1].negative,
10665 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10667 inst.instruction |= inst.operands[0].reg << 12;
10668 inst.instruction |= inst.operands[1].reg << 16;
10669 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10675 if (!inst.operands[1].present)
10677 constraint (inst.operands[0].reg == REG_LR,
10678 _("r14 not allowed as first register "
10679 "when second register is omitted"));
10680 inst.operands[1].reg = inst.operands[0].reg + 1;
10682 constraint (inst.operands[0].reg == inst.operands[1].reg,
10685 inst.instruction |= inst.operands[0].reg << 12;
10686 inst.instruction |= inst.operands[1].reg << 8;
10687 inst.instruction |= inst.operands[2].reg << 16;
10693 unsigned long opcode;
10696 if (inst.operands[0].isreg
10697 && !inst.operands[0].preind
10698 && inst.operands[0].reg == REG_PC)
10699 set_it_insn_type_last ();
10701 opcode = inst.instruction;
10702 if (unified_syntax)
10704 if (!inst.operands[1].isreg)
10706 if (opcode <= 0xffff)
10707 inst.instruction = THUMB_OP32 (opcode);
10708 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10711 if (inst.operands[1].isreg
10712 && !inst.operands[1].writeback
10713 && !inst.operands[1].shifted && !inst.operands[1].postind
10714 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10715 && opcode <= 0xffff
10716 && inst.size_req != 4)
10718 /* Insn may have a 16-bit form. */
10719 Rn = inst.operands[1].reg;
10720 if (inst.operands[1].immisreg)
10722 inst.instruction = THUMB_OP16 (opcode);
10724 if (Rn <= 7 && inst.operands[1].imm <= 7)
10726 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10727 reject_bad_reg (inst.operands[1].imm);
10729 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10730 && opcode != T_MNEM_ldrsb)
10731 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10732 || (Rn == REG_SP && opcode == T_MNEM_str))
10739 if (inst.reloc.pc_rel)
10740 opcode = T_MNEM_ldr_pc2;
10742 opcode = T_MNEM_ldr_pc;
10746 if (opcode == T_MNEM_ldr)
10747 opcode = T_MNEM_ldr_sp;
10749 opcode = T_MNEM_str_sp;
10751 inst.instruction = inst.operands[0].reg << 8;
10755 inst.instruction = inst.operands[0].reg;
10756 inst.instruction |= inst.operands[1].reg << 3;
10758 inst.instruction |= THUMB_OP16 (opcode);
10759 if (inst.size_req == 2)
10760 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10762 inst.relax = opcode;
10766 /* Definitely a 32-bit variant. */
10768 /* Warning for Erratum 752419. */
10769 if (opcode == T_MNEM_ldr
10770 && inst.operands[0].reg == REG_SP
10771 && inst.operands[1].writeback == 1
10772 && !inst.operands[1].immisreg)
10774 if (no_cpu_selected ()
10775 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10776 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10777 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10778 as_warn (_("This instruction may be unpredictable "
10779 "if executed on M-profile cores "
10780 "with interrupts enabled."));
10783 /* Do some validations regarding addressing modes. */
10784 if (inst.operands[1].immisreg)
10785 reject_bad_reg (inst.operands[1].imm);
10787 constraint (inst.operands[1].writeback == 1
10788 && inst.operands[0].reg == inst.operands[1].reg,
10791 inst.instruction = THUMB_OP32 (opcode);
10792 inst.instruction |= inst.operands[0].reg << 12;
10793 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10794 check_ldr_r15_aligned ();
10798 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10800 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10802 /* Only [Rn,Rm] is acceptable. */
10803 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10804 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10805 || inst.operands[1].postind || inst.operands[1].shifted
10806 || inst.operands[1].negative,
10807 _("Thumb does not support this addressing mode"));
10808 inst.instruction = THUMB_OP16 (inst.instruction);
10812 inst.instruction = THUMB_OP16 (inst.instruction);
10813 if (!inst.operands[1].isreg)
10814 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10817 constraint (!inst.operands[1].preind
10818 || inst.operands[1].shifted
10819 || inst.operands[1].writeback,
10820 _("Thumb does not support this addressing mode"));
10821 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10823 constraint (inst.instruction & 0x0600,
10824 _("byte or halfword not valid for base register"));
10825 constraint (inst.operands[1].reg == REG_PC
10826 && !(inst.instruction & THUMB_LOAD_BIT),
10827 _("r15 based store not allowed"));
10828 constraint (inst.operands[1].immisreg,
10829 _("invalid base register for register offset"));
10831 if (inst.operands[1].reg == REG_PC)
10832 inst.instruction = T_OPCODE_LDR_PC;
10833 else if (inst.instruction & THUMB_LOAD_BIT)
10834 inst.instruction = T_OPCODE_LDR_SP;
10836 inst.instruction = T_OPCODE_STR_SP;
10838 inst.instruction |= inst.operands[0].reg << 8;
10839 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10843 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10844 if (!inst.operands[1].immisreg)
10846 /* Immediate offset. */
10847 inst.instruction |= inst.operands[0].reg;
10848 inst.instruction |= inst.operands[1].reg << 3;
10849 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10853 /* Register offset. */
10854 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10855 constraint (inst.operands[1].negative,
10856 _("Thumb does not support this addressing mode"));
10859 switch (inst.instruction)
10861 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10862 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10863 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10864 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10865 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10866 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10867 case 0x5600 /* ldrsb */:
10868 case 0x5e00 /* ldrsh */: break;
10872 inst.instruction |= inst.operands[0].reg;
10873 inst.instruction |= inst.operands[1].reg << 3;
10874 inst.instruction |= inst.operands[1].imm << 6;
10880 if (!inst.operands[1].present)
10882 inst.operands[1].reg = inst.operands[0].reg + 1;
10883 constraint (inst.operands[0].reg == REG_LR,
10884 _("r14 not allowed here"));
10885 constraint (inst.operands[0].reg == REG_R12,
10886 _("r12 not allowed here"));
10889 if (inst.operands[2].writeback
10890 && (inst.operands[0].reg == inst.operands[2].reg
10891 || inst.operands[1].reg == inst.operands[2].reg))
10892 as_warn (_("base register written back, and overlaps "
10893 "one of transfer registers"));
10895 inst.instruction |= inst.operands[0].reg << 12;
10896 inst.instruction |= inst.operands[1].reg << 8;
10897 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10903 inst.instruction |= inst.operands[0].reg << 12;
10904 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10910 unsigned Rd, Rn, Rm, Ra;
10912 Rd = inst.operands[0].reg;
10913 Rn = inst.operands[1].reg;
10914 Rm = inst.operands[2].reg;
10915 Ra = inst.operands[3].reg;
10917 reject_bad_reg (Rd);
10918 reject_bad_reg (Rn);
10919 reject_bad_reg (Rm);
10920 reject_bad_reg (Ra);
10922 inst.instruction |= Rd << 8;
10923 inst.instruction |= Rn << 16;
10924 inst.instruction |= Rm;
10925 inst.instruction |= Ra << 12;
10931 unsigned RdLo, RdHi, Rn, Rm;
10933 RdLo = inst.operands[0].reg;
10934 RdHi = inst.operands[1].reg;
10935 Rn = inst.operands[2].reg;
10936 Rm = inst.operands[3].reg;
10938 reject_bad_reg (RdLo);
10939 reject_bad_reg (RdHi);
10940 reject_bad_reg (Rn);
10941 reject_bad_reg (Rm);
10943 inst.instruction |= RdLo << 12;
10944 inst.instruction |= RdHi << 8;
10945 inst.instruction |= Rn << 16;
10946 inst.instruction |= Rm;
10950 do_t_mov_cmp (void)
10954 Rn = inst.operands[0].reg;
10955 Rm = inst.operands[1].reg;
10958 set_it_insn_type_last ();
10960 if (unified_syntax)
10962 int r0off = (inst.instruction == T_MNEM_mov
10963 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10964 unsigned long opcode;
10965 bfd_boolean narrow;
10966 bfd_boolean low_regs;
10968 low_regs = (Rn <= 7 && Rm <= 7);
10969 opcode = inst.instruction;
10970 if (in_it_block ())
10971 narrow = opcode != T_MNEM_movs;
10973 narrow = opcode != T_MNEM_movs || low_regs;
10974 if (inst.size_req == 4
10975 || inst.operands[1].shifted)
10978 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10979 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10980 && !inst.operands[1].shifted
10984 inst.instruction = T2_SUBS_PC_LR;
10988 if (opcode == T_MNEM_cmp)
10990 constraint (Rn == REG_PC, BAD_PC);
10993 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10995 warn_deprecated_sp (Rm);
10996 /* R15 was documented as a valid choice for Rm in ARMv6,
10997 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10998 tools reject R15, so we do too. */
10999 constraint (Rm == REG_PC, BAD_PC);
11002 reject_bad_reg (Rm);
11004 else if (opcode == T_MNEM_mov
11005 || opcode == T_MNEM_movs)
11007 if (inst.operands[1].isreg)
11009 if (opcode == T_MNEM_movs)
11011 reject_bad_reg (Rn);
11012 reject_bad_reg (Rm);
11016 /* This is mov.n. */
11017 if ((Rn == REG_SP || Rn == REG_PC)
11018 && (Rm == REG_SP || Rm == REG_PC))
11020 as_warn (_("Use of r%u as a source register is "
11021 "deprecated when r%u is the destination "
11022 "register."), Rm, Rn);
11027 /* This is mov.w. */
11028 constraint (Rn == REG_PC, BAD_PC);
11029 constraint (Rm == REG_PC, BAD_PC);
11030 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11034 reject_bad_reg (Rn);
11037 if (!inst.operands[1].isreg)
11039 /* Immediate operand. */
11040 if (!in_it_block () && opcode == T_MNEM_mov)
11042 if (low_regs && narrow)
11044 inst.instruction = THUMB_OP16 (opcode);
11045 inst.instruction |= Rn << 8;
11046 if (inst.size_req == 2)
11047 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11049 inst.relax = opcode;
11053 inst.instruction = THUMB_OP32 (inst.instruction);
11054 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11055 inst.instruction |= Rn << r0off;
11056 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11059 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11060 && (inst.instruction == T_MNEM_mov
11061 || inst.instruction == T_MNEM_movs))
11063 /* Register shifts are encoded as separate shift instructions. */
11064 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11066 if (in_it_block ())
11071 if (inst.size_req == 4)
11074 if (!low_regs || inst.operands[1].imm > 7)
11080 switch (inst.operands[1].shift_kind)
11083 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11086 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11089 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11092 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11098 inst.instruction = opcode;
11101 inst.instruction |= Rn;
11102 inst.instruction |= inst.operands[1].imm << 3;
11107 inst.instruction |= CONDS_BIT;
11109 inst.instruction |= Rn << 8;
11110 inst.instruction |= Rm << 16;
11111 inst.instruction |= inst.operands[1].imm;
11116 /* Some mov with immediate shift have narrow variants.
11117 Register shifts are handled above. */
11118 if (low_regs && inst.operands[1].shifted
11119 && (inst.instruction == T_MNEM_mov
11120 || inst.instruction == T_MNEM_movs))
11122 if (in_it_block ())
11123 narrow = (inst.instruction == T_MNEM_mov);
11125 narrow = (inst.instruction == T_MNEM_movs);
11130 switch (inst.operands[1].shift_kind)
11132 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11133 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11134 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11135 default: narrow = FALSE; break;
11141 inst.instruction |= Rn;
11142 inst.instruction |= Rm << 3;
11143 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11147 inst.instruction = THUMB_OP32 (inst.instruction);
11148 inst.instruction |= Rn << r0off;
11149 encode_thumb32_shifted_operand (1);
11153 switch (inst.instruction)
11156 /* In v4t or v5t a move of two lowregs produces unpredictable
11157 results. Don't allow this. */
11160 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11161 "MOV Rd, Rs with two low registers is not "
11162 "permitted on this architecture");
11163 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11167 inst.instruction = T_OPCODE_MOV_HR;
11168 inst.instruction |= (Rn & 0x8) << 4;
11169 inst.instruction |= (Rn & 0x7);
11170 inst.instruction |= Rm << 3;
11174 /* We know we have low registers at this point.
11175 Generate LSLS Rd, Rs, #0. */
11176 inst.instruction = T_OPCODE_LSL_I;
11177 inst.instruction |= Rn;
11178 inst.instruction |= Rm << 3;
11184 inst.instruction = T_OPCODE_CMP_LR;
11185 inst.instruction |= Rn;
11186 inst.instruction |= Rm << 3;
11190 inst.instruction = T_OPCODE_CMP_HR;
11191 inst.instruction |= (Rn & 0x8) << 4;
11192 inst.instruction |= (Rn & 0x7);
11193 inst.instruction |= Rm << 3;
11200 inst.instruction = THUMB_OP16 (inst.instruction);
11202 /* PR 10443: Do not silently ignore shifted operands. */
11203 constraint (inst.operands[1].shifted,
11204 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11206 if (inst.operands[1].isreg)
11208 if (Rn < 8 && Rm < 8)
11210 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11211 since a MOV instruction produces unpredictable results. */
11212 if (inst.instruction == T_OPCODE_MOV_I8)
11213 inst.instruction = T_OPCODE_ADD_I3;
11215 inst.instruction = T_OPCODE_CMP_LR;
11217 inst.instruction |= Rn;
11218 inst.instruction |= Rm << 3;
11222 if (inst.instruction == T_OPCODE_MOV_I8)
11223 inst.instruction = T_OPCODE_MOV_HR;
11225 inst.instruction = T_OPCODE_CMP_HR;
11231 constraint (Rn > 7,
11232 _("only lo regs allowed with immediate"));
11233 inst.instruction |= Rn << 8;
11234 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11245 top = (inst.instruction & 0x00800000) != 0;
11246 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11248 constraint (top, _(":lower16: not allowed this instruction"));
11249 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11251 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11253 constraint (!top, _(":upper16: not allowed this instruction"));
11254 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11257 Rd = inst.operands[0].reg;
11258 reject_bad_reg (Rd);
11260 inst.instruction |= Rd << 8;
11261 if (inst.reloc.type == BFD_RELOC_UNUSED)
11263 imm = inst.reloc.exp.X_add_number;
11264 inst.instruction |= (imm & 0xf000) << 4;
11265 inst.instruction |= (imm & 0x0800) << 15;
11266 inst.instruction |= (imm & 0x0700) << 4;
11267 inst.instruction |= (imm & 0x00ff);
11272 do_t_mvn_tst (void)
11276 Rn = inst.operands[0].reg;
11277 Rm = inst.operands[1].reg;
11279 if (inst.instruction == T_MNEM_cmp
11280 || inst.instruction == T_MNEM_cmn)
11281 constraint (Rn == REG_PC, BAD_PC);
11283 reject_bad_reg (Rn);
11284 reject_bad_reg (Rm);
11286 if (unified_syntax)
11288 int r0off = (inst.instruction == T_MNEM_mvn
11289 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11290 bfd_boolean narrow;
11292 if (inst.size_req == 4
11293 || inst.instruction > 0xffff
11294 || inst.operands[1].shifted
11295 || Rn > 7 || Rm > 7)
11297 else if (inst.instruction == T_MNEM_cmn)
11299 else if (THUMB_SETS_FLAGS (inst.instruction))
11300 narrow = !in_it_block ();
11302 narrow = in_it_block ();
11304 if (!inst.operands[1].isreg)
11306 /* For an immediate, we always generate a 32-bit opcode;
11307 section relaxation will shrink it later if possible. */
11308 if (inst.instruction < 0xffff)
11309 inst.instruction = THUMB_OP32 (inst.instruction);
11310 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11311 inst.instruction |= Rn << r0off;
11312 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11316 /* See if we can do this with a 16-bit instruction. */
11319 inst.instruction = THUMB_OP16 (inst.instruction);
11320 inst.instruction |= Rn;
11321 inst.instruction |= Rm << 3;
11325 constraint (inst.operands[1].shifted
11326 && inst.operands[1].immisreg,
11327 _("shift must be constant"));
11328 if (inst.instruction < 0xffff)
11329 inst.instruction = THUMB_OP32 (inst.instruction);
11330 inst.instruction |= Rn << r0off;
11331 encode_thumb32_shifted_operand (1);
11337 constraint (inst.instruction > 0xffff
11338 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11339 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11340 _("unshifted register required"));
11341 constraint (Rn > 7 || Rm > 7,
11344 inst.instruction = THUMB_OP16 (inst.instruction);
11345 inst.instruction |= Rn;
11346 inst.instruction |= Rm << 3;
11355 if (do_vfp_nsyn_mrs () == SUCCESS)
11358 Rd = inst.operands[0].reg;
11359 reject_bad_reg (Rd);
11360 inst.instruction |= Rd << 8;
11362 if (inst.operands[1].isreg)
11364 unsigned br = inst.operands[1].reg;
11365 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11366 as_bad (_("bad register for mrs"));
11368 inst.instruction |= br & (0xf << 16);
11369 inst.instruction |= (br & 0x300) >> 4;
11370 inst.instruction |= (br & SPSR_BIT) >> 2;
11374 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11376 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11378 /* PR gas/12698: The constraint is only applied for m_profile.
11379 If the user has specified -march=all, we want to ignore it as
11380 we are building for any CPU type, including non-m variants. */
11381 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11382 constraint ((flags != 0) && m_profile, _("selected processor does "
11383 "not support requested special purpose register"));
11386 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11388 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11389 _("'APSR', 'CPSR' or 'SPSR' expected"));
11391 inst.instruction |= (flags & SPSR_BIT) >> 2;
11392 inst.instruction |= inst.operands[1].imm & 0xff;
11393 inst.instruction |= 0xf0000;
11403 if (do_vfp_nsyn_msr () == SUCCESS)
11406 constraint (!inst.operands[1].isreg,
11407 _("Thumb encoding does not support an immediate here"));
11409 if (inst.operands[0].isreg)
11410 flags = (int)(inst.operands[0].reg);
11412 flags = inst.operands[0].imm;
11414 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11416 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11418 /* PR gas/12698: The constraint is only applied for m_profile.
11419 If the user has specified -march=all, we want to ignore it as
11420 we are building for any CPU type, including non-m variants. */
11421 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11422 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11423 && (bits & ~(PSR_s | PSR_f)) != 0)
11424 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11425 && bits != PSR_f)) && m_profile,
11426 _("selected processor does not support requested special "
11427 "purpose register"));
11430 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11431 "requested special purpose register"));
11433 Rn = inst.operands[1].reg;
11434 reject_bad_reg (Rn);
11436 inst.instruction |= (flags & SPSR_BIT) >> 2;
11437 inst.instruction |= (flags & 0xf0000) >> 8;
11438 inst.instruction |= (flags & 0x300) >> 4;
11439 inst.instruction |= (flags & 0xff);
11440 inst.instruction |= Rn << 16;
11446 bfd_boolean narrow;
11447 unsigned Rd, Rn, Rm;
11449 if (!inst.operands[2].present)
11450 inst.operands[2].reg = inst.operands[0].reg;
11452 Rd = inst.operands[0].reg;
11453 Rn = inst.operands[1].reg;
11454 Rm = inst.operands[2].reg;
11456 if (unified_syntax)
11458 if (inst.size_req == 4
11464 else if (inst.instruction == T_MNEM_muls)
11465 narrow = !in_it_block ();
11467 narrow = in_it_block ();
11471 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11472 constraint (Rn > 7 || Rm > 7,
11479 /* 16-bit MULS/Conditional MUL. */
11480 inst.instruction = THUMB_OP16 (inst.instruction);
11481 inst.instruction |= Rd;
11484 inst.instruction |= Rm << 3;
11486 inst.instruction |= Rn << 3;
11488 constraint (1, _("dest must overlap one source register"));
11492 constraint (inst.instruction != T_MNEM_mul,
11493 _("Thumb-2 MUL must not set flags"));
11495 inst.instruction = THUMB_OP32 (inst.instruction);
11496 inst.instruction |= Rd << 8;
11497 inst.instruction |= Rn << 16;
11498 inst.instruction |= Rm << 0;
11500 reject_bad_reg (Rd);
11501 reject_bad_reg (Rn);
11502 reject_bad_reg (Rm);
11509 unsigned RdLo, RdHi, Rn, Rm;
11511 RdLo = inst.operands[0].reg;
11512 RdHi = inst.operands[1].reg;
11513 Rn = inst.operands[2].reg;
11514 Rm = inst.operands[3].reg;
11516 reject_bad_reg (RdLo);
11517 reject_bad_reg (RdHi);
11518 reject_bad_reg (Rn);
11519 reject_bad_reg (Rm);
11521 inst.instruction |= RdLo << 12;
11522 inst.instruction |= RdHi << 8;
11523 inst.instruction |= Rn << 16;
11524 inst.instruction |= Rm;
11527 as_tsktsk (_("rdhi and rdlo must be different"));
11533 set_it_insn_type (NEUTRAL_IT_INSN);
11535 if (unified_syntax)
11537 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11539 inst.instruction = THUMB_OP32 (inst.instruction);
11540 inst.instruction |= inst.operands[0].imm;
11544 /* PR9722: Check for Thumb2 availability before
11545 generating a thumb2 nop instruction. */
11546 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11548 inst.instruction = THUMB_OP16 (inst.instruction);
11549 inst.instruction |= inst.operands[0].imm << 4;
11552 inst.instruction = 0x46c0;
11557 constraint (inst.operands[0].present,
11558 _("Thumb does not support NOP with hints"));
11559 inst.instruction = 0x46c0;
11566 if (unified_syntax)
11568 bfd_boolean narrow;
11570 if (THUMB_SETS_FLAGS (inst.instruction))
11571 narrow = !in_it_block ();
11573 narrow = in_it_block ();
11574 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11576 if (inst.size_req == 4)
11581 inst.instruction = THUMB_OP32 (inst.instruction);
11582 inst.instruction |= inst.operands[0].reg << 8;
11583 inst.instruction |= inst.operands[1].reg << 16;
11587 inst.instruction = THUMB_OP16 (inst.instruction);
11588 inst.instruction |= inst.operands[0].reg;
11589 inst.instruction |= inst.operands[1].reg << 3;
11594 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11596 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11598 inst.instruction = THUMB_OP16 (inst.instruction);
11599 inst.instruction |= inst.operands[0].reg;
11600 inst.instruction |= inst.operands[1].reg << 3;
11609 Rd = inst.operands[0].reg;
11610 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11612 reject_bad_reg (Rd);
11613 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11614 reject_bad_reg (Rn);
11616 inst.instruction |= Rd << 8;
11617 inst.instruction |= Rn << 16;
11619 if (!inst.operands[2].isreg)
11621 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11622 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11628 Rm = inst.operands[2].reg;
11629 reject_bad_reg (Rm);
11631 constraint (inst.operands[2].shifted
11632 && inst.operands[2].immisreg,
11633 _("shift must be constant"));
11634 encode_thumb32_shifted_operand (2);
11641 unsigned Rd, Rn, Rm;
11643 Rd = inst.operands[0].reg;
11644 Rn = inst.operands[1].reg;
11645 Rm = inst.operands[2].reg;
11647 reject_bad_reg (Rd);
11648 reject_bad_reg (Rn);
11649 reject_bad_reg (Rm);
11651 inst.instruction |= Rd << 8;
11652 inst.instruction |= Rn << 16;
11653 inst.instruction |= Rm;
11654 if (inst.operands[3].present)
11656 unsigned int val = inst.reloc.exp.X_add_number;
11657 constraint (inst.reloc.exp.X_op != O_constant,
11658 _("expression too complex"));
11659 inst.instruction |= (val & 0x1c) << 10;
11660 inst.instruction |= (val & 0x03) << 6;
11667 if (!inst.operands[3].present)
11671 inst.instruction &= ~0x00000020;
11673 /* PR 10168. Swap the Rm and Rn registers. */
11674 Rtmp = inst.operands[1].reg;
11675 inst.operands[1].reg = inst.operands[2].reg;
11676 inst.operands[2].reg = Rtmp;
11684 if (inst.operands[0].immisreg)
11685 reject_bad_reg (inst.operands[0].imm);
11687 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11691 do_t_push_pop (void)
11695 constraint (inst.operands[0].writeback,
11696 _("push/pop do not support {reglist}^"));
11697 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11698 _("expression too complex"));
11700 mask = inst.operands[0].imm;
11701 if ((mask & ~0xff) == 0)
11702 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11703 else if ((inst.instruction == T_MNEM_push
11704 && (mask & ~0xff) == 1 << REG_LR)
11705 || (inst.instruction == T_MNEM_pop
11706 && (mask & ~0xff) == 1 << REG_PC))
11708 inst.instruction = THUMB_OP16 (inst.instruction);
11709 inst.instruction |= THUMB_PP_PC_LR;
11710 inst.instruction |= mask & 0xff;
11712 else if (unified_syntax)
11714 inst.instruction = THUMB_OP32 (inst.instruction);
11715 encode_thumb2_ldmstm (13, mask, TRUE);
11719 inst.error = _("invalid register list to push/pop instruction");
11729 Rd = inst.operands[0].reg;
11730 Rm = inst.operands[1].reg;
11732 reject_bad_reg (Rd);
11733 reject_bad_reg (Rm);
11735 inst.instruction |= Rd << 8;
11736 inst.instruction |= Rm << 16;
11737 inst.instruction |= Rm;
11745 Rd = inst.operands[0].reg;
11746 Rm = inst.operands[1].reg;
11748 reject_bad_reg (Rd);
11749 reject_bad_reg (Rm);
11751 if (Rd <= 7 && Rm <= 7
11752 && inst.size_req != 4)
11754 inst.instruction = THUMB_OP16 (inst.instruction);
11755 inst.instruction |= Rd;
11756 inst.instruction |= Rm << 3;
11758 else if (unified_syntax)
11760 inst.instruction = THUMB_OP32 (inst.instruction);
11761 inst.instruction |= Rd << 8;
11762 inst.instruction |= Rm << 16;
11763 inst.instruction |= Rm;
11766 inst.error = BAD_HIREG;
11774 Rd = inst.operands[0].reg;
11775 Rm = inst.operands[1].reg;
11777 reject_bad_reg (Rd);
11778 reject_bad_reg (Rm);
11780 inst.instruction |= Rd << 8;
11781 inst.instruction |= Rm;
11789 Rd = inst.operands[0].reg;
11790 Rs = (inst.operands[1].present
11791 ? inst.operands[1].reg /* Rd, Rs, foo */
11792 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11794 reject_bad_reg (Rd);
11795 reject_bad_reg (Rs);
11796 if (inst.operands[2].isreg)
11797 reject_bad_reg (inst.operands[2].reg);
11799 inst.instruction |= Rd << 8;
11800 inst.instruction |= Rs << 16;
11801 if (!inst.operands[2].isreg)
11803 bfd_boolean narrow;
11805 if ((inst.instruction & 0x00100000) != 0)
11806 narrow = !in_it_block ();
11808 narrow = in_it_block ();
11810 if (Rd > 7 || Rs > 7)
11813 if (inst.size_req == 4 || !unified_syntax)
11816 if (inst.reloc.exp.X_op != O_constant
11817 || inst.reloc.exp.X_add_number != 0)
11820 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11821 relaxation, but it doesn't seem worth the hassle. */
11824 inst.reloc.type = BFD_RELOC_UNUSED;
11825 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11826 inst.instruction |= Rs << 3;
11827 inst.instruction |= Rd;
11831 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11832 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11836 encode_thumb32_shifted_operand (2);
11842 if (warn_on_deprecated
11843 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11844 as_warn (_("setend use is deprecated for ARMv8"));
11846 set_it_insn_type (OUTSIDE_IT_INSN);
11847 if (inst.operands[0].imm)
11848 inst.instruction |= 0x8;
11854 if (!inst.operands[1].present)
11855 inst.operands[1].reg = inst.operands[0].reg;
11857 if (unified_syntax)
11859 bfd_boolean narrow;
11862 switch (inst.instruction)
11865 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11867 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11869 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11871 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11875 if (THUMB_SETS_FLAGS (inst.instruction))
11876 narrow = !in_it_block ();
11878 narrow = in_it_block ();
11879 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11881 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11883 if (inst.operands[2].isreg
11884 && (inst.operands[1].reg != inst.operands[0].reg
11885 || inst.operands[2].reg > 7))
11887 if (inst.size_req == 4)
11890 reject_bad_reg (inst.operands[0].reg);
11891 reject_bad_reg (inst.operands[1].reg);
11895 if (inst.operands[2].isreg)
11897 reject_bad_reg (inst.operands[2].reg);
11898 inst.instruction = THUMB_OP32 (inst.instruction);
11899 inst.instruction |= inst.operands[0].reg << 8;
11900 inst.instruction |= inst.operands[1].reg << 16;
11901 inst.instruction |= inst.operands[2].reg;
11903 /* PR 12854: Error on extraneous shifts. */
11904 constraint (inst.operands[2].shifted,
11905 _("extraneous shift as part of operand to shift insn"));
11909 inst.operands[1].shifted = 1;
11910 inst.operands[1].shift_kind = shift_kind;
11911 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11912 ? T_MNEM_movs : T_MNEM_mov);
11913 inst.instruction |= inst.operands[0].reg << 8;
11914 encode_thumb32_shifted_operand (1);
11915 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11916 inst.reloc.type = BFD_RELOC_UNUSED;
11921 if (inst.operands[2].isreg)
11923 switch (shift_kind)
11925 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11926 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11927 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11928 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11932 inst.instruction |= inst.operands[0].reg;
11933 inst.instruction |= inst.operands[2].reg << 3;
11935 /* PR 12854: Error on extraneous shifts. */
11936 constraint (inst.operands[2].shifted,
11937 _("extraneous shift as part of operand to shift insn"));
11941 switch (shift_kind)
11943 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11944 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11945 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11948 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11949 inst.instruction |= inst.operands[0].reg;
11950 inst.instruction |= inst.operands[1].reg << 3;
11956 constraint (inst.operands[0].reg > 7
11957 || inst.operands[1].reg > 7, BAD_HIREG);
11958 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11960 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11962 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11963 constraint (inst.operands[0].reg != inst.operands[1].reg,
11964 _("source1 and dest must be same register"));
11966 switch (inst.instruction)
11968 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11969 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11970 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11971 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11975 inst.instruction |= inst.operands[0].reg;
11976 inst.instruction |= inst.operands[2].reg << 3;
11978 /* PR 12854: Error on extraneous shifts. */
11979 constraint (inst.operands[2].shifted,
11980 _("extraneous shift as part of operand to shift insn"));
11984 switch (inst.instruction)
11986 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11987 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11988 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11989 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11992 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11993 inst.instruction |= inst.operands[0].reg;
11994 inst.instruction |= inst.operands[1].reg << 3;
12002 unsigned Rd, Rn, Rm;
12004 Rd = inst.operands[0].reg;
12005 Rn = inst.operands[1].reg;
12006 Rm = inst.operands[2].reg;
12008 reject_bad_reg (Rd);
12009 reject_bad_reg (Rn);
12010 reject_bad_reg (Rm);
12012 inst.instruction |= Rd << 8;
12013 inst.instruction |= Rn << 16;
12014 inst.instruction |= Rm;
12020 unsigned Rd, Rn, Rm;
12022 Rd = inst.operands[0].reg;
12023 Rm = inst.operands[1].reg;
12024 Rn = inst.operands[2].reg;
12026 reject_bad_reg (Rd);
12027 reject_bad_reg (Rn);
12028 reject_bad_reg (Rm);
12030 inst.instruction |= Rd << 8;
12031 inst.instruction |= Rn << 16;
12032 inst.instruction |= Rm;
12038 unsigned int value = inst.reloc.exp.X_add_number;
12039 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12040 _("SMC is not permitted on this architecture"));
12041 constraint (inst.reloc.exp.X_op != O_constant,
12042 _("expression too complex"));
12043 inst.reloc.type = BFD_RELOC_UNUSED;
12044 inst.instruction |= (value & 0xf000) >> 12;
12045 inst.instruction |= (value & 0x0ff0);
12046 inst.instruction |= (value & 0x000f) << 16;
12052 unsigned int value = inst.reloc.exp.X_add_number;
12054 inst.reloc.type = BFD_RELOC_UNUSED;
12055 inst.instruction |= (value & 0x0fff);
12056 inst.instruction |= (value & 0xf000) << 4;
12060 do_t_ssat_usat (int bias)
12064 Rd = inst.operands[0].reg;
12065 Rn = inst.operands[2].reg;
12067 reject_bad_reg (Rd);
12068 reject_bad_reg (Rn);
12070 inst.instruction |= Rd << 8;
12071 inst.instruction |= inst.operands[1].imm - bias;
12072 inst.instruction |= Rn << 16;
12074 if (inst.operands[3].present)
12076 offsetT shift_amount = inst.reloc.exp.X_add_number;
12078 inst.reloc.type = BFD_RELOC_UNUSED;
12080 constraint (inst.reloc.exp.X_op != O_constant,
12081 _("expression too complex"));
12083 if (shift_amount != 0)
12085 constraint (shift_amount > 31,
12086 _("shift expression is too large"));
12088 if (inst.operands[3].shift_kind == SHIFT_ASR)
12089 inst.instruction |= 0x00200000; /* sh bit. */
12091 inst.instruction |= (shift_amount & 0x1c) << 10;
12092 inst.instruction |= (shift_amount & 0x03) << 6;
12100 do_t_ssat_usat (1);
12108 Rd = inst.operands[0].reg;
12109 Rn = inst.operands[2].reg;
12111 reject_bad_reg (Rd);
12112 reject_bad_reg (Rn);
12114 inst.instruction |= Rd << 8;
12115 inst.instruction |= inst.operands[1].imm - 1;
12116 inst.instruction |= Rn << 16;
12122 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12123 || inst.operands[2].postind || inst.operands[2].writeback
12124 || inst.operands[2].immisreg || inst.operands[2].shifted
12125 || inst.operands[2].negative,
12128 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12130 inst.instruction |= inst.operands[0].reg << 8;
12131 inst.instruction |= inst.operands[1].reg << 12;
12132 inst.instruction |= inst.operands[2].reg << 16;
12133 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12139 if (!inst.operands[2].present)
12140 inst.operands[2].reg = inst.operands[1].reg + 1;
12142 constraint (inst.operands[0].reg == inst.operands[1].reg
12143 || inst.operands[0].reg == inst.operands[2].reg
12144 || inst.operands[0].reg == inst.operands[3].reg,
12147 inst.instruction |= inst.operands[0].reg;
12148 inst.instruction |= inst.operands[1].reg << 12;
12149 inst.instruction |= inst.operands[2].reg << 8;
12150 inst.instruction |= inst.operands[3].reg << 16;
12156 unsigned Rd, Rn, Rm;
12158 Rd = inst.operands[0].reg;
12159 Rn = inst.operands[1].reg;
12160 Rm = inst.operands[2].reg;
12162 reject_bad_reg (Rd);
12163 reject_bad_reg (Rn);
12164 reject_bad_reg (Rm);
12166 inst.instruction |= Rd << 8;
12167 inst.instruction |= Rn << 16;
12168 inst.instruction |= Rm;
12169 inst.instruction |= inst.operands[3].imm << 4;
12177 Rd = inst.operands[0].reg;
12178 Rm = inst.operands[1].reg;
12180 reject_bad_reg (Rd);
12181 reject_bad_reg (Rm);
12183 if (inst.instruction <= 0xffff
12184 && inst.size_req != 4
12185 && Rd <= 7 && Rm <= 7
12186 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12188 inst.instruction = THUMB_OP16 (inst.instruction);
12189 inst.instruction |= Rd;
12190 inst.instruction |= Rm << 3;
12192 else if (unified_syntax)
12194 if (inst.instruction <= 0xffff)
12195 inst.instruction = THUMB_OP32 (inst.instruction);
12196 inst.instruction |= Rd << 8;
12197 inst.instruction |= Rm;
12198 inst.instruction |= inst.operands[2].imm << 4;
12202 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12203 _("Thumb encoding does not support rotation"));
12204 constraint (1, BAD_HIREG);
12211 /* We have to do the following check manually as ARM_EXT_OS only applies
12213 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12215 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12216 /* This only applies to the v6m howver, not later architectures. */
12217 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12218 as_bad (_("SVC is not permitted on this architecture"));
12219 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12222 inst.reloc.type = BFD_RELOC_ARM_SWI;
12231 half = (inst.instruction & 0x10) != 0;
12232 set_it_insn_type_last ();
12233 constraint (inst.operands[0].immisreg,
12234 _("instruction requires register index"));
12236 Rn = inst.operands[0].reg;
12237 Rm = inst.operands[0].imm;
12239 constraint (Rn == REG_SP, BAD_SP);
12240 reject_bad_reg (Rm);
12242 constraint (!half && inst.operands[0].shifted,
12243 _("instruction does not allow shifted index"));
12244 inst.instruction |= (Rn << 16) | Rm;
12250 do_t_ssat_usat (0);
12258 Rd = inst.operands[0].reg;
12259 Rn = inst.operands[2].reg;
12261 reject_bad_reg (Rd);
12262 reject_bad_reg (Rn);
12264 inst.instruction |= Rd << 8;
12265 inst.instruction |= inst.operands[1].imm;
12266 inst.instruction |= Rn << 16;
12269 /* Neon instruction encoder helpers. */
12271 /* Encodings for the different types for various Neon opcodes. */
12273 /* An "invalid" code for the following tables. */
12276 struct neon_tab_entry
12279 unsigned float_or_poly;
12280 unsigned scalar_or_imm;
12283 /* Map overloaded Neon opcodes to their respective encodings. */
12284 #define NEON_ENC_TAB \
12285 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12286 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12287 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12288 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12289 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12290 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12291 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12292 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12293 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12294 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12295 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12296 /* Register variants of the following two instructions are encoded as
12297 vcge / vcgt with the operands reversed. */ \
12298 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12299 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12300 X(vfma, N_INV, 0x0000c10, N_INV), \
12301 X(vfms, N_INV, 0x0200c10, N_INV), \
12302 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12303 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12304 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12305 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12306 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12307 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12308 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12309 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12310 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12311 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12312 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12313 X(vshl, 0x0000400, N_INV, 0x0800510), \
12314 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12315 X(vand, 0x0000110, N_INV, 0x0800030), \
12316 X(vbic, 0x0100110, N_INV, 0x0800030), \
12317 X(veor, 0x1000110, N_INV, N_INV), \
12318 X(vorn, 0x0300110, N_INV, 0x0800010), \
12319 X(vorr, 0x0200110, N_INV, 0x0800010), \
12320 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12321 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12322 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12323 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12324 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12325 X(vst1, 0x0000000, 0x0800000, N_INV), \
12326 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12327 X(vst2, 0x0000100, 0x0800100, N_INV), \
12328 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12329 X(vst3, 0x0000200, 0x0800200, N_INV), \
12330 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12331 X(vst4, 0x0000300, 0x0800300, N_INV), \
12332 X(vmovn, 0x1b20200, N_INV, N_INV), \
12333 X(vtrn, 0x1b20080, N_INV, N_INV), \
12334 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12335 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12336 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12337 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12338 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12339 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12340 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12341 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12342 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12343 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12344 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12345 X(vseleq, 0xe000a00, N_INV, N_INV), \
12346 X(vselvs, 0xe100a00, N_INV, N_INV), \
12347 X(vselge, 0xe200a00, N_INV, N_INV), \
12348 X(vselgt, 0xe300a00, N_INV, N_INV)
12352 #define X(OPC,I,F,S) N_MNEM_##OPC
12357 static const struct neon_tab_entry neon_enc_tab[] =
12359 #define X(OPC,I,F,S) { (I), (F), (S) }
12364 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12365 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12366 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12367 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12368 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12369 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12370 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12371 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12372 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12373 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12374 #define NEON_ENC_SINGLE_(X) \
12375 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12376 #define NEON_ENC_DOUBLE_(X) \
12377 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12378 #define NEON_ENC_FPV8_(X) \
12379 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12381 #define NEON_ENCODE(type, inst) \
12384 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12385 inst.is_neon = 1; \
12389 #define check_neon_suffixes \
12392 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12394 as_bad (_("invalid neon suffix for non neon instruction")); \
12400 /* Define shapes for instruction operands. The following mnemonic characters
12401 are used in this table:
12403 F - VFP S<n> register
12404 D - Neon D<n> register
12405 Q - Neon Q<n> register
12409 L - D<n> register list
12411 This table is used to generate various data:
12412 - enumerations of the form NS_DDR to be used as arguments to
12414 - a table classifying shapes into single, double, quad, mixed.
12415 - a table used to drive neon_select_shape. */
12417 #define NEON_SHAPE_DEF \
12418 X(3, (D, D, D), DOUBLE), \
12419 X(3, (Q, Q, Q), QUAD), \
12420 X(3, (D, D, I), DOUBLE), \
12421 X(3, (Q, Q, I), QUAD), \
12422 X(3, (D, D, S), DOUBLE), \
12423 X(3, (Q, Q, S), QUAD), \
12424 X(2, (D, D), DOUBLE), \
12425 X(2, (Q, Q), QUAD), \
12426 X(2, (D, S), DOUBLE), \
12427 X(2, (Q, S), QUAD), \
12428 X(2, (D, R), DOUBLE), \
12429 X(2, (Q, R), QUAD), \
12430 X(2, (D, I), DOUBLE), \
12431 X(2, (Q, I), QUAD), \
12432 X(3, (D, L, D), DOUBLE), \
12433 X(2, (D, Q), MIXED), \
12434 X(2, (Q, D), MIXED), \
12435 X(3, (D, Q, I), MIXED), \
12436 X(3, (Q, D, I), MIXED), \
12437 X(3, (Q, D, D), MIXED), \
12438 X(3, (D, Q, Q), MIXED), \
12439 X(3, (Q, Q, D), MIXED), \
12440 X(3, (Q, D, S), MIXED), \
12441 X(3, (D, Q, S), MIXED), \
12442 X(4, (D, D, D, I), DOUBLE), \
12443 X(4, (Q, Q, Q, I), QUAD), \
12444 X(2, (F, F), SINGLE), \
12445 X(3, (F, F, F), SINGLE), \
12446 X(2, (F, I), SINGLE), \
12447 X(2, (F, D), MIXED), \
12448 X(2, (D, F), MIXED), \
12449 X(3, (F, F, I), MIXED), \
12450 X(4, (R, R, F, F), SINGLE), \
12451 X(4, (F, F, R, R), SINGLE), \
12452 X(3, (D, R, R), DOUBLE), \
12453 X(3, (R, R, D), DOUBLE), \
12454 X(2, (S, R), SINGLE), \
12455 X(2, (R, S), SINGLE), \
12456 X(2, (F, R), SINGLE), \
12457 X(2, (R, F), SINGLE)
12459 #define S2(A,B) NS_##A##B
12460 #define S3(A,B,C) NS_##A##B##C
12461 #define S4(A,B,C,D) NS_##A##B##C##D
12463 #define X(N, L, C) S##N L
12476 enum neon_shape_class
12484 #define X(N, L, C) SC_##C
12486 static enum neon_shape_class neon_shape_class[] =
12504 /* Register widths of above. */
12505 static unsigned neon_shape_el_size[] =
12516 struct neon_shape_info
12519 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12522 #define S2(A,B) { SE_##A, SE_##B }
12523 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12524 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12526 #define X(N, L, C) { N, S##N L }
12528 static struct neon_shape_info neon_shape_tab[] =
12538 /* Bit masks used in type checking given instructions.
12539 'N_EQK' means the type must be the same as (or based on in some way) the key
12540 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12541 set, various other bits can be set as well in order to modify the meaning of
12542 the type constraint. */
12544 enum neon_type_mask
12567 N_KEY = 0x1000000, /* Key element (main type specifier). */
12568 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12569 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12570 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12571 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12572 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12573 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12574 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12575 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12576 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12578 N_MAX_NONSPECIAL = N_F64
12581 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12583 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12584 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12585 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12586 #define N_SUF_32 (N_SU_32 | N_F32)
12587 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12588 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12590 /* Pass this as the first type argument to neon_check_type to ignore types
12592 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12594 /* Select a "shape" for the current instruction (describing register types or
12595 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12596 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12597 function of operand parsing, so this function doesn't need to be called.
12598 Shapes should be listed in order of decreasing length. */
12600 static enum neon_shape
12601 neon_select_shape (enum neon_shape shape, ...)
12604 enum neon_shape first_shape = shape;
12606 /* Fix missing optional operands. FIXME: we don't know at this point how
12607 many arguments we should have, so this makes the assumption that we have
12608 > 1. This is true of all current Neon opcodes, I think, but may not be
12609 true in the future. */
12610 if (!inst.operands[1].present)
12611 inst.operands[1] = inst.operands[0];
12613 va_start (ap, shape);
12615 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12620 for (j = 0; j < neon_shape_tab[shape].els; j++)
12622 if (!inst.operands[j].present)
12628 switch (neon_shape_tab[shape].el[j])
12631 if (!(inst.operands[j].isreg
12632 && inst.operands[j].isvec
12633 && inst.operands[j].issingle
12634 && !inst.operands[j].isquad))
12639 if (!(inst.operands[j].isreg
12640 && inst.operands[j].isvec
12641 && !inst.operands[j].isquad
12642 && !inst.operands[j].issingle))
12647 if (!(inst.operands[j].isreg
12648 && !inst.operands[j].isvec))
12653 if (!(inst.operands[j].isreg
12654 && inst.operands[j].isvec
12655 && inst.operands[j].isquad
12656 && !inst.operands[j].issingle))
12661 if (!(!inst.operands[j].isreg
12662 && !inst.operands[j].isscalar))
12667 if (!(!inst.operands[j].isreg
12668 && inst.operands[j].isscalar))
12678 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12679 /* We've matched all the entries in the shape table, and we don't
12680 have any left over operands which have not been matched. */
12686 if (shape == NS_NULL && first_shape != NS_NULL)
12687 first_error (_("invalid instruction shape"));
12692 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12693 means the Q bit should be set). */
12696 neon_quad (enum neon_shape shape)
12698 return neon_shape_class[shape] == SC_QUAD;
12702 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12705 /* Allow modification to be made to types which are constrained to be
12706 based on the key element, based on bits set alongside N_EQK. */
12707 if ((typebits & N_EQK) != 0)
12709 if ((typebits & N_HLF) != 0)
12711 else if ((typebits & N_DBL) != 0)
12713 if ((typebits & N_SGN) != 0)
12714 *g_type = NT_signed;
12715 else if ((typebits & N_UNS) != 0)
12716 *g_type = NT_unsigned;
12717 else if ((typebits & N_INT) != 0)
12718 *g_type = NT_integer;
12719 else if ((typebits & N_FLT) != 0)
12720 *g_type = NT_float;
12721 else if ((typebits & N_SIZ) != 0)
12722 *g_type = NT_untyped;
12726 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12727 operand type, i.e. the single type specified in a Neon instruction when it
12728 is the only one given. */
12730 static struct neon_type_el
12731 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12733 struct neon_type_el dest = *key;
12735 gas_assert ((thisarg & N_EQK) != 0);
12737 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12742 /* Convert Neon type and size into compact bitmask representation. */
12744 static enum neon_type_mask
12745 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12752 case 8: return N_8;
12753 case 16: return N_16;
12754 case 32: return N_32;
12755 case 64: return N_64;
12763 case 8: return N_I8;
12764 case 16: return N_I16;
12765 case 32: return N_I32;
12766 case 64: return N_I64;
12774 case 16: return N_F16;
12775 case 32: return N_F32;
12776 case 64: return N_F64;
12784 case 8: return N_P8;
12785 case 16: return N_P16;
12793 case 8: return N_S8;
12794 case 16: return N_S16;
12795 case 32: return N_S32;
12796 case 64: return N_S64;
12804 case 8: return N_U8;
12805 case 16: return N_U16;
12806 case 32: return N_U32;
12807 case 64: return N_U64;
12818 /* Convert compact Neon bitmask type representation to a type and size. Only
12819 handles the case where a single bit is set in the mask. */
12822 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12823 enum neon_type_mask mask)
12825 if ((mask & N_EQK) != 0)
12828 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12830 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12832 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12834 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12839 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12841 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12842 *type = NT_unsigned;
12843 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12844 *type = NT_integer;
12845 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12846 *type = NT_untyped;
12847 else if ((mask & (N_P8 | N_P16)) != 0)
12849 else if ((mask & (N_F32 | N_F64)) != 0)
12857 /* Modify a bitmask of allowed types. This is only needed for type
12861 modify_types_allowed (unsigned allowed, unsigned mods)
12864 enum neon_el_type type;
12870 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12872 if (el_type_of_type_chk (&type, &size,
12873 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12875 neon_modify_type_size (mods, &type, &size);
12876 destmask |= type_chk_of_el_type (type, size);
12883 /* Check type and return type classification.
12884 The manual states (paraphrase): If one datatype is given, it indicates the
12886 - the second operand, if there is one
12887 - the operand, if there is no second operand
12888 - the result, if there are no operands.
12889 This isn't quite good enough though, so we use a concept of a "key" datatype
12890 which is set on a per-instruction basis, which is the one which matters when
12891 only one data type is written.
12892 Note: this function has side-effects (e.g. filling in missing operands). All
12893 Neon instructions should call it before performing bit encoding. */
12895 static struct neon_type_el
12896 neon_check_type (unsigned els, enum neon_shape ns, ...)
12899 unsigned i, pass, key_el = 0;
12900 unsigned types[NEON_MAX_TYPE_ELS];
12901 enum neon_el_type k_type = NT_invtype;
12902 unsigned k_size = -1u;
12903 struct neon_type_el badtype = {NT_invtype, -1};
12904 unsigned key_allowed = 0;
12906 /* Optional registers in Neon instructions are always (not) in operand 1.
12907 Fill in the missing operand here, if it was omitted. */
12908 if (els > 1 && !inst.operands[1].present)
12909 inst.operands[1] = inst.operands[0];
12911 /* Suck up all the varargs. */
12913 for (i = 0; i < els; i++)
12915 unsigned thisarg = va_arg (ap, unsigned);
12916 if (thisarg == N_IGNORE_TYPE)
12921 types[i] = thisarg;
12922 if ((thisarg & N_KEY) != 0)
12927 if (inst.vectype.elems > 0)
12928 for (i = 0; i < els; i++)
12929 if (inst.operands[i].vectype.type != NT_invtype)
12931 first_error (_("types specified in both the mnemonic and operands"));
12935 /* Duplicate inst.vectype elements here as necessary.
12936 FIXME: No idea if this is exactly the same as the ARM assembler,
12937 particularly when an insn takes one register and one non-register
12939 if (inst.vectype.elems == 1 && els > 1)
12942 inst.vectype.elems = els;
12943 inst.vectype.el[key_el] = inst.vectype.el[0];
12944 for (j = 0; j < els; j++)
12946 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12949 else if (inst.vectype.elems == 0 && els > 0)
12952 /* No types were given after the mnemonic, so look for types specified
12953 after each operand. We allow some flexibility here; as long as the
12954 "key" operand has a type, we can infer the others. */
12955 for (j = 0; j < els; j++)
12956 if (inst.operands[j].vectype.type != NT_invtype)
12957 inst.vectype.el[j] = inst.operands[j].vectype;
12959 if (inst.operands[key_el].vectype.type != NT_invtype)
12961 for (j = 0; j < els; j++)
12962 if (inst.operands[j].vectype.type == NT_invtype)
12963 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12968 first_error (_("operand types can't be inferred"));
12972 else if (inst.vectype.elems != els)
12974 first_error (_("type specifier has the wrong number of parts"));
12978 for (pass = 0; pass < 2; pass++)
12980 for (i = 0; i < els; i++)
12982 unsigned thisarg = types[i];
12983 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12984 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12985 enum neon_el_type g_type = inst.vectype.el[i].type;
12986 unsigned g_size = inst.vectype.el[i].size;
12988 /* Decay more-specific signed & unsigned types to sign-insensitive
12989 integer types if sign-specific variants are unavailable. */
12990 if ((g_type == NT_signed || g_type == NT_unsigned)
12991 && (types_allowed & N_SU_ALL) == 0)
12992 g_type = NT_integer;
12994 /* If only untyped args are allowed, decay any more specific types to
12995 them. Some instructions only care about signs for some element
12996 sizes, so handle that properly. */
12997 if ((g_size == 8 && (types_allowed & N_8) != 0)
12998 || (g_size == 16 && (types_allowed & N_16) != 0)
12999 || (g_size == 32 && (types_allowed & N_32) != 0)
13000 || (g_size == 64 && (types_allowed & N_64) != 0))
13001 g_type = NT_untyped;
13005 if ((thisarg & N_KEY) != 0)
13009 key_allowed = thisarg & ~N_KEY;
13014 if ((thisarg & N_VFP) != 0)
13016 enum neon_shape_el regshape;
13017 unsigned regwidth, match;
13019 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13022 first_error (_("invalid instruction shape"));
13025 regshape = neon_shape_tab[ns].el[i];
13026 regwidth = neon_shape_el_size[regshape];
13028 /* In VFP mode, operands must match register widths. If we
13029 have a key operand, use its width, else use the width of
13030 the current operand. */
13036 if (regwidth != match)
13038 first_error (_("operand size must match register width"));
13043 if ((thisarg & N_EQK) == 0)
13045 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13047 if ((given_type & types_allowed) == 0)
13049 first_error (_("bad type in Neon instruction"));
13055 enum neon_el_type mod_k_type = k_type;
13056 unsigned mod_k_size = k_size;
13057 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13058 if (g_type != mod_k_type || g_size != mod_k_size)
13060 first_error (_("inconsistent types in Neon instruction"));
13068 return inst.vectype.el[key_el];
13071 /* Neon-style VFP instruction forwarding. */
13073 /* Thumb VFP instructions have 0xE in the condition field. */
13076 do_vfp_cond_or_thumb (void)
13081 inst.instruction |= 0xe0000000;
13083 inst.instruction |= inst.cond << 28;
13086 /* Look up and encode a simple mnemonic, for use as a helper function for the
13087 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13088 etc. It is assumed that operand parsing has already been done, and that the
13089 operands are in the form expected by the given opcode (this isn't necessarily
13090 the same as the form in which they were parsed, hence some massaging must
13091 take place before this function is called).
13092 Checks current arch version against that in the looked-up opcode. */
13095 do_vfp_nsyn_opcode (const char *opname)
13097 const struct asm_opcode *opcode;
13099 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13104 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13105 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13112 inst.instruction = opcode->tvalue;
13113 opcode->tencode ();
13117 inst.instruction = (inst.cond << 28) | opcode->avalue;
13118 opcode->aencode ();
13123 do_vfp_nsyn_add_sub (enum neon_shape rs)
13125 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13130 do_vfp_nsyn_opcode ("fadds");
13132 do_vfp_nsyn_opcode ("fsubs");
13137 do_vfp_nsyn_opcode ("faddd");
13139 do_vfp_nsyn_opcode ("fsubd");
13143 /* Check operand types to see if this is a VFP instruction, and if so call
13147 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13149 enum neon_shape rs;
13150 struct neon_type_el et;
13155 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13156 et = neon_check_type (2, rs,
13157 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13161 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13162 et = neon_check_type (3, rs,
13163 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13170 if (et.type != NT_invtype)
13181 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13183 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13188 do_vfp_nsyn_opcode ("fmacs");
13190 do_vfp_nsyn_opcode ("fnmacs");
13195 do_vfp_nsyn_opcode ("fmacd");
13197 do_vfp_nsyn_opcode ("fnmacd");
13202 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13204 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13209 do_vfp_nsyn_opcode ("ffmas");
13211 do_vfp_nsyn_opcode ("ffnmas");
13216 do_vfp_nsyn_opcode ("ffmad");
13218 do_vfp_nsyn_opcode ("ffnmad");
13223 do_vfp_nsyn_mul (enum neon_shape rs)
13226 do_vfp_nsyn_opcode ("fmuls");
13228 do_vfp_nsyn_opcode ("fmuld");
13232 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13234 int is_neg = (inst.instruction & 0x80) != 0;
13235 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13240 do_vfp_nsyn_opcode ("fnegs");
13242 do_vfp_nsyn_opcode ("fabss");
13247 do_vfp_nsyn_opcode ("fnegd");
13249 do_vfp_nsyn_opcode ("fabsd");
13253 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13254 insns belong to Neon, and are handled elsewhere. */
13257 do_vfp_nsyn_ldm_stm (int is_dbmode)
13259 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13263 do_vfp_nsyn_opcode ("fldmdbs");
13265 do_vfp_nsyn_opcode ("fldmias");
13270 do_vfp_nsyn_opcode ("fstmdbs");
13272 do_vfp_nsyn_opcode ("fstmias");
13277 do_vfp_nsyn_sqrt (void)
13279 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13280 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13283 do_vfp_nsyn_opcode ("fsqrts");
13285 do_vfp_nsyn_opcode ("fsqrtd");
13289 do_vfp_nsyn_div (void)
13291 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13292 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13293 N_F32 | N_F64 | N_KEY | N_VFP);
13296 do_vfp_nsyn_opcode ("fdivs");
13298 do_vfp_nsyn_opcode ("fdivd");
13302 do_vfp_nsyn_nmul (void)
13304 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13305 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13306 N_F32 | N_F64 | N_KEY | N_VFP);
13310 NEON_ENCODE (SINGLE, inst);
13311 do_vfp_sp_dyadic ();
13315 NEON_ENCODE (DOUBLE, inst);
13316 do_vfp_dp_rd_rn_rm ();
13318 do_vfp_cond_or_thumb ();
13322 do_vfp_nsyn_cmp (void)
13324 if (inst.operands[1].isreg)
13326 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13327 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13331 NEON_ENCODE (SINGLE, inst);
13332 do_vfp_sp_monadic ();
13336 NEON_ENCODE (DOUBLE, inst);
13337 do_vfp_dp_rd_rm ();
13342 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13343 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13345 switch (inst.instruction & 0x0fffffff)
13348 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13351 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13359 NEON_ENCODE (SINGLE, inst);
13360 do_vfp_sp_compare_z ();
13364 NEON_ENCODE (DOUBLE, inst);
13368 do_vfp_cond_or_thumb ();
13372 nsyn_insert_sp (void)
13374 inst.operands[1] = inst.operands[0];
13375 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13376 inst.operands[0].reg = REG_SP;
13377 inst.operands[0].isreg = 1;
13378 inst.operands[0].writeback = 1;
13379 inst.operands[0].present = 1;
13383 do_vfp_nsyn_push (void)
13386 if (inst.operands[1].issingle)
13387 do_vfp_nsyn_opcode ("fstmdbs");
13389 do_vfp_nsyn_opcode ("fstmdbd");
13393 do_vfp_nsyn_pop (void)
13396 if (inst.operands[1].issingle)
13397 do_vfp_nsyn_opcode ("fldmias");
13399 do_vfp_nsyn_opcode ("fldmiad");
13402 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13403 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13406 neon_dp_fixup (struct arm_it* insn)
13408 unsigned int i = insn->instruction;
13413 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13424 insn->instruction = i;
13427 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13431 neon_logbits (unsigned x)
13433 return ffs (x) - 4;
13436 #define LOW4(R) ((R) & 0xf)
13437 #define HI1(R) (((R) >> 4) & 1)
13439 /* Encode insns with bit pattern:
13441 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13442 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13444 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13445 different meaning for some instruction. */
13448 neon_three_same (int isquad, int ubit, int size)
13450 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13451 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13452 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13453 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13454 inst.instruction |= LOW4 (inst.operands[2].reg);
13455 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13456 inst.instruction |= (isquad != 0) << 6;
13457 inst.instruction |= (ubit != 0) << 24;
13459 inst.instruction |= neon_logbits (size) << 20;
13461 neon_dp_fixup (&inst);
13464 /* Encode instructions of the form:
13466 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13467 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13469 Don't write size if SIZE == -1. */
13472 neon_two_same (int qbit, int ubit, int size)
13474 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13475 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13476 inst.instruction |= LOW4 (inst.operands[1].reg);
13477 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13478 inst.instruction |= (qbit != 0) << 6;
13479 inst.instruction |= (ubit != 0) << 24;
13482 inst.instruction |= neon_logbits (size) << 18;
13484 neon_dp_fixup (&inst);
13487 /* Neon instruction encoders, in approximate order of appearance. */
13490 do_neon_dyadic_i_su (void)
13492 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13493 struct neon_type_el et = neon_check_type (3, rs,
13494 N_EQK, N_EQK, N_SU_32 | N_KEY);
13495 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13499 do_neon_dyadic_i64_su (void)
13501 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13502 struct neon_type_el et = neon_check_type (3, rs,
13503 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13504 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13508 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13511 unsigned size = et.size >> 3;
13512 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13513 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13514 inst.instruction |= LOW4 (inst.operands[1].reg);
13515 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13516 inst.instruction |= (isquad != 0) << 6;
13517 inst.instruction |= immbits << 16;
13518 inst.instruction |= (size >> 3) << 7;
13519 inst.instruction |= (size & 0x7) << 19;
13521 inst.instruction |= (uval != 0) << 24;
13523 neon_dp_fixup (&inst);
13527 do_neon_shl_imm (void)
13529 if (!inst.operands[2].isreg)
13531 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13532 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13533 NEON_ENCODE (IMMED, inst);
13534 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13538 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13539 struct neon_type_el et = neon_check_type (3, rs,
13540 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13543 /* VSHL/VQSHL 3-register variants have syntax such as:
13545 whereas other 3-register operations encoded by neon_three_same have
13548 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13550 tmp = inst.operands[2].reg;
13551 inst.operands[2].reg = inst.operands[1].reg;
13552 inst.operands[1].reg = tmp;
13553 NEON_ENCODE (INTEGER, inst);
13554 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13559 do_neon_qshl_imm (void)
13561 if (!inst.operands[2].isreg)
13563 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13564 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13566 NEON_ENCODE (IMMED, inst);
13567 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13568 inst.operands[2].imm);
13572 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13573 struct neon_type_el et = neon_check_type (3, rs,
13574 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13577 /* See note in do_neon_shl_imm. */
13578 tmp = inst.operands[2].reg;
13579 inst.operands[2].reg = inst.operands[1].reg;
13580 inst.operands[1].reg = tmp;
13581 NEON_ENCODE (INTEGER, inst);
13582 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13587 do_neon_rshl (void)
13589 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13590 struct neon_type_el et = neon_check_type (3, rs,
13591 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13594 tmp = inst.operands[2].reg;
13595 inst.operands[2].reg = inst.operands[1].reg;
13596 inst.operands[1].reg = tmp;
13597 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13601 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13603 /* Handle .I8 pseudo-instructions. */
13606 /* Unfortunately, this will make everything apart from zero out-of-range.
13607 FIXME is this the intended semantics? There doesn't seem much point in
13608 accepting .I8 if so. */
13609 immediate |= immediate << 8;
13615 if (immediate == (immediate & 0x000000ff))
13617 *immbits = immediate;
13620 else if (immediate == (immediate & 0x0000ff00))
13622 *immbits = immediate >> 8;
13625 else if (immediate == (immediate & 0x00ff0000))
13627 *immbits = immediate >> 16;
13630 else if (immediate == (immediate & 0xff000000))
13632 *immbits = immediate >> 24;
13635 if ((immediate & 0xffff) != (immediate >> 16))
13636 goto bad_immediate;
13637 immediate &= 0xffff;
13640 if (immediate == (immediate & 0x000000ff))
13642 *immbits = immediate;
13645 else if (immediate == (immediate & 0x0000ff00))
13647 *immbits = immediate >> 8;
13652 first_error (_("immediate value out of range"));
13656 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13660 neon_bits_same_in_bytes (unsigned imm)
13662 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13663 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13664 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13665 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13668 /* For immediate of above form, return 0bABCD. */
13671 neon_squash_bits (unsigned imm)
13673 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13674 | ((imm & 0x01000000) >> 21);
13677 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13680 neon_qfloat_bits (unsigned imm)
13682 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13685 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13686 the instruction. *OP is passed as the initial value of the op field, and
13687 may be set to a different value depending on the constant (i.e.
13688 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13689 MVN). If the immediate looks like a repeated pattern then also
13690 try smaller element sizes. */
13693 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13694 unsigned *immbits, int *op, int size,
13695 enum neon_el_type type)
13697 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13699 if (type == NT_float && !float_p)
13702 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13704 if (size != 32 || *op == 1)
13706 *immbits = neon_qfloat_bits (immlo);
13712 if (neon_bits_same_in_bytes (immhi)
13713 && neon_bits_same_in_bytes (immlo))
13717 *immbits = (neon_squash_bits (immhi) << 4)
13718 | neon_squash_bits (immlo);
13723 if (immhi != immlo)
13729 if (immlo == (immlo & 0x000000ff))
13734 else if (immlo == (immlo & 0x0000ff00))
13736 *immbits = immlo >> 8;
13739 else if (immlo == (immlo & 0x00ff0000))
13741 *immbits = immlo >> 16;
13744 else if (immlo == (immlo & 0xff000000))
13746 *immbits = immlo >> 24;
13749 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13751 *immbits = (immlo >> 8) & 0xff;
13754 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13756 *immbits = (immlo >> 16) & 0xff;
13760 if ((immlo & 0xffff) != (immlo >> 16))
13767 if (immlo == (immlo & 0x000000ff))
13772 else if (immlo == (immlo & 0x0000ff00))
13774 *immbits = immlo >> 8;
13778 if ((immlo & 0xff) != (immlo >> 8))
13783 if (immlo == (immlo & 0x000000ff))
13785 /* Don't allow MVN with 8-bit immediate. */
13795 /* Write immediate bits [7:0] to the following locations:
13797 |28/24|23 19|18 16|15 4|3 0|
13798 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13800 This function is used by VMOV/VMVN/VORR/VBIC. */
13803 neon_write_immbits (unsigned immbits)
13805 inst.instruction |= immbits & 0xf;
13806 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13807 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13810 /* Invert low-order SIZE bits of XHI:XLO. */
13813 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13815 unsigned immlo = xlo ? *xlo : 0;
13816 unsigned immhi = xhi ? *xhi : 0;
13821 immlo = (~immlo) & 0xff;
13825 immlo = (~immlo) & 0xffff;
13829 immhi = (~immhi) & 0xffffffff;
13830 /* fall through. */
13833 immlo = (~immlo) & 0xffffffff;
13848 do_neon_logic (void)
13850 if (inst.operands[2].present && inst.operands[2].isreg)
13852 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13853 neon_check_type (3, rs, N_IGNORE_TYPE);
13854 /* U bit and size field were set as part of the bitmask. */
13855 NEON_ENCODE (INTEGER, inst);
13856 neon_three_same (neon_quad (rs), 0, -1);
13860 const int three_ops_form = (inst.operands[2].present
13861 && !inst.operands[2].isreg);
13862 const int immoperand = (three_ops_form ? 2 : 1);
13863 enum neon_shape rs = (three_ops_form
13864 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13865 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13866 struct neon_type_el et = neon_check_type (2, rs,
13867 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13868 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13872 if (et.type == NT_invtype)
13875 if (three_ops_form)
13876 constraint (inst.operands[0].reg != inst.operands[1].reg,
13877 _("first and second operands shall be the same register"));
13879 NEON_ENCODE (IMMED, inst);
13881 immbits = inst.operands[immoperand].imm;
13884 /* .i64 is a pseudo-op, so the immediate must be a repeating
13886 if (immbits != (inst.operands[immoperand].regisimm ?
13887 inst.operands[immoperand].reg : 0))
13889 /* Set immbits to an invalid constant. */
13890 immbits = 0xdeadbeef;
13897 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13901 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13905 /* Pseudo-instruction for VBIC. */
13906 neon_invert_size (&immbits, 0, et.size);
13907 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13911 /* Pseudo-instruction for VORR. */
13912 neon_invert_size (&immbits, 0, et.size);
13913 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13923 inst.instruction |= neon_quad (rs) << 6;
13924 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13925 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13926 inst.instruction |= cmode << 8;
13927 neon_write_immbits (immbits);
13929 neon_dp_fixup (&inst);
13934 do_neon_bitfield (void)
13936 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13937 neon_check_type (3, rs, N_IGNORE_TYPE);
13938 neon_three_same (neon_quad (rs), 0, -1);
13942 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13945 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13946 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13948 if (et.type == NT_float)
13950 NEON_ENCODE (FLOAT, inst);
13951 neon_three_same (neon_quad (rs), 0, -1);
13955 NEON_ENCODE (INTEGER, inst);
13956 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13961 do_neon_dyadic_if_su (void)
13963 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13967 do_neon_dyadic_if_su_d (void)
13969 /* This version only allow D registers, but that constraint is enforced during
13970 operand parsing so we don't need to do anything extra here. */
13971 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13975 do_neon_dyadic_if_i_d (void)
13977 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13978 affected if we specify unsigned args. */
13979 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13982 enum vfp_or_neon_is_neon_bits
13985 NEON_CHECK_ARCH = 2
13988 /* Call this function if an instruction which may have belonged to the VFP or
13989 Neon instruction sets, but turned out to be a Neon instruction (due to the
13990 operand types involved, etc.). We have to check and/or fix-up a couple of
13993 - Make sure the user hasn't attempted to make a Neon instruction
13995 - Alter the value in the condition code field if necessary.
13996 - Make sure that the arch supports Neon instructions.
13998 Which of these operations take place depends on bits from enum
13999 vfp_or_neon_is_neon_bits.
14001 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14002 current instruction's condition is COND_ALWAYS, the condition field is
14003 changed to inst.uncond_value. This is necessary because instructions shared
14004 between VFP and Neon may be conditional for the VFP variants only, and the
14005 unconditional Neon version must have, e.g., 0xF in the condition field. */
14008 vfp_or_neon_is_neon (unsigned check)
14010 /* Conditions are always legal in Thumb mode (IT blocks). */
14011 if (!thumb_mode && (check & NEON_CHECK_CC))
14013 if (inst.cond != COND_ALWAYS)
14015 first_error (_(BAD_COND));
14018 if (inst.uncond_value != -1)
14019 inst.instruction |= inst.uncond_value << 28;
14022 if ((check & NEON_CHECK_ARCH)
14023 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
14025 first_error (_(BAD_FPU));
14033 do_neon_addsub_if_i (void)
14035 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14038 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14041 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14042 affected if we specify unsigned args. */
14043 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14046 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14048 V<op> A,B (A is operand 0, B is operand 2)
14053 so handle that case specially. */
14056 neon_exchange_operands (void)
14058 void *scratch = alloca (sizeof (inst.operands[0]));
14059 if (inst.operands[1].present)
14061 /* Swap operands[1] and operands[2]. */
14062 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14063 inst.operands[1] = inst.operands[2];
14064 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14068 inst.operands[1] = inst.operands[2];
14069 inst.operands[2] = inst.operands[0];
14074 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14076 if (inst.operands[2].isreg)
14079 neon_exchange_operands ();
14080 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14084 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14085 struct neon_type_el et = neon_check_type (2, rs,
14086 N_EQK | N_SIZ, immtypes | N_KEY);
14088 NEON_ENCODE (IMMED, inst);
14089 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14090 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14091 inst.instruction |= LOW4 (inst.operands[1].reg);
14092 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14093 inst.instruction |= neon_quad (rs) << 6;
14094 inst.instruction |= (et.type == NT_float) << 10;
14095 inst.instruction |= neon_logbits (et.size) << 18;
14097 neon_dp_fixup (&inst);
14104 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14108 do_neon_cmp_inv (void)
14110 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14116 neon_compare (N_IF_32, N_IF_32, FALSE);
14119 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14120 scalars, which are encoded in 5 bits, M : Rm.
14121 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14122 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14126 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14128 unsigned regno = NEON_SCALAR_REG (scalar);
14129 unsigned elno = NEON_SCALAR_INDEX (scalar);
14134 if (regno > 7 || elno > 3)
14136 return regno | (elno << 3);
14139 if (regno > 15 || elno > 1)
14141 return regno | (elno << 4);
14145 first_error (_("scalar out of range for multiply instruction"));
14151 /* Encode multiply / multiply-accumulate scalar instructions. */
14154 neon_mul_mac (struct neon_type_el et, int ubit)
14158 /* Give a more helpful error message if we have an invalid type. */
14159 if (et.type == NT_invtype)
14162 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14163 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14164 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14165 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14166 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14167 inst.instruction |= LOW4 (scalar);
14168 inst.instruction |= HI1 (scalar) << 5;
14169 inst.instruction |= (et.type == NT_float) << 8;
14170 inst.instruction |= neon_logbits (et.size) << 20;
14171 inst.instruction |= (ubit != 0) << 24;
14173 neon_dp_fixup (&inst);
14177 do_neon_mac_maybe_scalar (void)
14179 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14182 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14185 if (inst.operands[2].isscalar)
14187 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14188 struct neon_type_el et = neon_check_type (3, rs,
14189 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14190 NEON_ENCODE (SCALAR, inst);
14191 neon_mul_mac (et, neon_quad (rs));
14195 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14196 affected if we specify unsigned args. */
14197 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14202 do_neon_fmac (void)
14204 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14207 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14210 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14216 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14217 struct neon_type_el et = neon_check_type (3, rs,
14218 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14219 neon_three_same (neon_quad (rs), 0, et.size);
14222 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14223 same types as the MAC equivalents. The polynomial type for this instruction
14224 is encoded the same as the integer type. */
14229 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14232 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14235 if (inst.operands[2].isscalar)
14236 do_neon_mac_maybe_scalar ();
14238 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14242 do_neon_qdmulh (void)
14244 if (inst.operands[2].isscalar)
14246 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14247 struct neon_type_el et = neon_check_type (3, rs,
14248 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14249 NEON_ENCODE (SCALAR, inst);
14250 neon_mul_mac (et, neon_quad (rs));
14254 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14255 struct neon_type_el et = neon_check_type (3, rs,
14256 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14257 NEON_ENCODE (INTEGER, inst);
14258 /* The U bit (rounding) comes from bit mask. */
14259 neon_three_same (neon_quad (rs), 0, et.size);
14264 do_neon_fcmp_absolute (void)
14266 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14267 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14268 /* Size field comes from bit mask. */
14269 neon_three_same (neon_quad (rs), 1, -1);
14273 do_neon_fcmp_absolute_inv (void)
14275 neon_exchange_operands ();
14276 do_neon_fcmp_absolute ();
14280 do_neon_step (void)
14282 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14283 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14284 neon_three_same (neon_quad (rs), 0, -1);
14288 do_neon_abs_neg (void)
14290 enum neon_shape rs;
14291 struct neon_type_el et;
14293 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14296 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14299 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14300 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14302 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14303 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14304 inst.instruction |= LOW4 (inst.operands[1].reg);
14305 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14306 inst.instruction |= neon_quad (rs) << 6;
14307 inst.instruction |= (et.type == NT_float) << 10;
14308 inst.instruction |= neon_logbits (et.size) << 18;
14310 neon_dp_fixup (&inst);
14316 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14317 struct neon_type_el et = neon_check_type (2, rs,
14318 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14319 int imm = inst.operands[2].imm;
14320 constraint (imm < 0 || (unsigned)imm >= et.size,
14321 _("immediate out of range for insert"));
14322 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14328 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14329 struct neon_type_el et = neon_check_type (2, rs,
14330 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14331 int imm = inst.operands[2].imm;
14332 constraint (imm < 1 || (unsigned)imm > et.size,
14333 _("immediate out of range for insert"));
14334 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14338 do_neon_qshlu_imm (void)
14340 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14341 struct neon_type_el et = neon_check_type (2, rs,
14342 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14343 int imm = inst.operands[2].imm;
14344 constraint (imm < 0 || (unsigned)imm >= et.size,
14345 _("immediate out of range for shift"));
14346 /* Only encodes the 'U present' variant of the instruction.
14347 In this case, signed types have OP (bit 8) set to 0.
14348 Unsigned types have OP set to 1. */
14349 inst.instruction |= (et.type == NT_unsigned) << 8;
14350 /* The rest of the bits are the same as other immediate shifts. */
14351 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14355 do_neon_qmovn (void)
14357 struct neon_type_el et = neon_check_type (2, NS_DQ,
14358 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14359 /* Saturating move where operands can be signed or unsigned, and the
14360 destination has the same signedness. */
14361 NEON_ENCODE (INTEGER, inst);
14362 if (et.type == NT_unsigned)
14363 inst.instruction |= 0xc0;
14365 inst.instruction |= 0x80;
14366 neon_two_same (0, 1, et.size / 2);
14370 do_neon_qmovun (void)
14372 struct neon_type_el et = neon_check_type (2, NS_DQ,
14373 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14374 /* Saturating move with unsigned results. Operands must be signed. */
14375 NEON_ENCODE (INTEGER, inst);
14376 neon_two_same (0, 1, et.size / 2);
14380 do_neon_rshift_sat_narrow (void)
14382 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14383 or unsigned. If operands are unsigned, results must also be unsigned. */
14384 struct neon_type_el et = neon_check_type (2, NS_DQI,
14385 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14386 int imm = inst.operands[2].imm;
14387 /* This gets the bounds check, size encoding and immediate bits calculation
14391 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14392 VQMOVN.I<size> <Dd>, <Qm>. */
14395 inst.operands[2].present = 0;
14396 inst.instruction = N_MNEM_vqmovn;
14401 constraint (imm < 1 || (unsigned)imm > et.size,
14402 _("immediate out of range"));
14403 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14407 do_neon_rshift_sat_narrow_u (void)
14409 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14410 or unsigned. If operands are unsigned, results must also be unsigned. */
14411 struct neon_type_el et = neon_check_type (2, NS_DQI,
14412 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14413 int imm = inst.operands[2].imm;
14414 /* This gets the bounds check, size encoding and immediate bits calculation
14418 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14419 VQMOVUN.I<size> <Dd>, <Qm>. */
14422 inst.operands[2].present = 0;
14423 inst.instruction = N_MNEM_vqmovun;
14428 constraint (imm < 1 || (unsigned)imm > et.size,
14429 _("immediate out of range"));
14430 /* FIXME: The manual is kind of unclear about what value U should have in
14431 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14433 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14437 do_neon_movn (void)
14439 struct neon_type_el et = neon_check_type (2, NS_DQ,
14440 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14441 NEON_ENCODE (INTEGER, inst);
14442 neon_two_same (0, 1, et.size / 2);
14446 do_neon_rshift_narrow (void)
14448 struct neon_type_el et = neon_check_type (2, NS_DQI,
14449 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14450 int imm = inst.operands[2].imm;
14451 /* This gets the bounds check, size encoding and immediate bits calculation
14455 /* If immediate is zero then we are a pseudo-instruction for
14456 VMOVN.I<size> <Dd>, <Qm> */
14459 inst.operands[2].present = 0;
14460 inst.instruction = N_MNEM_vmovn;
14465 constraint (imm < 1 || (unsigned)imm > et.size,
14466 _("immediate out of range for narrowing operation"));
14467 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14471 do_neon_shll (void)
14473 /* FIXME: Type checking when lengthening. */
14474 struct neon_type_el et = neon_check_type (2, NS_QDI,
14475 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14476 unsigned imm = inst.operands[2].imm;
14478 if (imm == et.size)
14480 /* Maximum shift variant. */
14481 NEON_ENCODE (INTEGER, inst);
14482 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14483 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14484 inst.instruction |= LOW4 (inst.operands[1].reg);
14485 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14486 inst.instruction |= neon_logbits (et.size) << 18;
14488 neon_dp_fixup (&inst);
14492 /* A more-specific type check for non-max versions. */
14493 et = neon_check_type (2, NS_QDI,
14494 N_EQK | N_DBL, N_SU_32 | N_KEY);
14495 NEON_ENCODE (IMMED, inst);
14496 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14500 /* Check the various types for the VCVT instruction, and return which version
14501 the current instruction is. */
14504 neon_cvt_flavour (enum neon_shape rs)
14506 #define CVT_VAR(C,X,Y) \
14507 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14508 if (et.type != NT_invtype) \
14510 inst.error = NULL; \
14513 struct neon_type_el et;
14514 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14515 || rs == NS_FF) ? N_VFP : 0;
14516 /* The instruction versions which take an immediate take one register
14517 argument, which is extended to the width of the full register. Thus the
14518 "source" and "destination" registers must have the same width. Hack that
14519 here by making the size equal to the key (wider, in this case) operand. */
14520 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14522 CVT_VAR (0, N_S32, N_F32);
14523 CVT_VAR (1, N_U32, N_F32);
14524 CVT_VAR (2, N_F32, N_S32);
14525 CVT_VAR (3, N_F32, N_U32);
14526 /* Half-precision conversions. */
14527 CVT_VAR (4, N_F32, N_F16);
14528 CVT_VAR (5, N_F16, N_F32);
14532 /* VFP instructions. */
14533 CVT_VAR (6, N_F32, N_F64);
14534 CVT_VAR (7, N_F64, N_F32);
14535 CVT_VAR (8, N_S32, N_F64 | key);
14536 CVT_VAR (9, N_U32, N_F64 | key);
14537 CVT_VAR (10, N_F64 | key, N_S32);
14538 CVT_VAR (11, N_F64 | key, N_U32);
14539 /* VFP instructions with bitshift. */
14540 CVT_VAR (12, N_F32 | key, N_S16);
14541 CVT_VAR (13, N_F32 | key, N_U16);
14542 CVT_VAR (14, N_F64 | key, N_S16);
14543 CVT_VAR (15, N_F64 | key, N_U16);
14544 CVT_VAR (16, N_S16, N_F32 | key);
14545 CVT_VAR (17, N_U16, N_F32 | key);
14546 CVT_VAR (18, N_S16, N_F64 | key);
14547 CVT_VAR (19, N_U16, N_F64 | key);
14553 /* Neon-syntax VFP conversions. */
14556 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14558 const char *opname = 0;
14560 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14562 /* Conversions with immediate bitshift. */
14563 const char *enc[] =
14587 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14589 opname = enc[flavour];
14590 constraint (inst.operands[0].reg != inst.operands[1].reg,
14591 _("operands 0 and 1 must be the same register"));
14592 inst.operands[1] = inst.operands[2];
14593 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14598 /* Conversions without bitshift. */
14599 const char *enc[] =
14615 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14616 opname = enc[flavour];
14620 do_vfp_nsyn_opcode (opname);
14624 do_vfp_nsyn_cvtz (void)
14626 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14627 int flavour = neon_cvt_flavour (rs);
14628 const char *enc[] =
14642 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14643 do_vfp_nsyn_opcode (enc[flavour]);
14647 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14649 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14650 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14651 int flavour = neon_cvt_flavour (rs);
14653 /* PR11109: Handle round-to-zero for VCVT conversions. */
14655 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14656 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14657 && (rs == NS_FD || rs == NS_FF))
14659 do_vfp_nsyn_cvtz ();
14663 /* VFP rather than Neon conversions. */
14666 do_vfp_nsyn_cvt (rs, flavour);
14676 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14678 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14681 /* Fixed-point conversion with #0 immediate is encoded as an
14682 integer conversion. */
14683 if (inst.operands[2].present && inst.operands[2].imm == 0)
14685 immbits = 32 - inst.operands[2].imm;
14686 NEON_ENCODE (IMMED, inst);
14688 inst.instruction |= enctab[flavour];
14689 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14690 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14691 inst.instruction |= LOW4 (inst.operands[1].reg);
14692 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14693 inst.instruction |= neon_quad (rs) << 6;
14694 inst.instruction |= 1 << 21;
14695 inst.instruction |= immbits << 16;
14697 neon_dp_fixup (&inst);
14705 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14707 NEON_ENCODE (INTEGER, inst);
14709 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14713 inst.instruction |= enctab[flavour];
14715 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14716 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14717 inst.instruction |= LOW4 (inst.operands[1].reg);
14718 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14719 inst.instruction |= neon_quad (rs) << 6;
14720 inst.instruction |= 2 << 18;
14722 neon_dp_fixup (&inst);
14726 /* Half-precision conversions for Advanced SIMD -- neon. */
14731 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14733 as_bad (_("operand size must match register width"));
14738 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14740 as_bad (_("operand size must match register width"));
14745 inst.instruction = 0x3b60600;
14747 inst.instruction = 0x3b60700;
14749 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14750 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14751 inst.instruction |= LOW4 (inst.operands[1].reg);
14752 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14753 neon_dp_fixup (&inst);
14757 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14758 do_vfp_nsyn_cvt (rs, flavour);
14763 do_neon_cvtr (void)
14765 do_neon_cvt_1 (FALSE);
14771 do_neon_cvt_1 (TRUE);
14775 do_neon_cvtb (void)
14777 inst.instruction = 0xeb20a40;
14779 /* The sizes are attached to the mnemonic. */
14780 if (inst.vectype.el[0].type != NT_invtype
14781 && inst.vectype.el[0].size == 16)
14782 inst.instruction |= 0x00010000;
14784 /* Programmer's syntax: the sizes are attached to the operands. */
14785 else if (inst.operands[0].vectype.type != NT_invtype
14786 && inst.operands[0].vectype.size == 16)
14787 inst.instruction |= 0x00010000;
14789 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14790 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14791 do_vfp_cond_or_thumb ();
14796 do_neon_cvtt (void)
14799 inst.instruction |= 0x80;
14803 neon_move_immediate (void)
14805 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14806 struct neon_type_el et = neon_check_type (2, rs,
14807 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14808 unsigned immlo, immhi = 0, immbits;
14809 int op, cmode, float_p;
14811 constraint (et.type == NT_invtype,
14812 _("operand size must be specified for immediate VMOV"));
14814 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14815 op = (inst.instruction & (1 << 5)) != 0;
14817 immlo = inst.operands[1].imm;
14818 if (inst.operands[1].regisimm)
14819 immhi = inst.operands[1].reg;
14821 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14822 _("immediate has bits set outside the operand size"));
14824 float_p = inst.operands[1].immisfloat;
14826 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14827 et.size, et.type)) == FAIL)
14829 /* Invert relevant bits only. */
14830 neon_invert_size (&immlo, &immhi, et.size);
14831 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14832 with one or the other; those cases are caught by
14833 neon_cmode_for_move_imm. */
14835 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14836 &op, et.size, et.type)) == FAIL)
14838 first_error (_("immediate out of range"));
14843 inst.instruction &= ~(1 << 5);
14844 inst.instruction |= op << 5;
14846 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14847 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14848 inst.instruction |= neon_quad (rs) << 6;
14849 inst.instruction |= cmode << 8;
14851 neon_write_immbits (immbits);
14857 if (inst.operands[1].isreg)
14859 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14861 NEON_ENCODE (INTEGER, inst);
14862 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14863 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14864 inst.instruction |= LOW4 (inst.operands[1].reg);
14865 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14866 inst.instruction |= neon_quad (rs) << 6;
14870 NEON_ENCODE (IMMED, inst);
14871 neon_move_immediate ();
14874 neon_dp_fixup (&inst);
14877 /* Encode instructions of form:
14879 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14880 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14883 neon_mixed_length (struct neon_type_el et, unsigned size)
14885 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14886 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14887 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14888 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14889 inst.instruction |= LOW4 (inst.operands[2].reg);
14890 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14891 inst.instruction |= (et.type == NT_unsigned) << 24;
14892 inst.instruction |= neon_logbits (size) << 20;
14894 neon_dp_fixup (&inst);
14898 do_neon_dyadic_long (void)
14900 /* FIXME: Type checking for lengthening op. */
14901 struct neon_type_el et = neon_check_type (3, NS_QDD,
14902 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14903 neon_mixed_length (et, et.size);
14907 do_neon_abal (void)
14909 struct neon_type_el et = neon_check_type (3, NS_QDD,
14910 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14911 neon_mixed_length (et, et.size);
14915 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14917 if (inst.operands[2].isscalar)
14919 struct neon_type_el et = neon_check_type (3, NS_QDS,
14920 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14921 NEON_ENCODE (SCALAR, inst);
14922 neon_mul_mac (et, et.type == NT_unsigned);
14926 struct neon_type_el et = neon_check_type (3, NS_QDD,
14927 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14928 NEON_ENCODE (INTEGER, inst);
14929 neon_mixed_length (et, et.size);
14934 do_neon_mac_maybe_scalar_long (void)
14936 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14940 do_neon_dyadic_wide (void)
14942 struct neon_type_el et = neon_check_type (3, NS_QQD,
14943 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14944 neon_mixed_length (et, et.size);
14948 do_neon_dyadic_narrow (void)
14950 struct neon_type_el et = neon_check_type (3, NS_QDD,
14951 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14952 /* Operand sign is unimportant, and the U bit is part of the opcode,
14953 so force the operand type to integer. */
14954 et.type = NT_integer;
14955 neon_mixed_length (et, et.size / 2);
14959 do_neon_mul_sat_scalar_long (void)
14961 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14965 do_neon_vmull (void)
14967 if (inst.operands[2].isscalar)
14968 do_neon_mac_maybe_scalar_long ();
14971 struct neon_type_el et = neon_check_type (3, NS_QDD,
14972 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14973 if (et.type == NT_poly)
14974 NEON_ENCODE (POLY, inst);
14976 NEON_ENCODE (INTEGER, inst);
14977 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14978 zero. Should be OK as-is. */
14979 neon_mixed_length (et, et.size);
14986 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14987 struct neon_type_el et = neon_check_type (3, rs,
14988 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14989 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14991 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14992 _("shift out of range"));
14993 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14994 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14995 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14996 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14997 inst.instruction |= LOW4 (inst.operands[2].reg);
14998 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14999 inst.instruction |= neon_quad (rs) << 6;
15000 inst.instruction |= imm << 8;
15002 neon_dp_fixup (&inst);
15008 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15009 struct neon_type_el et = neon_check_type (2, rs,
15010 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15011 unsigned op = (inst.instruction >> 7) & 3;
15012 /* N (width of reversed regions) is encoded as part of the bitmask. We
15013 extract it here to check the elements to be reversed are smaller.
15014 Otherwise we'd get a reserved instruction. */
15015 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15016 gas_assert (elsize != 0);
15017 constraint (et.size >= elsize,
15018 _("elements must be smaller than reversal region"));
15019 neon_two_same (neon_quad (rs), 1, et.size);
15025 if (inst.operands[1].isscalar)
15027 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15028 struct neon_type_el et = neon_check_type (2, rs,
15029 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15030 unsigned sizebits = et.size >> 3;
15031 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15032 int logsize = neon_logbits (et.size);
15033 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15035 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15038 NEON_ENCODE (SCALAR, inst);
15039 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15040 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15041 inst.instruction |= LOW4 (dm);
15042 inst.instruction |= HI1 (dm) << 5;
15043 inst.instruction |= neon_quad (rs) << 6;
15044 inst.instruction |= x << 17;
15045 inst.instruction |= sizebits << 16;
15047 neon_dp_fixup (&inst);
15051 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15052 struct neon_type_el et = neon_check_type (2, rs,
15053 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15054 /* Duplicate ARM register to lanes of vector. */
15055 NEON_ENCODE (ARMREG, inst);
15058 case 8: inst.instruction |= 0x400000; break;
15059 case 16: inst.instruction |= 0x000020; break;
15060 case 32: inst.instruction |= 0x000000; break;
15063 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15064 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15065 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15066 inst.instruction |= neon_quad (rs) << 21;
15067 /* The encoding for this instruction is identical for the ARM and Thumb
15068 variants, except for the condition field. */
15069 do_vfp_cond_or_thumb ();
15073 /* VMOV has particularly many variations. It can be one of:
15074 0. VMOV<c><q> <Qd>, <Qm>
15075 1. VMOV<c><q> <Dd>, <Dm>
15076 (Register operations, which are VORR with Rm = Rn.)
15077 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15078 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15080 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15081 (ARM register to scalar.)
15082 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15083 (Two ARM registers to vector.)
15084 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15085 (Scalar to ARM register.)
15086 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15087 (Vector to two ARM registers.)
15088 8. VMOV.F32 <Sd>, <Sm>
15089 9. VMOV.F64 <Dd>, <Dm>
15090 (VFP register moves.)
15091 10. VMOV.F32 <Sd>, #imm
15092 11. VMOV.F64 <Dd>, #imm
15093 (VFP float immediate load.)
15094 12. VMOV <Rd>, <Sm>
15095 (VFP single to ARM reg.)
15096 13. VMOV <Sd>, <Rm>
15097 (ARM reg to VFP single.)
15098 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15099 (Two ARM regs to two VFP singles.)
15100 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15101 (Two VFP singles to two ARM regs.)
15103 These cases can be disambiguated using neon_select_shape, except cases 1/9
15104 and 3/11 which depend on the operand type too.
15106 All the encoded bits are hardcoded by this function.
15108 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15109 Cases 5, 7 may be used with VFPv2 and above.
15111 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15112 can specify a type where it doesn't make sense to, and is ignored). */
15117 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15118 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15120 struct neon_type_el et;
15121 const char *ldconst = 0;
15125 case NS_DD: /* case 1/9. */
15126 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15127 /* It is not an error here if no type is given. */
15129 if (et.type == NT_float && et.size == 64)
15131 do_vfp_nsyn_opcode ("fcpyd");
15134 /* fall through. */
15136 case NS_QQ: /* case 0/1. */
15138 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15140 /* The architecture manual I have doesn't explicitly state which
15141 value the U bit should have for register->register moves, but
15142 the equivalent VORR instruction has U = 0, so do that. */
15143 inst.instruction = 0x0200110;
15144 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15145 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15146 inst.instruction |= LOW4 (inst.operands[1].reg);
15147 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15148 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15149 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15150 inst.instruction |= neon_quad (rs) << 6;
15152 neon_dp_fixup (&inst);
15156 case NS_DI: /* case 3/11. */
15157 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15159 if (et.type == NT_float && et.size == 64)
15161 /* case 11 (fconstd). */
15162 ldconst = "fconstd";
15163 goto encode_fconstd;
15165 /* fall through. */
15167 case NS_QI: /* case 2/3. */
15168 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15170 inst.instruction = 0x0800010;
15171 neon_move_immediate ();
15172 neon_dp_fixup (&inst);
15175 case NS_SR: /* case 4. */
15177 unsigned bcdebits = 0;
15179 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15180 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15182 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15183 logsize = neon_logbits (et.size);
15185 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15187 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15188 && et.size != 32, _(BAD_FPU));
15189 constraint (et.type == NT_invtype, _("bad type for scalar"));
15190 constraint (x >= 64 / et.size, _("scalar index out of range"));
15194 case 8: bcdebits = 0x8; break;
15195 case 16: bcdebits = 0x1; break;
15196 case 32: bcdebits = 0x0; break;
15200 bcdebits |= x << logsize;
15202 inst.instruction = 0xe000b10;
15203 do_vfp_cond_or_thumb ();
15204 inst.instruction |= LOW4 (dn) << 16;
15205 inst.instruction |= HI1 (dn) << 7;
15206 inst.instruction |= inst.operands[1].reg << 12;
15207 inst.instruction |= (bcdebits & 3) << 5;
15208 inst.instruction |= (bcdebits >> 2) << 21;
15212 case NS_DRR: /* case 5 (fmdrr). */
15213 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15216 inst.instruction = 0xc400b10;
15217 do_vfp_cond_or_thumb ();
15218 inst.instruction |= LOW4 (inst.operands[0].reg);
15219 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15220 inst.instruction |= inst.operands[1].reg << 12;
15221 inst.instruction |= inst.operands[2].reg << 16;
15224 case NS_RS: /* case 6. */
15227 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15228 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15229 unsigned abcdebits = 0;
15231 et = neon_check_type (2, NS_NULL,
15232 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15233 logsize = neon_logbits (et.size);
15235 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15237 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15238 && et.size != 32, _(BAD_FPU));
15239 constraint (et.type == NT_invtype, _("bad type for scalar"));
15240 constraint (x >= 64 / et.size, _("scalar index out of range"));
15244 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15245 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15246 case 32: abcdebits = 0x00; break;
15250 abcdebits |= x << logsize;
15251 inst.instruction = 0xe100b10;
15252 do_vfp_cond_or_thumb ();
15253 inst.instruction |= LOW4 (dn) << 16;
15254 inst.instruction |= HI1 (dn) << 7;
15255 inst.instruction |= inst.operands[0].reg << 12;
15256 inst.instruction |= (abcdebits & 3) << 5;
15257 inst.instruction |= (abcdebits >> 2) << 21;
15261 case NS_RRD: /* case 7 (fmrrd). */
15262 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15265 inst.instruction = 0xc500b10;
15266 do_vfp_cond_or_thumb ();
15267 inst.instruction |= inst.operands[0].reg << 12;
15268 inst.instruction |= inst.operands[1].reg << 16;
15269 inst.instruction |= LOW4 (inst.operands[2].reg);
15270 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15273 case NS_FF: /* case 8 (fcpys). */
15274 do_vfp_nsyn_opcode ("fcpys");
15277 case NS_FI: /* case 10 (fconsts). */
15278 ldconst = "fconsts";
15280 if (is_quarter_float (inst.operands[1].imm))
15282 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15283 do_vfp_nsyn_opcode (ldconst);
15286 first_error (_("immediate out of range"));
15289 case NS_RF: /* case 12 (fmrs). */
15290 do_vfp_nsyn_opcode ("fmrs");
15293 case NS_FR: /* case 13 (fmsr). */
15294 do_vfp_nsyn_opcode ("fmsr");
15297 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15298 (one of which is a list), but we have parsed four. Do some fiddling to
15299 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15301 case NS_RRFF: /* case 14 (fmrrs). */
15302 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15303 _("VFP registers must be adjacent"));
15304 inst.operands[2].imm = 2;
15305 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15306 do_vfp_nsyn_opcode ("fmrrs");
15309 case NS_FFRR: /* case 15 (fmsrr). */
15310 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15311 _("VFP registers must be adjacent"));
15312 inst.operands[1] = inst.operands[2];
15313 inst.operands[2] = inst.operands[3];
15314 inst.operands[0].imm = 2;
15315 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15316 do_vfp_nsyn_opcode ("fmsrr");
15325 do_neon_rshift_round_imm (void)
15327 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15328 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15329 int imm = inst.operands[2].imm;
15331 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15334 inst.operands[2].present = 0;
15339 constraint (imm < 1 || (unsigned)imm > et.size,
15340 _("immediate out of range for shift"));
15341 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15346 do_neon_movl (void)
15348 struct neon_type_el et = neon_check_type (2, NS_QD,
15349 N_EQK | N_DBL, N_SU_32 | N_KEY);
15350 unsigned sizebits = et.size >> 3;
15351 inst.instruction |= sizebits << 19;
15352 neon_two_same (0, et.type == NT_unsigned, -1);
15358 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15359 struct neon_type_el et = neon_check_type (2, rs,
15360 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15361 NEON_ENCODE (INTEGER, inst);
15362 neon_two_same (neon_quad (rs), 1, et.size);
15366 do_neon_zip_uzp (void)
15368 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15369 struct neon_type_el et = neon_check_type (2, rs,
15370 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15371 if (rs == NS_DD && et.size == 32)
15373 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15374 inst.instruction = N_MNEM_vtrn;
15378 neon_two_same (neon_quad (rs), 1, et.size);
15382 do_neon_sat_abs_neg (void)
15384 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15385 struct neon_type_el et = neon_check_type (2, rs,
15386 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15387 neon_two_same (neon_quad (rs), 1, et.size);
15391 do_neon_pair_long (void)
15393 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15394 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15395 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15396 inst.instruction |= (et.type == NT_unsigned) << 7;
15397 neon_two_same (neon_quad (rs), 1, et.size);
15401 do_neon_recip_est (void)
15403 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15404 struct neon_type_el et = neon_check_type (2, rs,
15405 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15406 inst.instruction |= (et.type == NT_float) << 8;
15407 neon_two_same (neon_quad (rs), 1, et.size);
15413 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15414 struct neon_type_el et = neon_check_type (2, rs,
15415 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15416 neon_two_same (neon_quad (rs), 1, et.size);
15422 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15423 struct neon_type_el et = neon_check_type (2, rs,
15424 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15425 neon_two_same (neon_quad (rs), 1, et.size);
15431 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15432 struct neon_type_el et = neon_check_type (2, rs,
15433 N_EQK | N_INT, N_8 | N_KEY);
15434 neon_two_same (neon_quad (rs), 1, et.size);
15440 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15441 neon_two_same (neon_quad (rs), 1, -1);
15445 do_neon_tbl_tbx (void)
15447 unsigned listlenbits;
15448 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15450 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15452 first_error (_("bad list length for table lookup"));
15456 listlenbits = inst.operands[1].imm - 1;
15457 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15458 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15459 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15460 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15461 inst.instruction |= LOW4 (inst.operands[2].reg);
15462 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15463 inst.instruction |= listlenbits << 8;
15465 neon_dp_fixup (&inst);
15469 do_neon_ldm_stm (void)
15471 /* P, U and L bits are part of bitmask. */
15472 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15473 unsigned offsetbits = inst.operands[1].imm * 2;
15475 if (inst.operands[1].issingle)
15477 do_vfp_nsyn_ldm_stm (is_dbmode);
15481 constraint (is_dbmode && !inst.operands[0].writeback,
15482 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15484 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15485 _("register list must contain at least 1 and at most 16 "
15488 inst.instruction |= inst.operands[0].reg << 16;
15489 inst.instruction |= inst.operands[0].writeback << 21;
15490 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15491 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15493 inst.instruction |= offsetbits;
15495 do_vfp_cond_or_thumb ();
15499 do_neon_ldr_str (void)
15501 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15503 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15504 And is UNPREDICTABLE in thumb mode. */
15506 && inst.operands[1].reg == REG_PC
15507 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15509 if (!thumb_mode && warn_on_deprecated)
15510 as_warn (_("Use of PC here is deprecated"));
15512 inst.error = _("Use of PC here is UNPREDICTABLE");
15515 if (inst.operands[0].issingle)
15518 do_vfp_nsyn_opcode ("flds");
15520 do_vfp_nsyn_opcode ("fsts");
15525 do_vfp_nsyn_opcode ("fldd");
15527 do_vfp_nsyn_opcode ("fstd");
15531 /* "interleave" version also handles non-interleaving register VLD1/VST1
15535 do_neon_ld_st_interleave (void)
15537 struct neon_type_el et = neon_check_type (1, NS_NULL,
15538 N_8 | N_16 | N_32 | N_64);
15539 unsigned alignbits = 0;
15541 /* The bits in this table go:
15542 0: register stride of one (0) or two (1)
15543 1,2: register list length, minus one (1, 2, 3, 4).
15544 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15545 We use -1 for invalid entries. */
15546 const int typetable[] =
15548 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15549 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15550 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15551 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15555 if (et.type == NT_invtype)
15558 if (inst.operands[1].immisalign)
15559 switch (inst.operands[1].imm >> 8)
15561 case 64: alignbits = 1; break;
15563 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15564 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15565 goto bad_alignment;
15569 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15570 goto bad_alignment;
15575 first_error (_("bad alignment"));
15579 inst.instruction |= alignbits << 4;
15580 inst.instruction |= neon_logbits (et.size) << 6;
15582 /* Bits [4:6] of the immediate in a list specifier encode register stride
15583 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15584 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15585 up the right value for "type" in a table based on this value and the given
15586 list style, then stick it back. */
15587 idx = ((inst.operands[0].imm >> 4) & 7)
15588 | (((inst.instruction >> 8) & 3) << 3);
15590 typebits = typetable[idx];
15592 constraint (typebits == -1, _("bad list type for instruction"));
15594 inst.instruction &= ~0xf00;
15595 inst.instruction |= typebits << 8;
15598 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15599 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15600 otherwise. The variable arguments are a list of pairs of legal (size, align)
15601 values, terminated with -1. */
15604 neon_alignment_bit (int size, int align, int *do_align, ...)
15607 int result = FAIL, thissize, thisalign;
15609 if (!inst.operands[1].immisalign)
15615 va_start (ap, do_align);
15619 thissize = va_arg (ap, int);
15620 if (thissize == -1)
15622 thisalign = va_arg (ap, int);
15624 if (size == thissize && align == thisalign)
15627 while (result != SUCCESS);
15631 if (result == SUCCESS)
15634 first_error (_("unsupported alignment for instruction"));
15640 do_neon_ld_st_lane (void)
15642 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15643 int align_good, do_align = 0;
15644 int logsize = neon_logbits (et.size);
15645 int align = inst.operands[1].imm >> 8;
15646 int n = (inst.instruction >> 8) & 3;
15647 int max_el = 64 / et.size;
15649 if (et.type == NT_invtype)
15652 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15653 _("bad list length"));
15654 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15655 _("scalar index out of range"));
15656 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15658 _("stride of 2 unavailable when element size is 8"));
15662 case 0: /* VLD1 / VST1. */
15663 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15665 if (align_good == FAIL)
15669 unsigned alignbits = 0;
15672 case 16: alignbits = 0x1; break;
15673 case 32: alignbits = 0x3; break;
15676 inst.instruction |= alignbits << 4;
15680 case 1: /* VLD2 / VST2. */
15681 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15683 if (align_good == FAIL)
15686 inst.instruction |= 1 << 4;
15689 case 2: /* VLD3 / VST3. */
15690 constraint (inst.operands[1].immisalign,
15691 _("can't use alignment with this instruction"));
15694 case 3: /* VLD4 / VST4. */
15695 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15696 16, 64, 32, 64, 32, 128, -1);
15697 if (align_good == FAIL)
15701 unsigned alignbits = 0;
15704 case 8: alignbits = 0x1; break;
15705 case 16: alignbits = 0x1; break;
15706 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15709 inst.instruction |= alignbits << 4;
15716 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15717 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15718 inst.instruction |= 1 << (4 + logsize);
15720 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15721 inst.instruction |= logsize << 10;
15724 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15727 do_neon_ld_dup (void)
15729 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15730 int align_good, do_align = 0;
15732 if (et.type == NT_invtype)
15735 switch ((inst.instruction >> 8) & 3)
15737 case 0: /* VLD1. */
15738 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15739 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15740 &do_align, 16, 16, 32, 32, -1);
15741 if (align_good == FAIL)
15743 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15746 case 2: inst.instruction |= 1 << 5; break;
15747 default: first_error (_("bad list length")); return;
15749 inst.instruction |= neon_logbits (et.size) << 6;
15752 case 1: /* VLD2. */
15753 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15754 &do_align, 8, 16, 16, 32, 32, 64, -1);
15755 if (align_good == FAIL)
15757 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15758 _("bad list length"));
15759 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15760 inst.instruction |= 1 << 5;
15761 inst.instruction |= neon_logbits (et.size) << 6;
15764 case 2: /* VLD3. */
15765 constraint (inst.operands[1].immisalign,
15766 _("can't use alignment with this instruction"));
15767 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15768 _("bad list length"));
15769 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15770 inst.instruction |= 1 << 5;
15771 inst.instruction |= neon_logbits (et.size) << 6;
15774 case 3: /* VLD4. */
15776 int align = inst.operands[1].imm >> 8;
15777 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15778 16, 64, 32, 64, 32, 128, -1);
15779 if (align_good == FAIL)
15781 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15782 _("bad list length"));
15783 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15784 inst.instruction |= 1 << 5;
15785 if (et.size == 32 && align == 128)
15786 inst.instruction |= 0x3 << 6;
15788 inst.instruction |= neon_logbits (et.size) << 6;
15795 inst.instruction |= do_align << 4;
15798 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15799 apart from bits [11:4]. */
15802 do_neon_ldx_stx (void)
15804 if (inst.operands[1].isreg)
15805 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15807 switch (NEON_LANE (inst.operands[0].imm))
15809 case NEON_INTERLEAVE_LANES:
15810 NEON_ENCODE (INTERLV, inst);
15811 do_neon_ld_st_interleave ();
15814 case NEON_ALL_LANES:
15815 NEON_ENCODE (DUP, inst);
15820 NEON_ENCODE (LANE, inst);
15821 do_neon_ld_st_lane ();
15824 /* L bit comes from bit mask. */
15825 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15826 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15827 inst.instruction |= inst.operands[1].reg << 16;
15829 if (inst.operands[1].postind)
15831 int postreg = inst.operands[1].imm & 0xf;
15832 constraint (!inst.operands[1].immisreg,
15833 _("post-index must be a register"));
15834 constraint (postreg == 0xd || postreg == 0xf,
15835 _("bad register for post-index"));
15836 inst.instruction |= postreg;
15838 else if (inst.operands[1].writeback)
15840 inst.instruction |= 0xd;
15843 inst.instruction |= 0xf;
15846 inst.instruction |= 0xf9000000;
15848 inst.instruction |= 0xf4000000;
15853 do_vfp_nsyn_fpv8 (enum neon_shape rs)
15855 NEON_ENCODE (FPV8, inst);
15858 do_vfp_sp_dyadic ();
15860 do_vfp_dp_rd_rn_rm ();
15863 inst.instruction |= 0x100;
15865 inst.instruction |= 0xf0000000;
15871 set_it_insn_type (OUTSIDE_IT_INSN);
15873 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
15874 first_error (_("invalid instruction shape"));
15878 /* Overall per-instruction processing. */
15880 /* We need to be able to fix up arbitrary expressions in some statements.
15881 This is so that we can handle symbols that are an arbitrary distance from
15882 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15883 which returns part of an address in a form which will be valid for
15884 a data instruction. We do this by pushing the expression into a symbol
15885 in the expr_section, and creating a fix for that. */
15888 fix_new_arm (fragS * frag,
15902 /* Create an absolute valued symbol, so we have something to
15903 refer to in the object file. Unfortunately for us, gas's
15904 generic expression parsing will already have folded out
15905 any use of .set foo/.type foo %function that may have
15906 been used to set type information of the target location,
15907 that's being specified symbolically. We have to presume
15908 the user knows what they are doing. */
15912 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15914 symbol = symbol_find_or_make (name);
15915 S_SET_SEGMENT (symbol, absolute_section);
15916 symbol_set_frag (symbol, &zero_address_frag);
15917 S_SET_VALUE (symbol, exp->X_add_number);
15918 exp->X_op = O_symbol;
15919 exp->X_add_symbol = symbol;
15920 exp->X_add_number = 0;
15926 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15927 (enum bfd_reloc_code_real) reloc);
15931 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15932 pc_rel, (enum bfd_reloc_code_real) reloc);
15936 /* Mark whether the fix is to a THUMB instruction, or an ARM
15938 new_fix->tc_fix_data = thumb_mode;
15941 /* Create a frg for an instruction requiring relaxation. */
15943 output_relax_insn (void)
15949 /* The size of the instruction is unknown, so tie the debug info to the
15950 start of the instruction. */
15951 dwarf2_emit_insn (0);
15953 switch (inst.reloc.exp.X_op)
15956 sym = inst.reloc.exp.X_add_symbol;
15957 offset = inst.reloc.exp.X_add_number;
15961 offset = inst.reloc.exp.X_add_number;
15964 sym = make_expr_symbol (&inst.reloc.exp);
15968 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15969 inst.relax, sym, offset, NULL/*offset, opcode*/);
15970 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15973 /* Write a 32-bit thumb instruction to buf. */
15975 put_thumb32_insn (char * buf, unsigned long insn)
15977 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15978 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15982 output_inst (const char * str)
15988 as_bad ("%s -- `%s'", inst.error, str);
15993 output_relax_insn ();
15996 if (inst.size == 0)
15999 to = frag_more (inst.size);
16000 /* PR 9814: Record the thumb mode into the current frag so that we know
16001 what type of NOP padding to use, if necessary. We override any previous
16002 setting so that if the mode has changed then the NOPS that we use will
16003 match the encoding of the last instruction in the frag. */
16004 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
16006 if (thumb_mode && (inst.size > THUMB_SIZE))
16008 gas_assert (inst.size == (2 * THUMB_SIZE));
16009 put_thumb32_insn (to, inst.instruction);
16011 else if (inst.size > INSN_SIZE)
16013 gas_assert (inst.size == (2 * INSN_SIZE));
16014 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16015 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
16018 md_number_to_chars (to, inst.instruction, inst.size);
16020 if (inst.reloc.type != BFD_RELOC_UNUSED)
16021 fix_new_arm (frag_now, to - frag_now->fr_literal,
16022 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16025 dwarf2_emit_insn (inst.size);
16029 output_it_inst (int cond, int mask, char * to)
16031 unsigned long instruction = 0xbf00;
16034 instruction |= mask;
16035 instruction |= cond << 4;
16039 to = frag_more (2);
16041 dwarf2_emit_insn (2);
16045 md_number_to_chars (to, instruction, 2);
16050 /* Tag values used in struct asm_opcode's tag field. */
16053 OT_unconditional, /* Instruction cannot be conditionalized.
16054 The ARM condition field is still 0xE. */
16055 OT_unconditionalF, /* Instruction cannot be conditionalized
16056 and carries 0xF in its ARM condition field. */
16057 OT_csuffix, /* Instruction takes a conditional suffix. */
16058 OT_csuffixF, /* Some forms of the instruction take a conditional
16059 suffix, others place 0xF where the condition field
16061 OT_cinfix3, /* Instruction takes a conditional infix,
16062 beginning at character index 3. (In
16063 unified mode, it becomes a suffix.) */
16064 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16065 tsts, cmps, cmns, and teqs. */
16066 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16067 character index 3, even in unified mode. Used for
16068 legacy instructions where suffix and infix forms
16069 may be ambiguous. */
16070 OT_csuf_or_in3, /* Instruction takes either a conditional
16071 suffix or an infix at character index 3. */
16072 OT_odd_infix_unc, /* This is the unconditional variant of an
16073 instruction that takes a conditional infix
16074 at an unusual position. In unified mode,
16075 this variant will accept a suffix. */
16076 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16077 are the conditional variants of instructions that
16078 take conditional infixes in unusual positions.
16079 The infix appears at character index
16080 (tag - OT_odd_infix_0). These are not accepted
16081 in unified mode. */
16084 /* Subroutine of md_assemble, responsible for looking up the primary
16085 opcode from the mnemonic the user wrote. STR points to the
16086 beginning of the mnemonic.
16088 This is not simply a hash table lookup, because of conditional
16089 variants. Most instructions have conditional variants, which are
16090 expressed with a _conditional affix_ to the mnemonic. If we were
16091 to encode each conditional variant as a literal string in the opcode
16092 table, it would have approximately 20,000 entries.
16094 Most mnemonics take this affix as a suffix, and in unified syntax,
16095 'most' is upgraded to 'all'. However, in the divided syntax, some
16096 instructions take the affix as an infix, notably the s-variants of
16097 the arithmetic instructions. Of those instructions, all but six
16098 have the infix appear after the third character of the mnemonic.
16100 Accordingly, the algorithm for looking up primary opcodes given
16103 1. Look up the identifier in the opcode table.
16104 If we find a match, go to step U.
16106 2. Look up the last two characters of the identifier in the
16107 conditions table. If we find a match, look up the first N-2
16108 characters of the identifier in the opcode table. If we
16109 find a match, go to step CE.
16111 3. Look up the fourth and fifth characters of the identifier in
16112 the conditions table. If we find a match, extract those
16113 characters from the identifier, and look up the remaining
16114 characters in the opcode table. If we find a match, go
16119 U. Examine the tag field of the opcode structure, in case this is
16120 one of the six instructions with its conditional infix in an
16121 unusual place. If it is, the tag tells us where to find the
16122 infix; look it up in the conditions table and set inst.cond
16123 accordingly. Otherwise, this is an unconditional instruction.
16124 Again set inst.cond accordingly. Return the opcode structure.
16126 CE. Examine the tag field to make sure this is an instruction that
16127 should receive a conditional suffix. If it is not, fail.
16128 Otherwise, set inst.cond from the suffix we already looked up,
16129 and return the opcode structure.
16131 CM. Examine the tag field to make sure this is an instruction that
16132 should receive a conditional infix after the third character.
16133 If it is not, fail. Otherwise, undo the edits to the current
16134 line of input and proceed as for case CE. */
16136 static const struct asm_opcode *
16137 opcode_lookup (char **str)
16141 const struct asm_opcode *opcode;
16142 const struct asm_cond *cond;
16145 /* Scan up to the end of the mnemonic, which must end in white space,
16146 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16147 for (base = end = *str; *end != '\0'; end++)
16148 if (*end == ' ' || *end == '.')
16154 /* Handle a possible width suffix and/or Neon type suffix. */
16159 /* The .w and .n suffixes are only valid if the unified syntax is in
16161 if (unified_syntax && end[1] == 'w')
16163 else if (unified_syntax && end[1] == 'n')
16168 inst.vectype.elems = 0;
16170 *str = end + offset;
16172 if (end[offset] == '.')
16174 /* See if we have a Neon type suffix (possible in either unified or
16175 non-unified ARM syntax mode). */
16176 if (parse_neon_type (&inst.vectype, str) == FAIL)
16179 else if (end[offset] != '\0' && end[offset] != ' ')
16185 /* Look for unaffixed or special-case affixed mnemonic. */
16186 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16191 if (opcode->tag < OT_odd_infix_0)
16193 inst.cond = COND_ALWAYS;
16197 if (warn_on_deprecated && unified_syntax)
16198 as_warn (_("conditional infixes are deprecated in unified syntax"));
16199 affix = base + (opcode->tag - OT_odd_infix_0);
16200 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16203 inst.cond = cond->value;
16207 /* Cannot have a conditional suffix on a mnemonic of less than two
16209 if (end - base < 3)
16212 /* Look for suffixed mnemonic. */
16214 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16215 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16217 if (opcode && cond)
16220 switch (opcode->tag)
16222 case OT_cinfix3_legacy:
16223 /* Ignore conditional suffixes matched on infix only mnemonics. */
16227 case OT_cinfix3_deprecated:
16228 case OT_odd_infix_unc:
16229 if (!unified_syntax)
16231 /* else fall through */
16235 case OT_csuf_or_in3:
16236 inst.cond = cond->value;
16239 case OT_unconditional:
16240 case OT_unconditionalF:
16242 inst.cond = cond->value;
16245 /* Delayed diagnostic. */
16246 inst.error = BAD_COND;
16247 inst.cond = COND_ALWAYS;
16256 /* Cannot have a usual-position infix on a mnemonic of less than
16257 six characters (five would be a suffix). */
16258 if (end - base < 6)
16261 /* Look for infixed mnemonic in the usual position. */
16263 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16267 memcpy (save, affix, 2);
16268 memmove (affix, affix + 2, (end - affix) - 2);
16269 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16271 memmove (affix + 2, affix, (end - affix) - 2);
16272 memcpy (affix, save, 2);
16275 && (opcode->tag == OT_cinfix3
16276 || opcode->tag == OT_cinfix3_deprecated
16277 || opcode->tag == OT_csuf_or_in3
16278 || opcode->tag == OT_cinfix3_legacy))
16281 if (warn_on_deprecated && unified_syntax
16282 && (opcode->tag == OT_cinfix3
16283 || opcode->tag == OT_cinfix3_deprecated))
16284 as_warn (_("conditional infixes are deprecated in unified syntax"));
16286 inst.cond = cond->value;
16293 /* This function generates an initial IT instruction, leaving its block
16294 virtually open for the new instructions. Eventually,
16295 the mask will be updated by now_it_add_mask () each time
16296 a new instruction needs to be included in the IT block.
16297 Finally, the block is closed with close_automatic_it_block ().
16298 The block closure can be requested either from md_assemble (),
16299 a tencode (), or due to a label hook. */
16302 new_automatic_it_block (int cond)
16304 now_it.state = AUTOMATIC_IT_BLOCK;
16305 now_it.mask = 0x18;
16307 now_it.block_length = 1;
16308 mapping_state (MAP_THUMB);
16309 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16310 now_it.warn_deprecated = FALSE;
16311 now_it.insn_cond = TRUE;
16314 /* Close an automatic IT block.
16315 See comments in new_automatic_it_block (). */
16318 close_automatic_it_block (void)
16320 now_it.mask = 0x10;
16321 now_it.block_length = 0;
16324 /* Update the mask of the current automatically-generated IT
16325 instruction. See comments in new_automatic_it_block (). */
16328 now_it_add_mask (int cond)
16330 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16331 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16332 | ((bitvalue) << (nbit)))
16333 const int resulting_bit = (cond & 1);
16335 now_it.mask &= 0xf;
16336 now_it.mask = SET_BIT_VALUE (now_it.mask,
16338 (5 - now_it.block_length));
16339 now_it.mask = SET_BIT_VALUE (now_it.mask,
16341 ((5 - now_it.block_length) - 1) );
16342 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16345 #undef SET_BIT_VALUE
16348 /* The IT blocks handling machinery is accessed through the these functions:
16349 it_fsm_pre_encode () from md_assemble ()
16350 set_it_insn_type () optional, from the tencode functions
16351 set_it_insn_type_last () ditto
16352 in_it_block () ditto
16353 it_fsm_post_encode () from md_assemble ()
16354 force_automatic_it_block_close () from label habdling functions
16357 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16358 initializing the IT insn type with a generic initial value depending
16359 on the inst.condition.
16360 2) During the tencode function, two things may happen:
16361 a) The tencode function overrides the IT insn type by
16362 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16363 b) The tencode function queries the IT block state by
16364 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16366 Both set_it_insn_type and in_it_block run the internal FSM state
16367 handling function (handle_it_state), because: a) setting the IT insn
16368 type may incur in an invalid state (exiting the function),
16369 and b) querying the state requires the FSM to be updated.
16370 Specifically we want to avoid creating an IT block for conditional
16371 branches, so it_fsm_pre_encode is actually a guess and we can't
16372 determine whether an IT block is required until the tencode () routine
16373 has decided what type of instruction this actually it.
16374 Because of this, if set_it_insn_type and in_it_block have to be used,
16375 set_it_insn_type has to be called first.
16377 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16378 determines the insn IT type depending on the inst.cond code.
16379 When a tencode () routine encodes an instruction that can be
16380 either outside an IT block, or, in the case of being inside, has to be
16381 the last one, set_it_insn_type_last () will determine the proper
16382 IT instruction type based on the inst.cond code. Otherwise,
16383 set_it_insn_type can be called for overriding that logic or
16384 for covering other cases.
16386 Calling handle_it_state () may not transition the IT block state to
16387 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16388 still queried. Instead, if the FSM determines that the state should
16389 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16390 after the tencode () function: that's what it_fsm_post_encode () does.
16392 Since in_it_block () calls the state handling function to get an
16393 updated state, an error may occur (due to invalid insns combination).
16394 In that case, inst.error is set.
16395 Therefore, inst.error has to be checked after the execution of
16396 the tencode () routine.
16398 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16399 any pending state change (if any) that didn't take place in
16400 handle_it_state () as explained above. */
16403 it_fsm_pre_encode (void)
16405 if (inst.cond != COND_ALWAYS)
16406 inst.it_insn_type = INSIDE_IT_INSN;
16408 inst.it_insn_type = OUTSIDE_IT_INSN;
16410 now_it.state_handled = 0;
16413 /* IT state FSM handling function. */
16416 handle_it_state (void)
16418 now_it.state_handled = 1;
16419 now_it.insn_cond = FALSE;
16421 switch (now_it.state)
16423 case OUTSIDE_IT_BLOCK:
16424 switch (inst.it_insn_type)
16426 case OUTSIDE_IT_INSN:
16429 case INSIDE_IT_INSN:
16430 case INSIDE_IT_LAST_INSN:
16431 if (thumb_mode == 0)
16434 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16435 as_tsktsk (_("Warning: conditional outside an IT block"\
16440 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16441 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16443 /* Automatically generate the IT instruction. */
16444 new_automatic_it_block (inst.cond);
16445 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16446 close_automatic_it_block ();
16450 inst.error = BAD_OUT_IT;
16456 case IF_INSIDE_IT_LAST_INSN:
16457 case NEUTRAL_IT_INSN:
16461 now_it.state = MANUAL_IT_BLOCK;
16462 now_it.block_length = 0;
16467 case AUTOMATIC_IT_BLOCK:
16468 /* Three things may happen now:
16469 a) We should increment current it block size;
16470 b) We should close current it block (closing insn or 4 insns);
16471 c) We should close current it block and start a new one (due
16472 to incompatible conditions or
16473 4 insns-length block reached). */
16475 switch (inst.it_insn_type)
16477 case OUTSIDE_IT_INSN:
16478 /* The closure of the block shall happen immediatelly,
16479 so any in_it_block () call reports the block as closed. */
16480 force_automatic_it_block_close ();
16483 case INSIDE_IT_INSN:
16484 case INSIDE_IT_LAST_INSN:
16485 case IF_INSIDE_IT_LAST_INSN:
16486 now_it.block_length++;
16488 if (now_it.block_length > 4
16489 || !now_it_compatible (inst.cond))
16491 force_automatic_it_block_close ();
16492 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16493 new_automatic_it_block (inst.cond);
16497 now_it.insn_cond = TRUE;
16498 now_it_add_mask (inst.cond);
16501 if (now_it.state == AUTOMATIC_IT_BLOCK
16502 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16503 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16504 close_automatic_it_block ();
16507 case NEUTRAL_IT_INSN:
16508 now_it.block_length++;
16509 now_it.insn_cond = TRUE;
16511 if (now_it.block_length > 4)
16512 force_automatic_it_block_close ();
16514 now_it_add_mask (now_it.cc & 1);
16518 close_automatic_it_block ();
16519 now_it.state = MANUAL_IT_BLOCK;
16524 case MANUAL_IT_BLOCK:
16526 /* Check conditional suffixes. */
16527 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16530 now_it.mask &= 0x1f;
16531 is_last = (now_it.mask == 0x10);
16532 now_it.insn_cond = TRUE;
16534 switch (inst.it_insn_type)
16536 case OUTSIDE_IT_INSN:
16537 inst.error = BAD_NOT_IT;
16540 case INSIDE_IT_INSN:
16541 if (cond != inst.cond)
16543 inst.error = BAD_IT_COND;
16548 case INSIDE_IT_LAST_INSN:
16549 case IF_INSIDE_IT_LAST_INSN:
16550 if (cond != inst.cond)
16552 inst.error = BAD_IT_COND;
16557 inst.error = BAD_BRANCH;
16562 case NEUTRAL_IT_INSN:
16563 /* The BKPT instruction is unconditional even in an IT block. */
16567 inst.error = BAD_IT_IT;
16577 struct depr_insn_mask
16579 unsigned long pattern;
16580 unsigned long mask;
16581 const char* description;
16584 /* List of 16-bit instruction patterns deprecated in an IT block in
16586 static const struct depr_insn_mask depr_it_insns[] = {
16587 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
16588 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
16589 { 0xa000, 0xb800, N_("ADR") },
16590 { 0x4800, 0xf800, N_("Literal loads") },
16591 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
16592 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
16597 it_fsm_post_encode (void)
16601 if (!now_it.state_handled)
16602 handle_it_state ();
16604 if (now_it.insn_cond
16605 && !now_it.warn_deprecated
16606 && warn_on_deprecated
16607 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
16609 if (inst.instruction >= 0x10000)
16611 as_warn (_("it blocks containing wide Thumb instructions are "
16612 "deprecated in ARMv8"));
16613 now_it.warn_deprecated = TRUE;
16617 const struct depr_insn_mask *p = depr_it_insns;
16619 while (p->mask != 0)
16621 if ((inst.instruction & p->mask) == p->pattern)
16623 as_warn (_("it blocks containing 16-bit Thumb intsructions "
16624 "of the following class are deprecated in ARMv8: "
16625 "%s"), p->description);
16626 now_it.warn_deprecated = TRUE;
16634 if (now_it.block_length > 1)
16636 as_warn (_("it blocks of more than one conditional instruction are "
16637 "deprecated in ARMv8"));
16638 now_it.warn_deprecated = TRUE;
16642 is_last = (now_it.mask == 0x10);
16645 now_it.state = OUTSIDE_IT_BLOCK;
16651 force_automatic_it_block_close (void)
16653 if (now_it.state == AUTOMATIC_IT_BLOCK)
16655 close_automatic_it_block ();
16656 now_it.state = OUTSIDE_IT_BLOCK;
16664 if (!now_it.state_handled)
16665 handle_it_state ();
16667 return now_it.state != OUTSIDE_IT_BLOCK;
16671 md_assemble (char *str)
16674 const struct asm_opcode * opcode;
16676 /* Align the previous label if needed. */
16677 if (last_label_seen != NULL)
16679 symbol_set_frag (last_label_seen, frag_now);
16680 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16681 S_SET_SEGMENT (last_label_seen, now_seg);
16684 memset (&inst, '\0', sizeof (inst));
16685 inst.reloc.type = BFD_RELOC_UNUSED;
16687 opcode = opcode_lookup (&p);
16690 /* It wasn't an instruction, but it might be a register alias of
16691 the form alias .req reg, or a Neon .dn/.qn directive. */
16692 if (! create_register_alias (str, p)
16693 && ! create_neon_reg_alias (str, p))
16694 as_bad (_("bad instruction `%s'"), str);
16699 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16700 as_warn (_("s suffix on comparison instruction is deprecated"));
16702 /* The value which unconditional instructions should have in place of the
16703 condition field. */
16704 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16708 arm_feature_set variant;
16710 variant = cpu_variant;
16711 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16712 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16713 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16714 /* Check that this instruction is supported for this CPU. */
16715 if (!opcode->tvariant
16716 || (thumb_mode == 1
16717 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16719 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16722 if (inst.cond != COND_ALWAYS && !unified_syntax
16723 && opcode->tencode != do_t_branch)
16725 as_bad (_("Thumb does not support conditional execution"));
16729 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16731 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16732 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16733 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16735 /* Two things are addressed here.
16736 1) Implicit require narrow instructions on Thumb-1.
16737 This avoids relaxation accidentally introducing Thumb-2
16739 2) Reject wide instructions in non Thumb-2 cores. */
16740 if (inst.size_req == 0)
16742 else if (inst.size_req == 4)
16744 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16750 inst.instruction = opcode->tvalue;
16752 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16754 /* Prepare the it_insn_type for those encodings that don't set
16756 it_fsm_pre_encode ();
16758 opcode->tencode ();
16760 it_fsm_post_encode ();
16763 if (!(inst.error || inst.relax))
16765 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16766 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16767 if (inst.size_req && inst.size_req != inst.size)
16769 as_bad (_("cannot honor width suffix -- `%s'"), str);
16774 /* Something has gone badly wrong if we try to relax a fixed size
16776 gas_assert (inst.size_req == 0 || !inst.relax);
16778 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16779 *opcode->tvariant);
16780 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16781 set those bits when Thumb-2 32-bit instructions are seen. ie.
16782 anything other than bl/blx and v6-M instructions.
16783 This is overly pessimistic for relaxable instructions. */
16784 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16786 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16787 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16788 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16791 check_neon_suffixes;
16795 mapping_state (MAP_THUMB);
16798 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16802 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16803 is_bx = (opcode->aencode == do_bx);
16805 /* Check that this instruction is supported for this CPU. */
16806 if (!(is_bx && fix_v4bx)
16807 && !(opcode->avariant &&
16808 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16810 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16815 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16819 inst.instruction = opcode->avalue;
16820 if (opcode->tag == OT_unconditionalF)
16821 inst.instruction |= 0xF << 28;
16823 inst.instruction |= inst.cond << 28;
16824 inst.size = INSN_SIZE;
16825 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16827 it_fsm_pre_encode ();
16828 opcode->aencode ();
16829 it_fsm_post_encode ();
16831 /* Arm mode bx is marked as both v4T and v5 because it's still required
16832 on a hypothetical non-thumb v5 core. */
16834 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16836 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16837 *opcode->avariant);
16839 check_neon_suffixes;
16843 mapping_state (MAP_ARM);
16848 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16856 check_it_blocks_finished (void)
16861 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16862 if (seg_info (sect)->tc_segment_info_data.current_it.state
16863 == MANUAL_IT_BLOCK)
16865 as_warn (_("section '%s' finished with an open IT block."),
16869 if (now_it.state == MANUAL_IT_BLOCK)
16870 as_warn (_("file finished with an open IT block."));
16874 /* Various frobbings of labels and their addresses. */
16877 arm_start_line_hook (void)
16879 last_label_seen = NULL;
16883 arm_frob_label (symbolS * sym)
16885 last_label_seen = sym;
16887 ARM_SET_THUMB (sym, thumb_mode);
16889 #if defined OBJ_COFF || defined OBJ_ELF
16890 ARM_SET_INTERWORK (sym, support_interwork);
16893 force_automatic_it_block_close ();
16895 /* Note - do not allow local symbols (.Lxxx) to be labelled
16896 as Thumb functions. This is because these labels, whilst
16897 they exist inside Thumb code, are not the entry points for
16898 possible ARM->Thumb calls. Also, these labels can be used
16899 as part of a computed goto or switch statement. eg gcc
16900 can generate code that looks like this:
16902 ldr r2, [pc, .Laaa]
16912 The first instruction loads the address of the jump table.
16913 The second instruction converts a table index into a byte offset.
16914 The third instruction gets the jump address out of the table.
16915 The fourth instruction performs the jump.
16917 If the address stored at .Laaa is that of a symbol which has the
16918 Thumb_Func bit set, then the linker will arrange for this address
16919 to have the bottom bit set, which in turn would mean that the
16920 address computation performed by the third instruction would end
16921 up with the bottom bit set. Since the ARM is capable of unaligned
16922 word loads, the instruction would then load the incorrect address
16923 out of the jump table, and chaos would ensue. */
16924 if (label_is_thumb_function_name
16925 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16926 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16928 /* When the address of a Thumb function is taken the bottom
16929 bit of that address should be set. This will allow
16930 interworking between Arm and Thumb functions to work
16933 THUMB_SET_FUNC (sym, 1);
16935 label_is_thumb_function_name = FALSE;
16938 dwarf2_emit_label (sym);
16942 arm_data_in_code (void)
16944 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16946 *input_line_pointer = '/';
16947 input_line_pointer += 5;
16948 *input_line_pointer = 0;
16956 arm_canonicalize_symbol_name (char * name)
16960 if (thumb_mode && (len = strlen (name)) > 5
16961 && streq (name + len - 5, "/data"))
16962 *(name + len - 5) = 0;
16967 /* Table of all register names defined by default. The user can
16968 define additional names with .req. Note that all register names
16969 should appear in both upper and lowercase variants. Some registers
16970 also have mixed-case names. */
16972 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16973 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16974 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16975 #define REGSET(p,t) \
16976 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16977 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16978 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16979 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16980 #define REGSETH(p,t) \
16981 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16982 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16983 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16984 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16985 #define REGSET2(p,t) \
16986 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16987 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16988 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16989 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16990 #define SPLRBANK(base,bank,t) \
16991 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16992 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16993 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16994 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16995 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16996 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16998 static const struct reg_entry reg_names[] =
17000 /* ARM integer registers. */
17001 REGSET(r, RN), REGSET(R, RN),
17003 /* ATPCS synonyms. */
17004 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17005 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17006 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
17008 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17009 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17010 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
17012 /* Well-known aliases. */
17013 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17014 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17016 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17017 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17019 /* Coprocessor numbers. */
17020 REGSET(p, CP), REGSET(P, CP),
17022 /* Coprocessor register numbers. The "cr" variants are for backward
17024 REGSET(c, CN), REGSET(C, CN),
17025 REGSET(cr, CN), REGSET(CR, CN),
17027 /* ARM banked registers. */
17028 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17029 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17030 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17031 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17032 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17033 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17034 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17036 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17037 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17038 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17039 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17040 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
17041 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
17042 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17043 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17045 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17046 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17047 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17048 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17049 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17050 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17051 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
17052 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
17053 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17055 /* FPA registers. */
17056 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17057 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17059 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17060 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17062 /* VFP SP registers. */
17063 REGSET(s,VFS), REGSET(S,VFS),
17064 REGSETH(s,VFS), REGSETH(S,VFS),
17066 /* VFP DP Registers. */
17067 REGSET(d,VFD), REGSET(D,VFD),
17068 /* Extra Neon DP registers. */
17069 REGSETH(d,VFD), REGSETH(D,VFD),
17071 /* Neon QP registers. */
17072 REGSET2(q,NQ), REGSET2(Q,NQ),
17074 /* VFP control registers. */
17075 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17076 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
17077 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17078 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17079 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17080 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
17082 /* Maverick DSP coprocessor registers. */
17083 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17084 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17086 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17087 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17088 REGDEF(dspsc,0,DSPSC),
17090 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17091 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17092 REGDEF(DSPSC,0,DSPSC),
17094 /* iWMMXt data registers - p0, c0-15. */
17095 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17097 /* iWMMXt control registers - p1, c0-3. */
17098 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17099 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17100 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17101 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17103 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17104 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17105 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17106 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17107 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17109 /* XScale accumulator registers. */
17110 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17116 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17117 within psr_required_here. */
17118 static const struct asm_psr psrs[] =
17120 /* Backward compatibility notation. Note that "all" is no longer
17121 truly all possible PSR bits. */
17122 {"all", PSR_c | PSR_f},
17126 /* Individual flags. */
17132 /* Combinations of flags. */
17133 {"fs", PSR_f | PSR_s},
17134 {"fx", PSR_f | PSR_x},
17135 {"fc", PSR_f | PSR_c},
17136 {"sf", PSR_s | PSR_f},
17137 {"sx", PSR_s | PSR_x},
17138 {"sc", PSR_s | PSR_c},
17139 {"xf", PSR_x | PSR_f},
17140 {"xs", PSR_x | PSR_s},
17141 {"xc", PSR_x | PSR_c},
17142 {"cf", PSR_c | PSR_f},
17143 {"cs", PSR_c | PSR_s},
17144 {"cx", PSR_c | PSR_x},
17145 {"fsx", PSR_f | PSR_s | PSR_x},
17146 {"fsc", PSR_f | PSR_s | PSR_c},
17147 {"fxs", PSR_f | PSR_x | PSR_s},
17148 {"fxc", PSR_f | PSR_x | PSR_c},
17149 {"fcs", PSR_f | PSR_c | PSR_s},
17150 {"fcx", PSR_f | PSR_c | PSR_x},
17151 {"sfx", PSR_s | PSR_f | PSR_x},
17152 {"sfc", PSR_s | PSR_f | PSR_c},
17153 {"sxf", PSR_s | PSR_x | PSR_f},
17154 {"sxc", PSR_s | PSR_x | PSR_c},
17155 {"scf", PSR_s | PSR_c | PSR_f},
17156 {"scx", PSR_s | PSR_c | PSR_x},
17157 {"xfs", PSR_x | PSR_f | PSR_s},
17158 {"xfc", PSR_x | PSR_f | PSR_c},
17159 {"xsf", PSR_x | PSR_s | PSR_f},
17160 {"xsc", PSR_x | PSR_s | PSR_c},
17161 {"xcf", PSR_x | PSR_c | PSR_f},
17162 {"xcs", PSR_x | PSR_c | PSR_s},
17163 {"cfs", PSR_c | PSR_f | PSR_s},
17164 {"cfx", PSR_c | PSR_f | PSR_x},
17165 {"csf", PSR_c | PSR_s | PSR_f},
17166 {"csx", PSR_c | PSR_s | PSR_x},
17167 {"cxf", PSR_c | PSR_x | PSR_f},
17168 {"cxs", PSR_c | PSR_x | PSR_s},
17169 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17170 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17171 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17172 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17173 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17174 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17175 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17176 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17177 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17178 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17179 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17180 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17181 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17182 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17183 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17184 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17185 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17186 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17187 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17188 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17189 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17190 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17191 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17192 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17195 /* Table of V7M psr names. */
17196 static const struct asm_psr v7m_psrs[] =
17198 {"apsr", 0 }, {"APSR", 0 },
17199 {"iapsr", 1 }, {"IAPSR", 1 },
17200 {"eapsr", 2 }, {"EAPSR", 2 },
17201 {"psr", 3 }, {"PSR", 3 },
17202 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17203 {"ipsr", 5 }, {"IPSR", 5 },
17204 {"epsr", 6 }, {"EPSR", 6 },
17205 {"iepsr", 7 }, {"IEPSR", 7 },
17206 {"msp", 8 }, {"MSP", 8 },
17207 {"psp", 9 }, {"PSP", 9 },
17208 {"primask", 16}, {"PRIMASK", 16},
17209 {"basepri", 17}, {"BASEPRI", 17},
17210 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17211 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17212 {"faultmask", 19}, {"FAULTMASK", 19},
17213 {"control", 20}, {"CONTROL", 20}
17216 /* Table of all shift-in-operand names. */
17217 static const struct asm_shift_name shift_names [] =
17219 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17220 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17221 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17222 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17223 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17224 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17227 /* Table of all explicit relocation names. */
17229 static struct reloc_entry reloc_names[] =
17231 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17232 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17233 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17234 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17235 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17236 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17237 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17238 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17239 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17240 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17241 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17242 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17243 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17244 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17245 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17246 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17247 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17248 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17252 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17253 static const struct asm_cond conds[] =
17257 {"cs", 0x2}, {"hs", 0x2},
17258 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17272 #define UL_BARRIER(L,U,CODE,FEAT) \
17273 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17274 { U, CODE, ARM_FEATURE (FEAT, 0) }
17276 static struct asm_barrier_opt barrier_opt_names[] =
17278 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17279 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17280 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17281 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17282 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17283 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17284 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17285 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17286 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17287 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17288 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17289 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17290 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17291 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17292 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17293 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
17298 /* Table of ARM-format instructions. */
17300 /* Macros for gluing together operand strings. N.B. In all cases
17301 other than OPS0, the trailing OP_stop comes from default
17302 zero-initialization of the unspecified elements of the array. */
17303 #define OPS0() { OP_stop, }
17304 #define OPS1(a) { OP_##a, }
17305 #define OPS2(a,b) { OP_##a,OP_##b, }
17306 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17307 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17308 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17309 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17311 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17312 This is useful when mixing operands for ARM and THUMB, i.e. using the
17313 MIX_ARM_THUMB_OPERANDS macro.
17314 In order to use these macros, prefix the number of operands with _
17316 #define OPS_1(a) { a, }
17317 #define OPS_2(a,b) { a,b, }
17318 #define OPS_3(a,b,c) { a,b,c, }
17319 #define OPS_4(a,b,c,d) { a,b,c,d, }
17320 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17321 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17323 /* These macros abstract out the exact format of the mnemonic table and
17324 save some repeated characters. */
17326 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17327 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17328 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17329 THUMB_VARIANT, do_##ae, do_##te }
17331 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17332 a T_MNEM_xyz enumerator. */
17333 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17334 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17335 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17336 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17338 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17339 infix after the third character. */
17340 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17341 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17342 THUMB_VARIANT, do_##ae, do_##te }
17343 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17344 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17345 THUMB_VARIANT, do_##ae, do_##te }
17346 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17347 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17348 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17349 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17350 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17351 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17352 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17353 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17355 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
17356 appear in the condition table. */
17357 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17358 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17359 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17361 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17362 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17363 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17364 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17365 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17366 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17367 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17368 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17369 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17370 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17371 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17372 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17373 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17374 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17375 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17376 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17377 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17378 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17379 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17380 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17382 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17383 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17384 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17385 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17387 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17388 field is still 0xE. Many of the Thumb variants can be executed
17389 conditionally, so this is checked separately. */
17390 #define TUE(mnem, op, top, nops, ops, ae, te) \
17391 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17392 THUMB_VARIANT, do_##ae, do_##te }
17394 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17395 condition code field. */
17396 #define TUF(mnem, op, top, nops, ops, ae, te) \
17397 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17398 THUMB_VARIANT, do_##ae, do_##te }
17400 /* ARM-only variants of all the above. */
17401 #define CE(mnem, op, nops, ops, ae) \
17402 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17404 #define C3(mnem, op, nops, ops, ae) \
17405 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17407 /* Legacy mnemonics that always have conditional infix after the third
17409 #define CL(mnem, op, nops, ops, ae) \
17410 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17411 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17413 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17414 #define cCE(mnem, op, nops, ops, ae) \
17415 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17417 /* Legacy coprocessor instructions where conditional infix and conditional
17418 suffix are ambiguous. For consistency this includes all FPA instructions,
17419 not just the potentially ambiguous ones. */
17420 #define cCL(mnem, op, nops, ops, ae) \
17421 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17422 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17424 /* Coprocessor, takes either a suffix or a position-3 infix
17425 (for an FPA corner case). */
17426 #define C3E(mnem, op, nops, ops, ae) \
17427 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17428 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17430 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17431 { m1 #m2 m3, OPS##nops ops, \
17432 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17433 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17435 #define CM(m1, m2, op, nops, ops, ae) \
17436 xCM_ (m1, , m2, op, nops, ops, ae), \
17437 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17438 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17439 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17440 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17441 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17442 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17443 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17444 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17445 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17446 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17447 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17448 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17449 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17450 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17451 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17452 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17453 xCM_ (m1, le, m2, op, nops, ops, ae), \
17454 xCM_ (m1, al, m2, op, nops, ops, ae)
17456 #define UE(mnem, op, nops, ops, ae) \
17457 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17459 #define UF(mnem, op, nops, ops, ae) \
17460 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17462 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17463 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17464 use the same encoding function for each. */
17465 #define NUF(mnem, op, nops, ops, enc) \
17466 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17467 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17469 /* Neon data processing, version which indirects through neon_enc_tab for
17470 the various overloaded versions of opcodes. */
17471 #define nUF(mnem, op, nops, ops, enc) \
17472 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17473 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17475 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17477 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17478 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17479 THUMB_VARIANT, do_##enc, do_##enc }
17481 #define NCE(mnem, op, nops, ops, enc) \
17482 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17484 #define NCEF(mnem, op, nops, ops, enc) \
17485 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17487 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17488 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17489 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17490 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17492 #define nCE(mnem, op, nops, ops, enc) \
17493 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17495 #define nCEF(mnem, op, nops, ops, enc) \
17496 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17500 static const struct asm_opcode insns[] =
17502 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17503 #define THUMB_VARIANT &arm_ext_v4t
17504 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17505 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17506 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17507 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17508 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17509 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17510 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17511 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17512 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17513 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17514 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17515 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17516 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17517 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17518 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17519 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17521 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17522 for setting PSR flag bits. They are obsolete in V6 and do not
17523 have Thumb equivalents. */
17524 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17525 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17526 CL("tstp", 110f000, 2, (RR, SH), cmp),
17527 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17528 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17529 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17530 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17531 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17532 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17534 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17535 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17536 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17537 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17539 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17540 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17541 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17543 OP_ADDRGLDR),ldst, t_ldst),
17544 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17546 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17547 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17548 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17549 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17550 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17551 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17553 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17554 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17555 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17556 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17559 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17560 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17561 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17563 /* Thumb-compatibility pseudo ops. */
17564 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17565 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17566 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17567 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17568 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17569 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17570 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17571 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17572 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17573 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17574 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17575 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17577 /* These may simplify to neg. */
17578 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17579 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17581 #undef THUMB_VARIANT
17582 #define THUMB_VARIANT & arm_ext_v6
17584 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17586 /* V1 instructions with no Thumb analogue prior to V6T2. */
17587 #undef THUMB_VARIANT
17588 #define THUMB_VARIANT & arm_ext_v6t2
17590 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17591 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17592 CL("teqp", 130f000, 2, (RR, SH), cmp),
17594 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17595 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17596 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17597 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17599 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17600 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17602 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17603 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17605 /* V1 instructions with no Thumb analogue at all. */
17606 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17607 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17609 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17610 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17611 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17612 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17613 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17614 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17615 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17616 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17619 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17620 #undef THUMB_VARIANT
17621 #define THUMB_VARIANT & arm_ext_v4t
17623 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17624 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17626 #undef THUMB_VARIANT
17627 #define THUMB_VARIANT & arm_ext_v6t2
17629 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17630 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17632 /* Generic coprocessor instructions. */
17633 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17634 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17635 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17636 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17637 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17638 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17639 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17642 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17644 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17645 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17648 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17649 #undef THUMB_VARIANT
17650 #define THUMB_VARIANT & arm_ext_msr
17652 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17653 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17656 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17657 #undef THUMB_VARIANT
17658 #define THUMB_VARIANT & arm_ext_v6t2
17660 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17661 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17662 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17663 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17664 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17665 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17666 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17667 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17670 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17671 #undef THUMB_VARIANT
17672 #define THUMB_VARIANT & arm_ext_v4t
17674 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17675 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17676 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17677 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17678 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17679 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17682 #define ARM_VARIANT & arm_ext_v4t_5
17684 /* ARM Architecture 4T. */
17685 /* Note: bx (and blx) are required on V5, even if the processor does
17686 not support Thumb. */
17687 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17690 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17691 #undef THUMB_VARIANT
17692 #define THUMB_VARIANT & arm_ext_v5t
17694 /* Note: blx has 2 variants; the .value coded here is for
17695 BLX(2). Only this variant has conditional execution. */
17696 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17697 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17699 #undef THUMB_VARIANT
17700 #define THUMB_VARIANT & arm_ext_v6t2
17702 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17703 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17704 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17705 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17706 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17707 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17708 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17709 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17712 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17713 #undef THUMB_VARIANT
17714 #define THUMB_VARIANT &arm_ext_v5exp
17716 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17717 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17718 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17719 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17721 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17722 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17724 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17725 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17726 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17727 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17729 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17730 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17731 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17732 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17734 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17735 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17737 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17738 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17739 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17740 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17743 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17744 #undef THUMB_VARIANT
17745 #define THUMB_VARIANT &arm_ext_v6t2
17747 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17748 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17750 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17751 ADDRGLDRS), ldrd, t_ldstd),
17753 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17754 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17757 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17759 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17762 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17763 #undef THUMB_VARIANT
17764 #define THUMB_VARIANT & arm_ext_v6
17766 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17767 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17768 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17769 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17770 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17771 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17772 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17773 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17774 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17775 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17777 #undef THUMB_VARIANT
17778 #define THUMB_VARIANT & arm_ext_v6t2
17780 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17781 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17783 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17784 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17786 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17787 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17789 /* ARM V6 not included in V7M. */
17790 #undef THUMB_VARIANT
17791 #define THUMB_VARIANT & arm_ext_v6_notm
17792 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17793 UF(rfeib, 9900a00, 1, (RRw), rfe),
17794 UF(rfeda, 8100a00, 1, (RRw), rfe),
17795 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17796 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17797 UF(rfefa, 9900a00, 1, (RRw), rfe),
17798 UF(rfeea, 8100a00, 1, (RRw), rfe),
17799 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17800 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17801 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17802 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17803 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17805 /* ARM V6 not included in V7M (eg. integer SIMD). */
17806 #undef THUMB_VARIANT
17807 #define THUMB_VARIANT & arm_ext_v6_dsp
17808 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17809 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17810 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17811 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17812 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17813 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17814 /* Old name for QASX. */
17815 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17816 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17817 /* Old name for QSAX. */
17818 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17819 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17820 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17821 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17822 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17823 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17824 /* Old name for SASX. */
17825 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17826 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17827 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17828 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17829 /* Old name for SHASX. */
17830 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17831 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17832 /* Old name for SHSAX. */
17833 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17834 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17835 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17836 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17837 /* Old name for SSAX. */
17838 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17839 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17840 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17841 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17842 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17843 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17844 /* Old name for UASX. */
17845 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17846 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17847 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17848 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17849 /* Old name for UHASX. */
17850 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17851 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17852 /* Old name for UHSAX. */
17853 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17854 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17855 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17856 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17857 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17858 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17859 /* Old name for UQASX. */
17860 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17861 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17862 /* Old name for UQSAX. */
17863 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17864 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17865 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17866 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17867 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17868 /* Old name for USAX. */
17869 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17870 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17871 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17872 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17873 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17874 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17875 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17876 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17877 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17878 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17879 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17880 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17881 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17882 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17883 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17884 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17885 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17886 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17887 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17888 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17889 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17890 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17891 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17892 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17893 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17894 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17895 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17896 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17897 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17898 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17899 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17900 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17901 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17902 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17905 #define ARM_VARIANT & arm_ext_v6k
17906 #undef THUMB_VARIANT
17907 #define THUMB_VARIANT & arm_ext_v6k
17909 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17910 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17911 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17912 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17914 #undef THUMB_VARIANT
17915 #define THUMB_VARIANT & arm_ext_v6_notm
17916 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17918 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17919 RRnpcb), strexd, t_strexd),
17921 #undef THUMB_VARIANT
17922 #define THUMB_VARIANT & arm_ext_v6t2
17923 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17925 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17927 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17929 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17931 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17934 #define ARM_VARIANT & arm_ext_sec
17935 #undef THUMB_VARIANT
17936 #define THUMB_VARIANT & arm_ext_sec
17938 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17941 #define ARM_VARIANT & arm_ext_virt
17942 #undef THUMB_VARIANT
17943 #define THUMB_VARIANT & arm_ext_virt
17945 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17946 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17949 #define ARM_VARIANT & arm_ext_v6t2
17950 #undef THUMB_VARIANT
17951 #define THUMB_VARIANT & arm_ext_v6t2
17953 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17954 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17955 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17956 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17958 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17959 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17960 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17961 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17963 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17964 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17965 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17966 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17968 /* Thumb-only instructions. */
17970 #define ARM_VARIANT NULL
17971 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17972 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17974 /* ARM does not really have an IT instruction, so always allow it.
17975 The opcode is copied from Thumb in order to allow warnings in
17976 -mimplicit-it=[never | arm] modes. */
17978 #define ARM_VARIANT & arm_ext_v1
17980 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17981 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17982 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17983 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17984 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17985 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17986 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17987 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17988 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17989 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17990 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17991 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17992 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17993 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17994 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17995 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17996 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17997 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17999 /* Thumb2 only instructions. */
18001 #define ARM_VARIANT NULL
18003 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18004 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18005 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18006 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18007 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18008 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
18010 /* Hardware division instructions. */
18012 #define ARM_VARIANT & arm_ext_adiv
18013 #undef THUMB_VARIANT
18014 #define THUMB_VARIANT & arm_ext_div
18016 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18017 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
18019 /* ARM V6M/V7 instructions. */
18021 #define ARM_VARIANT & arm_ext_barrier
18022 #undef THUMB_VARIANT
18023 #define THUMB_VARIANT & arm_ext_barrier
18025 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
18026 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
18027 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
18029 /* ARM V7 instructions. */
18031 #define ARM_VARIANT & arm_ext_v7
18032 #undef THUMB_VARIANT
18033 #define THUMB_VARIANT & arm_ext_v7
18035 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18036 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
18039 #define ARM_VARIANT & arm_ext_mp
18040 #undef THUMB_VARIANT
18041 #define THUMB_VARIANT & arm_ext_mp
18043 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18045 /* AArchv8 instructions. */
18047 #define ARM_VARIANT & arm_ext_v8
18048 #undef THUMB_VARIANT
18049 #define THUMB_VARIANT & arm_ext_v8
18051 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
18052 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
18053 TCE("ldraex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18054 TCE("ldraexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
18056 TCE("ldraexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18057 TCE("ldraexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18058 TCE("strlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18060 TCE("strlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
18062 TCE("strlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18064 TCE("strlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18066 TCE("ldra", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18067 TCE("ldrab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18068 TCE("ldrah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18069 TCE("strl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18070 TCE("strlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18071 TCE("strlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18073 /* ARMv8 T32 only. */
18075 #define ARM_VARIANT NULL
18076 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18077 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18078 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18080 /* FP for ARMv8. */
18082 #define ARM_VARIANT & fpu_vfp_ext_armv8
18083 #undef THUMB_VARIANT
18084 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18086 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18087 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18088 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18089 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
18092 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18093 #undef THUMB_VARIANT
18094 #define THUMB_VARIANT NULL
18096 cCE("wfs", e200110, 1, (RR), rd),
18097 cCE("rfs", e300110, 1, (RR), rd),
18098 cCE("wfc", e400110, 1, (RR), rd),
18099 cCE("rfc", e500110, 1, (RR), rd),
18101 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18102 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18103 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18104 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18106 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18107 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18108 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18109 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18111 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18112 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18113 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18114 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18115 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18116 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18117 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18118 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18119 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18120 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18121 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18122 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18124 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18125 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18126 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18127 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18128 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18129 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18130 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18131 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18132 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18133 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18134 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18135 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18137 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18138 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18139 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18140 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18141 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18142 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18143 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18144 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18145 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18146 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18147 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18148 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18150 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18151 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18152 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18153 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18154 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18155 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18156 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18157 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18158 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18159 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18160 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18161 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18163 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18164 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18165 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18166 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18167 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18168 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18169 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18170 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18171 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18172 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18173 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18174 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18176 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18177 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18178 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18179 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18180 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18181 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18182 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18183 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18184 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18185 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18186 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18187 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18189 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18190 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18191 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18192 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18193 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18194 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18195 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18196 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18197 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18198 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18199 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18200 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18202 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18203 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18204 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18205 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18206 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18207 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18208 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18209 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18210 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18211 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18212 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18213 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18215 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18216 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18217 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18218 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18219 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18220 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18221 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18222 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18223 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18224 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18225 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18226 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18228 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18229 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18230 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18231 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18232 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18233 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18234 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18235 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18236 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18237 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18238 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18239 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18241 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18242 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18243 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18244 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18245 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18246 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18247 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18248 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18249 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18250 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18251 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18252 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18254 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18255 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18256 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18257 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18258 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18259 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18260 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18261 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18262 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18263 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18264 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18265 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18267 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18268 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18269 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18270 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18271 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18272 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18273 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18274 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18275 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18276 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18277 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18278 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18280 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18281 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18282 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18283 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18284 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18285 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18286 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18287 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18288 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18289 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18290 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18291 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18293 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18294 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18295 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18296 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18297 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18298 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18299 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18300 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18301 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18302 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18303 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18304 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18306 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18307 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18308 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18309 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18310 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18311 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18312 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18313 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18314 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18315 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18316 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18317 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18319 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18320 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18321 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18322 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18323 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18324 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18325 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18326 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18327 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18328 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18329 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18330 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18332 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18333 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18334 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18335 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18336 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18337 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18338 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18339 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18340 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18341 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18342 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18343 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18345 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18346 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18347 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18348 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18349 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18350 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18351 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18352 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18353 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18354 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18355 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18356 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18358 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18359 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18360 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18361 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18362 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18363 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18364 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18365 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18366 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18367 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18368 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18369 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18371 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18372 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18373 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18374 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18375 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18376 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18377 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18378 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18379 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18380 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18381 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18382 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18384 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18385 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18386 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18387 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18388 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18389 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18390 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18391 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18392 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18393 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18394 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18395 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18397 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18398 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18399 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18400 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18401 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18402 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18403 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18404 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18405 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18406 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18407 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18408 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18410 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18411 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18412 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18413 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18414 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18415 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18416 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18417 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18418 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18419 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18420 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18421 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18423 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18424 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18425 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18426 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18427 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18428 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18429 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18430 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18431 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18432 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18433 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18434 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18436 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18437 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18438 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18439 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18440 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18441 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18442 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18443 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18444 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18445 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18446 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18447 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18449 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18450 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18451 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18452 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18453 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18454 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18455 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18456 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18457 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18458 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18459 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18460 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18462 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18463 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18464 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18465 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18466 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18467 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18468 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18469 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18470 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18471 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18472 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18473 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18475 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18476 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18477 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18478 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18479 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18480 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18481 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18482 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18483 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18484 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18485 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18486 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18488 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18489 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18490 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18491 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18493 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18494 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18495 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18496 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18497 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18498 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18499 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18500 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18501 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18502 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18503 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18504 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18506 /* The implementation of the FIX instruction is broken on some
18507 assemblers, in that it accepts a precision specifier as well as a
18508 rounding specifier, despite the fact that this is meaningless.
18509 To be more compatible, we accept it as well, though of course it
18510 does not set any bits. */
18511 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18512 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18513 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18514 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18515 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18516 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18517 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18518 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18519 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18520 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18521 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18522 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18523 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18525 /* Instructions that were new with the real FPA, call them V2. */
18527 #define ARM_VARIANT & fpu_fpa_ext_v2
18529 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18530 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18531 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18532 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18533 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18534 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18537 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18539 /* Moves and type conversions. */
18540 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18541 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18542 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18543 cCE("fmstat", ef1fa10, 0, (), noargs),
18544 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
18545 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
18546 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18547 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18548 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18549 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18550 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18551 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18552 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18553 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18555 /* Memory operations. */
18556 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18557 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18558 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18559 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18560 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18561 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18562 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18563 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18564 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18565 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18566 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18567 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18568 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18569 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18570 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18571 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18572 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18573 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18575 /* Monadic operations. */
18576 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18577 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18578 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18580 /* Dyadic operations. */
18581 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18582 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18583 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18584 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18585 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18586 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18587 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18588 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18589 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18592 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18593 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18594 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18595 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18597 /* Double precision load/store are still present on single precision
18598 implementations. */
18599 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18600 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18601 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18602 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18603 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18604 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18605 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18606 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18607 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18608 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18611 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18613 /* Moves and type conversions. */
18614 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18615 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18616 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18617 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18618 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18619 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18620 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18621 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18622 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18623 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18624 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18625 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18626 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18628 /* Monadic operations. */
18629 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18630 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18631 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18633 /* Dyadic operations. */
18634 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18635 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18636 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18637 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18638 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18639 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18640 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18641 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18642 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18645 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18646 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18647 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18648 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18651 #define ARM_VARIANT & fpu_vfp_ext_v2
18653 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18654 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18655 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18656 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18658 /* Instructions which may belong to either the Neon or VFP instruction sets.
18659 Individual encoder functions perform additional architecture checks. */
18661 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18662 #undef THUMB_VARIANT
18663 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18665 /* These mnemonics are unique to VFP. */
18666 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18667 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18668 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18669 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18670 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18671 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18672 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18673 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18674 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18675 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18677 /* Mnemonics shared by Neon and VFP. */
18678 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18679 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18680 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18682 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18683 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18685 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18686 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18688 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18689 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18690 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18691 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18692 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18693 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18694 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18695 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18697 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18698 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18699 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18700 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18703 /* NOTE: All VMOV encoding is special-cased! */
18704 NCE(vmov, 0, 1, (VMOV), neon_mov),
18705 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18707 #undef THUMB_VARIANT
18708 #define THUMB_VARIANT & fpu_neon_ext_v1
18710 #define ARM_VARIANT & fpu_neon_ext_v1
18712 /* Data processing with three registers of the same length. */
18713 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18714 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18715 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18716 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18717 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18718 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18719 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18720 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18721 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18722 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18723 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18724 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18725 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18726 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18727 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18728 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18729 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18730 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18731 /* If not immediate, fall back to neon_dyadic_i64_su.
18732 shl_imm should accept I8 I16 I32 I64,
18733 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18734 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18735 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18736 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18737 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18738 /* Logic ops, types optional & ignored. */
18739 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18740 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18741 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18742 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18743 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18744 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18745 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18746 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18747 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18748 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18749 /* Bitfield ops, untyped. */
18750 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18751 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18752 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18753 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18754 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18755 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18756 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18757 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18758 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18759 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18760 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18761 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18762 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18763 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18764 back to neon_dyadic_if_su. */
18765 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18766 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18767 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18768 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18769 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18770 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18771 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18772 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18773 /* Comparison. Type I8 I16 I32 F32. */
18774 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18775 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18776 /* As above, D registers only. */
18777 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18778 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18779 /* Int and float variants, signedness unimportant. */
18780 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18781 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18782 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18783 /* Add/sub take types I8 I16 I32 I64 F32. */
18784 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18785 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18786 /* vtst takes sizes 8, 16, 32. */
18787 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18788 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18789 /* VMUL takes I8 I16 I32 F32 P8. */
18790 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18791 /* VQD{R}MULH takes S16 S32. */
18792 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18793 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18794 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18795 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18796 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18797 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18798 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18799 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18800 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18801 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18802 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18803 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18804 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18805 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18806 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18807 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18809 /* Two address, int/float. Types S8 S16 S32 F32. */
18810 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18811 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18813 /* Data processing with two registers and a shift amount. */
18814 /* Right shifts, and variants with rounding.
18815 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18816 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18817 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18818 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18819 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18820 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18821 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18822 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18823 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18824 /* Shift and insert. Sizes accepted 8 16 32 64. */
18825 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18826 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18827 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18828 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18829 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18830 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18831 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18832 /* Right shift immediate, saturating & narrowing, with rounding variants.
18833 Types accepted S16 S32 S64 U16 U32 U64. */
18834 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18835 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18836 /* As above, unsigned. Types accepted S16 S32 S64. */
18837 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18838 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18839 /* Right shift narrowing. Types accepted I16 I32 I64. */
18840 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18841 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18842 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18843 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18844 /* CVT with optional immediate for fixed-point variant. */
18845 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18847 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18848 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18850 /* Data processing, three registers of different lengths. */
18851 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18852 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18853 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18854 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18855 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18856 /* If not scalar, fall back to neon_dyadic_long.
18857 Vector types as above, scalar types S16 S32 U16 U32. */
18858 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18859 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18860 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18861 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18862 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18863 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18864 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18865 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18866 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18867 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18868 /* Saturating doubling multiplies. Types S16 S32. */
18869 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18870 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18871 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18872 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18873 S16 S32 U16 U32. */
18874 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18876 /* Extract. Size 8. */
18877 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18878 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18880 /* Two registers, miscellaneous. */
18881 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18882 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18883 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18884 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18885 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18886 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18887 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18888 /* Vector replicate. Sizes 8 16 32. */
18889 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18890 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18891 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18892 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18893 /* VMOVN. Types I16 I32 I64. */
18894 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18895 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18896 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18897 /* VQMOVUN. Types S16 S32 S64. */
18898 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18899 /* VZIP / VUZP. Sizes 8 16 32. */
18900 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18901 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18902 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18903 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18904 /* VQABS / VQNEG. Types S8 S16 S32. */
18905 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18906 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18907 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18908 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18909 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18910 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18911 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18912 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18913 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18914 /* Reciprocal estimates. Types U32 F32. */
18915 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18916 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18917 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18918 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18919 /* VCLS. Types S8 S16 S32. */
18920 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18921 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18922 /* VCLZ. Types I8 I16 I32. */
18923 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18924 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18925 /* VCNT. Size 8. */
18926 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18927 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18928 /* Two address, untyped. */
18929 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18930 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18931 /* VTRN. Sizes 8 16 32. */
18932 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18933 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18935 /* Table lookup. Size 8. */
18936 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18937 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18939 #undef THUMB_VARIANT
18940 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18942 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18944 /* Neon element/structure load/store. */
18945 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18946 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18947 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18948 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18949 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18950 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18951 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18952 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18954 #undef THUMB_VARIANT
18955 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18957 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18958 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18959 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18960 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18961 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18962 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18963 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18964 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18965 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18966 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18968 #undef THUMB_VARIANT
18969 #define THUMB_VARIANT & fpu_vfp_ext_v3
18971 #define ARM_VARIANT & fpu_vfp_ext_v3
18973 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18974 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18975 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18976 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18977 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18978 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18979 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18980 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18981 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18984 #define ARM_VARIANT &fpu_vfp_ext_fma
18985 #undef THUMB_VARIANT
18986 #define THUMB_VARIANT &fpu_vfp_ext_fma
18987 /* Mnemonics shared by Neon and VFP. These are included in the
18988 VFP FMA variant; NEON and VFP FMA always includes the NEON
18989 FMA instructions. */
18990 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18991 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18992 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18993 the v form should always be used. */
18994 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18995 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18996 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18997 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18998 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18999 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19001 #undef THUMB_VARIANT
19003 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19005 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19006 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19007 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19008 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19009 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19010 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19011 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19012 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
19015 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19017 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19018 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19019 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19020 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19021 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19022 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19023 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19024 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19025 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19026 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19027 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19028 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19029 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19030 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19031 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19032 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19033 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19034 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19035 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19036 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19037 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19038 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19039 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19040 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19041 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19042 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19043 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
19044 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
19045 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
19046 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19047 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19048 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19049 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19050 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19051 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19052 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19053 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19054 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19055 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19056 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19057 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19058 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19059 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19060 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19061 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19062 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19063 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19064 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19065 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19066 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19067 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19068 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19069 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19070 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19071 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19072 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19073 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19074 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19075 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19076 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19077 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19078 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19079 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19080 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19081 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19082 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19083 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19084 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19085 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19086 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19087 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19088 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19089 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19090 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19091 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19092 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19093 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19094 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19095 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19096 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19097 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19098 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19099 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19100 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19101 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19102 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19103 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19104 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19105 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19106 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19107 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19108 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19109 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19110 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19111 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19112 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19113 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19114 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19115 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19116 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19117 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19118 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19119 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19120 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19121 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19122 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19123 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19124 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19125 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19126 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19127 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19128 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19129 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19130 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19131 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19132 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19133 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19134 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19135 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19136 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19137 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19138 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19139 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19140 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19141 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19142 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19143 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19144 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19145 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19146 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19147 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19148 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19149 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19150 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19151 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19152 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19153 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19154 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19155 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19156 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19157 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19158 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19159 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19160 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19161 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19162 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19163 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19164 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19165 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19166 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19167 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19168 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19169 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19170 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19171 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19172 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19173 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19174 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19175 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19176 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19177 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19178 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
19181 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19183 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19184 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19185 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19186 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19187 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19188 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19189 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19190 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19191 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19192 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19193 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19194 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19195 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19196 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19197 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19198 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19199 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19200 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19201 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19202 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19203 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19204 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19205 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19206 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19207 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19208 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19209 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19210 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19211 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19212 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19213 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19214 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19215 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19216 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19217 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19218 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19219 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19220 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19221 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19222 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19223 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19224 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19225 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19226 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19227 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19228 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19229 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19230 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19231 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19232 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19233 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19234 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19235 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19236 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19237 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19238 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19239 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19242 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19244 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19245 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19246 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19247 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19248 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19249 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19250 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19251 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19252 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19253 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19254 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19255 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19256 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19257 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19258 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
19259 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
19260 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
19261 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
19262 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
19263 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
19264 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
19265 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
19266 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
19267 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
19268 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19269 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19270 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19271 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19272 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19273 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
19274 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19275 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19276 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19277 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19278 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
19279 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
19280 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
19281 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
19282 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
19283 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
19284 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19285 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19286 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
19287 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
19288 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19289 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19290 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19291 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19292 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19293 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19294 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19295 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19296 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19297 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19298 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19299 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19300 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19301 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19302 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19303 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19304 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19305 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19306 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19307 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19308 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19309 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19310 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19311 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19312 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19313 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19314 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19315 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19316 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19317 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19318 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19319 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19322 #undef THUMB_VARIANT
19349 /* MD interface: bits in the object file. */
19351 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19352 for use in the a.out file, and stores them in the array pointed to by buf.
19353 This knows about the endian-ness of the target machine and does
19354 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19355 2 (short) and 4 (long) Floating numbers are put out as a series of
19356 LITTLENUMS (shorts, here at least). */
19359 md_number_to_chars (char * buf, valueT val, int n)
19361 if (target_big_endian)
19362 number_to_chars_bigendian (buf, val, n);
19364 number_to_chars_littleendian (buf, val, n);
19368 md_chars_to_number (char * buf, int n)
19371 unsigned char * where = (unsigned char *) buf;
19373 if (target_big_endian)
19378 result |= (*where++ & 255);
19386 result |= (where[n] & 255);
19393 /* MD interface: Sections. */
19395 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19396 that an rs_machine_dependent frag may reach. */
19399 arm_frag_max_var (fragS *fragp)
19401 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19402 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19404 Note that we generate relaxable instructions even for cases that don't
19405 really need it, like an immediate that's a trivial constant. So we're
19406 overestimating the instruction size for some of those cases. Rather
19407 than putting more intelligence here, it would probably be better to
19408 avoid generating a relaxation frag in the first place when it can be
19409 determined up front that a short instruction will suffice. */
19411 gas_assert (fragp->fr_type == rs_machine_dependent);
19415 /* Estimate the size of a frag before relaxing. Assume everything fits in
19419 md_estimate_size_before_relax (fragS * fragp,
19420 segT segtype ATTRIBUTE_UNUSED)
19426 /* Convert a machine dependent frag. */
19429 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19431 unsigned long insn;
19432 unsigned long old_op;
19440 buf = fragp->fr_literal + fragp->fr_fix;
19442 old_op = bfd_get_16(abfd, buf);
19443 if (fragp->fr_symbol)
19445 exp.X_op = O_symbol;
19446 exp.X_add_symbol = fragp->fr_symbol;
19450 exp.X_op = O_constant;
19452 exp.X_add_number = fragp->fr_offset;
19453 opcode = fragp->fr_subtype;
19456 case T_MNEM_ldr_pc:
19457 case T_MNEM_ldr_pc2:
19458 case T_MNEM_ldr_sp:
19459 case T_MNEM_str_sp:
19466 if (fragp->fr_var == 4)
19468 insn = THUMB_OP32 (opcode);
19469 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19471 insn |= (old_op & 0x700) << 4;
19475 insn |= (old_op & 7) << 12;
19476 insn |= (old_op & 0x38) << 13;
19478 insn |= 0x00000c00;
19479 put_thumb32_insn (buf, insn);
19480 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19484 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19486 pc_rel = (opcode == T_MNEM_ldr_pc2);
19489 if (fragp->fr_var == 4)
19491 insn = THUMB_OP32 (opcode);
19492 insn |= (old_op & 0xf0) << 4;
19493 put_thumb32_insn (buf, insn);
19494 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19498 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19499 exp.X_add_number -= 4;
19507 if (fragp->fr_var == 4)
19509 int r0off = (opcode == T_MNEM_mov
19510 || opcode == T_MNEM_movs) ? 0 : 8;
19511 insn = THUMB_OP32 (opcode);
19512 insn = (insn & 0xe1ffffff) | 0x10000000;
19513 insn |= (old_op & 0x700) << r0off;
19514 put_thumb32_insn (buf, insn);
19515 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19519 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19524 if (fragp->fr_var == 4)
19526 insn = THUMB_OP32(opcode);
19527 put_thumb32_insn (buf, insn);
19528 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19531 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19535 if (fragp->fr_var == 4)
19537 insn = THUMB_OP32(opcode);
19538 insn |= (old_op & 0xf00) << 14;
19539 put_thumb32_insn (buf, insn);
19540 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19543 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19546 case T_MNEM_add_sp:
19547 case T_MNEM_add_pc:
19548 case T_MNEM_inc_sp:
19549 case T_MNEM_dec_sp:
19550 if (fragp->fr_var == 4)
19552 /* ??? Choose between add and addw. */
19553 insn = THUMB_OP32 (opcode);
19554 insn |= (old_op & 0xf0) << 4;
19555 put_thumb32_insn (buf, insn);
19556 if (opcode == T_MNEM_add_pc)
19557 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19559 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19562 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19570 if (fragp->fr_var == 4)
19572 insn = THUMB_OP32 (opcode);
19573 insn |= (old_op & 0xf0) << 4;
19574 insn |= (old_op & 0xf) << 16;
19575 put_thumb32_insn (buf, insn);
19576 if (insn & (1 << 20))
19577 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19579 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19582 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19588 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19589 (enum bfd_reloc_code_real) reloc_type);
19590 fixp->fx_file = fragp->fr_file;
19591 fixp->fx_line = fragp->fr_line;
19592 fragp->fr_fix += fragp->fr_var;
19595 /* Return the size of a relaxable immediate operand instruction.
19596 SHIFT and SIZE specify the form of the allowable immediate. */
19598 relax_immediate (fragS *fragp, int size, int shift)
19604 /* ??? Should be able to do better than this. */
19605 if (fragp->fr_symbol)
19608 low = (1 << shift) - 1;
19609 mask = (1 << (shift + size)) - (1 << shift);
19610 offset = fragp->fr_offset;
19611 /* Force misaligned offsets to 32-bit variant. */
19614 if (offset & ~mask)
19619 /* Get the address of a symbol during relaxation. */
19621 relaxed_symbol_addr (fragS *fragp, long stretch)
19627 sym = fragp->fr_symbol;
19628 sym_frag = symbol_get_frag (sym);
19629 know (S_GET_SEGMENT (sym) != absolute_section
19630 || sym_frag == &zero_address_frag);
19631 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19633 /* If frag has yet to be reached on this pass, assume it will
19634 move by STRETCH just as we did. If this is not so, it will
19635 be because some frag between grows, and that will force
19639 && sym_frag->relax_marker != fragp->relax_marker)
19643 /* Adjust stretch for any alignment frag. Note that if have
19644 been expanding the earlier code, the symbol may be
19645 defined in what appears to be an earlier frag. FIXME:
19646 This doesn't handle the fr_subtype field, which specifies
19647 a maximum number of bytes to skip when doing an
19649 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19651 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19654 stretch = - ((- stretch)
19655 & ~ ((1 << (int) f->fr_offset) - 1));
19657 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19669 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19672 relax_adr (fragS *fragp, asection *sec, long stretch)
19677 /* Assume worst case for symbols not known to be in the same section. */
19678 if (fragp->fr_symbol == NULL
19679 || !S_IS_DEFINED (fragp->fr_symbol)
19680 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19681 || S_IS_WEAK (fragp->fr_symbol))
19684 val = relaxed_symbol_addr (fragp, stretch);
19685 addr = fragp->fr_address + fragp->fr_fix;
19686 addr = (addr + 4) & ~3;
19687 /* Force misaligned targets to 32-bit variant. */
19691 if (val < 0 || val > 1020)
19696 /* Return the size of a relaxable add/sub immediate instruction. */
19698 relax_addsub (fragS *fragp, asection *sec)
19703 buf = fragp->fr_literal + fragp->fr_fix;
19704 op = bfd_get_16(sec->owner, buf);
19705 if ((op & 0xf) == ((op >> 4) & 0xf))
19706 return relax_immediate (fragp, 8, 0);
19708 return relax_immediate (fragp, 3, 0);
19712 /* Return the size of a relaxable branch instruction. BITS is the
19713 size of the offset field in the narrow instruction. */
19716 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19722 /* Assume worst case for symbols not known to be in the same section. */
19723 if (!S_IS_DEFINED (fragp->fr_symbol)
19724 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19725 || S_IS_WEAK (fragp->fr_symbol))
19729 if (S_IS_DEFINED (fragp->fr_symbol)
19730 && ARM_IS_FUNC (fragp->fr_symbol))
19733 /* PR 12532. Global symbols with default visibility might
19734 be preempted, so do not relax relocations to them. */
19735 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19736 && (! S_IS_LOCAL (fragp->fr_symbol)))
19740 val = relaxed_symbol_addr (fragp, stretch);
19741 addr = fragp->fr_address + fragp->fr_fix + 4;
19744 /* Offset is a signed value *2 */
19746 if (val >= limit || val < -limit)
19752 /* Relax a machine dependent frag. This returns the amount by which
19753 the current size of the frag should change. */
19756 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19761 oldsize = fragp->fr_var;
19762 switch (fragp->fr_subtype)
19764 case T_MNEM_ldr_pc2:
19765 newsize = relax_adr (fragp, sec, stretch);
19767 case T_MNEM_ldr_pc:
19768 case T_MNEM_ldr_sp:
19769 case T_MNEM_str_sp:
19770 newsize = relax_immediate (fragp, 8, 2);
19774 newsize = relax_immediate (fragp, 5, 2);
19778 newsize = relax_immediate (fragp, 5, 1);
19782 newsize = relax_immediate (fragp, 5, 0);
19785 newsize = relax_adr (fragp, sec, stretch);
19791 newsize = relax_immediate (fragp, 8, 0);
19794 newsize = relax_branch (fragp, sec, 11, stretch);
19797 newsize = relax_branch (fragp, sec, 8, stretch);
19799 case T_MNEM_add_sp:
19800 case T_MNEM_add_pc:
19801 newsize = relax_immediate (fragp, 8, 2);
19803 case T_MNEM_inc_sp:
19804 case T_MNEM_dec_sp:
19805 newsize = relax_immediate (fragp, 7, 2);
19811 newsize = relax_addsub (fragp, sec);
19817 fragp->fr_var = newsize;
19818 /* Freeze wide instructions that are at or before the same location as
19819 in the previous pass. This avoids infinite loops.
19820 Don't freeze them unconditionally because targets may be artificially
19821 misaligned by the expansion of preceding frags. */
19822 if (stretch <= 0 && newsize > 2)
19824 md_convert_frag (sec->owner, sec, fragp);
19828 return newsize - oldsize;
19831 /* Round up a section size to the appropriate boundary. */
19834 md_section_align (segT segment ATTRIBUTE_UNUSED,
19837 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19838 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19840 /* For a.out, force the section size to be aligned. If we don't do
19841 this, BFD will align it for us, but it will not write out the
19842 final bytes of the section. This may be a bug in BFD, but it is
19843 easier to fix it here since that is how the other a.out targets
19847 align = bfd_get_section_alignment (stdoutput, segment);
19848 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19855 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19856 of an rs_align_code fragment. */
19859 arm_handle_align (fragS * fragP)
19861 static char const arm_noop[2][2][4] =
19864 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19865 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19868 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19869 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19872 static char const thumb_noop[2][2][2] =
19875 {0xc0, 0x46}, /* LE */
19876 {0x46, 0xc0}, /* BE */
19879 {0x00, 0xbf}, /* LE */
19880 {0xbf, 0x00} /* BE */
19883 static char const wide_thumb_noop[2][4] =
19884 { /* Wide Thumb-2 */
19885 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19886 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19889 unsigned bytes, fix, noop_size;
19892 const char *narrow_noop = NULL;
19897 if (fragP->fr_type != rs_align_code)
19900 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19901 p = fragP->fr_literal + fragP->fr_fix;
19904 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19905 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19907 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19909 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19911 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19913 narrow_noop = thumb_noop[1][target_big_endian];
19914 noop = wide_thumb_noop[target_big_endian];
19917 noop = thumb_noop[0][target_big_endian];
19925 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19926 [target_big_endian];
19933 fragP->fr_var = noop_size;
19935 if (bytes & (noop_size - 1))
19937 fix = bytes & (noop_size - 1);
19939 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19941 memset (p, 0, fix);
19948 if (bytes & noop_size)
19950 /* Insert a narrow noop. */
19951 memcpy (p, narrow_noop, noop_size);
19953 bytes -= noop_size;
19957 /* Use wide noops for the remainder */
19961 while (bytes >= noop_size)
19963 memcpy (p, noop, noop_size);
19965 bytes -= noop_size;
19969 fragP->fr_fix += fix;
19972 /* Called from md_do_align. Used to create an alignment
19973 frag in a code section. */
19976 arm_frag_align_code (int n, int max)
19980 /* We assume that there will never be a requirement
19981 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19982 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19987 _("alignments greater than %d bytes not supported in .text sections."),
19988 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19989 as_fatal ("%s", err_msg);
19992 p = frag_var (rs_align_code,
19993 MAX_MEM_FOR_RS_ALIGN_CODE,
19995 (relax_substateT) max,
20002 /* Perform target specific initialisation of a frag.
20003 Note - despite the name this initialisation is not done when the frag
20004 is created, but only when its type is assigned. A frag can be created
20005 and used a long time before its type is set, so beware of assuming that
20006 this initialisationis performed first. */
20010 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20012 /* Record whether this frag is in an ARM or a THUMB area. */
20013 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20016 #else /* OBJ_ELF is defined. */
20018 arm_init_frag (fragS * fragP, int max_chars)
20020 /* If the current ARM vs THUMB mode has not already
20021 been recorded into this frag then do so now. */
20022 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20024 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20026 /* Record a mapping symbol for alignment frags. We will delete this
20027 later if the alignment ends up empty. */
20028 switch (fragP->fr_type)
20031 case rs_align_test:
20033 mapping_state_2 (MAP_DATA, max_chars);
20035 case rs_align_code:
20036 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20044 /* When we change sections we need to issue a new mapping symbol. */
20047 arm_elf_change_section (void)
20049 /* Link an unlinked unwind index table section to the .text section. */
20050 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20051 && elf_linked_to_section (now_seg) == NULL)
20052 elf_linked_to_section (now_seg) = text_section;
20056 arm_elf_section_type (const char * str, size_t len)
20058 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20059 return SHT_ARM_EXIDX;
20064 /* Code to deal with unwinding tables. */
20066 static void add_unwind_adjustsp (offsetT);
20068 /* Generate any deferred unwind frame offset. */
20071 flush_pending_unwind (void)
20075 offset = unwind.pending_offset;
20076 unwind.pending_offset = 0;
20078 add_unwind_adjustsp (offset);
20081 /* Add an opcode to this list for this function. Two-byte opcodes should
20082 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20086 add_unwind_opcode (valueT op, int length)
20088 /* Add any deferred stack adjustment. */
20089 if (unwind.pending_offset)
20090 flush_pending_unwind ();
20092 unwind.sp_restored = 0;
20094 if (unwind.opcode_count + length > unwind.opcode_alloc)
20096 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20097 if (unwind.opcodes)
20098 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
20099 unwind.opcode_alloc);
20101 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
20106 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20108 unwind.opcode_count++;
20112 /* Add unwind opcodes to adjust the stack pointer. */
20115 add_unwind_adjustsp (offsetT offset)
20119 if (offset > 0x200)
20121 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20126 /* Long form: 0xb2, uleb128. */
20127 /* This might not fit in a word so add the individual bytes,
20128 remembering the list is built in reverse order. */
20129 o = (valueT) ((offset - 0x204) >> 2);
20131 add_unwind_opcode (0, 1);
20133 /* Calculate the uleb128 encoding of the offset. */
20137 bytes[n] = o & 0x7f;
20143 /* Add the insn. */
20145 add_unwind_opcode (bytes[n - 1], 1);
20146 add_unwind_opcode (0xb2, 1);
20148 else if (offset > 0x100)
20150 /* Two short opcodes. */
20151 add_unwind_opcode (0x3f, 1);
20152 op = (offset - 0x104) >> 2;
20153 add_unwind_opcode (op, 1);
20155 else if (offset > 0)
20157 /* Short opcode. */
20158 op = (offset - 4) >> 2;
20159 add_unwind_opcode (op, 1);
20161 else if (offset < 0)
20164 while (offset > 0x100)
20166 add_unwind_opcode (0x7f, 1);
20169 op = ((offset - 4) >> 2) | 0x40;
20170 add_unwind_opcode (op, 1);
20174 /* Finish the list of unwind opcodes for this function. */
20176 finish_unwind_opcodes (void)
20180 if (unwind.fp_used)
20182 /* Adjust sp as necessary. */
20183 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20184 flush_pending_unwind ();
20186 /* After restoring sp from the frame pointer. */
20187 op = 0x90 | unwind.fp_reg;
20188 add_unwind_opcode (op, 1);
20191 flush_pending_unwind ();
20195 /* Start an exception table entry. If idx is nonzero this is an index table
20199 start_unwind_section (const segT text_seg, int idx)
20201 const char * text_name;
20202 const char * prefix;
20203 const char * prefix_once;
20204 const char * group_name;
20208 size_t sec_name_len;
20215 prefix = ELF_STRING_ARM_unwind;
20216 prefix_once = ELF_STRING_ARM_unwind_once;
20217 type = SHT_ARM_EXIDX;
20221 prefix = ELF_STRING_ARM_unwind_info;
20222 prefix_once = ELF_STRING_ARM_unwind_info_once;
20223 type = SHT_PROGBITS;
20226 text_name = segment_name (text_seg);
20227 if (streq (text_name, ".text"))
20230 if (strncmp (text_name, ".gnu.linkonce.t.",
20231 strlen (".gnu.linkonce.t.")) == 0)
20233 prefix = prefix_once;
20234 text_name += strlen (".gnu.linkonce.t.");
20237 prefix_len = strlen (prefix);
20238 text_len = strlen (text_name);
20239 sec_name_len = prefix_len + text_len;
20240 sec_name = (char *) xmalloc (sec_name_len + 1);
20241 memcpy (sec_name, prefix, prefix_len);
20242 memcpy (sec_name + prefix_len, text_name, text_len);
20243 sec_name[prefix_len + text_len] = '\0';
20249 /* Handle COMDAT group. */
20250 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20252 group_name = elf_group_name (text_seg);
20253 if (group_name == NULL)
20255 as_bad (_("Group section `%s' has no group signature"),
20256 segment_name (text_seg));
20257 ignore_rest_of_line ();
20260 flags |= SHF_GROUP;
20264 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20266 /* Set the section link for index tables. */
20268 elf_linked_to_section (now_seg) = text_seg;
20272 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20273 personality routine data. Returns zero, or the index table value for
20274 and inline entry. */
20277 create_unwind_entry (int have_data)
20282 /* The current word of data. */
20284 /* The number of bytes left in this word. */
20287 finish_unwind_opcodes ();
20289 /* Remember the current text section. */
20290 unwind.saved_seg = now_seg;
20291 unwind.saved_subseg = now_subseg;
20293 start_unwind_section (now_seg, 0);
20295 if (unwind.personality_routine == NULL)
20297 if (unwind.personality_index == -2)
20300 as_bad (_("handlerdata in cantunwind frame"));
20301 return 1; /* EXIDX_CANTUNWIND. */
20304 /* Use a default personality routine if none is specified. */
20305 if (unwind.personality_index == -1)
20307 if (unwind.opcode_count > 3)
20308 unwind.personality_index = 1;
20310 unwind.personality_index = 0;
20313 /* Space for the personality routine entry. */
20314 if (unwind.personality_index == 0)
20316 if (unwind.opcode_count > 3)
20317 as_bad (_("too many unwind opcodes for personality routine 0"));
20321 /* All the data is inline in the index table. */
20324 while (unwind.opcode_count > 0)
20326 unwind.opcode_count--;
20327 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20331 /* Pad with "finish" opcodes. */
20333 data = (data << 8) | 0xb0;
20340 /* We get two opcodes "free" in the first word. */
20341 size = unwind.opcode_count - 2;
20345 gas_assert (unwind.personality_index == -1);
20347 /* An extra byte is required for the opcode count. */
20348 size = unwind.opcode_count + 1;
20351 size = (size + 3) >> 2;
20353 as_bad (_("too many unwind opcodes"));
20355 frag_align (2, 0, 0);
20356 record_alignment (now_seg, 2);
20357 unwind.table_entry = expr_build_dot ();
20359 /* Allocate the table entry. */
20360 ptr = frag_more ((size << 2) + 4);
20361 /* PR 13449: Zero the table entries in case some of them are not used. */
20362 memset (ptr, 0, (size << 2) + 4);
20363 where = frag_now_fix () - ((size << 2) + 4);
20365 switch (unwind.personality_index)
20368 /* ??? Should this be a PLT generating relocation? */
20369 /* Custom personality routine. */
20370 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20371 BFD_RELOC_ARM_PREL31);
20376 /* Set the first byte to the number of additional words. */
20377 data = size > 0 ? size - 1 : 0;
20381 /* ABI defined personality routines. */
20383 /* Three opcodes bytes are packed into the first word. */
20390 /* The size and first two opcode bytes go in the first word. */
20391 data = ((0x80 + unwind.personality_index) << 8) | size;
20396 /* Should never happen. */
20400 /* Pack the opcodes into words (MSB first), reversing the list at the same
20402 while (unwind.opcode_count > 0)
20406 md_number_to_chars (ptr, data, 4);
20411 unwind.opcode_count--;
20413 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20416 /* Finish off the last word. */
20419 /* Pad with "finish" opcodes. */
20421 data = (data << 8) | 0xb0;
20423 md_number_to_chars (ptr, data, 4);
20428 /* Add an empty descriptor if there is no user-specified data. */
20429 ptr = frag_more (4);
20430 md_number_to_chars (ptr, 0, 4);
20437 /* Initialize the DWARF-2 unwind information for this procedure. */
20440 tc_arm_frame_initial_instructions (void)
20442 cfi_add_CFA_def_cfa (REG_SP, 0);
20444 #endif /* OBJ_ELF */
20446 /* Convert REGNAME to a DWARF-2 register number. */
20449 tc_arm_regname_to_dw2regnum (char *regname)
20451 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20461 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20465 exp.X_op = O_secrel;
20466 exp.X_add_symbol = symbol;
20467 exp.X_add_number = 0;
20468 emit_expr (&exp, size);
20472 /* MD interface: Symbol and relocation handling. */
20474 /* Return the address within the segment that a PC-relative fixup is
20475 relative to. For ARM, PC-relative fixups applied to instructions
20476 are generally relative to the location of the fixup plus 8 bytes.
20477 Thumb branches are offset by 4, and Thumb loads relative to PC
20478 require special handling. */
20481 md_pcrel_from_section (fixS * fixP, segT seg)
20483 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20485 /* If this is pc-relative and we are going to emit a relocation
20486 then we just want to put out any pipeline compensation that the linker
20487 will need. Otherwise we want to use the calculated base.
20488 For WinCE we skip the bias for externals as well, since this
20489 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20491 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20492 || (arm_force_relocation (fixP)
20494 && !S_IS_EXTERNAL (fixP->fx_addsy)
20500 switch (fixP->fx_r_type)
20502 /* PC relative addressing on the Thumb is slightly odd as the
20503 bottom two bits of the PC are forced to zero for the
20504 calculation. This happens *after* application of the
20505 pipeline offset. However, Thumb adrl already adjusts for
20506 this, so we need not do it again. */
20507 case BFD_RELOC_ARM_THUMB_ADD:
20510 case BFD_RELOC_ARM_THUMB_OFFSET:
20511 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20512 case BFD_RELOC_ARM_T32_ADD_PC12:
20513 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20514 return (base + 4) & ~3;
20516 /* Thumb branches are simply offset by +4. */
20517 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20518 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20519 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20520 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20521 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20524 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20526 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20527 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20528 && ARM_IS_FUNC (fixP->fx_addsy)
20529 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20530 base = fixP->fx_where + fixP->fx_frag->fr_address;
20533 /* BLX is like branches above, but forces the low two bits of PC to
20535 case BFD_RELOC_THUMB_PCREL_BLX:
20537 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20538 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20539 && THUMB_IS_FUNC (fixP->fx_addsy)
20540 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20541 base = fixP->fx_where + fixP->fx_frag->fr_address;
20542 return (base + 4) & ~3;
20544 /* ARM mode branches are offset by +8. However, the Windows CE
20545 loader expects the relocation not to take this into account. */
20546 case BFD_RELOC_ARM_PCREL_BLX:
20548 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20549 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20550 && ARM_IS_FUNC (fixP->fx_addsy)
20551 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20552 base = fixP->fx_where + fixP->fx_frag->fr_address;
20555 case BFD_RELOC_ARM_PCREL_CALL:
20557 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20558 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20559 && THUMB_IS_FUNC (fixP->fx_addsy)
20560 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20561 base = fixP->fx_where + fixP->fx_frag->fr_address;
20564 case BFD_RELOC_ARM_PCREL_BRANCH:
20565 case BFD_RELOC_ARM_PCREL_JUMP:
20566 case BFD_RELOC_ARM_PLT32:
20568 /* When handling fixups immediately, because we have already
20569 discovered the value of a symbol, or the address of the frag involved
20570 we must account for the offset by +8, as the OS loader will never see the reloc.
20571 see fixup_segment() in write.c
20572 The S_IS_EXTERNAL test handles the case of global symbols.
20573 Those need the calculated base, not just the pipe compensation the linker will need. */
20575 && fixP->fx_addsy != NULL
20576 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20577 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20585 /* ARM mode loads relative to PC are also offset by +8. Unlike
20586 branches, the Windows CE loader *does* expect the relocation
20587 to take this into account. */
20588 case BFD_RELOC_ARM_OFFSET_IMM:
20589 case BFD_RELOC_ARM_OFFSET_IMM8:
20590 case BFD_RELOC_ARM_HWLITERAL:
20591 case BFD_RELOC_ARM_LITERAL:
20592 case BFD_RELOC_ARM_CP_OFF_IMM:
20596 /* Other PC-relative relocations are un-offset. */
20602 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20603 Otherwise we have no need to default values of symbols. */
20606 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20609 if (name[0] == '_' && name[1] == 'G'
20610 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20614 if (symbol_find (name))
20615 as_bad (_("GOT already in the symbol table"));
20617 GOT_symbol = symbol_new (name, undefined_section,
20618 (valueT) 0, & zero_address_frag);
20628 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20629 computed as two separate immediate values, added together. We
20630 already know that this value cannot be computed by just one ARM
20633 static unsigned int
20634 validate_immediate_twopart (unsigned int val,
20635 unsigned int * highpart)
20640 for (i = 0; i < 32; i += 2)
20641 if (((a = rotate_left (val, i)) & 0xff) != 0)
20647 * highpart = (a >> 8) | ((i + 24) << 7);
20649 else if (a & 0xff0000)
20651 if (a & 0xff000000)
20653 * highpart = (a >> 16) | ((i + 16) << 7);
20657 gas_assert (a & 0xff000000);
20658 * highpart = (a >> 24) | ((i + 8) << 7);
20661 return (a & 0xff) | (i << 7);
20668 validate_offset_imm (unsigned int val, int hwse)
20670 if ((hwse && val > 255) || val > 4095)
20675 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20676 negative immediate constant by altering the instruction. A bit of
20681 by inverting the second operand, and
20684 by negating the second operand. */
20687 negate_data_op (unsigned long * instruction,
20688 unsigned long value)
20691 unsigned long negated, inverted;
20693 negated = encode_arm_immediate (-value);
20694 inverted = encode_arm_immediate (~value);
20696 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20699 /* First negates. */
20700 case OPCODE_SUB: /* ADD <-> SUB */
20701 new_inst = OPCODE_ADD;
20706 new_inst = OPCODE_SUB;
20710 case OPCODE_CMP: /* CMP <-> CMN */
20711 new_inst = OPCODE_CMN;
20716 new_inst = OPCODE_CMP;
20720 /* Now Inverted ops. */
20721 case OPCODE_MOV: /* MOV <-> MVN */
20722 new_inst = OPCODE_MVN;
20727 new_inst = OPCODE_MOV;
20731 case OPCODE_AND: /* AND <-> BIC */
20732 new_inst = OPCODE_BIC;
20737 new_inst = OPCODE_AND;
20741 case OPCODE_ADC: /* ADC <-> SBC */
20742 new_inst = OPCODE_SBC;
20747 new_inst = OPCODE_ADC;
20751 /* We cannot do anything. */
20756 if (value == (unsigned) FAIL)
20759 *instruction &= OPCODE_MASK;
20760 *instruction |= new_inst << DATA_OP_SHIFT;
20764 /* Like negate_data_op, but for Thumb-2. */
20766 static unsigned int
20767 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20771 unsigned int negated, inverted;
20773 negated = encode_thumb32_immediate (-value);
20774 inverted = encode_thumb32_immediate (~value);
20776 rd = (*instruction >> 8) & 0xf;
20777 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20780 /* ADD <-> SUB. Includes CMP <-> CMN. */
20781 case T2_OPCODE_SUB:
20782 new_inst = T2_OPCODE_ADD;
20786 case T2_OPCODE_ADD:
20787 new_inst = T2_OPCODE_SUB;
20791 /* ORR <-> ORN. Includes MOV <-> MVN. */
20792 case T2_OPCODE_ORR:
20793 new_inst = T2_OPCODE_ORN;
20797 case T2_OPCODE_ORN:
20798 new_inst = T2_OPCODE_ORR;
20802 /* AND <-> BIC. TST has no inverted equivalent. */
20803 case T2_OPCODE_AND:
20804 new_inst = T2_OPCODE_BIC;
20811 case T2_OPCODE_BIC:
20812 new_inst = T2_OPCODE_AND;
20817 case T2_OPCODE_ADC:
20818 new_inst = T2_OPCODE_SBC;
20822 case T2_OPCODE_SBC:
20823 new_inst = T2_OPCODE_ADC;
20827 /* We cannot do anything. */
20832 if (value == (unsigned int)FAIL)
20835 *instruction &= T2_OPCODE_MASK;
20836 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20840 /* Read a 32-bit thumb instruction from buf. */
20841 static unsigned long
20842 get_thumb32_insn (char * buf)
20844 unsigned long insn;
20845 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20846 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20852 /* We usually want to set the low bit on the address of thumb function
20853 symbols. In particular .word foo - . should have the low bit set.
20854 Generic code tries to fold the difference of two symbols to
20855 a constant. Prevent this and force a relocation when the first symbols
20856 is a thumb function. */
20859 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20861 if (op == O_subtract
20862 && l->X_op == O_symbol
20863 && r->X_op == O_symbol
20864 && THUMB_IS_FUNC (l->X_add_symbol))
20866 l->X_op = O_subtract;
20867 l->X_op_symbol = r->X_add_symbol;
20868 l->X_add_number -= r->X_add_number;
20872 /* Process as normal. */
20876 /* Encode Thumb2 unconditional branches and calls. The encoding
20877 for the 2 are identical for the immediate values. */
20880 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20882 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20885 addressT S, I1, I2, lo, hi;
20887 S = (value >> 24) & 0x01;
20888 I1 = (value >> 23) & 0x01;
20889 I2 = (value >> 22) & 0x01;
20890 hi = (value >> 12) & 0x3ff;
20891 lo = (value >> 1) & 0x7ff;
20892 newval = md_chars_to_number (buf, THUMB_SIZE);
20893 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20894 newval |= (S << 10) | hi;
20895 newval2 &= ~T2I1I2MASK;
20896 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20897 md_number_to_chars (buf, newval, THUMB_SIZE);
20898 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20902 md_apply_fix (fixS * fixP,
20906 offsetT value = * valP;
20908 unsigned int newimm;
20909 unsigned long temp;
20911 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20913 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20915 /* Note whether this will delete the relocation. */
20917 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20920 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20921 consistency with the behaviour on 32-bit hosts. Remember value
20923 value &= 0xffffffff;
20924 value ^= 0x80000000;
20925 value -= 0x80000000;
20928 fixP->fx_addnumber = value;
20930 /* Same treatment for fixP->fx_offset. */
20931 fixP->fx_offset &= 0xffffffff;
20932 fixP->fx_offset ^= 0x80000000;
20933 fixP->fx_offset -= 0x80000000;
20935 switch (fixP->fx_r_type)
20937 case BFD_RELOC_NONE:
20938 /* This will need to go in the object file. */
20942 case BFD_RELOC_ARM_IMMEDIATE:
20943 /* We claim that this fixup has been processed here,
20944 even if in fact we generate an error because we do
20945 not have a reloc for it, so tc_gen_reloc will reject it. */
20948 if (fixP->fx_addsy)
20950 const char *msg = 0;
20952 if (! S_IS_DEFINED (fixP->fx_addsy))
20953 msg = _("undefined symbol %s used as an immediate value");
20954 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20955 msg = _("symbol %s is in a different section");
20956 else if (S_IS_WEAK (fixP->fx_addsy))
20957 msg = _("symbol %s is weak and may be overridden later");
20961 as_bad_where (fixP->fx_file, fixP->fx_line,
20962 msg, S_GET_NAME (fixP->fx_addsy));
20967 temp = md_chars_to_number (buf, INSN_SIZE);
20969 /* If the offset is negative, we should use encoding A2 for ADR. */
20970 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
20971 newimm = negate_data_op (&temp, value);
20974 newimm = encode_arm_immediate (value);
20976 /* If the instruction will fail, see if we can fix things up by
20977 changing the opcode. */
20978 if (newimm == (unsigned int) FAIL)
20979 newimm = negate_data_op (&temp, value);
20982 if (newimm == (unsigned int) FAIL)
20984 as_bad_where (fixP->fx_file, fixP->fx_line,
20985 _("invalid constant (%lx) after fixup"),
20986 (unsigned long) value);
20990 newimm |= (temp & 0xfffff000);
20991 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20994 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20996 unsigned int highpart = 0;
20997 unsigned int newinsn = 0xe1a00000; /* nop. */
20999 if (fixP->fx_addsy)
21001 const char *msg = 0;
21003 if (! S_IS_DEFINED (fixP->fx_addsy))
21004 msg = _("undefined symbol %s used as an immediate value");
21005 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21006 msg = _("symbol %s is in a different section");
21007 else if (S_IS_WEAK (fixP->fx_addsy))
21008 msg = _("symbol %s is weak and may be overridden later");
21012 as_bad_where (fixP->fx_file, fixP->fx_line,
21013 msg, S_GET_NAME (fixP->fx_addsy));
21018 newimm = encode_arm_immediate (value);
21019 temp = md_chars_to_number (buf, INSN_SIZE);
21021 /* If the instruction will fail, see if we can fix things up by
21022 changing the opcode. */
21023 if (newimm == (unsigned int) FAIL
21024 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21026 /* No ? OK - try using two ADD instructions to generate
21028 newimm = validate_immediate_twopart (value, & highpart);
21030 /* Yes - then make sure that the second instruction is
21032 if (newimm != (unsigned int) FAIL)
21034 /* Still No ? Try using a negated value. */
21035 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21036 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21037 /* Otherwise - give up. */
21040 as_bad_where (fixP->fx_file, fixP->fx_line,
21041 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21046 /* Replace the first operand in the 2nd instruction (which
21047 is the PC) with the destination register. We have
21048 already added in the PC in the first instruction and we
21049 do not want to do it again. */
21050 newinsn &= ~ 0xf0000;
21051 newinsn |= ((newinsn & 0x0f000) << 4);
21054 newimm |= (temp & 0xfffff000);
21055 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21057 highpart |= (newinsn & 0xfffff000);
21058 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21062 case BFD_RELOC_ARM_OFFSET_IMM:
21063 if (!fixP->fx_done && seg->use_rela_p)
21066 case BFD_RELOC_ARM_LITERAL:
21072 if (validate_offset_imm (value, 0) == FAIL)
21074 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21075 as_bad_where (fixP->fx_file, fixP->fx_line,
21076 _("invalid literal constant: pool needs to be closer"));
21078 as_bad_where (fixP->fx_file, fixP->fx_line,
21079 _("bad immediate value for offset (%ld)"),
21084 newval = md_chars_to_number (buf, INSN_SIZE);
21086 newval &= 0xfffff000;
21089 newval &= 0xff7ff000;
21090 newval |= value | (sign ? INDEX_UP : 0);
21092 md_number_to_chars (buf, newval, INSN_SIZE);
21095 case BFD_RELOC_ARM_OFFSET_IMM8:
21096 case BFD_RELOC_ARM_HWLITERAL:
21102 if (validate_offset_imm (value, 1) == FAIL)
21104 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21105 as_bad_where (fixP->fx_file, fixP->fx_line,
21106 _("invalid literal constant: pool needs to be closer"));
21108 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
21113 newval = md_chars_to_number (buf, INSN_SIZE);
21115 newval &= 0xfffff0f0;
21118 newval &= 0xff7ff0f0;
21119 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21121 md_number_to_chars (buf, newval, INSN_SIZE);
21124 case BFD_RELOC_ARM_T32_OFFSET_U8:
21125 if (value < 0 || value > 1020 || value % 4 != 0)
21126 as_bad_where (fixP->fx_file, fixP->fx_line,
21127 _("bad immediate value for offset (%ld)"), (long) value);
21130 newval = md_chars_to_number (buf+2, THUMB_SIZE);
21132 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21135 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21136 /* This is a complicated relocation used for all varieties of Thumb32
21137 load/store instruction with immediate offset:
21139 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21140 *4, optional writeback(W)
21141 (doubleword load/store)
21143 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21144 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21145 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21146 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21147 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21149 Uppercase letters indicate bits that are already encoded at
21150 this point. Lowercase letters are our problem. For the
21151 second block of instructions, the secondary opcode nybble
21152 (bits 8..11) is present, and bit 23 is zero, even if this is
21153 a PC-relative operation. */
21154 newval = md_chars_to_number (buf, THUMB_SIZE);
21156 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
21158 if ((newval & 0xf0000000) == 0xe0000000)
21160 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21162 newval |= (1 << 23);
21165 if (value % 4 != 0)
21167 as_bad_where (fixP->fx_file, fixP->fx_line,
21168 _("offset not a multiple of 4"));
21174 as_bad_where (fixP->fx_file, fixP->fx_line,
21175 _("offset out of range"));
21180 else if ((newval & 0x000f0000) == 0x000f0000)
21182 /* PC-relative, 12-bit offset. */
21184 newval |= (1 << 23);
21189 as_bad_where (fixP->fx_file, fixP->fx_line,
21190 _("offset out of range"));
21195 else if ((newval & 0x00000100) == 0x00000100)
21197 /* Writeback: 8-bit, +/- offset. */
21199 newval |= (1 << 9);
21204 as_bad_where (fixP->fx_file, fixP->fx_line,
21205 _("offset out of range"));
21210 else if ((newval & 0x00000f00) == 0x00000e00)
21212 /* T-instruction: positive 8-bit offset. */
21213 if (value < 0 || value > 0xff)
21215 as_bad_where (fixP->fx_file, fixP->fx_line,
21216 _("offset out of range"));
21224 /* Positive 12-bit or negative 8-bit offset. */
21228 newval |= (1 << 23);
21238 as_bad_where (fixP->fx_file, fixP->fx_line,
21239 _("offset out of range"));
21246 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21247 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21250 case BFD_RELOC_ARM_SHIFT_IMM:
21251 newval = md_chars_to_number (buf, INSN_SIZE);
21252 if (((unsigned long) value) > 32
21254 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21256 as_bad_where (fixP->fx_file, fixP->fx_line,
21257 _("shift expression is too large"));
21262 /* Shifts of zero must be done as lsl. */
21264 else if (value == 32)
21266 newval &= 0xfffff07f;
21267 newval |= (value & 0x1f) << 7;
21268 md_number_to_chars (buf, newval, INSN_SIZE);
21271 case BFD_RELOC_ARM_T32_IMMEDIATE:
21272 case BFD_RELOC_ARM_T32_ADD_IMM:
21273 case BFD_RELOC_ARM_T32_IMM12:
21274 case BFD_RELOC_ARM_T32_ADD_PC12:
21275 /* We claim that this fixup has been processed here,
21276 even if in fact we generate an error because we do
21277 not have a reloc for it, so tc_gen_reloc will reject it. */
21281 && ! S_IS_DEFINED (fixP->fx_addsy))
21283 as_bad_where (fixP->fx_file, fixP->fx_line,
21284 _("undefined symbol %s used as an immediate value"),
21285 S_GET_NAME (fixP->fx_addsy));
21289 newval = md_chars_to_number (buf, THUMB_SIZE);
21291 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21294 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21295 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21297 newimm = encode_thumb32_immediate (value);
21298 if (newimm == (unsigned int) FAIL)
21299 newimm = thumb32_negate_data_op (&newval, value);
21301 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21302 && newimm == (unsigned int) FAIL)
21304 /* Turn add/sum into addw/subw. */
21305 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21306 newval = (newval & 0xfeffffff) | 0x02000000;
21307 /* No flat 12-bit imm encoding for addsw/subsw. */
21308 if ((newval & 0x00100000) == 0)
21310 /* 12 bit immediate for addw/subw. */
21314 newval ^= 0x00a00000;
21317 newimm = (unsigned int) FAIL;
21323 if (newimm == (unsigned int)FAIL)
21325 as_bad_where (fixP->fx_file, fixP->fx_line,
21326 _("invalid constant (%lx) after fixup"),
21327 (unsigned long) value);
21331 newval |= (newimm & 0x800) << 15;
21332 newval |= (newimm & 0x700) << 4;
21333 newval |= (newimm & 0x0ff);
21335 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21336 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21339 case BFD_RELOC_ARM_SMC:
21340 if (((unsigned long) value) > 0xffff)
21341 as_bad_where (fixP->fx_file, fixP->fx_line,
21342 _("invalid smc expression"));
21343 newval = md_chars_to_number (buf, INSN_SIZE);
21344 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21345 md_number_to_chars (buf, newval, INSN_SIZE);
21348 case BFD_RELOC_ARM_HVC:
21349 if (((unsigned long) value) > 0xffff)
21350 as_bad_where (fixP->fx_file, fixP->fx_line,
21351 _("invalid hvc expression"));
21352 newval = md_chars_to_number (buf, INSN_SIZE);
21353 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21354 md_number_to_chars (buf, newval, INSN_SIZE);
21357 case BFD_RELOC_ARM_SWI:
21358 if (fixP->tc_fix_data != 0)
21360 if (((unsigned long) value) > 0xff)
21361 as_bad_where (fixP->fx_file, fixP->fx_line,
21362 _("invalid swi expression"));
21363 newval = md_chars_to_number (buf, THUMB_SIZE);
21365 md_number_to_chars (buf, newval, THUMB_SIZE);
21369 if (((unsigned long) value) > 0x00ffffff)
21370 as_bad_where (fixP->fx_file, fixP->fx_line,
21371 _("invalid swi expression"));
21372 newval = md_chars_to_number (buf, INSN_SIZE);
21374 md_number_to_chars (buf, newval, INSN_SIZE);
21378 case BFD_RELOC_ARM_MULTI:
21379 if (((unsigned long) value) > 0xffff)
21380 as_bad_where (fixP->fx_file, fixP->fx_line,
21381 _("invalid expression in load/store multiple"));
21382 newval = value | md_chars_to_number (buf, INSN_SIZE);
21383 md_number_to_chars (buf, newval, INSN_SIZE);
21387 case BFD_RELOC_ARM_PCREL_CALL:
21389 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21391 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21392 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21393 && THUMB_IS_FUNC (fixP->fx_addsy))
21394 /* Flip the bl to blx. This is a simple flip
21395 bit here because we generate PCREL_CALL for
21396 unconditional bls. */
21398 newval = md_chars_to_number (buf, INSN_SIZE);
21399 newval = newval | 0x10000000;
21400 md_number_to_chars (buf, newval, INSN_SIZE);
21406 goto arm_branch_common;
21408 case BFD_RELOC_ARM_PCREL_JUMP:
21409 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21411 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21412 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21413 && THUMB_IS_FUNC (fixP->fx_addsy))
21415 /* This would map to a bl<cond>, b<cond>,
21416 b<always> to a Thumb function. We
21417 need to force a relocation for this particular
21419 newval = md_chars_to_number (buf, INSN_SIZE);
21423 case BFD_RELOC_ARM_PLT32:
21425 case BFD_RELOC_ARM_PCREL_BRANCH:
21427 goto arm_branch_common;
21429 case BFD_RELOC_ARM_PCREL_BLX:
21432 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21434 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21435 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21436 && ARM_IS_FUNC (fixP->fx_addsy))
21438 /* Flip the blx to a bl and warn. */
21439 const char *name = S_GET_NAME (fixP->fx_addsy);
21440 newval = 0xeb000000;
21441 as_warn_where (fixP->fx_file, fixP->fx_line,
21442 _("blx to '%s' an ARM ISA state function changed to bl"),
21444 md_number_to_chars (buf, newval, INSN_SIZE);
21450 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21451 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21455 /* We are going to store value (shifted right by two) in the
21456 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21457 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21458 also be be clear. */
21460 as_bad_where (fixP->fx_file, fixP->fx_line,
21461 _("misaligned branch destination"));
21462 if ((value & (offsetT)0xfe000000) != (offsetT)0
21463 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21464 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21466 if (fixP->fx_done || !seg->use_rela_p)
21468 newval = md_chars_to_number (buf, INSN_SIZE);
21469 newval |= (value >> 2) & 0x00ffffff;
21470 /* Set the H bit on BLX instructions. */
21474 newval |= 0x01000000;
21476 newval &= ~0x01000000;
21478 md_number_to_chars (buf, newval, INSN_SIZE);
21482 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21483 /* CBZ can only branch forward. */
21485 /* Attempts to use CBZ to branch to the next instruction
21486 (which, strictly speaking, are prohibited) will be turned into
21489 FIXME: It may be better to remove the instruction completely and
21490 perform relaxation. */
21493 newval = md_chars_to_number (buf, THUMB_SIZE);
21494 newval = 0xbf00; /* NOP encoding T1 */
21495 md_number_to_chars (buf, newval, THUMB_SIZE);
21500 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21502 if (fixP->fx_done || !seg->use_rela_p)
21504 newval = md_chars_to_number (buf, THUMB_SIZE);
21505 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21506 md_number_to_chars (buf, newval, THUMB_SIZE);
21511 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21512 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21513 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21515 if (fixP->fx_done || !seg->use_rela_p)
21517 newval = md_chars_to_number (buf, THUMB_SIZE);
21518 newval |= (value & 0x1ff) >> 1;
21519 md_number_to_chars (buf, newval, THUMB_SIZE);
21523 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21524 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21525 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21527 if (fixP->fx_done || !seg->use_rela_p)
21529 newval = md_chars_to_number (buf, THUMB_SIZE);
21530 newval |= (value & 0xfff) >> 1;
21531 md_number_to_chars (buf, newval, THUMB_SIZE);
21535 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21537 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21538 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21539 && ARM_IS_FUNC (fixP->fx_addsy)
21540 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21542 /* Force a relocation for a branch 20 bits wide. */
21545 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21546 as_bad_where (fixP->fx_file, fixP->fx_line,
21547 _("conditional branch out of range"));
21549 if (fixP->fx_done || !seg->use_rela_p)
21552 addressT S, J1, J2, lo, hi;
21554 S = (value & 0x00100000) >> 20;
21555 J2 = (value & 0x00080000) >> 19;
21556 J1 = (value & 0x00040000) >> 18;
21557 hi = (value & 0x0003f000) >> 12;
21558 lo = (value & 0x00000ffe) >> 1;
21560 newval = md_chars_to_number (buf, THUMB_SIZE);
21561 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21562 newval |= (S << 10) | hi;
21563 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21564 md_number_to_chars (buf, newval, THUMB_SIZE);
21565 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21569 case BFD_RELOC_THUMB_PCREL_BLX:
21570 /* If there is a blx from a thumb state function to
21571 another thumb function flip this to a bl and warn
21575 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21576 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21577 && THUMB_IS_FUNC (fixP->fx_addsy))
21579 const char *name = S_GET_NAME (fixP->fx_addsy);
21580 as_warn_where (fixP->fx_file, fixP->fx_line,
21581 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21583 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21584 newval = newval | 0x1000;
21585 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21586 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21591 goto thumb_bl_common;
21593 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21594 /* A bl from Thumb state ISA to an internal ARM state function
21595 is converted to a blx. */
21597 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21598 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21599 && ARM_IS_FUNC (fixP->fx_addsy)
21600 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21602 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21603 newval = newval & ~0x1000;
21604 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21605 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21612 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
21613 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21614 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21617 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21618 /* For a BLX instruction, make sure that the relocation is rounded up
21619 to a word boundary. This follows the semantics of the instruction
21620 which specifies that bit 1 of the target address will come from bit
21621 1 of the base address. */
21622 value = (value + 1) & ~ 1;
21624 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21626 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21627 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21628 else if ((value & ~0x1ffffff)
21629 && ((value & ~0x1ffffff) != ~0x1ffffff))
21630 as_bad_where (fixP->fx_file, fixP->fx_line,
21631 _("Thumb2 branch out of range"));
21634 if (fixP->fx_done || !seg->use_rela_p)
21635 encode_thumb2_b_bl_offset (buf, value);
21639 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21640 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21641 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21643 if (fixP->fx_done || !seg->use_rela_p)
21644 encode_thumb2_b_bl_offset (buf, value);
21649 if (fixP->fx_done || !seg->use_rela_p)
21650 md_number_to_chars (buf, value, 1);
21654 if (fixP->fx_done || !seg->use_rela_p)
21655 md_number_to_chars (buf, value, 2);
21659 case BFD_RELOC_ARM_TLS_CALL:
21660 case BFD_RELOC_ARM_THM_TLS_CALL:
21661 case BFD_RELOC_ARM_TLS_DESCSEQ:
21662 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21663 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21666 case BFD_RELOC_ARM_TLS_GOTDESC:
21667 case BFD_RELOC_ARM_TLS_GD32:
21668 case BFD_RELOC_ARM_TLS_LE32:
21669 case BFD_RELOC_ARM_TLS_IE32:
21670 case BFD_RELOC_ARM_TLS_LDM32:
21671 case BFD_RELOC_ARM_TLS_LDO32:
21672 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21675 case BFD_RELOC_ARM_GOT32:
21676 case BFD_RELOC_ARM_GOTOFF:
21677 if (fixP->fx_done || !seg->use_rela_p)
21678 md_number_to_chars (buf, 0, 4);
21681 case BFD_RELOC_ARM_GOT_PREL:
21682 if (fixP->fx_done || !seg->use_rela_p)
21683 md_number_to_chars (buf, value, 4);
21686 case BFD_RELOC_ARM_TARGET2:
21687 /* TARGET2 is not partial-inplace, so we need to write the
21688 addend here for REL targets, because it won't be written out
21689 during reloc processing later. */
21690 if (fixP->fx_done || !seg->use_rela_p)
21691 md_number_to_chars (buf, fixP->fx_offset, 4);
21695 case BFD_RELOC_RVA:
21697 case BFD_RELOC_ARM_TARGET1:
21698 case BFD_RELOC_ARM_ROSEGREL32:
21699 case BFD_RELOC_ARM_SBREL32:
21700 case BFD_RELOC_32_PCREL:
21702 case BFD_RELOC_32_SECREL:
21704 if (fixP->fx_done || !seg->use_rela_p)
21706 /* For WinCE we only do this for pcrel fixups. */
21707 if (fixP->fx_done || fixP->fx_pcrel)
21709 md_number_to_chars (buf, value, 4);
21713 case BFD_RELOC_ARM_PREL31:
21714 if (fixP->fx_done || !seg->use_rela_p)
21716 newval = md_chars_to_number (buf, 4) & 0x80000000;
21717 if ((value ^ (value >> 1)) & 0x40000000)
21719 as_bad_where (fixP->fx_file, fixP->fx_line,
21720 _("rel31 relocation overflow"));
21722 newval |= value & 0x7fffffff;
21723 md_number_to_chars (buf, newval, 4);
21728 case BFD_RELOC_ARM_CP_OFF_IMM:
21729 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21730 if (value < -1023 || value > 1023 || (value & 3))
21731 as_bad_where (fixP->fx_file, fixP->fx_line,
21732 _("co-processor offset out of range"));
21737 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21738 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21739 newval = md_chars_to_number (buf, INSN_SIZE);
21741 newval = get_thumb32_insn (buf);
21743 newval &= 0xffffff00;
21746 newval &= 0xff7fff00;
21747 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21749 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21750 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21751 md_number_to_chars (buf, newval, INSN_SIZE);
21753 put_thumb32_insn (buf, newval);
21756 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21757 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21758 if (value < -255 || value > 255)
21759 as_bad_where (fixP->fx_file, fixP->fx_line,
21760 _("co-processor offset out of range"));
21762 goto cp_off_common;
21764 case BFD_RELOC_ARM_THUMB_OFFSET:
21765 newval = md_chars_to_number (buf, THUMB_SIZE);
21766 /* Exactly what ranges, and where the offset is inserted depends
21767 on the type of instruction, we can establish this from the
21769 switch (newval >> 12)
21771 case 4: /* PC load. */
21772 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21773 forced to zero for these loads; md_pcrel_from has already
21774 compensated for this. */
21776 as_bad_where (fixP->fx_file, fixP->fx_line,
21777 _("invalid offset, target not word aligned (0x%08lX)"),
21778 (((unsigned long) fixP->fx_frag->fr_address
21779 + (unsigned long) fixP->fx_where) & ~3)
21780 + (unsigned long) value);
21782 if (value & ~0x3fc)
21783 as_bad_where (fixP->fx_file, fixP->fx_line,
21784 _("invalid offset, value too big (0x%08lX)"),
21787 newval |= value >> 2;
21790 case 9: /* SP load/store. */
21791 if (value & ~0x3fc)
21792 as_bad_where (fixP->fx_file, fixP->fx_line,
21793 _("invalid offset, value too big (0x%08lX)"),
21795 newval |= value >> 2;
21798 case 6: /* Word load/store. */
21800 as_bad_where (fixP->fx_file, fixP->fx_line,
21801 _("invalid offset, value too big (0x%08lX)"),
21803 newval |= value << 4; /* 6 - 2. */
21806 case 7: /* Byte load/store. */
21808 as_bad_where (fixP->fx_file, fixP->fx_line,
21809 _("invalid offset, value too big (0x%08lX)"),
21811 newval |= value << 6;
21814 case 8: /* Halfword load/store. */
21816 as_bad_where (fixP->fx_file, fixP->fx_line,
21817 _("invalid offset, value too big (0x%08lX)"),
21819 newval |= value << 5; /* 6 - 1. */
21823 as_bad_where (fixP->fx_file, fixP->fx_line,
21824 "Unable to process relocation for thumb opcode: %lx",
21825 (unsigned long) newval);
21828 md_number_to_chars (buf, newval, THUMB_SIZE);
21831 case BFD_RELOC_ARM_THUMB_ADD:
21832 /* This is a complicated relocation, since we use it for all of
21833 the following immediate relocations:
21837 9bit ADD/SUB SP word-aligned
21838 10bit ADD PC/SP word-aligned
21840 The type of instruction being processed is encoded in the
21847 newval = md_chars_to_number (buf, THUMB_SIZE);
21849 int rd = (newval >> 4) & 0xf;
21850 int rs = newval & 0xf;
21851 int subtract = !!(newval & 0x8000);
21853 /* Check for HI regs, only very restricted cases allowed:
21854 Adjusting SP, and using PC or SP to get an address. */
21855 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21856 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21857 as_bad_where (fixP->fx_file, fixP->fx_line,
21858 _("invalid Hi register with immediate"));
21860 /* If value is negative, choose the opposite instruction. */
21864 subtract = !subtract;
21866 as_bad_where (fixP->fx_file, fixP->fx_line,
21867 _("immediate value out of range"));
21872 if (value & ~0x1fc)
21873 as_bad_where (fixP->fx_file, fixP->fx_line,
21874 _("invalid immediate for stack address calculation"));
21875 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21876 newval |= value >> 2;
21878 else if (rs == REG_PC || rs == REG_SP)
21880 if (subtract || value & ~0x3fc)
21881 as_bad_where (fixP->fx_file, fixP->fx_line,
21882 _("invalid immediate for address calculation (value = 0x%08lX)"),
21883 (unsigned long) value);
21884 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21886 newval |= value >> 2;
21891 as_bad_where (fixP->fx_file, fixP->fx_line,
21892 _("immediate value out of range"));
21893 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21894 newval |= (rd << 8) | value;
21899 as_bad_where (fixP->fx_file, fixP->fx_line,
21900 _("immediate value out of range"));
21901 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21902 newval |= rd | (rs << 3) | (value << 6);
21905 md_number_to_chars (buf, newval, THUMB_SIZE);
21908 case BFD_RELOC_ARM_THUMB_IMM:
21909 newval = md_chars_to_number (buf, THUMB_SIZE);
21910 if (value < 0 || value > 255)
21911 as_bad_where (fixP->fx_file, fixP->fx_line,
21912 _("invalid immediate: %ld is out of range"),
21915 md_number_to_chars (buf, newval, THUMB_SIZE);
21918 case BFD_RELOC_ARM_THUMB_SHIFT:
21919 /* 5bit shift value (0..32). LSL cannot take 32. */
21920 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21921 temp = newval & 0xf800;
21922 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21923 as_bad_where (fixP->fx_file, fixP->fx_line,
21924 _("invalid shift value: %ld"), (long) value);
21925 /* Shifts of zero must be encoded as LSL. */
21927 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21928 /* Shifts of 32 are encoded as zero. */
21929 else if (value == 32)
21931 newval |= value << 6;
21932 md_number_to_chars (buf, newval, THUMB_SIZE);
21935 case BFD_RELOC_VTABLE_INHERIT:
21936 case BFD_RELOC_VTABLE_ENTRY:
21940 case BFD_RELOC_ARM_MOVW:
21941 case BFD_RELOC_ARM_MOVT:
21942 case BFD_RELOC_ARM_THUMB_MOVW:
21943 case BFD_RELOC_ARM_THUMB_MOVT:
21944 if (fixP->fx_done || !seg->use_rela_p)
21946 /* REL format relocations are limited to a 16-bit addend. */
21947 if (!fixP->fx_done)
21949 if (value < -0x8000 || value > 0x7fff)
21950 as_bad_where (fixP->fx_file, fixP->fx_line,
21951 _("offset out of range"));
21953 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21954 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21959 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21960 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21962 newval = get_thumb32_insn (buf);
21963 newval &= 0xfbf08f00;
21964 newval |= (value & 0xf000) << 4;
21965 newval |= (value & 0x0800) << 15;
21966 newval |= (value & 0x0700) << 4;
21967 newval |= (value & 0x00ff);
21968 put_thumb32_insn (buf, newval);
21972 newval = md_chars_to_number (buf, 4);
21973 newval &= 0xfff0f000;
21974 newval |= value & 0x0fff;
21975 newval |= (value & 0xf000) << 4;
21976 md_number_to_chars (buf, newval, 4);
21981 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21982 case BFD_RELOC_ARM_ALU_PC_G0:
21983 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21984 case BFD_RELOC_ARM_ALU_PC_G1:
21985 case BFD_RELOC_ARM_ALU_PC_G2:
21986 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21987 case BFD_RELOC_ARM_ALU_SB_G0:
21988 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21989 case BFD_RELOC_ARM_ALU_SB_G1:
21990 case BFD_RELOC_ARM_ALU_SB_G2:
21991 gas_assert (!fixP->fx_done);
21992 if (!seg->use_rela_p)
21995 bfd_vma encoded_addend;
21996 bfd_vma addend_abs = abs (value);
21998 /* Check that the absolute value of the addend can be
21999 expressed as an 8-bit constant plus a rotation. */
22000 encoded_addend = encode_arm_immediate (addend_abs);
22001 if (encoded_addend == (unsigned int) FAIL)
22002 as_bad_where (fixP->fx_file, fixP->fx_line,
22003 _("the offset 0x%08lX is not representable"),
22004 (unsigned long) addend_abs);
22006 /* Extract the instruction. */
22007 insn = md_chars_to_number (buf, INSN_SIZE);
22009 /* If the addend is positive, use an ADD instruction.
22010 Otherwise use a SUB. Take care not to destroy the S bit. */
22011 insn &= 0xff1fffff;
22017 /* Place the encoded addend into the first 12 bits of the
22019 insn &= 0xfffff000;
22020 insn |= encoded_addend;
22022 /* Update the instruction. */
22023 md_number_to_chars (buf, insn, INSN_SIZE);
22027 case BFD_RELOC_ARM_LDR_PC_G0:
22028 case BFD_RELOC_ARM_LDR_PC_G1:
22029 case BFD_RELOC_ARM_LDR_PC_G2:
22030 case BFD_RELOC_ARM_LDR_SB_G0:
22031 case BFD_RELOC_ARM_LDR_SB_G1:
22032 case BFD_RELOC_ARM_LDR_SB_G2:
22033 gas_assert (!fixP->fx_done);
22034 if (!seg->use_rela_p)
22037 bfd_vma addend_abs = abs (value);
22039 /* Check that the absolute value of the addend can be
22040 encoded in 12 bits. */
22041 if (addend_abs >= 0x1000)
22042 as_bad_where (fixP->fx_file, fixP->fx_line,
22043 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22044 (unsigned long) addend_abs);
22046 /* Extract the instruction. */
22047 insn = md_chars_to_number (buf, INSN_SIZE);
22049 /* If the addend is negative, clear bit 23 of the instruction.
22050 Otherwise set it. */
22052 insn &= ~(1 << 23);
22056 /* Place the absolute value of the addend into the first 12 bits
22057 of the instruction. */
22058 insn &= 0xfffff000;
22059 insn |= addend_abs;
22061 /* Update the instruction. */
22062 md_number_to_chars (buf, insn, INSN_SIZE);
22066 case BFD_RELOC_ARM_LDRS_PC_G0:
22067 case BFD_RELOC_ARM_LDRS_PC_G1:
22068 case BFD_RELOC_ARM_LDRS_PC_G2:
22069 case BFD_RELOC_ARM_LDRS_SB_G0:
22070 case BFD_RELOC_ARM_LDRS_SB_G1:
22071 case BFD_RELOC_ARM_LDRS_SB_G2:
22072 gas_assert (!fixP->fx_done);
22073 if (!seg->use_rela_p)
22076 bfd_vma addend_abs = abs (value);
22078 /* Check that the absolute value of the addend can be
22079 encoded in 8 bits. */
22080 if (addend_abs >= 0x100)
22081 as_bad_where (fixP->fx_file, fixP->fx_line,
22082 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22083 (unsigned long) addend_abs);
22085 /* Extract the instruction. */
22086 insn = md_chars_to_number (buf, INSN_SIZE);
22088 /* If the addend is negative, clear bit 23 of the instruction.
22089 Otherwise set it. */
22091 insn &= ~(1 << 23);
22095 /* Place the first four bits of the absolute value of the addend
22096 into the first 4 bits of the instruction, and the remaining
22097 four into bits 8 .. 11. */
22098 insn &= 0xfffff0f0;
22099 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22101 /* Update the instruction. */
22102 md_number_to_chars (buf, insn, INSN_SIZE);
22106 case BFD_RELOC_ARM_LDC_PC_G0:
22107 case BFD_RELOC_ARM_LDC_PC_G1:
22108 case BFD_RELOC_ARM_LDC_PC_G2:
22109 case BFD_RELOC_ARM_LDC_SB_G0:
22110 case BFD_RELOC_ARM_LDC_SB_G1:
22111 case BFD_RELOC_ARM_LDC_SB_G2:
22112 gas_assert (!fixP->fx_done);
22113 if (!seg->use_rela_p)
22116 bfd_vma addend_abs = abs (value);
22118 /* Check that the absolute value of the addend is a multiple of
22119 four and, when divided by four, fits in 8 bits. */
22120 if (addend_abs & 0x3)
22121 as_bad_where (fixP->fx_file, fixP->fx_line,
22122 _("bad offset 0x%08lX (must be word-aligned)"),
22123 (unsigned long) addend_abs);
22125 if ((addend_abs >> 2) > 0xff)
22126 as_bad_where (fixP->fx_file, fixP->fx_line,
22127 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22128 (unsigned long) addend_abs);
22130 /* Extract the instruction. */
22131 insn = md_chars_to_number (buf, INSN_SIZE);
22133 /* If the addend is negative, clear bit 23 of the instruction.
22134 Otherwise set it. */
22136 insn &= ~(1 << 23);
22140 /* Place the addend (divided by four) into the first eight
22141 bits of the instruction. */
22142 insn &= 0xfffffff0;
22143 insn |= addend_abs >> 2;
22145 /* Update the instruction. */
22146 md_number_to_chars (buf, insn, INSN_SIZE);
22150 case BFD_RELOC_ARM_V4BX:
22151 /* This will need to go in the object file. */
22155 case BFD_RELOC_UNUSED:
22157 as_bad_where (fixP->fx_file, fixP->fx_line,
22158 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22162 /* Translate internal representation of relocation info to BFD target
22166 tc_gen_reloc (asection *section, fixS *fixp)
22169 bfd_reloc_code_real_type code;
22171 reloc = (arelent *) xmalloc (sizeof (arelent));
22173 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
22174 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22175 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
22177 if (fixp->fx_pcrel)
22179 if (section->use_rela_p)
22180 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22182 fixp->fx_offset = reloc->address;
22184 reloc->addend = fixp->fx_offset;
22186 switch (fixp->fx_r_type)
22189 if (fixp->fx_pcrel)
22191 code = BFD_RELOC_8_PCREL;
22196 if (fixp->fx_pcrel)
22198 code = BFD_RELOC_16_PCREL;
22203 if (fixp->fx_pcrel)
22205 code = BFD_RELOC_32_PCREL;
22209 case BFD_RELOC_ARM_MOVW:
22210 if (fixp->fx_pcrel)
22212 code = BFD_RELOC_ARM_MOVW_PCREL;
22216 case BFD_RELOC_ARM_MOVT:
22217 if (fixp->fx_pcrel)
22219 code = BFD_RELOC_ARM_MOVT_PCREL;
22223 case BFD_RELOC_ARM_THUMB_MOVW:
22224 if (fixp->fx_pcrel)
22226 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22230 case BFD_RELOC_ARM_THUMB_MOVT:
22231 if (fixp->fx_pcrel)
22233 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22237 case BFD_RELOC_NONE:
22238 case BFD_RELOC_ARM_PCREL_BRANCH:
22239 case BFD_RELOC_ARM_PCREL_BLX:
22240 case BFD_RELOC_RVA:
22241 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22242 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22243 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22244 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22245 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22246 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22247 case BFD_RELOC_VTABLE_ENTRY:
22248 case BFD_RELOC_VTABLE_INHERIT:
22250 case BFD_RELOC_32_SECREL:
22252 code = fixp->fx_r_type;
22255 case BFD_RELOC_THUMB_PCREL_BLX:
22257 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22258 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22261 code = BFD_RELOC_THUMB_PCREL_BLX;
22264 case BFD_RELOC_ARM_LITERAL:
22265 case BFD_RELOC_ARM_HWLITERAL:
22266 /* If this is called then the a literal has
22267 been referenced across a section boundary. */
22268 as_bad_where (fixp->fx_file, fixp->fx_line,
22269 _("literal referenced across section boundary"));
22273 case BFD_RELOC_ARM_TLS_CALL:
22274 case BFD_RELOC_ARM_THM_TLS_CALL:
22275 case BFD_RELOC_ARM_TLS_DESCSEQ:
22276 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22277 case BFD_RELOC_ARM_GOT32:
22278 case BFD_RELOC_ARM_GOTOFF:
22279 case BFD_RELOC_ARM_GOT_PREL:
22280 case BFD_RELOC_ARM_PLT32:
22281 case BFD_RELOC_ARM_TARGET1:
22282 case BFD_RELOC_ARM_ROSEGREL32:
22283 case BFD_RELOC_ARM_SBREL32:
22284 case BFD_RELOC_ARM_PREL31:
22285 case BFD_RELOC_ARM_TARGET2:
22286 case BFD_RELOC_ARM_TLS_LE32:
22287 case BFD_RELOC_ARM_TLS_LDO32:
22288 case BFD_RELOC_ARM_PCREL_CALL:
22289 case BFD_RELOC_ARM_PCREL_JUMP:
22290 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22291 case BFD_RELOC_ARM_ALU_PC_G0:
22292 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22293 case BFD_RELOC_ARM_ALU_PC_G1:
22294 case BFD_RELOC_ARM_ALU_PC_G2:
22295 case BFD_RELOC_ARM_LDR_PC_G0:
22296 case BFD_RELOC_ARM_LDR_PC_G1:
22297 case BFD_RELOC_ARM_LDR_PC_G2:
22298 case BFD_RELOC_ARM_LDRS_PC_G0:
22299 case BFD_RELOC_ARM_LDRS_PC_G1:
22300 case BFD_RELOC_ARM_LDRS_PC_G2:
22301 case BFD_RELOC_ARM_LDC_PC_G0:
22302 case BFD_RELOC_ARM_LDC_PC_G1:
22303 case BFD_RELOC_ARM_LDC_PC_G2:
22304 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22305 case BFD_RELOC_ARM_ALU_SB_G0:
22306 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22307 case BFD_RELOC_ARM_ALU_SB_G1:
22308 case BFD_RELOC_ARM_ALU_SB_G2:
22309 case BFD_RELOC_ARM_LDR_SB_G0:
22310 case BFD_RELOC_ARM_LDR_SB_G1:
22311 case BFD_RELOC_ARM_LDR_SB_G2:
22312 case BFD_RELOC_ARM_LDRS_SB_G0:
22313 case BFD_RELOC_ARM_LDRS_SB_G1:
22314 case BFD_RELOC_ARM_LDRS_SB_G2:
22315 case BFD_RELOC_ARM_LDC_SB_G0:
22316 case BFD_RELOC_ARM_LDC_SB_G1:
22317 case BFD_RELOC_ARM_LDC_SB_G2:
22318 case BFD_RELOC_ARM_V4BX:
22319 code = fixp->fx_r_type;
22322 case BFD_RELOC_ARM_TLS_GOTDESC:
22323 case BFD_RELOC_ARM_TLS_GD32:
22324 case BFD_RELOC_ARM_TLS_IE32:
22325 case BFD_RELOC_ARM_TLS_LDM32:
22326 /* BFD will include the symbol's address in the addend.
22327 But we don't want that, so subtract it out again here. */
22328 if (!S_IS_COMMON (fixp->fx_addsy))
22329 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22330 code = fixp->fx_r_type;
22334 case BFD_RELOC_ARM_IMMEDIATE:
22335 as_bad_where (fixp->fx_file, fixp->fx_line,
22336 _("internal relocation (type: IMMEDIATE) not fixed up"));
22339 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22340 as_bad_where (fixp->fx_file, fixp->fx_line,
22341 _("ADRL used for a symbol not defined in the same file"));
22344 case BFD_RELOC_ARM_OFFSET_IMM:
22345 if (section->use_rela_p)
22347 code = fixp->fx_r_type;
22351 if (fixp->fx_addsy != NULL
22352 && !S_IS_DEFINED (fixp->fx_addsy)
22353 && S_IS_LOCAL (fixp->fx_addsy))
22355 as_bad_where (fixp->fx_file, fixp->fx_line,
22356 _("undefined local label `%s'"),
22357 S_GET_NAME (fixp->fx_addsy));
22361 as_bad_where (fixp->fx_file, fixp->fx_line,
22362 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22369 switch (fixp->fx_r_type)
22371 case BFD_RELOC_NONE: type = "NONE"; break;
22372 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22373 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22374 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22375 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22376 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22377 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22378 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22379 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22380 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22381 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22382 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22383 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22384 default: type = _("<unknown>"); break;
22386 as_bad_where (fixp->fx_file, fixp->fx_line,
22387 _("cannot represent %s relocation in this object file format"),
22394 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22396 && fixp->fx_addsy == GOT_symbol)
22398 code = BFD_RELOC_ARM_GOTPC;
22399 reloc->addend = fixp->fx_offset = reloc->address;
22403 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22405 if (reloc->howto == NULL)
22407 as_bad_where (fixp->fx_file, fixp->fx_line,
22408 _("cannot represent %s relocation in this object file format"),
22409 bfd_get_reloc_code_name (code));
22413 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22414 vtable entry to be used in the relocation's section offset. */
22415 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22416 reloc->address = fixp->fx_offset;
22421 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22424 cons_fix_new_arm (fragS * frag,
22429 bfd_reloc_code_real_type type;
22433 FIXME: @@ Should look at CPU word size. */
22437 type = BFD_RELOC_8;
22440 type = BFD_RELOC_16;
22444 type = BFD_RELOC_32;
22447 type = BFD_RELOC_64;
22452 if (exp->X_op == O_secrel)
22454 exp->X_op = O_symbol;
22455 type = BFD_RELOC_32_SECREL;
22459 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22462 #if defined (OBJ_COFF)
22464 arm_validate_fix (fixS * fixP)
22466 /* If the destination of the branch is a defined symbol which does not have
22467 the THUMB_FUNC attribute, then we must be calling a function which has
22468 the (interfacearm) attribute. We look for the Thumb entry point to that
22469 function and change the branch to refer to that function instead. */
22470 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22471 && fixP->fx_addsy != NULL
22472 && S_IS_DEFINED (fixP->fx_addsy)
22473 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22475 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22482 arm_force_relocation (struct fix * fixp)
22484 #if defined (OBJ_COFF) && defined (TE_PE)
22485 if (fixp->fx_r_type == BFD_RELOC_RVA)
22489 /* In case we have a call or a branch to a function in ARM ISA mode from
22490 a thumb function or vice-versa force the relocation. These relocations
22491 are cleared off for some cores that might have blx and simple transformations
22495 switch (fixp->fx_r_type)
22497 case BFD_RELOC_ARM_PCREL_JUMP:
22498 case BFD_RELOC_ARM_PCREL_CALL:
22499 case BFD_RELOC_THUMB_PCREL_BLX:
22500 if (THUMB_IS_FUNC (fixp->fx_addsy))
22504 case BFD_RELOC_ARM_PCREL_BLX:
22505 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22506 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22507 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22508 if (ARM_IS_FUNC (fixp->fx_addsy))
22517 /* Resolve these relocations even if the symbol is extern or weak.
22518 Technically this is probably wrong due to symbol preemption.
22519 In practice these relocations do not have enough range to be useful
22520 at dynamic link time, and some code (e.g. in the Linux kernel)
22521 expects these references to be resolved. */
22522 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22523 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22524 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22525 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22526 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22527 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22528 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22529 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22530 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22531 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22532 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22533 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22534 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22535 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22538 /* Always leave these relocations for the linker. */
22539 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22540 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22541 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22544 /* Always generate relocations against function symbols. */
22545 if (fixp->fx_r_type == BFD_RELOC_32
22547 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22550 return generic_force_reloc (fixp);
22553 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22554 /* Relocations against function names must be left unadjusted,
22555 so that the linker can use this information to generate interworking
22556 stubs. The MIPS version of this function
22557 also prevents relocations that are mips-16 specific, but I do not
22558 know why it does this.
22561 There is one other problem that ought to be addressed here, but
22562 which currently is not: Taking the address of a label (rather
22563 than a function) and then later jumping to that address. Such
22564 addresses also ought to have their bottom bit set (assuming that
22565 they reside in Thumb code), but at the moment they will not. */
22568 arm_fix_adjustable (fixS * fixP)
22570 if (fixP->fx_addsy == NULL)
22573 /* Preserve relocations against symbols with function type. */
22574 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22577 if (THUMB_IS_FUNC (fixP->fx_addsy)
22578 && fixP->fx_subsy == NULL)
22581 /* We need the symbol name for the VTABLE entries. */
22582 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22583 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22586 /* Don't allow symbols to be discarded on GOT related relocs. */
22587 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22588 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22589 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22590 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22591 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22592 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22593 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22594 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22595 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22596 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22597 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22598 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22599 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22600 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22603 /* Similarly for group relocations. */
22604 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22605 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22606 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22609 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22610 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22611 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22612 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22613 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22614 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22615 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22616 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22617 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22622 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22627 elf32_arm_target_format (void)
22630 return (target_big_endian
22631 ? "elf32-bigarm-symbian"
22632 : "elf32-littlearm-symbian");
22633 #elif defined (TE_VXWORKS)
22634 return (target_big_endian
22635 ? "elf32-bigarm-vxworks"
22636 : "elf32-littlearm-vxworks");
22637 #elif defined (TE_NACL)
22638 return (target_big_endian
22639 ? "elf32-bigarm-nacl"
22640 : "elf32-littlearm-nacl");
22642 if (target_big_endian)
22643 return "elf32-bigarm";
22645 return "elf32-littlearm";
22650 armelf_frob_symbol (symbolS * symp,
22653 elf_frob_symbol (symp, puntp);
22657 /* MD interface: Finalization. */
22662 literal_pool * pool;
22664 /* Ensure that all the IT blocks are properly closed. */
22665 check_it_blocks_finished ();
22667 for (pool = list_of_pools; pool; pool = pool->next)
22669 /* Put it at the end of the relevant section. */
22670 subseg_set (pool->section, pool->sub_section);
22672 arm_elf_change_section ();
22679 /* Remove any excess mapping symbols generated for alignment frags in
22680 SEC. We may have created a mapping symbol before a zero byte
22681 alignment; remove it if there's a mapping symbol after the
22684 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22685 void *dummy ATTRIBUTE_UNUSED)
22687 segment_info_type *seginfo = seg_info (sec);
22690 if (seginfo == NULL || seginfo->frchainP == NULL)
22693 for (fragp = seginfo->frchainP->frch_root;
22695 fragp = fragp->fr_next)
22697 symbolS *sym = fragp->tc_frag_data.last_map;
22698 fragS *next = fragp->fr_next;
22700 /* Variable-sized frags have been converted to fixed size by
22701 this point. But if this was variable-sized to start with,
22702 there will be a fixed-size frag after it. So don't handle
22704 if (sym == NULL || next == NULL)
22707 if (S_GET_VALUE (sym) < next->fr_address)
22708 /* Not at the end of this frag. */
22710 know (S_GET_VALUE (sym) == next->fr_address);
22714 if (next->tc_frag_data.first_map != NULL)
22716 /* Next frag starts with a mapping symbol. Discard this
22718 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22722 if (next->fr_next == NULL)
22724 /* This mapping symbol is at the end of the section. Discard
22726 know (next->fr_fix == 0 && next->fr_var == 0);
22727 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22731 /* As long as we have empty frags without any mapping symbols,
22733 /* If the next frag is non-empty and does not start with a
22734 mapping symbol, then this mapping symbol is required. */
22735 if (next->fr_address != next->fr_next->fr_address)
22738 next = next->fr_next;
22740 while (next != NULL);
22745 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22749 arm_adjust_symtab (void)
22754 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22756 if (ARM_IS_THUMB (sym))
22758 if (THUMB_IS_FUNC (sym))
22760 /* Mark the symbol as a Thumb function. */
22761 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22762 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22763 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22765 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22766 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22768 as_bad (_("%s: unexpected function type: %d"),
22769 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22771 else switch (S_GET_STORAGE_CLASS (sym))
22774 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22777 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22780 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22788 if (ARM_IS_INTERWORK (sym))
22789 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22796 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22798 if (ARM_IS_THUMB (sym))
22800 elf_symbol_type * elf_sym;
22802 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22803 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22805 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22806 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22808 /* If it's a .thumb_func, declare it as so,
22809 otherwise tag label as .code 16. */
22810 if (THUMB_IS_FUNC (sym))
22811 elf_sym->internal_elf_sym.st_target_internal
22812 = ST_BRANCH_TO_THUMB;
22813 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22814 elf_sym->internal_elf_sym.st_info =
22815 ELF_ST_INFO (bind, STT_ARM_16BIT);
22820 /* Remove any overlapping mapping symbols generated by alignment frags. */
22821 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22822 /* Now do generic ELF adjustments. */
22823 elf_adjust_symtab ();
22827 /* MD interface: Initialization. */
22830 set_constant_flonums (void)
22834 for (i = 0; i < NUM_FLOAT_VALS; i++)
22835 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22839 /* Auto-select Thumb mode if it's the only available instruction set for the
22840 given architecture. */
22843 autoselect_thumb_from_cpu_variant (void)
22845 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22846 opcode_select (16);
22855 if ( (arm_ops_hsh = hash_new ()) == NULL
22856 || (arm_cond_hsh = hash_new ()) == NULL
22857 || (arm_shift_hsh = hash_new ()) == NULL
22858 || (arm_psr_hsh = hash_new ()) == NULL
22859 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22860 || (arm_reg_hsh = hash_new ()) == NULL
22861 || (arm_reloc_hsh = hash_new ()) == NULL
22862 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22863 as_fatal (_("virtual memory exhausted"));
22865 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22866 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22867 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22868 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22869 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22870 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22871 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22872 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22873 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22874 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22875 (void *) (v7m_psrs + i));
22876 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22877 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22879 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22881 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22882 (void *) (barrier_opt_names + i));
22884 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
22886 struct reloc_entry * entry = reloc_names + i;
22888 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
22889 /* This makes encode_branch() use the EABI versions of this relocation. */
22890 entry->reloc = BFD_RELOC_UNUSED;
22892 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
22896 set_constant_flonums ();
22898 /* Set the cpu variant based on the command-line options. We prefer
22899 -mcpu= over -march= if both are set (as for GCC); and we prefer
22900 -mfpu= over any other way of setting the floating point unit.
22901 Use of legacy options with new options are faulted. */
22904 if (mcpu_cpu_opt || march_cpu_opt)
22905 as_bad (_("use of old and new-style options to set CPU type"));
22907 mcpu_cpu_opt = legacy_cpu;
22909 else if (!mcpu_cpu_opt)
22910 mcpu_cpu_opt = march_cpu_opt;
22915 as_bad (_("use of old and new-style options to set FPU type"));
22917 mfpu_opt = legacy_fpu;
22919 else if (!mfpu_opt)
22921 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22922 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22923 /* Some environments specify a default FPU. If they don't, infer it
22924 from the processor. */
22926 mfpu_opt = mcpu_fpu_opt;
22928 mfpu_opt = march_fpu_opt;
22930 mfpu_opt = &fpu_default;
22936 if (mcpu_cpu_opt != NULL)
22937 mfpu_opt = &fpu_default;
22938 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22939 mfpu_opt = &fpu_arch_vfp_v2;
22941 mfpu_opt = &fpu_arch_fpa;
22947 mcpu_cpu_opt = &cpu_default;
22948 selected_cpu = cpu_default;
22952 selected_cpu = *mcpu_cpu_opt;
22954 mcpu_cpu_opt = &arm_arch_any;
22957 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22959 autoselect_thumb_from_cpu_variant ();
22961 arm_arch_used = thumb_arch_used = arm_arch_none;
22963 #if defined OBJ_COFF || defined OBJ_ELF
22965 unsigned int flags = 0;
22967 #if defined OBJ_ELF
22968 flags = meabi_flags;
22970 switch (meabi_flags)
22972 case EF_ARM_EABI_UNKNOWN:
22974 /* Set the flags in the private structure. */
22975 if (uses_apcs_26) flags |= F_APCS26;
22976 if (support_interwork) flags |= F_INTERWORK;
22977 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22978 if (pic_code) flags |= F_PIC;
22979 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22980 flags |= F_SOFT_FLOAT;
22982 switch (mfloat_abi_opt)
22984 case ARM_FLOAT_ABI_SOFT:
22985 case ARM_FLOAT_ABI_SOFTFP:
22986 flags |= F_SOFT_FLOAT;
22989 case ARM_FLOAT_ABI_HARD:
22990 if (flags & F_SOFT_FLOAT)
22991 as_bad (_("hard-float conflicts with specified fpu"));
22995 /* Using pure-endian doubles (even if soft-float). */
22996 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22997 flags |= F_VFP_FLOAT;
22999 #if defined OBJ_ELF
23000 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
23001 flags |= EF_ARM_MAVERICK_FLOAT;
23004 case EF_ARM_EABI_VER4:
23005 case EF_ARM_EABI_VER5:
23006 /* No additional flags to set. */
23013 bfd_set_private_flags (stdoutput, flags);
23015 /* We have run out flags in the COFF header to encode the
23016 status of ATPCS support, so instead we create a dummy,
23017 empty, debug section called .arm.atpcs. */
23022 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23026 bfd_set_section_flags
23027 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23028 bfd_set_section_size (stdoutput, sec, 0);
23029 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23035 /* Record the CPU type as well. */
23036 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23037 mach = bfd_mach_arm_iWMMXt2;
23038 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
23039 mach = bfd_mach_arm_iWMMXt;
23040 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
23041 mach = bfd_mach_arm_XScale;
23042 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
23043 mach = bfd_mach_arm_ep9312;
23044 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
23045 mach = bfd_mach_arm_5TE;
23046 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
23048 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23049 mach = bfd_mach_arm_5T;
23051 mach = bfd_mach_arm_5;
23053 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
23055 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23056 mach = bfd_mach_arm_4T;
23058 mach = bfd_mach_arm_4;
23060 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
23061 mach = bfd_mach_arm_3M;
23062 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23063 mach = bfd_mach_arm_3;
23064 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23065 mach = bfd_mach_arm_2a;
23066 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23067 mach = bfd_mach_arm_2;
23069 mach = bfd_mach_arm_unknown;
23071 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23074 /* Command line processing. */
23077 Invocation line includes a switch not recognized by the base assembler.
23078 See if it's a processor-specific option.
23080 This routine is somewhat complicated by the need for backwards
23081 compatibility (since older releases of gcc can't be changed).
23082 The new options try to make the interface as compatible as
23085 New options (supported) are:
23087 -mcpu=<cpu name> Assemble for selected processor
23088 -march=<architecture name> Assemble for selected architecture
23089 -mfpu=<fpu architecture> Assemble for selected FPU.
23090 -EB/-mbig-endian Big-endian
23091 -EL/-mlittle-endian Little-endian
23092 -k Generate PIC code
23093 -mthumb Start in Thumb mode
23094 -mthumb-interwork Code supports ARM/Thumb interworking
23096 -m[no-]warn-deprecated Warn about deprecated features
23098 For now we will also provide support for:
23100 -mapcs-32 32-bit Program counter
23101 -mapcs-26 26-bit Program counter
23102 -macps-float Floats passed in FP registers
23103 -mapcs-reentrant Reentrant code
23105 (sometime these will probably be replaced with -mapcs=<list of options>
23106 and -matpcs=<list of options>)
23108 The remaining options are only supported for back-wards compatibility.
23109 Cpu variants, the arm part is optional:
23110 -m[arm]1 Currently not supported.
23111 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23112 -m[arm]3 Arm 3 processor
23113 -m[arm]6[xx], Arm 6 processors
23114 -m[arm]7[xx][t][[d]m] Arm 7 processors
23115 -m[arm]8[10] Arm 8 processors
23116 -m[arm]9[20][tdmi] Arm 9 processors
23117 -mstrongarm[110[0]] StrongARM processors
23118 -mxscale XScale processors
23119 -m[arm]v[2345[t[e]]] Arm architectures
23120 -mall All (except the ARM1)
23122 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23123 -mfpe-old (No float load/store multiples)
23124 -mvfpxd VFP Single precision
23126 -mno-fpu Disable all floating point instructions
23128 The following CPU names are recognized:
23129 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23130 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23131 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23132 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23133 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23134 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23135 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23139 const char * md_shortopts = "m:k";
23141 #ifdef ARM_BI_ENDIAN
23142 #define OPTION_EB (OPTION_MD_BASE + 0)
23143 #define OPTION_EL (OPTION_MD_BASE + 1)
23145 #if TARGET_BYTES_BIG_ENDIAN
23146 #define OPTION_EB (OPTION_MD_BASE + 0)
23148 #define OPTION_EL (OPTION_MD_BASE + 1)
23151 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23153 struct option md_longopts[] =
23156 {"EB", no_argument, NULL, OPTION_EB},
23159 {"EL", no_argument, NULL, OPTION_EL},
23161 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
23162 {NULL, no_argument, NULL, 0}
23165 size_t md_longopts_size = sizeof (md_longopts);
23167 struct arm_option_table
23169 char *option; /* Option name to match. */
23170 char *help; /* Help information. */
23171 int *var; /* Variable to change. */
23172 int value; /* What to change it to. */
23173 char *deprecated; /* If non-null, print this message. */
23176 struct arm_option_table arm_opts[] =
23178 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23179 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23180 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23181 &support_interwork, 1, NULL},
23182 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23183 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23184 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23186 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23187 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23188 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23189 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23192 /* These are recognized by the assembler, but have no affect on code. */
23193 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23194 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
23196 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23197 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23198 &warn_on_deprecated, 0, NULL},
23199 {NULL, NULL, NULL, 0, NULL}
23202 struct arm_legacy_option_table
23204 char *option; /* Option name to match. */
23205 const arm_feature_set **var; /* Variable to change. */
23206 const arm_feature_set value; /* What to change it to. */
23207 char *deprecated; /* If non-null, print this message. */
23210 const struct arm_legacy_option_table arm_legacy_opts[] =
23212 /* DON'T add any new processors to this list -- we want the whole list
23213 to go away... Add them to the processors table instead. */
23214 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23215 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23216 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23217 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23218 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23219 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23220 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23221 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23222 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23223 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23224 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23225 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23226 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23227 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23228 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23229 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23230 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23231 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23232 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23233 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23234 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23235 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23236 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23237 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23238 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23239 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23240 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23241 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23242 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23243 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23244 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23245 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23246 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23247 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23248 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23249 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23250 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23251 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23252 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23253 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23254 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23255 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23256 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23257 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23258 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23259 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23260 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23261 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23262 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23263 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23264 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23265 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23266 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23267 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23268 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23269 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23270 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23271 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23272 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23273 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23274 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23275 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23276 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23277 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23278 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23279 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23280 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23281 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23282 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23283 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23284 N_("use -mcpu=strongarm110")},
23285 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23286 N_("use -mcpu=strongarm1100")},
23287 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23288 N_("use -mcpu=strongarm1110")},
23289 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23290 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23291 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23293 /* Architecture variants -- don't add any more to this list either. */
23294 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23295 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23296 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23297 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23298 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23299 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23300 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23301 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23302 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23303 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23304 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23305 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23306 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23307 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23308 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23309 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23310 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23311 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23313 /* Floating point variants -- don't add any more to this list either. */
23314 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23315 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23316 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23317 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23318 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23320 {NULL, NULL, ARM_ARCH_NONE, NULL}
23323 struct arm_cpu_option_table
23327 const arm_feature_set value;
23328 /* For some CPUs we assume an FPU unless the user explicitly sets
23330 const arm_feature_set default_fpu;
23331 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23333 const char *canonical_name;
23336 /* This list should, at a minimum, contain all the cpu names
23337 recognized by GCC. */
23338 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23339 static const struct arm_cpu_option_table arm_cpus[] =
23341 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23342 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23343 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23344 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23345 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23346 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23347 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23348 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23349 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23350 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23351 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23352 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23353 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23354 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23355 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23356 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23357 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23358 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23359 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23360 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23361 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23362 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23363 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23364 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23365 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23366 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23367 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23368 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23369 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23370 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23371 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23372 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23373 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23374 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23375 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23376 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23377 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23378 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23379 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23380 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23381 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23382 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23383 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23384 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23385 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23386 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23387 /* For V5 or later processors we default to using VFP; but the user
23388 should really set the FPU type explicitly. */
23389 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23390 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23391 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23392 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23393 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23394 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23395 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23396 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23397 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23398 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23399 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23400 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23401 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23402 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23403 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23404 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23405 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23406 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23407 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23408 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23410 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23411 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23412 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23413 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23414 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23415 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23416 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23417 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23418 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23420 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23421 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23422 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23423 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23424 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23425 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23426 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23427 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23428 FPU_NONE, "Cortex-A5"),
23429 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23430 FPU_ARCH_NEON_VFP_V4,
23432 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23433 ARM_FEATURE (0, FPU_VFP_V3
23434 | FPU_NEON_EXT_V1),
23436 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23437 ARM_FEATURE (0, FPU_VFP_V3
23438 | FPU_NEON_EXT_V1),
23440 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23441 FPU_ARCH_NEON_VFP_V4,
23443 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23444 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23446 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23447 FPU_NONE, "Cortex-R5"),
23448 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23449 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23450 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23451 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23452 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
23453 /* ??? XSCALE is really an architecture. */
23454 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23455 /* ??? iwmmxt is not a processor. */
23456 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23457 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23458 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23460 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23463 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23467 struct arm_arch_option_table
23471 const arm_feature_set value;
23472 const arm_feature_set default_fpu;
23475 /* This list should, at a minimum, contain all the architecture names
23476 recognized by GCC. */
23477 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23478 static const struct arm_arch_option_table arm_archs[] =
23480 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23481 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23482 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23483 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
23484 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
23485 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
23486 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
23487 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
23488 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
23489 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
23490 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
23491 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
23492 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
23493 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
23494 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
23495 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
23496 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
23497 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
23498 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
23499 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
23500 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
23501 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
23502 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
23503 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
23504 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
23505 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
23506 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
23507 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
23508 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
23509 /* The official spelling of the ARMv7 profile variants is the dashed form.
23510 Accept the non-dashed form for compatibility with old toolchains. */
23511 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23512 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23513 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23514 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23515 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23516 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23517 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
23518 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
23519 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
23520 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
23521 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
23522 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23524 #undef ARM_ARCH_OPT
23526 /* ISA extensions in the co-processor and main instruction set space. */
23527 struct arm_option_extension_value_table
23531 const arm_feature_set value;
23532 const arm_feature_set allowed_archs;
23535 /* The following table must be in alphabetical order with a NULL last entry.
23537 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23538 static const struct arm_option_extension_value_table arm_extensions[] =
23540 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23541 ARM_FEATURE (ARM_EXT_V8, 0)),
23542 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
23543 ARM_FEATURE (ARM_EXT_V8, 0)),
23544 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23545 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23546 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
23547 ARM_EXT_OPT ("iwmmxt2",
23548 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
23549 ARM_EXT_OPT ("maverick",
23550 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
23551 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
23552 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23553 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
23554 ARM_FEATURE (ARM_EXT_V8, 0)),
23555 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
23556 ARM_FEATURE (ARM_EXT_V6M, 0)),
23557 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23558 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
23559 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
23561 ARM_FEATURE (ARM_EXT_V7A, 0)),
23562 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
23563 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23567 /* ISA floating-point and Advanced SIMD extensions. */
23568 struct arm_option_fpu_value_table
23571 const arm_feature_set value;
23574 /* This list should, at a minimum, contain all the fpu names
23575 recognized by GCC. */
23576 static const struct arm_option_fpu_value_table arm_fpus[] =
23578 {"softfpa", FPU_NONE},
23579 {"fpe", FPU_ARCH_FPE},
23580 {"fpe2", FPU_ARCH_FPE},
23581 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23582 {"fpa", FPU_ARCH_FPA},
23583 {"fpa10", FPU_ARCH_FPA},
23584 {"fpa11", FPU_ARCH_FPA},
23585 {"arm7500fe", FPU_ARCH_FPA},
23586 {"softvfp", FPU_ARCH_VFP},
23587 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23588 {"vfp", FPU_ARCH_VFP_V2},
23589 {"vfp9", FPU_ARCH_VFP_V2},
23590 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23591 {"vfp10", FPU_ARCH_VFP_V2},
23592 {"vfp10-r0", FPU_ARCH_VFP_V1},
23593 {"vfpxd", FPU_ARCH_VFP_V1xD},
23594 {"vfpv2", FPU_ARCH_VFP_V2},
23595 {"vfpv3", FPU_ARCH_VFP_V3},
23596 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23597 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23598 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23599 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23600 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23601 {"arm1020t", FPU_ARCH_VFP_V1},
23602 {"arm1020e", FPU_ARCH_VFP_V2},
23603 {"arm1136jfs", FPU_ARCH_VFP_V2},
23604 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23605 {"maverick", FPU_ARCH_MAVERICK},
23606 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23607 {"neon-fp16", FPU_ARCH_NEON_FP16},
23608 {"vfpv4", FPU_ARCH_VFP_V4},
23609 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23610 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23611 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23612 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
23613 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
23614 {"crypto-neon-fp-armv8",
23615 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
23616 {NULL, ARM_ARCH_NONE}
23619 struct arm_option_value_table
23625 static const struct arm_option_value_table arm_float_abis[] =
23627 {"hard", ARM_FLOAT_ABI_HARD},
23628 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23629 {"soft", ARM_FLOAT_ABI_SOFT},
23634 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23635 static const struct arm_option_value_table arm_eabis[] =
23637 {"gnu", EF_ARM_EABI_UNKNOWN},
23638 {"4", EF_ARM_EABI_VER4},
23639 {"5", EF_ARM_EABI_VER5},
23644 struct arm_long_option_table
23646 char * option; /* Substring to match. */
23647 char * help; /* Help information. */
23648 int (* func) (char * subopt); /* Function to decode sub-option. */
23649 char * deprecated; /* If non-null, print this message. */
23653 arm_parse_extension (char *str, const arm_feature_set **opt_p)
23655 arm_feature_set *ext_set = (arm_feature_set *)
23656 xmalloc (sizeof (arm_feature_set));
23658 /* We insist on extensions being specified in alphabetical order, and with
23659 extensions being added before being removed. We achieve this by having
23660 the global ARM_EXTENSIONS table in alphabetical order, and using the
23661 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23662 or removing it (0) and only allowing it to change in the order
23664 const struct arm_option_extension_value_table * opt = NULL;
23665 int adding_value = -1;
23667 /* Copy the feature set, so that we can modify it. */
23668 *ext_set = **opt_p;
23671 while (str != NULL && *str != 0)
23678 as_bad (_("invalid architectural extension"));
23683 ext = strchr (str, '+');
23688 len = strlen (str);
23690 if (len >= 2 && strncmp (str, "no", 2) == 0)
23692 if (adding_value != 0)
23695 opt = arm_extensions;
23703 if (adding_value == -1)
23706 opt = arm_extensions;
23708 else if (adding_value != 1)
23710 as_bad (_("must specify extensions to add before specifying "
23711 "those to remove"));
23718 as_bad (_("missing architectural extension"));
23722 gas_assert (adding_value != -1);
23723 gas_assert (opt != NULL);
23725 /* Scan over the options table trying to find an exact match. */
23726 for (; opt->name != NULL; opt++)
23727 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23729 /* Check we can apply the extension to this architecture. */
23730 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23732 as_bad (_("extension does not apply to the base architecture"));
23736 /* Add or remove the extension. */
23738 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23740 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23745 if (opt->name == NULL)
23747 /* Did we fail to find an extension because it wasn't specified in
23748 alphabetical order, or because it does not exist? */
23750 for (opt = arm_extensions; opt->name != NULL; opt++)
23751 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23754 if (opt->name == NULL)
23755 as_bad (_("unknown architectural extension `%s'"), str);
23757 as_bad (_("architectural extensions must be specified in "
23758 "alphabetical order"));
23764 /* We should skip the extension we've just matched the next time
23776 arm_parse_cpu (char *str)
23778 const struct arm_cpu_option_table *opt;
23779 char *ext = strchr (str, '+');
23785 len = strlen (str);
23789 as_bad (_("missing cpu name `%s'"), str);
23793 for (opt = arm_cpus; opt->name != NULL; opt++)
23794 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23796 mcpu_cpu_opt = &opt->value;
23797 mcpu_fpu_opt = &opt->default_fpu;
23798 if (opt->canonical_name)
23799 strcpy (selected_cpu_name, opt->canonical_name);
23804 for (i = 0; i < len; i++)
23805 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23806 selected_cpu_name[i] = 0;
23810 return arm_parse_extension (ext, &mcpu_cpu_opt);
23815 as_bad (_("unknown cpu `%s'"), str);
23820 arm_parse_arch (char *str)
23822 const struct arm_arch_option_table *opt;
23823 char *ext = strchr (str, '+');
23829 len = strlen (str);
23833 as_bad (_("missing architecture name `%s'"), str);
23837 for (opt = arm_archs; opt->name != NULL; opt++)
23838 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23840 march_cpu_opt = &opt->value;
23841 march_fpu_opt = &opt->default_fpu;
23842 strcpy (selected_cpu_name, opt->name);
23845 return arm_parse_extension (ext, &march_cpu_opt);
23850 as_bad (_("unknown architecture `%s'\n"), str);
23855 arm_parse_fpu (char * str)
23857 const struct arm_option_fpu_value_table * opt;
23859 for (opt = arm_fpus; opt->name != NULL; opt++)
23860 if (streq (opt->name, str))
23862 mfpu_opt = &opt->value;
23866 as_bad (_("unknown floating point format `%s'\n"), str);
23871 arm_parse_float_abi (char * str)
23873 const struct arm_option_value_table * opt;
23875 for (opt = arm_float_abis; opt->name != NULL; opt++)
23876 if (streq (opt->name, str))
23878 mfloat_abi_opt = opt->value;
23882 as_bad (_("unknown floating point abi `%s'\n"), str);
23888 arm_parse_eabi (char * str)
23890 const struct arm_option_value_table *opt;
23892 for (opt = arm_eabis; opt->name != NULL; opt++)
23893 if (streq (opt->name, str))
23895 meabi_flags = opt->value;
23898 as_bad (_("unknown EABI `%s'\n"), str);
23904 arm_parse_it_mode (char * str)
23906 bfd_boolean ret = TRUE;
23908 if (streq ("arm", str))
23909 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23910 else if (streq ("thumb", str))
23911 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23912 else if (streq ("always", str))
23913 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23914 else if (streq ("never", str))
23915 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23918 as_bad (_("unknown implicit IT mode `%s', should be "\
23919 "arm, thumb, always, or never."), str);
23926 struct arm_long_option_table arm_long_opts[] =
23928 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23929 arm_parse_cpu, NULL},
23930 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23931 arm_parse_arch, NULL},
23932 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23933 arm_parse_fpu, NULL},
23934 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23935 arm_parse_float_abi, NULL},
23937 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23938 arm_parse_eabi, NULL},
23940 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23941 arm_parse_it_mode, NULL},
23942 {NULL, NULL, 0, NULL}
23946 md_parse_option (int c, char * arg)
23948 struct arm_option_table *opt;
23949 const struct arm_legacy_option_table *fopt;
23950 struct arm_long_option_table *lopt;
23956 target_big_endian = 1;
23962 target_big_endian = 0;
23966 case OPTION_FIX_V4BX:
23971 /* Listing option. Just ignore these, we don't support additional
23976 for (opt = arm_opts; opt->option != NULL; opt++)
23978 if (c == opt->option[0]
23979 && ((arg == NULL && opt->option[1] == 0)
23980 || streq (arg, opt->option + 1)))
23982 /* If the option is deprecated, tell the user. */
23983 if (warn_on_deprecated && opt->deprecated != NULL)
23984 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23985 arg ? arg : "", _(opt->deprecated));
23987 if (opt->var != NULL)
23988 *opt->var = opt->value;
23994 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23996 if (c == fopt->option[0]
23997 && ((arg == NULL && fopt->option[1] == 0)
23998 || streq (arg, fopt->option + 1)))
24000 /* If the option is deprecated, tell the user. */
24001 if (warn_on_deprecated && fopt->deprecated != NULL)
24002 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24003 arg ? arg : "", _(fopt->deprecated));
24005 if (fopt->var != NULL)
24006 *fopt->var = &fopt->value;
24012 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24014 /* These options are expected to have an argument. */
24015 if (c == lopt->option[0]
24017 && strncmp (arg, lopt->option + 1,
24018 strlen (lopt->option + 1)) == 0)
24020 /* If the option is deprecated, tell the user. */
24021 if (warn_on_deprecated && lopt->deprecated != NULL)
24022 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24023 _(lopt->deprecated));
24025 /* Call the sup-option parser. */
24026 return lopt->func (arg + strlen (lopt->option) - 1);
24037 md_show_usage (FILE * fp)
24039 struct arm_option_table *opt;
24040 struct arm_long_option_table *lopt;
24042 fprintf (fp, _(" ARM-specific assembler options:\n"));
24044 for (opt = arm_opts; opt->option != NULL; opt++)
24045 if (opt->help != NULL)
24046 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
24048 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24049 if (lopt->help != NULL)
24050 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
24054 -EB assemble code for a big-endian cpu\n"));
24059 -EL assemble code for a little-endian cpu\n"));
24063 --fix-v4bx Allow BX in ARMv4 code\n"));
24071 arm_feature_set flags;
24072 } cpu_arch_ver_table;
24074 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24075 least features first. */
24076 static const cpu_arch_ver_table cpu_arch_ver[] =
24082 {4, ARM_ARCH_V5TE},
24083 {5, ARM_ARCH_V5TEJ},
24087 {11, ARM_ARCH_V6M},
24088 {12, ARM_ARCH_V6SM},
24089 {8, ARM_ARCH_V6T2},
24090 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
24091 {10, ARM_ARCH_V7R},
24092 {10, ARM_ARCH_V7M},
24093 {14, ARM_ARCH_V8A},
24097 /* Set an attribute if it has not already been set by the user. */
24099 aeabi_set_attribute_int (int tag, int value)
24102 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24103 || !attributes_set_explicitly[tag])
24104 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24108 aeabi_set_attribute_string (int tag, const char *value)
24111 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24112 || !attributes_set_explicitly[tag])
24113 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24116 /* Set the public EABI object attributes. */
24118 aeabi_set_public_attributes (void)
24123 int fp16_optional = 0;
24124 arm_feature_set flags;
24125 arm_feature_set tmp;
24126 const cpu_arch_ver_table *p;
24128 /* Choose the architecture based on the capabilities of the requested cpu
24129 (if any) and/or the instructions actually used. */
24130 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24131 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24132 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
24134 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24135 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24137 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24138 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24140 /* Allow the user to override the reported architecture. */
24143 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24144 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24147 /* We need to make sure that the attributes do not identify us as v6S-M
24148 when the only v6S-M feature in use is the Operating System Extensions. */
24149 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24150 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
24151 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
24155 for (p = cpu_arch_ver; p->val; p++)
24157 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24160 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24164 /* The table lookup above finds the last architecture to contribute
24165 a new feature. Unfortunately, Tag13 is a subset of the union of
24166 v6T2 and v7-M, so it is never seen as contributing a new feature.
24167 We can not search for the last entry which is entirely used,
24168 because if no CPU is specified we build up only those flags
24169 actually used. Perhaps we should separate out the specified
24170 and implicit cases. Avoid taking this path for -march=all by
24171 checking for contradictory v7-A / v7-M features. */
24173 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24174 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24175 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24178 /* Tag_CPU_name. */
24179 if (selected_cpu_name[0])
24183 q = selected_cpu_name;
24184 if (strncmp (q, "armv", 4) == 0)
24189 for (i = 0; q[i]; i++)
24190 q[i] = TOUPPER (q[i]);
24192 aeabi_set_attribute_string (Tag_CPU_name, q);
24195 /* Tag_CPU_arch. */
24196 aeabi_set_attribute_int (Tag_CPU_arch, arch);
24198 /* Tag_CPU_arch_profile. */
24199 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
24201 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
24203 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
24208 if (profile != '\0')
24209 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
24211 /* Tag_ARM_ISA_use. */
24212 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24214 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
24216 /* Tag_THUMB_ISA_use. */
24217 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24219 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24220 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
24222 /* Tag_VFP_arch. */
24223 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24224 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24225 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
24226 aeabi_set_attribute_int (Tag_VFP_arch,
24227 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24229 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
24232 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24234 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
24236 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24239 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24240 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24241 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24242 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24243 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24245 /* Tag_ABI_HardFP_use. */
24246 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24247 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24248 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24250 /* Tag_WMMX_arch. */
24251 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24252 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24253 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24254 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24256 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24257 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24258 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24259 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24261 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24263 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24267 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24272 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24273 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24274 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24278 We set Tag_DIV_use to two when integer divide instructions have been used
24279 in ARM state, or when Thumb integer divide instructions have been used,
24280 but we have no architecture profile set, nor have we any ARM instructions.
24282 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24285 For new architectures we will have to check these tests. */
24286 gas_assert (arch <= TAG_CPU_ARCH_V8);
24287 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24288 aeabi_set_attribute_int (Tag_DIV_use, 0);
24289 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24290 || (profile == '\0'
24291 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24292 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24293 aeabi_set_attribute_int (Tag_DIV_use, 2);
24295 /* Tag_MP_extension_use. */
24296 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24297 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24299 /* Tag Virtualization_use. */
24300 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24302 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24305 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24308 /* Add the default contents for the .ARM.attributes section. */
24312 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24315 aeabi_set_public_attributes ();
24317 #endif /* OBJ_ELF */
24320 /* Parse a .cpu directive. */
24323 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24325 const struct arm_cpu_option_table *opt;
24329 name = input_line_pointer;
24330 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24331 input_line_pointer++;
24332 saved_char = *input_line_pointer;
24333 *input_line_pointer = 0;
24335 /* Skip the first "all" entry. */
24336 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24337 if (streq (opt->name, name))
24339 mcpu_cpu_opt = &opt->value;
24340 selected_cpu = opt->value;
24341 if (opt->canonical_name)
24342 strcpy (selected_cpu_name, opt->canonical_name);
24346 for (i = 0; opt->name[i]; i++)
24347 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24349 selected_cpu_name[i] = 0;
24351 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24352 *input_line_pointer = saved_char;
24353 demand_empty_rest_of_line ();
24356 as_bad (_("unknown cpu `%s'"), name);
24357 *input_line_pointer = saved_char;
24358 ignore_rest_of_line ();
24362 /* Parse a .arch directive. */
24365 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24367 const struct arm_arch_option_table *opt;
24371 name = input_line_pointer;
24372 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24373 input_line_pointer++;
24374 saved_char = *input_line_pointer;
24375 *input_line_pointer = 0;
24377 /* Skip the first "all" entry. */
24378 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24379 if (streq (opt->name, name))
24381 mcpu_cpu_opt = &opt->value;
24382 selected_cpu = opt->value;
24383 strcpy (selected_cpu_name, opt->name);
24384 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24385 *input_line_pointer = saved_char;
24386 demand_empty_rest_of_line ();
24390 as_bad (_("unknown architecture `%s'\n"), name);
24391 *input_line_pointer = saved_char;
24392 ignore_rest_of_line ();
24396 /* Parse a .object_arch directive. */
24399 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24401 const struct arm_arch_option_table *opt;
24405 name = input_line_pointer;
24406 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24407 input_line_pointer++;
24408 saved_char = *input_line_pointer;
24409 *input_line_pointer = 0;
24411 /* Skip the first "all" entry. */
24412 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24413 if (streq (opt->name, name))
24415 object_arch = &opt->value;
24416 *input_line_pointer = saved_char;
24417 demand_empty_rest_of_line ();
24421 as_bad (_("unknown architecture `%s'\n"), name);
24422 *input_line_pointer = saved_char;
24423 ignore_rest_of_line ();
24426 /* Parse a .arch_extension directive. */
24429 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24431 const struct arm_option_extension_value_table *opt;
24434 int adding_value = 1;
24436 name = input_line_pointer;
24437 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24438 input_line_pointer++;
24439 saved_char = *input_line_pointer;
24440 *input_line_pointer = 0;
24442 if (strlen (name) >= 2
24443 && strncmp (name, "no", 2) == 0)
24449 for (opt = arm_extensions; opt->name != NULL; opt++)
24450 if (streq (opt->name, name))
24452 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
24454 as_bad (_("architectural extension `%s' is not allowed for the "
24455 "current base architecture"), name);
24460 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
24462 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
24464 mcpu_cpu_opt = &selected_cpu;
24465 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24466 *input_line_pointer = saved_char;
24467 demand_empty_rest_of_line ();
24471 if (opt->name == NULL)
24472 as_bad (_("unknown architecture `%s'\n"), name);
24474 *input_line_pointer = saved_char;
24475 ignore_rest_of_line ();
24478 /* Parse a .fpu directive. */
24481 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
24483 const struct arm_option_fpu_value_table *opt;
24487 name = input_line_pointer;
24488 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24489 input_line_pointer++;
24490 saved_char = *input_line_pointer;
24491 *input_line_pointer = 0;
24493 for (opt = arm_fpus; opt->name != NULL; opt++)
24494 if (streq (opt->name, name))
24496 mfpu_opt = &opt->value;
24497 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24498 *input_line_pointer = saved_char;
24499 demand_empty_rest_of_line ();
24503 as_bad (_("unknown floating point format `%s'\n"), name);
24504 *input_line_pointer = saved_char;
24505 ignore_rest_of_line ();
24508 /* Copy symbol information. */
24511 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
24513 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
24517 /* Given a symbolic attribute NAME, return the proper integer value.
24518 Returns -1 if the attribute is not known. */
24521 arm_convert_symbolic_attribute (const char *name)
24523 static const struct
24528 attribute_table[] =
24530 /* When you modify this table you should
24531 also modify the list in doc/c-arm.texi. */
24532 #define T(tag) {#tag, tag}
24533 T (Tag_CPU_raw_name),
24536 T (Tag_CPU_arch_profile),
24537 T (Tag_ARM_ISA_use),
24538 T (Tag_THUMB_ISA_use),
24542 T (Tag_Advanced_SIMD_arch),
24543 T (Tag_PCS_config),
24544 T (Tag_ABI_PCS_R9_use),
24545 T (Tag_ABI_PCS_RW_data),
24546 T (Tag_ABI_PCS_RO_data),
24547 T (Tag_ABI_PCS_GOT_use),
24548 T (Tag_ABI_PCS_wchar_t),
24549 T (Tag_ABI_FP_rounding),
24550 T (Tag_ABI_FP_denormal),
24551 T (Tag_ABI_FP_exceptions),
24552 T (Tag_ABI_FP_user_exceptions),
24553 T (Tag_ABI_FP_number_model),
24554 T (Tag_ABI_align_needed),
24555 T (Tag_ABI_align8_needed),
24556 T (Tag_ABI_align_preserved),
24557 T (Tag_ABI_align8_preserved),
24558 T (Tag_ABI_enum_size),
24559 T (Tag_ABI_HardFP_use),
24560 T (Tag_ABI_VFP_args),
24561 T (Tag_ABI_WMMX_args),
24562 T (Tag_ABI_optimization_goals),
24563 T (Tag_ABI_FP_optimization_goals),
24564 T (Tag_compatibility),
24565 T (Tag_CPU_unaligned_access),
24566 T (Tag_FP_HP_extension),
24567 T (Tag_VFP_HP_extension),
24568 T (Tag_ABI_FP_16bit_format),
24569 T (Tag_MPextension_use),
24571 T (Tag_nodefaults),
24572 T (Tag_also_compatible_with),
24573 T (Tag_conformance),
24575 T (Tag_Virtualization_use),
24576 /* We deliberately do not include Tag_MPextension_use_legacy. */
24584 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24585 if (streq (name, attribute_table[i].name))
24586 return attribute_table[i].tag;
24592 /* Apply sym value for relocations only in the case that
24593 they are for local symbols and you have the respective
24594 architectural feature for blx and simple switches. */
24596 arm_apply_sym_value (struct fix * fixP)
24599 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24600 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24602 switch (fixP->fx_r_type)
24604 case BFD_RELOC_ARM_PCREL_BLX:
24605 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24606 if (ARM_IS_FUNC (fixP->fx_addsy))
24610 case BFD_RELOC_ARM_PCREL_CALL:
24611 case BFD_RELOC_THUMB_PCREL_BLX:
24612 if (THUMB_IS_FUNC (fixP->fx_addsy))
24623 #endif /* OBJ_ELF */