1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
201 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
202 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
203 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
204 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
206 static const arm_feature_set arm_arch_any = ARM_ANY;
207 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
209 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
210 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
212 static const arm_feature_set arm_cext_iwmmxt2 =
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
214 static const arm_feature_set arm_cext_iwmmxt =
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
216 static const arm_feature_set arm_cext_xscale =
217 ARM_FEATURE (0, ARM_CEXT_XSCALE);
218 static const arm_feature_set arm_cext_maverick =
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
220 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
221 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
222 static const arm_feature_set fpu_vfp_ext_v1xd =
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
224 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
225 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
226 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
227 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
228 static const arm_feature_set fpu_vfp_ext_d32 =
229 ARM_FEATURE (0, FPU_VFP_EXT_D32);
230 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
233 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
234 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static int mfloat_abi_opt = -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu.core == arm_arch_none.core
248 && selected_cpu.coproc == arm_arch_none.coproc;
253 static int meabi_flags = EABI_DEFAULT;
255 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
258 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
263 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS * GOT_symbol;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode = 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER = 0x00,
286 IMPLICIT_IT_MODE_ARM = 0x01,
287 IMPLICIT_IT_MODE_THUMB = 0x02,
288 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
290 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax = FALSE;
330 enum neon_el_type type;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el[NEON_MAX_TYPE_ELS];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN /* The IT insn has been parsed. */
357 unsigned long instruction;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type;
379 enum it_instruction_type it_insn_type;
385 struct neon_type_el vectype;
386 unsigned present : 1; /* Operand present. */
387 unsigned isreg : 1; /* Operand was a register. */
388 unsigned immisreg : 1; /* .imm field is a second register. */
389 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle : 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc : 1; /* Operand has relocation suffix. */
399 unsigned writeback : 1; /* Operand has trailing ! */
400 unsigned preind : 1; /* Preindexed address. */
401 unsigned postind : 1; /* Postindexed address. */
402 unsigned negative : 1; /* Index register was negated. */
403 unsigned shifted : 1; /* Shift applied to operation. */
404 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name;
444 #define COND_ALWAYS 0xE
448 const char * template_name;
452 struct asm_barrier_opt
454 const char * template_name;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc;
475 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
476 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
481 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined;
492 struct neon_type_el eltype;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin;
533 struct neon_typed_alias * neon;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name;
576 /* Parameters to instruction. */
577 unsigned int operands[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag : 4;
582 /* Basic instruction code. */
583 unsigned int avalue : 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set * avariant;
590 const arm_feature_set * tvariant;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
728 static struct hash_control * arm_ops_hsh;
729 static struct hash_control * arm_cond_hsh;
730 static struct hash_control * arm_shift_hsh;
731 static struct hash_control * arm_psr_hsh;
732 static struct hash_control * arm_v7m_psr_hsh;
733 static struct hash_control * arm_reg_hsh;
734 static struct hash_control * arm_reloc_hsh;
735 static struct hash_control * arm_barrier_opt_hsh;
737 /* Stuff needed to resolve the label ambiguity
746 symbolS * last_label_seen;
747 static int label_is_thumb_function_name = FALSE;
749 /* Literal pool structure. Held on a per-section
750 and per-sub-section basis. */
752 #define MAX_LITERAL_POOL_SIZE 1024
753 typedef struct literal_pool
755 expressionS literals [MAX_LITERAL_POOL_SIZE];
756 unsigned int next_free_entry;
761 struct literal_pool * next;
764 /* Pointer to a linked list of literal pools. */
765 literal_pool * list_of_pools = NULL;
768 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
770 static struct current_it now_it;
774 now_it_compatible (int cond)
776 return (cond & ~1) == (now_it.cc & ~1);
780 conditional_insn (void)
782 return inst.cond != COND_ALWAYS;
785 static int in_it_block (void);
787 static int handle_it_state (void);
789 static void force_automatic_it_block_close (void);
791 static void it_fsm_post_encode (void);
793 #define set_it_insn_type(type) \
796 inst.it_insn_type = type; \
797 if (handle_it_state () == FAIL) \
802 #define set_it_insn_type_nonvoid(type, failret) \
805 inst.it_insn_type = type; \
806 if (handle_it_state () == FAIL) \
811 #define set_it_insn_type_last() \
814 if (inst.cond == COND_ALWAYS) \
815 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
817 set_it_insn_type (INSIDE_IT_LAST_INSN); \
823 /* This array holds the chars that always start a comment. If the
824 pre-processor is disabled, these aren't very useful. */
825 const char comment_chars[] = "@";
827 /* This array holds the chars that only start a comment at the beginning of
828 a line. If the line seems to have the form '# 123 filename'
829 .line and .file directives will appear in the pre-processed output. */
830 /* Note that input_file.c hand checks for '#' at the beginning of the
831 first line of the input file. This is because the compiler outputs
832 #NO_APP at the beginning of its output. */
833 /* Also note that comments like this one will always work. */
834 const char line_comment_chars[] = "#";
836 const char line_separator_chars[] = ";";
838 /* Chars that can be used to separate mant
839 from exp in floating point numbers. */
840 const char EXP_CHARS[] = "eE";
842 /* Chars that mean this number is a floating point constant. */
846 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
848 /* Prefix characters that indicate the start of an immediate
850 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
852 /* Separator character handling. */
854 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
857 skip_past_char (char ** str, char c)
868 #define skip_past_comma(str) skip_past_char (str, ',')
870 /* Arithmetic expressions (possibly involving symbols). */
872 /* Return TRUE if anything in the expression is a bignum. */
875 walk_no_bignums (symbolS * sp)
877 if (symbol_get_value_expression (sp)->X_op == O_big)
880 if (symbol_get_value_expression (sp)->X_add_symbol)
882 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
883 || (symbol_get_value_expression (sp)->X_op_symbol
884 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
890 static int in_my_get_expression = 0;
892 /* Third argument to my_get_expression. */
893 #define GE_NO_PREFIX 0
894 #define GE_IMM_PREFIX 1
895 #define GE_OPT_PREFIX 2
896 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
897 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
898 #define GE_OPT_PREFIX_BIG 3
901 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
906 /* In unified syntax, all prefixes are optional. */
908 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
913 case GE_NO_PREFIX: break;
915 if (!is_immediate_prefix (**str))
917 inst.error = _("immediate expression requires a # prefix");
923 case GE_OPT_PREFIX_BIG:
924 if (is_immediate_prefix (**str))
930 memset (ep, 0, sizeof (expressionS));
932 save_in = input_line_pointer;
933 input_line_pointer = *str;
934 in_my_get_expression = 1;
935 seg = expression (ep);
936 in_my_get_expression = 0;
938 if (ep->X_op == O_illegal || ep->X_op == O_absent)
940 /* We found a bad or missing expression in md_operand(). */
941 *str = input_line_pointer;
942 input_line_pointer = save_in;
943 if (inst.error == NULL)
944 inst.error = (ep->X_op == O_absent
945 ? _("missing expression") :_("bad expression"));
950 if (seg != absolute_section
951 && seg != text_section
952 && seg != data_section
953 && seg != bss_section
954 && seg != undefined_section)
956 inst.error = _("bad segment");
957 *str = input_line_pointer;
958 input_line_pointer = save_in;
965 /* Get rid of any bignums now, so that we don't generate an error for which
966 we can't establish a line number later on. Big numbers are never valid
967 in instructions, which is where this routine is always called. */
968 if (prefix_mode != GE_OPT_PREFIX_BIG
969 && (ep->X_op == O_big
971 && (walk_no_bignums (ep->X_add_symbol)
973 && walk_no_bignums (ep->X_op_symbol))))))
975 inst.error = _("invalid constant");
976 *str = input_line_pointer;
977 input_line_pointer = save_in;
981 *str = input_line_pointer;
982 input_line_pointer = save_in;
986 /* Turn a string in input_line_pointer into a floating point constant
987 of type TYPE, and store the appropriate bytes in *LITP. The number
988 of LITTLENUMS emitted is stored in *SIZEP. An error message is
989 returned, or NULL on OK.
991 Note that fp constants aren't represent in the normal way on the ARM.
992 In big endian mode, things are as expected. However, in little endian
993 mode fp constants are big-endian word-wise, and little-endian byte-wise
994 within the words. For example, (double) 1.1 in big endian mode is
995 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
996 the byte sequence 99 99 f1 3f 9a 99 99 99.
998 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1001 md_atof (int type, char * litP, int * sizeP)
1004 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1036 return _("Unrecognized or unsupported floating point constant");
1039 t = atof_ieee (input_line_pointer, type, words);
1041 input_line_pointer = t;
1042 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1044 if (target_big_endian)
1046 for (i = 0; i < prec; i++)
1048 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1049 litP += sizeof (LITTLENUM_TYPE);
1054 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1055 for (i = prec - 1; i >= 0; i--)
1057 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1058 litP += sizeof (LITTLENUM_TYPE);
1061 /* For a 4 byte float the order of elements in `words' is 1 0.
1062 For an 8 byte float the order is 1 0 3 2. */
1063 for (i = 0; i < prec; i += 2)
1065 md_number_to_chars (litP, (valueT) words[i + 1],
1066 sizeof (LITTLENUM_TYPE));
1067 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1068 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1069 litP += 2 * sizeof (LITTLENUM_TYPE);
1076 /* We handle all bad expressions here, so that we can report the faulty
1077 instruction in the error message. */
1079 md_operand (expressionS * exp)
1081 if (in_my_get_expression)
1082 exp->X_op = O_illegal;
1085 /* Immediate values. */
1087 /* Generic immediate-value read function for use in directives.
1088 Accepts anything that 'expression' can fold to a constant.
1089 *val receives the number. */
1092 immediate_for_directive (int *val)
1095 exp.X_op = O_illegal;
1097 if (is_immediate_prefix (*input_line_pointer))
1099 input_line_pointer++;
1103 if (exp.X_op != O_constant)
1105 as_bad (_("expected #constant"));
1106 ignore_rest_of_line ();
1109 *val = exp.X_add_number;
1114 /* Register parsing. */
1116 /* Generic register parser. CCP points to what should be the
1117 beginning of a register name. If it is indeed a valid register
1118 name, advance CCP over it and return the reg_entry structure;
1119 otherwise return NULL. Does not issue diagnostics. */
1121 static struct reg_entry *
1122 arm_reg_parse_multi (char **ccp)
1126 struct reg_entry *reg;
1128 #ifdef REGISTER_PREFIX
1129 if (*start != REGISTER_PREFIX)
1133 #ifdef OPTIONAL_REGISTER_PREFIX
1134 if (*start == OPTIONAL_REGISTER_PREFIX)
1139 if (!ISALPHA (*p) || !is_name_beginner (*p))
1144 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1146 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1156 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1157 enum arm_reg_type type)
1159 /* Alternative syntaxes are accepted for a few register classes. */
1166 /* Generic coprocessor register names are allowed for these. */
1167 if (reg && reg->type == REG_TYPE_CN)
1172 /* For backward compatibility, a bare number is valid here. */
1174 unsigned long processor = strtoul (start, ccp, 10);
1175 if (*ccp != start && processor <= 15)
1179 case REG_TYPE_MMXWC:
1180 /* WC includes WCG. ??? I'm not sure this is true for all
1181 instructions that take WC registers. */
1182 if (reg && reg->type == REG_TYPE_MMXWCG)
1193 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1194 return value is the register number or FAIL. */
1197 arm_reg_parse (char **ccp, enum arm_reg_type type)
1200 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1203 /* Do not allow a scalar (reg+index) to parse as a register. */
1204 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1207 if (reg && reg->type == type)
1210 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1217 /* Parse a Neon type specifier. *STR should point at the leading '.'
1218 character. Does no verification at this stage that the type fits the opcode
1225 Can all be legally parsed by this function.
1227 Fills in neon_type struct pointer with parsed information, and updates STR
1228 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1229 type, FAIL if not. */
1232 parse_neon_type (struct neon_type *type, char **str)
1239 while (type->elems < NEON_MAX_TYPE_ELS)
1241 enum neon_el_type thistype = NT_untyped;
1242 unsigned thissize = -1u;
1249 /* Just a size without an explicit type. */
1253 switch (TOLOWER (*ptr))
1255 case 'i': thistype = NT_integer; break;
1256 case 'f': thistype = NT_float; break;
1257 case 'p': thistype = NT_poly; break;
1258 case 's': thistype = NT_signed; break;
1259 case 'u': thistype = NT_unsigned; break;
1261 thistype = NT_float;
1266 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1272 /* .f is an abbreviation for .f32. */
1273 if (thistype == NT_float && !ISDIGIT (*ptr))
1278 thissize = strtoul (ptr, &ptr, 10);
1280 if (thissize != 8 && thissize != 16 && thissize != 32
1283 as_bad (_("bad size %d in type specifier"), thissize);
1291 type->el[type->elems].type = thistype;
1292 type->el[type->elems].size = thissize;
1297 /* Empty/missing type is not a successful parse. */
1298 if (type->elems == 0)
1306 /* Errors may be set multiple times during parsing or bit encoding
1307 (particularly in the Neon bits), but usually the earliest error which is set
1308 will be the most meaningful. Avoid overwriting it with later (cascading)
1309 errors by calling this function. */
1312 first_error (const char *err)
1318 /* Parse a single type, e.g. ".s32", leading period included. */
1320 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1323 struct neon_type optype;
1327 if (parse_neon_type (&optype, &str) == SUCCESS)
1329 if (optype.elems == 1)
1330 *vectype = optype.el[0];
1333 first_error (_("only one type should be specified for operand"));
1339 first_error (_("vector type expected"));
1351 /* Special meanings for indices (which have a range of 0-7), which will fit into
1354 #define NEON_ALL_LANES 15
1355 #define NEON_INTERLEAVE_LANES 14
1357 /* Parse either a register or a scalar, with an optional type. Return the
1358 register number, and optionally fill in the actual type of the register
1359 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1360 type/index information in *TYPEINFO. */
1363 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1364 enum arm_reg_type *rtype,
1365 struct neon_typed_alias *typeinfo)
1368 struct reg_entry *reg = arm_reg_parse_multi (&str);
1369 struct neon_typed_alias atype;
1370 struct neon_type_el parsetype;
1374 atype.eltype.type = NT_invtype;
1375 atype.eltype.size = -1;
1377 /* Try alternate syntax for some types of register. Note these are mutually
1378 exclusive with the Neon syntax extensions. */
1381 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1389 /* Undo polymorphism when a set of register types may be accepted. */
1390 if ((type == REG_TYPE_NDQ
1391 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1392 || (type == REG_TYPE_VFSD
1393 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1394 || (type == REG_TYPE_NSDQ
1395 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1396 || reg->type == REG_TYPE_NQ))
1397 || (type == REG_TYPE_MMXWC
1398 && (reg->type == REG_TYPE_MMXWCG)))
1399 type = (enum arm_reg_type) reg->type;
1401 if (type != reg->type)
1407 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1409 if ((atype.defined & NTA_HASTYPE) != 0)
1411 first_error (_("can't redefine type for operand"));
1414 atype.defined |= NTA_HASTYPE;
1415 atype.eltype = parsetype;
1418 if (skip_past_char (&str, '[') == SUCCESS)
1420 if (type != REG_TYPE_VFD)
1422 first_error (_("only D registers may be indexed"));
1426 if ((atype.defined & NTA_HASINDEX) != 0)
1428 first_error (_("can't change index for operand"));
1432 atype.defined |= NTA_HASINDEX;
1434 if (skip_past_char (&str, ']') == SUCCESS)
1435 atype.index = NEON_ALL_LANES;
1440 my_get_expression (&exp, &str, GE_NO_PREFIX);
1442 if (exp.X_op != O_constant)
1444 first_error (_("constant expression required"));
1448 if (skip_past_char (&str, ']') == FAIL)
1451 atype.index = exp.X_add_number;
1466 /* Like arm_reg_parse, but allow allow the following extra features:
1467 - If RTYPE is non-zero, return the (possibly restricted) type of the
1468 register (e.g. Neon double or quad reg when either has been requested).
1469 - If this is a Neon vector type with additional type information, fill
1470 in the struct pointed to by VECTYPE (if non-NULL).
1471 This function will fault on encountering a scalar. */
1474 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1475 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1477 struct neon_typed_alias atype;
1479 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1484 /* Do not allow regname(... to parse as a register. */
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if ((atype.defined & NTA_HASINDEX) != 0)
1491 first_error (_("register operand expected, but got scalar"));
1496 *vectype = atype.eltype;
1503 #define NEON_SCALAR_REG(X) ((X) >> 4)
1504 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1506 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1507 have enough information to be able to do a good job bounds-checking. So, we
1508 just do easy checks here, and do further checks later. */
1511 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1515 struct neon_typed_alias atype;
1517 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1519 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1522 if (atype.index == NEON_ALL_LANES)
1524 first_error (_("scalar must have an index"));
1527 else if (atype.index >= 64 / elsize)
1529 first_error (_("scalar index out of range"));
1534 *type = atype.eltype;
1538 return reg * 16 + atype.index;
1541 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1544 parse_reg_list (char ** strp)
1546 char * str = * strp;
1550 /* We come back here if we get ranges concatenated by '+' or '|'. */
1565 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1567 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1577 first_error (_("bad range in register list"));
1581 for (i = cur_reg + 1; i < reg; i++)
1583 if (range & (1 << i))
1585 (_("Warning: duplicated register (r%d) in register list"),
1593 if (range & (1 << reg))
1594 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1596 else if (reg <= cur_reg)
1597 as_tsktsk (_("Warning: register range not in ascending order"));
1602 while (skip_past_comma (&str) != FAIL
1603 || (in_range = 1, *str++ == '-'));
1608 first_error (_("missing `}'"));
1616 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1619 if (exp.X_op == O_constant)
1621 if (exp.X_add_number
1622 != (exp.X_add_number & 0x0000ffff))
1624 inst.error = _("invalid register mask");
1628 if ((range & exp.X_add_number) != 0)
1630 int regno = range & exp.X_add_number;
1633 regno = (1 << regno) - 1;
1635 (_("Warning: duplicated register (r%d) in register list"),
1639 range |= exp.X_add_number;
1643 if (inst.reloc.type != 0)
1645 inst.error = _("expression too complex");
1649 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1650 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1651 inst.reloc.pc_rel = 0;
1655 if (*str == '|' || *str == '+')
1661 while (another_range);
1667 /* Types of registers in a list. */
1676 /* Parse a VFP register list. If the string is invalid return FAIL.
1677 Otherwise return the number of registers, and set PBASE to the first
1678 register. Parses registers of type ETYPE.
1679 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1680 - Q registers can be used to specify pairs of D registers
1681 - { } can be omitted from around a singleton register list
1682 FIXME: This is not implemented, as it would require backtracking in
1685 This could be done (the meaning isn't really ambiguous), but doesn't
1686 fit in well with the current parsing framework.
1687 - 32 D registers may be used (also true for VFPv3).
1688 FIXME: Types are ignored in these register lists, which is probably a
1692 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1697 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1701 unsigned long mask = 0;
1706 inst.error = _("expecting {");
1715 regtype = REG_TYPE_VFS;
1720 regtype = REG_TYPE_VFD;
1723 case REGLIST_NEON_D:
1724 regtype = REG_TYPE_NDQ;
1728 if (etype != REGLIST_VFP_S)
1730 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1731 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1735 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1738 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1745 base_reg = max_regs;
1749 int setmask = 1, addregs = 1;
1751 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1753 if (new_base == FAIL)
1755 first_error (_(reg_expected_msgs[regtype]));
1759 if (new_base >= max_regs)
1761 first_error (_("register out of range in list"));
1765 /* Note: a value of 2 * n is returned for the register Q<n>. */
1766 if (regtype == REG_TYPE_NQ)
1772 if (new_base < base_reg)
1773 base_reg = new_base;
1775 if (mask & (setmask << new_base))
1777 first_error (_("invalid register list"));
1781 if ((mask >> new_base) != 0 && ! warned)
1783 as_tsktsk (_("register list not in ascending order"));
1787 mask |= setmask << new_base;
1790 if (*str == '-') /* We have the start of a range expression */
1796 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1799 inst.error = gettext (reg_expected_msgs[regtype]);
1803 if (high_range >= max_regs)
1805 first_error (_("register out of range in list"));
1809 if (regtype == REG_TYPE_NQ)
1810 high_range = high_range + 1;
1812 if (high_range <= new_base)
1814 inst.error = _("register range not in ascending order");
1818 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1820 if (mask & (setmask << new_base))
1822 inst.error = _("invalid register list");
1826 mask |= setmask << new_base;
1831 while (skip_past_comma (&str) != FAIL);
1835 /* Sanity check -- should have raised a parse error above. */
1836 if (count == 0 || count > max_regs)
1841 /* Final test -- the registers must be consecutive. */
1843 for (i = 0; i < count; i++)
1845 if ((mask & (1u << i)) == 0)
1847 inst.error = _("non-contiguous register range");
1857 /* True if two alias types are the same. */
1860 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1868 if (a->defined != b->defined)
1871 if ((a->defined & NTA_HASTYPE) != 0
1872 && (a->eltype.type != b->eltype.type
1873 || a->eltype.size != b->eltype.size))
1876 if ((a->defined & NTA_HASINDEX) != 0
1877 && (a->index != b->index))
1883 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1884 The base register is put in *PBASE.
1885 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1887 The register stride (minus one) is put in bit 4 of the return value.
1888 Bits [6:5] encode the list length (minus one).
1889 The type of the list elements is put in *ELTYPE, if non-NULL. */
1891 #define NEON_LANE(X) ((X) & 0xf)
1892 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1893 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1896 parse_neon_el_struct_list (char **str, unsigned *pbase,
1897 struct neon_type_el *eltype)
1904 int leading_brace = 0;
1905 enum arm_reg_type rtype = REG_TYPE_NDQ;
1906 const char *const incr_error = _("register stride must be 1 or 2");
1907 const char *const type_error = _("mismatched element/structure types in list");
1908 struct neon_typed_alias firsttype;
1910 if (skip_past_char (&ptr, '{') == SUCCESS)
1915 struct neon_typed_alias atype;
1916 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1920 first_error (_(reg_expected_msgs[rtype]));
1927 if (rtype == REG_TYPE_NQ)
1933 else if (reg_incr == -1)
1935 reg_incr = getreg - base_reg;
1936 if (reg_incr < 1 || reg_incr > 2)
1938 first_error (_(incr_error));
1942 else if (getreg != base_reg + reg_incr * count)
1944 first_error (_(incr_error));
1948 if (! neon_alias_types_same (&atype, &firsttype))
1950 first_error (_(type_error));
1954 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1958 struct neon_typed_alias htype;
1959 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1961 lane = NEON_INTERLEAVE_LANES;
1962 else if (lane != NEON_INTERLEAVE_LANES)
1964 first_error (_(type_error));
1969 else if (reg_incr != 1)
1971 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1975 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1978 first_error (_(reg_expected_msgs[rtype]));
1981 if (! neon_alias_types_same (&htype, &firsttype))
1983 first_error (_(type_error));
1986 count += hireg + dregs - getreg;
1990 /* If we're using Q registers, we can't use [] or [n] syntax. */
1991 if (rtype == REG_TYPE_NQ)
1997 if ((atype.defined & NTA_HASINDEX) != 0)
2001 else if (lane != atype.index)
2003 first_error (_(type_error));
2007 else if (lane == -1)
2008 lane = NEON_INTERLEAVE_LANES;
2009 else if (lane != NEON_INTERLEAVE_LANES)
2011 first_error (_(type_error));
2016 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2018 /* No lane set by [x]. We must be interleaving structures. */
2020 lane = NEON_INTERLEAVE_LANES;
2023 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2024 || (count > 1 && reg_incr == -1))
2026 first_error (_("error parsing element/structure list"));
2030 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2032 first_error (_("expected }"));
2040 *eltype = firsttype.eltype;
2045 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2048 /* Parse an explicit relocation suffix on an expression. This is
2049 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2050 arm_reloc_hsh contains no entries, so this function can only
2051 succeed if there is no () after the word. Returns -1 on error,
2052 BFD_RELOC_UNUSED if there wasn't any suffix. */
2054 parse_reloc (char **str)
2056 struct reloc_entry *r;
2060 return BFD_RELOC_UNUSED;
2065 while (*q && *q != ')' && *q != ',')
2070 if ((r = (struct reloc_entry *)
2071 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2078 /* Directives: register aliases. */
2080 static struct reg_entry *
2081 insert_reg_alias (char *str, unsigned number, int type)
2083 struct reg_entry *new_reg;
2086 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2088 if (new_reg->builtin)
2089 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2091 /* Only warn about a redefinition if it's not defined as the
2093 else if (new_reg->number != number || new_reg->type != type)
2094 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2099 name = xstrdup (str);
2100 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2102 new_reg->name = name;
2103 new_reg->number = number;
2104 new_reg->type = type;
2105 new_reg->builtin = FALSE;
2106 new_reg->neon = NULL;
2108 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2115 insert_neon_reg_alias (char *str, int number, int type,
2116 struct neon_typed_alias *atype)
2118 struct reg_entry *reg = insert_reg_alias (str, number, type);
2122 first_error (_("attempt to redefine typed alias"));
2128 reg->neon = (struct neon_typed_alias *)
2129 xmalloc (sizeof (struct neon_typed_alias));
2130 *reg->neon = *atype;
2134 /* Look for the .req directive. This is of the form:
2136 new_register_name .req existing_register_name
2138 If we find one, or if it looks sufficiently like one that we want to
2139 handle any error here, return TRUE. Otherwise return FALSE. */
2142 create_register_alias (char * newname, char *p)
2144 struct reg_entry *old;
2145 char *oldname, *nbuf;
2148 /* The input scrubber ensures that whitespace after the mnemonic is
2149 collapsed to single spaces. */
2151 if (strncmp (oldname, " .req ", 6) != 0)
2155 if (*oldname == '\0')
2158 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2161 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2165 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2166 the desired alias name, and p points to its end. If not, then
2167 the desired alias name is in the global original_case_string. */
2168 #ifdef TC_CASE_SENSITIVE
2171 newname = original_case_string;
2172 nlen = strlen (newname);
2175 nbuf = (char *) alloca (nlen + 1);
2176 memcpy (nbuf, newname, nlen);
2179 /* Create aliases under the new name as stated; an all-lowercase
2180 version of the new name; and an all-uppercase version of the new
2182 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2184 for (p = nbuf; *p; p++)
2187 if (strncmp (nbuf, newname, nlen))
2189 /* If this attempt to create an additional alias fails, do not bother
2190 trying to create the all-lower case alias. We will fail and issue
2191 a second, duplicate error message. This situation arises when the
2192 programmer does something like:
2195 The second .req creates the "Foo" alias but then fails to create
2196 the artificial FOO alias because it has already been created by the
2198 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2202 for (p = nbuf; *p; p++)
2205 if (strncmp (nbuf, newname, nlen))
2206 insert_reg_alias (nbuf, old->number, old->type);
2212 /* Create a Neon typed/indexed register alias using directives, e.g.:
2217 These typed registers can be used instead of the types specified after the
2218 Neon mnemonic, so long as all operands given have types. Types can also be
2219 specified directly, e.g.:
2220 vadd d0.s32, d1.s32, d2.s32 */
2223 create_neon_reg_alias (char *newname, char *p)
2225 enum arm_reg_type basetype;
2226 struct reg_entry *basereg;
2227 struct reg_entry mybasereg;
2228 struct neon_type ntype;
2229 struct neon_typed_alias typeinfo;
2230 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2233 typeinfo.defined = 0;
2234 typeinfo.eltype.type = NT_invtype;
2235 typeinfo.eltype.size = -1;
2236 typeinfo.index = -1;
2240 if (strncmp (p, " .dn ", 5) == 0)
2241 basetype = REG_TYPE_VFD;
2242 else if (strncmp (p, " .qn ", 5) == 0)
2243 basetype = REG_TYPE_NQ;
2252 basereg = arm_reg_parse_multi (&p);
2254 if (basereg && basereg->type != basetype)
2256 as_bad (_("bad type for register"));
2260 if (basereg == NULL)
2263 /* Try parsing as an integer. */
2264 my_get_expression (&exp, &p, GE_NO_PREFIX);
2265 if (exp.X_op != O_constant)
2267 as_bad (_("expression must be constant"));
2270 basereg = &mybasereg;
2271 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2277 typeinfo = *basereg->neon;
2279 if (parse_neon_type (&ntype, &p) == SUCCESS)
2281 /* We got a type. */
2282 if (typeinfo.defined & NTA_HASTYPE)
2284 as_bad (_("can't redefine the type of a register alias"));
2288 typeinfo.defined |= NTA_HASTYPE;
2289 if (ntype.elems != 1)
2291 as_bad (_("you must specify a single type only"));
2294 typeinfo.eltype = ntype.el[0];
2297 if (skip_past_char (&p, '[') == SUCCESS)
2300 /* We got a scalar index. */
2302 if (typeinfo.defined & NTA_HASINDEX)
2304 as_bad (_("can't redefine the index of a scalar alias"));
2308 my_get_expression (&exp, &p, GE_NO_PREFIX);
2310 if (exp.X_op != O_constant)
2312 as_bad (_("scalar index must be constant"));
2316 typeinfo.defined |= NTA_HASINDEX;
2317 typeinfo.index = exp.X_add_number;
2319 if (skip_past_char (&p, ']') == FAIL)
2321 as_bad (_("expecting ]"));
2326 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2327 the desired alias name, and p points to its end. If not, then
2328 the desired alias name is in the global original_case_string. */
2329 #ifdef TC_CASE_SENSITIVE
2330 namelen = nameend - newname;
2332 newname = original_case_string;
2333 namelen = strlen (newname);
2336 namebuf = (char *) alloca (namelen + 1);
2337 strncpy (namebuf, newname, namelen);
2338 namebuf[namelen] = '\0';
2340 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2341 typeinfo.defined != 0 ? &typeinfo : NULL);
2343 /* Insert name in all uppercase. */
2344 for (p = namebuf; *p; p++)
2347 if (strncmp (namebuf, newname, namelen))
2348 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2349 typeinfo.defined != 0 ? &typeinfo : NULL);
2351 /* Insert name in all lowercase. */
2352 for (p = namebuf; *p; p++)
2355 if (strncmp (namebuf, newname, namelen))
2356 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2357 typeinfo.defined != 0 ? &typeinfo : NULL);
2362 /* Should never be called, as .req goes between the alias and the
2363 register name, not at the beginning of the line. */
2366 s_req (int a ATTRIBUTE_UNUSED)
2368 as_bad (_("invalid syntax for .req directive"));
2372 s_dn (int a ATTRIBUTE_UNUSED)
2374 as_bad (_("invalid syntax for .dn directive"));
2378 s_qn (int a ATTRIBUTE_UNUSED)
2380 as_bad (_("invalid syntax for .qn directive"));
2383 /* The .unreq directive deletes an alias which was previously defined
2384 by .req. For example:
2390 s_unreq (int a ATTRIBUTE_UNUSED)
2395 name = input_line_pointer;
2397 while (*input_line_pointer != 0
2398 && *input_line_pointer != ' '
2399 && *input_line_pointer != '\n')
2400 ++input_line_pointer;
2402 saved_char = *input_line_pointer;
2403 *input_line_pointer = 0;
2406 as_bad (_("invalid syntax for .unreq directive"));
2409 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2413 as_bad (_("unknown register alias '%s'"), name);
2414 else if (reg->builtin)
2415 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2422 hash_delete (arm_reg_hsh, name, FALSE);
2423 free ((char *) reg->name);
2428 /* Also locate the all upper case and all lower case versions.
2429 Do not complain if we cannot find one or the other as it
2430 was probably deleted above. */
2432 nbuf = strdup (name);
2433 for (p = nbuf; *p; p++)
2435 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2438 hash_delete (arm_reg_hsh, nbuf, FALSE);
2439 free ((char *) reg->name);
2445 for (p = nbuf; *p; p++)
2447 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2450 hash_delete (arm_reg_hsh, nbuf, FALSE);
2451 free ((char *) reg->name);
2461 *input_line_pointer = saved_char;
2462 demand_empty_rest_of_line ();
2465 /* Directives: Instruction set selection. */
2468 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2469 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2470 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2471 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2473 /* Create a new mapping symbol for the transition to STATE. */
2476 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2479 const char * symname;
2486 type = BSF_NO_FLAGS;
2490 type = BSF_NO_FLAGS;
2494 type = BSF_NO_FLAGS;
2500 symbolP = symbol_new (symname, now_seg, value, frag);
2501 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2506 THUMB_SET_FUNC (symbolP, 0);
2507 ARM_SET_THUMB (symbolP, 0);
2508 ARM_SET_INTERWORK (symbolP, support_interwork);
2512 THUMB_SET_FUNC (symbolP, 1);
2513 ARM_SET_THUMB (symbolP, 1);
2514 ARM_SET_INTERWORK (symbolP, support_interwork);
2522 /* Save the mapping symbols for future reference. Also check that
2523 we do not place two mapping symbols at the same offset within a
2524 frag. We'll handle overlap between frags in
2525 check_mapping_symbols.
2527 If .fill or other data filling directive generates zero sized data,
2528 the mapping symbol for the following code will have the same value
2529 as the one generated for the data filling directive. In this case,
2530 we replace the old symbol with the new one at the same address. */
2533 if (frag->tc_frag_data.first_map != NULL)
2535 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2536 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2538 frag->tc_frag_data.first_map = symbolP;
2540 if (frag->tc_frag_data.last_map != NULL)
2542 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2543 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2544 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2546 frag->tc_frag_data.last_map = symbolP;
2549 /* We must sometimes convert a region marked as code to data during
2550 code alignment, if an odd number of bytes have to be padded. The
2551 code mapping symbol is pushed to an aligned address. */
2554 insert_data_mapping_symbol (enum mstate state,
2555 valueT value, fragS *frag, offsetT bytes)
2557 /* If there was already a mapping symbol, remove it. */
2558 if (frag->tc_frag_data.last_map != NULL
2559 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2561 symbolS *symp = frag->tc_frag_data.last_map;
2565 know (frag->tc_frag_data.first_map == symp);
2566 frag->tc_frag_data.first_map = NULL;
2568 frag->tc_frag_data.last_map = NULL;
2569 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2572 make_mapping_symbol (MAP_DATA, value, frag);
2573 make_mapping_symbol (state, value + bytes, frag);
2576 static void mapping_state_2 (enum mstate state, int max_chars);
2578 /* Set the mapping state to STATE. Only call this when about to
2579 emit some STATE bytes to the file. */
2582 mapping_state (enum mstate state)
2584 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2586 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2588 if (mapstate == state)
2589 /* The mapping symbol has already been emitted.
2590 There is nothing else to do. */
2592 else if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2593 /* This case will be evaluated later in the next else. */
2595 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2596 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2598 /* Only add the symbol if the offset is > 0:
2599 if we're at the first frag, check it's size > 0;
2600 if we're not at the first frag, then for sure
2601 the offset is > 0. */
2602 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2603 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2606 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2609 mapping_state_2 (state, 0);
2613 /* Same as mapping_state, but MAX_CHARS bytes have already been
2614 allocated. Put the mapping symbol that far back. */
2617 mapping_state_2 (enum mstate state, int max_chars)
2619 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2621 if (!SEG_NORMAL (now_seg))
2624 if (mapstate == state)
2625 /* The mapping symbol has already been emitted.
2626 There is nothing else to do. */
2629 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2630 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2633 #define mapping_state(x) ((void)0)
2634 #define mapping_state_2(x, y) ((void)0)
2637 /* Find the real, Thumb encoded start of a Thumb function. */
2641 find_real_start (symbolS * symbolP)
2644 const char * name = S_GET_NAME (symbolP);
2645 symbolS * new_target;
2647 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2648 #define STUB_NAME ".real_start_of"
2653 /* The compiler may generate BL instructions to local labels because
2654 it needs to perform a branch to a far away location. These labels
2655 do not have a corresponding ".real_start_of" label. We check
2656 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2657 the ".real_start_of" convention for nonlocal branches. */
2658 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2661 real_start = ACONCAT ((STUB_NAME, name, NULL));
2662 new_target = symbol_find (real_start);
2664 if (new_target == NULL)
2666 as_warn (_("Failed to find real start of function: %s\n"), name);
2667 new_target = symbolP;
2675 opcode_select (int width)
2682 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2683 as_bad (_("selected processor does not support THUMB opcodes"));
2686 /* No need to force the alignment, since we will have been
2687 coming from ARM mode, which is word-aligned. */
2688 record_alignment (now_seg, 1);
2695 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2696 as_bad (_("selected processor does not support ARM opcodes"));
2701 frag_align (2, 0, 0);
2703 record_alignment (now_seg, 1);
2708 as_bad (_("invalid instruction size selected (%d)"), width);
2713 s_arm (int ignore ATTRIBUTE_UNUSED)
2716 demand_empty_rest_of_line ();
2720 s_thumb (int ignore ATTRIBUTE_UNUSED)
2723 demand_empty_rest_of_line ();
2727 s_code (int unused ATTRIBUTE_UNUSED)
2731 temp = get_absolute_expression ();
2736 opcode_select (temp);
2740 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2745 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2747 /* If we are not already in thumb mode go into it, EVEN if
2748 the target processor does not support thumb instructions.
2749 This is used by gcc/config/arm/lib1funcs.asm for example
2750 to compile interworking support functions even if the
2751 target processor should not support interworking. */
2755 record_alignment (now_seg, 1);
2758 demand_empty_rest_of_line ();
2762 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2766 /* The following label is the name/address of the start of a Thumb function.
2767 We need to know this for the interworking support. */
2768 label_is_thumb_function_name = TRUE;
2771 /* Perform a .set directive, but also mark the alias as
2772 being a thumb function. */
2775 s_thumb_set (int equiv)
2777 /* XXX the following is a duplicate of the code for s_set() in read.c
2778 We cannot just call that code as we need to get at the symbol that
2785 /* Especial apologies for the random logic:
2786 This just grew, and could be parsed much more simply!
2788 name = input_line_pointer;
2789 delim = get_symbol_end ();
2790 end_name = input_line_pointer;
2793 if (*input_line_pointer != ',')
2796 as_bad (_("expected comma after name \"%s\""), name);
2798 ignore_rest_of_line ();
2802 input_line_pointer++;
2805 if (name[0] == '.' && name[1] == '\0')
2807 /* XXX - this should not happen to .thumb_set. */
2811 if ((symbolP = symbol_find (name)) == NULL
2812 && (symbolP = md_undefined_symbol (name)) == NULL)
2815 /* When doing symbol listings, play games with dummy fragments living
2816 outside the normal fragment chain to record the file and line info
2818 if (listing & LISTING_SYMBOLS)
2820 extern struct list_info_struct * listing_tail;
2821 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2823 memset (dummy_frag, 0, sizeof (fragS));
2824 dummy_frag->fr_type = rs_fill;
2825 dummy_frag->line = listing_tail;
2826 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2827 dummy_frag->fr_symbol = symbolP;
2831 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2834 /* "set" symbols are local unless otherwise specified. */
2835 SF_SET_LOCAL (symbolP);
2836 #endif /* OBJ_COFF */
2837 } /* Make a new symbol. */
2839 symbol_table_insert (symbolP);
2844 && S_IS_DEFINED (symbolP)
2845 && S_GET_SEGMENT (symbolP) != reg_section)
2846 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2848 pseudo_set (symbolP);
2850 demand_empty_rest_of_line ();
2852 /* XXX Now we come to the Thumb specific bit of code. */
2854 THUMB_SET_FUNC (symbolP, 1);
2855 ARM_SET_THUMB (symbolP, 1);
2856 #if defined OBJ_ELF || defined OBJ_COFF
2857 ARM_SET_INTERWORK (symbolP, support_interwork);
2861 /* Directives: Mode selection. */
2863 /* .syntax [unified|divided] - choose the new unified syntax
2864 (same for Arm and Thumb encoding, modulo slight differences in what
2865 can be represented) or the old divergent syntax for each mode. */
2867 s_syntax (int unused ATTRIBUTE_UNUSED)
2871 name = input_line_pointer;
2872 delim = get_symbol_end ();
2874 if (!strcasecmp (name, "unified"))
2875 unified_syntax = TRUE;
2876 else if (!strcasecmp (name, "divided"))
2877 unified_syntax = FALSE;
2880 as_bad (_("unrecognized syntax mode \"%s\""), name);
2883 *input_line_pointer = delim;
2884 demand_empty_rest_of_line ();
2887 /* Directives: sectioning and alignment. */
2889 /* Same as s_align_ptwo but align 0 => align 2. */
2892 s_align (int unused ATTRIBUTE_UNUSED)
2897 long max_alignment = 15;
2899 temp = get_absolute_expression ();
2900 if (temp > max_alignment)
2901 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2904 as_bad (_("alignment negative. 0 assumed."));
2908 if (*input_line_pointer == ',')
2910 input_line_pointer++;
2911 temp_fill = get_absolute_expression ();
2923 /* Only make a frag if we HAVE to. */
2924 if (temp && !need_pass_2)
2926 if (!fill_p && subseg_text_p (now_seg))
2927 frag_align_code (temp, 0);
2929 frag_align (temp, (int) temp_fill, 0);
2931 demand_empty_rest_of_line ();
2933 record_alignment (now_seg, temp);
2937 s_bss (int ignore ATTRIBUTE_UNUSED)
2939 /* We don't support putting frags in the BSS segment, we fake it by
2940 marking in_bss, then looking at s_skip for clues. */
2941 subseg_set (bss_section, 0);
2942 demand_empty_rest_of_line ();
2944 #ifdef md_elf_section_change_hook
2945 md_elf_section_change_hook ();
2950 s_even (int ignore ATTRIBUTE_UNUSED)
2952 /* Never make frag if expect extra pass. */
2954 frag_align (1, 0, 0);
2956 record_alignment (now_seg, 1);
2958 demand_empty_rest_of_line ();
2961 /* Directives: Literal pools. */
2963 static literal_pool *
2964 find_literal_pool (void)
2966 literal_pool * pool;
2968 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2970 if (pool->section == now_seg
2971 && pool->sub_section == now_subseg)
2978 static literal_pool *
2979 find_or_make_literal_pool (void)
2981 /* Next literal pool ID number. */
2982 static unsigned int latest_pool_num = 1;
2983 literal_pool * pool;
2985 pool = find_literal_pool ();
2989 /* Create a new pool. */
2990 pool = (literal_pool *) xmalloc (sizeof (* pool));
2994 pool->next_free_entry = 0;
2995 pool->section = now_seg;
2996 pool->sub_section = now_subseg;
2997 pool->next = list_of_pools;
2998 pool->symbol = NULL;
3000 /* Add it to the list. */
3001 list_of_pools = pool;
3004 /* New pools, and emptied pools, will have a NULL symbol. */
3005 if (pool->symbol == NULL)
3007 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3008 (valueT) 0, &zero_address_frag);
3009 pool->id = latest_pool_num ++;
3016 /* Add the literal in the global 'inst'
3017 structure to the relevant literal pool. */
3020 add_to_lit_pool (void)
3022 literal_pool * pool;
3025 pool = find_or_make_literal_pool ();
3027 /* Check if this literal value is already in the pool. */
3028 for (entry = 0; entry < pool->next_free_entry; entry ++)
3030 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3031 && (inst.reloc.exp.X_op == O_constant)
3032 && (pool->literals[entry].X_add_number
3033 == inst.reloc.exp.X_add_number)
3034 && (pool->literals[entry].X_unsigned
3035 == inst.reloc.exp.X_unsigned))
3038 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3039 && (inst.reloc.exp.X_op == O_symbol)
3040 && (pool->literals[entry].X_add_number
3041 == inst.reloc.exp.X_add_number)
3042 && (pool->literals[entry].X_add_symbol
3043 == inst.reloc.exp.X_add_symbol)
3044 && (pool->literals[entry].X_op_symbol
3045 == inst.reloc.exp.X_op_symbol))
3049 /* Do we need to create a new entry? */
3050 if (entry == pool->next_free_entry)
3052 if (entry >= MAX_LITERAL_POOL_SIZE)
3054 inst.error = _("literal pool overflow");
3058 pool->literals[entry] = inst.reloc.exp;
3059 pool->next_free_entry += 1;
3062 inst.reloc.exp.X_op = O_symbol;
3063 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3064 inst.reloc.exp.X_add_symbol = pool->symbol;
3069 /* Can't use symbol_new here, so have to create a symbol and then at
3070 a later date assign it a value. Thats what these functions do. */
3073 symbol_locate (symbolS * symbolP,
3074 const char * name, /* It is copied, the caller can modify. */
3075 segT segment, /* Segment identifier (SEG_<something>). */
3076 valueT valu, /* Symbol value. */
3077 fragS * frag) /* Associated fragment. */
3079 unsigned int name_length;
3080 char * preserved_copy_of_name;
3082 name_length = strlen (name) + 1; /* +1 for \0. */
3083 obstack_grow (¬es, name, name_length);
3084 preserved_copy_of_name = (char *) obstack_finish (¬es);
3086 #ifdef tc_canonicalize_symbol_name
3087 preserved_copy_of_name =
3088 tc_canonicalize_symbol_name (preserved_copy_of_name);
3091 S_SET_NAME (symbolP, preserved_copy_of_name);
3093 S_SET_SEGMENT (symbolP, segment);
3094 S_SET_VALUE (symbolP, valu);
3095 symbol_clear_list_pointers (symbolP);
3097 symbol_set_frag (symbolP, frag);
3099 /* Link to end of symbol chain. */
3101 extern int symbol_table_frozen;
3103 if (symbol_table_frozen)
3107 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3109 obj_symbol_new_hook (symbolP);
3111 #ifdef tc_symbol_new_hook
3112 tc_symbol_new_hook (symbolP);
3116 verify_symbol_chain (symbol_rootP, symbol_lastP);
3117 #endif /* DEBUG_SYMS */
3122 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3125 literal_pool * pool;
3128 pool = find_literal_pool ();
3130 || pool->symbol == NULL
3131 || pool->next_free_entry == 0)
3134 mapping_state (MAP_DATA);
3136 /* Align pool as you have word accesses.
3137 Only make a frag if we have to. */
3139 frag_align (2, 0, 0);
3141 record_alignment (now_seg, 2);
3143 sprintf (sym_name, "$$lit_\002%x", pool->id);
3145 symbol_locate (pool->symbol, sym_name, now_seg,
3146 (valueT) frag_now_fix (), frag_now);
3147 symbol_table_insert (pool->symbol);
3149 ARM_SET_THUMB (pool->symbol, thumb_mode);
3151 #if defined OBJ_COFF || defined OBJ_ELF
3152 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3155 for (entry = 0; entry < pool->next_free_entry; entry ++)
3156 /* First output the expression in the instruction to the pool. */
3157 emit_expr (&(pool->literals[entry]), 4); /* .word */
3159 /* Mark the pool as empty. */
3160 pool->next_free_entry = 0;
3161 pool->symbol = NULL;
3165 /* Forward declarations for functions below, in the MD interface
3167 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3168 static valueT create_unwind_entry (int);
3169 static void start_unwind_section (const segT, int);
3170 static void add_unwind_opcode (valueT, int);
3171 static void flush_pending_unwind (void);
3173 /* Directives: Data. */
3176 s_arm_elf_cons (int nbytes)
3180 #ifdef md_flush_pending_output
3181 md_flush_pending_output ();
3184 if (is_it_end_of_statement ())
3186 demand_empty_rest_of_line ();
3190 #ifdef md_cons_align
3191 md_cons_align (nbytes);
3194 mapping_state (MAP_DATA);
3198 char *base = input_line_pointer;
3202 if (exp.X_op != O_symbol)
3203 emit_expr (&exp, (unsigned int) nbytes);
3206 char *before_reloc = input_line_pointer;
3207 reloc = parse_reloc (&input_line_pointer);
3210 as_bad (_("unrecognized relocation suffix"));
3211 ignore_rest_of_line ();
3214 else if (reloc == BFD_RELOC_UNUSED)
3215 emit_expr (&exp, (unsigned int) nbytes);
3218 reloc_howto_type *howto = (reloc_howto_type *)
3219 bfd_reloc_type_lookup (stdoutput,
3220 (bfd_reloc_code_real_type) reloc);
3221 int size = bfd_get_reloc_size (howto);
3223 if (reloc == BFD_RELOC_ARM_PLT32)
3225 as_bad (_("(plt) is only valid on branch targets"));
3226 reloc = BFD_RELOC_UNUSED;
3231 as_bad (_("%s relocations do not fit in %d bytes"),
3232 howto->name, nbytes);
3235 /* We've parsed an expression stopping at O_symbol.
3236 But there may be more expression left now that we
3237 have parsed the relocation marker. Parse it again.
3238 XXX Surely there is a cleaner way to do this. */
3239 char *p = input_line_pointer;
3241 char *save_buf = (char *) alloca (input_line_pointer - base);
3242 memcpy (save_buf, base, input_line_pointer - base);
3243 memmove (base + (input_line_pointer - before_reloc),
3244 base, before_reloc - base);
3246 input_line_pointer = base + (input_line_pointer-before_reloc);
3248 memcpy (base, save_buf, p - base);
3250 offset = nbytes - size;
3251 p = frag_more ((int) nbytes);
3252 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3253 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3258 while (*input_line_pointer++ == ',');
3260 /* Put terminator back into stream. */
3261 input_line_pointer --;
3262 demand_empty_rest_of_line ();
3265 /* Emit an expression containing a 32-bit thumb instruction.
3266 Implementation based on put_thumb32_insn. */
3269 emit_thumb32_expr (expressionS * exp)
3271 expressionS exp_high = *exp;
3273 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3274 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3275 exp->X_add_number &= 0xffff;
3276 emit_expr (exp, (unsigned int) THUMB_SIZE);
3279 /* Guess the instruction size based on the opcode. */
3282 thumb_insn_size (int opcode)
3284 if ((unsigned int) opcode < 0xe800u)
3286 else if ((unsigned int) opcode >= 0xe8000000u)
3293 emit_insn (expressionS *exp, int nbytes)
3297 if (exp->X_op == O_constant)
3302 size = thumb_insn_size (exp->X_add_number);
3306 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3308 as_bad (_(".inst.n operand too big. "\
3309 "Use .inst.w instead"));
3314 if (now_it.state == AUTOMATIC_IT_BLOCK)
3315 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3317 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3319 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3320 emit_thumb32_expr (exp);
3322 emit_expr (exp, (unsigned int) size);
3324 it_fsm_post_encode ();
3328 as_bad (_("cannot determine Thumb instruction size. " \
3329 "Use .inst.n/.inst.w instead"));
3332 as_bad (_("constant expression required"));
3337 /* Like s_arm_elf_cons but do not use md_cons_align and
3338 set the mapping state to MAP_ARM/MAP_THUMB. */
3341 s_arm_elf_inst (int nbytes)
3343 if (is_it_end_of_statement ())
3345 demand_empty_rest_of_line ();
3349 /* Calling mapping_state () here will not change ARM/THUMB,
3350 but will ensure not to be in DATA state. */
3353 mapping_state (MAP_THUMB);
3358 as_bad (_("width suffixes are invalid in ARM mode"));
3359 ignore_rest_of_line ();
3365 mapping_state (MAP_ARM);
3374 if (! emit_insn (& exp, nbytes))
3376 ignore_rest_of_line ();
3380 while (*input_line_pointer++ == ',');
3382 /* Put terminator back into stream. */
3383 input_line_pointer --;
3384 demand_empty_rest_of_line ();
3387 /* Parse a .rel31 directive. */
3390 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3397 if (*input_line_pointer == '1')
3398 highbit = 0x80000000;
3399 else if (*input_line_pointer != '0')
3400 as_bad (_("expected 0 or 1"));
3402 input_line_pointer++;
3403 if (*input_line_pointer != ',')
3404 as_bad (_("missing comma"));
3405 input_line_pointer++;
3407 #ifdef md_flush_pending_output
3408 md_flush_pending_output ();
3411 #ifdef md_cons_align
3415 mapping_state (MAP_DATA);
3420 md_number_to_chars (p, highbit, 4);
3421 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3422 BFD_RELOC_ARM_PREL31);
3424 demand_empty_rest_of_line ();
3427 /* Directives: AEABI stack-unwind tables. */
3429 /* Parse an unwind_fnstart directive. Simply records the current location. */
3432 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3434 demand_empty_rest_of_line ();
3435 if (unwind.proc_start)
3437 as_bad (_("duplicate .fnstart directive"));
3441 /* Mark the start of the function. */
3442 unwind.proc_start = expr_build_dot ();
3444 /* Reset the rest of the unwind info. */
3445 unwind.opcode_count = 0;
3446 unwind.table_entry = NULL;
3447 unwind.personality_routine = NULL;
3448 unwind.personality_index = -1;
3449 unwind.frame_size = 0;
3450 unwind.fp_offset = 0;
3451 unwind.fp_reg = REG_SP;
3453 unwind.sp_restored = 0;
3457 /* Parse a handlerdata directive. Creates the exception handling table entry
3458 for the function. */
3461 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3463 demand_empty_rest_of_line ();
3464 if (!unwind.proc_start)
3465 as_bad (MISSING_FNSTART);
3467 if (unwind.table_entry)
3468 as_bad (_("duplicate .handlerdata directive"));
3470 create_unwind_entry (1);
3473 /* Parse an unwind_fnend directive. Generates the index table entry. */
3476 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3481 unsigned int marked_pr_dependency;
3483 demand_empty_rest_of_line ();
3485 if (!unwind.proc_start)
3487 as_bad (_(".fnend directive without .fnstart"));
3491 /* Add eh table entry. */
3492 if (unwind.table_entry == NULL)
3493 val = create_unwind_entry (0);
3497 /* Add index table entry. This is two words. */
3498 start_unwind_section (unwind.saved_seg, 1);
3499 frag_align (2, 0, 0);
3500 record_alignment (now_seg, 2);
3502 ptr = frag_more (8);
3503 where = frag_now_fix () - 8;
3505 /* Self relative offset of the function start. */
3506 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3507 BFD_RELOC_ARM_PREL31);
3509 /* Indicate dependency on EHABI-defined personality routines to the
3510 linker, if it hasn't been done already. */
3511 marked_pr_dependency
3512 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3513 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3514 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3516 static const char *const name[] =
3518 "__aeabi_unwind_cpp_pr0",
3519 "__aeabi_unwind_cpp_pr1",
3520 "__aeabi_unwind_cpp_pr2"
3522 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3523 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3524 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3525 |= 1 << unwind.personality_index;
3529 /* Inline exception table entry. */
3530 md_number_to_chars (ptr + 4, val, 4);
3532 /* Self relative offset of the table entry. */
3533 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3534 BFD_RELOC_ARM_PREL31);
3536 /* Restore the original section. */
3537 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3539 unwind.proc_start = NULL;
3543 /* Parse an unwind_cantunwind directive. */
3546 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3548 demand_empty_rest_of_line ();
3549 if (!unwind.proc_start)
3550 as_bad (MISSING_FNSTART);
3552 if (unwind.personality_routine || unwind.personality_index != -1)
3553 as_bad (_("personality routine specified for cantunwind frame"));
3555 unwind.personality_index = -2;
3559 /* Parse a personalityindex directive. */
3562 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3566 if (!unwind.proc_start)
3567 as_bad (MISSING_FNSTART);
3569 if (unwind.personality_routine || unwind.personality_index != -1)
3570 as_bad (_("duplicate .personalityindex directive"));
3574 if (exp.X_op != O_constant
3575 || exp.X_add_number < 0 || exp.X_add_number > 15)
3577 as_bad (_("bad personality routine number"));
3578 ignore_rest_of_line ();
3582 unwind.personality_index = exp.X_add_number;
3584 demand_empty_rest_of_line ();
3588 /* Parse a personality directive. */
3591 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3595 if (!unwind.proc_start)
3596 as_bad (MISSING_FNSTART);
3598 if (unwind.personality_routine || unwind.personality_index != -1)
3599 as_bad (_("duplicate .personality directive"));
3601 name = input_line_pointer;
3602 c = get_symbol_end ();
3603 p = input_line_pointer;
3604 unwind.personality_routine = symbol_find_or_make (name);
3606 demand_empty_rest_of_line ();
3610 /* Parse a directive saving core registers. */
3613 s_arm_unwind_save_core (void)
3619 range = parse_reg_list (&input_line_pointer);
3622 as_bad (_("expected register list"));
3623 ignore_rest_of_line ();
3627 demand_empty_rest_of_line ();
3629 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3630 into .unwind_save {..., sp...}. We aren't bothered about the value of
3631 ip because it is clobbered by calls. */
3632 if (unwind.sp_restored && unwind.fp_reg == 12
3633 && (range & 0x3000) == 0x1000)
3635 unwind.opcode_count--;
3636 unwind.sp_restored = 0;
3637 range = (range | 0x2000) & ~0x1000;
3638 unwind.pending_offset = 0;
3644 /* See if we can use the short opcodes. These pop a block of up to 8
3645 registers starting with r4, plus maybe r14. */
3646 for (n = 0; n < 8; n++)
3648 /* Break at the first non-saved register. */
3649 if ((range & (1 << (n + 4))) == 0)
3652 /* See if there are any other bits set. */
3653 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3655 /* Use the long form. */
3656 op = 0x8000 | ((range >> 4) & 0xfff);
3657 add_unwind_opcode (op, 2);
3661 /* Use the short form. */
3663 op = 0xa8; /* Pop r14. */
3665 op = 0xa0; /* Do not pop r14. */
3667 add_unwind_opcode (op, 1);
3674 op = 0xb100 | (range & 0xf);
3675 add_unwind_opcode (op, 2);
3678 /* Record the number of bytes pushed. */
3679 for (n = 0; n < 16; n++)
3681 if (range & (1 << n))
3682 unwind.frame_size += 4;
3687 /* Parse a directive saving FPA registers. */
3690 s_arm_unwind_save_fpa (int reg)
3696 /* Get Number of registers to transfer. */
3697 if (skip_past_comma (&input_line_pointer) != FAIL)
3700 exp.X_op = O_illegal;
3702 if (exp.X_op != O_constant)
3704 as_bad (_("expected , <constant>"));
3705 ignore_rest_of_line ();
3709 num_regs = exp.X_add_number;
3711 if (num_regs < 1 || num_regs > 4)
3713 as_bad (_("number of registers must be in the range [1:4]"));
3714 ignore_rest_of_line ();
3718 demand_empty_rest_of_line ();
3723 op = 0xb4 | (num_regs - 1);
3724 add_unwind_opcode (op, 1);
3729 op = 0xc800 | (reg << 4) | (num_regs - 1);
3730 add_unwind_opcode (op, 2);
3732 unwind.frame_size += num_regs * 12;
3736 /* Parse a directive saving VFP registers for ARMv6 and above. */
3739 s_arm_unwind_save_vfp_armv6 (void)
3744 int num_vfpv3_regs = 0;
3745 int num_regs_below_16;
3747 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3750 as_bad (_("expected register list"));
3751 ignore_rest_of_line ();
3755 demand_empty_rest_of_line ();
3757 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3758 than FSTMX/FLDMX-style ones). */
3760 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3762 num_vfpv3_regs = count;
3763 else if (start + count > 16)
3764 num_vfpv3_regs = start + count - 16;
3766 if (num_vfpv3_regs > 0)
3768 int start_offset = start > 16 ? start - 16 : 0;
3769 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3770 add_unwind_opcode (op, 2);
3773 /* Generate opcode for registers numbered in the range 0 .. 15. */
3774 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3775 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3776 if (num_regs_below_16 > 0)
3778 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3779 add_unwind_opcode (op, 2);
3782 unwind.frame_size += count * 8;
3786 /* Parse a directive saving VFP registers for pre-ARMv6. */
3789 s_arm_unwind_save_vfp (void)
3795 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3798 as_bad (_("expected register list"));
3799 ignore_rest_of_line ();
3803 demand_empty_rest_of_line ();
3808 op = 0xb8 | (count - 1);
3809 add_unwind_opcode (op, 1);
3814 op = 0xb300 | (reg << 4) | (count - 1);
3815 add_unwind_opcode (op, 2);
3817 unwind.frame_size += count * 8 + 4;
3821 /* Parse a directive saving iWMMXt data registers. */
3824 s_arm_unwind_save_mmxwr (void)
3832 if (*input_line_pointer == '{')
3833 input_line_pointer++;
3837 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3841 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3846 as_tsktsk (_("register list not in ascending order"));
3849 if (*input_line_pointer == '-')
3851 input_line_pointer++;
3852 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3855 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3858 else if (reg >= hi_reg)
3860 as_bad (_("bad register range"));
3863 for (; reg < hi_reg; reg++)
3867 while (skip_past_comma (&input_line_pointer) != FAIL);
3869 if (*input_line_pointer == '}')
3870 input_line_pointer++;
3872 demand_empty_rest_of_line ();
3874 /* Generate any deferred opcodes because we're going to be looking at
3876 flush_pending_unwind ();
3878 for (i = 0; i < 16; i++)
3880 if (mask & (1 << i))
3881 unwind.frame_size += 8;
3884 /* Attempt to combine with a previous opcode. We do this because gcc
3885 likes to output separate unwind directives for a single block of
3887 if (unwind.opcode_count > 0)
3889 i = unwind.opcodes[unwind.opcode_count - 1];
3890 if ((i & 0xf8) == 0xc0)
3893 /* Only merge if the blocks are contiguous. */
3896 if ((mask & 0xfe00) == (1 << 9))
3898 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3899 unwind.opcode_count--;
3902 else if (i == 6 && unwind.opcode_count >= 2)
3904 i = unwind.opcodes[unwind.opcode_count - 2];
3908 op = 0xffff << (reg - 1);
3910 && ((mask & op) == (1u << (reg - 1))))
3912 op = (1 << (reg + i + 1)) - 1;
3913 op &= ~((1 << reg) - 1);
3915 unwind.opcode_count -= 2;
3922 /* We want to generate opcodes in the order the registers have been
3923 saved, ie. descending order. */
3924 for (reg = 15; reg >= -1; reg--)
3926 /* Save registers in blocks. */
3928 || !(mask & (1 << reg)))
3930 /* We found an unsaved reg. Generate opcodes to save the
3937 op = 0xc0 | (hi_reg - 10);
3938 add_unwind_opcode (op, 1);
3943 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3944 add_unwind_opcode (op, 2);
3953 ignore_rest_of_line ();
3957 s_arm_unwind_save_mmxwcg (void)
3964 if (*input_line_pointer == '{')
3965 input_line_pointer++;
3969 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3973 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
3979 as_tsktsk (_("register list not in ascending order"));
3982 if (*input_line_pointer == '-')
3984 input_line_pointer++;
3985 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3988 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
3991 else if (reg >= hi_reg)
3993 as_bad (_("bad register range"));
3996 for (; reg < hi_reg; reg++)
4000 while (skip_past_comma (&input_line_pointer) != FAIL);
4002 if (*input_line_pointer == '}')
4003 input_line_pointer++;
4005 demand_empty_rest_of_line ();
4007 /* Generate any deferred opcodes because we're going to be looking at
4009 flush_pending_unwind ();
4011 for (reg = 0; reg < 16; reg++)
4013 if (mask & (1 << reg))
4014 unwind.frame_size += 4;
4017 add_unwind_opcode (op, 2);
4020 ignore_rest_of_line ();
4024 /* Parse an unwind_save directive.
4025 If the argument is non-zero, this is a .vsave directive. */
4028 s_arm_unwind_save (int arch_v6)
4031 struct reg_entry *reg;
4032 bfd_boolean had_brace = FALSE;
4034 if (!unwind.proc_start)
4035 as_bad (MISSING_FNSTART);
4037 /* Figure out what sort of save we have. */
4038 peek = input_line_pointer;
4046 reg = arm_reg_parse_multi (&peek);
4050 as_bad (_("register expected"));
4051 ignore_rest_of_line ();
4060 as_bad (_("FPA .unwind_save does not take a register list"));
4061 ignore_rest_of_line ();
4064 input_line_pointer = peek;
4065 s_arm_unwind_save_fpa (reg->number);
4068 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4071 s_arm_unwind_save_vfp_armv6 ();
4073 s_arm_unwind_save_vfp ();
4075 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4076 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4079 as_bad (_(".unwind_save does not support this kind of register"));
4080 ignore_rest_of_line ();
4085 /* Parse an unwind_movsp directive. */
4088 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4094 if (!unwind.proc_start)
4095 as_bad (MISSING_FNSTART);
4097 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4100 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4101 ignore_rest_of_line ();
4105 /* Optional constant. */
4106 if (skip_past_comma (&input_line_pointer) != FAIL)
4108 if (immediate_for_directive (&offset) == FAIL)
4114 demand_empty_rest_of_line ();
4116 if (reg == REG_SP || reg == REG_PC)
4118 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4122 if (unwind.fp_reg != REG_SP)
4123 as_bad (_("unexpected .unwind_movsp directive"));
4125 /* Generate opcode to restore the value. */
4127 add_unwind_opcode (op, 1);
4129 /* Record the information for later. */
4130 unwind.fp_reg = reg;
4131 unwind.fp_offset = unwind.frame_size - offset;
4132 unwind.sp_restored = 1;
4135 /* Parse an unwind_pad directive. */
4138 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4142 if (!unwind.proc_start)
4143 as_bad (MISSING_FNSTART);
4145 if (immediate_for_directive (&offset) == FAIL)
4150 as_bad (_("stack increment must be multiple of 4"));
4151 ignore_rest_of_line ();
4155 /* Don't generate any opcodes, just record the details for later. */
4156 unwind.frame_size += offset;
4157 unwind.pending_offset += offset;
4159 demand_empty_rest_of_line ();
4162 /* Parse an unwind_setfp directive. */
4165 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4171 if (!unwind.proc_start)
4172 as_bad (MISSING_FNSTART);
4174 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4175 if (skip_past_comma (&input_line_pointer) == FAIL)
4178 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4180 if (fp_reg == FAIL || sp_reg == FAIL)
4182 as_bad (_("expected <reg>, <reg>"));
4183 ignore_rest_of_line ();
4187 /* Optional constant. */
4188 if (skip_past_comma (&input_line_pointer) != FAIL)
4190 if (immediate_for_directive (&offset) == FAIL)
4196 demand_empty_rest_of_line ();
4198 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4200 as_bad (_("register must be either sp or set by a previous"
4201 "unwind_movsp directive"));
4205 /* Don't generate any opcodes, just record the information for later. */
4206 unwind.fp_reg = fp_reg;
4208 if (sp_reg == REG_SP)
4209 unwind.fp_offset = unwind.frame_size - offset;
4211 unwind.fp_offset -= offset;
4214 /* Parse an unwind_raw directive. */
4217 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4220 /* This is an arbitrary limit. */
4221 unsigned char op[16];
4224 if (!unwind.proc_start)
4225 as_bad (MISSING_FNSTART);
4228 if (exp.X_op == O_constant
4229 && skip_past_comma (&input_line_pointer) != FAIL)
4231 unwind.frame_size += exp.X_add_number;
4235 exp.X_op = O_illegal;
4237 if (exp.X_op != O_constant)
4239 as_bad (_("expected <offset>, <opcode>"));
4240 ignore_rest_of_line ();
4246 /* Parse the opcode. */
4251 as_bad (_("unwind opcode too long"));
4252 ignore_rest_of_line ();
4254 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4256 as_bad (_("invalid unwind opcode"));
4257 ignore_rest_of_line ();
4260 op[count++] = exp.X_add_number;
4262 /* Parse the next byte. */
4263 if (skip_past_comma (&input_line_pointer) == FAIL)
4269 /* Add the opcode bytes in reverse order. */
4271 add_unwind_opcode (op[count], 1);
4273 demand_empty_rest_of_line ();
4277 /* Parse a .eabi_attribute directive. */
4280 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4282 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4284 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4285 attributes_set_explicitly[tag] = 1;
4288 /* Emit a tls fix for the symbol. */
4291 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4295 #ifdef md_flush_pending_output
4296 md_flush_pending_output ();
4299 #ifdef md_cons_align
4303 /* Since we're just labelling the code, there's no need to define a
4306 p = obstack_next_free (&frchain_now->frch_obstack);
4307 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4308 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4309 : BFD_RELOC_ARM_TLS_DESCSEQ);
4311 #endif /* OBJ_ELF */
4313 static void s_arm_arch (int);
4314 static void s_arm_object_arch (int);
4315 static void s_arm_cpu (int);
4316 static void s_arm_fpu (int);
4317 static void s_arm_arch_extension (int);
4322 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4329 if (exp.X_op == O_symbol)
4330 exp.X_op = O_secrel;
4332 emit_expr (&exp, 4);
4334 while (*input_line_pointer++ == ',');
4336 input_line_pointer--;
4337 demand_empty_rest_of_line ();
4341 /* This table describes all the machine specific pseudo-ops the assembler
4342 has to support. The fields are:
4343 pseudo-op name without dot
4344 function to call to execute this pseudo-op
4345 Integer arg to pass to the function. */
4347 const pseudo_typeS md_pseudo_table[] =
4349 /* Never called because '.req' does not start a line. */
4350 { "req", s_req, 0 },
4351 /* Following two are likewise never called. */
4354 { "unreq", s_unreq, 0 },
4355 { "bss", s_bss, 0 },
4356 { "align", s_align, 0 },
4357 { "arm", s_arm, 0 },
4358 { "thumb", s_thumb, 0 },
4359 { "code", s_code, 0 },
4360 { "force_thumb", s_force_thumb, 0 },
4361 { "thumb_func", s_thumb_func, 0 },
4362 { "thumb_set", s_thumb_set, 0 },
4363 { "even", s_even, 0 },
4364 { "ltorg", s_ltorg, 0 },
4365 { "pool", s_ltorg, 0 },
4366 { "syntax", s_syntax, 0 },
4367 { "cpu", s_arm_cpu, 0 },
4368 { "arch", s_arm_arch, 0 },
4369 { "object_arch", s_arm_object_arch, 0 },
4370 { "fpu", s_arm_fpu, 0 },
4371 { "arch_extension", s_arm_arch_extension, 0 },
4373 { "word", s_arm_elf_cons, 4 },
4374 { "long", s_arm_elf_cons, 4 },
4375 { "inst.n", s_arm_elf_inst, 2 },
4376 { "inst.w", s_arm_elf_inst, 4 },
4377 { "inst", s_arm_elf_inst, 0 },
4378 { "rel31", s_arm_rel31, 0 },
4379 { "fnstart", s_arm_unwind_fnstart, 0 },
4380 { "fnend", s_arm_unwind_fnend, 0 },
4381 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4382 { "personality", s_arm_unwind_personality, 0 },
4383 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4384 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4385 { "save", s_arm_unwind_save, 0 },
4386 { "vsave", s_arm_unwind_save, 1 },
4387 { "movsp", s_arm_unwind_movsp, 0 },
4388 { "pad", s_arm_unwind_pad, 0 },
4389 { "setfp", s_arm_unwind_setfp, 0 },
4390 { "unwind_raw", s_arm_unwind_raw, 0 },
4391 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4392 { "tlsdescseq", s_arm_tls_descseq, 0 },
4396 /* These are used for dwarf. */
4400 /* These are used for dwarf2. */
4401 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4402 { "loc", dwarf2_directive_loc, 0 },
4403 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4405 { "extend", float_cons, 'x' },
4406 { "ldouble", float_cons, 'x' },
4407 { "packed", float_cons, 'p' },
4409 {"secrel32", pe_directive_secrel, 0},
4414 /* Parser functions used exclusively in instruction operands. */
4416 /* Generic immediate-value read function for use in insn parsing.
4417 STR points to the beginning of the immediate (the leading #);
4418 VAL receives the value; if the value is outside [MIN, MAX]
4419 issue an error. PREFIX_OPT is true if the immediate prefix is
4423 parse_immediate (char **str, int *val, int min, int max,
4424 bfd_boolean prefix_opt)
4427 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4428 if (exp.X_op != O_constant)
4430 inst.error = _("constant expression required");
4434 if (exp.X_add_number < min || exp.X_add_number > max)
4436 inst.error = _("immediate value out of range");
4440 *val = exp.X_add_number;
4444 /* Less-generic immediate-value read function with the possibility of loading a
4445 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4446 instructions. Puts the result directly in inst.operands[i]. */
4449 parse_big_immediate (char **str, int i)
4454 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4456 if (exp.X_op == O_constant)
4458 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4459 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4460 O_constant. We have to be careful not to break compilation for
4461 32-bit X_add_number, though. */
4462 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4464 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4465 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4466 inst.operands[i].regisimm = 1;
4469 else if (exp.X_op == O_big
4470 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4472 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4474 /* Bignums have their least significant bits in
4475 generic_bignum[0]. Make sure we put 32 bits in imm and
4476 32 bits in reg, in a (hopefully) portable way. */
4477 gas_assert (parts != 0);
4479 /* Make sure that the number is not too big.
4480 PR 11972: Bignums can now be sign-extended to the
4481 size of a .octa so check that the out of range bits
4482 are all zero or all one. */
4483 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4485 LITTLENUM_TYPE m = -1;
4487 if (generic_bignum[parts * 2] != 0
4488 && generic_bignum[parts * 2] != m)
4491 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4492 if (generic_bignum[j] != generic_bignum[j-1])
4496 inst.operands[i].imm = 0;
4497 for (j = 0; j < parts; j++, idx++)
4498 inst.operands[i].imm |= generic_bignum[idx]
4499 << (LITTLENUM_NUMBER_OF_BITS * j);
4500 inst.operands[i].reg = 0;
4501 for (j = 0; j < parts; j++, idx++)
4502 inst.operands[i].reg |= generic_bignum[idx]
4503 << (LITTLENUM_NUMBER_OF_BITS * j);
4504 inst.operands[i].regisimm = 1;
4514 /* Returns the pseudo-register number of an FPA immediate constant,
4515 or FAIL if there isn't a valid constant here. */
4518 parse_fpa_immediate (char ** str)
4520 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4526 /* First try and match exact strings, this is to guarantee
4527 that some formats will work even for cross assembly. */
4529 for (i = 0; fp_const[i]; i++)
4531 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4535 *str += strlen (fp_const[i]);
4536 if (is_end_of_line[(unsigned char) **str])
4542 /* Just because we didn't get a match doesn't mean that the constant
4543 isn't valid, just that it is in a format that we don't
4544 automatically recognize. Try parsing it with the standard
4545 expression routines. */
4547 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4549 /* Look for a raw floating point number. */
4550 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4551 && is_end_of_line[(unsigned char) *save_in])
4553 for (i = 0; i < NUM_FLOAT_VALS; i++)
4555 for (j = 0; j < MAX_LITTLENUMS; j++)
4557 if (words[j] != fp_values[i][j])
4561 if (j == MAX_LITTLENUMS)
4569 /* Try and parse a more complex expression, this will probably fail
4570 unless the code uses a floating point prefix (eg "0f"). */
4571 save_in = input_line_pointer;
4572 input_line_pointer = *str;
4573 if (expression (&exp) == absolute_section
4574 && exp.X_op == O_big
4575 && exp.X_add_number < 0)
4577 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4579 if (gen_to_words (words, 5, (long) 15) == 0)
4581 for (i = 0; i < NUM_FLOAT_VALS; i++)
4583 for (j = 0; j < MAX_LITTLENUMS; j++)
4585 if (words[j] != fp_values[i][j])
4589 if (j == MAX_LITTLENUMS)
4591 *str = input_line_pointer;
4592 input_line_pointer = save_in;
4599 *str = input_line_pointer;
4600 input_line_pointer = save_in;
4601 inst.error = _("invalid FPA immediate expression");
4605 /* Returns 1 if a number has "quarter-precision" float format
4606 0baBbbbbbc defgh000 00000000 00000000. */
4609 is_quarter_float (unsigned imm)
4611 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4612 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4615 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4616 0baBbbbbbc defgh000 00000000 00000000.
4617 The zero and minus-zero cases need special handling, since they can't be
4618 encoded in the "quarter-precision" float format, but can nonetheless be
4619 loaded as integer constants. */
4622 parse_qfloat_immediate (char **ccp, int *immed)
4626 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4627 int found_fpchar = 0;
4629 skip_past_char (&str, '#');
4631 /* We must not accidentally parse an integer as a floating-point number. Make
4632 sure that the value we parse is not an integer by checking for special
4633 characters '.' or 'e'.
4634 FIXME: This is a horrible hack, but doing better is tricky because type
4635 information isn't in a very usable state at parse time. */
4637 skip_whitespace (fpnum);
4639 if (strncmp (fpnum, "0x", 2) == 0)
4643 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4644 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4654 if ((str = atof_ieee (str, 's', words)) != NULL)
4656 unsigned fpword = 0;
4659 /* Our FP word must be 32 bits (single-precision FP). */
4660 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4662 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4666 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4679 /* Shift operands. */
4682 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4685 struct asm_shift_name
4688 enum shift_kind kind;
4691 /* Third argument to parse_shift. */
4692 enum parse_shift_mode
4694 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4695 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4696 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4697 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4698 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4701 /* Parse a <shift> specifier on an ARM data processing instruction.
4702 This has three forms:
4704 (LSL|LSR|ASL|ASR|ROR) Rs
4705 (LSL|LSR|ASL|ASR|ROR) #imm
4708 Note that ASL is assimilated to LSL in the instruction encoding, and
4709 RRX to ROR #0 (which cannot be written as such). */
4712 parse_shift (char **str, int i, enum parse_shift_mode mode)
4714 const struct asm_shift_name *shift_name;
4715 enum shift_kind shift;
4720 for (p = *str; ISALPHA (*p); p++)
4725 inst.error = _("shift expression expected");
4729 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4732 if (shift_name == NULL)
4734 inst.error = _("shift expression expected");
4738 shift = shift_name->kind;
4742 case NO_SHIFT_RESTRICT:
4743 case SHIFT_IMMEDIATE: break;
4745 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4746 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4748 inst.error = _("'LSL' or 'ASR' required");
4753 case SHIFT_LSL_IMMEDIATE:
4754 if (shift != SHIFT_LSL)
4756 inst.error = _("'LSL' required");
4761 case SHIFT_ASR_IMMEDIATE:
4762 if (shift != SHIFT_ASR)
4764 inst.error = _("'ASR' required");
4772 if (shift != SHIFT_RRX)
4774 /* Whitespace can appear here if the next thing is a bare digit. */
4775 skip_whitespace (p);
4777 if (mode == NO_SHIFT_RESTRICT
4778 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4780 inst.operands[i].imm = reg;
4781 inst.operands[i].immisreg = 1;
4783 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4786 inst.operands[i].shift_kind = shift;
4787 inst.operands[i].shifted = 1;
4792 /* Parse a <shifter_operand> for an ARM data processing instruction:
4795 #<immediate>, <rotate>
4799 where <shift> is defined by parse_shift above, and <rotate> is a
4800 multiple of 2 between 0 and 30. Validation of immediate operands
4801 is deferred to md_apply_fix. */
4804 parse_shifter_operand (char **str, int i)
4809 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4811 inst.operands[i].reg = value;
4812 inst.operands[i].isreg = 1;
4814 /* parse_shift will override this if appropriate */
4815 inst.reloc.exp.X_op = O_constant;
4816 inst.reloc.exp.X_add_number = 0;
4818 if (skip_past_comma (str) == FAIL)
4821 /* Shift operation on register. */
4822 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4825 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4828 if (skip_past_comma (str) == SUCCESS)
4830 /* #x, y -- ie explicit rotation by Y. */
4831 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4834 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4836 inst.error = _("constant expression expected");
4840 value = exp.X_add_number;
4841 if (value < 0 || value > 30 || value % 2 != 0)
4843 inst.error = _("invalid rotation");
4846 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4848 inst.error = _("invalid constant");
4852 /* Convert to decoded value. md_apply_fix will put it back. */
4853 inst.reloc.exp.X_add_number
4854 = (((inst.reloc.exp.X_add_number << (32 - value))
4855 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
4858 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4859 inst.reloc.pc_rel = 0;
4863 /* Group relocation information. Each entry in the table contains the
4864 textual name of the relocation as may appear in assembler source
4865 and must end with a colon.
4866 Along with this textual name are the relocation codes to be used if
4867 the corresponding instruction is an ALU instruction (ADD or SUB only),
4868 an LDR, an LDRS, or an LDC. */
4870 struct group_reloc_table_entry
4881 /* Varieties of non-ALU group relocation. */
4888 static struct group_reloc_table_entry group_reloc_table[] =
4889 { /* Program counter relative: */
4891 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4896 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4897 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4898 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4899 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4901 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4906 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4907 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4908 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4909 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4911 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4912 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4913 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4914 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4915 /* Section base relative */
4917 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4922 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4923 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4924 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4925 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4927 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4932 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4933 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4934 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4935 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4937 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4938 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4939 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4940 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4942 /* Given the address of a pointer pointing to the textual name of a group
4943 relocation as may appear in assembler source, attempt to find its details
4944 in group_reloc_table. The pointer will be updated to the character after
4945 the trailing colon. On failure, FAIL will be returned; SUCCESS
4946 otherwise. On success, *entry will be updated to point at the relevant
4947 group_reloc_table entry. */
4950 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4953 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4955 int length = strlen (group_reloc_table[i].name);
4957 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
4958 && (*str)[length] == ':')
4960 *out = &group_reloc_table[i];
4961 *str += (length + 1);
4969 /* Parse a <shifter_operand> for an ARM data processing instruction
4970 (as for parse_shifter_operand) where group relocations are allowed:
4973 #<immediate>, <rotate>
4974 #:<group_reloc>:<expression>
4978 where <group_reloc> is one of the strings defined in group_reloc_table.
4979 The hashes are optional.
4981 Everything else is as for parse_shifter_operand. */
4983 static parse_operand_result
4984 parse_shifter_operand_group_reloc (char **str, int i)
4986 /* Determine if we have the sequence of characters #: or just :
4987 coming next. If we do, then we check for a group relocation.
4988 If we don't, punt the whole lot to parse_shifter_operand. */
4990 if (((*str)[0] == '#' && (*str)[1] == ':')
4991 || (*str)[0] == ':')
4993 struct group_reloc_table_entry *entry;
4995 if ((*str)[0] == '#')
5000 /* Try to parse a group relocation. Anything else is an error. */
5001 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5003 inst.error = _("unknown group relocation");
5004 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5007 /* We now have the group relocation table entry corresponding to
5008 the name in the assembler source. Next, we parse the expression. */
5009 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5010 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5012 /* Record the relocation type (always the ALU variant here). */
5013 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5014 gas_assert (inst.reloc.type != 0);
5016 return PARSE_OPERAND_SUCCESS;
5019 return parse_shifter_operand (str, i) == SUCCESS
5020 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5022 /* Never reached. */
5025 /* Parse a Neon alignment expression. Information is written to
5026 inst.operands[i]. We assume the initial ':' has been skipped.
5028 align .imm = align << 8, .immisalign=1, .preind=0 */
5029 static parse_operand_result
5030 parse_neon_alignment (char **str, int i)
5035 my_get_expression (&exp, &p, GE_NO_PREFIX);
5037 if (exp.X_op != O_constant)
5039 inst.error = _("alignment must be constant");
5040 return PARSE_OPERAND_FAIL;
5043 inst.operands[i].imm = exp.X_add_number << 8;
5044 inst.operands[i].immisalign = 1;
5045 /* Alignments are not pre-indexes. */
5046 inst.operands[i].preind = 0;
5049 return PARSE_OPERAND_SUCCESS;
5052 /* Parse all forms of an ARM address expression. Information is written
5053 to inst.operands[i] and/or inst.reloc.
5055 Preindexed addressing (.preind=1):
5057 [Rn, #offset] .reg=Rn .reloc.exp=offset
5058 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5059 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5060 .shift_kind=shift .reloc.exp=shift_imm
5062 These three may have a trailing ! which causes .writeback to be set also.
5064 Postindexed addressing (.postind=1, .writeback=1):
5066 [Rn], #offset .reg=Rn .reloc.exp=offset
5067 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5068 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5069 .shift_kind=shift .reloc.exp=shift_imm
5071 Unindexed addressing (.preind=0, .postind=0):
5073 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5077 [Rn]{!} shorthand for [Rn,#0]{!}
5078 =immediate .isreg=0 .reloc.exp=immediate
5079 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5081 It is the caller's responsibility to check for addressing modes not
5082 supported by the instruction, and to set inst.reloc.type. */
5084 static parse_operand_result
5085 parse_address_main (char **str, int i, int group_relocations,
5086 group_reloc_type group_type)
5091 if (skip_past_char (&p, '[') == FAIL)
5093 if (skip_past_char (&p, '=') == FAIL)
5095 /* Bare address - translate to PC-relative offset. */
5096 inst.reloc.pc_rel = 1;
5097 inst.operands[i].reg = REG_PC;
5098 inst.operands[i].isreg = 1;
5099 inst.operands[i].preind = 1;
5101 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5103 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5104 return PARSE_OPERAND_FAIL;
5107 return PARSE_OPERAND_SUCCESS;
5110 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5112 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5113 return PARSE_OPERAND_FAIL;
5115 inst.operands[i].reg = reg;
5116 inst.operands[i].isreg = 1;
5118 if (skip_past_comma (&p) == SUCCESS)
5120 inst.operands[i].preind = 1;
5123 else if (*p == '-') p++, inst.operands[i].negative = 1;
5125 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5127 inst.operands[i].imm = reg;
5128 inst.operands[i].immisreg = 1;
5130 if (skip_past_comma (&p) == SUCCESS)
5131 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5132 return PARSE_OPERAND_FAIL;
5134 else if (skip_past_char (&p, ':') == SUCCESS)
5136 /* FIXME: '@' should be used here, but it's filtered out by generic
5137 code before we get to see it here. This may be subject to
5139 parse_operand_result result = parse_neon_alignment (&p, i);
5141 if (result != PARSE_OPERAND_SUCCESS)
5146 if (inst.operands[i].negative)
5148 inst.operands[i].negative = 0;
5152 if (group_relocations
5153 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5155 struct group_reloc_table_entry *entry;
5157 /* Skip over the #: or : sequence. */
5163 /* Try to parse a group relocation. Anything else is an
5165 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5167 inst.error = _("unknown group relocation");
5168 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5171 /* We now have the group relocation table entry corresponding to
5172 the name in the assembler source. Next, we parse the
5174 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5175 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5177 /* Record the relocation type. */
5181 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5185 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5189 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5196 if (inst.reloc.type == 0)
5198 inst.error = _("this group relocation is not allowed on this instruction");
5199 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5205 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5206 return PARSE_OPERAND_FAIL;
5207 /* If the offset is 0, find out if it's a +0 or -0. */
5208 if (inst.reloc.exp.X_op == O_constant
5209 && inst.reloc.exp.X_add_number == 0)
5211 skip_whitespace (q);
5215 skip_whitespace (q);
5218 inst.operands[i].negative = 1;
5223 else if (skip_past_char (&p, ':') == SUCCESS)
5225 /* FIXME: '@' should be used here, but it's filtered out by generic code
5226 before we get to see it here. This may be subject to change. */
5227 parse_operand_result result = parse_neon_alignment (&p, i);
5229 if (result != PARSE_OPERAND_SUCCESS)
5233 if (skip_past_char (&p, ']') == FAIL)
5235 inst.error = _("']' expected");
5236 return PARSE_OPERAND_FAIL;
5239 if (skip_past_char (&p, '!') == SUCCESS)
5240 inst.operands[i].writeback = 1;
5242 else if (skip_past_comma (&p) == SUCCESS)
5244 if (skip_past_char (&p, '{') == SUCCESS)
5246 /* [Rn], {expr} - unindexed, with option */
5247 if (parse_immediate (&p, &inst.operands[i].imm,
5248 0, 255, TRUE) == FAIL)
5249 return PARSE_OPERAND_FAIL;
5251 if (skip_past_char (&p, '}') == FAIL)
5253 inst.error = _("'}' expected at end of 'option' field");
5254 return PARSE_OPERAND_FAIL;
5256 if (inst.operands[i].preind)
5258 inst.error = _("cannot combine index with option");
5259 return PARSE_OPERAND_FAIL;
5262 return PARSE_OPERAND_SUCCESS;
5266 inst.operands[i].postind = 1;
5267 inst.operands[i].writeback = 1;
5269 if (inst.operands[i].preind)
5271 inst.error = _("cannot combine pre- and post-indexing");
5272 return PARSE_OPERAND_FAIL;
5276 else if (*p == '-') p++, inst.operands[i].negative = 1;
5278 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5280 /* We might be using the immediate for alignment already. If we
5281 are, OR the register number into the low-order bits. */
5282 if (inst.operands[i].immisalign)
5283 inst.operands[i].imm |= reg;
5285 inst.operands[i].imm = reg;
5286 inst.operands[i].immisreg = 1;
5288 if (skip_past_comma (&p) == SUCCESS)
5289 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5290 return PARSE_OPERAND_FAIL;
5295 if (inst.operands[i].negative)
5297 inst.operands[i].negative = 0;
5300 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5301 return PARSE_OPERAND_FAIL;
5302 /* If the offset is 0, find out if it's a +0 or -0. */
5303 if (inst.reloc.exp.X_op == O_constant
5304 && inst.reloc.exp.X_add_number == 0)
5306 skip_whitespace (q);
5310 skip_whitespace (q);
5313 inst.operands[i].negative = 1;
5319 /* If at this point neither .preind nor .postind is set, we have a
5320 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5321 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5323 inst.operands[i].preind = 1;
5324 inst.reloc.exp.X_op = O_constant;
5325 inst.reloc.exp.X_add_number = 0;
5328 return PARSE_OPERAND_SUCCESS;
5332 parse_address (char **str, int i)
5334 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5338 static parse_operand_result
5339 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5341 return parse_address_main (str, i, 1, type);
5344 /* Parse an operand for a MOVW or MOVT instruction. */
5346 parse_half (char **str)
5351 skip_past_char (&p, '#');
5352 if (strncasecmp (p, ":lower16:", 9) == 0)
5353 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5354 else if (strncasecmp (p, ":upper16:", 9) == 0)
5355 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5357 if (inst.reloc.type != BFD_RELOC_UNUSED)
5360 skip_whitespace (p);
5363 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5366 if (inst.reloc.type == BFD_RELOC_UNUSED)
5368 if (inst.reloc.exp.X_op != O_constant)
5370 inst.error = _("constant expression expected");
5373 if (inst.reloc.exp.X_add_number < 0
5374 || inst.reloc.exp.X_add_number > 0xffff)
5376 inst.error = _("immediate value out of range");
5384 /* Miscellaneous. */
5386 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5387 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5389 parse_psr (char **str, bfd_boolean lhs)
5392 unsigned long psr_field;
5393 const struct asm_psr *psr;
5395 bfd_boolean is_apsr = FALSE;
5396 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5398 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5399 feature for ease of use and backwards compatibility. */
5401 if (strncasecmp (p, "SPSR", 4) == 0)
5404 goto unsupported_psr;
5406 psr_field = SPSR_BIT;
5408 else if (strncasecmp (p, "CPSR", 4) == 0)
5411 goto unsupported_psr;
5415 else if (strncasecmp (p, "APSR", 4) == 0)
5417 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5418 and ARMv7-R architecture CPUs. */
5427 while (ISALNUM (*p) || *p == '_');
5429 if (strncasecmp (start, "iapsr", 5) == 0
5430 || strncasecmp (start, "eapsr", 5) == 0
5431 || strncasecmp (start, "xpsr", 4) == 0
5432 || strncasecmp (start, "psr", 3) == 0)
5433 p = start + strcspn (start, "rR") + 1;
5435 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5441 /* If APSR is being written, a bitfield may be specified. Note that
5442 APSR itself is handled above. */
5443 if (psr->field <= 3)
5445 psr_field = psr->field;
5451 /* M-profile MSR instructions have the mask field set to "10", except
5452 *PSR variants which modify APSR, which may use a different mask (and
5453 have been handled already). Do that by setting the PSR_f field
5455 return psr->field | (lhs ? PSR_f : 0);
5458 goto unsupported_psr;
5464 /* A suffix follows. */
5470 while (ISALNUM (*p) || *p == '_');
5474 /* APSR uses a notation for bits, rather than fields. */
5475 unsigned int nzcvq_bits = 0;
5476 unsigned int g_bit = 0;
5479 for (bit = start; bit != p; bit++)
5481 switch (TOLOWER (*bit))
5484 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5488 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5492 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5496 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5500 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5504 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5508 inst.error = _("unexpected bit specified after APSR");
5513 if (nzcvq_bits == 0x1f)
5518 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5520 inst.error = _("selected processor does not "
5521 "support DSP extension");
5528 if ((nzcvq_bits & 0x20) != 0
5529 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5530 || (g_bit & 0x2) != 0)
5532 inst.error = _("bad bitmask specified after APSR");
5538 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5543 psr_field |= psr->field;
5549 goto error; /* Garbage after "[CS]PSR". */
5551 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5552 is deprecated, but allow it anyway. */
5556 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5559 else if (!m_profile)
5560 /* These bits are never right for M-profile devices: don't set them
5561 (only code paths which read/write APSR reach here). */
5562 psr_field |= (PSR_c | PSR_f);
5568 inst.error = _("selected processor does not support requested special "
5569 "purpose register");
5573 inst.error = _("flag for {c}psr instruction expected");
5577 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5578 value suitable for splatting into the AIF field of the instruction. */
5581 parse_cps_flags (char **str)
5590 case '\0': case ',':
5593 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5594 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5595 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5598 inst.error = _("unrecognized CPS flag");
5603 if (saw_a_flag == 0)
5605 inst.error = _("missing CPS flags");
5613 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5614 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5617 parse_endian_specifier (char **str)
5622 if (strncasecmp (s, "BE", 2))
5624 else if (strncasecmp (s, "LE", 2))
5628 inst.error = _("valid endian specifiers are be or le");
5632 if (ISALNUM (s[2]) || s[2] == '_')
5634 inst.error = _("valid endian specifiers are be or le");
5639 return little_endian;
5642 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5643 value suitable for poking into the rotate field of an sxt or sxta
5644 instruction, or FAIL on error. */
5647 parse_ror (char **str)
5652 if (strncasecmp (s, "ROR", 3) == 0)
5656 inst.error = _("missing rotation field after comma");
5660 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5665 case 0: *str = s; return 0x0;
5666 case 8: *str = s; return 0x1;
5667 case 16: *str = s; return 0x2;
5668 case 24: *str = s; return 0x3;
5671 inst.error = _("rotation can only be 0, 8, 16, or 24");
5676 /* Parse a conditional code (from conds[] below). The value returned is in the
5677 range 0 .. 14, or FAIL. */
5679 parse_cond (char **str)
5682 const struct asm_cond *c;
5684 /* Condition codes are always 2 characters, so matching up to
5685 3 characters is sufficient. */
5690 while (ISALPHA (*q) && n < 3)
5692 cond[n] = TOLOWER (*q);
5697 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5700 inst.error = _("condition required");
5708 /* Parse an option for a barrier instruction. Returns the encoding for the
5711 parse_barrier (char **str)
5714 const struct asm_barrier_opt *o;
5717 while (ISALPHA (*q))
5720 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5729 /* Parse the operands of a table branch instruction. Similar to a memory
5732 parse_tb (char **str)
5737 if (skip_past_char (&p, '[') == FAIL)
5739 inst.error = _("'[' expected");
5743 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5745 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5748 inst.operands[0].reg = reg;
5750 if (skip_past_comma (&p) == FAIL)
5752 inst.error = _("',' expected");
5756 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5758 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5761 inst.operands[0].imm = reg;
5763 if (skip_past_comma (&p) == SUCCESS)
5765 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5767 if (inst.reloc.exp.X_add_number != 1)
5769 inst.error = _("invalid shift");
5772 inst.operands[0].shifted = 1;
5775 if (skip_past_char (&p, ']') == FAIL)
5777 inst.error = _("']' expected");
5784 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5785 information on the types the operands can take and how they are encoded.
5786 Up to four operands may be read; this function handles setting the
5787 ".present" field for each read operand itself.
5788 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5789 else returns FAIL. */
5792 parse_neon_mov (char **str, int *which_operand)
5794 int i = *which_operand, val;
5795 enum arm_reg_type rtype;
5797 struct neon_type_el optype;
5799 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5801 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5802 inst.operands[i].reg = val;
5803 inst.operands[i].isscalar = 1;
5804 inst.operands[i].vectype = optype;
5805 inst.operands[i++].present = 1;
5807 if (skip_past_comma (&ptr) == FAIL)
5810 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5813 inst.operands[i].reg = val;
5814 inst.operands[i].isreg = 1;
5815 inst.operands[i].present = 1;
5817 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5820 /* Cases 0, 1, 2, 3, 5 (D only). */
5821 if (skip_past_comma (&ptr) == FAIL)
5824 inst.operands[i].reg = val;
5825 inst.operands[i].isreg = 1;
5826 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5827 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5828 inst.operands[i].isvec = 1;
5829 inst.operands[i].vectype = optype;
5830 inst.operands[i++].present = 1;
5832 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5834 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5835 Case 13: VMOV <Sd>, <Rm> */
5836 inst.operands[i].reg = val;
5837 inst.operands[i].isreg = 1;
5838 inst.operands[i].present = 1;
5840 if (rtype == REG_TYPE_NQ)
5842 first_error (_("can't use Neon quad register here"));
5845 else if (rtype != REG_TYPE_VFS)
5848 if (skip_past_comma (&ptr) == FAIL)
5850 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5852 inst.operands[i].reg = val;
5853 inst.operands[i].isreg = 1;
5854 inst.operands[i].present = 1;
5857 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5860 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5861 Case 1: VMOV<c><q> <Dd>, <Dm>
5862 Case 8: VMOV.F32 <Sd>, <Sm>
5863 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5865 inst.operands[i].reg = val;
5866 inst.operands[i].isreg = 1;
5867 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5868 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5869 inst.operands[i].isvec = 1;
5870 inst.operands[i].vectype = optype;
5871 inst.operands[i].present = 1;
5873 if (skip_past_comma (&ptr) == SUCCESS)
5878 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5881 inst.operands[i].reg = val;
5882 inst.operands[i].isreg = 1;
5883 inst.operands[i++].present = 1;
5885 if (skip_past_comma (&ptr) == FAIL)
5888 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5891 inst.operands[i].reg = val;
5892 inst.operands[i].isreg = 1;
5893 inst.operands[i++].present = 1;
5896 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5897 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5898 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5899 Case 10: VMOV.F32 <Sd>, #<imm>
5900 Case 11: VMOV.F64 <Dd>, #<imm> */
5901 inst.operands[i].immisfloat = 1;
5902 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5903 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5904 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5908 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5912 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5915 inst.operands[i].reg = val;
5916 inst.operands[i].isreg = 1;
5917 inst.operands[i++].present = 1;
5919 if (skip_past_comma (&ptr) == FAIL)
5922 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5924 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5925 inst.operands[i].reg = val;
5926 inst.operands[i].isscalar = 1;
5927 inst.operands[i].present = 1;
5928 inst.operands[i].vectype = optype;
5930 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5932 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5933 inst.operands[i].reg = val;
5934 inst.operands[i].isreg = 1;
5935 inst.operands[i++].present = 1;
5937 if (skip_past_comma (&ptr) == FAIL)
5940 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5943 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5947 inst.operands[i].reg = val;
5948 inst.operands[i].isreg = 1;
5949 inst.operands[i].isvec = 1;
5950 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5951 inst.operands[i].vectype = optype;
5952 inst.operands[i].present = 1;
5954 if (rtype == REG_TYPE_VFS)
5958 if (skip_past_comma (&ptr) == FAIL)
5960 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
5963 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
5966 inst.operands[i].reg = val;
5967 inst.operands[i].isreg = 1;
5968 inst.operands[i].isvec = 1;
5969 inst.operands[i].issingle = 1;
5970 inst.operands[i].vectype = optype;
5971 inst.operands[i].present = 1;
5974 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
5978 inst.operands[i].reg = val;
5979 inst.operands[i].isreg = 1;
5980 inst.operands[i].isvec = 1;
5981 inst.operands[i].issingle = 1;
5982 inst.operands[i].vectype = optype;
5983 inst.operands[i++].present = 1;
5988 first_error (_("parse error"));
5992 /* Successfully parsed the operands. Update args. */
5998 first_error (_("expected comma"));
6002 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6006 /* Use this macro when the operand constraints are different
6007 for ARM and THUMB (e.g. ldrd). */
6008 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6009 ((arm_operand) | ((thumb_operand) << 16))
6011 /* Matcher codes for parse_operands. */
6012 enum operand_parse_code
6014 OP_stop, /* end of line */
6016 OP_RR, /* ARM register */
6017 OP_RRnpc, /* ARM register, not r15 */
6018 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6019 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6020 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6021 optional trailing ! */
6022 OP_RRw, /* ARM register, not r15, optional trailing ! */
6023 OP_RCP, /* Coprocessor number */
6024 OP_RCN, /* Coprocessor register */
6025 OP_RF, /* FPA register */
6026 OP_RVS, /* VFP single precision register */
6027 OP_RVD, /* VFP double precision register (0..15) */
6028 OP_RND, /* Neon double precision register (0..31) */
6029 OP_RNQ, /* Neon quad precision register */
6030 OP_RVSD, /* VFP single or double precision register */
6031 OP_RNDQ, /* Neon double or quad precision register */
6032 OP_RNSDQ, /* Neon single, double or quad precision register */
6033 OP_RNSC, /* Neon scalar D[X] */
6034 OP_RVC, /* VFP control register */
6035 OP_RMF, /* Maverick F register */
6036 OP_RMD, /* Maverick D register */
6037 OP_RMFX, /* Maverick FX register */
6038 OP_RMDX, /* Maverick DX register */
6039 OP_RMAX, /* Maverick AX register */
6040 OP_RMDS, /* Maverick DSPSC register */
6041 OP_RIWR, /* iWMMXt wR register */
6042 OP_RIWC, /* iWMMXt wC register */
6043 OP_RIWG, /* iWMMXt wCG register */
6044 OP_RXA, /* XScale accumulator register */
6046 OP_REGLST, /* ARM register list */
6047 OP_VRSLST, /* VFP single-precision register list */
6048 OP_VRDLST, /* VFP double-precision register list */
6049 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6050 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6051 OP_NSTRLST, /* Neon element/structure list */
6053 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6054 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6055 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6056 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6057 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6058 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6059 OP_VMOV, /* Neon VMOV operands. */
6060 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6061 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6062 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6064 OP_I0, /* immediate zero */
6065 OP_I7, /* immediate value 0 .. 7 */
6066 OP_I15, /* 0 .. 15 */
6067 OP_I16, /* 1 .. 16 */
6068 OP_I16z, /* 0 .. 16 */
6069 OP_I31, /* 0 .. 31 */
6070 OP_I31w, /* 0 .. 31, optional trailing ! */
6071 OP_I32, /* 1 .. 32 */
6072 OP_I32z, /* 0 .. 32 */
6073 OP_I63, /* 0 .. 63 */
6074 OP_I63s, /* -64 .. 63 */
6075 OP_I64, /* 1 .. 64 */
6076 OP_I64z, /* 0 .. 64 */
6077 OP_I255, /* 0 .. 255 */
6079 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6080 OP_I7b, /* 0 .. 7 */
6081 OP_I15b, /* 0 .. 15 */
6082 OP_I31b, /* 0 .. 31 */
6084 OP_SH, /* shifter operand */
6085 OP_SHG, /* shifter operand with possible group relocation */
6086 OP_ADDR, /* Memory address expression (any mode) */
6087 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6088 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6089 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6090 OP_EXP, /* arbitrary expression */
6091 OP_EXPi, /* same, with optional immediate prefix */
6092 OP_EXPr, /* same, with optional relocation suffix */
6093 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6095 OP_CPSF, /* CPS flags */
6096 OP_ENDI, /* Endianness specifier */
6097 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6098 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6099 OP_COND, /* conditional code */
6100 OP_TB, /* Table branch. */
6102 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6104 OP_RRnpc_I0, /* ARM register or literal 0 */
6105 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6106 OP_RR_EXi, /* ARM register or expression with imm prefix */
6107 OP_RF_IF, /* FPA register or immediate */
6108 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6109 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6111 /* Optional operands. */
6112 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6113 OP_oI31b, /* 0 .. 31 */
6114 OP_oI32b, /* 1 .. 32 */
6115 OP_oIffffb, /* 0 .. 65535 */
6116 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6118 OP_oRR, /* ARM register */
6119 OP_oRRnpc, /* ARM register, not the PC */
6120 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6121 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6122 OP_oRND, /* Optional Neon double precision register */
6123 OP_oRNQ, /* Optional Neon quad precision register */
6124 OP_oRNDQ, /* Optional Neon double or quad precision register */
6125 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6126 OP_oSHll, /* LSL immediate */
6127 OP_oSHar, /* ASR immediate */
6128 OP_oSHllar, /* LSL or ASR immediate */
6129 OP_oROR, /* ROR 0/8/16/24 */
6130 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6132 /* Some pre-defined mixed (ARM/THUMB) operands. */
6133 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6134 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6135 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6137 OP_FIRST_OPTIONAL = OP_oI7b
6140 /* Generic instruction operand parser. This does no encoding and no
6141 semantic validation; it merely squirrels values away in the inst
6142 structure. Returns SUCCESS or FAIL depending on whether the
6143 specified grammar matched. */
6145 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6147 unsigned const int *upat = pattern;
6148 char *backtrack_pos = 0;
6149 const char *backtrack_error = 0;
6150 int i, val, backtrack_index = 0;
6151 enum arm_reg_type rtype;
6152 parse_operand_result result;
6153 unsigned int op_parse_code;
6155 #define po_char_or_fail(chr) \
6158 if (skip_past_char (&str, chr) == FAIL) \
6163 #define po_reg_or_fail(regtype) \
6166 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6167 & inst.operands[i].vectype); \
6170 first_error (_(reg_expected_msgs[regtype])); \
6173 inst.operands[i].reg = val; \
6174 inst.operands[i].isreg = 1; \
6175 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6176 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6177 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6178 || rtype == REG_TYPE_VFD \
6179 || rtype == REG_TYPE_NQ); \
6183 #define po_reg_or_goto(regtype, label) \
6186 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6187 & inst.operands[i].vectype); \
6191 inst.operands[i].reg = val; \
6192 inst.operands[i].isreg = 1; \
6193 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6194 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6195 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6196 || rtype == REG_TYPE_VFD \
6197 || rtype == REG_TYPE_NQ); \
6201 #define po_imm_or_fail(min, max, popt) \
6204 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6206 inst.operands[i].imm = val; \
6210 #define po_scalar_or_goto(elsz, label) \
6213 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6216 inst.operands[i].reg = val; \
6217 inst.operands[i].isscalar = 1; \
6221 #define po_misc_or_fail(expr) \
6229 #define po_misc_or_fail_no_backtrack(expr) \
6233 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6234 backtrack_pos = 0; \
6235 if (result != PARSE_OPERAND_SUCCESS) \
6240 #define po_barrier_or_imm(str) \
6243 val = parse_barrier (&str); \
6246 if (ISALPHA (*str)) \
6253 if ((inst.instruction & 0xf0) == 0x60 \
6256 /* ISB can only take SY as an option. */ \
6257 inst.error = _("invalid barrier type"); \
6264 skip_whitespace (str);
6266 for (i = 0; upat[i] != OP_stop; i++)
6268 op_parse_code = upat[i];
6269 if (op_parse_code >= 1<<16)
6270 op_parse_code = thumb ? (op_parse_code >> 16)
6271 : (op_parse_code & ((1<<16)-1));
6273 if (op_parse_code >= OP_FIRST_OPTIONAL)
6275 /* Remember where we are in case we need to backtrack. */
6276 gas_assert (!backtrack_pos);
6277 backtrack_pos = str;
6278 backtrack_error = inst.error;
6279 backtrack_index = i;
6282 if (i > 0 && (i > 1 || inst.operands[0].present))
6283 po_char_or_fail (',');
6285 switch (op_parse_code)
6293 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6294 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6295 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6296 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6297 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6298 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6300 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6302 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6304 /* Also accept generic coprocessor regs for unknown registers. */
6306 po_reg_or_fail (REG_TYPE_CN);
6308 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6309 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6310 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6311 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6312 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6313 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6314 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6315 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6316 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6317 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6319 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6321 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6322 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6324 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6326 /* Neon scalar. Using an element size of 8 means that some invalid
6327 scalars are accepted here, so deal with those in later code. */
6328 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6332 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6335 po_imm_or_fail (0, 0, TRUE);
6340 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6345 po_scalar_or_goto (8, try_rr);
6348 po_reg_or_fail (REG_TYPE_RN);
6354 po_scalar_or_goto (8, try_nsdq);
6357 po_reg_or_fail (REG_TYPE_NSDQ);
6363 po_scalar_or_goto (8, try_ndq);
6366 po_reg_or_fail (REG_TYPE_NDQ);
6372 po_scalar_or_goto (8, try_vfd);
6375 po_reg_or_fail (REG_TYPE_VFD);
6380 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6381 not careful then bad things might happen. */
6382 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6387 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6390 /* There's a possibility of getting a 64-bit immediate here, so
6391 we need special handling. */
6392 if (parse_big_immediate (&str, i) == FAIL)
6394 inst.error = _("immediate value is out of range");
6402 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6405 po_imm_or_fail (0, 63, TRUE);
6410 po_char_or_fail ('[');
6411 po_reg_or_fail (REG_TYPE_RN);
6412 po_char_or_fail (']');
6418 po_reg_or_fail (REG_TYPE_RN);
6419 if (skip_past_char (&str, '!') == SUCCESS)
6420 inst.operands[i].writeback = 1;
6424 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6425 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6426 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6427 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6428 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6429 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6430 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6431 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6432 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6433 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6434 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6435 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6437 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6439 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6440 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6442 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6443 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6444 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6446 /* Immediate variants */
6448 po_char_or_fail ('{');
6449 po_imm_or_fail (0, 255, TRUE);
6450 po_char_or_fail ('}');
6454 /* The expression parser chokes on a trailing !, so we have
6455 to find it first and zap it. */
6458 while (*s && *s != ',')
6463 inst.operands[i].writeback = 1;
6465 po_imm_or_fail (0, 31, TRUE);
6473 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6478 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6483 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6485 if (inst.reloc.exp.X_op == O_symbol)
6487 val = parse_reloc (&str);
6490 inst.error = _("unrecognized relocation suffix");
6493 else if (val != BFD_RELOC_UNUSED)
6495 inst.operands[i].imm = val;
6496 inst.operands[i].hasreloc = 1;
6501 /* Operand for MOVW or MOVT. */
6503 po_misc_or_fail (parse_half (&str));
6506 /* Register or expression. */
6507 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6508 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6510 /* Register or immediate. */
6511 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6512 I0: po_imm_or_fail (0, 0, FALSE); break;
6514 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6516 if (!is_immediate_prefix (*str))
6519 val = parse_fpa_immediate (&str);
6522 /* FPA immediates are encoded as registers 8-15.
6523 parse_fpa_immediate has already applied the offset. */
6524 inst.operands[i].reg = val;
6525 inst.operands[i].isreg = 1;
6528 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6529 I32z: po_imm_or_fail (0, 32, FALSE); break;
6531 /* Two kinds of register. */
6534 struct reg_entry *rege = arm_reg_parse_multi (&str);
6536 || (rege->type != REG_TYPE_MMXWR
6537 && rege->type != REG_TYPE_MMXWC
6538 && rege->type != REG_TYPE_MMXWCG))
6540 inst.error = _("iWMMXt data or control register expected");
6543 inst.operands[i].reg = rege->number;
6544 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6550 struct reg_entry *rege = arm_reg_parse_multi (&str);
6552 || (rege->type != REG_TYPE_MMXWC
6553 && rege->type != REG_TYPE_MMXWCG))
6555 inst.error = _("iWMMXt control register expected");
6558 inst.operands[i].reg = rege->number;
6559 inst.operands[i].isreg = 1;
6564 case OP_CPSF: val = parse_cps_flags (&str); break;
6565 case OP_ENDI: val = parse_endian_specifier (&str); break;
6566 case OP_oROR: val = parse_ror (&str); break;
6567 case OP_COND: val = parse_cond (&str); break;
6568 case OP_oBARRIER_I15:
6569 po_barrier_or_imm (str); break;
6571 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6577 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6578 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6580 inst.error = _("Banked registers are not available with this "
6586 val = parse_psr (&str, op_parse_code == OP_wPSR);
6590 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6593 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6595 if (strncasecmp (str, "APSR_", 5) == 0)
6602 case 'c': found = (found & 1) ? 16 : found | 1; break;
6603 case 'n': found = (found & 2) ? 16 : found | 2; break;
6604 case 'z': found = (found & 4) ? 16 : found | 4; break;
6605 case 'v': found = (found & 8) ? 16 : found | 8; break;
6606 default: found = 16;
6610 inst.operands[i].isvec = 1;
6611 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6612 inst.operands[i].reg = REG_PC;
6619 po_misc_or_fail (parse_tb (&str));
6622 /* Register lists. */
6624 val = parse_reg_list (&str);
6627 inst.operands[1].writeback = 1;
6633 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6637 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6641 /* Allow Q registers too. */
6642 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6647 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6649 inst.operands[i].issingle = 1;
6654 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6659 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6660 &inst.operands[i].vectype);
6663 /* Addressing modes */
6665 po_misc_or_fail (parse_address (&str, i));
6669 po_misc_or_fail_no_backtrack (
6670 parse_address_group_reloc (&str, i, GROUP_LDR));
6674 po_misc_or_fail_no_backtrack (
6675 parse_address_group_reloc (&str, i, GROUP_LDRS));
6679 po_misc_or_fail_no_backtrack (
6680 parse_address_group_reloc (&str, i, GROUP_LDC));
6684 po_misc_or_fail (parse_shifter_operand (&str, i));
6688 po_misc_or_fail_no_backtrack (
6689 parse_shifter_operand_group_reloc (&str, i));
6693 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6697 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6701 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6705 as_fatal (_("unhandled operand code %d"), op_parse_code);
6708 /* Various value-based sanity checks and shared operations. We
6709 do not signal immediate failures for the register constraints;
6710 this allows a syntax error to take precedence. */
6711 switch (op_parse_code)
6719 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6720 inst.error = BAD_PC;
6725 if (inst.operands[i].isreg)
6727 if (inst.operands[i].reg == REG_PC)
6728 inst.error = BAD_PC;
6729 else if (inst.operands[i].reg == REG_SP)
6730 inst.error = BAD_SP;
6735 if (inst.operands[i].isreg
6736 && inst.operands[i].reg == REG_PC
6737 && (inst.operands[i].writeback || thumb))
6738 inst.error = BAD_PC;
6747 case OP_oBARRIER_I15:
6756 inst.operands[i].imm = val;
6763 /* If we get here, this operand was successfully parsed. */
6764 inst.operands[i].present = 1;
6768 inst.error = BAD_ARGS;
6773 /* The parse routine should already have set inst.error, but set a
6774 default here just in case. */
6776 inst.error = _("syntax error");
6780 /* Do not backtrack over a trailing optional argument that
6781 absorbed some text. We will only fail again, with the
6782 'garbage following instruction' error message, which is
6783 probably less helpful than the current one. */
6784 if (backtrack_index == i && backtrack_pos != str
6785 && upat[i+1] == OP_stop)
6788 inst.error = _("syntax error");
6792 /* Try again, skipping the optional argument at backtrack_pos. */
6793 str = backtrack_pos;
6794 inst.error = backtrack_error;
6795 inst.operands[backtrack_index].present = 0;
6796 i = backtrack_index;
6800 /* Check that we have parsed all the arguments. */
6801 if (*str != '\0' && !inst.error)
6802 inst.error = _("garbage following instruction");
6804 return inst.error ? FAIL : SUCCESS;
6807 #undef po_char_or_fail
6808 #undef po_reg_or_fail
6809 #undef po_reg_or_goto
6810 #undef po_imm_or_fail
6811 #undef po_scalar_or_fail
6812 #undef po_barrier_or_imm
6814 /* Shorthand macro for instruction encoding functions issuing errors. */
6815 #define constraint(expr, err) \
6826 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6827 instructions are unpredictable if these registers are used. This
6828 is the BadReg predicate in ARM's Thumb-2 documentation. */
6829 #define reject_bad_reg(reg) \
6831 if (reg == REG_SP || reg == REG_PC) \
6833 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6838 /* If REG is R13 (the stack pointer), warn that its use is
6840 #define warn_deprecated_sp(reg) \
6842 if (warn_on_deprecated && reg == REG_SP) \
6843 as_warn (_("use of r13 is deprecated")); \
6846 /* Functions for operand encoding. ARM, then Thumb. */
6848 #define rotate_left(v, n) (v << n | v >> (32 - n))
6850 /* If VAL can be encoded in the immediate field of an ARM instruction,
6851 return the encoded form. Otherwise, return FAIL. */
6854 encode_arm_immediate (unsigned int val)
6858 for (i = 0; i < 32; i += 2)
6859 if ((a = rotate_left (val, i)) <= 0xff)
6860 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6865 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6866 return the encoded form. Otherwise, return FAIL. */
6868 encode_thumb32_immediate (unsigned int val)
6875 for (i = 1; i <= 24; i++)
6878 if ((val & ~(0xff << i)) == 0)
6879 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6883 if (val == ((a << 16) | a))
6885 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6889 if (val == ((a << 16) | a))
6890 return 0x200 | (a >> 8);
6894 /* Encode a VFP SP or DP register number into inst.instruction. */
6897 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6899 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6902 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6905 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6908 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6913 first_error (_("D register out of range for selected VFP version"));
6921 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6925 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6929 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6933 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6937 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6941 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6949 /* Encode a <shift> in an ARM-format instruction. The immediate,
6950 if any, is handled by md_apply_fix. */
6952 encode_arm_shift (int i)
6954 if (inst.operands[i].shift_kind == SHIFT_RRX)
6955 inst.instruction |= SHIFT_ROR << 5;
6958 inst.instruction |= inst.operands[i].shift_kind << 5;
6959 if (inst.operands[i].immisreg)
6961 inst.instruction |= SHIFT_BY_REG;
6962 inst.instruction |= inst.operands[i].imm << 8;
6965 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6970 encode_arm_shifter_operand (int i)
6972 if (inst.operands[i].isreg)
6974 inst.instruction |= inst.operands[i].reg;
6975 encode_arm_shift (i);
6978 inst.instruction |= INST_IMMEDIATE;
6981 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6983 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
6985 gas_assert (inst.operands[i].isreg);
6986 inst.instruction |= inst.operands[i].reg << 16;
6988 if (inst.operands[i].preind)
6992 inst.error = _("instruction does not accept preindexed addressing");
6995 inst.instruction |= PRE_INDEX;
6996 if (inst.operands[i].writeback)
6997 inst.instruction |= WRITE_BACK;
7000 else if (inst.operands[i].postind)
7002 gas_assert (inst.operands[i].writeback);
7004 inst.instruction |= WRITE_BACK;
7006 else /* unindexed - only for coprocessor */
7008 inst.error = _("instruction does not accept unindexed addressing");
7012 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7013 && (((inst.instruction & 0x000f0000) >> 16)
7014 == ((inst.instruction & 0x0000f000) >> 12)))
7015 as_warn ((inst.instruction & LOAD_BIT)
7016 ? _("destination register same as write-back base")
7017 : _("source register same as write-back base"));
7020 /* inst.operands[i] was set up by parse_address. Encode it into an
7021 ARM-format mode 2 load or store instruction. If is_t is true,
7022 reject forms that cannot be used with a T instruction (i.e. not
7025 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7027 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7029 encode_arm_addr_mode_common (i, is_t);
7031 if (inst.operands[i].immisreg)
7033 constraint ((inst.operands[i].imm == REG_PC
7034 || (is_pc && inst.operands[i].writeback)),
7036 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7037 inst.instruction |= inst.operands[i].imm;
7038 if (!inst.operands[i].negative)
7039 inst.instruction |= INDEX_UP;
7040 if (inst.operands[i].shifted)
7042 if (inst.operands[i].shift_kind == SHIFT_RRX)
7043 inst.instruction |= SHIFT_ROR << 5;
7046 inst.instruction |= inst.operands[i].shift_kind << 5;
7047 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7051 else /* immediate offset in inst.reloc */
7053 if (is_pc && !inst.reloc.pc_rel)
7055 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7057 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7058 cannot use PC in addressing.
7059 PC cannot be used in writeback addressing, either. */
7060 constraint ((is_t || inst.operands[i].writeback),
7063 /* Use of PC in str is deprecated for ARMv7. */
7064 if (warn_on_deprecated
7066 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7067 as_warn (_("use of PC in this instruction is deprecated"));
7070 if (inst.reloc.type == BFD_RELOC_UNUSED)
7072 /* Prefer + for zero encoded value. */
7073 if (!inst.operands[i].negative)
7074 inst.instruction |= INDEX_UP;
7075 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7080 /* inst.operands[i] was set up by parse_address. Encode it into an
7081 ARM-format mode 3 load or store instruction. Reject forms that
7082 cannot be used with such instructions. If is_t is true, reject
7083 forms that cannot be used with a T instruction (i.e. not
7086 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7088 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7090 inst.error = _("instruction does not accept scaled register index");
7094 encode_arm_addr_mode_common (i, is_t);
7096 if (inst.operands[i].immisreg)
7098 constraint ((inst.operands[i].imm == REG_PC
7099 || inst.operands[i].reg == REG_PC),
7101 inst.instruction |= inst.operands[i].imm;
7102 if (!inst.operands[i].negative)
7103 inst.instruction |= INDEX_UP;
7105 else /* immediate offset in inst.reloc */
7107 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7108 && inst.operands[i].writeback),
7110 inst.instruction |= HWOFFSET_IMM;
7111 if (inst.reloc.type == BFD_RELOC_UNUSED)
7113 /* Prefer + for zero encoded value. */
7114 if (!inst.operands[i].negative)
7115 inst.instruction |= INDEX_UP;
7117 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7122 /* inst.operands[i] was set up by parse_address. Encode it into an
7123 ARM-format instruction. Reject all forms which cannot be encoded
7124 into a coprocessor load/store instruction. If wb_ok is false,
7125 reject use of writeback; if unind_ok is false, reject use of
7126 unindexed addressing. If reloc_override is not 0, use it instead
7127 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7128 (in which case it is preserved). */
7131 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7133 inst.instruction |= inst.operands[i].reg << 16;
7135 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7137 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7139 gas_assert (!inst.operands[i].writeback);
7142 inst.error = _("instruction does not support unindexed addressing");
7145 inst.instruction |= inst.operands[i].imm;
7146 inst.instruction |= INDEX_UP;
7150 if (inst.operands[i].preind)
7151 inst.instruction |= PRE_INDEX;
7153 if (inst.operands[i].writeback)
7155 if (inst.operands[i].reg == REG_PC)
7157 inst.error = _("pc may not be used with write-back");
7162 inst.error = _("instruction does not support writeback");
7165 inst.instruction |= WRITE_BACK;
7169 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7170 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7171 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7172 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7175 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7177 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7180 /* Prefer + for zero encoded value. */
7181 if (!inst.operands[i].negative)
7182 inst.instruction |= INDEX_UP;
7187 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7188 Determine whether it can be performed with a move instruction; if
7189 it can, convert inst.instruction to that move instruction and
7190 return TRUE; if it can't, convert inst.instruction to a literal-pool
7191 load and return FALSE. If this is not a valid thing to do in the
7192 current context, set inst.error and return TRUE.
7194 inst.operands[i] describes the destination register. */
7197 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7202 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7206 if ((inst.instruction & tbit) == 0)
7208 inst.error = _("invalid pseudo operation");
7211 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7213 inst.error = _("constant expression expected");
7216 if (inst.reloc.exp.X_op == O_constant)
7220 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7222 /* This can be done with a mov(1) instruction. */
7223 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7224 inst.instruction |= inst.reloc.exp.X_add_number;
7230 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7233 /* This can be done with a mov instruction. */
7234 inst.instruction &= LITERAL_MASK;
7235 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7236 inst.instruction |= value & 0xfff;
7240 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7243 /* This can be done with a mvn instruction. */
7244 inst.instruction &= LITERAL_MASK;
7245 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7246 inst.instruction |= value & 0xfff;
7252 if (add_to_lit_pool () == FAIL)
7254 inst.error = _("literal pool insertion failed");
7257 inst.operands[1].reg = REG_PC;
7258 inst.operands[1].isreg = 1;
7259 inst.operands[1].preind = 1;
7260 inst.reloc.pc_rel = 1;
7261 inst.reloc.type = (thumb_p
7262 ? BFD_RELOC_ARM_THUMB_OFFSET
7264 ? BFD_RELOC_ARM_HWLITERAL
7265 : BFD_RELOC_ARM_LITERAL));
7269 /* Functions for instruction encoding, sorted by sub-architecture.
7270 First some generics; their names are taken from the conventional
7271 bit positions for register arguments in ARM format instructions. */
7281 inst.instruction |= inst.operands[0].reg << 12;
7287 inst.instruction |= inst.operands[0].reg << 12;
7288 inst.instruction |= inst.operands[1].reg;
7294 inst.instruction |= inst.operands[0].reg << 12;
7295 inst.instruction |= inst.operands[1].reg << 16;
7301 inst.instruction |= inst.operands[0].reg << 16;
7302 inst.instruction |= inst.operands[1].reg << 12;
7308 unsigned Rn = inst.operands[2].reg;
7309 /* Enforce restrictions on SWP instruction. */
7310 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7312 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7313 _("Rn must not overlap other operands"));
7315 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7316 if (warn_on_deprecated
7317 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7318 as_warn (_("swp{b} use is deprecated for this architecture"));
7321 inst.instruction |= inst.operands[0].reg << 12;
7322 inst.instruction |= inst.operands[1].reg;
7323 inst.instruction |= Rn << 16;
7329 inst.instruction |= inst.operands[0].reg << 12;
7330 inst.instruction |= inst.operands[1].reg << 16;
7331 inst.instruction |= inst.operands[2].reg;
7337 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7338 constraint (((inst.reloc.exp.X_op != O_constant
7339 && inst.reloc.exp.X_op != O_illegal)
7340 || inst.reloc.exp.X_add_number != 0),
7342 inst.instruction |= inst.operands[0].reg;
7343 inst.instruction |= inst.operands[1].reg << 12;
7344 inst.instruction |= inst.operands[2].reg << 16;
7350 inst.instruction |= inst.operands[0].imm;
7356 inst.instruction |= inst.operands[0].reg << 12;
7357 encode_arm_cp_address (1, TRUE, TRUE, 0);
7360 /* ARM instructions, in alphabetical order by function name (except
7361 that wrapper functions appear immediately after the function they
7364 /* This is a pseudo-op of the form "adr rd, label" to be converted
7365 into a relative address of the form "add rd, pc, #label-.-8". */
7370 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7372 /* Frag hacking will turn this into a sub instruction if the offset turns
7373 out to be negative. */
7374 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7375 inst.reloc.pc_rel = 1;
7376 inst.reloc.exp.X_add_number -= 8;
7379 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7380 into a relative address of the form:
7381 add rd, pc, #low(label-.-8)"
7382 add rd, rd, #high(label-.-8)" */
7387 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7389 /* Frag hacking will turn this into a sub instruction if the offset turns
7390 out to be negative. */
7391 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7392 inst.reloc.pc_rel = 1;
7393 inst.size = INSN_SIZE * 2;
7394 inst.reloc.exp.X_add_number -= 8;
7400 if (!inst.operands[1].present)
7401 inst.operands[1].reg = inst.operands[0].reg;
7402 inst.instruction |= inst.operands[0].reg << 12;
7403 inst.instruction |= inst.operands[1].reg << 16;
7404 encode_arm_shifter_operand (2);
7410 if (inst.operands[0].present)
7412 constraint ((inst.instruction & 0xf0) != 0x40
7413 && inst.operands[0].imm > 0xf
7414 && inst.operands[0].imm < 0x0,
7415 _("bad barrier type"));
7416 inst.instruction |= inst.operands[0].imm;
7419 inst.instruction |= 0xf;
7425 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7426 constraint (msb > 32, _("bit-field extends past end of register"));
7427 /* The instruction encoding stores the LSB and MSB,
7428 not the LSB and width. */
7429 inst.instruction |= inst.operands[0].reg << 12;
7430 inst.instruction |= inst.operands[1].imm << 7;
7431 inst.instruction |= (msb - 1) << 16;
7439 /* #0 in second position is alternative syntax for bfc, which is
7440 the same instruction but with REG_PC in the Rm field. */
7441 if (!inst.operands[1].isreg)
7442 inst.operands[1].reg = REG_PC;
7444 msb = inst.operands[2].imm + inst.operands[3].imm;
7445 constraint (msb > 32, _("bit-field extends past end of register"));
7446 /* The instruction encoding stores the LSB and MSB,
7447 not the LSB and width. */
7448 inst.instruction |= inst.operands[0].reg << 12;
7449 inst.instruction |= inst.operands[1].reg;
7450 inst.instruction |= inst.operands[2].imm << 7;
7451 inst.instruction |= (msb - 1) << 16;
7457 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7458 _("bit-field extends past end of register"));
7459 inst.instruction |= inst.operands[0].reg << 12;
7460 inst.instruction |= inst.operands[1].reg;
7461 inst.instruction |= inst.operands[2].imm << 7;
7462 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7465 /* ARM V5 breakpoint instruction (argument parse)
7466 BKPT <16 bit unsigned immediate>
7467 Instruction is not conditional.
7468 The bit pattern given in insns[] has the COND_ALWAYS condition,
7469 and it is an error if the caller tried to override that. */
7474 /* Top 12 of 16 bits to bits 19:8. */
7475 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7477 /* Bottom 4 of 16 bits to bits 3:0. */
7478 inst.instruction |= inst.operands[0].imm & 0xf;
7482 encode_branch (int default_reloc)
7484 if (inst.operands[0].hasreloc)
7486 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7487 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7488 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7489 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7490 ? BFD_RELOC_ARM_PLT32
7491 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7494 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7495 inst.reloc.pc_rel = 1;
7502 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7503 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7506 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7513 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7515 if (inst.cond == COND_ALWAYS)
7516 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7518 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7522 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7525 /* ARM V5 branch-link-exchange instruction (argument parse)
7526 BLX <target_addr> ie BLX(1)
7527 BLX{<condition>} <Rm> ie BLX(2)
7528 Unfortunately, there are two different opcodes for this mnemonic.
7529 So, the insns[].value is not used, and the code here zaps values
7530 into inst.instruction.
7531 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7536 if (inst.operands[0].isreg)
7538 /* Arg is a register; the opcode provided by insns[] is correct.
7539 It is not illegal to do "blx pc", just useless. */
7540 if (inst.operands[0].reg == REG_PC)
7541 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7543 inst.instruction |= inst.operands[0].reg;
7547 /* Arg is an address; this instruction cannot be executed
7548 conditionally, and the opcode must be adjusted.
7549 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7550 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7551 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7552 inst.instruction = 0xfa000000;
7553 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7560 bfd_boolean want_reloc;
7562 if (inst.operands[0].reg == REG_PC)
7563 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7565 inst.instruction |= inst.operands[0].reg;
7566 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7567 it is for ARMv4t or earlier. */
7568 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7569 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7573 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7578 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7582 /* ARM v5TEJ. Jump to Jazelle code. */
7587 if (inst.operands[0].reg == REG_PC)
7588 as_tsktsk (_("use of r15 in bxj is not really useful"));
7590 inst.instruction |= inst.operands[0].reg;
7593 /* Co-processor data operation:
7594 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7595 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7599 inst.instruction |= inst.operands[0].reg << 8;
7600 inst.instruction |= inst.operands[1].imm << 20;
7601 inst.instruction |= inst.operands[2].reg << 12;
7602 inst.instruction |= inst.operands[3].reg << 16;
7603 inst.instruction |= inst.operands[4].reg;
7604 inst.instruction |= inst.operands[5].imm << 5;
7610 inst.instruction |= inst.operands[0].reg << 16;
7611 encode_arm_shifter_operand (1);
7614 /* Transfer between coprocessor and ARM registers.
7615 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7620 No special properties. */
7627 Rd = inst.operands[2].reg;
7630 if (inst.instruction == 0xee000010
7631 || inst.instruction == 0xfe000010)
7633 reject_bad_reg (Rd);
7636 constraint (Rd == REG_SP, BAD_SP);
7641 if (inst.instruction == 0xe000010)
7642 constraint (Rd == REG_PC, BAD_PC);
7646 inst.instruction |= inst.operands[0].reg << 8;
7647 inst.instruction |= inst.operands[1].imm << 21;
7648 inst.instruction |= Rd << 12;
7649 inst.instruction |= inst.operands[3].reg << 16;
7650 inst.instruction |= inst.operands[4].reg;
7651 inst.instruction |= inst.operands[5].imm << 5;
7654 /* Transfer between coprocessor register and pair of ARM registers.
7655 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7660 Two XScale instructions are special cases of these:
7662 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7663 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7665 Result unpredictable if Rd or Rn is R15. */
7672 Rd = inst.operands[2].reg;
7673 Rn = inst.operands[3].reg;
7677 reject_bad_reg (Rd);
7678 reject_bad_reg (Rn);
7682 constraint (Rd == REG_PC, BAD_PC);
7683 constraint (Rn == REG_PC, BAD_PC);
7686 inst.instruction |= inst.operands[0].reg << 8;
7687 inst.instruction |= inst.operands[1].imm << 4;
7688 inst.instruction |= Rd << 12;
7689 inst.instruction |= Rn << 16;
7690 inst.instruction |= inst.operands[4].reg;
7696 inst.instruction |= inst.operands[0].imm << 6;
7697 if (inst.operands[1].present)
7699 inst.instruction |= CPSI_MMOD;
7700 inst.instruction |= inst.operands[1].imm;
7707 inst.instruction |= inst.operands[0].imm;
7713 unsigned Rd, Rn, Rm;
7715 Rd = inst.operands[0].reg;
7716 Rn = (inst.operands[1].present
7717 ? inst.operands[1].reg : Rd);
7718 Rm = inst.operands[2].reg;
7720 constraint ((Rd == REG_PC), BAD_PC);
7721 constraint ((Rn == REG_PC), BAD_PC);
7722 constraint ((Rm == REG_PC), BAD_PC);
7724 inst.instruction |= Rd << 16;
7725 inst.instruction |= Rn << 0;
7726 inst.instruction |= Rm << 8;
7732 /* There is no IT instruction in ARM mode. We
7733 process it to do the validation as if in
7734 thumb mode, just in case the code gets
7735 assembled for thumb using the unified syntax. */
7740 set_it_insn_type (IT_INSN);
7741 now_it.mask = (inst.instruction & 0xf) | 0x10;
7742 now_it.cc = inst.operands[0].imm;
7749 int base_reg = inst.operands[0].reg;
7750 int range = inst.operands[1].imm;
7752 inst.instruction |= base_reg << 16;
7753 inst.instruction |= range;
7755 if (inst.operands[1].writeback)
7756 inst.instruction |= LDM_TYPE_2_OR_3;
7758 if (inst.operands[0].writeback)
7760 inst.instruction |= WRITE_BACK;
7761 /* Check for unpredictable uses of writeback. */
7762 if (inst.instruction & LOAD_BIT)
7764 /* Not allowed in LDM type 2. */
7765 if ((inst.instruction & LDM_TYPE_2_OR_3)
7766 && ((range & (1 << REG_PC)) == 0))
7767 as_warn (_("writeback of base register is UNPREDICTABLE"));
7768 /* Only allowed if base reg not in list for other types. */
7769 else if (range & (1 << base_reg))
7770 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7774 /* Not allowed for type 2. */
7775 if (inst.instruction & LDM_TYPE_2_OR_3)
7776 as_warn (_("writeback of base register is UNPREDICTABLE"));
7777 /* Only allowed if base reg not in list, or first in list. */
7778 else if ((range & (1 << base_reg))
7779 && (range & ((1 << base_reg) - 1)))
7780 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7785 /* ARMv5TE load-consecutive (argument parse)
7794 constraint (inst.operands[0].reg % 2 != 0,
7795 _("first destination register must be even"));
7796 constraint (inst.operands[1].present
7797 && inst.operands[1].reg != inst.operands[0].reg + 1,
7798 _("can only load two consecutive registers"));
7799 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7800 constraint (!inst.operands[2].isreg, _("'[' expected"));
7802 if (!inst.operands[1].present)
7803 inst.operands[1].reg = inst.operands[0].reg + 1;
7805 if (inst.instruction & LOAD_BIT)
7807 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7808 register and the first register written; we have to diagnose
7809 overlap between the base and the second register written here. */
7811 if (inst.operands[2].reg == inst.operands[1].reg
7812 && (inst.operands[2].writeback || inst.operands[2].postind))
7813 as_warn (_("base register written back, and overlaps "
7814 "second destination register"));
7816 /* For an index-register load, the index register must not overlap the
7817 destination (even if not write-back). */
7818 else if (inst.operands[2].immisreg
7819 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7820 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7821 as_warn (_("index register overlaps destination register"));
7824 inst.instruction |= inst.operands[0].reg << 12;
7825 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7831 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7832 || inst.operands[1].postind || inst.operands[1].writeback
7833 || inst.operands[1].immisreg || inst.operands[1].shifted
7834 || inst.operands[1].negative
7835 /* This can arise if the programmer has written
7837 or if they have mistakenly used a register name as the last
7840 It is very difficult to distinguish between these two cases
7841 because "rX" might actually be a label. ie the register
7842 name has been occluded by a symbol of the same name. So we
7843 just generate a general 'bad addressing mode' type error
7844 message and leave it up to the programmer to discover the
7845 true cause and fix their mistake. */
7846 || (inst.operands[1].reg == REG_PC),
7849 constraint (inst.reloc.exp.X_op != O_constant
7850 || inst.reloc.exp.X_add_number != 0,
7851 _("offset must be zero in ARM encoding"));
7853 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7855 inst.instruction |= inst.operands[0].reg << 12;
7856 inst.instruction |= inst.operands[1].reg << 16;
7857 inst.reloc.type = BFD_RELOC_UNUSED;
7863 constraint (inst.operands[0].reg % 2 != 0,
7864 _("even register required"));
7865 constraint (inst.operands[1].present
7866 && inst.operands[1].reg != inst.operands[0].reg + 1,
7867 _("can only load two consecutive registers"));
7868 /* If op 1 were present and equal to PC, this function wouldn't
7869 have been called in the first place. */
7870 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7872 inst.instruction |= inst.operands[0].reg << 12;
7873 inst.instruction |= inst.operands[2].reg << 16;
7879 inst.instruction |= inst.operands[0].reg << 12;
7880 if (!inst.operands[1].isreg)
7881 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
7883 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
7889 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7891 if (inst.operands[1].preind)
7893 constraint (inst.reloc.exp.X_op != O_constant
7894 || inst.reloc.exp.X_add_number != 0,
7895 _("this instruction requires a post-indexed address"));
7897 inst.operands[1].preind = 0;
7898 inst.operands[1].postind = 1;
7899 inst.operands[1].writeback = 1;
7901 inst.instruction |= inst.operands[0].reg << 12;
7902 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7905 /* Halfword and signed-byte load/store operations. */
7910 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
7911 inst.instruction |= inst.operands[0].reg << 12;
7912 if (!inst.operands[1].isreg)
7913 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
7915 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
7921 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7923 if (inst.operands[1].preind)
7925 constraint (inst.reloc.exp.X_op != O_constant
7926 || inst.reloc.exp.X_add_number != 0,
7927 _("this instruction requires a post-indexed address"));
7929 inst.operands[1].preind = 0;
7930 inst.operands[1].postind = 1;
7931 inst.operands[1].writeback = 1;
7933 inst.instruction |= inst.operands[0].reg << 12;
7934 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7937 /* Co-processor register load/store.
7938 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7942 inst.instruction |= inst.operands[0].reg << 8;
7943 inst.instruction |= inst.operands[1].reg << 12;
7944 encode_arm_cp_address (2, TRUE, TRUE, 0);
7950 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7951 if (inst.operands[0].reg == inst.operands[1].reg
7952 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
7953 && !(inst.instruction & 0x00400000))
7954 as_tsktsk (_("Rd and Rm should be different in mla"));
7956 inst.instruction |= inst.operands[0].reg << 16;
7957 inst.instruction |= inst.operands[1].reg;
7958 inst.instruction |= inst.operands[2].reg << 8;
7959 inst.instruction |= inst.operands[3].reg << 12;
7965 inst.instruction |= inst.operands[0].reg << 12;
7966 encode_arm_shifter_operand (1);
7969 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7976 top = (inst.instruction & 0x00400000) != 0;
7977 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
7978 _(":lower16: not allowed this instruction"));
7979 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
7980 _(":upper16: not allowed instruction"));
7981 inst.instruction |= inst.operands[0].reg << 12;
7982 if (inst.reloc.type == BFD_RELOC_UNUSED)
7984 imm = inst.reloc.exp.X_add_number;
7985 /* The value is in two pieces: 0:11, 16:19. */
7986 inst.instruction |= (imm & 0x00000fff);
7987 inst.instruction |= (imm & 0x0000f000) << 4;
7991 static void do_vfp_nsyn_opcode (const char *);
7994 do_vfp_nsyn_mrs (void)
7996 if (inst.operands[0].isvec)
7998 if (inst.operands[1].reg != 1)
7999 first_error (_("operand 1 must be FPSCR"));
8000 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8001 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8002 do_vfp_nsyn_opcode ("fmstat");
8004 else if (inst.operands[1].isvec)
8005 do_vfp_nsyn_opcode ("fmrx");
8013 do_vfp_nsyn_msr (void)
8015 if (inst.operands[0].isvec)
8016 do_vfp_nsyn_opcode ("fmxr");
8026 unsigned Rt = inst.operands[0].reg;
8028 if (thumb_mode && inst.operands[0].reg == REG_SP)
8030 inst.error = BAD_SP;
8034 /* APSR_ sets isvec. All other refs to PC are illegal. */
8035 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8037 inst.error = BAD_PC;
8041 if (inst.operands[1].reg != 1)
8042 first_error (_("operand 1 must be FPSCR"));
8044 inst.instruction |= (Rt << 12);
8050 unsigned Rt = inst.operands[1].reg;
8053 reject_bad_reg (Rt);
8054 else if (Rt == REG_PC)
8056 inst.error = BAD_PC;
8060 if (inst.operands[0].reg != 1)
8061 first_error (_("operand 0 must be FPSCR"));
8063 inst.instruction |= (Rt << 12);
8071 if (do_vfp_nsyn_mrs () == SUCCESS)
8074 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8075 inst.instruction |= inst.operands[0].reg << 12;
8077 if (inst.operands[1].isreg)
8079 br = inst.operands[1].reg;
8080 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8081 as_bad (_("bad register for mrs"));
8085 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8086 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8088 _("'APSR', 'CPSR' or 'SPSR' expected"));
8089 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8092 inst.instruction |= br;
8095 /* Two possible forms:
8096 "{C|S}PSR_<field>, Rm",
8097 "{C|S}PSR_f, #expression". */
8102 if (do_vfp_nsyn_msr () == SUCCESS)
8105 inst.instruction |= inst.operands[0].imm;
8106 if (inst.operands[1].isreg)
8107 inst.instruction |= inst.operands[1].reg;
8110 inst.instruction |= INST_IMMEDIATE;
8111 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8112 inst.reloc.pc_rel = 0;
8119 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8121 if (!inst.operands[2].present)
8122 inst.operands[2].reg = inst.operands[0].reg;
8123 inst.instruction |= inst.operands[0].reg << 16;
8124 inst.instruction |= inst.operands[1].reg;
8125 inst.instruction |= inst.operands[2].reg << 8;
8127 if (inst.operands[0].reg == inst.operands[1].reg
8128 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8129 as_tsktsk (_("Rd and Rm should be different in mul"));
8132 /* Long Multiply Parser
8133 UMULL RdLo, RdHi, Rm, Rs
8134 SMULL RdLo, RdHi, Rm, Rs
8135 UMLAL RdLo, RdHi, Rm, Rs
8136 SMLAL RdLo, RdHi, Rm, Rs. */
8141 inst.instruction |= inst.operands[0].reg << 12;
8142 inst.instruction |= inst.operands[1].reg << 16;
8143 inst.instruction |= inst.operands[2].reg;
8144 inst.instruction |= inst.operands[3].reg << 8;
8146 /* rdhi and rdlo must be different. */
8147 if (inst.operands[0].reg == inst.operands[1].reg)
8148 as_tsktsk (_("rdhi and rdlo must be different"));
8150 /* rdhi, rdlo and rm must all be different before armv6. */
8151 if ((inst.operands[0].reg == inst.operands[2].reg
8152 || inst.operands[1].reg == inst.operands[2].reg)
8153 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8154 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8160 if (inst.operands[0].present
8161 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8163 /* Architectural NOP hints are CPSR sets with no bits selected. */
8164 inst.instruction &= 0xf0000000;
8165 inst.instruction |= 0x0320f000;
8166 if (inst.operands[0].present)
8167 inst.instruction |= inst.operands[0].imm;
8171 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8172 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8173 Condition defaults to COND_ALWAYS.
8174 Error if Rd, Rn or Rm are R15. */
8179 inst.instruction |= inst.operands[0].reg << 12;
8180 inst.instruction |= inst.operands[1].reg << 16;
8181 inst.instruction |= inst.operands[2].reg;
8182 if (inst.operands[3].present)
8183 encode_arm_shift (3);
8186 /* ARM V6 PKHTB (Argument Parse). */
8191 if (!inst.operands[3].present)
8193 /* If the shift specifier is omitted, turn the instruction
8194 into pkhbt rd, rm, rn. */
8195 inst.instruction &= 0xfff00010;
8196 inst.instruction |= inst.operands[0].reg << 12;
8197 inst.instruction |= inst.operands[1].reg;
8198 inst.instruction |= inst.operands[2].reg << 16;
8202 inst.instruction |= inst.operands[0].reg << 12;
8203 inst.instruction |= inst.operands[1].reg << 16;
8204 inst.instruction |= inst.operands[2].reg;
8205 encode_arm_shift (3);
8209 /* ARMv5TE: Preload-Cache
8210 MP Extensions: Preload for write
8214 Syntactically, like LDR with B=1, W=0, L=1. */
8219 constraint (!inst.operands[0].isreg,
8220 _("'[' expected after PLD mnemonic"));
8221 constraint (inst.operands[0].postind,
8222 _("post-indexed expression used in preload instruction"));
8223 constraint (inst.operands[0].writeback,
8224 _("writeback used in preload instruction"));
8225 constraint (!inst.operands[0].preind,
8226 _("unindexed addressing used in preload instruction"));
8227 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8230 /* ARMv7: PLI <addr_mode> */
8234 constraint (!inst.operands[0].isreg,
8235 _("'[' expected after PLI mnemonic"));
8236 constraint (inst.operands[0].postind,
8237 _("post-indexed expression used in preload instruction"));
8238 constraint (inst.operands[0].writeback,
8239 _("writeback used in preload instruction"));
8240 constraint (!inst.operands[0].preind,
8241 _("unindexed addressing used in preload instruction"));
8242 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8243 inst.instruction &= ~PRE_INDEX;
8249 inst.operands[1] = inst.operands[0];
8250 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8251 inst.operands[0].isreg = 1;
8252 inst.operands[0].writeback = 1;
8253 inst.operands[0].reg = REG_SP;
8257 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8258 word at the specified address and the following word
8260 Unconditionally executed.
8261 Error if Rn is R15. */
8266 inst.instruction |= inst.operands[0].reg << 16;
8267 if (inst.operands[0].writeback)
8268 inst.instruction |= WRITE_BACK;
8271 /* ARM V6 ssat (argument parse). */
8276 inst.instruction |= inst.operands[0].reg << 12;
8277 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8278 inst.instruction |= inst.operands[2].reg;
8280 if (inst.operands[3].present)
8281 encode_arm_shift (3);
8284 /* ARM V6 usat (argument parse). */
8289 inst.instruction |= inst.operands[0].reg << 12;
8290 inst.instruction |= inst.operands[1].imm << 16;
8291 inst.instruction |= inst.operands[2].reg;
8293 if (inst.operands[3].present)
8294 encode_arm_shift (3);
8297 /* ARM V6 ssat16 (argument parse). */
8302 inst.instruction |= inst.operands[0].reg << 12;
8303 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8304 inst.instruction |= inst.operands[2].reg;
8310 inst.instruction |= inst.operands[0].reg << 12;
8311 inst.instruction |= inst.operands[1].imm << 16;
8312 inst.instruction |= inst.operands[2].reg;
8315 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8316 preserving the other bits.
8318 setend <endian_specifier>, where <endian_specifier> is either
8324 if (inst.operands[0].imm)
8325 inst.instruction |= 0x200;
8331 unsigned int Rm = (inst.operands[1].present
8332 ? inst.operands[1].reg
8333 : inst.operands[0].reg);
8335 inst.instruction |= inst.operands[0].reg << 12;
8336 inst.instruction |= Rm;
8337 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8339 inst.instruction |= inst.operands[2].reg << 8;
8340 inst.instruction |= SHIFT_BY_REG;
8343 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8349 inst.reloc.type = BFD_RELOC_ARM_SMC;
8350 inst.reloc.pc_rel = 0;
8356 inst.reloc.type = BFD_RELOC_ARM_HVC;
8357 inst.reloc.pc_rel = 0;
8363 inst.reloc.type = BFD_RELOC_ARM_SWI;
8364 inst.reloc.pc_rel = 0;
8367 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8368 SMLAxy{cond} Rd,Rm,Rs,Rn
8369 SMLAWy{cond} Rd,Rm,Rs,Rn
8370 Error if any register is R15. */
8375 inst.instruction |= inst.operands[0].reg << 16;
8376 inst.instruction |= inst.operands[1].reg;
8377 inst.instruction |= inst.operands[2].reg << 8;
8378 inst.instruction |= inst.operands[3].reg << 12;
8381 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8382 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8383 Error if any register is R15.
8384 Warning if Rdlo == Rdhi. */
8389 inst.instruction |= inst.operands[0].reg << 12;
8390 inst.instruction |= inst.operands[1].reg << 16;
8391 inst.instruction |= inst.operands[2].reg;
8392 inst.instruction |= inst.operands[3].reg << 8;
8394 if (inst.operands[0].reg == inst.operands[1].reg)
8395 as_tsktsk (_("rdhi and rdlo must be different"));
8398 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8399 SMULxy{cond} Rd,Rm,Rs
8400 Error if any register is R15. */
8405 inst.instruction |= inst.operands[0].reg << 16;
8406 inst.instruction |= inst.operands[1].reg;
8407 inst.instruction |= inst.operands[2].reg << 8;
8410 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8411 the same for both ARM and Thumb-2. */
8418 if (inst.operands[0].present)
8420 reg = inst.operands[0].reg;
8421 constraint (reg != REG_SP, _("SRS base register must be r13"));
8426 inst.instruction |= reg << 16;
8427 inst.instruction |= inst.operands[1].imm;
8428 if (inst.operands[0].writeback || inst.operands[1].writeback)
8429 inst.instruction |= WRITE_BACK;
8432 /* ARM V6 strex (argument parse). */
8437 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8438 || inst.operands[2].postind || inst.operands[2].writeback
8439 || inst.operands[2].immisreg || inst.operands[2].shifted
8440 || inst.operands[2].negative
8441 /* See comment in do_ldrex(). */
8442 || (inst.operands[2].reg == REG_PC),
8445 constraint (inst.operands[0].reg == inst.operands[1].reg
8446 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8448 constraint (inst.reloc.exp.X_op != O_constant
8449 || inst.reloc.exp.X_add_number != 0,
8450 _("offset must be zero in ARM encoding"));
8452 inst.instruction |= inst.operands[0].reg << 12;
8453 inst.instruction |= inst.operands[1].reg;
8454 inst.instruction |= inst.operands[2].reg << 16;
8455 inst.reloc.type = BFD_RELOC_UNUSED;
8461 constraint (inst.operands[1].reg % 2 != 0,
8462 _("even register required"));
8463 constraint (inst.operands[2].present
8464 && inst.operands[2].reg != inst.operands[1].reg + 1,
8465 _("can only store two consecutive registers"));
8466 /* If op 2 were present and equal to PC, this function wouldn't
8467 have been called in the first place. */
8468 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8470 constraint (inst.operands[0].reg == inst.operands[1].reg
8471 || inst.operands[0].reg == inst.operands[1].reg + 1
8472 || inst.operands[0].reg == inst.operands[3].reg,
8475 inst.instruction |= inst.operands[0].reg << 12;
8476 inst.instruction |= inst.operands[1].reg;
8477 inst.instruction |= inst.operands[3].reg << 16;
8480 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8481 extends it to 32-bits, and adds the result to a value in another
8482 register. You can specify a rotation by 0, 8, 16, or 24 bits
8483 before extracting the 16-bit value.
8484 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8485 Condition defaults to COND_ALWAYS.
8486 Error if any register uses R15. */
8491 inst.instruction |= inst.operands[0].reg << 12;
8492 inst.instruction |= inst.operands[1].reg << 16;
8493 inst.instruction |= inst.operands[2].reg;
8494 inst.instruction |= inst.operands[3].imm << 10;
8499 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8500 Condition defaults to COND_ALWAYS.
8501 Error if any register uses R15. */
8506 inst.instruction |= inst.operands[0].reg << 12;
8507 inst.instruction |= inst.operands[1].reg;
8508 inst.instruction |= inst.operands[2].imm << 10;
8511 /* VFP instructions. In a logical order: SP variant first, monad
8512 before dyad, arithmetic then move then load/store. */
8515 do_vfp_sp_monadic (void)
8517 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8518 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8522 do_vfp_sp_dyadic (void)
8524 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8525 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8526 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8530 do_vfp_sp_compare_z (void)
8532 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8536 do_vfp_dp_sp_cvt (void)
8538 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8539 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8543 do_vfp_sp_dp_cvt (void)
8545 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8546 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8550 do_vfp_reg_from_sp (void)
8552 inst.instruction |= inst.operands[0].reg << 12;
8553 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8557 do_vfp_reg2_from_sp2 (void)
8559 constraint (inst.operands[2].imm != 2,
8560 _("only two consecutive VFP SP registers allowed here"));
8561 inst.instruction |= inst.operands[0].reg << 12;
8562 inst.instruction |= inst.operands[1].reg << 16;
8563 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8567 do_vfp_sp_from_reg (void)
8569 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8570 inst.instruction |= inst.operands[1].reg << 12;
8574 do_vfp_sp2_from_reg2 (void)
8576 constraint (inst.operands[0].imm != 2,
8577 _("only two consecutive VFP SP registers allowed here"));
8578 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8579 inst.instruction |= inst.operands[1].reg << 12;
8580 inst.instruction |= inst.operands[2].reg << 16;
8584 do_vfp_sp_ldst (void)
8586 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8587 encode_arm_cp_address (1, FALSE, TRUE, 0);
8591 do_vfp_dp_ldst (void)
8593 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8594 encode_arm_cp_address (1, FALSE, TRUE, 0);
8599 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8601 if (inst.operands[0].writeback)
8602 inst.instruction |= WRITE_BACK;
8604 constraint (ldstm_type != VFP_LDSTMIA,
8605 _("this addressing mode requires base-register writeback"));
8606 inst.instruction |= inst.operands[0].reg << 16;
8607 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8608 inst.instruction |= inst.operands[1].imm;
8612 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8616 if (inst.operands[0].writeback)
8617 inst.instruction |= WRITE_BACK;
8619 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8620 _("this addressing mode requires base-register writeback"));
8622 inst.instruction |= inst.operands[0].reg << 16;
8623 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8625 count = inst.operands[1].imm << 1;
8626 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8629 inst.instruction |= count;
8633 do_vfp_sp_ldstmia (void)
8635 vfp_sp_ldstm (VFP_LDSTMIA);
8639 do_vfp_sp_ldstmdb (void)
8641 vfp_sp_ldstm (VFP_LDSTMDB);
8645 do_vfp_dp_ldstmia (void)
8647 vfp_dp_ldstm (VFP_LDSTMIA);
8651 do_vfp_dp_ldstmdb (void)
8653 vfp_dp_ldstm (VFP_LDSTMDB);
8657 do_vfp_xp_ldstmia (void)
8659 vfp_dp_ldstm (VFP_LDSTMIAX);
8663 do_vfp_xp_ldstmdb (void)
8665 vfp_dp_ldstm (VFP_LDSTMDBX);
8669 do_vfp_dp_rd_rm (void)
8671 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8672 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8676 do_vfp_dp_rn_rd (void)
8678 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8679 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8683 do_vfp_dp_rd_rn (void)
8685 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8686 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8690 do_vfp_dp_rd_rn_rm (void)
8692 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8693 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8694 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8700 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8704 do_vfp_dp_rm_rd_rn (void)
8706 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8707 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8708 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8711 /* VFPv3 instructions. */
8713 do_vfp_sp_const (void)
8715 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8716 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8717 inst.instruction |= (inst.operands[1].imm & 0x0f);
8721 do_vfp_dp_const (void)
8723 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8724 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8725 inst.instruction |= (inst.operands[1].imm & 0x0f);
8729 vfp_conv (int srcsize)
8731 unsigned immbits = srcsize - inst.operands[1].imm;
8732 inst.instruction |= (immbits & 1) << 5;
8733 inst.instruction |= (immbits >> 1);
8737 do_vfp_sp_conv_16 (void)
8739 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8744 do_vfp_dp_conv_16 (void)
8746 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8751 do_vfp_sp_conv_32 (void)
8753 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8758 do_vfp_dp_conv_32 (void)
8760 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8764 /* FPA instructions. Also in a logical order. */
8769 inst.instruction |= inst.operands[0].reg << 16;
8770 inst.instruction |= inst.operands[1].reg;
8774 do_fpa_ldmstm (void)
8776 inst.instruction |= inst.operands[0].reg << 12;
8777 switch (inst.operands[1].imm)
8779 case 1: inst.instruction |= CP_T_X; break;
8780 case 2: inst.instruction |= CP_T_Y; break;
8781 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8786 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8788 /* The instruction specified "ea" or "fd", so we can only accept
8789 [Rn]{!}. The instruction does not really support stacking or
8790 unstacking, so we have to emulate these by setting appropriate
8791 bits and offsets. */
8792 constraint (inst.reloc.exp.X_op != O_constant
8793 || inst.reloc.exp.X_add_number != 0,
8794 _("this instruction does not support indexing"));
8796 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8797 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8799 if (!(inst.instruction & INDEX_UP))
8800 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8802 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8804 inst.operands[2].preind = 0;
8805 inst.operands[2].postind = 1;
8809 encode_arm_cp_address (2, TRUE, TRUE, 0);
8812 /* iWMMXt instructions: strictly in alphabetical order. */
8815 do_iwmmxt_tandorc (void)
8817 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8821 do_iwmmxt_textrc (void)
8823 inst.instruction |= inst.operands[0].reg << 12;
8824 inst.instruction |= inst.operands[1].imm;
8828 do_iwmmxt_textrm (void)
8830 inst.instruction |= inst.operands[0].reg << 12;
8831 inst.instruction |= inst.operands[1].reg << 16;
8832 inst.instruction |= inst.operands[2].imm;
8836 do_iwmmxt_tinsr (void)
8838 inst.instruction |= inst.operands[0].reg << 16;
8839 inst.instruction |= inst.operands[1].reg << 12;
8840 inst.instruction |= inst.operands[2].imm;
8844 do_iwmmxt_tmia (void)
8846 inst.instruction |= inst.operands[0].reg << 5;
8847 inst.instruction |= inst.operands[1].reg;
8848 inst.instruction |= inst.operands[2].reg << 12;
8852 do_iwmmxt_waligni (void)
8854 inst.instruction |= inst.operands[0].reg << 12;
8855 inst.instruction |= inst.operands[1].reg << 16;
8856 inst.instruction |= inst.operands[2].reg;
8857 inst.instruction |= inst.operands[3].imm << 20;
8861 do_iwmmxt_wmerge (void)
8863 inst.instruction |= inst.operands[0].reg << 12;
8864 inst.instruction |= inst.operands[1].reg << 16;
8865 inst.instruction |= inst.operands[2].reg;
8866 inst.instruction |= inst.operands[3].imm << 21;
8870 do_iwmmxt_wmov (void)
8872 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8873 inst.instruction |= inst.operands[0].reg << 12;
8874 inst.instruction |= inst.operands[1].reg << 16;
8875 inst.instruction |= inst.operands[1].reg;
8879 do_iwmmxt_wldstbh (void)
8882 inst.instruction |= inst.operands[0].reg << 12;
8884 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
8886 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
8887 encode_arm_cp_address (1, TRUE, FALSE, reloc);
8891 do_iwmmxt_wldstw (void)
8893 /* RIWR_RIWC clears .isreg for a control register. */
8894 if (!inst.operands[0].isreg)
8896 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8897 inst.instruction |= 0xf0000000;
8900 inst.instruction |= inst.operands[0].reg << 12;
8901 encode_arm_cp_address (1, TRUE, TRUE, 0);
8905 do_iwmmxt_wldstd (void)
8907 inst.instruction |= inst.operands[0].reg << 12;
8908 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
8909 && inst.operands[1].immisreg)
8911 inst.instruction &= ~0x1a000ff;
8912 inst.instruction |= (0xf << 28);
8913 if (inst.operands[1].preind)
8914 inst.instruction |= PRE_INDEX;
8915 if (!inst.operands[1].negative)
8916 inst.instruction |= INDEX_UP;
8917 if (inst.operands[1].writeback)
8918 inst.instruction |= WRITE_BACK;
8919 inst.instruction |= inst.operands[1].reg << 16;
8920 inst.instruction |= inst.reloc.exp.X_add_number << 4;
8921 inst.instruction |= inst.operands[1].imm;
8924 encode_arm_cp_address (1, TRUE, FALSE, 0);
8928 do_iwmmxt_wshufh (void)
8930 inst.instruction |= inst.operands[0].reg << 12;
8931 inst.instruction |= inst.operands[1].reg << 16;
8932 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
8933 inst.instruction |= (inst.operands[2].imm & 0x0f);
8937 do_iwmmxt_wzero (void)
8939 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8940 inst.instruction |= inst.operands[0].reg;
8941 inst.instruction |= inst.operands[0].reg << 12;
8942 inst.instruction |= inst.operands[0].reg << 16;
8946 do_iwmmxt_wrwrwr_or_imm5 (void)
8948 if (inst.operands[2].isreg)
8951 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
8952 _("immediate operand requires iWMMXt2"));
8954 if (inst.operands[2].imm == 0)
8956 switch ((inst.instruction >> 20) & 0xf)
8962 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8963 inst.operands[2].imm = 16;
8964 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
8970 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8971 inst.operands[2].imm = 32;
8972 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
8979 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8981 wrn = (inst.instruction >> 16) & 0xf;
8982 inst.instruction &= 0xff0fff0f;
8983 inst.instruction |= wrn;
8984 /* Bail out here; the instruction is now assembled. */
8989 /* Map 32 -> 0, etc. */
8990 inst.operands[2].imm &= 0x1f;
8991 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
8995 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8996 operations first, then control, shift, and load/store. */
8998 /* Insns like "foo X,Y,Z". */
9001 do_mav_triple (void)
9003 inst.instruction |= inst.operands[0].reg << 16;
9004 inst.instruction |= inst.operands[1].reg;
9005 inst.instruction |= inst.operands[2].reg << 12;
9008 /* Insns like "foo W,X,Y,Z".
9009 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9014 inst.instruction |= inst.operands[0].reg << 5;
9015 inst.instruction |= inst.operands[1].reg << 12;
9016 inst.instruction |= inst.operands[2].reg << 16;
9017 inst.instruction |= inst.operands[3].reg;
9020 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9024 inst.instruction |= inst.operands[1].reg << 12;
9027 /* Maverick shift immediate instructions.
9028 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9029 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9034 int imm = inst.operands[2].imm;
9036 inst.instruction |= inst.operands[0].reg << 12;
9037 inst.instruction |= inst.operands[1].reg << 16;
9039 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9040 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9041 Bit 4 should be 0. */
9042 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9044 inst.instruction |= imm;
9047 /* XScale instructions. Also sorted arithmetic before move. */
9049 /* Xscale multiply-accumulate (argument parse)
9052 MIAxycc acc0,Rm,Rs. */
9057 inst.instruction |= inst.operands[1].reg;
9058 inst.instruction |= inst.operands[2].reg << 12;
9061 /* Xscale move-accumulator-register (argument parse)
9063 MARcc acc0,RdLo,RdHi. */
9068 inst.instruction |= inst.operands[1].reg << 12;
9069 inst.instruction |= inst.operands[2].reg << 16;
9072 /* Xscale move-register-accumulator (argument parse)
9074 MRAcc RdLo,RdHi,acc0. */
9079 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9080 inst.instruction |= inst.operands[0].reg << 12;
9081 inst.instruction |= inst.operands[1].reg << 16;
9084 /* Encoding functions relevant only to Thumb. */
9086 /* inst.operands[i] is a shifted-register operand; encode
9087 it into inst.instruction in the format used by Thumb32. */
9090 encode_thumb32_shifted_operand (int i)
9092 unsigned int value = inst.reloc.exp.X_add_number;
9093 unsigned int shift = inst.operands[i].shift_kind;
9095 constraint (inst.operands[i].immisreg,
9096 _("shift by register not allowed in thumb mode"));
9097 inst.instruction |= inst.operands[i].reg;
9098 if (shift == SHIFT_RRX)
9099 inst.instruction |= SHIFT_ROR << 4;
9102 constraint (inst.reloc.exp.X_op != O_constant,
9103 _("expression too complex"));
9105 constraint (value > 32
9106 || (value == 32 && (shift == SHIFT_LSL
9107 || shift == SHIFT_ROR)),
9108 _("shift expression is too large"));
9112 else if (value == 32)
9115 inst.instruction |= shift << 4;
9116 inst.instruction |= (value & 0x1c) << 10;
9117 inst.instruction |= (value & 0x03) << 6;
9122 /* inst.operands[i] was set up by parse_address. Encode it into a
9123 Thumb32 format load or store instruction. Reject forms that cannot
9124 be used with such instructions. If is_t is true, reject forms that
9125 cannot be used with a T instruction; if is_d is true, reject forms
9126 that cannot be used with a D instruction. If it is a store insn,
9130 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9132 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9134 constraint (!inst.operands[i].isreg,
9135 _("Instruction does not support =N addresses"));
9137 inst.instruction |= inst.operands[i].reg << 16;
9138 if (inst.operands[i].immisreg)
9140 constraint (is_pc, BAD_PC_ADDRESSING);
9141 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9142 constraint (inst.operands[i].negative,
9143 _("Thumb does not support negative register indexing"));
9144 constraint (inst.operands[i].postind,
9145 _("Thumb does not support register post-indexing"));
9146 constraint (inst.operands[i].writeback,
9147 _("Thumb does not support register indexing with writeback"));
9148 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9149 _("Thumb supports only LSL in shifted register indexing"));
9151 inst.instruction |= inst.operands[i].imm;
9152 if (inst.operands[i].shifted)
9154 constraint (inst.reloc.exp.X_op != O_constant,
9155 _("expression too complex"));
9156 constraint (inst.reloc.exp.X_add_number < 0
9157 || inst.reloc.exp.X_add_number > 3,
9158 _("shift out of range"));
9159 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9161 inst.reloc.type = BFD_RELOC_UNUSED;
9163 else if (inst.operands[i].preind)
9165 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9166 constraint (is_t && inst.operands[i].writeback,
9167 _("cannot use writeback with this instruction"));
9168 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9169 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9173 inst.instruction |= 0x01000000;
9174 if (inst.operands[i].writeback)
9175 inst.instruction |= 0x00200000;
9179 inst.instruction |= 0x00000c00;
9180 if (inst.operands[i].writeback)
9181 inst.instruction |= 0x00000100;
9183 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9185 else if (inst.operands[i].postind)
9187 gas_assert (inst.operands[i].writeback);
9188 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9189 constraint (is_t, _("cannot use post-indexing with this instruction"));
9192 inst.instruction |= 0x00200000;
9194 inst.instruction |= 0x00000900;
9195 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9197 else /* unindexed - only for coprocessor */
9198 inst.error = _("instruction does not accept unindexed addressing");
9201 /* Table of Thumb instructions which exist in both 16- and 32-bit
9202 encodings (the latter only in post-V6T2 cores). The index is the
9203 value used in the insns table below. When there is more than one
9204 possible 16-bit encoding for the instruction, this table always
9206 Also contains several pseudo-instructions used during relaxation. */
9207 #define T16_32_TAB \
9208 X(_adc, 4140, eb400000), \
9209 X(_adcs, 4140, eb500000), \
9210 X(_add, 1c00, eb000000), \
9211 X(_adds, 1c00, eb100000), \
9212 X(_addi, 0000, f1000000), \
9213 X(_addis, 0000, f1100000), \
9214 X(_add_pc,000f, f20f0000), \
9215 X(_add_sp,000d, f10d0000), \
9216 X(_adr, 000f, f20f0000), \
9217 X(_and, 4000, ea000000), \
9218 X(_ands, 4000, ea100000), \
9219 X(_asr, 1000, fa40f000), \
9220 X(_asrs, 1000, fa50f000), \
9221 X(_b, e000, f000b000), \
9222 X(_bcond, d000, f0008000), \
9223 X(_bic, 4380, ea200000), \
9224 X(_bics, 4380, ea300000), \
9225 X(_cmn, 42c0, eb100f00), \
9226 X(_cmp, 2800, ebb00f00), \
9227 X(_cpsie, b660, f3af8400), \
9228 X(_cpsid, b670, f3af8600), \
9229 X(_cpy, 4600, ea4f0000), \
9230 X(_dec_sp,80dd, f1ad0d00), \
9231 X(_eor, 4040, ea800000), \
9232 X(_eors, 4040, ea900000), \
9233 X(_inc_sp,00dd, f10d0d00), \
9234 X(_ldmia, c800, e8900000), \
9235 X(_ldr, 6800, f8500000), \
9236 X(_ldrb, 7800, f8100000), \
9237 X(_ldrh, 8800, f8300000), \
9238 X(_ldrsb, 5600, f9100000), \
9239 X(_ldrsh, 5e00, f9300000), \
9240 X(_ldr_pc,4800, f85f0000), \
9241 X(_ldr_pc2,4800, f85f0000), \
9242 X(_ldr_sp,9800, f85d0000), \
9243 X(_lsl, 0000, fa00f000), \
9244 X(_lsls, 0000, fa10f000), \
9245 X(_lsr, 0800, fa20f000), \
9246 X(_lsrs, 0800, fa30f000), \
9247 X(_mov, 2000, ea4f0000), \
9248 X(_movs, 2000, ea5f0000), \
9249 X(_mul, 4340, fb00f000), \
9250 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9251 X(_mvn, 43c0, ea6f0000), \
9252 X(_mvns, 43c0, ea7f0000), \
9253 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9254 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9255 X(_orr, 4300, ea400000), \
9256 X(_orrs, 4300, ea500000), \
9257 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9258 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9259 X(_rev, ba00, fa90f080), \
9260 X(_rev16, ba40, fa90f090), \
9261 X(_revsh, bac0, fa90f0b0), \
9262 X(_ror, 41c0, fa60f000), \
9263 X(_rors, 41c0, fa70f000), \
9264 X(_sbc, 4180, eb600000), \
9265 X(_sbcs, 4180, eb700000), \
9266 X(_stmia, c000, e8800000), \
9267 X(_str, 6000, f8400000), \
9268 X(_strb, 7000, f8000000), \
9269 X(_strh, 8000, f8200000), \
9270 X(_str_sp,9000, f84d0000), \
9271 X(_sub, 1e00, eba00000), \
9272 X(_subs, 1e00, ebb00000), \
9273 X(_subi, 8000, f1a00000), \
9274 X(_subis, 8000, f1b00000), \
9275 X(_sxtb, b240, fa4ff080), \
9276 X(_sxth, b200, fa0ff080), \
9277 X(_tst, 4200, ea100f00), \
9278 X(_uxtb, b2c0, fa5ff080), \
9279 X(_uxth, b280, fa1ff080), \
9280 X(_nop, bf00, f3af8000), \
9281 X(_yield, bf10, f3af8001), \
9282 X(_wfe, bf20, f3af8002), \
9283 X(_wfi, bf30, f3af8003), \
9284 X(_sev, bf40, f3af8004),
9286 /* To catch errors in encoding functions, the codes are all offset by
9287 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9288 as 16-bit instructions. */
9289 #define X(a,b,c) T_MNEM##a
9290 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9293 #define X(a,b,c) 0x##b
9294 static const unsigned short thumb_op16[] = { T16_32_TAB };
9295 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9298 #define X(a,b,c) 0x##c
9299 static const unsigned int thumb_op32[] = { T16_32_TAB };
9300 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9301 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9305 /* Thumb instruction encoders, in alphabetical order. */
9310 do_t_add_sub_w (void)
9314 Rd = inst.operands[0].reg;
9315 Rn = inst.operands[1].reg;
9317 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9318 is the SP-{plus,minus}-immediate form of the instruction. */
9320 constraint (Rd == REG_PC, BAD_PC);
9322 reject_bad_reg (Rd);
9324 inst.instruction |= (Rn << 16) | (Rd << 8);
9325 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9328 /* Parse an add or subtract instruction. We get here with inst.instruction
9329 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9336 Rd = inst.operands[0].reg;
9337 Rs = (inst.operands[1].present
9338 ? inst.operands[1].reg /* Rd, Rs, foo */
9339 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9342 set_it_insn_type_last ();
9350 flags = (inst.instruction == T_MNEM_adds
9351 || inst.instruction == T_MNEM_subs);
9353 narrow = !in_it_block ();
9355 narrow = in_it_block ();
9356 if (!inst.operands[2].isreg)
9360 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9362 add = (inst.instruction == T_MNEM_add
9363 || inst.instruction == T_MNEM_adds);
9365 if (inst.size_req != 4)
9367 /* Attempt to use a narrow opcode, with relaxation if
9369 if (Rd == REG_SP && Rs == REG_SP && !flags)
9370 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9371 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9372 opcode = T_MNEM_add_sp;
9373 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9374 opcode = T_MNEM_add_pc;
9375 else if (Rd <= 7 && Rs <= 7 && narrow)
9378 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9380 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9384 inst.instruction = THUMB_OP16(opcode);
9385 inst.instruction |= (Rd << 4) | Rs;
9386 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9387 if (inst.size_req != 2)
9388 inst.relax = opcode;
9391 constraint (inst.size_req == 2, BAD_HIREG);
9393 if (inst.size_req == 4
9394 || (inst.size_req != 2 && !opcode))
9398 constraint (add, BAD_PC);
9399 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9400 _("only SUBS PC, LR, #const allowed"));
9401 constraint (inst.reloc.exp.X_op != O_constant,
9402 _("expression too complex"));
9403 constraint (inst.reloc.exp.X_add_number < 0
9404 || inst.reloc.exp.X_add_number > 0xff,
9405 _("immediate value out of range"));
9406 inst.instruction = T2_SUBS_PC_LR
9407 | inst.reloc.exp.X_add_number;
9408 inst.reloc.type = BFD_RELOC_UNUSED;
9411 else if (Rs == REG_PC)
9413 /* Always use addw/subw. */
9414 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9415 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9419 inst.instruction = THUMB_OP32 (inst.instruction);
9420 inst.instruction = (inst.instruction & 0xe1ffffff)
9423 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9425 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9427 inst.instruction |= Rd << 8;
9428 inst.instruction |= Rs << 16;
9433 Rn = inst.operands[2].reg;
9434 /* See if we can do this with a 16-bit instruction. */
9435 if (!inst.operands[2].shifted && inst.size_req != 4)
9437 if (Rd > 7 || Rs > 7 || Rn > 7)
9442 inst.instruction = ((inst.instruction == T_MNEM_adds
9443 || inst.instruction == T_MNEM_add)
9446 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9450 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9452 /* Thumb-1 cores (except v6-M) require at least one high
9453 register in a narrow non flag setting add. */
9454 if (Rd > 7 || Rn > 7
9455 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9456 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9463 inst.instruction = T_OPCODE_ADD_HI;
9464 inst.instruction |= (Rd & 8) << 4;
9465 inst.instruction |= (Rd & 7);
9466 inst.instruction |= Rn << 3;
9472 constraint (Rd == REG_PC, BAD_PC);
9473 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9474 constraint (Rs == REG_PC, BAD_PC);
9475 reject_bad_reg (Rn);
9477 /* If we get here, it can't be done in 16 bits. */
9478 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9479 _("shift must be constant"));
9480 inst.instruction = THUMB_OP32 (inst.instruction);
9481 inst.instruction |= Rd << 8;
9482 inst.instruction |= Rs << 16;
9483 encode_thumb32_shifted_operand (2);
9488 constraint (inst.instruction == T_MNEM_adds
9489 || inst.instruction == T_MNEM_subs,
9492 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9494 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9495 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9498 inst.instruction = (inst.instruction == T_MNEM_add
9500 inst.instruction |= (Rd << 4) | Rs;
9501 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9505 Rn = inst.operands[2].reg;
9506 constraint (inst.operands[2].shifted, _("unshifted register required"));
9508 /* We now have Rd, Rs, and Rn set to registers. */
9509 if (Rd > 7 || Rs > 7 || Rn > 7)
9511 /* Can't do this for SUB. */
9512 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9513 inst.instruction = T_OPCODE_ADD_HI;
9514 inst.instruction |= (Rd & 8) << 4;
9515 inst.instruction |= (Rd & 7);
9517 inst.instruction |= Rn << 3;
9519 inst.instruction |= Rs << 3;
9521 constraint (1, _("dest must overlap one source register"));
9525 inst.instruction = (inst.instruction == T_MNEM_add
9526 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9527 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9537 Rd = inst.operands[0].reg;
9538 reject_bad_reg (Rd);
9540 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9542 /* Defer to section relaxation. */
9543 inst.relax = inst.instruction;
9544 inst.instruction = THUMB_OP16 (inst.instruction);
9545 inst.instruction |= Rd << 4;
9547 else if (unified_syntax && inst.size_req != 2)
9549 /* Generate a 32-bit opcode. */
9550 inst.instruction = THUMB_OP32 (inst.instruction);
9551 inst.instruction |= Rd << 8;
9552 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9553 inst.reloc.pc_rel = 1;
9557 /* Generate a 16-bit opcode. */
9558 inst.instruction = THUMB_OP16 (inst.instruction);
9559 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9560 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9561 inst.reloc.pc_rel = 1;
9563 inst.instruction |= Rd << 4;
9567 /* Arithmetic instructions for which there is just one 16-bit
9568 instruction encoding, and it allows only two low registers.
9569 For maximal compatibility with ARM syntax, we allow three register
9570 operands even when Thumb-32 instructions are not available, as long
9571 as the first two are identical. For instance, both "sbc r0,r1" and
9572 "sbc r0,r0,r1" are allowed. */
9578 Rd = inst.operands[0].reg;
9579 Rs = (inst.operands[1].present
9580 ? inst.operands[1].reg /* Rd, Rs, foo */
9581 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9582 Rn = inst.operands[2].reg;
9584 reject_bad_reg (Rd);
9585 reject_bad_reg (Rs);
9586 if (inst.operands[2].isreg)
9587 reject_bad_reg (Rn);
9591 if (!inst.operands[2].isreg)
9593 /* For an immediate, we always generate a 32-bit opcode;
9594 section relaxation will shrink it later if possible. */
9595 inst.instruction = THUMB_OP32 (inst.instruction);
9596 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9597 inst.instruction |= Rd << 8;
9598 inst.instruction |= Rs << 16;
9599 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9605 /* See if we can do this with a 16-bit instruction. */
9606 if (THUMB_SETS_FLAGS (inst.instruction))
9607 narrow = !in_it_block ();
9609 narrow = in_it_block ();
9611 if (Rd > 7 || Rn > 7 || Rs > 7)
9613 if (inst.operands[2].shifted)
9615 if (inst.size_req == 4)
9621 inst.instruction = THUMB_OP16 (inst.instruction);
9622 inst.instruction |= Rd;
9623 inst.instruction |= Rn << 3;
9627 /* If we get here, it can't be done in 16 bits. */
9628 constraint (inst.operands[2].shifted
9629 && inst.operands[2].immisreg,
9630 _("shift must be constant"));
9631 inst.instruction = THUMB_OP32 (inst.instruction);
9632 inst.instruction |= Rd << 8;
9633 inst.instruction |= Rs << 16;
9634 encode_thumb32_shifted_operand (2);
9639 /* On its face this is a lie - the instruction does set the
9640 flags. However, the only supported mnemonic in this mode
9642 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9644 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9645 _("unshifted register required"));
9646 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9647 constraint (Rd != Rs,
9648 _("dest and source1 must be the same register"));
9650 inst.instruction = THUMB_OP16 (inst.instruction);
9651 inst.instruction |= Rd;
9652 inst.instruction |= Rn << 3;
9656 /* Similarly, but for instructions where the arithmetic operation is
9657 commutative, so we can allow either of them to be different from
9658 the destination operand in a 16-bit instruction. For instance, all
9659 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9666 Rd = inst.operands[0].reg;
9667 Rs = (inst.operands[1].present
9668 ? inst.operands[1].reg /* Rd, Rs, foo */
9669 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9670 Rn = inst.operands[2].reg;
9672 reject_bad_reg (Rd);
9673 reject_bad_reg (Rs);
9674 if (inst.operands[2].isreg)
9675 reject_bad_reg (Rn);
9679 if (!inst.operands[2].isreg)
9681 /* For an immediate, we always generate a 32-bit opcode;
9682 section relaxation will shrink it later if possible. */
9683 inst.instruction = THUMB_OP32 (inst.instruction);
9684 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9685 inst.instruction |= Rd << 8;
9686 inst.instruction |= Rs << 16;
9687 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9693 /* See if we can do this with a 16-bit instruction. */
9694 if (THUMB_SETS_FLAGS (inst.instruction))
9695 narrow = !in_it_block ();
9697 narrow = in_it_block ();
9699 if (Rd > 7 || Rn > 7 || Rs > 7)
9701 if (inst.operands[2].shifted)
9703 if (inst.size_req == 4)
9710 inst.instruction = THUMB_OP16 (inst.instruction);
9711 inst.instruction |= Rd;
9712 inst.instruction |= Rn << 3;
9717 inst.instruction = THUMB_OP16 (inst.instruction);
9718 inst.instruction |= Rd;
9719 inst.instruction |= Rs << 3;
9724 /* If we get here, it can't be done in 16 bits. */
9725 constraint (inst.operands[2].shifted
9726 && inst.operands[2].immisreg,
9727 _("shift must be constant"));
9728 inst.instruction = THUMB_OP32 (inst.instruction);
9729 inst.instruction |= Rd << 8;
9730 inst.instruction |= Rs << 16;
9731 encode_thumb32_shifted_operand (2);
9736 /* On its face this is a lie - the instruction does set the
9737 flags. However, the only supported mnemonic in this mode
9739 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9741 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9742 _("unshifted register required"));
9743 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9745 inst.instruction = THUMB_OP16 (inst.instruction);
9746 inst.instruction |= Rd;
9749 inst.instruction |= Rn << 3;
9751 inst.instruction |= Rs << 3;
9753 constraint (1, _("dest must overlap one source register"));
9760 if (inst.operands[0].present)
9762 constraint ((inst.instruction & 0xf0) != 0x40
9763 && inst.operands[0].imm > 0xf
9764 && inst.operands[0].imm < 0x0,
9765 _("bad barrier type"));
9766 inst.instruction |= inst.operands[0].imm;
9769 inst.instruction |= 0xf;
9776 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9777 constraint (msb > 32, _("bit-field extends past end of register"));
9778 /* The instruction encoding stores the LSB and MSB,
9779 not the LSB and width. */
9780 Rd = inst.operands[0].reg;
9781 reject_bad_reg (Rd);
9782 inst.instruction |= Rd << 8;
9783 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9784 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9785 inst.instruction |= msb - 1;
9794 Rd = inst.operands[0].reg;
9795 reject_bad_reg (Rd);
9797 /* #0 in second position is alternative syntax for bfc, which is
9798 the same instruction but with REG_PC in the Rm field. */
9799 if (!inst.operands[1].isreg)
9803 Rn = inst.operands[1].reg;
9804 reject_bad_reg (Rn);
9807 msb = inst.operands[2].imm + inst.operands[3].imm;
9808 constraint (msb > 32, _("bit-field extends past end of register"));
9809 /* The instruction encoding stores the LSB and MSB,
9810 not the LSB and width. */
9811 inst.instruction |= Rd << 8;
9812 inst.instruction |= Rn << 16;
9813 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9814 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9815 inst.instruction |= msb - 1;
9823 Rd = inst.operands[0].reg;
9824 Rn = inst.operands[1].reg;
9826 reject_bad_reg (Rd);
9827 reject_bad_reg (Rn);
9829 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9830 _("bit-field extends past end of register"));
9831 inst.instruction |= Rd << 8;
9832 inst.instruction |= Rn << 16;
9833 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9834 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9835 inst.instruction |= inst.operands[3].imm - 1;
9838 /* ARM V5 Thumb BLX (argument parse)
9839 BLX <target_addr> which is BLX(1)
9840 BLX <Rm> which is BLX(2)
9841 Unfortunately, there are two different opcodes for this mnemonic.
9842 So, the insns[].value is not used, and the code here zaps values
9843 into inst.instruction.
9845 ??? How to take advantage of the additional two bits of displacement
9846 available in Thumb32 mode? Need new relocation? */
9851 set_it_insn_type_last ();
9853 if (inst.operands[0].isreg)
9855 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9856 /* We have a register, so this is BLX(2). */
9857 inst.instruction |= inst.operands[0].reg << 3;
9861 /* No register. This must be BLX(1). */
9862 inst.instruction = 0xf000e800;
9863 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
9875 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
9879 /* Conditional branches inside IT blocks are encoded as unconditional
9886 if (cond != COND_ALWAYS)
9887 opcode = T_MNEM_bcond;
9889 opcode = inst.instruction;
9892 && (inst.size_req == 4
9893 || (inst.size_req != 2
9894 && (inst.operands[0].hasreloc
9895 || inst.reloc.exp.X_op == O_constant))))
9897 inst.instruction = THUMB_OP32(opcode);
9898 if (cond == COND_ALWAYS)
9899 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
9902 gas_assert (cond != 0xF);
9903 inst.instruction |= cond << 22;
9904 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
9909 inst.instruction = THUMB_OP16(opcode);
9910 if (cond == COND_ALWAYS)
9911 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
9914 inst.instruction |= cond << 8;
9915 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
9917 /* Allow section relaxation. */
9918 if (unified_syntax && inst.size_req != 2)
9919 inst.relax = opcode;
9921 inst.reloc.type = reloc;
9922 inst.reloc.pc_rel = 1;
9928 constraint (inst.cond != COND_ALWAYS,
9929 _("instruction is always unconditional"));
9930 if (inst.operands[0].present)
9932 constraint (inst.operands[0].imm > 255,
9933 _("immediate value out of range"));
9934 inst.instruction |= inst.operands[0].imm;
9935 set_it_insn_type (NEUTRAL_IT_INSN);
9940 do_t_branch23 (void)
9942 set_it_insn_type_last ();
9943 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
9945 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
9946 this file. We used to simply ignore the PLT reloc type here --
9947 the branch encoding is now needed to deal with TLSCALL relocs.
9948 So if we see a PLT reloc now, put it back to how it used to be to
9949 keep the preexisting behaviour. */
9950 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
9951 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
9953 #if defined(OBJ_COFF)
9954 /* If the destination of the branch is a defined symbol which does not have
9955 the THUMB_FUNC attribute, then we must be calling a function which has
9956 the (interfacearm) attribute. We look for the Thumb entry point to that
9957 function and change the branch to refer to that function instead. */
9958 if ( inst.reloc.exp.X_op == O_symbol
9959 && inst.reloc.exp.X_add_symbol != NULL
9960 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
9961 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
9962 inst.reloc.exp.X_add_symbol =
9963 find_real_start (inst.reloc.exp.X_add_symbol);
9970 set_it_insn_type_last ();
9971 inst.instruction |= inst.operands[0].reg << 3;
9972 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9973 should cause the alignment to be checked once it is known. This is
9974 because BX PC only works if the instruction is word aligned. */
9982 set_it_insn_type_last ();
9983 Rm = inst.operands[0].reg;
9984 reject_bad_reg (Rm);
9985 inst.instruction |= Rm << 16;
9994 Rd = inst.operands[0].reg;
9995 Rm = inst.operands[1].reg;
9997 reject_bad_reg (Rd);
9998 reject_bad_reg (Rm);
10000 inst.instruction |= Rd << 8;
10001 inst.instruction |= Rm << 16;
10002 inst.instruction |= Rm;
10008 set_it_insn_type (OUTSIDE_IT_INSN);
10009 inst.instruction |= inst.operands[0].imm;
10015 set_it_insn_type (OUTSIDE_IT_INSN);
10017 && (inst.operands[1].present || inst.size_req == 4)
10018 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10020 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10021 inst.instruction = 0xf3af8000;
10022 inst.instruction |= imod << 9;
10023 inst.instruction |= inst.operands[0].imm << 5;
10024 if (inst.operands[1].present)
10025 inst.instruction |= 0x100 | inst.operands[1].imm;
10029 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10030 && (inst.operands[0].imm & 4),
10031 _("selected processor does not support 'A' form "
10032 "of this instruction"));
10033 constraint (inst.operands[1].present || inst.size_req == 4,
10034 _("Thumb does not support the 2-argument "
10035 "form of this instruction"));
10036 inst.instruction |= inst.operands[0].imm;
10040 /* THUMB CPY instruction (argument parse). */
10045 if (inst.size_req == 4)
10047 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10048 inst.instruction |= inst.operands[0].reg << 8;
10049 inst.instruction |= inst.operands[1].reg;
10053 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10054 inst.instruction |= (inst.operands[0].reg & 0x7);
10055 inst.instruction |= inst.operands[1].reg << 3;
10062 set_it_insn_type (OUTSIDE_IT_INSN);
10063 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10064 inst.instruction |= inst.operands[0].reg;
10065 inst.reloc.pc_rel = 1;
10066 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10072 inst.instruction |= inst.operands[0].imm;
10078 unsigned Rd, Rn, Rm;
10080 Rd = inst.operands[0].reg;
10081 Rn = (inst.operands[1].present
10082 ? inst.operands[1].reg : Rd);
10083 Rm = inst.operands[2].reg;
10085 reject_bad_reg (Rd);
10086 reject_bad_reg (Rn);
10087 reject_bad_reg (Rm);
10089 inst.instruction |= Rd << 8;
10090 inst.instruction |= Rn << 16;
10091 inst.instruction |= Rm;
10097 if (unified_syntax && inst.size_req == 4)
10098 inst.instruction = THUMB_OP32 (inst.instruction);
10100 inst.instruction = THUMB_OP16 (inst.instruction);
10106 unsigned int cond = inst.operands[0].imm;
10108 set_it_insn_type (IT_INSN);
10109 now_it.mask = (inst.instruction & 0xf) | 0x10;
10112 /* If the condition is a negative condition, invert the mask. */
10113 if ((cond & 0x1) == 0x0)
10115 unsigned int mask = inst.instruction & 0x000f;
10117 if ((mask & 0x7) == 0)
10118 /* no conversion needed */;
10119 else if ((mask & 0x3) == 0)
10121 else if ((mask & 0x1) == 0)
10126 inst.instruction &= 0xfff0;
10127 inst.instruction |= mask;
10130 inst.instruction |= cond << 4;
10133 /* Helper function used for both push/pop and ldm/stm. */
10135 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10139 load = (inst.instruction & (1 << 20)) != 0;
10141 if (mask & (1 << 13))
10142 inst.error = _("SP not allowed in register list");
10144 if ((mask & (1 << base)) != 0
10146 inst.error = _("having the base register in the register list when "
10147 "using write back is UNPREDICTABLE");
10151 if (mask & (1 << 15))
10153 if (mask & (1 << 14))
10154 inst.error = _("LR and PC should not both be in register list");
10156 set_it_insn_type_last ();
10161 if (mask & (1 << 15))
10162 inst.error = _("PC not allowed in register list");
10165 if ((mask & (mask - 1)) == 0)
10167 /* Single register transfers implemented as str/ldr. */
10170 if (inst.instruction & (1 << 23))
10171 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10173 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10177 if (inst.instruction & (1 << 23))
10178 inst.instruction = 0x00800000; /* ia -> [base] */
10180 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10183 inst.instruction |= 0xf8400000;
10185 inst.instruction |= 0x00100000;
10187 mask = ffs (mask) - 1;
10190 else if (writeback)
10191 inst.instruction |= WRITE_BACK;
10193 inst.instruction |= mask;
10194 inst.instruction |= base << 16;
10200 /* This really doesn't seem worth it. */
10201 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10202 _("expression too complex"));
10203 constraint (inst.operands[1].writeback,
10204 _("Thumb load/store multiple does not support {reglist}^"));
10206 if (unified_syntax)
10208 bfd_boolean narrow;
10212 /* See if we can use a 16-bit instruction. */
10213 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10214 && inst.size_req != 4
10215 && !(inst.operands[1].imm & ~0xff))
10217 mask = 1 << inst.operands[0].reg;
10219 if (inst.operands[0].reg <= 7)
10221 if (inst.instruction == T_MNEM_stmia
10222 ? inst.operands[0].writeback
10223 : (inst.operands[0].writeback
10224 == !(inst.operands[1].imm & mask)))
10226 if (inst.instruction == T_MNEM_stmia
10227 && (inst.operands[1].imm & mask)
10228 && (inst.operands[1].imm & (mask - 1)))
10229 as_warn (_("value stored for r%d is UNKNOWN"),
10230 inst.operands[0].reg);
10232 inst.instruction = THUMB_OP16 (inst.instruction);
10233 inst.instruction |= inst.operands[0].reg << 8;
10234 inst.instruction |= inst.operands[1].imm;
10237 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10239 /* This means 1 register in reg list one of 3 situations:
10240 1. Instruction is stmia, but without writeback.
10241 2. lmdia without writeback, but with Rn not in
10243 3. ldmia with writeback, but with Rn in reglist.
10244 Case 3 is UNPREDICTABLE behaviour, so we handle
10245 case 1 and 2 which can be converted into a 16-bit
10246 str or ldr. The SP cases are handled below. */
10247 unsigned long opcode;
10248 /* First, record an error for Case 3. */
10249 if (inst.operands[1].imm & mask
10250 && inst.operands[0].writeback)
10252 _("having the base register in the register list when "
10253 "using write back is UNPREDICTABLE");
10255 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10257 inst.instruction = THUMB_OP16 (opcode);
10258 inst.instruction |= inst.operands[0].reg << 3;
10259 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10263 else if (inst.operands[0] .reg == REG_SP)
10265 if (inst.operands[0].writeback)
10268 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10269 ? T_MNEM_push : T_MNEM_pop);
10270 inst.instruction |= inst.operands[1].imm;
10273 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10276 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10277 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10278 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10286 if (inst.instruction < 0xffff)
10287 inst.instruction = THUMB_OP32 (inst.instruction);
10289 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10290 inst.operands[0].writeback);
10295 constraint (inst.operands[0].reg > 7
10296 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10297 constraint (inst.instruction != T_MNEM_ldmia
10298 && inst.instruction != T_MNEM_stmia,
10299 _("Thumb-2 instruction only valid in unified syntax"));
10300 if (inst.instruction == T_MNEM_stmia)
10302 if (!inst.operands[0].writeback)
10303 as_warn (_("this instruction will write back the base register"));
10304 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10305 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10306 as_warn (_("value stored for r%d is UNKNOWN"),
10307 inst.operands[0].reg);
10311 if (!inst.operands[0].writeback
10312 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10313 as_warn (_("this instruction will write back the base register"));
10314 else if (inst.operands[0].writeback
10315 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10316 as_warn (_("this instruction will not write back the base register"));
10319 inst.instruction = THUMB_OP16 (inst.instruction);
10320 inst.instruction |= inst.operands[0].reg << 8;
10321 inst.instruction |= inst.operands[1].imm;
10328 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10329 || inst.operands[1].postind || inst.operands[1].writeback
10330 || inst.operands[1].immisreg || inst.operands[1].shifted
10331 || inst.operands[1].negative,
10334 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10336 inst.instruction |= inst.operands[0].reg << 12;
10337 inst.instruction |= inst.operands[1].reg << 16;
10338 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10344 if (!inst.operands[1].present)
10346 constraint (inst.operands[0].reg == REG_LR,
10347 _("r14 not allowed as first register "
10348 "when second register is omitted"));
10349 inst.operands[1].reg = inst.operands[0].reg + 1;
10351 constraint (inst.operands[0].reg == inst.operands[1].reg,
10354 inst.instruction |= inst.operands[0].reg << 12;
10355 inst.instruction |= inst.operands[1].reg << 8;
10356 inst.instruction |= inst.operands[2].reg << 16;
10362 unsigned long opcode;
10365 if (inst.operands[0].isreg
10366 && !inst.operands[0].preind
10367 && inst.operands[0].reg == REG_PC)
10368 set_it_insn_type_last ();
10370 opcode = inst.instruction;
10371 if (unified_syntax)
10373 if (!inst.operands[1].isreg)
10375 if (opcode <= 0xffff)
10376 inst.instruction = THUMB_OP32 (opcode);
10377 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10380 if (inst.operands[1].isreg
10381 && !inst.operands[1].writeback
10382 && !inst.operands[1].shifted && !inst.operands[1].postind
10383 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10384 && opcode <= 0xffff
10385 && inst.size_req != 4)
10387 /* Insn may have a 16-bit form. */
10388 Rn = inst.operands[1].reg;
10389 if (inst.operands[1].immisreg)
10391 inst.instruction = THUMB_OP16 (opcode);
10393 if (Rn <= 7 && inst.operands[1].imm <= 7)
10395 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10396 reject_bad_reg (inst.operands[1].imm);
10398 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10399 && opcode != T_MNEM_ldrsb)
10400 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10401 || (Rn == REG_SP && opcode == T_MNEM_str))
10408 if (inst.reloc.pc_rel)
10409 opcode = T_MNEM_ldr_pc2;
10411 opcode = T_MNEM_ldr_pc;
10415 if (opcode == T_MNEM_ldr)
10416 opcode = T_MNEM_ldr_sp;
10418 opcode = T_MNEM_str_sp;
10420 inst.instruction = inst.operands[0].reg << 8;
10424 inst.instruction = inst.operands[0].reg;
10425 inst.instruction |= inst.operands[1].reg << 3;
10427 inst.instruction |= THUMB_OP16 (opcode);
10428 if (inst.size_req == 2)
10429 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10431 inst.relax = opcode;
10435 /* Definitely a 32-bit variant. */
10437 /* Warning for Erratum 752419. */
10438 if (opcode == T_MNEM_ldr
10439 && inst.operands[0].reg == REG_SP
10440 && inst.operands[1].writeback == 1
10441 && !inst.operands[1].immisreg)
10443 if (no_cpu_selected ()
10444 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10445 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10446 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10447 as_warn (_("This instruction may be unpredictable "
10448 "if executed on M-profile cores "
10449 "with interrupts enabled."));
10452 /* Do some validations regarding addressing modes. */
10453 if (inst.operands[1].immisreg && opcode != T_MNEM_ldr
10454 && opcode != T_MNEM_str)
10455 reject_bad_reg (inst.operands[1].imm);
10457 inst.instruction = THUMB_OP32 (opcode);
10458 inst.instruction |= inst.operands[0].reg << 12;
10459 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10463 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10465 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10467 /* Only [Rn,Rm] is acceptable. */
10468 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10469 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10470 || inst.operands[1].postind || inst.operands[1].shifted
10471 || inst.operands[1].negative,
10472 _("Thumb does not support this addressing mode"));
10473 inst.instruction = THUMB_OP16 (inst.instruction);
10477 inst.instruction = THUMB_OP16 (inst.instruction);
10478 if (!inst.operands[1].isreg)
10479 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10482 constraint (!inst.operands[1].preind
10483 || inst.operands[1].shifted
10484 || inst.operands[1].writeback,
10485 _("Thumb does not support this addressing mode"));
10486 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10488 constraint (inst.instruction & 0x0600,
10489 _("byte or halfword not valid for base register"));
10490 constraint (inst.operands[1].reg == REG_PC
10491 && !(inst.instruction & THUMB_LOAD_BIT),
10492 _("r15 based store not allowed"));
10493 constraint (inst.operands[1].immisreg,
10494 _("invalid base register for register offset"));
10496 if (inst.operands[1].reg == REG_PC)
10497 inst.instruction = T_OPCODE_LDR_PC;
10498 else if (inst.instruction & THUMB_LOAD_BIT)
10499 inst.instruction = T_OPCODE_LDR_SP;
10501 inst.instruction = T_OPCODE_STR_SP;
10503 inst.instruction |= inst.operands[0].reg << 8;
10504 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10508 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10509 if (!inst.operands[1].immisreg)
10511 /* Immediate offset. */
10512 inst.instruction |= inst.operands[0].reg;
10513 inst.instruction |= inst.operands[1].reg << 3;
10514 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10518 /* Register offset. */
10519 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10520 constraint (inst.operands[1].negative,
10521 _("Thumb does not support this addressing mode"));
10524 switch (inst.instruction)
10526 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10527 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10528 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10529 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10530 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10531 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10532 case 0x5600 /* ldrsb */:
10533 case 0x5e00 /* ldrsh */: break;
10537 inst.instruction |= inst.operands[0].reg;
10538 inst.instruction |= inst.operands[1].reg << 3;
10539 inst.instruction |= inst.operands[1].imm << 6;
10545 if (!inst.operands[1].present)
10547 inst.operands[1].reg = inst.operands[0].reg + 1;
10548 constraint (inst.operands[0].reg == REG_LR,
10549 _("r14 not allowed here"));
10551 inst.instruction |= inst.operands[0].reg << 12;
10552 inst.instruction |= inst.operands[1].reg << 8;
10553 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10559 inst.instruction |= inst.operands[0].reg << 12;
10560 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10566 unsigned Rd, Rn, Rm, Ra;
10568 Rd = inst.operands[0].reg;
10569 Rn = inst.operands[1].reg;
10570 Rm = inst.operands[2].reg;
10571 Ra = inst.operands[3].reg;
10573 reject_bad_reg (Rd);
10574 reject_bad_reg (Rn);
10575 reject_bad_reg (Rm);
10576 reject_bad_reg (Ra);
10578 inst.instruction |= Rd << 8;
10579 inst.instruction |= Rn << 16;
10580 inst.instruction |= Rm;
10581 inst.instruction |= Ra << 12;
10587 unsigned RdLo, RdHi, Rn, Rm;
10589 RdLo = inst.operands[0].reg;
10590 RdHi = inst.operands[1].reg;
10591 Rn = inst.operands[2].reg;
10592 Rm = inst.operands[3].reg;
10594 reject_bad_reg (RdLo);
10595 reject_bad_reg (RdHi);
10596 reject_bad_reg (Rn);
10597 reject_bad_reg (Rm);
10599 inst.instruction |= RdLo << 12;
10600 inst.instruction |= RdHi << 8;
10601 inst.instruction |= Rn << 16;
10602 inst.instruction |= Rm;
10606 do_t_mov_cmp (void)
10610 Rn = inst.operands[0].reg;
10611 Rm = inst.operands[1].reg;
10614 set_it_insn_type_last ();
10616 if (unified_syntax)
10618 int r0off = (inst.instruction == T_MNEM_mov
10619 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10620 unsigned long opcode;
10621 bfd_boolean narrow;
10622 bfd_boolean low_regs;
10624 low_regs = (Rn <= 7 && Rm <= 7);
10625 opcode = inst.instruction;
10626 if (in_it_block ())
10627 narrow = opcode != T_MNEM_movs;
10629 narrow = opcode != T_MNEM_movs || low_regs;
10630 if (inst.size_req == 4
10631 || inst.operands[1].shifted)
10634 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10635 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10636 && !inst.operands[1].shifted
10640 inst.instruction = T2_SUBS_PC_LR;
10644 if (opcode == T_MNEM_cmp)
10646 constraint (Rn == REG_PC, BAD_PC);
10649 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10651 warn_deprecated_sp (Rm);
10652 /* R15 was documented as a valid choice for Rm in ARMv6,
10653 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10654 tools reject R15, so we do too. */
10655 constraint (Rm == REG_PC, BAD_PC);
10658 reject_bad_reg (Rm);
10660 else if (opcode == T_MNEM_mov
10661 || opcode == T_MNEM_movs)
10663 if (inst.operands[1].isreg)
10665 if (opcode == T_MNEM_movs)
10667 reject_bad_reg (Rn);
10668 reject_bad_reg (Rm);
10672 /* This is mov.n. */
10673 if ((Rn == REG_SP || Rn == REG_PC)
10674 && (Rm == REG_SP || Rm == REG_PC))
10676 as_warn (_("Use of r%u as a source register is "
10677 "deprecated when r%u is the destination "
10678 "register."), Rm, Rn);
10683 /* This is mov.w. */
10684 constraint (Rn == REG_PC, BAD_PC);
10685 constraint (Rm == REG_PC, BAD_PC);
10686 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10690 reject_bad_reg (Rn);
10693 if (!inst.operands[1].isreg)
10695 /* Immediate operand. */
10696 if (!in_it_block () && opcode == T_MNEM_mov)
10698 if (low_regs && narrow)
10700 inst.instruction = THUMB_OP16 (opcode);
10701 inst.instruction |= Rn << 8;
10702 if (inst.size_req == 2)
10703 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10705 inst.relax = opcode;
10709 inst.instruction = THUMB_OP32 (inst.instruction);
10710 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10711 inst.instruction |= Rn << r0off;
10712 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10715 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10716 && (inst.instruction == T_MNEM_mov
10717 || inst.instruction == T_MNEM_movs))
10719 /* Register shifts are encoded as separate shift instructions. */
10720 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10722 if (in_it_block ())
10727 if (inst.size_req == 4)
10730 if (!low_regs || inst.operands[1].imm > 7)
10736 switch (inst.operands[1].shift_kind)
10739 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10742 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10745 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10748 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10754 inst.instruction = opcode;
10757 inst.instruction |= Rn;
10758 inst.instruction |= inst.operands[1].imm << 3;
10763 inst.instruction |= CONDS_BIT;
10765 inst.instruction |= Rn << 8;
10766 inst.instruction |= Rm << 16;
10767 inst.instruction |= inst.operands[1].imm;
10772 /* Some mov with immediate shift have narrow variants.
10773 Register shifts are handled above. */
10774 if (low_regs && inst.operands[1].shifted
10775 && (inst.instruction == T_MNEM_mov
10776 || inst.instruction == T_MNEM_movs))
10778 if (in_it_block ())
10779 narrow = (inst.instruction == T_MNEM_mov);
10781 narrow = (inst.instruction == T_MNEM_movs);
10786 switch (inst.operands[1].shift_kind)
10788 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10789 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10790 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10791 default: narrow = FALSE; break;
10797 inst.instruction |= Rn;
10798 inst.instruction |= Rm << 3;
10799 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10803 inst.instruction = THUMB_OP32 (inst.instruction);
10804 inst.instruction |= Rn << r0off;
10805 encode_thumb32_shifted_operand (1);
10809 switch (inst.instruction)
10812 inst.instruction = T_OPCODE_MOV_HR;
10813 inst.instruction |= (Rn & 0x8) << 4;
10814 inst.instruction |= (Rn & 0x7);
10815 inst.instruction |= Rm << 3;
10819 /* We know we have low registers at this point.
10820 Generate LSLS Rd, Rs, #0. */
10821 inst.instruction = T_OPCODE_LSL_I;
10822 inst.instruction |= Rn;
10823 inst.instruction |= Rm << 3;
10829 inst.instruction = T_OPCODE_CMP_LR;
10830 inst.instruction |= Rn;
10831 inst.instruction |= Rm << 3;
10835 inst.instruction = T_OPCODE_CMP_HR;
10836 inst.instruction |= (Rn & 0x8) << 4;
10837 inst.instruction |= (Rn & 0x7);
10838 inst.instruction |= Rm << 3;
10845 inst.instruction = THUMB_OP16 (inst.instruction);
10847 /* PR 10443: Do not silently ignore shifted operands. */
10848 constraint (inst.operands[1].shifted,
10849 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10851 if (inst.operands[1].isreg)
10853 if (Rn < 8 && Rm < 8)
10855 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10856 since a MOV instruction produces unpredictable results. */
10857 if (inst.instruction == T_OPCODE_MOV_I8)
10858 inst.instruction = T_OPCODE_ADD_I3;
10860 inst.instruction = T_OPCODE_CMP_LR;
10862 inst.instruction |= Rn;
10863 inst.instruction |= Rm << 3;
10867 if (inst.instruction == T_OPCODE_MOV_I8)
10868 inst.instruction = T_OPCODE_MOV_HR;
10870 inst.instruction = T_OPCODE_CMP_HR;
10876 constraint (Rn > 7,
10877 _("only lo regs allowed with immediate"));
10878 inst.instruction |= Rn << 8;
10879 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10890 top = (inst.instruction & 0x00800000) != 0;
10891 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
10893 constraint (top, _(":lower16: not allowed this instruction"));
10894 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
10896 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
10898 constraint (!top, _(":upper16: not allowed this instruction"));
10899 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
10902 Rd = inst.operands[0].reg;
10903 reject_bad_reg (Rd);
10905 inst.instruction |= Rd << 8;
10906 if (inst.reloc.type == BFD_RELOC_UNUSED)
10908 imm = inst.reloc.exp.X_add_number;
10909 inst.instruction |= (imm & 0xf000) << 4;
10910 inst.instruction |= (imm & 0x0800) << 15;
10911 inst.instruction |= (imm & 0x0700) << 4;
10912 inst.instruction |= (imm & 0x00ff);
10917 do_t_mvn_tst (void)
10921 Rn = inst.operands[0].reg;
10922 Rm = inst.operands[1].reg;
10924 if (inst.instruction == T_MNEM_cmp
10925 || inst.instruction == T_MNEM_cmn)
10926 constraint (Rn == REG_PC, BAD_PC);
10928 reject_bad_reg (Rn);
10929 reject_bad_reg (Rm);
10931 if (unified_syntax)
10933 int r0off = (inst.instruction == T_MNEM_mvn
10934 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
10935 bfd_boolean narrow;
10937 if (inst.size_req == 4
10938 || inst.instruction > 0xffff
10939 || inst.operands[1].shifted
10940 || Rn > 7 || Rm > 7)
10942 else if (inst.instruction == T_MNEM_cmn)
10944 else if (THUMB_SETS_FLAGS (inst.instruction))
10945 narrow = !in_it_block ();
10947 narrow = in_it_block ();
10949 if (!inst.operands[1].isreg)
10951 /* For an immediate, we always generate a 32-bit opcode;
10952 section relaxation will shrink it later if possible. */
10953 if (inst.instruction < 0xffff)
10954 inst.instruction = THUMB_OP32 (inst.instruction);
10955 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10956 inst.instruction |= Rn << r0off;
10957 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10961 /* See if we can do this with a 16-bit instruction. */
10964 inst.instruction = THUMB_OP16 (inst.instruction);
10965 inst.instruction |= Rn;
10966 inst.instruction |= Rm << 3;
10970 constraint (inst.operands[1].shifted
10971 && inst.operands[1].immisreg,
10972 _("shift must be constant"));
10973 if (inst.instruction < 0xffff)
10974 inst.instruction = THUMB_OP32 (inst.instruction);
10975 inst.instruction |= Rn << r0off;
10976 encode_thumb32_shifted_operand (1);
10982 constraint (inst.instruction > 0xffff
10983 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
10984 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
10985 _("unshifted register required"));
10986 constraint (Rn > 7 || Rm > 7,
10989 inst.instruction = THUMB_OP16 (inst.instruction);
10990 inst.instruction |= Rn;
10991 inst.instruction |= Rm << 3;
11000 if (do_vfp_nsyn_mrs () == SUCCESS)
11003 Rd = inst.operands[0].reg;
11004 reject_bad_reg (Rd);
11005 inst.instruction |= Rd << 8;
11007 if (inst.operands[1].isreg)
11009 unsigned br = inst.operands[1].reg;
11010 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11011 as_bad (_("bad register for mrs"));
11013 inst.instruction |= br & (0xf << 16);
11014 inst.instruction |= (br & 0x300) >> 4;
11015 inst.instruction |= (br & SPSR_BIT) >> 2;
11019 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11021 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11022 constraint (flags != 0, _("selected processor does not support "
11023 "requested special purpose register"));
11025 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11027 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11028 _("'APSR', 'CPSR' or 'SPSR' expected"));
11030 inst.instruction |= (flags & SPSR_BIT) >> 2;
11031 inst.instruction |= inst.operands[1].imm & 0xff;
11032 inst.instruction |= 0xf0000;
11042 if (do_vfp_nsyn_msr () == SUCCESS)
11045 constraint (!inst.operands[1].isreg,
11046 _("Thumb encoding does not support an immediate here"));
11048 if (inst.operands[0].isreg)
11049 flags = (int)(inst.operands[0].reg);
11051 flags = inst.operands[0].imm;
11053 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11055 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11057 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11058 && (bits & ~(PSR_s | PSR_f)) != 0)
11059 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11061 _("selected processor does not support requested special "
11062 "purpose register"));
11065 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11066 "requested special purpose register"));
11068 Rn = inst.operands[1].reg;
11069 reject_bad_reg (Rn);
11071 inst.instruction |= (flags & SPSR_BIT) >> 2;
11072 inst.instruction |= (flags & 0xf0000) >> 8;
11073 inst.instruction |= (flags & 0x300) >> 4;
11074 inst.instruction |= (flags & 0xff);
11075 inst.instruction |= Rn << 16;
11081 bfd_boolean narrow;
11082 unsigned Rd, Rn, Rm;
11084 if (!inst.operands[2].present)
11085 inst.operands[2].reg = inst.operands[0].reg;
11087 Rd = inst.operands[0].reg;
11088 Rn = inst.operands[1].reg;
11089 Rm = inst.operands[2].reg;
11091 if (unified_syntax)
11093 if (inst.size_req == 4
11099 else if (inst.instruction == T_MNEM_muls)
11100 narrow = !in_it_block ();
11102 narrow = in_it_block ();
11106 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11107 constraint (Rn > 7 || Rm > 7,
11114 /* 16-bit MULS/Conditional MUL. */
11115 inst.instruction = THUMB_OP16 (inst.instruction);
11116 inst.instruction |= Rd;
11119 inst.instruction |= Rm << 3;
11121 inst.instruction |= Rn << 3;
11123 constraint (1, _("dest must overlap one source register"));
11127 constraint (inst.instruction != T_MNEM_mul,
11128 _("Thumb-2 MUL must not set flags"));
11130 inst.instruction = THUMB_OP32 (inst.instruction);
11131 inst.instruction |= Rd << 8;
11132 inst.instruction |= Rn << 16;
11133 inst.instruction |= Rm << 0;
11135 reject_bad_reg (Rd);
11136 reject_bad_reg (Rn);
11137 reject_bad_reg (Rm);
11144 unsigned RdLo, RdHi, Rn, Rm;
11146 RdLo = inst.operands[0].reg;
11147 RdHi = inst.operands[1].reg;
11148 Rn = inst.operands[2].reg;
11149 Rm = inst.operands[3].reg;
11151 reject_bad_reg (RdLo);
11152 reject_bad_reg (RdHi);
11153 reject_bad_reg (Rn);
11154 reject_bad_reg (Rm);
11156 inst.instruction |= RdLo << 12;
11157 inst.instruction |= RdHi << 8;
11158 inst.instruction |= Rn << 16;
11159 inst.instruction |= Rm;
11162 as_tsktsk (_("rdhi and rdlo must be different"));
11168 set_it_insn_type (NEUTRAL_IT_INSN);
11170 if (unified_syntax)
11172 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11174 inst.instruction = THUMB_OP32 (inst.instruction);
11175 inst.instruction |= inst.operands[0].imm;
11179 /* PR9722: Check for Thumb2 availability before
11180 generating a thumb2 nop instruction. */
11181 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11183 inst.instruction = THUMB_OP16 (inst.instruction);
11184 inst.instruction |= inst.operands[0].imm << 4;
11187 inst.instruction = 0x46c0;
11192 constraint (inst.operands[0].present,
11193 _("Thumb does not support NOP with hints"));
11194 inst.instruction = 0x46c0;
11201 if (unified_syntax)
11203 bfd_boolean narrow;
11205 if (THUMB_SETS_FLAGS (inst.instruction))
11206 narrow = !in_it_block ();
11208 narrow = in_it_block ();
11209 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11211 if (inst.size_req == 4)
11216 inst.instruction = THUMB_OP32 (inst.instruction);
11217 inst.instruction |= inst.operands[0].reg << 8;
11218 inst.instruction |= inst.operands[1].reg << 16;
11222 inst.instruction = THUMB_OP16 (inst.instruction);
11223 inst.instruction |= inst.operands[0].reg;
11224 inst.instruction |= inst.operands[1].reg << 3;
11229 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11231 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11233 inst.instruction = THUMB_OP16 (inst.instruction);
11234 inst.instruction |= inst.operands[0].reg;
11235 inst.instruction |= inst.operands[1].reg << 3;
11244 Rd = inst.operands[0].reg;
11245 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11247 reject_bad_reg (Rd);
11248 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11249 reject_bad_reg (Rn);
11251 inst.instruction |= Rd << 8;
11252 inst.instruction |= Rn << 16;
11254 if (!inst.operands[2].isreg)
11256 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11257 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11263 Rm = inst.operands[2].reg;
11264 reject_bad_reg (Rm);
11266 constraint (inst.operands[2].shifted
11267 && inst.operands[2].immisreg,
11268 _("shift must be constant"));
11269 encode_thumb32_shifted_operand (2);
11276 unsigned Rd, Rn, Rm;
11278 Rd = inst.operands[0].reg;
11279 Rn = inst.operands[1].reg;
11280 Rm = inst.operands[2].reg;
11282 reject_bad_reg (Rd);
11283 reject_bad_reg (Rn);
11284 reject_bad_reg (Rm);
11286 inst.instruction |= Rd << 8;
11287 inst.instruction |= Rn << 16;
11288 inst.instruction |= Rm;
11289 if (inst.operands[3].present)
11291 unsigned int val = inst.reloc.exp.X_add_number;
11292 constraint (inst.reloc.exp.X_op != O_constant,
11293 _("expression too complex"));
11294 inst.instruction |= (val & 0x1c) << 10;
11295 inst.instruction |= (val & 0x03) << 6;
11302 if (!inst.operands[3].present)
11306 inst.instruction &= ~0x00000020;
11308 /* PR 10168. Swap the Rm and Rn registers. */
11309 Rtmp = inst.operands[1].reg;
11310 inst.operands[1].reg = inst.operands[2].reg;
11311 inst.operands[2].reg = Rtmp;
11319 if (inst.operands[0].immisreg)
11320 reject_bad_reg (inst.operands[0].imm);
11322 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11326 do_t_push_pop (void)
11330 constraint (inst.operands[0].writeback,
11331 _("push/pop do not support {reglist}^"));
11332 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11333 _("expression too complex"));
11335 mask = inst.operands[0].imm;
11336 if ((mask & ~0xff) == 0)
11337 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11338 else if ((inst.instruction == T_MNEM_push
11339 && (mask & ~0xff) == 1 << REG_LR)
11340 || (inst.instruction == T_MNEM_pop
11341 && (mask & ~0xff) == 1 << REG_PC))
11343 inst.instruction = THUMB_OP16 (inst.instruction);
11344 inst.instruction |= THUMB_PP_PC_LR;
11345 inst.instruction |= mask & 0xff;
11347 else if (unified_syntax)
11349 inst.instruction = THUMB_OP32 (inst.instruction);
11350 encode_thumb2_ldmstm (13, mask, TRUE);
11354 inst.error = _("invalid register list to push/pop instruction");
11364 Rd = inst.operands[0].reg;
11365 Rm = inst.operands[1].reg;
11367 reject_bad_reg (Rd);
11368 reject_bad_reg (Rm);
11370 inst.instruction |= Rd << 8;
11371 inst.instruction |= Rm << 16;
11372 inst.instruction |= Rm;
11380 Rd = inst.operands[0].reg;
11381 Rm = inst.operands[1].reg;
11383 reject_bad_reg (Rd);
11384 reject_bad_reg (Rm);
11386 if (Rd <= 7 && Rm <= 7
11387 && inst.size_req != 4)
11389 inst.instruction = THUMB_OP16 (inst.instruction);
11390 inst.instruction |= Rd;
11391 inst.instruction |= Rm << 3;
11393 else if (unified_syntax)
11395 inst.instruction = THUMB_OP32 (inst.instruction);
11396 inst.instruction |= Rd << 8;
11397 inst.instruction |= Rm << 16;
11398 inst.instruction |= Rm;
11401 inst.error = BAD_HIREG;
11409 Rd = inst.operands[0].reg;
11410 Rm = inst.operands[1].reg;
11412 reject_bad_reg (Rd);
11413 reject_bad_reg (Rm);
11415 inst.instruction |= Rd << 8;
11416 inst.instruction |= Rm;
11424 Rd = inst.operands[0].reg;
11425 Rs = (inst.operands[1].present
11426 ? inst.operands[1].reg /* Rd, Rs, foo */
11427 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11429 reject_bad_reg (Rd);
11430 reject_bad_reg (Rs);
11431 if (inst.operands[2].isreg)
11432 reject_bad_reg (inst.operands[2].reg);
11434 inst.instruction |= Rd << 8;
11435 inst.instruction |= Rs << 16;
11436 if (!inst.operands[2].isreg)
11438 bfd_boolean narrow;
11440 if ((inst.instruction & 0x00100000) != 0)
11441 narrow = !in_it_block ();
11443 narrow = in_it_block ();
11445 if (Rd > 7 || Rs > 7)
11448 if (inst.size_req == 4 || !unified_syntax)
11451 if (inst.reloc.exp.X_op != O_constant
11452 || inst.reloc.exp.X_add_number != 0)
11455 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11456 relaxation, but it doesn't seem worth the hassle. */
11459 inst.reloc.type = BFD_RELOC_UNUSED;
11460 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11461 inst.instruction |= Rs << 3;
11462 inst.instruction |= Rd;
11466 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11467 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11471 encode_thumb32_shifted_operand (2);
11477 set_it_insn_type (OUTSIDE_IT_INSN);
11478 if (inst.operands[0].imm)
11479 inst.instruction |= 0x8;
11485 if (!inst.operands[1].present)
11486 inst.operands[1].reg = inst.operands[0].reg;
11488 if (unified_syntax)
11490 bfd_boolean narrow;
11493 switch (inst.instruction)
11496 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11498 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11500 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11502 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11506 if (THUMB_SETS_FLAGS (inst.instruction))
11507 narrow = !in_it_block ();
11509 narrow = in_it_block ();
11510 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11512 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11514 if (inst.operands[2].isreg
11515 && (inst.operands[1].reg != inst.operands[0].reg
11516 || inst.operands[2].reg > 7))
11518 if (inst.size_req == 4)
11521 reject_bad_reg (inst.operands[0].reg);
11522 reject_bad_reg (inst.operands[1].reg);
11526 if (inst.operands[2].isreg)
11528 reject_bad_reg (inst.operands[2].reg);
11529 inst.instruction = THUMB_OP32 (inst.instruction);
11530 inst.instruction |= inst.operands[0].reg << 8;
11531 inst.instruction |= inst.operands[1].reg << 16;
11532 inst.instruction |= inst.operands[2].reg;
11536 inst.operands[1].shifted = 1;
11537 inst.operands[1].shift_kind = shift_kind;
11538 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11539 ? T_MNEM_movs : T_MNEM_mov);
11540 inst.instruction |= inst.operands[0].reg << 8;
11541 encode_thumb32_shifted_operand (1);
11542 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11543 inst.reloc.type = BFD_RELOC_UNUSED;
11548 if (inst.operands[2].isreg)
11550 switch (shift_kind)
11552 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11553 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11554 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11555 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11559 inst.instruction |= inst.operands[0].reg;
11560 inst.instruction |= inst.operands[2].reg << 3;
11564 switch (shift_kind)
11566 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11567 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11568 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11571 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11572 inst.instruction |= inst.operands[0].reg;
11573 inst.instruction |= inst.operands[1].reg << 3;
11579 constraint (inst.operands[0].reg > 7
11580 || inst.operands[1].reg > 7, BAD_HIREG);
11581 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11583 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11585 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11586 constraint (inst.operands[0].reg != inst.operands[1].reg,
11587 _("source1 and dest must be same register"));
11589 switch (inst.instruction)
11591 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11592 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11593 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11594 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11598 inst.instruction |= inst.operands[0].reg;
11599 inst.instruction |= inst.operands[2].reg << 3;
11603 switch (inst.instruction)
11605 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11606 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11607 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11608 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11611 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11612 inst.instruction |= inst.operands[0].reg;
11613 inst.instruction |= inst.operands[1].reg << 3;
11621 unsigned Rd, Rn, Rm;
11623 Rd = inst.operands[0].reg;
11624 Rn = inst.operands[1].reg;
11625 Rm = inst.operands[2].reg;
11627 reject_bad_reg (Rd);
11628 reject_bad_reg (Rn);
11629 reject_bad_reg (Rm);
11631 inst.instruction |= Rd << 8;
11632 inst.instruction |= Rn << 16;
11633 inst.instruction |= Rm;
11639 unsigned Rd, Rn, Rm;
11641 Rd = inst.operands[0].reg;
11642 Rm = inst.operands[1].reg;
11643 Rn = inst.operands[2].reg;
11645 reject_bad_reg (Rd);
11646 reject_bad_reg (Rn);
11647 reject_bad_reg (Rm);
11649 inst.instruction |= Rd << 8;
11650 inst.instruction |= Rn << 16;
11651 inst.instruction |= Rm;
11657 unsigned int value = inst.reloc.exp.X_add_number;
11658 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11659 _("SMC is not permitted on this architecture"));
11660 constraint (inst.reloc.exp.X_op != O_constant,
11661 _("expression too complex"));
11662 inst.reloc.type = BFD_RELOC_UNUSED;
11663 inst.instruction |= (value & 0xf000) >> 12;
11664 inst.instruction |= (value & 0x0ff0);
11665 inst.instruction |= (value & 0x000f) << 16;
11671 unsigned int value = inst.reloc.exp.X_add_number;
11673 inst.reloc.type = BFD_RELOC_UNUSED;
11674 inst.instruction |= (value & 0x0fff);
11675 inst.instruction |= (value & 0xf000) << 4;
11679 do_t_ssat_usat (int bias)
11683 Rd = inst.operands[0].reg;
11684 Rn = inst.operands[2].reg;
11686 reject_bad_reg (Rd);
11687 reject_bad_reg (Rn);
11689 inst.instruction |= Rd << 8;
11690 inst.instruction |= inst.operands[1].imm - bias;
11691 inst.instruction |= Rn << 16;
11693 if (inst.operands[3].present)
11695 offsetT shift_amount = inst.reloc.exp.X_add_number;
11697 inst.reloc.type = BFD_RELOC_UNUSED;
11699 constraint (inst.reloc.exp.X_op != O_constant,
11700 _("expression too complex"));
11702 if (shift_amount != 0)
11704 constraint (shift_amount > 31,
11705 _("shift expression is too large"));
11707 if (inst.operands[3].shift_kind == SHIFT_ASR)
11708 inst.instruction |= 0x00200000; /* sh bit. */
11710 inst.instruction |= (shift_amount & 0x1c) << 10;
11711 inst.instruction |= (shift_amount & 0x03) << 6;
11719 do_t_ssat_usat (1);
11727 Rd = inst.operands[0].reg;
11728 Rn = inst.operands[2].reg;
11730 reject_bad_reg (Rd);
11731 reject_bad_reg (Rn);
11733 inst.instruction |= Rd << 8;
11734 inst.instruction |= inst.operands[1].imm - 1;
11735 inst.instruction |= Rn << 16;
11741 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11742 || inst.operands[2].postind || inst.operands[2].writeback
11743 || inst.operands[2].immisreg || inst.operands[2].shifted
11744 || inst.operands[2].negative,
11747 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11749 inst.instruction |= inst.operands[0].reg << 8;
11750 inst.instruction |= inst.operands[1].reg << 12;
11751 inst.instruction |= inst.operands[2].reg << 16;
11752 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11758 if (!inst.operands[2].present)
11759 inst.operands[2].reg = inst.operands[1].reg + 1;
11761 constraint (inst.operands[0].reg == inst.operands[1].reg
11762 || inst.operands[0].reg == inst.operands[2].reg
11763 || inst.operands[0].reg == inst.operands[3].reg,
11766 inst.instruction |= inst.operands[0].reg;
11767 inst.instruction |= inst.operands[1].reg << 12;
11768 inst.instruction |= inst.operands[2].reg << 8;
11769 inst.instruction |= inst.operands[3].reg << 16;
11775 unsigned Rd, Rn, Rm;
11777 Rd = inst.operands[0].reg;
11778 Rn = inst.operands[1].reg;
11779 Rm = inst.operands[2].reg;
11781 reject_bad_reg (Rd);
11782 reject_bad_reg (Rn);
11783 reject_bad_reg (Rm);
11785 inst.instruction |= Rd << 8;
11786 inst.instruction |= Rn << 16;
11787 inst.instruction |= Rm;
11788 inst.instruction |= inst.operands[3].imm << 4;
11796 Rd = inst.operands[0].reg;
11797 Rm = inst.operands[1].reg;
11799 reject_bad_reg (Rd);
11800 reject_bad_reg (Rm);
11802 if (inst.instruction <= 0xffff
11803 && inst.size_req != 4
11804 && Rd <= 7 && Rm <= 7
11805 && (!inst.operands[2].present || inst.operands[2].imm == 0))
11807 inst.instruction = THUMB_OP16 (inst.instruction);
11808 inst.instruction |= Rd;
11809 inst.instruction |= Rm << 3;
11811 else if (unified_syntax)
11813 if (inst.instruction <= 0xffff)
11814 inst.instruction = THUMB_OP32 (inst.instruction);
11815 inst.instruction |= Rd << 8;
11816 inst.instruction |= Rm;
11817 inst.instruction |= inst.operands[2].imm << 4;
11821 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
11822 _("Thumb encoding does not support rotation"));
11823 constraint (1, BAD_HIREG);
11830 /* We have to do the following check manually as ARM_EXT_OS only applies
11832 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
11834 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
11835 /* This only applies to the v6m howver, not later architectures. */
11836 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
11837 as_bad (_("SVC is not permitted on this architecture"));
11838 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
11841 inst.reloc.type = BFD_RELOC_ARM_SWI;
11850 half = (inst.instruction & 0x10) != 0;
11851 set_it_insn_type_last ();
11852 constraint (inst.operands[0].immisreg,
11853 _("instruction requires register index"));
11855 Rn = inst.operands[0].reg;
11856 Rm = inst.operands[0].imm;
11858 constraint (Rn == REG_SP, BAD_SP);
11859 reject_bad_reg (Rm);
11861 constraint (!half && inst.operands[0].shifted,
11862 _("instruction does not allow shifted index"));
11863 inst.instruction |= (Rn << 16) | Rm;
11869 do_t_ssat_usat (0);
11877 Rd = inst.operands[0].reg;
11878 Rn = inst.operands[2].reg;
11880 reject_bad_reg (Rd);
11881 reject_bad_reg (Rn);
11883 inst.instruction |= Rd << 8;
11884 inst.instruction |= inst.operands[1].imm;
11885 inst.instruction |= Rn << 16;
11888 /* Neon instruction encoder helpers. */
11890 /* Encodings for the different types for various Neon opcodes. */
11892 /* An "invalid" code for the following tables. */
11895 struct neon_tab_entry
11898 unsigned float_or_poly;
11899 unsigned scalar_or_imm;
11902 /* Map overloaded Neon opcodes to their respective encodings. */
11903 #define NEON_ENC_TAB \
11904 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11905 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11906 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11907 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11908 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11909 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11910 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11911 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11912 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11913 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11914 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11915 /* Register variants of the following two instructions are encoded as
11916 vcge / vcgt with the operands reversed. */ \
11917 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11918 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11919 X(vfma, N_INV, 0x0000c10, N_INV), \
11920 X(vfms, N_INV, 0x0200c10, N_INV), \
11921 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11922 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11923 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11924 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11925 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11926 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11927 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11928 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11929 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11930 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11931 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11932 X(vshl, 0x0000400, N_INV, 0x0800510), \
11933 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11934 X(vand, 0x0000110, N_INV, 0x0800030), \
11935 X(vbic, 0x0100110, N_INV, 0x0800030), \
11936 X(veor, 0x1000110, N_INV, N_INV), \
11937 X(vorn, 0x0300110, N_INV, 0x0800010), \
11938 X(vorr, 0x0200110, N_INV, 0x0800010), \
11939 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11940 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11941 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11942 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11943 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11944 X(vst1, 0x0000000, 0x0800000, N_INV), \
11945 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11946 X(vst2, 0x0000100, 0x0800100, N_INV), \
11947 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11948 X(vst3, 0x0000200, 0x0800200, N_INV), \
11949 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11950 X(vst4, 0x0000300, 0x0800300, N_INV), \
11951 X(vmovn, 0x1b20200, N_INV, N_INV), \
11952 X(vtrn, 0x1b20080, N_INV, N_INV), \
11953 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11954 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11955 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11956 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11957 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11958 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11959 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11960 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11961 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11962 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11963 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11967 #define X(OPC,I,F,S) N_MNEM_##OPC
11972 static const struct neon_tab_entry neon_enc_tab[] =
11974 #define X(OPC,I,F,S) { (I), (F), (S) }
11979 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11980 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11981 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11982 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11983 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11984 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11985 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11986 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11987 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11988 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11989 #define NEON_ENC_SINGLE_(X) \
11990 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11991 #define NEON_ENC_DOUBLE_(X) \
11992 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11994 #define NEON_ENCODE(type, inst) \
11997 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11998 inst.is_neon = 1; \
12002 #define check_neon_suffixes \
12005 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12007 as_bad (_("invalid neon suffix for non neon instruction")); \
12013 /* Define shapes for instruction operands. The following mnemonic characters
12014 are used in this table:
12016 F - VFP S<n> register
12017 D - Neon D<n> register
12018 Q - Neon Q<n> register
12022 L - D<n> register list
12024 This table is used to generate various data:
12025 - enumerations of the form NS_DDR to be used as arguments to
12027 - a table classifying shapes into single, double, quad, mixed.
12028 - a table used to drive neon_select_shape. */
12030 #define NEON_SHAPE_DEF \
12031 X(3, (D, D, D), DOUBLE), \
12032 X(3, (Q, Q, Q), QUAD), \
12033 X(3, (D, D, I), DOUBLE), \
12034 X(3, (Q, Q, I), QUAD), \
12035 X(3, (D, D, S), DOUBLE), \
12036 X(3, (Q, Q, S), QUAD), \
12037 X(2, (D, D), DOUBLE), \
12038 X(2, (Q, Q), QUAD), \
12039 X(2, (D, S), DOUBLE), \
12040 X(2, (Q, S), QUAD), \
12041 X(2, (D, R), DOUBLE), \
12042 X(2, (Q, R), QUAD), \
12043 X(2, (D, I), DOUBLE), \
12044 X(2, (Q, I), QUAD), \
12045 X(3, (D, L, D), DOUBLE), \
12046 X(2, (D, Q), MIXED), \
12047 X(2, (Q, D), MIXED), \
12048 X(3, (D, Q, I), MIXED), \
12049 X(3, (Q, D, I), MIXED), \
12050 X(3, (Q, D, D), MIXED), \
12051 X(3, (D, Q, Q), MIXED), \
12052 X(3, (Q, Q, D), MIXED), \
12053 X(3, (Q, D, S), MIXED), \
12054 X(3, (D, Q, S), MIXED), \
12055 X(4, (D, D, D, I), DOUBLE), \
12056 X(4, (Q, Q, Q, I), QUAD), \
12057 X(2, (F, F), SINGLE), \
12058 X(3, (F, F, F), SINGLE), \
12059 X(2, (F, I), SINGLE), \
12060 X(2, (F, D), MIXED), \
12061 X(2, (D, F), MIXED), \
12062 X(3, (F, F, I), MIXED), \
12063 X(4, (R, R, F, F), SINGLE), \
12064 X(4, (F, F, R, R), SINGLE), \
12065 X(3, (D, R, R), DOUBLE), \
12066 X(3, (R, R, D), DOUBLE), \
12067 X(2, (S, R), SINGLE), \
12068 X(2, (R, S), SINGLE), \
12069 X(2, (F, R), SINGLE), \
12070 X(2, (R, F), SINGLE)
12072 #define S2(A,B) NS_##A##B
12073 #define S3(A,B,C) NS_##A##B##C
12074 #define S4(A,B,C,D) NS_##A##B##C##D
12076 #define X(N, L, C) S##N L
12089 enum neon_shape_class
12097 #define X(N, L, C) SC_##C
12099 static enum neon_shape_class neon_shape_class[] =
12117 /* Register widths of above. */
12118 static unsigned neon_shape_el_size[] =
12129 struct neon_shape_info
12132 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12135 #define S2(A,B) { SE_##A, SE_##B }
12136 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12137 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12139 #define X(N, L, C) { N, S##N L }
12141 static struct neon_shape_info neon_shape_tab[] =
12151 /* Bit masks used in type checking given instructions.
12152 'N_EQK' means the type must be the same as (or based on in some way) the key
12153 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12154 set, various other bits can be set as well in order to modify the meaning of
12155 the type constraint. */
12157 enum neon_type_mask
12180 N_KEY = 0x1000000, /* Key element (main type specifier). */
12181 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12182 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12183 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12184 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12185 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12186 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12187 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12188 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12189 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12191 N_MAX_NONSPECIAL = N_F64
12194 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12196 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12197 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12198 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12199 #define N_SUF_32 (N_SU_32 | N_F32)
12200 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12201 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12203 /* Pass this as the first type argument to neon_check_type to ignore types
12205 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12207 /* Select a "shape" for the current instruction (describing register types or
12208 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12209 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12210 function of operand parsing, so this function doesn't need to be called.
12211 Shapes should be listed in order of decreasing length. */
12213 static enum neon_shape
12214 neon_select_shape (enum neon_shape shape, ...)
12217 enum neon_shape first_shape = shape;
12219 /* Fix missing optional operands. FIXME: we don't know at this point how
12220 many arguments we should have, so this makes the assumption that we have
12221 > 1. This is true of all current Neon opcodes, I think, but may not be
12222 true in the future. */
12223 if (!inst.operands[1].present)
12224 inst.operands[1] = inst.operands[0];
12226 va_start (ap, shape);
12228 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12233 for (j = 0; j < neon_shape_tab[shape].els; j++)
12235 if (!inst.operands[j].present)
12241 switch (neon_shape_tab[shape].el[j])
12244 if (!(inst.operands[j].isreg
12245 && inst.operands[j].isvec
12246 && inst.operands[j].issingle
12247 && !inst.operands[j].isquad))
12252 if (!(inst.operands[j].isreg
12253 && inst.operands[j].isvec
12254 && !inst.operands[j].isquad
12255 && !inst.operands[j].issingle))
12260 if (!(inst.operands[j].isreg
12261 && !inst.operands[j].isvec))
12266 if (!(inst.operands[j].isreg
12267 && inst.operands[j].isvec
12268 && inst.operands[j].isquad
12269 && !inst.operands[j].issingle))
12274 if (!(!inst.operands[j].isreg
12275 && !inst.operands[j].isscalar))
12280 if (!(!inst.operands[j].isreg
12281 && inst.operands[j].isscalar))
12297 if (shape == NS_NULL && first_shape != NS_NULL)
12298 first_error (_("invalid instruction shape"));
12303 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12304 means the Q bit should be set). */
12307 neon_quad (enum neon_shape shape)
12309 return neon_shape_class[shape] == SC_QUAD;
12313 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12316 /* Allow modification to be made to types which are constrained to be
12317 based on the key element, based on bits set alongside N_EQK. */
12318 if ((typebits & N_EQK) != 0)
12320 if ((typebits & N_HLF) != 0)
12322 else if ((typebits & N_DBL) != 0)
12324 if ((typebits & N_SGN) != 0)
12325 *g_type = NT_signed;
12326 else if ((typebits & N_UNS) != 0)
12327 *g_type = NT_unsigned;
12328 else if ((typebits & N_INT) != 0)
12329 *g_type = NT_integer;
12330 else if ((typebits & N_FLT) != 0)
12331 *g_type = NT_float;
12332 else if ((typebits & N_SIZ) != 0)
12333 *g_type = NT_untyped;
12337 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12338 operand type, i.e. the single type specified in a Neon instruction when it
12339 is the only one given. */
12341 static struct neon_type_el
12342 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12344 struct neon_type_el dest = *key;
12346 gas_assert ((thisarg & N_EQK) != 0);
12348 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12353 /* Convert Neon type and size into compact bitmask representation. */
12355 static enum neon_type_mask
12356 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12363 case 8: return N_8;
12364 case 16: return N_16;
12365 case 32: return N_32;
12366 case 64: return N_64;
12374 case 8: return N_I8;
12375 case 16: return N_I16;
12376 case 32: return N_I32;
12377 case 64: return N_I64;
12385 case 16: return N_F16;
12386 case 32: return N_F32;
12387 case 64: return N_F64;
12395 case 8: return N_P8;
12396 case 16: return N_P16;
12404 case 8: return N_S8;
12405 case 16: return N_S16;
12406 case 32: return N_S32;
12407 case 64: return N_S64;
12415 case 8: return N_U8;
12416 case 16: return N_U16;
12417 case 32: return N_U32;
12418 case 64: return N_U64;
12429 /* Convert compact Neon bitmask type representation to a type and size. Only
12430 handles the case where a single bit is set in the mask. */
12433 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12434 enum neon_type_mask mask)
12436 if ((mask & N_EQK) != 0)
12439 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12441 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12443 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12445 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12450 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12452 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12453 *type = NT_unsigned;
12454 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12455 *type = NT_integer;
12456 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12457 *type = NT_untyped;
12458 else if ((mask & (N_P8 | N_P16)) != 0)
12460 else if ((mask & (N_F32 | N_F64)) != 0)
12468 /* Modify a bitmask of allowed types. This is only needed for type
12472 modify_types_allowed (unsigned allowed, unsigned mods)
12475 enum neon_el_type type;
12481 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12483 if (el_type_of_type_chk (&type, &size,
12484 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12486 neon_modify_type_size (mods, &type, &size);
12487 destmask |= type_chk_of_el_type (type, size);
12494 /* Check type and return type classification.
12495 The manual states (paraphrase): If one datatype is given, it indicates the
12497 - the second operand, if there is one
12498 - the operand, if there is no second operand
12499 - the result, if there are no operands.
12500 This isn't quite good enough though, so we use a concept of a "key" datatype
12501 which is set on a per-instruction basis, which is the one which matters when
12502 only one data type is written.
12503 Note: this function has side-effects (e.g. filling in missing operands). All
12504 Neon instructions should call it before performing bit encoding. */
12506 static struct neon_type_el
12507 neon_check_type (unsigned els, enum neon_shape ns, ...)
12510 unsigned i, pass, key_el = 0;
12511 unsigned types[NEON_MAX_TYPE_ELS];
12512 enum neon_el_type k_type = NT_invtype;
12513 unsigned k_size = -1u;
12514 struct neon_type_el badtype = {NT_invtype, -1};
12515 unsigned key_allowed = 0;
12517 /* Optional registers in Neon instructions are always (not) in operand 1.
12518 Fill in the missing operand here, if it was omitted. */
12519 if (els > 1 && !inst.operands[1].present)
12520 inst.operands[1] = inst.operands[0];
12522 /* Suck up all the varargs. */
12524 for (i = 0; i < els; i++)
12526 unsigned thisarg = va_arg (ap, unsigned);
12527 if (thisarg == N_IGNORE_TYPE)
12532 types[i] = thisarg;
12533 if ((thisarg & N_KEY) != 0)
12538 if (inst.vectype.elems > 0)
12539 for (i = 0; i < els; i++)
12540 if (inst.operands[i].vectype.type != NT_invtype)
12542 first_error (_("types specified in both the mnemonic and operands"));
12546 /* Duplicate inst.vectype elements here as necessary.
12547 FIXME: No idea if this is exactly the same as the ARM assembler,
12548 particularly when an insn takes one register and one non-register
12550 if (inst.vectype.elems == 1 && els > 1)
12553 inst.vectype.elems = els;
12554 inst.vectype.el[key_el] = inst.vectype.el[0];
12555 for (j = 0; j < els; j++)
12557 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12560 else if (inst.vectype.elems == 0 && els > 0)
12563 /* No types were given after the mnemonic, so look for types specified
12564 after each operand. We allow some flexibility here; as long as the
12565 "key" operand has a type, we can infer the others. */
12566 for (j = 0; j < els; j++)
12567 if (inst.operands[j].vectype.type != NT_invtype)
12568 inst.vectype.el[j] = inst.operands[j].vectype;
12570 if (inst.operands[key_el].vectype.type != NT_invtype)
12572 for (j = 0; j < els; j++)
12573 if (inst.operands[j].vectype.type == NT_invtype)
12574 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12579 first_error (_("operand types can't be inferred"));
12583 else if (inst.vectype.elems != els)
12585 first_error (_("type specifier has the wrong number of parts"));
12589 for (pass = 0; pass < 2; pass++)
12591 for (i = 0; i < els; i++)
12593 unsigned thisarg = types[i];
12594 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12595 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12596 enum neon_el_type g_type = inst.vectype.el[i].type;
12597 unsigned g_size = inst.vectype.el[i].size;
12599 /* Decay more-specific signed & unsigned types to sign-insensitive
12600 integer types if sign-specific variants are unavailable. */
12601 if ((g_type == NT_signed || g_type == NT_unsigned)
12602 && (types_allowed & N_SU_ALL) == 0)
12603 g_type = NT_integer;
12605 /* If only untyped args are allowed, decay any more specific types to
12606 them. Some instructions only care about signs for some element
12607 sizes, so handle that properly. */
12608 if ((g_size == 8 && (types_allowed & N_8) != 0)
12609 || (g_size == 16 && (types_allowed & N_16) != 0)
12610 || (g_size == 32 && (types_allowed & N_32) != 0)
12611 || (g_size == 64 && (types_allowed & N_64) != 0))
12612 g_type = NT_untyped;
12616 if ((thisarg & N_KEY) != 0)
12620 key_allowed = thisarg & ~N_KEY;
12625 if ((thisarg & N_VFP) != 0)
12627 enum neon_shape_el regshape;
12628 unsigned regwidth, match;
12630 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12633 first_error (_("invalid instruction shape"));
12636 regshape = neon_shape_tab[ns].el[i];
12637 regwidth = neon_shape_el_size[regshape];
12639 /* In VFP mode, operands must match register widths. If we
12640 have a key operand, use its width, else use the width of
12641 the current operand. */
12647 if (regwidth != match)
12649 first_error (_("operand size must match register width"));
12654 if ((thisarg & N_EQK) == 0)
12656 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12658 if ((given_type & types_allowed) == 0)
12660 first_error (_("bad type in Neon instruction"));
12666 enum neon_el_type mod_k_type = k_type;
12667 unsigned mod_k_size = k_size;
12668 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12669 if (g_type != mod_k_type || g_size != mod_k_size)
12671 first_error (_("inconsistent types in Neon instruction"));
12679 return inst.vectype.el[key_el];
12682 /* Neon-style VFP instruction forwarding. */
12684 /* Thumb VFP instructions have 0xE in the condition field. */
12687 do_vfp_cond_or_thumb (void)
12692 inst.instruction |= 0xe0000000;
12694 inst.instruction |= inst.cond << 28;
12697 /* Look up and encode a simple mnemonic, for use as a helper function for the
12698 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12699 etc. It is assumed that operand parsing has already been done, and that the
12700 operands are in the form expected by the given opcode (this isn't necessarily
12701 the same as the form in which they were parsed, hence some massaging must
12702 take place before this function is called).
12703 Checks current arch version against that in the looked-up opcode. */
12706 do_vfp_nsyn_opcode (const char *opname)
12708 const struct asm_opcode *opcode;
12710 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12715 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12716 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12723 inst.instruction = opcode->tvalue;
12724 opcode->tencode ();
12728 inst.instruction = (inst.cond << 28) | opcode->avalue;
12729 opcode->aencode ();
12734 do_vfp_nsyn_add_sub (enum neon_shape rs)
12736 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12741 do_vfp_nsyn_opcode ("fadds");
12743 do_vfp_nsyn_opcode ("fsubs");
12748 do_vfp_nsyn_opcode ("faddd");
12750 do_vfp_nsyn_opcode ("fsubd");
12754 /* Check operand types to see if this is a VFP instruction, and if so call
12758 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12760 enum neon_shape rs;
12761 struct neon_type_el et;
12766 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12767 et = neon_check_type (2, rs,
12768 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12772 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12773 et = neon_check_type (3, rs,
12774 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12781 if (et.type != NT_invtype)
12792 do_vfp_nsyn_mla_mls (enum neon_shape rs)
12794 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
12799 do_vfp_nsyn_opcode ("fmacs");
12801 do_vfp_nsyn_opcode ("fnmacs");
12806 do_vfp_nsyn_opcode ("fmacd");
12808 do_vfp_nsyn_opcode ("fnmacd");
12813 do_vfp_nsyn_fma_fms (enum neon_shape rs)
12815 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
12820 do_vfp_nsyn_opcode ("ffmas");
12822 do_vfp_nsyn_opcode ("ffnmas");
12827 do_vfp_nsyn_opcode ("ffmad");
12829 do_vfp_nsyn_opcode ("ffnmad");
12834 do_vfp_nsyn_mul (enum neon_shape rs)
12837 do_vfp_nsyn_opcode ("fmuls");
12839 do_vfp_nsyn_opcode ("fmuld");
12843 do_vfp_nsyn_abs_neg (enum neon_shape rs)
12845 int is_neg = (inst.instruction & 0x80) != 0;
12846 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
12851 do_vfp_nsyn_opcode ("fnegs");
12853 do_vfp_nsyn_opcode ("fabss");
12858 do_vfp_nsyn_opcode ("fnegd");
12860 do_vfp_nsyn_opcode ("fabsd");
12864 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12865 insns belong to Neon, and are handled elsewhere. */
12868 do_vfp_nsyn_ldm_stm (int is_dbmode)
12870 int is_ldm = (inst.instruction & (1 << 20)) != 0;
12874 do_vfp_nsyn_opcode ("fldmdbs");
12876 do_vfp_nsyn_opcode ("fldmias");
12881 do_vfp_nsyn_opcode ("fstmdbs");
12883 do_vfp_nsyn_opcode ("fstmias");
12888 do_vfp_nsyn_sqrt (void)
12890 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12891 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12894 do_vfp_nsyn_opcode ("fsqrts");
12896 do_vfp_nsyn_opcode ("fsqrtd");
12900 do_vfp_nsyn_div (void)
12902 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12903 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
12904 N_F32 | N_F64 | N_KEY | N_VFP);
12907 do_vfp_nsyn_opcode ("fdivs");
12909 do_vfp_nsyn_opcode ("fdivd");
12913 do_vfp_nsyn_nmul (void)
12915 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12916 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
12917 N_F32 | N_F64 | N_KEY | N_VFP);
12921 NEON_ENCODE (SINGLE, inst);
12922 do_vfp_sp_dyadic ();
12926 NEON_ENCODE (DOUBLE, inst);
12927 do_vfp_dp_rd_rn_rm ();
12929 do_vfp_cond_or_thumb ();
12933 do_vfp_nsyn_cmp (void)
12935 if (inst.operands[1].isreg)
12937 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12938 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12942 NEON_ENCODE (SINGLE, inst);
12943 do_vfp_sp_monadic ();
12947 NEON_ENCODE (DOUBLE, inst);
12948 do_vfp_dp_rd_rm ();
12953 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
12954 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
12956 switch (inst.instruction & 0x0fffffff)
12959 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
12962 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
12970 NEON_ENCODE (SINGLE, inst);
12971 do_vfp_sp_compare_z ();
12975 NEON_ENCODE (DOUBLE, inst);
12979 do_vfp_cond_or_thumb ();
12983 nsyn_insert_sp (void)
12985 inst.operands[1] = inst.operands[0];
12986 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
12987 inst.operands[0].reg = REG_SP;
12988 inst.operands[0].isreg = 1;
12989 inst.operands[0].writeback = 1;
12990 inst.operands[0].present = 1;
12994 do_vfp_nsyn_push (void)
12997 if (inst.operands[1].issingle)
12998 do_vfp_nsyn_opcode ("fstmdbs");
13000 do_vfp_nsyn_opcode ("fstmdbd");
13004 do_vfp_nsyn_pop (void)
13007 if (inst.operands[1].issingle)
13008 do_vfp_nsyn_opcode ("fldmias");
13010 do_vfp_nsyn_opcode ("fldmiad");
13013 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13014 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13017 neon_dp_fixup (struct arm_it* insn)
13019 unsigned int i = insn->instruction;
13024 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13035 insn->instruction = i;
13038 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13042 neon_logbits (unsigned x)
13044 return ffs (x) - 4;
13047 #define LOW4(R) ((R) & 0xf)
13048 #define HI1(R) (((R) >> 4) & 1)
13050 /* Encode insns with bit pattern:
13052 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13053 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13055 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13056 different meaning for some instruction. */
13059 neon_three_same (int isquad, int ubit, int size)
13061 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13062 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13063 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13064 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13065 inst.instruction |= LOW4 (inst.operands[2].reg);
13066 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13067 inst.instruction |= (isquad != 0) << 6;
13068 inst.instruction |= (ubit != 0) << 24;
13070 inst.instruction |= neon_logbits (size) << 20;
13072 neon_dp_fixup (&inst);
13075 /* Encode instructions of the form:
13077 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13078 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13080 Don't write size if SIZE == -1. */
13083 neon_two_same (int qbit, int ubit, int size)
13085 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13086 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13087 inst.instruction |= LOW4 (inst.operands[1].reg);
13088 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13089 inst.instruction |= (qbit != 0) << 6;
13090 inst.instruction |= (ubit != 0) << 24;
13093 inst.instruction |= neon_logbits (size) << 18;
13095 neon_dp_fixup (&inst);
13098 /* Neon instruction encoders, in approximate order of appearance. */
13101 do_neon_dyadic_i_su (void)
13103 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13104 struct neon_type_el et = neon_check_type (3, rs,
13105 N_EQK, N_EQK, N_SU_32 | N_KEY);
13106 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13110 do_neon_dyadic_i64_su (void)
13112 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13113 struct neon_type_el et = neon_check_type (3, rs,
13114 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13115 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13119 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13122 unsigned size = et.size >> 3;
13123 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13124 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13125 inst.instruction |= LOW4 (inst.operands[1].reg);
13126 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13127 inst.instruction |= (isquad != 0) << 6;
13128 inst.instruction |= immbits << 16;
13129 inst.instruction |= (size >> 3) << 7;
13130 inst.instruction |= (size & 0x7) << 19;
13132 inst.instruction |= (uval != 0) << 24;
13134 neon_dp_fixup (&inst);
13138 do_neon_shl_imm (void)
13140 if (!inst.operands[2].isreg)
13142 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13143 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13144 NEON_ENCODE (IMMED, inst);
13145 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13149 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13150 struct neon_type_el et = neon_check_type (3, rs,
13151 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13154 /* VSHL/VQSHL 3-register variants have syntax such as:
13156 whereas other 3-register operations encoded by neon_three_same have
13159 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13161 tmp = inst.operands[2].reg;
13162 inst.operands[2].reg = inst.operands[1].reg;
13163 inst.operands[1].reg = tmp;
13164 NEON_ENCODE (INTEGER, inst);
13165 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13170 do_neon_qshl_imm (void)
13172 if (!inst.operands[2].isreg)
13174 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13175 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13177 NEON_ENCODE (IMMED, inst);
13178 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13179 inst.operands[2].imm);
13183 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13184 struct neon_type_el et = neon_check_type (3, rs,
13185 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13188 /* See note in do_neon_shl_imm. */
13189 tmp = inst.operands[2].reg;
13190 inst.operands[2].reg = inst.operands[1].reg;
13191 inst.operands[1].reg = tmp;
13192 NEON_ENCODE (INTEGER, inst);
13193 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13198 do_neon_rshl (void)
13200 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13201 struct neon_type_el et = neon_check_type (3, rs,
13202 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13205 tmp = inst.operands[2].reg;
13206 inst.operands[2].reg = inst.operands[1].reg;
13207 inst.operands[1].reg = tmp;
13208 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13212 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13214 /* Handle .I8 pseudo-instructions. */
13217 /* Unfortunately, this will make everything apart from zero out-of-range.
13218 FIXME is this the intended semantics? There doesn't seem much point in
13219 accepting .I8 if so. */
13220 immediate |= immediate << 8;
13226 if (immediate == (immediate & 0x000000ff))
13228 *immbits = immediate;
13231 else if (immediate == (immediate & 0x0000ff00))
13233 *immbits = immediate >> 8;
13236 else if (immediate == (immediate & 0x00ff0000))
13238 *immbits = immediate >> 16;
13241 else if (immediate == (immediate & 0xff000000))
13243 *immbits = immediate >> 24;
13246 if ((immediate & 0xffff) != (immediate >> 16))
13247 goto bad_immediate;
13248 immediate &= 0xffff;
13251 if (immediate == (immediate & 0x000000ff))
13253 *immbits = immediate;
13256 else if (immediate == (immediate & 0x0000ff00))
13258 *immbits = immediate >> 8;
13263 first_error (_("immediate value out of range"));
13267 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13271 neon_bits_same_in_bytes (unsigned imm)
13273 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13274 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13275 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13276 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13279 /* For immediate of above form, return 0bABCD. */
13282 neon_squash_bits (unsigned imm)
13284 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13285 | ((imm & 0x01000000) >> 21);
13288 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13291 neon_qfloat_bits (unsigned imm)
13293 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13296 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13297 the instruction. *OP is passed as the initial value of the op field, and
13298 may be set to a different value depending on the constant (i.e.
13299 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13300 MVN). If the immediate looks like a repeated pattern then also
13301 try smaller element sizes. */
13304 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13305 unsigned *immbits, int *op, int size,
13306 enum neon_el_type type)
13308 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13310 if (type == NT_float && !float_p)
13313 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13315 if (size != 32 || *op == 1)
13317 *immbits = neon_qfloat_bits (immlo);
13323 if (neon_bits_same_in_bytes (immhi)
13324 && neon_bits_same_in_bytes (immlo))
13328 *immbits = (neon_squash_bits (immhi) << 4)
13329 | neon_squash_bits (immlo);
13334 if (immhi != immlo)
13340 if (immlo == (immlo & 0x000000ff))
13345 else if (immlo == (immlo & 0x0000ff00))
13347 *immbits = immlo >> 8;
13350 else if (immlo == (immlo & 0x00ff0000))
13352 *immbits = immlo >> 16;
13355 else if (immlo == (immlo & 0xff000000))
13357 *immbits = immlo >> 24;
13360 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13362 *immbits = (immlo >> 8) & 0xff;
13365 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13367 *immbits = (immlo >> 16) & 0xff;
13371 if ((immlo & 0xffff) != (immlo >> 16))
13378 if (immlo == (immlo & 0x000000ff))
13383 else if (immlo == (immlo & 0x0000ff00))
13385 *immbits = immlo >> 8;
13389 if ((immlo & 0xff) != (immlo >> 8))
13394 if (immlo == (immlo & 0x000000ff))
13396 /* Don't allow MVN with 8-bit immediate. */
13406 /* Write immediate bits [7:0] to the following locations:
13408 |28/24|23 19|18 16|15 4|3 0|
13409 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13411 This function is used by VMOV/VMVN/VORR/VBIC. */
13414 neon_write_immbits (unsigned immbits)
13416 inst.instruction |= immbits & 0xf;
13417 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13418 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13421 /* Invert low-order SIZE bits of XHI:XLO. */
13424 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13426 unsigned immlo = xlo ? *xlo : 0;
13427 unsigned immhi = xhi ? *xhi : 0;
13432 immlo = (~immlo) & 0xff;
13436 immlo = (~immlo) & 0xffff;
13440 immhi = (~immhi) & 0xffffffff;
13441 /* fall through. */
13444 immlo = (~immlo) & 0xffffffff;
13459 do_neon_logic (void)
13461 if (inst.operands[2].present && inst.operands[2].isreg)
13463 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13464 neon_check_type (3, rs, N_IGNORE_TYPE);
13465 /* U bit and size field were set as part of the bitmask. */
13466 NEON_ENCODE (INTEGER, inst);
13467 neon_three_same (neon_quad (rs), 0, -1);
13471 const int three_ops_form = (inst.operands[2].present
13472 && !inst.operands[2].isreg);
13473 const int immoperand = (three_ops_form ? 2 : 1);
13474 enum neon_shape rs = (three_ops_form
13475 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13476 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13477 struct neon_type_el et = neon_check_type (2, rs,
13478 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13479 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13483 if (et.type == NT_invtype)
13486 if (three_ops_form)
13487 constraint (inst.operands[0].reg != inst.operands[1].reg,
13488 _("first and second operands shall be the same register"));
13490 NEON_ENCODE (IMMED, inst);
13492 immbits = inst.operands[immoperand].imm;
13495 /* .i64 is a pseudo-op, so the immediate must be a repeating
13497 if (immbits != (inst.operands[immoperand].regisimm ?
13498 inst.operands[immoperand].reg : 0))
13500 /* Set immbits to an invalid constant. */
13501 immbits = 0xdeadbeef;
13508 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13512 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13516 /* Pseudo-instruction for VBIC. */
13517 neon_invert_size (&immbits, 0, et.size);
13518 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13522 /* Pseudo-instruction for VORR. */
13523 neon_invert_size (&immbits, 0, et.size);
13524 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13534 inst.instruction |= neon_quad (rs) << 6;
13535 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13536 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13537 inst.instruction |= cmode << 8;
13538 neon_write_immbits (immbits);
13540 neon_dp_fixup (&inst);
13545 do_neon_bitfield (void)
13547 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13548 neon_check_type (3, rs, N_IGNORE_TYPE);
13549 neon_three_same (neon_quad (rs), 0, -1);
13553 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13556 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13557 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13559 if (et.type == NT_float)
13561 NEON_ENCODE (FLOAT, inst);
13562 neon_three_same (neon_quad (rs), 0, -1);
13566 NEON_ENCODE (INTEGER, inst);
13567 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13572 do_neon_dyadic_if_su (void)
13574 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13578 do_neon_dyadic_if_su_d (void)
13580 /* This version only allow D registers, but that constraint is enforced during
13581 operand parsing so we don't need to do anything extra here. */
13582 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13586 do_neon_dyadic_if_i_d (void)
13588 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13589 affected if we specify unsigned args. */
13590 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13593 enum vfp_or_neon_is_neon_bits
13596 NEON_CHECK_ARCH = 2
13599 /* Call this function if an instruction which may have belonged to the VFP or
13600 Neon instruction sets, but turned out to be a Neon instruction (due to the
13601 operand types involved, etc.). We have to check and/or fix-up a couple of
13604 - Make sure the user hasn't attempted to make a Neon instruction
13606 - Alter the value in the condition code field if necessary.
13607 - Make sure that the arch supports Neon instructions.
13609 Which of these operations take place depends on bits from enum
13610 vfp_or_neon_is_neon_bits.
13612 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13613 current instruction's condition is COND_ALWAYS, the condition field is
13614 changed to inst.uncond_value. This is necessary because instructions shared
13615 between VFP and Neon may be conditional for the VFP variants only, and the
13616 unconditional Neon version must have, e.g., 0xF in the condition field. */
13619 vfp_or_neon_is_neon (unsigned check)
13621 /* Conditions are always legal in Thumb mode (IT blocks). */
13622 if (!thumb_mode && (check & NEON_CHECK_CC))
13624 if (inst.cond != COND_ALWAYS)
13626 first_error (_(BAD_COND));
13629 if (inst.uncond_value != -1)
13630 inst.instruction |= inst.uncond_value << 28;
13633 if ((check & NEON_CHECK_ARCH)
13634 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13636 first_error (_(BAD_FPU));
13644 do_neon_addsub_if_i (void)
13646 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13649 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13652 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13653 affected if we specify unsigned args. */
13654 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13657 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13659 V<op> A,B (A is operand 0, B is operand 2)
13664 so handle that case specially. */
13667 neon_exchange_operands (void)
13669 void *scratch = alloca (sizeof (inst.operands[0]));
13670 if (inst.operands[1].present)
13672 /* Swap operands[1] and operands[2]. */
13673 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13674 inst.operands[1] = inst.operands[2];
13675 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13679 inst.operands[1] = inst.operands[2];
13680 inst.operands[2] = inst.operands[0];
13685 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13687 if (inst.operands[2].isreg)
13690 neon_exchange_operands ();
13691 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13695 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13696 struct neon_type_el et = neon_check_type (2, rs,
13697 N_EQK | N_SIZ, immtypes | N_KEY);
13699 NEON_ENCODE (IMMED, inst);
13700 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13701 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13702 inst.instruction |= LOW4 (inst.operands[1].reg);
13703 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13704 inst.instruction |= neon_quad (rs) << 6;
13705 inst.instruction |= (et.type == NT_float) << 10;
13706 inst.instruction |= neon_logbits (et.size) << 18;
13708 neon_dp_fixup (&inst);
13715 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13719 do_neon_cmp_inv (void)
13721 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13727 neon_compare (N_IF_32, N_IF_32, FALSE);
13730 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13731 scalars, which are encoded in 5 bits, M : Rm.
13732 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13733 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13737 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13739 unsigned regno = NEON_SCALAR_REG (scalar);
13740 unsigned elno = NEON_SCALAR_INDEX (scalar);
13745 if (regno > 7 || elno > 3)
13747 return regno | (elno << 3);
13750 if (regno > 15 || elno > 1)
13752 return regno | (elno << 4);
13756 first_error (_("scalar out of range for multiply instruction"));
13762 /* Encode multiply / multiply-accumulate scalar instructions. */
13765 neon_mul_mac (struct neon_type_el et, int ubit)
13769 /* Give a more helpful error message if we have an invalid type. */
13770 if (et.type == NT_invtype)
13773 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
13774 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13775 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13776 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13777 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13778 inst.instruction |= LOW4 (scalar);
13779 inst.instruction |= HI1 (scalar) << 5;
13780 inst.instruction |= (et.type == NT_float) << 8;
13781 inst.instruction |= neon_logbits (et.size) << 20;
13782 inst.instruction |= (ubit != 0) << 24;
13784 neon_dp_fixup (&inst);
13788 do_neon_mac_maybe_scalar (void)
13790 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
13793 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13796 if (inst.operands[2].isscalar)
13798 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13799 struct neon_type_el et = neon_check_type (3, rs,
13800 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
13801 NEON_ENCODE (SCALAR, inst);
13802 neon_mul_mac (et, neon_quad (rs));
13806 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13807 affected if we specify unsigned args. */
13808 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13813 do_neon_fmac (void)
13815 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
13818 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13821 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13827 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13828 struct neon_type_el et = neon_check_type (3, rs,
13829 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
13830 neon_three_same (neon_quad (rs), 0, et.size);
13833 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13834 same types as the MAC equivalents. The polynomial type for this instruction
13835 is encoded the same as the integer type. */
13840 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
13843 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13846 if (inst.operands[2].isscalar)
13847 do_neon_mac_maybe_scalar ();
13849 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
13853 do_neon_qdmulh (void)
13855 if (inst.operands[2].isscalar)
13857 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13858 struct neon_type_el et = neon_check_type (3, rs,
13859 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13860 NEON_ENCODE (SCALAR, inst);
13861 neon_mul_mac (et, neon_quad (rs));
13865 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13866 struct neon_type_el et = neon_check_type (3, rs,
13867 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13868 NEON_ENCODE (INTEGER, inst);
13869 /* The U bit (rounding) comes from bit mask. */
13870 neon_three_same (neon_quad (rs), 0, et.size);
13875 do_neon_fcmp_absolute (void)
13877 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13878 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
13879 /* Size field comes from bit mask. */
13880 neon_three_same (neon_quad (rs), 1, -1);
13884 do_neon_fcmp_absolute_inv (void)
13886 neon_exchange_operands ();
13887 do_neon_fcmp_absolute ();
13891 do_neon_step (void)
13893 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13894 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
13895 neon_three_same (neon_quad (rs), 0, -1);
13899 do_neon_abs_neg (void)
13901 enum neon_shape rs;
13902 struct neon_type_el et;
13904 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
13907 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13910 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13911 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
13913 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13914 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13915 inst.instruction |= LOW4 (inst.operands[1].reg);
13916 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13917 inst.instruction |= neon_quad (rs) << 6;
13918 inst.instruction |= (et.type == NT_float) << 10;
13919 inst.instruction |= neon_logbits (et.size) << 18;
13921 neon_dp_fixup (&inst);
13927 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13928 struct neon_type_el et = neon_check_type (2, rs,
13929 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
13930 int imm = inst.operands[2].imm;
13931 constraint (imm < 0 || (unsigned)imm >= et.size,
13932 _("immediate out of range for insert"));
13933 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
13939 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13940 struct neon_type_el et = neon_check_type (2, rs,
13941 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
13942 int imm = inst.operands[2].imm;
13943 constraint (imm < 1 || (unsigned)imm > et.size,
13944 _("immediate out of range for insert"));
13945 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
13949 do_neon_qshlu_imm (void)
13951 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13952 struct neon_type_el et = neon_check_type (2, rs,
13953 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
13954 int imm = inst.operands[2].imm;
13955 constraint (imm < 0 || (unsigned)imm >= et.size,
13956 _("immediate out of range for shift"));
13957 /* Only encodes the 'U present' variant of the instruction.
13958 In this case, signed types have OP (bit 8) set to 0.
13959 Unsigned types have OP set to 1. */
13960 inst.instruction |= (et.type == NT_unsigned) << 8;
13961 /* The rest of the bits are the same as other immediate shifts. */
13962 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
13966 do_neon_qmovn (void)
13968 struct neon_type_el et = neon_check_type (2, NS_DQ,
13969 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
13970 /* Saturating move where operands can be signed or unsigned, and the
13971 destination has the same signedness. */
13972 NEON_ENCODE (INTEGER, inst);
13973 if (et.type == NT_unsigned)
13974 inst.instruction |= 0xc0;
13976 inst.instruction |= 0x80;
13977 neon_two_same (0, 1, et.size / 2);
13981 do_neon_qmovun (void)
13983 struct neon_type_el et = neon_check_type (2, NS_DQ,
13984 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
13985 /* Saturating move with unsigned results. Operands must be signed. */
13986 NEON_ENCODE (INTEGER, inst);
13987 neon_two_same (0, 1, et.size / 2);
13991 do_neon_rshift_sat_narrow (void)
13993 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13994 or unsigned. If operands are unsigned, results must also be unsigned. */
13995 struct neon_type_el et = neon_check_type (2, NS_DQI,
13996 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
13997 int imm = inst.operands[2].imm;
13998 /* This gets the bounds check, size encoding and immediate bits calculation
14002 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14003 VQMOVN.I<size> <Dd>, <Qm>. */
14006 inst.operands[2].present = 0;
14007 inst.instruction = N_MNEM_vqmovn;
14012 constraint (imm < 1 || (unsigned)imm > et.size,
14013 _("immediate out of range"));
14014 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14018 do_neon_rshift_sat_narrow_u (void)
14020 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14021 or unsigned. If operands are unsigned, results must also be unsigned. */
14022 struct neon_type_el et = neon_check_type (2, NS_DQI,
14023 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14024 int imm = inst.operands[2].imm;
14025 /* This gets the bounds check, size encoding and immediate bits calculation
14029 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14030 VQMOVUN.I<size> <Dd>, <Qm>. */
14033 inst.operands[2].present = 0;
14034 inst.instruction = N_MNEM_vqmovun;
14039 constraint (imm < 1 || (unsigned)imm > et.size,
14040 _("immediate out of range"));
14041 /* FIXME: The manual is kind of unclear about what value U should have in
14042 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14044 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14048 do_neon_movn (void)
14050 struct neon_type_el et = neon_check_type (2, NS_DQ,
14051 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14052 NEON_ENCODE (INTEGER, inst);
14053 neon_two_same (0, 1, et.size / 2);
14057 do_neon_rshift_narrow (void)
14059 struct neon_type_el et = neon_check_type (2, NS_DQI,
14060 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14061 int imm = inst.operands[2].imm;
14062 /* This gets the bounds check, size encoding and immediate bits calculation
14066 /* If immediate is zero then we are a pseudo-instruction for
14067 VMOVN.I<size> <Dd>, <Qm> */
14070 inst.operands[2].present = 0;
14071 inst.instruction = N_MNEM_vmovn;
14076 constraint (imm < 1 || (unsigned)imm > et.size,
14077 _("immediate out of range for narrowing operation"));
14078 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14082 do_neon_shll (void)
14084 /* FIXME: Type checking when lengthening. */
14085 struct neon_type_el et = neon_check_type (2, NS_QDI,
14086 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14087 unsigned imm = inst.operands[2].imm;
14089 if (imm == et.size)
14091 /* Maximum shift variant. */
14092 NEON_ENCODE (INTEGER, inst);
14093 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14094 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14095 inst.instruction |= LOW4 (inst.operands[1].reg);
14096 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14097 inst.instruction |= neon_logbits (et.size) << 18;
14099 neon_dp_fixup (&inst);
14103 /* A more-specific type check for non-max versions. */
14104 et = neon_check_type (2, NS_QDI,
14105 N_EQK | N_DBL, N_SU_32 | N_KEY);
14106 NEON_ENCODE (IMMED, inst);
14107 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14111 /* Check the various types for the VCVT instruction, and return which version
14112 the current instruction is. */
14115 neon_cvt_flavour (enum neon_shape rs)
14117 #define CVT_VAR(C,X,Y) \
14118 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14119 if (et.type != NT_invtype) \
14121 inst.error = NULL; \
14124 struct neon_type_el et;
14125 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14126 || rs == NS_FF) ? N_VFP : 0;
14127 /* The instruction versions which take an immediate take one register
14128 argument, which is extended to the width of the full register. Thus the
14129 "source" and "destination" registers must have the same width. Hack that
14130 here by making the size equal to the key (wider, in this case) operand. */
14131 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14133 CVT_VAR (0, N_S32, N_F32);
14134 CVT_VAR (1, N_U32, N_F32);
14135 CVT_VAR (2, N_F32, N_S32);
14136 CVT_VAR (3, N_F32, N_U32);
14137 /* Half-precision conversions. */
14138 CVT_VAR (4, N_F32, N_F16);
14139 CVT_VAR (5, N_F16, N_F32);
14143 /* VFP instructions. */
14144 CVT_VAR (6, N_F32, N_F64);
14145 CVT_VAR (7, N_F64, N_F32);
14146 CVT_VAR (8, N_S32, N_F64 | key);
14147 CVT_VAR (9, N_U32, N_F64 | key);
14148 CVT_VAR (10, N_F64 | key, N_S32);
14149 CVT_VAR (11, N_F64 | key, N_U32);
14150 /* VFP instructions with bitshift. */
14151 CVT_VAR (12, N_F32 | key, N_S16);
14152 CVT_VAR (13, N_F32 | key, N_U16);
14153 CVT_VAR (14, N_F64 | key, N_S16);
14154 CVT_VAR (15, N_F64 | key, N_U16);
14155 CVT_VAR (16, N_S16, N_F32 | key);
14156 CVT_VAR (17, N_U16, N_F32 | key);
14157 CVT_VAR (18, N_S16, N_F64 | key);
14158 CVT_VAR (19, N_U16, N_F64 | key);
14164 /* Neon-syntax VFP conversions. */
14167 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14169 const char *opname = 0;
14171 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14173 /* Conversions with immediate bitshift. */
14174 const char *enc[] =
14198 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14200 opname = enc[flavour];
14201 constraint (inst.operands[0].reg != inst.operands[1].reg,
14202 _("operands 0 and 1 must be the same register"));
14203 inst.operands[1] = inst.operands[2];
14204 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14209 /* Conversions without bitshift. */
14210 const char *enc[] =
14226 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14227 opname = enc[flavour];
14231 do_vfp_nsyn_opcode (opname);
14235 do_vfp_nsyn_cvtz (void)
14237 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14238 int flavour = neon_cvt_flavour (rs);
14239 const char *enc[] =
14253 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14254 do_vfp_nsyn_opcode (enc[flavour]);
14258 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14260 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14261 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14262 int flavour = neon_cvt_flavour (rs);
14264 /* PR11109: Handle round-to-zero for VCVT conversions. */
14266 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14267 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14268 && (rs == NS_FD || rs == NS_FF))
14270 do_vfp_nsyn_cvtz ();
14274 /* VFP rather than Neon conversions. */
14277 do_vfp_nsyn_cvt (rs, flavour);
14287 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14289 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14292 /* Fixed-point conversion with #0 immediate is encoded as an
14293 integer conversion. */
14294 if (inst.operands[2].present && inst.operands[2].imm == 0)
14296 immbits = 32 - inst.operands[2].imm;
14297 NEON_ENCODE (IMMED, inst);
14299 inst.instruction |= enctab[flavour];
14300 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14301 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14302 inst.instruction |= LOW4 (inst.operands[1].reg);
14303 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14304 inst.instruction |= neon_quad (rs) << 6;
14305 inst.instruction |= 1 << 21;
14306 inst.instruction |= immbits << 16;
14308 neon_dp_fixup (&inst);
14316 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14318 NEON_ENCODE (INTEGER, inst);
14320 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14324 inst.instruction |= enctab[flavour];
14326 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14327 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14328 inst.instruction |= LOW4 (inst.operands[1].reg);
14329 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14330 inst.instruction |= neon_quad (rs) << 6;
14331 inst.instruction |= 2 << 18;
14333 neon_dp_fixup (&inst);
14337 /* Half-precision conversions for Advanced SIMD -- neon. */
14342 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14344 as_bad (_("operand size must match register width"));
14349 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14351 as_bad (_("operand size must match register width"));
14356 inst.instruction = 0x3b60600;
14358 inst.instruction = 0x3b60700;
14360 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14361 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14362 inst.instruction |= LOW4 (inst.operands[1].reg);
14363 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14364 neon_dp_fixup (&inst);
14368 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14369 do_vfp_nsyn_cvt (rs, flavour);
14374 do_neon_cvtr (void)
14376 do_neon_cvt_1 (FALSE);
14382 do_neon_cvt_1 (TRUE);
14386 do_neon_cvtb (void)
14388 inst.instruction = 0xeb20a40;
14390 /* The sizes are attached to the mnemonic. */
14391 if (inst.vectype.el[0].type != NT_invtype
14392 && inst.vectype.el[0].size == 16)
14393 inst.instruction |= 0x00010000;
14395 /* Programmer's syntax: the sizes are attached to the operands. */
14396 else if (inst.operands[0].vectype.type != NT_invtype
14397 && inst.operands[0].vectype.size == 16)
14398 inst.instruction |= 0x00010000;
14400 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14401 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14402 do_vfp_cond_or_thumb ();
14407 do_neon_cvtt (void)
14410 inst.instruction |= 0x80;
14414 neon_move_immediate (void)
14416 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14417 struct neon_type_el et = neon_check_type (2, rs,
14418 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14419 unsigned immlo, immhi = 0, immbits;
14420 int op, cmode, float_p;
14422 constraint (et.type == NT_invtype,
14423 _("operand size must be specified for immediate VMOV"));
14425 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14426 op = (inst.instruction & (1 << 5)) != 0;
14428 immlo = inst.operands[1].imm;
14429 if (inst.operands[1].regisimm)
14430 immhi = inst.operands[1].reg;
14432 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14433 _("immediate has bits set outside the operand size"));
14435 float_p = inst.operands[1].immisfloat;
14437 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14438 et.size, et.type)) == FAIL)
14440 /* Invert relevant bits only. */
14441 neon_invert_size (&immlo, &immhi, et.size);
14442 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14443 with one or the other; those cases are caught by
14444 neon_cmode_for_move_imm. */
14446 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14447 &op, et.size, et.type)) == FAIL)
14449 first_error (_("immediate out of range"));
14454 inst.instruction &= ~(1 << 5);
14455 inst.instruction |= op << 5;
14457 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14458 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14459 inst.instruction |= neon_quad (rs) << 6;
14460 inst.instruction |= cmode << 8;
14462 neon_write_immbits (immbits);
14468 if (inst.operands[1].isreg)
14470 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14472 NEON_ENCODE (INTEGER, inst);
14473 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14474 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14475 inst.instruction |= LOW4 (inst.operands[1].reg);
14476 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14477 inst.instruction |= neon_quad (rs) << 6;
14481 NEON_ENCODE (IMMED, inst);
14482 neon_move_immediate ();
14485 neon_dp_fixup (&inst);
14488 /* Encode instructions of form:
14490 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14491 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14494 neon_mixed_length (struct neon_type_el et, unsigned size)
14496 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14497 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14498 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14499 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14500 inst.instruction |= LOW4 (inst.operands[2].reg);
14501 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14502 inst.instruction |= (et.type == NT_unsigned) << 24;
14503 inst.instruction |= neon_logbits (size) << 20;
14505 neon_dp_fixup (&inst);
14509 do_neon_dyadic_long (void)
14511 /* FIXME: Type checking for lengthening op. */
14512 struct neon_type_el et = neon_check_type (3, NS_QDD,
14513 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14514 neon_mixed_length (et, et.size);
14518 do_neon_abal (void)
14520 struct neon_type_el et = neon_check_type (3, NS_QDD,
14521 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14522 neon_mixed_length (et, et.size);
14526 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14528 if (inst.operands[2].isscalar)
14530 struct neon_type_el et = neon_check_type (3, NS_QDS,
14531 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14532 NEON_ENCODE (SCALAR, inst);
14533 neon_mul_mac (et, et.type == NT_unsigned);
14537 struct neon_type_el et = neon_check_type (3, NS_QDD,
14538 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14539 NEON_ENCODE (INTEGER, inst);
14540 neon_mixed_length (et, et.size);
14545 do_neon_mac_maybe_scalar_long (void)
14547 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14551 do_neon_dyadic_wide (void)
14553 struct neon_type_el et = neon_check_type (3, NS_QQD,
14554 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14555 neon_mixed_length (et, et.size);
14559 do_neon_dyadic_narrow (void)
14561 struct neon_type_el et = neon_check_type (3, NS_QDD,
14562 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14563 /* Operand sign is unimportant, and the U bit is part of the opcode,
14564 so force the operand type to integer. */
14565 et.type = NT_integer;
14566 neon_mixed_length (et, et.size / 2);
14570 do_neon_mul_sat_scalar_long (void)
14572 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14576 do_neon_vmull (void)
14578 if (inst.operands[2].isscalar)
14579 do_neon_mac_maybe_scalar_long ();
14582 struct neon_type_el et = neon_check_type (3, NS_QDD,
14583 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14584 if (et.type == NT_poly)
14585 NEON_ENCODE (POLY, inst);
14587 NEON_ENCODE (INTEGER, inst);
14588 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14589 zero. Should be OK as-is. */
14590 neon_mixed_length (et, et.size);
14597 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14598 struct neon_type_el et = neon_check_type (3, rs,
14599 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14600 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14602 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14603 _("shift out of range"));
14604 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14605 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14606 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14607 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14608 inst.instruction |= LOW4 (inst.operands[2].reg);
14609 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14610 inst.instruction |= neon_quad (rs) << 6;
14611 inst.instruction |= imm << 8;
14613 neon_dp_fixup (&inst);
14619 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14620 struct neon_type_el et = neon_check_type (2, rs,
14621 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14622 unsigned op = (inst.instruction >> 7) & 3;
14623 /* N (width of reversed regions) is encoded as part of the bitmask. We
14624 extract it here to check the elements to be reversed are smaller.
14625 Otherwise we'd get a reserved instruction. */
14626 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14627 gas_assert (elsize != 0);
14628 constraint (et.size >= elsize,
14629 _("elements must be smaller than reversal region"));
14630 neon_two_same (neon_quad (rs), 1, et.size);
14636 if (inst.operands[1].isscalar)
14638 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14639 struct neon_type_el et = neon_check_type (2, rs,
14640 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14641 unsigned sizebits = et.size >> 3;
14642 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14643 int logsize = neon_logbits (et.size);
14644 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14646 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14649 NEON_ENCODE (SCALAR, inst);
14650 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14651 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14652 inst.instruction |= LOW4 (dm);
14653 inst.instruction |= HI1 (dm) << 5;
14654 inst.instruction |= neon_quad (rs) << 6;
14655 inst.instruction |= x << 17;
14656 inst.instruction |= sizebits << 16;
14658 neon_dp_fixup (&inst);
14662 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14663 struct neon_type_el et = neon_check_type (2, rs,
14664 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14665 /* Duplicate ARM register to lanes of vector. */
14666 NEON_ENCODE (ARMREG, inst);
14669 case 8: inst.instruction |= 0x400000; break;
14670 case 16: inst.instruction |= 0x000020; break;
14671 case 32: inst.instruction |= 0x000000; break;
14674 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14675 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14676 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14677 inst.instruction |= neon_quad (rs) << 21;
14678 /* The encoding for this instruction is identical for the ARM and Thumb
14679 variants, except for the condition field. */
14680 do_vfp_cond_or_thumb ();
14684 /* VMOV has particularly many variations. It can be one of:
14685 0. VMOV<c><q> <Qd>, <Qm>
14686 1. VMOV<c><q> <Dd>, <Dm>
14687 (Register operations, which are VORR with Rm = Rn.)
14688 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14689 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14691 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14692 (ARM register to scalar.)
14693 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14694 (Two ARM registers to vector.)
14695 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14696 (Scalar to ARM register.)
14697 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14698 (Vector to two ARM registers.)
14699 8. VMOV.F32 <Sd>, <Sm>
14700 9. VMOV.F64 <Dd>, <Dm>
14701 (VFP register moves.)
14702 10. VMOV.F32 <Sd>, #imm
14703 11. VMOV.F64 <Dd>, #imm
14704 (VFP float immediate load.)
14705 12. VMOV <Rd>, <Sm>
14706 (VFP single to ARM reg.)
14707 13. VMOV <Sd>, <Rm>
14708 (ARM reg to VFP single.)
14709 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14710 (Two ARM regs to two VFP singles.)
14711 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14712 (Two VFP singles to two ARM regs.)
14714 These cases can be disambiguated using neon_select_shape, except cases 1/9
14715 and 3/11 which depend on the operand type too.
14717 All the encoded bits are hardcoded by this function.
14719 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14720 Cases 5, 7 may be used with VFPv2 and above.
14722 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14723 can specify a type where it doesn't make sense to, and is ignored). */
14728 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14729 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14731 struct neon_type_el et;
14732 const char *ldconst = 0;
14736 case NS_DD: /* case 1/9. */
14737 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14738 /* It is not an error here if no type is given. */
14740 if (et.type == NT_float && et.size == 64)
14742 do_vfp_nsyn_opcode ("fcpyd");
14745 /* fall through. */
14747 case NS_QQ: /* case 0/1. */
14749 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14751 /* The architecture manual I have doesn't explicitly state which
14752 value the U bit should have for register->register moves, but
14753 the equivalent VORR instruction has U = 0, so do that. */
14754 inst.instruction = 0x0200110;
14755 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14756 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14757 inst.instruction |= LOW4 (inst.operands[1].reg);
14758 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14759 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14760 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14761 inst.instruction |= neon_quad (rs) << 6;
14763 neon_dp_fixup (&inst);
14767 case NS_DI: /* case 3/11. */
14768 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14770 if (et.type == NT_float && et.size == 64)
14772 /* case 11 (fconstd). */
14773 ldconst = "fconstd";
14774 goto encode_fconstd;
14776 /* fall through. */
14778 case NS_QI: /* case 2/3. */
14779 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14781 inst.instruction = 0x0800010;
14782 neon_move_immediate ();
14783 neon_dp_fixup (&inst);
14786 case NS_SR: /* case 4. */
14788 unsigned bcdebits = 0;
14790 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
14791 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
14793 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
14794 logsize = neon_logbits (et.size);
14796 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14798 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14799 && et.size != 32, _(BAD_FPU));
14800 constraint (et.type == NT_invtype, _("bad type for scalar"));
14801 constraint (x >= 64 / et.size, _("scalar index out of range"));
14805 case 8: bcdebits = 0x8; break;
14806 case 16: bcdebits = 0x1; break;
14807 case 32: bcdebits = 0x0; break;
14811 bcdebits |= x << logsize;
14813 inst.instruction = 0xe000b10;
14814 do_vfp_cond_or_thumb ();
14815 inst.instruction |= LOW4 (dn) << 16;
14816 inst.instruction |= HI1 (dn) << 7;
14817 inst.instruction |= inst.operands[1].reg << 12;
14818 inst.instruction |= (bcdebits & 3) << 5;
14819 inst.instruction |= (bcdebits >> 2) << 21;
14823 case NS_DRR: /* case 5 (fmdrr). */
14824 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14827 inst.instruction = 0xc400b10;
14828 do_vfp_cond_or_thumb ();
14829 inst.instruction |= LOW4 (inst.operands[0].reg);
14830 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
14831 inst.instruction |= inst.operands[1].reg << 12;
14832 inst.instruction |= inst.operands[2].reg << 16;
14835 case NS_RS: /* case 6. */
14838 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
14839 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
14840 unsigned abcdebits = 0;
14842 et = neon_check_type (2, NS_NULL,
14843 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
14844 logsize = neon_logbits (et.size);
14846 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14848 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14849 && et.size != 32, _(BAD_FPU));
14850 constraint (et.type == NT_invtype, _("bad type for scalar"));
14851 constraint (x >= 64 / et.size, _("scalar index out of range"));
14855 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
14856 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
14857 case 32: abcdebits = 0x00; break;
14861 abcdebits |= x << logsize;
14862 inst.instruction = 0xe100b10;
14863 do_vfp_cond_or_thumb ();
14864 inst.instruction |= LOW4 (dn) << 16;
14865 inst.instruction |= HI1 (dn) << 7;
14866 inst.instruction |= inst.operands[0].reg << 12;
14867 inst.instruction |= (abcdebits & 3) << 5;
14868 inst.instruction |= (abcdebits >> 2) << 21;
14872 case NS_RRD: /* case 7 (fmrrd). */
14873 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14876 inst.instruction = 0xc500b10;
14877 do_vfp_cond_or_thumb ();
14878 inst.instruction |= inst.operands[0].reg << 12;
14879 inst.instruction |= inst.operands[1].reg << 16;
14880 inst.instruction |= LOW4 (inst.operands[2].reg);
14881 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14884 case NS_FF: /* case 8 (fcpys). */
14885 do_vfp_nsyn_opcode ("fcpys");
14888 case NS_FI: /* case 10 (fconsts). */
14889 ldconst = "fconsts";
14891 if (is_quarter_float (inst.operands[1].imm))
14893 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
14894 do_vfp_nsyn_opcode (ldconst);
14897 first_error (_("immediate out of range"));
14900 case NS_RF: /* case 12 (fmrs). */
14901 do_vfp_nsyn_opcode ("fmrs");
14904 case NS_FR: /* case 13 (fmsr). */
14905 do_vfp_nsyn_opcode ("fmsr");
14908 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14909 (one of which is a list), but we have parsed four. Do some fiddling to
14910 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14912 case NS_RRFF: /* case 14 (fmrrs). */
14913 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
14914 _("VFP registers must be adjacent"));
14915 inst.operands[2].imm = 2;
14916 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
14917 do_vfp_nsyn_opcode ("fmrrs");
14920 case NS_FFRR: /* case 15 (fmsrr). */
14921 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
14922 _("VFP registers must be adjacent"));
14923 inst.operands[1] = inst.operands[2];
14924 inst.operands[2] = inst.operands[3];
14925 inst.operands[0].imm = 2;
14926 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
14927 do_vfp_nsyn_opcode ("fmsrr");
14936 do_neon_rshift_round_imm (void)
14938 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14939 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
14940 int imm = inst.operands[2].imm;
14942 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14945 inst.operands[2].present = 0;
14950 constraint (imm < 1 || (unsigned)imm > et.size,
14951 _("immediate out of range for shift"));
14952 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
14957 do_neon_movl (void)
14959 struct neon_type_el et = neon_check_type (2, NS_QD,
14960 N_EQK | N_DBL, N_SU_32 | N_KEY);
14961 unsigned sizebits = et.size >> 3;
14962 inst.instruction |= sizebits << 19;
14963 neon_two_same (0, et.type == NT_unsigned, -1);
14969 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14970 struct neon_type_el et = neon_check_type (2, rs,
14971 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14972 NEON_ENCODE (INTEGER, inst);
14973 neon_two_same (neon_quad (rs), 1, et.size);
14977 do_neon_zip_uzp (void)
14979 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14980 struct neon_type_el et = neon_check_type (2, rs,
14981 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14982 if (rs == NS_DD && et.size == 32)
14984 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14985 inst.instruction = N_MNEM_vtrn;
14989 neon_two_same (neon_quad (rs), 1, et.size);
14993 do_neon_sat_abs_neg (void)
14995 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14996 struct neon_type_el et = neon_check_type (2, rs,
14997 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
14998 neon_two_same (neon_quad (rs), 1, et.size);
15002 do_neon_pair_long (void)
15004 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15005 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15006 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15007 inst.instruction |= (et.type == NT_unsigned) << 7;
15008 neon_two_same (neon_quad (rs), 1, et.size);
15012 do_neon_recip_est (void)
15014 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15015 struct neon_type_el et = neon_check_type (2, rs,
15016 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15017 inst.instruction |= (et.type == NT_float) << 8;
15018 neon_two_same (neon_quad (rs), 1, et.size);
15024 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15025 struct neon_type_el et = neon_check_type (2, rs,
15026 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15027 neon_two_same (neon_quad (rs), 1, et.size);
15033 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15034 struct neon_type_el et = neon_check_type (2, rs,
15035 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15036 neon_two_same (neon_quad (rs), 1, et.size);
15042 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15043 struct neon_type_el et = neon_check_type (2, rs,
15044 N_EQK | N_INT, N_8 | N_KEY);
15045 neon_two_same (neon_quad (rs), 1, et.size);
15051 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15052 neon_two_same (neon_quad (rs), 1, -1);
15056 do_neon_tbl_tbx (void)
15058 unsigned listlenbits;
15059 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15061 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15063 first_error (_("bad list length for table lookup"));
15067 listlenbits = inst.operands[1].imm - 1;
15068 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15069 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15070 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15071 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15072 inst.instruction |= LOW4 (inst.operands[2].reg);
15073 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15074 inst.instruction |= listlenbits << 8;
15076 neon_dp_fixup (&inst);
15080 do_neon_ldm_stm (void)
15082 /* P, U and L bits are part of bitmask. */
15083 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15084 unsigned offsetbits = inst.operands[1].imm * 2;
15086 if (inst.operands[1].issingle)
15088 do_vfp_nsyn_ldm_stm (is_dbmode);
15092 constraint (is_dbmode && !inst.operands[0].writeback,
15093 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15095 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15096 _("register list must contain at least 1 and at most 16 "
15099 inst.instruction |= inst.operands[0].reg << 16;
15100 inst.instruction |= inst.operands[0].writeback << 21;
15101 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15102 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15104 inst.instruction |= offsetbits;
15106 do_vfp_cond_or_thumb ();
15110 do_neon_ldr_str (void)
15112 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15114 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15115 And is UNPREDICTABLE in thumb mode. */
15117 && inst.operands[1].reg == REG_PC
15118 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15120 if (!thumb_mode && warn_on_deprecated)
15121 as_warn (_("Use of PC here is deprecated"));
15123 inst.error = _("Use of PC here is UNPREDICTABLE");
15126 if (inst.operands[0].issingle)
15129 do_vfp_nsyn_opcode ("flds");
15131 do_vfp_nsyn_opcode ("fsts");
15136 do_vfp_nsyn_opcode ("fldd");
15138 do_vfp_nsyn_opcode ("fstd");
15142 /* "interleave" version also handles non-interleaving register VLD1/VST1
15146 do_neon_ld_st_interleave (void)
15148 struct neon_type_el et = neon_check_type (1, NS_NULL,
15149 N_8 | N_16 | N_32 | N_64);
15150 unsigned alignbits = 0;
15152 /* The bits in this table go:
15153 0: register stride of one (0) or two (1)
15154 1,2: register list length, minus one (1, 2, 3, 4).
15155 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15156 We use -1 for invalid entries. */
15157 const int typetable[] =
15159 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15160 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15161 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15162 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15166 if (et.type == NT_invtype)
15169 if (inst.operands[1].immisalign)
15170 switch (inst.operands[1].imm >> 8)
15172 case 64: alignbits = 1; break;
15174 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15175 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15176 goto bad_alignment;
15180 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15181 goto bad_alignment;
15186 first_error (_("bad alignment"));
15190 inst.instruction |= alignbits << 4;
15191 inst.instruction |= neon_logbits (et.size) << 6;
15193 /* Bits [4:6] of the immediate in a list specifier encode register stride
15194 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15195 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15196 up the right value for "type" in a table based on this value and the given
15197 list style, then stick it back. */
15198 idx = ((inst.operands[0].imm >> 4) & 7)
15199 | (((inst.instruction >> 8) & 3) << 3);
15201 typebits = typetable[idx];
15203 constraint (typebits == -1, _("bad list type for instruction"));
15205 inst.instruction &= ~0xf00;
15206 inst.instruction |= typebits << 8;
15209 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15210 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15211 otherwise. The variable arguments are a list of pairs of legal (size, align)
15212 values, terminated with -1. */
15215 neon_alignment_bit (int size, int align, int *do_align, ...)
15218 int result = FAIL, thissize, thisalign;
15220 if (!inst.operands[1].immisalign)
15226 va_start (ap, do_align);
15230 thissize = va_arg (ap, int);
15231 if (thissize == -1)
15233 thisalign = va_arg (ap, int);
15235 if (size == thissize && align == thisalign)
15238 while (result != SUCCESS);
15242 if (result == SUCCESS)
15245 first_error (_("unsupported alignment for instruction"));
15251 do_neon_ld_st_lane (void)
15253 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15254 int align_good, do_align = 0;
15255 int logsize = neon_logbits (et.size);
15256 int align = inst.operands[1].imm >> 8;
15257 int n = (inst.instruction >> 8) & 3;
15258 int max_el = 64 / et.size;
15260 if (et.type == NT_invtype)
15263 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15264 _("bad list length"));
15265 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15266 _("scalar index out of range"));
15267 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15269 _("stride of 2 unavailable when element size is 8"));
15273 case 0: /* VLD1 / VST1. */
15274 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15276 if (align_good == FAIL)
15280 unsigned alignbits = 0;
15283 case 16: alignbits = 0x1; break;
15284 case 32: alignbits = 0x3; break;
15287 inst.instruction |= alignbits << 4;
15291 case 1: /* VLD2 / VST2. */
15292 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15294 if (align_good == FAIL)
15297 inst.instruction |= 1 << 4;
15300 case 2: /* VLD3 / VST3. */
15301 constraint (inst.operands[1].immisalign,
15302 _("can't use alignment with this instruction"));
15305 case 3: /* VLD4 / VST4. */
15306 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15307 16, 64, 32, 64, 32, 128, -1);
15308 if (align_good == FAIL)
15312 unsigned alignbits = 0;
15315 case 8: alignbits = 0x1; break;
15316 case 16: alignbits = 0x1; break;
15317 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15320 inst.instruction |= alignbits << 4;
15327 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15328 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15329 inst.instruction |= 1 << (4 + logsize);
15331 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15332 inst.instruction |= logsize << 10;
15335 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15338 do_neon_ld_dup (void)
15340 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15341 int align_good, do_align = 0;
15343 if (et.type == NT_invtype)
15346 switch ((inst.instruction >> 8) & 3)
15348 case 0: /* VLD1. */
15349 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15350 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15351 &do_align, 16, 16, 32, 32, -1);
15352 if (align_good == FAIL)
15354 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15357 case 2: inst.instruction |= 1 << 5; break;
15358 default: first_error (_("bad list length")); return;
15360 inst.instruction |= neon_logbits (et.size) << 6;
15363 case 1: /* VLD2. */
15364 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15365 &do_align, 8, 16, 16, 32, 32, 64, -1);
15366 if (align_good == FAIL)
15368 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15369 _("bad list length"));
15370 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15371 inst.instruction |= 1 << 5;
15372 inst.instruction |= neon_logbits (et.size) << 6;
15375 case 2: /* VLD3. */
15376 constraint (inst.operands[1].immisalign,
15377 _("can't use alignment with this instruction"));
15378 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15379 _("bad list length"));
15380 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15381 inst.instruction |= 1 << 5;
15382 inst.instruction |= neon_logbits (et.size) << 6;
15385 case 3: /* VLD4. */
15387 int align = inst.operands[1].imm >> 8;
15388 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15389 16, 64, 32, 64, 32, 128, -1);
15390 if (align_good == FAIL)
15392 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15393 _("bad list length"));
15394 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15395 inst.instruction |= 1 << 5;
15396 if (et.size == 32 && align == 128)
15397 inst.instruction |= 0x3 << 6;
15399 inst.instruction |= neon_logbits (et.size) << 6;
15406 inst.instruction |= do_align << 4;
15409 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15410 apart from bits [11:4]. */
15413 do_neon_ldx_stx (void)
15415 if (inst.operands[1].isreg)
15416 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15418 switch (NEON_LANE (inst.operands[0].imm))
15420 case NEON_INTERLEAVE_LANES:
15421 NEON_ENCODE (INTERLV, inst);
15422 do_neon_ld_st_interleave ();
15425 case NEON_ALL_LANES:
15426 NEON_ENCODE (DUP, inst);
15431 NEON_ENCODE (LANE, inst);
15432 do_neon_ld_st_lane ();
15435 /* L bit comes from bit mask. */
15436 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15437 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15438 inst.instruction |= inst.operands[1].reg << 16;
15440 if (inst.operands[1].postind)
15442 int postreg = inst.operands[1].imm & 0xf;
15443 constraint (!inst.operands[1].immisreg,
15444 _("post-index must be a register"));
15445 constraint (postreg == 0xd || postreg == 0xf,
15446 _("bad register for post-index"));
15447 inst.instruction |= postreg;
15449 else if (inst.operands[1].writeback)
15451 inst.instruction |= 0xd;
15454 inst.instruction |= 0xf;
15457 inst.instruction |= 0xf9000000;
15459 inst.instruction |= 0xf4000000;
15462 /* Overall per-instruction processing. */
15464 /* We need to be able to fix up arbitrary expressions in some statements.
15465 This is so that we can handle symbols that are an arbitrary distance from
15466 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15467 which returns part of an address in a form which will be valid for
15468 a data instruction. We do this by pushing the expression into a symbol
15469 in the expr_section, and creating a fix for that. */
15472 fix_new_arm (fragS * frag,
15486 /* Create an absolute valued symbol, so we have something to
15487 refer to in the object file. Unfortunately for us, gas's
15488 generic expression parsing will already have folded out
15489 any use of .set foo/.type foo %function that may have
15490 been used to set type information of the target location,
15491 that's being specified symbolically. We have to presume
15492 the user knows what they are doing. */
15496 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15498 symbol = symbol_find_or_make (name);
15499 S_SET_SEGMENT (symbol, absolute_section);
15500 symbol_set_frag (symbol, &zero_address_frag);
15501 S_SET_VALUE (symbol, exp->X_add_number);
15502 exp->X_op = O_symbol;
15503 exp->X_add_symbol = symbol;
15504 exp->X_add_number = 0;
15510 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15511 (enum bfd_reloc_code_real) reloc);
15515 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15516 pc_rel, (enum bfd_reloc_code_real) reloc);
15520 /* Mark whether the fix is to a THUMB instruction, or an ARM
15522 new_fix->tc_fix_data = thumb_mode;
15525 /* Create a frg for an instruction requiring relaxation. */
15527 output_relax_insn (void)
15533 /* The size of the instruction is unknown, so tie the debug info to the
15534 start of the instruction. */
15535 dwarf2_emit_insn (0);
15537 switch (inst.reloc.exp.X_op)
15540 sym = inst.reloc.exp.X_add_symbol;
15541 offset = inst.reloc.exp.X_add_number;
15545 offset = inst.reloc.exp.X_add_number;
15548 sym = make_expr_symbol (&inst.reloc.exp);
15552 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15553 inst.relax, sym, offset, NULL/*offset, opcode*/);
15554 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15557 /* Write a 32-bit thumb instruction to buf. */
15559 put_thumb32_insn (char * buf, unsigned long insn)
15561 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15562 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15566 output_inst (const char * str)
15572 as_bad ("%s -- `%s'", inst.error, str);
15577 output_relax_insn ();
15580 if (inst.size == 0)
15583 to = frag_more (inst.size);
15584 /* PR 9814: Record the thumb mode into the current frag so that we know
15585 what type of NOP padding to use, if necessary. We override any previous
15586 setting so that if the mode has changed then the NOPS that we use will
15587 match the encoding of the last instruction in the frag. */
15588 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15590 if (thumb_mode && (inst.size > THUMB_SIZE))
15592 gas_assert (inst.size == (2 * THUMB_SIZE));
15593 put_thumb32_insn (to, inst.instruction);
15595 else if (inst.size > INSN_SIZE)
15597 gas_assert (inst.size == (2 * INSN_SIZE));
15598 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15599 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15602 md_number_to_chars (to, inst.instruction, inst.size);
15604 if (inst.reloc.type != BFD_RELOC_UNUSED)
15605 fix_new_arm (frag_now, to - frag_now->fr_literal,
15606 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15609 dwarf2_emit_insn (inst.size);
15613 output_it_inst (int cond, int mask, char * to)
15615 unsigned long instruction = 0xbf00;
15618 instruction |= mask;
15619 instruction |= cond << 4;
15623 to = frag_more (2);
15625 dwarf2_emit_insn (2);
15629 md_number_to_chars (to, instruction, 2);
15634 /* Tag values used in struct asm_opcode's tag field. */
15637 OT_unconditional, /* Instruction cannot be conditionalized.
15638 The ARM condition field is still 0xE. */
15639 OT_unconditionalF, /* Instruction cannot be conditionalized
15640 and carries 0xF in its ARM condition field. */
15641 OT_csuffix, /* Instruction takes a conditional suffix. */
15642 OT_csuffixF, /* Some forms of the instruction take a conditional
15643 suffix, others place 0xF where the condition field
15645 OT_cinfix3, /* Instruction takes a conditional infix,
15646 beginning at character index 3. (In
15647 unified mode, it becomes a suffix.) */
15648 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15649 tsts, cmps, cmns, and teqs. */
15650 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15651 character index 3, even in unified mode. Used for
15652 legacy instructions where suffix and infix forms
15653 may be ambiguous. */
15654 OT_csuf_or_in3, /* Instruction takes either a conditional
15655 suffix or an infix at character index 3. */
15656 OT_odd_infix_unc, /* This is the unconditional variant of an
15657 instruction that takes a conditional infix
15658 at an unusual position. In unified mode,
15659 this variant will accept a suffix. */
15660 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15661 are the conditional variants of instructions that
15662 take conditional infixes in unusual positions.
15663 The infix appears at character index
15664 (tag - OT_odd_infix_0). These are not accepted
15665 in unified mode. */
15668 /* Subroutine of md_assemble, responsible for looking up the primary
15669 opcode from the mnemonic the user wrote. STR points to the
15670 beginning of the mnemonic.
15672 This is not simply a hash table lookup, because of conditional
15673 variants. Most instructions have conditional variants, which are
15674 expressed with a _conditional affix_ to the mnemonic. If we were
15675 to encode each conditional variant as a literal string in the opcode
15676 table, it would have approximately 20,000 entries.
15678 Most mnemonics take this affix as a suffix, and in unified syntax,
15679 'most' is upgraded to 'all'. However, in the divided syntax, some
15680 instructions take the affix as an infix, notably the s-variants of
15681 the arithmetic instructions. Of those instructions, all but six
15682 have the infix appear after the third character of the mnemonic.
15684 Accordingly, the algorithm for looking up primary opcodes given
15687 1. Look up the identifier in the opcode table.
15688 If we find a match, go to step U.
15690 2. Look up the last two characters of the identifier in the
15691 conditions table. If we find a match, look up the first N-2
15692 characters of the identifier in the opcode table. If we
15693 find a match, go to step CE.
15695 3. Look up the fourth and fifth characters of the identifier in
15696 the conditions table. If we find a match, extract those
15697 characters from the identifier, and look up the remaining
15698 characters in the opcode table. If we find a match, go
15703 U. Examine the tag field of the opcode structure, in case this is
15704 one of the six instructions with its conditional infix in an
15705 unusual place. If it is, the tag tells us where to find the
15706 infix; look it up in the conditions table and set inst.cond
15707 accordingly. Otherwise, this is an unconditional instruction.
15708 Again set inst.cond accordingly. Return the opcode structure.
15710 CE. Examine the tag field to make sure this is an instruction that
15711 should receive a conditional suffix. If it is not, fail.
15712 Otherwise, set inst.cond from the suffix we already looked up,
15713 and return the opcode structure.
15715 CM. Examine the tag field to make sure this is an instruction that
15716 should receive a conditional infix after the third character.
15717 If it is not, fail. Otherwise, undo the edits to the current
15718 line of input and proceed as for case CE. */
15720 static const struct asm_opcode *
15721 opcode_lookup (char **str)
15725 const struct asm_opcode *opcode;
15726 const struct asm_cond *cond;
15729 /* Scan up to the end of the mnemonic, which must end in white space,
15730 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15731 for (base = end = *str; *end != '\0'; end++)
15732 if (*end == ' ' || *end == '.')
15738 /* Handle a possible width suffix and/or Neon type suffix. */
15743 /* The .w and .n suffixes are only valid if the unified syntax is in
15745 if (unified_syntax && end[1] == 'w')
15747 else if (unified_syntax && end[1] == 'n')
15752 inst.vectype.elems = 0;
15754 *str = end + offset;
15756 if (end[offset] == '.')
15758 /* See if we have a Neon type suffix (possible in either unified or
15759 non-unified ARM syntax mode). */
15760 if (parse_neon_type (&inst.vectype, str) == FAIL)
15763 else if (end[offset] != '\0' && end[offset] != ' ')
15769 /* Look for unaffixed or special-case affixed mnemonic. */
15770 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15775 if (opcode->tag < OT_odd_infix_0)
15777 inst.cond = COND_ALWAYS;
15781 if (warn_on_deprecated && unified_syntax)
15782 as_warn (_("conditional infixes are deprecated in unified syntax"));
15783 affix = base + (opcode->tag - OT_odd_infix_0);
15784 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15787 inst.cond = cond->value;
15791 /* Cannot have a conditional suffix on a mnemonic of less than two
15793 if (end - base < 3)
15796 /* Look for suffixed mnemonic. */
15798 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15799 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15801 if (opcode && cond)
15804 switch (opcode->tag)
15806 case OT_cinfix3_legacy:
15807 /* Ignore conditional suffixes matched on infix only mnemonics. */
15811 case OT_cinfix3_deprecated:
15812 case OT_odd_infix_unc:
15813 if (!unified_syntax)
15815 /* else fall through */
15819 case OT_csuf_or_in3:
15820 inst.cond = cond->value;
15823 case OT_unconditional:
15824 case OT_unconditionalF:
15826 inst.cond = cond->value;
15829 /* Delayed diagnostic. */
15830 inst.error = BAD_COND;
15831 inst.cond = COND_ALWAYS;
15840 /* Cannot have a usual-position infix on a mnemonic of less than
15841 six characters (five would be a suffix). */
15842 if (end - base < 6)
15845 /* Look for infixed mnemonic in the usual position. */
15847 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15851 memcpy (save, affix, 2);
15852 memmove (affix, affix + 2, (end - affix) - 2);
15853 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15855 memmove (affix + 2, affix, (end - affix) - 2);
15856 memcpy (affix, save, 2);
15859 && (opcode->tag == OT_cinfix3
15860 || opcode->tag == OT_cinfix3_deprecated
15861 || opcode->tag == OT_csuf_or_in3
15862 || opcode->tag == OT_cinfix3_legacy))
15865 if (warn_on_deprecated && unified_syntax
15866 && (opcode->tag == OT_cinfix3
15867 || opcode->tag == OT_cinfix3_deprecated))
15868 as_warn (_("conditional infixes are deprecated in unified syntax"));
15870 inst.cond = cond->value;
15877 /* This function generates an initial IT instruction, leaving its block
15878 virtually open for the new instructions. Eventually,
15879 the mask will be updated by now_it_add_mask () each time
15880 a new instruction needs to be included in the IT block.
15881 Finally, the block is closed with close_automatic_it_block ().
15882 The block closure can be requested either from md_assemble (),
15883 a tencode (), or due to a label hook. */
15886 new_automatic_it_block (int cond)
15888 now_it.state = AUTOMATIC_IT_BLOCK;
15889 now_it.mask = 0x18;
15891 now_it.block_length = 1;
15892 mapping_state (MAP_THUMB);
15893 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
15896 /* Close an automatic IT block.
15897 See comments in new_automatic_it_block (). */
15900 close_automatic_it_block (void)
15902 now_it.mask = 0x10;
15903 now_it.block_length = 0;
15906 /* Update the mask of the current automatically-generated IT
15907 instruction. See comments in new_automatic_it_block (). */
15910 now_it_add_mask (int cond)
15912 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15913 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15914 | ((bitvalue) << (nbit)))
15915 const int resulting_bit = (cond & 1);
15917 now_it.mask &= 0xf;
15918 now_it.mask = SET_BIT_VALUE (now_it.mask,
15920 (5 - now_it.block_length));
15921 now_it.mask = SET_BIT_VALUE (now_it.mask,
15923 ((5 - now_it.block_length) - 1) );
15924 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
15927 #undef SET_BIT_VALUE
15930 /* The IT blocks handling machinery is accessed through the these functions:
15931 it_fsm_pre_encode () from md_assemble ()
15932 set_it_insn_type () optional, from the tencode functions
15933 set_it_insn_type_last () ditto
15934 in_it_block () ditto
15935 it_fsm_post_encode () from md_assemble ()
15936 force_automatic_it_block_close () from label habdling functions
15939 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15940 initializing the IT insn type with a generic initial value depending
15941 on the inst.condition.
15942 2) During the tencode function, two things may happen:
15943 a) The tencode function overrides the IT insn type by
15944 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15945 b) The tencode function queries the IT block state by
15946 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15948 Both set_it_insn_type and in_it_block run the internal FSM state
15949 handling function (handle_it_state), because: a) setting the IT insn
15950 type may incur in an invalid state (exiting the function),
15951 and b) querying the state requires the FSM to be updated.
15952 Specifically we want to avoid creating an IT block for conditional
15953 branches, so it_fsm_pre_encode is actually a guess and we can't
15954 determine whether an IT block is required until the tencode () routine
15955 has decided what type of instruction this actually it.
15956 Because of this, if set_it_insn_type and in_it_block have to be used,
15957 set_it_insn_type has to be called first.
15959 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15960 determines the insn IT type depending on the inst.cond code.
15961 When a tencode () routine encodes an instruction that can be
15962 either outside an IT block, or, in the case of being inside, has to be
15963 the last one, set_it_insn_type_last () will determine the proper
15964 IT instruction type based on the inst.cond code. Otherwise,
15965 set_it_insn_type can be called for overriding that logic or
15966 for covering other cases.
15968 Calling handle_it_state () may not transition the IT block state to
15969 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15970 still queried. Instead, if the FSM determines that the state should
15971 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15972 after the tencode () function: that's what it_fsm_post_encode () does.
15974 Since in_it_block () calls the state handling function to get an
15975 updated state, an error may occur (due to invalid insns combination).
15976 In that case, inst.error is set.
15977 Therefore, inst.error has to be checked after the execution of
15978 the tencode () routine.
15980 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15981 any pending state change (if any) that didn't take place in
15982 handle_it_state () as explained above. */
15985 it_fsm_pre_encode (void)
15987 if (inst.cond != COND_ALWAYS)
15988 inst.it_insn_type = INSIDE_IT_INSN;
15990 inst.it_insn_type = OUTSIDE_IT_INSN;
15992 now_it.state_handled = 0;
15995 /* IT state FSM handling function. */
15998 handle_it_state (void)
16000 now_it.state_handled = 1;
16002 switch (now_it.state)
16004 case OUTSIDE_IT_BLOCK:
16005 switch (inst.it_insn_type)
16007 case OUTSIDE_IT_INSN:
16010 case INSIDE_IT_INSN:
16011 case INSIDE_IT_LAST_INSN:
16012 if (thumb_mode == 0)
16015 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16016 as_tsktsk (_("Warning: conditional outside an IT block"\
16021 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16022 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16024 /* Automatically generate the IT instruction. */
16025 new_automatic_it_block (inst.cond);
16026 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16027 close_automatic_it_block ();
16031 inst.error = BAD_OUT_IT;
16037 case IF_INSIDE_IT_LAST_INSN:
16038 case NEUTRAL_IT_INSN:
16042 now_it.state = MANUAL_IT_BLOCK;
16043 now_it.block_length = 0;
16048 case AUTOMATIC_IT_BLOCK:
16049 /* Three things may happen now:
16050 a) We should increment current it block size;
16051 b) We should close current it block (closing insn or 4 insns);
16052 c) We should close current it block and start a new one (due
16053 to incompatible conditions or
16054 4 insns-length block reached). */
16056 switch (inst.it_insn_type)
16058 case OUTSIDE_IT_INSN:
16059 /* The closure of the block shall happen immediatelly,
16060 so any in_it_block () call reports the block as closed. */
16061 force_automatic_it_block_close ();
16064 case INSIDE_IT_INSN:
16065 case INSIDE_IT_LAST_INSN:
16066 case IF_INSIDE_IT_LAST_INSN:
16067 now_it.block_length++;
16069 if (now_it.block_length > 4
16070 || !now_it_compatible (inst.cond))
16072 force_automatic_it_block_close ();
16073 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16074 new_automatic_it_block (inst.cond);
16078 now_it_add_mask (inst.cond);
16081 if (now_it.state == AUTOMATIC_IT_BLOCK
16082 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16083 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16084 close_automatic_it_block ();
16087 case NEUTRAL_IT_INSN:
16088 now_it.block_length++;
16090 if (now_it.block_length > 4)
16091 force_automatic_it_block_close ();
16093 now_it_add_mask (now_it.cc & 1);
16097 close_automatic_it_block ();
16098 now_it.state = MANUAL_IT_BLOCK;
16103 case MANUAL_IT_BLOCK:
16105 /* Check conditional suffixes. */
16106 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16109 now_it.mask &= 0x1f;
16110 is_last = (now_it.mask == 0x10);
16112 switch (inst.it_insn_type)
16114 case OUTSIDE_IT_INSN:
16115 inst.error = BAD_NOT_IT;
16118 case INSIDE_IT_INSN:
16119 if (cond != inst.cond)
16121 inst.error = BAD_IT_COND;
16126 case INSIDE_IT_LAST_INSN:
16127 case IF_INSIDE_IT_LAST_INSN:
16128 if (cond != inst.cond)
16130 inst.error = BAD_IT_COND;
16135 inst.error = BAD_BRANCH;
16140 case NEUTRAL_IT_INSN:
16141 /* The BKPT instruction is unconditional even in an IT block. */
16145 inst.error = BAD_IT_IT;
16156 it_fsm_post_encode (void)
16160 if (!now_it.state_handled)
16161 handle_it_state ();
16163 is_last = (now_it.mask == 0x10);
16166 now_it.state = OUTSIDE_IT_BLOCK;
16172 force_automatic_it_block_close (void)
16174 if (now_it.state == AUTOMATIC_IT_BLOCK)
16176 close_automatic_it_block ();
16177 now_it.state = OUTSIDE_IT_BLOCK;
16185 if (!now_it.state_handled)
16186 handle_it_state ();
16188 return now_it.state != OUTSIDE_IT_BLOCK;
16192 md_assemble (char *str)
16195 const struct asm_opcode * opcode;
16197 /* Align the previous label if needed. */
16198 if (last_label_seen != NULL)
16200 symbol_set_frag (last_label_seen, frag_now);
16201 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16202 S_SET_SEGMENT (last_label_seen, now_seg);
16205 memset (&inst, '\0', sizeof (inst));
16206 inst.reloc.type = BFD_RELOC_UNUSED;
16208 opcode = opcode_lookup (&p);
16211 /* It wasn't an instruction, but it might be a register alias of
16212 the form alias .req reg, or a Neon .dn/.qn directive. */
16213 if (! create_register_alias (str, p)
16214 && ! create_neon_reg_alias (str, p))
16215 as_bad (_("bad instruction `%s'"), str);
16220 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16221 as_warn (_("s suffix on comparison instruction is deprecated"));
16223 /* The value which unconditional instructions should have in place of the
16224 condition field. */
16225 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16229 arm_feature_set variant;
16231 variant = cpu_variant;
16232 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16233 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16234 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16235 /* Check that this instruction is supported for this CPU. */
16236 if (!opcode->tvariant
16237 || (thumb_mode == 1
16238 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16240 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16243 if (inst.cond != COND_ALWAYS && !unified_syntax
16244 && opcode->tencode != do_t_branch)
16246 as_bad (_("Thumb does not support conditional execution"));
16250 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16252 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16253 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16254 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16256 /* Two things are addressed here.
16257 1) Implicit require narrow instructions on Thumb-1.
16258 This avoids relaxation accidentally introducing Thumb-2
16260 2) Reject wide instructions in non Thumb-2 cores. */
16261 if (inst.size_req == 0)
16263 else if (inst.size_req == 4)
16265 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16271 inst.instruction = opcode->tvalue;
16273 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16275 /* Prepare the it_insn_type for those encodings that don't set
16277 it_fsm_pre_encode ();
16279 opcode->tencode ();
16281 it_fsm_post_encode ();
16284 if (!(inst.error || inst.relax))
16286 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16287 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16288 if (inst.size_req && inst.size_req != inst.size)
16290 as_bad (_("cannot honor width suffix -- `%s'"), str);
16295 /* Something has gone badly wrong if we try to relax a fixed size
16297 gas_assert (inst.size_req == 0 || !inst.relax);
16299 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16300 *opcode->tvariant);
16301 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16302 set those bits when Thumb-2 32-bit instructions are seen. ie.
16303 anything other than bl/blx and v6-M instructions.
16304 This is overly pessimistic for relaxable instructions. */
16305 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16307 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16308 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16309 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16312 check_neon_suffixes;
16316 mapping_state (MAP_THUMB);
16319 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16323 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16324 is_bx = (opcode->aencode == do_bx);
16326 /* Check that this instruction is supported for this CPU. */
16327 if (!(is_bx && fix_v4bx)
16328 && !(opcode->avariant &&
16329 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16331 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16336 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16340 inst.instruction = opcode->avalue;
16341 if (opcode->tag == OT_unconditionalF)
16342 inst.instruction |= 0xF << 28;
16344 inst.instruction |= inst.cond << 28;
16345 inst.size = INSN_SIZE;
16346 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16348 it_fsm_pre_encode ();
16349 opcode->aencode ();
16350 it_fsm_post_encode ();
16352 /* Arm mode bx is marked as both v4T and v5 because it's still required
16353 on a hypothetical non-thumb v5 core. */
16355 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16357 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16358 *opcode->avariant);
16360 check_neon_suffixes;
16364 mapping_state (MAP_ARM);
16369 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16377 check_it_blocks_finished (void)
16382 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16383 if (seg_info (sect)->tc_segment_info_data.current_it.state
16384 == MANUAL_IT_BLOCK)
16386 as_warn (_("section '%s' finished with an open IT block."),
16390 if (now_it.state == MANUAL_IT_BLOCK)
16391 as_warn (_("file finished with an open IT block."));
16395 /* Various frobbings of labels and their addresses. */
16398 arm_start_line_hook (void)
16400 last_label_seen = NULL;
16404 arm_frob_label (symbolS * sym)
16406 last_label_seen = sym;
16408 ARM_SET_THUMB (sym, thumb_mode);
16410 #if defined OBJ_COFF || defined OBJ_ELF
16411 ARM_SET_INTERWORK (sym, support_interwork);
16414 force_automatic_it_block_close ();
16416 /* Note - do not allow local symbols (.Lxxx) to be labelled
16417 as Thumb functions. This is because these labels, whilst
16418 they exist inside Thumb code, are not the entry points for
16419 possible ARM->Thumb calls. Also, these labels can be used
16420 as part of a computed goto or switch statement. eg gcc
16421 can generate code that looks like this:
16423 ldr r2, [pc, .Laaa]
16433 The first instruction loads the address of the jump table.
16434 The second instruction converts a table index into a byte offset.
16435 The third instruction gets the jump address out of the table.
16436 The fourth instruction performs the jump.
16438 If the address stored at .Laaa is that of a symbol which has the
16439 Thumb_Func bit set, then the linker will arrange for this address
16440 to have the bottom bit set, which in turn would mean that the
16441 address computation performed by the third instruction would end
16442 up with the bottom bit set. Since the ARM is capable of unaligned
16443 word loads, the instruction would then load the incorrect address
16444 out of the jump table, and chaos would ensue. */
16445 if (label_is_thumb_function_name
16446 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16447 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16449 /* When the address of a Thumb function is taken the bottom
16450 bit of that address should be set. This will allow
16451 interworking between Arm and Thumb functions to work
16454 THUMB_SET_FUNC (sym, 1);
16456 label_is_thumb_function_name = FALSE;
16459 dwarf2_emit_label (sym);
16463 arm_data_in_code (void)
16465 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16467 *input_line_pointer = '/';
16468 input_line_pointer += 5;
16469 *input_line_pointer = 0;
16477 arm_canonicalize_symbol_name (char * name)
16481 if (thumb_mode && (len = strlen (name)) > 5
16482 && streq (name + len - 5, "/data"))
16483 *(name + len - 5) = 0;
16488 /* Table of all register names defined by default. The user can
16489 define additional names with .req. Note that all register names
16490 should appear in both upper and lowercase variants. Some registers
16491 also have mixed-case names. */
16493 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16494 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16495 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16496 #define REGSET(p,t) \
16497 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16498 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16499 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16500 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16501 #define REGSETH(p,t) \
16502 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16503 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16504 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16505 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16506 #define REGSET2(p,t) \
16507 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16508 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16509 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16510 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16511 #define SPLRBANK(base,bank,t) \
16512 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16513 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16514 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16515 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16516 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16517 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16519 static const struct reg_entry reg_names[] =
16521 /* ARM integer registers. */
16522 REGSET(r, RN), REGSET(R, RN),
16524 /* ATPCS synonyms. */
16525 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16526 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16527 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16529 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16530 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16531 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16533 /* Well-known aliases. */
16534 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16535 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16537 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16538 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16540 /* Coprocessor numbers. */
16541 REGSET(p, CP), REGSET(P, CP),
16543 /* Coprocessor register numbers. The "cr" variants are for backward
16545 REGSET(c, CN), REGSET(C, CN),
16546 REGSET(cr, CN), REGSET(CR, CN),
16548 /* ARM banked registers. */
16549 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16550 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16551 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16552 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16553 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16554 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16555 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16557 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16558 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16559 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16560 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16561 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16562 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16563 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16564 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16566 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16567 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16568 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16569 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16570 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16571 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16572 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16573 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16574 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16576 /* FPA registers. */
16577 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16578 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16580 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16581 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16583 /* VFP SP registers. */
16584 REGSET(s,VFS), REGSET(S,VFS),
16585 REGSETH(s,VFS), REGSETH(S,VFS),
16587 /* VFP DP Registers. */
16588 REGSET(d,VFD), REGSET(D,VFD),
16589 /* Extra Neon DP registers. */
16590 REGSETH(d,VFD), REGSETH(D,VFD),
16592 /* Neon QP registers. */
16593 REGSET2(q,NQ), REGSET2(Q,NQ),
16595 /* VFP control registers. */
16596 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16597 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16598 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16599 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16600 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16601 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16603 /* Maverick DSP coprocessor registers. */
16604 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16605 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16607 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16608 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16609 REGDEF(dspsc,0,DSPSC),
16611 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16612 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16613 REGDEF(DSPSC,0,DSPSC),
16615 /* iWMMXt data registers - p0, c0-15. */
16616 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16618 /* iWMMXt control registers - p1, c0-3. */
16619 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16620 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16621 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16622 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16624 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16625 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16626 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16627 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16628 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16630 /* XScale accumulator registers. */
16631 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16637 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16638 within psr_required_here. */
16639 static const struct asm_psr psrs[] =
16641 /* Backward compatibility notation. Note that "all" is no longer
16642 truly all possible PSR bits. */
16643 {"all", PSR_c | PSR_f},
16647 /* Individual flags. */
16653 /* Combinations of flags. */
16654 {"fs", PSR_f | PSR_s},
16655 {"fx", PSR_f | PSR_x},
16656 {"fc", PSR_f | PSR_c},
16657 {"sf", PSR_s | PSR_f},
16658 {"sx", PSR_s | PSR_x},
16659 {"sc", PSR_s | PSR_c},
16660 {"xf", PSR_x | PSR_f},
16661 {"xs", PSR_x | PSR_s},
16662 {"xc", PSR_x | PSR_c},
16663 {"cf", PSR_c | PSR_f},
16664 {"cs", PSR_c | PSR_s},
16665 {"cx", PSR_c | PSR_x},
16666 {"fsx", PSR_f | PSR_s | PSR_x},
16667 {"fsc", PSR_f | PSR_s | PSR_c},
16668 {"fxs", PSR_f | PSR_x | PSR_s},
16669 {"fxc", PSR_f | PSR_x | PSR_c},
16670 {"fcs", PSR_f | PSR_c | PSR_s},
16671 {"fcx", PSR_f | PSR_c | PSR_x},
16672 {"sfx", PSR_s | PSR_f | PSR_x},
16673 {"sfc", PSR_s | PSR_f | PSR_c},
16674 {"sxf", PSR_s | PSR_x | PSR_f},
16675 {"sxc", PSR_s | PSR_x | PSR_c},
16676 {"scf", PSR_s | PSR_c | PSR_f},
16677 {"scx", PSR_s | PSR_c | PSR_x},
16678 {"xfs", PSR_x | PSR_f | PSR_s},
16679 {"xfc", PSR_x | PSR_f | PSR_c},
16680 {"xsf", PSR_x | PSR_s | PSR_f},
16681 {"xsc", PSR_x | PSR_s | PSR_c},
16682 {"xcf", PSR_x | PSR_c | PSR_f},
16683 {"xcs", PSR_x | PSR_c | PSR_s},
16684 {"cfs", PSR_c | PSR_f | PSR_s},
16685 {"cfx", PSR_c | PSR_f | PSR_x},
16686 {"csf", PSR_c | PSR_s | PSR_f},
16687 {"csx", PSR_c | PSR_s | PSR_x},
16688 {"cxf", PSR_c | PSR_x | PSR_f},
16689 {"cxs", PSR_c | PSR_x | PSR_s},
16690 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16691 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16692 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16693 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16694 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16695 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16696 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16697 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16698 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16699 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16700 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16701 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16702 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16703 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16704 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16705 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16706 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16707 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16708 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16709 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16710 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16711 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16712 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16713 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16716 /* Table of V7M psr names. */
16717 static const struct asm_psr v7m_psrs[] =
16719 {"apsr", 0 }, {"APSR", 0 },
16720 {"iapsr", 1 }, {"IAPSR", 1 },
16721 {"eapsr", 2 }, {"EAPSR", 2 },
16722 {"psr", 3 }, {"PSR", 3 },
16723 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16724 {"ipsr", 5 }, {"IPSR", 5 },
16725 {"epsr", 6 }, {"EPSR", 6 },
16726 {"iepsr", 7 }, {"IEPSR", 7 },
16727 {"msp", 8 }, {"MSP", 8 },
16728 {"psp", 9 }, {"PSP", 9 },
16729 {"primask", 16}, {"PRIMASK", 16},
16730 {"basepri", 17}, {"BASEPRI", 17},
16731 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16732 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16733 {"faultmask", 19}, {"FAULTMASK", 19},
16734 {"control", 20}, {"CONTROL", 20}
16737 /* Table of all shift-in-operand names. */
16738 static const struct asm_shift_name shift_names [] =
16740 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16741 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16742 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16743 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16744 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16745 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16748 /* Table of all explicit relocation names. */
16750 static struct reloc_entry reloc_names[] =
16752 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16753 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16754 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16755 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16756 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16757 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16758 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16759 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16760 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16761 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16762 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16763 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
16764 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
16765 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
16766 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
16767 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
16768 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
16769 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
16773 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16774 static const struct asm_cond conds[] =
16778 {"cs", 0x2}, {"hs", 0x2},
16779 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16793 static struct asm_barrier_opt barrier_opt_names[] =
16795 { "sy", 0xf }, { "SY", 0xf },
16796 { "un", 0x7 }, { "UN", 0x7 },
16797 { "st", 0xe }, { "ST", 0xe },
16798 { "unst", 0x6 }, { "UNST", 0x6 },
16799 { "ish", 0xb }, { "ISH", 0xb },
16800 { "sh", 0xb }, { "SH", 0xb },
16801 { "ishst", 0xa }, { "ISHST", 0xa },
16802 { "shst", 0xa }, { "SHST", 0xa },
16803 { "nsh", 0x7 }, { "NSH", 0x7 },
16804 { "nshst", 0x6 }, { "NSHST", 0x6 },
16805 { "osh", 0x3 }, { "OSH", 0x3 },
16806 { "oshst", 0x2 }, { "OSHST", 0x2 }
16809 /* Table of ARM-format instructions. */
16811 /* Macros for gluing together operand strings. N.B. In all cases
16812 other than OPS0, the trailing OP_stop comes from default
16813 zero-initialization of the unspecified elements of the array. */
16814 #define OPS0() { OP_stop, }
16815 #define OPS1(a) { OP_##a, }
16816 #define OPS2(a,b) { OP_##a,OP_##b, }
16817 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16818 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16819 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16820 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16822 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16823 This is useful when mixing operands for ARM and THUMB, i.e. using the
16824 MIX_ARM_THUMB_OPERANDS macro.
16825 In order to use these macros, prefix the number of operands with _
16827 #define OPS_1(a) { a, }
16828 #define OPS_2(a,b) { a,b, }
16829 #define OPS_3(a,b,c) { a,b,c, }
16830 #define OPS_4(a,b,c,d) { a,b,c,d, }
16831 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16832 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16834 /* These macros abstract out the exact format of the mnemonic table and
16835 save some repeated characters. */
16837 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16838 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16839 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16840 THUMB_VARIANT, do_##ae, do_##te }
16842 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16843 a T_MNEM_xyz enumerator. */
16844 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16845 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16846 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16847 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16849 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16850 infix after the third character. */
16851 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16852 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16853 THUMB_VARIANT, do_##ae, do_##te }
16854 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16855 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16856 THUMB_VARIANT, do_##ae, do_##te }
16857 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16858 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16859 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16860 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16861 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16862 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16863 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16864 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16866 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16867 appear in the condition table. */
16868 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16869 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16870 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16872 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16873 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16874 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16875 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16876 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16877 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16878 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16879 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16880 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16881 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16882 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16883 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16884 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16885 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16886 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16887 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16888 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16889 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16890 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16891 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16893 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16894 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16895 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16896 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16898 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16899 field is still 0xE. Many of the Thumb variants can be executed
16900 conditionally, so this is checked separately. */
16901 #define TUE(mnem, op, top, nops, ops, ae, te) \
16902 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16903 THUMB_VARIANT, do_##ae, do_##te }
16905 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16906 condition code field. */
16907 #define TUF(mnem, op, top, nops, ops, ae, te) \
16908 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16909 THUMB_VARIANT, do_##ae, do_##te }
16911 /* ARM-only variants of all the above. */
16912 #define CE(mnem, op, nops, ops, ae) \
16913 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16915 #define C3(mnem, op, nops, ops, ae) \
16916 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16918 /* Legacy mnemonics that always have conditional infix after the third
16920 #define CL(mnem, op, nops, ops, ae) \
16921 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16922 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16924 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16925 #define cCE(mnem, op, nops, ops, ae) \
16926 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16928 /* Legacy coprocessor instructions where conditional infix and conditional
16929 suffix are ambiguous. For consistency this includes all FPA instructions,
16930 not just the potentially ambiguous ones. */
16931 #define cCL(mnem, op, nops, ops, ae) \
16932 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16933 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16935 /* Coprocessor, takes either a suffix or a position-3 infix
16936 (for an FPA corner case). */
16937 #define C3E(mnem, op, nops, ops, ae) \
16938 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16939 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16941 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16942 { m1 #m2 m3, OPS##nops ops, \
16943 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16944 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16946 #define CM(m1, m2, op, nops, ops, ae) \
16947 xCM_ (m1, , m2, op, nops, ops, ae), \
16948 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16949 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16950 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16951 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16952 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16953 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16954 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16955 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16956 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16957 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16958 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16959 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16960 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16961 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16962 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16963 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16964 xCM_ (m1, le, m2, op, nops, ops, ae), \
16965 xCM_ (m1, al, m2, op, nops, ops, ae)
16967 #define UE(mnem, op, nops, ops, ae) \
16968 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16970 #define UF(mnem, op, nops, ops, ae) \
16971 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16973 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16974 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16975 use the same encoding function for each. */
16976 #define NUF(mnem, op, nops, ops, enc) \
16977 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16978 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16980 /* Neon data processing, version which indirects through neon_enc_tab for
16981 the various overloaded versions of opcodes. */
16982 #define nUF(mnem, op, nops, ops, enc) \
16983 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16984 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16986 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16988 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16989 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16990 THUMB_VARIANT, do_##enc, do_##enc }
16992 #define NCE(mnem, op, nops, ops, enc) \
16993 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16995 #define NCEF(mnem, op, nops, ops, enc) \
16996 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16998 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16999 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17000 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17001 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17003 #define nCE(mnem, op, nops, ops, enc) \
17004 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17006 #define nCEF(mnem, op, nops, ops, enc) \
17007 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17011 static const struct asm_opcode insns[] =
17013 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17014 #define THUMB_VARIANT &arm_ext_v4t
17015 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17016 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17017 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17018 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17019 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17020 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17021 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17022 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17023 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17024 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17025 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17026 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17027 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17028 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17029 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17030 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17032 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17033 for setting PSR flag bits. They are obsolete in V6 and do not
17034 have Thumb equivalents. */
17035 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17036 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17037 CL("tstp", 110f000, 2, (RR, SH), cmp),
17038 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17039 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17040 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17041 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17042 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17043 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17045 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17046 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17047 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17048 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17050 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17051 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17052 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17054 OP_ADDRGLDR),ldst, t_ldst),
17055 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17057 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17058 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17059 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17060 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17061 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17062 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17064 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17065 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17066 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17067 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17070 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17071 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17072 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17074 /* Thumb-compatibility pseudo ops. */
17075 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17076 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17077 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17078 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17079 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17080 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17081 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17082 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17083 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17084 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17085 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17086 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17088 /* These may simplify to neg. */
17089 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17090 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17092 #undef THUMB_VARIANT
17093 #define THUMB_VARIANT & arm_ext_v6
17095 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17097 /* V1 instructions with no Thumb analogue prior to V6T2. */
17098 #undef THUMB_VARIANT
17099 #define THUMB_VARIANT & arm_ext_v6t2
17101 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17102 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17103 CL("teqp", 130f000, 2, (RR, SH), cmp),
17105 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17106 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17107 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17108 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17110 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17111 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17113 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17114 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17116 /* V1 instructions with no Thumb analogue at all. */
17117 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17118 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17120 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17121 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17122 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17123 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17124 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17125 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17126 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17127 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17130 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17131 #undef THUMB_VARIANT
17132 #define THUMB_VARIANT & arm_ext_v4t
17134 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17135 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17137 #undef THUMB_VARIANT
17138 #define THUMB_VARIANT & arm_ext_v6t2
17140 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17141 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17143 /* Generic coprocessor instructions. */
17144 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17145 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17146 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17147 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17148 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17149 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17150 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17153 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17155 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17156 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17159 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17160 #undef THUMB_VARIANT
17161 #define THUMB_VARIANT & arm_ext_msr
17163 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17164 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17167 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17168 #undef THUMB_VARIANT
17169 #define THUMB_VARIANT & arm_ext_v6t2
17171 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17172 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17173 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17174 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17175 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17176 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17177 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17178 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17181 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17182 #undef THUMB_VARIANT
17183 #define THUMB_VARIANT & arm_ext_v4t
17185 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17186 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17187 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17188 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17189 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17190 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17193 #define ARM_VARIANT & arm_ext_v4t_5
17195 /* ARM Architecture 4T. */
17196 /* Note: bx (and blx) are required on V5, even if the processor does
17197 not support Thumb. */
17198 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17201 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17202 #undef THUMB_VARIANT
17203 #define THUMB_VARIANT & arm_ext_v5t
17205 /* Note: blx has 2 variants; the .value coded here is for
17206 BLX(2). Only this variant has conditional execution. */
17207 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17208 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17210 #undef THUMB_VARIANT
17211 #define THUMB_VARIANT & arm_ext_v6t2
17213 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17214 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17215 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17216 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17217 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17218 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17219 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17220 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17223 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17224 #undef THUMB_VARIANT
17225 #define THUMB_VARIANT &arm_ext_v5exp
17227 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17228 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17229 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17230 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17232 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17233 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17235 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17236 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17237 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17238 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17240 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17241 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17242 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17243 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17245 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17246 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17248 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17249 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17250 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17251 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17254 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17255 #undef THUMB_VARIANT
17256 #define THUMB_VARIANT &arm_ext_v6t2
17258 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17259 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17261 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17262 ADDRGLDRS), ldrd, t_ldstd),
17264 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17265 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17268 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17270 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17273 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17274 #undef THUMB_VARIANT
17275 #define THUMB_VARIANT & arm_ext_v6
17277 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17278 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17279 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17280 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17281 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17282 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17283 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17284 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17285 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17286 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17288 #undef THUMB_VARIANT
17289 #define THUMB_VARIANT & arm_ext_v6t2
17291 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17292 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17294 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17295 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17297 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17298 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17300 /* ARM V6 not included in V7M. */
17301 #undef THUMB_VARIANT
17302 #define THUMB_VARIANT & arm_ext_v6_notm
17303 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17304 UF(rfeib, 9900a00, 1, (RRw), rfe),
17305 UF(rfeda, 8100a00, 1, (RRw), rfe),
17306 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17307 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17308 UF(rfefa, 9900a00, 1, (RRw), rfe),
17309 UF(rfeea, 8100a00, 1, (RRw), rfe),
17310 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17311 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17312 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17313 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17314 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17316 /* ARM V6 not included in V7M (eg. integer SIMD). */
17317 #undef THUMB_VARIANT
17318 #define THUMB_VARIANT & arm_ext_v6_dsp
17319 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17320 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17321 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17322 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17323 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17324 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17325 /* Old name for QASX. */
17326 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17327 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17328 /* Old name for QSAX. */
17329 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17330 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17331 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17332 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17333 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17334 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17335 /* Old name for SASX. */
17336 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17337 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17338 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17339 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17340 /* Old name for SHASX. */
17341 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17342 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17343 /* Old name for SHSAX. */
17344 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17345 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17346 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17347 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17348 /* Old name for SSAX. */
17349 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17350 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17351 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17352 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17353 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17354 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17355 /* Old name for UASX. */
17356 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17357 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17358 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17359 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17360 /* Old name for UHASX. */
17361 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17362 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17363 /* Old name for UHSAX. */
17364 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17365 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17366 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17367 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17368 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17369 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17370 /* Old name for UQASX. */
17371 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17372 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17373 /* Old name for UQSAX. */
17374 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17375 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17376 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17377 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17378 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17379 /* Old name for USAX. */
17380 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17381 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17382 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17383 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17384 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17385 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17386 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17387 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17388 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17389 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17390 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17391 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17392 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17393 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17394 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17395 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17396 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17397 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17398 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17399 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17400 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17401 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17402 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17403 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17404 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17405 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17406 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17407 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17408 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17409 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17410 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17411 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17412 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17413 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17416 #define ARM_VARIANT & arm_ext_v6k
17417 #undef THUMB_VARIANT
17418 #define THUMB_VARIANT & arm_ext_v6k
17420 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17421 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17422 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17423 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17425 #undef THUMB_VARIANT
17426 #define THUMB_VARIANT & arm_ext_v6_notm
17427 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17429 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17430 RRnpcb), strexd, t_strexd),
17432 #undef THUMB_VARIANT
17433 #define THUMB_VARIANT & arm_ext_v6t2
17434 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17436 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17438 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17440 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17442 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17445 #define ARM_VARIANT & arm_ext_sec
17446 #undef THUMB_VARIANT
17447 #define THUMB_VARIANT & arm_ext_sec
17449 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17452 #define ARM_VARIANT & arm_ext_virt
17453 #undef THUMB_VARIANT
17454 #define THUMB_VARIANT & arm_ext_virt
17456 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17457 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17460 #define ARM_VARIANT & arm_ext_v6t2
17461 #undef THUMB_VARIANT
17462 #define THUMB_VARIANT & arm_ext_v6t2
17464 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17465 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17466 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17467 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17469 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17470 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17471 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17472 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17474 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17475 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17476 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17477 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17479 /* Thumb-only instructions. */
17481 #define ARM_VARIANT NULL
17482 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17483 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17485 /* ARM does not really have an IT instruction, so always allow it.
17486 The opcode is copied from Thumb in order to allow warnings in
17487 -mimplicit-it=[never | arm] modes. */
17489 #define ARM_VARIANT & arm_ext_v1
17491 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17492 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17493 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17494 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17495 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17496 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17497 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17498 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17499 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17500 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17501 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17502 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17503 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17504 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17505 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17506 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17507 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17508 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17510 /* Thumb2 only instructions. */
17512 #define ARM_VARIANT NULL
17514 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17515 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17516 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17517 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17518 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17519 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17521 /* Hardware division instructions. */
17523 #define ARM_VARIANT & arm_ext_adiv
17524 #undef THUMB_VARIANT
17525 #define THUMB_VARIANT & arm_ext_div
17527 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17528 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17530 /* ARM V6M/V7 instructions. */
17532 #define ARM_VARIANT & arm_ext_barrier
17533 #undef THUMB_VARIANT
17534 #define THUMB_VARIANT & arm_ext_barrier
17536 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17537 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17538 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17540 /* ARM V7 instructions. */
17542 #define ARM_VARIANT & arm_ext_v7
17543 #undef THUMB_VARIANT
17544 #define THUMB_VARIANT & arm_ext_v7
17546 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17547 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17550 #define ARM_VARIANT & arm_ext_mp
17551 #undef THUMB_VARIANT
17552 #define THUMB_VARIANT & arm_ext_mp
17554 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17557 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17559 cCE("wfs", e200110, 1, (RR), rd),
17560 cCE("rfs", e300110, 1, (RR), rd),
17561 cCE("wfc", e400110, 1, (RR), rd),
17562 cCE("rfc", e500110, 1, (RR), rd),
17564 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17565 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17566 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17567 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17569 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17570 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17571 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17572 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17574 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17575 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17576 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17577 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17578 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17579 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17580 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17581 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17582 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17583 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17584 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17585 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17587 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17588 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17589 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17590 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17591 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17592 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17593 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17594 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17595 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17596 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17597 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17598 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17600 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17601 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17602 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17603 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17604 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17605 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17606 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17607 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17608 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17609 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17610 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17611 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17613 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17614 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17615 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17616 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17617 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17618 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17619 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17620 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17621 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17622 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17623 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17624 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17626 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17627 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17628 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17629 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17630 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17631 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17632 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17633 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17634 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17635 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17636 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17637 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17639 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17640 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17641 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17642 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17643 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17644 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17645 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17646 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17647 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17648 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17649 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17650 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17652 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17653 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17654 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17655 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17656 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17657 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17658 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17659 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17660 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17661 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17662 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17663 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17665 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17666 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17667 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17668 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17669 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17670 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17671 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17672 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17673 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17674 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17675 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17676 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17678 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17679 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17680 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17681 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17682 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17683 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17684 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17685 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17686 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17687 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17688 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17689 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17691 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17692 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17693 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17694 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17695 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17696 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17697 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17698 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17699 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17700 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17701 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17702 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17704 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17705 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17706 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17707 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17708 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17709 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17710 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17711 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17712 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17713 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17714 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17715 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17717 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17718 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17719 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17720 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17721 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17722 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17723 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17724 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17725 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17726 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17727 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17728 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17730 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17731 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17732 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17733 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17734 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17735 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17736 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17737 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17738 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17739 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17740 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17741 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17743 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17744 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17745 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17746 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17747 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17748 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17749 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17750 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17751 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17752 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17753 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17754 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17756 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17757 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17758 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17759 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17760 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17761 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17762 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17763 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17764 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17765 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17766 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17767 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17769 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17770 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17771 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17772 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17773 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17774 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17775 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17776 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17777 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17778 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17779 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17780 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17782 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17783 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17784 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17785 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17786 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17787 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17788 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17789 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17790 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
17791 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
17792 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
17793 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
17795 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
17796 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
17797 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
17798 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
17799 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
17800 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17801 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17802 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17803 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
17804 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
17805 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
17806 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
17808 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
17809 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
17810 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
17811 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
17812 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
17813 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17814 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17815 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17816 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
17817 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
17818 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
17819 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
17821 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
17822 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
17823 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
17824 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
17825 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
17826 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17827 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17828 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17829 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
17830 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
17831 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
17832 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
17834 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
17835 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
17836 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
17837 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
17838 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
17839 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17840 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17841 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17842 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
17843 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
17844 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
17845 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
17847 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
17848 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
17849 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
17850 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
17851 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
17852 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17853 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17854 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17855 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
17856 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
17857 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
17858 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
17860 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
17861 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
17862 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
17863 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
17864 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
17865 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17866 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17867 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17868 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
17869 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
17870 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
17871 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
17873 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
17874 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
17875 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
17876 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
17877 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
17878 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17879 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17880 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17881 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
17882 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
17883 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
17884 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
17886 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
17887 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
17888 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
17889 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
17890 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
17891 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17892 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17893 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17894 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
17895 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
17896 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
17897 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
17899 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
17900 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
17901 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
17902 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
17903 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
17904 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17905 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17906 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17907 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
17908 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
17909 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
17910 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
17912 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
17913 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
17914 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
17915 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
17916 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
17917 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17918 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17919 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17920 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
17921 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
17922 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
17923 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
17925 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
17926 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
17927 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
17928 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
17929 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
17930 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17931 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17932 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17933 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
17934 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
17935 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
17936 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
17938 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
17939 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
17940 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
17941 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
17942 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
17943 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17944 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17945 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17946 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
17947 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
17948 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
17949 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
17951 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
17952 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
17953 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
17954 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
17956 cCL("flts", e000110, 2, (RF, RR), rn_rd),
17957 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
17958 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
17959 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
17960 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
17961 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
17962 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
17963 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
17964 cCL("flte", e080110, 2, (RF, RR), rn_rd),
17965 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
17966 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
17967 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
17969 /* The implementation of the FIX instruction is broken on some
17970 assemblers, in that it accepts a precision specifier as well as a
17971 rounding specifier, despite the fact that this is meaningless.
17972 To be more compatible, we accept it as well, though of course it
17973 does not set any bits. */
17974 cCE("fix", e100110, 2, (RR, RF), rd_rm),
17975 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
17976 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
17977 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
17978 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
17979 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
17980 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
17981 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
17982 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
17983 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
17984 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
17985 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
17986 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
17988 /* Instructions that were new with the real FPA, call them V2. */
17990 #define ARM_VARIANT & fpu_fpa_ext_v2
17992 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17993 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17994 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17995 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17996 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
17997 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18000 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18002 /* Moves and type conversions. */
18003 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18004 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18005 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18006 cCE("fmstat", ef1fa10, 0, (), noargs),
18007 cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
18008 cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
18009 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18010 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18011 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18012 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18013 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18014 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18015 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18016 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18018 /* Memory operations. */
18019 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18020 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18021 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18022 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18023 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18024 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18025 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18026 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18027 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18028 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18029 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18030 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18031 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18032 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18033 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18034 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18035 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18036 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18038 /* Monadic operations. */
18039 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18040 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18041 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18043 /* Dyadic operations. */
18044 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18045 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18046 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18047 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18048 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18049 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18050 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18051 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18052 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18055 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18056 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18057 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18058 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18060 /* Double precision load/store are still present on single precision
18061 implementations. */
18062 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18063 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18064 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18065 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18066 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18067 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18068 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18069 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18070 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18071 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18074 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18076 /* Moves and type conversions. */
18077 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18078 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18079 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18080 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18081 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18082 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18083 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18084 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18085 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18086 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18087 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18088 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18089 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18091 /* Monadic operations. */
18092 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18093 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18094 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18096 /* Dyadic operations. */
18097 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18098 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18099 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18100 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18101 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18102 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18103 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18104 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18105 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18108 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18109 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18110 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18111 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18114 #define ARM_VARIANT & fpu_vfp_ext_v2
18116 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18117 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18118 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18119 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18121 /* Instructions which may belong to either the Neon or VFP instruction sets.
18122 Individual encoder functions perform additional architecture checks. */
18124 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18125 #undef THUMB_VARIANT
18126 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18128 /* These mnemonics are unique to VFP. */
18129 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18130 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18131 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18132 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18133 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18134 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18135 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18136 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18137 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18138 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18140 /* Mnemonics shared by Neon and VFP. */
18141 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18142 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18143 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18145 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18146 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18148 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18149 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18151 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18152 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18153 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18154 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18155 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18156 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18157 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18158 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18160 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
18161 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18162 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18163 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18166 /* NOTE: All VMOV encoding is special-cased! */
18167 NCE(vmov, 0, 1, (VMOV), neon_mov),
18168 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18170 #undef THUMB_VARIANT
18171 #define THUMB_VARIANT & fpu_neon_ext_v1
18173 #define ARM_VARIANT & fpu_neon_ext_v1
18175 /* Data processing with three registers of the same length. */
18176 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18177 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18178 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18179 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18180 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18181 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18182 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18183 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18184 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18185 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18186 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18187 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18188 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18189 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18190 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18191 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18192 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18193 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18194 /* If not immediate, fall back to neon_dyadic_i64_su.
18195 shl_imm should accept I8 I16 I32 I64,
18196 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18197 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18198 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18199 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18200 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18201 /* Logic ops, types optional & ignored. */
18202 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18203 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18204 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18205 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18206 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18207 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18208 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18209 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18210 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18211 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18212 /* Bitfield ops, untyped. */
18213 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18214 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18215 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18216 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18217 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18218 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18219 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18220 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18221 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18222 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18223 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18224 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18225 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18226 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18227 back to neon_dyadic_if_su. */
18228 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18229 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18230 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18231 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18232 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18233 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18234 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18235 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18236 /* Comparison. Type I8 I16 I32 F32. */
18237 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18238 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18239 /* As above, D registers only. */
18240 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18241 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18242 /* Int and float variants, signedness unimportant. */
18243 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18244 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18245 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18246 /* Add/sub take types I8 I16 I32 I64 F32. */
18247 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18248 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18249 /* vtst takes sizes 8, 16, 32. */
18250 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18251 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18252 /* VMUL takes I8 I16 I32 F32 P8. */
18253 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18254 /* VQD{R}MULH takes S16 S32. */
18255 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18256 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18257 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18258 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18259 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18260 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18261 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18262 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18263 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18264 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18265 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18266 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18267 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18268 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18269 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18270 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18272 /* Two address, int/float. Types S8 S16 S32 F32. */
18273 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18274 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18276 /* Data processing with two registers and a shift amount. */
18277 /* Right shifts, and variants with rounding.
18278 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18279 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18280 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18281 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18282 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18283 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18284 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18285 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18286 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18287 /* Shift and insert. Sizes accepted 8 16 32 64. */
18288 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18289 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18290 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18291 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18292 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18293 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18294 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18295 /* Right shift immediate, saturating & narrowing, with rounding variants.
18296 Types accepted S16 S32 S64 U16 U32 U64. */
18297 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18298 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18299 /* As above, unsigned. Types accepted S16 S32 S64. */
18300 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18301 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18302 /* Right shift narrowing. Types accepted I16 I32 I64. */
18303 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18304 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18305 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18306 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18307 /* CVT with optional immediate for fixed-point variant. */
18308 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18310 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18311 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18313 /* Data processing, three registers of different lengths. */
18314 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18315 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18316 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18317 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18318 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18319 /* If not scalar, fall back to neon_dyadic_long.
18320 Vector types as above, scalar types S16 S32 U16 U32. */
18321 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18322 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18323 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18324 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18325 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18326 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18327 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18328 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18329 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18330 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18331 /* Saturating doubling multiplies. Types S16 S32. */
18332 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18333 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18334 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18335 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18336 S16 S32 U16 U32. */
18337 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18339 /* Extract. Size 8. */
18340 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18341 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18343 /* Two registers, miscellaneous. */
18344 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18345 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18346 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18347 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18348 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18349 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18350 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18351 /* Vector replicate. Sizes 8 16 32. */
18352 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18353 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18354 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18355 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18356 /* VMOVN. Types I16 I32 I64. */
18357 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18358 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18359 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18360 /* VQMOVUN. Types S16 S32 S64. */
18361 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18362 /* VZIP / VUZP. Sizes 8 16 32. */
18363 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18364 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18365 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18366 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18367 /* VQABS / VQNEG. Types S8 S16 S32. */
18368 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18369 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18370 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18371 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18372 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18373 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18374 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18375 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18376 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18377 /* Reciprocal estimates. Types U32 F32. */
18378 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18379 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18380 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18381 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18382 /* VCLS. Types S8 S16 S32. */
18383 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18384 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18385 /* VCLZ. Types I8 I16 I32. */
18386 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18387 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18388 /* VCNT. Size 8. */
18389 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18390 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18391 /* Two address, untyped. */
18392 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18393 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18394 /* VTRN. Sizes 8 16 32. */
18395 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18396 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18398 /* Table lookup. Size 8. */
18399 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18400 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18402 #undef THUMB_VARIANT
18403 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18405 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18407 /* Neon element/structure load/store. */
18408 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18409 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18410 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18411 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18412 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18413 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18414 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18415 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18417 #undef THUMB_VARIANT
18418 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18420 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18421 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18422 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18423 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18424 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18425 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18426 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18427 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18428 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18429 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18431 #undef THUMB_VARIANT
18432 #define THUMB_VARIANT & fpu_vfp_ext_v3
18434 #define ARM_VARIANT & fpu_vfp_ext_v3
18436 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18437 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18438 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18439 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18440 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18441 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18442 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18443 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18444 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18447 #define ARM_VARIANT &fpu_vfp_ext_fma
18448 #undef THUMB_VARIANT
18449 #define THUMB_VARIANT &fpu_vfp_ext_fma
18450 /* Mnemonics shared by Neon and VFP. These are included in the
18451 VFP FMA variant; NEON and VFP FMA always includes the NEON
18452 FMA instructions. */
18453 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18454 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18455 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18456 the v form should always be used. */
18457 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18458 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18459 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18460 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18461 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18462 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18464 #undef THUMB_VARIANT
18466 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18468 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18469 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18470 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18471 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18472 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18473 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18474 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18475 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18478 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18480 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18481 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18482 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18483 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18484 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18485 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18486 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18487 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18488 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18489 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18490 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18491 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18492 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18493 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18494 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18495 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18496 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18497 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18498 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18499 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18500 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18501 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18502 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18503 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18504 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18505 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18506 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18507 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18508 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18509 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18510 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18511 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18512 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18513 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18514 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18515 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18516 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18517 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18518 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18519 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18520 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18521 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18522 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18523 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18524 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18525 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18526 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18527 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18528 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18529 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18530 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18531 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18532 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18533 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18534 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18535 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18536 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18537 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18538 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18539 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18540 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18541 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18542 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18543 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18544 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18545 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18546 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18547 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18548 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18549 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18550 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18551 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18552 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18553 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18554 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18555 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18556 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18557 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18558 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18559 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18560 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18561 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18562 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18563 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18564 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18565 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18566 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18567 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18568 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18569 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18570 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18571 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18572 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18573 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18574 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18575 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18576 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18577 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18578 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18579 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18580 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18581 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18582 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18583 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18584 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18585 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18586 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18587 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18588 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18589 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18590 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18591 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18592 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18593 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18594 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18595 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18596 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18597 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18598 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18599 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18600 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18601 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18602 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18603 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18604 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18605 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18606 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18607 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18608 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18609 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18610 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18611 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18612 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18613 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18614 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18615 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18616 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18617 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18618 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18619 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18620 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18621 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18622 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18623 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18624 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18625 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18626 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18627 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18628 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18629 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18630 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18631 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18632 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18633 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18634 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18635 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18636 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18637 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18638 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18639 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18640 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18641 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18644 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18646 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18647 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18648 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18649 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18650 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18651 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18652 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18653 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18654 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18655 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18656 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18657 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18658 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18659 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18660 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18661 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18662 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18663 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18664 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18665 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18666 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18667 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18668 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18669 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18670 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18671 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18672 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18673 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18674 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18675 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18676 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18677 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18678 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18679 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18680 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18681 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18682 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18683 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18684 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18685 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18686 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18687 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18688 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18689 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18690 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18691 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18692 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18693 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18694 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18695 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18696 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18697 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18698 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18699 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18700 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18701 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18702 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18705 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18707 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18708 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18709 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18710 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18711 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18712 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18713 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18714 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18715 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18716 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18717 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18718 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18719 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18720 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18721 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18722 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18723 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18724 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18725 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18726 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18727 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18728 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18729 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18730 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18731 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18732 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18733 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18734 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18735 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18736 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18737 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18738 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18739 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18740 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18741 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18742 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18743 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18744 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18745 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18746 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18747 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18748 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18749 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18750 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18751 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18752 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18753 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18754 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18755 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18756 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18757 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18758 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18759 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18760 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18761 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18762 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18763 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18764 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18765 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18766 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18767 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18768 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18769 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18770 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18771 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18772 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18773 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18774 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18775 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18776 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18777 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18778 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18779 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18780 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18781 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18782 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18785 #undef THUMB_VARIANT
18812 /* MD interface: bits in the object file. */
18814 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18815 for use in the a.out file, and stores them in the array pointed to by buf.
18816 This knows about the endian-ness of the target machine and does
18817 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18818 2 (short) and 4 (long) Floating numbers are put out as a series of
18819 LITTLENUMS (shorts, here at least). */
18822 md_number_to_chars (char * buf, valueT val, int n)
18824 if (target_big_endian)
18825 number_to_chars_bigendian (buf, val, n);
18827 number_to_chars_littleendian (buf, val, n);
18831 md_chars_to_number (char * buf, int n)
18834 unsigned char * where = (unsigned char *) buf;
18836 if (target_big_endian)
18841 result |= (*where++ & 255);
18849 result |= (where[n] & 255);
18856 /* MD interface: Sections. */
18858 /* Estimate the size of a frag before relaxing. Assume everything fits in
18862 md_estimate_size_before_relax (fragS * fragp,
18863 segT segtype ATTRIBUTE_UNUSED)
18869 /* Convert a machine dependent frag. */
18872 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
18874 unsigned long insn;
18875 unsigned long old_op;
18883 buf = fragp->fr_literal + fragp->fr_fix;
18885 old_op = bfd_get_16(abfd, buf);
18886 if (fragp->fr_symbol)
18888 exp.X_op = O_symbol;
18889 exp.X_add_symbol = fragp->fr_symbol;
18893 exp.X_op = O_constant;
18895 exp.X_add_number = fragp->fr_offset;
18896 opcode = fragp->fr_subtype;
18899 case T_MNEM_ldr_pc:
18900 case T_MNEM_ldr_pc2:
18901 case T_MNEM_ldr_sp:
18902 case T_MNEM_str_sp:
18909 if (fragp->fr_var == 4)
18911 insn = THUMB_OP32 (opcode);
18912 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
18914 insn |= (old_op & 0x700) << 4;
18918 insn |= (old_op & 7) << 12;
18919 insn |= (old_op & 0x38) << 13;
18921 insn |= 0x00000c00;
18922 put_thumb32_insn (buf, insn);
18923 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
18927 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
18929 pc_rel = (opcode == T_MNEM_ldr_pc2);
18932 if (fragp->fr_var == 4)
18934 insn = THUMB_OP32 (opcode);
18935 insn |= (old_op & 0xf0) << 4;
18936 put_thumb32_insn (buf, insn);
18937 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
18941 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
18942 exp.X_add_number -= 4;
18950 if (fragp->fr_var == 4)
18952 int r0off = (opcode == T_MNEM_mov
18953 || opcode == T_MNEM_movs) ? 0 : 8;
18954 insn = THUMB_OP32 (opcode);
18955 insn = (insn & 0xe1ffffff) | 0x10000000;
18956 insn |= (old_op & 0x700) << r0off;
18957 put_thumb32_insn (buf, insn);
18958 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
18962 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
18967 if (fragp->fr_var == 4)
18969 insn = THUMB_OP32(opcode);
18970 put_thumb32_insn (buf, insn);
18971 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
18974 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
18978 if (fragp->fr_var == 4)
18980 insn = THUMB_OP32(opcode);
18981 insn |= (old_op & 0xf00) << 14;
18982 put_thumb32_insn (buf, insn);
18983 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
18986 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
18989 case T_MNEM_add_sp:
18990 case T_MNEM_add_pc:
18991 case T_MNEM_inc_sp:
18992 case T_MNEM_dec_sp:
18993 if (fragp->fr_var == 4)
18995 /* ??? Choose between add and addw. */
18996 insn = THUMB_OP32 (opcode);
18997 insn |= (old_op & 0xf0) << 4;
18998 put_thumb32_insn (buf, insn);
18999 if (opcode == T_MNEM_add_pc)
19000 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19002 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19005 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19013 if (fragp->fr_var == 4)
19015 insn = THUMB_OP32 (opcode);
19016 insn |= (old_op & 0xf0) << 4;
19017 insn |= (old_op & 0xf) << 16;
19018 put_thumb32_insn (buf, insn);
19019 if (insn & (1 << 20))
19020 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19022 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19025 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19031 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19032 (enum bfd_reloc_code_real) reloc_type);
19033 fixp->fx_file = fragp->fr_file;
19034 fixp->fx_line = fragp->fr_line;
19035 fragp->fr_fix += fragp->fr_var;
19038 /* Return the size of a relaxable immediate operand instruction.
19039 SHIFT and SIZE specify the form of the allowable immediate. */
19041 relax_immediate (fragS *fragp, int size, int shift)
19047 /* ??? Should be able to do better than this. */
19048 if (fragp->fr_symbol)
19051 low = (1 << shift) - 1;
19052 mask = (1 << (shift + size)) - (1 << shift);
19053 offset = fragp->fr_offset;
19054 /* Force misaligned offsets to 32-bit variant. */
19057 if (offset & ~mask)
19062 /* Get the address of a symbol during relaxation. */
19064 relaxed_symbol_addr (fragS *fragp, long stretch)
19070 sym = fragp->fr_symbol;
19071 sym_frag = symbol_get_frag (sym);
19072 know (S_GET_SEGMENT (sym) != absolute_section
19073 || sym_frag == &zero_address_frag);
19074 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19076 /* If frag has yet to be reached on this pass, assume it will
19077 move by STRETCH just as we did. If this is not so, it will
19078 be because some frag between grows, and that will force
19082 && sym_frag->relax_marker != fragp->relax_marker)
19086 /* Adjust stretch for any alignment frag. Note that if have
19087 been expanding the earlier code, the symbol may be
19088 defined in what appears to be an earlier frag. FIXME:
19089 This doesn't handle the fr_subtype field, which specifies
19090 a maximum number of bytes to skip when doing an
19092 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19094 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19097 stretch = - ((- stretch)
19098 & ~ ((1 << (int) f->fr_offset) - 1));
19100 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19112 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19115 relax_adr (fragS *fragp, asection *sec, long stretch)
19120 /* Assume worst case for symbols not known to be in the same section. */
19121 if (fragp->fr_symbol == NULL
19122 || !S_IS_DEFINED (fragp->fr_symbol)
19123 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19124 || S_IS_WEAK (fragp->fr_symbol))
19127 val = relaxed_symbol_addr (fragp, stretch);
19128 addr = fragp->fr_address + fragp->fr_fix;
19129 addr = (addr + 4) & ~3;
19130 /* Force misaligned targets to 32-bit variant. */
19134 if (val < 0 || val > 1020)
19139 /* Return the size of a relaxable add/sub immediate instruction. */
19141 relax_addsub (fragS *fragp, asection *sec)
19146 buf = fragp->fr_literal + fragp->fr_fix;
19147 op = bfd_get_16(sec->owner, buf);
19148 if ((op & 0xf) == ((op >> 4) & 0xf))
19149 return relax_immediate (fragp, 8, 0);
19151 return relax_immediate (fragp, 3, 0);
19155 /* Return the size of a relaxable branch instruction. BITS is the
19156 size of the offset field in the narrow instruction. */
19159 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19165 /* Assume worst case for symbols not known to be in the same section. */
19166 if (!S_IS_DEFINED (fragp->fr_symbol)
19167 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19168 || S_IS_WEAK (fragp->fr_symbol))
19172 if (S_IS_DEFINED (fragp->fr_symbol)
19173 && ARM_IS_FUNC (fragp->fr_symbol))
19176 /* PR 12532. Global symbols with default visibility might
19177 be preempted, so do not relax relocations to them. */
19178 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19179 && (! S_IS_LOCAL (fragp->fr_symbol)))
19183 val = relaxed_symbol_addr (fragp, stretch);
19184 addr = fragp->fr_address + fragp->fr_fix + 4;
19187 /* Offset is a signed value *2 */
19189 if (val >= limit || val < -limit)
19195 /* Relax a machine dependent frag. This returns the amount by which
19196 the current size of the frag should change. */
19199 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19204 oldsize = fragp->fr_var;
19205 switch (fragp->fr_subtype)
19207 case T_MNEM_ldr_pc2:
19208 newsize = relax_adr (fragp, sec, stretch);
19210 case T_MNEM_ldr_pc:
19211 case T_MNEM_ldr_sp:
19212 case T_MNEM_str_sp:
19213 newsize = relax_immediate (fragp, 8, 2);
19217 newsize = relax_immediate (fragp, 5, 2);
19221 newsize = relax_immediate (fragp, 5, 1);
19225 newsize = relax_immediate (fragp, 5, 0);
19228 newsize = relax_adr (fragp, sec, stretch);
19234 newsize = relax_immediate (fragp, 8, 0);
19237 newsize = relax_branch (fragp, sec, 11, stretch);
19240 newsize = relax_branch (fragp, sec, 8, stretch);
19242 case T_MNEM_add_sp:
19243 case T_MNEM_add_pc:
19244 newsize = relax_immediate (fragp, 8, 2);
19246 case T_MNEM_inc_sp:
19247 case T_MNEM_dec_sp:
19248 newsize = relax_immediate (fragp, 7, 2);
19254 newsize = relax_addsub (fragp, sec);
19260 fragp->fr_var = newsize;
19261 /* Freeze wide instructions that are at or before the same location as
19262 in the previous pass. This avoids infinite loops.
19263 Don't freeze them unconditionally because targets may be artificially
19264 misaligned by the expansion of preceding frags. */
19265 if (stretch <= 0 && newsize > 2)
19267 md_convert_frag (sec->owner, sec, fragp);
19271 return newsize - oldsize;
19274 /* Round up a section size to the appropriate boundary. */
19277 md_section_align (segT segment ATTRIBUTE_UNUSED,
19280 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19281 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19283 /* For a.out, force the section size to be aligned. If we don't do
19284 this, BFD will align it for us, but it will not write out the
19285 final bytes of the section. This may be a bug in BFD, but it is
19286 easier to fix it here since that is how the other a.out targets
19290 align = bfd_get_section_alignment (stdoutput, segment);
19291 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19298 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19299 of an rs_align_code fragment. */
19302 arm_handle_align (fragS * fragP)
19304 static char const arm_noop[2][2][4] =
19307 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19308 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19311 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19312 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19315 static char const thumb_noop[2][2][2] =
19318 {0xc0, 0x46}, /* LE */
19319 {0x46, 0xc0}, /* BE */
19322 {0x00, 0xbf}, /* LE */
19323 {0xbf, 0x00} /* BE */
19326 static char const wide_thumb_noop[2][4] =
19327 { /* Wide Thumb-2 */
19328 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19329 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19332 unsigned bytes, fix, noop_size;
19335 const char *narrow_noop = NULL;
19340 if (fragP->fr_type != rs_align_code)
19343 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19344 p = fragP->fr_literal + fragP->fr_fix;
19347 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19348 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19350 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19352 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19354 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19356 narrow_noop = thumb_noop[1][target_big_endian];
19357 noop = wide_thumb_noop[target_big_endian];
19360 noop = thumb_noop[0][target_big_endian];
19368 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19369 [target_big_endian];
19376 fragP->fr_var = noop_size;
19378 if (bytes & (noop_size - 1))
19380 fix = bytes & (noop_size - 1);
19382 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19384 memset (p, 0, fix);
19391 if (bytes & noop_size)
19393 /* Insert a narrow noop. */
19394 memcpy (p, narrow_noop, noop_size);
19396 bytes -= noop_size;
19400 /* Use wide noops for the remainder */
19404 while (bytes >= noop_size)
19406 memcpy (p, noop, noop_size);
19408 bytes -= noop_size;
19412 fragP->fr_fix += fix;
19415 /* Called from md_do_align. Used to create an alignment
19416 frag in a code section. */
19419 arm_frag_align_code (int n, int max)
19423 /* We assume that there will never be a requirement
19424 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19425 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19430 _("alignments greater than %d bytes not supported in .text sections."),
19431 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19432 as_fatal ("%s", err_msg);
19435 p = frag_var (rs_align_code,
19436 MAX_MEM_FOR_RS_ALIGN_CODE,
19438 (relax_substateT) max,
19445 /* Perform target specific initialisation of a frag.
19446 Note - despite the name this initialisation is not done when the frag
19447 is created, but only when its type is assigned. A frag can be created
19448 and used a long time before its type is set, so beware of assuming that
19449 this initialisationis performed first. */
19453 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19455 /* Record whether this frag is in an ARM or a THUMB area. */
19456 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19459 #else /* OBJ_ELF is defined. */
19461 arm_init_frag (fragS * fragP, int max_chars)
19463 /* If the current ARM vs THUMB mode has not already
19464 been recorded into this frag then do so now. */
19465 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19467 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19469 /* Record a mapping symbol for alignment frags. We will delete this
19470 later if the alignment ends up empty. */
19471 switch (fragP->fr_type)
19474 case rs_align_test:
19476 mapping_state_2 (MAP_DATA, max_chars);
19478 case rs_align_code:
19479 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19487 /* When we change sections we need to issue a new mapping symbol. */
19490 arm_elf_change_section (void)
19492 /* Link an unlinked unwind index table section to the .text section. */
19493 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19494 && elf_linked_to_section (now_seg) == NULL)
19495 elf_linked_to_section (now_seg) = text_section;
19499 arm_elf_section_type (const char * str, size_t len)
19501 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19502 return SHT_ARM_EXIDX;
19507 /* Code to deal with unwinding tables. */
19509 static void add_unwind_adjustsp (offsetT);
19511 /* Generate any deferred unwind frame offset. */
19514 flush_pending_unwind (void)
19518 offset = unwind.pending_offset;
19519 unwind.pending_offset = 0;
19521 add_unwind_adjustsp (offset);
19524 /* Add an opcode to this list for this function. Two-byte opcodes should
19525 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19529 add_unwind_opcode (valueT op, int length)
19531 /* Add any deferred stack adjustment. */
19532 if (unwind.pending_offset)
19533 flush_pending_unwind ();
19535 unwind.sp_restored = 0;
19537 if (unwind.opcode_count + length > unwind.opcode_alloc)
19539 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19540 if (unwind.opcodes)
19541 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19542 unwind.opcode_alloc);
19544 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19549 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19551 unwind.opcode_count++;
19555 /* Add unwind opcodes to adjust the stack pointer. */
19558 add_unwind_adjustsp (offsetT offset)
19562 if (offset > 0x200)
19564 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19569 /* Long form: 0xb2, uleb128. */
19570 /* This might not fit in a word so add the individual bytes,
19571 remembering the list is built in reverse order. */
19572 o = (valueT) ((offset - 0x204) >> 2);
19574 add_unwind_opcode (0, 1);
19576 /* Calculate the uleb128 encoding of the offset. */
19580 bytes[n] = o & 0x7f;
19586 /* Add the insn. */
19588 add_unwind_opcode (bytes[n - 1], 1);
19589 add_unwind_opcode (0xb2, 1);
19591 else if (offset > 0x100)
19593 /* Two short opcodes. */
19594 add_unwind_opcode (0x3f, 1);
19595 op = (offset - 0x104) >> 2;
19596 add_unwind_opcode (op, 1);
19598 else if (offset > 0)
19600 /* Short opcode. */
19601 op = (offset - 4) >> 2;
19602 add_unwind_opcode (op, 1);
19604 else if (offset < 0)
19607 while (offset > 0x100)
19609 add_unwind_opcode (0x7f, 1);
19612 op = ((offset - 4) >> 2) | 0x40;
19613 add_unwind_opcode (op, 1);
19617 /* Finish the list of unwind opcodes for this function. */
19619 finish_unwind_opcodes (void)
19623 if (unwind.fp_used)
19625 /* Adjust sp as necessary. */
19626 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19627 flush_pending_unwind ();
19629 /* After restoring sp from the frame pointer. */
19630 op = 0x90 | unwind.fp_reg;
19631 add_unwind_opcode (op, 1);
19634 flush_pending_unwind ();
19638 /* Start an exception table entry. If idx is nonzero this is an index table
19642 start_unwind_section (const segT text_seg, int idx)
19644 const char * text_name;
19645 const char * prefix;
19646 const char * prefix_once;
19647 const char * group_name;
19651 size_t sec_name_len;
19658 prefix = ELF_STRING_ARM_unwind;
19659 prefix_once = ELF_STRING_ARM_unwind_once;
19660 type = SHT_ARM_EXIDX;
19664 prefix = ELF_STRING_ARM_unwind_info;
19665 prefix_once = ELF_STRING_ARM_unwind_info_once;
19666 type = SHT_PROGBITS;
19669 text_name = segment_name (text_seg);
19670 if (streq (text_name, ".text"))
19673 if (strncmp (text_name, ".gnu.linkonce.t.",
19674 strlen (".gnu.linkonce.t.")) == 0)
19676 prefix = prefix_once;
19677 text_name += strlen (".gnu.linkonce.t.");
19680 prefix_len = strlen (prefix);
19681 text_len = strlen (text_name);
19682 sec_name_len = prefix_len + text_len;
19683 sec_name = (char *) xmalloc (sec_name_len + 1);
19684 memcpy (sec_name, prefix, prefix_len);
19685 memcpy (sec_name + prefix_len, text_name, text_len);
19686 sec_name[prefix_len + text_len] = '\0';
19692 /* Handle COMDAT group. */
19693 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19695 group_name = elf_group_name (text_seg);
19696 if (group_name == NULL)
19698 as_bad (_("Group section `%s' has no group signature"),
19699 segment_name (text_seg));
19700 ignore_rest_of_line ();
19703 flags |= SHF_GROUP;
19707 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19709 /* Set the section link for index tables. */
19711 elf_linked_to_section (now_seg) = text_seg;
19715 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19716 personality routine data. Returns zero, or the index table value for
19717 and inline entry. */
19720 create_unwind_entry (int have_data)
19725 /* The current word of data. */
19727 /* The number of bytes left in this word. */
19730 finish_unwind_opcodes ();
19732 /* Remember the current text section. */
19733 unwind.saved_seg = now_seg;
19734 unwind.saved_subseg = now_subseg;
19736 start_unwind_section (now_seg, 0);
19738 if (unwind.personality_routine == NULL)
19740 if (unwind.personality_index == -2)
19743 as_bad (_("handlerdata in cantunwind frame"));
19744 return 1; /* EXIDX_CANTUNWIND. */
19747 /* Use a default personality routine if none is specified. */
19748 if (unwind.personality_index == -1)
19750 if (unwind.opcode_count > 3)
19751 unwind.personality_index = 1;
19753 unwind.personality_index = 0;
19756 /* Space for the personality routine entry. */
19757 if (unwind.personality_index == 0)
19759 if (unwind.opcode_count > 3)
19760 as_bad (_("too many unwind opcodes for personality routine 0"));
19764 /* All the data is inline in the index table. */
19767 while (unwind.opcode_count > 0)
19769 unwind.opcode_count--;
19770 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19774 /* Pad with "finish" opcodes. */
19776 data = (data << 8) | 0xb0;
19783 /* We get two opcodes "free" in the first word. */
19784 size = unwind.opcode_count - 2;
19787 /* An extra byte is required for the opcode count. */
19788 size = unwind.opcode_count + 1;
19790 size = (size + 3) >> 2;
19792 as_bad (_("too many unwind opcodes"));
19794 frag_align (2, 0, 0);
19795 record_alignment (now_seg, 2);
19796 unwind.table_entry = expr_build_dot ();
19798 /* Allocate the table entry. */
19799 ptr = frag_more ((size << 2) + 4);
19800 where = frag_now_fix () - ((size << 2) + 4);
19802 switch (unwind.personality_index)
19805 /* ??? Should this be a PLT generating relocation? */
19806 /* Custom personality routine. */
19807 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
19808 BFD_RELOC_ARM_PREL31);
19813 /* Set the first byte to the number of additional words. */
19818 /* ABI defined personality routines. */
19820 /* Three opcodes bytes are packed into the first word. */
19827 /* The size and first two opcode bytes go in the first word. */
19828 data = ((0x80 + unwind.personality_index) << 8) | size;
19833 /* Should never happen. */
19837 /* Pack the opcodes into words (MSB first), reversing the list at the same
19839 while (unwind.opcode_count > 0)
19843 md_number_to_chars (ptr, data, 4);
19848 unwind.opcode_count--;
19850 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19853 /* Finish off the last word. */
19856 /* Pad with "finish" opcodes. */
19858 data = (data << 8) | 0xb0;
19860 md_number_to_chars (ptr, data, 4);
19865 /* Add an empty descriptor if there is no user-specified data. */
19866 ptr = frag_more (4);
19867 md_number_to_chars (ptr, 0, 4);
19874 /* Initialize the DWARF-2 unwind information for this procedure. */
19877 tc_arm_frame_initial_instructions (void)
19879 cfi_add_CFA_def_cfa (REG_SP, 0);
19881 #endif /* OBJ_ELF */
19883 /* Convert REGNAME to a DWARF-2 register number. */
19886 tc_arm_regname_to_dw2regnum (char *regname)
19888 int reg = arm_reg_parse (®name, REG_TYPE_RN);
19898 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
19902 exp.X_op = O_secrel;
19903 exp.X_add_symbol = symbol;
19904 exp.X_add_number = 0;
19905 emit_expr (&exp, size);
19909 /* MD interface: Symbol and relocation handling. */
19911 /* Return the address within the segment that a PC-relative fixup is
19912 relative to. For ARM, PC-relative fixups applied to instructions
19913 are generally relative to the location of the fixup plus 8 bytes.
19914 Thumb branches are offset by 4, and Thumb loads relative to PC
19915 require special handling. */
19918 md_pcrel_from_section (fixS * fixP, segT seg)
19920 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
19922 /* If this is pc-relative and we are going to emit a relocation
19923 then we just want to put out any pipeline compensation that the linker
19924 will need. Otherwise we want to use the calculated base.
19925 For WinCE we skip the bias for externals as well, since this
19926 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19928 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
19929 || (arm_force_relocation (fixP)
19931 && !S_IS_EXTERNAL (fixP->fx_addsy)
19937 switch (fixP->fx_r_type)
19939 /* PC relative addressing on the Thumb is slightly odd as the
19940 bottom two bits of the PC are forced to zero for the
19941 calculation. This happens *after* application of the
19942 pipeline offset. However, Thumb adrl already adjusts for
19943 this, so we need not do it again. */
19944 case BFD_RELOC_ARM_THUMB_ADD:
19947 case BFD_RELOC_ARM_THUMB_OFFSET:
19948 case BFD_RELOC_ARM_T32_OFFSET_IMM:
19949 case BFD_RELOC_ARM_T32_ADD_PC12:
19950 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
19951 return (base + 4) & ~3;
19953 /* Thumb branches are simply offset by +4. */
19954 case BFD_RELOC_THUMB_PCREL_BRANCH7:
19955 case BFD_RELOC_THUMB_PCREL_BRANCH9:
19956 case BFD_RELOC_THUMB_PCREL_BRANCH12:
19957 case BFD_RELOC_THUMB_PCREL_BRANCH20:
19958 case BFD_RELOC_THUMB_PCREL_BRANCH25:
19961 case BFD_RELOC_THUMB_PCREL_BRANCH23:
19963 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19964 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
19965 && ARM_IS_FUNC (fixP->fx_addsy)
19966 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19967 base = fixP->fx_where + fixP->fx_frag->fr_address;
19970 /* BLX is like branches above, but forces the low two bits of PC to
19972 case BFD_RELOC_THUMB_PCREL_BLX:
19974 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19975 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
19976 && THUMB_IS_FUNC (fixP->fx_addsy)
19977 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19978 base = fixP->fx_where + fixP->fx_frag->fr_address;
19979 return (base + 4) & ~3;
19981 /* ARM mode branches are offset by +8. However, the Windows CE
19982 loader expects the relocation not to take this into account. */
19983 case BFD_RELOC_ARM_PCREL_BLX:
19985 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19986 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
19987 && ARM_IS_FUNC (fixP->fx_addsy)
19988 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19989 base = fixP->fx_where + fixP->fx_frag->fr_address;
19992 case BFD_RELOC_ARM_PCREL_CALL:
19994 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
19995 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
19996 && THUMB_IS_FUNC (fixP->fx_addsy)
19997 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
19998 base = fixP->fx_where + fixP->fx_frag->fr_address;
20001 case BFD_RELOC_ARM_PCREL_BRANCH:
20002 case BFD_RELOC_ARM_PCREL_JUMP:
20003 case BFD_RELOC_ARM_PLT32:
20005 /* When handling fixups immediately, because we have already
20006 discovered the value of a symbol, or the address of the frag involved
20007 we must account for the offset by +8, as the OS loader will never see the reloc.
20008 see fixup_segment() in write.c
20009 The S_IS_EXTERNAL test handles the case of global symbols.
20010 Those need the calculated base, not just the pipe compensation the linker will need. */
20012 && fixP->fx_addsy != NULL
20013 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20014 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20022 /* ARM mode loads relative to PC are also offset by +8. Unlike
20023 branches, the Windows CE loader *does* expect the relocation
20024 to take this into account. */
20025 case BFD_RELOC_ARM_OFFSET_IMM:
20026 case BFD_RELOC_ARM_OFFSET_IMM8:
20027 case BFD_RELOC_ARM_HWLITERAL:
20028 case BFD_RELOC_ARM_LITERAL:
20029 case BFD_RELOC_ARM_CP_OFF_IMM:
20033 /* Other PC-relative relocations are un-offset. */
20039 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20040 Otherwise we have no need to default values of symbols. */
20043 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20046 if (name[0] == '_' && name[1] == 'G'
20047 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20051 if (symbol_find (name))
20052 as_bad (_("GOT already in the symbol table"));
20054 GOT_symbol = symbol_new (name, undefined_section,
20055 (valueT) 0, & zero_address_frag);
20065 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20066 computed as two separate immediate values, added together. We
20067 already know that this value cannot be computed by just one ARM
20070 static unsigned int
20071 validate_immediate_twopart (unsigned int val,
20072 unsigned int * highpart)
20077 for (i = 0; i < 32; i += 2)
20078 if (((a = rotate_left (val, i)) & 0xff) != 0)
20084 * highpart = (a >> 8) | ((i + 24) << 7);
20086 else if (a & 0xff0000)
20088 if (a & 0xff000000)
20090 * highpart = (a >> 16) | ((i + 16) << 7);
20094 gas_assert (a & 0xff000000);
20095 * highpart = (a >> 24) | ((i + 8) << 7);
20098 return (a & 0xff) | (i << 7);
20105 validate_offset_imm (unsigned int val, int hwse)
20107 if ((hwse && val > 255) || val > 4095)
20112 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20113 negative immediate constant by altering the instruction. A bit of
20118 by inverting the second operand, and
20121 by negating the second operand. */
20124 negate_data_op (unsigned long * instruction,
20125 unsigned long value)
20128 unsigned long negated, inverted;
20130 negated = encode_arm_immediate (-value);
20131 inverted = encode_arm_immediate (~value);
20133 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20136 /* First negates. */
20137 case OPCODE_SUB: /* ADD <-> SUB */
20138 new_inst = OPCODE_ADD;
20143 new_inst = OPCODE_SUB;
20147 case OPCODE_CMP: /* CMP <-> CMN */
20148 new_inst = OPCODE_CMN;
20153 new_inst = OPCODE_CMP;
20157 /* Now Inverted ops. */
20158 case OPCODE_MOV: /* MOV <-> MVN */
20159 new_inst = OPCODE_MVN;
20164 new_inst = OPCODE_MOV;
20168 case OPCODE_AND: /* AND <-> BIC */
20169 new_inst = OPCODE_BIC;
20174 new_inst = OPCODE_AND;
20178 case OPCODE_ADC: /* ADC <-> SBC */
20179 new_inst = OPCODE_SBC;
20184 new_inst = OPCODE_ADC;
20188 /* We cannot do anything. */
20193 if (value == (unsigned) FAIL)
20196 *instruction &= OPCODE_MASK;
20197 *instruction |= new_inst << DATA_OP_SHIFT;
20201 /* Like negate_data_op, but for Thumb-2. */
20203 static unsigned int
20204 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20208 unsigned int negated, inverted;
20210 negated = encode_thumb32_immediate (-value);
20211 inverted = encode_thumb32_immediate (~value);
20213 rd = (*instruction >> 8) & 0xf;
20214 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20217 /* ADD <-> SUB. Includes CMP <-> CMN. */
20218 case T2_OPCODE_SUB:
20219 new_inst = T2_OPCODE_ADD;
20223 case T2_OPCODE_ADD:
20224 new_inst = T2_OPCODE_SUB;
20228 /* ORR <-> ORN. Includes MOV <-> MVN. */
20229 case T2_OPCODE_ORR:
20230 new_inst = T2_OPCODE_ORN;
20234 case T2_OPCODE_ORN:
20235 new_inst = T2_OPCODE_ORR;
20239 /* AND <-> BIC. TST has no inverted equivalent. */
20240 case T2_OPCODE_AND:
20241 new_inst = T2_OPCODE_BIC;
20248 case T2_OPCODE_BIC:
20249 new_inst = T2_OPCODE_AND;
20254 case T2_OPCODE_ADC:
20255 new_inst = T2_OPCODE_SBC;
20259 case T2_OPCODE_SBC:
20260 new_inst = T2_OPCODE_ADC;
20264 /* We cannot do anything. */
20269 if (value == (unsigned int)FAIL)
20272 *instruction &= T2_OPCODE_MASK;
20273 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20277 /* Read a 32-bit thumb instruction from buf. */
20278 static unsigned long
20279 get_thumb32_insn (char * buf)
20281 unsigned long insn;
20282 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20283 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20289 /* We usually want to set the low bit on the address of thumb function
20290 symbols. In particular .word foo - . should have the low bit set.
20291 Generic code tries to fold the difference of two symbols to
20292 a constant. Prevent this and force a relocation when the first symbols
20293 is a thumb function. */
20296 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20298 if (op == O_subtract
20299 && l->X_op == O_symbol
20300 && r->X_op == O_symbol
20301 && THUMB_IS_FUNC (l->X_add_symbol))
20303 l->X_op = O_subtract;
20304 l->X_op_symbol = r->X_add_symbol;
20305 l->X_add_number -= r->X_add_number;
20309 /* Process as normal. */
20313 /* Encode Thumb2 unconditional branches and calls. The encoding
20314 for the 2 are identical for the immediate values. */
20317 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20319 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20322 addressT S, I1, I2, lo, hi;
20324 S = (value >> 24) & 0x01;
20325 I1 = (value >> 23) & 0x01;
20326 I2 = (value >> 22) & 0x01;
20327 hi = (value >> 12) & 0x3ff;
20328 lo = (value >> 1) & 0x7ff;
20329 newval = md_chars_to_number (buf, THUMB_SIZE);
20330 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20331 newval |= (S << 10) | hi;
20332 newval2 &= ~T2I1I2MASK;
20333 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20334 md_number_to_chars (buf, newval, THUMB_SIZE);
20335 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20339 md_apply_fix (fixS * fixP,
20343 offsetT value = * valP;
20345 unsigned int newimm;
20346 unsigned long temp;
20348 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20350 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20352 /* Note whether this will delete the relocation. */
20354 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20357 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20358 consistency with the behaviour on 32-bit hosts. Remember value
20360 value &= 0xffffffff;
20361 value ^= 0x80000000;
20362 value -= 0x80000000;
20365 fixP->fx_addnumber = value;
20367 /* Same treatment for fixP->fx_offset. */
20368 fixP->fx_offset &= 0xffffffff;
20369 fixP->fx_offset ^= 0x80000000;
20370 fixP->fx_offset -= 0x80000000;
20372 switch (fixP->fx_r_type)
20374 case BFD_RELOC_NONE:
20375 /* This will need to go in the object file. */
20379 case BFD_RELOC_ARM_IMMEDIATE:
20380 /* We claim that this fixup has been processed here,
20381 even if in fact we generate an error because we do
20382 not have a reloc for it, so tc_gen_reloc will reject it. */
20385 if (fixP->fx_addsy)
20387 const char *msg = 0;
20389 if (! S_IS_DEFINED (fixP->fx_addsy))
20390 msg = _("undefined symbol %s used as an immediate value");
20391 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20392 msg = _("symbol %s is in a different section");
20393 else if (S_IS_WEAK (fixP->fx_addsy))
20394 msg = _("symbol %s is weak and may be overridden later");
20398 as_bad_where (fixP->fx_file, fixP->fx_line,
20399 msg, S_GET_NAME (fixP->fx_addsy));
20404 newimm = encode_arm_immediate (value);
20405 temp = md_chars_to_number (buf, INSN_SIZE);
20407 /* If the instruction will fail, see if we can fix things up by
20408 changing the opcode. */
20409 if (newimm == (unsigned int) FAIL
20410 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
20412 as_bad_where (fixP->fx_file, fixP->fx_line,
20413 _("invalid constant (%lx) after fixup"),
20414 (unsigned long) value);
20418 newimm |= (temp & 0xfffff000);
20419 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20422 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20424 unsigned int highpart = 0;
20425 unsigned int newinsn = 0xe1a00000; /* nop. */
20427 if (fixP->fx_addsy)
20429 const char *msg = 0;
20431 if (! S_IS_DEFINED (fixP->fx_addsy))
20432 msg = _("undefined symbol %s used as an immediate value");
20433 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20434 msg = _("symbol %s is in a different section");
20435 else if (S_IS_WEAK (fixP->fx_addsy))
20436 msg = _("symbol %s is weak and may be overridden later");
20440 as_bad_where (fixP->fx_file, fixP->fx_line,
20441 msg, S_GET_NAME (fixP->fx_addsy));
20446 newimm = encode_arm_immediate (value);
20447 temp = md_chars_to_number (buf, INSN_SIZE);
20449 /* If the instruction will fail, see if we can fix things up by
20450 changing the opcode. */
20451 if (newimm == (unsigned int) FAIL
20452 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20454 /* No ? OK - try using two ADD instructions to generate
20456 newimm = validate_immediate_twopart (value, & highpart);
20458 /* Yes - then make sure that the second instruction is
20460 if (newimm != (unsigned int) FAIL)
20462 /* Still No ? Try using a negated value. */
20463 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20464 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20465 /* Otherwise - give up. */
20468 as_bad_where (fixP->fx_file, fixP->fx_line,
20469 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20474 /* Replace the first operand in the 2nd instruction (which
20475 is the PC) with the destination register. We have
20476 already added in the PC in the first instruction and we
20477 do not want to do it again. */
20478 newinsn &= ~ 0xf0000;
20479 newinsn |= ((newinsn & 0x0f000) << 4);
20482 newimm |= (temp & 0xfffff000);
20483 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20485 highpart |= (newinsn & 0xfffff000);
20486 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20490 case BFD_RELOC_ARM_OFFSET_IMM:
20491 if (!fixP->fx_done && seg->use_rela_p)
20494 case BFD_RELOC_ARM_LITERAL:
20500 if (validate_offset_imm (value, 0) == FAIL)
20502 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20503 as_bad_where (fixP->fx_file, fixP->fx_line,
20504 _("invalid literal constant: pool needs to be closer"));
20506 as_bad_where (fixP->fx_file, fixP->fx_line,
20507 _("bad immediate value for offset (%ld)"),
20512 newval = md_chars_to_number (buf, INSN_SIZE);
20514 newval &= 0xfffff000;
20517 newval &= 0xff7ff000;
20518 newval |= value | (sign ? INDEX_UP : 0);
20520 md_number_to_chars (buf, newval, INSN_SIZE);
20523 case BFD_RELOC_ARM_OFFSET_IMM8:
20524 case BFD_RELOC_ARM_HWLITERAL:
20530 if (validate_offset_imm (value, 1) == FAIL)
20532 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20533 as_bad_where (fixP->fx_file, fixP->fx_line,
20534 _("invalid literal constant: pool needs to be closer"));
20536 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20541 newval = md_chars_to_number (buf, INSN_SIZE);
20543 newval &= 0xfffff0f0;
20546 newval &= 0xff7ff0f0;
20547 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20549 md_number_to_chars (buf, newval, INSN_SIZE);
20552 case BFD_RELOC_ARM_T32_OFFSET_U8:
20553 if (value < 0 || value > 1020 || value % 4 != 0)
20554 as_bad_where (fixP->fx_file, fixP->fx_line,
20555 _("bad immediate value for offset (%ld)"), (long) value);
20558 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20560 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20563 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20564 /* This is a complicated relocation used for all varieties of Thumb32
20565 load/store instruction with immediate offset:
20567 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20568 *4, optional writeback(W)
20569 (doubleword load/store)
20571 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20572 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20573 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20574 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20575 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20577 Uppercase letters indicate bits that are already encoded at
20578 this point. Lowercase letters are our problem. For the
20579 second block of instructions, the secondary opcode nybble
20580 (bits 8..11) is present, and bit 23 is zero, even if this is
20581 a PC-relative operation. */
20582 newval = md_chars_to_number (buf, THUMB_SIZE);
20584 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20586 if ((newval & 0xf0000000) == 0xe0000000)
20588 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20590 newval |= (1 << 23);
20593 if (value % 4 != 0)
20595 as_bad_where (fixP->fx_file, fixP->fx_line,
20596 _("offset not a multiple of 4"));
20602 as_bad_where (fixP->fx_file, fixP->fx_line,
20603 _("offset out of range"));
20608 else if ((newval & 0x000f0000) == 0x000f0000)
20610 /* PC-relative, 12-bit offset. */
20612 newval |= (1 << 23);
20617 as_bad_where (fixP->fx_file, fixP->fx_line,
20618 _("offset out of range"));
20623 else if ((newval & 0x00000100) == 0x00000100)
20625 /* Writeback: 8-bit, +/- offset. */
20627 newval |= (1 << 9);
20632 as_bad_where (fixP->fx_file, fixP->fx_line,
20633 _("offset out of range"));
20638 else if ((newval & 0x00000f00) == 0x00000e00)
20640 /* T-instruction: positive 8-bit offset. */
20641 if (value < 0 || value > 0xff)
20643 as_bad_where (fixP->fx_file, fixP->fx_line,
20644 _("offset out of range"));
20652 /* Positive 12-bit or negative 8-bit offset. */
20656 newval |= (1 << 23);
20666 as_bad_where (fixP->fx_file, fixP->fx_line,
20667 _("offset out of range"));
20674 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20675 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20678 case BFD_RELOC_ARM_SHIFT_IMM:
20679 newval = md_chars_to_number (buf, INSN_SIZE);
20680 if (((unsigned long) value) > 32
20682 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20684 as_bad_where (fixP->fx_file, fixP->fx_line,
20685 _("shift expression is too large"));
20690 /* Shifts of zero must be done as lsl. */
20692 else if (value == 32)
20694 newval &= 0xfffff07f;
20695 newval |= (value & 0x1f) << 7;
20696 md_number_to_chars (buf, newval, INSN_SIZE);
20699 case BFD_RELOC_ARM_T32_IMMEDIATE:
20700 case BFD_RELOC_ARM_T32_ADD_IMM:
20701 case BFD_RELOC_ARM_T32_IMM12:
20702 case BFD_RELOC_ARM_T32_ADD_PC12:
20703 /* We claim that this fixup has been processed here,
20704 even if in fact we generate an error because we do
20705 not have a reloc for it, so tc_gen_reloc will reject it. */
20709 && ! S_IS_DEFINED (fixP->fx_addsy))
20711 as_bad_where (fixP->fx_file, fixP->fx_line,
20712 _("undefined symbol %s used as an immediate value"),
20713 S_GET_NAME (fixP->fx_addsy));
20717 newval = md_chars_to_number (buf, THUMB_SIZE);
20719 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20722 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20723 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20725 newimm = encode_thumb32_immediate (value);
20726 if (newimm == (unsigned int) FAIL)
20727 newimm = thumb32_negate_data_op (&newval, value);
20729 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20730 && newimm == (unsigned int) FAIL)
20732 /* Turn add/sum into addw/subw. */
20733 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20734 newval = (newval & 0xfeffffff) | 0x02000000;
20735 /* No flat 12-bit imm encoding for addsw/subsw. */
20736 if ((newval & 0x00100000) == 0)
20738 /* 12 bit immediate for addw/subw. */
20742 newval ^= 0x00a00000;
20745 newimm = (unsigned int) FAIL;
20751 if (newimm == (unsigned int)FAIL)
20753 as_bad_where (fixP->fx_file, fixP->fx_line,
20754 _("invalid constant (%lx) after fixup"),
20755 (unsigned long) value);
20759 newval |= (newimm & 0x800) << 15;
20760 newval |= (newimm & 0x700) << 4;
20761 newval |= (newimm & 0x0ff);
20763 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
20764 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
20767 case BFD_RELOC_ARM_SMC:
20768 if (((unsigned long) value) > 0xffff)
20769 as_bad_where (fixP->fx_file, fixP->fx_line,
20770 _("invalid smc expression"));
20771 newval = md_chars_to_number (buf, INSN_SIZE);
20772 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20773 md_number_to_chars (buf, newval, INSN_SIZE);
20776 case BFD_RELOC_ARM_HVC:
20777 if (((unsigned long) value) > 0xffff)
20778 as_bad_where (fixP->fx_file, fixP->fx_line,
20779 _("invalid hvc expression"));
20780 newval = md_chars_to_number (buf, INSN_SIZE);
20781 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20782 md_number_to_chars (buf, newval, INSN_SIZE);
20785 case BFD_RELOC_ARM_SWI:
20786 if (fixP->tc_fix_data != 0)
20788 if (((unsigned long) value) > 0xff)
20789 as_bad_where (fixP->fx_file, fixP->fx_line,
20790 _("invalid swi expression"));
20791 newval = md_chars_to_number (buf, THUMB_SIZE);
20793 md_number_to_chars (buf, newval, THUMB_SIZE);
20797 if (((unsigned long) value) > 0x00ffffff)
20798 as_bad_where (fixP->fx_file, fixP->fx_line,
20799 _("invalid swi expression"));
20800 newval = md_chars_to_number (buf, INSN_SIZE);
20802 md_number_to_chars (buf, newval, INSN_SIZE);
20806 case BFD_RELOC_ARM_MULTI:
20807 if (((unsigned long) value) > 0xffff)
20808 as_bad_where (fixP->fx_file, fixP->fx_line,
20809 _("invalid expression in load/store multiple"));
20810 newval = value | md_chars_to_number (buf, INSN_SIZE);
20811 md_number_to_chars (buf, newval, INSN_SIZE);
20815 case BFD_RELOC_ARM_PCREL_CALL:
20817 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20819 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20820 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20821 && THUMB_IS_FUNC (fixP->fx_addsy))
20822 /* Flip the bl to blx. This is a simple flip
20823 bit here because we generate PCREL_CALL for
20824 unconditional bls. */
20826 newval = md_chars_to_number (buf, INSN_SIZE);
20827 newval = newval | 0x10000000;
20828 md_number_to_chars (buf, newval, INSN_SIZE);
20834 goto arm_branch_common;
20836 case BFD_RELOC_ARM_PCREL_JUMP:
20837 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20839 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20840 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20841 && THUMB_IS_FUNC (fixP->fx_addsy))
20843 /* This would map to a bl<cond>, b<cond>,
20844 b<always> to a Thumb function. We
20845 need to force a relocation for this particular
20847 newval = md_chars_to_number (buf, INSN_SIZE);
20851 case BFD_RELOC_ARM_PLT32:
20853 case BFD_RELOC_ARM_PCREL_BRANCH:
20855 goto arm_branch_common;
20857 case BFD_RELOC_ARM_PCREL_BLX:
20860 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20862 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20863 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20864 && ARM_IS_FUNC (fixP->fx_addsy))
20866 /* Flip the blx to a bl and warn. */
20867 const char *name = S_GET_NAME (fixP->fx_addsy);
20868 newval = 0xeb000000;
20869 as_warn_where (fixP->fx_file, fixP->fx_line,
20870 _("blx to '%s' an ARM ISA state function changed to bl"),
20872 md_number_to_chars (buf, newval, INSN_SIZE);
20878 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
20879 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
20883 /* We are going to store value (shifted right by two) in the
20884 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20885 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20886 also be be clear. */
20888 as_bad_where (fixP->fx_file, fixP->fx_line,
20889 _("misaligned branch destination"));
20890 if ((value & (offsetT)0xfe000000) != (offsetT)0
20891 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
20892 as_bad_where (fixP->fx_file, fixP->fx_line,
20893 _("branch out of range"));
20895 if (fixP->fx_done || !seg->use_rela_p)
20897 newval = md_chars_to_number (buf, INSN_SIZE);
20898 newval |= (value >> 2) & 0x00ffffff;
20899 /* Set the H bit on BLX instructions. */
20903 newval |= 0x01000000;
20905 newval &= ~0x01000000;
20907 md_number_to_chars (buf, newval, INSN_SIZE);
20911 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
20912 /* CBZ can only branch forward. */
20914 /* Attempts to use CBZ to branch to the next instruction
20915 (which, strictly speaking, are prohibited) will be turned into
20918 FIXME: It may be better to remove the instruction completely and
20919 perform relaxation. */
20922 newval = md_chars_to_number (buf, THUMB_SIZE);
20923 newval = 0xbf00; /* NOP encoding T1 */
20924 md_number_to_chars (buf, newval, THUMB_SIZE);
20929 as_bad_where (fixP->fx_file, fixP->fx_line,
20930 _("branch out of range"));
20932 if (fixP->fx_done || !seg->use_rela_p)
20934 newval = md_chars_to_number (buf, THUMB_SIZE);
20935 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
20936 md_number_to_chars (buf, newval, THUMB_SIZE);
20941 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
20942 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
20943 as_bad_where (fixP->fx_file, fixP->fx_line,
20944 _("branch out of range"));
20946 if (fixP->fx_done || !seg->use_rela_p)
20948 newval = md_chars_to_number (buf, THUMB_SIZE);
20949 newval |= (value & 0x1ff) >> 1;
20950 md_number_to_chars (buf, newval, THUMB_SIZE);
20954 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
20955 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
20956 as_bad_where (fixP->fx_file, fixP->fx_line,
20957 _("branch out of range"));
20959 if (fixP->fx_done || !seg->use_rela_p)
20961 newval = md_chars_to_number (buf, THUMB_SIZE);
20962 newval |= (value & 0xfff) >> 1;
20963 md_number_to_chars (buf, newval, THUMB_SIZE);
20967 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20969 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20970 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20971 && ARM_IS_FUNC (fixP->fx_addsy)
20972 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20974 /* Force a relocation for a branch 20 bits wide. */
20977 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
20978 as_bad_where (fixP->fx_file, fixP->fx_line,
20979 _("conditional branch out of range"));
20981 if (fixP->fx_done || !seg->use_rela_p)
20984 addressT S, J1, J2, lo, hi;
20986 S = (value & 0x00100000) >> 20;
20987 J2 = (value & 0x00080000) >> 19;
20988 J1 = (value & 0x00040000) >> 18;
20989 hi = (value & 0x0003f000) >> 12;
20990 lo = (value & 0x00000ffe) >> 1;
20992 newval = md_chars_to_number (buf, THUMB_SIZE);
20993 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20994 newval |= (S << 10) | hi;
20995 newval2 |= (J1 << 13) | (J2 << 11) | lo;
20996 md_number_to_chars (buf, newval, THUMB_SIZE);
20997 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21001 case BFD_RELOC_THUMB_PCREL_BLX:
21003 /* If there is a blx from a thumb state function to
21004 another thumb function flip this to a bl and warn
21008 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21009 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21010 && THUMB_IS_FUNC (fixP->fx_addsy))
21012 const char *name = S_GET_NAME (fixP->fx_addsy);
21013 as_warn_where (fixP->fx_file, fixP->fx_line,
21014 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21016 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21017 newval = newval | 0x1000;
21018 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21019 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21024 goto thumb_bl_common;
21026 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21028 /* A bl from Thumb state ISA to an internal ARM state function
21029 is converted to a blx. */
21031 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21032 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21033 && ARM_IS_FUNC (fixP->fx_addsy)
21034 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21036 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21037 newval = newval & ~0x1000;
21038 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21039 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21046 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
21047 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21048 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21051 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21052 /* For a BLX instruction, make sure that the relocation is rounded up
21053 to a word boundary. This follows the semantics of the instruction
21054 which specifies that bit 1 of the target address will come from bit
21055 1 of the base address. */
21056 value = (value + 1) & ~ 1;
21059 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21061 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21063 as_bad_where (fixP->fx_file, fixP->fx_line,
21064 _("branch out of range"));
21066 else if ((value & ~0x1ffffff)
21067 && ((value & ~0x1ffffff) != ~0x1ffffff))
21069 as_bad_where (fixP->fx_file, fixP->fx_line,
21070 _("Thumb2 branch out of range"));
21074 if (fixP->fx_done || !seg->use_rela_p)
21075 encode_thumb2_b_bl_offset (buf, value);
21079 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21080 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
21081 as_bad_where (fixP->fx_file, fixP->fx_line,
21082 _("branch out of range"));
21084 if (fixP->fx_done || !seg->use_rela_p)
21085 encode_thumb2_b_bl_offset (buf, value);
21090 if (fixP->fx_done || !seg->use_rela_p)
21091 md_number_to_chars (buf, value, 1);
21095 if (fixP->fx_done || !seg->use_rela_p)
21096 md_number_to_chars (buf, value, 2);
21100 case BFD_RELOC_ARM_TLS_CALL:
21101 case BFD_RELOC_ARM_THM_TLS_CALL:
21102 case BFD_RELOC_ARM_TLS_DESCSEQ:
21103 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21104 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21107 case BFD_RELOC_ARM_TLS_GOTDESC:
21108 case BFD_RELOC_ARM_TLS_GD32:
21109 case BFD_RELOC_ARM_TLS_LE32:
21110 case BFD_RELOC_ARM_TLS_IE32:
21111 case BFD_RELOC_ARM_TLS_LDM32:
21112 case BFD_RELOC_ARM_TLS_LDO32:
21113 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21116 case BFD_RELOC_ARM_GOT32:
21117 case BFD_RELOC_ARM_GOTOFF:
21118 if (fixP->fx_done || !seg->use_rela_p)
21119 md_number_to_chars (buf, 0, 4);
21122 case BFD_RELOC_ARM_GOT_PREL:
21123 if (fixP->fx_done || !seg->use_rela_p)
21124 md_number_to_chars (buf, value, 4);
21127 case BFD_RELOC_ARM_TARGET2:
21128 /* TARGET2 is not partial-inplace, so we need to write the
21129 addend here for REL targets, because it won't be written out
21130 during reloc processing later. */
21131 if (fixP->fx_done || !seg->use_rela_p)
21132 md_number_to_chars (buf, fixP->fx_offset, 4);
21136 case BFD_RELOC_RVA:
21138 case BFD_RELOC_ARM_TARGET1:
21139 case BFD_RELOC_ARM_ROSEGREL32:
21140 case BFD_RELOC_ARM_SBREL32:
21141 case BFD_RELOC_32_PCREL:
21143 case BFD_RELOC_32_SECREL:
21145 if (fixP->fx_done || !seg->use_rela_p)
21147 /* For WinCE we only do this for pcrel fixups. */
21148 if (fixP->fx_done || fixP->fx_pcrel)
21150 md_number_to_chars (buf, value, 4);
21154 case BFD_RELOC_ARM_PREL31:
21155 if (fixP->fx_done || !seg->use_rela_p)
21157 newval = md_chars_to_number (buf, 4) & 0x80000000;
21158 if ((value ^ (value >> 1)) & 0x40000000)
21160 as_bad_where (fixP->fx_file, fixP->fx_line,
21161 _("rel31 relocation overflow"));
21163 newval |= value & 0x7fffffff;
21164 md_number_to_chars (buf, newval, 4);
21169 case BFD_RELOC_ARM_CP_OFF_IMM:
21170 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21171 if (value < -1023 || value > 1023 || (value & 3))
21172 as_bad_where (fixP->fx_file, fixP->fx_line,
21173 _("co-processor offset out of range"));
21178 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21179 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21180 newval = md_chars_to_number (buf, INSN_SIZE);
21182 newval = get_thumb32_insn (buf);
21184 newval &= 0xffffff00;
21187 newval &= 0xff7fff00;
21188 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21190 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21191 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21192 md_number_to_chars (buf, newval, INSN_SIZE);
21194 put_thumb32_insn (buf, newval);
21197 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21198 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21199 if (value < -255 || value > 255)
21200 as_bad_where (fixP->fx_file, fixP->fx_line,
21201 _("co-processor offset out of range"));
21203 goto cp_off_common;
21205 case BFD_RELOC_ARM_THUMB_OFFSET:
21206 newval = md_chars_to_number (buf, THUMB_SIZE);
21207 /* Exactly what ranges, and where the offset is inserted depends
21208 on the type of instruction, we can establish this from the
21210 switch (newval >> 12)
21212 case 4: /* PC load. */
21213 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21214 forced to zero for these loads; md_pcrel_from has already
21215 compensated for this. */
21217 as_bad_where (fixP->fx_file, fixP->fx_line,
21218 _("invalid offset, target not word aligned (0x%08lX)"),
21219 (((unsigned long) fixP->fx_frag->fr_address
21220 + (unsigned long) fixP->fx_where) & ~3)
21221 + (unsigned long) value);
21223 if (value & ~0x3fc)
21224 as_bad_where (fixP->fx_file, fixP->fx_line,
21225 _("invalid offset, value too big (0x%08lX)"),
21228 newval |= value >> 2;
21231 case 9: /* SP load/store. */
21232 if (value & ~0x3fc)
21233 as_bad_where (fixP->fx_file, fixP->fx_line,
21234 _("invalid offset, value too big (0x%08lX)"),
21236 newval |= value >> 2;
21239 case 6: /* Word load/store. */
21241 as_bad_where (fixP->fx_file, fixP->fx_line,
21242 _("invalid offset, value too big (0x%08lX)"),
21244 newval |= value << 4; /* 6 - 2. */
21247 case 7: /* Byte load/store. */
21249 as_bad_where (fixP->fx_file, fixP->fx_line,
21250 _("invalid offset, value too big (0x%08lX)"),
21252 newval |= value << 6;
21255 case 8: /* Halfword load/store. */
21257 as_bad_where (fixP->fx_file, fixP->fx_line,
21258 _("invalid offset, value too big (0x%08lX)"),
21260 newval |= value << 5; /* 6 - 1. */
21264 as_bad_where (fixP->fx_file, fixP->fx_line,
21265 "Unable to process relocation for thumb opcode: %lx",
21266 (unsigned long) newval);
21269 md_number_to_chars (buf, newval, THUMB_SIZE);
21272 case BFD_RELOC_ARM_THUMB_ADD:
21273 /* This is a complicated relocation, since we use it for all of
21274 the following immediate relocations:
21278 9bit ADD/SUB SP word-aligned
21279 10bit ADD PC/SP word-aligned
21281 The type of instruction being processed is encoded in the
21288 newval = md_chars_to_number (buf, THUMB_SIZE);
21290 int rd = (newval >> 4) & 0xf;
21291 int rs = newval & 0xf;
21292 int subtract = !!(newval & 0x8000);
21294 /* Check for HI regs, only very restricted cases allowed:
21295 Adjusting SP, and using PC or SP to get an address. */
21296 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21297 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21298 as_bad_where (fixP->fx_file, fixP->fx_line,
21299 _("invalid Hi register with immediate"));
21301 /* If value is negative, choose the opposite instruction. */
21305 subtract = !subtract;
21307 as_bad_where (fixP->fx_file, fixP->fx_line,
21308 _("immediate value out of range"));
21313 if (value & ~0x1fc)
21314 as_bad_where (fixP->fx_file, fixP->fx_line,
21315 _("invalid immediate for stack address calculation"));
21316 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21317 newval |= value >> 2;
21319 else if (rs == REG_PC || rs == REG_SP)
21321 if (subtract || value & ~0x3fc)
21322 as_bad_where (fixP->fx_file, fixP->fx_line,
21323 _("invalid immediate for address calculation (value = 0x%08lX)"),
21324 (unsigned long) value);
21325 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21327 newval |= value >> 2;
21332 as_bad_where (fixP->fx_file, fixP->fx_line,
21333 _("immediate value out of range"));
21334 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21335 newval |= (rd << 8) | value;
21340 as_bad_where (fixP->fx_file, fixP->fx_line,
21341 _("immediate value out of range"));
21342 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21343 newval |= rd | (rs << 3) | (value << 6);
21346 md_number_to_chars (buf, newval, THUMB_SIZE);
21349 case BFD_RELOC_ARM_THUMB_IMM:
21350 newval = md_chars_to_number (buf, THUMB_SIZE);
21351 if (value < 0 || value > 255)
21352 as_bad_where (fixP->fx_file, fixP->fx_line,
21353 _("invalid immediate: %ld is out of range"),
21356 md_number_to_chars (buf, newval, THUMB_SIZE);
21359 case BFD_RELOC_ARM_THUMB_SHIFT:
21360 /* 5bit shift value (0..32). LSL cannot take 32. */
21361 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21362 temp = newval & 0xf800;
21363 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21364 as_bad_where (fixP->fx_file, fixP->fx_line,
21365 _("invalid shift value: %ld"), (long) value);
21366 /* Shifts of zero must be encoded as LSL. */
21368 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21369 /* Shifts of 32 are encoded as zero. */
21370 else if (value == 32)
21372 newval |= value << 6;
21373 md_number_to_chars (buf, newval, THUMB_SIZE);
21376 case BFD_RELOC_VTABLE_INHERIT:
21377 case BFD_RELOC_VTABLE_ENTRY:
21381 case BFD_RELOC_ARM_MOVW:
21382 case BFD_RELOC_ARM_MOVT:
21383 case BFD_RELOC_ARM_THUMB_MOVW:
21384 case BFD_RELOC_ARM_THUMB_MOVT:
21385 if (fixP->fx_done || !seg->use_rela_p)
21387 /* REL format relocations are limited to a 16-bit addend. */
21388 if (!fixP->fx_done)
21390 if (value < -0x8000 || value > 0x7fff)
21391 as_bad_where (fixP->fx_file, fixP->fx_line,
21392 _("offset out of range"));
21394 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21395 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21400 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21401 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21403 newval = get_thumb32_insn (buf);
21404 newval &= 0xfbf08f00;
21405 newval |= (value & 0xf000) << 4;
21406 newval |= (value & 0x0800) << 15;
21407 newval |= (value & 0x0700) << 4;
21408 newval |= (value & 0x00ff);
21409 put_thumb32_insn (buf, newval);
21413 newval = md_chars_to_number (buf, 4);
21414 newval &= 0xfff0f000;
21415 newval |= value & 0x0fff;
21416 newval |= (value & 0xf000) << 4;
21417 md_number_to_chars (buf, newval, 4);
21422 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21423 case BFD_RELOC_ARM_ALU_PC_G0:
21424 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21425 case BFD_RELOC_ARM_ALU_PC_G1:
21426 case BFD_RELOC_ARM_ALU_PC_G2:
21427 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21428 case BFD_RELOC_ARM_ALU_SB_G0:
21429 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21430 case BFD_RELOC_ARM_ALU_SB_G1:
21431 case BFD_RELOC_ARM_ALU_SB_G2:
21432 gas_assert (!fixP->fx_done);
21433 if (!seg->use_rela_p)
21436 bfd_vma encoded_addend;
21437 bfd_vma addend_abs = abs (value);
21439 /* Check that the absolute value of the addend can be
21440 expressed as an 8-bit constant plus a rotation. */
21441 encoded_addend = encode_arm_immediate (addend_abs);
21442 if (encoded_addend == (unsigned int) FAIL)
21443 as_bad_where (fixP->fx_file, fixP->fx_line,
21444 _("the offset 0x%08lX is not representable"),
21445 (unsigned long) addend_abs);
21447 /* Extract the instruction. */
21448 insn = md_chars_to_number (buf, INSN_SIZE);
21450 /* If the addend is positive, use an ADD instruction.
21451 Otherwise use a SUB. Take care not to destroy the S bit. */
21452 insn &= 0xff1fffff;
21458 /* Place the encoded addend into the first 12 bits of the
21460 insn &= 0xfffff000;
21461 insn |= encoded_addend;
21463 /* Update the instruction. */
21464 md_number_to_chars (buf, insn, INSN_SIZE);
21468 case BFD_RELOC_ARM_LDR_PC_G0:
21469 case BFD_RELOC_ARM_LDR_PC_G1:
21470 case BFD_RELOC_ARM_LDR_PC_G2:
21471 case BFD_RELOC_ARM_LDR_SB_G0:
21472 case BFD_RELOC_ARM_LDR_SB_G1:
21473 case BFD_RELOC_ARM_LDR_SB_G2:
21474 gas_assert (!fixP->fx_done);
21475 if (!seg->use_rela_p)
21478 bfd_vma addend_abs = abs (value);
21480 /* Check that the absolute value of the addend can be
21481 encoded in 12 bits. */
21482 if (addend_abs >= 0x1000)
21483 as_bad_where (fixP->fx_file, fixP->fx_line,
21484 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21485 (unsigned long) addend_abs);
21487 /* Extract the instruction. */
21488 insn = md_chars_to_number (buf, INSN_SIZE);
21490 /* If the addend is negative, clear bit 23 of the instruction.
21491 Otherwise set it. */
21493 insn &= ~(1 << 23);
21497 /* Place the absolute value of the addend into the first 12 bits
21498 of the instruction. */
21499 insn &= 0xfffff000;
21500 insn |= addend_abs;
21502 /* Update the instruction. */
21503 md_number_to_chars (buf, insn, INSN_SIZE);
21507 case BFD_RELOC_ARM_LDRS_PC_G0:
21508 case BFD_RELOC_ARM_LDRS_PC_G1:
21509 case BFD_RELOC_ARM_LDRS_PC_G2:
21510 case BFD_RELOC_ARM_LDRS_SB_G0:
21511 case BFD_RELOC_ARM_LDRS_SB_G1:
21512 case BFD_RELOC_ARM_LDRS_SB_G2:
21513 gas_assert (!fixP->fx_done);
21514 if (!seg->use_rela_p)
21517 bfd_vma addend_abs = abs (value);
21519 /* Check that the absolute value of the addend can be
21520 encoded in 8 bits. */
21521 if (addend_abs >= 0x100)
21522 as_bad_where (fixP->fx_file, fixP->fx_line,
21523 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21524 (unsigned long) addend_abs);
21526 /* Extract the instruction. */
21527 insn = md_chars_to_number (buf, INSN_SIZE);
21529 /* If the addend is negative, clear bit 23 of the instruction.
21530 Otherwise set it. */
21532 insn &= ~(1 << 23);
21536 /* Place the first four bits of the absolute value of the addend
21537 into the first 4 bits of the instruction, and the remaining
21538 four into bits 8 .. 11. */
21539 insn &= 0xfffff0f0;
21540 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21542 /* Update the instruction. */
21543 md_number_to_chars (buf, insn, INSN_SIZE);
21547 case BFD_RELOC_ARM_LDC_PC_G0:
21548 case BFD_RELOC_ARM_LDC_PC_G1:
21549 case BFD_RELOC_ARM_LDC_PC_G2:
21550 case BFD_RELOC_ARM_LDC_SB_G0:
21551 case BFD_RELOC_ARM_LDC_SB_G1:
21552 case BFD_RELOC_ARM_LDC_SB_G2:
21553 gas_assert (!fixP->fx_done);
21554 if (!seg->use_rela_p)
21557 bfd_vma addend_abs = abs (value);
21559 /* Check that the absolute value of the addend is a multiple of
21560 four and, when divided by four, fits in 8 bits. */
21561 if (addend_abs & 0x3)
21562 as_bad_where (fixP->fx_file, fixP->fx_line,
21563 _("bad offset 0x%08lX (must be word-aligned)"),
21564 (unsigned long) addend_abs);
21566 if ((addend_abs >> 2) > 0xff)
21567 as_bad_where (fixP->fx_file, fixP->fx_line,
21568 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21569 (unsigned long) addend_abs);
21571 /* Extract the instruction. */
21572 insn = md_chars_to_number (buf, INSN_SIZE);
21574 /* If the addend is negative, clear bit 23 of the instruction.
21575 Otherwise set it. */
21577 insn &= ~(1 << 23);
21581 /* Place the addend (divided by four) into the first eight
21582 bits of the instruction. */
21583 insn &= 0xfffffff0;
21584 insn |= addend_abs >> 2;
21586 /* Update the instruction. */
21587 md_number_to_chars (buf, insn, INSN_SIZE);
21591 case BFD_RELOC_ARM_V4BX:
21592 /* This will need to go in the object file. */
21596 case BFD_RELOC_UNUSED:
21598 as_bad_where (fixP->fx_file, fixP->fx_line,
21599 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21603 /* Translate internal representation of relocation info to BFD target
21607 tc_gen_reloc (asection *section, fixS *fixp)
21610 bfd_reloc_code_real_type code;
21612 reloc = (arelent *) xmalloc (sizeof (arelent));
21614 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21615 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21616 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21618 if (fixp->fx_pcrel)
21620 if (section->use_rela_p)
21621 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21623 fixp->fx_offset = reloc->address;
21625 reloc->addend = fixp->fx_offset;
21627 switch (fixp->fx_r_type)
21630 if (fixp->fx_pcrel)
21632 code = BFD_RELOC_8_PCREL;
21637 if (fixp->fx_pcrel)
21639 code = BFD_RELOC_16_PCREL;
21644 if (fixp->fx_pcrel)
21646 code = BFD_RELOC_32_PCREL;
21650 case BFD_RELOC_ARM_MOVW:
21651 if (fixp->fx_pcrel)
21653 code = BFD_RELOC_ARM_MOVW_PCREL;
21657 case BFD_RELOC_ARM_MOVT:
21658 if (fixp->fx_pcrel)
21660 code = BFD_RELOC_ARM_MOVT_PCREL;
21664 case BFD_RELOC_ARM_THUMB_MOVW:
21665 if (fixp->fx_pcrel)
21667 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21671 case BFD_RELOC_ARM_THUMB_MOVT:
21672 if (fixp->fx_pcrel)
21674 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21678 case BFD_RELOC_NONE:
21679 case BFD_RELOC_ARM_PCREL_BRANCH:
21680 case BFD_RELOC_ARM_PCREL_BLX:
21681 case BFD_RELOC_RVA:
21682 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21683 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21684 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21685 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21686 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21687 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21688 case BFD_RELOC_VTABLE_ENTRY:
21689 case BFD_RELOC_VTABLE_INHERIT:
21691 case BFD_RELOC_32_SECREL:
21693 code = fixp->fx_r_type;
21696 case BFD_RELOC_THUMB_PCREL_BLX:
21698 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21699 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21702 code = BFD_RELOC_THUMB_PCREL_BLX;
21705 case BFD_RELOC_ARM_LITERAL:
21706 case BFD_RELOC_ARM_HWLITERAL:
21707 /* If this is called then the a literal has
21708 been referenced across a section boundary. */
21709 as_bad_where (fixp->fx_file, fixp->fx_line,
21710 _("literal referenced across section boundary"));
21714 case BFD_RELOC_ARM_TLS_CALL:
21715 case BFD_RELOC_ARM_THM_TLS_CALL:
21716 case BFD_RELOC_ARM_TLS_DESCSEQ:
21717 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21718 case BFD_RELOC_ARM_GOT32:
21719 case BFD_RELOC_ARM_GOTOFF:
21720 case BFD_RELOC_ARM_GOT_PREL:
21721 case BFD_RELOC_ARM_PLT32:
21722 case BFD_RELOC_ARM_TARGET1:
21723 case BFD_RELOC_ARM_ROSEGREL32:
21724 case BFD_RELOC_ARM_SBREL32:
21725 case BFD_RELOC_ARM_PREL31:
21726 case BFD_RELOC_ARM_TARGET2:
21727 case BFD_RELOC_ARM_TLS_LE32:
21728 case BFD_RELOC_ARM_TLS_LDO32:
21729 case BFD_RELOC_ARM_PCREL_CALL:
21730 case BFD_RELOC_ARM_PCREL_JUMP:
21731 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21732 case BFD_RELOC_ARM_ALU_PC_G0:
21733 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21734 case BFD_RELOC_ARM_ALU_PC_G1:
21735 case BFD_RELOC_ARM_ALU_PC_G2:
21736 case BFD_RELOC_ARM_LDR_PC_G0:
21737 case BFD_RELOC_ARM_LDR_PC_G1:
21738 case BFD_RELOC_ARM_LDR_PC_G2:
21739 case BFD_RELOC_ARM_LDRS_PC_G0:
21740 case BFD_RELOC_ARM_LDRS_PC_G1:
21741 case BFD_RELOC_ARM_LDRS_PC_G2:
21742 case BFD_RELOC_ARM_LDC_PC_G0:
21743 case BFD_RELOC_ARM_LDC_PC_G1:
21744 case BFD_RELOC_ARM_LDC_PC_G2:
21745 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21746 case BFD_RELOC_ARM_ALU_SB_G0:
21747 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21748 case BFD_RELOC_ARM_ALU_SB_G1:
21749 case BFD_RELOC_ARM_ALU_SB_G2:
21750 case BFD_RELOC_ARM_LDR_SB_G0:
21751 case BFD_RELOC_ARM_LDR_SB_G1:
21752 case BFD_RELOC_ARM_LDR_SB_G2:
21753 case BFD_RELOC_ARM_LDRS_SB_G0:
21754 case BFD_RELOC_ARM_LDRS_SB_G1:
21755 case BFD_RELOC_ARM_LDRS_SB_G2:
21756 case BFD_RELOC_ARM_LDC_SB_G0:
21757 case BFD_RELOC_ARM_LDC_SB_G1:
21758 case BFD_RELOC_ARM_LDC_SB_G2:
21759 case BFD_RELOC_ARM_V4BX:
21760 code = fixp->fx_r_type;
21763 case BFD_RELOC_ARM_TLS_GOTDESC:
21764 case BFD_RELOC_ARM_TLS_GD32:
21765 case BFD_RELOC_ARM_TLS_IE32:
21766 case BFD_RELOC_ARM_TLS_LDM32:
21767 /* BFD will include the symbol's address in the addend.
21768 But we don't want that, so subtract it out again here. */
21769 if (!S_IS_COMMON (fixp->fx_addsy))
21770 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21771 code = fixp->fx_r_type;
21775 case BFD_RELOC_ARM_IMMEDIATE:
21776 as_bad_where (fixp->fx_file, fixp->fx_line,
21777 _("internal relocation (type: IMMEDIATE) not fixed up"));
21780 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21781 as_bad_where (fixp->fx_file, fixp->fx_line,
21782 _("ADRL used for a symbol not defined in the same file"));
21785 case BFD_RELOC_ARM_OFFSET_IMM:
21786 if (section->use_rela_p)
21788 code = fixp->fx_r_type;
21792 if (fixp->fx_addsy != NULL
21793 && !S_IS_DEFINED (fixp->fx_addsy)
21794 && S_IS_LOCAL (fixp->fx_addsy))
21796 as_bad_where (fixp->fx_file, fixp->fx_line,
21797 _("undefined local label `%s'"),
21798 S_GET_NAME (fixp->fx_addsy));
21802 as_bad_where (fixp->fx_file, fixp->fx_line,
21803 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21810 switch (fixp->fx_r_type)
21812 case BFD_RELOC_NONE: type = "NONE"; break;
21813 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
21814 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
21815 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
21816 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
21817 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
21818 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
21819 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
21820 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
21821 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
21822 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
21823 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
21824 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
21825 default: type = _("<unknown>"); break;
21827 as_bad_where (fixp->fx_file, fixp->fx_line,
21828 _("cannot represent %s relocation in this object file format"),
21835 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
21837 && fixp->fx_addsy == GOT_symbol)
21839 code = BFD_RELOC_ARM_GOTPC;
21840 reloc->addend = fixp->fx_offset = reloc->address;
21844 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
21846 if (reloc->howto == NULL)
21848 as_bad_where (fixp->fx_file, fixp->fx_line,
21849 _("cannot represent %s relocation in this object file format"),
21850 bfd_get_reloc_code_name (code));
21854 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21855 vtable entry to be used in the relocation's section offset. */
21856 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
21857 reloc->address = fixp->fx_offset;
21862 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21865 cons_fix_new_arm (fragS * frag,
21870 bfd_reloc_code_real_type type;
21874 FIXME: @@ Should look at CPU word size. */
21878 type = BFD_RELOC_8;
21881 type = BFD_RELOC_16;
21885 type = BFD_RELOC_32;
21888 type = BFD_RELOC_64;
21893 if (exp->X_op == O_secrel)
21895 exp->X_op = O_symbol;
21896 type = BFD_RELOC_32_SECREL;
21900 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
21903 #if defined (OBJ_COFF)
21905 arm_validate_fix (fixS * fixP)
21907 /* If the destination of the branch is a defined symbol which does not have
21908 the THUMB_FUNC attribute, then we must be calling a function which has
21909 the (interfacearm) attribute. We look for the Thumb entry point to that
21910 function and change the branch to refer to that function instead. */
21911 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
21912 && fixP->fx_addsy != NULL
21913 && S_IS_DEFINED (fixP->fx_addsy)
21914 && ! THUMB_IS_FUNC (fixP->fx_addsy))
21916 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
21923 arm_force_relocation (struct fix * fixp)
21925 #if defined (OBJ_COFF) && defined (TE_PE)
21926 if (fixp->fx_r_type == BFD_RELOC_RVA)
21930 /* In case we have a call or a branch to a function in ARM ISA mode from
21931 a thumb function or vice-versa force the relocation. These relocations
21932 are cleared off for some cores that might have blx and simple transformations
21936 switch (fixp->fx_r_type)
21938 case BFD_RELOC_ARM_PCREL_JUMP:
21939 case BFD_RELOC_ARM_PCREL_CALL:
21940 case BFD_RELOC_THUMB_PCREL_BLX:
21941 if (THUMB_IS_FUNC (fixp->fx_addsy))
21945 case BFD_RELOC_ARM_PCREL_BLX:
21946 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21947 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21948 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21949 if (ARM_IS_FUNC (fixp->fx_addsy))
21958 /* Resolve these relocations even if the symbol is extern or weak.
21959 Technically this is probably wrong due to symbol preemption.
21960 In practice these relocations do not have enough range to be useful
21961 at dynamic link time, and some code (e.g. in the Linux kernel)
21962 expects these references to be resolved. */
21963 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
21964 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
21965 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
21966 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
21967 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21968 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
21969 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
21970 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
21971 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21972 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
21973 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
21974 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
21975 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
21976 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
21979 /* Always leave these relocations for the linker. */
21980 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
21981 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
21982 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
21985 /* Always generate relocations against function symbols. */
21986 if (fixp->fx_r_type == BFD_RELOC_32
21988 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
21991 return generic_force_reloc (fixp);
21994 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21995 /* Relocations against function names must be left unadjusted,
21996 so that the linker can use this information to generate interworking
21997 stubs. The MIPS version of this function
21998 also prevents relocations that are mips-16 specific, but I do not
21999 know why it does this.
22002 There is one other problem that ought to be addressed here, but
22003 which currently is not: Taking the address of a label (rather
22004 than a function) and then later jumping to that address. Such
22005 addresses also ought to have their bottom bit set (assuming that
22006 they reside in Thumb code), but at the moment they will not. */
22009 arm_fix_adjustable (fixS * fixP)
22011 if (fixP->fx_addsy == NULL)
22014 /* Preserve relocations against symbols with function type. */
22015 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22018 if (THUMB_IS_FUNC (fixP->fx_addsy)
22019 && fixP->fx_subsy == NULL)
22022 /* We need the symbol name for the VTABLE entries. */
22023 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22024 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22027 /* Don't allow symbols to be discarded on GOT related relocs. */
22028 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22029 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22030 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22031 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22032 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22033 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22034 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22035 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22036 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22037 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22038 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22039 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22040 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22041 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22044 /* Similarly for group relocations. */
22045 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22046 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22047 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22050 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22051 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22052 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22053 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22054 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22055 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22056 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22057 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22058 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22063 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22068 elf32_arm_target_format (void)
22071 return (target_big_endian
22072 ? "elf32-bigarm-symbian"
22073 : "elf32-littlearm-symbian");
22074 #elif defined (TE_VXWORKS)
22075 return (target_big_endian
22076 ? "elf32-bigarm-vxworks"
22077 : "elf32-littlearm-vxworks");
22079 if (target_big_endian)
22080 return "elf32-bigarm";
22082 return "elf32-littlearm";
22087 armelf_frob_symbol (symbolS * symp,
22090 elf_frob_symbol (symp, puntp);
22094 /* MD interface: Finalization. */
22099 literal_pool * pool;
22101 /* Ensure that all the IT blocks are properly closed. */
22102 check_it_blocks_finished ();
22104 for (pool = list_of_pools; pool; pool = pool->next)
22106 /* Put it at the end of the relevant section. */
22107 subseg_set (pool->section, pool->sub_section);
22109 arm_elf_change_section ();
22116 /* Remove any excess mapping symbols generated for alignment frags in
22117 SEC. We may have created a mapping symbol before a zero byte
22118 alignment; remove it if there's a mapping symbol after the
22121 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22122 void *dummy ATTRIBUTE_UNUSED)
22124 segment_info_type *seginfo = seg_info (sec);
22127 if (seginfo == NULL || seginfo->frchainP == NULL)
22130 for (fragp = seginfo->frchainP->frch_root;
22132 fragp = fragp->fr_next)
22134 symbolS *sym = fragp->tc_frag_data.last_map;
22135 fragS *next = fragp->fr_next;
22137 /* Variable-sized frags have been converted to fixed size by
22138 this point. But if this was variable-sized to start with,
22139 there will be a fixed-size frag after it. So don't handle
22141 if (sym == NULL || next == NULL)
22144 if (S_GET_VALUE (sym) < next->fr_address)
22145 /* Not at the end of this frag. */
22147 know (S_GET_VALUE (sym) == next->fr_address);
22151 if (next->tc_frag_data.first_map != NULL)
22153 /* Next frag starts with a mapping symbol. Discard this
22155 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22159 if (next->fr_next == NULL)
22161 /* This mapping symbol is at the end of the section. Discard
22163 know (next->fr_fix == 0 && next->fr_var == 0);
22164 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22168 /* As long as we have empty frags without any mapping symbols,
22170 /* If the next frag is non-empty and does not start with a
22171 mapping symbol, then this mapping symbol is required. */
22172 if (next->fr_address != next->fr_next->fr_address)
22175 next = next->fr_next;
22177 while (next != NULL);
22182 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22186 arm_adjust_symtab (void)
22191 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22193 if (ARM_IS_THUMB (sym))
22195 if (THUMB_IS_FUNC (sym))
22197 /* Mark the symbol as a Thumb function. */
22198 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22199 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22200 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22202 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22203 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22205 as_bad (_("%s: unexpected function type: %d"),
22206 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22208 else switch (S_GET_STORAGE_CLASS (sym))
22211 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22214 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22217 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22225 if (ARM_IS_INTERWORK (sym))
22226 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22233 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22235 if (ARM_IS_THUMB (sym))
22237 elf_symbol_type * elf_sym;
22239 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22240 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22242 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22243 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22245 /* If it's a .thumb_func, declare it as so,
22246 otherwise tag label as .code 16. */
22247 if (THUMB_IS_FUNC (sym))
22248 elf_sym->internal_elf_sym.st_target_internal
22249 = ST_BRANCH_TO_THUMB;
22250 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22251 elf_sym->internal_elf_sym.st_info =
22252 ELF_ST_INFO (bind, STT_ARM_16BIT);
22257 /* Remove any overlapping mapping symbols generated by alignment frags. */
22258 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22259 /* Now do generic ELF adjustments. */
22260 elf_adjust_symtab ();
22264 /* MD interface: Initialization. */
22267 set_constant_flonums (void)
22271 for (i = 0; i < NUM_FLOAT_VALS; i++)
22272 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22276 /* Auto-select Thumb mode if it's the only available instruction set for the
22277 given architecture. */
22280 autoselect_thumb_from_cpu_variant (void)
22282 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22283 opcode_select (16);
22292 if ( (arm_ops_hsh = hash_new ()) == NULL
22293 || (arm_cond_hsh = hash_new ()) == NULL
22294 || (arm_shift_hsh = hash_new ()) == NULL
22295 || (arm_psr_hsh = hash_new ()) == NULL
22296 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22297 || (arm_reg_hsh = hash_new ()) == NULL
22298 || (arm_reloc_hsh = hash_new ()) == NULL
22299 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22300 as_fatal (_("virtual memory exhausted"));
22302 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22303 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22304 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22305 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22306 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22307 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22308 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22309 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22310 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22311 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22312 (void *) (v7m_psrs + i));
22313 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22314 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22316 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22318 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22319 (void *) (barrier_opt_names + i));
22321 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
22322 hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i));
22325 set_constant_flonums ();
22327 /* Set the cpu variant based on the command-line options. We prefer
22328 -mcpu= over -march= if both are set (as for GCC); and we prefer
22329 -mfpu= over any other way of setting the floating point unit.
22330 Use of legacy options with new options are faulted. */
22333 if (mcpu_cpu_opt || march_cpu_opt)
22334 as_bad (_("use of old and new-style options to set CPU type"));
22336 mcpu_cpu_opt = legacy_cpu;
22338 else if (!mcpu_cpu_opt)
22339 mcpu_cpu_opt = march_cpu_opt;
22344 as_bad (_("use of old and new-style options to set FPU type"));
22346 mfpu_opt = legacy_fpu;
22348 else if (!mfpu_opt)
22350 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22351 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22352 /* Some environments specify a default FPU. If they don't, infer it
22353 from the processor. */
22355 mfpu_opt = mcpu_fpu_opt;
22357 mfpu_opt = march_fpu_opt;
22359 mfpu_opt = &fpu_default;
22365 if (mcpu_cpu_opt != NULL)
22366 mfpu_opt = &fpu_default;
22367 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22368 mfpu_opt = &fpu_arch_vfp_v2;
22370 mfpu_opt = &fpu_arch_fpa;
22376 mcpu_cpu_opt = &cpu_default;
22377 selected_cpu = cpu_default;
22381 selected_cpu = *mcpu_cpu_opt;
22383 mcpu_cpu_opt = &arm_arch_any;
22386 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22388 autoselect_thumb_from_cpu_variant ();
22390 arm_arch_used = thumb_arch_used = arm_arch_none;
22392 #if defined OBJ_COFF || defined OBJ_ELF
22394 unsigned int flags = 0;
22396 #if defined OBJ_ELF
22397 flags = meabi_flags;
22399 switch (meabi_flags)
22401 case EF_ARM_EABI_UNKNOWN:
22403 /* Set the flags in the private structure. */
22404 if (uses_apcs_26) flags |= F_APCS26;
22405 if (support_interwork) flags |= F_INTERWORK;
22406 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22407 if (pic_code) flags |= F_PIC;
22408 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22409 flags |= F_SOFT_FLOAT;
22411 switch (mfloat_abi_opt)
22413 case ARM_FLOAT_ABI_SOFT:
22414 case ARM_FLOAT_ABI_SOFTFP:
22415 flags |= F_SOFT_FLOAT;
22418 case ARM_FLOAT_ABI_HARD:
22419 if (flags & F_SOFT_FLOAT)
22420 as_bad (_("hard-float conflicts with specified fpu"));
22424 /* Using pure-endian doubles (even if soft-float). */
22425 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22426 flags |= F_VFP_FLOAT;
22428 #if defined OBJ_ELF
22429 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22430 flags |= EF_ARM_MAVERICK_FLOAT;
22433 case EF_ARM_EABI_VER4:
22434 case EF_ARM_EABI_VER5:
22435 /* No additional flags to set. */
22442 bfd_set_private_flags (stdoutput, flags);
22444 /* We have run out flags in the COFF header to encode the
22445 status of ATPCS support, so instead we create a dummy,
22446 empty, debug section called .arm.atpcs. */
22451 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22455 bfd_set_section_flags
22456 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22457 bfd_set_section_size (stdoutput, sec, 0);
22458 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22464 /* Record the CPU type as well. */
22465 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22466 mach = bfd_mach_arm_iWMMXt2;
22467 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22468 mach = bfd_mach_arm_iWMMXt;
22469 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22470 mach = bfd_mach_arm_XScale;
22471 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22472 mach = bfd_mach_arm_ep9312;
22473 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22474 mach = bfd_mach_arm_5TE;
22475 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22477 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22478 mach = bfd_mach_arm_5T;
22480 mach = bfd_mach_arm_5;
22482 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22484 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22485 mach = bfd_mach_arm_4T;
22487 mach = bfd_mach_arm_4;
22489 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22490 mach = bfd_mach_arm_3M;
22491 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22492 mach = bfd_mach_arm_3;
22493 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22494 mach = bfd_mach_arm_2a;
22495 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22496 mach = bfd_mach_arm_2;
22498 mach = bfd_mach_arm_unknown;
22500 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22503 /* Command line processing. */
22506 Invocation line includes a switch not recognized by the base assembler.
22507 See if it's a processor-specific option.
22509 This routine is somewhat complicated by the need for backwards
22510 compatibility (since older releases of gcc can't be changed).
22511 The new options try to make the interface as compatible as
22514 New options (supported) are:
22516 -mcpu=<cpu name> Assemble for selected processor
22517 -march=<architecture name> Assemble for selected architecture
22518 -mfpu=<fpu architecture> Assemble for selected FPU.
22519 -EB/-mbig-endian Big-endian
22520 -EL/-mlittle-endian Little-endian
22521 -k Generate PIC code
22522 -mthumb Start in Thumb mode
22523 -mthumb-interwork Code supports ARM/Thumb interworking
22525 -m[no-]warn-deprecated Warn about deprecated features
22527 For now we will also provide support for:
22529 -mapcs-32 32-bit Program counter
22530 -mapcs-26 26-bit Program counter
22531 -macps-float Floats passed in FP registers
22532 -mapcs-reentrant Reentrant code
22534 (sometime these will probably be replaced with -mapcs=<list of options>
22535 and -matpcs=<list of options>)
22537 The remaining options are only supported for back-wards compatibility.
22538 Cpu variants, the arm part is optional:
22539 -m[arm]1 Currently not supported.
22540 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22541 -m[arm]3 Arm 3 processor
22542 -m[arm]6[xx], Arm 6 processors
22543 -m[arm]7[xx][t][[d]m] Arm 7 processors
22544 -m[arm]8[10] Arm 8 processors
22545 -m[arm]9[20][tdmi] Arm 9 processors
22546 -mstrongarm[110[0]] StrongARM processors
22547 -mxscale XScale processors
22548 -m[arm]v[2345[t[e]]] Arm architectures
22549 -mall All (except the ARM1)
22551 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22552 -mfpe-old (No float load/store multiples)
22553 -mvfpxd VFP Single precision
22555 -mno-fpu Disable all floating point instructions
22557 The following CPU names are recognized:
22558 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22559 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22560 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22561 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22562 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22563 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22564 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22568 const char * md_shortopts = "m:k";
22570 #ifdef ARM_BI_ENDIAN
22571 #define OPTION_EB (OPTION_MD_BASE + 0)
22572 #define OPTION_EL (OPTION_MD_BASE + 1)
22574 #if TARGET_BYTES_BIG_ENDIAN
22575 #define OPTION_EB (OPTION_MD_BASE + 0)
22577 #define OPTION_EL (OPTION_MD_BASE + 1)
22580 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22582 struct option md_longopts[] =
22585 {"EB", no_argument, NULL, OPTION_EB},
22588 {"EL", no_argument, NULL, OPTION_EL},
22590 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22591 {NULL, no_argument, NULL, 0}
22594 size_t md_longopts_size = sizeof (md_longopts);
22596 struct arm_option_table
22598 char *option; /* Option name to match. */
22599 char *help; /* Help information. */
22600 int *var; /* Variable to change. */
22601 int value; /* What to change it to. */
22602 char *deprecated; /* If non-null, print this message. */
22605 struct arm_option_table arm_opts[] =
22607 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22608 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22609 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22610 &support_interwork, 1, NULL},
22611 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22612 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22613 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22615 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22616 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22617 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22618 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22621 /* These are recognized by the assembler, but have no affect on code. */
22622 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22623 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22625 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22626 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22627 &warn_on_deprecated, 0, NULL},
22628 {NULL, NULL, NULL, 0, NULL}
22631 struct arm_legacy_option_table
22633 char *option; /* Option name to match. */
22634 const arm_feature_set **var; /* Variable to change. */
22635 const arm_feature_set value; /* What to change it to. */
22636 char *deprecated; /* If non-null, print this message. */
22639 const struct arm_legacy_option_table arm_legacy_opts[] =
22641 /* DON'T add any new processors to this list -- we want the whole list
22642 to go away... Add them to the processors table instead. */
22643 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22644 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22645 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22646 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22647 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22648 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22649 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22650 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22651 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22652 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22653 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22654 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22655 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22656 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22657 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22658 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22659 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22660 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22661 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22662 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22663 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22664 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22665 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22666 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22667 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22668 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22669 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22670 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22671 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22672 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22673 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22674 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22675 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22676 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22677 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22678 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22679 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22680 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22681 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22682 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22683 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22684 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22685 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22686 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22687 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22688 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22689 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22690 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22691 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22692 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22693 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22694 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22695 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22696 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22697 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22698 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22699 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22700 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22701 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22702 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22703 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22704 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22705 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22706 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22707 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22708 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22709 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22710 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22711 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22712 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22713 N_("use -mcpu=strongarm110")},
22714 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22715 N_("use -mcpu=strongarm1100")},
22716 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22717 N_("use -mcpu=strongarm1110")},
22718 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22719 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22720 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22722 /* Architecture variants -- don't add any more to this list either. */
22723 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22724 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22725 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22726 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22727 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22728 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22729 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22730 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22731 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22732 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22733 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22734 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22735 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22736 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22737 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22738 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22739 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22740 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22742 /* Floating point variants -- don't add any more to this list either. */
22743 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22744 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22745 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22746 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
22747 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22749 {NULL, NULL, ARM_ARCH_NONE, NULL}
22752 struct arm_cpu_option_table
22755 const arm_feature_set value;
22756 /* For some CPUs we assume an FPU unless the user explicitly sets
22758 const arm_feature_set default_fpu;
22759 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22761 const char *canonical_name;
22764 /* This list should, at a minimum, contain all the cpu names
22765 recognized by GCC. */
22766 static const struct arm_cpu_option_table arm_cpus[] =
22768 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
22769 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
22770 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
22771 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22772 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22773 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22774 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22775 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22776 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22777 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22778 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22779 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22780 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22781 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22782 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22783 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22784 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22785 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22786 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22787 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22788 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22789 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22790 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22791 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22792 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22793 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22794 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22795 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22796 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22797 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22798 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22799 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22800 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22801 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22802 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22803 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22804 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22805 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22806 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22807 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
22808 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22809 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22810 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22811 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22812 {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22813 {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22814 /* For V5 or later processors we default to using VFP; but the user
22815 should really set the FPU type explicitly. */
22816 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22817 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22818 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22819 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22820 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22821 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22822 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
22823 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22824 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22825 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
22826 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22827 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22828 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22829 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22830 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22831 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
22832 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22833 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22834 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22835 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
22836 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22837 {"fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22838 {"fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22839 {"fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22840 {"fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22841 {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22842 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
22843 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
22844 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
22845 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
22846 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"},
22847 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"},
22848 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
22849 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
22850 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
22851 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
22852 {"cortex-a5", ARM_ARCH_V7A_MP_SEC,
22853 FPU_NONE, "Cortex-A5"},
22854 {"cortex-a8", ARM_ARCH_V7A_SEC,
22855 ARM_FEATURE (0, FPU_VFP_V3
22856 | FPU_NEON_EXT_V1),
22858 {"cortex-a9", ARM_ARCH_V7A_MP_SEC,
22859 ARM_FEATURE (0, FPU_VFP_V3
22860 | FPU_NEON_EXT_V1),
22862 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
22863 FPU_ARCH_NEON_VFP_V4,
22865 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
22866 {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
22868 {"cortex-r5", ARM_ARCH_V7R_IDIV,
22869 FPU_NONE, "Cortex-R5"},
22870 {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"},
22871 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"},
22872 {"cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"},
22873 {"cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"},
22874 /* ??? XSCALE is really an architecture. */
22875 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
22876 /* ??? iwmmxt is not a processor. */
22877 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
22878 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
22879 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
22881 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
22882 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
22885 struct arm_arch_option_table
22888 const arm_feature_set value;
22889 const arm_feature_set default_fpu;
22892 /* This list should, at a minimum, contain all the architecture names
22893 recognized by GCC. */
22894 static const struct arm_arch_option_table arm_archs[] =
22896 {"all", ARM_ANY, FPU_ARCH_FPA},
22897 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
22898 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
22899 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
22900 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
22901 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
22902 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
22903 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
22904 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
22905 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
22906 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
22907 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
22908 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
22909 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
22910 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
22911 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
22912 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
22913 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
22914 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
22915 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
22916 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
22917 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
22918 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
22919 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
22920 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
22921 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
22922 {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP},
22923 {"armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP},
22924 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
22925 /* The official spelling of the ARMv7 profile variants is the dashed form.
22926 Accept the non-dashed form for compatibility with old toolchains. */
22927 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
22928 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
22929 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
22930 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
22931 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
22932 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
22933 {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP},
22934 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
22935 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
22936 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
22937 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
22940 /* ISA extensions in the co-processor and main instruction set space. */
22941 struct arm_option_extension_value_table
22944 const arm_feature_set value;
22945 const arm_feature_set allowed_archs;
22948 /* The following table must be in alphabetical order with a NULL last entry.
22950 static const struct arm_option_extension_value_table arm_extensions[] =
22952 {"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
22953 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
22954 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
22955 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
22956 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
22957 {"mp", ARM_FEATURE (ARM_EXT_MP, 0),
22958 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
22959 {"os", ARM_FEATURE (ARM_EXT_OS, 0),
22960 ARM_FEATURE (ARM_EXT_V6M, 0)},
22961 {"sec", ARM_FEATURE (ARM_EXT_SEC, 0),
22962 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)},
22963 {"virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | ARM_EXT_DIV, 0),
22964 ARM_FEATURE (ARM_EXT_V7A, 0)},
22965 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY},
22966 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
22969 /* ISA floating-point and Advanced SIMD extensions. */
22970 struct arm_option_fpu_value_table
22973 const arm_feature_set value;
22976 /* This list should, at a minimum, contain all the fpu names
22977 recognized by GCC. */
22978 static const struct arm_option_fpu_value_table arm_fpus[] =
22980 {"softfpa", FPU_NONE},
22981 {"fpe", FPU_ARCH_FPE},
22982 {"fpe2", FPU_ARCH_FPE},
22983 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
22984 {"fpa", FPU_ARCH_FPA},
22985 {"fpa10", FPU_ARCH_FPA},
22986 {"fpa11", FPU_ARCH_FPA},
22987 {"arm7500fe", FPU_ARCH_FPA},
22988 {"softvfp", FPU_ARCH_VFP},
22989 {"softvfp+vfp", FPU_ARCH_VFP_V2},
22990 {"vfp", FPU_ARCH_VFP_V2},
22991 {"vfp9", FPU_ARCH_VFP_V2},
22992 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
22993 {"vfp10", FPU_ARCH_VFP_V2},
22994 {"vfp10-r0", FPU_ARCH_VFP_V1},
22995 {"vfpxd", FPU_ARCH_VFP_V1xD},
22996 {"vfpv2", FPU_ARCH_VFP_V2},
22997 {"vfpv3", FPU_ARCH_VFP_V3},
22998 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
22999 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23000 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23001 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23002 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23003 {"arm1020t", FPU_ARCH_VFP_V1},
23004 {"arm1020e", FPU_ARCH_VFP_V2},
23005 {"arm1136jfs", FPU_ARCH_VFP_V2},
23006 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23007 {"maverick", FPU_ARCH_MAVERICK},
23008 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23009 {"neon-fp16", FPU_ARCH_NEON_FP16},
23010 {"vfpv4", FPU_ARCH_VFP_V4},
23011 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23012 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23013 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23014 {NULL, ARM_ARCH_NONE}
23017 struct arm_option_value_table
23023 static const struct arm_option_value_table arm_float_abis[] =
23025 {"hard", ARM_FLOAT_ABI_HARD},
23026 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23027 {"soft", ARM_FLOAT_ABI_SOFT},
23032 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23033 static const struct arm_option_value_table arm_eabis[] =
23035 {"gnu", EF_ARM_EABI_UNKNOWN},
23036 {"4", EF_ARM_EABI_VER4},
23037 {"5", EF_ARM_EABI_VER5},
23042 struct arm_long_option_table
23044 char * option; /* Substring to match. */
23045 char * help; /* Help information. */
23046 int (* func) (char * subopt); /* Function to decode sub-option. */
23047 char * deprecated; /* If non-null, print this message. */
23051 arm_parse_extension (char * str, const arm_feature_set **opt_p)
23053 arm_feature_set *ext_set = (arm_feature_set *)
23054 xmalloc (sizeof (arm_feature_set));
23056 /* We insist on extensions being specified in alphabetical order, and with
23057 extensions being added before being removed. We achieve this by having
23058 the global ARM_EXTENSIONS table in alphabetical order, and using the
23059 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23060 or removing it (0) and only allowing it to change in the order
23062 const struct arm_option_extension_value_table * opt = NULL;
23063 int adding_value = -1;
23065 /* Copy the feature set, so that we can modify it. */
23066 *ext_set = **opt_p;
23069 while (str != NULL && *str != 0)
23076 as_bad (_("invalid architectural extension"));
23081 ext = strchr (str, '+');
23084 optlen = ext - str;
23086 optlen = strlen (str);
23089 && strncmp (str, "no", 2) == 0)
23091 if (adding_value != 0)
23094 opt = arm_extensions;
23100 else if (optlen > 0)
23102 if (adding_value == -1)
23105 opt = arm_extensions;
23107 else if (adding_value != 1)
23109 as_bad (_("must specify extensions to add before specifying "
23110 "those to remove"));
23117 as_bad (_("missing architectural extension"));
23121 gas_assert (adding_value != -1);
23122 gas_assert (opt != NULL);
23124 /* Scan over the options table trying to find an exact match. */
23125 for (; opt->name != NULL; opt++)
23126 if (strncmp (opt->name, str, optlen) == 0
23127 && strlen (opt->name) == optlen)
23129 /* Check we can apply the extension to this architecture. */
23130 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23132 as_bad (_("extension does not apply to the base architecture"));
23136 /* Add or remove the extension. */
23138 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23140 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23145 if (opt->name == NULL)
23147 /* Did we fail to find an extension because it wasn't specified in
23148 alphabetical order, or because it does not exist? */
23150 for (opt = arm_extensions; opt->name != NULL; opt++)
23151 if (strncmp (opt->name, str, optlen) == 0)
23154 if (opt->name == NULL)
23155 as_bad (_("unknown architectural extension `%s'"), str);
23157 as_bad (_("architectural extensions must be specified in "
23158 "alphabetical order"));
23164 /* We should skip the extension we've just matched the next time
23176 arm_parse_cpu (char * str)
23178 const struct arm_cpu_option_table * opt;
23179 char * ext = strchr (str, '+');
23183 optlen = ext - str;
23185 optlen = strlen (str);
23189 as_bad (_("missing cpu name `%s'"), str);
23193 for (opt = arm_cpus; opt->name != NULL; opt++)
23194 if (strncmp (opt->name, str, optlen) == 0)
23196 mcpu_cpu_opt = &opt->value;
23197 mcpu_fpu_opt = &opt->default_fpu;
23198 if (opt->canonical_name)
23199 strcpy (selected_cpu_name, opt->canonical_name);
23204 for (i = 0; i < optlen; i++)
23205 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23206 selected_cpu_name[i] = 0;
23210 return arm_parse_extension (ext, &mcpu_cpu_opt);
23215 as_bad (_("unknown cpu `%s'"), str);
23220 arm_parse_arch (char * str)
23222 const struct arm_arch_option_table *opt;
23223 char *ext = strchr (str, '+');
23227 optlen = ext - str;
23229 optlen = strlen (str);
23233 as_bad (_("missing architecture name `%s'"), str);
23237 for (opt = arm_archs; opt->name != NULL; opt++)
23238 if (strncmp (opt->name, str, optlen) == 0)
23240 march_cpu_opt = &opt->value;
23241 march_fpu_opt = &opt->default_fpu;
23242 strcpy (selected_cpu_name, opt->name);
23245 return arm_parse_extension (ext, &march_cpu_opt);
23250 as_bad (_("unknown architecture `%s'\n"), str);
23255 arm_parse_fpu (char * str)
23257 const struct arm_option_fpu_value_table * opt;
23259 for (opt = arm_fpus; opt->name != NULL; opt++)
23260 if (streq (opt->name, str))
23262 mfpu_opt = &opt->value;
23266 as_bad (_("unknown floating point format `%s'\n"), str);
23271 arm_parse_float_abi (char * str)
23273 const struct arm_option_value_table * opt;
23275 for (opt = arm_float_abis; opt->name != NULL; opt++)
23276 if (streq (opt->name, str))
23278 mfloat_abi_opt = opt->value;
23282 as_bad (_("unknown floating point abi `%s'\n"), str);
23288 arm_parse_eabi (char * str)
23290 const struct arm_option_value_table *opt;
23292 for (opt = arm_eabis; opt->name != NULL; opt++)
23293 if (streq (opt->name, str))
23295 meabi_flags = opt->value;
23298 as_bad (_("unknown EABI `%s'\n"), str);
23304 arm_parse_it_mode (char * str)
23306 bfd_boolean ret = TRUE;
23308 if (streq ("arm", str))
23309 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23310 else if (streq ("thumb", str))
23311 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23312 else if (streq ("always", str))
23313 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23314 else if (streq ("never", str))
23315 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23318 as_bad (_("unknown implicit IT mode `%s', should be "\
23319 "arm, thumb, always, or never."), str);
23326 struct arm_long_option_table arm_long_opts[] =
23328 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23329 arm_parse_cpu, NULL},
23330 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23331 arm_parse_arch, NULL},
23332 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23333 arm_parse_fpu, NULL},
23334 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23335 arm_parse_float_abi, NULL},
23337 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23338 arm_parse_eabi, NULL},
23340 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23341 arm_parse_it_mode, NULL},
23342 {NULL, NULL, 0, NULL}
23346 md_parse_option (int c, char * arg)
23348 struct arm_option_table *opt;
23349 const struct arm_legacy_option_table *fopt;
23350 struct arm_long_option_table *lopt;
23356 target_big_endian = 1;
23362 target_big_endian = 0;
23366 case OPTION_FIX_V4BX:
23371 /* Listing option. Just ignore these, we don't support additional
23376 for (opt = arm_opts; opt->option != NULL; opt++)
23378 if (c == opt->option[0]
23379 && ((arg == NULL && opt->option[1] == 0)
23380 || streq (arg, opt->option + 1)))
23382 /* If the option is deprecated, tell the user. */
23383 if (warn_on_deprecated && opt->deprecated != NULL)
23384 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23385 arg ? arg : "", _(opt->deprecated));
23387 if (opt->var != NULL)
23388 *opt->var = opt->value;
23394 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23396 if (c == fopt->option[0]
23397 && ((arg == NULL && fopt->option[1] == 0)
23398 || streq (arg, fopt->option + 1)))
23400 /* If the option is deprecated, tell the user. */
23401 if (warn_on_deprecated && fopt->deprecated != NULL)
23402 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23403 arg ? arg : "", _(fopt->deprecated));
23405 if (fopt->var != NULL)
23406 *fopt->var = &fopt->value;
23412 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23414 /* These options are expected to have an argument. */
23415 if (c == lopt->option[0]
23417 && strncmp (arg, lopt->option + 1,
23418 strlen (lopt->option + 1)) == 0)
23420 /* If the option is deprecated, tell the user. */
23421 if (warn_on_deprecated && lopt->deprecated != NULL)
23422 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23423 _(lopt->deprecated));
23425 /* Call the sup-option parser. */
23426 return lopt->func (arg + strlen (lopt->option) - 1);
23437 md_show_usage (FILE * fp)
23439 struct arm_option_table *opt;
23440 struct arm_long_option_table *lopt;
23442 fprintf (fp, _(" ARM-specific assembler options:\n"));
23444 for (opt = arm_opts; opt->option != NULL; opt++)
23445 if (opt->help != NULL)
23446 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23448 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23449 if (lopt->help != NULL)
23450 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23454 -EB assemble code for a big-endian cpu\n"));
23459 -EL assemble code for a little-endian cpu\n"));
23463 --fix-v4bx Allow BX in ARMv4 code\n"));
23471 arm_feature_set flags;
23472 } cpu_arch_ver_table;
23474 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23475 least features first. */
23476 static const cpu_arch_ver_table cpu_arch_ver[] =
23482 {4, ARM_ARCH_V5TE},
23483 {5, ARM_ARCH_V5TEJ},
23487 {11, ARM_ARCH_V6M},
23488 {12, ARM_ARCH_V6SM},
23489 {8, ARM_ARCH_V6T2},
23490 {10, ARM_ARCH_V7A},
23491 {10, ARM_ARCH_V7R},
23492 {10, ARM_ARCH_V7M},
23496 /* Set an attribute if it has not already been set by the user. */
23498 aeabi_set_attribute_int (int tag, int value)
23501 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23502 || !attributes_set_explicitly[tag])
23503 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23507 aeabi_set_attribute_string (int tag, const char *value)
23510 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23511 || !attributes_set_explicitly[tag])
23512 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23515 /* Set the public EABI object attributes. */
23517 aeabi_set_public_attributes (void)
23521 arm_feature_set flags;
23522 arm_feature_set tmp;
23523 const cpu_arch_ver_table *p;
23525 /* Choose the architecture based on the capabilities of the requested cpu
23526 (if any) and/or the instructions actually used. */
23527 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23528 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23529 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23530 /*Allow the user to override the reported architecture. */
23533 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23534 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23537 /* We need to make sure that the attributes do not identify us as v6S-M
23538 when the only v6S-M feature in use is the Operating System Extensions. */
23539 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23540 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23541 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23545 for (p = cpu_arch_ver; p->val; p++)
23547 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23550 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23554 /* The table lookup above finds the last architecture to contribute
23555 a new feature. Unfortunately, Tag13 is a subset of the union of
23556 v6T2 and v7-M, so it is never seen as contributing a new feature.
23557 We can not search for the last entry which is entirely used,
23558 because if no CPU is specified we build up only those flags
23559 actually used. Perhaps we should separate out the specified
23560 and implicit cases. Avoid taking this path for -march=all by
23561 checking for contradictory v7-A / v7-M features. */
23563 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23564 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23565 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23568 /* Tag_CPU_name. */
23569 if (selected_cpu_name[0])
23573 q = selected_cpu_name;
23574 if (strncmp (q, "armv", 4) == 0)
23579 for (i = 0; q[i]; i++)
23580 q[i] = TOUPPER (q[i]);
23582 aeabi_set_attribute_string (Tag_CPU_name, q);
23585 /* Tag_CPU_arch. */
23586 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23588 /* Tag_CPU_arch_profile. */
23589 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23590 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A');
23591 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23592 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R');
23593 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23594 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M');
23596 /* Tag_ARM_ISA_use. */
23597 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23599 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23601 /* Tag_THUMB_ISA_use. */
23602 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23604 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23605 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23607 /* Tag_VFP_arch. */
23608 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23609 aeabi_set_attribute_int (Tag_VFP_arch,
23610 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23612 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23613 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23614 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23615 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23616 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23617 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23618 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23619 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23620 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23622 /* Tag_ABI_HardFP_use. */
23623 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23624 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23625 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23627 /* Tag_WMMX_arch. */
23628 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23629 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23630 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23631 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23633 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23634 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23635 aeabi_set_attribute_int
23636 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
23639 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23640 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
23641 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23644 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
23645 aeabi_set_attribute_int (Tag_DIV_use, 2);
23646 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
23647 aeabi_set_attribute_int (Tag_DIV_use, 0);
23649 aeabi_set_attribute_int (Tag_DIV_use, 1);
23651 /* Tag_MP_extension_use. */
23652 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23653 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23655 /* Tag Virtualization_use. */
23656 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
23658 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
23661 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
23664 /* Add the default contents for the .ARM.attributes section. */
23668 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23671 aeabi_set_public_attributes ();
23673 #endif /* OBJ_ELF */
23676 /* Parse a .cpu directive. */
23679 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
23681 const struct arm_cpu_option_table *opt;
23685 name = input_line_pointer;
23686 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23687 input_line_pointer++;
23688 saved_char = *input_line_pointer;
23689 *input_line_pointer = 0;
23691 /* Skip the first "all" entry. */
23692 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
23693 if (streq (opt->name, name))
23695 mcpu_cpu_opt = &opt->value;
23696 selected_cpu = opt->value;
23697 if (opt->canonical_name)
23698 strcpy (selected_cpu_name, opt->canonical_name);
23702 for (i = 0; opt->name[i]; i++)
23703 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23704 selected_cpu_name[i] = 0;
23706 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23707 *input_line_pointer = saved_char;
23708 demand_empty_rest_of_line ();
23711 as_bad (_("unknown cpu `%s'"), name);
23712 *input_line_pointer = saved_char;
23713 ignore_rest_of_line ();
23717 /* Parse a .arch directive. */
23720 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
23722 const struct arm_arch_option_table *opt;
23726 name = input_line_pointer;
23727 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23728 input_line_pointer++;
23729 saved_char = *input_line_pointer;
23730 *input_line_pointer = 0;
23732 /* Skip the first "all" entry. */
23733 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23734 if (streq (opt->name, name))
23736 mcpu_cpu_opt = &opt->value;
23737 selected_cpu = opt->value;
23738 strcpy (selected_cpu_name, opt->name);
23739 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23740 *input_line_pointer = saved_char;
23741 demand_empty_rest_of_line ();
23745 as_bad (_("unknown architecture `%s'\n"), name);
23746 *input_line_pointer = saved_char;
23747 ignore_rest_of_line ();
23751 /* Parse a .object_arch directive. */
23754 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
23756 const struct arm_arch_option_table *opt;
23760 name = input_line_pointer;
23761 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23762 input_line_pointer++;
23763 saved_char = *input_line_pointer;
23764 *input_line_pointer = 0;
23766 /* Skip the first "all" entry. */
23767 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23768 if (streq (opt->name, name))
23770 object_arch = &opt->value;
23771 *input_line_pointer = saved_char;
23772 demand_empty_rest_of_line ();
23776 as_bad (_("unknown architecture `%s'\n"), name);
23777 *input_line_pointer = saved_char;
23778 ignore_rest_of_line ();
23781 /* Parse a .arch_extension directive. */
23784 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
23786 const struct arm_option_extension_value_table *opt;
23789 int adding_value = 1;
23791 name = input_line_pointer;
23792 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23793 input_line_pointer++;
23794 saved_char = *input_line_pointer;
23795 *input_line_pointer = 0;
23797 if (strlen (name) >= 2
23798 && strncmp (name, "no", 2) == 0)
23804 for (opt = arm_extensions; opt->name != NULL; opt++)
23805 if (streq (opt->name, name))
23807 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
23809 as_bad (_("architectural extension `%s' is not allowed for the "
23810 "current base architecture"), name);
23815 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
23817 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
23819 mcpu_cpu_opt = &selected_cpu;
23820 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23821 *input_line_pointer = saved_char;
23822 demand_empty_rest_of_line ();
23826 if (opt->name == NULL)
23827 as_bad (_("unknown architecture `%s'\n"), name);
23829 *input_line_pointer = saved_char;
23830 ignore_rest_of_line ();
23833 /* Parse a .fpu directive. */
23836 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
23838 const struct arm_option_fpu_value_table *opt;
23842 name = input_line_pointer;
23843 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23844 input_line_pointer++;
23845 saved_char = *input_line_pointer;
23846 *input_line_pointer = 0;
23848 for (opt = arm_fpus; opt->name != NULL; opt++)
23849 if (streq (opt->name, name))
23851 mfpu_opt = &opt->value;
23852 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23853 *input_line_pointer = saved_char;
23854 demand_empty_rest_of_line ();
23858 as_bad (_("unknown floating point format `%s'\n"), name);
23859 *input_line_pointer = saved_char;
23860 ignore_rest_of_line ();
23863 /* Copy symbol information. */
23866 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
23868 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
23872 /* Given a symbolic attribute NAME, return the proper integer value.
23873 Returns -1 if the attribute is not known. */
23876 arm_convert_symbolic_attribute (const char *name)
23878 static const struct
23883 attribute_table[] =
23885 /* When you modify this table you should
23886 also modify the list in doc/c-arm.texi. */
23887 #define T(tag) {#tag, tag}
23888 T (Tag_CPU_raw_name),
23891 T (Tag_CPU_arch_profile),
23892 T (Tag_ARM_ISA_use),
23893 T (Tag_THUMB_ISA_use),
23897 T (Tag_Advanced_SIMD_arch),
23898 T (Tag_PCS_config),
23899 T (Tag_ABI_PCS_R9_use),
23900 T (Tag_ABI_PCS_RW_data),
23901 T (Tag_ABI_PCS_RO_data),
23902 T (Tag_ABI_PCS_GOT_use),
23903 T (Tag_ABI_PCS_wchar_t),
23904 T (Tag_ABI_FP_rounding),
23905 T (Tag_ABI_FP_denormal),
23906 T (Tag_ABI_FP_exceptions),
23907 T (Tag_ABI_FP_user_exceptions),
23908 T (Tag_ABI_FP_number_model),
23909 T (Tag_ABI_align_needed),
23910 T (Tag_ABI_align8_needed),
23911 T (Tag_ABI_align_preserved),
23912 T (Tag_ABI_align8_preserved),
23913 T (Tag_ABI_enum_size),
23914 T (Tag_ABI_HardFP_use),
23915 T (Tag_ABI_VFP_args),
23916 T (Tag_ABI_WMMX_args),
23917 T (Tag_ABI_optimization_goals),
23918 T (Tag_ABI_FP_optimization_goals),
23919 T (Tag_compatibility),
23920 T (Tag_CPU_unaligned_access),
23921 T (Tag_FP_HP_extension),
23922 T (Tag_VFP_HP_extension),
23923 T (Tag_ABI_FP_16bit_format),
23924 T (Tag_MPextension_use),
23926 T (Tag_nodefaults),
23927 T (Tag_also_compatible_with),
23928 T (Tag_conformance),
23930 T (Tag_Virtualization_use),
23931 /* We deliberately do not include Tag_MPextension_use_legacy. */
23939 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
23940 if (streq (name, attribute_table[i].name))
23941 return attribute_table[i].tag;
23947 /* Apply sym value for relocations only in the case that
23948 they are for local symbols and you have the respective
23949 architectural feature for blx and simple switches. */
23951 arm_apply_sym_value (struct fix * fixP)
23954 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23955 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
23957 switch (fixP->fx_r_type)
23959 case BFD_RELOC_ARM_PCREL_BLX:
23960 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23961 if (ARM_IS_FUNC (fixP->fx_addsy))
23965 case BFD_RELOC_ARM_PCREL_CALL:
23966 case BFD_RELOC_THUMB_PCREL_BLX:
23967 if (THUMB_IS_FUNC (fixP->fx_addsy))
23978 #endif /* OBJ_ELF */