1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2014 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant;
127 static arm_feature_set arm_arch_used;
128 static arm_feature_set thumb_arch_used;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26 = FALSE;
132 static int atpcs = FALSE;
133 static int support_interwork = FALSE;
134 static int uses_apcs_float = FALSE;
135 static int pic_code = FALSE;
136 static int fix_v4bx = FALSE;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated = TRUE;
141 /* Variables that we set while parsing command-line options. Once all
142 options have been read we re-process these values to set the real
144 static const arm_feature_set *legacy_cpu = NULL;
145 static const arm_feature_set *legacy_fpu = NULL;
147 static const arm_feature_set *mcpu_cpu_opt = NULL;
148 static const arm_feature_set *mcpu_fpu_opt = NULL;
149 static const arm_feature_set *march_cpu_opt = NULL;
150 static const arm_feature_set *march_fpu_opt = NULL;
151 static const arm_feature_set *mfpu_opt = NULL;
152 static const arm_feature_set *object_arch = NULL;
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default = FPU_DEFAULT;
156 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
158 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
159 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
160 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
161 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
162 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
163 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
166 static const arm_feature_set cpu_default = CPU_DEFAULT;
169 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
170 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
171 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
172 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
173 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
174 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
175 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
176 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
177 static const arm_feature_set arm_ext_v4t_5 =
178 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
180 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
181 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
182 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
183 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
184 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
185 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
186 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
187 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
188 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
189 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
190 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
191 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
192 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
193 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
194 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
195 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
196 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
197 static const arm_feature_set arm_ext_m =
198 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
199 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
200 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
201 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
202 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
203 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
205 static const arm_feature_set arm_arch_any = ARM_ANY;
206 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
208 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
209 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
211 static const arm_feature_set arm_cext_iwmmxt2 =
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
213 static const arm_feature_set arm_cext_iwmmxt =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
215 static const arm_feature_set arm_cext_xscale =
216 ARM_FEATURE (0, ARM_CEXT_XSCALE);
217 static const arm_feature_set arm_cext_maverick =
218 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
219 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
220 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
221 static const arm_feature_set fpu_vfp_ext_v1xd =
222 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
223 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
224 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
225 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
226 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
227 static const arm_feature_set fpu_vfp_ext_d32 =
228 ARM_FEATURE (0, FPU_VFP_EXT_D32);
229 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
230 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
231 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
232 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
233 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
234 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_armv8 =
236 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
237 static const arm_feature_set fpu_neon_ext_armv8 =
238 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
239 static const arm_feature_set fpu_crypto_ext_armv8 =
240 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
241 static const arm_feature_set crc_ext_armv8 =
242 ARM_FEATURE (0, CRC_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
324 /* An immediate operand can start with #, and ld*, st*, pld operands
325 can contain [ and ]. We need to tell APP not to elide whitespace
326 before a [, which can appear as the first operand for pld.
327 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
328 const char arm_symbol_chars[] = "#[]{}";
343 enum neon_el_type type;
347 #define NEON_MAX_TYPE_ELS 4
351 struct neon_type_el el[NEON_MAX_TYPE_ELS];
355 enum it_instruction_type
360 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
361 if inside, should be the last one. */
362 NEUTRAL_IT_INSN, /* This could be either inside or outside,
363 i.e. BKPT and NOP. */
364 IT_INSN /* The IT insn has been parsed. */
367 /* The maximum number of operands we need. */
368 #define ARM_IT_MAX_OPERANDS 6
373 unsigned long instruction;
377 /* "uncond_value" is set to the value in place of the conditional field in
378 unconditional versions of the instruction, or -1 if nothing is
381 struct neon_type vectype;
382 /* This does not indicate an actual NEON instruction, only that
383 the mnemonic accepts neon-style type suffixes. */
385 /* Set to the opcode if the instruction needs relaxation.
386 Zero if the instruction is not relaxed. */
390 bfd_reloc_code_real_type type;
395 enum it_instruction_type it_insn_type;
401 struct neon_type_el vectype;
402 unsigned present : 1; /* Operand present. */
403 unsigned isreg : 1; /* Operand was a register. */
404 unsigned immisreg : 1; /* .imm field is a second register. */
405 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
406 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
407 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
408 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
409 instructions. This allows us to disambiguate ARM <-> vector insns. */
410 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
411 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
412 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
413 unsigned issingle : 1; /* Operand is VFP single-precision register. */
414 unsigned hasreloc : 1; /* Operand has relocation suffix. */
415 unsigned writeback : 1; /* Operand has trailing ! */
416 unsigned preind : 1; /* Preindexed address. */
417 unsigned postind : 1; /* Postindexed address. */
418 unsigned negative : 1; /* Index register was negated. */
419 unsigned shifted : 1; /* Shift applied to operation. */
420 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
421 } operands[ARM_IT_MAX_OPERANDS];
424 static struct arm_it inst;
426 #define NUM_FLOAT_VALS 8
428 const char * fp_const[] =
430 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
433 /* Number of littlenums required to hold an extended precision number. */
434 #define MAX_LITTLENUMS 6
436 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
446 #define CP_T_X 0x00008000
447 #define CP_T_Y 0x00400000
449 #define CONDS_BIT 0x00100000
450 #define LOAD_BIT 0x00100000
452 #define DOUBLE_LOAD_FLAG 0x00000001
456 const char * template_name;
460 #define COND_ALWAYS 0xE
464 const char * template_name;
468 struct asm_barrier_opt
470 const char * template_name;
472 const arm_feature_set arch;
475 /* The bit that distinguishes CPSR and SPSR. */
476 #define SPSR_BIT (1 << 22)
478 /* The individual PSR flag bits. */
479 #define PSR_c (1 << 16)
480 #define PSR_x (1 << 17)
481 #define PSR_s (1 << 18)
482 #define PSR_f (1 << 19)
487 bfd_reloc_code_real_type reloc;
492 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
493 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
498 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
501 /* Bits for DEFINED field in neon_typed_alias. */
502 #define NTA_HASTYPE 1
503 #define NTA_HASINDEX 2
505 struct neon_typed_alias
507 unsigned char defined;
509 struct neon_type_el eltype;
512 /* ARM register categories. This includes coprocessor numbers and various
513 architecture extensions' registers. */
540 /* Structure for a hash table entry for a register.
541 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
542 information which states whether a vector type or index is specified (for a
543 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
549 unsigned char builtin;
550 struct neon_typed_alias * neon;
553 /* Diagnostics used when we don't get a register of the expected type. */
554 const char * const reg_expected_msgs[] =
556 N_("ARM register expected"),
557 N_("bad or missing co-processor number"),
558 N_("co-processor register expected"),
559 N_("FPA register expected"),
560 N_("VFP single precision register expected"),
561 N_("VFP/Neon double precision register expected"),
562 N_("Neon quad precision register expected"),
563 N_("VFP single or double precision register expected"),
564 N_("Neon double or quad precision register expected"),
565 N_("VFP single, double or Neon quad precision register expected"),
566 N_("VFP system register expected"),
567 N_("Maverick MVF register expected"),
568 N_("Maverick MVD register expected"),
569 N_("Maverick MVFX register expected"),
570 N_("Maverick MVDX register expected"),
571 N_("Maverick MVAX register expected"),
572 N_("Maverick DSPSC register expected"),
573 N_("iWMMXt data register expected"),
574 N_("iWMMXt control register expected"),
575 N_("iWMMXt scalar register expected"),
576 N_("XScale accumulator register expected"),
579 /* Some well known registers that we refer to directly elsewhere. */
585 /* ARM instructions take 4bytes in the object file, Thumb instructions
591 /* Basic string to match. */
592 const char * template_name;
594 /* Parameters to instruction. */
595 unsigned int operands[8];
597 /* Conditional tag - see opcode_lookup. */
598 unsigned int tag : 4;
600 /* Basic instruction code. */
601 unsigned int avalue : 28;
603 /* Thumb-format instruction code. */
606 /* Which architecture variant provides this instruction. */
607 const arm_feature_set * avariant;
608 const arm_feature_set * tvariant;
610 /* Function to call to encode instruction in ARM format. */
611 void (* aencode) (void);
613 /* Function to call to encode instruction in Thumb format. */
614 void (* tencode) (void);
617 /* Defines for various bits that we will want to toggle. */
618 #define INST_IMMEDIATE 0x02000000
619 #define OFFSET_REG 0x02000000
620 #define HWOFFSET_IMM 0x00400000
621 #define SHIFT_BY_REG 0x00000010
622 #define PRE_INDEX 0x01000000
623 #define INDEX_UP 0x00800000
624 #define WRITE_BACK 0x00200000
625 #define LDM_TYPE_2_OR_3 0x00400000
626 #define CPSI_MMOD 0x00020000
628 #define LITERAL_MASK 0xf000f000
629 #define OPCODE_MASK 0xfe1fffff
630 #define V4_STR_BIT 0x00000020
632 #define T2_SUBS_PC_LR 0xf3de8f00
634 #define DATA_OP_SHIFT 21
636 #define T2_OPCODE_MASK 0xfe1fffff
637 #define T2_DATA_OP_SHIFT 21
639 #define A_COND_MASK 0xf0000000
640 #define A_PUSH_POP_OP_MASK 0x0fff0000
642 /* Opcodes for pushing/poping registers to/from the stack. */
643 #define A1_OPCODE_PUSH 0x092d0000
644 #define A2_OPCODE_PUSH 0x052d0004
645 #define A2_OPCODE_POP 0x049d0004
647 /* Codes to distinguish the arithmetic instructions. */
658 #define OPCODE_CMP 10
659 #define OPCODE_CMN 11
660 #define OPCODE_ORR 12
661 #define OPCODE_MOV 13
662 #define OPCODE_BIC 14
663 #define OPCODE_MVN 15
665 #define T2_OPCODE_AND 0
666 #define T2_OPCODE_BIC 1
667 #define T2_OPCODE_ORR 2
668 #define T2_OPCODE_ORN 3
669 #define T2_OPCODE_EOR 4
670 #define T2_OPCODE_ADD 8
671 #define T2_OPCODE_ADC 10
672 #define T2_OPCODE_SBC 11
673 #define T2_OPCODE_SUB 13
674 #define T2_OPCODE_RSB 14
676 #define T_OPCODE_MUL 0x4340
677 #define T_OPCODE_TST 0x4200
678 #define T_OPCODE_CMN 0x42c0
679 #define T_OPCODE_NEG 0x4240
680 #define T_OPCODE_MVN 0x43c0
682 #define T_OPCODE_ADD_R3 0x1800
683 #define T_OPCODE_SUB_R3 0x1a00
684 #define T_OPCODE_ADD_HI 0x4400
685 #define T_OPCODE_ADD_ST 0xb000
686 #define T_OPCODE_SUB_ST 0xb080
687 #define T_OPCODE_ADD_SP 0xa800
688 #define T_OPCODE_ADD_PC 0xa000
689 #define T_OPCODE_ADD_I8 0x3000
690 #define T_OPCODE_SUB_I8 0x3800
691 #define T_OPCODE_ADD_I3 0x1c00
692 #define T_OPCODE_SUB_I3 0x1e00
694 #define T_OPCODE_ASR_R 0x4100
695 #define T_OPCODE_LSL_R 0x4080
696 #define T_OPCODE_LSR_R 0x40c0
697 #define T_OPCODE_ROR_R 0x41c0
698 #define T_OPCODE_ASR_I 0x1000
699 #define T_OPCODE_LSL_I 0x0000
700 #define T_OPCODE_LSR_I 0x0800
702 #define T_OPCODE_MOV_I8 0x2000
703 #define T_OPCODE_CMP_I8 0x2800
704 #define T_OPCODE_CMP_LR 0x4280
705 #define T_OPCODE_MOV_HR 0x4600
706 #define T_OPCODE_CMP_HR 0x4500
708 #define T_OPCODE_LDR_PC 0x4800
709 #define T_OPCODE_LDR_SP 0x9800
710 #define T_OPCODE_STR_SP 0x9000
711 #define T_OPCODE_LDR_IW 0x6800
712 #define T_OPCODE_STR_IW 0x6000
713 #define T_OPCODE_LDR_IH 0x8800
714 #define T_OPCODE_STR_IH 0x8000
715 #define T_OPCODE_LDR_IB 0x7800
716 #define T_OPCODE_STR_IB 0x7000
717 #define T_OPCODE_LDR_RW 0x5800
718 #define T_OPCODE_STR_RW 0x5000
719 #define T_OPCODE_LDR_RH 0x5a00
720 #define T_OPCODE_STR_RH 0x5200
721 #define T_OPCODE_LDR_RB 0x5c00
722 #define T_OPCODE_STR_RB 0x5400
724 #define T_OPCODE_PUSH 0xb400
725 #define T_OPCODE_POP 0xbc00
727 #define T_OPCODE_BRANCH 0xe000
729 #define THUMB_SIZE 2 /* Size of thumb instruction. */
730 #define THUMB_PP_PC_LR 0x0100
731 #define THUMB_LOAD_BIT 0x0800
732 #define THUMB2_LOAD_BIT 0x00100000
734 #define BAD_ARGS _("bad arguments to instruction")
735 #define BAD_SP _("r13 not allowed here")
736 #define BAD_PC _("r15 not allowed here")
737 #define BAD_COND _("instruction cannot be conditional")
738 #define BAD_OVERLAP _("registers may not be the same")
739 #define BAD_HIREG _("lo register required")
740 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
741 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
742 #define BAD_BRANCH _("branch must be last instruction in IT block")
743 #define BAD_NOT_IT _("instruction not allowed in IT block")
744 #define BAD_FPU _("selected FPU does not support instruction")
745 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
746 #define BAD_IT_COND _("incorrect condition in IT block")
747 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
748 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
749 #define BAD_PC_ADDRESSING \
750 _("cannot use register index with PC-relative addressing")
751 #define BAD_PC_WRITEBACK \
752 _("cannot use writeback with PC-relative addressing")
753 #define BAD_RANGE _("branch out of range")
754 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
756 static struct hash_control * arm_ops_hsh;
757 static struct hash_control * arm_cond_hsh;
758 static struct hash_control * arm_shift_hsh;
759 static struct hash_control * arm_psr_hsh;
760 static struct hash_control * arm_v7m_psr_hsh;
761 static struct hash_control * arm_reg_hsh;
762 static struct hash_control * arm_reloc_hsh;
763 static struct hash_control * arm_barrier_opt_hsh;
765 /* Stuff needed to resolve the label ambiguity
774 symbolS * last_label_seen;
775 static int label_is_thumb_function_name = FALSE;
777 /* Literal pool structure. Held on a per-section
778 and per-sub-section basis. */
780 #define MAX_LITERAL_POOL_SIZE 1024
781 typedef struct literal_pool
783 expressionS literals [MAX_LITERAL_POOL_SIZE];
784 unsigned int next_free_entry;
790 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
792 struct literal_pool * next;
795 /* Pointer to a linked list of literal pools. */
796 literal_pool * list_of_pools = NULL;
799 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
801 static struct current_it now_it;
805 now_it_compatible (int cond)
807 return (cond & ~1) == (now_it.cc & ~1);
811 conditional_insn (void)
813 return inst.cond != COND_ALWAYS;
816 static int in_it_block (void);
818 static int handle_it_state (void);
820 static void force_automatic_it_block_close (void);
822 static void it_fsm_post_encode (void);
824 #define set_it_insn_type(type) \
827 inst.it_insn_type = type; \
828 if (handle_it_state () == FAIL) \
833 #define set_it_insn_type_nonvoid(type, failret) \
836 inst.it_insn_type = type; \
837 if (handle_it_state () == FAIL) \
842 #define set_it_insn_type_last() \
845 if (inst.cond == COND_ALWAYS) \
846 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
848 set_it_insn_type (INSIDE_IT_LAST_INSN); \
854 /* This array holds the chars that always start a comment. If the
855 pre-processor is disabled, these aren't very useful. */
856 const char comment_chars[] = "@";
858 /* This array holds the chars that only start a comment at the beginning of
859 a line. If the line seems to have the form '# 123 filename'
860 .line and .file directives will appear in the pre-processed output. */
861 /* Note that input_file.c hand checks for '#' at the beginning of the
862 first line of the input file. This is because the compiler outputs
863 #NO_APP at the beginning of its output. */
864 /* Also note that comments like this one will always work. */
865 const char line_comment_chars[] = "#";
867 const char line_separator_chars[] = ";";
869 /* Chars that can be used to separate mant
870 from exp in floating point numbers. */
871 const char EXP_CHARS[] = "eE";
873 /* Chars that mean this number is a floating point constant. */
877 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
879 /* Prefix characters that indicate the start of an immediate
881 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
883 /* Separator character handling. */
885 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
888 skip_past_char (char ** str, char c)
890 /* PR gas/14987: Allow for whitespace before the expected character. */
891 skip_whitespace (*str);
902 #define skip_past_comma(str) skip_past_char (str, ',')
904 /* Arithmetic expressions (possibly involving symbols). */
906 /* Return TRUE if anything in the expression is a bignum. */
909 walk_no_bignums (symbolS * sp)
911 if (symbol_get_value_expression (sp)->X_op == O_big)
914 if (symbol_get_value_expression (sp)->X_add_symbol)
916 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
917 || (symbol_get_value_expression (sp)->X_op_symbol
918 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
924 static int in_my_get_expression = 0;
926 /* Third argument to my_get_expression. */
927 #define GE_NO_PREFIX 0
928 #define GE_IMM_PREFIX 1
929 #define GE_OPT_PREFIX 2
930 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
931 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
932 #define GE_OPT_PREFIX_BIG 3
935 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
940 /* In unified syntax, all prefixes are optional. */
942 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
947 case GE_NO_PREFIX: break;
949 if (!is_immediate_prefix (**str))
951 inst.error = _("immediate expression requires a # prefix");
957 case GE_OPT_PREFIX_BIG:
958 if (is_immediate_prefix (**str))
964 memset (ep, 0, sizeof (expressionS));
966 save_in = input_line_pointer;
967 input_line_pointer = *str;
968 in_my_get_expression = 1;
969 seg = expression (ep);
970 in_my_get_expression = 0;
972 if (ep->X_op == O_illegal || ep->X_op == O_absent)
974 /* We found a bad or missing expression in md_operand(). */
975 *str = input_line_pointer;
976 input_line_pointer = save_in;
977 if (inst.error == NULL)
978 inst.error = (ep->X_op == O_absent
979 ? _("missing expression") :_("bad expression"));
984 if (seg != absolute_section
985 && seg != text_section
986 && seg != data_section
987 && seg != bss_section
988 && seg != undefined_section)
990 inst.error = _("bad segment");
991 *str = input_line_pointer;
992 input_line_pointer = save_in;
999 /* Get rid of any bignums now, so that we don't generate an error for which
1000 we can't establish a line number later on. Big numbers are never valid
1001 in instructions, which is where this routine is always called. */
1002 if (prefix_mode != GE_OPT_PREFIX_BIG
1003 && (ep->X_op == O_big
1004 || (ep->X_add_symbol
1005 && (walk_no_bignums (ep->X_add_symbol)
1007 && walk_no_bignums (ep->X_op_symbol))))))
1009 inst.error = _("invalid constant");
1010 *str = input_line_pointer;
1011 input_line_pointer = save_in;
1015 *str = input_line_pointer;
1016 input_line_pointer = save_in;
1020 /* Turn a string in input_line_pointer into a floating point constant
1021 of type TYPE, and store the appropriate bytes in *LITP. The number
1022 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1023 returned, or NULL on OK.
1025 Note that fp constants aren't represent in the normal way on the ARM.
1026 In big endian mode, things are as expected. However, in little endian
1027 mode fp constants are big-endian word-wise, and little-endian byte-wise
1028 within the words. For example, (double) 1.1 in big endian mode is
1029 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1030 the byte sequence 99 99 f1 3f 9a 99 99 99.
1032 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1035 md_atof (int type, char * litP, int * sizeP)
1038 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1070 return _("Unrecognized or unsupported floating point constant");
1073 t = atof_ieee (input_line_pointer, type, words);
1075 input_line_pointer = t;
1076 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1078 if (target_big_endian)
1080 for (i = 0; i < prec; i++)
1082 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1083 litP += sizeof (LITTLENUM_TYPE);
1088 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1089 for (i = prec - 1; i >= 0; i--)
1091 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1092 litP += sizeof (LITTLENUM_TYPE);
1095 /* For a 4 byte float the order of elements in `words' is 1 0.
1096 For an 8 byte float the order is 1 0 3 2. */
1097 for (i = 0; i < prec; i += 2)
1099 md_number_to_chars (litP, (valueT) words[i + 1],
1100 sizeof (LITTLENUM_TYPE));
1101 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1102 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1103 litP += 2 * sizeof (LITTLENUM_TYPE);
1110 /* We handle all bad expressions here, so that we can report the faulty
1111 instruction in the error message. */
1113 md_operand (expressionS * exp)
1115 if (in_my_get_expression)
1116 exp->X_op = O_illegal;
1119 /* Immediate values. */
1121 /* Generic immediate-value read function for use in directives.
1122 Accepts anything that 'expression' can fold to a constant.
1123 *val receives the number. */
1126 immediate_for_directive (int *val)
1129 exp.X_op = O_illegal;
1131 if (is_immediate_prefix (*input_line_pointer))
1133 input_line_pointer++;
1137 if (exp.X_op != O_constant)
1139 as_bad (_("expected #constant"));
1140 ignore_rest_of_line ();
1143 *val = exp.X_add_number;
1148 /* Register parsing. */
1150 /* Generic register parser. CCP points to what should be the
1151 beginning of a register name. If it is indeed a valid register
1152 name, advance CCP over it and return the reg_entry structure;
1153 otherwise return NULL. Does not issue diagnostics. */
1155 static struct reg_entry *
1156 arm_reg_parse_multi (char **ccp)
1160 struct reg_entry *reg;
1162 skip_whitespace (start);
1164 #ifdef REGISTER_PREFIX
1165 if (*start != REGISTER_PREFIX)
1169 #ifdef OPTIONAL_REGISTER_PREFIX
1170 if (*start == OPTIONAL_REGISTER_PREFIX)
1175 if (!ISALPHA (*p) || !is_name_beginner (*p))
1180 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1182 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1192 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1193 enum arm_reg_type type)
1195 /* Alternative syntaxes are accepted for a few register classes. */
1202 /* Generic coprocessor register names are allowed for these. */
1203 if (reg && reg->type == REG_TYPE_CN)
1208 /* For backward compatibility, a bare number is valid here. */
1210 unsigned long processor = strtoul (start, ccp, 10);
1211 if (*ccp != start && processor <= 15)
1215 case REG_TYPE_MMXWC:
1216 /* WC includes WCG. ??? I'm not sure this is true for all
1217 instructions that take WC registers. */
1218 if (reg && reg->type == REG_TYPE_MMXWCG)
1229 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1230 return value is the register number or FAIL. */
1233 arm_reg_parse (char **ccp, enum arm_reg_type type)
1236 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1239 /* Do not allow a scalar (reg+index) to parse as a register. */
1240 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1243 if (reg && reg->type == type)
1246 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1253 /* Parse a Neon type specifier. *STR should point at the leading '.'
1254 character. Does no verification at this stage that the type fits the opcode
1261 Can all be legally parsed by this function.
1263 Fills in neon_type struct pointer with parsed information, and updates STR
1264 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1265 type, FAIL if not. */
1268 parse_neon_type (struct neon_type *type, char **str)
1275 while (type->elems < NEON_MAX_TYPE_ELS)
1277 enum neon_el_type thistype = NT_untyped;
1278 unsigned thissize = -1u;
1285 /* Just a size without an explicit type. */
1289 switch (TOLOWER (*ptr))
1291 case 'i': thistype = NT_integer; break;
1292 case 'f': thistype = NT_float; break;
1293 case 'p': thistype = NT_poly; break;
1294 case 's': thistype = NT_signed; break;
1295 case 'u': thistype = NT_unsigned; break;
1297 thistype = NT_float;
1302 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1308 /* .f is an abbreviation for .f32. */
1309 if (thistype == NT_float && !ISDIGIT (*ptr))
1314 thissize = strtoul (ptr, &ptr, 10);
1316 if (thissize != 8 && thissize != 16 && thissize != 32
1319 as_bad (_("bad size %d in type specifier"), thissize);
1327 type->el[type->elems].type = thistype;
1328 type->el[type->elems].size = thissize;
1333 /* Empty/missing type is not a successful parse. */
1334 if (type->elems == 0)
1342 /* Errors may be set multiple times during parsing or bit encoding
1343 (particularly in the Neon bits), but usually the earliest error which is set
1344 will be the most meaningful. Avoid overwriting it with later (cascading)
1345 errors by calling this function. */
1348 first_error (const char *err)
1354 /* Parse a single type, e.g. ".s32", leading period included. */
1356 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1359 struct neon_type optype;
1363 if (parse_neon_type (&optype, &str) == SUCCESS)
1365 if (optype.elems == 1)
1366 *vectype = optype.el[0];
1369 first_error (_("only one type should be specified for operand"));
1375 first_error (_("vector type expected"));
1387 /* Special meanings for indices (which have a range of 0-7), which will fit into
1390 #define NEON_ALL_LANES 15
1391 #define NEON_INTERLEAVE_LANES 14
1393 /* Parse either a register or a scalar, with an optional type. Return the
1394 register number, and optionally fill in the actual type of the register
1395 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1396 type/index information in *TYPEINFO. */
1399 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1400 enum arm_reg_type *rtype,
1401 struct neon_typed_alias *typeinfo)
1404 struct reg_entry *reg = arm_reg_parse_multi (&str);
1405 struct neon_typed_alias atype;
1406 struct neon_type_el parsetype;
1410 atype.eltype.type = NT_invtype;
1411 atype.eltype.size = -1;
1413 /* Try alternate syntax for some types of register. Note these are mutually
1414 exclusive with the Neon syntax extensions. */
1417 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1425 /* Undo polymorphism when a set of register types may be accepted. */
1426 if ((type == REG_TYPE_NDQ
1427 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1428 || (type == REG_TYPE_VFSD
1429 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1430 || (type == REG_TYPE_NSDQ
1431 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1432 || reg->type == REG_TYPE_NQ))
1433 || (type == REG_TYPE_MMXWC
1434 && (reg->type == REG_TYPE_MMXWCG)))
1435 type = (enum arm_reg_type) reg->type;
1437 if (type != reg->type)
1443 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1445 if ((atype.defined & NTA_HASTYPE) != 0)
1447 first_error (_("can't redefine type for operand"));
1450 atype.defined |= NTA_HASTYPE;
1451 atype.eltype = parsetype;
1454 if (skip_past_char (&str, '[') == SUCCESS)
1456 if (type != REG_TYPE_VFD)
1458 first_error (_("only D registers may be indexed"));
1462 if ((atype.defined & NTA_HASINDEX) != 0)
1464 first_error (_("can't change index for operand"));
1468 atype.defined |= NTA_HASINDEX;
1470 if (skip_past_char (&str, ']') == SUCCESS)
1471 atype.index = NEON_ALL_LANES;
1476 my_get_expression (&exp, &str, GE_NO_PREFIX);
1478 if (exp.X_op != O_constant)
1480 first_error (_("constant expression required"));
1484 if (skip_past_char (&str, ']') == FAIL)
1487 atype.index = exp.X_add_number;
1502 /* Like arm_reg_parse, but allow allow the following extra features:
1503 - If RTYPE is non-zero, return the (possibly restricted) type of the
1504 register (e.g. Neon double or quad reg when either has been requested).
1505 - If this is a Neon vector type with additional type information, fill
1506 in the struct pointed to by VECTYPE (if non-NULL).
1507 This function will fault on encountering a scalar. */
1510 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1511 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1513 struct neon_typed_alias atype;
1515 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1520 /* Do not allow regname(... to parse as a register. */
1524 /* Do not allow a scalar (reg+index) to parse as a register. */
1525 if ((atype.defined & NTA_HASINDEX) != 0)
1527 first_error (_("register operand expected, but got scalar"));
1532 *vectype = atype.eltype;
1539 #define NEON_SCALAR_REG(X) ((X) >> 4)
1540 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1542 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1543 have enough information to be able to do a good job bounds-checking. So, we
1544 just do easy checks here, and do further checks later. */
1547 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1551 struct neon_typed_alias atype;
1553 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1555 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1558 if (atype.index == NEON_ALL_LANES)
1560 first_error (_("scalar must have an index"));
1563 else if (atype.index >= 64 / elsize)
1565 first_error (_("scalar index out of range"));
1570 *type = atype.eltype;
1574 return reg * 16 + atype.index;
1577 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1580 parse_reg_list (char ** strp)
1582 char * str = * strp;
1586 /* We come back here if we get ranges concatenated by '+' or '|'. */
1589 skip_whitespace (str);
1603 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1605 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1615 first_error (_("bad range in register list"));
1619 for (i = cur_reg + 1; i < reg; i++)
1621 if (range & (1 << i))
1623 (_("Warning: duplicated register (r%d) in register list"),
1631 if (range & (1 << reg))
1632 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1634 else if (reg <= cur_reg)
1635 as_tsktsk (_("Warning: register range not in ascending order"));
1640 while (skip_past_comma (&str) != FAIL
1641 || (in_range = 1, *str++ == '-'));
1644 if (skip_past_char (&str, '}') == FAIL)
1646 first_error (_("missing `}'"));
1654 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1657 if (exp.X_op == O_constant)
1659 if (exp.X_add_number
1660 != (exp.X_add_number & 0x0000ffff))
1662 inst.error = _("invalid register mask");
1666 if ((range & exp.X_add_number) != 0)
1668 int regno = range & exp.X_add_number;
1671 regno = (1 << regno) - 1;
1673 (_("Warning: duplicated register (r%d) in register list"),
1677 range |= exp.X_add_number;
1681 if (inst.reloc.type != 0)
1683 inst.error = _("expression too complex");
1687 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1688 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1689 inst.reloc.pc_rel = 0;
1693 if (*str == '|' || *str == '+')
1699 while (another_range);
1705 /* Types of registers in a list. */
1714 /* Parse a VFP register list. If the string is invalid return FAIL.
1715 Otherwise return the number of registers, and set PBASE to the first
1716 register. Parses registers of type ETYPE.
1717 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1718 - Q registers can be used to specify pairs of D registers
1719 - { } can be omitted from around a singleton register list
1720 FIXME: This is not implemented, as it would require backtracking in
1723 This could be done (the meaning isn't really ambiguous), but doesn't
1724 fit in well with the current parsing framework.
1725 - 32 D registers may be used (also true for VFPv3).
1726 FIXME: Types are ignored in these register lists, which is probably a
1730 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1735 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1739 unsigned long mask = 0;
1742 if (skip_past_char (&str, '{') == FAIL)
1744 inst.error = _("expecting {");
1751 regtype = REG_TYPE_VFS;
1756 regtype = REG_TYPE_VFD;
1759 case REGLIST_NEON_D:
1760 regtype = REG_TYPE_NDQ;
1764 if (etype != REGLIST_VFP_S)
1766 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1767 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1771 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1774 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1781 base_reg = max_regs;
1785 int setmask = 1, addregs = 1;
1787 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1789 if (new_base == FAIL)
1791 first_error (_(reg_expected_msgs[regtype]));
1795 if (new_base >= max_regs)
1797 first_error (_("register out of range in list"));
1801 /* Note: a value of 2 * n is returned for the register Q<n>. */
1802 if (regtype == REG_TYPE_NQ)
1808 if (new_base < base_reg)
1809 base_reg = new_base;
1811 if (mask & (setmask << new_base))
1813 first_error (_("invalid register list"));
1817 if ((mask >> new_base) != 0 && ! warned)
1819 as_tsktsk (_("register list not in ascending order"));
1823 mask |= setmask << new_base;
1826 if (*str == '-') /* We have the start of a range expression */
1832 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1835 inst.error = gettext (reg_expected_msgs[regtype]);
1839 if (high_range >= max_regs)
1841 first_error (_("register out of range in list"));
1845 if (regtype == REG_TYPE_NQ)
1846 high_range = high_range + 1;
1848 if (high_range <= new_base)
1850 inst.error = _("register range not in ascending order");
1854 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1856 if (mask & (setmask << new_base))
1858 inst.error = _("invalid register list");
1862 mask |= setmask << new_base;
1867 while (skip_past_comma (&str) != FAIL);
1871 /* Sanity check -- should have raised a parse error above. */
1872 if (count == 0 || count > max_regs)
1877 /* Final test -- the registers must be consecutive. */
1879 for (i = 0; i < count; i++)
1881 if ((mask & (1u << i)) == 0)
1883 inst.error = _("non-contiguous register range");
1893 /* True if two alias types are the same. */
1896 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1904 if (a->defined != b->defined)
1907 if ((a->defined & NTA_HASTYPE) != 0
1908 && (a->eltype.type != b->eltype.type
1909 || a->eltype.size != b->eltype.size))
1912 if ((a->defined & NTA_HASINDEX) != 0
1913 && (a->index != b->index))
1919 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1920 The base register is put in *PBASE.
1921 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1923 The register stride (minus one) is put in bit 4 of the return value.
1924 Bits [6:5] encode the list length (minus one).
1925 The type of the list elements is put in *ELTYPE, if non-NULL. */
1927 #define NEON_LANE(X) ((X) & 0xf)
1928 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1929 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1932 parse_neon_el_struct_list (char **str, unsigned *pbase,
1933 struct neon_type_el *eltype)
1940 int leading_brace = 0;
1941 enum arm_reg_type rtype = REG_TYPE_NDQ;
1942 const char *const incr_error = _("register stride must be 1 or 2");
1943 const char *const type_error = _("mismatched element/structure types in list");
1944 struct neon_typed_alias firsttype;
1946 if (skip_past_char (&ptr, '{') == SUCCESS)
1951 struct neon_typed_alias atype;
1952 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1956 first_error (_(reg_expected_msgs[rtype]));
1963 if (rtype == REG_TYPE_NQ)
1969 else if (reg_incr == -1)
1971 reg_incr = getreg - base_reg;
1972 if (reg_incr < 1 || reg_incr > 2)
1974 first_error (_(incr_error));
1978 else if (getreg != base_reg + reg_incr * count)
1980 first_error (_(incr_error));
1984 if (! neon_alias_types_same (&atype, &firsttype))
1986 first_error (_(type_error));
1990 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1994 struct neon_typed_alias htype;
1995 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1997 lane = NEON_INTERLEAVE_LANES;
1998 else if (lane != NEON_INTERLEAVE_LANES)
2000 first_error (_(type_error));
2005 else if (reg_incr != 1)
2007 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2011 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2014 first_error (_(reg_expected_msgs[rtype]));
2017 if (! neon_alias_types_same (&htype, &firsttype))
2019 first_error (_(type_error));
2022 count += hireg + dregs - getreg;
2026 /* If we're using Q registers, we can't use [] or [n] syntax. */
2027 if (rtype == REG_TYPE_NQ)
2033 if ((atype.defined & NTA_HASINDEX) != 0)
2037 else if (lane != atype.index)
2039 first_error (_(type_error));
2043 else if (lane == -1)
2044 lane = NEON_INTERLEAVE_LANES;
2045 else if (lane != NEON_INTERLEAVE_LANES)
2047 first_error (_(type_error));
2052 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2054 /* No lane set by [x]. We must be interleaving structures. */
2056 lane = NEON_INTERLEAVE_LANES;
2059 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2060 || (count > 1 && reg_incr == -1))
2062 first_error (_("error parsing element/structure list"));
2066 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2068 first_error (_("expected }"));
2076 *eltype = firsttype.eltype;
2081 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2084 /* Parse an explicit relocation suffix on an expression. This is
2085 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2086 arm_reloc_hsh contains no entries, so this function can only
2087 succeed if there is no () after the word. Returns -1 on error,
2088 BFD_RELOC_UNUSED if there wasn't any suffix. */
2091 parse_reloc (char **str)
2093 struct reloc_entry *r;
2097 return BFD_RELOC_UNUSED;
2102 while (*q && *q != ')' && *q != ',')
2107 if ((r = (struct reloc_entry *)
2108 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2115 /* Directives: register aliases. */
2117 static struct reg_entry *
2118 insert_reg_alias (char *str, unsigned number, int type)
2120 struct reg_entry *new_reg;
2123 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2125 if (new_reg->builtin)
2126 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2128 /* Only warn about a redefinition if it's not defined as the
2130 else if (new_reg->number != number || new_reg->type != type)
2131 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2136 name = xstrdup (str);
2137 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2139 new_reg->name = name;
2140 new_reg->number = number;
2141 new_reg->type = type;
2142 new_reg->builtin = FALSE;
2143 new_reg->neon = NULL;
2145 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2152 insert_neon_reg_alias (char *str, int number, int type,
2153 struct neon_typed_alias *atype)
2155 struct reg_entry *reg = insert_reg_alias (str, number, type);
2159 first_error (_("attempt to redefine typed alias"));
2165 reg->neon = (struct neon_typed_alias *)
2166 xmalloc (sizeof (struct neon_typed_alias));
2167 *reg->neon = *atype;
2171 /* Look for the .req directive. This is of the form:
2173 new_register_name .req existing_register_name
2175 If we find one, or if it looks sufficiently like one that we want to
2176 handle any error here, return TRUE. Otherwise return FALSE. */
2179 create_register_alias (char * newname, char *p)
2181 struct reg_entry *old;
2182 char *oldname, *nbuf;
2185 /* The input scrubber ensures that whitespace after the mnemonic is
2186 collapsed to single spaces. */
2188 if (strncmp (oldname, " .req ", 6) != 0)
2192 if (*oldname == '\0')
2195 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2198 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2202 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2203 the desired alias name, and p points to its end. If not, then
2204 the desired alias name is in the global original_case_string. */
2205 #ifdef TC_CASE_SENSITIVE
2208 newname = original_case_string;
2209 nlen = strlen (newname);
2212 nbuf = (char *) alloca (nlen + 1);
2213 memcpy (nbuf, newname, nlen);
2216 /* Create aliases under the new name as stated; an all-lowercase
2217 version of the new name; and an all-uppercase version of the new
2219 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2221 for (p = nbuf; *p; p++)
2224 if (strncmp (nbuf, newname, nlen))
2226 /* If this attempt to create an additional alias fails, do not bother
2227 trying to create the all-lower case alias. We will fail and issue
2228 a second, duplicate error message. This situation arises when the
2229 programmer does something like:
2232 The second .req creates the "Foo" alias but then fails to create
2233 the artificial FOO alias because it has already been created by the
2235 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2239 for (p = nbuf; *p; p++)
2242 if (strncmp (nbuf, newname, nlen))
2243 insert_reg_alias (nbuf, old->number, old->type);
2249 /* Create a Neon typed/indexed register alias using directives, e.g.:
2254 These typed registers can be used instead of the types specified after the
2255 Neon mnemonic, so long as all operands given have types. Types can also be
2256 specified directly, e.g.:
2257 vadd d0.s32, d1.s32, d2.s32 */
2260 create_neon_reg_alias (char *newname, char *p)
2262 enum arm_reg_type basetype;
2263 struct reg_entry *basereg;
2264 struct reg_entry mybasereg;
2265 struct neon_type ntype;
2266 struct neon_typed_alias typeinfo;
2267 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2270 typeinfo.defined = 0;
2271 typeinfo.eltype.type = NT_invtype;
2272 typeinfo.eltype.size = -1;
2273 typeinfo.index = -1;
2277 if (strncmp (p, " .dn ", 5) == 0)
2278 basetype = REG_TYPE_VFD;
2279 else if (strncmp (p, " .qn ", 5) == 0)
2280 basetype = REG_TYPE_NQ;
2289 basereg = arm_reg_parse_multi (&p);
2291 if (basereg && basereg->type != basetype)
2293 as_bad (_("bad type for register"));
2297 if (basereg == NULL)
2300 /* Try parsing as an integer. */
2301 my_get_expression (&exp, &p, GE_NO_PREFIX);
2302 if (exp.X_op != O_constant)
2304 as_bad (_("expression must be constant"));
2307 basereg = &mybasereg;
2308 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2314 typeinfo = *basereg->neon;
2316 if (parse_neon_type (&ntype, &p) == SUCCESS)
2318 /* We got a type. */
2319 if (typeinfo.defined & NTA_HASTYPE)
2321 as_bad (_("can't redefine the type of a register alias"));
2325 typeinfo.defined |= NTA_HASTYPE;
2326 if (ntype.elems != 1)
2328 as_bad (_("you must specify a single type only"));
2331 typeinfo.eltype = ntype.el[0];
2334 if (skip_past_char (&p, '[') == SUCCESS)
2337 /* We got a scalar index. */
2339 if (typeinfo.defined & NTA_HASINDEX)
2341 as_bad (_("can't redefine the index of a scalar alias"));
2345 my_get_expression (&exp, &p, GE_NO_PREFIX);
2347 if (exp.X_op != O_constant)
2349 as_bad (_("scalar index must be constant"));
2353 typeinfo.defined |= NTA_HASINDEX;
2354 typeinfo.index = exp.X_add_number;
2356 if (skip_past_char (&p, ']') == FAIL)
2358 as_bad (_("expecting ]"));
2363 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2364 the desired alias name, and p points to its end. If not, then
2365 the desired alias name is in the global original_case_string. */
2366 #ifdef TC_CASE_SENSITIVE
2367 namelen = nameend - newname;
2369 newname = original_case_string;
2370 namelen = strlen (newname);
2373 namebuf = (char *) alloca (namelen + 1);
2374 strncpy (namebuf, newname, namelen);
2375 namebuf[namelen] = '\0';
2377 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2378 typeinfo.defined != 0 ? &typeinfo : NULL);
2380 /* Insert name in all uppercase. */
2381 for (p = namebuf; *p; p++)
2384 if (strncmp (namebuf, newname, namelen))
2385 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2386 typeinfo.defined != 0 ? &typeinfo : NULL);
2388 /* Insert name in all lowercase. */
2389 for (p = namebuf; *p; p++)
2392 if (strncmp (namebuf, newname, namelen))
2393 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2394 typeinfo.defined != 0 ? &typeinfo : NULL);
2399 /* Should never be called, as .req goes between the alias and the
2400 register name, not at the beginning of the line. */
2403 s_req (int a ATTRIBUTE_UNUSED)
2405 as_bad (_("invalid syntax for .req directive"));
2409 s_dn (int a ATTRIBUTE_UNUSED)
2411 as_bad (_("invalid syntax for .dn directive"));
2415 s_qn (int a ATTRIBUTE_UNUSED)
2417 as_bad (_("invalid syntax for .qn directive"));
2420 /* The .unreq directive deletes an alias which was previously defined
2421 by .req. For example:
2427 s_unreq (int a ATTRIBUTE_UNUSED)
2432 name = input_line_pointer;
2434 while (*input_line_pointer != 0
2435 && *input_line_pointer != ' '
2436 && *input_line_pointer != '\n')
2437 ++input_line_pointer;
2439 saved_char = *input_line_pointer;
2440 *input_line_pointer = 0;
2443 as_bad (_("invalid syntax for .unreq directive"));
2446 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2450 as_bad (_("unknown register alias '%s'"), name);
2451 else if (reg->builtin)
2452 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2459 hash_delete (arm_reg_hsh, name, FALSE);
2460 free ((char *) reg->name);
2465 /* Also locate the all upper case and all lower case versions.
2466 Do not complain if we cannot find one or the other as it
2467 was probably deleted above. */
2469 nbuf = strdup (name);
2470 for (p = nbuf; *p; p++)
2472 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2475 hash_delete (arm_reg_hsh, nbuf, FALSE);
2476 free ((char *) reg->name);
2482 for (p = nbuf; *p; p++)
2484 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2487 hash_delete (arm_reg_hsh, nbuf, FALSE);
2488 free ((char *) reg->name);
2498 *input_line_pointer = saved_char;
2499 demand_empty_rest_of_line ();
2502 /* Directives: Instruction set selection. */
2505 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2506 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2507 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2508 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2510 /* Create a new mapping symbol for the transition to STATE. */
2513 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2516 const char * symname;
2523 type = BSF_NO_FLAGS;
2527 type = BSF_NO_FLAGS;
2531 type = BSF_NO_FLAGS;
2537 symbolP = symbol_new (symname, now_seg, value, frag);
2538 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2543 THUMB_SET_FUNC (symbolP, 0);
2544 ARM_SET_THUMB (symbolP, 0);
2545 ARM_SET_INTERWORK (symbolP, support_interwork);
2549 THUMB_SET_FUNC (symbolP, 1);
2550 ARM_SET_THUMB (symbolP, 1);
2551 ARM_SET_INTERWORK (symbolP, support_interwork);
2559 /* Save the mapping symbols for future reference. Also check that
2560 we do not place two mapping symbols at the same offset within a
2561 frag. We'll handle overlap between frags in
2562 check_mapping_symbols.
2564 If .fill or other data filling directive generates zero sized data,
2565 the mapping symbol for the following code will have the same value
2566 as the one generated for the data filling directive. In this case,
2567 we replace the old symbol with the new one at the same address. */
2570 if (frag->tc_frag_data.first_map != NULL)
2572 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2573 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2575 frag->tc_frag_data.first_map = symbolP;
2577 if (frag->tc_frag_data.last_map != NULL)
2579 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2580 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2581 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2583 frag->tc_frag_data.last_map = symbolP;
2586 /* We must sometimes convert a region marked as code to data during
2587 code alignment, if an odd number of bytes have to be padded. The
2588 code mapping symbol is pushed to an aligned address. */
2591 insert_data_mapping_symbol (enum mstate state,
2592 valueT value, fragS *frag, offsetT bytes)
2594 /* If there was already a mapping symbol, remove it. */
2595 if (frag->tc_frag_data.last_map != NULL
2596 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2598 symbolS *symp = frag->tc_frag_data.last_map;
2602 know (frag->tc_frag_data.first_map == symp);
2603 frag->tc_frag_data.first_map = NULL;
2605 frag->tc_frag_data.last_map = NULL;
2606 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2609 make_mapping_symbol (MAP_DATA, value, frag);
2610 make_mapping_symbol (state, value + bytes, frag);
2613 static void mapping_state_2 (enum mstate state, int max_chars);
2615 /* Set the mapping state to STATE. Only call this when about to
2616 emit some STATE bytes to the file. */
2619 mapping_state (enum mstate state)
2621 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2623 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2625 if (mapstate == state)
2626 /* The mapping symbol has already been emitted.
2627 There is nothing else to do. */
2630 if (state == MAP_ARM || state == MAP_THUMB)
2632 All ARM instructions require 4-byte alignment.
2633 (Almost) all Thumb instructions require 2-byte alignment.
2635 When emitting instructions into any section, mark the section
2638 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2639 but themselves require 2-byte alignment; this applies to some
2640 PC- relative forms. However, these cases will invovle implicit
2641 literal pool generation or an explicit .align >=2, both of
2642 which will cause the section to me marked with sufficient
2643 alignment. Thus, we don't handle those cases here. */
2644 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2646 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2647 /* This case will be evaluated later in the next else. */
2649 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2650 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2652 /* Only add the symbol if the offset is > 0:
2653 if we're at the first frag, check it's size > 0;
2654 if we're not at the first frag, then for sure
2655 the offset is > 0. */
2656 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2657 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2660 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2663 mapping_state_2 (state, 0);
2667 /* Same as mapping_state, but MAX_CHARS bytes have already been
2668 allocated. Put the mapping symbol that far back. */
2671 mapping_state_2 (enum mstate state, int max_chars)
2673 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2675 if (!SEG_NORMAL (now_seg))
2678 if (mapstate == state)
2679 /* The mapping symbol has already been emitted.
2680 There is nothing else to do. */
2683 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2684 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2687 #define mapping_state(x) ((void)0)
2688 #define mapping_state_2(x, y) ((void)0)
2691 /* Find the real, Thumb encoded start of a Thumb function. */
2695 find_real_start (symbolS * symbolP)
2698 const char * name = S_GET_NAME (symbolP);
2699 symbolS * new_target;
2701 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2702 #define STUB_NAME ".real_start_of"
2707 /* The compiler may generate BL instructions to local labels because
2708 it needs to perform a branch to a far away location. These labels
2709 do not have a corresponding ".real_start_of" label. We check
2710 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2711 the ".real_start_of" convention for nonlocal branches. */
2712 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2715 real_start = ACONCAT ((STUB_NAME, name, NULL));
2716 new_target = symbol_find (real_start);
2718 if (new_target == NULL)
2720 as_warn (_("Failed to find real start of function: %s\n"), name);
2721 new_target = symbolP;
2729 opcode_select (int width)
2736 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2737 as_bad (_("selected processor does not support THUMB opcodes"));
2740 /* No need to force the alignment, since we will have been
2741 coming from ARM mode, which is word-aligned. */
2742 record_alignment (now_seg, 1);
2749 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2750 as_bad (_("selected processor does not support ARM opcodes"));
2755 frag_align (2, 0, 0);
2757 record_alignment (now_seg, 1);
2762 as_bad (_("invalid instruction size selected (%d)"), width);
2767 s_arm (int ignore ATTRIBUTE_UNUSED)
2770 demand_empty_rest_of_line ();
2774 s_thumb (int ignore ATTRIBUTE_UNUSED)
2777 demand_empty_rest_of_line ();
2781 s_code (int unused ATTRIBUTE_UNUSED)
2785 temp = get_absolute_expression ();
2790 opcode_select (temp);
2794 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2799 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2801 /* If we are not already in thumb mode go into it, EVEN if
2802 the target processor does not support thumb instructions.
2803 This is used by gcc/config/arm/lib1funcs.asm for example
2804 to compile interworking support functions even if the
2805 target processor should not support interworking. */
2809 record_alignment (now_seg, 1);
2812 demand_empty_rest_of_line ();
2816 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2820 /* The following label is the name/address of the start of a Thumb function.
2821 We need to know this for the interworking support. */
2822 label_is_thumb_function_name = TRUE;
2825 /* Perform a .set directive, but also mark the alias as
2826 being a thumb function. */
2829 s_thumb_set (int equiv)
2831 /* XXX the following is a duplicate of the code for s_set() in read.c
2832 We cannot just call that code as we need to get at the symbol that
2839 /* Especial apologies for the random logic:
2840 This just grew, and could be parsed much more simply!
2842 name = input_line_pointer;
2843 delim = get_symbol_end ();
2844 end_name = input_line_pointer;
2847 if (*input_line_pointer != ',')
2850 as_bad (_("expected comma after name \"%s\""), name);
2852 ignore_rest_of_line ();
2856 input_line_pointer++;
2859 if (name[0] == '.' && name[1] == '\0')
2861 /* XXX - this should not happen to .thumb_set. */
2865 if ((symbolP = symbol_find (name)) == NULL
2866 && (symbolP = md_undefined_symbol (name)) == NULL)
2869 /* When doing symbol listings, play games with dummy fragments living
2870 outside the normal fragment chain to record the file and line info
2872 if (listing & LISTING_SYMBOLS)
2874 extern struct list_info_struct * listing_tail;
2875 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2877 memset (dummy_frag, 0, sizeof (fragS));
2878 dummy_frag->fr_type = rs_fill;
2879 dummy_frag->line = listing_tail;
2880 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2881 dummy_frag->fr_symbol = symbolP;
2885 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2888 /* "set" symbols are local unless otherwise specified. */
2889 SF_SET_LOCAL (symbolP);
2890 #endif /* OBJ_COFF */
2891 } /* Make a new symbol. */
2893 symbol_table_insert (symbolP);
2898 && S_IS_DEFINED (symbolP)
2899 && S_GET_SEGMENT (symbolP) != reg_section)
2900 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2902 pseudo_set (symbolP);
2904 demand_empty_rest_of_line ();
2906 /* XXX Now we come to the Thumb specific bit of code. */
2908 THUMB_SET_FUNC (symbolP, 1);
2909 ARM_SET_THUMB (symbolP, 1);
2910 #if defined OBJ_ELF || defined OBJ_COFF
2911 ARM_SET_INTERWORK (symbolP, support_interwork);
2915 /* Directives: Mode selection. */
2917 /* .syntax [unified|divided] - choose the new unified syntax
2918 (same for Arm and Thumb encoding, modulo slight differences in what
2919 can be represented) or the old divergent syntax for each mode. */
2921 s_syntax (int unused ATTRIBUTE_UNUSED)
2925 name = input_line_pointer;
2926 delim = get_symbol_end ();
2928 if (!strcasecmp (name, "unified"))
2929 unified_syntax = TRUE;
2930 else if (!strcasecmp (name, "divided"))
2931 unified_syntax = FALSE;
2934 as_bad (_("unrecognized syntax mode \"%s\""), name);
2937 *input_line_pointer = delim;
2938 demand_empty_rest_of_line ();
2941 /* Directives: sectioning and alignment. */
2943 /* Same as s_align_ptwo but align 0 => align 2. */
2946 s_align (int unused ATTRIBUTE_UNUSED)
2951 long max_alignment = 15;
2953 temp = get_absolute_expression ();
2954 if (temp > max_alignment)
2955 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2958 as_bad (_("alignment negative. 0 assumed."));
2962 if (*input_line_pointer == ',')
2964 input_line_pointer++;
2965 temp_fill = get_absolute_expression ();
2977 /* Only make a frag if we HAVE to. */
2978 if (temp && !need_pass_2)
2980 if (!fill_p && subseg_text_p (now_seg))
2981 frag_align_code (temp, 0);
2983 frag_align (temp, (int) temp_fill, 0);
2985 demand_empty_rest_of_line ();
2987 record_alignment (now_seg, temp);
2991 s_bss (int ignore ATTRIBUTE_UNUSED)
2993 /* We don't support putting frags in the BSS segment, we fake it by
2994 marking in_bss, then looking at s_skip for clues. */
2995 subseg_set (bss_section, 0);
2996 demand_empty_rest_of_line ();
2998 #ifdef md_elf_section_change_hook
2999 md_elf_section_change_hook ();
3004 s_even (int ignore ATTRIBUTE_UNUSED)
3006 /* Never make frag if expect extra pass. */
3008 frag_align (1, 0, 0);
3010 record_alignment (now_seg, 1);
3012 demand_empty_rest_of_line ();
3015 /* Directives: Literal pools. */
3017 static literal_pool *
3018 find_literal_pool (void)
3020 literal_pool * pool;
3022 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3024 if (pool->section == now_seg
3025 && pool->sub_section == now_subseg)
3032 static literal_pool *
3033 find_or_make_literal_pool (void)
3035 /* Next literal pool ID number. */
3036 static unsigned int latest_pool_num = 1;
3037 literal_pool * pool;
3039 pool = find_literal_pool ();
3043 /* Create a new pool. */
3044 pool = (literal_pool *) xmalloc (sizeof (* pool));
3048 pool->next_free_entry = 0;
3049 pool->section = now_seg;
3050 pool->sub_section = now_subseg;
3051 pool->next = list_of_pools;
3052 pool->symbol = NULL;
3054 /* Add it to the list. */
3055 list_of_pools = pool;
3058 /* New pools, and emptied pools, will have a NULL symbol. */
3059 if (pool->symbol == NULL)
3061 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3062 (valueT) 0, &zero_address_frag);
3063 pool->id = latest_pool_num ++;
3070 /* Add the literal in the global 'inst'
3071 structure to the relevant literal pool. */
3074 add_to_lit_pool (void)
3076 literal_pool * pool;
3079 pool = find_or_make_literal_pool ();
3081 /* Check if this literal value is already in the pool. */
3082 for (entry = 0; entry < pool->next_free_entry; entry ++)
3084 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3085 && (inst.reloc.exp.X_op == O_constant)
3086 && (pool->literals[entry].X_add_number
3087 == inst.reloc.exp.X_add_number)
3088 && (pool->literals[entry].X_unsigned
3089 == inst.reloc.exp.X_unsigned))
3092 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3093 && (inst.reloc.exp.X_op == O_symbol)
3094 && (pool->literals[entry].X_add_number
3095 == inst.reloc.exp.X_add_number)
3096 && (pool->literals[entry].X_add_symbol
3097 == inst.reloc.exp.X_add_symbol)
3098 && (pool->literals[entry].X_op_symbol
3099 == inst.reloc.exp.X_op_symbol))
3103 /* Do we need to create a new entry? */
3104 if (entry == pool->next_free_entry)
3106 if (entry >= MAX_LITERAL_POOL_SIZE)
3108 inst.error = _("literal pool overflow");
3112 pool->literals[entry] = inst.reloc.exp;
3114 /* PR ld/12974: Record the location of the first source line to reference
3115 this entry in the literal pool. If it turns out during linking that the
3116 symbol does not exist we will be able to give an accurate line number for
3117 the (first use of the) missing reference. */
3118 if (debug_type == DEBUG_DWARF2)
3119 dwarf2_where (pool->locs + entry);
3121 pool->next_free_entry += 1;
3124 inst.reloc.exp.X_op = O_symbol;
3125 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3126 inst.reloc.exp.X_add_symbol = pool->symbol;
3131 /* Can't use symbol_new here, so have to create a symbol and then at
3132 a later date assign it a value. Thats what these functions do. */
3135 symbol_locate (symbolS * symbolP,
3136 const char * name, /* It is copied, the caller can modify. */
3137 segT segment, /* Segment identifier (SEG_<something>). */
3138 valueT valu, /* Symbol value. */
3139 fragS * frag) /* Associated fragment. */
3141 unsigned int name_length;
3142 char * preserved_copy_of_name;
3144 name_length = strlen (name) + 1; /* +1 for \0. */
3145 obstack_grow (¬es, name, name_length);
3146 preserved_copy_of_name = (char *) obstack_finish (¬es);
3148 #ifdef tc_canonicalize_symbol_name
3149 preserved_copy_of_name =
3150 tc_canonicalize_symbol_name (preserved_copy_of_name);
3153 S_SET_NAME (symbolP, preserved_copy_of_name);
3155 S_SET_SEGMENT (symbolP, segment);
3156 S_SET_VALUE (symbolP, valu);
3157 symbol_clear_list_pointers (symbolP);
3159 symbol_set_frag (symbolP, frag);
3161 /* Link to end of symbol chain. */
3163 extern int symbol_table_frozen;
3165 if (symbol_table_frozen)
3169 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3171 obj_symbol_new_hook (symbolP);
3173 #ifdef tc_symbol_new_hook
3174 tc_symbol_new_hook (symbolP);
3178 verify_symbol_chain (symbol_rootP, symbol_lastP);
3179 #endif /* DEBUG_SYMS */
3184 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3187 literal_pool * pool;
3190 pool = find_literal_pool ();
3192 || pool->symbol == NULL
3193 || pool->next_free_entry == 0)
3196 mapping_state (MAP_DATA);
3198 /* Align pool as you have word accesses.
3199 Only make a frag if we have to. */
3201 frag_align (2, 0, 0);
3203 record_alignment (now_seg, 2);
3205 sprintf (sym_name, "$$lit_\002%x", pool->id);
3207 symbol_locate (pool->symbol, sym_name, now_seg,
3208 (valueT) frag_now_fix (), frag_now);
3209 symbol_table_insert (pool->symbol);
3211 ARM_SET_THUMB (pool->symbol, thumb_mode);
3213 #if defined OBJ_COFF || defined OBJ_ELF
3214 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3217 for (entry = 0; entry < pool->next_free_entry; entry ++)
3220 if (debug_type == DEBUG_DWARF2)
3221 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3223 /* First output the expression in the instruction to the pool. */
3224 emit_expr (&(pool->literals[entry]), 4); /* .word */
3227 /* Mark the pool as empty. */
3228 pool->next_free_entry = 0;
3229 pool->symbol = NULL;
3233 /* Forward declarations for functions below, in the MD interface
3235 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3236 static valueT create_unwind_entry (int);
3237 static void start_unwind_section (const segT, int);
3238 static void add_unwind_opcode (valueT, int);
3239 static void flush_pending_unwind (void);
3241 /* Directives: Data. */
3244 s_arm_elf_cons (int nbytes)
3248 #ifdef md_flush_pending_output
3249 md_flush_pending_output ();
3252 if (is_it_end_of_statement ())
3254 demand_empty_rest_of_line ();
3258 #ifdef md_cons_align
3259 md_cons_align (nbytes);
3262 mapping_state (MAP_DATA);
3266 char *base = input_line_pointer;
3270 if (exp.X_op != O_symbol)
3271 emit_expr (&exp, (unsigned int) nbytes);
3274 char *before_reloc = input_line_pointer;
3275 reloc = parse_reloc (&input_line_pointer);
3278 as_bad (_("unrecognized relocation suffix"));
3279 ignore_rest_of_line ();
3282 else if (reloc == BFD_RELOC_UNUSED)
3283 emit_expr (&exp, (unsigned int) nbytes);
3286 reloc_howto_type *howto = (reloc_howto_type *)
3287 bfd_reloc_type_lookup (stdoutput,
3288 (bfd_reloc_code_real_type) reloc);
3289 int size = bfd_get_reloc_size (howto);
3291 if (reloc == BFD_RELOC_ARM_PLT32)
3293 as_bad (_("(plt) is only valid on branch targets"));
3294 reloc = BFD_RELOC_UNUSED;
3299 as_bad (_("%s relocations do not fit in %d bytes"),
3300 howto->name, nbytes);
3303 /* We've parsed an expression stopping at O_symbol.
3304 But there may be more expression left now that we
3305 have parsed the relocation marker. Parse it again.
3306 XXX Surely there is a cleaner way to do this. */
3307 char *p = input_line_pointer;
3309 char *save_buf = (char *) alloca (input_line_pointer - base);
3310 memcpy (save_buf, base, input_line_pointer - base);
3311 memmove (base + (input_line_pointer - before_reloc),
3312 base, before_reloc - base);
3314 input_line_pointer = base + (input_line_pointer-before_reloc);
3316 memcpy (base, save_buf, p - base);
3318 offset = nbytes - size;
3319 p = frag_more ((int) nbytes);
3320 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3321 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3326 while (*input_line_pointer++ == ',');
3328 /* Put terminator back into stream. */
3329 input_line_pointer --;
3330 demand_empty_rest_of_line ();
3333 /* Emit an expression containing a 32-bit thumb instruction.
3334 Implementation based on put_thumb32_insn. */
3337 emit_thumb32_expr (expressionS * exp)
3339 expressionS exp_high = *exp;
3341 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3342 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3343 exp->X_add_number &= 0xffff;
3344 emit_expr (exp, (unsigned int) THUMB_SIZE);
3347 /* Guess the instruction size based on the opcode. */
3350 thumb_insn_size (int opcode)
3352 if ((unsigned int) opcode < 0xe800u)
3354 else if ((unsigned int) opcode >= 0xe8000000u)
3361 emit_insn (expressionS *exp, int nbytes)
3365 if (exp->X_op == O_constant)
3370 size = thumb_insn_size (exp->X_add_number);
3374 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3376 as_bad (_(".inst.n operand too big. "\
3377 "Use .inst.w instead"));
3382 if (now_it.state == AUTOMATIC_IT_BLOCK)
3383 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3385 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3387 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3388 emit_thumb32_expr (exp);
3390 emit_expr (exp, (unsigned int) size);
3392 it_fsm_post_encode ();
3396 as_bad (_("cannot determine Thumb instruction size. " \
3397 "Use .inst.n/.inst.w instead"));
3400 as_bad (_("constant expression required"));
3405 /* Like s_arm_elf_cons but do not use md_cons_align and
3406 set the mapping state to MAP_ARM/MAP_THUMB. */
3409 s_arm_elf_inst (int nbytes)
3411 if (is_it_end_of_statement ())
3413 demand_empty_rest_of_line ();
3417 /* Calling mapping_state () here will not change ARM/THUMB,
3418 but will ensure not to be in DATA state. */
3421 mapping_state (MAP_THUMB);
3426 as_bad (_("width suffixes are invalid in ARM mode"));
3427 ignore_rest_of_line ();
3433 mapping_state (MAP_ARM);
3442 if (! emit_insn (& exp, nbytes))
3444 ignore_rest_of_line ();
3448 while (*input_line_pointer++ == ',');
3450 /* Put terminator back into stream. */
3451 input_line_pointer --;
3452 demand_empty_rest_of_line ();
3455 /* Parse a .rel31 directive. */
3458 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3465 if (*input_line_pointer == '1')
3466 highbit = 0x80000000;
3467 else if (*input_line_pointer != '0')
3468 as_bad (_("expected 0 or 1"));
3470 input_line_pointer++;
3471 if (*input_line_pointer != ',')
3472 as_bad (_("missing comma"));
3473 input_line_pointer++;
3475 #ifdef md_flush_pending_output
3476 md_flush_pending_output ();
3479 #ifdef md_cons_align
3483 mapping_state (MAP_DATA);
3488 md_number_to_chars (p, highbit, 4);
3489 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3490 BFD_RELOC_ARM_PREL31);
3492 demand_empty_rest_of_line ();
3495 /* Directives: AEABI stack-unwind tables. */
3497 /* Parse an unwind_fnstart directive. Simply records the current location. */
3500 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3502 demand_empty_rest_of_line ();
3503 if (unwind.proc_start)
3505 as_bad (_("duplicate .fnstart directive"));
3509 /* Mark the start of the function. */
3510 unwind.proc_start = expr_build_dot ();
3512 /* Reset the rest of the unwind info. */
3513 unwind.opcode_count = 0;
3514 unwind.table_entry = NULL;
3515 unwind.personality_routine = NULL;
3516 unwind.personality_index = -1;
3517 unwind.frame_size = 0;
3518 unwind.fp_offset = 0;
3519 unwind.fp_reg = REG_SP;
3521 unwind.sp_restored = 0;
3525 /* Parse a handlerdata directive. Creates the exception handling table entry
3526 for the function. */
3529 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3531 demand_empty_rest_of_line ();
3532 if (!unwind.proc_start)
3533 as_bad (MISSING_FNSTART);
3535 if (unwind.table_entry)
3536 as_bad (_("duplicate .handlerdata directive"));
3538 create_unwind_entry (1);
3541 /* Parse an unwind_fnend directive. Generates the index table entry. */
3544 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3549 unsigned int marked_pr_dependency;
3551 demand_empty_rest_of_line ();
3553 if (!unwind.proc_start)
3555 as_bad (_(".fnend directive without .fnstart"));
3559 /* Add eh table entry. */
3560 if (unwind.table_entry == NULL)
3561 val = create_unwind_entry (0);
3565 /* Add index table entry. This is two words. */
3566 start_unwind_section (unwind.saved_seg, 1);
3567 frag_align (2, 0, 0);
3568 record_alignment (now_seg, 2);
3570 ptr = frag_more (8);
3572 where = frag_now_fix () - 8;
3574 /* Self relative offset of the function start. */
3575 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3576 BFD_RELOC_ARM_PREL31);
3578 /* Indicate dependency on EHABI-defined personality routines to the
3579 linker, if it hasn't been done already. */
3580 marked_pr_dependency
3581 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3582 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3583 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3585 static const char *const name[] =
3587 "__aeabi_unwind_cpp_pr0",
3588 "__aeabi_unwind_cpp_pr1",
3589 "__aeabi_unwind_cpp_pr2"
3591 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3592 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3593 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3594 |= 1 << unwind.personality_index;
3598 /* Inline exception table entry. */
3599 md_number_to_chars (ptr + 4, val, 4);
3601 /* Self relative offset of the table entry. */
3602 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3603 BFD_RELOC_ARM_PREL31);
3605 /* Restore the original section. */
3606 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3608 unwind.proc_start = NULL;
3612 /* Parse an unwind_cantunwind directive. */
3615 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3617 demand_empty_rest_of_line ();
3618 if (!unwind.proc_start)
3619 as_bad (MISSING_FNSTART);
3621 if (unwind.personality_routine || unwind.personality_index != -1)
3622 as_bad (_("personality routine specified for cantunwind frame"));
3624 unwind.personality_index = -2;
3628 /* Parse a personalityindex directive. */
3631 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3635 if (!unwind.proc_start)
3636 as_bad (MISSING_FNSTART);
3638 if (unwind.personality_routine || unwind.personality_index != -1)
3639 as_bad (_("duplicate .personalityindex directive"));
3643 if (exp.X_op != O_constant
3644 || exp.X_add_number < 0 || exp.X_add_number > 15)
3646 as_bad (_("bad personality routine number"));
3647 ignore_rest_of_line ();
3651 unwind.personality_index = exp.X_add_number;
3653 demand_empty_rest_of_line ();
3657 /* Parse a personality directive. */
3660 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3664 if (!unwind.proc_start)
3665 as_bad (MISSING_FNSTART);
3667 if (unwind.personality_routine || unwind.personality_index != -1)
3668 as_bad (_("duplicate .personality directive"));
3670 name = input_line_pointer;
3671 c = get_symbol_end ();
3672 p = input_line_pointer;
3673 unwind.personality_routine = symbol_find_or_make (name);
3675 demand_empty_rest_of_line ();
3679 /* Parse a directive saving core registers. */
3682 s_arm_unwind_save_core (void)
3688 range = parse_reg_list (&input_line_pointer);
3691 as_bad (_("expected register list"));
3692 ignore_rest_of_line ();
3696 demand_empty_rest_of_line ();
3698 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3699 into .unwind_save {..., sp...}. We aren't bothered about the value of
3700 ip because it is clobbered by calls. */
3701 if (unwind.sp_restored && unwind.fp_reg == 12
3702 && (range & 0x3000) == 0x1000)
3704 unwind.opcode_count--;
3705 unwind.sp_restored = 0;
3706 range = (range | 0x2000) & ~0x1000;
3707 unwind.pending_offset = 0;
3713 /* See if we can use the short opcodes. These pop a block of up to 8
3714 registers starting with r4, plus maybe r14. */
3715 for (n = 0; n < 8; n++)
3717 /* Break at the first non-saved register. */
3718 if ((range & (1 << (n + 4))) == 0)
3721 /* See if there are any other bits set. */
3722 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3724 /* Use the long form. */
3725 op = 0x8000 | ((range >> 4) & 0xfff);
3726 add_unwind_opcode (op, 2);
3730 /* Use the short form. */
3732 op = 0xa8; /* Pop r14. */
3734 op = 0xa0; /* Do not pop r14. */
3736 add_unwind_opcode (op, 1);
3743 op = 0xb100 | (range & 0xf);
3744 add_unwind_opcode (op, 2);
3747 /* Record the number of bytes pushed. */
3748 for (n = 0; n < 16; n++)
3750 if (range & (1 << n))
3751 unwind.frame_size += 4;
3756 /* Parse a directive saving FPA registers. */
3759 s_arm_unwind_save_fpa (int reg)
3765 /* Get Number of registers to transfer. */
3766 if (skip_past_comma (&input_line_pointer) != FAIL)
3769 exp.X_op = O_illegal;
3771 if (exp.X_op != O_constant)
3773 as_bad (_("expected , <constant>"));
3774 ignore_rest_of_line ();
3778 num_regs = exp.X_add_number;
3780 if (num_regs < 1 || num_regs > 4)
3782 as_bad (_("number of registers must be in the range [1:4]"));
3783 ignore_rest_of_line ();
3787 demand_empty_rest_of_line ();
3792 op = 0xb4 | (num_regs - 1);
3793 add_unwind_opcode (op, 1);
3798 op = 0xc800 | (reg << 4) | (num_regs - 1);
3799 add_unwind_opcode (op, 2);
3801 unwind.frame_size += num_regs * 12;
3805 /* Parse a directive saving VFP registers for ARMv6 and above. */
3808 s_arm_unwind_save_vfp_armv6 (void)
3813 int num_vfpv3_regs = 0;
3814 int num_regs_below_16;
3816 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3819 as_bad (_("expected register list"));
3820 ignore_rest_of_line ();
3824 demand_empty_rest_of_line ();
3826 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3827 than FSTMX/FLDMX-style ones). */
3829 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3831 num_vfpv3_regs = count;
3832 else if (start + count > 16)
3833 num_vfpv3_regs = start + count - 16;
3835 if (num_vfpv3_regs > 0)
3837 int start_offset = start > 16 ? start - 16 : 0;
3838 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3839 add_unwind_opcode (op, 2);
3842 /* Generate opcode for registers numbered in the range 0 .. 15. */
3843 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3844 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3845 if (num_regs_below_16 > 0)
3847 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3848 add_unwind_opcode (op, 2);
3851 unwind.frame_size += count * 8;
3855 /* Parse a directive saving VFP registers for pre-ARMv6. */
3858 s_arm_unwind_save_vfp (void)
3864 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3867 as_bad (_("expected register list"));
3868 ignore_rest_of_line ();
3872 demand_empty_rest_of_line ();
3877 op = 0xb8 | (count - 1);
3878 add_unwind_opcode (op, 1);
3883 op = 0xb300 | (reg << 4) | (count - 1);
3884 add_unwind_opcode (op, 2);
3886 unwind.frame_size += count * 8 + 4;
3890 /* Parse a directive saving iWMMXt data registers. */
3893 s_arm_unwind_save_mmxwr (void)
3901 if (*input_line_pointer == '{')
3902 input_line_pointer++;
3906 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3910 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3915 as_tsktsk (_("register list not in ascending order"));
3918 if (*input_line_pointer == '-')
3920 input_line_pointer++;
3921 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3924 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3927 else if (reg >= hi_reg)
3929 as_bad (_("bad register range"));
3932 for (; reg < hi_reg; reg++)
3936 while (skip_past_comma (&input_line_pointer) != FAIL);
3938 skip_past_char (&input_line_pointer, '}');
3940 demand_empty_rest_of_line ();
3942 /* Generate any deferred opcodes because we're going to be looking at
3944 flush_pending_unwind ();
3946 for (i = 0; i < 16; i++)
3948 if (mask & (1 << i))
3949 unwind.frame_size += 8;
3952 /* Attempt to combine with a previous opcode. We do this because gcc
3953 likes to output separate unwind directives for a single block of
3955 if (unwind.opcode_count > 0)
3957 i = unwind.opcodes[unwind.opcode_count - 1];
3958 if ((i & 0xf8) == 0xc0)
3961 /* Only merge if the blocks are contiguous. */
3964 if ((mask & 0xfe00) == (1 << 9))
3966 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3967 unwind.opcode_count--;
3970 else if (i == 6 && unwind.opcode_count >= 2)
3972 i = unwind.opcodes[unwind.opcode_count - 2];
3976 op = 0xffff << (reg - 1);
3978 && ((mask & op) == (1u << (reg - 1))))
3980 op = (1 << (reg + i + 1)) - 1;
3981 op &= ~((1 << reg) - 1);
3983 unwind.opcode_count -= 2;
3990 /* We want to generate opcodes in the order the registers have been
3991 saved, ie. descending order. */
3992 for (reg = 15; reg >= -1; reg--)
3994 /* Save registers in blocks. */
3996 || !(mask & (1 << reg)))
3998 /* We found an unsaved reg. Generate opcodes to save the
4005 op = 0xc0 | (hi_reg - 10);
4006 add_unwind_opcode (op, 1);
4011 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4012 add_unwind_opcode (op, 2);
4021 ignore_rest_of_line ();
4025 s_arm_unwind_save_mmxwcg (void)
4032 if (*input_line_pointer == '{')
4033 input_line_pointer++;
4035 skip_whitespace (input_line_pointer);
4039 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4043 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4049 as_tsktsk (_("register list not in ascending order"));
4052 if (*input_line_pointer == '-')
4054 input_line_pointer++;
4055 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4058 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4061 else if (reg >= hi_reg)
4063 as_bad (_("bad register range"));
4066 for (; reg < hi_reg; reg++)
4070 while (skip_past_comma (&input_line_pointer) != FAIL);
4072 skip_past_char (&input_line_pointer, '}');
4074 demand_empty_rest_of_line ();
4076 /* Generate any deferred opcodes because we're going to be looking at
4078 flush_pending_unwind ();
4080 for (reg = 0; reg < 16; reg++)
4082 if (mask & (1 << reg))
4083 unwind.frame_size += 4;
4086 add_unwind_opcode (op, 2);
4089 ignore_rest_of_line ();
4093 /* Parse an unwind_save directive.
4094 If the argument is non-zero, this is a .vsave directive. */
4097 s_arm_unwind_save (int arch_v6)
4100 struct reg_entry *reg;
4101 bfd_boolean had_brace = FALSE;
4103 if (!unwind.proc_start)
4104 as_bad (MISSING_FNSTART);
4106 /* Figure out what sort of save we have. */
4107 peek = input_line_pointer;
4115 reg = arm_reg_parse_multi (&peek);
4119 as_bad (_("register expected"));
4120 ignore_rest_of_line ();
4129 as_bad (_("FPA .unwind_save does not take a register list"));
4130 ignore_rest_of_line ();
4133 input_line_pointer = peek;
4134 s_arm_unwind_save_fpa (reg->number);
4138 s_arm_unwind_save_core ();
4143 s_arm_unwind_save_vfp_armv6 ();
4145 s_arm_unwind_save_vfp ();
4148 case REG_TYPE_MMXWR:
4149 s_arm_unwind_save_mmxwr ();
4152 case REG_TYPE_MMXWCG:
4153 s_arm_unwind_save_mmxwcg ();
4157 as_bad (_(".unwind_save does not support this kind of register"));
4158 ignore_rest_of_line ();
4163 /* Parse an unwind_movsp directive. */
4166 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4172 if (!unwind.proc_start)
4173 as_bad (MISSING_FNSTART);
4175 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4178 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4179 ignore_rest_of_line ();
4183 /* Optional constant. */
4184 if (skip_past_comma (&input_line_pointer) != FAIL)
4186 if (immediate_for_directive (&offset) == FAIL)
4192 demand_empty_rest_of_line ();
4194 if (reg == REG_SP || reg == REG_PC)
4196 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4200 if (unwind.fp_reg != REG_SP)
4201 as_bad (_("unexpected .unwind_movsp directive"));
4203 /* Generate opcode to restore the value. */
4205 add_unwind_opcode (op, 1);
4207 /* Record the information for later. */
4208 unwind.fp_reg = reg;
4209 unwind.fp_offset = unwind.frame_size - offset;
4210 unwind.sp_restored = 1;
4213 /* Parse an unwind_pad directive. */
4216 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4220 if (!unwind.proc_start)
4221 as_bad (MISSING_FNSTART);
4223 if (immediate_for_directive (&offset) == FAIL)
4228 as_bad (_("stack increment must be multiple of 4"));
4229 ignore_rest_of_line ();
4233 /* Don't generate any opcodes, just record the details for later. */
4234 unwind.frame_size += offset;
4235 unwind.pending_offset += offset;
4237 demand_empty_rest_of_line ();
4240 /* Parse an unwind_setfp directive. */
4243 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4249 if (!unwind.proc_start)
4250 as_bad (MISSING_FNSTART);
4252 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4253 if (skip_past_comma (&input_line_pointer) == FAIL)
4256 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4258 if (fp_reg == FAIL || sp_reg == FAIL)
4260 as_bad (_("expected <reg>, <reg>"));
4261 ignore_rest_of_line ();
4265 /* Optional constant. */
4266 if (skip_past_comma (&input_line_pointer) != FAIL)
4268 if (immediate_for_directive (&offset) == FAIL)
4274 demand_empty_rest_of_line ();
4276 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4278 as_bad (_("register must be either sp or set by a previous"
4279 "unwind_movsp directive"));
4283 /* Don't generate any opcodes, just record the information for later. */
4284 unwind.fp_reg = fp_reg;
4286 if (sp_reg == REG_SP)
4287 unwind.fp_offset = unwind.frame_size - offset;
4289 unwind.fp_offset -= offset;
4292 /* Parse an unwind_raw directive. */
4295 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4298 /* This is an arbitrary limit. */
4299 unsigned char op[16];
4302 if (!unwind.proc_start)
4303 as_bad (MISSING_FNSTART);
4306 if (exp.X_op == O_constant
4307 && skip_past_comma (&input_line_pointer) != FAIL)
4309 unwind.frame_size += exp.X_add_number;
4313 exp.X_op = O_illegal;
4315 if (exp.X_op != O_constant)
4317 as_bad (_("expected <offset>, <opcode>"));
4318 ignore_rest_of_line ();
4324 /* Parse the opcode. */
4329 as_bad (_("unwind opcode too long"));
4330 ignore_rest_of_line ();
4332 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4334 as_bad (_("invalid unwind opcode"));
4335 ignore_rest_of_line ();
4338 op[count++] = exp.X_add_number;
4340 /* Parse the next byte. */
4341 if (skip_past_comma (&input_line_pointer) == FAIL)
4347 /* Add the opcode bytes in reverse order. */
4349 add_unwind_opcode (op[count], 1);
4351 demand_empty_rest_of_line ();
4355 /* Parse a .eabi_attribute directive. */
4358 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4360 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4362 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4363 attributes_set_explicitly[tag] = 1;
4366 /* Emit a tls fix for the symbol. */
4369 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4373 #ifdef md_flush_pending_output
4374 md_flush_pending_output ();
4377 #ifdef md_cons_align
4381 /* Since we're just labelling the code, there's no need to define a
4384 p = obstack_next_free (&frchain_now->frch_obstack);
4385 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4386 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4387 : BFD_RELOC_ARM_TLS_DESCSEQ);
4389 #endif /* OBJ_ELF */
4391 static void s_arm_arch (int);
4392 static void s_arm_object_arch (int);
4393 static void s_arm_cpu (int);
4394 static void s_arm_fpu (int);
4395 static void s_arm_arch_extension (int);
4400 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4407 if (exp.X_op == O_symbol)
4408 exp.X_op = O_secrel;
4410 emit_expr (&exp, 4);
4412 while (*input_line_pointer++ == ',');
4414 input_line_pointer--;
4415 demand_empty_rest_of_line ();
4419 /* This table describes all the machine specific pseudo-ops the assembler
4420 has to support. The fields are:
4421 pseudo-op name without dot
4422 function to call to execute this pseudo-op
4423 Integer arg to pass to the function. */
4425 const pseudo_typeS md_pseudo_table[] =
4427 /* Never called because '.req' does not start a line. */
4428 { "req", s_req, 0 },
4429 /* Following two are likewise never called. */
4432 { "unreq", s_unreq, 0 },
4433 { "bss", s_bss, 0 },
4434 { "align", s_align, 0 },
4435 { "arm", s_arm, 0 },
4436 { "thumb", s_thumb, 0 },
4437 { "code", s_code, 0 },
4438 { "force_thumb", s_force_thumb, 0 },
4439 { "thumb_func", s_thumb_func, 0 },
4440 { "thumb_set", s_thumb_set, 0 },
4441 { "even", s_even, 0 },
4442 { "ltorg", s_ltorg, 0 },
4443 { "pool", s_ltorg, 0 },
4444 { "syntax", s_syntax, 0 },
4445 { "cpu", s_arm_cpu, 0 },
4446 { "arch", s_arm_arch, 0 },
4447 { "object_arch", s_arm_object_arch, 0 },
4448 { "fpu", s_arm_fpu, 0 },
4449 { "arch_extension", s_arm_arch_extension, 0 },
4451 { "word", s_arm_elf_cons, 4 },
4452 { "long", s_arm_elf_cons, 4 },
4453 { "inst.n", s_arm_elf_inst, 2 },
4454 { "inst.w", s_arm_elf_inst, 4 },
4455 { "inst", s_arm_elf_inst, 0 },
4456 { "rel31", s_arm_rel31, 0 },
4457 { "fnstart", s_arm_unwind_fnstart, 0 },
4458 { "fnend", s_arm_unwind_fnend, 0 },
4459 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4460 { "personality", s_arm_unwind_personality, 0 },
4461 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4462 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4463 { "save", s_arm_unwind_save, 0 },
4464 { "vsave", s_arm_unwind_save, 1 },
4465 { "movsp", s_arm_unwind_movsp, 0 },
4466 { "pad", s_arm_unwind_pad, 0 },
4467 { "setfp", s_arm_unwind_setfp, 0 },
4468 { "unwind_raw", s_arm_unwind_raw, 0 },
4469 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4470 { "tlsdescseq", s_arm_tls_descseq, 0 },
4474 /* These are used for dwarf. */
4478 /* These are used for dwarf2. */
4479 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4480 { "loc", dwarf2_directive_loc, 0 },
4481 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4483 { "extend", float_cons, 'x' },
4484 { "ldouble", float_cons, 'x' },
4485 { "packed", float_cons, 'p' },
4487 {"secrel32", pe_directive_secrel, 0},
4492 /* Parser functions used exclusively in instruction operands. */
4494 /* Generic immediate-value read function for use in insn parsing.
4495 STR points to the beginning of the immediate (the leading #);
4496 VAL receives the value; if the value is outside [MIN, MAX]
4497 issue an error. PREFIX_OPT is true if the immediate prefix is
4501 parse_immediate (char **str, int *val, int min, int max,
4502 bfd_boolean prefix_opt)
4505 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4506 if (exp.X_op != O_constant)
4508 inst.error = _("constant expression required");
4512 if (exp.X_add_number < min || exp.X_add_number > max)
4514 inst.error = _("immediate value out of range");
4518 *val = exp.X_add_number;
4522 /* Less-generic immediate-value read function with the possibility of loading a
4523 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4524 instructions. Puts the result directly in inst.operands[i]. */
4527 parse_big_immediate (char **str, int i)
4532 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4534 if (exp.X_op == O_constant)
4536 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4537 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4538 O_constant. We have to be careful not to break compilation for
4539 32-bit X_add_number, though. */
4540 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4542 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4543 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4544 inst.operands[i].regisimm = 1;
4547 else if (exp.X_op == O_big
4548 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4550 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4552 /* Bignums have their least significant bits in
4553 generic_bignum[0]. Make sure we put 32 bits in imm and
4554 32 bits in reg, in a (hopefully) portable way. */
4555 gas_assert (parts != 0);
4557 /* Make sure that the number is not too big.
4558 PR 11972: Bignums can now be sign-extended to the
4559 size of a .octa so check that the out of range bits
4560 are all zero or all one. */
4561 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4563 LITTLENUM_TYPE m = -1;
4565 if (generic_bignum[parts * 2] != 0
4566 && generic_bignum[parts * 2] != m)
4569 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4570 if (generic_bignum[j] != generic_bignum[j-1])
4574 inst.operands[i].imm = 0;
4575 for (j = 0; j < parts; j++, idx++)
4576 inst.operands[i].imm |= generic_bignum[idx]
4577 << (LITTLENUM_NUMBER_OF_BITS * j);
4578 inst.operands[i].reg = 0;
4579 for (j = 0; j < parts; j++, idx++)
4580 inst.operands[i].reg |= generic_bignum[idx]
4581 << (LITTLENUM_NUMBER_OF_BITS * j);
4582 inst.operands[i].regisimm = 1;
4592 /* Returns the pseudo-register number of an FPA immediate constant,
4593 or FAIL if there isn't a valid constant here. */
4596 parse_fpa_immediate (char ** str)
4598 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4604 /* First try and match exact strings, this is to guarantee
4605 that some formats will work even for cross assembly. */
4607 for (i = 0; fp_const[i]; i++)
4609 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4613 *str += strlen (fp_const[i]);
4614 if (is_end_of_line[(unsigned char) **str])
4620 /* Just because we didn't get a match doesn't mean that the constant
4621 isn't valid, just that it is in a format that we don't
4622 automatically recognize. Try parsing it with the standard
4623 expression routines. */
4625 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4627 /* Look for a raw floating point number. */
4628 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4629 && is_end_of_line[(unsigned char) *save_in])
4631 for (i = 0; i < NUM_FLOAT_VALS; i++)
4633 for (j = 0; j < MAX_LITTLENUMS; j++)
4635 if (words[j] != fp_values[i][j])
4639 if (j == MAX_LITTLENUMS)
4647 /* Try and parse a more complex expression, this will probably fail
4648 unless the code uses a floating point prefix (eg "0f"). */
4649 save_in = input_line_pointer;
4650 input_line_pointer = *str;
4651 if (expression (&exp) == absolute_section
4652 && exp.X_op == O_big
4653 && exp.X_add_number < 0)
4655 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4657 if (gen_to_words (words, 5, (long) 15) == 0)
4659 for (i = 0; i < NUM_FLOAT_VALS; i++)
4661 for (j = 0; j < MAX_LITTLENUMS; j++)
4663 if (words[j] != fp_values[i][j])
4667 if (j == MAX_LITTLENUMS)
4669 *str = input_line_pointer;
4670 input_line_pointer = save_in;
4677 *str = input_line_pointer;
4678 input_line_pointer = save_in;
4679 inst.error = _("invalid FPA immediate expression");
4683 /* Returns 1 if a number has "quarter-precision" float format
4684 0baBbbbbbc defgh000 00000000 00000000. */
4687 is_quarter_float (unsigned imm)
4689 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4690 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4693 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4694 0baBbbbbbc defgh000 00000000 00000000.
4695 The zero and minus-zero cases need special handling, since they can't be
4696 encoded in the "quarter-precision" float format, but can nonetheless be
4697 loaded as integer constants. */
4700 parse_qfloat_immediate (char **ccp, int *immed)
4704 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4705 int found_fpchar = 0;
4707 skip_past_char (&str, '#');
4709 /* We must not accidentally parse an integer as a floating-point number. Make
4710 sure that the value we parse is not an integer by checking for special
4711 characters '.' or 'e'.
4712 FIXME: This is a horrible hack, but doing better is tricky because type
4713 information isn't in a very usable state at parse time. */
4715 skip_whitespace (fpnum);
4717 if (strncmp (fpnum, "0x", 2) == 0)
4721 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4722 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4732 if ((str = atof_ieee (str, 's', words)) != NULL)
4734 unsigned fpword = 0;
4737 /* Our FP word must be 32 bits (single-precision FP). */
4738 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4740 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4744 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4757 /* Shift operands. */
4760 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4763 struct asm_shift_name
4766 enum shift_kind kind;
4769 /* Third argument to parse_shift. */
4770 enum parse_shift_mode
4772 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4773 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4774 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4775 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4776 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4779 /* Parse a <shift> specifier on an ARM data processing instruction.
4780 This has three forms:
4782 (LSL|LSR|ASL|ASR|ROR) Rs
4783 (LSL|LSR|ASL|ASR|ROR) #imm
4786 Note that ASL is assimilated to LSL in the instruction encoding, and
4787 RRX to ROR #0 (which cannot be written as such). */
4790 parse_shift (char **str, int i, enum parse_shift_mode mode)
4792 const struct asm_shift_name *shift_name;
4793 enum shift_kind shift;
4798 for (p = *str; ISALPHA (*p); p++)
4803 inst.error = _("shift expression expected");
4807 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4810 if (shift_name == NULL)
4812 inst.error = _("shift expression expected");
4816 shift = shift_name->kind;
4820 case NO_SHIFT_RESTRICT:
4821 case SHIFT_IMMEDIATE: break;
4823 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4824 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4826 inst.error = _("'LSL' or 'ASR' required");
4831 case SHIFT_LSL_IMMEDIATE:
4832 if (shift != SHIFT_LSL)
4834 inst.error = _("'LSL' required");
4839 case SHIFT_ASR_IMMEDIATE:
4840 if (shift != SHIFT_ASR)
4842 inst.error = _("'ASR' required");
4850 if (shift != SHIFT_RRX)
4852 /* Whitespace can appear here if the next thing is a bare digit. */
4853 skip_whitespace (p);
4855 if (mode == NO_SHIFT_RESTRICT
4856 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4858 inst.operands[i].imm = reg;
4859 inst.operands[i].immisreg = 1;
4861 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4864 inst.operands[i].shift_kind = shift;
4865 inst.operands[i].shifted = 1;
4870 /* Parse a <shifter_operand> for an ARM data processing instruction:
4873 #<immediate>, <rotate>
4877 where <shift> is defined by parse_shift above, and <rotate> is a
4878 multiple of 2 between 0 and 30. Validation of immediate operands
4879 is deferred to md_apply_fix. */
4882 parse_shifter_operand (char **str, int i)
4887 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4889 inst.operands[i].reg = value;
4890 inst.operands[i].isreg = 1;
4892 /* parse_shift will override this if appropriate */
4893 inst.reloc.exp.X_op = O_constant;
4894 inst.reloc.exp.X_add_number = 0;
4896 if (skip_past_comma (str) == FAIL)
4899 /* Shift operation on register. */
4900 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4903 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4906 if (skip_past_comma (str) == SUCCESS)
4908 /* #x, y -- ie explicit rotation by Y. */
4909 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4912 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4914 inst.error = _("constant expression expected");
4918 value = exp.X_add_number;
4919 if (value < 0 || value > 30 || value % 2 != 0)
4921 inst.error = _("invalid rotation");
4924 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4926 inst.error = _("invalid constant");
4930 /* Encode as specified. */
4931 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4935 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4936 inst.reloc.pc_rel = 0;
4940 /* Group relocation information. Each entry in the table contains the
4941 textual name of the relocation as may appear in assembler source
4942 and must end with a colon.
4943 Along with this textual name are the relocation codes to be used if
4944 the corresponding instruction is an ALU instruction (ADD or SUB only),
4945 an LDR, an LDRS, or an LDC. */
4947 struct group_reloc_table_entry
4958 /* Varieties of non-ALU group relocation. */
4965 static struct group_reloc_table_entry group_reloc_table[] =
4966 { /* Program counter relative: */
4968 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4973 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4974 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4975 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4976 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4978 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4983 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4984 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4985 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4986 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4988 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4989 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4990 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4991 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4992 /* Section base relative */
4994 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4999 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5000 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5001 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5002 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5004 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5009 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5010 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5011 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5012 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5014 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5015 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5016 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5017 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5019 /* Given the address of a pointer pointing to the textual name of a group
5020 relocation as may appear in assembler source, attempt to find its details
5021 in group_reloc_table. The pointer will be updated to the character after
5022 the trailing colon. On failure, FAIL will be returned; SUCCESS
5023 otherwise. On success, *entry will be updated to point at the relevant
5024 group_reloc_table entry. */
5027 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5030 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5032 int length = strlen (group_reloc_table[i].name);
5034 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5035 && (*str)[length] == ':')
5037 *out = &group_reloc_table[i];
5038 *str += (length + 1);
5046 /* Parse a <shifter_operand> for an ARM data processing instruction
5047 (as for parse_shifter_operand) where group relocations are allowed:
5050 #<immediate>, <rotate>
5051 #:<group_reloc>:<expression>
5055 where <group_reloc> is one of the strings defined in group_reloc_table.
5056 The hashes are optional.
5058 Everything else is as for parse_shifter_operand. */
5060 static parse_operand_result
5061 parse_shifter_operand_group_reloc (char **str, int i)
5063 /* Determine if we have the sequence of characters #: or just :
5064 coming next. If we do, then we check for a group relocation.
5065 If we don't, punt the whole lot to parse_shifter_operand. */
5067 if (((*str)[0] == '#' && (*str)[1] == ':')
5068 || (*str)[0] == ':')
5070 struct group_reloc_table_entry *entry;
5072 if ((*str)[0] == '#')
5077 /* Try to parse a group relocation. Anything else is an error. */
5078 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5080 inst.error = _("unknown group relocation");
5081 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5084 /* We now have the group relocation table entry corresponding to
5085 the name in the assembler source. Next, we parse the expression. */
5086 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5087 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5089 /* Record the relocation type (always the ALU variant here). */
5090 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5091 gas_assert (inst.reloc.type != 0);
5093 return PARSE_OPERAND_SUCCESS;
5096 return parse_shifter_operand (str, i) == SUCCESS
5097 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5099 /* Never reached. */
5102 /* Parse a Neon alignment expression. Information is written to
5103 inst.operands[i]. We assume the initial ':' has been skipped.
5105 align .imm = align << 8, .immisalign=1, .preind=0 */
5106 static parse_operand_result
5107 parse_neon_alignment (char **str, int i)
5112 my_get_expression (&exp, &p, GE_NO_PREFIX);
5114 if (exp.X_op != O_constant)
5116 inst.error = _("alignment must be constant");
5117 return PARSE_OPERAND_FAIL;
5120 inst.operands[i].imm = exp.X_add_number << 8;
5121 inst.operands[i].immisalign = 1;
5122 /* Alignments are not pre-indexes. */
5123 inst.operands[i].preind = 0;
5126 return PARSE_OPERAND_SUCCESS;
5129 /* Parse all forms of an ARM address expression. Information is written
5130 to inst.operands[i] and/or inst.reloc.
5132 Preindexed addressing (.preind=1):
5134 [Rn, #offset] .reg=Rn .reloc.exp=offset
5135 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5136 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5137 .shift_kind=shift .reloc.exp=shift_imm
5139 These three may have a trailing ! which causes .writeback to be set also.
5141 Postindexed addressing (.postind=1, .writeback=1):
5143 [Rn], #offset .reg=Rn .reloc.exp=offset
5144 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5145 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5146 .shift_kind=shift .reloc.exp=shift_imm
5148 Unindexed addressing (.preind=0, .postind=0):
5150 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5154 [Rn]{!} shorthand for [Rn,#0]{!}
5155 =immediate .isreg=0 .reloc.exp=immediate
5156 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5158 It is the caller's responsibility to check for addressing modes not
5159 supported by the instruction, and to set inst.reloc.type. */
5161 static parse_operand_result
5162 parse_address_main (char **str, int i, int group_relocations,
5163 group_reloc_type group_type)
5168 if (skip_past_char (&p, '[') == FAIL)
5170 if (skip_past_char (&p, '=') == FAIL)
5172 /* Bare address - translate to PC-relative offset. */
5173 inst.reloc.pc_rel = 1;
5174 inst.operands[i].reg = REG_PC;
5175 inst.operands[i].isreg = 1;
5176 inst.operands[i].preind = 1;
5178 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5180 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5181 return PARSE_OPERAND_FAIL;
5184 return PARSE_OPERAND_SUCCESS;
5187 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5188 skip_whitespace (p);
5190 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5192 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5193 return PARSE_OPERAND_FAIL;
5195 inst.operands[i].reg = reg;
5196 inst.operands[i].isreg = 1;
5198 if (skip_past_comma (&p) == SUCCESS)
5200 inst.operands[i].preind = 1;
5203 else if (*p == '-') p++, inst.operands[i].negative = 1;
5205 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5207 inst.operands[i].imm = reg;
5208 inst.operands[i].immisreg = 1;
5210 if (skip_past_comma (&p) == SUCCESS)
5211 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5212 return PARSE_OPERAND_FAIL;
5214 else if (skip_past_char (&p, ':') == SUCCESS)
5216 /* FIXME: '@' should be used here, but it's filtered out by generic
5217 code before we get to see it here. This may be subject to
5219 parse_operand_result result = parse_neon_alignment (&p, i);
5221 if (result != PARSE_OPERAND_SUCCESS)
5226 if (inst.operands[i].negative)
5228 inst.operands[i].negative = 0;
5232 if (group_relocations
5233 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5235 struct group_reloc_table_entry *entry;
5237 /* Skip over the #: or : sequence. */
5243 /* Try to parse a group relocation. Anything else is an
5245 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5247 inst.error = _("unknown group relocation");
5248 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5251 /* We now have the group relocation table entry corresponding to
5252 the name in the assembler source. Next, we parse the
5254 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5255 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5257 /* Record the relocation type. */
5261 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5265 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5269 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5276 if (inst.reloc.type == 0)
5278 inst.error = _("this group relocation is not allowed on this instruction");
5279 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5285 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5286 return PARSE_OPERAND_FAIL;
5287 /* If the offset is 0, find out if it's a +0 or -0. */
5288 if (inst.reloc.exp.X_op == O_constant
5289 && inst.reloc.exp.X_add_number == 0)
5291 skip_whitespace (q);
5295 skip_whitespace (q);
5298 inst.operands[i].negative = 1;
5303 else if (skip_past_char (&p, ':') == SUCCESS)
5305 /* FIXME: '@' should be used here, but it's filtered out by generic code
5306 before we get to see it here. This may be subject to change. */
5307 parse_operand_result result = parse_neon_alignment (&p, i);
5309 if (result != PARSE_OPERAND_SUCCESS)
5313 if (skip_past_char (&p, ']') == FAIL)
5315 inst.error = _("']' expected");
5316 return PARSE_OPERAND_FAIL;
5319 if (skip_past_char (&p, '!') == SUCCESS)
5320 inst.operands[i].writeback = 1;
5322 else if (skip_past_comma (&p) == SUCCESS)
5324 if (skip_past_char (&p, '{') == SUCCESS)
5326 /* [Rn], {expr} - unindexed, with option */
5327 if (parse_immediate (&p, &inst.operands[i].imm,
5328 0, 255, TRUE) == FAIL)
5329 return PARSE_OPERAND_FAIL;
5331 if (skip_past_char (&p, '}') == FAIL)
5333 inst.error = _("'}' expected at end of 'option' field");
5334 return PARSE_OPERAND_FAIL;
5336 if (inst.operands[i].preind)
5338 inst.error = _("cannot combine index with option");
5339 return PARSE_OPERAND_FAIL;
5342 return PARSE_OPERAND_SUCCESS;
5346 inst.operands[i].postind = 1;
5347 inst.operands[i].writeback = 1;
5349 if (inst.operands[i].preind)
5351 inst.error = _("cannot combine pre- and post-indexing");
5352 return PARSE_OPERAND_FAIL;
5356 else if (*p == '-') p++, inst.operands[i].negative = 1;
5358 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5360 /* We might be using the immediate for alignment already. If we
5361 are, OR the register number into the low-order bits. */
5362 if (inst.operands[i].immisalign)
5363 inst.operands[i].imm |= reg;
5365 inst.operands[i].imm = reg;
5366 inst.operands[i].immisreg = 1;
5368 if (skip_past_comma (&p) == SUCCESS)
5369 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5370 return PARSE_OPERAND_FAIL;
5375 if (inst.operands[i].negative)
5377 inst.operands[i].negative = 0;
5380 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5381 return PARSE_OPERAND_FAIL;
5382 /* If the offset is 0, find out if it's a +0 or -0. */
5383 if (inst.reloc.exp.X_op == O_constant
5384 && inst.reloc.exp.X_add_number == 0)
5386 skip_whitespace (q);
5390 skip_whitespace (q);
5393 inst.operands[i].negative = 1;
5399 /* If at this point neither .preind nor .postind is set, we have a
5400 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5401 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5403 inst.operands[i].preind = 1;
5404 inst.reloc.exp.X_op = O_constant;
5405 inst.reloc.exp.X_add_number = 0;
5408 return PARSE_OPERAND_SUCCESS;
5412 parse_address (char **str, int i)
5414 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5418 static parse_operand_result
5419 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5421 return parse_address_main (str, i, 1, type);
5424 /* Parse an operand for a MOVW or MOVT instruction. */
5426 parse_half (char **str)
5431 skip_past_char (&p, '#');
5432 if (strncasecmp (p, ":lower16:", 9) == 0)
5433 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5434 else if (strncasecmp (p, ":upper16:", 9) == 0)
5435 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5437 if (inst.reloc.type != BFD_RELOC_UNUSED)
5440 skip_whitespace (p);
5443 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5446 if (inst.reloc.type == BFD_RELOC_UNUSED)
5448 if (inst.reloc.exp.X_op != O_constant)
5450 inst.error = _("constant expression expected");
5453 if (inst.reloc.exp.X_add_number < 0
5454 || inst.reloc.exp.X_add_number > 0xffff)
5456 inst.error = _("immediate value out of range");
5464 /* Miscellaneous. */
5466 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5467 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5469 parse_psr (char **str, bfd_boolean lhs)
5472 unsigned long psr_field;
5473 const struct asm_psr *psr;
5475 bfd_boolean is_apsr = FALSE;
5476 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5478 /* PR gas/12698: If the user has specified -march=all then m_profile will
5479 be TRUE, but we want to ignore it in this case as we are building for any
5480 CPU type, including non-m variants. */
5481 if (selected_cpu.core == arm_arch_any.core)
5484 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5485 feature for ease of use and backwards compatibility. */
5487 if (strncasecmp (p, "SPSR", 4) == 0)
5490 goto unsupported_psr;
5492 psr_field = SPSR_BIT;
5494 else if (strncasecmp (p, "CPSR", 4) == 0)
5497 goto unsupported_psr;
5501 else if (strncasecmp (p, "APSR", 4) == 0)
5503 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5504 and ARMv7-R architecture CPUs. */
5513 while (ISALNUM (*p) || *p == '_');
5515 if (strncasecmp (start, "iapsr", 5) == 0
5516 || strncasecmp (start, "eapsr", 5) == 0
5517 || strncasecmp (start, "xpsr", 4) == 0
5518 || strncasecmp (start, "psr", 3) == 0)
5519 p = start + strcspn (start, "rR") + 1;
5521 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5527 /* If APSR is being written, a bitfield may be specified. Note that
5528 APSR itself is handled above. */
5529 if (psr->field <= 3)
5531 psr_field = psr->field;
5537 /* M-profile MSR instructions have the mask field set to "10", except
5538 *PSR variants which modify APSR, which may use a different mask (and
5539 have been handled already). Do that by setting the PSR_f field
5541 return psr->field | (lhs ? PSR_f : 0);
5544 goto unsupported_psr;
5550 /* A suffix follows. */
5556 while (ISALNUM (*p) || *p == '_');
5560 /* APSR uses a notation for bits, rather than fields. */
5561 unsigned int nzcvq_bits = 0;
5562 unsigned int g_bit = 0;
5565 for (bit = start; bit != p; bit++)
5567 switch (TOLOWER (*bit))
5570 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5574 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5578 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5582 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5586 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5590 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5594 inst.error = _("unexpected bit specified after APSR");
5599 if (nzcvq_bits == 0x1f)
5604 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5606 inst.error = _("selected processor does not "
5607 "support DSP extension");
5614 if ((nzcvq_bits & 0x20) != 0
5615 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5616 || (g_bit & 0x2) != 0)
5618 inst.error = _("bad bitmask specified after APSR");
5624 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5629 psr_field |= psr->field;
5635 goto error; /* Garbage after "[CS]PSR". */
5637 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5638 is deprecated, but allow it anyway. */
5642 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5645 else if (!m_profile)
5646 /* These bits are never right for M-profile devices: don't set them
5647 (only code paths which read/write APSR reach here). */
5648 psr_field |= (PSR_c | PSR_f);
5654 inst.error = _("selected processor does not support requested special "
5655 "purpose register");
5659 inst.error = _("flag for {c}psr instruction expected");
5663 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5664 value suitable for splatting into the AIF field of the instruction. */
5667 parse_cps_flags (char **str)
5676 case '\0': case ',':
5679 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5680 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5681 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5684 inst.error = _("unrecognized CPS flag");
5689 if (saw_a_flag == 0)
5691 inst.error = _("missing CPS flags");
5699 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5700 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5703 parse_endian_specifier (char **str)
5708 if (strncasecmp (s, "BE", 2))
5710 else if (strncasecmp (s, "LE", 2))
5714 inst.error = _("valid endian specifiers are be or le");
5718 if (ISALNUM (s[2]) || s[2] == '_')
5720 inst.error = _("valid endian specifiers are be or le");
5725 return little_endian;
5728 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5729 value suitable for poking into the rotate field of an sxt or sxta
5730 instruction, or FAIL on error. */
5733 parse_ror (char **str)
5738 if (strncasecmp (s, "ROR", 3) == 0)
5742 inst.error = _("missing rotation field after comma");
5746 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5751 case 0: *str = s; return 0x0;
5752 case 8: *str = s; return 0x1;
5753 case 16: *str = s; return 0x2;
5754 case 24: *str = s; return 0x3;
5757 inst.error = _("rotation can only be 0, 8, 16, or 24");
5762 /* Parse a conditional code (from conds[] below). The value returned is in the
5763 range 0 .. 14, or FAIL. */
5765 parse_cond (char **str)
5768 const struct asm_cond *c;
5770 /* Condition codes are always 2 characters, so matching up to
5771 3 characters is sufficient. */
5776 while (ISALPHA (*q) && n < 3)
5778 cond[n] = TOLOWER (*q);
5783 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5786 inst.error = _("condition required");
5794 /* If the given feature available in the selected CPU, mark it as used.
5795 Returns TRUE iff feature is available. */
5797 mark_feature_used (const arm_feature_set *feature)
5799 /* Ensure the option is valid on the current architecture. */
5800 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5803 /* Add the appropriate architecture feature for the barrier option used.
5806 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5808 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5813 /* Parse an option for a barrier instruction. Returns the encoding for the
5816 parse_barrier (char **str)
5819 const struct asm_barrier_opt *o;
5822 while (ISALPHA (*q))
5825 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5830 if (!mark_feature_used (&o->arch))
5837 /* Parse the operands of a table branch instruction. Similar to a memory
5840 parse_tb (char **str)
5845 if (skip_past_char (&p, '[') == FAIL)
5847 inst.error = _("'[' expected");
5851 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5853 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5856 inst.operands[0].reg = reg;
5858 if (skip_past_comma (&p) == FAIL)
5860 inst.error = _("',' expected");
5864 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5866 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5869 inst.operands[0].imm = reg;
5871 if (skip_past_comma (&p) == SUCCESS)
5873 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5875 if (inst.reloc.exp.X_add_number != 1)
5877 inst.error = _("invalid shift");
5880 inst.operands[0].shifted = 1;
5883 if (skip_past_char (&p, ']') == FAIL)
5885 inst.error = _("']' expected");
5892 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5893 information on the types the operands can take and how they are encoded.
5894 Up to four operands may be read; this function handles setting the
5895 ".present" field for each read operand itself.
5896 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5897 else returns FAIL. */
5900 parse_neon_mov (char **str, int *which_operand)
5902 int i = *which_operand, val;
5903 enum arm_reg_type rtype;
5905 struct neon_type_el optype;
5907 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5909 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5910 inst.operands[i].reg = val;
5911 inst.operands[i].isscalar = 1;
5912 inst.operands[i].vectype = optype;
5913 inst.operands[i++].present = 1;
5915 if (skip_past_comma (&ptr) == FAIL)
5918 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5921 inst.operands[i].reg = val;
5922 inst.operands[i].isreg = 1;
5923 inst.operands[i].present = 1;
5925 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5928 /* Cases 0, 1, 2, 3, 5 (D only). */
5929 if (skip_past_comma (&ptr) == FAIL)
5932 inst.operands[i].reg = val;
5933 inst.operands[i].isreg = 1;
5934 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5935 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5936 inst.operands[i].isvec = 1;
5937 inst.operands[i].vectype = optype;
5938 inst.operands[i++].present = 1;
5940 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5942 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5943 Case 13: VMOV <Sd>, <Rm> */
5944 inst.operands[i].reg = val;
5945 inst.operands[i].isreg = 1;
5946 inst.operands[i].present = 1;
5948 if (rtype == REG_TYPE_NQ)
5950 first_error (_("can't use Neon quad register here"));
5953 else if (rtype != REG_TYPE_VFS)
5956 if (skip_past_comma (&ptr) == FAIL)
5958 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5960 inst.operands[i].reg = val;
5961 inst.operands[i].isreg = 1;
5962 inst.operands[i].present = 1;
5965 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5968 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5969 Case 1: VMOV<c><q> <Dd>, <Dm>
5970 Case 8: VMOV.F32 <Sd>, <Sm>
5971 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5973 inst.operands[i].reg = val;
5974 inst.operands[i].isreg = 1;
5975 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5976 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5977 inst.operands[i].isvec = 1;
5978 inst.operands[i].vectype = optype;
5979 inst.operands[i].present = 1;
5981 if (skip_past_comma (&ptr) == SUCCESS)
5986 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5989 inst.operands[i].reg = val;
5990 inst.operands[i].isreg = 1;
5991 inst.operands[i++].present = 1;
5993 if (skip_past_comma (&ptr) == FAIL)
5996 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5999 inst.operands[i].reg = val;
6000 inst.operands[i].isreg = 1;
6001 inst.operands[i].present = 1;
6004 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6005 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6006 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6007 Case 10: VMOV.F32 <Sd>, #<imm>
6008 Case 11: VMOV.F64 <Dd>, #<imm> */
6009 inst.operands[i].immisfloat = 1;
6010 else if (parse_big_immediate (&ptr, i) == SUCCESS)
6011 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6012 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6016 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6020 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6023 inst.operands[i].reg = val;
6024 inst.operands[i].isreg = 1;
6025 inst.operands[i++].present = 1;
6027 if (skip_past_comma (&ptr) == FAIL)
6030 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6032 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6033 inst.operands[i].reg = val;
6034 inst.operands[i].isscalar = 1;
6035 inst.operands[i].present = 1;
6036 inst.operands[i].vectype = optype;
6038 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6040 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6041 inst.operands[i].reg = val;
6042 inst.operands[i].isreg = 1;
6043 inst.operands[i++].present = 1;
6045 if (skip_past_comma (&ptr) == FAIL)
6048 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6051 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6055 inst.operands[i].reg = val;
6056 inst.operands[i].isreg = 1;
6057 inst.operands[i].isvec = 1;
6058 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6059 inst.operands[i].vectype = optype;
6060 inst.operands[i].present = 1;
6062 if (rtype == REG_TYPE_VFS)
6066 if (skip_past_comma (&ptr) == FAIL)
6068 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6071 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6074 inst.operands[i].reg = val;
6075 inst.operands[i].isreg = 1;
6076 inst.operands[i].isvec = 1;
6077 inst.operands[i].issingle = 1;
6078 inst.operands[i].vectype = optype;
6079 inst.operands[i].present = 1;
6082 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6086 inst.operands[i].reg = val;
6087 inst.operands[i].isreg = 1;
6088 inst.operands[i].isvec = 1;
6089 inst.operands[i].issingle = 1;
6090 inst.operands[i].vectype = optype;
6091 inst.operands[i].present = 1;
6096 first_error (_("parse error"));
6100 /* Successfully parsed the operands. Update args. */
6106 first_error (_("expected comma"));
6110 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6114 /* Use this macro when the operand constraints are different
6115 for ARM and THUMB (e.g. ldrd). */
6116 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6117 ((arm_operand) | ((thumb_operand) << 16))
6119 /* Matcher codes for parse_operands. */
6120 enum operand_parse_code
6122 OP_stop, /* end of line */
6124 OP_RR, /* ARM register */
6125 OP_RRnpc, /* ARM register, not r15 */
6126 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6127 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6128 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6129 optional trailing ! */
6130 OP_RRw, /* ARM register, not r15, optional trailing ! */
6131 OP_RCP, /* Coprocessor number */
6132 OP_RCN, /* Coprocessor register */
6133 OP_RF, /* FPA register */
6134 OP_RVS, /* VFP single precision register */
6135 OP_RVD, /* VFP double precision register (0..15) */
6136 OP_RND, /* Neon double precision register (0..31) */
6137 OP_RNQ, /* Neon quad precision register */
6138 OP_RVSD, /* VFP single or double precision register */
6139 OP_RNDQ, /* Neon double or quad precision register */
6140 OP_RNSDQ, /* Neon single, double or quad precision register */
6141 OP_RNSC, /* Neon scalar D[X] */
6142 OP_RVC, /* VFP control register */
6143 OP_RMF, /* Maverick F register */
6144 OP_RMD, /* Maverick D register */
6145 OP_RMFX, /* Maverick FX register */
6146 OP_RMDX, /* Maverick DX register */
6147 OP_RMAX, /* Maverick AX register */
6148 OP_RMDS, /* Maverick DSPSC register */
6149 OP_RIWR, /* iWMMXt wR register */
6150 OP_RIWC, /* iWMMXt wC register */
6151 OP_RIWG, /* iWMMXt wCG register */
6152 OP_RXA, /* XScale accumulator register */
6154 OP_REGLST, /* ARM register list */
6155 OP_VRSLST, /* VFP single-precision register list */
6156 OP_VRDLST, /* VFP double-precision register list */
6157 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6158 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6159 OP_NSTRLST, /* Neon element/structure list */
6161 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6162 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6163 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6164 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6165 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6166 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6167 OP_VMOV, /* Neon VMOV operands. */
6168 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6169 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6170 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6172 OP_I0, /* immediate zero */
6173 OP_I7, /* immediate value 0 .. 7 */
6174 OP_I15, /* 0 .. 15 */
6175 OP_I16, /* 1 .. 16 */
6176 OP_I16z, /* 0 .. 16 */
6177 OP_I31, /* 0 .. 31 */
6178 OP_I31w, /* 0 .. 31, optional trailing ! */
6179 OP_I32, /* 1 .. 32 */
6180 OP_I32z, /* 0 .. 32 */
6181 OP_I63, /* 0 .. 63 */
6182 OP_I63s, /* -64 .. 63 */
6183 OP_I64, /* 1 .. 64 */
6184 OP_I64z, /* 0 .. 64 */
6185 OP_I255, /* 0 .. 255 */
6187 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6188 OP_I7b, /* 0 .. 7 */
6189 OP_I15b, /* 0 .. 15 */
6190 OP_I31b, /* 0 .. 31 */
6192 OP_SH, /* shifter operand */
6193 OP_SHG, /* shifter operand with possible group relocation */
6194 OP_ADDR, /* Memory address expression (any mode) */
6195 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6196 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6197 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6198 OP_EXP, /* arbitrary expression */
6199 OP_EXPi, /* same, with optional immediate prefix */
6200 OP_EXPr, /* same, with optional relocation suffix */
6201 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6203 OP_CPSF, /* CPS flags */
6204 OP_ENDI, /* Endianness specifier */
6205 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6206 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6207 OP_COND, /* conditional code */
6208 OP_TB, /* Table branch. */
6210 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6212 OP_RRnpc_I0, /* ARM register or literal 0 */
6213 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6214 OP_RR_EXi, /* ARM register or expression with imm prefix */
6215 OP_RF_IF, /* FPA register or immediate */
6216 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6217 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6219 /* Optional operands. */
6220 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6221 OP_oI31b, /* 0 .. 31 */
6222 OP_oI32b, /* 1 .. 32 */
6223 OP_oI32z, /* 0 .. 32 */
6224 OP_oIffffb, /* 0 .. 65535 */
6225 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6227 OP_oRR, /* ARM register */
6228 OP_oRRnpc, /* ARM register, not the PC */
6229 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6230 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6231 OP_oRND, /* Optional Neon double precision register */
6232 OP_oRNQ, /* Optional Neon quad precision register */
6233 OP_oRNDQ, /* Optional Neon double or quad precision register */
6234 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6235 OP_oSHll, /* LSL immediate */
6236 OP_oSHar, /* ASR immediate */
6237 OP_oSHllar, /* LSL or ASR immediate */
6238 OP_oROR, /* ROR 0/8/16/24 */
6239 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6241 /* Some pre-defined mixed (ARM/THUMB) operands. */
6242 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6243 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6244 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6246 OP_FIRST_OPTIONAL = OP_oI7b
6249 /* Generic instruction operand parser. This does no encoding and no
6250 semantic validation; it merely squirrels values away in the inst
6251 structure. Returns SUCCESS or FAIL depending on whether the
6252 specified grammar matched. */
6254 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6256 unsigned const int *upat = pattern;
6257 char *backtrack_pos = 0;
6258 const char *backtrack_error = 0;
6259 int i, val = 0, backtrack_index = 0;
6260 enum arm_reg_type rtype;
6261 parse_operand_result result;
6262 unsigned int op_parse_code;
6264 #define po_char_or_fail(chr) \
6267 if (skip_past_char (&str, chr) == FAIL) \
6272 #define po_reg_or_fail(regtype) \
6275 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6276 & inst.operands[i].vectype); \
6279 first_error (_(reg_expected_msgs[regtype])); \
6282 inst.operands[i].reg = val; \
6283 inst.operands[i].isreg = 1; \
6284 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6285 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6286 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6287 || rtype == REG_TYPE_VFD \
6288 || rtype == REG_TYPE_NQ); \
6292 #define po_reg_or_goto(regtype, label) \
6295 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6296 & inst.operands[i].vectype); \
6300 inst.operands[i].reg = val; \
6301 inst.operands[i].isreg = 1; \
6302 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6303 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6304 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6305 || rtype == REG_TYPE_VFD \
6306 || rtype == REG_TYPE_NQ); \
6310 #define po_imm_or_fail(min, max, popt) \
6313 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6315 inst.operands[i].imm = val; \
6319 #define po_scalar_or_goto(elsz, label) \
6322 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6325 inst.operands[i].reg = val; \
6326 inst.operands[i].isscalar = 1; \
6330 #define po_misc_or_fail(expr) \
6338 #define po_misc_or_fail_no_backtrack(expr) \
6342 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6343 backtrack_pos = 0; \
6344 if (result != PARSE_OPERAND_SUCCESS) \
6349 #define po_barrier_or_imm(str) \
6352 val = parse_barrier (&str); \
6353 if (val == FAIL && ! ISALPHA (*str)) \
6356 /* ISB can only take SY as an option. */ \
6357 || ((inst.instruction & 0xf0) == 0x60 \
6360 inst.error = _("invalid barrier type"); \
6361 backtrack_pos = 0; \
6367 skip_whitespace (str);
6369 for (i = 0; upat[i] != OP_stop; i++)
6371 op_parse_code = upat[i];
6372 if (op_parse_code >= 1<<16)
6373 op_parse_code = thumb ? (op_parse_code >> 16)
6374 : (op_parse_code & ((1<<16)-1));
6376 if (op_parse_code >= OP_FIRST_OPTIONAL)
6378 /* Remember where we are in case we need to backtrack. */
6379 gas_assert (!backtrack_pos);
6380 backtrack_pos = str;
6381 backtrack_error = inst.error;
6382 backtrack_index = i;
6385 if (i > 0 && (i > 1 || inst.operands[0].present))
6386 po_char_or_fail (',');
6388 switch (op_parse_code)
6396 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6397 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6398 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6399 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6400 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6401 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6403 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6405 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6407 /* Also accept generic coprocessor regs for unknown registers. */
6409 po_reg_or_fail (REG_TYPE_CN);
6411 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6412 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6413 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6414 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6415 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6416 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6417 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6418 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6419 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6420 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6422 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6424 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6425 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6427 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6429 /* Neon scalar. Using an element size of 8 means that some invalid
6430 scalars are accepted here, so deal with those in later code. */
6431 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6435 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6438 po_imm_or_fail (0, 0, TRUE);
6443 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6448 po_scalar_or_goto (8, try_rr);
6451 po_reg_or_fail (REG_TYPE_RN);
6457 po_scalar_or_goto (8, try_nsdq);
6460 po_reg_or_fail (REG_TYPE_NSDQ);
6466 po_scalar_or_goto (8, try_ndq);
6469 po_reg_or_fail (REG_TYPE_NDQ);
6475 po_scalar_or_goto (8, try_vfd);
6478 po_reg_or_fail (REG_TYPE_VFD);
6483 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6484 not careful then bad things might happen. */
6485 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6490 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6493 /* There's a possibility of getting a 64-bit immediate here, so
6494 we need special handling. */
6495 if (parse_big_immediate (&str, i) == FAIL)
6497 inst.error = _("immediate value is out of range");
6505 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6508 po_imm_or_fail (0, 63, TRUE);
6513 po_char_or_fail ('[');
6514 po_reg_or_fail (REG_TYPE_RN);
6515 po_char_or_fail (']');
6521 po_reg_or_fail (REG_TYPE_RN);
6522 if (skip_past_char (&str, '!') == SUCCESS)
6523 inst.operands[i].writeback = 1;
6527 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6528 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6529 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6530 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6531 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6532 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6533 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6534 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6535 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6536 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6537 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6538 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6540 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6542 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6543 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6545 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6546 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6547 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6548 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6550 /* Immediate variants */
6552 po_char_or_fail ('{');
6553 po_imm_or_fail (0, 255, TRUE);
6554 po_char_or_fail ('}');
6558 /* The expression parser chokes on a trailing !, so we have
6559 to find it first and zap it. */
6562 while (*s && *s != ',')
6567 inst.operands[i].writeback = 1;
6569 po_imm_or_fail (0, 31, TRUE);
6577 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6582 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6587 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6589 if (inst.reloc.exp.X_op == O_symbol)
6591 val = parse_reloc (&str);
6594 inst.error = _("unrecognized relocation suffix");
6597 else if (val != BFD_RELOC_UNUSED)
6599 inst.operands[i].imm = val;
6600 inst.operands[i].hasreloc = 1;
6605 /* Operand for MOVW or MOVT. */
6607 po_misc_or_fail (parse_half (&str));
6610 /* Register or expression. */
6611 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6612 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6614 /* Register or immediate. */
6615 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6616 I0: po_imm_or_fail (0, 0, FALSE); break;
6618 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6620 if (!is_immediate_prefix (*str))
6623 val = parse_fpa_immediate (&str);
6626 /* FPA immediates are encoded as registers 8-15.
6627 parse_fpa_immediate has already applied the offset. */
6628 inst.operands[i].reg = val;
6629 inst.operands[i].isreg = 1;
6632 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6633 I32z: po_imm_or_fail (0, 32, FALSE); break;
6635 /* Two kinds of register. */
6638 struct reg_entry *rege = arm_reg_parse_multi (&str);
6640 || (rege->type != REG_TYPE_MMXWR
6641 && rege->type != REG_TYPE_MMXWC
6642 && rege->type != REG_TYPE_MMXWCG))
6644 inst.error = _("iWMMXt data or control register expected");
6647 inst.operands[i].reg = rege->number;
6648 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6654 struct reg_entry *rege = arm_reg_parse_multi (&str);
6656 || (rege->type != REG_TYPE_MMXWC
6657 && rege->type != REG_TYPE_MMXWCG))
6659 inst.error = _("iWMMXt control register expected");
6662 inst.operands[i].reg = rege->number;
6663 inst.operands[i].isreg = 1;
6668 case OP_CPSF: val = parse_cps_flags (&str); break;
6669 case OP_ENDI: val = parse_endian_specifier (&str); break;
6670 case OP_oROR: val = parse_ror (&str); break;
6671 case OP_COND: val = parse_cond (&str); break;
6672 case OP_oBARRIER_I15:
6673 po_barrier_or_imm (str); break;
6675 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6681 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6682 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6684 inst.error = _("Banked registers are not available with this "
6690 val = parse_psr (&str, op_parse_code == OP_wPSR);
6694 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6697 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6699 if (strncasecmp (str, "APSR_", 5) == 0)
6706 case 'c': found = (found & 1) ? 16 : found | 1; break;
6707 case 'n': found = (found & 2) ? 16 : found | 2; break;
6708 case 'z': found = (found & 4) ? 16 : found | 4; break;
6709 case 'v': found = (found & 8) ? 16 : found | 8; break;
6710 default: found = 16;
6714 inst.operands[i].isvec = 1;
6715 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6716 inst.operands[i].reg = REG_PC;
6723 po_misc_or_fail (parse_tb (&str));
6726 /* Register lists. */
6728 val = parse_reg_list (&str);
6731 inst.operands[1].writeback = 1;
6737 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6741 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6745 /* Allow Q registers too. */
6746 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6751 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6753 inst.operands[i].issingle = 1;
6758 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6763 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6764 &inst.operands[i].vectype);
6767 /* Addressing modes */
6769 po_misc_or_fail (parse_address (&str, i));
6773 po_misc_or_fail_no_backtrack (
6774 parse_address_group_reloc (&str, i, GROUP_LDR));
6778 po_misc_or_fail_no_backtrack (
6779 parse_address_group_reloc (&str, i, GROUP_LDRS));
6783 po_misc_or_fail_no_backtrack (
6784 parse_address_group_reloc (&str, i, GROUP_LDC));
6788 po_misc_or_fail (parse_shifter_operand (&str, i));
6792 po_misc_or_fail_no_backtrack (
6793 parse_shifter_operand_group_reloc (&str, i));
6797 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6801 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6805 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6809 as_fatal (_("unhandled operand code %d"), op_parse_code);
6812 /* Various value-based sanity checks and shared operations. We
6813 do not signal immediate failures for the register constraints;
6814 this allows a syntax error to take precedence. */
6815 switch (op_parse_code)
6823 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6824 inst.error = BAD_PC;
6829 if (inst.operands[i].isreg)
6831 if (inst.operands[i].reg == REG_PC)
6832 inst.error = BAD_PC;
6833 else if (inst.operands[i].reg == REG_SP)
6834 inst.error = BAD_SP;
6839 if (inst.operands[i].isreg
6840 && inst.operands[i].reg == REG_PC
6841 && (inst.operands[i].writeback || thumb))
6842 inst.error = BAD_PC;
6851 case OP_oBARRIER_I15:
6860 inst.operands[i].imm = val;
6867 /* If we get here, this operand was successfully parsed. */
6868 inst.operands[i].present = 1;
6872 inst.error = BAD_ARGS;
6877 /* The parse routine should already have set inst.error, but set a
6878 default here just in case. */
6880 inst.error = _("syntax error");
6884 /* Do not backtrack over a trailing optional argument that
6885 absorbed some text. We will only fail again, with the
6886 'garbage following instruction' error message, which is
6887 probably less helpful than the current one. */
6888 if (backtrack_index == i && backtrack_pos != str
6889 && upat[i+1] == OP_stop)
6892 inst.error = _("syntax error");
6896 /* Try again, skipping the optional argument at backtrack_pos. */
6897 str = backtrack_pos;
6898 inst.error = backtrack_error;
6899 inst.operands[backtrack_index].present = 0;
6900 i = backtrack_index;
6904 /* Check that we have parsed all the arguments. */
6905 if (*str != '\0' && !inst.error)
6906 inst.error = _("garbage following instruction");
6908 return inst.error ? FAIL : SUCCESS;
6911 #undef po_char_or_fail
6912 #undef po_reg_or_fail
6913 #undef po_reg_or_goto
6914 #undef po_imm_or_fail
6915 #undef po_scalar_or_fail
6916 #undef po_barrier_or_imm
6918 /* Shorthand macro for instruction encoding functions issuing errors. */
6919 #define constraint(expr, err) \
6930 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6931 instructions are unpredictable if these registers are used. This
6932 is the BadReg predicate in ARM's Thumb-2 documentation. */
6933 #define reject_bad_reg(reg) \
6935 if (reg == REG_SP || reg == REG_PC) \
6937 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6942 /* If REG is R13 (the stack pointer), warn that its use is
6944 #define warn_deprecated_sp(reg) \
6946 if (warn_on_deprecated && reg == REG_SP) \
6947 as_warn (_("use of r13 is deprecated")); \
6950 /* Functions for operand encoding. ARM, then Thumb. */
6952 #define rotate_left(v, n) (v << n | v >> (32 - n))
6954 /* If VAL can be encoded in the immediate field of an ARM instruction,
6955 return the encoded form. Otherwise, return FAIL. */
6958 encode_arm_immediate (unsigned int val)
6962 for (i = 0; i < 32; i += 2)
6963 if ((a = rotate_left (val, i)) <= 0xff)
6964 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6969 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6970 return the encoded form. Otherwise, return FAIL. */
6972 encode_thumb32_immediate (unsigned int val)
6979 for (i = 1; i <= 24; i++)
6982 if ((val & ~(0xff << i)) == 0)
6983 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6987 if (val == ((a << 16) | a))
6989 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6993 if (val == ((a << 16) | a))
6994 return 0x200 | (a >> 8);
6998 /* Encode a VFP SP or DP register number into inst.instruction. */
7001 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
7003 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
7006 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
7009 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7012 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7017 first_error (_("D register out of range for selected VFP version"));
7025 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7029 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7033 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7037 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7041 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7045 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7053 /* Encode a <shift> in an ARM-format instruction. The immediate,
7054 if any, is handled by md_apply_fix. */
7056 encode_arm_shift (int i)
7058 if (inst.operands[i].shift_kind == SHIFT_RRX)
7059 inst.instruction |= SHIFT_ROR << 5;
7062 inst.instruction |= inst.operands[i].shift_kind << 5;
7063 if (inst.operands[i].immisreg)
7065 inst.instruction |= SHIFT_BY_REG;
7066 inst.instruction |= inst.operands[i].imm << 8;
7069 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7074 encode_arm_shifter_operand (int i)
7076 if (inst.operands[i].isreg)
7078 inst.instruction |= inst.operands[i].reg;
7079 encode_arm_shift (i);
7083 inst.instruction |= INST_IMMEDIATE;
7084 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7085 inst.instruction |= inst.operands[i].imm;
7089 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7091 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7094 Generate an error if the operand is not a register. */
7095 constraint (!inst.operands[i].isreg,
7096 _("Instruction does not support =N addresses"));
7098 inst.instruction |= inst.operands[i].reg << 16;
7100 if (inst.operands[i].preind)
7104 inst.error = _("instruction does not accept preindexed addressing");
7107 inst.instruction |= PRE_INDEX;
7108 if (inst.operands[i].writeback)
7109 inst.instruction |= WRITE_BACK;
7112 else if (inst.operands[i].postind)
7114 gas_assert (inst.operands[i].writeback);
7116 inst.instruction |= WRITE_BACK;
7118 else /* unindexed - only for coprocessor */
7120 inst.error = _("instruction does not accept unindexed addressing");
7124 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7125 && (((inst.instruction & 0x000f0000) >> 16)
7126 == ((inst.instruction & 0x0000f000) >> 12)))
7127 as_warn ((inst.instruction & LOAD_BIT)
7128 ? _("destination register same as write-back base")
7129 : _("source register same as write-back base"));
7132 /* inst.operands[i] was set up by parse_address. Encode it into an
7133 ARM-format mode 2 load or store instruction. If is_t is true,
7134 reject forms that cannot be used with a T instruction (i.e. not
7137 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7139 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7141 encode_arm_addr_mode_common (i, is_t);
7143 if (inst.operands[i].immisreg)
7145 constraint ((inst.operands[i].imm == REG_PC
7146 || (is_pc && inst.operands[i].writeback)),
7148 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7149 inst.instruction |= inst.operands[i].imm;
7150 if (!inst.operands[i].negative)
7151 inst.instruction |= INDEX_UP;
7152 if (inst.operands[i].shifted)
7154 if (inst.operands[i].shift_kind == SHIFT_RRX)
7155 inst.instruction |= SHIFT_ROR << 5;
7158 inst.instruction |= inst.operands[i].shift_kind << 5;
7159 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7163 else /* immediate offset in inst.reloc */
7165 if (is_pc && !inst.reloc.pc_rel)
7167 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7169 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7170 cannot use PC in addressing.
7171 PC cannot be used in writeback addressing, either. */
7172 constraint ((is_t || inst.operands[i].writeback),
7175 /* Use of PC in str is deprecated for ARMv7. */
7176 if (warn_on_deprecated
7178 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7179 as_warn (_("use of PC in this instruction is deprecated"));
7182 if (inst.reloc.type == BFD_RELOC_UNUSED)
7184 /* Prefer + for zero encoded value. */
7185 if (!inst.operands[i].negative)
7186 inst.instruction |= INDEX_UP;
7187 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7192 /* inst.operands[i] was set up by parse_address. Encode it into an
7193 ARM-format mode 3 load or store instruction. Reject forms that
7194 cannot be used with such instructions. If is_t is true, reject
7195 forms that cannot be used with a T instruction (i.e. not
7198 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7200 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7202 inst.error = _("instruction does not accept scaled register index");
7206 encode_arm_addr_mode_common (i, is_t);
7208 if (inst.operands[i].immisreg)
7210 constraint ((inst.operands[i].imm == REG_PC
7211 || (is_t && inst.operands[i].reg == REG_PC)),
7213 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7215 inst.instruction |= inst.operands[i].imm;
7216 if (!inst.operands[i].negative)
7217 inst.instruction |= INDEX_UP;
7219 else /* immediate offset in inst.reloc */
7221 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7222 && inst.operands[i].writeback),
7224 inst.instruction |= HWOFFSET_IMM;
7225 if (inst.reloc.type == BFD_RELOC_UNUSED)
7227 /* Prefer + for zero encoded value. */
7228 if (!inst.operands[i].negative)
7229 inst.instruction |= INDEX_UP;
7231 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7236 /* inst.operands[i] was set up by parse_address. Encode it into an
7237 ARM-format instruction. Reject all forms which cannot be encoded
7238 into a coprocessor load/store instruction. If wb_ok is false,
7239 reject use of writeback; if unind_ok is false, reject use of
7240 unindexed addressing. If reloc_override is not 0, use it instead
7241 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7242 (in which case it is preserved). */
7245 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7247 inst.instruction |= inst.operands[i].reg << 16;
7249 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7251 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7253 gas_assert (!inst.operands[i].writeback);
7256 inst.error = _("instruction does not support unindexed addressing");
7259 inst.instruction |= inst.operands[i].imm;
7260 inst.instruction |= INDEX_UP;
7264 if (inst.operands[i].preind)
7265 inst.instruction |= PRE_INDEX;
7267 if (inst.operands[i].writeback)
7269 if (inst.operands[i].reg == REG_PC)
7271 inst.error = _("pc may not be used with write-back");
7276 inst.error = _("instruction does not support writeback");
7279 inst.instruction |= WRITE_BACK;
7283 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7284 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7285 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7286 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7289 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7291 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7294 /* Prefer + for zero encoded value. */
7295 if (!inst.operands[i].negative)
7296 inst.instruction |= INDEX_UP;
7301 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7302 Determine whether it can be performed with a move instruction; if
7303 it can, convert inst.instruction to that move instruction and
7304 return TRUE; if it can't, convert inst.instruction to a literal-pool
7305 load and return FALSE. If this is not a valid thing to do in the
7306 current context, set inst.error and return TRUE.
7308 inst.operands[i] describes the destination register. */
7311 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7316 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7320 if ((inst.instruction & tbit) == 0)
7322 inst.error = _("invalid pseudo operation");
7325 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7327 inst.error = _("constant expression expected");
7330 if (inst.reloc.exp.X_op == O_constant)
7334 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7336 /* This can be done with a mov(1) instruction. */
7337 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7338 inst.instruction |= inst.reloc.exp.X_add_number;
7344 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7347 /* This can be done with a mov instruction. */
7348 inst.instruction &= LITERAL_MASK;
7349 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7350 inst.instruction |= value & 0xfff;
7354 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7357 /* This can be done with a mvn instruction. */
7358 inst.instruction &= LITERAL_MASK;
7359 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7360 inst.instruction |= value & 0xfff;
7366 if (add_to_lit_pool () == FAIL)
7368 inst.error = _("literal pool insertion failed");
7371 inst.operands[1].reg = REG_PC;
7372 inst.operands[1].isreg = 1;
7373 inst.operands[1].preind = 1;
7374 inst.reloc.pc_rel = 1;
7375 inst.reloc.type = (thumb_p
7376 ? BFD_RELOC_ARM_THUMB_OFFSET
7378 ? BFD_RELOC_ARM_HWLITERAL
7379 : BFD_RELOC_ARM_LITERAL));
7383 /* Functions for instruction encoding, sorted by sub-architecture.
7384 First some generics; their names are taken from the conventional
7385 bit positions for register arguments in ARM format instructions. */
7395 inst.instruction |= inst.operands[0].reg << 12;
7401 inst.instruction |= inst.operands[0].reg << 12;
7402 inst.instruction |= inst.operands[1].reg;
7408 inst.instruction |= inst.operands[0].reg;
7409 inst.instruction |= inst.operands[1].reg << 16;
7415 inst.instruction |= inst.operands[0].reg << 12;
7416 inst.instruction |= inst.operands[1].reg << 16;
7422 inst.instruction |= inst.operands[0].reg << 16;
7423 inst.instruction |= inst.operands[1].reg << 12;
7427 check_obsolete (const arm_feature_set *feature, const char *msg)
7429 if (ARM_CPU_IS_ANY (cpu_variant))
7431 as_warn ("%s", msg);
7434 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7446 unsigned Rn = inst.operands[2].reg;
7447 /* Enforce restrictions on SWP instruction. */
7448 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7450 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7451 _("Rn must not overlap other operands"));
7453 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7455 if (!check_obsolete (&arm_ext_v8,
7456 _("swp{b} use is obsoleted for ARMv8 and later"))
7457 && warn_on_deprecated
7458 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7459 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7462 inst.instruction |= inst.operands[0].reg << 12;
7463 inst.instruction |= inst.operands[1].reg;
7464 inst.instruction |= Rn << 16;
7470 inst.instruction |= inst.operands[0].reg << 12;
7471 inst.instruction |= inst.operands[1].reg << 16;
7472 inst.instruction |= inst.operands[2].reg;
7478 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7479 constraint (((inst.reloc.exp.X_op != O_constant
7480 && inst.reloc.exp.X_op != O_illegal)
7481 || inst.reloc.exp.X_add_number != 0),
7483 inst.instruction |= inst.operands[0].reg;
7484 inst.instruction |= inst.operands[1].reg << 12;
7485 inst.instruction |= inst.operands[2].reg << 16;
7491 inst.instruction |= inst.operands[0].imm;
7497 inst.instruction |= inst.operands[0].reg << 12;
7498 encode_arm_cp_address (1, TRUE, TRUE, 0);
7501 /* ARM instructions, in alphabetical order by function name (except
7502 that wrapper functions appear immediately after the function they
7505 /* This is a pseudo-op of the form "adr rd, label" to be converted
7506 into a relative address of the form "add rd, pc, #label-.-8". */
7511 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7513 /* Frag hacking will turn this into a sub instruction if the offset turns
7514 out to be negative. */
7515 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7516 inst.reloc.pc_rel = 1;
7517 inst.reloc.exp.X_add_number -= 8;
7520 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7521 into a relative address of the form:
7522 add rd, pc, #low(label-.-8)"
7523 add rd, rd, #high(label-.-8)" */
7528 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7530 /* Frag hacking will turn this into a sub instruction if the offset turns
7531 out to be negative. */
7532 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7533 inst.reloc.pc_rel = 1;
7534 inst.size = INSN_SIZE * 2;
7535 inst.reloc.exp.X_add_number -= 8;
7541 if (!inst.operands[1].present)
7542 inst.operands[1].reg = inst.operands[0].reg;
7543 inst.instruction |= inst.operands[0].reg << 12;
7544 inst.instruction |= inst.operands[1].reg << 16;
7545 encode_arm_shifter_operand (2);
7551 if (inst.operands[0].present)
7552 inst.instruction |= inst.operands[0].imm;
7554 inst.instruction |= 0xf;
7560 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7561 constraint (msb > 32, _("bit-field extends past end of register"));
7562 /* The instruction encoding stores the LSB and MSB,
7563 not the LSB and width. */
7564 inst.instruction |= inst.operands[0].reg << 12;
7565 inst.instruction |= inst.operands[1].imm << 7;
7566 inst.instruction |= (msb - 1) << 16;
7574 /* #0 in second position is alternative syntax for bfc, which is
7575 the same instruction but with REG_PC in the Rm field. */
7576 if (!inst.operands[1].isreg)
7577 inst.operands[1].reg = REG_PC;
7579 msb = inst.operands[2].imm + inst.operands[3].imm;
7580 constraint (msb > 32, _("bit-field extends past end of register"));
7581 /* The instruction encoding stores the LSB and MSB,
7582 not the LSB and width. */
7583 inst.instruction |= inst.operands[0].reg << 12;
7584 inst.instruction |= inst.operands[1].reg;
7585 inst.instruction |= inst.operands[2].imm << 7;
7586 inst.instruction |= (msb - 1) << 16;
7592 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7593 _("bit-field extends past end of register"));
7594 inst.instruction |= inst.operands[0].reg << 12;
7595 inst.instruction |= inst.operands[1].reg;
7596 inst.instruction |= inst.operands[2].imm << 7;
7597 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7600 /* ARM V5 breakpoint instruction (argument parse)
7601 BKPT <16 bit unsigned immediate>
7602 Instruction is not conditional.
7603 The bit pattern given in insns[] has the COND_ALWAYS condition,
7604 and it is an error if the caller tried to override that. */
7609 /* Top 12 of 16 bits to bits 19:8. */
7610 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7612 /* Bottom 4 of 16 bits to bits 3:0. */
7613 inst.instruction |= inst.operands[0].imm & 0xf;
7617 encode_branch (int default_reloc)
7619 if (inst.operands[0].hasreloc)
7621 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7622 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7623 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7624 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7625 ? BFD_RELOC_ARM_PLT32
7626 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7629 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7630 inst.reloc.pc_rel = 1;
7637 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7638 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7641 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7648 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7650 if (inst.cond == COND_ALWAYS)
7651 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7653 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7657 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7660 /* ARM V5 branch-link-exchange instruction (argument parse)
7661 BLX <target_addr> ie BLX(1)
7662 BLX{<condition>} <Rm> ie BLX(2)
7663 Unfortunately, there are two different opcodes for this mnemonic.
7664 So, the insns[].value is not used, and the code here zaps values
7665 into inst.instruction.
7666 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7671 if (inst.operands[0].isreg)
7673 /* Arg is a register; the opcode provided by insns[] is correct.
7674 It is not illegal to do "blx pc", just useless. */
7675 if (inst.operands[0].reg == REG_PC)
7676 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7678 inst.instruction |= inst.operands[0].reg;
7682 /* Arg is an address; this instruction cannot be executed
7683 conditionally, and the opcode must be adjusted.
7684 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7685 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7686 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7687 inst.instruction = 0xfa000000;
7688 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7695 bfd_boolean want_reloc;
7697 if (inst.operands[0].reg == REG_PC)
7698 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7700 inst.instruction |= inst.operands[0].reg;
7701 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7702 it is for ARMv4t or earlier. */
7703 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7704 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7708 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7713 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7717 /* ARM v5TEJ. Jump to Jazelle code. */
7722 if (inst.operands[0].reg == REG_PC)
7723 as_tsktsk (_("use of r15 in bxj is not really useful"));
7725 inst.instruction |= inst.operands[0].reg;
7728 /* Co-processor data operation:
7729 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7730 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7734 inst.instruction |= inst.operands[0].reg << 8;
7735 inst.instruction |= inst.operands[1].imm << 20;
7736 inst.instruction |= inst.operands[2].reg << 12;
7737 inst.instruction |= inst.operands[3].reg << 16;
7738 inst.instruction |= inst.operands[4].reg;
7739 inst.instruction |= inst.operands[5].imm << 5;
7745 inst.instruction |= inst.operands[0].reg << 16;
7746 encode_arm_shifter_operand (1);
7749 /* Transfer between coprocessor and ARM registers.
7750 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7755 No special properties. */
7757 struct deprecated_coproc_regs_s
7764 arm_feature_set deprecated;
7765 arm_feature_set obsoleted;
7766 const char *dep_msg;
7767 const char *obs_msg;
7770 #define DEPR_ACCESS_V8 \
7771 N_("This coprocessor register access is deprecated in ARMv8")
7773 /* Table of all deprecated coprocessor registers. */
7774 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7776 {15, 0, 7, 10, 5, /* CP15DMB. */
7777 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7778 DEPR_ACCESS_V8, NULL},
7779 {15, 0, 7, 10, 4, /* CP15DSB. */
7780 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7781 DEPR_ACCESS_V8, NULL},
7782 {15, 0, 7, 5, 4, /* CP15ISB. */
7783 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7784 DEPR_ACCESS_V8, NULL},
7785 {14, 6, 1, 0, 0, /* TEEHBR. */
7786 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7787 DEPR_ACCESS_V8, NULL},
7788 {14, 6, 0, 0, 0, /* TEECR. */
7789 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7790 DEPR_ACCESS_V8, NULL},
7793 #undef DEPR_ACCESS_V8
7795 static const size_t deprecated_coproc_reg_count =
7796 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7804 Rd = inst.operands[2].reg;
7807 if (inst.instruction == 0xee000010
7808 || inst.instruction == 0xfe000010)
7810 reject_bad_reg (Rd);
7813 constraint (Rd == REG_SP, BAD_SP);
7818 if (inst.instruction == 0xe000010)
7819 constraint (Rd == REG_PC, BAD_PC);
7822 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7824 const struct deprecated_coproc_regs_s *r =
7825 deprecated_coproc_regs + i;
7827 if (inst.operands[0].reg == r->cp
7828 && inst.operands[1].imm == r->opc1
7829 && inst.operands[3].reg == r->crn
7830 && inst.operands[4].reg == r->crm
7831 && inst.operands[5].imm == r->opc2)
7833 if (! ARM_CPU_IS_ANY (cpu_variant)
7834 && warn_on_deprecated
7835 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7836 as_warn ("%s", r->dep_msg);
7840 inst.instruction |= inst.operands[0].reg << 8;
7841 inst.instruction |= inst.operands[1].imm << 21;
7842 inst.instruction |= Rd << 12;
7843 inst.instruction |= inst.operands[3].reg << 16;
7844 inst.instruction |= inst.operands[4].reg;
7845 inst.instruction |= inst.operands[5].imm << 5;
7848 /* Transfer between coprocessor register and pair of ARM registers.
7849 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7854 Two XScale instructions are special cases of these:
7856 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7857 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7859 Result unpredictable if Rd or Rn is R15. */
7866 Rd = inst.operands[2].reg;
7867 Rn = inst.operands[3].reg;
7871 reject_bad_reg (Rd);
7872 reject_bad_reg (Rn);
7876 constraint (Rd == REG_PC, BAD_PC);
7877 constraint (Rn == REG_PC, BAD_PC);
7880 inst.instruction |= inst.operands[0].reg << 8;
7881 inst.instruction |= inst.operands[1].imm << 4;
7882 inst.instruction |= Rd << 12;
7883 inst.instruction |= Rn << 16;
7884 inst.instruction |= inst.operands[4].reg;
7890 inst.instruction |= inst.operands[0].imm << 6;
7891 if (inst.operands[1].present)
7893 inst.instruction |= CPSI_MMOD;
7894 inst.instruction |= inst.operands[1].imm;
7901 inst.instruction |= inst.operands[0].imm;
7907 unsigned Rd, Rn, Rm;
7909 Rd = inst.operands[0].reg;
7910 Rn = (inst.operands[1].present
7911 ? inst.operands[1].reg : Rd);
7912 Rm = inst.operands[2].reg;
7914 constraint ((Rd == REG_PC), BAD_PC);
7915 constraint ((Rn == REG_PC), BAD_PC);
7916 constraint ((Rm == REG_PC), BAD_PC);
7918 inst.instruction |= Rd << 16;
7919 inst.instruction |= Rn << 0;
7920 inst.instruction |= Rm << 8;
7926 /* There is no IT instruction in ARM mode. We
7927 process it to do the validation as if in
7928 thumb mode, just in case the code gets
7929 assembled for thumb using the unified syntax. */
7934 set_it_insn_type (IT_INSN);
7935 now_it.mask = (inst.instruction & 0xf) | 0x10;
7936 now_it.cc = inst.operands[0].imm;
7940 /* If there is only one register in the register list,
7941 then return its register number. Otherwise return -1. */
7943 only_one_reg_in_list (int range)
7945 int i = ffs (range) - 1;
7946 return (i > 15 || range != (1 << i)) ? -1 : i;
7950 encode_ldmstm(int from_push_pop_mnem)
7952 int base_reg = inst.operands[0].reg;
7953 int range = inst.operands[1].imm;
7956 inst.instruction |= base_reg << 16;
7957 inst.instruction |= range;
7959 if (inst.operands[1].writeback)
7960 inst.instruction |= LDM_TYPE_2_OR_3;
7962 if (inst.operands[0].writeback)
7964 inst.instruction |= WRITE_BACK;
7965 /* Check for unpredictable uses of writeback. */
7966 if (inst.instruction & LOAD_BIT)
7968 /* Not allowed in LDM type 2. */
7969 if ((inst.instruction & LDM_TYPE_2_OR_3)
7970 && ((range & (1 << REG_PC)) == 0))
7971 as_warn (_("writeback of base register is UNPREDICTABLE"));
7972 /* Only allowed if base reg not in list for other types. */
7973 else if (range & (1 << base_reg))
7974 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7978 /* Not allowed for type 2. */
7979 if (inst.instruction & LDM_TYPE_2_OR_3)
7980 as_warn (_("writeback of base register is UNPREDICTABLE"));
7981 /* Only allowed if base reg not in list, or first in list. */
7982 else if ((range & (1 << base_reg))
7983 && (range & ((1 << base_reg) - 1)))
7984 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7988 /* If PUSH/POP has only one register, then use the A2 encoding. */
7989 one_reg = only_one_reg_in_list (range);
7990 if (from_push_pop_mnem && one_reg >= 0)
7992 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7994 inst.instruction &= A_COND_MASK;
7995 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7996 inst.instruction |= one_reg << 12;
8003 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
8006 /* ARMv5TE load-consecutive (argument parse)
8015 constraint (inst.operands[0].reg % 2 != 0,
8016 _("first transfer register must be even"));
8017 constraint (inst.operands[1].present
8018 && inst.operands[1].reg != inst.operands[0].reg + 1,
8019 _("can only transfer two consecutive registers"));
8020 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8021 constraint (!inst.operands[2].isreg, _("'[' expected"));
8023 if (!inst.operands[1].present)
8024 inst.operands[1].reg = inst.operands[0].reg + 1;
8026 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8027 register and the first register written; we have to diagnose
8028 overlap between the base and the second register written here. */
8030 if (inst.operands[2].reg == inst.operands[1].reg
8031 && (inst.operands[2].writeback || inst.operands[2].postind))
8032 as_warn (_("base register written back, and overlaps "
8033 "second transfer register"));
8035 if (!(inst.instruction & V4_STR_BIT))
8037 /* For an index-register load, the index register must not overlap the
8038 destination (even if not write-back). */
8039 if (inst.operands[2].immisreg
8040 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8041 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8042 as_warn (_("index register overlaps transfer register"));
8044 inst.instruction |= inst.operands[0].reg << 12;
8045 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8051 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8052 || inst.operands[1].postind || inst.operands[1].writeback
8053 || inst.operands[1].immisreg || inst.operands[1].shifted
8054 || inst.operands[1].negative
8055 /* This can arise if the programmer has written
8057 or if they have mistakenly used a register name as the last
8060 It is very difficult to distinguish between these two cases
8061 because "rX" might actually be a label. ie the register
8062 name has been occluded by a symbol of the same name. So we
8063 just generate a general 'bad addressing mode' type error
8064 message and leave it up to the programmer to discover the
8065 true cause and fix their mistake. */
8066 || (inst.operands[1].reg == REG_PC),
8069 constraint (inst.reloc.exp.X_op != O_constant
8070 || inst.reloc.exp.X_add_number != 0,
8071 _("offset must be zero in ARM encoding"));
8073 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8075 inst.instruction |= inst.operands[0].reg << 12;
8076 inst.instruction |= inst.operands[1].reg << 16;
8077 inst.reloc.type = BFD_RELOC_UNUSED;
8083 constraint (inst.operands[0].reg % 2 != 0,
8084 _("even register required"));
8085 constraint (inst.operands[1].present
8086 && inst.operands[1].reg != inst.operands[0].reg + 1,
8087 _("can only load two consecutive registers"));
8088 /* If op 1 were present and equal to PC, this function wouldn't
8089 have been called in the first place. */
8090 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8092 inst.instruction |= inst.operands[0].reg << 12;
8093 inst.instruction |= inst.operands[2].reg << 16;
8096 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8097 which is not a multiple of four is UNPREDICTABLE. */
8099 check_ldr_r15_aligned (void)
8101 constraint (!(inst.operands[1].immisreg)
8102 && (inst.operands[0].reg == REG_PC
8103 && inst.operands[1].reg == REG_PC
8104 && (inst.reloc.exp.X_add_number & 0x3)),
8105 _("ldr to register 15 must be 4-byte alligned"));
8111 inst.instruction |= inst.operands[0].reg << 12;
8112 if (!inst.operands[1].isreg)
8113 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8115 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8116 check_ldr_r15_aligned ();
8122 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8124 if (inst.operands[1].preind)
8126 constraint (inst.reloc.exp.X_op != O_constant
8127 || inst.reloc.exp.X_add_number != 0,
8128 _("this instruction requires a post-indexed address"));
8130 inst.operands[1].preind = 0;
8131 inst.operands[1].postind = 1;
8132 inst.operands[1].writeback = 1;
8134 inst.instruction |= inst.operands[0].reg << 12;
8135 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8138 /* Halfword and signed-byte load/store operations. */
8143 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8144 inst.instruction |= inst.operands[0].reg << 12;
8145 if (!inst.operands[1].isreg)
8146 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8148 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8154 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8156 if (inst.operands[1].preind)
8158 constraint (inst.reloc.exp.X_op != O_constant
8159 || inst.reloc.exp.X_add_number != 0,
8160 _("this instruction requires a post-indexed address"));
8162 inst.operands[1].preind = 0;
8163 inst.operands[1].postind = 1;
8164 inst.operands[1].writeback = 1;
8166 inst.instruction |= inst.operands[0].reg << 12;
8167 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8170 /* Co-processor register load/store.
8171 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8175 inst.instruction |= inst.operands[0].reg << 8;
8176 inst.instruction |= inst.operands[1].reg << 12;
8177 encode_arm_cp_address (2, TRUE, TRUE, 0);
8183 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8184 if (inst.operands[0].reg == inst.operands[1].reg
8185 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8186 && !(inst.instruction & 0x00400000))
8187 as_tsktsk (_("Rd and Rm should be different in mla"));
8189 inst.instruction |= inst.operands[0].reg << 16;
8190 inst.instruction |= inst.operands[1].reg;
8191 inst.instruction |= inst.operands[2].reg << 8;
8192 inst.instruction |= inst.operands[3].reg << 12;
8198 inst.instruction |= inst.operands[0].reg << 12;
8199 encode_arm_shifter_operand (1);
8202 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8209 top = (inst.instruction & 0x00400000) != 0;
8210 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8211 _(":lower16: not allowed this instruction"));
8212 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8213 _(":upper16: not allowed instruction"));
8214 inst.instruction |= inst.operands[0].reg << 12;
8215 if (inst.reloc.type == BFD_RELOC_UNUSED)
8217 imm = inst.reloc.exp.X_add_number;
8218 /* The value is in two pieces: 0:11, 16:19. */
8219 inst.instruction |= (imm & 0x00000fff);
8220 inst.instruction |= (imm & 0x0000f000) << 4;
8224 static void do_vfp_nsyn_opcode (const char *);
8227 do_vfp_nsyn_mrs (void)
8229 if (inst.operands[0].isvec)
8231 if (inst.operands[1].reg != 1)
8232 first_error (_("operand 1 must be FPSCR"));
8233 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8234 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8235 do_vfp_nsyn_opcode ("fmstat");
8237 else if (inst.operands[1].isvec)
8238 do_vfp_nsyn_opcode ("fmrx");
8246 do_vfp_nsyn_msr (void)
8248 if (inst.operands[0].isvec)
8249 do_vfp_nsyn_opcode ("fmxr");
8259 unsigned Rt = inst.operands[0].reg;
8261 if (thumb_mode && Rt == REG_SP)
8263 inst.error = BAD_SP;
8267 /* APSR_ sets isvec. All other refs to PC are illegal. */
8268 if (!inst.operands[0].isvec && Rt == REG_PC)
8270 inst.error = BAD_PC;
8274 /* If we get through parsing the register name, we just insert the number
8275 generated into the instruction without further validation. */
8276 inst.instruction |= (inst.operands[1].reg << 16);
8277 inst.instruction |= (Rt << 12);
8283 unsigned Rt = inst.operands[1].reg;
8286 reject_bad_reg (Rt);
8287 else if (Rt == REG_PC)
8289 inst.error = BAD_PC;
8293 /* If we get through parsing the register name, we just insert the number
8294 generated into the instruction without further validation. */
8295 inst.instruction |= (inst.operands[0].reg << 16);
8296 inst.instruction |= (Rt << 12);
8304 if (do_vfp_nsyn_mrs () == SUCCESS)
8307 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8308 inst.instruction |= inst.operands[0].reg << 12;
8310 if (inst.operands[1].isreg)
8312 br = inst.operands[1].reg;
8313 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8314 as_bad (_("bad register for mrs"));
8318 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8319 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8321 _("'APSR', 'CPSR' or 'SPSR' expected"));
8322 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8325 inst.instruction |= br;
8328 /* Two possible forms:
8329 "{C|S}PSR_<field>, Rm",
8330 "{C|S}PSR_f, #expression". */
8335 if (do_vfp_nsyn_msr () == SUCCESS)
8338 inst.instruction |= inst.operands[0].imm;
8339 if (inst.operands[1].isreg)
8340 inst.instruction |= inst.operands[1].reg;
8343 inst.instruction |= INST_IMMEDIATE;
8344 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8345 inst.reloc.pc_rel = 0;
8352 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8354 if (!inst.operands[2].present)
8355 inst.operands[2].reg = inst.operands[0].reg;
8356 inst.instruction |= inst.operands[0].reg << 16;
8357 inst.instruction |= inst.operands[1].reg;
8358 inst.instruction |= inst.operands[2].reg << 8;
8360 if (inst.operands[0].reg == inst.operands[1].reg
8361 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8362 as_tsktsk (_("Rd and Rm should be different in mul"));
8365 /* Long Multiply Parser
8366 UMULL RdLo, RdHi, Rm, Rs
8367 SMULL RdLo, RdHi, Rm, Rs
8368 UMLAL RdLo, RdHi, Rm, Rs
8369 SMLAL RdLo, RdHi, Rm, Rs. */
8374 inst.instruction |= inst.operands[0].reg << 12;
8375 inst.instruction |= inst.operands[1].reg << 16;
8376 inst.instruction |= inst.operands[2].reg;
8377 inst.instruction |= inst.operands[3].reg << 8;
8379 /* rdhi and rdlo must be different. */
8380 if (inst.operands[0].reg == inst.operands[1].reg)
8381 as_tsktsk (_("rdhi and rdlo must be different"));
8383 /* rdhi, rdlo and rm must all be different before armv6. */
8384 if ((inst.operands[0].reg == inst.operands[2].reg
8385 || inst.operands[1].reg == inst.operands[2].reg)
8386 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8387 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8393 if (inst.operands[0].present
8394 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8396 /* Architectural NOP hints are CPSR sets with no bits selected. */
8397 inst.instruction &= 0xf0000000;
8398 inst.instruction |= 0x0320f000;
8399 if (inst.operands[0].present)
8400 inst.instruction |= inst.operands[0].imm;
8404 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8405 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8406 Condition defaults to COND_ALWAYS.
8407 Error if Rd, Rn or Rm are R15. */
8412 inst.instruction |= inst.operands[0].reg << 12;
8413 inst.instruction |= inst.operands[1].reg << 16;
8414 inst.instruction |= inst.operands[2].reg;
8415 if (inst.operands[3].present)
8416 encode_arm_shift (3);
8419 /* ARM V6 PKHTB (Argument Parse). */
8424 if (!inst.operands[3].present)
8426 /* If the shift specifier is omitted, turn the instruction
8427 into pkhbt rd, rm, rn. */
8428 inst.instruction &= 0xfff00010;
8429 inst.instruction |= inst.operands[0].reg << 12;
8430 inst.instruction |= inst.operands[1].reg;
8431 inst.instruction |= inst.operands[2].reg << 16;
8435 inst.instruction |= inst.operands[0].reg << 12;
8436 inst.instruction |= inst.operands[1].reg << 16;
8437 inst.instruction |= inst.operands[2].reg;
8438 encode_arm_shift (3);
8442 /* ARMv5TE: Preload-Cache
8443 MP Extensions: Preload for write
8447 Syntactically, like LDR with B=1, W=0, L=1. */
8452 constraint (!inst.operands[0].isreg,
8453 _("'[' expected after PLD mnemonic"));
8454 constraint (inst.operands[0].postind,
8455 _("post-indexed expression used in preload instruction"));
8456 constraint (inst.operands[0].writeback,
8457 _("writeback used in preload instruction"));
8458 constraint (!inst.operands[0].preind,
8459 _("unindexed addressing used in preload instruction"));
8460 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8463 /* ARMv7: PLI <addr_mode> */
8467 constraint (!inst.operands[0].isreg,
8468 _("'[' expected after PLI mnemonic"));
8469 constraint (inst.operands[0].postind,
8470 _("post-indexed expression used in preload instruction"));
8471 constraint (inst.operands[0].writeback,
8472 _("writeback used in preload instruction"));
8473 constraint (!inst.operands[0].preind,
8474 _("unindexed addressing used in preload instruction"));
8475 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8476 inst.instruction &= ~PRE_INDEX;
8482 inst.operands[1] = inst.operands[0];
8483 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8484 inst.operands[0].isreg = 1;
8485 inst.operands[0].writeback = 1;
8486 inst.operands[0].reg = REG_SP;
8487 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8490 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8491 word at the specified address and the following word
8493 Unconditionally executed.
8494 Error if Rn is R15. */
8499 inst.instruction |= inst.operands[0].reg << 16;
8500 if (inst.operands[0].writeback)
8501 inst.instruction |= WRITE_BACK;
8504 /* ARM V6 ssat (argument parse). */
8509 inst.instruction |= inst.operands[0].reg << 12;
8510 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8511 inst.instruction |= inst.operands[2].reg;
8513 if (inst.operands[3].present)
8514 encode_arm_shift (3);
8517 /* ARM V6 usat (argument parse). */
8522 inst.instruction |= inst.operands[0].reg << 12;
8523 inst.instruction |= inst.operands[1].imm << 16;
8524 inst.instruction |= inst.operands[2].reg;
8526 if (inst.operands[3].present)
8527 encode_arm_shift (3);
8530 /* ARM V6 ssat16 (argument parse). */
8535 inst.instruction |= inst.operands[0].reg << 12;
8536 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8537 inst.instruction |= inst.operands[2].reg;
8543 inst.instruction |= inst.operands[0].reg << 12;
8544 inst.instruction |= inst.operands[1].imm << 16;
8545 inst.instruction |= inst.operands[2].reg;
8548 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8549 preserving the other bits.
8551 setend <endian_specifier>, where <endian_specifier> is either
8557 if (warn_on_deprecated
8558 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8559 as_warn (_("setend use is deprecated for ARMv8"));
8561 if (inst.operands[0].imm)
8562 inst.instruction |= 0x200;
8568 unsigned int Rm = (inst.operands[1].present
8569 ? inst.operands[1].reg
8570 : inst.operands[0].reg);
8572 inst.instruction |= inst.operands[0].reg << 12;
8573 inst.instruction |= Rm;
8574 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8576 inst.instruction |= inst.operands[2].reg << 8;
8577 inst.instruction |= SHIFT_BY_REG;
8578 /* PR 12854: Error on extraneous shifts. */
8579 constraint (inst.operands[2].shifted,
8580 _("extraneous shift as part of operand to shift insn"));
8583 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8589 inst.reloc.type = BFD_RELOC_ARM_SMC;
8590 inst.reloc.pc_rel = 0;
8596 inst.reloc.type = BFD_RELOC_ARM_HVC;
8597 inst.reloc.pc_rel = 0;
8603 inst.reloc.type = BFD_RELOC_ARM_SWI;
8604 inst.reloc.pc_rel = 0;
8607 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8608 SMLAxy{cond} Rd,Rm,Rs,Rn
8609 SMLAWy{cond} Rd,Rm,Rs,Rn
8610 Error if any register is R15. */
8615 inst.instruction |= inst.operands[0].reg << 16;
8616 inst.instruction |= inst.operands[1].reg;
8617 inst.instruction |= inst.operands[2].reg << 8;
8618 inst.instruction |= inst.operands[3].reg << 12;
8621 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8622 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8623 Error if any register is R15.
8624 Warning if Rdlo == Rdhi. */
8629 inst.instruction |= inst.operands[0].reg << 12;
8630 inst.instruction |= inst.operands[1].reg << 16;
8631 inst.instruction |= inst.operands[2].reg;
8632 inst.instruction |= inst.operands[3].reg << 8;
8634 if (inst.operands[0].reg == inst.operands[1].reg)
8635 as_tsktsk (_("rdhi and rdlo must be different"));
8638 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8639 SMULxy{cond} Rd,Rm,Rs
8640 Error if any register is R15. */
8645 inst.instruction |= inst.operands[0].reg << 16;
8646 inst.instruction |= inst.operands[1].reg;
8647 inst.instruction |= inst.operands[2].reg << 8;
8650 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8651 the same for both ARM and Thumb-2. */
8658 if (inst.operands[0].present)
8660 reg = inst.operands[0].reg;
8661 constraint (reg != REG_SP, _("SRS base register must be r13"));
8666 inst.instruction |= reg << 16;
8667 inst.instruction |= inst.operands[1].imm;
8668 if (inst.operands[0].writeback || inst.operands[1].writeback)
8669 inst.instruction |= WRITE_BACK;
8672 /* ARM V6 strex (argument parse). */
8677 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8678 || inst.operands[2].postind || inst.operands[2].writeback
8679 || inst.operands[2].immisreg || inst.operands[2].shifted
8680 || inst.operands[2].negative
8681 /* See comment in do_ldrex(). */
8682 || (inst.operands[2].reg == REG_PC),
8685 constraint (inst.operands[0].reg == inst.operands[1].reg
8686 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8688 constraint (inst.reloc.exp.X_op != O_constant
8689 || inst.reloc.exp.X_add_number != 0,
8690 _("offset must be zero in ARM encoding"));
8692 inst.instruction |= inst.operands[0].reg << 12;
8693 inst.instruction |= inst.operands[1].reg;
8694 inst.instruction |= inst.operands[2].reg << 16;
8695 inst.reloc.type = BFD_RELOC_UNUSED;
8701 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8702 || inst.operands[2].postind || inst.operands[2].writeback
8703 || inst.operands[2].immisreg || inst.operands[2].shifted
8704 || inst.operands[2].negative,
8707 constraint (inst.operands[0].reg == inst.operands[1].reg
8708 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8716 constraint (inst.operands[1].reg % 2 != 0,
8717 _("even register required"));
8718 constraint (inst.operands[2].present
8719 && inst.operands[2].reg != inst.operands[1].reg + 1,
8720 _("can only store two consecutive registers"));
8721 /* If op 2 were present and equal to PC, this function wouldn't
8722 have been called in the first place. */
8723 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8725 constraint (inst.operands[0].reg == inst.operands[1].reg
8726 || inst.operands[0].reg == inst.operands[1].reg + 1
8727 || inst.operands[0].reg == inst.operands[3].reg,
8730 inst.instruction |= inst.operands[0].reg << 12;
8731 inst.instruction |= inst.operands[1].reg;
8732 inst.instruction |= inst.operands[3].reg << 16;
8739 constraint (inst.operands[0].reg == inst.operands[1].reg
8740 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8748 constraint (inst.operands[0].reg == inst.operands[1].reg
8749 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8754 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8755 extends it to 32-bits, and adds the result to a value in another
8756 register. You can specify a rotation by 0, 8, 16, or 24 bits
8757 before extracting the 16-bit value.
8758 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8759 Condition defaults to COND_ALWAYS.
8760 Error if any register uses R15. */
8765 inst.instruction |= inst.operands[0].reg << 12;
8766 inst.instruction |= inst.operands[1].reg << 16;
8767 inst.instruction |= inst.operands[2].reg;
8768 inst.instruction |= inst.operands[3].imm << 10;
8773 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8774 Condition defaults to COND_ALWAYS.
8775 Error if any register uses R15. */
8780 inst.instruction |= inst.operands[0].reg << 12;
8781 inst.instruction |= inst.operands[1].reg;
8782 inst.instruction |= inst.operands[2].imm << 10;
8785 /* VFP instructions. In a logical order: SP variant first, monad
8786 before dyad, arithmetic then move then load/store. */
8789 do_vfp_sp_monadic (void)
8791 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8792 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8796 do_vfp_sp_dyadic (void)
8798 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8799 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8800 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8804 do_vfp_sp_compare_z (void)
8806 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8810 do_vfp_dp_sp_cvt (void)
8812 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8813 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8817 do_vfp_sp_dp_cvt (void)
8819 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8820 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8824 do_vfp_reg_from_sp (void)
8826 inst.instruction |= inst.operands[0].reg << 12;
8827 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8831 do_vfp_reg2_from_sp2 (void)
8833 constraint (inst.operands[2].imm != 2,
8834 _("only two consecutive VFP SP registers allowed here"));
8835 inst.instruction |= inst.operands[0].reg << 12;
8836 inst.instruction |= inst.operands[1].reg << 16;
8837 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8841 do_vfp_sp_from_reg (void)
8843 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8844 inst.instruction |= inst.operands[1].reg << 12;
8848 do_vfp_sp2_from_reg2 (void)
8850 constraint (inst.operands[0].imm != 2,
8851 _("only two consecutive VFP SP registers allowed here"));
8852 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8853 inst.instruction |= inst.operands[1].reg << 12;
8854 inst.instruction |= inst.operands[2].reg << 16;
8858 do_vfp_sp_ldst (void)
8860 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8861 encode_arm_cp_address (1, FALSE, TRUE, 0);
8865 do_vfp_dp_ldst (void)
8867 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8868 encode_arm_cp_address (1, FALSE, TRUE, 0);
8873 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8875 if (inst.operands[0].writeback)
8876 inst.instruction |= WRITE_BACK;
8878 constraint (ldstm_type != VFP_LDSTMIA,
8879 _("this addressing mode requires base-register writeback"));
8880 inst.instruction |= inst.operands[0].reg << 16;
8881 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8882 inst.instruction |= inst.operands[1].imm;
8886 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8890 if (inst.operands[0].writeback)
8891 inst.instruction |= WRITE_BACK;
8893 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8894 _("this addressing mode requires base-register writeback"));
8896 inst.instruction |= inst.operands[0].reg << 16;
8897 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8899 count = inst.operands[1].imm << 1;
8900 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8903 inst.instruction |= count;
8907 do_vfp_sp_ldstmia (void)
8909 vfp_sp_ldstm (VFP_LDSTMIA);
8913 do_vfp_sp_ldstmdb (void)
8915 vfp_sp_ldstm (VFP_LDSTMDB);
8919 do_vfp_dp_ldstmia (void)
8921 vfp_dp_ldstm (VFP_LDSTMIA);
8925 do_vfp_dp_ldstmdb (void)
8927 vfp_dp_ldstm (VFP_LDSTMDB);
8931 do_vfp_xp_ldstmia (void)
8933 vfp_dp_ldstm (VFP_LDSTMIAX);
8937 do_vfp_xp_ldstmdb (void)
8939 vfp_dp_ldstm (VFP_LDSTMDBX);
8943 do_vfp_dp_rd_rm (void)
8945 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8946 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8950 do_vfp_dp_rn_rd (void)
8952 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8953 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8957 do_vfp_dp_rd_rn (void)
8959 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8960 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8964 do_vfp_dp_rd_rn_rm (void)
8966 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8967 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8968 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8974 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8978 do_vfp_dp_rm_rd_rn (void)
8980 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8981 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8982 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8985 /* VFPv3 instructions. */
8987 do_vfp_sp_const (void)
8989 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8990 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8991 inst.instruction |= (inst.operands[1].imm & 0x0f);
8995 do_vfp_dp_const (void)
8997 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8998 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8999 inst.instruction |= (inst.operands[1].imm & 0x0f);
9003 vfp_conv (int srcsize)
9005 int immbits = srcsize - inst.operands[1].imm;
9007 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9009 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9010 i.e. immbits must be in range 0 - 16. */
9011 inst.error = _("immediate value out of range, expected range [0, 16]");
9014 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9016 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9017 i.e. immbits must be in range 0 - 31. */
9018 inst.error = _("immediate value out of range, expected range [1, 32]");
9022 inst.instruction |= (immbits & 1) << 5;
9023 inst.instruction |= (immbits >> 1);
9027 do_vfp_sp_conv_16 (void)
9029 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9034 do_vfp_dp_conv_16 (void)
9036 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9041 do_vfp_sp_conv_32 (void)
9043 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9048 do_vfp_dp_conv_32 (void)
9050 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9054 /* FPA instructions. Also in a logical order. */
9059 inst.instruction |= inst.operands[0].reg << 16;
9060 inst.instruction |= inst.operands[1].reg;
9064 do_fpa_ldmstm (void)
9066 inst.instruction |= inst.operands[0].reg << 12;
9067 switch (inst.operands[1].imm)
9069 case 1: inst.instruction |= CP_T_X; break;
9070 case 2: inst.instruction |= CP_T_Y; break;
9071 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9076 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9078 /* The instruction specified "ea" or "fd", so we can only accept
9079 [Rn]{!}. The instruction does not really support stacking or
9080 unstacking, so we have to emulate these by setting appropriate
9081 bits and offsets. */
9082 constraint (inst.reloc.exp.X_op != O_constant
9083 || inst.reloc.exp.X_add_number != 0,
9084 _("this instruction does not support indexing"));
9086 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9087 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9089 if (!(inst.instruction & INDEX_UP))
9090 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9092 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9094 inst.operands[2].preind = 0;
9095 inst.operands[2].postind = 1;
9099 encode_arm_cp_address (2, TRUE, TRUE, 0);
9102 /* iWMMXt instructions: strictly in alphabetical order. */
9105 do_iwmmxt_tandorc (void)
9107 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9111 do_iwmmxt_textrc (void)
9113 inst.instruction |= inst.operands[0].reg << 12;
9114 inst.instruction |= inst.operands[1].imm;
9118 do_iwmmxt_textrm (void)
9120 inst.instruction |= inst.operands[0].reg << 12;
9121 inst.instruction |= inst.operands[1].reg << 16;
9122 inst.instruction |= inst.operands[2].imm;
9126 do_iwmmxt_tinsr (void)
9128 inst.instruction |= inst.operands[0].reg << 16;
9129 inst.instruction |= inst.operands[1].reg << 12;
9130 inst.instruction |= inst.operands[2].imm;
9134 do_iwmmxt_tmia (void)
9136 inst.instruction |= inst.operands[0].reg << 5;
9137 inst.instruction |= inst.operands[1].reg;
9138 inst.instruction |= inst.operands[2].reg << 12;
9142 do_iwmmxt_waligni (void)
9144 inst.instruction |= inst.operands[0].reg << 12;
9145 inst.instruction |= inst.operands[1].reg << 16;
9146 inst.instruction |= inst.operands[2].reg;
9147 inst.instruction |= inst.operands[3].imm << 20;
9151 do_iwmmxt_wmerge (void)
9153 inst.instruction |= inst.operands[0].reg << 12;
9154 inst.instruction |= inst.operands[1].reg << 16;
9155 inst.instruction |= inst.operands[2].reg;
9156 inst.instruction |= inst.operands[3].imm << 21;
9160 do_iwmmxt_wmov (void)
9162 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9163 inst.instruction |= inst.operands[0].reg << 12;
9164 inst.instruction |= inst.operands[1].reg << 16;
9165 inst.instruction |= inst.operands[1].reg;
9169 do_iwmmxt_wldstbh (void)
9172 inst.instruction |= inst.operands[0].reg << 12;
9174 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9176 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9177 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9181 do_iwmmxt_wldstw (void)
9183 /* RIWR_RIWC clears .isreg for a control register. */
9184 if (!inst.operands[0].isreg)
9186 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9187 inst.instruction |= 0xf0000000;
9190 inst.instruction |= inst.operands[0].reg << 12;
9191 encode_arm_cp_address (1, TRUE, TRUE, 0);
9195 do_iwmmxt_wldstd (void)
9197 inst.instruction |= inst.operands[0].reg << 12;
9198 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9199 && inst.operands[1].immisreg)
9201 inst.instruction &= ~0x1a000ff;
9202 inst.instruction |= (0xf << 28);
9203 if (inst.operands[1].preind)
9204 inst.instruction |= PRE_INDEX;
9205 if (!inst.operands[1].negative)
9206 inst.instruction |= INDEX_UP;
9207 if (inst.operands[1].writeback)
9208 inst.instruction |= WRITE_BACK;
9209 inst.instruction |= inst.operands[1].reg << 16;
9210 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9211 inst.instruction |= inst.operands[1].imm;
9214 encode_arm_cp_address (1, TRUE, FALSE, 0);
9218 do_iwmmxt_wshufh (void)
9220 inst.instruction |= inst.operands[0].reg << 12;
9221 inst.instruction |= inst.operands[1].reg << 16;
9222 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9223 inst.instruction |= (inst.operands[2].imm & 0x0f);
9227 do_iwmmxt_wzero (void)
9229 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9230 inst.instruction |= inst.operands[0].reg;
9231 inst.instruction |= inst.operands[0].reg << 12;
9232 inst.instruction |= inst.operands[0].reg << 16;
9236 do_iwmmxt_wrwrwr_or_imm5 (void)
9238 if (inst.operands[2].isreg)
9241 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9242 _("immediate operand requires iWMMXt2"));
9244 if (inst.operands[2].imm == 0)
9246 switch ((inst.instruction >> 20) & 0xf)
9252 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9253 inst.operands[2].imm = 16;
9254 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9260 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9261 inst.operands[2].imm = 32;
9262 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9269 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9271 wrn = (inst.instruction >> 16) & 0xf;
9272 inst.instruction &= 0xff0fff0f;
9273 inst.instruction |= wrn;
9274 /* Bail out here; the instruction is now assembled. */
9279 /* Map 32 -> 0, etc. */
9280 inst.operands[2].imm &= 0x1f;
9281 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9285 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9286 operations first, then control, shift, and load/store. */
9288 /* Insns like "foo X,Y,Z". */
9291 do_mav_triple (void)
9293 inst.instruction |= inst.operands[0].reg << 16;
9294 inst.instruction |= inst.operands[1].reg;
9295 inst.instruction |= inst.operands[2].reg << 12;
9298 /* Insns like "foo W,X,Y,Z".
9299 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9304 inst.instruction |= inst.operands[0].reg << 5;
9305 inst.instruction |= inst.operands[1].reg << 12;
9306 inst.instruction |= inst.operands[2].reg << 16;
9307 inst.instruction |= inst.operands[3].reg;
9310 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9314 inst.instruction |= inst.operands[1].reg << 12;
9317 /* Maverick shift immediate instructions.
9318 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9319 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9324 int imm = inst.operands[2].imm;
9326 inst.instruction |= inst.operands[0].reg << 12;
9327 inst.instruction |= inst.operands[1].reg << 16;
9329 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9330 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9331 Bit 4 should be 0. */
9332 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9334 inst.instruction |= imm;
9337 /* XScale instructions. Also sorted arithmetic before move. */
9339 /* Xscale multiply-accumulate (argument parse)
9342 MIAxycc acc0,Rm,Rs. */
9347 inst.instruction |= inst.operands[1].reg;
9348 inst.instruction |= inst.operands[2].reg << 12;
9351 /* Xscale move-accumulator-register (argument parse)
9353 MARcc acc0,RdLo,RdHi. */
9358 inst.instruction |= inst.operands[1].reg << 12;
9359 inst.instruction |= inst.operands[2].reg << 16;
9362 /* Xscale move-register-accumulator (argument parse)
9364 MRAcc RdLo,RdHi,acc0. */
9369 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9370 inst.instruction |= inst.operands[0].reg << 12;
9371 inst.instruction |= inst.operands[1].reg << 16;
9374 /* Encoding functions relevant only to Thumb. */
9376 /* inst.operands[i] is a shifted-register operand; encode
9377 it into inst.instruction in the format used by Thumb32. */
9380 encode_thumb32_shifted_operand (int i)
9382 unsigned int value = inst.reloc.exp.X_add_number;
9383 unsigned int shift = inst.operands[i].shift_kind;
9385 constraint (inst.operands[i].immisreg,
9386 _("shift by register not allowed in thumb mode"));
9387 inst.instruction |= inst.operands[i].reg;
9388 if (shift == SHIFT_RRX)
9389 inst.instruction |= SHIFT_ROR << 4;
9392 constraint (inst.reloc.exp.X_op != O_constant,
9393 _("expression too complex"));
9395 constraint (value > 32
9396 || (value == 32 && (shift == SHIFT_LSL
9397 || shift == SHIFT_ROR)),
9398 _("shift expression is too large"));
9402 else if (value == 32)
9405 inst.instruction |= shift << 4;
9406 inst.instruction |= (value & 0x1c) << 10;
9407 inst.instruction |= (value & 0x03) << 6;
9412 /* inst.operands[i] was set up by parse_address. Encode it into a
9413 Thumb32 format load or store instruction. Reject forms that cannot
9414 be used with such instructions. If is_t is true, reject forms that
9415 cannot be used with a T instruction; if is_d is true, reject forms
9416 that cannot be used with a D instruction. If it is a store insn,
9420 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9422 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9424 constraint (!inst.operands[i].isreg,
9425 _("Instruction does not support =N addresses"));
9427 inst.instruction |= inst.operands[i].reg << 16;
9428 if (inst.operands[i].immisreg)
9430 constraint (is_pc, BAD_PC_ADDRESSING);
9431 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9432 constraint (inst.operands[i].negative,
9433 _("Thumb does not support negative register indexing"));
9434 constraint (inst.operands[i].postind,
9435 _("Thumb does not support register post-indexing"));
9436 constraint (inst.operands[i].writeback,
9437 _("Thumb does not support register indexing with writeback"));
9438 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9439 _("Thumb supports only LSL in shifted register indexing"));
9441 inst.instruction |= inst.operands[i].imm;
9442 if (inst.operands[i].shifted)
9444 constraint (inst.reloc.exp.X_op != O_constant,
9445 _("expression too complex"));
9446 constraint (inst.reloc.exp.X_add_number < 0
9447 || inst.reloc.exp.X_add_number > 3,
9448 _("shift out of range"));
9449 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9451 inst.reloc.type = BFD_RELOC_UNUSED;
9453 else if (inst.operands[i].preind)
9455 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9456 constraint (is_t && inst.operands[i].writeback,
9457 _("cannot use writeback with this instruction"));
9458 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
9463 inst.instruction |= 0x01000000;
9464 if (inst.operands[i].writeback)
9465 inst.instruction |= 0x00200000;
9469 inst.instruction |= 0x00000c00;
9470 if (inst.operands[i].writeback)
9471 inst.instruction |= 0x00000100;
9473 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9475 else if (inst.operands[i].postind)
9477 gas_assert (inst.operands[i].writeback);
9478 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9479 constraint (is_t, _("cannot use post-indexing with this instruction"));
9482 inst.instruction |= 0x00200000;
9484 inst.instruction |= 0x00000900;
9485 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9487 else /* unindexed - only for coprocessor */
9488 inst.error = _("instruction does not accept unindexed addressing");
9491 /* Table of Thumb instructions which exist in both 16- and 32-bit
9492 encodings (the latter only in post-V6T2 cores). The index is the
9493 value used in the insns table below. When there is more than one
9494 possible 16-bit encoding for the instruction, this table always
9496 Also contains several pseudo-instructions used during relaxation. */
9497 #define T16_32_TAB \
9498 X(_adc, 4140, eb400000), \
9499 X(_adcs, 4140, eb500000), \
9500 X(_add, 1c00, eb000000), \
9501 X(_adds, 1c00, eb100000), \
9502 X(_addi, 0000, f1000000), \
9503 X(_addis, 0000, f1100000), \
9504 X(_add_pc,000f, f20f0000), \
9505 X(_add_sp,000d, f10d0000), \
9506 X(_adr, 000f, f20f0000), \
9507 X(_and, 4000, ea000000), \
9508 X(_ands, 4000, ea100000), \
9509 X(_asr, 1000, fa40f000), \
9510 X(_asrs, 1000, fa50f000), \
9511 X(_b, e000, f000b000), \
9512 X(_bcond, d000, f0008000), \
9513 X(_bic, 4380, ea200000), \
9514 X(_bics, 4380, ea300000), \
9515 X(_cmn, 42c0, eb100f00), \
9516 X(_cmp, 2800, ebb00f00), \
9517 X(_cpsie, b660, f3af8400), \
9518 X(_cpsid, b670, f3af8600), \
9519 X(_cpy, 4600, ea4f0000), \
9520 X(_dec_sp,80dd, f1ad0d00), \
9521 X(_eor, 4040, ea800000), \
9522 X(_eors, 4040, ea900000), \
9523 X(_inc_sp,00dd, f10d0d00), \
9524 X(_ldmia, c800, e8900000), \
9525 X(_ldr, 6800, f8500000), \
9526 X(_ldrb, 7800, f8100000), \
9527 X(_ldrh, 8800, f8300000), \
9528 X(_ldrsb, 5600, f9100000), \
9529 X(_ldrsh, 5e00, f9300000), \
9530 X(_ldr_pc,4800, f85f0000), \
9531 X(_ldr_pc2,4800, f85f0000), \
9532 X(_ldr_sp,9800, f85d0000), \
9533 X(_lsl, 0000, fa00f000), \
9534 X(_lsls, 0000, fa10f000), \
9535 X(_lsr, 0800, fa20f000), \
9536 X(_lsrs, 0800, fa30f000), \
9537 X(_mov, 2000, ea4f0000), \
9538 X(_movs, 2000, ea5f0000), \
9539 X(_mul, 4340, fb00f000), \
9540 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9541 X(_mvn, 43c0, ea6f0000), \
9542 X(_mvns, 43c0, ea7f0000), \
9543 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9544 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9545 X(_orr, 4300, ea400000), \
9546 X(_orrs, 4300, ea500000), \
9547 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9548 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9549 X(_rev, ba00, fa90f080), \
9550 X(_rev16, ba40, fa90f090), \
9551 X(_revsh, bac0, fa90f0b0), \
9552 X(_ror, 41c0, fa60f000), \
9553 X(_rors, 41c0, fa70f000), \
9554 X(_sbc, 4180, eb600000), \
9555 X(_sbcs, 4180, eb700000), \
9556 X(_stmia, c000, e8800000), \
9557 X(_str, 6000, f8400000), \
9558 X(_strb, 7000, f8000000), \
9559 X(_strh, 8000, f8200000), \
9560 X(_str_sp,9000, f84d0000), \
9561 X(_sub, 1e00, eba00000), \
9562 X(_subs, 1e00, ebb00000), \
9563 X(_subi, 8000, f1a00000), \
9564 X(_subis, 8000, f1b00000), \
9565 X(_sxtb, b240, fa4ff080), \
9566 X(_sxth, b200, fa0ff080), \
9567 X(_tst, 4200, ea100f00), \
9568 X(_uxtb, b2c0, fa5ff080), \
9569 X(_uxth, b280, fa1ff080), \
9570 X(_nop, bf00, f3af8000), \
9571 X(_yield, bf10, f3af8001), \
9572 X(_wfe, bf20, f3af8002), \
9573 X(_wfi, bf30, f3af8003), \
9574 X(_sev, bf40, f3af8004), \
9575 X(_sevl, bf50, f3af8005), \
9576 X(_udf, de00, f7f0a000)
9578 /* To catch errors in encoding functions, the codes are all offset by
9579 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9580 as 16-bit instructions. */
9581 #define X(a,b,c) T_MNEM##a
9582 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9585 #define X(a,b,c) 0x##b
9586 static const unsigned short thumb_op16[] = { T16_32_TAB };
9587 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9590 #define X(a,b,c) 0x##c
9591 static const unsigned int thumb_op32[] = { T16_32_TAB };
9592 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9593 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9597 /* Thumb instruction encoders, in alphabetical order. */
9602 do_t_add_sub_w (void)
9606 Rd = inst.operands[0].reg;
9607 Rn = inst.operands[1].reg;
9609 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9610 is the SP-{plus,minus}-immediate form of the instruction. */
9612 constraint (Rd == REG_PC, BAD_PC);
9614 reject_bad_reg (Rd);
9616 inst.instruction |= (Rn << 16) | (Rd << 8);
9617 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9620 /* Parse an add or subtract instruction. We get here with inst.instruction
9621 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9628 Rd = inst.operands[0].reg;
9629 Rs = (inst.operands[1].present
9630 ? inst.operands[1].reg /* Rd, Rs, foo */
9631 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9634 set_it_insn_type_last ();
9642 flags = (inst.instruction == T_MNEM_adds
9643 || inst.instruction == T_MNEM_subs);
9645 narrow = !in_it_block ();
9647 narrow = in_it_block ();
9648 if (!inst.operands[2].isreg)
9652 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9654 add = (inst.instruction == T_MNEM_add
9655 || inst.instruction == T_MNEM_adds);
9657 if (inst.size_req != 4)
9659 /* Attempt to use a narrow opcode, with relaxation if
9661 if (Rd == REG_SP && Rs == REG_SP && !flags)
9662 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9663 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9664 opcode = T_MNEM_add_sp;
9665 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9666 opcode = T_MNEM_add_pc;
9667 else if (Rd <= 7 && Rs <= 7 && narrow)
9670 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9672 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9676 inst.instruction = THUMB_OP16(opcode);
9677 inst.instruction |= (Rd << 4) | Rs;
9678 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9679 if (inst.size_req != 2)
9680 inst.relax = opcode;
9683 constraint (inst.size_req == 2, BAD_HIREG);
9685 if (inst.size_req == 4
9686 || (inst.size_req != 2 && !opcode))
9690 constraint (add, BAD_PC);
9691 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9692 _("only SUBS PC, LR, #const allowed"));
9693 constraint (inst.reloc.exp.X_op != O_constant,
9694 _("expression too complex"));
9695 constraint (inst.reloc.exp.X_add_number < 0
9696 || inst.reloc.exp.X_add_number > 0xff,
9697 _("immediate value out of range"));
9698 inst.instruction = T2_SUBS_PC_LR
9699 | inst.reloc.exp.X_add_number;
9700 inst.reloc.type = BFD_RELOC_UNUSED;
9703 else if (Rs == REG_PC)
9705 /* Always use addw/subw. */
9706 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9707 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9711 inst.instruction = THUMB_OP32 (inst.instruction);
9712 inst.instruction = (inst.instruction & 0xe1ffffff)
9715 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9717 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9719 inst.instruction |= Rd << 8;
9720 inst.instruction |= Rs << 16;
9725 unsigned int value = inst.reloc.exp.X_add_number;
9726 unsigned int shift = inst.operands[2].shift_kind;
9728 Rn = inst.operands[2].reg;
9729 /* See if we can do this with a 16-bit instruction. */
9730 if (!inst.operands[2].shifted && inst.size_req != 4)
9732 if (Rd > 7 || Rs > 7 || Rn > 7)
9737 inst.instruction = ((inst.instruction == T_MNEM_adds
9738 || inst.instruction == T_MNEM_add)
9741 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9745 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9747 /* Thumb-1 cores (except v6-M) require at least one high
9748 register in a narrow non flag setting add. */
9749 if (Rd > 7 || Rn > 7
9750 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9751 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9758 inst.instruction = T_OPCODE_ADD_HI;
9759 inst.instruction |= (Rd & 8) << 4;
9760 inst.instruction |= (Rd & 7);
9761 inst.instruction |= Rn << 3;
9767 constraint (Rd == REG_PC, BAD_PC);
9768 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9769 constraint (Rs == REG_PC, BAD_PC);
9770 reject_bad_reg (Rn);
9772 /* If we get here, it can't be done in 16 bits. */
9773 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9774 _("shift must be constant"));
9775 inst.instruction = THUMB_OP32 (inst.instruction);
9776 inst.instruction |= Rd << 8;
9777 inst.instruction |= Rs << 16;
9778 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9779 _("shift value over 3 not allowed in thumb mode"));
9780 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9781 _("only LSL shift allowed in thumb mode"));
9782 encode_thumb32_shifted_operand (2);
9787 constraint (inst.instruction == T_MNEM_adds
9788 || inst.instruction == T_MNEM_subs,
9791 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9793 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9794 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9797 inst.instruction = (inst.instruction == T_MNEM_add
9799 inst.instruction |= (Rd << 4) | Rs;
9800 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9804 Rn = inst.operands[2].reg;
9805 constraint (inst.operands[2].shifted, _("unshifted register required"));
9807 /* We now have Rd, Rs, and Rn set to registers. */
9808 if (Rd > 7 || Rs > 7 || Rn > 7)
9810 /* Can't do this for SUB. */
9811 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9812 inst.instruction = T_OPCODE_ADD_HI;
9813 inst.instruction |= (Rd & 8) << 4;
9814 inst.instruction |= (Rd & 7);
9816 inst.instruction |= Rn << 3;
9818 inst.instruction |= Rs << 3;
9820 constraint (1, _("dest must overlap one source register"));
9824 inst.instruction = (inst.instruction == T_MNEM_add
9825 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9826 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9836 Rd = inst.operands[0].reg;
9837 reject_bad_reg (Rd);
9839 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9841 /* Defer to section relaxation. */
9842 inst.relax = inst.instruction;
9843 inst.instruction = THUMB_OP16 (inst.instruction);
9844 inst.instruction |= Rd << 4;
9846 else if (unified_syntax && inst.size_req != 2)
9848 /* Generate a 32-bit opcode. */
9849 inst.instruction = THUMB_OP32 (inst.instruction);
9850 inst.instruction |= Rd << 8;
9851 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9852 inst.reloc.pc_rel = 1;
9856 /* Generate a 16-bit opcode. */
9857 inst.instruction = THUMB_OP16 (inst.instruction);
9858 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9859 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9860 inst.reloc.pc_rel = 1;
9862 inst.instruction |= Rd << 4;
9866 /* Arithmetic instructions for which there is just one 16-bit
9867 instruction encoding, and it allows only two low registers.
9868 For maximal compatibility with ARM syntax, we allow three register
9869 operands even when Thumb-32 instructions are not available, as long
9870 as the first two are identical. For instance, both "sbc r0,r1" and
9871 "sbc r0,r0,r1" are allowed. */
9877 Rd = inst.operands[0].reg;
9878 Rs = (inst.operands[1].present
9879 ? inst.operands[1].reg /* Rd, Rs, foo */
9880 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9881 Rn = inst.operands[2].reg;
9883 reject_bad_reg (Rd);
9884 reject_bad_reg (Rs);
9885 if (inst.operands[2].isreg)
9886 reject_bad_reg (Rn);
9890 if (!inst.operands[2].isreg)
9892 /* For an immediate, we always generate a 32-bit opcode;
9893 section relaxation will shrink it later if possible. */
9894 inst.instruction = THUMB_OP32 (inst.instruction);
9895 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9896 inst.instruction |= Rd << 8;
9897 inst.instruction |= Rs << 16;
9898 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9904 /* See if we can do this with a 16-bit instruction. */
9905 if (THUMB_SETS_FLAGS (inst.instruction))
9906 narrow = !in_it_block ();
9908 narrow = in_it_block ();
9910 if (Rd > 7 || Rn > 7 || Rs > 7)
9912 if (inst.operands[2].shifted)
9914 if (inst.size_req == 4)
9920 inst.instruction = THUMB_OP16 (inst.instruction);
9921 inst.instruction |= Rd;
9922 inst.instruction |= Rn << 3;
9926 /* If we get here, it can't be done in 16 bits. */
9927 constraint (inst.operands[2].shifted
9928 && inst.operands[2].immisreg,
9929 _("shift must be constant"));
9930 inst.instruction = THUMB_OP32 (inst.instruction);
9931 inst.instruction |= Rd << 8;
9932 inst.instruction |= Rs << 16;
9933 encode_thumb32_shifted_operand (2);
9938 /* On its face this is a lie - the instruction does set the
9939 flags. However, the only supported mnemonic in this mode
9941 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9943 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9944 _("unshifted register required"));
9945 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9946 constraint (Rd != Rs,
9947 _("dest and source1 must be the same register"));
9949 inst.instruction = THUMB_OP16 (inst.instruction);
9950 inst.instruction |= Rd;
9951 inst.instruction |= Rn << 3;
9955 /* Similarly, but for instructions where the arithmetic operation is
9956 commutative, so we can allow either of them to be different from
9957 the destination operand in a 16-bit instruction. For instance, all
9958 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9965 Rd = inst.operands[0].reg;
9966 Rs = (inst.operands[1].present
9967 ? inst.operands[1].reg /* Rd, Rs, foo */
9968 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9969 Rn = inst.operands[2].reg;
9971 reject_bad_reg (Rd);
9972 reject_bad_reg (Rs);
9973 if (inst.operands[2].isreg)
9974 reject_bad_reg (Rn);
9978 if (!inst.operands[2].isreg)
9980 /* For an immediate, we always generate a 32-bit opcode;
9981 section relaxation will shrink it later if possible. */
9982 inst.instruction = THUMB_OP32 (inst.instruction);
9983 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9984 inst.instruction |= Rd << 8;
9985 inst.instruction |= Rs << 16;
9986 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9992 /* See if we can do this with a 16-bit instruction. */
9993 if (THUMB_SETS_FLAGS (inst.instruction))
9994 narrow = !in_it_block ();
9996 narrow = in_it_block ();
9998 if (Rd > 7 || Rn > 7 || Rs > 7)
10000 if (inst.operands[2].shifted)
10002 if (inst.size_req == 4)
10009 inst.instruction = THUMB_OP16 (inst.instruction);
10010 inst.instruction |= Rd;
10011 inst.instruction |= Rn << 3;
10016 inst.instruction = THUMB_OP16 (inst.instruction);
10017 inst.instruction |= Rd;
10018 inst.instruction |= Rs << 3;
10023 /* If we get here, it can't be done in 16 bits. */
10024 constraint (inst.operands[2].shifted
10025 && inst.operands[2].immisreg,
10026 _("shift must be constant"));
10027 inst.instruction = THUMB_OP32 (inst.instruction);
10028 inst.instruction |= Rd << 8;
10029 inst.instruction |= Rs << 16;
10030 encode_thumb32_shifted_operand (2);
10035 /* On its face this is a lie - the instruction does set the
10036 flags. However, the only supported mnemonic in this mode
10037 says it doesn't. */
10038 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10040 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10041 _("unshifted register required"));
10042 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10044 inst.instruction = THUMB_OP16 (inst.instruction);
10045 inst.instruction |= Rd;
10048 inst.instruction |= Rn << 3;
10050 inst.instruction |= Rs << 3;
10052 constraint (1, _("dest must overlap one source register"));
10060 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10061 constraint (msb > 32, _("bit-field extends past end of register"));
10062 /* The instruction encoding stores the LSB and MSB,
10063 not the LSB and width. */
10064 Rd = inst.operands[0].reg;
10065 reject_bad_reg (Rd);
10066 inst.instruction |= Rd << 8;
10067 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10068 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10069 inst.instruction |= msb - 1;
10078 Rd = inst.operands[0].reg;
10079 reject_bad_reg (Rd);
10081 /* #0 in second position is alternative syntax for bfc, which is
10082 the same instruction but with REG_PC in the Rm field. */
10083 if (!inst.operands[1].isreg)
10087 Rn = inst.operands[1].reg;
10088 reject_bad_reg (Rn);
10091 msb = inst.operands[2].imm + inst.operands[3].imm;
10092 constraint (msb > 32, _("bit-field extends past end of register"));
10093 /* The instruction encoding stores the LSB and MSB,
10094 not the LSB and width. */
10095 inst.instruction |= Rd << 8;
10096 inst.instruction |= Rn << 16;
10097 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10098 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10099 inst.instruction |= msb - 1;
10107 Rd = inst.operands[0].reg;
10108 Rn = inst.operands[1].reg;
10110 reject_bad_reg (Rd);
10111 reject_bad_reg (Rn);
10113 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10114 _("bit-field extends past end of register"));
10115 inst.instruction |= Rd << 8;
10116 inst.instruction |= Rn << 16;
10117 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10118 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10119 inst.instruction |= inst.operands[3].imm - 1;
10122 /* ARM V5 Thumb BLX (argument parse)
10123 BLX <target_addr> which is BLX(1)
10124 BLX <Rm> which is BLX(2)
10125 Unfortunately, there are two different opcodes for this mnemonic.
10126 So, the insns[].value is not used, and the code here zaps values
10127 into inst.instruction.
10129 ??? How to take advantage of the additional two bits of displacement
10130 available in Thumb32 mode? Need new relocation? */
10135 set_it_insn_type_last ();
10137 if (inst.operands[0].isreg)
10139 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10140 /* We have a register, so this is BLX(2). */
10141 inst.instruction |= inst.operands[0].reg << 3;
10145 /* No register. This must be BLX(1). */
10146 inst.instruction = 0xf000e800;
10147 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10159 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10161 if (in_it_block ())
10163 /* Conditional branches inside IT blocks are encoded as unconditional
10165 cond = COND_ALWAYS;
10170 if (cond != COND_ALWAYS)
10171 opcode = T_MNEM_bcond;
10173 opcode = inst.instruction;
10176 && (inst.size_req == 4
10177 || (inst.size_req != 2
10178 && (inst.operands[0].hasreloc
10179 || inst.reloc.exp.X_op == O_constant))))
10181 inst.instruction = THUMB_OP32(opcode);
10182 if (cond == COND_ALWAYS)
10183 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10186 gas_assert (cond != 0xF);
10187 inst.instruction |= cond << 22;
10188 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10193 inst.instruction = THUMB_OP16(opcode);
10194 if (cond == COND_ALWAYS)
10195 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10198 inst.instruction |= cond << 8;
10199 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10201 /* Allow section relaxation. */
10202 if (unified_syntax && inst.size_req != 2)
10203 inst.relax = opcode;
10205 inst.reloc.type = reloc;
10206 inst.reloc.pc_rel = 1;
10209 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10210 between the two is the maximum immediate allowed - which is passed in
10213 do_t_bkpt_hlt1 (int range)
10215 constraint (inst.cond != COND_ALWAYS,
10216 _("instruction is always unconditional"));
10217 if (inst.operands[0].present)
10219 constraint (inst.operands[0].imm > range,
10220 _("immediate value out of range"));
10221 inst.instruction |= inst.operands[0].imm;
10224 set_it_insn_type (NEUTRAL_IT_INSN);
10230 do_t_bkpt_hlt1 (63);
10236 do_t_bkpt_hlt1 (255);
10240 do_t_branch23 (void)
10242 set_it_insn_type_last ();
10243 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10245 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10246 this file. We used to simply ignore the PLT reloc type here --
10247 the branch encoding is now needed to deal with TLSCALL relocs.
10248 So if we see a PLT reloc now, put it back to how it used to be to
10249 keep the preexisting behaviour. */
10250 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10251 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10253 #if defined(OBJ_COFF)
10254 /* If the destination of the branch is a defined symbol which does not have
10255 the THUMB_FUNC attribute, then we must be calling a function which has
10256 the (interfacearm) attribute. We look for the Thumb entry point to that
10257 function and change the branch to refer to that function instead. */
10258 if ( inst.reloc.exp.X_op == O_symbol
10259 && inst.reloc.exp.X_add_symbol != NULL
10260 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10261 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10262 inst.reloc.exp.X_add_symbol =
10263 find_real_start (inst.reloc.exp.X_add_symbol);
10270 set_it_insn_type_last ();
10271 inst.instruction |= inst.operands[0].reg << 3;
10272 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10273 should cause the alignment to be checked once it is known. This is
10274 because BX PC only works if the instruction is word aligned. */
10282 set_it_insn_type_last ();
10283 Rm = inst.operands[0].reg;
10284 reject_bad_reg (Rm);
10285 inst.instruction |= Rm << 16;
10294 Rd = inst.operands[0].reg;
10295 Rm = inst.operands[1].reg;
10297 reject_bad_reg (Rd);
10298 reject_bad_reg (Rm);
10300 inst.instruction |= Rd << 8;
10301 inst.instruction |= Rm << 16;
10302 inst.instruction |= Rm;
10308 set_it_insn_type (OUTSIDE_IT_INSN);
10309 inst.instruction |= inst.operands[0].imm;
10315 set_it_insn_type (OUTSIDE_IT_INSN);
10317 && (inst.operands[1].present || inst.size_req == 4)
10318 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10320 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10321 inst.instruction = 0xf3af8000;
10322 inst.instruction |= imod << 9;
10323 inst.instruction |= inst.operands[0].imm << 5;
10324 if (inst.operands[1].present)
10325 inst.instruction |= 0x100 | inst.operands[1].imm;
10329 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10330 && (inst.operands[0].imm & 4),
10331 _("selected processor does not support 'A' form "
10332 "of this instruction"));
10333 constraint (inst.operands[1].present || inst.size_req == 4,
10334 _("Thumb does not support the 2-argument "
10335 "form of this instruction"));
10336 inst.instruction |= inst.operands[0].imm;
10340 /* THUMB CPY instruction (argument parse). */
10345 if (inst.size_req == 4)
10347 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10348 inst.instruction |= inst.operands[0].reg << 8;
10349 inst.instruction |= inst.operands[1].reg;
10353 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10354 inst.instruction |= (inst.operands[0].reg & 0x7);
10355 inst.instruction |= inst.operands[1].reg << 3;
10362 set_it_insn_type (OUTSIDE_IT_INSN);
10363 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10364 inst.instruction |= inst.operands[0].reg;
10365 inst.reloc.pc_rel = 1;
10366 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10372 inst.instruction |= inst.operands[0].imm;
10378 unsigned Rd, Rn, Rm;
10380 Rd = inst.operands[0].reg;
10381 Rn = (inst.operands[1].present
10382 ? inst.operands[1].reg : Rd);
10383 Rm = inst.operands[2].reg;
10385 reject_bad_reg (Rd);
10386 reject_bad_reg (Rn);
10387 reject_bad_reg (Rm);
10389 inst.instruction |= Rd << 8;
10390 inst.instruction |= Rn << 16;
10391 inst.instruction |= Rm;
10397 if (unified_syntax && inst.size_req == 4)
10398 inst.instruction = THUMB_OP32 (inst.instruction);
10400 inst.instruction = THUMB_OP16 (inst.instruction);
10406 unsigned int cond = inst.operands[0].imm;
10408 set_it_insn_type (IT_INSN);
10409 now_it.mask = (inst.instruction & 0xf) | 0x10;
10411 now_it.warn_deprecated = FALSE;
10413 /* If the condition is a negative condition, invert the mask. */
10414 if ((cond & 0x1) == 0x0)
10416 unsigned int mask = inst.instruction & 0x000f;
10418 if ((mask & 0x7) == 0)
10420 /* No conversion needed. */
10421 now_it.block_length = 1;
10423 else if ((mask & 0x3) == 0)
10426 now_it.block_length = 2;
10428 else if ((mask & 0x1) == 0)
10431 now_it.block_length = 3;
10436 now_it.block_length = 4;
10439 inst.instruction &= 0xfff0;
10440 inst.instruction |= mask;
10443 inst.instruction |= cond << 4;
10446 /* Helper function used for both push/pop and ldm/stm. */
10448 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10452 load = (inst.instruction & (1 << 20)) != 0;
10454 if (mask & (1 << 13))
10455 inst.error = _("SP not allowed in register list");
10457 if ((mask & (1 << base)) != 0
10459 inst.error = _("having the base register in the register list when "
10460 "using write back is UNPREDICTABLE");
10464 if (mask & (1 << 15))
10466 if (mask & (1 << 14))
10467 inst.error = _("LR and PC should not both be in register list");
10469 set_it_insn_type_last ();
10474 if (mask & (1 << 15))
10475 inst.error = _("PC not allowed in register list");
10478 if ((mask & (mask - 1)) == 0)
10480 /* Single register transfers implemented as str/ldr. */
10483 if (inst.instruction & (1 << 23))
10484 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10486 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10490 if (inst.instruction & (1 << 23))
10491 inst.instruction = 0x00800000; /* ia -> [base] */
10493 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10496 inst.instruction |= 0xf8400000;
10498 inst.instruction |= 0x00100000;
10500 mask = ffs (mask) - 1;
10503 else if (writeback)
10504 inst.instruction |= WRITE_BACK;
10506 inst.instruction |= mask;
10507 inst.instruction |= base << 16;
10513 /* This really doesn't seem worth it. */
10514 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10515 _("expression too complex"));
10516 constraint (inst.operands[1].writeback,
10517 _("Thumb load/store multiple does not support {reglist}^"));
10519 if (unified_syntax)
10521 bfd_boolean narrow;
10525 /* See if we can use a 16-bit instruction. */
10526 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10527 && inst.size_req != 4
10528 && !(inst.operands[1].imm & ~0xff))
10530 mask = 1 << inst.operands[0].reg;
10532 if (inst.operands[0].reg <= 7)
10534 if (inst.instruction == T_MNEM_stmia
10535 ? inst.operands[0].writeback
10536 : (inst.operands[0].writeback
10537 == !(inst.operands[1].imm & mask)))
10539 if (inst.instruction == T_MNEM_stmia
10540 && (inst.operands[1].imm & mask)
10541 && (inst.operands[1].imm & (mask - 1)))
10542 as_warn (_("value stored for r%d is UNKNOWN"),
10543 inst.operands[0].reg);
10545 inst.instruction = THUMB_OP16 (inst.instruction);
10546 inst.instruction |= inst.operands[0].reg << 8;
10547 inst.instruction |= inst.operands[1].imm;
10550 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10552 /* This means 1 register in reg list one of 3 situations:
10553 1. Instruction is stmia, but without writeback.
10554 2. lmdia without writeback, but with Rn not in
10556 3. ldmia with writeback, but with Rn in reglist.
10557 Case 3 is UNPREDICTABLE behaviour, so we handle
10558 case 1 and 2 which can be converted into a 16-bit
10559 str or ldr. The SP cases are handled below. */
10560 unsigned long opcode;
10561 /* First, record an error for Case 3. */
10562 if (inst.operands[1].imm & mask
10563 && inst.operands[0].writeback)
10565 _("having the base register in the register list when "
10566 "using write back is UNPREDICTABLE");
10568 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10570 inst.instruction = THUMB_OP16 (opcode);
10571 inst.instruction |= inst.operands[0].reg << 3;
10572 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10576 else if (inst.operands[0] .reg == REG_SP)
10578 if (inst.operands[0].writeback)
10581 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10582 ? T_MNEM_push : T_MNEM_pop);
10583 inst.instruction |= inst.operands[1].imm;
10586 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10589 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10590 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10591 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10599 if (inst.instruction < 0xffff)
10600 inst.instruction = THUMB_OP32 (inst.instruction);
10602 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10603 inst.operands[0].writeback);
10608 constraint (inst.operands[0].reg > 7
10609 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10610 constraint (inst.instruction != T_MNEM_ldmia
10611 && inst.instruction != T_MNEM_stmia,
10612 _("Thumb-2 instruction only valid in unified syntax"));
10613 if (inst.instruction == T_MNEM_stmia)
10615 if (!inst.operands[0].writeback)
10616 as_warn (_("this instruction will write back the base register"));
10617 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10618 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10619 as_warn (_("value stored for r%d is UNKNOWN"),
10620 inst.operands[0].reg);
10624 if (!inst.operands[0].writeback
10625 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10626 as_warn (_("this instruction will write back the base register"));
10627 else if (inst.operands[0].writeback
10628 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10629 as_warn (_("this instruction will not write back the base register"));
10632 inst.instruction = THUMB_OP16 (inst.instruction);
10633 inst.instruction |= inst.operands[0].reg << 8;
10634 inst.instruction |= inst.operands[1].imm;
10641 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10642 || inst.operands[1].postind || inst.operands[1].writeback
10643 || inst.operands[1].immisreg || inst.operands[1].shifted
10644 || inst.operands[1].negative,
10647 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10649 inst.instruction |= inst.operands[0].reg << 12;
10650 inst.instruction |= inst.operands[1].reg << 16;
10651 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10657 if (!inst.operands[1].present)
10659 constraint (inst.operands[0].reg == REG_LR,
10660 _("r14 not allowed as first register "
10661 "when second register is omitted"));
10662 inst.operands[1].reg = inst.operands[0].reg + 1;
10664 constraint (inst.operands[0].reg == inst.operands[1].reg,
10667 inst.instruction |= inst.operands[0].reg << 12;
10668 inst.instruction |= inst.operands[1].reg << 8;
10669 inst.instruction |= inst.operands[2].reg << 16;
10675 unsigned long opcode;
10678 if (inst.operands[0].isreg
10679 && !inst.operands[0].preind
10680 && inst.operands[0].reg == REG_PC)
10681 set_it_insn_type_last ();
10683 opcode = inst.instruction;
10684 if (unified_syntax)
10686 if (!inst.operands[1].isreg)
10688 if (opcode <= 0xffff)
10689 inst.instruction = THUMB_OP32 (opcode);
10690 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10693 if (inst.operands[1].isreg
10694 && !inst.operands[1].writeback
10695 && !inst.operands[1].shifted && !inst.operands[1].postind
10696 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10697 && opcode <= 0xffff
10698 && inst.size_req != 4)
10700 /* Insn may have a 16-bit form. */
10701 Rn = inst.operands[1].reg;
10702 if (inst.operands[1].immisreg)
10704 inst.instruction = THUMB_OP16 (opcode);
10706 if (Rn <= 7 && inst.operands[1].imm <= 7)
10708 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10709 reject_bad_reg (inst.operands[1].imm);
10711 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10712 && opcode != T_MNEM_ldrsb)
10713 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10714 || (Rn == REG_SP && opcode == T_MNEM_str))
10721 if (inst.reloc.pc_rel)
10722 opcode = T_MNEM_ldr_pc2;
10724 opcode = T_MNEM_ldr_pc;
10728 if (opcode == T_MNEM_ldr)
10729 opcode = T_MNEM_ldr_sp;
10731 opcode = T_MNEM_str_sp;
10733 inst.instruction = inst.operands[0].reg << 8;
10737 inst.instruction = inst.operands[0].reg;
10738 inst.instruction |= inst.operands[1].reg << 3;
10740 inst.instruction |= THUMB_OP16 (opcode);
10741 if (inst.size_req == 2)
10742 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10744 inst.relax = opcode;
10748 /* Definitely a 32-bit variant. */
10750 /* Warning for Erratum 752419. */
10751 if (opcode == T_MNEM_ldr
10752 && inst.operands[0].reg == REG_SP
10753 && inst.operands[1].writeback == 1
10754 && !inst.operands[1].immisreg)
10756 if (no_cpu_selected ()
10757 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10758 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10759 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10760 as_warn (_("This instruction may be unpredictable "
10761 "if executed on M-profile cores "
10762 "with interrupts enabled."));
10765 /* Do some validations regarding addressing modes. */
10766 if (inst.operands[1].immisreg)
10767 reject_bad_reg (inst.operands[1].imm);
10769 constraint (inst.operands[1].writeback == 1
10770 && inst.operands[0].reg == inst.operands[1].reg,
10773 inst.instruction = THUMB_OP32 (opcode);
10774 inst.instruction |= inst.operands[0].reg << 12;
10775 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10776 check_ldr_r15_aligned ();
10780 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10782 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10784 /* Only [Rn,Rm] is acceptable. */
10785 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10786 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10787 || inst.operands[1].postind || inst.operands[1].shifted
10788 || inst.operands[1].negative,
10789 _("Thumb does not support this addressing mode"));
10790 inst.instruction = THUMB_OP16 (inst.instruction);
10794 inst.instruction = THUMB_OP16 (inst.instruction);
10795 if (!inst.operands[1].isreg)
10796 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10799 constraint (!inst.operands[1].preind
10800 || inst.operands[1].shifted
10801 || inst.operands[1].writeback,
10802 _("Thumb does not support this addressing mode"));
10803 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10805 constraint (inst.instruction & 0x0600,
10806 _("byte or halfword not valid for base register"));
10807 constraint (inst.operands[1].reg == REG_PC
10808 && !(inst.instruction & THUMB_LOAD_BIT),
10809 _("r15 based store not allowed"));
10810 constraint (inst.operands[1].immisreg,
10811 _("invalid base register for register offset"));
10813 if (inst.operands[1].reg == REG_PC)
10814 inst.instruction = T_OPCODE_LDR_PC;
10815 else if (inst.instruction & THUMB_LOAD_BIT)
10816 inst.instruction = T_OPCODE_LDR_SP;
10818 inst.instruction = T_OPCODE_STR_SP;
10820 inst.instruction |= inst.operands[0].reg << 8;
10821 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10825 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10826 if (!inst.operands[1].immisreg)
10828 /* Immediate offset. */
10829 inst.instruction |= inst.operands[0].reg;
10830 inst.instruction |= inst.operands[1].reg << 3;
10831 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10835 /* Register offset. */
10836 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10837 constraint (inst.operands[1].negative,
10838 _("Thumb does not support this addressing mode"));
10841 switch (inst.instruction)
10843 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10844 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10845 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10846 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10847 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10848 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10849 case 0x5600 /* ldrsb */:
10850 case 0x5e00 /* ldrsh */: break;
10854 inst.instruction |= inst.operands[0].reg;
10855 inst.instruction |= inst.operands[1].reg << 3;
10856 inst.instruction |= inst.operands[1].imm << 6;
10862 if (!inst.operands[1].present)
10864 inst.operands[1].reg = inst.operands[0].reg + 1;
10865 constraint (inst.operands[0].reg == REG_LR,
10866 _("r14 not allowed here"));
10867 constraint (inst.operands[0].reg == REG_R12,
10868 _("r12 not allowed here"));
10871 if (inst.operands[2].writeback
10872 && (inst.operands[0].reg == inst.operands[2].reg
10873 || inst.operands[1].reg == inst.operands[2].reg))
10874 as_warn (_("base register written back, and overlaps "
10875 "one of transfer registers"));
10877 inst.instruction |= inst.operands[0].reg << 12;
10878 inst.instruction |= inst.operands[1].reg << 8;
10879 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10885 inst.instruction |= inst.operands[0].reg << 12;
10886 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10892 unsigned Rd, Rn, Rm, Ra;
10894 Rd = inst.operands[0].reg;
10895 Rn = inst.operands[1].reg;
10896 Rm = inst.operands[2].reg;
10897 Ra = inst.operands[3].reg;
10899 reject_bad_reg (Rd);
10900 reject_bad_reg (Rn);
10901 reject_bad_reg (Rm);
10902 reject_bad_reg (Ra);
10904 inst.instruction |= Rd << 8;
10905 inst.instruction |= Rn << 16;
10906 inst.instruction |= Rm;
10907 inst.instruction |= Ra << 12;
10913 unsigned RdLo, RdHi, Rn, Rm;
10915 RdLo = inst.operands[0].reg;
10916 RdHi = inst.operands[1].reg;
10917 Rn = inst.operands[2].reg;
10918 Rm = inst.operands[3].reg;
10920 reject_bad_reg (RdLo);
10921 reject_bad_reg (RdHi);
10922 reject_bad_reg (Rn);
10923 reject_bad_reg (Rm);
10925 inst.instruction |= RdLo << 12;
10926 inst.instruction |= RdHi << 8;
10927 inst.instruction |= Rn << 16;
10928 inst.instruction |= Rm;
10932 do_t_mov_cmp (void)
10936 Rn = inst.operands[0].reg;
10937 Rm = inst.operands[1].reg;
10940 set_it_insn_type_last ();
10942 if (unified_syntax)
10944 int r0off = (inst.instruction == T_MNEM_mov
10945 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10946 unsigned long opcode;
10947 bfd_boolean narrow;
10948 bfd_boolean low_regs;
10950 low_regs = (Rn <= 7 && Rm <= 7);
10951 opcode = inst.instruction;
10952 if (in_it_block ())
10953 narrow = opcode != T_MNEM_movs;
10955 narrow = opcode != T_MNEM_movs || low_regs;
10956 if (inst.size_req == 4
10957 || inst.operands[1].shifted)
10960 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10961 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10962 && !inst.operands[1].shifted
10966 inst.instruction = T2_SUBS_PC_LR;
10970 if (opcode == T_MNEM_cmp)
10972 constraint (Rn == REG_PC, BAD_PC);
10975 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10977 warn_deprecated_sp (Rm);
10978 /* R15 was documented as a valid choice for Rm in ARMv6,
10979 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10980 tools reject R15, so we do too. */
10981 constraint (Rm == REG_PC, BAD_PC);
10984 reject_bad_reg (Rm);
10986 else if (opcode == T_MNEM_mov
10987 || opcode == T_MNEM_movs)
10989 if (inst.operands[1].isreg)
10991 if (opcode == T_MNEM_movs)
10993 reject_bad_reg (Rn);
10994 reject_bad_reg (Rm);
10998 /* This is mov.n. */
10999 if ((Rn == REG_SP || Rn == REG_PC)
11000 && (Rm == REG_SP || Rm == REG_PC))
11002 as_warn (_("Use of r%u as a source register is "
11003 "deprecated when r%u is the destination "
11004 "register."), Rm, Rn);
11009 /* This is mov.w. */
11010 constraint (Rn == REG_PC, BAD_PC);
11011 constraint (Rm == REG_PC, BAD_PC);
11012 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11016 reject_bad_reg (Rn);
11019 if (!inst.operands[1].isreg)
11021 /* Immediate operand. */
11022 if (!in_it_block () && opcode == T_MNEM_mov)
11024 if (low_regs && narrow)
11026 inst.instruction = THUMB_OP16 (opcode);
11027 inst.instruction |= Rn << 8;
11028 if (inst.size_req == 2)
11029 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11031 inst.relax = opcode;
11035 inst.instruction = THUMB_OP32 (inst.instruction);
11036 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11037 inst.instruction |= Rn << r0off;
11038 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11041 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11042 && (inst.instruction == T_MNEM_mov
11043 || inst.instruction == T_MNEM_movs))
11045 /* Register shifts are encoded as separate shift instructions. */
11046 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11048 if (in_it_block ())
11053 if (inst.size_req == 4)
11056 if (!low_regs || inst.operands[1].imm > 7)
11062 switch (inst.operands[1].shift_kind)
11065 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11068 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11071 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11074 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11080 inst.instruction = opcode;
11083 inst.instruction |= Rn;
11084 inst.instruction |= inst.operands[1].imm << 3;
11089 inst.instruction |= CONDS_BIT;
11091 inst.instruction |= Rn << 8;
11092 inst.instruction |= Rm << 16;
11093 inst.instruction |= inst.operands[1].imm;
11098 /* Some mov with immediate shift have narrow variants.
11099 Register shifts are handled above. */
11100 if (low_regs && inst.operands[1].shifted
11101 && (inst.instruction == T_MNEM_mov
11102 || inst.instruction == T_MNEM_movs))
11104 if (in_it_block ())
11105 narrow = (inst.instruction == T_MNEM_mov);
11107 narrow = (inst.instruction == T_MNEM_movs);
11112 switch (inst.operands[1].shift_kind)
11114 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11115 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11116 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11117 default: narrow = FALSE; break;
11123 inst.instruction |= Rn;
11124 inst.instruction |= Rm << 3;
11125 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11129 inst.instruction = THUMB_OP32 (inst.instruction);
11130 inst.instruction |= Rn << r0off;
11131 encode_thumb32_shifted_operand (1);
11135 switch (inst.instruction)
11138 /* In v4t or v5t a move of two lowregs produces unpredictable
11139 results. Don't allow this. */
11142 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11143 "MOV Rd, Rs with two low registers is not "
11144 "permitted on this architecture");
11145 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11149 inst.instruction = T_OPCODE_MOV_HR;
11150 inst.instruction |= (Rn & 0x8) << 4;
11151 inst.instruction |= (Rn & 0x7);
11152 inst.instruction |= Rm << 3;
11156 /* We know we have low registers at this point.
11157 Generate LSLS Rd, Rs, #0. */
11158 inst.instruction = T_OPCODE_LSL_I;
11159 inst.instruction |= Rn;
11160 inst.instruction |= Rm << 3;
11166 inst.instruction = T_OPCODE_CMP_LR;
11167 inst.instruction |= Rn;
11168 inst.instruction |= Rm << 3;
11172 inst.instruction = T_OPCODE_CMP_HR;
11173 inst.instruction |= (Rn & 0x8) << 4;
11174 inst.instruction |= (Rn & 0x7);
11175 inst.instruction |= Rm << 3;
11182 inst.instruction = THUMB_OP16 (inst.instruction);
11184 /* PR 10443: Do not silently ignore shifted operands. */
11185 constraint (inst.operands[1].shifted,
11186 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11188 if (inst.operands[1].isreg)
11190 if (Rn < 8 && Rm < 8)
11192 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11193 since a MOV instruction produces unpredictable results. */
11194 if (inst.instruction == T_OPCODE_MOV_I8)
11195 inst.instruction = T_OPCODE_ADD_I3;
11197 inst.instruction = T_OPCODE_CMP_LR;
11199 inst.instruction |= Rn;
11200 inst.instruction |= Rm << 3;
11204 if (inst.instruction == T_OPCODE_MOV_I8)
11205 inst.instruction = T_OPCODE_MOV_HR;
11207 inst.instruction = T_OPCODE_CMP_HR;
11213 constraint (Rn > 7,
11214 _("only lo regs allowed with immediate"));
11215 inst.instruction |= Rn << 8;
11216 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11227 top = (inst.instruction & 0x00800000) != 0;
11228 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11230 constraint (top, _(":lower16: not allowed this instruction"));
11231 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11233 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11235 constraint (!top, _(":upper16: not allowed this instruction"));
11236 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11239 Rd = inst.operands[0].reg;
11240 reject_bad_reg (Rd);
11242 inst.instruction |= Rd << 8;
11243 if (inst.reloc.type == BFD_RELOC_UNUSED)
11245 imm = inst.reloc.exp.X_add_number;
11246 inst.instruction |= (imm & 0xf000) << 4;
11247 inst.instruction |= (imm & 0x0800) << 15;
11248 inst.instruction |= (imm & 0x0700) << 4;
11249 inst.instruction |= (imm & 0x00ff);
11254 do_t_mvn_tst (void)
11258 Rn = inst.operands[0].reg;
11259 Rm = inst.operands[1].reg;
11261 if (inst.instruction == T_MNEM_cmp
11262 || inst.instruction == T_MNEM_cmn)
11263 constraint (Rn == REG_PC, BAD_PC);
11265 reject_bad_reg (Rn);
11266 reject_bad_reg (Rm);
11268 if (unified_syntax)
11270 int r0off = (inst.instruction == T_MNEM_mvn
11271 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11272 bfd_boolean narrow;
11274 if (inst.size_req == 4
11275 || inst.instruction > 0xffff
11276 || inst.operands[1].shifted
11277 || Rn > 7 || Rm > 7)
11279 else if (inst.instruction == T_MNEM_cmn
11280 || inst.instruction == T_MNEM_tst)
11282 else if (THUMB_SETS_FLAGS (inst.instruction))
11283 narrow = !in_it_block ();
11285 narrow = in_it_block ();
11287 if (!inst.operands[1].isreg)
11289 /* For an immediate, we always generate a 32-bit opcode;
11290 section relaxation will shrink it later if possible. */
11291 if (inst.instruction < 0xffff)
11292 inst.instruction = THUMB_OP32 (inst.instruction);
11293 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11294 inst.instruction |= Rn << r0off;
11295 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11299 /* See if we can do this with a 16-bit instruction. */
11302 inst.instruction = THUMB_OP16 (inst.instruction);
11303 inst.instruction |= Rn;
11304 inst.instruction |= Rm << 3;
11308 constraint (inst.operands[1].shifted
11309 && inst.operands[1].immisreg,
11310 _("shift must be constant"));
11311 if (inst.instruction < 0xffff)
11312 inst.instruction = THUMB_OP32 (inst.instruction);
11313 inst.instruction |= Rn << r0off;
11314 encode_thumb32_shifted_operand (1);
11320 constraint (inst.instruction > 0xffff
11321 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11322 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11323 _("unshifted register required"));
11324 constraint (Rn > 7 || Rm > 7,
11327 inst.instruction = THUMB_OP16 (inst.instruction);
11328 inst.instruction |= Rn;
11329 inst.instruction |= Rm << 3;
11338 if (do_vfp_nsyn_mrs () == SUCCESS)
11341 Rd = inst.operands[0].reg;
11342 reject_bad_reg (Rd);
11343 inst.instruction |= Rd << 8;
11345 if (inst.operands[1].isreg)
11347 unsigned br = inst.operands[1].reg;
11348 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11349 as_bad (_("bad register for mrs"));
11351 inst.instruction |= br & (0xf << 16);
11352 inst.instruction |= (br & 0x300) >> 4;
11353 inst.instruction |= (br & SPSR_BIT) >> 2;
11357 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11359 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11361 /* PR gas/12698: The constraint is only applied for m_profile.
11362 If the user has specified -march=all, we want to ignore it as
11363 we are building for any CPU type, including non-m variants. */
11364 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11365 constraint ((flags != 0) && m_profile, _("selected processor does "
11366 "not support requested special purpose register"));
11369 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11371 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11372 _("'APSR', 'CPSR' or 'SPSR' expected"));
11374 inst.instruction |= (flags & SPSR_BIT) >> 2;
11375 inst.instruction |= inst.operands[1].imm & 0xff;
11376 inst.instruction |= 0xf0000;
11386 if (do_vfp_nsyn_msr () == SUCCESS)
11389 constraint (!inst.operands[1].isreg,
11390 _("Thumb encoding does not support an immediate here"));
11392 if (inst.operands[0].isreg)
11393 flags = (int)(inst.operands[0].reg);
11395 flags = inst.operands[0].imm;
11397 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11399 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11401 /* PR gas/12698: The constraint is only applied for m_profile.
11402 If the user has specified -march=all, we want to ignore it as
11403 we are building for any CPU type, including non-m variants. */
11404 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11405 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11406 && (bits & ~(PSR_s | PSR_f)) != 0)
11407 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11408 && bits != PSR_f)) && m_profile,
11409 _("selected processor does not support requested special "
11410 "purpose register"));
11413 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11414 "requested special purpose register"));
11416 Rn = inst.operands[1].reg;
11417 reject_bad_reg (Rn);
11419 inst.instruction |= (flags & SPSR_BIT) >> 2;
11420 inst.instruction |= (flags & 0xf0000) >> 8;
11421 inst.instruction |= (flags & 0x300) >> 4;
11422 inst.instruction |= (flags & 0xff);
11423 inst.instruction |= Rn << 16;
11429 bfd_boolean narrow;
11430 unsigned Rd, Rn, Rm;
11432 if (!inst.operands[2].present)
11433 inst.operands[2].reg = inst.operands[0].reg;
11435 Rd = inst.operands[0].reg;
11436 Rn = inst.operands[1].reg;
11437 Rm = inst.operands[2].reg;
11439 if (unified_syntax)
11441 if (inst.size_req == 4
11447 else if (inst.instruction == T_MNEM_muls)
11448 narrow = !in_it_block ();
11450 narrow = in_it_block ();
11454 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11455 constraint (Rn > 7 || Rm > 7,
11462 /* 16-bit MULS/Conditional MUL. */
11463 inst.instruction = THUMB_OP16 (inst.instruction);
11464 inst.instruction |= Rd;
11467 inst.instruction |= Rm << 3;
11469 inst.instruction |= Rn << 3;
11471 constraint (1, _("dest must overlap one source register"));
11475 constraint (inst.instruction != T_MNEM_mul,
11476 _("Thumb-2 MUL must not set flags"));
11478 inst.instruction = THUMB_OP32 (inst.instruction);
11479 inst.instruction |= Rd << 8;
11480 inst.instruction |= Rn << 16;
11481 inst.instruction |= Rm << 0;
11483 reject_bad_reg (Rd);
11484 reject_bad_reg (Rn);
11485 reject_bad_reg (Rm);
11492 unsigned RdLo, RdHi, Rn, Rm;
11494 RdLo = inst.operands[0].reg;
11495 RdHi = inst.operands[1].reg;
11496 Rn = inst.operands[2].reg;
11497 Rm = inst.operands[3].reg;
11499 reject_bad_reg (RdLo);
11500 reject_bad_reg (RdHi);
11501 reject_bad_reg (Rn);
11502 reject_bad_reg (Rm);
11504 inst.instruction |= RdLo << 12;
11505 inst.instruction |= RdHi << 8;
11506 inst.instruction |= Rn << 16;
11507 inst.instruction |= Rm;
11510 as_tsktsk (_("rdhi and rdlo must be different"));
11516 set_it_insn_type (NEUTRAL_IT_INSN);
11518 if (unified_syntax)
11520 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11522 inst.instruction = THUMB_OP32 (inst.instruction);
11523 inst.instruction |= inst.operands[0].imm;
11527 /* PR9722: Check for Thumb2 availability before
11528 generating a thumb2 nop instruction. */
11529 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11531 inst.instruction = THUMB_OP16 (inst.instruction);
11532 inst.instruction |= inst.operands[0].imm << 4;
11535 inst.instruction = 0x46c0;
11540 constraint (inst.operands[0].present,
11541 _("Thumb does not support NOP with hints"));
11542 inst.instruction = 0x46c0;
11549 if (unified_syntax)
11551 bfd_boolean narrow;
11553 if (THUMB_SETS_FLAGS (inst.instruction))
11554 narrow = !in_it_block ();
11556 narrow = in_it_block ();
11557 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11559 if (inst.size_req == 4)
11564 inst.instruction = THUMB_OP32 (inst.instruction);
11565 inst.instruction |= inst.operands[0].reg << 8;
11566 inst.instruction |= inst.operands[1].reg << 16;
11570 inst.instruction = THUMB_OP16 (inst.instruction);
11571 inst.instruction |= inst.operands[0].reg;
11572 inst.instruction |= inst.operands[1].reg << 3;
11577 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11579 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11581 inst.instruction = THUMB_OP16 (inst.instruction);
11582 inst.instruction |= inst.operands[0].reg;
11583 inst.instruction |= inst.operands[1].reg << 3;
11592 Rd = inst.operands[0].reg;
11593 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11595 reject_bad_reg (Rd);
11596 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11597 reject_bad_reg (Rn);
11599 inst.instruction |= Rd << 8;
11600 inst.instruction |= Rn << 16;
11602 if (!inst.operands[2].isreg)
11604 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11605 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11611 Rm = inst.operands[2].reg;
11612 reject_bad_reg (Rm);
11614 constraint (inst.operands[2].shifted
11615 && inst.operands[2].immisreg,
11616 _("shift must be constant"));
11617 encode_thumb32_shifted_operand (2);
11624 unsigned Rd, Rn, Rm;
11626 Rd = inst.operands[0].reg;
11627 Rn = inst.operands[1].reg;
11628 Rm = inst.operands[2].reg;
11630 reject_bad_reg (Rd);
11631 reject_bad_reg (Rn);
11632 reject_bad_reg (Rm);
11634 inst.instruction |= Rd << 8;
11635 inst.instruction |= Rn << 16;
11636 inst.instruction |= Rm;
11637 if (inst.operands[3].present)
11639 unsigned int val = inst.reloc.exp.X_add_number;
11640 constraint (inst.reloc.exp.X_op != O_constant,
11641 _("expression too complex"));
11642 inst.instruction |= (val & 0x1c) << 10;
11643 inst.instruction |= (val & 0x03) << 6;
11650 if (!inst.operands[3].present)
11654 inst.instruction &= ~0x00000020;
11656 /* PR 10168. Swap the Rm and Rn registers. */
11657 Rtmp = inst.operands[1].reg;
11658 inst.operands[1].reg = inst.operands[2].reg;
11659 inst.operands[2].reg = Rtmp;
11667 if (inst.operands[0].immisreg)
11668 reject_bad_reg (inst.operands[0].imm);
11670 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11674 do_t_push_pop (void)
11678 constraint (inst.operands[0].writeback,
11679 _("push/pop do not support {reglist}^"));
11680 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11681 _("expression too complex"));
11683 mask = inst.operands[0].imm;
11684 if (inst.size_req != 4 && (mask & ~0xff) == 0)
11685 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11686 else if (inst.size_req != 4
11687 && (mask & ~0xff) == (1 << (inst.instruction == T_MNEM_push
11688 ? REG_LR : REG_PC)))
11690 inst.instruction = THUMB_OP16 (inst.instruction);
11691 inst.instruction |= THUMB_PP_PC_LR;
11692 inst.instruction |= mask & 0xff;
11694 else if (unified_syntax)
11696 inst.instruction = THUMB_OP32 (inst.instruction);
11697 encode_thumb2_ldmstm (13, mask, TRUE);
11701 inst.error = _("invalid register list to push/pop instruction");
11711 Rd = inst.operands[0].reg;
11712 Rm = inst.operands[1].reg;
11714 reject_bad_reg (Rd);
11715 reject_bad_reg (Rm);
11717 inst.instruction |= Rd << 8;
11718 inst.instruction |= Rm << 16;
11719 inst.instruction |= Rm;
11727 Rd = inst.operands[0].reg;
11728 Rm = inst.operands[1].reg;
11730 reject_bad_reg (Rd);
11731 reject_bad_reg (Rm);
11733 if (Rd <= 7 && Rm <= 7
11734 && inst.size_req != 4)
11736 inst.instruction = THUMB_OP16 (inst.instruction);
11737 inst.instruction |= Rd;
11738 inst.instruction |= Rm << 3;
11740 else if (unified_syntax)
11742 inst.instruction = THUMB_OP32 (inst.instruction);
11743 inst.instruction |= Rd << 8;
11744 inst.instruction |= Rm << 16;
11745 inst.instruction |= Rm;
11748 inst.error = BAD_HIREG;
11756 Rd = inst.operands[0].reg;
11757 Rm = inst.operands[1].reg;
11759 reject_bad_reg (Rd);
11760 reject_bad_reg (Rm);
11762 inst.instruction |= Rd << 8;
11763 inst.instruction |= Rm;
11771 Rd = inst.operands[0].reg;
11772 Rs = (inst.operands[1].present
11773 ? inst.operands[1].reg /* Rd, Rs, foo */
11774 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11776 reject_bad_reg (Rd);
11777 reject_bad_reg (Rs);
11778 if (inst.operands[2].isreg)
11779 reject_bad_reg (inst.operands[2].reg);
11781 inst.instruction |= Rd << 8;
11782 inst.instruction |= Rs << 16;
11783 if (!inst.operands[2].isreg)
11785 bfd_boolean narrow;
11787 if ((inst.instruction & 0x00100000) != 0)
11788 narrow = !in_it_block ();
11790 narrow = in_it_block ();
11792 if (Rd > 7 || Rs > 7)
11795 if (inst.size_req == 4 || !unified_syntax)
11798 if (inst.reloc.exp.X_op != O_constant
11799 || inst.reloc.exp.X_add_number != 0)
11802 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11803 relaxation, but it doesn't seem worth the hassle. */
11806 inst.reloc.type = BFD_RELOC_UNUSED;
11807 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11808 inst.instruction |= Rs << 3;
11809 inst.instruction |= Rd;
11813 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11814 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11818 encode_thumb32_shifted_operand (2);
11824 if (warn_on_deprecated
11825 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11826 as_warn (_("setend use is deprecated for ARMv8"));
11828 set_it_insn_type (OUTSIDE_IT_INSN);
11829 if (inst.operands[0].imm)
11830 inst.instruction |= 0x8;
11836 if (!inst.operands[1].present)
11837 inst.operands[1].reg = inst.operands[0].reg;
11839 if (unified_syntax)
11841 bfd_boolean narrow;
11844 switch (inst.instruction)
11847 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11849 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11851 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11853 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11857 if (THUMB_SETS_FLAGS (inst.instruction))
11858 narrow = !in_it_block ();
11860 narrow = in_it_block ();
11861 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11863 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11865 if (inst.operands[2].isreg
11866 && (inst.operands[1].reg != inst.operands[0].reg
11867 || inst.operands[2].reg > 7))
11869 if (inst.size_req == 4)
11872 reject_bad_reg (inst.operands[0].reg);
11873 reject_bad_reg (inst.operands[1].reg);
11877 if (inst.operands[2].isreg)
11879 reject_bad_reg (inst.operands[2].reg);
11880 inst.instruction = THUMB_OP32 (inst.instruction);
11881 inst.instruction |= inst.operands[0].reg << 8;
11882 inst.instruction |= inst.operands[1].reg << 16;
11883 inst.instruction |= inst.operands[2].reg;
11885 /* PR 12854: Error on extraneous shifts. */
11886 constraint (inst.operands[2].shifted,
11887 _("extraneous shift as part of operand to shift insn"));
11891 inst.operands[1].shifted = 1;
11892 inst.operands[1].shift_kind = shift_kind;
11893 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11894 ? T_MNEM_movs : T_MNEM_mov);
11895 inst.instruction |= inst.operands[0].reg << 8;
11896 encode_thumb32_shifted_operand (1);
11897 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11898 inst.reloc.type = BFD_RELOC_UNUSED;
11903 if (inst.operands[2].isreg)
11905 switch (shift_kind)
11907 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11908 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11909 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11910 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11914 inst.instruction |= inst.operands[0].reg;
11915 inst.instruction |= inst.operands[2].reg << 3;
11917 /* PR 12854: Error on extraneous shifts. */
11918 constraint (inst.operands[2].shifted,
11919 _("extraneous shift as part of operand to shift insn"));
11923 switch (shift_kind)
11925 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11926 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11927 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11930 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11931 inst.instruction |= inst.operands[0].reg;
11932 inst.instruction |= inst.operands[1].reg << 3;
11938 constraint (inst.operands[0].reg > 7
11939 || inst.operands[1].reg > 7, BAD_HIREG);
11940 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11942 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11944 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11945 constraint (inst.operands[0].reg != inst.operands[1].reg,
11946 _("source1 and dest must be same register"));
11948 switch (inst.instruction)
11950 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11951 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11952 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11953 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11957 inst.instruction |= inst.operands[0].reg;
11958 inst.instruction |= inst.operands[2].reg << 3;
11960 /* PR 12854: Error on extraneous shifts. */
11961 constraint (inst.operands[2].shifted,
11962 _("extraneous shift as part of operand to shift insn"));
11966 switch (inst.instruction)
11968 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11969 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11970 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11971 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11974 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11975 inst.instruction |= inst.operands[0].reg;
11976 inst.instruction |= inst.operands[1].reg << 3;
11984 unsigned Rd, Rn, Rm;
11986 Rd = inst.operands[0].reg;
11987 Rn = inst.operands[1].reg;
11988 Rm = inst.operands[2].reg;
11990 reject_bad_reg (Rd);
11991 reject_bad_reg (Rn);
11992 reject_bad_reg (Rm);
11994 inst.instruction |= Rd << 8;
11995 inst.instruction |= Rn << 16;
11996 inst.instruction |= Rm;
12002 unsigned Rd, Rn, Rm;
12004 Rd = inst.operands[0].reg;
12005 Rm = inst.operands[1].reg;
12006 Rn = inst.operands[2].reg;
12008 reject_bad_reg (Rd);
12009 reject_bad_reg (Rn);
12010 reject_bad_reg (Rm);
12012 inst.instruction |= Rd << 8;
12013 inst.instruction |= Rn << 16;
12014 inst.instruction |= Rm;
12020 unsigned int value = inst.reloc.exp.X_add_number;
12021 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12022 _("SMC is not permitted on this architecture"));
12023 constraint (inst.reloc.exp.X_op != O_constant,
12024 _("expression too complex"));
12025 inst.reloc.type = BFD_RELOC_UNUSED;
12026 inst.instruction |= (value & 0xf000) >> 12;
12027 inst.instruction |= (value & 0x0ff0);
12028 inst.instruction |= (value & 0x000f) << 16;
12029 /* PR gas/15623: SMC instructions must be last in an IT block. */
12030 set_it_insn_type_last ();
12036 unsigned int value = inst.reloc.exp.X_add_number;
12038 inst.reloc.type = BFD_RELOC_UNUSED;
12039 inst.instruction |= (value & 0x0fff);
12040 inst.instruction |= (value & 0xf000) << 4;
12044 do_t_ssat_usat (int bias)
12048 Rd = inst.operands[0].reg;
12049 Rn = inst.operands[2].reg;
12051 reject_bad_reg (Rd);
12052 reject_bad_reg (Rn);
12054 inst.instruction |= Rd << 8;
12055 inst.instruction |= inst.operands[1].imm - bias;
12056 inst.instruction |= Rn << 16;
12058 if (inst.operands[3].present)
12060 offsetT shift_amount = inst.reloc.exp.X_add_number;
12062 inst.reloc.type = BFD_RELOC_UNUSED;
12064 constraint (inst.reloc.exp.X_op != O_constant,
12065 _("expression too complex"));
12067 if (shift_amount != 0)
12069 constraint (shift_amount > 31,
12070 _("shift expression is too large"));
12072 if (inst.operands[3].shift_kind == SHIFT_ASR)
12073 inst.instruction |= 0x00200000; /* sh bit. */
12075 inst.instruction |= (shift_amount & 0x1c) << 10;
12076 inst.instruction |= (shift_amount & 0x03) << 6;
12084 do_t_ssat_usat (1);
12092 Rd = inst.operands[0].reg;
12093 Rn = inst.operands[2].reg;
12095 reject_bad_reg (Rd);
12096 reject_bad_reg (Rn);
12098 inst.instruction |= Rd << 8;
12099 inst.instruction |= inst.operands[1].imm - 1;
12100 inst.instruction |= Rn << 16;
12106 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12107 || inst.operands[2].postind || inst.operands[2].writeback
12108 || inst.operands[2].immisreg || inst.operands[2].shifted
12109 || inst.operands[2].negative,
12112 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12114 inst.instruction |= inst.operands[0].reg << 8;
12115 inst.instruction |= inst.operands[1].reg << 12;
12116 inst.instruction |= inst.operands[2].reg << 16;
12117 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12123 if (!inst.operands[2].present)
12124 inst.operands[2].reg = inst.operands[1].reg + 1;
12126 constraint (inst.operands[0].reg == inst.operands[1].reg
12127 || inst.operands[0].reg == inst.operands[2].reg
12128 || inst.operands[0].reg == inst.operands[3].reg,
12131 inst.instruction |= inst.operands[0].reg;
12132 inst.instruction |= inst.operands[1].reg << 12;
12133 inst.instruction |= inst.operands[2].reg << 8;
12134 inst.instruction |= inst.operands[3].reg << 16;
12140 unsigned Rd, Rn, Rm;
12142 Rd = inst.operands[0].reg;
12143 Rn = inst.operands[1].reg;
12144 Rm = inst.operands[2].reg;
12146 reject_bad_reg (Rd);
12147 reject_bad_reg (Rn);
12148 reject_bad_reg (Rm);
12150 inst.instruction |= Rd << 8;
12151 inst.instruction |= Rn << 16;
12152 inst.instruction |= Rm;
12153 inst.instruction |= inst.operands[3].imm << 4;
12161 Rd = inst.operands[0].reg;
12162 Rm = inst.operands[1].reg;
12164 reject_bad_reg (Rd);
12165 reject_bad_reg (Rm);
12167 if (inst.instruction <= 0xffff
12168 && inst.size_req != 4
12169 && Rd <= 7 && Rm <= 7
12170 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12172 inst.instruction = THUMB_OP16 (inst.instruction);
12173 inst.instruction |= Rd;
12174 inst.instruction |= Rm << 3;
12176 else if (unified_syntax)
12178 if (inst.instruction <= 0xffff)
12179 inst.instruction = THUMB_OP32 (inst.instruction);
12180 inst.instruction |= Rd << 8;
12181 inst.instruction |= Rm;
12182 inst.instruction |= inst.operands[2].imm << 4;
12186 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12187 _("Thumb encoding does not support rotation"));
12188 constraint (1, BAD_HIREG);
12195 /* We have to do the following check manually as ARM_EXT_OS only applies
12197 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12199 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12200 /* This only applies to the v6m howver, not later architectures. */
12201 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12202 as_bad (_("SVC is not permitted on this architecture"));
12203 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12206 inst.reloc.type = BFD_RELOC_ARM_SWI;
12215 half = (inst.instruction & 0x10) != 0;
12216 set_it_insn_type_last ();
12217 constraint (inst.operands[0].immisreg,
12218 _("instruction requires register index"));
12220 Rn = inst.operands[0].reg;
12221 Rm = inst.operands[0].imm;
12223 constraint (Rn == REG_SP, BAD_SP);
12224 reject_bad_reg (Rm);
12226 constraint (!half && inst.operands[0].shifted,
12227 _("instruction does not allow shifted index"));
12228 inst.instruction |= (Rn << 16) | Rm;
12234 if (!inst.operands[0].present)
12235 inst.operands[0].imm = 0;
12237 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
12239 constraint (inst.size_req == 2,
12240 _("immediate value out of range"));
12241 inst.instruction = THUMB_OP32 (inst.instruction);
12242 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
12243 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
12247 inst.instruction = THUMB_OP16 (inst.instruction);
12248 inst.instruction |= inst.operands[0].imm;
12251 set_it_insn_type (NEUTRAL_IT_INSN);
12258 do_t_ssat_usat (0);
12266 Rd = inst.operands[0].reg;
12267 Rn = inst.operands[2].reg;
12269 reject_bad_reg (Rd);
12270 reject_bad_reg (Rn);
12272 inst.instruction |= Rd << 8;
12273 inst.instruction |= inst.operands[1].imm;
12274 inst.instruction |= Rn << 16;
12277 /* Neon instruction encoder helpers. */
12279 /* Encodings for the different types for various Neon opcodes. */
12281 /* An "invalid" code for the following tables. */
12284 struct neon_tab_entry
12287 unsigned float_or_poly;
12288 unsigned scalar_or_imm;
12291 /* Map overloaded Neon opcodes to their respective encodings. */
12292 #define NEON_ENC_TAB \
12293 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12294 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12295 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12296 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12297 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12298 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12299 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12300 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12301 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12302 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12303 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12304 /* Register variants of the following two instructions are encoded as
12305 vcge / vcgt with the operands reversed. */ \
12306 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12307 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12308 X(vfma, N_INV, 0x0000c10, N_INV), \
12309 X(vfms, N_INV, 0x0200c10, N_INV), \
12310 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12311 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12312 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12313 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12314 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12315 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12316 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12317 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12318 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12319 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12320 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12321 X(vshl, 0x0000400, N_INV, 0x0800510), \
12322 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12323 X(vand, 0x0000110, N_INV, 0x0800030), \
12324 X(vbic, 0x0100110, N_INV, 0x0800030), \
12325 X(veor, 0x1000110, N_INV, N_INV), \
12326 X(vorn, 0x0300110, N_INV, 0x0800010), \
12327 X(vorr, 0x0200110, N_INV, 0x0800010), \
12328 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12329 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12330 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12331 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12332 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12333 X(vst1, 0x0000000, 0x0800000, N_INV), \
12334 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12335 X(vst2, 0x0000100, 0x0800100, N_INV), \
12336 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12337 X(vst3, 0x0000200, 0x0800200, N_INV), \
12338 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12339 X(vst4, 0x0000300, 0x0800300, N_INV), \
12340 X(vmovn, 0x1b20200, N_INV, N_INV), \
12341 X(vtrn, 0x1b20080, N_INV, N_INV), \
12342 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12343 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12344 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12345 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12346 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12347 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12348 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12349 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12350 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12351 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12352 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12353 X(vseleq, 0xe000a00, N_INV, N_INV), \
12354 X(vselvs, 0xe100a00, N_INV, N_INV), \
12355 X(vselge, 0xe200a00, N_INV, N_INV), \
12356 X(vselgt, 0xe300a00, N_INV, N_INV), \
12357 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12358 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12359 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12360 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12361 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12362 X(aes, 0x3b00300, N_INV, N_INV), \
12363 X(sha3op, 0x2000c00, N_INV, N_INV), \
12364 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12365 X(sha2op, 0x3ba0380, N_INV, N_INV)
12369 #define X(OPC,I,F,S) N_MNEM_##OPC
12374 static const struct neon_tab_entry neon_enc_tab[] =
12376 #define X(OPC,I,F,S) { (I), (F), (S) }
12381 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12382 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12383 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12384 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12385 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12386 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12387 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12388 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12389 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12390 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12391 #define NEON_ENC_SINGLE_(X) \
12392 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12393 #define NEON_ENC_DOUBLE_(X) \
12394 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12395 #define NEON_ENC_FPV8_(X) \
12396 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12398 #define NEON_ENCODE(type, inst) \
12401 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12402 inst.is_neon = 1; \
12406 #define check_neon_suffixes \
12409 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12411 as_bad (_("invalid neon suffix for non neon instruction")); \
12417 /* Define shapes for instruction operands. The following mnemonic characters
12418 are used in this table:
12420 F - VFP S<n> register
12421 D - Neon D<n> register
12422 Q - Neon Q<n> register
12426 L - D<n> register list
12428 This table is used to generate various data:
12429 - enumerations of the form NS_DDR to be used as arguments to
12431 - a table classifying shapes into single, double, quad, mixed.
12432 - a table used to drive neon_select_shape. */
12434 #define NEON_SHAPE_DEF \
12435 X(3, (D, D, D), DOUBLE), \
12436 X(3, (Q, Q, Q), QUAD), \
12437 X(3, (D, D, I), DOUBLE), \
12438 X(3, (Q, Q, I), QUAD), \
12439 X(3, (D, D, S), DOUBLE), \
12440 X(3, (Q, Q, S), QUAD), \
12441 X(2, (D, D), DOUBLE), \
12442 X(2, (Q, Q), QUAD), \
12443 X(2, (D, S), DOUBLE), \
12444 X(2, (Q, S), QUAD), \
12445 X(2, (D, R), DOUBLE), \
12446 X(2, (Q, R), QUAD), \
12447 X(2, (D, I), DOUBLE), \
12448 X(2, (Q, I), QUAD), \
12449 X(3, (D, L, D), DOUBLE), \
12450 X(2, (D, Q), MIXED), \
12451 X(2, (Q, D), MIXED), \
12452 X(3, (D, Q, I), MIXED), \
12453 X(3, (Q, D, I), MIXED), \
12454 X(3, (Q, D, D), MIXED), \
12455 X(3, (D, Q, Q), MIXED), \
12456 X(3, (Q, Q, D), MIXED), \
12457 X(3, (Q, D, S), MIXED), \
12458 X(3, (D, Q, S), MIXED), \
12459 X(4, (D, D, D, I), DOUBLE), \
12460 X(4, (Q, Q, Q, I), QUAD), \
12461 X(2, (F, F), SINGLE), \
12462 X(3, (F, F, F), SINGLE), \
12463 X(2, (F, I), SINGLE), \
12464 X(2, (F, D), MIXED), \
12465 X(2, (D, F), MIXED), \
12466 X(3, (F, F, I), MIXED), \
12467 X(4, (R, R, F, F), SINGLE), \
12468 X(4, (F, F, R, R), SINGLE), \
12469 X(3, (D, R, R), DOUBLE), \
12470 X(3, (R, R, D), DOUBLE), \
12471 X(2, (S, R), SINGLE), \
12472 X(2, (R, S), SINGLE), \
12473 X(2, (F, R), SINGLE), \
12474 X(2, (R, F), SINGLE)
12476 #define S2(A,B) NS_##A##B
12477 #define S3(A,B,C) NS_##A##B##C
12478 #define S4(A,B,C,D) NS_##A##B##C##D
12480 #define X(N, L, C) S##N L
12493 enum neon_shape_class
12501 #define X(N, L, C) SC_##C
12503 static enum neon_shape_class neon_shape_class[] =
12521 /* Register widths of above. */
12522 static unsigned neon_shape_el_size[] =
12533 struct neon_shape_info
12536 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12539 #define S2(A,B) { SE_##A, SE_##B }
12540 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12541 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12543 #define X(N, L, C) { N, S##N L }
12545 static struct neon_shape_info neon_shape_tab[] =
12555 /* Bit masks used in type checking given instructions.
12556 'N_EQK' means the type must be the same as (or based on in some way) the key
12557 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12558 set, various other bits can be set as well in order to modify the meaning of
12559 the type constraint. */
12561 enum neon_type_mask
12585 N_KEY = 0x1000000, /* Key element (main type specifier). */
12586 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12587 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12588 N_UNT = 0x8000000, /* Must be explicitly untyped. */
12589 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12590 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12591 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12592 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12593 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12594 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12595 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12597 N_MAX_NONSPECIAL = N_P64
12600 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12602 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12603 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12604 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12605 #define N_SUF_32 (N_SU_32 | N_F32)
12606 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12607 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12609 /* Pass this as the first type argument to neon_check_type to ignore types
12611 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12613 /* Select a "shape" for the current instruction (describing register types or
12614 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12615 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12616 function of operand parsing, so this function doesn't need to be called.
12617 Shapes should be listed in order of decreasing length. */
12619 static enum neon_shape
12620 neon_select_shape (enum neon_shape shape, ...)
12623 enum neon_shape first_shape = shape;
12625 /* Fix missing optional operands. FIXME: we don't know at this point how
12626 many arguments we should have, so this makes the assumption that we have
12627 > 1. This is true of all current Neon opcodes, I think, but may not be
12628 true in the future. */
12629 if (!inst.operands[1].present)
12630 inst.operands[1] = inst.operands[0];
12632 va_start (ap, shape);
12634 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12639 for (j = 0; j < neon_shape_tab[shape].els; j++)
12641 if (!inst.operands[j].present)
12647 switch (neon_shape_tab[shape].el[j])
12650 if (!(inst.operands[j].isreg
12651 && inst.operands[j].isvec
12652 && inst.operands[j].issingle
12653 && !inst.operands[j].isquad))
12658 if (!(inst.operands[j].isreg
12659 && inst.operands[j].isvec
12660 && !inst.operands[j].isquad
12661 && !inst.operands[j].issingle))
12666 if (!(inst.operands[j].isreg
12667 && !inst.operands[j].isvec))
12672 if (!(inst.operands[j].isreg
12673 && inst.operands[j].isvec
12674 && inst.operands[j].isquad
12675 && !inst.operands[j].issingle))
12680 if (!(!inst.operands[j].isreg
12681 && !inst.operands[j].isscalar))
12686 if (!(!inst.operands[j].isreg
12687 && inst.operands[j].isscalar))
12697 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12698 /* We've matched all the entries in the shape table, and we don't
12699 have any left over operands which have not been matched. */
12705 if (shape == NS_NULL && first_shape != NS_NULL)
12706 first_error (_("invalid instruction shape"));
12711 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12712 means the Q bit should be set). */
12715 neon_quad (enum neon_shape shape)
12717 return neon_shape_class[shape] == SC_QUAD;
12721 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12724 /* Allow modification to be made to types which are constrained to be
12725 based on the key element, based on bits set alongside N_EQK. */
12726 if ((typebits & N_EQK) != 0)
12728 if ((typebits & N_HLF) != 0)
12730 else if ((typebits & N_DBL) != 0)
12732 if ((typebits & N_SGN) != 0)
12733 *g_type = NT_signed;
12734 else if ((typebits & N_UNS) != 0)
12735 *g_type = NT_unsigned;
12736 else if ((typebits & N_INT) != 0)
12737 *g_type = NT_integer;
12738 else if ((typebits & N_FLT) != 0)
12739 *g_type = NT_float;
12740 else if ((typebits & N_SIZ) != 0)
12741 *g_type = NT_untyped;
12745 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12746 operand type, i.e. the single type specified in a Neon instruction when it
12747 is the only one given. */
12749 static struct neon_type_el
12750 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12752 struct neon_type_el dest = *key;
12754 gas_assert ((thisarg & N_EQK) != 0);
12756 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12761 /* Convert Neon type and size into compact bitmask representation. */
12763 static enum neon_type_mask
12764 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12771 case 8: return N_8;
12772 case 16: return N_16;
12773 case 32: return N_32;
12774 case 64: return N_64;
12782 case 8: return N_I8;
12783 case 16: return N_I16;
12784 case 32: return N_I32;
12785 case 64: return N_I64;
12793 case 16: return N_F16;
12794 case 32: return N_F32;
12795 case 64: return N_F64;
12803 case 8: return N_P8;
12804 case 16: return N_P16;
12805 case 64: return N_P64;
12813 case 8: return N_S8;
12814 case 16: return N_S16;
12815 case 32: return N_S32;
12816 case 64: return N_S64;
12824 case 8: return N_U8;
12825 case 16: return N_U16;
12826 case 32: return N_U32;
12827 case 64: return N_U64;
12838 /* Convert compact Neon bitmask type representation to a type and size. Only
12839 handles the case where a single bit is set in the mask. */
12842 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12843 enum neon_type_mask mask)
12845 if ((mask & N_EQK) != 0)
12848 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12850 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
12852 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12854 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
12859 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12861 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12862 *type = NT_unsigned;
12863 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12864 *type = NT_integer;
12865 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12866 *type = NT_untyped;
12867 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
12869 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
12877 /* Modify a bitmask of allowed types. This is only needed for type
12881 modify_types_allowed (unsigned allowed, unsigned mods)
12884 enum neon_el_type type;
12890 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12892 if (el_type_of_type_chk (&type, &size,
12893 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12895 neon_modify_type_size (mods, &type, &size);
12896 destmask |= type_chk_of_el_type (type, size);
12903 /* Check type and return type classification.
12904 The manual states (paraphrase): If one datatype is given, it indicates the
12906 - the second operand, if there is one
12907 - the operand, if there is no second operand
12908 - the result, if there are no operands.
12909 This isn't quite good enough though, so we use a concept of a "key" datatype
12910 which is set on a per-instruction basis, which is the one which matters when
12911 only one data type is written.
12912 Note: this function has side-effects (e.g. filling in missing operands). All
12913 Neon instructions should call it before performing bit encoding. */
12915 static struct neon_type_el
12916 neon_check_type (unsigned els, enum neon_shape ns, ...)
12919 unsigned i, pass, key_el = 0;
12920 unsigned types[NEON_MAX_TYPE_ELS];
12921 enum neon_el_type k_type = NT_invtype;
12922 unsigned k_size = -1u;
12923 struct neon_type_el badtype = {NT_invtype, -1};
12924 unsigned key_allowed = 0;
12926 /* Optional registers in Neon instructions are always (not) in operand 1.
12927 Fill in the missing operand here, if it was omitted. */
12928 if (els > 1 && !inst.operands[1].present)
12929 inst.operands[1] = inst.operands[0];
12931 /* Suck up all the varargs. */
12933 for (i = 0; i < els; i++)
12935 unsigned thisarg = va_arg (ap, unsigned);
12936 if (thisarg == N_IGNORE_TYPE)
12941 types[i] = thisarg;
12942 if ((thisarg & N_KEY) != 0)
12947 if (inst.vectype.elems > 0)
12948 for (i = 0; i < els; i++)
12949 if (inst.operands[i].vectype.type != NT_invtype)
12951 first_error (_("types specified in both the mnemonic and operands"));
12955 /* Duplicate inst.vectype elements here as necessary.
12956 FIXME: No idea if this is exactly the same as the ARM assembler,
12957 particularly when an insn takes one register and one non-register
12959 if (inst.vectype.elems == 1 && els > 1)
12962 inst.vectype.elems = els;
12963 inst.vectype.el[key_el] = inst.vectype.el[0];
12964 for (j = 0; j < els; j++)
12966 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12969 else if (inst.vectype.elems == 0 && els > 0)
12972 /* No types were given after the mnemonic, so look for types specified
12973 after each operand. We allow some flexibility here; as long as the
12974 "key" operand has a type, we can infer the others. */
12975 for (j = 0; j < els; j++)
12976 if (inst.operands[j].vectype.type != NT_invtype)
12977 inst.vectype.el[j] = inst.operands[j].vectype;
12979 if (inst.operands[key_el].vectype.type != NT_invtype)
12981 for (j = 0; j < els; j++)
12982 if (inst.operands[j].vectype.type == NT_invtype)
12983 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12988 first_error (_("operand types can't be inferred"));
12992 else if (inst.vectype.elems != els)
12994 first_error (_("type specifier has the wrong number of parts"));
12998 for (pass = 0; pass < 2; pass++)
13000 for (i = 0; i < els; i++)
13002 unsigned thisarg = types[i];
13003 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
13004 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
13005 enum neon_el_type g_type = inst.vectype.el[i].type;
13006 unsigned g_size = inst.vectype.el[i].size;
13008 /* Decay more-specific signed & unsigned types to sign-insensitive
13009 integer types if sign-specific variants are unavailable. */
13010 if ((g_type == NT_signed || g_type == NT_unsigned)
13011 && (types_allowed & N_SU_ALL) == 0)
13012 g_type = NT_integer;
13014 /* If only untyped args are allowed, decay any more specific types to
13015 them. Some instructions only care about signs for some element
13016 sizes, so handle that properly. */
13017 if (((types_allowed & N_UNT) == 0)
13018 && ((g_size == 8 && (types_allowed & N_8) != 0)
13019 || (g_size == 16 && (types_allowed & N_16) != 0)
13020 || (g_size == 32 && (types_allowed & N_32) != 0)
13021 || (g_size == 64 && (types_allowed & N_64) != 0)))
13022 g_type = NT_untyped;
13026 if ((thisarg & N_KEY) != 0)
13030 key_allowed = thisarg & ~N_KEY;
13035 if ((thisarg & N_VFP) != 0)
13037 enum neon_shape_el regshape;
13038 unsigned regwidth, match;
13040 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13043 first_error (_("invalid instruction shape"));
13046 regshape = neon_shape_tab[ns].el[i];
13047 regwidth = neon_shape_el_size[regshape];
13049 /* In VFP mode, operands must match register widths. If we
13050 have a key operand, use its width, else use the width of
13051 the current operand. */
13057 if (regwidth != match)
13059 first_error (_("operand size must match register width"));
13064 if ((thisarg & N_EQK) == 0)
13066 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13068 if ((given_type & types_allowed) == 0)
13070 first_error (_("bad type in Neon instruction"));
13076 enum neon_el_type mod_k_type = k_type;
13077 unsigned mod_k_size = k_size;
13078 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13079 if (g_type != mod_k_type || g_size != mod_k_size)
13081 first_error (_("inconsistent types in Neon instruction"));
13089 return inst.vectype.el[key_el];
13092 /* Neon-style VFP instruction forwarding. */
13094 /* Thumb VFP instructions have 0xE in the condition field. */
13097 do_vfp_cond_or_thumb (void)
13102 inst.instruction |= 0xe0000000;
13104 inst.instruction |= inst.cond << 28;
13107 /* Look up and encode a simple mnemonic, for use as a helper function for the
13108 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13109 etc. It is assumed that operand parsing has already been done, and that the
13110 operands are in the form expected by the given opcode (this isn't necessarily
13111 the same as the form in which they were parsed, hence some massaging must
13112 take place before this function is called).
13113 Checks current arch version against that in the looked-up opcode. */
13116 do_vfp_nsyn_opcode (const char *opname)
13118 const struct asm_opcode *opcode;
13120 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13125 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13126 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13133 inst.instruction = opcode->tvalue;
13134 opcode->tencode ();
13138 inst.instruction = (inst.cond << 28) | opcode->avalue;
13139 opcode->aencode ();
13144 do_vfp_nsyn_add_sub (enum neon_shape rs)
13146 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13151 do_vfp_nsyn_opcode ("fadds");
13153 do_vfp_nsyn_opcode ("fsubs");
13158 do_vfp_nsyn_opcode ("faddd");
13160 do_vfp_nsyn_opcode ("fsubd");
13164 /* Check operand types to see if this is a VFP instruction, and if so call
13168 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13170 enum neon_shape rs;
13171 struct neon_type_el et;
13176 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13177 et = neon_check_type (2, rs,
13178 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13182 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13183 et = neon_check_type (3, rs,
13184 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13191 if (et.type != NT_invtype)
13202 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13204 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13209 do_vfp_nsyn_opcode ("fmacs");
13211 do_vfp_nsyn_opcode ("fnmacs");
13216 do_vfp_nsyn_opcode ("fmacd");
13218 do_vfp_nsyn_opcode ("fnmacd");
13223 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13225 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13230 do_vfp_nsyn_opcode ("ffmas");
13232 do_vfp_nsyn_opcode ("ffnmas");
13237 do_vfp_nsyn_opcode ("ffmad");
13239 do_vfp_nsyn_opcode ("ffnmad");
13244 do_vfp_nsyn_mul (enum neon_shape rs)
13247 do_vfp_nsyn_opcode ("fmuls");
13249 do_vfp_nsyn_opcode ("fmuld");
13253 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13255 int is_neg = (inst.instruction & 0x80) != 0;
13256 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13261 do_vfp_nsyn_opcode ("fnegs");
13263 do_vfp_nsyn_opcode ("fabss");
13268 do_vfp_nsyn_opcode ("fnegd");
13270 do_vfp_nsyn_opcode ("fabsd");
13274 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13275 insns belong to Neon, and are handled elsewhere. */
13278 do_vfp_nsyn_ldm_stm (int is_dbmode)
13280 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13284 do_vfp_nsyn_opcode ("fldmdbs");
13286 do_vfp_nsyn_opcode ("fldmias");
13291 do_vfp_nsyn_opcode ("fstmdbs");
13293 do_vfp_nsyn_opcode ("fstmias");
13298 do_vfp_nsyn_sqrt (void)
13300 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13301 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13304 do_vfp_nsyn_opcode ("fsqrts");
13306 do_vfp_nsyn_opcode ("fsqrtd");
13310 do_vfp_nsyn_div (void)
13312 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13313 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13314 N_F32 | N_F64 | N_KEY | N_VFP);
13317 do_vfp_nsyn_opcode ("fdivs");
13319 do_vfp_nsyn_opcode ("fdivd");
13323 do_vfp_nsyn_nmul (void)
13325 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13326 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13327 N_F32 | N_F64 | N_KEY | N_VFP);
13331 NEON_ENCODE (SINGLE, inst);
13332 do_vfp_sp_dyadic ();
13336 NEON_ENCODE (DOUBLE, inst);
13337 do_vfp_dp_rd_rn_rm ();
13339 do_vfp_cond_or_thumb ();
13343 do_vfp_nsyn_cmp (void)
13345 if (inst.operands[1].isreg)
13347 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13348 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13352 NEON_ENCODE (SINGLE, inst);
13353 do_vfp_sp_monadic ();
13357 NEON_ENCODE (DOUBLE, inst);
13358 do_vfp_dp_rd_rm ();
13363 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13364 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13366 switch (inst.instruction & 0x0fffffff)
13369 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13372 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13380 NEON_ENCODE (SINGLE, inst);
13381 do_vfp_sp_compare_z ();
13385 NEON_ENCODE (DOUBLE, inst);
13389 do_vfp_cond_or_thumb ();
13393 nsyn_insert_sp (void)
13395 inst.operands[1] = inst.operands[0];
13396 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13397 inst.operands[0].reg = REG_SP;
13398 inst.operands[0].isreg = 1;
13399 inst.operands[0].writeback = 1;
13400 inst.operands[0].present = 1;
13404 do_vfp_nsyn_push (void)
13407 if (inst.operands[1].issingle)
13408 do_vfp_nsyn_opcode ("fstmdbs");
13410 do_vfp_nsyn_opcode ("fstmdbd");
13414 do_vfp_nsyn_pop (void)
13417 if (inst.operands[1].issingle)
13418 do_vfp_nsyn_opcode ("fldmias");
13420 do_vfp_nsyn_opcode ("fldmiad");
13423 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13424 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13427 neon_dp_fixup (struct arm_it* insn)
13429 unsigned int i = insn->instruction;
13434 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13445 insn->instruction = i;
13448 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13452 neon_logbits (unsigned x)
13454 return ffs (x) - 4;
13457 #define LOW4(R) ((R) & 0xf)
13458 #define HI1(R) (((R) >> 4) & 1)
13460 /* Encode insns with bit pattern:
13462 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13463 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13465 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13466 different meaning for some instruction. */
13469 neon_three_same (int isquad, int ubit, int size)
13471 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13472 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13473 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13474 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13475 inst.instruction |= LOW4 (inst.operands[2].reg);
13476 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13477 inst.instruction |= (isquad != 0) << 6;
13478 inst.instruction |= (ubit != 0) << 24;
13480 inst.instruction |= neon_logbits (size) << 20;
13482 neon_dp_fixup (&inst);
13485 /* Encode instructions of the form:
13487 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13488 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13490 Don't write size if SIZE == -1. */
13493 neon_two_same (int qbit, int ubit, int size)
13495 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13496 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13497 inst.instruction |= LOW4 (inst.operands[1].reg);
13498 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13499 inst.instruction |= (qbit != 0) << 6;
13500 inst.instruction |= (ubit != 0) << 24;
13503 inst.instruction |= neon_logbits (size) << 18;
13505 neon_dp_fixup (&inst);
13508 /* Neon instruction encoders, in approximate order of appearance. */
13511 do_neon_dyadic_i_su (void)
13513 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13514 struct neon_type_el et = neon_check_type (3, rs,
13515 N_EQK, N_EQK, N_SU_32 | N_KEY);
13516 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13520 do_neon_dyadic_i64_su (void)
13522 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13523 struct neon_type_el et = neon_check_type (3, rs,
13524 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13525 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13529 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13532 unsigned size = et.size >> 3;
13533 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13534 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13535 inst.instruction |= LOW4 (inst.operands[1].reg);
13536 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13537 inst.instruction |= (isquad != 0) << 6;
13538 inst.instruction |= immbits << 16;
13539 inst.instruction |= (size >> 3) << 7;
13540 inst.instruction |= (size & 0x7) << 19;
13542 inst.instruction |= (uval != 0) << 24;
13544 neon_dp_fixup (&inst);
13548 do_neon_shl_imm (void)
13550 if (!inst.operands[2].isreg)
13552 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13553 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13554 NEON_ENCODE (IMMED, inst);
13555 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13559 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13560 struct neon_type_el et = neon_check_type (3, rs,
13561 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13564 /* VSHL/VQSHL 3-register variants have syntax such as:
13566 whereas other 3-register operations encoded by neon_three_same have
13569 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13571 tmp = inst.operands[2].reg;
13572 inst.operands[2].reg = inst.operands[1].reg;
13573 inst.operands[1].reg = tmp;
13574 NEON_ENCODE (INTEGER, inst);
13575 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13580 do_neon_qshl_imm (void)
13582 if (!inst.operands[2].isreg)
13584 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13585 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13587 NEON_ENCODE (IMMED, inst);
13588 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13589 inst.operands[2].imm);
13593 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13594 struct neon_type_el et = neon_check_type (3, rs,
13595 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13598 /* See note in do_neon_shl_imm. */
13599 tmp = inst.operands[2].reg;
13600 inst.operands[2].reg = inst.operands[1].reg;
13601 inst.operands[1].reg = tmp;
13602 NEON_ENCODE (INTEGER, inst);
13603 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13608 do_neon_rshl (void)
13610 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13611 struct neon_type_el et = neon_check_type (3, rs,
13612 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13615 tmp = inst.operands[2].reg;
13616 inst.operands[2].reg = inst.operands[1].reg;
13617 inst.operands[1].reg = tmp;
13618 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13622 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13624 /* Handle .I8 pseudo-instructions. */
13627 /* Unfortunately, this will make everything apart from zero out-of-range.
13628 FIXME is this the intended semantics? There doesn't seem much point in
13629 accepting .I8 if so. */
13630 immediate |= immediate << 8;
13636 if (immediate == (immediate & 0x000000ff))
13638 *immbits = immediate;
13641 else if (immediate == (immediate & 0x0000ff00))
13643 *immbits = immediate >> 8;
13646 else if (immediate == (immediate & 0x00ff0000))
13648 *immbits = immediate >> 16;
13651 else if (immediate == (immediate & 0xff000000))
13653 *immbits = immediate >> 24;
13656 if ((immediate & 0xffff) != (immediate >> 16))
13657 goto bad_immediate;
13658 immediate &= 0xffff;
13661 if (immediate == (immediate & 0x000000ff))
13663 *immbits = immediate;
13666 else if (immediate == (immediate & 0x0000ff00))
13668 *immbits = immediate >> 8;
13673 first_error (_("immediate value out of range"));
13677 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13681 neon_bits_same_in_bytes (unsigned imm)
13683 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13684 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13685 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13686 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13689 /* For immediate of above form, return 0bABCD. */
13692 neon_squash_bits (unsigned imm)
13694 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13695 | ((imm & 0x01000000) >> 21);
13698 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13701 neon_qfloat_bits (unsigned imm)
13703 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13706 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13707 the instruction. *OP is passed as the initial value of the op field, and
13708 may be set to a different value depending on the constant (i.e.
13709 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13710 MVN). If the immediate looks like a repeated pattern then also
13711 try smaller element sizes. */
13714 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13715 unsigned *immbits, int *op, int size,
13716 enum neon_el_type type)
13718 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13720 if (type == NT_float && !float_p)
13723 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13725 if (size != 32 || *op == 1)
13727 *immbits = neon_qfloat_bits (immlo);
13733 if (neon_bits_same_in_bytes (immhi)
13734 && neon_bits_same_in_bytes (immlo))
13738 *immbits = (neon_squash_bits (immhi) << 4)
13739 | neon_squash_bits (immlo);
13744 if (immhi != immlo)
13750 if (immlo == (immlo & 0x000000ff))
13755 else if (immlo == (immlo & 0x0000ff00))
13757 *immbits = immlo >> 8;
13760 else if (immlo == (immlo & 0x00ff0000))
13762 *immbits = immlo >> 16;
13765 else if (immlo == (immlo & 0xff000000))
13767 *immbits = immlo >> 24;
13770 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13772 *immbits = (immlo >> 8) & 0xff;
13775 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13777 *immbits = (immlo >> 16) & 0xff;
13781 if ((immlo & 0xffff) != (immlo >> 16))
13788 if (immlo == (immlo & 0x000000ff))
13793 else if (immlo == (immlo & 0x0000ff00))
13795 *immbits = immlo >> 8;
13799 if ((immlo & 0xff) != (immlo >> 8))
13804 if (immlo == (immlo & 0x000000ff))
13806 /* Don't allow MVN with 8-bit immediate. */
13816 /* Write immediate bits [7:0] to the following locations:
13818 |28/24|23 19|18 16|15 4|3 0|
13819 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13821 This function is used by VMOV/VMVN/VORR/VBIC. */
13824 neon_write_immbits (unsigned immbits)
13826 inst.instruction |= immbits & 0xf;
13827 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13828 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13831 /* Invert low-order SIZE bits of XHI:XLO. */
13834 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13836 unsigned immlo = xlo ? *xlo : 0;
13837 unsigned immhi = xhi ? *xhi : 0;
13842 immlo = (~immlo) & 0xff;
13846 immlo = (~immlo) & 0xffff;
13850 immhi = (~immhi) & 0xffffffff;
13851 /* fall through. */
13854 immlo = (~immlo) & 0xffffffff;
13869 do_neon_logic (void)
13871 if (inst.operands[2].present && inst.operands[2].isreg)
13873 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13874 neon_check_type (3, rs, N_IGNORE_TYPE);
13875 /* U bit and size field were set as part of the bitmask. */
13876 NEON_ENCODE (INTEGER, inst);
13877 neon_three_same (neon_quad (rs), 0, -1);
13881 const int three_ops_form = (inst.operands[2].present
13882 && !inst.operands[2].isreg);
13883 const int immoperand = (three_ops_form ? 2 : 1);
13884 enum neon_shape rs = (three_ops_form
13885 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13886 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13887 struct neon_type_el et = neon_check_type (2, rs,
13888 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13889 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13893 if (et.type == NT_invtype)
13896 if (three_ops_form)
13897 constraint (inst.operands[0].reg != inst.operands[1].reg,
13898 _("first and second operands shall be the same register"));
13900 NEON_ENCODE (IMMED, inst);
13902 immbits = inst.operands[immoperand].imm;
13905 /* .i64 is a pseudo-op, so the immediate must be a repeating
13907 if (immbits != (inst.operands[immoperand].regisimm ?
13908 inst.operands[immoperand].reg : 0))
13910 /* Set immbits to an invalid constant. */
13911 immbits = 0xdeadbeef;
13918 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13922 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13926 /* Pseudo-instruction for VBIC. */
13927 neon_invert_size (&immbits, 0, et.size);
13928 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13932 /* Pseudo-instruction for VORR. */
13933 neon_invert_size (&immbits, 0, et.size);
13934 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13944 inst.instruction |= neon_quad (rs) << 6;
13945 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13946 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13947 inst.instruction |= cmode << 8;
13948 neon_write_immbits (immbits);
13950 neon_dp_fixup (&inst);
13955 do_neon_bitfield (void)
13957 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13958 neon_check_type (3, rs, N_IGNORE_TYPE);
13959 neon_three_same (neon_quad (rs), 0, -1);
13963 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13966 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13967 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13969 if (et.type == NT_float)
13971 NEON_ENCODE (FLOAT, inst);
13972 neon_three_same (neon_quad (rs), 0, -1);
13976 NEON_ENCODE (INTEGER, inst);
13977 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13982 do_neon_dyadic_if_su (void)
13984 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13988 do_neon_dyadic_if_su_d (void)
13990 /* This version only allow D registers, but that constraint is enforced during
13991 operand parsing so we don't need to do anything extra here. */
13992 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13996 do_neon_dyadic_if_i_d (void)
13998 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13999 affected if we specify unsigned args. */
14000 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14003 enum vfp_or_neon_is_neon_bits
14006 NEON_CHECK_ARCH = 2,
14007 NEON_CHECK_ARCH8 = 4
14010 /* Call this function if an instruction which may have belonged to the VFP or
14011 Neon instruction sets, but turned out to be a Neon instruction (due to the
14012 operand types involved, etc.). We have to check and/or fix-up a couple of
14015 - Make sure the user hasn't attempted to make a Neon instruction
14017 - Alter the value in the condition code field if necessary.
14018 - Make sure that the arch supports Neon instructions.
14020 Which of these operations take place depends on bits from enum
14021 vfp_or_neon_is_neon_bits.
14023 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14024 current instruction's condition is COND_ALWAYS, the condition field is
14025 changed to inst.uncond_value. This is necessary because instructions shared
14026 between VFP and Neon may be conditional for the VFP variants only, and the
14027 unconditional Neon version must have, e.g., 0xF in the condition field. */
14030 vfp_or_neon_is_neon (unsigned check)
14032 /* Conditions are always legal in Thumb mode (IT blocks). */
14033 if (!thumb_mode && (check & NEON_CHECK_CC))
14035 if (inst.cond != COND_ALWAYS)
14037 first_error (_(BAD_COND));
14040 if (inst.uncond_value != -1)
14041 inst.instruction |= inst.uncond_value << 28;
14044 if ((check & NEON_CHECK_ARCH)
14045 && !mark_feature_used (&fpu_neon_ext_v1))
14047 first_error (_(BAD_FPU));
14051 if ((check & NEON_CHECK_ARCH8)
14052 && !mark_feature_used (&fpu_neon_ext_armv8))
14054 first_error (_(BAD_FPU));
14062 do_neon_addsub_if_i (void)
14064 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14067 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14070 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14071 affected if we specify unsigned args. */
14072 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14075 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14077 V<op> A,B (A is operand 0, B is operand 2)
14082 so handle that case specially. */
14085 neon_exchange_operands (void)
14087 void *scratch = alloca (sizeof (inst.operands[0]));
14088 if (inst.operands[1].present)
14090 /* Swap operands[1] and operands[2]. */
14091 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14092 inst.operands[1] = inst.operands[2];
14093 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14097 inst.operands[1] = inst.operands[2];
14098 inst.operands[2] = inst.operands[0];
14103 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14105 if (inst.operands[2].isreg)
14108 neon_exchange_operands ();
14109 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14113 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14114 struct neon_type_el et = neon_check_type (2, rs,
14115 N_EQK | N_SIZ, immtypes | N_KEY);
14117 NEON_ENCODE (IMMED, inst);
14118 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14119 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14120 inst.instruction |= LOW4 (inst.operands[1].reg);
14121 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14122 inst.instruction |= neon_quad (rs) << 6;
14123 inst.instruction |= (et.type == NT_float) << 10;
14124 inst.instruction |= neon_logbits (et.size) << 18;
14126 neon_dp_fixup (&inst);
14133 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14137 do_neon_cmp_inv (void)
14139 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14145 neon_compare (N_IF_32, N_IF_32, FALSE);
14148 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14149 scalars, which are encoded in 5 bits, M : Rm.
14150 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14151 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14155 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14157 unsigned regno = NEON_SCALAR_REG (scalar);
14158 unsigned elno = NEON_SCALAR_INDEX (scalar);
14163 if (regno > 7 || elno > 3)
14165 return regno | (elno << 3);
14168 if (regno > 15 || elno > 1)
14170 return regno | (elno << 4);
14174 first_error (_("scalar out of range for multiply instruction"));
14180 /* Encode multiply / multiply-accumulate scalar instructions. */
14183 neon_mul_mac (struct neon_type_el et, int ubit)
14187 /* Give a more helpful error message if we have an invalid type. */
14188 if (et.type == NT_invtype)
14191 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14192 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14193 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14194 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14195 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14196 inst.instruction |= LOW4 (scalar);
14197 inst.instruction |= HI1 (scalar) << 5;
14198 inst.instruction |= (et.type == NT_float) << 8;
14199 inst.instruction |= neon_logbits (et.size) << 20;
14200 inst.instruction |= (ubit != 0) << 24;
14202 neon_dp_fixup (&inst);
14206 do_neon_mac_maybe_scalar (void)
14208 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14211 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14214 if (inst.operands[2].isscalar)
14216 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14217 struct neon_type_el et = neon_check_type (3, rs,
14218 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14219 NEON_ENCODE (SCALAR, inst);
14220 neon_mul_mac (et, neon_quad (rs));
14224 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14225 affected if we specify unsigned args. */
14226 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14231 do_neon_fmac (void)
14233 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14236 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14239 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14245 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14246 struct neon_type_el et = neon_check_type (3, rs,
14247 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14248 neon_three_same (neon_quad (rs), 0, et.size);
14251 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14252 same types as the MAC equivalents. The polynomial type for this instruction
14253 is encoded the same as the integer type. */
14258 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14261 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14264 if (inst.operands[2].isscalar)
14265 do_neon_mac_maybe_scalar ();
14267 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14271 do_neon_qdmulh (void)
14273 if (inst.operands[2].isscalar)
14275 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14276 struct neon_type_el et = neon_check_type (3, rs,
14277 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14278 NEON_ENCODE (SCALAR, inst);
14279 neon_mul_mac (et, neon_quad (rs));
14283 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14284 struct neon_type_el et = neon_check_type (3, rs,
14285 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14286 NEON_ENCODE (INTEGER, inst);
14287 /* The U bit (rounding) comes from bit mask. */
14288 neon_three_same (neon_quad (rs), 0, et.size);
14293 do_neon_fcmp_absolute (void)
14295 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14296 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14297 /* Size field comes from bit mask. */
14298 neon_three_same (neon_quad (rs), 1, -1);
14302 do_neon_fcmp_absolute_inv (void)
14304 neon_exchange_operands ();
14305 do_neon_fcmp_absolute ();
14309 do_neon_step (void)
14311 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14312 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14313 neon_three_same (neon_quad (rs), 0, -1);
14317 do_neon_abs_neg (void)
14319 enum neon_shape rs;
14320 struct neon_type_el et;
14322 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14325 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14328 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14329 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14331 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14332 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14333 inst.instruction |= LOW4 (inst.operands[1].reg);
14334 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14335 inst.instruction |= neon_quad (rs) << 6;
14336 inst.instruction |= (et.type == NT_float) << 10;
14337 inst.instruction |= neon_logbits (et.size) << 18;
14339 neon_dp_fixup (&inst);
14345 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14346 struct neon_type_el et = neon_check_type (2, rs,
14347 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14348 int imm = inst.operands[2].imm;
14349 constraint (imm < 0 || (unsigned)imm >= et.size,
14350 _("immediate out of range for insert"));
14351 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14357 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14358 struct neon_type_el et = neon_check_type (2, rs,
14359 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14360 int imm = inst.operands[2].imm;
14361 constraint (imm < 1 || (unsigned)imm > et.size,
14362 _("immediate out of range for insert"));
14363 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14367 do_neon_qshlu_imm (void)
14369 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14370 struct neon_type_el et = neon_check_type (2, rs,
14371 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14372 int imm = inst.operands[2].imm;
14373 constraint (imm < 0 || (unsigned)imm >= et.size,
14374 _("immediate out of range for shift"));
14375 /* Only encodes the 'U present' variant of the instruction.
14376 In this case, signed types have OP (bit 8) set to 0.
14377 Unsigned types have OP set to 1. */
14378 inst.instruction |= (et.type == NT_unsigned) << 8;
14379 /* The rest of the bits are the same as other immediate shifts. */
14380 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14384 do_neon_qmovn (void)
14386 struct neon_type_el et = neon_check_type (2, NS_DQ,
14387 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14388 /* Saturating move where operands can be signed or unsigned, and the
14389 destination has the same signedness. */
14390 NEON_ENCODE (INTEGER, inst);
14391 if (et.type == NT_unsigned)
14392 inst.instruction |= 0xc0;
14394 inst.instruction |= 0x80;
14395 neon_two_same (0, 1, et.size / 2);
14399 do_neon_qmovun (void)
14401 struct neon_type_el et = neon_check_type (2, NS_DQ,
14402 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14403 /* Saturating move with unsigned results. Operands must be signed. */
14404 NEON_ENCODE (INTEGER, inst);
14405 neon_two_same (0, 1, et.size / 2);
14409 do_neon_rshift_sat_narrow (void)
14411 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14412 or unsigned. If operands are unsigned, results must also be unsigned. */
14413 struct neon_type_el et = neon_check_type (2, NS_DQI,
14414 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14415 int imm = inst.operands[2].imm;
14416 /* This gets the bounds check, size encoding and immediate bits calculation
14420 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14421 VQMOVN.I<size> <Dd>, <Qm>. */
14424 inst.operands[2].present = 0;
14425 inst.instruction = N_MNEM_vqmovn;
14430 constraint (imm < 1 || (unsigned)imm > et.size,
14431 _("immediate out of range"));
14432 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14436 do_neon_rshift_sat_narrow_u (void)
14438 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14439 or unsigned. If operands are unsigned, results must also be unsigned. */
14440 struct neon_type_el et = neon_check_type (2, NS_DQI,
14441 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14442 int imm = inst.operands[2].imm;
14443 /* This gets the bounds check, size encoding and immediate bits calculation
14447 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14448 VQMOVUN.I<size> <Dd>, <Qm>. */
14451 inst.operands[2].present = 0;
14452 inst.instruction = N_MNEM_vqmovun;
14457 constraint (imm < 1 || (unsigned)imm > et.size,
14458 _("immediate out of range"));
14459 /* FIXME: The manual is kind of unclear about what value U should have in
14460 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14462 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14466 do_neon_movn (void)
14468 struct neon_type_el et = neon_check_type (2, NS_DQ,
14469 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14470 NEON_ENCODE (INTEGER, inst);
14471 neon_two_same (0, 1, et.size / 2);
14475 do_neon_rshift_narrow (void)
14477 struct neon_type_el et = neon_check_type (2, NS_DQI,
14478 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14479 int imm = inst.operands[2].imm;
14480 /* This gets the bounds check, size encoding and immediate bits calculation
14484 /* If immediate is zero then we are a pseudo-instruction for
14485 VMOVN.I<size> <Dd>, <Qm> */
14488 inst.operands[2].present = 0;
14489 inst.instruction = N_MNEM_vmovn;
14494 constraint (imm < 1 || (unsigned)imm > et.size,
14495 _("immediate out of range for narrowing operation"));
14496 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14500 do_neon_shll (void)
14502 /* FIXME: Type checking when lengthening. */
14503 struct neon_type_el et = neon_check_type (2, NS_QDI,
14504 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14505 unsigned imm = inst.operands[2].imm;
14507 if (imm == et.size)
14509 /* Maximum shift variant. */
14510 NEON_ENCODE (INTEGER, inst);
14511 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14512 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14513 inst.instruction |= LOW4 (inst.operands[1].reg);
14514 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14515 inst.instruction |= neon_logbits (et.size) << 18;
14517 neon_dp_fixup (&inst);
14521 /* A more-specific type check for non-max versions. */
14522 et = neon_check_type (2, NS_QDI,
14523 N_EQK | N_DBL, N_SU_32 | N_KEY);
14524 NEON_ENCODE (IMMED, inst);
14525 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14529 /* Check the various types for the VCVT instruction, and return which version
14530 the current instruction is. */
14532 #define CVT_FLAVOUR_VAR \
14533 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14534 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14535 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14536 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14537 /* Half-precision conversions. */ \
14538 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14539 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14540 /* VFP instructions. */ \
14541 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14542 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14543 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14544 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14545 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14546 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14547 /* VFP instructions with bitshift. */ \
14548 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14549 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14550 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14551 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14552 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14553 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14554 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14555 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14557 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14558 neon_cvt_flavour_##C,
14560 /* The different types of conversions we can do. */
14561 enum neon_cvt_flavour
14564 neon_cvt_flavour_invalid,
14565 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14570 static enum neon_cvt_flavour
14571 get_neon_cvt_flavour (enum neon_shape rs)
14573 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14574 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14575 if (et.type != NT_invtype) \
14577 inst.error = NULL; \
14578 return (neon_cvt_flavour_##C); \
14581 struct neon_type_el et;
14582 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14583 || rs == NS_FF) ? N_VFP : 0;
14584 /* The instruction versions which take an immediate take one register
14585 argument, which is extended to the width of the full register. Thus the
14586 "source" and "destination" registers must have the same width. Hack that
14587 here by making the size equal to the key (wider, in this case) operand. */
14588 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14592 return neon_cvt_flavour_invalid;
14607 /* Neon-syntax VFP conversions. */
14610 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
14612 const char *opname = 0;
14614 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14616 /* Conversions with immediate bitshift. */
14617 const char *enc[] =
14619 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14625 if (flavour < (int) ARRAY_SIZE (enc))
14627 opname = enc[flavour];
14628 constraint (inst.operands[0].reg != inst.operands[1].reg,
14629 _("operands 0 and 1 must be the same register"));
14630 inst.operands[1] = inst.operands[2];
14631 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14636 /* Conversions without bitshift. */
14637 const char *enc[] =
14639 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14645 if (flavour < (int) ARRAY_SIZE (enc))
14646 opname = enc[flavour];
14650 do_vfp_nsyn_opcode (opname);
14654 do_vfp_nsyn_cvtz (void)
14656 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14657 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14658 const char *enc[] =
14660 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14666 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14667 do_vfp_nsyn_opcode (enc[flavour]);
14671 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
14672 enum neon_cvt_mode mode)
14677 set_it_insn_type (OUTSIDE_IT_INSN);
14681 case neon_cvt_flavour_s32_f64:
14685 case neon_cvt_flavour_s32_f32:
14689 case neon_cvt_flavour_u32_f64:
14693 case neon_cvt_flavour_u32_f32:
14698 first_error (_("invalid instruction shape"));
14704 case neon_cvt_mode_a: rm = 0; break;
14705 case neon_cvt_mode_n: rm = 1; break;
14706 case neon_cvt_mode_p: rm = 2; break;
14707 case neon_cvt_mode_m: rm = 3; break;
14708 default: first_error (_("invalid rounding mode")); return;
14711 NEON_ENCODE (FPV8, inst);
14712 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14713 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
14714 inst.instruction |= sz << 8;
14715 inst.instruction |= op << 7;
14716 inst.instruction |= rm << 16;
14717 inst.instruction |= 0xf0000000;
14718 inst.is_neon = TRUE;
14722 do_neon_cvt_1 (enum neon_cvt_mode mode)
14724 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14725 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14726 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14728 /* PR11109: Handle round-to-zero for VCVT conversions. */
14729 if (mode == neon_cvt_mode_z
14730 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14731 && (flavour == neon_cvt_flavour_s32_f32
14732 || flavour == neon_cvt_flavour_u32_f32
14733 || flavour == neon_cvt_flavour_s32_f64
14734 || flavour == neon_cvt_flavour_u32_f64)
14735 && (rs == NS_FD || rs == NS_FF))
14737 do_vfp_nsyn_cvtz ();
14741 /* VFP rather than Neon conversions. */
14742 if (flavour >= neon_cvt_flavour_first_fp)
14744 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14745 do_vfp_nsyn_cvt (rs, flavour);
14747 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14758 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14760 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14763 /* Fixed-point conversion with #0 immediate is encoded as an
14764 integer conversion. */
14765 if (inst.operands[2].present && inst.operands[2].imm == 0)
14767 immbits = 32 - inst.operands[2].imm;
14768 NEON_ENCODE (IMMED, inst);
14769 if (flavour != neon_cvt_flavour_invalid)
14770 inst.instruction |= enctab[flavour];
14771 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14772 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14773 inst.instruction |= LOW4 (inst.operands[1].reg);
14774 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14775 inst.instruction |= neon_quad (rs) << 6;
14776 inst.instruction |= 1 << 21;
14777 inst.instruction |= immbits << 16;
14779 neon_dp_fixup (&inst);
14785 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
14787 NEON_ENCODE (FLOAT, inst);
14788 set_it_insn_type (OUTSIDE_IT_INSN);
14790 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
14793 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14794 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14795 inst.instruction |= LOW4 (inst.operands[1].reg);
14796 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14797 inst.instruction |= neon_quad (rs) << 6;
14798 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
14799 inst.instruction |= mode << 8;
14801 inst.instruction |= 0xfc000000;
14803 inst.instruction |= 0xf0000000;
14809 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14811 NEON_ENCODE (INTEGER, inst);
14813 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14816 if (flavour != neon_cvt_flavour_invalid)
14817 inst.instruction |= enctab[flavour];
14819 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14820 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14821 inst.instruction |= LOW4 (inst.operands[1].reg);
14822 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14823 inst.instruction |= neon_quad (rs) << 6;
14824 inst.instruction |= 2 << 18;
14826 neon_dp_fixup (&inst);
14831 /* Half-precision conversions for Advanced SIMD -- neon. */
14836 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14838 as_bad (_("operand size must match register width"));
14843 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14845 as_bad (_("operand size must match register width"));
14850 inst.instruction = 0x3b60600;
14852 inst.instruction = 0x3b60700;
14854 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14855 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14856 inst.instruction |= LOW4 (inst.operands[1].reg);
14857 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14858 neon_dp_fixup (&inst);
14862 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14863 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14864 do_vfp_nsyn_cvt (rs, flavour);
14866 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14871 do_neon_cvtr (void)
14873 do_neon_cvt_1 (neon_cvt_mode_x);
14879 do_neon_cvt_1 (neon_cvt_mode_z);
14883 do_neon_cvta (void)
14885 do_neon_cvt_1 (neon_cvt_mode_a);
14889 do_neon_cvtn (void)
14891 do_neon_cvt_1 (neon_cvt_mode_n);
14895 do_neon_cvtp (void)
14897 do_neon_cvt_1 (neon_cvt_mode_p);
14901 do_neon_cvtm (void)
14903 do_neon_cvt_1 (neon_cvt_mode_m);
14907 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
14910 mark_feature_used (&fpu_vfp_ext_armv8);
14912 encode_arm_vfp_reg (inst.operands[0].reg,
14913 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
14914 encode_arm_vfp_reg (inst.operands[1].reg,
14915 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
14916 inst.instruction |= to ? 0x10000 : 0;
14917 inst.instruction |= t ? 0x80 : 0;
14918 inst.instruction |= is_double ? 0x100 : 0;
14919 do_vfp_cond_or_thumb ();
14923 do_neon_cvttb_1 (bfd_boolean t)
14925 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
14929 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
14932 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
14934 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
14937 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
14939 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
14942 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
14944 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
14947 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
14954 do_neon_cvtb (void)
14956 do_neon_cvttb_1 (FALSE);
14961 do_neon_cvtt (void)
14963 do_neon_cvttb_1 (TRUE);
14967 neon_move_immediate (void)
14969 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14970 struct neon_type_el et = neon_check_type (2, rs,
14971 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14972 unsigned immlo, immhi = 0, immbits;
14973 int op, cmode, float_p;
14975 constraint (et.type == NT_invtype,
14976 _("operand size must be specified for immediate VMOV"));
14978 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14979 op = (inst.instruction & (1 << 5)) != 0;
14981 immlo = inst.operands[1].imm;
14982 if (inst.operands[1].regisimm)
14983 immhi = inst.operands[1].reg;
14985 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14986 _("immediate has bits set outside the operand size"));
14988 float_p = inst.operands[1].immisfloat;
14990 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14991 et.size, et.type)) == FAIL)
14993 /* Invert relevant bits only. */
14994 neon_invert_size (&immlo, &immhi, et.size);
14995 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14996 with one or the other; those cases are caught by
14997 neon_cmode_for_move_imm. */
14999 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
15000 &op, et.size, et.type)) == FAIL)
15002 first_error (_("immediate out of range"));
15007 inst.instruction &= ~(1 << 5);
15008 inst.instruction |= op << 5;
15010 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15011 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15012 inst.instruction |= neon_quad (rs) << 6;
15013 inst.instruction |= cmode << 8;
15015 neon_write_immbits (immbits);
15021 if (inst.operands[1].isreg)
15023 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15025 NEON_ENCODE (INTEGER, inst);
15026 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15027 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15028 inst.instruction |= LOW4 (inst.operands[1].reg);
15029 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15030 inst.instruction |= neon_quad (rs) << 6;
15034 NEON_ENCODE (IMMED, inst);
15035 neon_move_immediate ();
15038 neon_dp_fixup (&inst);
15041 /* Encode instructions of form:
15043 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15044 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15047 neon_mixed_length (struct neon_type_el et, unsigned size)
15049 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15050 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15051 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15052 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15053 inst.instruction |= LOW4 (inst.operands[2].reg);
15054 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15055 inst.instruction |= (et.type == NT_unsigned) << 24;
15056 inst.instruction |= neon_logbits (size) << 20;
15058 neon_dp_fixup (&inst);
15062 do_neon_dyadic_long (void)
15064 /* FIXME: Type checking for lengthening op. */
15065 struct neon_type_el et = neon_check_type (3, NS_QDD,
15066 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15067 neon_mixed_length (et, et.size);
15071 do_neon_abal (void)
15073 struct neon_type_el et = neon_check_type (3, NS_QDD,
15074 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15075 neon_mixed_length (et, et.size);
15079 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15081 if (inst.operands[2].isscalar)
15083 struct neon_type_el et = neon_check_type (3, NS_QDS,
15084 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
15085 NEON_ENCODE (SCALAR, inst);
15086 neon_mul_mac (et, et.type == NT_unsigned);
15090 struct neon_type_el et = neon_check_type (3, NS_QDD,
15091 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
15092 NEON_ENCODE (INTEGER, inst);
15093 neon_mixed_length (et, et.size);
15098 do_neon_mac_maybe_scalar_long (void)
15100 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15104 do_neon_dyadic_wide (void)
15106 struct neon_type_el et = neon_check_type (3, NS_QQD,
15107 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15108 neon_mixed_length (et, et.size);
15112 do_neon_dyadic_narrow (void)
15114 struct neon_type_el et = neon_check_type (3, NS_QDD,
15115 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
15116 /* Operand sign is unimportant, and the U bit is part of the opcode,
15117 so force the operand type to integer. */
15118 et.type = NT_integer;
15119 neon_mixed_length (et, et.size / 2);
15123 do_neon_mul_sat_scalar_long (void)
15125 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15129 do_neon_vmull (void)
15131 if (inst.operands[2].isscalar)
15132 do_neon_mac_maybe_scalar_long ();
15135 struct neon_type_el et = neon_check_type (3, NS_QDD,
15136 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
15138 if (et.type == NT_poly)
15139 NEON_ENCODE (POLY, inst);
15141 NEON_ENCODE (INTEGER, inst);
15143 /* For polynomial encoding the U bit must be zero, and the size must
15144 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15145 obviously, as 0b10). */
15148 /* Check we're on the correct architecture. */
15149 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15151 _("Instruction form not available on this architecture.");
15156 neon_mixed_length (et, et.size);
15163 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
15164 struct neon_type_el et = neon_check_type (3, rs,
15165 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15166 unsigned imm = (inst.operands[3].imm * et.size) / 8;
15168 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15169 _("shift out of range"));
15170 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15171 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15172 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15173 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15174 inst.instruction |= LOW4 (inst.operands[2].reg);
15175 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15176 inst.instruction |= neon_quad (rs) << 6;
15177 inst.instruction |= imm << 8;
15179 neon_dp_fixup (&inst);
15185 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15186 struct neon_type_el et = neon_check_type (2, rs,
15187 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15188 unsigned op = (inst.instruction >> 7) & 3;
15189 /* N (width of reversed regions) is encoded as part of the bitmask. We
15190 extract it here to check the elements to be reversed are smaller.
15191 Otherwise we'd get a reserved instruction. */
15192 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15193 gas_assert (elsize != 0);
15194 constraint (et.size >= elsize,
15195 _("elements must be smaller than reversal region"));
15196 neon_two_same (neon_quad (rs), 1, et.size);
15202 if (inst.operands[1].isscalar)
15204 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15205 struct neon_type_el et = neon_check_type (2, rs,
15206 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15207 unsigned sizebits = et.size >> 3;
15208 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15209 int logsize = neon_logbits (et.size);
15210 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15212 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15215 NEON_ENCODE (SCALAR, inst);
15216 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15217 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15218 inst.instruction |= LOW4 (dm);
15219 inst.instruction |= HI1 (dm) << 5;
15220 inst.instruction |= neon_quad (rs) << 6;
15221 inst.instruction |= x << 17;
15222 inst.instruction |= sizebits << 16;
15224 neon_dp_fixup (&inst);
15228 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15229 struct neon_type_el et = neon_check_type (2, rs,
15230 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15231 /* Duplicate ARM register to lanes of vector. */
15232 NEON_ENCODE (ARMREG, inst);
15235 case 8: inst.instruction |= 0x400000; break;
15236 case 16: inst.instruction |= 0x000020; break;
15237 case 32: inst.instruction |= 0x000000; break;
15240 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15241 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15242 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15243 inst.instruction |= neon_quad (rs) << 21;
15244 /* The encoding for this instruction is identical for the ARM and Thumb
15245 variants, except for the condition field. */
15246 do_vfp_cond_or_thumb ();
15250 /* VMOV has particularly many variations. It can be one of:
15251 0. VMOV<c><q> <Qd>, <Qm>
15252 1. VMOV<c><q> <Dd>, <Dm>
15253 (Register operations, which are VORR with Rm = Rn.)
15254 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15255 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15257 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15258 (ARM register to scalar.)
15259 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15260 (Two ARM registers to vector.)
15261 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15262 (Scalar to ARM register.)
15263 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15264 (Vector to two ARM registers.)
15265 8. VMOV.F32 <Sd>, <Sm>
15266 9. VMOV.F64 <Dd>, <Dm>
15267 (VFP register moves.)
15268 10. VMOV.F32 <Sd>, #imm
15269 11. VMOV.F64 <Dd>, #imm
15270 (VFP float immediate load.)
15271 12. VMOV <Rd>, <Sm>
15272 (VFP single to ARM reg.)
15273 13. VMOV <Sd>, <Rm>
15274 (ARM reg to VFP single.)
15275 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15276 (Two ARM regs to two VFP singles.)
15277 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15278 (Two VFP singles to two ARM regs.)
15280 These cases can be disambiguated using neon_select_shape, except cases 1/9
15281 and 3/11 which depend on the operand type too.
15283 All the encoded bits are hardcoded by this function.
15285 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15286 Cases 5, 7 may be used with VFPv2 and above.
15288 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15289 can specify a type where it doesn't make sense to, and is ignored). */
15294 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15295 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15297 struct neon_type_el et;
15298 const char *ldconst = 0;
15302 case NS_DD: /* case 1/9. */
15303 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15304 /* It is not an error here if no type is given. */
15306 if (et.type == NT_float && et.size == 64)
15308 do_vfp_nsyn_opcode ("fcpyd");
15311 /* fall through. */
15313 case NS_QQ: /* case 0/1. */
15315 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15317 /* The architecture manual I have doesn't explicitly state which
15318 value the U bit should have for register->register moves, but
15319 the equivalent VORR instruction has U = 0, so do that. */
15320 inst.instruction = 0x0200110;
15321 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15322 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15323 inst.instruction |= LOW4 (inst.operands[1].reg);
15324 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15325 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15326 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15327 inst.instruction |= neon_quad (rs) << 6;
15329 neon_dp_fixup (&inst);
15333 case NS_DI: /* case 3/11. */
15334 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15336 if (et.type == NT_float && et.size == 64)
15338 /* case 11 (fconstd). */
15339 ldconst = "fconstd";
15340 goto encode_fconstd;
15342 /* fall through. */
15344 case NS_QI: /* case 2/3. */
15345 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15347 inst.instruction = 0x0800010;
15348 neon_move_immediate ();
15349 neon_dp_fixup (&inst);
15352 case NS_SR: /* case 4. */
15354 unsigned bcdebits = 0;
15356 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15357 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15359 /* .<size> is optional here, defaulting to .32. */
15360 if (inst.vectype.elems == 0
15361 && inst.operands[0].vectype.type == NT_invtype
15362 && inst.operands[1].vectype.type == NT_invtype)
15364 inst.vectype.el[0].type = NT_untyped;
15365 inst.vectype.el[0].size = 32;
15366 inst.vectype.elems = 1;
15369 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15370 logsize = neon_logbits (et.size);
15372 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15374 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15375 && et.size != 32, _(BAD_FPU));
15376 constraint (et.type == NT_invtype, _("bad type for scalar"));
15377 constraint (x >= 64 / et.size, _("scalar index out of range"));
15381 case 8: bcdebits = 0x8; break;
15382 case 16: bcdebits = 0x1; break;
15383 case 32: bcdebits = 0x0; break;
15387 bcdebits |= x << logsize;
15389 inst.instruction = 0xe000b10;
15390 do_vfp_cond_or_thumb ();
15391 inst.instruction |= LOW4 (dn) << 16;
15392 inst.instruction |= HI1 (dn) << 7;
15393 inst.instruction |= inst.operands[1].reg << 12;
15394 inst.instruction |= (bcdebits & 3) << 5;
15395 inst.instruction |= (bcdebits >> 2) << 21;
15399 case NS_DRR: /* case 5 (fmdrr). */
15400 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15403 inst.instruction = 0xc400b10;
15404 do_vfp_cond_or_thumb ();
15405 inst.instruction |= LOW4 (inst.operands[0].reg);
15406 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15407 inst.instruction |= inst.operands[1].reg << 12;
15408 inst.instruction |= inst.operands[2].reg << 16;
15411 case NS_RS: /* case 6. */
15414 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15415 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15416 unsigned abcdebits = 0;
15418 /* .<dt> is optional here, defaulting to .32. */
15419 if (inst.vectype.elems == 0
15420 && inst.operands[0].vectype.type == NT_invtype
15421 && inst.operands[1].vectype.type == NT_invtype)
15423 inst.vectype.el[0].type = NT_untyped;
15424 inst.vectype.el[0].size = 32;
15425 inst.vectype.elems = 1;
15428 et = neon_check_type (2, NS_NULL,
15429 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15430 logsize = neon_logbits (et.size);
15432 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15434 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15435 && et.size != 32, _(BAD_FPU));
15436 constraint (et.type == NT_invtype, _("bad type for scalar"));
15437 constraint (x >= 64 / et.size, _("scalar index out of range"));
15441 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15442 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15443 case 32: abcdebits = 0x00; break;
15447 abcdebits |= x << logsize;
15448 inst.instruction = 0xe100b10;
15449 do_vfp_cond_or_thumb ();
15450 inst.instruction |= LOW4 (dn) << 16;
15451 inst.instruction |= HI1 (dn) << 7;
15452 inst.instruction |= inst.operands[0].reg << 12;
15453 inst.instruction |= (abcdebits & 3) << 5;
15454 inst.instruction |= (abcdebits >> 2) << 21;
15458 case NS_RRD: /* case 7 (fmrrd). */
15459 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15462 inst.instruction = 0xc500b10;
15463 do_vfp_cond_or_thumb ();
15464 inst.instruction |= inst.operands[0].reg << 12;
15465 inst.instruction |= inst.operands[1].reg << 16;
15466 inst.instruction |= LOW4 (inst.operands[2].reg);
15467 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15470 case NS_FF: /* case 8 (fcpys). */
15471 do_vfp_nsyn_opcode ("fcpys");
15474 case NS_FI: /* case 10 (fconsts). */
15475 ldconst = "fconsts";
15477 if (is_quarter_float (inst.operands[1].imm))
15479 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15480 do_vfp_nsyn_opcode (ldconst);
15483 first_error (_("immediate out of range"));
15486 case NS_RF: /* case 12 (fmrs). */
15487 do_vfp_nsyn_opcode ("fmrs");
15490 case NS_FR: /* case 13 (fmsr). */
15491 do_vfp_nsyn_opcode ("fmsr");
15494 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15495 (one of which is a list), but we have parsed four. Do some fiddling to
15496 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15498 case NS_RRFF: /* case 14 (fmrrs). */
15499 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15500 _("VFP registers must be adjacent"));
15501 inst.operands[2].imm = 2;
15502 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15503 do_vfp_nsyn_opcode ("fmrrs");
15506 case NS_FFRR: /* case 15 (fmsrr). */
15507 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15508 _("VFP registers must be adjacent"));
15509 inst.operands[1] = inst.operands[2];
15510 inst.operands[2] = inst.operands[3];
15511 inst.operands[0].imm = 2;
15512 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15513 do_vfp_nsyn_opcode ("fmsrr");
15517 /* neon_select_shape has determined that the instruction
15518 shape is wrong and has already set the error message. */
15527 do_neon_rshift_round_imm (void)
15529 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15530 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15531 int imm = inst.operands[2].imm;
15533 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15536 inst.operands[2].present = 0;
15541 constraint (imm < 1 || (unsigned)imm > et.size,
15542 _("immediate out of range for shift"));
15543 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15548 do_neon_movl (void)
15550 struct neon_type_el et = neon_check_type (2, NS_QD,
15551 N_EQK | N_DBL, N_SU_32 | N_KEY);
15552 unsigned sizebits = et.size >> 3;
15553 inst.instruction |= sizebits << 19;
15554 neon_two_same (0, et.type == NT_unsigned, -1);
15560 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15561 struct neon_type_el et = neon_check_type (2, rs,
15562 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15563 NEON_ENCODE (INTEGER, inst);
15564 neon_two_same (neon_quad (rs), 1, et.size);
15568 do_neon_zip_uzp (void)
15570 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15571 struct neon_type_el et = neon_check_type (2, rs,
15572 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15573 if (rs == NS_DD && et.size == 32)
15575 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15576 inst.instruction = N_MNEM_vtrn;
15580 neon_two_same (neon_quad (rs), 1, et.size);
15584 do_neon_sat_abs_neg (void)
15586 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15587 struct neon_type_el et = neon_check_type (2, rs,
15588 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15589 neon_two_same (neon_quad (rs), 1, et.size);
15593 do_neon_pair_long (void)
15595 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15596 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15597 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15598 inst.instruction |= (et.type == NT_unsigned) << 7;
15599 neon_two_same (neon_quad (rs), 1, et.size);
15603 do_neon_recip_est (void)
15605 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15606 struct neon_type_el et = neon_check_type (2, rs,
15607 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15608 inst.instruction |= (et.type == NT_float) << 8;
15609 neon_two_same (neon_quad (rs), 1, et.size);
15615 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15616 struct neon_type_el et = neon_check_type (2, rs,
15617 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15618 neon_two_same (neon_quad (rs), 1, et.size);
15624 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15625 struct neon_type_el et = neon_check_type (2, rs,
15626 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15627 neon_two_same (neon_quad (rs), 1, et.size);
15633 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15634 struct neon_type_el et = neon_check_type (2, rs,
15635 N_EQK | N_INT, N_8 | N_KEY);
15636 neon_two_same (neon_quad (rs), 1, et.size);
15642 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15643 neon_two_same (neon_quad (rs), 1, -1);
15647 do_neon_tbl_tbx (void)
15649 unsigned listlenbits;
15650 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15652 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15654 first_error (_("bad list length for table lookup"));
15658 listlenbits = inst.operands[1].imm - 1;
15659 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15660 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15661 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15662 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15663 inst.instruction |= LOW4 (inst.operands[2].reg);
15664 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15665 inst.instruction |= listlenbits << 8;
15667 neon_dp_fixup (&inst);
15671 do_neon_ldm_stm (void)
15673 /* P, U and L bits are part of bitmask. */
15674 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15675 unsigned offsetbits = inst.operands[1].imm * 2;
15677 if (inst.operands[1].issingle)
15679 do_vfp_nsyn_ldm_stm (is_dbmode);
15683 constraint (is_dbmode && !inst.operands[0].writeback,
15684 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15686 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15687 _("register list must contain at least 1 and at most 16 "
15690 inst.instruction |= inst.operands[0].reg << 16;
15691 inst.instruction |= inst.operands[0].writeback << 21;
15692 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15693 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15695 inst.instruction |= offsetbits;
15697 do_vfp_cond_or_thumb ();
15701 do_neon_ldr_str (void)
15703 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15705 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15706 And is UNPREDICTABLE in thumb mode. */
15708 && inst.operands[1].reg == REG_PC
15709 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
15712 inst.error = _("Use of PC here is UNPREDICTABLE");
15713 else if (warn_on_deprecated)
15714 as_warn (_("Use of PC here is deprecated"));
15717 if (inst.operands[0].issingle)
15720 do_vfp_nsyn_opcode ("flds");
15722 do_vfp_nsyn_opcode ("fsts");
15727 do_vfp_nsyn_opcode ("fldd");
15729 do_vfp_nsyn_opcode ("fstd");
15733 /* "interleave" version also handles non-interleaving register VLD1/VST1
15737 do_neon_ld_st_interleave (void)
15739 struct neon_type_el et = neon_check_type (1, NS_NULL,
15740 N_8 | N_16 | N_32 | N_64);
15741 unsigned alignbits = 0;
15743 /* The bits in this table go:
15744 0: register stride of one (0) or two (1)
15745 1,2: register list length, minus one (1, 2, 3, 4).
15746 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15747 We use -1 for invalid entries. */
15748 const int typetable[] =
15750 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15751 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15752 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15753 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15757 if (et.type == NT_invtype)
15760 if (inst.operands[1].immisalign)
15761 switch (inst.operands[1].imm >> 8)
15763 case 64: alignbits = 1; break;
15765 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15766 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15767 goto bad_alignment;
15771 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15772 goto bad_alignment;
15777 first_error (_("bad alignment"));
15781 inst.instruction |= alignbits << 4;
15782 inst.instruction |= neon_logbits (et.size) << 6;
15784 /* Bits [4:6] of the immediate in a list specifier encode register stride
15785 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15786 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15787 up the right value for "type" in a table based on this value and the given
15788 list style, then stick it back. */
15789 idx = ((inst.operands[0].imm >> 4) & 7)
15790 | (((inst.instruction >> 8) & 3) << 3);
15792 typebits = typetable[idx];
15794 constraint (typebits == -1, _("bad list type for instruction"));
15795 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
15796 _("bad element type for instruction"));
15798 inst.instruction &= ~0xf00;
15799 inst.instruction |= typebits << 8;
15802 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15803 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15804 otherwise. The variable arguments are a list of pairs of legal (size, align)
15805 values, terminated with -1. */
15808 neon_alignment_bit (int size, int align, int *do_align, ...)
15811 int result = FAIL, thissize, thisalign;
15813 if (!inst.operands[1].immisalign)
15819 va_start (ap, do_align);
15823 thissize = va_arg (ap, int);
15824 if (thissize == -1)
15826 thisalign = va_arg (ap, int);
15828 if (size == thissize && align == thisalign)
15831 while (result != SUCCESS);
15835 if (result == SUCCESS)
15838 first_error (_("unsupported alignment for instruction"));
15844 do_neon_ld_st_lane (void)
15846 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15847 int align_good, do_align = 0;
15848 int logsize = neon_logbits (et.size);
15849 int align = inst.operands[1].imm >> 8;
15850 int n = (inst.instruction >> 8) & 3;
15851 int max_el = 64 / et.size;
15853 if (et.type == NT_invtype)
15856 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15857 _("bad list length"));
15858 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15859 _("scalar index out of range"));
15860 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15862 _("stride of 2 unavailable when element size is 8"));
15866 case 0: /* VLD1 / VST1. */
15867 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15869 if (align_good == FAIL)
15873 unsigned alignbits = 0;
15876 case 16: alignbits = 0x1; break;
15877 case 32: alignbits = 0x3; break;
15880 inst.instruction |= alignbits << 4;
15884 case 1: /* VLD2 / VST2. */
15885 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15887 if (align_good == FAIL)
15890 inst.instruction |= 1 << 4;
15893 case 2: /* VLD3 / VST3. */
15894 constraint (inst.operands[1].immisalign,
15895 _("can't use alignment with this instruction"));
15898 case 3: /* VLD4 / VST4. */
15899 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15900 16, 64, 32, 64, 32, 128, -1);
15901 if (align_good == FAIL)
15905 unsigned alignbits = 0;
15908 case 8: alignbits = 0x1; break;
15909 case 16: alignbits = 0x1; break;
15910 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15913 inst.instruction |= alignbits << 4;
15920 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15921 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15922 inst.instruction |= 1 << (4 + logsize);
15924 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15925 inst.instruction |= logsize << 10;
15928 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15931 do_neon_ld_dup (void)
15933 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15934 int align_good, do_align = 0;
15936 if (et.type == NT_invtype)
15939 switch ((inst.instruction >> 8) & 3)
15941 case 0: /* VLD1. */
15942 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15943 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15944 &do_align, 16, 16, 32, 32, -1);
15945 if (align_good == FAIL)
15947 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15950 case 2: inst.instruction |= 1 << 5; break;
15951 default: first_error (_("bad list length")); return;
15953 inst.instruction |= neon_logbits (et.size) << 6;
15956 case 1: /* VLD2. */
15957 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15958 &do_align, 8, 16, 16, 32, 32, 64, -1);
15959 if (align_good == FAIL)
15961 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15962 _("bad list length"));
15963 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15964 inst.instruction |= 1 << 5;
15965 inst.instruction |= neon_logbits (et.size) << 6;
15968 case 2: /* VLD3. */
15969 constraint (inst.operands[1].immisalign,
15970 _("can't use alignment with this instruction"));
15971 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15972 _("bad list length"));
15973 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15974 inst.instruction |= 1 << 5;
15975 inst.instruction |= neon_logbits (et.size) << 6;
15978 case 3: /* VLD4. */
15980 int align = inst.operands[1].imm >> 8;
15981 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15982 16, 64, 32, 64, 32, 128, -1);
15983 if (align_good == FAIL)
15985 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15986 _("bad list length"));
15987 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15988 inst.instruction |= 1 << 5;
15989 if (et.size == 32 && align == 128)
15990 inst.instruction |= 0x3 << 6;
15992 inst.instruction |= neon_logbits (et.size) << 6;
15999 inst.instruction |= do_align << 4;
16002 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16003 apart from bits [11:4]. */
16006 do_neon_ldx_stx (void)
16008 if (inst.operands[1].isreg)
16009 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16011 switch (NEON_LANE (inst.operands[0].imm))
16013 case NEON_INTERLEAVE_LANES:
16014 NEON_ENCODE (INTERLV, inst);
16015 do_neon_ld_st_interleave ();
16018 case NEON_ALL_LANES:
16019 NEON_ENCODE (DUP, inst);
16020 if (inst.instruction == N_INV)
16022 first_error ("only loads support such operands");
16029 NEON_ENCODE (LANE, inst);
16030 do_neon_ld_st_lane ();
16033 /* L bit comes from bit mask. */
16034 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16035 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16036 inst.instruction |= inst.operands[1].reg << 16;
16038 if (inst.operands[1].postind)
16040 int postreg = inst.operands[1].imm & 0xf;
16041 constraint (!inst.operands[1].immisreg,
16042 _("post-index must be a register"));
16043 constraint (postreg == 0xd || postreg == 0xf,
16044 _("bad register for post-index"));
16045 inst.instruction |= postreg;
16049 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16050 constraint (inst.reloc.exp.X_op != O_constant
16051 || inst.reloc.exp.X_add_number != 0,
16054 if (inst.operands[1].writeback)
16056 inst.instruction |= 0xd;
16059 inst.instruction |= 0xf;
16063 inst.instruction |= 0xf9000000;
16065 inst.instruction |= 0xf4000000;
16070 do_vfp_nsyn_fpv8 (enum neon_shape rs)
16072 NEON_ENCODE (FPV8, inst);
16075 do_vfp_sp_dyadic ();
16077 do_vfp_dp_rd_rn_rm ();
16080 inst.instruction |= 0x100;
16082 inst.instruction |= 0xf0000000;
16088 set_it_insn_type (OUTSIDE_IT_INSN);
16090 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16091 first_error (_("invalid instruction shape"));
16097 set_it_insn_type (OUTSIDE_IT_INSN);
16099 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16102 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16105 neon_dyadic_misc (NT_untyped, N_F32, 0);
16109 do_vrint_1 (enum neon_cvt_mode mode)
16111 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16112 struct neon_type_el et;
16117 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16118 if (et.type != NT_invtype)
16120 /* VFP encodings. */
16121 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16122 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16123 set_it_insn_type (OUTSIDE_IT_INSN);
16125 NEON_ENCODE (FPV8, inst);
16127 do_vfp_sp_monadic ();
16129 do_vfp_dp_rd_rm ();
16133 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16134 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16135 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16136 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16137 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16138 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16139 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16143 inst.instruction |= (rs == NS_DD) << 8;
16144 do_vfp_cond_or_thumb ();
16148 /* Neon encodings (or something broken...). */
16150 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16152 if (et.type == NT_invtype)
16155 set_it_insn_type (OUTSIDE_IT_INSN);
16156 NEON_ENCODE (FLOAT, inst);
16158 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16161 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16162 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16163 inst.instruction |= LOW4 (inst.operands[1].reg);
16164 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16165 inst.instruction |= neon_quad (rs) << 6;
16168 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16169 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16170 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16171 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16172 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16173 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16174 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16179 inst.instruction |= 0xfc000000;
16181 inst.instruction |= 0xf0000000;
16188 do_vrint_1 (neon_cvt_mode_x);
16194 do_vrint_1 (neon_cvt_mode_z);
16200 do_vrint_1 (neon_cvt_mode_r);
16206 do_vrint_1 (neon_cvt_mode_a);
16212 do_vrint_1 (neon_cvt_mode_n);
16218 do_vrint_1 (neon_cvt_mode_p);
16224 do_vrint_1 (neon_cvt_mode_m);
16227 /* Crypto v1 instructions. */
16229 do_crypto_2op_1 (unsigned elttype, int op)
16231 set_it_insn_type (OUTSIDE_IT_INSN);
16233 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16239 NEON_ENCODE (INTEGER, inst);
16240 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16241 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16242 inst.instruction |= LOW4 (inst.operands[1].reg);
16243 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16245 inst.instruction |= op << 6;
16248 inst.instruction |= 0xfc000000;
16250 inst.instruction |= 0xf0000000;
16254 do_crypto_3op_1 (int u, int op)
16256 set_it_insn_type (OUTSIDE_IT_INSN);
16258 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16259 N_32 | N_UNT | N_KEY).type == NT_invtype)
16264 NEON_ENCODE (INTEGER, inst);
16265 neon_three_same (1, u, 8 << op);
16271 do_crypto_2op_1 (N_8, 0);
16277 do_crypto_2op_1 (N_8, 1);
16283 do_crypto_2op_1 (N_8, 2);
16289 do_crypto_2op_1 (N_8, 3);
16295 do_crypto_3op_1 (0, 0);
16301 do_crypto_3op_1 (0, 1);
16307 do_crypto_3op_1 (0, 2);
16313 do_crypto_3op_1 (0, 3);
16319 do_crypto_3op_1 (1, 0);
16325 do_crypto_3op_1 (1, 1);
16329 do_sha256su1 (void)
16331 do_crypto_3op_1 (1, 2);
16337 do_crypto_2op_1 (N_32, -1);
16343 do_crypto_2op_1 (N_32, 0);
16347 do_sha256su0 (void)
16349 do_crypto_2op_1 (N_32, 1);
16353 do_crc32_1 (unsigned int poly, unsigned int sz)
16355 unsigned int Rd = inst.operands[0].reg;
16356 unsigned int Rn = inst.operands[1].reg;
16357 unsigned int Rm = inst.operands[2].reg;
16359 set_it_insn_type (OUTSIDE_IT_INSN);
16360 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
16361 inst.instruction |= LOW4 (Rn) << 16;
16362 inst.instruction |= LOW4 (Rm);
16363 inst.instruction |= sz << (thumb_mode ? 4 : 21);
16364 inst.instruction |= poly << (thumb_mode ? 20 : 9);
16366 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
16367 as_warn (UNPRED_REG ("r15"));
16368 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
16369 as_warn (UNPRED_REG ("r13"));
16409 /* Overall per-instruction processing. */
16411 /* We need to be able to fix up arbitrary expressions in some statements.
16412 This is so that we can handle symbols that are an arbitrary distance from
16413 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16414 which returns part of an address in a form which will be valid for
16415 a data instruction. We do this by pushing the expression into a symbol
16416 in the expr_section, and creating a fix for that. */
16419 fix_new_arm (fragS * frag,
16433 /* Create an absolute valued symbol, so we have something to
16434 refer to in the object file. Unfortunately for us, gas's
16435 generic expression parsing will already have folded out
16436 any use of .set foo/.type foo %function that may have
16437 been used to set type information of the target location,
16438 that's being specified symbolically. We have to presume
16439 the user knows what they are doing. */
16443 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16445 symbol = symbol_find_or_make (name);
16446 S_SET_SEGMENT (symbol, absolute_section);
16447 symbol_set_frag (symbol, &zero_address_frag);
16448 S_SET_VALUE (symbol, exp->X_add_number);
16449 exp->X_op = O_symbol;
16450 exp->X_add_symbol = symbol;
16451 exp->X_add_number = 0;
16457 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
16458 (enum bfd_reloc_code_real) reloc);
16462 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
16463 pc_rel, (enum bfd_reloc_code_real) reloc);
16467 /* Mark whether the fix is to a THUMB instruction, or an ARM
16469 new_fix->tc_fix_data = thumb_mode;
16472 /* Create a frg for an instruction requiring relaxation. */
16474 output_relax_insn (void)
16480 /* The size of the instruction is unknown, so tie the debug info to the
16481 start of the instruction. */
16482 dwarf2_emit_insn (0);
16484 switch (inst.reloc.exp.X_op)
16487 sym = inst.reloc.exp.X_add_symbol;
16488 offset = inst.reloc.exp.X_add_number;
16492 offset = inst.reloc.exp.X_add_number;
16495 sym = make_expr_symbol (&inst.reloc.exp);
16499 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16500 inst.relax, sym, offset, NULL/*offset, opcode*/);
16501 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
16504 /* Write a 32-bit thumb instruction to buf. */
16506 put_thumb32_insn (char * buf, unsigned long insn)
16508 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16509 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16513 output_inst (const char * str)
16519 as_bad ("%s -- `%s'", inst.error, str);
16524 output_relax_insn ();
16527 if (inst.size == 0)
16530 to = frag_more (inst.size);
16531 /* PR 9814: Record the thumb mode into the current frag so that we know
16532 what type of NOP padding to use, if necessary. We override any previous
16533 setting so that if the mode has changed then the NOPS that we use will
16534 match the encoding of the last instruction in the frag. */
16535 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
16537 if (thumb_mode && (inst.size > THUMB_SIZE))
16539 gas_assert (inst.size == (2 * THUMB_SIZE));
16540 put_thumb32_insn (to, inst.instruction);
16542 else if (inst.size > INSN_SIZE)
16544 gas_assert (inst.size == (2 * INSN_SIZE));
16545 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16546 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
16549 md_number_to_chars (to, inst.instruction, inst.size);
16551 if (inst.reloc.type != BFD_RELOC_UNUSED)
16552 fix_new_arm (frag_now, to - frag_now->fr_literal,
16553 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16556 dwarf2_emit_insn (inst.size);
16560 output_it_inst (int cond, int mask, char * to)
16562 unsigned long instruction = 0xbf00;
16565 instruction |= mask;
16566 instruction |= cond << 4;
16570 to = frag_more (2);
16572 dwarf2_emit_insn (2);
16576 md_number_to_chars (to, instruction, 2);
16581 /* Tag values used in struct asm_opcode's tag field. */
16584 OT_unconditional, /* Instruction cannot be conditionalized.
16585 The ARM condition field is still 0xE. */
16586 OT_unconditionalF, /* Instruction cannot be conditionalized
16587 and carries 0xF in its ARM condition field. */
16588 OT_csuffix, /* Instruction takes a conditional suffix. */
16589 OT_csuffixF, /* Some forms of the instruction take a conditional
16590 suffix, others place 0xF where the condition field
16592 OT_cinfix3, /* Instruction takes a conditional infix,
16593 beginning at character index 3. (In
16594 unified mode, it becomes a suffix.) */
16595 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16596 tsts, cmps, cmns, and teqs. */
16597 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16598 character index 3, even in unified mode. Used for
16599 legacy instructions where suffix and infix forms
16600 may be ambiguous. */
16601 OT_csuf_or_in3, /* Instruction takes either a conditional
16602 suffix or an infix at character index 3. */
16603 OT_odd_infix_unc, /* This is the unconditional variant of an
16604 instruction that takes a conditional infix
16605 at an unusual position. In unified mode,
16606 this variant will accept a suffix. */
16607 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16608 are the conditional variants of instructions that
16609 take conditional infixes in unusual positions.
16610 The infix appears at character index
16611 (tag - OT_odd_infix_0). These are not accepted
16612 in unified mode. */
16615 /* Subroutine of md_assemble, responsible for looking up the primary
16616 opcode from the mnemonic the user wrote. STR points to the
16617 beginning of the mnemonic.
16619 This is not simply a hash table lookup, because of conditional
16620 variants. Most instructions have conditional variants, which are
16621 expressed with a _conditional affix_ to the mnemonic. If we were
16622 to encode each conditional variant as a literal string in the opcode
16623 table, it would have approximately 20,000 entries.
16625 Most mnemonics take this affix as a suffix, and in unified syntax,
16626 'most' is upgraded to 'all'. However, in the divided syntax, some
16627 instructions take the affix as an infix, notably the s-variants of
16628 the arithmetic instructions. Of those instructions, all but six
16629 have the infix appear after the third character of the mnemonic.
16631 Accordingly, the algorithm for looking up primary opcodes given
16634 1. Look up the identifier in the opcode table.
16635 If we find a match, go to step U.
16637 2. Look up the last two characters of the identifier in the
16638 conditions table. If we find a match, look up the first N-2
16639 characters of the identifier in the opcode table. If we
16640 find a match, go to step CE.
16642 3. Look up the fourth and fifth characters of the identifier in
16643 the conditions table. If we find a match, extract those
16644 characters from the identifier, and look up the remaining
16645 characters in the opcode table. If we find a match, go
16650 U. Examine the tag field of the opcode structure, in case this is
16651 one of the six instructions with its conditional infix in an
16652 unusual place. If it is, the tag tells us where to find the
16653 infix; look it up in the conditions table and set inst.cond
16654 accordingly. Otherwise, this is an unconditional instruction.
16655 Again set inst.cond accordingly. Return the opcode structure.
16657 CE. Examine the tag field to make sure this is an instruction that
16658 should receive a conditional suffix. If it is not, fail.
16659 Otherwise, set inst.cond from the suffix we already looked up,
16660 and return the opcode structure.
16662 CM. Examine the tag field to make sure this is an instruction that
16663 should receive a conditional infix after the third character.
16664 If it is not, fail. Otherwise, undo the edits to the current
16665 line of input and proceed as for case CE. */
16667 static const struct asm_opcode *
16668 opcode_lookup (char **str)
16672 const struct asm_opcode *opcode;
16673 const struct asm_cond *cond;
16676 /* Scan up to the end of the mnemonic, which must end in white space,
16677 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16678 for (base = end = *str; *end != '\0'; end++)
16679 if (*end == ' ' || *end == '.')
16685 /* Handle a possible width suffix and/or Neon type suffix. */
16690 /* The .w and .n suffixes are only valid if the unified syntax is in
16692 if (unified_syntax && end[1] == 'w')
16694 else if (unified_syntax && end[1] == 'n')
16699 inst.vectype.elems = 0;
16701 *str = end + offset;
16703 if (end[offset] == '.')
16705 /* See if we have a Neon type suffix (possible in either unified or
16706 non-unified ARM syntax mode). */
16707 if (parse_neon_type (&inst.vectype, str) == FAIL)
16710 else if (end[offset] != '\0' && end[offset] != ' ')
16716 /* Look for unaffixed or special-case affixed mnemonic. */
16717 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16722 if (opcode->tag < OT_odd_infix_0)
16724 inst.cond = COND_ALWAYS;
16728 if (warn_on_deprecated && unified_syntax)
16729 as_warn (_("conditional infixes are deprecated in unified syntax"));
16730 affix = base + (opcode->tag - OT_odd_infix_0);
16731 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16734 inst.cond = cond->value;
16738 /* Cannot have a conditional suffix on a mnemonic of less than two
16740 if (end - base < 3)
16743 /* Look for suffixed mnemonic. */
16745 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16746 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16748 if (opcode && cond)
16751 switch (opcode->tag)
16753 case OT_cinfix3_legacy:
16754 /* Ignore conditional suffixes matched on infix only mnemonics. */
16758 case OT_cinfix3_deprecated:
16759 case OT_odd_infix_unc:
16760 if (!unified_syntax)
16762 /* else fall through */
16766 case OT_csuf_or_in3:
16767 inst.cond = cond->value;
16770 case OT_unconditional:
16771 case OT_unconditionalF:
16773 inst.cond = cond->value;
16776 /* Delayed diagnostic. */
16777 inst.error = BAD_COND;
16778 inst.cond = COND_ALWAYS;
16787 /* Cannot have a usual-position infix on a mnemonic of less than
16788 six characters (five would be a suffix). */
16789 if (end - base < 6)
16792 /* Look for infixed mnemonic in the usual position. */
16794 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16798 memcpy (save, affix, 2);
16799 memmove (affix, affix + 2, (end - affix) - 2);
16800 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16802 memmove (affix + 2, affix, (end - affix) - 2);
16803 memcpy (affix, save, 2);
16806 && (opcode->tag == OT_cinfix3
16807 || opcode->tag == OT_cinfix3_deprecated
16808 || opcode->tag == OT_csuf_or_in3
16809 || opcode->tag == OT_cinfix3_legacy))
16812 if (warn_on_deprecated && unified_syntax
16813 && (opcode->tag == OT_cinfix3
16814 || opcode->tag == OT_cinfix3_deprecated))
16815 as_warn (_("conditional infixes are deprecated in unified syntax"));
16817 inst.cond = cond->value;
16824 /* This function generates an initial IT instruction, leaving its block
16825 virtually open for the new instructions. Eventually,
16826 the mask will be updated by now_it_add_mask () each time
16827 a new instruction needs to be included in the IT block.
16828 Finally, the block is closed with close_automatic_it_block ().
16829 The block closure can be requested either from md_assemble (),
16830 a tencode (), or due to a label hook. */
16833 new_automatic_it_block (int cond)
16835 now_it.state = AUTOMATIC_IT_BLOCK;
16836 now_it.mask = 0x18;
16838 now_it.block_length = 1;
16839 mapping_state (MAP_THUMB);
16840 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16841 now_it.warn_deprecated = FALSE;
16842 now_it.insn_cond = TRUE;
16845 /* Close an automatic IT block.
16846 See comments in new_automatic_it_block (). */
16849 close_automatic_it_block (void)
16851 now_it.mask = 0x10;
16852 now_it.block_length = 0;
16855 /* Update the mask of the current automatically-generated IT
16856 instruction. See comments in new_automatic_it_block (). */
16859 now_it_add_mask (int cond)
16861 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16862 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16863 | ((bitvalue) << (nbit)))
16864 const int resulting_bit = (cond & 1);
16866 now_it.mask &= 0xf;
16867 now_it.mask = SET_BIT_VALUE (now_it.mask,
16869 (5 - now_it.block_length));
16870 now_it.mask = SET_BIT_VALUE (now_it.mask,
16872 ((5 - now_it.block_length) - 1) );
16873 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16876 #undef SET_BIT_VALUE
16879 /* The IT blocks handling machinery is accessed through the these functions:
16880 it_fsm_pre_encode () from md_assemble ()
16881 set_it_insn_type () optional, from the tencode functions
16882 set_it_insn_type_last () ditto
16883 in_it_block () ditto
16884 it_fsm_post_encode () from md_assemble ()
16885 force_automatic_it_block_close () from label habdling functions
16888 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16889 initializing the IT insn type with a generic initial value depending
16890 on the inst.condition.
16891 2) During the tencode function, two things may happen:
16892 a) The tencode function overrides the IT insn type by
16893 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16894 b) The tencode function queries the IT block state by
16895 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16897 Both set_it_insn_type and in_it_block run the internal FSM state
16898 handling function (handle_it_state), because: a) setting the IT insn
16899 type may incur in an invalid state (exiting the function),
16900 and b) querying the state requires the FSM to be updated.
16901 Specifically we want to avoid creating an IT block for conditional
16902 branches, so it_fsm_pre_encode is actually a guess and we can't
16903 determine whether an IT block is required until the tencode () routine
16904 has decided what type of instruction this actually it.
16905 Because of this, if set_it_insn_type and in_it_block have to be used,
16906 set_it_insn_type has to be called first.
16908 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16909 determines the insn IT type depending on the inst.cond code.
16910 When a tencode () routine encodes an instruction that can be
16911 either outside an IT block, or, in the case of being inside, has to be
16912 the last one, set_it_insn_type_last () will determine the proper
16913 IT instruction type based on the inst.cond code. Otherwise,
16914 set_it_insn_type can be called for overriding that logic or
16915 for covering other cases.
16917 Calling handle_it_state () may not transition the IT block state to
16918 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16919 still queried. Instead, if the FSM determines that the state should
16920 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16921 after the tencode () function: that's what it_fsm_post_encode () does.
16923 Since in_it_block () calls the state handling function to get an
16924 updated state, an error may occur (due to invalid insns combination).
16925 In that case, inst.error is set.
16926 Therefore, inst.error has to be checked after the execution of
16927 the tencode () routine.
16929 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16930 any pending state change (if any) that didn't take place in
16931 handle_it_state () as explained above. */
16934 it_fsm_pre_encode (void)
16936 if (inst.cond != COND_ALWAYS)
16937 inst.it_insn_type = INSIDE_IT_INSN;
16939 inst.it_insn_type = OUTSIDE_IT_INSN;
16941 now_it.state_handled = 0;
16944 /* IT state FSM handling function. */
16947 handle_it_state (void)
16949 now_it.state_handled = 1;
16950 now_it.insn_cond = FALSE;
16952 switch (now_it.state)
16954 case OUTSIDE_IT_BLOCK:
16955 switch (inst.it_insn_type)
16957 case OUTSIDE_IT_INSN:
16960 case INSIDE_IT_INSN:
16961 case INSIDE_IT_LAST_INSN:
16962 if (thumb_mode == 0)
16965 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16966 as_tsktsk (_("Warning: conditional outside an IT block"\
16971 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16972 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16974 /* Automatically generate the IT instruction. */
16975 new_automatic_it_block (inst.cond);
16976 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16977 close_automatic_it_block ();
16981 inst.error = BAD_OUT_IT;
16987 case IF_INSIDE_IT_LAST_INSN:
16988 case NEUTRAL_IT_INSN:
16992 now_it.state = MANUAL_IT_BLOCK;
16993 now_it.block_length = 0;
16998 case AUTOMATIC_IT_BLOCK:
16999 /* Three things may happen now:
17000 a) We should increment current it block size;
17001 b) We should close current it block (closing insn or 4 insns);
17002 c) We should close current it block and start a new one (due
17003 to incompatible conditions or
17004 4 insns-length block reached). */
17006 switch (inst.it_insn_type)
17008 case OUTSIDE_IT_INSN:
17009 /* The closure of the block shall happen immediatelly,
17010 so any in_it_block () call reports the block as closed. */
17011 force_automatic_it_block_close ();
17014 case INSIDE_IT_INSN:
17015 case INSIDE_IT_LAST_INSN:
17016 case IF_INSIDE_IT_LAST_INSN:
17017 now_it.block_length++;
17019 if (now_it.block_length > 4
17020 || !now_it_compatible (inst.cond))
17022 force_automatic_it_block_close ();
17023 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
17024 new_automatic_it_block (inst.cond);
17028 now_it.insn_cond = TRUE;
17029 now_it_add_mask (inst.cond);
17032 if (now_it.state == AUTOMATIC_IT_BLOCK
17033 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
17034 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
17035 close_automatic_it_block ();
17038 case NEUTRAL_IT_INSN:
17039 now_it.block_length++;
17040 now_it.insn_cond = TRUE;
17042 if (now_it.block_length > 4)
17043 force_automatic_it_block_close ();
17045 now_it_add_mask (now_it.cc & 1);
17049 close_automatic_it_block ();
17050 now_it.state = MANUAL_IT_BLOCK;
17055 case MANUAL_IT_BLOCK:
17057 /* Check conditional suffixes. */
17058 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
17061 now_it.mask &= 0x1f;
17062 is_last = (now_it.mask == 0x10);
17063 now_it.insn_cond = TRUE;
17065 switch (inst.it_insn_type)
17067 case OUTSIDE_IT_INSN:
17068 inst.error = BAD_NOT_IT;
17071 case INSIDE_IT_INSN:
17072 if (cond != inst.cond)
17074 inst.error = BAD_IT_COND;
17079 case INSIDE_IT_LAST_INSN:
17080 case IF_INSIDE_IT_LAST_INSN:
17081 if (cond != inst.cond)
17083 inst.error = BAD_IT_COND;
17088 inst.error = BAD_BRANCH;
17093 case NEUTRAL_IT_INSN:
17094 /* The BKPT instruction is unconditional even in an IT block. */
17098 inst.error = BAD_IT_IT;
17108 struct depr_insn_mask
17110 unsigned long pattern;
17111 unsigned long mask;
17112 const char* description;
17115 /* List of 16-bit instruction patterns deprecated in an IT block in
17117 static const struct depr_insn_mask depr_it_insns[] = {
17118 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17119 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17120 { 0xa000, 0xb800, N_("ADR") },
17121 { 0x4800, 0xf800, N_("Literal loads") },
17122 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17123 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17128 it_fsm_post_encode (void)
17132 if (!now_it.state_handled)
17133 handle_it_state ();
17135 if (now_it.insn_cond
17136 && !now_it.warn_deprecated
17137 && warn_on_deprecated
17138 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17140 if (inst.instruction >= 0x10000)
17142 as_warn (_("IT blocks containing 32-bit Thumb instructions are "
17143 "deprecated in ARMv8"));
17144 now_it.warn_deprecated = TRUE;
17148 const struct depr_insn_mask *p = depr_it_insns;
17150 while (p->mask != 0)
17152 if ((inst.instruction & p->mask) == p->pattern)
17154 as_warn (_("IT blocks containing 16-bit Thumb instructions "
17155 "of the following class are deprecated in ARMv8: "
17156 "%s"), p->description);
17157 now_it.warn_deprecated = TRUE;
17165 if (now_it.block_length > 1)
17167 as_warn (_("IT blocks containing more than one conditional "
17168 "instruction are deprecated in ARMv8"));
17169 now_it.warn_deprecated = TRUE;
17173 is_last = (now_it.mask == 0x10);
17176 now_it.state = OUTSIDE_IT_BLOCK;
17182 force_automatic_it_block_close (void)
17184 if (now_it.state == AUTOMATIC_IT_BLOCK)
17186 close_automatic_it_block ();
17187 now_it.state = OUTSIDE_IT_BLOCK;
17195 if (!now_it.state_handled)
17196 handle_it_state ();
17198 return now_it.state != OUTSIDE_IT_BLOCK;
17202 md_assemble (char *str)
17205 const struct asm_opcode * opcode;
17207 /* Align the previous label if needed. */
17208 if (last_label_seen != NULL)
17210 symbol_set_frag (last_label_seen, frag_now);
17211 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17212 S_SET_SEGMENT (last_label_seen, now_seg);
17215 memset (&inst, '\0', sizeof (inst));
17216 inst.reloc.type = BFD_RELOC_UNUSED;
17218 opcode = opcode_lookup (&p);
17221 /* It wasn't an instruction, but it might be a register alias of
17222 the form alias .req reg, or a Neon .dn/.qn directive. */
17223 if (! create_register_alias (str, p)
17224 && ! create_neon_reg_alias (str, p))
17225 as_bad (_("bad instruction `%s'"), str);
17230 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
17231 as_warn (_("s suffix on comparison instruction is deprecated"));
17233 /* The value which unconditional instructions should have in place of the
17234 condition field. */
17235 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17239 arm_feature_set variant;
17241 variant = cpu_variant;
17242 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17243 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17244 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
17245 /* Check that this instruction is supported for this CPU. */
17246 if (!opcode->tvariant
17247 || (thumb_mode == 1
17248 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
17250 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
17253 if (inst.cond != COND_ALWAYS && !unified_syntax
17254 && opcode->tencode != do_t_branch)
17256 as_bad (_("Thumb does not support conditional execution"));
17260 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
17262 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
17263 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17264 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17266 /* Two things are addressed here.
17267 1) Implicit require narrow instructions on Thumb-1.
17268 This avoids relaxation accidentally introducing Thumb-2
17270 2) Reject wide instructions in non Thumb-2 cores. */
17271 if (inst.size_req == 0)
17273 else if (inst.size_req == 4)
17275 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
17281 inst.instruction = opcode->tvalue;
17283 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
17285 /* Prepare the it_insn_type for those encodings that don't set
17287 it_fsm_pre_encode ();
17289 opcode->tencode ();
17291 it_fsm_post_encode ();
17294 if (!(inst.error || inst.relax))
17296 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
17297 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17298 if (inst.size_req && inst.size_req != inst.size)
17300 as_bad (_("cannot honor width suffix -- `%s'"), str);
17305 /* Something has gone badly wrong if we try to relax a fixed size
17307 gas_assert (inst.size_req == 0 || !inst.relax);
17309 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17310 *opcode->tvariant);
17311 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17312 set those bits when Thumb-2 32-bit instructions are seen. ie.
17313 anything other than bl/blx and v6-M instructions.
17314 This is overly pessimistic for relaxable instructions. */
17315 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
17317 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17318 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
17319 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17322 check_neon_suffixes;
17326 mapping_state (MAP_THUMB);
17329 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
17333 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17334 is_bx = (opcode->aencode == do_bx);
17336 /* Check that this instruction is supported for this CPU. */
17337 if (!(is_bx && fix_v4bx)
17338 && !(opcode->avariant &&
17339 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
17341 as_bad (_("selected processor does not support ARM mode `%s'"), str);
17346 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17350 inst.instruction = opcode->avalue;
17351 if (opcode->tag == OT_unconditionalF)
17352 inst.instruction |= 0xF << 28;
17354 inst.instruction |= inst.cond << 28;
17355 inst.size = INSN_SIZE;
17356 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
17358 it_fsm_pre_encode ();
17359 opcode->aencode ();
17360 it_fsm_post_encode ();
17362 /* Arm mode bx is marked as both v4T and v5 because it's still required
17363 on a hypothetical non-thumb v5 core. */
17365 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
17367 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17368 *opcode->avariant);
17370 check_neon_suffixes;
17374 mapping_state (MAP_ARM);
17379 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17387 check_it_blocks_finished (void)
17392 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17393 if (seg_info (sect)->tc_segment_info_data.current_it.state
17394 == MANUAL_IT_BLOCK)
17396 as_warn (_("section '%s' finished with an open IT block."),
17400 if (now_it.state == MANUAL_IT_BLOCK)
17401 as_warn (_("file finished with an open IT block."));
17405 /* Various frobbings of labels and their addresses. */
17408 arm_start_line_hook (void)
17410 last_label_seen = NULL;
17414 arm_frob_label (symbolS * sym)
17416 last_label_seen = sym;
17418 ARM_SET_THUMB (sym, thumb_mode);
17420 #if defined OBJ_COFF || defined OBJ_ELF
17421 ARM_SET_INTERWORK (sym, support_interwork);
17424 force_automatic_it_block_close ();
17426 /* Note - do not allow local symbols (.Lxxx) to be labelled
17427 as Thumb functions. This is because these labels, whilst
17428 they exist inside Thumb code, are not the entry points for
17429 possible ARM->Thumb calls. Also, these labels can be used
17430 as part of a computed goto or switch statement. eg gcc
17431 can generate code that looks like this:
17433 ldr r2, [pc, .Laaa]
17443 The first instruction loads the address of the jump table.
17444 The second instruction converts a table index into a byte offset.
17445 The third instruction gets the jump address out of the table.
17446 The fourth instruction performs the jump.
17448 If the address stored at .Laaa is that of a symbol which has the
17449 Thumb_Func bit set, then the linker will arrange for this address
17450 to have the bottom bit set, which in turn would mean that the
17451 address computation performed by the third instruction would end
17452 up with the bottom bit set. Since the ARM is capable of unaligned
17453 word loads, the instruction would then load the incorrect address
17454 out of the jump table, and chaos would ensue. */
17455 if (label_is_thumb_function_name
17456 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17457 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
17459 /* When the address of a Thumb function is taken the bottom
17460 bit of that address should be set. This will allow
17461 interworking between Arm and Thumb functions to work
17464 THUMB_SET_FUNC (sym, 1);
17466 label_is_thumb_function_name = FALSE;
17469 dwarf2_emit_label (sym);
17473 arm_data_in_code (void)
17475 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
17477 *input_line_pointer = '/';
17478 input_line_pointer += 5;
17479 *input_line_pointer = 0;
17487 arm_canonicalize_symbol_name (char * name)
17491 if (thumb_mode && (len = strlen (name)) > 5
17492 && streq (name + len - 5, "/data"))
17493 *(name + len - 5) = 0;
17498 /* Table of all register names defined by default. The user can
17499 define additional names with .req. Note that all register names
17500 should appear in both upper and lowercase variants. Some registers
17501 also have mixed-case names. */
17503 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17504 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17505 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17506 #define REGSET(p,t) \
17507 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17508 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17509 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17510 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17511 #define REGSETH(p,t) \
17512 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17513 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17514 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17515 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17516 #define REGSET2(p,t) \
17517 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17518 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17519 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17520 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17521 #define SPLRBANK(base,bank,t) \
17522 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17523 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17524 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17525 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17526 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17527 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17529 static const struct reg_entry reg_names[] =
17531 /* ARM integer registers. */
17532 REGSET(r, RN), REGSET(R, RN),
17534 /* ATPCS synonyms. */
17535 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17536 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17537 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
17539 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17540 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17541 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
17543 /* Well-known aliases. */
17544 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17545 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17547 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17548 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17550 /* Coprocessor numbers. */
17551 REGSET(p, CP), REGSET(P, CP),
17553 /* Coprocessor register numbers. The "cr" variants are for backward
17555 REGSET(c, CN), REGSET(C, CN),
17556 REGSET(cr, CN), REGSET(CR, CN),
17558 /* ARM banked registers. */
17559 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17560 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17561 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17562 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17563 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17564 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17565 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17567 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17568 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17569 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17570 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17571 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
17572 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
17573 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17574 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17576 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17577 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17578 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17579 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17580 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17581 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17582 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
17583 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
17584 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17586 /* FPA registers. */
17587 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17588 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17590 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17591 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17593 /* VFP SP registers. */
17594 REGSET(s,VFS), REGSET(S,VFS),
17595 REGSETH(s,VFS), REGSETH(S,VFS),
17597 /* VFP DP Registers. */
17598 REGSET(d,VFD), REGSET(D,VFD),
17599 /* Extra Neon DP registers. */
17600 REGSETH(d,VFD), REGSETH(D,VFD),
17602 /* Neon QP registers. */
17603 REGSET2(q,NQ), REGSET2(Q,NQ),
17605 /* VFP control registers. */
17606 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17607 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
17608 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17609 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17610 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17611 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
17613 /* Maverick DSP coprocessor registers. */
17614 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17615 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17617 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17618 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17619 REGDEF(dspsc,0,DSPSC),
17621 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17622 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17623 REGDEF(DSPSC,0,DSPSC),
17625 /* iWMMXt data registers - p0, c0-15. */
17626 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17628 /* iWMMXt control registers - p1, c0-3. */
17629 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17630 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17631 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17632 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17634 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17635 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17636 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17637 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17638 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17640 /* XScale accumulator registers. */
17641 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17647 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17648 within psr_required_here. */
17649 static const struct asm_psr psrs[] =
17651 /* Backward compatibility notation. Note that "all" is no longer
17652 truly all possible PSR bits. */
17653 {"all", PSR_c | PSR_f},
17657 /* Individual flags. */
17663 /* Combinations of flags. */
17664 {"fs", PSR_f | PSR_s},
17665 {"fx", PSR_f | PSR_x},
17666 {"fc", PSR_f | PSR_c},
17667 {"sf", PSR_s | PSR_f},
17668 {"sx", PSR_s | PSR_x},
17669 {"sc", PSR_s | PSR_c},
17670 {"xf", PSR_x | PSR_f},
17671 {"xs", PSR_x | PSR_s},
17672 {"xc", PSR_x | PSR_c},
17673 {"cf", PSR_c | PSR_f},
17674 {"cs", PSR_c | PSR_s},
17675 {"cx", PSR_c | PSR_x},
17676 {"fsx", PSR_f | PSR_s | PSR_x},
17677 {"fsc", PSR_f | PSR_s | PSR_c},
17678 {"fxs", PSR_f | PSR_x | PSR_s},
17679 {"fxc", PSR_f | PSR_x | PSR_c},
17680 {"fcs", PSR_f | PSR_c | PSR_s},
17681 {"fcx", PSR_f | PSR_c | PSR_x},
17682 {"sfx", PSR_s | PSR_f | PSR_x},
17683 {"sfc", PSR_s | PSR_f | PSR_c},
17684 {"sxf", PSR_s | PSR_x | PSR_f},
17685 {"sxc", PSR_s | PSR_x | PSR_c},
17686 {"scf", PSR_s | PSR_c | PSR_f},
17687 {"scx", PSR_s | PSR_c | PSR_x},
17688 {"xfs", PSR_x | PSR_f | PSR_s},
17689 {"xfc", PSR_x | PSR_f | PSR_c},
17690 {"xsf", PSR_x | PSR_s | PSR_f},
17691 {"xsc", PSR_x | PSR_s | PSR_c},
17692 {"xcf", PSR_x | PSR_c | PSR_f},
17693 {"xcs", PSR_x | PSR_c | PSR_s},
17694 {"cfs", PSR_c | PSR_f | PSR_s},
17695 {"cfx", PSR_c | PSR_f | PSR_x},
17696 {"csf", PSR_c | PSR_s | PSR_f},
17697 {"csx", PSR_c | PSR_s | PSR_x},
17698 {"cxf", PSR_c | PSR_x | PSR_f},
17699 {"cxs", PSR_c | PSR_x | PSR_s},
17700 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17701 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17702 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17703 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17704 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17705 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17706 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17707 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17708 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17709 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17710 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17711 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17712 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17713 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17714 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17715 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17716 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17717 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17718 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17719 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17720 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17721 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17722 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17723 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17726 /* Table of V7M psr names. */
17727 static const struct asm_psr v7m_psrs[] =
17729 {"apsr", 0 }, {"APSR", 0 },
17730 {"iapsr", 1 }, {"IAPSR", 1 },
17731 {"eapsr", 2 }, {"EAPSR", 2 },
17732 {"psr", 3 }, {"PSR", 3 },
17733 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17734 {"ipsr", 5 }, {"IPSR", 5 },
17735 {"epsr", 6 }, {"EPSR", 6 },
17736 {"iepsr", 7 }, {"IEPSR", 7 },
17737 {"msp", 8 }, {"MSP", 8 },
17738 {"psp", 9 }, {"PSP", 9 },
17739 {"primask", 16}, {"PRIMASK", 16},
17740 {"basepri", 17}, {"BASEPRI", 17},
17741 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17742 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17743 {"faultmask", 19}, {"FAULTMASK", 19},
17744 {"control", 20}, {"CONTROL", 20}
17747 /* Table of all shift-in-operand names. */
17748 static const struct asm_shift_name shift_names [] =
17750 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17751 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17752 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17753 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17754 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17755 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17758 /* Table of all explicit relocation names. */
17760 static struct reloc_entry reloc_names[] =
17762 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17763 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17764 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17765 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17766 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17767 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17768 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17769 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17770 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17771 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17772 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17773 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17774 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17775 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17776 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17777 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17778 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17779 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17783 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17784 static const struct asm_cond conds[] =
17788 {"cs", 0x2}, {"hs", 0x2},
17789 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17803 #define UL_BARRIER(L,U,CODE,FEAT) \
17804 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17805 { U, CODE, ARM_FEATURE (FEAT, 0) }
17807 static struct asm_barrier_opt barrier_opt_names[] =
17809 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17810 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17811 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17812 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17813 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17814 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17815 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17816 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17817 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17818 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17819 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17820 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17821 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17822 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17823 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17824 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
17829 /* Table of ARM-format instructions. */
17831 /* Macros for gluing together operand strings. N.B. In all cases
17832 other than OPS0, the trailing OP_stop comes from default
17833 zero-initialization of the unspecified elements of the array. */
17834 #define OPS0() { OP_stop, }
17835 #define OPS1(a) { OP_##a, }
17836 #define OPS2(a,b) { OP_##a,OP_##b, }
17837 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17838 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17839 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17840 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17842 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17843 This is useful when mixing operands for ARM and THUMB, i.e. using the
17844 MIX_ARM_THUMB_OPERANDS macro.
17845 In order to use these macros, prefix the number of operands with _
17847 #define OPS_1(a) { a, }
17848 #define OPS_2(a,b) { a,b, }
17849 #define OPS_3(a,b,c) { a,b,c, }
17850 #define OPS_4(a,b,c,d) { a,b,c,d, }
17851 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17852 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17854 /* These macros abstract out the exact format of the mnemonic table and
17855 save some repeated characters. */
17857 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17858 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17859 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17860 THUMB_VARIANT, do_##ae, do_##te }
17862 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17863 a T_MNEM_xyz enumerator. */
17864 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17865 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17866 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17867 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17869 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17870 infix after the third character. */
17871 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17872 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17873 THUMB_VARIANT, do_##ae, do_##te }
17874 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17875 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17876 THUMB_VARIANT, do_##ae, do_##te }
17877 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17878 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17879 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17880 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17881 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17882 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17883 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17884 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17886 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17887 field is still 0xE. Many of the Thumb variants can be executed
17888 conditionally, so this is checked separately. */
17889 #define TUE(mnem, op, top, nops, ops, ae, te) \
17890 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17891 THUMB_VARIANT, do_##ae, do_##te }
17893 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
17894 Used by mnemonics that have very minimal differences in the encoding for
17895 ARM and Thumb variants and can be handled in a common function. */
17896 #define TUEc(mnem, op, top, nops, ops, en) \
17897 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17898 THUMB_VARIANT, do_##en, do_##en }
17900 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17901 condition code field. */
17902 #define TUF(mnem, op, top, nops, ops, ae, te) \
17903 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17904 THUMB_VARIANT, do_##ae, do_##te }
17906 /* ARM-only variants of all the above. */
17907 #define CE(mnem, op, nops, ops, ae) \
17908 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17910 #define C3(mnem, op, nops, ops, ae) \
17911 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17913 /* Legacy mnemonics that always have conditional infix after the third
17915 #define CL(mnem, op, nops, ops, ae) \
17916 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17917 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17919 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17920 #define cCE(mnem, op, nops, ops, ae) \
17921 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17923 /* Legacy coprocessor instructions where conditional infix and conditional
17924 suffix are ambiguous. For consistency this includes all FPA instructions,
17925 not just the potentially ambiguous ones. */
17926 #define cCL(mnem, op, nops, ops, ae) \
17927 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17928 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17930 /* Coprocessor, takes either a suffix or a position-3 infix
17931 (for an FPA corner case). */
17932 #define C3E(mnem, op, nops, ops, ae) \
17933 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17934 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17936 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17937 { m1 #m2 m3, OPS##nops ops, \
17938 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17939 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17941 #define CM(m1, m2, op, nops, ops, ae) \
17942 xCM_ (m1, , m2, op, nops, ops, ae), \
17943 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17944 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17945 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17946 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17947 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17948 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17949 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17950 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17951 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17952 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17953 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17954 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17955 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17956 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17957 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17958 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17959 xCM_ (m1, le, m2, op, nops, ops, ae), \
17960 xCM_ (m1, al, m2, op, nops, ops, ae)
17962 #define UE(mnem, op, nops, ops, ae) \
17963 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17965 #define UF(mnem, op, nops, ops, ae) \
17966 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17968 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17969 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17970 use the same encoding function for each. */
17971 #define NUF(mnem, op, nops, ops, enc) \
17972 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17973 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17975 /* Neon data processing, version which indirects through neon_enc_tab for
17976 the various overloaded versions of opcodes. */
17977 #define nUF(mnem, op, nops, ops, enc) \
17978 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17979 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17981 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17983 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17984 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17985 THUMB_VARIANT, do_##enc, do_##enc }
17987 #define NCE(mnem, op, nops, ops, enc) \
17988 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17990 #define NCEF(mnem, op, nops, ops, enc) \
17991 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17993 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17994 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17995 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17996 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17998 #define nCE(mnem, op, nops, ops, enc) \
17999 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18001 #define nCEF(mnem, op, nops, ops, enc) \
18002 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18006 static const struct asm_opcode insns[] =
18008 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18009 #define THUMB_VARIANT & arm_ext_v4t
18010 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
18011 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
18012 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
18013 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
18014 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
18015 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
18016 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
18017 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
18018 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
18019 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
18020 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
18021 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
18022 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
18023 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
18024 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
18025 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
18027 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18028 for setting PSR flag bits. They are obsolete in V6 and do not
18029 have Thumb equivalents. */
18030 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18031 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18032 CL("tstp", 110f000, 2, (RR, SH), cmp),
18033 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18034 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18035 CL("cmpp", 150f000, 2, (RR, SH), cmp),
18036 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18037 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18038 CL("cmnp", 170f000, 2, (RR, SH), cmp),
18040 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
18041 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
18042 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
18043 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
18045 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
18046 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18047 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
18049 OP_ADDRGLDR),ldst, t_ldst),
18050 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18052 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18053 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18054 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18055 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18056 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18057 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18059 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
18060 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
18061 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
18062 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
18065 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
18066 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
18067 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
18068 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
18070 /* Thumb-compatibility pseudo ops. */
18071 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
18072 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
18073 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
18074 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
18075 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
18076 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
18077 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
18078 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
18079 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
18080 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
18081 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
18082 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
18084 /* These may simplify to neg. */
18085 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
18086 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
18088 #undef THUMB_VARIANT
18089 #define THUMB_VARIANT & arm_ext_v6
18091 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
18093 /* V1 instructions with no Thumb analogue prior to V6T2. */
18094 #undef THUMB_VARIANT
18095 #define THUMB_VARIANT & arm_ext_v6t2
18097 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18098 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18099 CL("teqp", 130f000, 2, (RR, SH), cmp),
18101 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18102 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18103 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18104 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18106 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18107 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18109 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18110 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18112 /* V1 instructions with no Thumb analogue at all. */
18113 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
18114 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18116 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18117 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18118 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18119 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18120 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18121 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18122 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18123 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18126 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18127 #undef THUMB_VARIANT
18128 #define THUMB_VARIANT & arm_ext_v4t
18130 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18131 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18133 #undef THUMB_VARIANT
18134 #define THUMB_VARIANT & arm_ext_v6t2
18136 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18137 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18139 /* Generic coprocessor instructions. */
18140 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18141 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18142 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18143 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18144 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18145 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18146 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
18149 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18151 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18152 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18155 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18156 #undef THUMB_VARIANT
18157 #define THUMB_VARIANT & arm_ext_msr
18159 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18160 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
18163 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18164 #undef THUMB_VARIANT
18165 #define THUMB_VARIANT & arm_ext_v6t2
18167 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18168 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18169 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18170 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18171 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18172 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18173 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18174 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18177 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18178 #undef THUMB_VARIANT
18179 #define THUMB_VARIANT & arm_ext_v4t
18181 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18182 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18183 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18184 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18185 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18186 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18189 #define ARM_VARIANT & arm_ext_v4t_5
18191 /* ARM Architecture 4T. */
18192 /* Note: bx (and blx) are required on V5, even if the processor does
18193 not support Thumb. */
18194 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
18197 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18198 #undef THUMB_VARIANT
18199 #define THUMB_VARIANT & arm_ext_v5t
18201 /* Note: blx has 2 variants; the .value coded here is for
18202 BLX(2). Only this variant has conditional execution. */
18203 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18204 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
18206 #undef THUMB_VARIANT
18207 #define THUMB_VARIANT & arm_ext_v6t2
18209 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18210 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18211 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18212 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18213 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18214 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18215 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18216 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18219 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18220 #undef THUMB_VARIANT
18221 #define THUMB_VARIANT & arm_ext_v5exp
18223 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18224 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18225 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18226 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18228 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18229 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18231 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18232 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18233 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18234 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18236 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18237 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18238 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18239 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18241 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18242 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18244 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18245 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18246 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18247 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18250 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18251 #undef THUMB_VARIANT
18252 #define THUMB_VARIANT & arm_ext_v6t2
18254 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
18255 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18257 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18258 ADDRGLDRS), ldrd, t_ldstd),
18260 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18261 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18264 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18266 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
18269 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18270 #undef THUMB_VARIANT
18271 #define THUMB_VARIANT & arm_ext_v6
18273 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18274 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18275 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18276 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18277 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18278 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18279 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18280 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18281 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18282 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
18284 #undef THUMB_VARIANT
18285 #define THUMB_VARIANT & arm_ext_v6t2
18287 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18288 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18290 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18291 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18293 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18294 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
18296 /* ARM V6 not included in V7M. */
18297 #undef THUMB_VARIANT
18298 #define THUMB_VARIANT & arm_ext_v6_notm
18299 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18300 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18301 UF(rfeib, 9900a00, 1, (RRw), rfe),
18302 UF(rfeda, 8100a00, 1, (RRw), rfe),
18303 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18304 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18305 UF(rfefa, 8100a00, 1, (RRw), rfe),
18306 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18307 UF(rfeed, 9900a00, 1, (RRw), rfe),
18308 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18309 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18310 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18311 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
18312 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
18313 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
18314 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
18315 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18316 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18318 /* ARM V6 not included in V7M (eg. integer SIMD). */
18319 #undef THUMB_VARIANT
18320 #define THUMB_VARIANT & arm_ext_v6_dsp
18321 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18322 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18323 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18324 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18325 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18326 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18327 /* Old name for QASX. */
18328 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18329 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18330 /* Old name for QSAX. */
18331 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18332 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18333 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18334 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18335 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18336 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18337 /* Old name for SASX. */
18338 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18339 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18340 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18341 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18342 /* Old name for SHASX. */
18343 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18344 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18345 /* Old name for SHSAX. */
18346 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18347 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18348 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18349 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18350 /* Old name for SSAX. */
18351 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18352 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18353 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18354 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18355 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18356 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18357 /* Old name for UASX. */
18358 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18359 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18360 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18361 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18362 /* Old name for UHASX. */
18363 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18364 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18365 /* Old name for UHSAX. */
18366 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18367 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18368 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18369 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18370 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18371 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18372 /* Old name for UQASX. */
18373 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18374 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18375 /* Old name for UQSAX. */
18376 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18377 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18378 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18379 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18380 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18381 /* Old name for USAX. */
18382 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18383 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18384 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18385 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18386 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18387 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18388 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18389 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18390 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18391 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18392 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18393 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18394 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18395 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18396 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18397 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18398 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18399 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18400 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18401 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18402 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18403 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18404 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18405 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18406 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18407 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18408 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18409 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18410 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18411 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18412 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18413 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18414 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18415 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
18418 #define ARM_VARIANT & arm_ext_v6k
18419 #undef THUMB_VARIANT
18420 #define THUMB_VARIANT & arm_ext_v6k
18422 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18423 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18424 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18425 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
18427 #undef THUMB_VARIANT
18428 #define THUMB_VARIANT & arm_ext_v6_notm
18429 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18431 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18432 RRnpcb), strexd, t_strexd),
18434 #undef THUMB_VARIANT
18435 #define THUMB_VARIANT & arm_ext_v6t2
18436 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18438 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18440 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18442 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18444 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
18447 #define ARM_VARIANT & arm_ext_sec
18448 #undef THUMB_VARIANT
18449 #define THUMB_VARIANT & arm_ext_sec
18451 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
18454 #define ARM_VARIANT & arm_ext_virt
18455 #undef THUMB_VARIANT
18456 #define THUMB_VARIANT & arm_ext_virt
18458 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18459 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18462 #define ARM_VARIANT & arm_ext_v6t2
18463 #undef THUMB_VARIANT
18464 #define THUMB_VARIANT & arm_ext_v6t2
18466 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18467 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18468 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18469 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18471 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18472 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18473 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18474 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
18476 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18477 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18478 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18479 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18481 /* Thumb-only instructions. */
18483 #define ARM_VARIANT NULL
18484 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18485 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
18487 /* ARM does not really have an IT instruction, so always allow it.
18488 The opcode is copied from Thumb in order to allow warnings in
18489 -mimplicit-it=[never | arm] modes. */
18491 #define ARM_VARIANT & arm_ext_v1
18493 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18494 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18495 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18496 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18497 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18498 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18499 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18500 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18501 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18502 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18503 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18504 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18505 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18506 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18507 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
18508 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18509 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18510 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
18512 /* Thumb2 only instructions. */
18514 #define ARM_VARIANT NULL
18516 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18517 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18518 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18519 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18520 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18521 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
18523 /* Hardware division instructions. */
18525 #define ARM_VARIANT & arm_ext_adiv
18526 #undef THUMB_VARIANT
18527 #define THUMB_VARIANT & arm_ext_div
18529 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18530 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
18532 /* ARM V6M/V7 instructions. */
18534 #define ARM_VARIANT & arm_ext_barrier
18535 #undef THUMB_VARIANT
18536 #define THUMB_VARIANT & arm_ext_barrier
18538 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
18539 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
18540 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
18542 /* ARM V7 instructions. */
18544 #define ARM_VARIANT & arm_ext_v7
18545 #undef THUMB_VARIANT
18546 #define THUMB_VARIANT & arm_ext_v7
18548 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18549 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
18552 #define ARM_VARIANT & arm_ext_mp
18553 #undef THUMB_VARIANT
18554 #define THUMB_VARIANT & arm_ext_mp
18556 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18558 /* AArchv8 instructions. */
18560 #define ARM_VARIANT & arm_ext_v8
18561 #undef THUMB_VARIANT
18562 #define THUMB_VARIANT & arm_ext_v8
18564 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
18565 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
18566 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18567 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
18569 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18570 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18571 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18573 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
18575 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18577 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18579 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18580 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18581 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18582 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18583 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18584 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18586 /* ARMv8 T32 only. */
18588 #define ARM_VARIANT NULL
18589 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18590 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18591 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18593 /* FP for ARMv8. */
18595 #define ARM_VARIANT & fpu_vfp_ext_armv8
18596 #undef THUMB_VARIANT
18597 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18599 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18600 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18601 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18602 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
18603 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18604 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18605 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
18606 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
18607 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
18608 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
18609 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
18610 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
18611 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
18612 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
18613 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
18614 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
18615 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
18617 /* Crypto v1 extensions. */
18619 #define ARM_VARIANT & fpu_crypto_ext_armv8
18620 #undef THUMB_VARIANT
18621 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18623 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
18624 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
18625 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
18626 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
18627 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
18628 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
18629 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
18630 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
18631 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
18632 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
18633 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
18634 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
18635 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
18636 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
18639 #define ARM_VARIANT & crc_ext_armv8
18640 #undef THUMB_VARIANT
18641 #define THUMB_VARIANT & crc_ext_armv8
18642 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
18643 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
18644 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
18645 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
18646 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
18647 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
18650 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18651 #undef THUMB_VARIANT
18652 #define THUMB_VARIANT NULL
18654 cCE("wfs", e200110, 1, (RR), rd),
18655 cCE("rfs", e300110, 1, (RR), rd),
18656 cCE("wfc", e400110, 1, (RR), rd),
18657 cCE("rfc", e500110, 1, (RR), rd),
18659 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18660 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18661 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18662 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18664 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18665 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18666 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18667 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18669 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18670 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18671 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18672 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18673 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18674 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18675 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18676 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18677 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18678 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18679 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18680 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18682 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18683 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18684 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18685 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18686 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18687 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18688 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18689 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18690 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18691 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18692 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18693 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18695 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18696 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18697 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18698 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18699 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18700 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18701 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18702 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18703 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18704 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18705 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18706 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18708 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18709 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18710 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18711 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18712 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18713 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18714 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18715 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18716 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18717 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18718 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18719 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18721 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18722 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18723 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18724 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18725 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18726 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18727 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18728 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18729 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18730 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18731 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18732 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18734 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18735 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18736 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18737 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18738 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18739 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18740 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18741 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18742 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18743 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18744 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18745 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18747 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18748 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18749 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18750 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18751 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18752 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18753 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18754 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18755 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18756 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18757 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18758 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18760 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18761 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18762 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18763 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18764 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18765 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18766 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18767 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18768 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18769 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18770 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18771 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18773 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18774 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18775 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18776 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18777 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18778 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18779 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18780 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18781 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18782 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18783 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18784 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18786 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18787 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18788 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18789 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18790 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18791 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18792 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18793 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18794 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18795 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18796 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18797 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18799 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18800 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18801 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18802 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18803 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18804 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18805 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18806 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18807 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18808 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18809 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18810 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18812 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18813 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18814 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18815 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18816 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18817 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18818 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18819 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18820 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18821 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18822 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18823 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18825 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18826 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18827 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18828 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18829 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18830 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18831 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18832 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18833 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18834 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18835 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18836 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18838 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18839 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18840 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18841 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18842 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18843 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18844 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18845 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18846 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18847 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18848 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18849 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18851 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18852 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18853 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18854 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18855 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18856 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18857 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18858 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18859 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18860 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18861 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18862 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18864 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18865 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18866 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18867 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18868 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18869 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18870 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18871 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18872 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18873 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18874 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18875 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18877 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18878 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18879 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18880 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18881 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18882 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18883 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18884 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18885 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18886 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18887 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18888 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18890 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18891 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18892 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18893 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18894 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18895 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18896 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18897 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18898 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18899 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18900 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18901 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18903 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18904 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18905 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18906 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18907 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18908 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18909 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18910 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18911 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18912 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18913 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18914 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18916 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18917 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18918 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18919 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18920 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18921 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18922 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18923 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18924 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18925 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18926 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18927 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18929 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18930 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18931 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18932 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18933 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18934 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18935 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18936 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18937 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18938 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18939 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18940 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18942 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18943 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18944 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18945 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18946 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18947 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18948 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18949 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18950 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18951 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18952 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18953 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18955 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18956 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18957 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18958 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18959 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18960 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18961 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18962 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18963 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18964 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18965 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18966 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18968 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18969 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18970 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18971 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18972 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18973 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18974 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18975 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18976 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18977 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18978 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18979 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18981 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18982 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18983 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18984 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18985 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18986 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18987 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18988 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18989 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18990 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18991 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18992 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18994 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18995 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18996 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18997 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18998 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18999 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19000 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19001 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19002 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
19003 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
19004 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
19005 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
19007 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19008 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19009 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19010 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19011 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19012 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19013 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19014 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19015 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19016 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19017 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19018 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19020 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19021 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19022 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19023 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19024 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19025 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19026 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19027 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19028 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19029 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19030 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19031 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19033 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19034 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19035 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19036 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19037 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19038 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19039 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19040 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19041 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19042 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19043 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19044 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19046 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
19047 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
19048 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
19049 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
19051 cCL("flts", e000110, 2, (RF, RR), rn_rd),
19052 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
19053 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
19054 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
19055 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
19056 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
19057 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
19058 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
19059 cCL("flte", e080110, 2, (RF, RR), rn_rd),
19060 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
19061 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
19062 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
19064 /* The implementation of the FIX instruction is broken on some
19065 assemblers, in that it accepts a precision specifier as well as a
19066 rounding specifier, despite the fact that this is meaningless.
19067 To be more compatible, we accept it as well, though of course it
19068 does not set any bits. */
19069 cCE("fix", e100110, 2, (RR, RF), rd_rm),
19070 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
19071 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
19072 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
19073 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
19074 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
19075 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
19076 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
19077 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
19078 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
19079 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
19080 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
19081 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
19083 /* Instructions that were new with the real FPA, call them V2. */
19085 #define ARM_VARIANT & fpu_fpa_ext_v2
19087 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19088 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19089 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19090 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19091 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19092 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19095 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19097 /* Moves and type conversions. */
19098 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
19099 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
19100 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
19101 cCE("fmstat", ef1fa10, 0, (), noargs),
19102 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
19103 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
19104 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
19105 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
19106 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
19107 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19108 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
19109 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19110 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
19111 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
19113 /* Memory operations. */
19114 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19115 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19116 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19117 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19118 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19119 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19120 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19121 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19122 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19123 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19124 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19125 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19126 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19127 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19128 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19129 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19130 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19131 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19133 /* Monadic operations. */
19134 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19135 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19136 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
19138 /* Dyadic operations. */
19139 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19140 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19141 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19142 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19143 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19144 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19145 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19146 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19147 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19150 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19151 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19152 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19153 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
19155 /* Double precision load/store are still present on single precision
19156 implementations. */
19157 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19158 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19159 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19160 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19161 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19162 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19163 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19164 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19165 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19166 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19169 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19171 /* Moves and type conversions. */
19172 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19173 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19174 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19175 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19176 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19177 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19178 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19179 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19180 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19181 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19182 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19183 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19184 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19186 /* Monadic operations. */
19187 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19188 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19189 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19191 /* Dyadic operations. */
19192 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19193 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19194 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19195 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19196 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19197 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19198 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19199 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19200 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19203 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19204 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19205 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19206 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
19209 #define ARM_VARIANT & fpu_vfp_ext_v2
19211 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19212 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19213 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19214 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
19216 /* Instructions which may belong to either the Neon or VFP instruction sets.
19217 Individual encoder functions perform additional architecture checks. */
19219 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19220 #undef THUMB_VARIANT
19221 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19223 /* These mnemonics are unique to VFP. */
19224 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19225 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
19226 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19227 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19228 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19229 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19230 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19231 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19232 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19233 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19235 /* Mnemonics shared by Neon and VFP. */
19236 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19237 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19238 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19240 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19241 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19243 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19244 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19246 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19247 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19248 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19249 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19250 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19251 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19252 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19253 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19255 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
19256 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
19257 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19258 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
19261 /* NOTE: All VMOV encoding is special-cased! */
19262 NCE(vmov, 0, 1, (VMOV), neon_mov),
19263 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19265 #undef THUMB_VARIANT
19266 #define THUMB_VARIANT & fpu_neon_ext_v1
19268 #define ARM_VARIANT & fpu_neon_ext_v1
19270 /* Data processing with three registers of the same length. */
19271 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19272 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19273 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19274 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19275 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19276 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19277 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19278 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19279 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19280 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19281 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19282 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19283 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19284 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19285 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19286 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19287 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19288 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19289 /* If not immediate, fall back to neon_dyadic_i64_su.
19290 shl_imm should accept I8 I16 I32 I64,
19291 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19292 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19293 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19294 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19295 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
19296 /* Logic ops, types optional & ignored. */
19297 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19298 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19299 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19300 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19301 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19302 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19303 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19304 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19305 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19306 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
19307 /* Bitfield ops, untyped. */
19308 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19309 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19310 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19311 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19312 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19313 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19314 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19315 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19316 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19317 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19318 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19319 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19320 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19321 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19322 back to neon_dyadic_if_su. */
19323 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19324 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19325 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19326 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19327 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19328 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19329 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19330 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19331 /* Comparison. Type I8 I16 I32 F32. */
19332 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19333 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
19334 /* As above, D registers only. */
19335 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19336 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19337 /* Int and float variants, signedness unimportant. */
19338 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19339 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19340 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
19341 /* Add/sub take types I8 I16 I32 I64 F32. */
19342 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19343 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19344 /* vtst takes sizes 8, 16, 32. */
19345 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19346 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19347 /* VMUL takes I8 I16 I32 F32 P8. */
19348 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
19349 /* VQD{R}MULH takes S16 S32. */
19350 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19351 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19352 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19353 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19354 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19355 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19356 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19357 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19358 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19359 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19360 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19361 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19362 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19363 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19364 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19365 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19367 /* Two address, int/float. Types S8 S16 S32 F32. */
19368 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
19369 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19371 /* Data processing with two registers and a shift amount. */
19372 /* Right shifts, and variants with rounding.
19373 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19374 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19375 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19376 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19377 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19378 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19379 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19380 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19381 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19382 /* Shift and insert. Sizes accepted 8 16 32 64. */
19383 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19384 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19385 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19386 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19387 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19388 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19389 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19390 /* Right shift immediate, saturating & narrowing, with rounding variants.
19391 Types accepted S16 S32 S64 U16 U32 U64. */
19392 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19393 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19394 /* As above, unsigned. Types accepted S16 S32 S64. */
19395 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19396 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19397 /* Right shift narrowing. Types accepted I16 I32 I64. */
19398 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19399 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19400 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19401 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
19402 /* CVT with optional immediate for fixed-point variant. */
19403 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
19405 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19406 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
19408 /* Data processing, three registers of different lengths. */
19409 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19410 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19411 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19412 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19413 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19414 /* If not scalar, fall back to neon_dyadic_long.
19415 Vector types as above, scalar types S16 S32 U16 U32. */
19416 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19417 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19418 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19419 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19420 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19421 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19422 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19423 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19424 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19425 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19426 /* Saturating doubling multiplies. Types S16 S32. */
19427 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19428 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19429 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19430 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19431 S16 S32 U16 U32. */
19432 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
19434 /* Extract. Size 8. */
19435 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19436 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
19438 /* Two registers, miscellaneous. */
19439 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19440 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19441 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19442 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19443 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19444 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19445 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19446 /* Vector replicate. Sizes 8 16 32. */
19447 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19448 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
19449 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19450 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19451 /* VMOVN. Types I16 I32 I64. */
19452 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
19453 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19454 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
19455 /* VQMOVUN. Types S16 S32 S64. */
19456 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
19457 /* VZIP / VUZP. Sizes 8 16 32. */
19458 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19459 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19460 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19461 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19462 /* VQABS / VQNEG. Types S8 S16 S32. */
19463 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19464 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19465 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19466 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19467 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19468 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19469 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19470 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19471 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19472 /* Reciprocal estimates. Types U32 F32. */
19473 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19474 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19475 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19476 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19477 /* VCLS. Types S8 S16 S32. */
19478 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19479 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19480 /* VCLZ. Types I8 I16 I32. */
19481 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19482 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19483 /* VCNT. Size 8. */
19484 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19485 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19486 /* Two address, untyped. */
19487 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19488 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19489 /* VTRN. Sizes 8 16 32. */
19490 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19491 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
19493 /* Table lookup. Size 8. */
19494 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19495 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19497 #undef THUMB_VARIANT
19498 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19500 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19502 /* Neon element/structure load/store. */
19503 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19504 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19505 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19506 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19507 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19508 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19509 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19510 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19512 #undef THUMB_VARIANT
19513 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
19515 #define ARM_VARIANT & fpu_vfp_ext_v3xd
19516 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19517 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19518 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19519 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19520 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19521 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19522 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19523 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19524 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19526 #undef THUMB_VARIANT
19527 #define THUMB_VARIANT & fpu_vfp_ext_v3
19529 #define ARM_VARIANT & fpu_vfp_ext_v3
19531 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
19532 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19533 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19534 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19535 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19536 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19537 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19538 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19539 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19542 #define ARM_VARIANT & fpu_vfp_ext_fma
19543 #undef THUMB_VARIANT
19544 #define THUMB_VARIANT & fpu_vfp_ext_fma
19545 /* Mnemonics shared by Neon and VFP. These are included in the
19546 VFP FMA variant; NEON and VFP FMA always includes the NEON
19547 FMA instructions. */
19548 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19549 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19550 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19551 the v form should always be used. */
19552 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19553 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19554 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19555 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19556 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19557 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19559 #undef THUMB_VARIANT
19561 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19563 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19564 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19565 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19566 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19567 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19568 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19569 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19570 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
19573 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19575 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19576 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19577 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19578 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19579 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19580 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19581 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19582 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19583 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19584 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19585 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19586 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19587 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19588 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19589 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19590 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19591 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19592 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19593 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19594 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19595 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19596 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19597 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19598 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19599 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19600 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19601 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
19602 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
19603 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
19604 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19605 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19606 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19607 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19608 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19609 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19610 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19611 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19612 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19613 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19614 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19615 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19616 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19617 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19618 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19619 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19620 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19621 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19622 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19623 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19624 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19625 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19626 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19627 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19628 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19629 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19630 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19631 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19632 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19633 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19634 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19635 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19636 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19637 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19638 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19639 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19640 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19641 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19642 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19643 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19644 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19645 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19646 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19647 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19648 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19649 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19650 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19651 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19652 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19653 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19654 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19655 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19656 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19657 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19658 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19659 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19660 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19661 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19662 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19663 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19664 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19665 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19666 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19667 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19668 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19669 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19670 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19671 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19672 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19673 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19674 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19675 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19676 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19677 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19678 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19679 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19680 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19681 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19682 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19683 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19684 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19685 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19686 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19687 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19688 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19689 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19690 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19691 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19692 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19693 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19694 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19695 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19696 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19697 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19698 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19699 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19700 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19701 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19702 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19703 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19704 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19705 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19706 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19707 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19708 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19709 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19710 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19711 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19712 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19713 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19714 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19715 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19716 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19717 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19718 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19719 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19720 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19721 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19722 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19723 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19724 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19725 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19726 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19727 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19728 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19729 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19730 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19731 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19732 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19733 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19734 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19735 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19736 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
19739 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19741 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19742 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19743 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19744 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19745 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19746 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19747 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19748 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19749 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19750 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19751 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19752 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19753 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19754 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19755 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19756 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19757 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19758 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19759 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19760 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19761 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19762 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19763 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19764 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19765 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19766 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19767 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19768 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19769 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19770 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19771 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19772 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19773 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19774 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19775 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19776 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19777 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19778 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19779 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19780 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19781 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19782 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19783 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19784 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19785 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19786 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19787 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19788 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19789 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19790 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19791 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19792 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19793 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19794 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19795 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19796 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19797 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19800 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19802 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19803 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19804 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19805 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19806 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19807 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19808 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19809 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19810 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19811 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19812 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19813 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19814 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19815 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19816 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
19817 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
19818 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
19819 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
19820 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
19821 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
19822 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
19823 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
19824 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
19825 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
19826 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19827 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19828 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19829 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19830 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19831 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
19832 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19833 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19834 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19835 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19836 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
19837 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
19838 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
19839 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
19840 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
19841 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
19842 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19843 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19844 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
19845 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
19846 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19847 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19848 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19849 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19850 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19851 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19852 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19853 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19854 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19855 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19856 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19857 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19858 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19859 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19860 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19861 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19862 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19863 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19864 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19865 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19866 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19867 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19868 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19869 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19870 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19871 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19872 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19873 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19874 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19875 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19876 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19877 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19880 #undef THUMB_VARIANT
19906 /* MD interface: bits in the object file. */
19908 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19909 for use in the a.out file, and stores them in the array pointed to by buf.
19910 This knows about the endian-ness of the target machine and does
19911 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19912 2 (short) and 4 (long) Floating numbers are put out as a series of
19913 LITTLENUMS (shorts, here at least). */
19916 md_number_to_chars (char * buf, valueT val, int n)
19918 if (target_big_endian)
19919 number_to_chars_bigendian (buf, val, n);
19921 number_to_chars_littleendian (buf, val, n);
19925 md_chars_to_number (char * buf, int n)
19928 unsigned char * where = (unsigned char *) buf;
19930 if (target_big_endian)
19935 result |= (*where++ & 255);
19943 result |= (where[n] & 255);
19950 /* MD interface: Sections. */
19952 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19953 that an rs_machine_dependent frag may reach. */
19956 arm_frag_max_var (fragS *fragp)
19958 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19959 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19961 Note that we generate relaxable instructions even for cases that don't
19962 really need it, like an immediate that's a trivial constant. So we're
19963 overestimating the instruction size for some of those cases. Rather
19964 than putting more intelligence here, it would probably be better to
19965 avoid generating a relaxation frag in the first place when it can be
19966 determined up front that a short instruction will suffice. */
19968 gas_assert (fragp->fr_type == rs_machine_dependent);
19972 /* Estimate the size of a frag before relaxing. Assume everything fits in
19976 md_estimate_size_before_relax (fragS * fragp,
19977 segT segtype ATTRIBUTE_UNUSED)
19983 /* Convert a machine dependent frag. */
19986 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19988 unsigned long insn;
19989 unsigned long old_op;
19997 buf = fragp->fr_literal + fragp->fr_fix;
19999 old_op = bfd_get_16(abfd, buf);
20000 if (fragp->fr_symbol)
20002 exp.X_op = O_symbol;
20003 exp.X_add_symbol = fragp->fr_symbol;
20007 exp.X_op = O_constant;
20009 exp.X_add_number = fragp->fr_offset;
20010 opcode = fragp->fr_subtype;
20013 case T_MNEM_ldr_pc:
20014 case T_MNEM_ldr_pc2:
20015 case T_MNEM_ldr_sp:
20016 case T_MNEM_str_sp:
20023 if (fragp->fr_var == 4)
20025 insn = THUMB_OP32 (opcode);
20026 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
20028 insn |= (old_op & 0x700) << 4;
20032 insn |= (old_op & 7) << 12;
20033 insn |= (old_op & 0x38) << 13;
20035 insn |= 0x00000c00;
20036 put_thumb32_insn (buf, insn);
20037 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
20041 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
20043 pc_rel = (opcode == T_MNEM_ldr_pc2);
20046 if (fragp->fr_var == 4)
20048 insn = THUMB_OP32 (opcode);
20049 insn |= (old_op & 0xf0) << 4;
20050 put_thumb32_insn (buf, insn);
20051 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
20055 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20056 exp.X_add_number -= 4;
20064 if (fragp->fr_var == 4)
20066 int r0off = (opcode == T_MNEM_mov
20067 || opcode == T_MNEM_movs) ? 0 : 8;
20068 insn = THUMB_OP32 (opcode);
20069 insn = (insn & 0xe1ffffff) | 0x10000000;
20070 insn |= (old_op & 0x700) << r0off;
20071 put_thumb32_insn (buf, insn);
20072 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20076 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
20081 if (fragp->fr_var == 4)
20083 insn = THUMB_OP32(opcode);
20084 put_thumb32_insn (buf, insn);
20085 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
20088 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
20092 if (fragp->fr_var == 4)
20094 insn = THUMB_OP32(opcode);
20095 insn |= (old_op & 0xf00) << 14;
20096 put_thumb32_insn (buf, insn);
20097 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
20100 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
20103 case T_MNEM_add_sp:
20104 case T_MNEM_add_pc:
20105 case T_MNEM_inc_sp:
20106 case T_MNEM_dec_sp:
20107 if (fragp->fr_var == 4)
20109 /* ??? Choose between add and addw. */
20110 insn = THUMB_OP32 (opcode);
20111 insn |= (old_op & 0xf0) << 4;
20112 put_thumb32_insn (buf, insn);
20113 if (opcode == T_MNEM_add_pc)
20114 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20116 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20119 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20127 if (fragp->fr_var == 4)
20129 insn = THUMB_OP32 (opcode);
20130 insn |= (old_op & 0xf0) << 4;
20131 insn |= (old_op & 0xf) << 16;
20132 put_thumb32_insn (buf, insn);
20133 if (insn & (1 << 20))
20134 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20136 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20139 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20145 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
20146 (enum bfd_reloc_code_real) reloc_type);
20147 fixp->fx_file = fragp->fr_file;
20148 fixp->fx_line = fragp->fr_line;
20149 fragp->fr_fix += fragp->fr_var;
20152 /* Return the size of a relaxable immediate operand instruction.
20153 SHIFT and SIZE specify the form of the allowable immediate. */
20155 relax_immediate (fragS *fragp, int size, int shift)
20161 /* ??? Should be able to do better than this. */
20162 if (fragp->fr_symbol)
20165 low = (1 << shift) - 1;
20166 mask = (1 << (shift + size)) - (1 << shift);
20167 offset = fragp->fr_offset;
20168 /* Force misaligned offsets to 32-bit variant. */
20171 if (offset & ~mask)
20176 /* Get the address of a symbol during relaxation. */
20178 relaxed_symbol_addr (fragS *fragp, long stretch)
20184 sym = fragp->fr_symbol;
20185 sym_frag = symbol_get_frag (sym);
20186 know (S_GET_SEGMENT (sym) != absolute_section
20187 || sym_frag == &zero_address_frag);
20188 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20190 /* If frag has yet to be reached on this pass, assume it will
20191 move by STRETCH just as we did. If this is not so, it will
20192 be because some frag between grows, and that will force
20196 && sym_frag->relax_marker != fragp->relax_marker)
20200 /* Adjust stretch for any alignment frag. Note that if have
20201 been expanding the earlier code, the symbol may be
20202 defined in what appears to be an earlier frag. FIXME:
20203 This doesn't handle the fr_subtype field, which specifies
20204 a maximum number of bytes to skip when doing an
20206 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20208 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20211 stretch = - ((- stretch)
20212 & ~ ((1 << (int) f->fr_offset) - 1));
20214 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20226 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20229 relax_adr (fragS *fragp, asection *sec, long stretch)
20234 /* Assume worst case for symbols not known to be in the same section. */
20235 if (fragp->fr_symbol == NULL
20236 || !S_IS_DEFINED (fragp->fr_symbol)
20237 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20238 || S_IS_WEAK (fragp->fr_symbol))
20241 val = relaxed_symbol_addr (fragp, stretch);
20242 addr = fragp->fr_address + fragp->fr_fix;
20243 addr = (addr + 4) & ~3;
20244 /* Force misaligned targets to 32-bit variant. */
20248 if (val < 0 || val > 1020)
20253 /* Return the size of a relaxable add/sub immediate instruction. */
20255 relax_addsub (fragS *fragp, asection *sec)
20260 buf = fragp->fr_literal + fragp->fr_fix;
20261 op = bfd_get_16(sec->owner, buf);
20262 if ((op & 0xf) == ((op >> 4) & 0xf))
20263 return relax_immediate (fragp, 8, 0);
20265 return relax_immediate (fragp, 3, 0);
20268 /* Return TRUE iff the definition of symbol S could be pre-empted
20269 (overridden) at link or load time. */
20271 symbol_preemptible (symbolS *s)
20273 /* Weak symbols can always be pre-empted. */
20277 /* Non-global symbols cannot be pre-empted. */
20278 if (! S_IS_EXTERNAL (s))
20282 /* In ELF, a global symbol can be marked protected, or private. In that
20283 case it can't be pre-empted (other definitions in the same link unit
20284 would violate the ODR). */
20285 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
20289 /* Other global symbols might be pre-empted. */
20293 /* Return the size of a relaxable branch instruction. BITS is the
20294 size of the offset field in the narrow instruction. */
20297 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
20303 /* Assume worst case for symbols not known to be in the same section. */
20304 if (!S_IS_DEFINED (fragp->fr_symbol)
20305 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20306 || S_IS_WEAK (fragp->fr_symbol))
20310 /* A branch to a function in ARM state will require interworking. */
20311 if (S_IS_DEFINED (fragp->fr_symbol)
20312 && ARM_IS_FUNC (fragp->fr_symbol))
20316 if (symbol_preemptible (fragp->fr_symbol))
20319 val = relaxed_symbol_addr (fragp, stretch);
20320 addr = fragp->fr_address + fragp->fr_fix + 4;
20323 /* Offset is a signed value *2 */
20325 if (val >= limit || val < -limit)
20331 /* Relax a machine dependent frag. This returns the amount by which
20332 the current size of the frag should change. */
20335 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
20340 oldsize = fragp->fr_var;
20341 switch (fragp->fr_subtype)
20343 case T_MNEM_ldr_pc2:
20344 newsize = relax_adr (fragp, sec, stretch);
20346 case T_MNEM_ldr_pc:
20347 case T_MNEM_ldr_sp:
20348 case T_MNEM_str_sp:
20349 newsize = relax_immediate (fragp, 8, 2);
20353 newsize = relax_immediate (fragp, 5, 2);
20357 newsize = relax_immediate (fragp, 5, 1);
20361 newsize = relax_immediate (fragp, 5, 0);
20364 newsize = relax_adr (fragp, sec, stretch);
20370 newsize = relax_immediate (fragp, 8, 0);
20373 newsize = relax_branch (fragp, sec, 11, stretch);
20376 newsize = relax_branch (fragp, sec, 8, stretch);
20378 case T_MNEM_add_sp:
20379 case T_MNEM_add_pc:
20380 newsize = relax_immediate (fragp, 8, 2);
20382 case T_MNEM_inc_sp:
20383 case T_MNEM_dec_sp:
20384 newsize = relax_immediate (fragp, 7, 2);
20390 newsize = relax_addsub (fragp, sec);
20396 fragp->fr_var = newsize;
20397 /* Freeze wide instructions that are at or before the same location as
20398 in the previous pass. This avoids infinite loops.
20399 Don't freeze them unconditionally because targets may be artificially
20400 misaligned by the expansion of preceding frags. */
20401 if (stretch <= 0 && newsize > 2)
20403 md_convert_frag (sec->owner, sec, fragp);
20407 return newsize - oldsize;
20410 /* Round up a section size to the appropriate boundary. */
20413 md_section_align (segT segment ATTRIBUTE_UNUSED,
20416 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20417 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20419 /* For a.out, force the section size to be aligned. If we don't do
20420 this, BFD will align it for us, but it will not write out the
20421 final bytes of the section. This may be a bug in BFD, but it is
20422 easier to fix it here since that is how the other a.out targets
20426 align = bfd_get_section_alignment (stdoutput, segment);
20427 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20434 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20435 of an rs_align_code fragment. */
20438 arm_handle_align (fragS * fragP)
20440 static char const arm_noop[2][2][4] =
20443 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20444 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20447 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20448 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20451 static char const thumb_noop[2][2][2] =
20454 {0xc0, 0x46}, /* LE */
20455 {0x46, 0xc0}, /* BE */
20458 {0x00, 0xbf}, /* LE */
20459 {0xbf, 0x00} /* BE */
20462 static char const wide_thumb_noop[2][4] =
20463 { /* Wide Thumb-2 */
20464 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20465 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20468 unsigned bytes, fix, noop_size;
20471 const char *narrow_noop = NULL;
20476 if (fragP->fr_type != rs_align_code)
20479 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20480 p = fragP->fr_literal + fragP->fr_fix;
20483 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20484 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
20486 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
20488 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
20490 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
20492 narrow_noop = thumb_noop[1][target_big_endian];
20493 noop = wide_thumb_noop[target_big_endian];
20496 noop = thumb_noop[0][target_big_endian];
20504 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
20505 [target_big_endian];
20512 fragP->fr_var = noop_size;
20514 if (bytes & (noop_size - 1))
20516 fix = bytes & (noop_size - 1);
20518 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20520 memset (p, 0, fix);
20527 if (bytes & noop_size)
20529 /* Insert a narrow noop. */
20530 memcpy (p, narrow_noop, noop_size);
20532 bytes -= noop_size;
20536 /* Use wide noops for the remainder */
20540 while (bytes >= noop_size)
20542 memcpy (p, noop, noop_size);
20544 bytes -= noop_size;
20548 fragP->fr_fix += fix;
20551 /* Called from md_do_align. Used to create an alignment
20552 frag in a code section. */
20555 arm_frag_align_code (int n, int max)
20559 /* We assume that there will never be a requirement
20560 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20561 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
20566 _("alignments greater than %d bytes not supported in .text sections."),
20567 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20568 as_fatal ("%s", err_msg);
20571 p = frag_var (rs_align_code,
20572 MAX_MEM_FOR_RS_ALIGN_CODE,
20574 (relax_substateT) max,
20581 /* Perform target specific initialisation of a frag.
20582 Note - despite the name this initialisation is not done when the frag
20583 is created, but only when its type is assigned. A frag can be created
20584 and used a long time before its type is set, so beware of assuming that
20585 this initialisationis performed first. */
20589 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20591 /* Record whether this frag is in an ARM or a THUMB area. */
20592 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20595 #else /* OBJ_ELF is defined. */
20597 arm_init_frag (fragS * fragP, int max_chars)
20599 /* If the current ARM vs THUMB mode has not already
20600 been recorded into this frag then do so now. */
20601 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20603 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20605 /* Record a mapping symbol for alignment frags. We will delete this
20606 later if the alignment ends up empty. */
20607 switch (fragP->fr_type)
20610 case rs_align_test:
20612 mapping_state_2 (MAP_DATA, max_chars);
20614 case rs_align_code:
20615 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20623 /* When we change sections we need to issue a new mapping symbol. */
20626 arm_elf_change_section (void)
20628 /* Link an unlinked unwind index table section to the .text section. */
20629 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20630 && elf_linked_to_section (now_seg) == NULL)
20631 elf_linked_to_section (now_seg) = text_section;
20635 arm_elf_section_type (const char * str, size_t len)
20637 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20638 return SHT_ARM_EXIDX;
20643 /* Code to deal with unwinding tables. */
20645 static void add_unwind_adjustsp (offsetT);
20647 /* Generate any deferred unwind frame offset. */
20650 flush_pending_unwind (void)
20654 offset = unwind.pending_offset;
20655 unwind.pending_offset = 0;
20657 add_unwind_adjustsp (offset);
20660 /* Add an opcode to this list for this function. Two-byte opcodes should
20661 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20665 add_unwind_opcode (valueT op, int length)
20667 /* Add any deferred stack adjustment. */
20668 if (unwind.pending_offset)
20669 flush_pending_unwind ();
20671 unwind.sp_restored = 0;
20673 if (unwind.opcode_count + length > unwind.opcode_alloc)
20675 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20676 if (unwind.opcodes)
20677 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
20678 unwind.opcode_alloc);
20680 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
20685 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20687 unwind.opcode_count++;
20691 /* Add unwind opcodes to adjust the stack pointer. */
20694 add_unwind_adjustsp (offsetT offset)
20698 if (offset > 0x200)
20700 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20705 /* Long form: 0xb2, uleb128. */
20706 /* This might not fit in a word so add the individual bytes,
20707 remembering the list is built in reverse order. */
20708 o = (valueT) ((offset - 0x204) >> 2);
20710 add_unwind_opcode (0, 1);
20712 /* Calculate the uleb128 encoding of the offset. */
20716 bytes[n] = o & 0x7f;
20722 /* Add the insn. */
20724 add_unwind_opcode (bytes[n - 1], 1);
20725 add_unwind_opcode (0xb2, 1);
20727 else if (offset > 0x100)
20729 /* Two short opcodes. */
20730 add_unwind_opcode (0x3f, 1);
20731 op = (offset - 0x104) >> 2;
20732 add_unwind_opcode (op, 1);
20734 else if (offset > 0)
20736 /* Short opcode. */
20737 op = (offset - 4) >> 2;
20738 add_unwind_opcode (op, 1);
20740 else if (offset < 0)
20743 while (offset > 0x100)
20745 add_unwind_opcode (0x7f, 1);
20748 op = ((offset - 4) >> 2) | 0x40;
20749 add_unwind_opcode (op, 1);
20753 /* Finish the list of unwind opcodes for this function. */
20755 finish_unwind_opcodes (void)
20759 if (unwind.fp_used)
20761 /* Adjust sp as necessary. */
20762 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20763 flush_pending_unwind ();
20765 /* After restoring sp from the frame pointer. */
20766 op = 0x90 | unwind.fp_reg;
20767 add_unwind_opcode (op, 1);
20770 flush_pending_unwind ();
20774 /* Start an exception table entry. If idx is nonzero this is an index table
20778 start_unwind_section (const segT text_seg, int idx)
20780 const char * text_name;
20781 const char * prefix;
20782 const char * prefix_once;
20783 const char * group_name;
20787 size_t sec_name_len;
20794 prefix = ELF_STRING_ARM_unwind;
20795 prefix_once = ELF_STRING_ARM_unwind_once;
20796 type = SHT_ARM_EXIDX;
20800 prefix = ELF_STRING_ARM_unwind_info;
20801 prefix_once = ELF_STRING_ARM_unwind_info_once;
20802 type = SHT_PROGBITS;
20805 text_name = segment_name (text_seg);
20806 if (streq (text_name, ".text"))
20809 if (strncmp (text_name, ".gnu.linkonce.t.",
20810 strlen (".gnu.linkonce.t.")) == 0)
20812 prefix = prefix_once;
20813 text_name += strlen (".gnu.linkonce.t.");
20816 prefix_len = strlen (prefix);
20817 text_len = strlen (text_name);
20818 sec_name_len = prefix_len + text_len;
20819 sec_name = (char *) xmalloc (sec_name_len + 1);
20820 memcpy (sec_name, prefix, prefix_len);
20821 memcpy (sec_name + prefix_len, text_name, text_len);
20822 sec_name[prefix_len + text_len] = '\0';
20828 /* Handle COMDAT group. */
20829 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20831 group_name = elf_group_name (text_seg);
20832 if (group_name == NULL)
20834 as_bad (_("Group section `%s' has no group signature"),
20835 segment_name (text_seg));
20836 ignore_rest_of_line ();
20839 flags |= SHF_GROUP;
20843 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20845 /* Set the section link for index tables. */
20847 elf_linked_to_section (now_seg) = text_seg;
20851 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20852 personality routine data. Returns zero, or the index table value for
20853 and inline entry. */
20856 create_unwind_entry (int have_data)
20861 /* The current word of data. */
20863 /* The number of bytes left in this word. */
20866 finish_unwind_opcodes ();
20868 /* Remember the current text section. */
20869 unwind.saved_seg = now_seg;
20870 unwind.saved_subseg = now_subseg;
20872 start_unwind_section (now_seg, 0);
20874 if (unwind.personality_routine == NULL)
20876 if (unwind.personality_index == -2)
20879 as_bad (_("handlerdata in cantunwind frame"));
20880 return 1; /* EXIDX_CANTUNWIND. */
20883 /* Use a default personality routine if none is specified. */
20884 if (unwind.personality_index == -1)
20886 if (unwind.opcode_count > 3)
20887 unwind.personality_index = 1;
20889 unwind.personality_index = 0;
20892 /* Space for the personality routine entry. */
20893 if (unwind.personality_index == 0)
20895 if (unwind.opcode_count > 3)
20896 as_bad (_("too many unwind opcodes for personality routine 0"));
20900 /* All the data is inline in the index table. */
20903 while (unwind.opcode_count > 0)
20905 unwind.opcode_count--;
20906 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20910 /* Pad with "finish" opcodes. */
20912 data = (data << 8) | 0xb0;
20919 /* We get two opcodes "free" in the first word. */
20920 size = unwind.opcode_count - 2;
20924 gas_assert (unwind.personality_index == -1);
20926 /* An extra byte is required for the opcode count. */
20927 size = unwind.opcode_count + 1;
20930 size = (size + 3) >> 2;
20932 as_bad (_("too many unwind opcodes"));
20934 frag_align (2, 0, 0);
20935 record_alignment (now_seg, 2);
20936 unwind.table_entry = expr_build_dot ();
20938 /* Allocate the table entry. */
20939 ptr = frag_more ((size << 2) + 4);
20940 /* PR 13449: Zero the table entries in case some of them are not used. */
20941 memset (ptr, 0, (size << 2) + 4);
20942 where = frag_now_fix () - ((size << 2) + 4);
20944 switch (unwind.personality_index)
20947 /* ??? Should this be a PLT generating relocation? */
20948 /* Custom personality routine. */
20949 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20950 BFD_RELOC_ARM_PREL31);
20955 /* Set the first byte to the number of additional words. */
20956 data = size > 0 ? size - 1 : 0;
20960 /* ABI defined personality routines. */
20962 /* Three opcodes bytes are packed into the first word. */
20969 /* The size and first two opcode bytes go in the first word. */
20970 data = ((0x80 + unwind.personality_index) << 8) | size;
20975 /* Should never happen. */
20979 /* Pack the opcodes into words (MSB first), reversing the list at the same
20981 while (unwind.opcode_count > 0)
20985 md_number_to_chars (ptr, data, 4);
20990 unwind.opcode_count--;
20992 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20995 /* Finish off the last word. */
20998 /* Pad with "finish" opcodes. */
21000 data = (data << 8) | 0xb0;
21002 md_number_to_chars (ptr, data, 4);
21007 /* Add an empty descriptor if there is no user-specified data. */
21008 ptr = frag_more (4);
21009 md_number_to_chars (ptr, 0, 4);
21016 /* Initialize the DWARF-2 unwind information for this procedure. */
21019 tc_arm_frame_initial_instructions (void)
21021 cfi_add_CFA_def_cfa (REG_SP, 0);
21023 #endif /* OBJ_ELF */
21025 /* Convert REGNAME to a DWARF-2 register number. */
21028 tc_arm_regname_to_dw2regnum (char *regname)
21030 int reg = arm_reg_parse (®name, REG_TYPE_RN);
21034 /* PR 16694: Allow VFP registers as well. */
21035 reg = arm_reg_parse (®name, REG_TYPE_VFS);
21039 reg = arm_reg_parse (®name, REG_TYPE_VFD);
21048 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
21052 exp.X_op = O_secrel;
21053 exp.X_add_symbol = symbol;
21054 exp.X_add_number = 0;
21055 emit_expr (&exp, size);
21059 /* MD interface: Symbol and relocation handling. */
21061 /* Return the address within the segment that a PC-relative fixup is
21062 relative to. For ARM, PC-relative fixups applied to instructions
21063 are generally relative to the location of the fixup plus 8 bytes.
21064 Thumb branches are offset by 4, and Thumb loads relative to PC
21065 require special handling. */
21068 md_pcrel_from_section (fixS * fixP, segT seg)
21070 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
21072 /* If this is pc-relative and we are going to emit a relocation
21073 then we just want to put out any pipeline compensation that the linker
21074 will need. Otherwise we want to use the calculated base.
21075 For WinCE we skip the bias for externals as well, since this
21076 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21078 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
21079 || (arm_force_relocation (fixP)
21081 && !S_IS_EXTERNAL (fixP->fx_addsy)
21087 switch (fixP->fx_r_type)
21089 /* PC relative addressing on the Thumb is slightly odd as the
21090 bottom two bits of the PC are forced to zero for the
21091 calculation. This happens *after* application of the
21092 pipeline offset. However, Thumb adrl already adjusts for
21093 this, so we need not do it again. */
21094 case BFD_RELOC_ARM_THUMB_ADD:
21097 case BFD_RELOC_ARM_THUMB_OFFSET:
21098 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21099 case BFD_RELOC_ARM_T32_ADD_PC12:
21100 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21101 return (base + 4) & ~3;
21103 /* Thumb branches are simply offset by +4. */
21104 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21105 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21106 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21107 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21108 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21111 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21113 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21114 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21115 && ARM_IS_FUNC (fixP->fx_addsy)
21116 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21117 base = fixP->fx_where + fixP->fx_frag->fr_address;
21120 /* BLX is like branches above, but forces the low two bits of PC to
21122 case BFD_RELOC_THUMB_PCREL_BLX:
21124 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21125 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21126 && THUMB_IS_FUNC (fixP->fx_addsy)
21127 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21128 base = fixP->fx_where + fixP->fx_frag->fr_address;
21129 return (base + 4) & ~3;
21131 /* ARM mode branches are offset by +8. However, the Windows CE
21132 loader expects the relocation not to take this into account. */
21133 case BFD_RELOC_ARM_PCREL_BLX:
21135 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21136 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21137 && ARM_IS_FUNC (fixP->fx_addsy)
21138 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21139 base = fixP->fx_where + fixP->fx_frag->fr_address;
21142 case BFD_RELOC_ARM_PCREL_CALL:
21144 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21145 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21146 && THUMB_IS_FUNC (fixP->fx_addsy)
21147 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21148 base = fixP->fx_where + fixP->fx_frag->fr_address;
21151 case BFD_RELOC_ARM_PCREL_BRANCH:
21152 case BFD_RELOC_ARM_PCREL_JUMP:
21153 case BFD_RELOC_ARM_PLT32:
21155 /* When handling fixups immediately, because we have already
21156 discovered the value of a symbol, or the address of the frag involved
21157 we must account for the offset by +8, as the OS loader will never see the reloc.
21158 see fixup_segment() in write.c
21159 The S_IS_EXTERNAL test handles the case of global symbols.
21160 Those need the calculated base, not just the pipe compensation the linker will need. */
21162 && fixP->fx_addsy != NULL
21163 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21164 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21172 /* ARM mode loads relative to PC are also offset by +8. Unlike
21173 branches, the Windows CE loader *does* expect the relocation
21174 to take this into account. */
21175 case BFD_RELOC_ARM_OFFSET_IMM:
21176 case BFD_RELOC_ARM_OFFSET_IMM8:
21177 case BFD_RELOC_ARM_HWLITERAL:
21178 case BFD_RELOC_ARM_LITERAL:
21179 case BFD_RELOC_ARM_CP_OFF_IMM:
21183 /* Other PC-relative relocations are un-offset. */
21189 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21190 Otherwise we have no need to default values of symbols. */
21193 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
21196 if (name[0] == '_' && name[1] == 'G'
21197 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21201 if (symbol_find (name))
21202 as_bad (_("GOT already in the symbol table"));
21204 GOT_symbol = symbol_new (name, undefined_section,
21205 (valueT) 0, & zero_address_frag);
21215 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21216 computed as two separate immediate values, added together. We
21217 already know that this value cannot be computed by just one ARM
21220 static unsigned int
21221 validate_immediate_twopart (unsigned int val,
21222 unsigned int * highpart)
21227 for (i = 0; i < 32; i += 2)
21228 if (((a = rotate_left (val, i)) & 0xff) != 0)
21234 * highpart = (a >> 8) | ((i + 24) << 7);
21236 else if (a & 0xff0000)
21238 if (a & 0xff000000)
21240 * highpart = (a >> 16) | ((i + 16) << 7);
21244 gas_assert (a & 0xff000000);
21245 * highpart = (a >> 24) | ((i + 8) << 7);
21248 return (a & 0xff) | (i << 7);
21255 validate_offset_imm (unsigned int val, int hwse)
21257 if ((hwse && val > 255) || val > 4095)
21262 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21263 negative immediate constant by altering the instruction. A bit of
21268 by inverting the second operand, and
21271 by negating the second operand. */
21274 negate_data_op (unsigned long * instruction,
21275 unsigned long value)
21278 unsigned long negated, inverted;
21280 negated = encode_arm_immediate (-value);
21281 inverted = encode_arm_immediate (~value);
21283 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21286 /* First negates. */
21287 case OPCODE_SUB: /* ADD <-> SUB */
21288 new_inst = OPCODE_ADD;
21293 new_inst = OPCODE_SUB;
21297 case OPCODE_CMP: /* CMP <-> CMN */
21298 new_inst = OPCODE_CMN;
21303 new_inst = OPCODE_CMP;
21307 /* Now Inverted ops. */
21308 case OPCODE_MOV: /* MOV <-> MVN */
21309 new_inst = OPCODE_MVN;
21314 new_inst = OPCODE_MOV;
21318 case OPCODE_AND: /* AND <-> BIC */
21319 new_inst = OPCODE_BIC;
21324 new_inst = OPCODE_AND;
21328 case OPCODE_ADC: /* ADC <-> SBC */
21329 new_inst = OPCODE_SBC;
21334 new_inst = OPCODE_ADC;
21338 /* We cannot do anything. */
21343 if (value == (unsigned) FAIL)
21346 *instruction &= OPCODE_MASK;
21347 *instruction |= new_inst << DATA_OP_SHIFT;
21351 /* Like negate_data_op, but for Thumb-2. */
21353 static unsigned int
21354 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
21358 unsigned int negated, inverted;
21360 negated = encode_thumb32_immediate (-value);
21361 inverted = encode_thumb32_immediate (~value);
21363 rd = (*instruction >> 8) & 0xf;
21364 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21367 /* ADD <-> SUB. Includes CMP <-> CMN. */
21368 case T2_OPCODE_SUB:
21369 new_inst = T2_OPCODE_ADD;
21373 case T2_OPCODE_ADD:
21374 new_inst = T2_OPCODE_SUB;
21378 /* ORR <-> ORN. Includes MOV <-> MVN. */
21379 case T2_OPCODE_ORR:
21380 new_inst = T2_OPCODE_ORN;
21384 case T2_OPCODE_ORN:
21385 new_inst = T2_OPCODE_ORR;
21389 /* AND <-> BIC. TST has no inverted equivalent. */
21390 case T2_OPCODE_AND:
21391 new_inst = T2_OPCODE_BIC;
21398 case T2_OPCODE_BIC:
21399 new_inst = T2_OPCODE_AND;
21404 case T2_OPCODE_ADC:
21405 new_inst = T2_OPCODE_SBC;
21409 case T2_OPCODE_SBC:
21410 new_inst = T2_OPCODE_ADC;
21414 /* We cannot do anything. */
21419 if (value == (unsigned int)FAIL)
21422 *instruction &= T2_OPCODE_MASK;
21423 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21427 /* Read a 32-bit thumb instruction from buf. */
21428 static unsigned long
21429 get_thumb32_insn (char * buf)
21431 unsigned long insn;
21432 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21433 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21439 /* We usually want to set the low bit on the address of thumb function
21440 symbols. In particular .word foo - . should have the low bit set.
21441 Generic code tries to fold the difference of two symbols to
21442 a constant. Prevent this and force a relocation when the first symbols
21443 is a thumb function. */
21446 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21448 if (op == O_subtract
21449 && l->X_op == O_symbol
21450 && r->X_op == O_symbol
21451 && THUMB_IS_FUNC (l->X_add_symbol))
21453 l->X_op = O_subtract;
21454 l->X_op_symbol = r->X_add_symbol;
21455 l->X_add_number -= r->X_add_number;
21459 /* Process as normal. */
21463 /* Encode Thumb2 unconditional branches and calls. The encoding
21464 for the 2 are identical for the immediate values. */
21467 encode_thumb2_b_bl_offset (char * buf, offsetT value)
21469 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21472 addressT S, I1, I2, lo, hi;
21474 S = (value >> 24) & 0x01;
21475 I1 = (value >> 23) & 0x01;
21476 I2 = (value >> 22) & 0x01;
21477 hi = (value >> 12) & 0x3ff;
21478 lo = (value >> 1) & 0x7ff;
21479 newval = md_chars_to_number (buf, THUMB_SIZE);
21480 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21481 newval |= (S << 10) | hi;
21482 newval2 &= ~T2I1I2MASK;
21483 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21484 md_number_to_chars (buf, newval, THUMB_SIZE);
21485 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21489 md_apply_fix (fixS * fixP,
21493 offsetT value = * valP;
21495 unsigned int newimm;
21496 unsigned long temp;
21498 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
21500 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
21502 /* Note whether this will delete the relocation. */
21504 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21507 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21508 consistency with the behaviour on 32-bit hosts. Remember value
21510 value &= 0xffffffff;
21511 value ^= 0x80000000;
21512 value -= 0x80000000;
21515 fixP->fx_addnumber = value;
21517 /* Same treatment for fixP->fx_offset. */
21518 fixP->fx_offset &= 0xffffffff;
21519 fixP->fx_offset ^= 0x80000000;
21520 fixP->fx_offset -= 0x80000000;
21522 switch (fixP->fx_r_type)
21524 case BFD_RELOC_NONE:
21525 /* This will need to go in the object file. */
21529 case BFD_RELOC_ARM_IMMEDIATE:
21530 /* We claim that this fixup has been processed here,
21531 even if in fact we generate an error because we do
21532 not have a reloc for it, so tc_gen_reloc will reject it. */
21535 if (fixP->fx_addsy)
21537 const char *msg = 0;
21539 if (! S_IS_DEFINED (fixP->fx_addsy))
21540 msg = _("undefined symbol %s used as an immediate value");
21541 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21542 msg = _("symbol %s is in a different section");
21543 else if (S_IS_WEAK (fixP->fx_addsy))
21544 msg = _("symbol %s is weak and may be overridden later");
21548 as_bad_where (fixP->fx_file, fixP->fx_line,
21549 msg, S_GET_NAME (fixP->fx_addsy));
21554 temp = md_chars_to_number (buf, INSN_SIZE);
21556 /* If the offset is negative, we should use encoding A2 for ADR. */
21557 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21558 newimm = negate_data_op (&temp, value);
21561 newimm = encode_arm_immediate (value);
21563 /* If the instruction will fail, see if we can fix things up by
21564 changing the opcode. */
21565 if (newimm == (unsigned int) FAIL)
21566 newimm = negate_data_op (&temp, value);
21569 if (newimm == (unsigned int) FAIL)
21571 as_bad_where (fixP->fx_file, fixP->fx_line,
21572 _("invalid constant (%lx) after fixup"),
21573 (unsigned long) value);
21577 newimm |= (temp & 0xfffff000);
21578 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21581 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21583 unsigned int highpart = 0;
21584 unsigned int newinsn = 0xe1a00000; /* nop. */
21586 if (fixP->fx_addsy)
21588 const char *msg = 0;
21590 if (! S_IS_DEFINED (fixP->fx_addsy))
21591 msg = _("undefined symbol %s used as an immediate value");
21592 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21593 msg = _("symbol %s is in a different section");
21594 else if (S_IS_WEAK (fixP->fx_addsy))
21595 msg = _("symbol %s is weak and may be overridden later");
21599 as_bad_where (fixP->fx_file, fixP->fx_line,
21600 msg, S_GET_NAME (fixP->fx_addsy));
21605 newimm = encode_arm_immediate (value);
21606 temp = md_chars_to_number (buf, INSN_SIZE);
21608 /* If the instruction will fail, see if we can fix things up by
21609 changing the opcode. */
21610 if (newimm == (unsigned int) FAIL
21611 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21613 /* No ? OK - try using two ADD instructions to generate
21615 newimm = validate_immediate_twopart (value, & highpart);
21617 /* Yes - then make sure that the second instruction is
21619 if (newimm != (unsigned int) FAIL)
21621 /* Still No ? Try using a negated value. */
21622 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21623 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21624 /* Otherwise - give up. */
21627 as_bad_where (fixP->fx_file, fixP->fx_line,
21628 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21633 /* Replace the first operand in the 2nd instruction (which
21634 is the PC) with the destination register. We have
21635 already added in the PC in the first instruction and we
21636 do not want to do it again. */
21637 newinsn &= ~ 0xf0000;
21638 newinsn |= ((newinsn & 0x0f000) << 4);
21641 newimm |= (temp & 0xfffff000);
21642 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21644 highpart |= (newinsn & 0xfffff000);
21645 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21649 case BFD_RELOC_ARM_OFFSET_IMM:
21650 if (!fixP->fx_done && seg->use_rela_p)
21653 case BFD_RELOC_ARM_LITERAL:
21659 if (validate_offset_imm (value, 0) == FAIL)
21661 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21662 as_bad_where (fixP->fx_file, fixP->fx_line,
21663 _("invalid literal constant: pool needs to be closer"));
21665 as_bad_where (fixP->fx_file, fixP->fx_line,
21666 _("bad immediate value for offset (%ld)"),
21671 newval = md_chars_to_number (buf, INSN_SIZE);
21673 newval &= 0xfffff000;
21676 newval &= 0xff7ff000;
21677 newval |= value | (sign ? INDEX_UP : 0);
21679 md_number_to_chars (buf, newval, INSN_SIZE);
21682 case BFD_RELOC_ARM_OFFSET_IMM8:
21683 case BFD_RELOC_ARM_HWLITERAL:
21689 if (validate_offset_imm (value, 1) == FAIL)
21691 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21692 as_bad_where (fixP->fx_file, fixP->fx_line,
21693 _("invalid literal constant: pool needs to be closer"));
21695 as_bad_where (fixP->fx_file, fixP->fx_line,
21696 _("bad immediate value for 8-bit offset (%ld)"),
21701 newval = md_chars_to_number (buf, INSN_SIZE);
21703 newval &= 0xfffff0f0;
21706 newval &= 0xff7ff0f0;
21707 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21709 md_number_to_chars (buf, newval, INSN_SIZE);
21712 case BFD_RELOC_ARM_T32_OFFSET_U8:
21713 if (value < 0 || value > 1020 || value % 4 != 0)
21714 as_bad_where (fixP->fx_file, fixP->fx_line,
21715 _("bad immediate value for offset (%ld)"), (long) value);
21718 newval = md_chars_to_number (buf+2, THUMB_SIZE);
21720 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21723 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21724 /* This is a complicated relocation used for all varieties of Thumb32
21725 load/store instruction with immediate offset:
21727 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21728 *4, optional writeback(W)
21729 (doubleword load/store)
21731 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21732 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21733 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21734 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21735 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21737 Uppercase letters indicate bits that are already encoded at
21738 this point. Lowercase letters are our problem. For the
21739 second block of instructions, the secondary opcode nybble
21740 (bits 8..11) is present, and bit 23 is zero, even if this is
21741 a PC-relative operation. */
21742 newval = md_chars_to_number (buf, THUMB_SIZE);
21744 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
21746 if ((newval & 0xf0000000) == 0xe0000000)
21748 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21750 newval |= (1 << 23);
21753 if (value % 4 != 0)
21755 as_bad_where (fixP->fx_file, fixP->fx_line,
21756 _("offset not a multiple of 4"));
21762 as_bad_where (fixP->fx_file, fixP->fx_line,
21763 _("offset out of range"));
21768 else if ((newval & 0x000f0000) == 0x000f0000)
21770 /* PC-relative, 12-bit offset. */
21772 newval |= (1 << 23);
21777 as_bad_where (fixP->fx_file, fixP->fx_line,
21778 _("offset out of range"));
21783 else if ((newval & 0x00000100) == 0x00000100)
21785 /* Writeback: 8-bit, +/- offset. */
21787 newval |= (1 << 9);
21792 as_bad_where (fixP->fx_file, fixP->fx_line,
21793 _("offset out of range"));
21798 else if ((newval & 0x00000f00) == 0x00000e00)
21800 /* T-instruction: positive 8-bit offset. */
21801 if (value < 0 || value > 0xff)
21803 as_bad_where (fixP->fx_file, fixP->fx_line,
21804 _("offset out of range"));
21812 /* Positive 12-bit or negative 8-bit offset. */
21816 newval |= (1 << 23);
21826 as_bad_where (fixP->fx_file, fixP->fx_line,
21827 _("offset out of range"));
21834 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21835 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21838 case BFD_RELOC_ARM_SHIFT_IMM:
21839 newval = md_chars_to_number (buf, INSN_SIZE);
21840 if (((unsigned long) value) > 32
21842 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21844 as_bad_where (fixP->fx_file, fixP->fx_line,
21845 _("shift expression is too large"));
21850 /* Shifts of zero must be done as lsl. */
21852 else if (value == 32)
21854 newval &= 0xfffff07f;
21855 newval |= (value & 0x1f) << 7;
21856 md_number_to_chars (buf, newval, INSN_SIZE);
21859 case BFD_RELOC_ARM_T32_IMMEDIATE:
21860 case BFD_RELOC_ARM_T32_ADD_IMM:
21861 case BFD_RELOC_ARM_T32_IMM12:
21862 case BFD_RELOC_ARM_T32_ADD_PC12:
21863 /* We claim that this fixup has been processed here,
21864 even if in fact we generate an error because we do
21865 not have a reloc for it, so tc_gen_reloc will reject it. */
21869 && ! S_IS_DEFINED (fixP->fx_addsy))
21871 as_bad_where (fixP->fx_file, fixP->fx_line,
21872 _("undefined symbol %s used as an immediate value"),
21873 S_GET_NAME (fixP->fx_addsy));
21877 newval = md_chars_to_number (buf, THUMB_SIZE);
21879 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21882 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21883 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21885 newimm = encode_thumb32_immediate (value);
21886 if (newimm == (unsigned int) FAIL)
21887 newimm = thumb32_negate_data_op (&newval, value);
21889 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21890 && newimm == (unsigned int) FAIL)
21892 /* Turn add/sum into addw/subw. */
21893 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21894 newval = (newval & 0xfeffffff) | 0x02000000;
21895 /* No flat 12-bit imm encoding for addsw/subsw. */
21896 if ((newval & 0x00100000) == 0)
21898 /* 12 bit immediate for addw/subw. */
21902 newval ^= 0x00a00000;
21905 newimm = (unsigned int) FAIL;
21911 if (newimm == (unsigned int)FAIL)
21913 as_bad_where (fixP->fx_file, fixP->fx_line,
21914 _("invalid constant (%lx) after fixup"),
21915 (unsigned long) value);
21919 newval |= (newimm & 0x800) << 15;
21920 newval |= (newimm & 0x700) << 4;
21921 newval |= (newimm & 0x0ff);
21923 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21924 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21927 case BFD_RELOC_ARM_SMC:
21928 if (((unsigned long) value) > 0xffff)
21929 as_bad_where (fixP->fx_file, fixP->fx_line,
21930 _("invalid smc expression"));
21931 newval = md_chars_to_number (buf, INSN_SIZE);
21932 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21933 md_number_to_chars (buf, newval, INSN_SIZE);
21936 case BFD_RELOC_ARM_HVC:
21937 if (((unsigned long) value) > 0xffff)
21938 as_bad_where (fixP->fx_file, fixP->fx_line,
21939 _("invalid hvc expression"));
21940 newval = md_chars_to_number (buf, INSN_SIZE);
21941 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21942 md_number_to_chars (buf, newval, INSN_SIZE);
21945 case BFD_RELOC_ARM_SWI:
21946 if (fixP->tc_fix_data != 0)
21948 if (((unsigned long) value) > 0xff)
21949 as_bad_where (fixP->fx_file, fixP->fx_line,
21950 _("invalid swi expression"));
21951 newval = md_chars_to_number (buf, THUMB_SIZE);
21953 md_number_to_chars (buf, newval, THUMB_SIZE);
21957 if (((unsigned long) value) > 0x00ffffff)
21958 as_bad_where (fixP->fx_file, fixP->fx_line,
21959 _("invalid swi expression"));
21960 newval = md_chars_to_number (buf, INSN_SIZE);
21962 md_number_to_chars (buf, newval, INSN_SIZE);
21966 case BFD_RELOC_ARM_MULTI:
21967 if (((unsigned long) value) > 0xffff)
21968 as_bad_where (fixP->fx_file, fixP->fx_line,
21969 _("invalid expression in load/store multiple"));
21970 newval = value | md_chars_to_number (buf, INSN_SIZE);
21971 md_number_to_chars (buf, newval, INSN_SIZE);
21975 case BFD_RELOC_ARM_PCREL_CALL:
21977 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21979 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21980 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21981 && THUMB_IS_FUNC (fixP->fx_addsy))
21982 /* Flip the bl to blx. This is a simple flip
21983 bit here because we generate PCREL_CALL for
21984 unconditional bls. */
21986 newval = md_chars_to_number (buf, INSN_SIZE);
21987 newval = newval | 0x10000000;
21988 md_number_to_chars (buf, newval, INSN_SIZE);
21994 goto arm_branch_common;
21996 case BFD_RELOC_ARM_PCREL_JUMP:
21997 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21999 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22000 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22001 && THUMB_IS_FUNC (fixP->fx_addsy))
22003 /* This would map to a bl<cond>, b<cond>,
22004 b<always> to a Thumb function. We
22005 need to force a relocation for this particular
22007 newval = md_chars_to_number (buf, INSN_SIZE);
22011 case BFD_RELOC_ARM_PLT32:
22013 case BFD_RELOC_ARM_PCREL_BRANCH:
22015 goto arm_branch_common;
22017 case BFD_RELOC_ARM_PCREL_BLX:
22020 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22022 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22023 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22024 && ARM_IS_FUNC (fixP->fx_addsy))
22026 /* Flip the blx to a bl and warn. */
22027 const char *name = S_GET_NAME (fixP->fx_addsy);
22028 newval = 0xeb000000;
22029 as_warn_where (fixP->fx_file, fixP->fx_line,
22030 _("blx to '%s' an ARM ISA state function changed to bl"),
22032 md_number_to_chars (buf, newval, INSN_SIZE);
22038 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22039 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
22043 /* We are going to store value (shifted right by two) in the
22044 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22045 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22046 also be be clear. */
22048 as_bad_where (fixP->fx_file, fixP->fx_line,
22049 _("misaligned branch destination"));
22050 if ((value & (offsetT)0xfe000000) != (offsetT)0
22051 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
22052 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22054 if (fixP->fx_done || !seg->use_rela_p)
22056 newval = md_chars_to_number (buf, INSN_SIZE);
22057 newval |= (value >> 2) & 0x00ffffff;
22058 /* Set the H bit on BLX instructions. */
22062 newval |= 0x01000000;
22064 newval &= ~0x01000000;
22066 md_number_to_chars (buf, newval, INSN_SIZE);
22070 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
22071 /* CBZ can only branch forward. */
22073 /* Attempts to use CBZ to branch to the next instruction
22074 (which, strictly speaking, are prohibited) will be turned into
22077 FIXME: It may be better to remove the instruction completely and
22078 perform relaxation. */
22081 newval = md_chars_to_number (buf, THUMB_SIZE);
22082 newval = 0xbf00; /* NOP encoding T1 */
22083 md_number_to_chars (buf, newval, THUMB_SIZE);
22088 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22090 if (fixP->fx_done || !seg->use_rela_p)
22092 newval = md_chars_to_number (buf, THUMB_SIZE);
22093 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
22094 md_number_to_chars (buf, newval, THUMB_SIZE);
22099 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
22100 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
22101 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22103 if (fixP->fx_done || !seg->use_rela_p)
22105 newval = md_chars_to_number (buf, THUMB_SIZE);
22106 newval |= (value & 0x1ff) >> 1;
22107 md_number_to_chars (buf, newval, THUMB_SIZE);
22111 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
22112 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
22113 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22115 if (fixP->fx_done || !seg->use_rela_p)
22117 newval = md_chars_to_number (buf, THUMB_SIZE);
22118 newval |= (value & 0xfff) >> 1;
22119 md_number_to_chars (buf, newval, THUMB_SIZE);
22123 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22125 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22126 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22127 && ARM_IS_FUNC (fixP->fx_addsy)
22128 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22130 /* Force a relocation for a branch 20 bits wide. */
22133 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
22134 as_bad_where (fixP->fx_file, fixP->fx_line,
22135 _("conditional branch out of range"));
22137 if (fixP->fx_done || !seg->use_rela_p)
22140 addressT S, J1, J2, lo, hi;
22142 S = (value & 0x00100000) >> 20;
22143 J2 = (value & 0x00080000) >> 19;
22144 J1 = (value & 0x00040000) >> 18;
22145 hi = (value & 0x0003f000) >> 12;
22146 lo = (value & 0x00000ffe) >> 1;
22148 newval = md_chars_to_number (buf, THUMB_SIZE);
22149 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22150 newval |= (S << 10) | hi;
22151 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22152 md_number_to_chars (buf, newval, THUMB_SIZE);
22153 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22157 case BFD_RELOC_THUMB_PCREL_BLX:
22158 /* If there is a blx from a thumb state function to
22159 another thumb function flip this to a bl and warn
22163 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22164 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22165 && THUMB_IS_FUNC (fixP->fx_addsy))
22167 const char *name = S_GET_NAME (fixP->fx_addsy);
22168 as_warn_where (fixP->fx_file, fixP->fx_line,
22169 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22171 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22172 newval = newval | 0x1000;
22173 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22174 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22179 goto thumb_bl_common;
22181 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22182 /* A bl from Thumb state ISA to an internal ARM state function
22183 is converted to a blx. */
22185 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22186 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22187 && ARM_IS_FUNC (fixP->fx_addsy)
22188 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22190 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22191 newval = newval & ~0x1000;
22192 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22193 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22199 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22200 /* For a BLX instruction, make sure that the relocation is rounded up
22201 to a word boundary. This follows the semantics of the instruction
22202 which specifies that bit 1 of the target address will come from bit
22203 1 of the base address. */
22204 value = (value + 3) & ~ 3;
22207 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22208 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22209 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22212 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22214 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22215 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22216 else if ((value & ~0x1ffffff)
22217 && ((value & ~0x1ffffff) != ~0x1ffffff))
22218 as_bad_where (fixP->fx_file, fixP->fx_line,
22219 _("Thumb2 branch out of range"));
22222 if (fixP->fx_done || !seg->use_rela_p)
22223 encode_thumb2_b_bl_offset (buf, value);
22227 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22228 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22229 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22231 if (fixP->fx_done || !seg->use_rela_p)
22232 encode_thumb2_b_bl_offset (buf, value);
22237 if (fixP->fx_done || !seg->use_rela_p)
22238 md_number_to_chars (buf, value, 1);
22242 if (fixP->fx_done || !seg->use_rela_p)
22243 md_number_to_chars (buf, value, 2);
22247 case BFD_RELOC_ARM_TLS_CALL:
22248 case BFD_RELOC_ARM_THM_TLS_CALL:
22249 case BFD_RELOC_ARM_TLS_DESCSEQ:
22250 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22251 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22254 case BFD_RELOC_ARM_TLS_GOTDESC:
22255 case BFD_RELOC_ARM_TLS_GD32:
22256 case BFD_RELOC_ARM_TLS_LE32:
22257 case BFD_RELOC_ARM_TLS_IE32:
22258 case BFD_RELOC_ARM_TLS_LDM32:
22259 case BFD_RELOC_ARM_TLS_LDO32:
22260 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22263 case BFD_RELOC_ARM_GOT32:
22264 case BFD_RELOC_ARM_GOTOFF:
22265 if (fixP->fx_done || !seg->use_rela_p)
22266 md_number_to_chars (buf, 0, 4);
22269 case BFD_RELOC_ARM_GOT_PREL:
22270 if (fixP->fx_done || !seg->use_rela_p)
22271 md_number_to_chars (buf, value, 4);
22274 case BFD_RELOC_ARM_TARGET2:
22275 /* TARGET2 is not partial-inplace, so we need to write the
22276 addend here for REL targets, because it won't be written out
22277 during reloc processing later. */
22278 if (fixP->fx_done || !seg->use_rela_p)
22279 md_number_to_chars (buf, fixP->fx_offset, 4);
22283 case BFD_RELOC_RVA:
22285 case BFD_RELOC_ARM_TARGET1:
22286 case BFD_RELOC_ARM_ROSEGREL32:
22287 case BFD_RELOC_ARM_SBREL32:
22288 case BFD_RELOC_32_PCREL:
22290 case BFD_RELOC_32_SECREL:
22292 if (fixP->fx_done || !seg->use_rela_p)
22294 /* For WinCE we only do this for pcrel fixups. */
22295 if (fixP->fx_done || fixP->fx_pcrel)
22297 md_number_to_chars (buf, value, 4);
22301 case BFD_RELOC_ARM_PREL31:
22302 if (fixP->fx_done || !seg->use_rela_p)
22304 newval = md_chars_to_number (buf, 4) & 0x80000000;
22305 if ((value ^ (value >> 1)) & 0x40000000)
22307 as_bad_where (fixP->fx_file, fixP->fx_line,
22308 _("rel31 relocation overflow"));
22310 newval |= value & 0x7fffffff;
22311 md_number_to_chars (buf, newval, 4);
22316 case BFD_RELOC_ARM_CP_OFF_IMM:
22317 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22318 if (value < -1023 || value > 1023 || (value & 3))
22319 as_bad_where (fixP->fx_file, fixP->fx_line,
22320 _("co-processor offset out of range"));
22325 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22326 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22327 newval = md_chars_to_number (buf, INSN_SIZE);
22329 newval = get_thumb32_insn (buf);
22331 newval &= 0xffffff00;
22334 newval &= 0xff7fff00;
22335 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22337 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22338 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22339 md_number_to_chars (buf, newval, INSN_SIZE);
22341 put_thumb32_insn (buf, newval);
22344 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
22345 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
22346 if (value < -255 || value > 255)
22347 as_bad_where (fixP->fx_file, fixP->fx_line,
22348 _("co-processor offset out of range"));
22350 goto cp_off_common;
22352 case BFD_RELOC_ARM_THUMB_OFFSET:
22353 newval = md_chars_to_number (buf, THUMB_SIZE);
22354 /* Exactly what ranges, and where the offset is inserted depends
22355 on the type of instruction, we can establish this from the
22357 switch (newval >> 12)
22359 case 4: /* PC load. */
22360 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22361 forced to zero for these loads; md_pcrel_from has already
22362 compensated for this. */
22364 as_bad_where (fixP->fx_file, fixP->fx_line,
22365 _("invalid offset, target not word aligned (0x%08lX)"),
22366 (((unsigned long) fixP->fx_frag->fr_address
22367 + (unsigned long) fixP->fx_where) & ~3)
22368 + (unsigned long) value);
22370 if (value & ~0x3fc)
22371 as_bad_where (fixP->fx_file, fixP->fx_line,
22372 _("invalid offset, value too big (0x%08lX)"),
22375 newval |= value >> 2;
22378 case 9: /* SP load/store. */
22379 if (value & ~0x3fc)
22380 as_bad_where (fixP->fx_file, fixP->fx_line,
22381 _("invalid offset, value too big (0x%08lX)"),
22383 newval |= value >> 2;
22386 case 6: /* Word load/store. */
22388 as_bad_where (fixP->fx_file, fixP->fx_line,
22389 _("invalid offset, value too big (0x%08lX)"),
22391 newval |= value << 4; /* 6 - 2. */
22394 case 7: /* Byte load/store. */
22396 as_bad_where (fixP->fx_file, fixP->fx_line,
22397 _("invalid offset, value too big (0x%08lX)"),
22399 newval |= value << 6;
22402 case 8: /* Halfword load/store. */
22404 as_bad_where (fixP->fx_file, fixP->fx_line,
22405 _("invalid offset, value too big (0x%08lX)"),
22407 newval |= value << 5; /* 6 - 1. */
22411 as_bad_where (fixP->fx_file, fixP->fx_line,
22412 "Unable to process relocation for thumb opcode: %lx",
22413 (unsigned long) newval);
22416 md_number_to_chars (buf, newval, THUMB_SIZE);
22419 case BFD_RELOC_ARM_THUMB_ADD:
22420 /* This is a complicated relocation, since we use it for all of
22421 the following immediate relocations:
22425 9bit ADD/SUB SP word-aligned
22426 10bit ADD PC/SP word-aligned
22428 The type of instruction being processed is encoded in the
22435 newval = md_chars_to_number (buf, THUMB_SIZE);
22437 int rd = (newval >> 4) & 0xf;
22438 int rs = newval & 0xf;
22439 int subtract = !!(newval & 0x8000);
22441 /* Check for HI regs, only very restricted cases allowed:
22442 Adjusting SP, and using PC or SP to get an address. */
22443 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22444 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22445 as_bad_where (fixP->fx_file, fixP->fx_line,
22446 _("invalid Hi register with immediate"));
22448 /* If value is negative, choose the opposite instruction. */
22452 subtract = !subtract;
22454 as_bad_where (fixP->fx_file, fixP->fx_line,
22455 _("immediate value out of range"));
22460 if (value & ~0x1fc)
22461 as_bad_where (fixP->fx_file, fixP->fx_line,
22462 _("invalid immediate for stack address calculation"));
22463 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22464 newval |= value >> 2;
22466 else if (rs == REG_PC || rs == REG_SP)
22468 if (subtract || value & ~0x3fc)
22469 as_bad_where (fixP->fx_file, fixP->fx_line,
22470 _("invalid immediate for address calculation (value = 0x%08lX)"),
22471 (unsigned long) value);
22472 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22474 newval |= value >> 2;
22479 as_bad_where (fixP->fx_file, fixP->fx_line,
22480 _("immediate value out of range"));
22481 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22482 newval |= (rd << 8) | value;
22487 as_bad_where (fixP->fx_file, fixP->fx_line,
22488 _("immediate value out of range"));
22489 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22490 newval |= rd | (rs << 3) | (value << 6);
22493 md_number_to_chars (buf, newval, THUMB_SIZE);
22496 case BFD_RELOC_ARM_THUMB_IMM:
22497 newval = md_chars_to_number (buf, THUMB_SIZE);
22498 if (value < 0 || value > 255)
22499 as_bad_where (fixP->fx_file, fixP->fx_line,
22500 _("invalid immediate: %ld is out of range"),
22503 md_number_to_chars (buf, newval, THUMB_SIZE);
22506 case BFD_RELOC_ARM_THUMB_SHIFT:
22507 /* 5bit shift value (0..32). LSL cannot take 32. */
22508 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22509 temp = newval & 0xf800;
22510 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22511 as_bad_where (fixP->fx_file, fixP->fx_line,
22512 _("invalid shift value: %ld"), (long) value);
22513 /* Shifts of zero must be encoded as LSL. */
22515 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22516 /* Shifts of 32 are encoded as zero. */
22517 else if (value == 32)
22519 newval |= value << 6;
22520 md_number_to_chars (buf, newval, THUMB_SIZE);
22523 case BFD_RELOC_VTABLE_INHERIT:
22524 case BFD_RELOC_VTABLE_ENTRY:
22528 case BFD_RELOC_ARM_MOVW:
22529 case BFD_RELOC_ARM_MOVT:
22530 case BFD_RELOC_ARM_THUMB_MOVW:
22531 case BFD_RELOC_ARM_THUMB_MOVT:
22532 if (fixP->fx_done || !seg->use_rela_p)
22534 /* REL format relocations are limited to a 16-bit addend. */
22535 if (!fixP->fx_done)
22537 if (value < -0x8000 || value > 0x7fff)
22538 as_bad_where (fixP->fx_file, fixP->fx_line,
22539 _("offset out of range"));
22541 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22542 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22547 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22548 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22550 newval = get_thumb32_insn (buf);
22551 newval &= 0xfbf08f00;
22552 newval |= (value & 0xf000) << 4;
22553 newval |= (value & 0x0800) << 15;
22554 newval |= (value & 0x0700) << 4;
22555 newval |= (value & 0x00ff);
22556 put_thumb32_insn (buf, newval);
22560 newval = md_chars_to_number (buf, 4);
22561 newval &= 0xfff0f000;
22562 newval |= value & 0x0fff;
22563 newval |= (value & 0xf000) << 4;
22564 md_number_to_chars (buf, newval, 4);
22569 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22570 case BFD_RELOC_ARM_ALU_PC_G0:
22571 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22572 case BFD_RELOC_ARM_ALU_PC_G1:
22573 case BFD_RELOC_ARM_ALU_PC_G2:
22574 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22575 case BFD_RELOC_ARM_ALU_SB_G0:
22576 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22577 case BFD_RELOC_ARM_ALU_SB_G1:
22578 case BFD_RELOC_ARM_ALU_SB_G2:
22579 gas_assert (!fixP->fx_done);
22580 if (!seg->use_rela_p)
22583 bfd_vma encoded_addend;
22584 bfd_vma addend_abs = abs (value);
22586 /* Check that the absolute value of the addend can be
22587 expressed as an 8-bit constant plus a rotation. */
22588 encoded_addend = encode_arm_immediate (addend_abs);
22589 if (encoded_addend == (unsigned int) FAIL)
22590 as_bad_where (fixP->fx_file, fixP->fx_line,
22591 _("the offset 0x%08lX is not representable"),
22592 (unsigned long) addend_abs);
22594 /* Extract the instruction. */
22595 insn = md_chars_to_number (buf, INSN_SIZE);
22597 /* If the addend is positive, use an ADD instruction.
22598 Otherwise use a SUB. Take care not to destroy the S bit. */
22599 insn &= 0xff1fffff;
22605 /* Place the encoded addend into the first 12 bits of the
22607 insn &= 0xfffff000;
22608 insn |= encoded_addend;
22610 /* Update the instruction. */
22611 md_number_to_chars (buf, insn, INSN_SIZE);
22615 case BFD_RELOC_ARM_LDR_PC_G0:
22616 case BFD_RELOC_ARM_LDR_PC_G1:
22617 case BFD_RELOC_ARM_LDR_PC_G2:
22618 case BFD_RELOC_ARM_LDR_SB_G0:
22619 case BFD_RELOC_ARM_LDR_SB_G1:
22620 case BFD_RELOC_ARM_LDR_SB_G2:
22621 gas_assert (!fixP->fx_done);
22622 if (!seg->use_rela_p)
22625 bfd_vma addend_abs = abs (value);
22627 /* Check that the absolute value of the addend can be
22628 encoded in 12 bits. */
22629 if (addend_abs >= 0x1000)
22630 as_bad_where (fixP->fx_file, fixP->fx_line,
22631 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22632 (unsigned long) addend_abs);
22634 /* Extract the instruction. */
22635 insn = md_chars_to_number (buf, INSN_SIZE);
22637 /* If the addend is negative, clear bit 23 of the instruction.
22638 Otherwise set it. */
22640 insn &= ~(1 << 23);
22644 /* Place the absolute value of the addend into the first 12 bits
22645 of the instruction. */
22646 insn &= 0xfffff000;
22647 insn |= addend_abs;
22649 /* Update the instruction. */
22650 md_number_to_chars (buf, insn, INSN_SIZE);
22654 case BFD_RELOC_ARM_LDRS_PC_G0:
22655 case BFD_RELOC_ARM_LDRS_PC_G1:
22656 case BFD_RELOC_ARM_LDRS_PC_G2:
22657 case BFD_RELOC_ARM_LDRS_SB_G0:
22658 case BFD_RELOC_ARM_LDRS_SB_G1:
22659 case BFD_RELOC_ARM_LDRS_SB_G2:
22660 gas_assert (!fixP->fx_done);
22661 if (!seg->use_rela_p)
22664 bfd_vma addend_abs = abs (value);
22666 /* Check that the absolute value of the addend can be
22667 encoded in 8 bits. */
22668 if (addend_abs >= 0x100)
22669 as_bad_where (fixP->fx_file, fixP->fx_line,
22670 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22671 (unsigned long) addend_abs);
22673 /* Extract the instruction. */
22674 insn = md_chars_to_number (buf, INSN_SIZE);
22676 /* If the addend is negative, clear bit 23 of the instruction.
22677 Otherwise set it. */
22679 insn &= ~(1 << 23);
22683 /* Place the first four bits of the absolute value of the addend
22684 into the first 4 bits of the instruction, and the remaining
22685 four into bits 8 .. 11. */
22686 insn &= 0xfffff0f0;
22687 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22689 /* Update the instruction. */
22690 md_number_to_chars (buf, insn, INSN_SIZE);
22694 case BFD_RELOC_ARM_LDC_PC_G0:
22695 case BFD_RELOC_ARM_LDC_PC_G1:
22696 case BFD_RELOC_ARM_LDC_PC_G2:
22697 case BFD_RELOC_ARM_LDC_SB_G0:
22698 case BFD_RELOC_ARM_LDC_SB_G1:
22699 case BFD_RELOC_ARM_LDC_SB_G2:
22700 gas_assert (!fixP->fx_done);
22701 if (!seg->use_rela_p)
22704 bfd_vma addend_abs = abs (value);
22706 /* Check that the absolute value of the addend is a multiple of
22707 four and, when divided by four, fits in 8 bits. */
22708 if (addend_abs & 0x3)
22709 as_bad_where (fixP->fx_file, fixP->fx_line,
22710 _("bad offset 0x%08lX (must be word-aligned)"),
22711 (unsigned long) addend_abs);
22713 if ((addend_abs >> 2) > 0xff)
22714 as_bad_where (fixP->fx_file, fixP->fx_line,
22715 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22716 (unsigned long) addend_abs);
22718 /* Extract the instruction. */
22719 insn = md_chars_to_number (buf, INSN_SIZE);
22721 /* If the addend is negative, clear bit 23 of the instruction.
22722 Otherwise set it. */
22724 insn &= ~(1 << 23);
22728 /* Place the addend (divided by four) into the first eight
22729 bits of the instruction. */
22730 insn &= 0xfffffff0;
22731 insn |= addend_abs >> 2;
22733 /* Update the instruction. */
22734 md_number_to_chars (buf, insn, INSN_SIZE);
22738 case BFD_RELOC_ARM_V4BX:
22739 /* This will need to go in the object file. */
22743 case BFD_RELOC_UNUSED:
22745 as_bad_where (fixP->fx_file, fixP->fx_line,
22746 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22750 /* Translate internal representation of relocation info to BFD target
22754 tc_gen_reloc (asection *section, fixS *fixp)
22757 bfd_reloc_code_real_type code;
22759 reloc = (arelent *) xmalloc (sizeof (arelent));
22761 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
22762 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22763 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
22765 if (fixp->fx_pcrel)
22767 if (section->use_rela_p)
22768 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22770 fixp->fx_offset = reloc->address;
22772 reloc->addend = fixp->fx_offset;
22774 switch (fixp->fx_r_type)
22777 if (fixp->fx_pcrel)
22779 code = BFD_RELOC_8_PCREL;
22784 if (fixp->fx_pcrel)
22786 code = BFD_RELOC_16_PCREL;
22791 if (fixp->fx_pcrel)
22793 code = BFD_RELOC_32_PCREL;
22797 case BFD_RELOC_ARM_MOVW:
22798 if (fixp->fx_pcrel)
22800 code = BFD_RELOC_ARM_MOVW_PCREL;
22804 case BFD_RELOC_ARM_MOVT:
22805 if (fixp->fx_pcrel)
22807 code = BFD_RELOC_ARM_MOVT_PCREL;
22811 case BFD_RELOC_ARM_THUMB_MOVW:
22812 if (fixp->fx_pcrel)
22814 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22818 case BFD_RELOC_ARM_THUMB_MOVT:
22819 if (fixp->fx_pcrel)
22821 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22825 case BFD_RELOC_NONE:
22826 case BFD_RELOC_ARM_PCREL_BRANCH:
22827 case BFD_RELOC_ARM_PCREL_BLX:
22828 case BFD_RELOC_RVA:
22829 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22830 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22831 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22832 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22833 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22834 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22835 case BFD_RELOC_VTABLE_ENTRY:
22836 case BFD_RELOC_VTABLE_INHERIT:
22838 case BFD_RELOC_32_SECREL:
22840 code = fixp->fx_r_type;
22843 case BFD_RELOC_THUMB_PCREL_BLX:
22845 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22846 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22849 code = BFD_RELOC_THUMB_PCREL_BLX;
22852 case BFD_RELOC_ARM_LITERAL:
22853 case BFD_RELOC_ARM_HWLITERAL:
22854 /* If this is called then the a literal has
22855 been referenced across a section boundary. */
22856 as_bad_where (fixp->fx_file, fixp->fx_line,
22857 _("literal referenced across section boundary"));
22861 case BFD_RELOC_ARM_TLS_CALL:
22862 case BFD_RELOC_ARM_THM_TLS_CALL:
22863 case BFD_RELOC_ARM_TLS_DESCSEQ:
22864 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22865 case BFD_RELOC_ARM_GOT32:
22866 case BFD_RELOC_ARM_GOTOFF:
22867 case BFD_RELOC_ARM_GOT_PREL:
22868 case BFD_RELOC_ARM_PLT32:
22869 case BFD_RELOC_ARM_TARGET1:
22870 case BFD_RELOC_ARM_ROSEGREL32:
22871 case BFD_RELOC_ARM_SBREL32:
22872 case BFD_RELOC_ARM_PREL31:
22873 case BFD_RELOC_ARM_TARGET2:
22874 case BFD_RELOC_ARM_TLS_LE32:
22875 case BFD_RELOC_ARM_TLS_LDO32:
22876 case BFD_RELOC_ARM_PCREL_CALL:
22877 case BFD_RELOC_ARM_PCREL_JUMP:
22878 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22879 case BFD_RELOC_ARM_ALU_PC_G0:
22880 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22881 case BFD_RELOC_ARM_ALU_PC_G1:
22882 case BFD_RELOC_ARM_ALU_PC_G2:
22883 case BFD_RELOC_ARM_LDR_PC_G0:
22884 case BFD_RELOC_ARM_LDR_PC_G1:
22885 case BFD_RELOC_ARM_LDR_PC_G2:
22886 case BFD_RELOC_ARM_LDRS_PC_G0:
22887 case BFD_RELOC_ARM_LDRS_PC_G1:
22888 case BFD_RELOC_ARM_LDRS_PC_G2:
22889 case BFD_RELOC_ARM_LDC_PC_G0:
22890 case BFD_RELOC_ARM_LDC_PC_G1:
22891 case BFD_RELOC_ARM_LDC_PC_G2:
22892 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22893 case BFD_RELOC_ARM_ALU_SB_G0:
22894 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22895 case BFD_RELOC_ARM_ALU_SB_G1:
22896 case BFD_RELOC_ARM_ALU_SB_G2:
22897 case BFD_RELOC_ARM_LDR_SB_G0:
22898 case BFD_RELOC_ARM_LDR_SB_G1:
22899 case BFD_RELOC_ARM_LDR_SB_G2:
22900 case BFD_RELOC_ARM_LDRS_SB_G0:
22901 case BFD_RELOC_ARM_LDRS_SB_G1:
22902 case BFD_RELOC_ARM_LDRS_SB_G2:
22903 case BFD_RELOC_ARM_LDC_SB_G0:
22904 case BFD_RELOC_ARM_LDC_SB_G1:
22905 case BFD_RELOC_ARM_LDC_SB_G2:
22906 case BFD_RELOC_ARM_V4BX:
22907 code = fixp->fx_r_type;
22910 case BFD_RELOC_ARM_TLS_GOTDESC:
22911 case BFD_RELOC_ARM_TLS_GD32:
22912 case BFD_RELOC_ARM_TLS_IE32:
22913 case BFD_RELOC_ARM_TLS_LDM32:
22914 /* BFD will include the symbol's address in the addend.
22915 But we don't want that, so subtract it out again here. */
22916 if (!S_IS_COMMON (fixp->fx_addsy))
22917 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22918 code = fixp->fx_r_type;
22922 case BFD_RELOC_ARM_IMMEDIATE:
22923 as_bad_where (fixp->fx_file, fixp->fx_line,
22924 _("internal relocation (type: IMMEDIATE) not fixed up"));
22927 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22928 as_bad_where (fixp->fx_file, fixp->fx_line,
22929 _("ADRL used for a symbol not defined in the same file"));
22932 case BFD_RELOC_ARM_OFFSET_IMM:
22933 if (section->use_rela_p)
22935 code = fixp->fx_r_type;
22939 if (fixp->fx_addsy != NULL
22940 && !S_IS_DEFINED (fixp->fx_addsy)
22941 && S_IS_LOCAL (fixp->fx_addsy))
22943 as_bad_where (fixp->fx_file, fixp->fx_line,
22944 _("undefined local label `%s'"),
22945 S_GET_NAME (fixp->fx_addsy));
22949 as_bad_where (fixp->fx_file, fixp->fx_line,
22950 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22957 switch (fixp->fx_r_type)
22959 case BFD_RELOC_NONE: type = "NONE"; break;
22960 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22961 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22962 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22963 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22964 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22965 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22966 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22967 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22968 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22969 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22970 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22971 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22972 default: type = _("<unknown>"); break;
22974 as_bad_where (fixp->fx_file, fixp->fx_line,
22975 _("cannot represent %s relocation in this object file format"),
22982 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22984 && fixp->fx_addsy == GOT_symbol)
22986 code = BFD_RELOC_ARM_GOTPC;
22987 reloc->addend = fixp->fx_offset = reloc->address;
22991 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22993 if (reloc->howto == NULL)
22995 as_bad_where (fixp->fx_file, fixp->fx_line,
22996 _("cannot represent %s relocation in this object file format"),
22997 bfd_get_reloc_code_name (code));
23001 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23002 vtable entry to be used in the relocation's section offset. */
23003 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23004 reloc->address = fixp->fx_offset;
23009 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23012 cons_fix_new_arm (fragS * frag,
23017 bfd_reloc_code_real_type type;
23021 FIXME: @@ Should look at CPU word size. */
23025 type = BFD_RELOC_8;
23028 type = BFD_RELOC_16;
23032 type = BFD_RELOC_32;
23035 type = BFD_RELOC_64;
23040 if (exp->X_op == O_secrel)
23042 exp->X_op = O_symbol;
23043 type = BFD_RELOC_32_SECREL;
23047 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
23050 #if defined (OBJ_COFF)
23052 arm_validate_fix (fixS * fixP)
23054 /* If the destination of the branch is a defined symbol which does not have
23055 the THUMB_FUNC attribute, then we must be calling a function which has
23056 the (interfacearm) attribute. We look for the Thumb entry point to that
23057 function and change the branch to refer to that function instead. */
23058 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
23059 && fixP->fx_addsy != NULL
23060 && S_IS_DEFINED (fixP->fx_addsy)
23061 && ! THUMB_IS_FUNC (fixP->fx_addsy))
23063 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
23070 arm_force_relocation (struct fix * fixp)
23072 #if defined (OBJ_COFF) && defined (TE_PE)
23073 if (fixp->fx_r_type == BFD_RELOC_RVA)
23077 /* In case we have a call or a branch to a function in ARM ISA mode from
23078 a thumb function or vice-versa force the relocation. These relocations
23079 are cleared off for some cores that might have blx and simple transformations
23083 switch (fixp->fx_r_type)
23085 case BFD_RELOC_ARM_PCREL_JUMP:
23086 case BFD_RELOC_ARM_PCREL_CALL:
23087 case BFD_RELOC_THUMB_PCREL_BLX:
23088 if (THUMB_IS_FUNC (fixp->fx_addsy))
23092 case BFD_RELOC_ARM_PCREL_BLX:
23093 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23094 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23095 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23096 if (ARM_IS_FUNC (fixp->fx_addsy))
23105 /* Resolve these relocations even if the symbol is extern or weak.
23106 Technically this is probably wrong due to symbol preemption.
23107 In practice these relocations do not have enough range to be useful
23108 at dynamic link time, and some code (e.g. in the Linux kernel)
23109 expects these references to be resolved. */
23110 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
23111 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
23112 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
23113 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
23114 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23115 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
23116 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
23117 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
23118 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23119 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
23120 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
23121 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
23122 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
23123 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
23126 /* Always leave these relocations for the linker. */
23127 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23128 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23129 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23132 /* Always generate relocations against function symbols. */
23133 if (fixp->fx_r_type == BFD_RELOC_32
23135 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
23138 return generic_force_reloc (fixp);
23141 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23142 /* Relocations against function names must be left unadjusted,
23143 so that the linker can use this information to generate interworking
23144 stubs. The MIPS version of this function
23145 also prevents relocations that are mips-16 specific, but I do not
23146 know why it does this.
23149 There is one other problem that ought to be addressed here, but
23150 which currently is not: Taking the address of a label (rather
23151 than a function) and then later jumping to that address. Such
23152 addresses also ought to have their bottom bit set (assuming that
23153 they reside in Thumb code), but at the moment they will not. */
23156 arm_fix_adjustable (fixS * fixP)
23158 if (fixP->fx_addsy == NULL)
23161 /* Preserve relocations against symbols with function type. */
23162 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
23165 if (THUMB_IS_FUNC (fixP->fx_addsy)
23166 && fixP->fx_subsy == NULL)
23169 /* We need the symbol name for the VTABLE entries. */
23170 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23171 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23174 /* Don't allow symbols to be discarded on GOT related relocs. */
23175 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23176 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23177 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23178 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23179 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23180 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23181 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23182 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
23183 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23184 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23185 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23186 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23187 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
23188 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
23191 /* Similarly for group relocations. */
23192 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23193 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23194 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23197 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23198 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23199 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23200 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23201 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23202 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23203 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23204 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23205 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
23210 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23215 elf32_arm_target_format (void)
23218 return (target_big_endian
23219 ? "elf32-bigarm-symbian"
23220 : "elf32-littlearm-symbian");
23221 #elif defined (TE_VXWORKS)
23222 return (target_big_endian
23223 ? "elf32-bigarm-vxworks"
23224 : "elf32-littlearm-vxworks");
23225 #elif defined (TE_NACL)
23226 return (target_big_endian
23227 ? "elf32-bigarm-nacl"
23228 : "elf32-littlearm-nacl");
23230 if (target_big_endian)
23231 return "elf32-bigarm";
23233 return "elf32-littlearm";
23238 armelf_frob_symbol (symbolS * symp,
23241 elf_frob_symbol (symp, puntp);
23245 /* MD interface: Finalization. */
23250 literal_pool * pool;
23252 /* Ensure that all the IT blocks are properly closed. */
23253 check_it_blocks_finished ();
23255 for (pool = list_of_pools; pool; pool = pool->next)
23257 /* Put it at the end of the relevant section. */
23258 subseg_set (pool->section, pool->sub_section);
23260 arm_elf_change_section ();
23267 /* Remove any excess mapping symbols generated for alignment frags in
23268 SEC. We may have created a mapping symbol before a zero byte
23269 alignment; remove it if there's a mapping symbol after the
23272 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23273 void *dummy ATTRIBUTE_UNUSED)
23275 segment_info_type *seginfo = seg_info (sec);
23278 if (seginfo == NULL || seginfo->frchainP == NULL)
23281 for (fragp = seginfo->frchainP->frch_root;
23283 fragp = fragp->fr_next)
23285 symbolS *sym = fragp->tc_frag_data.last_map;
23286 fragS *next = fragp->fr_next;
23288 /* Variable-sized frags have been converted to fixed size by
23289 this point. But if this was variable-sized to start with,
23290 there will be a fixed-size frag after it. So don't handle
23292 if (sym == NULL || next == NULL)
23295 if (S_GET_VALUE (sym) < next->fr_address)
23296 /* Not at the end of this frag. */
23298 know (S_GET_VALUE (sym) == next->fr_address);
23302 if (next->tc_frag_data.first_map != NULL)
23304 /* Next frag starts with a mapping symbol. Discard this
23306 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23310 if (next->fr_next == NULL)
23312 /* This mapping symbol is at the end of the section. Discard
23314 know (next->fr_fix == 0 && next->fr_var == 0);
23315 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23319 /* As long as we have empty frags without any mapping symbols,
23321 /* If the next frag is non-empty and does not start with a
23322 mapping symbol, then this mapping symbol is required. */
23323 if (next->fr_address != next->fr_next->fr_address)
23326 next = next->fr_next;
23328 while (next != NULL);
23333 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23337 arm_adjust_symtab (void)
23342 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23344 if (ARM_IS_THUMB (sym))
23346 if (THUMB_IS_FUNC (sym))
23348 /* Mark the symbol as a Thumb function. */
23349 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23350 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23351 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
23353 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23354 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23356 as_bad (_("%s: unexpected function type: %d"),
23357 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23359 else switch (S_GET_STORAGE_CLASS (sym))
23362 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23365 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23368 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23376 if (ARM_IS_INTERWORK (sym))
23377 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
23384 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23386 if (ARM_IS_THUMB (sym))
23388 elf_symbol_type * elf_sym;
23390 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23391 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
23393 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23394 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
23396 /* If it's a .thumb_func, declare it as so,
23397 otherwise tag label as .code 16. */
23398 if (THUMB_IS_FUNC (sym))
23399 elf_sym->internal_elf_sym.st_target_internal
23400 = ST_BRANCH_TO_THUMB;
23401 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23402 elf_sym->internal_elf_sym.st_info =
23403 ELF_ST_INFO (bind, STT_ARM_16BIT);
23408 /* Remove any overlapping mapping symbols generated by alignment frags. */
23409 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
23410 /* Now do generic ELF adjustments. */
23411 elf_adjust_symtab ();
23415 /* MD interface: Initialization. */
23418 set_constant_flonums (void)
23422 for (i = 0; i < NUM_FLOAT_VALS; i++)
23423 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23427 /* Auto-select Thumb mode if it's the only available instruction set for the
23428 given architecture. */
23431 autoselect_thumb_from_cpu_variant (void)
23433 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23434 opcode_select (16);
23443 if ( (arm_ops_hsh = hash_new ()) == NULL
23444 || (arm_cond_hsh = hash_new ()) == NULL
23445 || (arm_shift_hsh = hash_new ()) == NULL
23446 || (arm_psr_hsh = hash_new ()) == NULL
23447 || (arm_v7m_psr_hsh = hash_new ()) == NULL
23448 || (arm_reg_hsh = hash_new ()) == NULL
23449 || (arm_reloc_hsh = hash_new ()) == NULL
23450 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
23451 as_fatal (_("virtual memory exhausted"));
23453 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
23454 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
23455 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
23456 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
23457 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
23458 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
23459 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
23460 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
23461 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
23462 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
23463 (void *) (v7m_psrs + i));
23464 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
23465 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
23467 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23469 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
23470 (void *) (barrier_opt_names + i));
23472 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23474 struct reloc_entry * entry = reloc_names + i;
23476 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23477 /* This makes encode_branch() use the EABI versions of this relocation. */
23478 entry->reloc = BFD_RELOC_UNUSED;
23480 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23484 set_constant_flonums ();
23486 /* Set the cpu variant based on the command-line options. We prefer
23487 -mcpu= over -march= if both are set (as for GCC); and we prefer
23488 -mfpu= over any other way of setting the floating point unit.
23489 Use of legacy options with new options are faulted. */
23492 if (mcpu_cpu_opt || march_cpu_opt)
23493 as_bad (_("use of old and new-style options to set CPU type"));
23495 mcpu_cpu_opt = legacy_cpu;
23497 else if (!mcpu_cpu_opt)
23498 mcpu_cpu_opt = march_cpu_opt;
23503 as_bad (_("use of old and new-style options to set FPU type"));
23505 mfpu_opt = legacy_fpu;
23507 else if (!mfpu_opt)
23509 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23510 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23511 /* Some environments specify a default FPU. If they don't, infer it
23512 from the processor. */
23514 mfpu_opt = mcpu_fpu_opt;
23516 mfpu_opt = march_fpu_opt;
23518 mfpu_opt = &fpu_default;
23524 if (mcpu_cpu_opt != NULL)
23525 mfpu_opt = &fpu_default;
23526 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
23527 mfpu_opt = &fpu_arch_vfp_v2;
23529 mfpu_opt = &fpu_arch_fpa;
23535 mcpu_cpu_opt = &cpu_default;
23536 selected_cpu = cpu_default;
23540 selected_cpu = *mcpu_cpu_opt;
23542 mcpu_cpu_opt = &arm_arch_any;
23545 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23547 autoselect_thumb_from_cpu_variant ();
23549 arm_arch_used = thumb_arch_used = arm_arch_none;
23551 #if defined OBJ_COFF || defined OBJ_ELF
23553 unsigned int flags = 0;
23555 #if defined OBJ_ELF
23556 flags = meabi_flags;
23558 switch (meabi_flags)
23560 case EF_ARM_EABI_UNKNOWN:
23562 /* Set the flags in the private structure. */
23563 if (uses_apcs_26) flags |= F_APCS26;
23564 if (support_interwork) flags |= F_INTERWORK;
23565 if (uses_apcs_float) flags |= F_APCS_FLOAT;
23566 if (pic_code) flags |= F_PIC;
23567 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
23568 flags |= F_SOFT_FLOAT;
23570 switch (mfloat_abi_opt)
23572 case ARM_FLOAT_ABI_SOFT:
23573 case ARM_FLOAT_ABI_SOFTFP:
23574 flags |= F_SOFT_FLOAT;
23577 case ARM_FLOAT_ABI_HARD:
23578 if (flags & F_SOFT_FLOAT)
23579 as_bad (_("hard-float conflicts with specified fpu"));
23583 /* Using pure-endian doubles (even if soft-float). */
23584 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
23585 flags |= F_VFP_FLOAT;
23587 #if defined OBJ_ELF
23588 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
23589 flags |= EF_ARM_MAVERICK_FLOAT;
23592 case EF_ARM_EABI_VER4:
23593 case EF_ARM_EABI_VER5:
23594 /* No additional flags to set. */
23601 bfd_set_private_flags (stdoutput, flags);
23603 /* We have run out flags in the COFF header to encode the
23604 status of ATPCS support, so instead we create a dummy,
23605 empty, debug section called .arm.atpcs. */
23610 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23614 bfd_set_section_flags
23615 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23616 bfd_set_section_size (stdoutput, sec, 0);
23617 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23623 /* Record the CPU type as well. */
23624 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23625 mach = bfd_mach_arm_iWMMXt2;
23626 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
23627 mach = bfd_mach_arm_iWMMXt;
23628 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
23629 mach = bfd_mach_arm_XScale;
23630 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
23631 mach = bfd_mach_arm_ep9312;
23632 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
23633 mach = bfd_mach_arm_5TE;
23634 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
23636 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23637 mach = bfd_mach_arm_5T;
23639 mach = bfd_mach_arm_5;
23641 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
23643 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23644 mach = bfd_mach_arm_4T;
23646 mach = bfd_mach_arm_4;
23648 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
23649 mach = bfd_mach_arm_3M;
23650 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23651 mach = bfd_mach_arm_3;
23652 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23653 mach = bfd_mach_arm_2a;
23654 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23655 mach = bfd_mach_arm_2;
23657 mach = bfd_mach_arm_unknown;
23659 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23662 /* Command line processing. */
23665 Invocation line includes a switch not recognized by the base assembler.
23666 See if it's a processor-specific option.
23668 This routine is somewhat complicated by the need for backwards
23669 compatibility (since older releases of gcc can't be changed).
23670 The new options try to make the interface as compatible as
23673 New options (supported) are:
23675 -mcpu=<cpu name> Assemble for selected processor
23676 -march=<architecture name> Assemble for selected architecture
23677 -mfpu=<fpu architecture> Assemble for selected FPU.
23678 -EB/-mbig-endian Big-endian
23679 -EL/-mlittle-endian Little-endian
23680 -k Generate PIC code
23681 -mthumb Start in Thumb mode
23682 -mthumb-interwork Code supports ARM/Thumb interworking
23684 -m[no-]warn-deprecated Warn about deprecated features
23686 For now we will also provide support for:
23688 -mapcs-32 32-bit Program counter
23689 -mapcs-26 26-bit Program counter
23690 -macps-float Floats passed in FP registers
23691 -mapcs-reentrant Reentrant code
23693 (sometime these will probably be replaced with -mapcs=<list of options>
23694 and -matpcs=<list of options>)
23696 The remaining options are only supported for back-wards compatibility.
23697 Cpu variants, the arm part is optional:
23698 -m[arm]1 Currently not supported.
23699 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23700 -m[arm]3 Arm 3 processor
23701 -m[arm]6[xx], Arm 6 processors
23702 -m[arm]7[xx][t][[d]m] Arm 7 processors
23703 -m[arm]8[10] Arm 8 processors
23704 -m[arm]9[20][tdmi] Arm 9 processors
23705 -mstrongarm[110[0]] StrongARM processors
23706 -mxscale XScale processors
23707 -m[arm]v[2345[t[e]]] Arm architectures
23708 -mall All (except the ARM1)
23710 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23711 -mfpe-old (No float load/store multiples)
23712 -mvfpxd VFP Single precision
23714 -mno-fpu Disable all floating point instructions
23716 The following CPU names are recognized:
23717 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23718 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23719 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23720 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23721 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23722 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23723 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23727 const char * md_shortopts = "m:k";
23729 #ifdef ARM_BI_ENDIAN
23730 #define OPTION_EB (OPTION_MD_BASE + 0)
23731 #define OPTION_EL (OPTION_MD_BASE + 1)
23733 #if TARGET_BYTES_BIG_ENDIAN
23734 #define OPTION_EB (OPTION_MD_BASE + 0)
23736 #define OPTION_EL (OPTION_MD_BASE + 1)
23739 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23741 struct option md_longopts[] =
23744 {"EB", no_argument, NULL, OPTION_EB},
23747 {"EL", no_argument, NULL, OPTION_EL},
23749 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
23750 {NULL, no_argument, NULL, 0}
23753 size_t md_longopts_size = sizeof (md_longopts);
23755 struct arm_option_table
23757 char *option; /* Option name to match. */
23758 char *help; /* Help information. */
23759 int *var; /* Variable to change. */
23760 int value; /* What to change it to. */
23761 char *deprecated; /* If non-null, print this message. */
23764 struct arm_option_table arm_opts[] =
23766 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23767 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23768 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23769 &support_interwork, 1, NULL},
23770 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23771 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23772 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23774 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23775 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23776 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23777 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23780 /* These are recognized by the assembler, but have no affect on code. */
23781 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23782 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
23784 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23785 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23786 &warn_on_deprecated, 0, NULL},
23787 {NULL, NULL, NULL, 0, NULL}
23790 struct arm_legacy_option_table
23792 char *option; /* Option name to match. */
23793 const arm_feature_set **var; /* Variable to change. */
23794 const arm_feature_set value; /* What to change it to. */
23795 char *deprecated; /* If non-null, print this message. */
23798 const struct arm_legacy_option_table arm_legacy_opts[] =
23800 /* DON'T add any new processors to this list -- we want the whole list
23801 to go away... Add them to the processors table instead. */
23802 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23803 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23804 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23805 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23806 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23807 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23808 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23809 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23810 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23811 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23812 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23813 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23814 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23815 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23816 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23817 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23818 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23819 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23820 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23821 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23822 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23823 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23824 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23825 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23826 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23827 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23828 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23829 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23830 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23831 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23832 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23833 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23834 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23835 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23836 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23837 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23838 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23839 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23840 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23841 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23842 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23843 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23844 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23845 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23846 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23847 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23848 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23849 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23850 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23851 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23852 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23853 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23854 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23855 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23856 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23857 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23858 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23859 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23860 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23861 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23862 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23863 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23864 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23865 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23866 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23867 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23868 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23869 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23870 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23871 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23872 N_("use -mcpu=strongarm110")},
23873 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23874 N_("use -mcpu=strongarm1100")},
23875 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23876 N_("use -mcpu=strongarm1110")},
23877 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23878 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23879 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23881 /* Architecture variants -- don't add any more to this list either. */
23882 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23883 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23884 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23885 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23886 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23887 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23888 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23889 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23890 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23891 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23892 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23893 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23894 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23895 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23896 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23897 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23898 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23899 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23901 /* Floating point variants -- don't add any more to this list either. */
23902 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23903 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23904 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23905 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23906 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23908 {NULL, NULL, ARM_ARCH_NONE, NULL}
23911 struct arm_cpu_option_table
23915 const arm_feature_set value;
23916 /* For some CPUs we assume an FPU unless the user explicitly sets
23918 const arm_feature_set default_fpu;
23919 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23921 const char *canonical_name;
23924 /* This list should, at a minimum, contain all the cpu names
23925 recognized by GCC. */
23926 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23927 static const struct arm_cpu_option_table arm_cpus[] =
23929 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23930 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23931 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23932 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23933 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23934 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23935 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23936 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23937 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23938 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23939 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23940 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23941 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23942 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23943 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23944 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23945 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23946 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23947 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23948 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23949 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23950 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23951 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23952 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23953 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23954 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23955 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23956 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23957 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23958 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23959 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23960 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23961 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23962 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23963 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23964 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23965 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23966 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23967 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23968 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23969 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23970 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23971 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23972 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23973 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23974 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23975 /* For V5 or later processors we default to using VFP; but the user
23976 should really set the FPU type explicitly. */
23977 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23978 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23979 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23980 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23981 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23982 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23983 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23984 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23985 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23986 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23987 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23988 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23989 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23990 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23991 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23992 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23993 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23994 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23995 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23996 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23998 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23999 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24000 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24001 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24002 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24003 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24004 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
24005 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
24006 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
24008 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
24009 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
24010 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
24011 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
24012 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
24013 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
24014 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
24015 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
24016 FPU_NONE, "Cortex-A5"),
24017 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
24019 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
24020 ARM_FEATURE (0, FPU_VFP_V3
24021 | FPU_NEON_EXT_V1),
24023 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
24024 ARM_FEATURE (0, FPU_VFP_V3
24025 | FPU_NEON_EXT_V1),
24027 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
24029 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
24031 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24033 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24035 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
24036 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
24038 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
24039 FPU_NONE, "Cortex-R5"),
24040 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
24041 FPU_ARCH_VFP_V3D16,
24043 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
24044 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
24045 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
24046 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
24047 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
24048 /* ??? XSCALE is really an architecture. */
24049 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24050 /* ??? iwmmxt is not a processor. */
24051 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
24052 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
24053 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24055 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
24056 FPU_ARCH_MAVERICK, "ARM920T"),
24057 /* Marvell processors. */
24058 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0),
24059 FPU_ARCH_VFP_V3D16, NULL),
24061 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
24065 struct arm_arch_option_table
24069 const arm_feature_set value;
24070 const arm_feature_set default_fpu;
24073 /* This list should, at a minimum, contain all the architecture names
24074 recognized by GCC. */
24075 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24076 static const struct arm_arch_option_table arm_archs[] =
24078 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
24079 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
24080 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
24081 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
24082 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
24083 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
24084 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
24085 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
24086 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
24087 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
24088 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
24089 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
24090 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
24091 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
24092 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
24093 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
24094 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
24095 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
24096 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
24097 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
24098 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
24099 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
24100 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
24101 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
24102 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
24103 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
24104 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
24105 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
24106 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
24107 /* The official spelling of the ARMv7 profile variants is the dashed form.
24108 Accept the non-dashed form for compatibility with old toolchains. */
24109 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24110 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP),
24111 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24112 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24113 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24114 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24115 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24116 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
24117 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
24118 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
24119 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
24120 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
24121 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24123 #undef ARM_ARCH_OPT
24125 /* ISA extensions in the co-processor and main instruction set space. */
24126 struct arm_option_extension_value_table
24130 const arm_feature_set value;
24131 const arm_feature_set allowed_archs;
24134 /* The following table must be in alphabetical order with a NULL last entry.
24136 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
24137 static const struct arm_option_extension_value_table arm_extensions[] =
24139 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (ARM_EXT_V8, 0)),
24140 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24141 ARM_FEATURE (ARM_EXT_V8, 0)),
24142 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
24143 ARM_FEATURE (ARM_EXT_V8, 0)),
24144 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
24145 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24146 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
24147 ARM_EXT_OPT ("iwmmxt2",
24148 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
24149 ARM_EXT_OPT ("maverick",
24150 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
24151 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
24152 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24153 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
24154 ARM_FEATURE (ARM_EXT_V8, 0)),
24155 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
24156 ARM_FEATURE (ARM_EXT_V6M, 0)),
24157 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
24158 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
24159 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
24161 ARM_FEATURE (ARM_EXT_V7A, 0)),
24162 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24163 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24167 /* ISA floating-point and Advanced SIMD extensions. */
24168 struct arm_option_fpu_value_table
24171 const arm_feature_set value;
24174 /* This list should, at a minimum, contain all the fpu names
24175 recognized by GCC. */
24176 static const struct arm_option_fpu_value_table arm_fpus[] =
24178 {"softfpa", FPU_NONE},
24179 {"fpe", FPU_ARCH_FPE},
24180 {"fpe2", FPU_ARCH_FPE},
24181 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24182 {"fpa", FPU_ARCH_FPA},
24183 {"fpa10", FPU_ARCH_FPA},
24184 {"fpa11", FPU_ARCH_FPA},
24185 {"arm7500fe", FPU_ARCH_FPA},
24186 {"softvfp", FPU_ARCH_VFP},
24187 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24188 {"vfp", FPU_ARCH_VFP_V2},
24189 {"vfp9", FPU_ARCH_VFP_V2},
24190 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
24191 {"vfp10", FPU_ARCH_VFP_V2},
24192 {"vfp10-r0", FPU_ARCH_VFP_V1},
24193 {"vfpxd", FPU_ARCH_VFP_V1xD},
24194 {"vfpv2", FPU_ARCH_VFP_V2},
24195 {"vfpv3", FPU_ARCH_VFP_V3},
24196 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
24197 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
24198 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24199 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24200 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
24201 {"arm1020t", FPU_ARCH_VFP_V1},
24202 {"arm1020e", FPU_ARCH_VFP_V2},
24203 {"arm1136jfs", FPU_ARCH_VFP_V2},
24204 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24205 {"maverick", FPU_ARCH_MAVERICK},
24206 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
24207 {"neon-fp16", FPU_ARCH_NEON_FP16},
24208 {"vfpv4", FPU_ARCH_VFP_V4},
24209 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
24210 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
24211 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
24212 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24213 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24214 {"crypto-neon-fp-armv8",
24215 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
24216 {NULL, ARM_ARCH_NONE}
24219 struct arm_option_value_table
24225 static const struct arm_option_value_table arm_float_abis[] =
24227 {"hard", ARM_FLOAT_ABI_HARD},
24228 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24229 {"soft", ARM_FLOAT_ABI_SOFT},
24234 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24235 static const struct arm_option_value_table arm_eabis[] =
24237 {"gnu", EF_ARM_EABI_UNKNOWN},
24238 {"4", EF_ARM_EABI_VER4},
24239 {"5", EF_ARM_EABI_VER5},
24244 struct arm_long_option_table
24246 char * option; /* Substring to match. */
24247 char * help; /* Help information. */
24248 int (* func) (char * subopt); /* Function to decode sub-option. */
24249 char * deprecated; /* If non-null, print this message. */
24253 arm_parse_extension (char *str, const arm_feature_set **opt_p)
24255 arm_feature_set *ext_set = (arm_feature_set *)
24256 xmalloc (sizeof (arm_feature_set));
24258 /* We insist on extensions being specified in alphabetical order, and with
24259 extensions being added before being removed. We achieve this by having
24260 the global ARM_EXTENSIONS table in alphabetical order, and using the
24261 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24262 or removing it (0) and only allowing it to change in the order
24264 const struct arm_option_extension_value_table * opt = NULL;
24265 int adding_value = -1;
24267 /* Copy the feature set, so that we can modify it. */
24268 *ext_set = **opt_p;
24271 while (str != NULL && *str != 0)
24278 as_bad (_("invalid architectural extension"));
24283 ext = strchr (str, '+');
24288 len = strlen (str);
24290 if (len >= 2 && strncmp (str, "no", 2) == 0)
24292 if (adding_value != 0)
24295 opt = arm_extensions;
24303 if (adding_value == -1)
24306 opt = arm_extensions;
24308 else if (adding_value != 1)
24310 as_bad (_("must specify extensions to add before specifying "
24311 "those to remove"));
24318 as_bad (_("missing architectural extension"));
24322 gas_assert (adding_value != -1);
24323 gas_assert (opt != NULL);
24325 /* Scan over the options table trying to find an exact match. */
24326 for (; opt->name != NULL; opt++)
24327 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24329 /* Check we can apply the extension to this architecture. */
24330 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24332 as_bad (_("extension does not apply to the base architecture"));
24336 /* Add or remove the extension. */
24338 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
24340 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
24345 if (opt->name == NULL)
24347 /* Did we fail to find an extension because it wasn't specified in
24348 alphabetical order, or because it does not exist? */
24350 for (opt = arm_extensions; opt->name != NULL; opt++)
24351 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24354 if (opt->name == NULL)
24355 as_bad (_("unknown architectural extension `%s'"), str);
24357 as_bad (_("architectural extensions must be specified in "
24358 "alphabetical order"));
24364 /* We should skip the extension we've just matched the next time
24376 arm_parse_cpu (char *str)
24378 const struct arm_cpu_option_table *opt;
24379 char *ext = strchr (str, '+');
24385 len = strlen (str);
24389 as_bad (_("missing cpu name `%s'"), str);
24393 for (opt = arm_cpus; opt->name != NULL; opt++)
24394 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24396 mcpu_cpu_opt = &opt->value;
24397 mcpu_fpu_opt = &opt->default_fpu;
24398 if (opt->canonical_name)
24399 strcpy (selected_cpu_name, opt->canonical_name);
24404 for (i = 0; i < len; i++)
24405 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24406 selected_cpu_name[i] = 0;
24410 return arm_parse_extension (ext, &mcpu_cpu_opt);
24415 as_bad (_("unknown cpu `%s'"), str);
24420 arm_parse_arch (char *str)
24422 const struct arm_arch_option_table *opt;
24423 char *ext = strchr (str, '+');
24429 len = strlen (str);
24433 as_bad (_("missing architecture name `%s'"), str);
24437 for (opt = arm_archs; opt->name != NULL; opt++)
24438 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24440 march_cpu_opt = &opt->value;
24441 march_fpu_opt = &opt->default_fpu;
24442 strcpy (selected_cpu_name, opt->name);
24445 return arm_parse_extension (ext, &march_cpu_opt);
24450 as_bad (_("unknown architecture `%s'\n"), str);
24455 arm_parse_fpu (char * str)
24457 const struct arm_option_fpu_value_table * opt;
24459 for (opt = arm_fpus; opt->name != NULL; opt++)
24460 if (streq (opt->name, str))
24462 mfpu_opt = &opt->value;
24466 as_bad (_("unknown floating point format `%s'\n"), str);
24471 arm_parse_float_abi (char * str)
24473 const struct arm_option_value_table * opt;
24475 for (opt = arm_float_abis; opt->name != NULL; opt++)
24476 if (streq (opt->name, str))
24478 mfloat_abi_opt = opt->value;
24482 as_bad (_("unknown floating point abi `%s'\n"), str);
24488 arm_parse_eabi (char * str)
24490 const struct arm_option_value_table *opt;
24492 for (opt = arm_eabis; opt->name != NULL; opt++)
24493 if (streq (opt->name, str))
24495 meabi_flags = opt->value;
24498 as_bad (_("unknown EABI `%s'\n"), str);
24504 arm_parse_it_mode (char * str)
24506 bfd_boolean ret = TRUE;
24508 if (streq ("arm", str))
24509 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24510 else if (streq ("thumb", str))
24511 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24512 else if (streq ("always", str))
24513 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24514 else if (streq ("never", str))
24515 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24518 as_bad (_("unknown implicit IT mode `%s', should be "\
24519 "arm, thumb, always, or never."), str);
24526 struct arm_long_option_table arm_long_opts[] =
24528 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24529 arm_parse_cpu, NULL},
24530 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24531 arm_parse_arch, NULL},
24532 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24533 arm_parse_fpu, NULL},
24534 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24535 arm_parse_float_abi, NULL},
24537 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24538 arm_parse_eabi, NULL},
24540 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24541 arm_parse_it_mode, NULL},
24542 {NULL, NULL, 0, NULL}
24546 md_parse_option (int c, char * arg)
24548 struct arm_option_table *opt;
24549 const struct arm_legacy_option_table *fopt;
24550 struct arm_long_option_table *lopt;
24556 target_big_endian = 1;
24562 target_big_endian = 0;
24566 case OPTION_FIX_V4BX:
24571 /* Listing option. Just ignore these, we don't support additional
24576 for (opt = arm_opts; opt->option != NULL; opt++)
24578 if (c == opt->option[0]
24579 && ((arg == NULL && opt->option[1] == 0)
24580 || streq (arg, opt->option + 1)))
24582 /* If the option is deprecated, tell the user. */
24583 if (warn_on_deprecated && opt->deprecated != NULL)
24584 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24585 arg ? arg : "", _(opt->deprecated));
24587 if (opt->var != NULL)
24588 *opt->var = opt->value;
24594 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
24596 if (c == fopt->option[0]
24597 && ((arg == NULL && fopt->option[1] == 0)
24598 || streq (arg, fopt->option + 1)))
24600 /* If the option is deprecated, tell the user. */
24601 if (warn_on_deprecated && fopt->deprecated != NULL)
24602 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24603 arg ? arg : "", _(fopt->deprecated));
24605 if (fopt->var != NULL)
24606 *fopt->var = &fopt->value;
24612 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24614 /* These options are expected to have an argument. */
24615 if (c == lopt->option[0]
24617 && strncmp (arg, lopt->option + 1,
24618 strlen (lopt->option + 1)) == 0)
24620 /* If the option is deprecated, tell the user. */
24621 if (warn_on_deprecated && lopt->deprecated != NULL)
24622 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24623 _(lopt->deprecated));
24625 /* Call the sup-option parser. */
24626 return lopt->func (arg + strlen (lopt->option) - 1);
24637 md_show_usage (FILE * fp)
24639 struct arm_option_table *opt;
24640 struct arm_long_option_table *lopt;
24642 fprintf (fp, _(" ARM-specific assembler options:\n"));
24644 for (opt = arm_opts; opt->option != NULL; opt++)
24645 if (opt->help != NULL)
24646 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
24648 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24649 if (lopt->help != NULL)
24650 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
24654 -EB assemble code for a big-endian cpu\n"));
24659 -EL assemble code for a little-endian cpu\n"));
24663 --fix-v4bx Allow BX in ARMv4 code\n"));
24671 arm_feature_set flags;
24672 } cpu_arch_ver_table;
24674 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24675 least features first. */
24676 static const cpu_arch_ver_table cpu_arch_ver[] =
24682 {4, ARM_ARCH_V5TE},
24683 {5, ARM_ARCH_V5TEJ},
24687 {11, ARM_ARCH_V6M},
24688 {12, ARM_ARCH_V6SM},
24689 {8, ARM_ARCH_V6T2},
24690 {10, ARM_ARCH_V7VE},
24691 {10, ARM_ARCH_V7R},
24692 {10, ARM_ARCH_V7M},
24693 {14, ARM_ARCH_V8A},
24697 /* Set an attribute if it has not already been set by the user. */
24699 aeabi_set_attribute_int (int tag, int value)
24702 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24703 || !attributes_set_explicitly[tag])
24704 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24708 aeabi_set_attribute_string (int tag, const char *value)
24711 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24712 || !attributes_set_explicitly[tag])
24713 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24716 /* Set the public EABI object attributes. */
24718 aeabi_set_public_attributes (void)
24723 int fp16_optional = 0;
24724 arm_feature_set flags;
24725 arm_feature_set tmp;
24726 const cpu_arch_ver_table *p;
24728 /* Choose the architecture based on the capabilities of the requested cpu
24729 (if any) and/or the instructions actually used. */
24730 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24731 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24732 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
24734 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24735 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24737 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24738 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24740 /* Allow the user to override the reported architecture. */
24743 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24744 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24747 /* We need to make sure that the attributes do not identify us as v6S-M
24748 when the only v6S-M feature in use is the Operating System Extensions. */
24749 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24750 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
24751 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
24755 for (p = cpu_arch_ver; p->val; p++)
24757 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24760 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24764 /* The table lookup above finds the last architecture to contribute
24765 a new feature. Unfortunately, Tag13 is a subset of the union of
24766 v6T2 and v7-M, so it is never seen as contributing a new feature.
24767 We can not search for the last entry which is entirely used,
24768 because if no CPU is specified we build up only those flags
24769 actually used. Perhaps we should separate out the specified
24770 and implicit cases. Avoid taking this path for -march=all by
24771 checking for contradictory v7-A / v7-M features. */
24773 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24774 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24775 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24778 /* Tag_CPU_name. */
24779 if (selected_cpu_name[0])
24783 q = selected_cpu_name;
24784 if (strncmp (q, "armv", 4) == 0)
24789 for (i = 0; q[i]; i++)
24790 q[i] = TOUPPER (q[i]);
24792 aeabi_set_attribute_string (Tag_CPU_name, q);
24795 /* Tag_CPU_arch. */
24796 aeabi_set_attribute_int (Tag_CPU_arch, arch);
24798 /* Tag_CPU_arch_profile. */
24799 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
24801 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
24803 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
24808 if (profile != '\0')
24809 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
24811 /* Tag_ARM_ISA_use. */
24812 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24814 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
24816 /* Tag_THUMB_ISA_use. */
24817 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24819 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24820 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
24822 /* Tag_VFP_arch. */
24823 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24824 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24825 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
24826 aeabi_set_attribute_int (Tag_VFP_arch,
24827 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24829 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
24832 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24834 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
24836 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24839 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24840 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24841 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24842 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24843 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24845 /* Tag_ABI_HardFP_use. */
24846 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24847 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24848 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24850 /* Tag_WMMX_arch. */
24851 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24852 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24853 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24854 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24856 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24857 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24858 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24859 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24861 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24863 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24867 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24872 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24873 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24874 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24878 We set Tag_DIV_use to two when integer divide instructions have been used
24879 in ARM state, or when Thumb integer divide instructions have been used,
24880 but we have no architecture profile set, nor have we any ARM instructions.
24882 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24885 For new architectures we will have to check these tests. */
24886 gas_assert (arch <= TAG_CPU_ARCH_V8);
24887 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24888 aeabi_set_attribute_int (Tag_DIV_use, 0);
24889 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24890 || (profile == '\0'
24891 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24892 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24893 aeabi_set_attribute_int (Tag_DIV_use, 2);
24895 /* Tag_MP_extension_use. */
24896 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24897 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24899 /* Tag Virtualization_use. */
24900 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24902 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24905 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24908 /* Add the default contents for the .ARM.attributes section. */
24912 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24915 aeabi_set_public_attributes ();
24917 #endif /* OBJ_ELF */
24920 /* Parse a .cpu directive. */
24923 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24925 const struct arm_cpu_option_table *opt;
24929 name = input_line_pointer;
24930 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24931 input_line_pointer++;
24932 saved_char = *input_line_pointer;
24933 *input_line_pointer = 0;
24935 /* Skip the first "all" entry. */
24936 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24937 if (streq (opt->name, name))
24939 mcpu_cpu_opt = &opt->value;
24940 selected_cpu = opt->value;
24941 if (opt->canonical_name)
24942 strcpy (selected_cpu_name, opt->canonical_name);
24946 for (i = 0; opt->name[i]; i++)
24947 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24949 selected_cpu_name[i] = 0;
24951 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24952 *input_line_pointer = saved_char;
24953 demand_empty_rest_of_line ();
24956 as_bad (_("unknown cpu `%s'"), name);
24957 *input_line_pointer = saved_char;
24958 ignore_rest_of_line ();
24962 /* Parse a .arch directive. */
24965 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24967 const struct arm_arch_option_table *opt;
24971 name = input_line_pointer;
24972 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24973 input_line_pointer++;
24974 saved_char = *input_line_pointer;
24975 *input_line_pointer = 0;
24977 /* Skip the first "all" entry. */
24978 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24979 if (streq (opt->name, name))
24981 mcpu_cpu_opt = &opt->value;
24982 selected_cpu = opt->value;
24983 strcpy (selected_cpu_name, opt->name);
24984 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24985 *input_line_pointer = saved_char;
24986 demand_empty_rest_of_line ();
24990 as_bad (_("unknown architecture `%s'\n"), name);
24991 *input_line_pointer = saved_char;
24992 ignore_rest_of_line ();
24996 /* Parse a .object_arch directive. */
24999 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
25001 const struct arm_arch_option_table *opt;
25005 name = input_line_pointer;
25006 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25007 input_line_pointer++;
25008 saved_char = *input_line_pointer;
25009 *input_line_pointer = 0;
25011 /* Skip the first "all" entry. */
25012 for (opt = arm_archs + 1; opt->name != NULL; opt++)
25013 if (streq (opt->name, name))
25015 object_arch = &opt->value;
25016 *input_line_pointer = saved_char;
25017 demand_empty_rest_of_line ();
25021 as_bad (_("unknown architecture `%s'\n"), name);
25022 *input_line_pointer = saved_char;
25023 ignore_rest_of_line ();
25026 /* Parse a .arch_extension directive. */
25029 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
25031 const struct arm_option_extension_value_table *opt;
25034 int adding_value = 1;
25036 name = input_line_pointer;
25037 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25038 input_line_pointer++;
25039 saved_char = *input_line_pointer;
25040 *input_line_pointer = 0;
25042 if (strlen (name) >= 2
25043 && strncmp (name, "no", 2) == 0)
25049 for (opt = arm_extensions; opt->name != NULL; opt++)
25050 if (streq (opt->name, name))
25052 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
25054 as_bad (_("architectural extension `%s' is not allowed for the "
25055 "current base architecture"), name);
25060 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
25062 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
25064 mcpu_cpu_opt = &selected_cpu;
25065 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25066 *input_line_pointer = saved_char;
25067 demand_empty_rest_of_line ();
25071 if (opt->name == NULL)
25072 as_bad (_("unknown architecture extension `%s'\n"), name);
25074 *input_line_pointer = saved_char;
25075 ignore_rest_of_line ();
25078 /* Parse a .fpu directive. */
25081 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
25083 const struct arm_option_fpu_value_table *opt;
25087 name = input_line_pointer;
25088 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25089 input_line_pointer++;
25090 saved_char = *input_line_pointer;
25091 *input_line_pointer = 0;
25093 for (opt = arm_fpus; opt->name != NULL; opt++)
25094 if (streq (opt->name, name))
25096 mfpu_opt = &opt->value;
25097 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25098 *input_line_pointer = saved_char;
25099 demand_empty_rest_of_line ();
25103 as_bad (_("unknown floating point format `%s'\n"), name);
25104 *input_line_pointer = saved_char;
25105 ignore_rest_of_line ();
25108 /* Copy symbol information. */
25111 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
25113 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
25117 /* Given a symbolic attribute NAME, return the proper integer value.
25118 Returns -1 if the attribute is not known. */
25121 arm_convert_symbolic_attribute (const char *name)
25123 static const struct
25128 attribute_table[] =
25130 /* When you modify this table you should
25131 also modify the list in doc/c-arm.texi. */
25132 #define T(tag) {#tag, tag}
25133 T (Tag_CPU_raw_name),
25136 T (Tag_CPU_arch_profile),
25137 T (Tag_ARM_ISA_use),
25138 T (Tag_THUMB_ISA_use),
25142 T (Tag_Advanced_SIMD_arch),
25143 T (Tag_PCS_config),
25144 T (Tag_ABI_PCS_R9_use),
25145 T (Tag_ABI_PCS_RW_data),
25146 T (Tag_ABI_PCS_RO_data),
25147 T (Tag_ABI_PCS_GOT_use),
25148 T (Tag_ABI_PCS_wchar_t),
25149 T (Tag_ABI_FP_rounding),
25150 T (Tag_ABI_FP_denormal),
25151 T (Tag_ABI_FP_exceptions),
25152 T (Tag_ABI_FP_user_exceptions),
25153 T (Tag_ABI_FP_number_model),
25154 T (Tag_ABI_align_needed),
25155 T (Tag_ABI_align8_needed),
25156 T (Tag_ABI_align_preserved),
25157 T (Tag_ABI_align8_preserved),
25158 T (Tag_ABI_enum_size),
25159 T (Tag_ABI_HardFP_use),
25160 T (Tag_ABI_VFP_args),
25161 T (Tag_ABI_WMMX_args),
25162 T (Tag_ABI_optimization_goals),
25163 T (Tag_ABI_FP_optimization_goals),
25164 T (Tag_compatibility),
25165 T (Tag_CPU_unaligned_access),
25166 T (Tag_FP_HP_extension),
25167 T (Tag_VFP_HP_extension),
25168 T (Tag_ABI_FP_16bit_format),
25169 T (Tag_MPextension_use),
25171 T (Tag_nodefaults),
25172 T (Tag_also_compatible_with),
25173 T (Tag_conformance),
25175 T (Tag_Virtualization_use),
25176 /* We deliberately do not include Tag_MPextension_use_legacy. */
25184 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
25185 if (streq (name, attribute_table[i].name))
25186 return attribute_table[i].tag;
25192 /* Apply sym value for relocations only in the case that
25193 they are for local symbols and you have the respective
25194 architectural feature for blx and simple switches. */
25196 arm_apply_sym_value (struct fix * fixP)
25199 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
25200 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
25202 switch (fixP->fx_r_type)
25204 case BFD_RELOC_ARM_PCREL_BLX:
25205 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25206 if (ARM_IS_FUNC (fixP->fx_addsy))
25210 case BFD_RELOC_ARM_PCREL_CALL:
25211 case BFD_RELOC_THUMB_PCREL_BLX:
25212 if (THUMB_IS_FUNC (fixP->fx_addsy))
25223 #endif /* OBJ_ELF */