1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
201 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
202 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
203 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
204 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
206 static const arm_feature_set arm_arch_any = ARM_ANY;
207 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
209 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
210 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
212 static const arm_feature_set arm_cext_iwmmxt2 =
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
214 static const arm_feature_set arm_cext_iwmmxt =
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
216 static const arm_feature_set arm_cext_xscale =
217 ARM_FEATURE (0, ARM_CEXT_XSCALE);
218 static const arm_feature_set arm_cext_maverick =
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
220 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
221 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
222 static const arm_feature_set fpu_vfp_ext_v1xd =
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
224 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
225 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
226 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
227 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
228 static const arm_feature_set fpu_vfp_ext_d32 =
229 ARM_FEATURE (0, FPU_VFP_EXT_D32);
230 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
233 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
234 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static int mfloat_abi_opt = -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu.core == arm_arch_none.core
248 && selected_cpu.coproc == arm_arch_none.coproc;
253 static int meabi_flags = EABI_DEFAULT;
255 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
258 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
263 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS * GOT_symbol;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode = 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER = 0x00,
286 IMPLICIT_IT_MODE_ARM = 0x01,
287 IMPLICIT_IT_MODE_THUMB = 0x02,
288 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
290 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax = FALSE;
330 enum neon_el_type type;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el[NEON_MAX_TYPE_ELS];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN /* The IT insn has been parsed. */
357 unsigned long instruction;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type;
379 enum it_instruction_type it_insn_type;
385 struct neon_type_el vectype;
386 unsigned present : 1; /* Operand present. */
387 unsigned isreg : 1; /* Operand was a register. */
388 unsigned immisreg : 1; /* .imm field is a second register. */
389 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle : 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc : 1; /* Operand has relocation suffix. */
399 unsigned writeback : 1; /* Operand has trailing ! */
400 unsigned preind : 1; /* Preindexed address. */
401 unsigned postind : 1; /* Postindexed address. */
402 unsigned negative : 1; /* Index register was negated. */
403 unsigned shifted : 1; /* Shift applied to operation. */
404 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name;
444 #define COND_ALWAYS 0xE
448 const char * template_name;
452 struct asm_barrier_opt
454 const char * template_name;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc;
475 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
476 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
481 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined;
492 struct neon_type_el eltype;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin;
533 struct neon_typed_alias * neon;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name;
576 /* Parameters to instruction. */
577 unsigned int operands[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag : 4;
582 /* Basic instruction code. */
583 unsigned int avalue : 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set * avariant;
590 const arm_feature_set * tvariant;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
727 #define BAD_RANGE _("branch out of range")
729 static struct hash_control * arm_ops_hsh;
730 static struct hash_control * arm_cond_hsh;
731 static struct hash_control * arm_shift_hsh;
732 static struct hash_control * arm_psr_hsh;
733 static struct hash_control * arm_v7m_psr_hsh;
734 static struct hash_control * arm_reg_hsh;
735 static struct hash_control * arm_reloc_hsh;
736 static struct hash_control * arm_barrier_opt_hsh;
738 /* Stuff needed to resolve the label ambiguity
747 symbolS * last_label_seen;
748 static int label_is_thumb_function_name = FALSE;
750 /* Literal pool structure. Held on a per-section
751 and per-sub-section basis. */
753 #define MAX_LITERAL_POOL_SIZE 1024
754 typedef struct literal_pool
756 expressionS literals [MAX_LITERAL_POOL_SIZE];
757 unsigned int next_free_entry;
763 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
765 struct literal_pool * next;
768 /* Pointer to a linked list of literal pools. */
769 literal_pool * list_of_pools = NULL;
772 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
774 static struct current_it now_it;
778 now_it_compatible (int cond)
780 return (cond & ~1) == (now_it.cc & ~1);
784 conditional_insn (void)
786 return inst.cond != COND_ALWAYS;
789 static int in_it_block (void);
791 static int handle_it_state (void);
793 static void force_automatic_it_block_close (void);
795 static void it_fsm_post_encode (void);
797 #define set_it_insn_type(type) \
800 inst.it_insn_type = type; \
801 if (handle_it_state () == FAIL) \
806 #define set_it_insn_type_nonvoid(type, failret) \
809 inst.it_insn_type = type; \
810 if (handle_it_state () == FAIL) \
815 #define set_it_insn_type_last() \
818 if (inst.cond == COND_ALWAYS) \
819 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
821 set_it_insn_type (INSIDE_IT_LAST_INSN); \
827 /* This array holds the chars that always start a comment. If the
828 pre-processor is disabled, these aren't very useful. */
829 const char comment_chars[] = "@";
831 /* This array holds the chars that only start a comment at the beginning of
832 a line. If the line seems to have the form '# 123 filename'
833 .line and .file directives will appear in the pre-processed output. */
834 /* Note that input_file.c hand checks for '#' at the beginning of the
835 first line of the input file. This is because the compiler outputs
836 #NO_APP at the beginning of its output. */
837 /* Also note that comments like this one will always work. */
838 const char line_comment_chars[] = "#";
840 const char line_separator_chars[] = ";";
842 /* Chars that can be used to separate mant
843 from exp in floating point numbers. */
844 const char EXP_CHARS[] = "eE";
846 /* Chars that mean this number is a floating point constant. */
850 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
852 /* Prefix characters that indicate the start of an immediate
854 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
856 /* Separator character handling. */
858 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
861 skip_past_char (char ** str, char c)
872 #define skip_past_comma(str) skip_past_char (str, ',')
874 /* Arithmetic expressions (possibly involving symbols). */
876 /* Return TRUE if anything in the expression is a bignum. */
879 walk_no_bignums (symbolS * sp)
881 if (symbol_get_value_expression (sp)->X_op == O_big)
884 if (symbol_get_value_expression (sp)->X_add_symbol)
886 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
887 || (symbol_get_value_expression (sp)->X_op_symbol
888 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
894 static int in_my_get_expression = 0;
896 /* Third argument to my_get_expression. */
897 #define GE_NO_PREFIX 0
898 #define GE_IMM_PREFIX 1
899 #define GE_OPT_PREFIX 2
900 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
901 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
902 #define GE_OPT_PREFIX_BIG 3
905 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
910 /* In unified syntax, all prefixes are optional. */
912 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
917 case GE_NO_PREFIX: break;
919 if (!is_immediate_prefix (**str))
921 inst.error = _("immediate expression requires a # prefix");
927 case GE_OPT_PREFIX_BIG:
928 if (is_immediate_prefix (**str))
934 memset (ep, 0, sizeof (expressionS));
936 save_in = input_line_pointer;
937 input_line_pointer = *str;
938 in_my_get_expression = 1;
939 seg = expression (ep);
940 in_my_get_expression = 0;
942 if (ep->X_op == O_illegal || ep->X_op == O_absent)
944 /* We found a bad or missing expression in md_operand(). */
945 *str = input_line_pointer;
946 input_line_pointer = save_in;
947 if (inst.error == NULL)
948 inst.error = (ep->X_op == O_absent
949 ? _("missing expression") :_("bad expression"));
954 if (seg != absolute_section
955 && seg != text_section
956 && seg != data_section
957 && seg != bss_section
958 && seg != undefined_section)
960 inst.error = _("bad segment");
961 *str = input_line_pointer;
962 input_line_pointer = save_in;
969 /* Get rid of any bignums now, so that we don't generate an error for which
970 we can't establish a line number later on. Big numbers are never valid
971 in instructions, which is where this routine is always called. */
972 if (prefix_mode != GE_OPT_PREFIX_BIG
973 && (ep->X_op == O_big
975 && (walk_no_bignums (ep->X_add_symbol)
977 && walk_no_bignums (ep->X_op_symbol))))))
979 inst.error = _("invalid constant");
980 *str = input_line_pointer;
981 input_line_pointer = save_in;
985 *str = input_line_pointer;
986 input_line_pointer = save_in;
990 /* Turn a string in input_line_pointer into a floating point constant
991 of type TYPE, and store the appropriate bytes in *LITP. The number
992 of LITTLENUMS emitted is stored in *SIZEP. An error message is
993 returned, or NULL on OK.
995 Note that fp constants aren't represent in the normal way on the ARM.
996 In big endian mode, things are as expected. However, in little endian
997 mode fp constants are big-endian word-wise, and little-endian byte-wise
998 within the words. For example, (double) 1.1 in big endian mode is
999 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1000 the byte sequence 99 99 f1 3f 9a 99 99 99.
1002 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1005 md_atof (int type, char * litP, int * sizeP)
1008 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1040 return _("Unrecognized or unsupported floating point constant");
1043 t = atof_ieee (input_line_pointer, type, words);
1045 input_line_pointer = t;
1046 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1048 if (target_big_endian)
1050 for (i = 0; i < prec; i++)
1052 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1053 litP += sizeof (LITTLENUM_TYPE);
1058 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1059 for (i = prec - 1; i >= 0; i--)
1061 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1062 litP += sizeof (LITTLENUM_TYPE);
1065 /* For a 4 byte float the order of elements in `words' is 1 0.
1066 For an 8 byte float the order is 1 0 3 2. */
1067 for (i = 0; i < prec; i += 2)
1069 md_number_to_chars (litP, (valueT) words[i + 1],
1070 sizeof (LITTLENUM_TYPE));
1071 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1072 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1073 litP += 2 * sizeof (LITTLENUM_TYPE);
1080 /* We handle all bad expressions here, so that we can report the faulty
1081 instruction in the error message. */
1083 md_operand (expressionS * exp)
1085 if (in_my_get_expression)
1086 exp->X_op = O_illegal;
1089 /* Immediate values. */
1091 /* Generic immediate-value read function for use in directives.
1092 Accepts anything that 'expression' can fold to a constant.
1093 *val receives the number. */
1096 immediate_for_directive (int *val)
1099 exp.X_op = O_illegal;
1101 if (is_immediate_prefix (*input_line_pointer))
1103 input_line_pointer++;
1107 if (exp.X_op != O_constant)
1109 as_bad (_("expected #constant"));
1110 ignore_rest_of_line ();
1113 *val = exp.X_add_number;
1118 /* Register parsing. */
1120 /* Generic register parser. CCP points to what should be the
1121 beginning of a register name. If it is indeed a valid register
1122 name, advance CCP over it and return the reg_entry structure;
1123 otherwise return NULL. Does not issue diagnostics. */
1125 static struct reg_entry *
1126 arm_reg_parse_multi (char **ccp)
1130 struct reg_entry *reg;
1132 #ifdef REGISTER_PREFIX
1133 if (*start != REGISTER_PREFIX)
1137 #ifdef OPTIONAL_REGISTER_PREFIX
1138 if (*start == OPTIONAL_REGISTER_PREFIX)
1143 if (!ISALPHA (*p) || !is_name_beginner (*p))
1148 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1150 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1160 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1161 enum arm_reg_type type)
1163 /* Alternative syntaxes are accepted for a few register classes. */
1170 /* Generic coprocessor register names are allowed for these. */
1171 if (reg && reg->type == REG_TYPE_CN)
1176 /* For backward compatibility, a bare number is valid here. */
1178 unsigned long processor = strtoul (start, ccp, 10);
1179 if (*ccp != start && processor <= 15)
1183 case REG_TYPE_MMXWC:
1184 /* WC includes WCG. ??? I'm not sure this is true for all
1185 instructions that take WC registers. */
1186 if (reg && reg->type == REG_TYPE_MMXWCG)
1197 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1198 return value is the register number or FAIL. */
1201 arm_reg_parse (char **ccp, enum arm_reg_type type)
1204 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1207 /* Do not allow a scalar (reg+index) to parse as a register. */
1208 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1211 if (reg && reg->type == type)
1214 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1221 /* Parse a Neon type specifier. *STR should point at the leading '.'
1222 character. Does no verification at this stage that the type fits the opcode
1229 Can all be legally parsed by this function.
1231 Fills in neon_type struct pointer with parsed information, and updates STR
1232 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1233 type, FAIL if not. */
1236 parse_neon_type (struct neon_type *type, char **str)
1243 while (type->elems < NEON_MAX_TYPE_ELS)
1245 enum neon_el_type thistype = NT_untyped;
1246 unsigned thissize = -1u;
1253 /* Just a size without an explicit type. */
1257 switch (TOLOWER (*ptr))
1259 case 'i': thistype = NT_integer; break;
1260 case 'f': thistype = NT_float; break;
1261 case 'p': thistype = NT_poly; break;
1262 case 's': thistype = NT_signed; break;
1263 case 'u': thistype = NT_unsigned; break;
1265 thistype = NT_float;
1270 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1276 /* .f is an abbreviation for .f32. */
1277 if (thistype == NT_float && !ISDIGIT (*ptr))
1282 thissize = strtoul (ptr, &ptr, 10);
1284 if (thissize != 8 && thissize != 16 && thissize != 32
1287 as_bad (_("bad size %d in type specifier"), thissize);
1295 type->el[type->elems].type = thistype;
1296 type->el[type->elems].size = thissize;
1301 /* Empty/missing type is not a successful parse. */
1302 if (type->elems == 0)
1310 /* Errors may be set multiple times during parsing or bit encoding
1311 (particularly in the Neon bits), but usually the earliest error which is set
1312 will be the most meaningful. Avoid overwriting it with later (cascading)
1313 errors by calling this function. */
1316 first_error (const char *err)
1322 /* Parse a single type, e.g. ".s32", leading period included. */
1324 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1327 struct neon_type optype;
1331 if (parse_neon_type (&optype, &str) == SUCCESS)
1333 if (optype.elems == 1)
1334 *vectype = optype.el[0];
1337 first_error (_("only one type should be specified for operand"));
1343 first_error (_("vector type expected"));
1355 /* Special meanings for indices (which have a range of 0-7), which will fit into
1358 #define NEON_ALL_LANES 15
1359 #define NEON_INTERLEAVE_LANES 14
1361 /* Parse either a register or a scalar, with an optional type. Return the
1362 register number, and optionally fill in the actual type of the register
1363 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1364 type/index information in *TYPEINFO. */
1367 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1368 enum arm_reg_type *rtype,
1369 struct neon_typed_alias *typeinfo)
1372 struct reg_entry *reg = arm_reg_parse_multi (&str);
1373 struct neon_typed_alias atype;
1374 struct neon_type_el parsetype;
1378 atype.eltype.type = NT_invtype;
1379 atype.eltype.size = -1;
1381 /* Try alternate syntax for some types of register. Note these are mutually
1382 exclusive with the Neon syntax extensions. */
1385 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1393 /* Undo polymorphism when a set of register types may be accepted. */
1394 if ((type == REG_TYPE_NDQ
1395 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1396 || (type == REG_TYPE_VFSD
1397 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1398 || (type == REG_TYPE_NSDQ
1399 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1400 || reg->type == REG_TYPE_NQ))
1401 || (type == REG_TYPE_MMXWC
1402 && (reg->type == REG_TYPE_MMXWCG)))
1403 type = (enum arm_reg_type) reg->type;
1405 if (type != reg->type)
1411 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1413 if ((atype.defined & NTA_HASTYPE) != 0)
1415 first_error (_("can't redefine type for operand"));
1418 atype.defined |= NTA_HASTYPE;
1419 atype.eltype = parsetype;
1422 if (skip_past_char (&str, '[') == SUCCESS)
1424 if (type != REG_TYPE_VFD)
1426 first_error (_("only D registers may be indexed"));
1430 if ((atype.defined & NTA_HASINDEX) != 0)
1432 first_error (_("can't change index for operand"));
1436 atype.defined |= NTA_HASINDEX;
1438 if (skip_past_char (&str, ']') == SUCCESS)
1439 atype.index = NEON_ALL_LANES;
1444 my_get_expression (&exp, &str, GE_NO_PREFIX);
1446 if (exp.X_op != O_constant)
1448 first_error (_("constant expression required"));
1452 if (skip_past_char (&str, ']') == FAIL)
1455 atype.index = exp.X_add_number;
1470 /* Like arm_reg_parse, but allow allow the following extra features:
1471 - If RTYPE is non-zero, return the (possibly restricted) type of the
1472 register (e.g. Neon double or quad reg when either has been requested).
1473 - If this is a Neon vector type with additional type information, fill
1474 in the struct pointed to by VECTYPE (if non-NULL).
1475 This function will fault on encountering a scalar. */
1478 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1479 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1481 struct neon_typed_alias atype;
1483 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1488 /* Do not allow regname(... to parse as a register. */
1492 /* Do not allow a scalar (reg+index) to parse as a register. */
1493 if ((atype.defined & NTA_HASINDEX) != 0)
1495 first_error (_("register operand expected, but got scalar"));
1500 *vectype = atype.eltype;
1507 #define NEON_SCALAR_REG(X) ((X) >> 4)
1508 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1510 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1511 have enough information to be able to do a good job bounds-checking. So, we
1512 just do easy checks here, and do further checks later. */
1515 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1519 struct neon_typed_alias atype;
1521 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1523 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1526 if (atype.index == NEON_ALL_LANES)
1528 first_error (_("scalar must have an index"));
1531 else if (atype.index >= 64 / elsize)
1533 first_error (_("scalar index out of range"));
1538 *type = atype.eltype;
1542 return reg * 16 + atype.index;
1545 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1548 parse_reg_list (char ** strp)
1550 char * str = * strp;
1554 /* We come back here if we get ranges concatenated by '+' or '|'. */
1569 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1571 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1581 first_error (_("bad range in register list"));
1585 for (i = cur_reg + 1; i < reg; i++)
1587 if (range & (1 << i))
1589 (_("Warning: duplicated register (r%d) in register list"),
1597 if (range & (1 << reg))
1598 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1600 else if (reg <= cur_reg)
1601 as_tsktsk (_("Warning: register range not in ascending order"));
1606 while (skip_past_comma (&str) != FAIL
1607 || (in_range = 1, *str++ == '-'));
1612 first_error (_("missing `}'"));
1620 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1623 if (exp.X_op == O_constant)
1625 if (exp.X_add_number
1626 != (exp.X_add_number & 0x0000ffff))
1628 inst.error = _("invalid register mask");
1632 if ((range & exp.X_add_number) != 0)
1634 int regno = range & exp.X_add_number;
1637 regno = (1 << regno) - 1;
1639 (_("Warning: duplicated register (r%d) in register list"),
1643 range |= exp.X_add_number;
1647 if (inst.reloc.type != 0)
1649 inst.error = _("expression too complex");
1653 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1654 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1655 inst.reloc.pc_rel = 0;
1659 if (*str == '|' || *str == '+')
1665 while (another_range);
1671 /* Types of registers in a list. */
1680 /* Parse a VFP register list. If the string is invalid return FAIL.
1681 Otherwise return the number of registers, and set PBASE to the first
1682 register. Parses registers of type ETYPE.
1683 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1684 - Q registers can be used to specify pairs of D registers
1685 - { } can be omitted from around a singleton register list
1686 FIXME: This is not implemented, as it would require backtracking in
1689 This could be done (the meaning isn't really ambiguous), but doesn't
1690 fit in well with the current parsing framework.
1691 - 32 D registers may be used (also true for VFPv3).
1692 FIXME: Types are ignored in these register lists, which is probably a
1696 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1701 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1705 unsigned long mask = 0;
1710 inst.error = _("expecting {");
1719 regtype = REG_TYPE_VFS;
1724 regtype = REG_TYPE_VFD;
1727 case REGLIST_NEON_D:
1728 regtype = REG_TYPE_NDQ;
1732 if (etype != REGLIST_VFP_S)
1734 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1735 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1739 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1742 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1749 base_reg = max_regs;
1753 int setmask = 1, addregs = 1;
1755 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1757 if (new_base == FAIL)
1759 first_error (_(reg_expected_msgs[regtype]));
1763 if (new_base >= max_regs)
1765 first_error (_("register out of range in list"));
1769 /* Note: a value of 2 * n is returned for the register Q<n>. */
1770 if (regtype == REG_TYPE_NQ)
1776 if (new_base < base_reg)
1777 base_reg = new_base;
1779 if (mask & (setmask << new_base))
1781 first_error (_("invalid register list"));
1785 if ((mask >> new_base) != 0 && ! warned)
1787 as_tsktsk (_("register list not in ascending order"));
1791 mask |= setmask << new_base;
1794 if (*str == '-') /* We have the start of a range expression */
1800 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1803 inst.error = gettext (reg_expected_msgs[regtype]);
1807 if (high_range >= max_regs)
1809 first_error (_("register out of range in list"));
1813 if (regtype == REG_TYPE_NQ)
1814 high_range = high_range + 1;
1816 if (high_range <= new_base)
1818 inst.error = _("register range not in ascending order");
1822 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1824 if (mask & (setmask << new_base))
1826 inst.error = _("invalid register list");
1830 mask |= setmask << new_base;
1835 while (skip_past_comma (&str) != FAIL);
1839 /* Sanity check -- should have raised a parse error above. */
1840 if (count == 0 || count > max_regs)
1845 /* Final test -- the registers must be consecutive. */
1847 for (i = 0; i < count; i++)
1849 if ((mask & (1u << i)) == 0)
1851 inst.error = _("non-contiguous register range");
1861 /* True if two alias types are the same. */
1864 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1872 if (a->defined != b->defined)
1875 if ((a->defined & NTA_HASTYPE) != 0
1876 && (a->eltype.type != b->eltype.type
1877 || a->eltype.size != b->eltype.size))
1880 if ((a->defined & NTA_HASINDEX) != 0
1881 && (a->index != b->index))
1887 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1888 The base register is put in *PBASE.
1889 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1891 The register stride (minus one) is put in bit 4 of the return value.
1892 Bits [6:5] encode the list length (minus one).
1893 The type of the list elements is put in *ELTYPE, if non-NULL. */
1895 #define NEON_LANE(X) ((X) & 0xf)
1896 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1897 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1900 parse_neon_el_struct_list (char **str, unsigned *pbase,
1901 struct neon_type_el *eltype)
1908 int leading_brace = 0;
1909 enum arm_reg_type rtype = REG_TYPE_NDQ;
1910 const char *const incr_error = _("register stride must be 1 or 2");
1911 const char *const type_error = _("mismatched element/structure types in list");
1912 struct neon_typed_alias firsttype;
1914 if (skip_past_char (&ptr, '{') == SUCCESS)
1919 struct neon_typed_alias atype;
1920 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1924 first_error (_(reg_expected_msgs[rtype]));
1931 if (rtype == REG_TYPE_NQ)
1937 else if (reg_incr == -1)
1939 reg_incr = getreg - base_reg;
1940 if (reg_incr < 1 || reg_incr > 2)
1942 first_error (_(incr_error));
1946 else if (getreg != base_reg + reg_incr * count)
1948 first_error (_(incr_error));
1952 if (! neon_alias_types_same (&atype, &firsttype))
1954 first_error (_(type_error));
1958 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1962 struct neon_typed_alias htype;
1963 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1965 lane = NEON_INTERLEAVE_LANES;
1966 else if (lane != NEON_INTERLEAVE_LANES)
1968 first_error (_(type_error));
1973 else if (reg_incr != 1)
1975 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1979 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1982 first_error (_(reg_expected_msgs[rtype]));
1985 if (! neon_alias_types_same (&htype, &firsttype))
1987 first_error (_(type_error));
1990 count += hireg + dregs - getreg;
1994 /* If we're using Q registers, we can't use [] or [n] syntax. */
1995 if (rtype == REG_TYPE_NQ)
2001 if ((atype.defined & NTA_HASINDEX) != 0)
2005 else if (lane != atype.index)
2007 first_error (_(type_error));
2011 else if (lane == -1)
2012 lane = NEON_INTERLEAVE_LANES;
2013 else if (lane != NEON_INTERLEAVE_LANES)
2015 first_error (_(type_error));
2020 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2022 /* No lane set by [x]. We must be interleaving structures. */
2024 lane = NEON_INTERLEAVE_LANES;
2027 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2028 || (count > 1 && reg_incr == -1))
2030 first_error (_("error parsing element/structure list"));
2034 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2036 first_error (_("expected }"));
2044 *eltype = firsttype.eltype;
2049 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2052 /* Parse an explicit relocation suffix on an expression. This is
2053 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2054 arm_reloc_hsh contains no entries, so this function can only
2055 succeed if there is no () after the word. Returns -1 on error,
2056 BFD_RELOC_UNUSED if there wasn't any suffix. */
2058 parse_reloc (char **str)
2060 struct reloc_entry *r;
2064 return BFD_RELOC_UNUSED;
2069 while (*q && *q != ')' && *q != ',')
2074 if ((r = (struct reloc_entry *)
2075 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2082 /* Directives: register aliases. */
2084 static struct reg_entry *
2085 insert_reg_alias (char *str, unsigned number, int type)
2087 struct reg_entry *new_reg;
2090 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2092 if (new_reg->builtin)
2093 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2095 /* Only warn about a redefinition if it's not defined as the
2097 else if (new_reg->number != number || new_reg->type != type)
2098 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2103 name = xstrdup (str);
2104 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2106 new_reg->name = name;
2107 new_reg->number = number;
2108 new_reg->type = type;
2109 new_reg->builtin = FALSE;
2110 new_reg->neon = NULL;
2112 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2119 insert_neon_reg_alias (char *str, int number, int type,
2120 struct neon_typed_alias *atype)
2122 struct reg_entry *reg = insert_reg_alias (str, number, type);
2126 first_error (_("attempt to redefine typed alias"));
2132 reg->neon = (struct neon_typed_alias *)
2133 xmalloc (sizeof (struct neon_typed_alias));
2134 *reg->neon = *atype;
2138 /* Look for the .req directive. This is of the form:
2140 new_register_name .req existing_register_name
2142 If we find one, or if it looks sufficiently like one that we want to
2143 handle any error here, return TRUE. Otherwise return FALSE. */
2146 create_register_alias (char * newname, char *p)
2148 struct reg_entry *old;
2149 char *oldname, *nbuf;
2152 /* The input scrubber ensures that whitespace after the mnemonic is
2153 collapsed to single spaces. */
2155 if (strncmp (oldname, " .req ", 6) != 0)
2159 if (*oldname == '\0')
2162 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2165 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2169 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2170 the desired alias name, and p points to its end. If not, then
2171 the desired alias name is in the global original_case_string. */
2172 #ifdef TC_CASE_SENSITIVE
2175 newname = original_case_string;
2176 nlen = strlen (newname);
2179 nbuf = (char *) alloca (nlen + 1);
2180 memcpy (nbuf, newname, nlen);
2183 /* Create aliases under the new name as stated; an all-lowercase
2184 version of the new name; and an all-uppercase version of the new
2186 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2188 for (p = nbuf; *p; p++)
2191 if (strncmp (nbuf, newname, nlen))
2193 /* If this attempt to create an additional alias fails, do not bother
2194 trying to create the all-lower case alias. We will fail and issue
2195 a second, duplicate error message. This situation arises when the
2196 programmer does something like:
2199 The second .req creates the "Foo" alias but then fails to create
2200 the artificial FOO alias because it has already been created by the
2202 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2206 for (p = nbuf; *p; p++)
2209 if (strncmp (nbuf, newname, nlen))
2210 insert_reg_alias (nbuf, old->number, old->type);
2216 /* Create a Neon typed/indexed register alias using directives, e.g.:
2221 These typed registers can be used instead of the types specified after the
2222 Neon mnemonic, so long as all operands given have types. Types can also be
2223 specified directly, e.g.:
2224 vadd d0.s32, d1.s32, d2.s32 */
2227 create_neon_reg_alias (char *newname, char *p)
2229 enum arm_reg_type basetype;
2230 struct reg_entry *basereg;
2231 struct reg_entry mybasereg;
2232 struct neon_type ntype;
2233 struct neon_typed_alias typeinfo;
2234 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2237 typeinfo.defined = 0;
2238 typeinfo.eltype.type = NT_invtype;
2239 typeinfo.eltype.size = -1;
2240 typeinfo.index = -1;
2244 if (strncmp (p, " .dn ", 5) == 0)
2245 basetype = REG_TYPE_VFD;
2246 else if (strncmp (p, " .qn ", 5) == 0)
2247 basetype = REG_TYPE_NQ;
2256 basereg = arm_reg_parse_multi (&p);
2258 if (basereg && basereg->type != basetype)
2260 as_bad (_("bad type for register"));
2264 if (basereg == NULL)
2267 /* Try parsing as an integer. */
2268 my_get_expression (&exp, &p, GE_NO_PREFIX);
2269 if (exp.X_op != O_constant)
2271 as_bad (_("expression must be constant"));
2274 basereg = &mybasereg;
2275 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2281 typeinfo = *basereg->neon;
2283 if (parse_neon_type (&ntype, &p) == SUCCESS)
2285 /* We got a type. */
2286 if (typeinfo.defined & NTA_HASTYPE)
2288 as_bad (_("can't redefine the type of a register alias"));
2292 typeinfo.defined |= NTA_HASTYPE;
2293 if (ntype.elems != 1)
2295 as_bad (_("you must specify a single type only"));
2298 typeinfo.eltype = ntype.el[0];
2301 if (skip_past_char (&p, '[') == SUCCESS)
2304 /* We got a scalar index. */
2306 if (typeinfo.defined & NTA_HASINDEX)
2308 as_bad (_("can't redefine the index of a scalar alias"));
2312 my_get_expression (&exp, &p, GE_NO_PREFIX);
2314 if (exp.X_op != O_constant)
2316 as_bad (_("scalar index must be constant"));
2320 typeinfo.defined |= NTA_HASINDEX;
2321 typeinfo.index = exp.X_add_number;
2323 if (skip_past_char (&p, ']') == FAIL)
2325 as_bad (_("expecting ]"));
2330 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2331 the desired alias name, and p points to its end. If not, then
2332 the desired alias name is in the global original_case_string. */
2333 #ifdef TC_CASE_SENSITIVE
2334 namelen = nameend - newname;
2336 newname = original_case_string;
2337 namelen = strlen (newname);
2340 namebuf = (char *) alloca (namelen + 1);
2341 strncpy (namebuf, newname, namelen);
2342 namebuf[namelen] = '\0';
2344 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2345 typeinfo.defined != 0 ? &typeinfo : NULL);
2347 /* Insert name in all uppercase. */
2348 for (p = namebuf; *p; p++)
2351 if (strncmp (namebuf, newname, namelen))
2352 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2353 typeinfo.defined != 0 ? &typeinfo : NULL);
2355 /* Insert name in all lowercase. */
2356 for (p = namebuf; *p; p++)
2359 if (strncmp (namebuf, newname, namelen))
2360 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2361 typeinfo.defined != 0 ? &typeinfo : NULL);
2366 /* Should never be called, as .req goes between the alias and the
2367 register name, not at the beginning of the line. */
2370 s_req (int a ATTRIBUTE_UNUSED)
2372 as_bad (_("invalid syntax for .req directive"));
2376 s_dn (int a ATTRIBUTE_UNUSED)
2378 as_bad (_("invalid syntax for .dn directive"));
2382 s_qn (int a ATTRIBUTE_UNUSED)
2384 as_bad (_("invalid syntax for .qn directive"));
2387 /* The .unreq directive deletes an alias which was previously defined
2388 by .req. For example:
2394 s_unreq (int a ATTRIBUTE_UNUSED)
2399 name = input_line_pointer;
2401 while (*input_line_pointer != 0
2402 && *input_line_pointer != ' '
2403 && *input_line_pointer != '\n')
2404 ++input_line_pointer;
2406 saved_char = *input_line_pointer;
2407 *input_line_pointer = 0;
2410 as_bad (_("invalid syntax for .unreq directive"));
2413 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2417 as_bad (_("unknown register alias '%s'"), name);
2418 else if (reg->builtin)
2419 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2426 hash_delete (arm_reg_hsh, name, FALSE);
2427 free ((char *) reg->name);
2432 /* Also locate the all upper case and all lower case versions.
2433 Do not complain if we cannot find one or the other as it
2434 was probably deleted above. */
2436 nbuf = strdup (name);
2437 for (p = nbuf; *p; p++)
2439 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2442 hash_delete (arm_reg_hsh, nbuf, FALSE);
2443 free ((char *) reg->name);
2449 for (p = nbuf; *p; p++)
2451 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2454 hash_delete (arm_reg_hsh, nbuf, FALSE);
2455 free ((char *) reg->name);
2465 *input_line_pointer = saved_char;
2466 demand_empty_rest_of_line ();
2469 /* Directives: Instruction set selection. */
2472 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2473 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2474 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2475 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2477 /* Create a new mapping symbol for the transition to STATE. */
2480 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2483 const char * symname;
2490 type = BSF_NO_FLAGS;
2494 type = BSF_NO_FLAGS;
2498 type = BSF_NO_FLAGS;
2504 symbolP = symbol_new (symname, now_seg, value, frag);
2505 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2510 THUMB_SET_FUNC (symbolP, 0);
2511 ARM_SET_THUMB (symbolP, 0);
2512 ARM_SET_INTERWORK (symbolP, support_interwork);
2516 THUMB_SET_FUNC (symbolP, 1);
2517 ARM_SET_THUMB (symbolP, 1);
2518 ARM_SET_INTERWORK (symbolP, support_interwork);
2526 /* Save the mapping symbols for future reference. Also check that
2527 we do not place two mapping symbols at the same offset within a
2528 frag. We'll handle overlap between frags in
2529 check_mapping_symbols.
2531 If .fill or other data filling directive generates zero sized data,
2532 the mapping symbol for the following code will have the same value
2533 as the one generated for the data filling directive. In this case,
2534 we replace the old symbol with the new one at the same address. */
2537 if (frag->tc_frag_data.first_map != NULL)
2539 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2540 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2542 frag->tc_frag_data.first_map = symbolP;
2544 if (frag->tc_frag_data.last_map != NULL)
2546 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2547 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2548 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2550 frag->tc_frag_data.last_map = symbolP;
2553 /* We must sometimes convert a region marked as code to data during
2554 code alignment, if an odd number of bytes have to be padded. The
2555 code mapping symbol is pushed to an aligned address. */
2558 insert_data_mapping_symbol (enum mstate state,
2559 valueT value, fragS *frag, offsetT bytes)
2561 /* If there was already a mapping symbol, remove it. */
2562 if (frag->tc_frag_data.last_map != NULL
2563 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2565 symbolS *symp = frag->tc_frag_data.last_map;
2569 know (frag->tc_frag_data.first_map == symp);
2570 frag->tc_frag_data.first_map = NULL;
2572 frag->tc_frag_data.last_map = NULL;
2573 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2576 make_mapping_symbol (MAP_DATA, value, frag);
2577 make_mapping_symbol (state, value + bytes, frag);
2580 static void mapping_state_2 (enum mstate state, int max_chars);
2582 /* Set the mapping state to STATE. Only call this when about to
2583 emit some STATE bytes to the file. */
2586 mapping_state (enum mstate state)
2588 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2590 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2592 if (mapstate == state)
2593 /* The mapping symbol has already been emitted.
2594 There is nothing else to do. */
2597 if (state == MAP_ARM || state == MAP_THUMB)
2599 All ARM instructions require 4-byte alignment.
2600 (Almost) all Thumb instructions require 2-byte alignment.
2602 When emitting instructions into any section, mark the section
2605 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2606 but themselves require 2-byte alignment; this applies to some
2607 PC- relative forms. However, these cases will invovle implicit
2608 literal pool generation or an explicit .align >=2, both of
2609 which will cause the section to me marked with sufficient
2610 alignment. Thus, we don't handle those cases here. */
2611 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2613 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2614 /* This case will be evaluated later in the next else. */
2616 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2617 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2619 /* Only add the symbol if the offset is > 0:
2620 if we're at the first frag, check it's size > 0;
2621 if we're not at the first frag, then for sure
2622 the offset is > 0. */
2623 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2624 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2627 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2630 mapping_state_2 (state, 0);
2634 /* Same as mapping_state, but MAX_CHARS bytes have already been
2635 allocated. Put the mapping symbol that far back. */
2638 mapping_state_2 (enum mstate state, int max_chars)
2640 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2642 if (!SEG_NORMAL (now_seg))
2645 if (mapstate == state)
2646 /* The mapping symbol has already been emitted.
2647 There is nothing else to do. */
2650 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2651 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2654 #define mapping_state(x) ((void)0)
2655 #define mapping_state_2(x, y) ((void)0)
2658 /* Find the real, Thumb encoded start of a Thumb function. */
2662 find_real_start (symbolS * symbolP)
2665 const char * name = S_GET_NAME (symbolP);
2666 symbolS * new_target;
2668 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2669 #define STUB_NAME ".real_start_of"
2674 /* The compiler may generate BL instructions to local labels because
2675 it needs to perform a branch to a far away location. These labels
2676 do not have a corresponding ".real_start_of" label. We check
2677 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2678 the ".real_start_of" convention for nonlocal branches. */
2679 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2682 real_start = ACONCAT ((STUB_NAME, name, NULL));
2683 new_target = symbol_find (real_start);
2685 if (new_target == NULL)
2687 as_warn (_("Failed to find real start of function: %s\n"), name);
2688 new_target = symbolP;
2696 opcode_select (int width)
2703 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2704 as_bad (_("selected processor does not support THUMB opcodes"));
2707 /* No need to force the alignment, since we will have been
2708 coming from ARM mode, which is word-aligned. */
2709 record_alignment (now_seg, 1);
2716 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2717 as_bad (_("selected processor does not support ARM opcodes"));
2722 frag_align (2, 0, 0);
2724 record_alignment (now_seg, 1);
2729 as_bad (_("invalid instruction size selected (%d)"), width);
2734 s_arm (int ignore ATTRIBUTE_UNUSED)
2737 demand_empty_rest_of_line ();
2741 s_thumb (int ignore ATTRIBUTE_UNUSED)
2744 demand_empty_rest_of_line ();
2748 s_code (int unused ATTRIBUTE_UNUSED)
2752 temp = get_absolute_expression ();
2757 opcode_select (temp);
2761 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2766 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2768 /* If we are not already in thumb mode go into it, EVEN if
2769 the target processor does not support thumb instructions.
2770 This is used by gcc/config/arm/lib1funcs.asm for example
2771 to compile interworking support functions even if the
2772 target processor should not support interworking. */
2776 record_alignment (now_seg, 1);
2779 demand_empty_rest_of_line ();
2783 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2787 /* The following label is the name/address of the start of a Thumb function.
2788 We need to know this for the interworking support. */
2789 label_is_thumb_function_name = TRUE;
2792 /* Perform a .set directive, but also mark the alias as
2793 being a thumb function. */
2796 s_thumb_set (int equiv)
2798 /* XXX the following is a duplicate of the code for s_set() in read.c
2799 We cannot just call that code as we need to get at the symbol that
2806 /* Especial apologies for the random logic:
2807 This just grew, and could be parsed much more simply!
2809 name = input_line_pointer;
2810 delim = get_symbol_end ();
2811 end_name = input_line_pointer;
2814 if (*input_line_pointer != ',')
2817 as_bad (_("expected comma after name \"%s\""), name);
2819 ignore_rest_of_line ();
2823 input_line_pointer++;
2826 if (name[0] == '.' && name[1] == '\0')
2828 /* XXX - this should not happen to .thumb_set. */
2832 if ((symbolP = symbol_find (name)) == NULL
2833 && (symbolP = md_undefined_symbol (name)) == NULL)
2836 /* When doing symbol listings, play games with dummy fragments living
2837 outside the normal fragment chain to record the file and line info
2839 if (listing & LISTING_SYMBOLS)
2841 extern struct list_info_struct * listing_tail;
2842 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2844 memset (dummy_frag, 0, sizeof (fragS));
2845 dummy_frag->fr_type = rs_fill;
2846 dummy_frag->line = listing_tail;
2847 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2848 dummy_frag->fr_symbol = symbolP;
2852 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2855 /* "set" symbols are local unless otherwise specified. */
2856 SF_SET_LOCAL (symbolP);
2857 #endif /* OBJ_COFF */
2858 } /* Make a new symbol. */
2860 symbol_table_insert (symbolP);
2865 && S_IS_DEFINED (symbolP)
2866 && S_GET_SEGMENT (symbolP) != reg_section)
2867 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2869 pseudo_set (symbolP);
2871 demand_empty_rest_of_line ();
2873 /* XXX Now we come to the Thumb specific bit of code. */
2875 THUMB_SET_FUNC (symbolP, 1);
2876 ARM_SET_THUMB (symbolP, 1);
2877 #if defined OBJ_ELF || defined OBJ_COFF
2878 ARM_SET_INTERWORK (symbolP, support_interwork);
2882 /* Directives: Mode selection. */
2884 /* .syntax [unified|divided] - choose the new unified syntax
2885 (same for Arm and Thumb encoding, modulo slight differences in what
2886 can be represented) or the old divergent syntax for each mode. */
2888 s_syntax (int unused ATTRIBUTE_UNUSED)
2892 name = input_line_pointer;
2893 delim = get_symbol_end ();
2895 if (!strcasecmp (name, "unified"))
2896 unified_syntax = TRUE;
2897 else if (!strcasecmp (name, "divided"))
2898 unified_syntax = FALSE;
2901 as_bad (_("unrecognized syntax mode \"%s\""), name);
2904 *input_line_pointer = delim;
2905 demand_empty_rest_of_line ();
2908 /* Directives: sectioning and alignment. */
2910 /* Same as s_align_ptwo but align 0 => align 2. */
2913 s_align (int unused ATTRIBUTE_UNUSED)
2918 long max_alignment = 15;
2920 temp = get_absolute_expression ();
2921 if (temp > max_alignment)
2922 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2925 as_bad (_("alignment negative. 0 assumed."));
2929 if (*input_line_pointer == ',')
2931 input_line_pointer++;
2932 temp_fill = get_absolute_expression ();
2944 /* Only make a frag if we HAVE to. */
2945 if (temp && !need_pass_2)
2947 if (!fill_p && subseg_text_p (now_seg))
2948 frag_align_code (temp, 0);
2950 frag_align (temp, (int) temp_fill, 0);
2952 demand_empty_rest_of_line ();
2954 record_alignment (now_seg, temp);
2958 s_bss (int ignore ATTRIBUTE_UNUSED)
2960 /* We don't support putting frags in the BSS segment, we fake it by
2961 marking in_bss, then looking at s_skip for clues. */
2962 subseg_set (bss_section, 0);
2963 demand_empty_rest_of_line ();
2965 #ifdef md_elf_section_change_hook
2966 md_elf_section_change_hook ();
2971 s_even (int ignore ATTRIBUTE_UNUSED)
2973 /* Never make frag if expect extra pass. */
2975 frag_align (1, 0, 0);
2977 record_alignment (now_seg, 1);
2979 demand_empty_rest_of_line ();
2982 /* Directives: Literal pools. */
2984 static literal_pool *
2985 find_literal_pool (void)
2987 literal_pool * pool;
2989 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2991 if (pool->section == now_seg
2992 && pool->sub_section == now_subseg)
2999 static literal_pool *
3000 find_or_make_literal_pool (void)
3002 /* Next literal pool ID number. */
3003 static unsigned int latest_pool_num = 1;
3004 literal_pool * pool;
3006 pool = find_literal_pool ();
3010 /* Create a new pool. */
3011 pool = (literal_pool *) xmalloc (sizeof (* pool));
3015 pool->next_free_entry = 0;
3016 pool->section = now_seg;
3017 pool->sub_section = now_subseg;
3018 pool->next = list_of_pools;
3019 pool->symbol = NULL;
3021 /* Add it to the list. */
3022 list_of_pools = pool;
3025 /* New pools, and emptied pools, will have a NULL symbol. */
3026 if (pool->symbol == NULL)
3028 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3029 (valueT) 0, &zero_address_frag);
3030 pool->id = latest_pool_num ++;
3037 /* Add the literal in the global 'inst'
3038 structure to the relevant literal pool. */
3041 add_to_lit_pool (void)
3043 literal_pool * pool;
3046 pool = find_or_make_literal_pool ();
3048 /* Check if this literal value is already in the pool. */
3049 for (entry = 0; entry < pool->next_free_entry; entry ++)
3051 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3052 && (inst.reloc.exp.X_op == O_constant)
3053 && (pool->literals[entry].X_add_number
3054 == inst.reloc.exp.X_add_number)
3055 && (pool->literals[entry].X_unsigned
3056 == inst.reloc.exp.X_unsigned))
3059 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3060 && (inst.reloc.exp.X_op == O_symbol)
3061 && (pool->literals[entry].X_add_number
3062 == inst.reloc.exp.X_add_number)
3063 && (pool->literals[entry].X_add_symbol
3064 == inst.reloc.exp.X_add_symbol)
3065 && (pool->literals[entry].X_op_symbol
3066 == inst.reloc.exp.X_op_symbol))
3070 /* Do we need to create a new entry? */
3071 if (entry == pool->next_free_entry)
3073 if (entry >= MAX_LITERAL_POOL_SIZE)
3075 inst.error = _("literal pool overflow");
3079 pool->literals[entry] = inst.reloc.exp;
3081 /* PR ld/12974: Record the location of the first source line to reference
3082 this entry in the literal pool. If it turns out during linking that the
3083 symbol does not exist we will be able to give an accurate line number for
3084 the (first use of the) missing reference. */
3085 if (debug_type == DEBUG_DWARF2)
3086 dwarf2_where (pool->locs + entry);
3088 pool->next_free_entry += 1;
3091 inst.reloc.exp.X_op = O_symbol;
3092 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3093 inst.reloc.exp.X_add_symbol = pool->symbol;
3098 /* Can't use symbol_new here, so have to create a symbol and then at
3099 a later date assign it a value. Thats what these functions do. */
3102 symbol_locate (symbolS * symbolP,
3103 const char * name, /* It is copied, the caller can modify. */
3104 segT segment, /* Segment identifier (SEG_<something>). */
3105 valueT valu, /* Symbol value. */
3106 fragS * frag) /* Associated fragment. */
3108 unsigned int name_length;
3109 char * preserved_copy_of_name;
3111 name_length = strlen (name) + 1; /* +1 for \0. */
3112 obstack_grow (¬es, name, name_length);
3113 preserved_copy_of_name = (char *) obstack_finish (¬es);
3115 #ifdef tc_canonicalize_symbol_name
3116 preserved_copy_of_name =
3117 tc_canonicalize_symbol_name (preserved_copy_of_name);
3120 S_SET_NAME (symbolP, preserved_copy_of_name);
3122 S_SET_SEGMENT (symbolP, segment);
3123 S_SET_VALUE (symbolP, valu);
3124 symbol_clear_list_pointers (symbolP);
3126 symbol_set_frag (symbolP, frag);
3128 /* Link to end of symbol chain. */
3130 extern int symbol_table_frozen;
3132 if (symbol_table_frozen)
3136 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3138 obj_symbol_new_hook (symbolP);
3140 #ifdef tc_symbol_new_hook
3141 tc_symbol_new_hook (symbolP);
3145 verify_symbol_chain (symbol_rootP, symbol_lastP);
3146 #endif /* DEBUG_SYMS */
3151 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3154 literal_pool * pool;
3157 pool = find_literal_pool ();
3159 || pool->symbol == NULL
3160 || pool->next_free_entry == 0)
3163 mapping_state (MAP_DATA);
3165 /* Align pool as you have word accesses.
3166 Only make a frag if we have to. */
3168 frag_align (2, 0, 0);
3170 record_alignment (now_seg, 2);
3172 sprintf (sym_name, "$$lit_\002%x", pool->id);
3174 symbol_locate (pool->symbol, sym_name, now_seg,
3175 (valueT) frag_now_fix (), frag_now);
3176 symbol_table_insert (pool->symbol);
3178 ARM_SET_THUMB (pool->symbol, thumb_mode);
3180 #if defined OBJ_COFF || defined OBJ_ELF
3181 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3184 for (entry = 0; entry < pool->next_free_entry; entry ++)
3187 if (debug_type == DEBUG_DWARF2)
3188 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3190 /* First output the expression in the instruction to the pool. */
3191 emit_expr (&(pool->literals[entry]), 4); /* .word */
3194 /* Mark the pool as empty. */
3195 pool->next_free_entry = 0;
3196 pool->symbol = NULL;
3200 /* Forward declarations for functions below, in the MD interface
3202 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3203 static valueT create_unwind_entry (int);
3204 static void start_unwind_section (const segT, int);
3205 static void add_unwind_opcode (valueT, int);
3206 static void flush_pending_unwind (void);
3208 /* Directives: Data. */
3211 s_arm_elf_cons (int nbytes)
3215 #ifdef md_flush_pending_output
3216 md_flush_pending_output ();
3219 if (is_it_end_of_statement ())
3221 demand_empty_rest_of_line ();
3225 #ifdef md_cons_align
3226 md_cons_align (nbytes);
3229 mapping_state (MAP_DATA);
3233 char *base = input_line_pointer;
3237 if (exp.X_op != O_symbol)
3238 emit_expr (&exp, (unsigned int) nbytes);
3241 char *before_reloc = input_line_pointer;
3242 reloc = parse_reloc (&input_line_pointer);
3245 as_bad (_("unrecognized relocation suffix"));
3246 ignore_rest_of_line ();
3249 else if (reloc == BFD_RELOC_UNUSED)
3250 emit_expr (&exp, (unsigned int) nbytes);
3253 reloc_howto_type *howto = (reloc_howto_type *)
3254 bfd_reloc_type_lookup (stdoutput,
3255 (bfd_reloc_code_real_type) reloc);
3256 int size = bfd_get_reloc_size (howto);
3258 if (reloc == BFD_RELOC_ARM_PLT32)
3260 as_bad (_("(plt) is only valid on branch targets"));
3261 reloc = BFD_RELOC_UNUSED;
3266 as_bad (_("%s relocations do not fit in %d bytes"),
3267 howto->name, nbytes);
3270 /* We've parsed an expression stopping at O_symbol.
3271 But there may be more expression left now that we
3272 have parsed the relocation marker. Parse it again.
3273 XXX Surely there is a cleaner way to do this. */
3274 char *p = input_line_pointer;
3276 char *save_buf = (char *) alloca (input_line_pointer - base);
3277 memcpy (save_buf, base, input_line_pointer - base);
3278 memmove (base + (input_line_pointer - before_reloc),
3279 base, before_reloc - base);
3281 input_line_pointer = base + (input_line_pointer-before_reloc);
3283 memcpy (base, save_buf, p - base);
3285 offset = nbytes - size;
3286 p = frag_more ((int) nbytes);
3287 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3288 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3293 while (*input_line_pointer++ == ',');
3295 /* Put terminator back into stream. */
3296 input_line_pointer --;
3297 demand_empty_rest_of_line ();
3300 /* Emit an expression containing a 32-bit thumb instruction.
3301 Implementation based on put_thumb32_insn. */
3304 emit_thumb32_expr (expressionS * exp)
3306 expressionS exp_high = *exp;
3308 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3309 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3310 exp->X_add_number &= 0xffff;
3311 emit_expr (exp, (unsigned int) THUMB_SIZE);
3314 /* Guess the instruction size based on the opcode. */
3317 thumb_insn_size (int opcode)
3319 if ((unsigned int) opcode < 0xe800u)
3321 else if ((unsigned int) opcode >= 0xe8000000u)
3328 emit_insn (expressionS *exp, int nbytes)
3332 if (exp->X_op == O_constant)
3337 size = thumb_insn_size (exp->X_add_number);
3341 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3343 as_bad (_(".inst.n operand too big. "\
3344 "Use .inst.w instead"));
3349 if (now_it.state == AUTOMATIC_IT_BLOCK)
3350 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3352 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3354 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3355 emit_thumb32_expr (exp);
3357 emit_expr (exp, (unsigned int) size);
3359 it_fsm_post_encode ();
3363 as_bad (_("cannot determine Thumb instruction size. " \
3364 "Use .inst.n/.inst.w instead"));
3367 as_bad (_("constant expression required"));
3372 /* Like s_arm_elf_cons but do not use md_cons_align and
3373 set the mapping state to MAP_ARM/MAP_THUMB. */
3376 s_arm_elf_inst (int nbytes)
3378 if (is_it_end_of_statement ())
3380 demand_empty_rest_of_line ();
3384 /* Calling mapping_state () here will not change ARM/THUMB,
3385 but will ensure not to be in DATA state. */
3388 mapping_state (MAP_THUMB);
3393 as_bad (_("width suffixes are invalid in ARM mode"));
3394 ignore_rest_of_line ();
3400 mapping_state (MAP_ARM);
3409 if (! emit_insn (& exp, nbytes))
3411 ignore_rest_of_line ();
3415 while (*input_line_pointer++ == ',');
3417 /* Put terminator back into stream. */
3418 input_line_pointer --;
3419 demand_empty_rest_of_line ();
3422 /* Parse a .rel31 directive. */
3425 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3432 if (*input_line_pointer == '1')
3433 highbit = 0x80000000;
3434 else if (*input_line_pointer != '0')
3435 as_bad (_("expected 0 or 1"));
3437 input_line_pointer++;
3438 if (*input_line_pointer != ',')
3439 as_bad (_("missing comma"));
3440 input_line_pointer++;
3442 #ifdef md_flush_pending_output
3443 md_flush_pending_output ();
3446 #ifdef md_cons_align
3450 mapping_state (MAP_DATA);
3455 md_number_to_chars (p, highbit, 4);
3456 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3457 BFD_RELOC_ARM_PREL31);
3459 demand_empty_rest_of_line ();
3462 /* Directives: AEABI stack-unwind tables. */
3464 /* Parse an unwind_fnstart directive. Simply records the current location. */
3467 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3469 demand_empty_rest_of_line ();
3470 if (unwind.proc_start)
3472 as_bad (_("duplicate .fnstart directive"));
3476 /* Mark the start of the function. */
3477 unwind.proc_start = expr_build_dot ();
3479 /* Reset the rest of the unwind info. */
3480 unwind.opcode_count = 0;
3481 unwind.table_entry = NULL;
3482 unwind.personality_routine = NULL;
3483 unwind.personality_index = -1;
3484 unwind.frame_size = 0;
3485 unwind.fp_offset = 0;
3486 unwind.fp_reg = REG_SP;
3488 unwind.sp_restored = 0;
3492 /* Parse a handlerdata directive. Creates the exception handling table entry
3493 for the function. */
3496 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3498 demand_empty_rest_of_line ();
3499 if (!unwind.proc_start)
3500 as_bad (MISSING_FNSTART);
3502 if (unwind.table_entry)
3503 as_bad (_("duplicate .handlerdata directive"));
3505 create_unwind_entry (1);
3508 /* Parse an unwind_fnend directive. Generates the index table entry. */
3511 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3516 unsigned int marked_pr_dependency;
3518 demand_empty_rest_of_line ();
3520 if (!unwind.proc_start)
3522 as_bad (_(".fnend directive without .fnstart"));
3526 /* Add eh table entry. */
3527 if (unwind.table_entry == NULL)
3528 val = create_unwind_entry (0);
3532 /* Add index table entry. This is two words. */
3533 start_unwind_section (unwind.saved_seg, 1);
3534 frag_align (2, 0, 0);
3535 record_alignment (now_seg, 2);
3537 ptr = frag_more (8);
3538 where = frag_now_fix () - 8;
3540 /* Self relative offset of the function start. */
3541 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3542 BFD_RELOC_ARM_PREL31);
3544 /* Indicate dependency on EHABI-defined personality routines to the
3545 linker, if it hasn't been done already. */
3546 marked_pr_dependency
3547 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3548 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3549 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3551 static const char *const name[] =
3553 "__aeabi_unwind_cpp_pr0",
3554 "__aeabi_unwind_cpp_pr1",
3555 "__aeabi_unwind_cpp_pr2"
3557 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3558 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3559 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3560 |= 1 << unwind.personality_index;
3564 /* Inline exception table entry. */
3565 md_number_to_chars (ptr + 4, val, 4);
3567 /* Self relative offset of the table entry. */
3568 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3569 BFD_RELOC_ARM_PREL31);
3571 /* Restore the original section. */
3572 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3574 unwind.proc_start = NULL;
3578 /* Parse an unwind_cantunwind directive. */
3581 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3583 demand_empty_rest_of_line ();
3584 if (!unwind.proc_start)
3585 as_bad (MISSING_FNSTART);
3587 if (unwind.personality_routine || unwind.personality_index != -1)
3588 as_bad (_("personality routine specified for cantunwind frame"));
3590 unwind.personality_index = -2;
3594 /* Parse a personalityindex directive. */
3597 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3601 if (!unwind.proc_start)
3602 as_bad (MISSING_FNSTART);
3604 if (unwind.personality_routine || unwind.personality_index != -1)
3605 as_bad (_("duplicate .personalityindex directive"));
3609 if (exp.X_op != O_constant
3610 || exp.X_add_number < 0 || exp.X_add_number > 15)
3612 as_bad (_("bad personality routine number"));
3613 ignore_rest_of_line ();
3617 unwind.personality_index = exp.X_add_number;
3619 demand_empty_rest_of_line ();
3623 /* Parse a personality directive. */
3626 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3630 if (!unwind.proc_start)
3631 as_bad (MISSING_FNSTART);
3633 if (unwind.personality_routine || unwind.personality_index != -1)
3634 as_bad (_("duplicate .personality directive"));
3636 name = input_line_pointer;
3637 c = get_symbol_end ();
3638 p = input_line_pointer;
3639 unwind.personality_routine = symbol_find_or_make (name);
3641 demand_empty_rest_of_line ();
3645 /* Parse a directive saving core registers. */
3648 s_arm_unwind_save_core (void)
3654 range = parse_reg_list (&input_line_pointer);
3657 as_bad (_("expected register list"));
3658 ignore_rest_of_line ();
3662 demand_empty_rest_of_line ();
3664 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3665 into .unwind_save {..., sp...}. We aren't bothered about the value of
3666 ip because it is clobbered by calls. */
3667 if (unwind.sp_restored && unwind.fp_reg == 12
3668 && (range & 0x3000) == 0x1000)
3670 unwind.opcode_count--;
3671 unwind.sp_restored = 0;
3672 range = (range | 0x2000) & ~0x1000;
3673 unwind.pending_offset = 0;
3679 /* See if we can use the short opcodes. These pop a block of up to 8
3680 registers starting with r4, plus maybe r14. */
3681 for (n = 0; n < 8; n++)
3683 /* Break at the first non-saved register. */
3684 if ((range & (1 << (n + 4))) == 0)
3687 /* See if there are any other bits set. */
3688 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3690 /* Use the long form. */
3691 op = 0x8000 | ((range >> 4) & 0xfff);
3692 add_unwind_opcode (op, 2);
3696 /* Use the short form. */
3698 op = 0xa8; /* Pop r14. */
3700 op = 0xa0; /* Do not pop r14. */
3702 add_unwind_opcode (op, 1);
3709 op = 0xb100 | (range & 0xf);
3710 add_unwind_opcode (op, 2);
3713 /* Record the number of bytes pushed. */
3714 for (n = 0; n < 16; n++)
3716 if (range & (1 << n))
3717 unwind.frame_size += 4;
3722 /* Parse a directive saving FPA registers. */
3725 s_arm_unwind_save_fpa (int reg)
3731 /* Get Number of registers to transfer. */
3732 if (skip_past_comma (&input_line_pointer) != FAIL)
3735 exp.X_op = O_illegal;
3737 if (exp.X_op != O_constant)
3739 as_bad (_("expected , <constant>"));
3740 ignore_rest_of_line ();
3744 num_regs = exp.X_add_number;
3746 if (num_regs < 1 || num_regs > 4)
3748 as_bad (_("number of registers must be in the range [1:4]"));
3749 ignore_rest_of_line ();
3753 demand_empty_rest_of_line ();
3758 op = 0xb4 | (num_regs - 1);
3759 add_unwind_opcode (op, 1);
3764 op = 0xc800 | (reg << 4) | (num_regs - 1);
3765 add_unwind_opcode (op, 2);
3767 unwind.frame_size += num_regs * 12;
3771 /* Parse a directive saving VFP registers for ARMv6 and above. */
3774 s_arm_unwind_save_vfp_armv6 (void)
3779 int num_vfpv3_regs = 0;
3780 int num_regs_below_16;
3782 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3785 as_bad (_("expected register list"));
3786 ignore_rest_of_line ();
3790 demand_empty_rest_of_line ();
3792 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3793 than FSTMX/FLDMX-style ones). */
3795 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3797 num_vfpv3_regs = count;
3798 else if (start + count > 16)
3799 num_vfpv3_regs = start + count - 16;
3801 if (num_vfpv3_regs > 0)
3803 int start_offset = start > 16 ? start - 16 : 0;
3804 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3805 add_unwind_opcode (op, 2);
3808 /* Generate opcode for registers numbered in the range 0 .. 15. */
3809 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3810 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3811 if (num_regs_below_16 > 0)
3813 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3814 add_unwind_opcode (op, 2);
3817 unwind.frame_size += count * 8;
3821 /* Parse a directive saving VFP registers for pre-ARMv6. */
3824 s_arm_unwind_save_vfp (void)
3830 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3833 as_bad (_("expected register list"));
3834 ignore_rest_of_line ();
3838 demand_empty_rest_of_line ();
3843 op = 0xb8 | (count - 1);
3844 add_unwind_opcode (op, 1);
3849 op = 0xb300 | (reg << 4) | (count - 1);
3850 add_unwind_opcode (op, 2);
3852 unwind.frame_size += count * 8 + 4;
3856 /* Parse a directive saving iWMMXt data registers. */
3859 s_arm_unwind_save_mmxwr (void)
3867 if (*input_line_pointer == '{')
3868 input_line_pointer++;
3872 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3876 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3881 as_tsktsk (_("register list not in ascending order"));
3884 if (*input_line_pointer == '-')
3886 input_line_pointer++;
3887 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3890 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3893 else if (reg >= hi_reg)
3895 as_bad (_("bad register range"));
3898 for (; reg < hi_reg; reg++)
3902 while (skip_past_comma (&input_line_pointer) != FAIL);
3904 if (*input_line_pointer == '}')
3905 input_line_pointer++;
3907 demand_empty_rest_of_line ();
3909 /* Generate any deferred opcodes because we're going to be looking at
3911 flush_pending_unwind ();
3913 for (i = 0; i < 16; i++)
3915 if (mask & (1 << i))
3916 unwind.frame_size += 8;
3919 /* Attempt to combine with a previous opcode. We do this because gcc
3920 likes to output separate unwind directives for a single block of
3922 if (unwind.opcode_count > 0)
3924 i = unwind.opcodes[unwind.opcode_count - 1];
3925 if ((i & 0xf8) == 0xc0)
3928 /* Only merge if the blocks are contiguous. */
3931 if ((mask & 0xfe00) == (1 << 9))
3933 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3934 unwind.opcode_count--;
3937 else if (i == 6 && unwind.opcode_count >= 2)
3939 i = unwind.opcodes[unwind.opcode_count - 2];
3943 op = 0xffff << (reg - 1);
3945 && ((mask & op) == (1u << (reg - 1))))
3947 op = (1 << (reg + i + 1)) - 1;
3948 op &= ~((1 << reg) - 1);
3950 unwind.opcode_count -= 2;
3957 /* We want to generate opcodes in the order the registers have been
3958 saved, ie. descending order. */
3959 for (reg = 15; reg >= -1; reg--)
3961 /* Save registers in blocks. */
3963 || !(mask & (1 << reg)))
3965 /* We found an unsaved reg. Generate opcodes to save the
3972 op = 0xc0 | (hi_reg - 10);
3973 add_unwind_opcode (op, 1);
3978 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3979 add_unwind_opcode (op, 2);
3988 ignore_rest_of_line ();
3992 s_arm_unwind_save_mmxwcg (void)
3999 if (*input_line_pointer == '{')
4000 input_line_pointer++;
4004 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4008 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4014 as_tsktsk (_("register list not in ascending order"));
4017 if (*input_line_pointer == '-')
4019 input_line_pointer++;
4020 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4023 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4026 else if (reg >= hi_reg)
4028 as_bad (_("bad register range"));
4031 for (; reg < hi_reg; reg++)
4035 while (skip_past_comma (&input_line_pointer) != FAIL);
4037 if (*input_line_pointer == '}')
4038 input_line_pointer++;
4040 demand_empty_rest_of_line ();
4042 /* Generate any deferred opcodes because we're going to be looking at
4044 flush_pending_unwind ();
4046 for (reg = 0; reg < 16; reg++)
4048 if (mask & (1 << reg))
4049 unwind.frame_size += 4;
4052 add_unwind_opcode (op, 2);
4055 ignore_rest_of_line ();
4059 /* Parse an unwind_save directive.
4060 If the argument is non-zero, this is a .vsave directive. */
4063 s_arm_unwind_save (int arch_v6)
4066 struct reg_entry *reg;
4067 bfd_boolean had_brace = FALSE;
4069 if (!unwind.proc_start)
4070 as_bad (MISSING_FNSTART);
4072 /* Figure out what sort of save we have. */
4073 peek = input_line_pointer;
4081 reg = arm_reg_parse_multi (&peek);
4085 as_bad (_("register expected"));
4086 ignore_rest_of_line ();
4095 as_bad (_("FPA .unwind_save does not take a register list"));
4096 ignore_rest_of_line ();
4099 input_line_pointer = peek;
4100 s_arm_unwind_save_fpa (reg->number);
4103 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4106 s_arm_unwind_save_vfp_armv6 ();
4108 s_arm_unwind_save_vfp ();
4110 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4111 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4114 as_bad (_(".unwind_save does not support this kind of register"));
4115 ignore_rest_of_line ();
4120 /* Parse an unwind_movsp directive. */
4123 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4129 if (!unwind.proc_start)
4130 as_bad (MISSING_FNSTART);
4132 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4135 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4136 ignore_rest_of_line ();
4140 /* Optional constant. */
4141 if (skip_past_comma (&input_line_pointer) != FAIL)
4143 if (immediate_for_directive (&offset) == FAIL)
4149 demand_empty_rest_of_line ();
4151 if (reg == REG_SP || reg == REG_PC)
4153 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4157 if (unwind.fp_reg != REG_SP)
4158 as_bad (_("unexpected .unwind_movsp directive"));
4160 /* Generate opcode to restore the value. */
4162 add_unwind_opcode (op, 1);
4164 /* Record the information for later. */
4165 unwind.fp_reg = reg;
4166 unwind.fp_offset = unwind.frame_size - offset;
4167 unwind.sp_restored = 1;
4170 /* Parse an unwind_pad directive. */
4173 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4177 if (!unwind.proc_start)
4178 as_bad (MISSING_FNSTART);
4180 if (immediate_for_directive (&offset) == FAIL)
4185 as_bad (_("stack increment must be multiple of 4"));
4186 ignore_rest_of_line ();
4190 /* Don't generate any opcodes, just record the details for later. */
4191 unwind.frame_size += offset;
4192 unwind.pending_offset += offset;
4194 demand_empty_rest_of_line ();
4197 /* Parse an unwind_setfp directive. */
4200 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4206 if (!unwind.proc_start)
4207 as_bad (MISSING_FNSTART);
4209 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4210 if (skip_past_comma (&input_line_pointer) == FAIL)
4213 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4215 if (fp_reg == FAIL || sp_reg == FAIL)
4217 as_bad (_("expected <reg>, <reg>"));
4218 ignore_rest_of_line ();
4222 /* Optional constant. */
4223 if (skip_past_comma (&input_line_pointer) != FAIL)
4225 if (immediate_for_directive (&offset) == FAIL)
4231 demand_empty_rest_of_line ();
4233 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4235 as_bad (_("register must be either sp or set by a previous"
4236 "unwind_movsp directive"));
4240 /* Don't generate any opcodes, just record the information for later. */
4241 unwind.fp_reg = fp_reg;
4243 if (sp_reg == REG_SP)
4244 unwind.fp_offset = unwind.frame_size - offset;
4246 unwind.fp_offset -= offset;
4249 /* Parse an unwind_raw directive. */
4252 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4255 /* This is an arbitrary limit. */
4256 unsigned char op[16];
4259 if (!unwind.proc_start)
4260 as_bad (MISSING_FNSTART);
4263 if (exp.X_op == O_constant
4264 && skip_past_comma (&input_line_pointer) != FAIL)
4266 unwind.frame_size += exp.X_add_number;
4270 exp.X_op = O_illegal;
4272 if (exp.X_op != O_constant)
4274 as_bad (_("expected <offset>, <opcode>"));
4275 ignore_rest_of_line ();
4281 /* Parse the opcode. */
4286 as_bad (_("unwind opcode too long"));
4287 ignore_rest_of_line ();
4289 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4291 as_bad (_("invalid unwind opcode"));
4292 ignore_rest_of_line ();
4295 op[count++] = exp.X_add_number;
4297 /* Parse the next byte. */
4298 if (skip_past_comma (&input_line_pointer) == FAIL)
4304 /* Add the opcode bytes in reverse order. */
4306 add_unwind_opcode (op[count], 1);
4308 demand_empty_rest_of_line ();
4312 /* Parse a .eabi_attribute directive. */
4315 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4317 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4319 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4320 attributes_set_explicitly[tag] = 1;
4323 /* Emit a tls fix for the symbol. */
4326 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4330 #ifdef md_flush_pending_output
4331 md_flush_pending_output ();
4334 #ifdef md_cons_align
4338 /* Since we're just labelling the code, there's no need to define a
4341 p = obstack_next_free (&frchain_now->frch_obstack);
4342 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4343 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4344 : BFD_RELOC_ARM_TLS_DESCSEQ);
4346 #endif /* OBJ_ELF */
4348 static void s_arm_arch (int);
4349 static void s_arm_object_arch (int);
4350 static void s_arm_cpu (int);
4351 static void s_arm_fpu (int);
4352 static void s_arm_arch_extension (int);
4357 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4364 if (exp.X_op == O_symbol)
4365 exp.X_op = O_secrel;
4367 emit_expr (&exp, 4);
4369 while (*input_line_pointer++ == ',');
4371 input_line_pointer--;
4372 demand_empty_rest_of_line ();
4376 /* This table describes all the machine specific pseudo-ops the assembler
4377 has to support. The fields are:
4378 pseudo-op name without dot
4379 function to call to execute this pseudo-op
4380 Integer arg to pass to the function. */
4382 const pseudo_typeS md_pseudo_table[] =
4384 /* Never called because '.req' does not start a line. */
4385 { "req", s_req, 0 },
4386 /* Following two are likewise never called. */
4389 { "unreq", s_unreq, 0 },
4390 { "bss", s_bss, 0 },
4391 { "align", s_align, 0 },
4392 { "arm", s_arm, 0 },
4393 { "thumb", s_thumb, 0 },
4394 { "code", s_code, 0 },
4395 { "force_thumb", s_force_thumb, 0 },
4396 { "thumb_func", s_thumb_func, 0 },
4397 { "thumb_set", s_thumb_set, 0 },
4398 { "even", s_even, 0 },
4399 { "ltorg", s_ltorg, 0 },
4400 { "pool", s_ltorg, 0 },
4401 { "syntax", s_syntax, 0 },
4402 { "cpu", s_arm_cpu, 0 },
4403 { "arch", s_arm_arch, 0 },
4404 { "object_arch", s_arm_object_arch, 0 },
4405 { "fpu", s_arm_fpu, 0 },
4406 { "arch_extension", s_arm_arch_extension, 0 },
4408 { "word", s_arm_elf_cons, 4 },
4409 { "long", s_arm_elf_cons, 4 },
4410 { "inst.n", s_arm_elf_inst, 2 },
4411 { "inst.w", s_arm_elf_inst, 4 },
4412 { "inst", s_arm_elf_inst, 0 },
4413 { "rel31", s_arm_rel31, 0 },
4414 { "fnstart", s_arm_unwind_fnstart, 0 },
4415 { "fnend", s_arm_unwind_fnend, 0 },
4416 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4417 { "personality", s_arm_unwind_personality, 0 },
4418 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4419 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4420 { "save", s_arm_unwind_save, 0 },
4421 { "vsave", s_arm_unwind_save, 1 },
4422 { "movsp", s_arm_unwind_movsp, 0 },
4423 { "pad", s_arm_unwind_pad, 0 },
4424 { "setfp", s_arm_unwind_setfp, 0 },
4425 { "unwind_raw", s_arm_unwind_raw, 0 },
4426 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4427 { "tlsdescseq", s_arm_tls_descseq, 0 },
4431 /* These are used for dwarf. */
4435 /* These are used for dwarf2. */
4436 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4437 { "loc", dwarf2_directive_loc, 0 },
4438 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4440 { "extend", float_cons, 'x' },
4441 { "ldouble", float_cons, 'x' },
4442 { "packed", float_cons, 'p' },
4444 {"secrel32", pe_directive_secrel, 0},
4449 /* Parser functions used exclusively in instruction operands. */
4451 /* Generic immediate-value read function for use in insn parsing.
4452 STR points to the beginning of the immediate (the leading #);
4453 VAL receives the value; if the value is outside [MIN, MAX]
4454 issue an error. PREFIX_OPT is true if the immediate prefix is
4458 parse_immediate (char **str, int *val, int min, int max,
4459 bfd_boolean prefix_opt)
4462 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4463 if (exp.X_op != O_constant)
4465 inst.error = _("constant expression required");
4469 if (exp.X_add_number < min || exp.X_add_number > max)
4471 inst.error = _("immediate value out of range");
4475 *val = exp.X_add_number;
4479 /* Less-generic immediate-value read function with the possibility of loading a
4480 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4481 instructions. Puts the result directly in inst.operands[i]. */
4484 parse_big_immediate (char **str, int i)
4489 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4491 if (exp.X_op == O_constant)
4493 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4494 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4495 O_constant. We have to be careful not to break compilation for
4496 32-bit X_add_number, though. */
4497 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4499 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4500 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4501 inst.operands[i].regisimm = 1;
4504 else if (exp.X_op == O_big
4505 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4507 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4509 /* Bignums have their least significant bits in
4510 generic_bignum[0]. Make sure we put 32 bits in imm and
4511 32 bits in reg, in a (hopefully) portable way. */
4512 gas_assert (parts != 0);
4514 /* Make sure that the number is not too big.
4515 PR 11972: Bignums can now be sign-extended to the
4516 size of a .octa so check that the out of range bits
4517 are all zero or all one. */
4518 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4520 LITTLENUM_TYPE m = -1;
4522 if (generic_bignum[parts * 2] != 0
4523 && generic_bignum[parts * 2] != m)
4526 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4527 if (generic_bignum[j] != generic_bignum[j-1])
4531 inst.operands[i].imm = 0;
4532 for (j = 0; j < parts; j++, idx++)
4533 inst.operands[i].imm |= generic_bignum[idx]
4534 << (LITTLENUM_NUMBER_OF_BITS * j);
4535 inst.operands[i].reg = 0;
4536 for (j = 0; j < parts; j++, idx++)
4537 inst.operands[i].reg |= generic_bignum[idx]
4538 << (LITTLENUM_NUMBER_OF_BITS * j);
4539 inst.operands[i].regisimm = 1;
4549 /* Returns the pseudo-register number of an FPA immediate constant,
4550 or FAIL if there isn't a valid constant here. */
4553 parse_fpa_immediate (char ** str)
4555 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4561 /* First try and match exact strings, this is to guarantee
4562 that some formats will work even for cross assembly. */
4564 for (i = 0; fp_const[i]; i++)
4566 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4570 *str += strlen (fp_const[i]);
4571 if (is_end_of_line[(unsigned char) **str])
4577 /* Just because we didn't get a match doesn't mean that the constant
4578 isn't valid, just that it is in a format that we don't
4579 automatically recognize. Try parsing it with the standard
4580 expression routines. */
4582 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4584 /* Look for a raw floating point number. */
4585 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4586 && is_end_of_line[(unsigned char) *save_in])
4588 for (i = 0; i < NUM_FLOAT_VALS; i++)
4590 for (j = 0; j < MAX_LITTLENUMS; j++)
4592 if (words[j] != fp_values[i][j])
4596 if (j == MAX_LITTLENUMS)
4604 /* Try and parse a more complex expression, this will probably fail
4605 unless the code uses a floating point prefix (eg "0f"). */
4606 save_in = input_line_pointer;
4607 input_line_pointer = *str;
4608 if (expression (&exp) == absolute_section
4609 && exp.X_op == O_big
4610 && exp.X_add_number < 0)
4612 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4614 if (gen_to_words (words, 5, (long) 15) == 0)
4616 for (i = 0; i < NUM_FLOAT_VALS; i++)
4618 for (j = 0; j < MAX_LITTLENUMS; j++)
4620 if (words[j] != fp_values[i][j])
4624 if (j == MAX_LITTLENUMS)
4626 *str = input_line_pointer;
4627 input_line_pointer = save_in;
4634 *str = input_line_pointer;
4635 input_line_pointer = save_in;
4636 inst.error = _("invalid FPA immediate expression");
4640 /* Returns 1 if a number has "quarter-precision" float format
4641 0baBbbbbbc defgh000 00000000 00000000. */
4644 is_quarter_float (unsigned imm)
4646 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4647 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4650 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4651 0baBbbbbbc defgh000 00000000 00000000.
4652 The zero and minus-zero cases need special handling, since they can't be
4653 encoded in the "quarter-precision" float format, but can nonetheless be
4654 loaded as integer constants. */
4657 parse_qfloat_immediate (char **ccp, int *immed)
4661 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4662 int found_fpchar = 0;
4664 skip_past_char (&str, '#');
4666 /* We must not accidentally parse an integer as a floating-point number. Make
4667 sure that the value we parse is not an integer by checking for special
4668 characters '.' or 'e'.
4669 FIXME: This is a horrible hack, but doing better is tricky because type
4670 information isn't in a very usable state at parse time. */
4672 skip_whitespace (fpnum);
4674 if (strncmp (fpnum, "0x", 2) == 0)
4678 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4679 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4689 if ((str = atof_ieee (str, 's', words)) != NULL)
4691 unsigned fpword = 0;
4694 /* Our FP word must be 32 bits (single-precision FP). */
4695 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4697 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4701 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4714 /* Shift operands. */
4717 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4720 struct asm_shift_name
4723 enum shift_kind kind;
4726 /* Third argument to parse_shift. */
4727 enum parse_shift_mode
4729 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4730 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4731 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4732 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4733 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4736 /* Parse a <shift> specifier on an ARM data processing instruction.
4737 This has three forms:
4739 (LSL|LSR|ASL|ASR|ROR) Rs
4740 (LSL|LSR|ASL|ASR|ROR) #imm
4743 Note that ASL is assimilated to LSL in the instruction encoding, and
4744 RRX to ROR #0 (which cannot be written as such). */
4747 parse_shift (char **str, int i, enum parse_shift_mode mode)
4749 const struct asm_shift_name *shift_name;
4750 enum shift_kind shift;
4755 for (p = *str; ISALPHA (*p); p++)
4760 inst.error = _("shift expression expected");
4764 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4767 if (shift_name == NULL)
4769 inst.error = _("shift expression expected");
4773 shift = shift_name->kind;
4777 case NO_SHIFT_RESTRICT:
4778 case SHIFT_IMMEDIATE: break;
4780 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4781 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4783 inst.error = _("'LSL' or 'ASR' required");
4788 case SHIFT_LSL_IMMEDIATE:
4789 if (shift != SHIFT_LSL)
4791 inst.error = _("'LSL' required");
4796 case SHIFT_ASR_IMMEDIATE:
4797 if (shift != SHIFT_ASR)
4799 inst.error = _("'ASR' required");
4807 if (shift != SHIFT_RRX)
4809 /* Whitespace can appear here if the next thing is a bare digit. */
4810 skip_whitespace (p);
4812 if (mode == NO_SHIFT_RESTRICT
4813 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4815 inst.operands[i].imm = reg;
4816 inst.operands[i].immisreg = 1;
4818 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4821 inst.operands[i].shift_kind = shift;
4822 inst.operands[i].shifted = 1;
4827 /* Parse a <shifter_operand> for an ARM data processing instruction:
4830 #<immediate>, <rotate>
4834 where <shift> is defined by parse_shift above, and <rotate> is a
4835 multiple of 2 between 0 and 30. Validation of immediate operands
4836 is deferred to md_apply_fix. */
4839 parse_shifter_operand (char **str, int i)
4844 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4846 inst.operands[i].reg = value;
4847 inst.operands[i].isreg = 1;
4849 /* parse_shift will override this if appropriate */
4850 inst.reloc.exp.X_op = O_constant;
4851 inst.reloc.exp.X_add_number = 0;
4853 if (skip_past_comma (str) == FAIL)
4856 /* Shift operation on register. */
4857 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4860 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4863 if (skip_past_comma (str) == SUCCESS)
4865 /* #x, y -- ie explicit rotation by Y. */
4866 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4869 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4871 inst.error = _("constant expression expected");
4875 value = exp.X_add_number;
4876 if (value < 0 || value > 30 || value % 2 != 0)
4878 inst.error = _("invalid rotation");
4881 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4883 inst.error = _("invalid constant");
4887 /* Convert to decoded value. md_apply_fix will put it back. */
4888 inst.reloc.exp.X_add_number
4889 = (((inst.reloc.exp.X_add_number << (32 - value))
4890 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
4893 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4894 inst.reloc.pc_rel = 0;
4898 /* Group relocation information. Each entry in the table contains the
4899 textual name of the relocation as may appear in assembler source
4900 and must end with a colon.
4901 Along with this textual name are the relocation codes to be used if
4902 the corresponding instruction is an ALU instruction (ADD or SUB only),
4903 an LDR, an LDRS, or an LDC. */
4905 struct group_reloc_table_entry
4916 /* Varieties of non-ALU group relocation. */
4923 static struct group_reloc_table_entry group_reloc_table[] =
4924 { /* Program counter relative: */
4926 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4931 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4932 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4933 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4934 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4936 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4941 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4942 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4943 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4944 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4946 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4947 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4948 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4949 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4950 /* Section base relative */
4952 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4957 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4958 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4959 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4960 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4962 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4967 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4968 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4969 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4970 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4972 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4973 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4974 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4975 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4977 /* Given the address of a pointer pointing to the textual name of a group
4978 relocation as may appear in assembler source, attempt to find its details
4979 in group_reloc_table. The pointer will be updated to the character after
4980 the trailing colon. On failure, FAIL will be returned; SUCCESS
4981 otherwise. On success, *entry will be updated to point at the relevant
4982 group_reloc_table entry. */
4985 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4988 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4990 int length = strlen (group_reloc_table[i].name);
4992 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
4993 && (*str)[length] == ':')
4995 *out = &group_reloc_table[i];
4996 *str += (length + 1);
5004 /* Parse a <shifter_operand> for an ARM data processing instruction
5005 (as for parse_shifter_operand) where group relocations are allowed:
5008 #<immediate>, <rotate>
5009 #:<group_reloc>:<expression>
5013 where <group_reloc> is one of the strings defined in group_reloc_table.
5014 The hashes are optional.
5016 Everything else is as for parse_shifter_operand. */
5018 static parse_operand_result
5019 parse_shifter_operand_group_reloc (char **str, int i)
5021 /* Determine if we have the sequence of characters #: or just :
5022 coming next. If we do, then we check for a group relocation.
5023 If we don't, punt the whole lot to parse_shifter_operand. */
5025 if (((*str)[0] == '#' && (*str)[1] == ':')
5026 || (*str)[0] == ':')
5028 struct group_reloc_table_entry *entry;
5030 if ((*str)[0] == '#')
5035 /* Try to parse a group relocation. Anything else is an error. */
5036 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5038 inst.error = _("unknown group relocation");
5039 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5042 /* We now have the group relocation table entry corresponding to
5043 the name in the assembler source. Next, we parse the expression. */
5044 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5045 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5047 /* Record the relocation type (always the ALU variant here). */
5048 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5049 gas_assert (inst.reloc.type != 0);
5051 return PARSE_OPERAND_SUCCESS;
5054 return parse_shifter_operand (str, i) == SUCCESS
5055 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5057 /* Never reached. */
5060 /* Parse a Neon alignment expression. Information is written to
5061 inst.operands[i]. We assume the initial ':' has been skipped.
5063 align .imm = align << 8, .immisalign=1, .preind=0 */
5064 static parse_operand_result
5065 parse_neon_alignment (char **str, int i)
5070 my_get_expression (&exp, &p, GE_NO_PREFIX);
5072 if (exp.X_op != O_constant)
5074 inst.error = _("alignment must be constant");
5075 return PARSE_OPERAND_FAIL;
5078 inst.operands[i].imm = exp.X_add_number << 8;
5079 inst.operands[i].immisalign = 1;
5080 /* Alignments are not pre-indexes. */
5081 inst.operands[i].preind = 0;
5084 return PARSE_OPERAND_SUCCESS;
5087 /* Parse all forms of an ARM address expression. Information is written
5088 to inst.operands[i] and/or inst.reloc.
5090 Preindexed addressing (.preind=1):
5092 [Rn, #offset] .reg=Rn .reloc.exp=offset
5093 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5094 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5095 .shift_kind=shift .reloc.exp=shift_imm
5097 These three may have a trailing ! which causes .writeback to be set also.
5099 Postindexed addressing (.postind=1, .writeback=1):
5101 [Rn], #offset .reg=Rn .reloc.exp=offset
5102 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5103 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5104 .shift_kind=shift .reloc.exp=shift_imm
5106 Unindexed addressing (.preind=0, .postind=0):
5108 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5112 [Rn]{!} shorthand for [Rn,#0]{!}
5113 =immediate .isreg=0 .reloc.exp=immediate
5114 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5116 It is the caller's responsibility to check for addressing modes not
5117 supported by the instruction, and to set inst.reloc.type. */
5119 static parse_operand_result
5120 parse_address_main (char **str, int i, int group_relocations,
5121 group_reloc_type group_type)
5126 if (skip_past_char (&p, '[') == FAIL)
5128 if (skip_past_char (&p, '=') == FAIL)
5130 /* Bare address - translate to PC-relative offset. */
5131 inst.reloc.pc_rel = 1;
5132 inst.operands[i].reg = REG_PC;
5133 inst.operands[i].isreg = 1;
5134 inst.operands[i].preind = 1;
5136 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5138 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5139 return PARSE_OPERAND_FAIL;
5142 return PARSE_OPERAND_SUCCESS;
5145 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5147 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5148 return PARSE_OPERAND_FAIL;
5150 inst.operands[i].reg = reg;
5151 inst.operands[i].isreg = 1;
5153 if (skip_past_comma (&p) == SUCCESS)
5155 inst.operands[i].preind = 1;
5158 else if (*p == '-') p++, inst.operands[i].negative = 1;
5160 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5162 inst.operands[i].imm = reg;
5163 inst.operands[i].immisreg = 1;
5165 if (skip_past_comma (&p) == SUCCESS)
5166 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5167 return PARSE_OPERAND_FAIL;
5169 else if (skip_past_char (&p, ':') == SUCCESS)
5171 /* FIXME: '@' should be used here, but it's filtered out by generic
5172 code before we get to see it here. This may be subject to
5174 parse_operand_result result = parse_neon_alignment (&p, i);
5176 if (result != PARSE_OPERAND_SUCCESS)
5181 if (inst.operands[i].negative)
5183 inst.operands[i].negative = 0;
5187 if (group_relocations
5188 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5190 struct group_reloc_table_entry *entry;
5192 /* Skip over the #: or : sequence. */
5198 /* Try to parse a group relocation. Anything else is an
5200 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5202 inst.error = _("unknown group relocation");
5203 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5206 /* We now have the group relocation table entry corresponding to
5207 the name in the assembler source. Next, we parse the
5209 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5210 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5212 /* Record the relocation type. */
5216 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5220 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5224 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5231 if (inst.reloc.type == 0)
5233 inst.error = _("this group relocation is not allowed on this instruction");
5234 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5240 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5241 return PARSE_OPERAND_FAIL;
5242 /* If the offset is 0, find out if it's a +0 or -0. */
5243 if (inst.reloc.exp.X_op == O_constant
5244 && inst.reloc.exp.X_add_number == 0)
5246 skip_whitespace (q);
5250 skip_whitespace (q);
5253 inst.operands[i].negative = 1;
5258 else if (skip_past_char (&p, ':') == SUCCESS)
5260 /* FIXME: '@' should be used here, but it's filtered out by generic code
5261 before we get to see it here. This may be subject to change. */
5262 parse_operand_result result = parse_neon_alignment (&p, i);
5264 if (result != PARSE_OPERAND_SUCCESS)
5268 if (skip_past_char (&p, ']') == FAIL)
5270 inst.error = _("']' expected");
5271 return PARSE_OPERAND_FAIL;
5274 if (skip_past_char (&p, '!') == SUCCESS)
5275 inst.operands[i].writeback = 1;
5277 else if (skip_past_comma (&p) == SUCCESS)
5279 if (skip_past_char (&p, '{') == SUCCESS)
5281 /* [Rn], {expr} - unindexed, with option */
5282 if (parse_immediate (&p, &inst.operands[i].imm,
5283 0, 255, TRUE) == FAIL)
5284 return PARSE_OPERAND_FAIL;
5286 if (skip_past_char (&p, '}') == FAIL)
5288 inst.error = _("'}' expected at end of 'option' field");
5289 return PARSE_OPERAND_FAIL;
5291 if (inst.operands[i].preind)
5293 inst.error = _("cannot combine index with option");
5294 return PARSE_OPERAND_FAIL;
5297 return PARSE_OPERAND_SUCCESS;
5301 inst.operands[i].postind = 1;
5302 inst.operands[i].writeback = 1;
5304 if (inst.operands[i].preind)
5306 inst.error = _("cannot combine pre- and post-indexing");
5307 return PARSE_OPERAND_FAIL;
5311 else if (*p == '-') p++, inst.operands[i].negative = 1;
5313 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5315 /* We might be using the immediate for alignment already. If we
5316 are, OR the register number into the low-order bits. */
5317 if (inst.operands[i].immisalign)
5318 inst.operands[i].imm |= reg;
5320 inst.operands[i].imm = reg;
5321 inst.operands[i].immisreg = 1;
5323 if (skip_past_comma (&p) == SUCCESS)
5324 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5325 return PARSE_OPERAND_FAIL;
5330 if (inst.operands[i].negative)
5332 inst.operands[i].negative = 0;
5335 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5336 return PARSE_OPERAND_FAIL;
5337 /* If the offset is 0, find out if it's a +0 or -0. */
5338 if (inst.reloc.exp.X_op == O_constant
5339 && inst.reloc.exp.X_add_number == 0)
5341 skip_whitespace (q);
5345 skip_whitespace (q);
5348 inst.operands[i].negative = 1;
5354 /* If at this point neither .preind nor .postind is set, we have a
5355 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5356 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5358 inst.operands[i].preind = 1;
5359 inst.reloc.exp.X_op = O_constant;
5360 inst.reloc.exp.X_add_number = 0;
5363 return PARSE_OPERAND_SUCCESS;
5367 parse_address (char **str, int i)
5369 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5373 static parse_operand_result
5374 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5376 return parse_address_main (str, i, 1, type);
5379 /* Parse an operand for a MOVW or MOVT instruction. */
5381 parse_half (char **str)
5386 skip_past_char (&p, '#');
5387 if (strncasecmp (p, ":lower16:", 9) == 0)
5388 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5389 else if (strncasecmp (p, ":upper16:", 9) == 0)
5390 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5392 if (inst.reloc.type != BFD_RELOC_UNUSED)
5395 skip_whitespace (p);
5398 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5401 if (inst.reloc.type == BFD_RELOC_UNUSED)
5403 if (inst.reloc.exp.X_op != O_constant)
5405 inst.error = _("constant expression expected");
5408 if (inst.reloc.exp.X_add_number < 0
5409 || inst.reloc.exp.X_add_number > 0xffff)
5411 inst.error = _("immediate value out of range");
5419 /* Miscellaneous. */
5421 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5422 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5424 parse_psr (char **str, bfd_boolean lhs)
5427 unsigned long psr_field;
5428 const struct asm_psr *psr;
5430 bfd_boolean is_apsr = FALSE;
5431 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5433 /* PR gas/12698: If the user has specified -march=all then m_profile will
5434 be TRUE, but we want to ignore it in this case as we are building for any
5435 CPU type, including non-m variants. */
5436 if (selected_cpu.core == arm_arch_any.core)
5439 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5440 feature for ease of use and backwards compatibility. */
5442 if (strncasecmp (p, "SPSR", 4) == 0)
5445 goto unsupported_psr;
5447 psr_field = SPSR_BIT;
5449 else if (strncasecmp (p, "CPSR", 4) == 0)
5452 goto unsupported_psr;
5456 else if (strncasecmp (p, "APSR", 4) == 0)
5458 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5459 and ARMv7-R architecture CPUs. */
5468 while (ISALNUM (*p) || *p == '_');
5470 if (strncasecmp (start, "iapsr", 5) == 0
5471 || strncasecmp (start, "eapsr", 5) == 0
5472 || strncasecmp (start, "xpsr", 4) == 0
5473 || strncasecmp (start, "psr", 3) == 0)
5474 p = start + strcspn (start, "rR") + 1;
5476 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5482 /* If APSR is being written, a bitfield may be specified. Note that
5483 APSR itself is handled above. */
5484 if (psr->field <= 3)
5486 psr_field = psr->field;
5492 /* M-profile MSR instructions have the mask field set to "10", except
5493 *PSR variants which modify APSR, which may use a different mask (and
5494 have been handled already). Do that by setting the PSR_f field
5496 return psr->field | (lhs ? PSR_f : 0);
5499 goto unsupported_psr;
5505 /* A suffix follows. */
5511 while (ISALNUM (*p) || *p == '_');
5515 /* APSR uses a notation for bits, rather than fields. */
5516 unsigned int nzcvq_bits = 0;
5517 unsigned int g_bit = 0;
5520 for (bit = start; bit != p; bit++)
5522 switch (TOLOWER (*bit))
5525 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5529 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5533 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5537 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5541 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5545 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5549 inst.error = _("unexpected bit specified after APSR");
5554 if (nzcvq_bits == 0x1f)
5559 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5561 inst.error = _("selected processor does not "
5562 "support DSP extension");
5569 if ((nzcvq_bits & 0x20) != 0
5570 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5571 || (g_bit & 0x2) != 0)
5573 inst.error = _("bad bitmask specified after APSR");
5579 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5584 psr_field |= psr->field;
5590 goto error; /* Garbage after "[CS]PSR". */
5592 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5593 is deprecated, but allow it anyway. */
5597 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5600 else if (!m_profile)
5601 /* These bits are never right for M-profile devices: don't set them
5602 (only code paths which read/write APSR reach here). */
5603 psr_field |= (PSR_c | PSR_f);
5609 inst.error = _("selected processor does not support requested special "
5610 "purpose register");
5614 inst.error = _("flag for {c}psr instruction expected");
5618 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5619 value suitable for splatting into the AIF field of the instruction. */
5622 parse_cps_flags (char **str)
5631 case '\0': case ',':
5634 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5635 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5636 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5639 inst.error = _("unrecognized CPS flag");
5644 if (saw_a_flag == 0)
5646 inst.error = _("missing CPS flags");
5654 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5655 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5658 parse_endian_specifier (char **str)
5663 if (strncasecmp (s, "BE", 2))
5665 else if (strncasecmp (s, "LE", 2))
5669 inst.error = _("valid endian specifiers are be or le");
5673 if (ISALNUM (s[2]) || s[2] == '_')
5675 inst.error = _("valid endian specifiers are be or le");
5680 return little_endian;
5683 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5684 value suitable for poking into the rotate field of an sxt or sxta
5685 instruction, or FAIL on error. */
5688 parse_ror (char **str)
5693 if (strncasecmp (s, "ROR", 3) == 0)
5697 inst.error = _("missing rotation field after comma");
5701 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5706 case 0: *str = s; return 0x0;
5707 case 8: *str = s; return 0x1;
5708 case 16: *str = s; return 0x2;
5709 case 24: *str = s; return 0x3;
5712 inst.error = _("rotation can only be 0, 8, 16, or 24");
5717 /* Parse a conditional code (from conds[] below). The value returned is in the
5718 range 0 .. 14, or FAIL. */
5720 parse_cond (char **str)
5723 const struct asm_cond *c;
5725 /* Condition codes are always 2 characters, so matching up to
5726 3 characters is sufficient. */
5731 while (ISALPHA (*q) && n < 3)
5733 cond[n] = TOLOWER (*q);
5738 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5741 inst.error = _("condition required");
5749 /* Parse an option for a barrier instruction. Returns the encoding for the
5752 parse_barrier (char **str)
5755 const struct asm_barrier_opt *o;
5758 while (ISALPHA (*q))
5761 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5770 /* Parse the operands of a table branch instruction. Similar to a memory
5773 parse_tb (char **str)
5778 if (skip_past_char (&p, '[') == FAIL)
5780 inst.error = _("'[' expected");
5784 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5786 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5789 inst.operands[0].reg = reg;
5791 if (skip_past_comma (&p) == FAIL)
5793 inst.error = _("',' expected");
5797 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5799 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5802 inst.operands[0].imm = reg;
5804 if (skip_past_comma (&p) == SUCCESS)
5806 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5808 if (inst.reloc.exp.X_add_number != 1)
5810 inst.error = _("invalid shift");
5813 inst.operands[0].shifted = 1;
5816 if (skip_past_char (&p, ']') == FAIL)
5818 inst.error = _("']' expected");
5825 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5826 information on the types the operands can take and how they are encoded.
5827 Up to four operands may be read; this function handles setting the
5828 ".present" field for each read operand itself.
5829 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5830 else returns FAIL. */
5833 parse_neon_mov (char **str, int *which_operand)
5835 int i = *which_operand, val;
5836 enum arm_reg_type rtype;
5838 struct neon_type_el optype;
5840 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5842 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5843 inst.operands[i].reg = val;
5844 inst.operands[i].isscalar = 1;
5845 inst.operands[i].vectype = optype;
5846 inst.operands[i++].present = 1;
5848 if (skip_past_comma (&ptr) == FAIL)
5851 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5854 inst.operands[i].reg = val;
5855 inst.operands[i].isreg = 1;
5856 inst.operands[i].present = 1;
5858 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5861 /* Cases 0, 1, 2, 3, 5 (D only). */
5862 if (skip_past_comma (&ptr) == FAIL)
5865 inst.operands[i].reg = val;
5866 inst.operands[i].isreg = 1;
5867 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5868 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5869 inst.operands[i].isvec = 1;
5870 inst.operands[i].vectype = optype;
5871 inst.operands[i++].present = 1;
5873 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5875 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5876 Case 13: VMOV <Sd>, <Rm> */
5877 inst.operands[i].reg = val;
5878 inst.operands[i].isreg = 1;
5879 inst.operands[i].present = 1;
5881 if (rtype == REG_TYPE_NQ)
5883 first_error (_("can't use Neon quad register here"));
5886 else if (rtype != REG_TYPE_VFS)
5889 if (skip_past_comma (&ptr) == FAIL)
5891 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5893 inst.operands[i].reg = val;
5894 inst.operands[i].isreg = 1;
5895 inst.operands[i].present = 1;
5898 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5901 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5902 Case 1: VMOV<c><q> <Dd>, <Dm>
5903 Case 8: VMOV.F32 <Sd>, <Sm>
5904 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5906 inst.operands[i].reg = val;
5907 inst.operands[i].isreg = 1;
5908 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5909 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5910 inst.operands[i].isvec = 1;
5911 inst.operands[i].vectype = optype;
5912 inst.operands[i].present = 1;
5914 if (skip_past_comma (&ptr) == SUCCESS)
5919 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5922 inst.operands[i].reg = val;
5923 inst.operands[i].isreg = 1;
5924 inst.operands[i++].present = 1;
5926 if (skip_past_comma (&ptr) == FAIL)
5929 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5932 inst.operands[i].reg = val;
5933 inst.operands[i].isreg = 1;
5934 inst.operands[i++].present = 1;
5937 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5938 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5939 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5940 Case 10: VMOV.F32 <Sd>, #<imm>
5941 Case 11: VMOV.F64 <Dd>, #<imm> */
5942 inst.operands[i].immisfloat = 1;
5943 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5944 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5945 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5949 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5953 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5956 inst.operands[i].reg = val;
5957 inst.operands[i].isreg = 1;
5958 inst.operands[i++].present = 1;
5960 if (skip_past_comma (&ptr) == FAIL)
5963 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5965 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5966 inst.operands[i].reg = val;
5967 inst.operands[i].isscalar = 1;
5968 inst.operands[i].present = 1;
5969 inst.operands[i].vectype = optype;
5971 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5973 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5974 inst.operands[i].reg = val;
5975 inst.operands[i].isreg = 1;
5976 inst.operands[i++].present = 1;
5978 if (skip_past_comma (&ptr) == FAIL)
5981 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5984 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5988 inst.operands[i].reg = val;
5989 inst.operands[i].isreg = 1;
5990 inst.operands[i].isvec = 1;
5991 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5992 inst.operands[i].vectype = optype;
5993 inst.operands[i].present = 1;
5995 if (rtype == REG_TYPE_VFS)
5999 if (skip_past_comma (&ptr) == FAIL)
6001 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6004 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6007 inst.operands[i].reg = val;
6008 inst.operands[i].isreg = 1;
6009 inst.operands[i].isvec = 1;
6010 inst.operands[i].issingle = 1;
6011 inst.operands[i].vectype = optype;
6012 inst.operands[i].present = 1;
6015 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6019 inst.operands[i].reg = val;
6020 inst.operands[i].isreg = 1;
6021 inst.operands[i].isvec = 1;
6022 inst.operands[i].issingle = 1;
6023 inst.operands[i].vectype = optype;
6024 inst.operands[i++].present = 1;
6029 first_error (_("parse error"));
6033 /* Successfully parsed the operands. Update args. */
6039 first_error (_("expected comma"));
6043 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6047 /* Use this macro when the operand constraints are different
6048 for ARM and THUMB (e.g. ldrd). */
6049 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6050 ((arm_operand) | ((thumb_operand) << 16))
6052 /* Matcher codes for parse_operands. */
6053 enum operand_parse_code
6055 OP_stop, /* end of line */
6057 OP_RR, /* ARM register */
6058 OP_RRnpc, /* ARM register, not r15 */
6059 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6060 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6061 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6062 optional trailing ! */
6063 OP_RRw, /* ARM register, not r15, optional trailing ! */
6064 OP_RCP, /* Coprocessor number */
6065 OP_RCN, /* Coprocessor register */
6066 OP_RF, /* FPA register */
6067 OP_RVS, /* VFP single precision register */
6068 OP_RVD, /* VFP double precision register (0..15) */
6069 OP_RND, /* Neon double precision register (0..31) */
6070 OP_RNQ, /* Neon quad precision register */
6071 OP_RVSD, /* VFP single or double precision register */
6072 OP_RNDQ, /* Neon double or quad precision register */
6073 OP_RNSDQ, /* Neon single, double or quad precision register */
6074 OP_RNSC, /* Neon scalar D[X] */
6075 OP_RVC, /* VFP control register */
6076 OP_RMF, /* Maverick F register */
6077 OP_RMD, /* Maverick D register */
6078 OP_RMFX, /* Maverick FX register */
6079 OP_RMDX, /* Maverick DX register */
6080 OP_RMAX, /* Maverick AX register */
6081 OP_RMDS, /* Maverick DSPSC register */
6082 OP_RIWR, /* iWMMXt wR register */
6083 OP_RIWC, /* iWMMXt wC register */
6084 OP_RIWG, /* iWMMXt wCG register */
6085 OP_RXA, /* XScale accumulator register */
6087 OP_REGLST, /* ARM register list */
6088 OP_VRSLST, /* VFP single-precision register list */
6089 OP_VRDLST, /* VFP double-precision register list */
6090 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6091 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6092 OP_NSTRLST, /* Neon element/structure list */
6094 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6095 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6096 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6097 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6098 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6099 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6100 OP_VMOV, /* Neon VMOV operands. */
6101 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6102 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6103 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6105 OP_I0, /* immediate zero */
6106 OP_I7, /* immediate value 0 .. 7 */
6107 OP_I15, /* 0 .. 15 */
6108 OP_I16, /* 1 .. 16 */
6109 OP_I16z, /* 0 .. 16 */
6110 OP_I31, /* 0 .. 31 */
6111 OP_I31w, /* 0 .. 31, optional trailing ! */
6112 OP_I32, /* 1 .. 32 */
6113 OP_I32z, /* 0 .. 32 */
6114 OP_I63, /* 0 .. 63 */
6115 OP_I63s, /* -64 .. 63 */
6116 OP_I64, /* 1 .. 64 */
6117 OP_I64z, /* 0 .. 64 */
6118 OP_I255, /* 0 .. 255 */
6120 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6121 OP_I7b, /* 0 .. 7 */
6122 OP_I15b, /* 0 .. 15 */
6123 OP_I31b, /* 0 .. 31 */
6125 OP_SH, /* shifter operand */
6126 OP_SHG, /* shifter operand with possible group relocation */
6127 OP_ADDR, /* Memory address expression (any mode) */
6128 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6129 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6130 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6131 OP_EXP, /* arbitrary expression */
6132 OP_EXPi, /* same, with optional immediate prefix */
6133 OP_EXPr, /* same, with optional relocation suffix */
6134 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6136 OP_CPSF, /* CPS flags */
6137 OP_ENDI, /* Endianness specifier */
6138 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6139 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6140 OP_COND, /* conditional code */
6141 OP_TB, /* Table branch. */
6143 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6145 OP_RRnpc_I0, /* ARM register or literal 0 */
6146 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6147 OP_RR_EXi, /* ARM register or expression with imm prefix */
6148 OP_RF_IF, /* FPA register or immediate */
6149 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6150 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6152 /* Optional operands. */
6153 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6154 OP_oI31b, /* 0 .. 31 */
6155 OP_oI32b, /* 1 .. 32 */
6156 OP_oI32z, /* 0 .. 32 */
6157 OP_oIffffb, /* 0 .. 65535 */
6158 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6160 OP_oRR, /* ARM register */
6161 OP_oRRnpc, /* ARM register, not the PC */
6162 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6163 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6164 OP_oRND, /* Optional Neon double precision register */
6165 OP_oRNQ, /* Optional Neon quad precision register */
6166 OP_oRNDQ, /* Optional Neon double or quad precision register */
6167 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6168 OP_oSHll, /* LSL immediate */
6169 OP_oSHar, /* ASR immediate */
6170 OP_oSHllar, /* LSL or ASR immediate */
6171 OP_oROR, /* ROR 0/8/16/24 */
6172 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6174 /* Some pre-defined mixed (ARM/THUMB) operands. */
6175 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6176 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6177 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6179 OP_FIRST_OPTIONAL = OP_oI7b
6182 /* Generic instruction operand parser. This does no encoding and no
6183 semantic validation; it merely squirrels values away in the inst
6184 structure. Returns SUCCESS or FAIL depending on whether the
6185 specified grammar matched. */
6187 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6189 unsigned const int *upat = pattern;
6190 char *backtrack_pos = 0;
6191 const char *backtrack_error = 0;
6192 int i, val, backtrack_index = 0;
6193 enum arm_reg_type rtype;
6194 parse_operand_result result;
6195 unsigned int op_parse_code;
6197 #define po_char_or_fail(chr) \
6200 if (skip_past_char (&str, chr) == FAIL) \
6205 #define po_reg_or_fail(regtype) \
6208 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6209 & inst.operands[i].vectype); \
6212 first_error (_(reg_expected_msgs[regtype])); \
6215 inst.operands[i].reg = val; \
6216 inst.operands[i].isreg = 1; \
6217 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6218 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6219 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6220 || rtype == REG_TYPE_VFD \
6221 || rtype == REG_TYPE_NQ); \
6225 #define po_reg_or_goto(regtype, label) \
6228 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6229 & inst.operands[i].vectype); \
6233 inst.operands[i].reg = val; \
6234 inst.operands[i].isreg = 1; \
6235 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6236 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6237 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6238 || rtype == REG_TYPE_VFD \
6239 || rtype == REG_TYPE_NQ); \
6243 #define po_imm_or_fail(min, max, popt) \
6246 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6248 inst.operands[i].imm = val; \
6252 #define po_scalar_or_goto(elsz, label) \
6255 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6258 inst.operands[i].reg = val; \
6259 inst.operands[i].isscalar = 1; \
6263 #define po_misc_or_fail(expr) \
6271 #define po_misc_or_fail_no_backtrack(expr) \
6275 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6276 backtrack_pos = 0; \
6277 if (result != PARSE_OPERAND_SUCCESS) \
6282 #define po_barrier_or_imm(str) \
6285 val = parse_barrier (&str); \
6288 if (ISALPHA (*str)) \
6295 if ((inst.instruction & 0xf0) == 0x60 \
6298 /* ISB can only take SY as an option. */ \
6299 inst.error = _("invalid barrier type"); \
6306 skip_whitespace (str);
6308 for (i = 0; upat[i] != OP_stop; i++)
6310 op_parse_code = upat[i];
6311 if (op_parse_code >= 1<<16)
6312 op_parse_code = thumb ? (op_parse_code >> 16)
6313 : (op_parse_code & ((1<<16)-1));
6315 if (op_parse_code >= OP_FIRST_OPTIONAL)
6317 /* Remember where we are in case we need to backtrack. */
6318 gas_assert (!backtrack_pos);
6319 backtrack_pos = str;
6320 backtrack_error = inst.error;
6321 backtrack_index = i;
6324 if (i > 0 && (i > 1 || inst.operands[0].present))
6325 po_char_or_fail (',');
6327 switch (op_parse_code)
6335 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6336 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6337 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6338 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6339 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6340 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6342 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6344 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6346 /* Also accept generic coprocessor regs for unknown registers. */
6348 po_reg_or_fail (REG_TYPE_CN);
6350 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6351 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6352 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6353 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6354 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6355 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6356 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6357 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6358 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6359 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6361 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6363 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6364 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6366 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6368 /* Neon scalar. Using an element size of 8 means that some invalid
6369 scalars are accepted here, so deal with those in later code. */
6370 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6374 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6377 po_imm_or_fail (0, 0, TRUE);
6382 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6387 po_scalar_or_goto (8, try_rr);
6390 po_reg_or_fail (REG_TYPE_RN);
6396 po_scalar_or_goto (8, try_nsdq);
6399 po_reg_or_fail (REG_TYPE_NSDQ);
6405 po_scalar_or_goto (8, try_ndq);
6408 po_reg_or_fail (REG_TYPE_NDQ);
6414 po_scalar_or_goto (8, try_vfd);
6417 po_reg_or_fail (REG_TYPE_VFD);
6422 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6423 not careful then bad things might happen. */
6424 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6429 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6432 /* There's a possibility of getting a 64-bit immediate here, so
6433 we need special handling. */
6434 if (parse_big_immediate (&str, i) == FAIL)
6436 inst.error = _("immediate value is out of range");
6444 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6447 po_imm_or_fail (0, 63, TRUE);
6452 po_char_or_fail ('[');
6453 po_reg_or_fail (REG_TYPE_RN);
6454 po_char_or_fail (']');
6460 po_reg_or_fail (REG_TYPE_RN);
6461 if (skip_past_char (&str, '!') == SUCCESS)
6462 inst.operands[i].writeback = 1;
6466 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6467 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6468 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6469 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6470 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6471 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6472 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6473 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6474 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6475 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6476 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6477 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6479 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6481 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6482 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6484 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6485 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6486 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6487 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6489 /* Immediate variants */
6491 po_char_or_fail ('{');
6492 po_imm_or_fail (0, 255, TRUE);
6493 po_char_or_fail ('}');
6497 /* The expression parser chokes on a trailing !, so we have
6498 to find it first and zap it. */
6501 while (*s && *s != ',')
6506 inst.operands[i].writeback = 1;
6508 po_imm_or_fail (0, 31, TRUE);
6516 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6521 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6526 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6528 if (inst.reloc.exp.X_op == O_symbol)
6530 val = parse_reloc (&str);
6533 inst.error = _("unrecognized relocation suffix");
6536 else if (val != BFD_RELOC_UNUSED)
6538 inst.operands[i].imm = val;
6539 inst.operands[i].hasreloc = 1;
6544 /* Operand for MOVW or MOVT. */
6546 po_misc_or_fail (parse_half (&str));
6549 /* Register or expression. */
6550 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6551 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6553 /* Register or immediate. */
6554 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6555 I0: po_imm_or_fail (0, 0, FALSE); break;
6557 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6559 if (!is_immediate_prefix (*str))
6562 val = parse_fpa_immediate (&str);
6565 /* FPA immediates are encoded as registers 8-15.
6566 parse_fpa_immediate has already applied the offset. */
6567 inst.operands[i].reg = val;
6568 inst.operands[i].isreg = 1;
6571 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6572 I32z: po_imm_or_fail (0, 32, FALSE); break;
6574 /* Two kinds of register. */
6577 struct reg_entry *rege = arm_reg_parse_multi (&str);
6579 || (rege->type != REG_TYPE_MMXWR
6580 && rege->type != REG_TYPE_MMXWC
6581 && rege->type != REG_TYPE_MMXWCG))
6583 inst.error = _("iWMMXt data or control register expected");
6586 inst.operands[i].reg = rege->number;
6587 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6593 struct reg_entry *rege = arm_reg_parse_multi (&str);
6595 || (rege->type != REG_TYPE_MMXWC
6596 && rege->type != REG_TYPE_MMXWCG))
6598 inst.error = _("iWMMXt control register expected");
6601 inst.operands[i].reg = rege->number;
6602 inst.operands[i].isreg = 1;
6607 case OP_CPSF: val = parse_cps_flags (&str); break;
6608 case OP_ENDI: val = parse_endian_specifier (&str); break;
6609 case OP_oROR: val = parse_ror (&str); break;
6610 case OP_COND: val = parse_cond (&str); break;
6611 case OP_oBARRIER_I15:
6612 po_barrier_or_imm (str); break;
6614 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6620 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6621 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6623 inst.error = _("Banked registers are not available with this "
6629 val = parse_psr (&str, op_parse_code == OP_wPSR);
6633 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6636 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6638 if (strncasecmp (str, "APSR_", 5) == 0)
6645 case 'c': found = (found & 1) ? 16 : found | 1; break;
6646 case 'n': found = (found & 2) ? 16 : found | 2; break;
6647 case 'z': found = (found & 4) ? 16 : found | 4; break;
6648 case 'v': found = (found & 8) ? 16 : found | 8; break;
6649 default: found = 16;
6653 inst.operands[i].isvec = 1;
6654 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6655 inst.operands[i].reg = REG_PC;
6662 po_misc_or_fail (parse_tb (&str));
6665 /* Register lists. */
6667 val = parse_reg_list (&str);
6670 inst.operands[1].writeback = 1;
6676 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6680 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6684 /* Allow Q registers too. */
6685 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6690 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6692 inst.operands[i].issingle = 1;
6697 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6702 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6703 &inst.operands[i].vectype);
6706 /* Addressing modes */
6708 po_misc_or_fail (parse_address (&str, i));
6712 po_misc_or_fail_no_backtrack (
6713 parse_address_group_reloc (&str, i, GROUP_LDR));
6717 po_misc_or_fail_no_backtrack (
6718 parse_address_group_reloc (&str, i, GROUP_LDRS));
6722 po_misc_or_fail_no_backtrack (
6723 parse_address_group_reloc (&str, i, GROUP_LDC));
6727 po_misc_or_fail (parse_shifter_operand (&str, i));
6731 po_misc_or_fail_no_backtrack (
6732 parse_shifter_operand_group_reloc (&str, i));
6736 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6740 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6744 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6748 as_fatal (_("unhandled operand code %d"), op_parse_code);
6751 /* Various value-based sanity checks and shared operations. We
6752 do not signal immediate failures for the register constraints;
6753 this allows a syntax error to take precedence. */
6754 switch (op_parse_code)
6762 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6763 inst.error = BAD_PC;
6768 if (inst.operands[i].isreg)
6770 if (inst.operands[i].reg == REG_PC)
6771 inst.error = BAD_PC;
6772 else if (inst.operands[i].reg == REG_SP)
6773 inst.error = BAD_SP;
6778 if (inst.operands[i].isreg
6779 && inst.operands[i].reg == REG_PC
6780 && (inst.operands[i].writeback || thumb))
6781 inst.error = BAD_PC;
6790 case OP_oBARRIER_I15:
6799 inst.operands[i].imm = val;
6806 /* If we get here, this operand was successfully parsed. */
6807 inst.operands[i].present = 1;
6811 inst.error = BAD_ARGS;
6816 /* The parse routine should already have set inst.error, but set a
6817 default here just in case. */
6819 inst.error = _("syntax error");
6823 /* Do not backtrack over a trailing optional argument that
6824 absorbed some text. We will only fail again, with the
6825 'garbage following instruction' error message, which is
6826 probably less helpful than the current one. */
6827 if (backtrack_index == i && backtrack_pos != str
6828 && upat[i+1] == OP_stop)
6831 inst.error = _("syntax error");
6835 /* Try again, skipping the optional argument at backtrack_pos. */
6836 str = backtrack_pos;
6837 inst.error = backtrack_error;
6838 inst.operands[backtrack_index].present = 0;
6839 i = backtrack_index;
6843 /* Check that we have parsed all the arguments. */
6844 if (*str != '\0' && !inst.error)
6845 inst.error = _("garbage following instruction");
6847 return inst.error ? FAIL : SUCCESS;
6850 #undef po_char_or_fail
6851 #undef po_reg_or_fail
6852 #undef po_reg_or_goto
6853 #undef po_imm_or_fail
6854 #undef po_scalar_or_fail
6855 #undef po_barrier_or_imm
6857 /* Shorthand macro for instruction encoding functions issuing errors. */
6858 #define constraint(expr, err) \
6869 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6870 instructions are unpredictable if these registers are used. This
6871 is the BadReg predicate in ARM's Thumb-2 documentation. */
6872 #define reject_bad_reg(reg) \
6874 if (reg == REG_SP || reg == REG_PC) \
6876 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6881 /* If REG is R13 (the stack pointer), warn that its use is
6883 #define warn_deprecated_sp(reg) \
6885 if (warn_on_deprecated && reg == REG_SP) \
6886 as_warn (_("use of r13 is deprecated")); \
6889 /* Functions for operand encoding. ARM, then Thumb. */
6891 #define rotate_left(v, n) (v << n | v >> (32 - n))
6893 /* If VAL can be encoded in the immediate field of an ARM instruction,
6894 return the encoded form. Otherwise, return FAIL. */
6897 encode_arm_immediate (unsigned int val)
6901 for (i = 0; i < 32; i += 2)
6902 if ((a = rotate_left (val, i)) <= 0xff)
6903 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6908 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6909 return the encoded form. Otherwise, return FAIL. */
6911 encode_thumb32_immediate (unsigned int val)
6918 for (i = 1; i <= 24; i++)
6921 if ((val & ~(0xff << i)) == 0)
6922 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6926 if (val == ((a << 16) | a))
6928 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6932 if (val == ((a << 16) | a))
6933 return 0x200 | (a >> 8);
6937 /* Encode a VFP SP or DP register number into inst.instruction. */
6940 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6942 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6945 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6948 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6951 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6956 first_error (_("D register out of range for selected VFP version"));
6964 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6968 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6972 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6976 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6980 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6984 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6992 /* Encode a <shift> in an ARM-format instruction. The immediate,
6993 if any, is handled by md_apply_fix. */
6995 encode_arm_shift (int i)
6997 if (inst.operands[i].shift_kind == SHIFT_RRX)
6998 inst.instruction |= SHIFT_ROR << 5;
7001 inst.instruction |= inst.operands[i].shift_kind << 5;
7002 if (inst.operands[i].immisreg)
7004 inst.instruction |= SHIFT_BY_REG;
7005 inst.instruction |= inst.operands[i].imm << 8;
7008 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7013 encode_arm_shifter_operand (int i)
7015 if (inst.operands[i].isreg)
7017 inst.instruction |= inst.operands[i].reg;
7018 encode_arm_shift (i);
7021 inst.instruction |= INST_IMMEDIATE;
7024 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7026 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7028 gas_assert (inst.operands[i].isreg);
7029 inst.instruction |= inst.operands[i].reg << 16;
7031 if (inst.operands[i].preind)
7035 inst.error = _("instruction does not accept preindexed addressing");
7038 inst.instruction |= PRE_INDEX;
7039 if (inst.operands[i].writeback)
7040 inst.instruction |= WRITE_BACK;
7043 else if (inst.operands[i].postind)
7045 gas_assert (inst.operands[i].writeback);
7047 inst.instruction |= WRITE_BACK;
7049 else /* unindexed - only for coprocessor */
7051 inst.error = _("instruction does not accept unindexed addressing");
7055 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7056 && (((inst.instruction & 0x000f0000) >> 16)
7057 == ((inst.instruction & 0x0000f000) >> 12)))
7058 as_warn ((inst.instruction & LOAD_BIT)
7059 ? _("destination register same as write-back base")
7060 : _("source register same as write-back base"));
7063 /* inst.operands[i] was set up by parse_address. Encode it into an
7064 ARM-format mode 2 load or store instruction. If is_t is true,
7065 reject forms that cannot be used with a T instruction (i.e. not
7068 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7070 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7072 encode_arm_addr_mode_common (i, is_t);
7074 if (inst.operands[i].immisreg)
7076 constraint ((inst.operands[i].imm == REG_PC
7077 || (is_pc && inst.operands[i].writeback)),
7079 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7080 inst.instruction |= inst.operands[i].imm;
7081 if (!inst.operands[i].negative)
7082 inst.instruction |= INDEX_UP;
7083 if (inst.operands[i].shifted)
7085 if (inst.operands[i].shift_kind == SHIFT_RRX)
7086 inst.instruction |= SHIFT_ROR << 5;
7089 inst.instruction |= inst.operands[i].shift_kind << 5;
7090 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7094 else /* immediate offset in inst.reloc */
7096 if (is_pc && !inst.reloc.pc_rel)
7098 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7100 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7101 cannot use PC in addressing.
7102 PC cannot be used in writeback addressing, either. */
7103 constraint ((is_t || inst.operands[i].writeback),
7106 /* Use of PC in str is deprecated for ARMv7. */
7107 if (warn_on_deprecated
7109 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7110 as_warn (_("use of PC in this instruction is deprecated"));
7113 if (inst.reloc.type == BFD_RELOC_UNUSED)
7115 /* Prefer + for zero encoded value. */
7116 if (!inst.operands[i].negative)
7117 inst.instruction |= INDEX_UP;
7118 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7123 /* inst.operands[i] was set up by parse_address. Encode it into an
7124 ARM-format mode 3 load or store instruction. Reject forms that
7125 cannot be used with such instructions. If is_t is true, reject
7126 forms that cannot be used with a T instruction (i.e. not
7129 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7131 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7133 inst.error = _("instruction does not accept scaled register index");
7137 encode_arm_addr_mode_common (i, is_t);
7139 if (inst.operands[i].immisreg)
7141 constraint ((inst.operands[i].imm == REG_PC
7142 || inst.operands[i].reg == REG_PC),
7144 inst.instruction |= inst.operands[i].imm;
7145 if (!inst.operands[i].negative)
7146 inst.instruction |= INDEX_UP;
7148 else /* immediate offset in inst.reloc */
7150 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7151 && inst.operands[i].writeback),
7153 inst.instruction |= HWOFFSET_IMM;
7154 if (inst.reloc.type == BFD_RELOC_UNUSED)
7156 /* Prefer + for zero encoded value. */
7157 if (!inst.operands[i].negative)
7158 inst.instruction |= INDEX_UP;
7160 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7165 /* inst.operands[i] was set up by parse_address. Encode it into an
7166 ARM-format instruction. Reject all forms which cannot be encoded
7167 into a coprocessor load/store instruction. If wb_ok is false,
7168 reject use of writeback; if unind_ok is false, reject use of
7169 unindexed addressing. If reloc_override is not 0, use it instead
7170 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7171 (in which case it is preserved). */
7174 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7176 inst.instruction |= inst.operands[i].reg << 16;
7178 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7180 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7182 gas_assert (!inst.operands[i].writeback);
7185 inst.error = _("instruction does not support unindexed addressing");
7188 inst.instruction |= inst.operands[i].imm;
7189 inst.instruction |= INDEX_UP;
7193 if (inst.operands[i].preind)
7194 inst.instruction |= PRE_INDEX;
7196 if (inst.operands[i].writeback)
7198 if (inst.operands[i].reg == REG_PC)
7200 inst.error = _("pc may not be used with write-back");
7205 inst.error = _("instruction does not support writeback");
7208 inst.instruction |= WRITE_BACK;
7212 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7213 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7214 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7215 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7218 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7220 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7223 /* Prefer + for zero encoded value. */
7224 if (!inst.operands[i].negative)
7225 inst.instruction |= INDEX_UP;
7230 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7231 Determine whether it can be performed with a move instruction; if
7232 it can, convert inst.instruction to that move instruction and
7233 return TRUE; if it can't, convert inst.instruction to a literal-pool
7234 load and return FALSE. If this is not a valid thing to do in the
7235 current context, set inst.error and return TRUE.
7237 inst.operands[i] describes the destination register. */
7240 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7245 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7249 if ((inst.instruction & tbit) == 0)
7251 inst.error = _("invalid pseudo operation");
7254 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7256 inst.error = _("constant expression expected");
7259 if (inst.reloc.exp.X_op == O_constant)
7263 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7265 /* This can be done with a mov(1) instruction. */
7266 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7267 inst.instruction |= inst.reloc.exp.X_add_number;
7273 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7276 /* This can be done with a mov instruction. */
7277 inst.instruction &= LITERAL_MASK;
7278 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7279 inst.instruction |= value & 0xfff;
7283 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7286 /* This can be done with a mvn instruction. */
7287 inst.instruction &= LITERAL_MASK;
7288 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7289 inst.instruction |= value & 0xfff;
7295 if (add_to_lit_pool () == FAIL)
7297 inst.error = _("literal pool insertion failed");
7300 inst.operands[1].reg = REG_PC;
7301 inst.operands[1].isreg = 1;
7302 inst.operands[1].preind = 1;
7303 inst.reloc.pc_rel = 1;
7304 inst.reloc.type = (thumb_p
7305 ? BFD_RELOC_ARM_THUMB_OFFSET
7307 ? BFD_RELOC_ARM_HWLITERAL
7308 : BFD_RELOC_ARM_LITERAL));
7312 /* Functions for instruction encoding, sorted by sub-architecture.
7313 First some generics; their names are taken from the conventional
7314 bit positions for register arguments in ARM format instructions. */
7324 inst.instruction |= inst.operands[0].reg << 12;
7330 inst.instruction |= inst.operands[0].reg << 12;
7331 inst.instruction |= inst.operands[1].reg;
7337 inst.instruction |= inst.operands[0].reg << 12;
7338 inst.instruction |= inst.operands[1].reg << 16;
7344 inst.instruction |= inst.operands[0].reg << 16;
7345 inst.instruction |= inst.operands[1].reg << 12;
7351 unsigned Rn = inst.operands[2].reg;
7352 /* Enforce restrictions on SWP instruction. */
7353 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7355 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7356 _("Rn must not overlap other operands"));
7358 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7359 if (warn_on_deprecated
7360 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7361 as_warn (_("swp{b} use is deprecated for this architecture"));
7364 inst.instruction |= inst.operands[0].reg << 12;
7365 inst.instruction |= inst.operands[1].reg;
7366 inst.instruction |= Rn << 16;
7372 inst.instruction |= inst.operands[0].reg << 12;
7373 inst.instruction |= inst.operands[1].reg << 16;
7374 inst.instruction |= inst.operands[2].reg;
7380 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7381 constraint (((inst.reloc.exp.X_op != O_constant
7382 && inst.reloc.exp.X_op != O_illegal)
7383 || inst.reloc.exp.X_add_number != 0),
7385 inst.instruction |= inst.operands[0].reg;
7386 inst.instruction |= inst.operands[1].reg << 12;
7387 inst.instruction |= inst.operands[2].reg << 16;
7393 inst.instruction |= inst.operands[0].imm;
7399 inst.instruction |= inst.operands[0].reg << 12;
7400 encode_arm_cp_address (1, TRUE, TRUE, 0);
7403 /* ARM instructions, in alphabetical order by function name (except
7404 that wrapper functions appear immediately after the function they
7407 /* This is a pseudo-op of the form "adr rd, label" to be converted
7408 into a relative address of the form "add rd, pc, #label-.-8". */
7413 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7415 /* Frag hacking will turn this into a sub instruction if the offset turns
7416 out to be negative. */
7417 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7418 inst.reloc.pc_rel = 1;
7419 inst.reloc.exp.X_add_number -= 8;
7422 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7423 into a relative address of the form:
7424 add rd, pc, #low(label-.-8)"
7425 add rd, rd, #high(label-.-8)" */
7430 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7432 /* Frag hacking will turn this into a sub instruction if the offset turns
7433 out to be negative. */
7434 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7435 inst.reloc.pc_rel = 1;
7436 inst.size = INSN_SIZE * 2;
7437 inst.reloc.exp.X_add_number -= 8;
7443 if (!inst.operands[1].present)
7444 inst.operands[1].reg = inst.operands[0].reg;
7445 inst.instruction |= inst.operands[0].reg << 12;
7446 inst.instruction |= inst.operands[1].reg << 16;
7447 encode_arm_shifter_operand (2);
7453 if (inst.operands[0].present)
7455 constraint ((inst.instruction & 0xf0) != 0x40
7456 && inst.operands[0].imm > 0xf
7457 && inst.operands[0].imm < 0x0,
7458 _("bad barrier type"));
7459 inst.instruction |= inst.operands[0].imm;
7462 inst.instruction |= 0xf;
7468 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7469 constraint (msb > 32, _("bit-field extends past end of register"));
7470 /* The instruction encoding stores the LSB and MSB,
7471 not the LSB and width. */
7472 inst.instruction |= inst.operands[0].reg << 12;
7473 inst.instruction |= inst.operands[1].imm << 7;
7474 inst.instruction |= (msb - 1) << 16;
7482 /* #0 in second position is alternative syntax for bfc, which is
7483 the same instruction but with REG_PC in the Rm field. */
7484 if (!inst.operands[1].isreg)
7485 inst.operands[1].reg = REG_PC;
7487 msb = inst.operands[2].imm + inst.operands[3].imm;
7488 constraint (msb > 32, _("bit-field extends past end of register"));
7489 /* The instruction encoding stores the LSB and MSB,
7490 not the LSB and width. */
7491 inst.instruction |= inst.operands[0].reg << 12;
7492 inst.instruction |= inst.operands[1].reg;
7493 inst.instruction |= inst.operands[2].imm << 7;
7494 inst.instruction |= (msb - 1) << 16;
7500 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7501 _("bit-field extends past end of register"));
7502 inst.instruction |= inst.operands[0].reg << 12;
7503 inst.instruction |= inst.operands[1].reg;
7504 inst.instruction |= inst.operands[2].imm << 7;
7505 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7508 /* ARM V5 breakpoint instruction (argument parse)
7509 BKPT <16 bit unsigned immediate>
7510 Instruction is not conditional.
7511 The bit pattern given in insns[] has the COND_ALWAYS condition,
7512 and it is an error if the caller tried to override that. */
7517 /* Top 12 of 16 bits to bits 19:8. */
7518 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7520 /* Bottom 4 of 16 bits to bits 3:0. */
7521 inst.instruction |= inst.operands[0].imm & 0xf;
7525 encode_branch (int default_reloc)
7527 if (inst.operands[0].hasreloc)
7529 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7530 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7531 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7532 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7533 ? BFD_RELOC_ARM_PLT32
7534 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7537 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7538 inst.reloc.pc_rel = 1;
7545 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7546 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7549 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7556 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7558 if (inst.cond == COND_ALWAYS)
7559 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7561 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7565 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7568 /* ARM V5 branch-link-exchange instruction (argument parse)
7569 BLX <target_addr> ie BLX(1)
7570 BLX{<condition>} <Rm> ie BLX(2)
7571 Unfortunately, there are two different opcodes for this mnemonic.
7572 So, the insns[].value is not used, and the code here zaps values
7573 into inst.instruction.
7574 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7579 if (inst.operands[0].isreg)
7581 /* Arg is a register; the opcode provided by insns[] is correct.
7582 It is not illegal to do "blx pc", just useless. */
7583 if (inst.operands[0].reg == REG_PC)
7584 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7586 inst.instruction |= inst.operands[0].reg;
7590 /* Arg is an address; this instruction cannot be executed
7591 conditionally, and the opcode must be adjusted.
7592 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7593 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7594 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7595 inst.instruction = 0xfa000000;
7596 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7603 bfd_boolean want_reloc;
7605 if (inst.operands[0].reg == REG_PC)
7606 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7608 inst.instruction |= inst.operands[0].reg;
7609 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7610 it is for ARMv4t or earlier. */
7611 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7612 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7616 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7621 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7625 /* ARM v5TEJ. Jump to Jazelle code. */
7630 if (inst.operands[0].reg == REG_PC)
7631 as_tsktsk (_("use of r15 in bxj is not really useful"));
7633 inst.instruction |= inst.operands[0].reg;
7636 /* Co-processor data operation:
7637 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7638 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7642 inst.instruction |= inst.operands[0].reg << 8;
7643 inst.instruction |= inst.operands[1].imm << 20;
7644 inst.instruction |= inst.operands[2].reg << 12;
7645 inst.instruction |= inst.operands[3].reg << 16;
7646 inst.instruction |= inst.operands[4].reg;
7647 inst.instruction |= inst.operands[5].imm << 5;
7653 inst.instruction |= inst.operands[0].reg << 16;
7654 encode_arm_shifter_operand (1);
7657 /* Transfer between coprocessor and ARM registers.
7658 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7663 No special properties. */
7670 Rd = inst.operands[2].reg;
7673 if (inst.instruction == 0xee000010
7674 || inst.instruction == 0xfe000010)
7676 reject_bad_reg (Rd);
7679 constraint (Rd == REG_SP, BAD_SP);
7684 if (inst.instruction == 0xe000010)
7685 constraint (Rd == REG_PC, BAD_PC);
7689 inst.instruction |= inst.operands[0].reg << 8;
7690 inst.instruction |= inst.operands[1].imm << 21;
7691 inst.instruction |= Rd << 12;
7692 inst.instruction |= inst.operands[3].reg << 16;
7693 inst.instruction |= inst.operands[4].reg;
7694 inst.instruction |= inst.operands[5].imm << 5;
7697 /* Transfer between coprocessor register and pair of ARM registers.
7698 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7703 Two XScale instructions are special cases of these:
7705 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7706 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7708 Result unpredictable if Rd or Rn is R15. */
7715 Rd = inst.operands[2].reg;
7716 Rn = inst.operands[3].reg;
7720 reject_bad_reg (Rd);
7721 reject_bad_reg (Rn);
7725 constraint (Rd == REG_PC, BAD_PC);
7726 constraint (Rn == REG_PC, BAD_PC);
7729 inst.instruction |= inst.operands[0].reg << 8;
7730 inst.instruction |= inst.operands[1].imm << 4;
7731 inst.instruction |= Rd << 12;
7732 inst.instruction |= Rn << 16;
7733 inst.instruction |= inst.operands[4].reg;
7739 inst.instruction |= inst.operands[0].imm << 6;
7740 if (inst.operands[1].present)
7742 inst.instruction |= CPSI_MMOD;
7743 inst.instruction |= inst.operands[1].imm;
7750 inst.instruction |= inst.operands[0].imm;
7756 unsigned Rd, Rn, Rm;
7758 Rd = inst.operands[0].reg;
7759 Rn = (inst.operands[1].present
7760 ? inst.operands[1].reg : Rd);
7761 Rm = inst.operands[2].reg;
7763 constraint ((Rd == REG_PC), BAD_PC);
7764 constraint ((Rn == REG_PC), BAD_PC);
7765 constraint ((Rm == REG_PC), BAD_PC);
7767 inst.instruction |= Rd << 16;
7768 inst.instruction |= Rn << 0;
7769 inst.instruction |= Rm << 8;
7775 /* There is no IT instruction in ARM mode. We
7776 process it to do the validation as if in
7777 thumb mode, just in case the code gets
7778 assembled for thumb using the unified syntax. */
7783 set_it_insn_type (IT_INSN);
7784 now_it.mask = (inst.instruction & 0xf) | 0x10;
7785 now_it.cc = inst.operands[0].imm;
7792 int base_reg = inst.operands[0].reg;
7793 int range = inst.operands[1].imm;
7795 inst.instruction |= base_reg << 16;
7796 inst.instruction |= range;
7798 if (inst.operands[1].writeback)
7799 inst.instruction |= LDM_TYPE_2_OR_3;
7801 if (inst.operands[0].writeback)
7803 inst.instruction |= WRITE_BACK;
7804 /* Check for unpredictable uses of writeback. */
7805 if (inst.instruction & LOAD_BIT)
7807 /* Not allowed in LDM type 2. */
7808 if ((inst.instruction & LDM_TYPE_2_OR_3)
7809 && ((range & (1 << REG_PC)) == 0))
7810 as_warn (_("writeback of base register is UNPREDICTABLE"));
7811 /* Only allowed if base reg not in list for other types. */
7812 else if (range & (1 << base_reg))
7813 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7817 /* Not allowed for type 2. */
7818 if (inst.instruction & LDM_TYPE_2_OR_3)
7819 as_warn (_("writeback of base register is UNPREDICTABLE"));
7820 /* Only allowed if base reg not in list, or first in list. */
7821 else if ((range & (1 << base_reg))
7822 && (range & ((1 << base_reg) - 1)))
7823 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7828 /* ARMv5TE load-consecutive (argument parse)
7837 constraint (inst.operands[0].reg % 2 != 0,
7838 _("first transfer register must be even"));
7839 constraint (inst.operands[1].present
7840 && inst.operands[1].reg != inst.operands[0].reg + 1,
7841 _("can only transfer two consecutive registers"));
7842 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7843 constraint (!inst.operands[2].isreg, _("'[' expected"));
7845 if (!inst.operands[1].present)
7846 inst.operands[1].reg = inst.operands[0].reg + 1;
7848 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7849 register and the first register written; we have to diagnose
7850 overlap between the base and the second register written here. */
7852 if (inst.operands[2].reg == inst.operands[1].reg
7853 && (inst.operands[2].writeback || inst.operands[2].postind))
7854 as_warn (_("base register written back, and overlaps "
7855 "second transfer register"));
7857 if (!(inst.instruction & V4_STR_BIT))
7859 /* For an index-register load, the index register must not overlap the
7860 destination (even if not write-back). */
7861 if (inst.operands[2].immisreg
7862 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7863 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7864 as_warn (_("index register overlaps transfer register"));
7866 inst.instruction |= inst.operands[0].reg << 12;
7867 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7873 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7874 || inst.operands[1].postind || inst.operands[1].writeback
7875 || inst.operands[1].immisreg || inst.operands[1].shifted
7876 || inst.operands[1].negative
7877 /* This can arise if the programmer has written
7879 or if they have mistakenly used a register name as the last
7882 It is very difficult to distinguish between these two cases
7883 because "rX" might actually be a label. ie the register
7884 name has been occluded by a symbol of the same name. So we
7885 just generate a general 'bad addressing mode' type error
7886 message and leave it up to the programmer to discover the
7887 true cause and fix their mistake. */
7888 || (inst.operands[1].reg == REG_PC),
7891 constraint (inst.reloc.exp.X_op != O_constant
7892 || inst.reloc.exp.X_add_number != 0,
7893 _("offset must be zero in ARM encoding"));
7895 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7897 inst.instruction |= inst.operands[0].reg << 12;
7898 inst.instruction |= inst.operands[1].reg << 16;
7899 inst.reloc.type = BFD_RELOC_UNUSED;
7905 constraint (inst.operands[0].reg % 2 != 0,
7906 _("even register required"));
7907 constraint (inst.operands[1].present
7908 && inst.operands[1].reg != inst.operands[0].reg + 1,
7909 _("can only load two consecutive registers"));
7910 /* If op 1 were present and equal to PC, this function wouldn't
7911 have been called in the first place. */
7912 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7914 inst.instruction |= inst.operands[0].reg << 12;
7915 inst.instruction |= inst.operands[2].reg << 16;
7918 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
7919 which is not a multiple of four is UNPREDICTABLE. */
7921 check_ldr_r15_aligned (void)
7923 constraint (!(inst.operands[1].immisreg)
7924 && (inst.operands[0].reg == REG_PC
7925 && inst.operands[1].reg == REG_PC
7926 && (inst.reloc.exp.X_add_number & 0x3)),
7927 _("ldr to register 15 must be 4-byte alligned"));
7933 inst.instruction |= inst.operands[0].reg << 12;
7934 if (!inst.operands[1].isreg)
7935 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
7937 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
7938 check_ldr_r15_aligned ();
7944 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7946 if (inst.operands[1].preind)
7948 constraint (inst.reloc.exp.X_op != O_constant
7949 || inst.reloc.exp.X_add_number != 0,
7950 _("this instruction requires a post-indexed address"));
7952 inst.operands[1].preind = 0;
7953 inst.operands[1].postind = 1;
7954 inst.operands[1].writeback = 1;
7956 inst.instruction |= inst.operands[0].reg << 12;
7957 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7960 /* Halfword and signed-byte load/store operations. */
7965 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
7966 inst.instruction |= inst.operands[0].reg << 12;
7967 if (!inst.operands[1].isreg)
7968 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
7970 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
7976 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7978 if (inst.operands[1].preind)
7980 constraint (inst.reloc.exp.X_op != O_constant
7981 || inst.reloc.exp.X_add_number != 0,
7982 _("this instruction requires a post-indexed address"));
7984 inst.operands[1].preind = 0;
7985 inst.operands[1].postind = 1;
7986 inst.operands[1].writeback = 1;
7988 inst.instruction |= inst.operands[0].reg << 12;
7989 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7992 /* Co-processor register load/store.
7993 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7997 inst.instruction |= inst.operands[0].reg << 8;
7998 inst.instruction |= inst.operands[1].reg << 12;
7999 encode_arm_cp_address (2, TRUE, TRUE, 0);
8005 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8006 if (inst.operands[0].reg == inst.operands[1].reg
8007 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8008 && !(inst.instruction & 0x00400000))
8009 as_tsktsk (_("Rd and Rm should be different in mla"));
8011 inst.instruction |= inst.operands[0].reg << 16;
8012 inst.instruction |= inst.operands[1].reg;
8013 inst.instruction |= inst.operands[2].reg << 8;
8014 inst.instruction |= inst.operands[3].reg << 12;
8020 inst.instruction |= inst.operands[0].reg << 12;
8021 encode_arm_shifter_operand (1);
8024 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8031 top = (inst.instruction & 0x00400000) != 0;
8032 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8033 _(":lower16: not allowed this instruction"));
8034 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8035 _(":upper16: not allowed instruction"));
8036 inst.instruction |= inst.operands[0].reg << 12;
8037 if (inst.reloc.type == BFD_RELOC_UNUSED)
8039 imm = inst.reloc.exp.X_add_number;
8040 /* The value is in two pieces: 0:11, 16:19. */
8041 inst.instruction |= (imm & 0x00000fff);
8042 inst.instruction |= (imm & 0x0000f000) << 4;
8046 static void do_vfp_nsyn_opcode (const char *);
8049 do_vfp_nsyn_mrs (void)
8051 if (inst.operands[0].isvec)
8053 if (inst.operands[1].reg != 1)
8054 first_error (_("operand 1 must be FPSCR"));
8055 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8056 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8057 do_vfp_nsyn_opcode ("fmstat");
8059 else if (inst.operands[1].isvec)
8060 do_vfp_nsyn_opcode ("fmrx");
8068 do_vfp_nsyn_msr (void)
8070 if (inst.operands[0].isvec)
8071 do_vfp_nsyn_opcode ("fmxr");
8081 unsigned Rt = inst.operands[0].reg;
8083 if (thumb_mode && inst.operands[0].reg == REG_SP)
8085 inst.error = BAD_SP;
8089 /* APSR_ sets isvec. All other refs to PC are illegal. */
8090 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8092 inst.error = BAD_PC;
8096 if (inst.operands[1].reg != 1)
8097 first_error (_("operand 1 must be FPSCR"));
8099 inst.instruction |= (Rt << 12);
8105 unsigned Rt = inst.operands[1].reg;
8108 reject_bad_reg (Rt);
8109 else if (Rt == REG_PC)
8111 inst.error = BAD_PC;
8115 if (inst.operands[0].reg != 1)
8116 first_error (_("operand 0 must be FPSCR"));
8118 inst.instruction |= (Rt << 12);
8126 if (do_vfp_nsyn_mrs () == SUCCESS)
8129 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8130 inst.instruction |= inst.operands[0].reg << 12;
8132 if (inst.operands[1].isreg)
8134 br = inst.operands[1].reg;
8135 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8136 as_bad (_("bad register for mrs"));
8140 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8141 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8143 _("'APSR', 'CPSR' or 'SPSR' expected"));
8144 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8147 inst.instruction |= br;
8150 /* Two possible forms:
8151 "{C|S}PSR_<field>, Rm",
8152 "{C|S}PSR_f, #expression". */
8157 if (do_vfp_nsyn_msr () == SUCCESS)
8160 inst.instruction |= inst.operands[0].imm;
8161 if (inst.operands[1].isreg)
8162 inst.instruction |= inst.operands[1].reg;
8165 inst.instruction |= INST_IMMEDIATE;
8166 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8167 inst.reloc.pc_rel = 0;
8174 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8176 if (!inst.operands[2].present)
8177 inst.operands[2].reg = inst.operands[0].reg;
8178 inst.instruction |= inst.operands[0].reg << 16;
8179 inst.instruction |= inst.operands[1].reg;
8180 inst.instruction |= inst.operands[2].reg << 8;
8182 if (inst.operands[0].reg == inst.operands[1].reg
8183 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8184 as_tsktsk (_("Rd and Rm should be different in mul"));
8187 /* Long Multiply Parser
8188 UMULL RdLo, RdHi, Rm, Rs
8189 SMULL RdLo, RdHi, Rm, Rs
8190 UMLAL RdLo, RdHi, Rm, Rs
8191 SMLAL RdLo, RdHi, Rm, Rs. */
8196 inst.instruction |= inst.operands[0].reg << 12;
8197 inst.instruction |= inst.operands[1].reg << 16;
8198 inst.instruction |= inst.operands[2].reg;
8199 inst.instruction |= inst.operands[3].reg << 8;
8201 /* rdhi and rdlo must be different. */
8202 if (inst.operands[0].reg == inst.operands[1].reg)
8203 as_tsktsk (_("rdhi and rdlo must be different"));
8205 /* rdhi, rdlo and rm must all be different before armv6. */
8206 if ((inst.operands[0].reg == inst.operands[2].reg
8207 || inst.operands[1].reg == inst.operands[2].reg)
8208 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8209 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8215 if (inst.operands[0].present
8216 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8218 /* Architectural NOP hints are CPSR sets with no bits selected. */
8219 inst.instruction &= 0xf0000000;
8220 inst.instruction |= 0x0320f000;
8221 if (inst.operands[0].present)
8222 inst.instruction |= inst.operands[0].imm;
8226 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8227 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8228 Condition defaults to COND_ALWAYS.
8229 Error if Rd, Rn or Rm are R15. */
8234 inst.instruction |= inst.operands[0].reg << 12;
8235 inst.instruction |= inst.operands[1].reg << 16;
8236 inst.instruction |= inst.operands[2].reg;
8237 if (inst.operands[3].present)
8238 encode_arm_shift (3);
8241 /* ARM V6 PKHTB (Argument Parse). */
8246 if (!inst.operands[3].present)
8248 /* If the shift specifier is omitted, turn the instruction
8249 into pkhbt rd, rm, rn. */
8250 inst.instruction &= 0xfff00010;
8251 inst.instruction |= inst.operands[0].reg << 12;
8252 inst.instruction |= inst.operands[1].reg;
8253 inst.instruction |= inst.operands[2].reg << 16;
8257 inst.instruction |= inst.operands[0].reg << 12;
8258 inst.instruction |= inst.operands[1].reg << 16;
8259 inst.instruction |= inst.operands[2].reg;
8260 encode_arm_shift (3);
8264 /* ARMv5TE: Preload-Cache
8265 MP Extensions: Preload for write
8269 Syntactically, like LDR with B=1, W=0, L=1. */
8274 constraint (!inst.operands[0].isreg,
8275 _("'[' expected after PLD mnemonic"));
8276 constraint (inst.operands[0].postind,
8277 _("post-indexed expression used in preload instruction"));
8278 constraint (inst.operands[0].writeback,
8279 _("writeback used in preload instruction"));
8280 constraint (!inst.operands[0].preind,
8281 _("unindexed addressing used in preload instruction"));
8282 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8285 /* ARMv7: PLI <addr_mode> */
8289 constraint (!inst.operands[0].isreg,
8290 _("'[' expected after PLI mnemonic"));
8291 constraint (inst.operands[0].postind,
8292 _("post-indexed expression used in preload instruction"));
8293 constraint (inst.operands[0].writeback,
8294 _("writeback used in preload instruction"));
8295 constraint (!inst.operands[0].preind,
8296 _("unindexed addressing used in preload instruction"));
8297 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8298 inst.instruction &= ~PRE_INDEX;
8304 inst.operands[1] = inst.operands[0];
8305 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8306 inst.operands[0].isreg = 1;
8307 inst.operands[0].writeback = 1;
8308 inst.operands[0].reg = REG_SP;
8312 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8313 word at the specified address and the following word
8315 Unconditionally executed.
8316 Error if Rn is R15. */
8321 inst.instruction |= inst.operands[0].reg << 16;
8322 if (inst.operands[0].writeback)
8323 inst.instruction |= WRITE_BACK;
8326 /* ARM V6 ssat (argument parse). */
8331 inst.instruction |= inst.operands[0].reg << 12;
8332 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8333 inst.instruction |= inst.operands[2].reg;
8335 if (inst.operands[3].present)
8336 encode_arm_shift (3);
8339 /* ARM V6 usat (argument parse). */
8344 inst.instruction |= inst.operands[0].reg << 12;
8345 inst.instruction |= inst.operands[1].imm << 16;
8346 inst.instruction |= inst.operands[2].reg;
8348 if (inst.operands[3].present)
8349 encode_arm_shift (3);
8352 /* ARM V6 ssat16 (argument parse). */
8357 inst.instruction |= inst.operands[0].reg << 12;
8358 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8359 inst.instruction |= inst.operands[2].reg;
8365 inst.instruction |= inst.operands[0].reg << 12;
8366 inst.instruction |= inst.operands[1].imm << 16;
8367 inst.instruction |= inst.operands[2].reg;
8370 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8371 preserving the other bits.
8373 setend <endian_specifier>, where <endian_specifier> is either
8379 if (inst.operands[0].imm)
8380 inst.instruction |= 0x200;
8386 unsigned int Rm = (inst.operands[1].present
8387 ? inst.operands[1].reg
8388 : inst.operands[0].reg);
8390 inst.instruction |= inst.operands[0].reg << 12;
8391 inst.instruction |= Rm;
8392 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8394 inst.instruction |= inst.operands[2].reg << 8;
8395 inst.instruction |= SHIFT_BY_REG;
8396 /* PR 12854: Error on extraneous shifts. */
8397 constraint (inst.operands[2].shifted,
8398 _("extraneous shift as part of operand to shift insn"));
8401 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8407 inst.reloc.type = BFD_RELOC_ARM_SMC;
8408 inst.reloc.pc_rel = 0;
8414 inst.reloc.type = BFD_RELOC_ARM_HVC;
8415 inst.reloc.pc_rel = 0;
8421 inst.reloc.type = BFD_RELOC_ARM_SWI;
8422 inst.reloc.pc_rel = 0;
8425 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8426 SMLAxy{cond} Rd,Rm,Rs,Rn
8427 SMLAWy{cond} Rd,Rm,Rs,Rn
8428 Error if any register is R15. */
8433 inst.instruction |= inst.operands[0].reg << 16;
8434 inst.instruction |= inst.operands[1].reg;
8435 inst.instruction |= inst.operands[2].reg << 8;
8436 inst.instruction |= inst.operands[3].reg << 12;
8439 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8440 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8441 Error if any register is R15.
8442 Warning if Rdlo == Rdhi. */
8447 inst.instruction |= inst.operands[0].reg << 12;
8448 inst.instruction |= inst.operands[1].reg << 16;
8449 inst.instruction |= inst.operands[2].reg;
8450 inst.instruction |= inst.operands[3].reg << 8;
8452 if (inst.operands[0].reg == inst.operands[1].reg)
8453 as_tsktsk (_("rdhi and rdlo must be different"));
8456 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8457 SMULxy{cond} Rd,Rm,Rs
8458 Error if any register is R15. */
8463 inst.instruction |= inst.operands[0].reg << 16;
8464 inst.instruction |= inst.operands[1].reg;
8465 inst.instruction |= inst.operands[2].reg << 8;
8468 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8469 the same for both ARM and Thumb-2. */
8476 if (inst.operands[0].present)
8478 reg = inst.operands[0].reg;
8479 constraint (reg != REG_SP, _("SRS base register must be r13"));
8484 inst.instruction |= reg << 16;
8485 inst.instruction |= inst.operands[1].imm;
8486 if (inst.operands[0].writeback || inst.operands[1].writeback)
8487 inst.instruction |= WRITE_BACK;
8490 /* ARM V6 strex (argument parse). */
8495 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8496 || inst.operands[2].postind || inst.operands[2].writeback
8497 || inst.operands[2].immisreg || inst.operands[2].shifted
8498 || inst.operands[2].negative
8499 /* See comment in do_ldrex(). */
8500 || (inst.operands[2].reg == REG_PC),
8503 constraint (inst.operands[0].reg == inst.operands[1].reg
8504 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8506 constraint (inst.reloc.exp.X_op != O_constant
8507 || inst.reloc.exp.X_add_number != 0,
8508 _("offset must be zero in ARM encoding"));
8510 inst.instruction |= inst.operands[0].reg << 12;
8511 inst.instruction |= inst.operands[1].reg;
8512 inst.instruction |= inst.operands[2].reg << 16;
8513 inst.reloc.type = BFD_RELOC_UNUSED;
8519 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8520 || inst.operands[2].postind || inst.operands[2].writeback
8521 || inst.operands[2].immisreg || inst.operands[2].shifted
8522 || inst.operands[2].negative,
8525 constraint (inst.operands[0].reg == inst.operands[1].reg
8526 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8534 constraint (inst.operands[1].reg % 2 != 0,
8535 _("even register required"));
8536 constraint (inst.operands[2].present
8537 && inst.operands[2].reg != inst.operands[1].reg + 1,
8538 _("can only store two consecutive registers"));
8539 /* If op 2 were present and equal to PC, this function wouldn't
8540 have been called in the first place. */
8541 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8543 constraint (inst.operands[0].reg == inst.operands[1].reg
8544 || inst.operands[0].reg == inst.operands[1].reg + 1
8545 || inst.operands[0].reg == inst.operands[3].reg,
8548 inst.instruction |= inst.operands[0].reg << 12;
8549 inst.instruction |= inst.operands[1].reg;
8550 inst.instruction |= inst.operands[3].reg << 16;
8553 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8554 extends it to 32-bits, and adds the result to a value in another
8555 register. You can specify a rotation by 0, 8, 16, or 24 bits
8556 before extracting the 16-bit value.
8557 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8558 Condition defaults to COND_ALWAYS.
8559 Error if any register uses R15. */
8564 inst.instruction |= inst.operands[0].reg << 12;
8565 inst.instruction |= inst.operands[1].reg << 16;
8566 inst.instruction |= inst.operands[2].reg;
8567 inst.instruction |= inst.operands[3].imm << 10;
8572 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8573 Condition defaults to COND_ALWAYS.
8574 Error if any register uses R15. */
8579 inst.instruction |= inst.operands[0].reg << 12;
8580 inst.instruction |= inst.operands[1].reg;
8581 inst.instruction |= inst.operands[2].imm << 10;
8584 /* VFP instructions. In a logical order: SP variant first, monad
8585 before dyad, arithmetic then move then load/store. */
8588 do_vfp_sp_monadic (void)
8590 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8591 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8595 do_vfp_sp_dyadic (void)
8597 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8598 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8599 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8603 do_vfp_sp_compare_z (void)
8605 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8609 do_vfp_dp_sp_cvt (void)
8611 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8612 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8616 do_vfp_sp_dp_cvt (void)
8618 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8619 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8623 do_vfp_reg_from_sp (void)
8625 inst.instruction |= inst.operands[0].reg << 12;
8626 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8630 do_vfp_reg2_from_sp2 (void)
8632 constraint (inst.operands[2].imm != 2,
8633 _("only two consecutive VFP SP registers allowed here"));
8634 inst.instruction |= inst.operands[0].reg << 12;
8635 inst.instruction |= inst.operands[1].reg << 16;
8636 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8640 do_vfp_sp_from_reg (void)
8642 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8643 inst.instruction |= inst.operands[1].reg << 12;
8647 do_vfp_sp2_from_reg2 (void)
8649 constraint (inst.operands[0].imm != 2,
8650 _("only two consecutive VFP SP registers allowed here"));
8651 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8652 inst.instruction |= inst.operands[1].reg << 12;
8653 inst.instruction |= inst.operands[2].reg << 16;
8657 do_vfp_sp_ldst (void)
8659 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8660 encode_arm_cp_address (1, FALSE, TRUE, 0);
8664 do_vfp_dp_ldst (void)
8666 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8667 encode_arm_cp_address (1, FALSE, TRUE, 0);
8672 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8674 if (inst.operands[0].writeback)
8675 inst.instruction |= WRITE_BACK;
8677 constraint (ldstm_type != VFP_LDSTMIA,
8678 _("this addressing mode requires base-register writeback"));
8679 inst.instruction |= inst.operands[0].reg << 16;
8680 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8681 inst.instruction |= inst.operands[1].imm;
8685 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8689 if (inst.operands[0].writeback)
8690 inst.instruction |= WRITE_BACK;
8692 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8693 _("this addressing mode requires base-register writeback"));
8695 inst.instruction |= inst.operands[0].reg << 16;
8696 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8698 count = inst.operands[1].imm << 1;
8699 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8702 inst.instruction |= count;
8706 do_vfp_sp_ldstmia (void)
8708 vfp_sp_ldstm (VFP_LDSTMIA);
8712 do_vfp_sp_ldstmdb (void)
8714 vfp_sp_ldstm (VFP_LDSTMDB);
8718 do_vfp_dp_ldstmia (void)
8720 vfp_dp_ldstm (VFP_LDSTMIA);
8724 do_vfp_dp_ldstmdb (void)
8726 vfp_dp_ldstm (VFP_LDSTMDB);
8730 do_vfp_xp_ldstmia (void)
8732 vfp_dp_ldstm (VFP_LDSTMIAX);
8736 do_vfp_xp_ldstmdb (void)
8738 vfp_dp_ldstm (VFP_LDSTMDBX);
8742 do_vfp_dp_rd_rm (void)
8744 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8745 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8749 do_vfp_dp_rn_rd (void)
8751 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8752 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8756 do_vfp_dp_rd_rn (void)
8758 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8759 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8763 do_vfp_dp_rd_rn_rm (void)
8765 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8766 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8767 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8773 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8777 do_vfp_dp_rm_rd_rn (void)
8779 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8780 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8781 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8784 /* VFPv3 instructions. */
8786 do_vfp_sp_const (void)
8788 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8789 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8790 inst.instruction |= (inst.operands[1].imm & 0x0f);
8794 do_vfp_dp_const (void)
8796 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8797 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8798 inst.instruction |= (inst.operands[1].imm & 0x0f);
8802 vfp_conv (int srcsize)
8804 int immbits = srcsize - inst.operands[1].imm;
8806 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8808 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8809 i.e. immbits must be in range 0 - 16. */
8810 inst.error = _("immediate value out of range, expected range [0, 16]");
8813 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
8815 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8816 i.e. immbits must be in range 0 - 31. */
8817 inst.error = _("immediate value out of range, expected range [1, 32]");
8821 inst.instruction |= (immbits & 1) << 5;
8822 inst.instruction |= (immbits >> 1);
8826 do_vfp_sp_conv_16 (void)
8828 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8833 do_vfp_dp_conv_16 (void)
8835 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8840 do_vfp_sp_conv_32 (void)
8842 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8847 do_vfp_dp_conv_32 (void)
8849 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8853 /* FPA instructions. Also in a logical order. */
8858 inst.instruction |= inst.operands[0].reg << 16;
8859 inst.instruction |= inst.operands[1].reg;
8863 do_fpa_ldmstm (void)
8865 inst.instruction |= inst.operands[0].reg << 12;
8866 switch (inst.operands[1].imm)
8868 case 1: inst.instruction |= CP_T_X; break;
8869 case 2: inst.instruction |= CP_T_Y; break;
8870 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8875 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8877 /* The instruction specified "ea" or "fd", so we can only accept
8878 [Rn]{!}. The instruction does not really support stacking or
8879 unstacking, so we have to emulate these by setting appropriate
8880 bits and offsets. */
8881 constraint (inst.reloc.exp.X_op != O_constant
8882 || inst.reloc.exp.X_add_number != 0,
8883 _("this instruction does not support indexing"));
8885 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8886 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8888 if (!(inst.instruction & INDEX_UP))
8889 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8891 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8893 inst.operands[2].preind = 0;
8894 inst.operands[2].postind = 1;
8898 encode_arm_cp_address (2, TRUE, TRUE, 0);
8901 /* iWMMXt instructions: strictly in alphabetical order. */
8904 do_iwmmxt_tandorc (void)
8906 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8910 do_iwmmxt_textrc (void)
8912 inst.instruction |= inst.operands[0].reg << 12;
8913 inst.instruction |= inst.operands[1].imm;
8917 do_iwmmxt_textrm (void)
8919 inst.instruction |= inst.operands[0].reg << 12;
8920 inst.instruction |= inst.operands[1].reg << 16;
8921 inst.instruction |= inst.operands[2].imm;
8925 do_iwmmxt_tinsr (void)
8927 inst.instruction |= inst.operands[0].reg << 16;
8928 inst.instruction |= inst.operands[1].reg << 12;
8929 inst.instruction |= inst.operands[2].imm;
8933 do_iwmmxt_tmia (void)
8935 inst.instruction |= inst.operands[0].reg << 5;
8936 inst.instruction |= inst.operands[1].reg;
8937 inst.instruction |= inst.operands[2].reg << 12;
8941 do_iwmmxt_waligni (void)
8943 inst.instruction |= inst.operands[0].reg << 12;
8944 inst.instruction |= inst.operands[1].reg << 16;
8945 inst.instruction |= inst.operands[2].reg;
8946 inst.instruction |= inst.operands[3].imm << 20;
8950 do_iwmmxt_wmerge (void)
8952 inst.instruction |= inst.operands[0].reg << 12;
8953 inst.instruction |= inst.operands[1].reg << 16;
8954 inst.instruction |= inst.operands[2].reg;
8955 inst.instruction |= inst.operands[3].imm << 21;
8959 do_iwmmxt_wmov (void)
8961 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8962 inst.instruction |= inst.operands[0].reg << 12;
8963 inst.instruction |= inst.operands[1].reg << 16;
8964 inst.instruction |= inst.operands[1].reg;
8968 do_iwmmxt_wldstbh (void)
8971 inst.instruction |= inst.operands[0].reg << 12;
8973 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
8975 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
8976 encode_arm_cp_address (1, TRUE, FALSE, reloc);
8980 do_iwmmxt_wldstw (void)
8982 /* RIWR_RIWC clears .isreg for a control register. */
8983 if (!inst.operands[0].isreg)
8985 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8986 inst.instruction |= 0xf0000000;
8989 inst.instruction |= inst.operands[0].reg << 12;
8990 encode_arm_cp_address (1, TRUE, TRUE, 0);
8994 do_iwmmxt_wldstd (void)
8996 inst.instruction |= inst.operands[0].reg << 12;
8997 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
8998 && inst.operands[1].immisreg)
9000 inst.instruction &= ~0x1a000ff;
9001 inst.instruction |= (0xf << 28);
9002 if (inst.operands[1].preind)
9003 inst.instruction |= PRE_INDEX;
9004 if (!inst.operands[1].negative)
9005 inst.instruction |= INDEX_UP;
9006 if (inst.operands[1].writeback)
9007 inst.instruction |= WRITE_BACK;
9008 inst.instruction |= inst.operands[1].reg << 16;
9009 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9010 inst.instruction |= inst.operands[1].imm;
9013 encode_arm_cp_address (1, TRUE, FALSE, 0);
9017 do_iwmmxt_wshufh (void)
9019 inst.instruction |= inst.operands[0].reg << 12;
9020 inst.instruction |= inst.operands[1].reg << 16;
9021 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9022 inst.instruction |= (inst.operands[2].imm & 0x0f);
9026 do_iwmmxt_wzero (void)
9028 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9029 inst.instruction |= inst.operands[0].reg;
9030 inst.instruction |= inst.operands[0].reg << 12;
9031 inst.instruction |= inst.operands[0].reg << 16;
9035 do_iwmmxt_wrwrwr_or_imm5 (void)
9037 if (inst.operands[2].isreg)
9040 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9041 _("immediate operand requires iWMMXt2"));
9043 if (inst.operands[2].imm == 0)
9045 switch ((inst.instruction >> 20) & 0xf)
9051 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9052 inst.operands[2].imm = 16;
9053 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9059 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9060 inst.operands[2].imm = 32;
9061 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9068 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9070 wrn = (inst.instruction >> 16) & 0xf;
9071 inst.instruction &= 0xff0fff0f;
9072 inst.instruction |= wrn;
9073 /* Bail out here; the instruction is now assembled. */
9078 /* Map 32 -> 0, etc. */
9079 inst.operands[2].imm &= 0x1f;
9080 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9084 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9085 operations first, then control, shift, and load/store. */
9087 /* Insns like "foo X,Y,Z". */
9090 do_mav_triple (void)
9092 inst.instruction |= inst.operands[0].reg << 16;
9093 inst.instruction |= inst.operands[1].reg;
9094 inst.instruction |= inst.operands[2].reg << 12;
9097 /* Insns like "foo W,X,Y,Z".
9098 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9103 inst.instruction |= inst.operands[0].reg << 5;
9104 inst.instruction |= inst.operands[1].reg << 12;
9105 inst.instruction |= inst.operands[2].reg << 16;
9106 inst.instruction |= inst.operands[3].reg;
9109 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9113 inst.instruction |= inst.operands[1].reg << 12;
9116 /* Maverick shift immediate instructions.
9117 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9118 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9123 int imm = inst.operands[2].imm;
9125 inst.instruction |= inst.operands[0].reg << 12;
9126 inst.instruction |= inst.operands[1].reg << 16;
9128 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9129 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9130 Bit 4 should be 0. */
9131 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9133 inst.instruction |= imm;
9136 /* XScale instructions. Also sorted arithmetic before move. */
9138 /* Xscale multiply-accumulate (argument parse)
9141 MIAxycc acc0,Rm,Rs. */
9146 inst.instruction |= inst.operands[1].reg;
9147 inst.instruction |= inst.operands[2].reg << 12;
9150 /* Xscale move-accumulator-register (argument parse)
9152 MARcc acc0,RdLo,RdHi. */
9157 inst.instruction |= inst.operands[1].reg << 12;
9158 inst.instruction |= inst.operands[2].reg << 16;
9161 /* Xscale move-register-accumulator (argument parse)
9163 MRAcc RdLo,RdHi,acc0. */
9168 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9169 inst.instruction |= inst.operands[0].reg << 12;
9170 inst.instruction |= inst.operands[1].reg << 16;
9173 /* Encoding functions relevant only to Thumb. */
9175 /* inst.operands[i] is a shifted-register operand; encode
9176 it into inst.instruction in the format used by Thumb32. */
9179 encode_thumb32_shifted_operand (int i)
9181 unsigned int value = inst.reloc.exp.X_add_number;
9182 unsigned int shift = inst.operands[i].shift_kind;
9184 constraint (inst.operands[i].immisreg,
9185 _("shift by register not allowed in thumb mode"));
9186 inst.instruction |= inst.operands[i].reg;
9187 if (shift == SHIFT_RRX)
9188 inst.instruction |= SHIFT_ROR << 4;
9191 constraint (inst.reloc.exp.X_op != O_constant,
9192 _("expression too complex"));
9194 constraint (value > 32
9195 || (value == 32 && (shift == SHIFT_LSL
9196 || shift == SHIFT_ROR)),
9197 _("shift expression is too large"));
9201 else if (value == 32)
9204 inst.instruction |= shift << 4;
9205 inst.instruction |= (value & 0x1c) << 10;
9206 inst.instruction |= (value & 0x03) << 6;
9211 /* inst.operands[i] was set up by parse_address. Encode it into a
9212 Thumb32 format load or store instruction. Reject forms that cannot
9213 be used with such instructions. If is_t is true, reject forms that
9214 cannot be used with a T instruction; if is_d is true, reject forms
9215 that cannot be used with a D instruction. If it is a store insn,
9219 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9221 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9223 constraint (!inst.operands[i].isreg,
9224 _("Instruction does not support =N addresses"));
9226 inst.instruction |= inst.operands[i].reg << 16;
9227 if (inst.operands[i].immisreg)
9229 constraint (is_pc, BAD_PC_ADDRESSING);
9230 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9231 constraint (inst.operands[i].negative,
9232 _("Thumb does not support negative register indexing"));
9233 constraint (inst.operands[i].postind,
9234 _("Thumb does not support register post-indexing"));
9235 constraint (inst.operands[i].writeback,
9236 _("Thumb does not support register indexing with writeback"));
9237 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9238 _("Thumb supports only LSL in shifted register indexing"));
9240 inst.instruction |= inst.operands[i].imm;
9241 if (inst.operands[i].shifted)
9243 constraint (inst.reloc.exp.X_op != O_constant,
9244 _("expression too complex"));
9245 constraint (inst.reloc.exp.X_add_number < 0
9246 || inst.reloc.exp.X_add_number > 3,
9247 _("shift out of range"));
9248 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9250 inst.reloc.type = BFD_RELOC_UNUSED;
9252 else if (inst.operands[i].preind)
9254 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9255 constraint (is_t && inst.operands[i].writeback,
9256 _("cannot use writeback with this instruction"));
9257 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9258 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9262 inst.instruction |= 0x01000000;
9263 if (inst.operands[i].writeback)
9264 inst.instruction |= 0x00200000;
9268 inst.instruction |= 0x00000c00;
9269 if (inst.operands[i].writeback)
9270 inst.instruction |= 0x00000100;
9272 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9274 else if (inst.operands[i].postind)
9276 gas_assert (inst.operands[i].writeback);
9277 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9278 constraint (is_t, _("cannot use post-indexing with this instruction"));
9281 inst.instruction |= 0x00200000;
9283 inst.instruction |= 0x00000900;
9284 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9286 else /* unindexed - only for coprocessor */
9287 inst.error = _("instruction does not accept unindexed addressing");
9290 /* Table of Thumb instructions which exist in both 16- and 32-bit
9291 encodings (the latter only in post-V6T2 cores). The index is the
9292 value used in the insns table below. When there is more than one
9293 possible 16-bit encoding for the instruction, this table always
9295 Also contains several pseudo-instructions used during relaxation. */
9296 #define T16_32_TAB \
9297 X(_adc, 4140, eb400000), \
9298 X(_adcs, 4140, eb500000), \
9299 X(_add, 1c00, eb000000), \
9300 X(_adds, 1c00, eb100000), \
9301 X(_addi, 0000, f1000000), \
9302 X(_addis, 0000, f1100000), \
9303 X(_add_pc,000f, f20f0000), \
9304 X(_add_sp,000d, f10d0000), \
9305 X(_adr, 000f, f20f0000), \
9306 X(_and, 4000, ea000000), \
9307 X(_ands, 4000, ea100000), \
9308 X(_asr, 1000, fa40f000), \
9309 X(_asrs, 1000, fa50f000), \
9310 X(_b, e000, f000b000), \
9311 X(_bcond, d000, f0008000), \
9312 X(_bic, 4380, ea200000), \
9313 X(_bics, 4380, ea300000), \
9314 X(_cmn, 42c0, eb100f00), \
9315 X(_cmp, 2800, ebb00f00), \
9316 X(_cpsie, b660, f3af8400), \
9317 X(_cpsid, b670, f3af8600), \
9318 X(_cpy, 4600, ea4f0000), \
9319 X(_dec_sp,80dd, f1ad0d00), \
9320 X(_eor, 4040, ea800000), \
9321 X(_eors, 4040, ea900000), \
9322 X(_inc_sp,00dd, f10d0d00), \
9323 X(_ldmia, c800, e8900000), \
9324 X(_ldr, 6800, f8500000), \
9325 X(_ldrb, 7800, f8100000), \
9326 X(_ldrh, 8800, f8300000), \
9327 X(_ldrsb, 5600, f9100000), \
9328 X(_ldrsh, 5e00, f9300000), \
9329 X(_ldr_pc,4800, f85f0000), \
9330 X(_ldr_pc2,4800, f85f0000), \
9331 X(_ldr_sp,9800, f85d0000), \
9332 X(_lsl, 0000, fa00f000), \
9333 X(_lsls, 0000, fa10f000), \
9334 X(_lsr, 0800, fa20f000), \
9335 X(_lsrs, 0800, fa30f000), \
9336 X(_mov, 2000, ea4f0000), \
9337 X(_movs, 2000, ea5f0000), \
9338 X(_mul, 4340, fb00f000), \
9339 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9340 X(_mvn, 43c0, ea6f0000), \
9341 X(_mvns, 43c0, ea7f0000), \
9342 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9343 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9344 X(_orr, 4300, ea400000), \
9345 X(_orrs, 4300, ea500000), \
9346 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9347 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9348 X(_rev, ba00, fa90f080), \
9349 X(_rev16, ba40, fa90f090), \
9350 X(_revsh, bac0, fa90f0b0), \
9351 X(_ror, 41c0, fa60f000), \
9352 X(_rors, 41c0, fa70f000), \
9353 X(_sbc, 4180, eb600000), \
9354 X(_sbcs, 4180, eb700000), \
9355 X(_stmia, c000, e8800000), \
9356 X(_str, 6000, f8400000), \
9357 X(_strb, 7000, f8000000), \
9358 X(_strh, 8000, f8200000), \
9359 X(_str_sp,9000, f84d0000), \
9360 X(_sub, 1e00, eba00000), \
9361 X(_subs, 1e00, ebb00000), \
9362 X(_subi, 8000, f1a00000), \
9363 X(_subis, 8000, f1b00000), \
9364 X(_sxtb, b240, fa4ff080), \
9365 X(_sxth, b200, fa0ff080), \
9366 X(_tst, 4200, ea100f00), \
9367 X(_uxtb, b2c0, fa5ff080), \
9368 X(_uxth, b280, fa1ff080), \
9369 X(_nop, bf00, f3af8000), \
9370 X(_yield, bf10, f3af8001), \
9371 X(_wfe, bf20, f3af8002), \
9372 X(_wfi, bf30, f3af8003), \
9373 X(_sev, bf40, f3af8004),
9375 /* To catch errors in encoding functions, the codes are all offset by
9376 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9377 as 16-bit instructions. */
9378 #define X(a,b,c) T_MNEM##a
9379 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9382 #define X(a,b,c) 0x##b
9383 static const unsigned short thumb_op16[] = { T16_32_TAB };
9384 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9387 #define X(a,b,c) 0x##c
9388 static const unsigned int thumb_op32[] = { T16_32_TAB };
9389 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9390 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9394 /* Thumb instruction encoders, in alphabetical order. */
9399 do_t_add_sub_w (void)
9403 Rd = inst.operands[0].reg;
9404 Rn = inst.operands[1].reg;
9406 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9407 is the SP-{plus,minus}-immediate form of the instruction. */
9409 constraint (Rd == REG_PC, BAD_PC);
9411 reject_bad_reg (Rd);
9413 inst.instruction |= (Rn << 16) | (Rd << 8);
9414 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9417 /* Parse an add or subtract instruction. We get here with inst.instruction
9418 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9425 Rd = inst.operands[0].reg;
9426 Rs = (inst.operands[1].present
9427 ? inst.operands[1].reg /* Rd, Rs, foo */
9428 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9431 set_it_insn_type_last ();
9439 flags = (inst.instruction == T_MNEM_adds
9440 || inst.instruction == T_MNEM_subs);
9442 narrow = !in_it_block ();
9444 narrow = in_it_block ();
9445 if (!inst.operands[2].isreg)
9449 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9451 add = (inst.instruction == T_MNEM_add
9452 || inst.instruction == T_MNEM_adds);
9454 if (inst.size_req != 4)
9456 /* Attempt to use a narrow opcode, with relaxation if
9458 if (Rd == REG_SP && Rs == REG_SP && !flags)
9459 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9460 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9461 opcode = T_MNEM_add_sp;
9462 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9463 opcode = T_MNEM_add_pc;
9464 else if (Rd <= 7 && Rs <= 7 && narrow)
9467 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9469 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9473 inst.instruction = THUMB_OP16(opcode);
9474 inst.instruction |= (Rd << 4) | Rs;
9475 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9476 if (inst.size_req != 2)
9477 inst.relax = opcode;
9480 constraint (inst.size_req == 2, BAD_HIREG);
9482 if (inst.size_req == 4
9483 || (inst.size_req != 2 && !opcode))
9487 constraint (add, BAD_PC);
9488 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9489 _("only SUBS PC, LR, #const allowed"));
9490 constraint (inst.reloc.exp.X_op != O_constant,
9491 _("expression too complex"));
9492 constraint (inst.reloc.exp.X_add_number < 0
9493 || inst.reloc.exp.X_add_number > 0xff,
9494 _("immediate value out of range"));
9495 inst.instruction = T2_SUBS_PC_LR
9496 | inst.reloc.exp.X_add_number;
9497 inst.reloc.type = BFD_RELOC_UNUSED;
9500 else if (Rs == REG_PC)
9502 /* Always use addw/subw. */
9503 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9504 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9508 inst.instruction = THUMB_OP32 (inst.instruction);
9509 inst.instruction = (inst.instruction & 0xe1ffffff)
9512 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9514 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9516 inst.instruction |= Rd << 8;
9517 inst.instruction |= Rs << 16;
9522 unsigned int value = inst.reloc.exp.X_add_number;
9523 unsigned int shift = inst.operands[2].shift_kind;
9525 Rn = inst.operands[2].reg;
9526 /* See if we can do this with a 16-bit instruction. */
9527 if (!inst.operands[2].shifted && inst.size_req != 4)
9529 if (Rd > 7 || Rs > 7 || Rn > 7)
9534 inst.instruction = ((inst.instruction == T_MNEM_adds
9535 || inst.instruction == T_MNEM_add)
9538 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9542 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9544 /* Thumb-1 cores (except v6-M) require at least one high
9545 register in a narrow non flag setting add. */
9546 if (Rd > 7 || Rn > 7
9547 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9548 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9555 inst.instruction = T_OPCODE_ADD_HI;
9556 inst.instruction |= (Rd & 8) << 4;
9557 inst.instruction |= (Rd & 7);
9558 inst.instruction |= Rn << 3;
9564 constraint (Rd == REG_PC, BAD_PC);
9565 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9566 constraint (Rs == REG_PC, BAD_PC);
9567 reject_bad_reg (Rn);
9569 /* If we get here, it can't be done in 16 bits. */
9570 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9571 _("shift must be constant"));
9572 inst.instruction = THUMB_OP32 (inst.instruction);
9573 inst.instruction |= Rd << 8;
9574 inst.instruction |= Rs << 16;
9575 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9576 _("shift value over 3 not allowed in thumb mode"));
9577 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9578 _("only LSL shift allowed in thumb mode"));
9579 encode_thumb32_shifted_operand (2);
9584 constraint (inst.instruction == T_MNEM_adds
9585 || inst.instruction == T_MNEM_subs,
9588 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9590 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9591 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9594 inst.instruction = (inst.instruction == T_MNEM_add
9596 inst.instruction |= (Rd << 4) | Rs;
9597 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9601 Rn = inst.operands[2].reg;
9602 constraint (inst.operands[2].shifted, _("unshifted register required"));
9604 /* We now have Rd, Rs, and Rn set to registers. */
9605 if (Rd > 7 || Rs > 7 || Rn > 7)
9607 /* Can't do this for SUB. */
9608 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9609 inst.instruction = T_OPCODE_ADD_HI;
9610 inst.instruction |= (Rd & 8) << 4;
9611 inst.instruction |= (Rd & 7);
9613 inst.instruction |= Rn << 3;
9615 inst.instruction |= Rs << 3;
9617 constraint (1, _("dest must overlap one source register"));
9621 inst.instruction = (inst.instruction == T_MNEM_add
9622 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9623 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9633 Rd = inst.operands[0].reg;
9634 reject_bad_reg (Rd);
9636 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9638 /* Defer to section relaxation. */
9639 inst.relax = inst.instruction;
9640 inst.instruction = THUMB_OP16 (inst.instruction);
9641 inst.instruction |= Rd << 4;
9643 else if (unified_syntax && inst.size_req != 2)
9645 /* Generate a 32-bit opcode. */
9646 inst.instruction = THUMB_OP32 (inst.instruction);
9647 inst.instruction |= Rd << 8;
9648 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9649 inst.reloc.pc_rel = 1;
9653 /* Generate a 16-bit opcode. */
9654 inst.instruction = THUMB_OP16 (inst.instruction);
9655 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9656 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9657 inst.reloc.pc_rel = 1;
9659 inst.instruction |= Rd << 4;
9663 /* Arithmetic instructions for which there is just one 16-bit
9664 instruction encoding, and it allows only two low registers.
9665 For maximal compatibility with ARM syntax, we allow three register
9666 operands even when Thumb-32 instructions are not available, as long
9667 as the first two are identical. For instance, both "sbc r0,r1" and
9668 "sbc r0,r0,r1" are allowed. */
9674 Rd = inst.operands[0].reg;
9675 Rs = (inst.operands[1].present
9676 ? inst.operands[1].reg /* Rd, Rs, foo */
9677 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9678 Rn = inst.operands[2].reg;
9680 reject_bad_reg (Rd);
9681 reject_bad_reg (Rs);
9682 if (inst.operands[2].isreg)
9683 reject_bad_reg (Rn);
9687 if (!inst.operands[2].isreg)
9689 /* For an immediate, we always generate a 32-bit opcode;
9690 section relaxation will shrink it later if possible. */
9691 inst.instruction = THUMB_OP32 (inst.instruction);
9692 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9693 inst.instruction |= Rd << 8;
9694 inst.instruction |= Rs << 16;
9695 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9701 /* See if we can do this with a 16-bit instruction. */
9702 if (THUMB_SETS_FLAGS (inst.instruction))
9703 narrow = !in_it_block ();
9705 narrow = in_it_block ();
9707 if (Rd > 7 || Rn > 7 || Rs > 7)
9709 if (inst.operands[2].shifted)
9711 if (inst.size_req == 4)
9717 inst.instruction = THUMB_OP16 (inst.instruction);
9718 inst.instruction |= Rd;
9719 inst.instruction |= Rn << 3;
9723 /* If we get here, it can't be done in 16 bits. */
9724 constraint (inst.operands[2].shifted
9725 && inst.operands[2].immisreg,
9726 _("shift must be constant"));
9727 inst.instruction = THUMB_OP32 (inst.instruction);
9728 inst.instruction |= Rd << 8;
9729 inst.instruction |= Rs << 16;
9730 encode_thumb32_shifted_operand (2);
9735 /* On its face this is a lie - the instruction does set the
9736 flags. However, the only supported mnemonic in this mode
9738 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9740 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9741 _("unshifted register required"));
9742 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9743 constraint (Rd != Rs,
9744 _("dest and source1 must be the same register"));
9746 inst.instruction = THUMB_OP16 (inst.instruction);
9747 inst.instruction |= Rd;
9748 inst.instruction |= Rn << 3;
9752 /* Similarly, but for instructions where the arithmetic operation is
9753 commutative, so we can allow either of them to be different from
9754 the destination operand in a 16-bit instruction. For instance, all
9755 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9762 Rd = inst.operands[0].reg;
9763 Rs = (inst.operands[1].present
9764 ? inst.operands[1].reg /* Rd, Rs, foo */
9765 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9766 Rn = inst.operands[2].reg;
9768 reject_bad_reg (Rd);
9769 reject_bad_reg (Rs);
9770 if (inst.operands[2].isreg)
9771 reject_bad_reg (Rn);
9775 if (!inst.operands[2].isreg)
9777 /* For an immediate, we always generate a 32-bit opcode;
9778 section relaxation will shrink it later if possible. */
9779 inst.instruction = THUMB_OP32 (inst.instruction);
9780 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9781 inst.instruction |= Rd << 8;
9782 inst.instruction |= Rs << 16;
9783 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9789 /* See if we can do this with a 16-bit instruction. */
9790 if (THUMB_SETS_FLAGS (inst.instruction))
9791 narrow = !in_it_block ();
9793 narrow = in_it_block ();
9795 if (Rd > 7 || Rn > 7 || Rs > 7)
9797 if (inst.operands[2].shifted)
9799 if (inst.size_req == 4)
9806 inst.instruction = THUMB_OP16 (inst.instruction);
9807 inst.instruction |= Rd;
9808 inst.instruction |= Rn << 3;
9813 inst.instruction = THUMB_OP16 (inst.instruction);
9814 inst.instruction |= Rd;
9815 inst.instruction |= Rs << 3;
9820 /* If we get here, it can't be done in 16 bits. */
9821 constraint (inst.operands[2].shifted
9822 && inst.operands[2].immisreg,
9823 _("shift must be constant"));
9824 inst.instruction = THUMB_OP32 (inst.instruction);
9825 inst.instruction |= Rd << 8;
9826 inst.instruction |= Rs << 16;
9827 encode_thumb32_shifted_operand (2);
9832 /* On its face this is a lie - the instruction does set the
9833 flags. However, the only supported mnemonic in this mode
9835 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9837 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9838 _("unshifted register required"));
9839 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9841 inst.instruction = THUMB_OP16 (inst.instruction);
9842 inst.instruction |= Rd;
9845 inst.instruction |= Rn << 3;
9847 inst.instruction |= Rs << 3;
9849 constraint (1, _("dest must overlap one source register"));
9856 if (inst.operands[0].present)
9858 constraint ((inst.instruction & 0xf0) != 0x40
9859 && inst.operands[0].imm > 0xf
9860 && inst.operands[0].imm < 0x0,
9861 _("bad barrier type"));
9862 inst.instruction |= inst.operands[0].imm;
9865 inst.instruction |= 0xf;
9872 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9873 constraint (msb > 32, _("bit-field extends past end of register"));
9874 /* The instruction encoding stores the LSB and MSB,
9875 not the LSB and width. */
9876 Rd = inst.operands[0].reg;
9877 reject_bad_reg (Rd);
9878 inst.instruction |= Rd << 8;
9879 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9880 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9881 inst.instruction |= msb - 1;
9890 Rd = inst.operands[0].reg;
9891 reject_bad_reg (Rd);
9893 /* #0 in second position is alternative syntax for bfc, which is
9894 the same instruction but with REG_PC in the Rm field. */
9895 if (!inst.operands[1].isreg)
9899 Rn = inst.operands[1].reg;
9900 reject_bad_reg (Rn);
9903 msb = inst.operands[2].imm + inst.operands[3].imm;
9904 constraint (msb > 32, _("bit-field extends past end of register"));
9905 /* The instruction encoding stores the LSB and MSB,
9906 not the LSB and width. */
9907 inst.instruction |= Rd << 8;
9908 inst.instruction |= Rn << 16;
9909 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9910 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9911 inst.instruction |= msb - 1;
9919 Rd = inst.operands[0].reg;
9920 Rn = inst.operands[1].reg;
9922 reject_bad_reg (Rd);
9923 reject_bad_reg (Rn);
9925 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9926 _("bit-field extends past end of register"));
9927 inst.instruction |= Rd << 8;
9928 inst.instruction |= Rn << 16;
9929 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9930 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9931 inst.instruction |= inst.operands[3].imm - 1;
9934 /* ARM V5 Thumb BLX (argument parse)
9935 BLX <target_addr> which is BLX(1)
9936 BLX <Rm> which is BLX(2)
9937 Unfortunately, there are two different opcodes for this mnemonic.
9938 So, the insns[].value is not used, and the code here zaps values
9939 into inst.instruction.
9941 ??? How to take advantage of the additional two bits of displacement
9942 available in Thumb32 mode? Need new relocation? */
9947 set_it_insn_type_last ();
9949 if (inst.operands[0].isreg)
9951 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9952 /* We have a register, so this is BLX(2). */
9953 inst.instruction |= inst.operands[0].reg << 3;
9957 /* No register. This must be BLX(1). */
9958 inst.instruction = 0xf000e800;
9959 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
9971 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
9975 /* Conditional branches inside IT blocks are encoded as unconditional
9982 if (cond != COND_ALWAYS)
9983 opcode = T_MNEM_bcond;
9985 opcode = inst.instruction;
9988 && (inst.size_req == 4
9989 || (inst.size_req != 2
9990 && (inst.operands[0].hasreloc
9991 || inst.reloc.exp.X_op == O_constant))))
9993 inst.instruction = THUMB_OP32(opcode);
9994 if (cond == COND_ALWAYS)
9995 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
9998 gas_assert (cond != 0xF);
9999 inst.instruction |= cond << 22;
10000 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10005 inst.instruction = THUMB_OP16(opcode);
10006 if (cond == COND_ALWAYS)
10007 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10010 inst.instruction |= cond << 8;
10011 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10013 /* Allow section relaxation. */
10014 if (unified_syntax && inst.size_req != 2)
10015 inst.relax = opcode;
10017 inst.reloc.type = reloc;
10018 inst.reloc.pc_rel = 1;
10024 constraint (inst.cond != COND_ALWAYS,
10025 _("instruction is always unconditional"));
10026 if (inst.operands[0].present)
10028 constraint (inst.operands[0].imm > 255,
10029 _("immediate value out of range"));
10030 inst.instruction |= inst.operands[0].imm;
10031 set_it_insn_type (NEUTRAL_IT_INSN);
10036 do_t_branch23 (void)
10038 set_it_insn_type_last ();
10039 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10041 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10042 this file. We used to simply ignore the PLT reloc type here --
10043 the branch encoding is now needed to deal with TLSCALL relocs.
10044 So if we see a PLT reloc now, put it back to how it used to be to
10045 keep the preexisting behaviour. */
10046 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10047 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10049 #if defined(OBJ_COFF)
10050 /* If the destination of the branch is a defined symbol which does not have
10051 the THUMB_FUNC attribute, then we must be calling a function which has
10052 the (interfacearm) attribute. We look for the Thumb entry point to that
10053 function and change the branch to refer to that function instead. */
10054 if ( inst.reloc.exp.X_op == O_symbol
10055 && inst.reloc.exp.X_add_symbol != NULL
10056 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10057 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10058 inst.reloc.exp.X_add_symbol =
10059 find_real_start (inst.reloc.exp.X_add_symbol);
10066 set_it_insn_type_last ();
10067 inst.instruction |= inst.operands[0].reg << 3;
10068 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10069 should cause the alignment to be checked once it is known. This is
10070 because BX PC only works if the instruction is word aligned. */
10078 set_it_insn_type_last ();
10079 Rm = inst.operands[0].reg;
10080 reject_bad_reg (Rm);
10081 inst.instruction |= Rm << 16;
10090 Rd = inst.operands[0].reg;
10091 Rm = inst.operands[1].reg;
10093 reject_bad_reg (Rd);
10094 reject_bad_reg (Rm);
10096 inst.instruction |= Rd << 8;
10097 inst.instruction |= Rm << 16;
10098 inst.instruction |= Rm;
10104 set_it_insn_type (OUTSIDE_IT_INSN);
10105 inst.instruction |= inst.operands[0].imm;
10111 set_it_insn_type (OUTSIDE_IT_INSN);
10113 && (inst.operands[1].present || inst.size_req == 4)
10114 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10116 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10117 inst.instruction = 0xf3af8000;
10118 inst.instruction |= imod << 9;
10119 inst.instruction |= inst.operands[0].imm << 5;
10120 if (inst.operands[1].present)
10121 inst.instruction |= 0x100 | inst.operands[1].imm;
10125 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10126 && (inst.operands[0].imm & 4),
10127 _("selected processor does not support 'A' form "
10128 "of this instruction"));
10129 constraint (inst.operands[1].present || inst.size_req == 4,
10130 _("Thumb does not support the 2-argument "
10131 "form of this instruction"));
10132 inst.instruction |= inst.operands[0].imm;
10136 /* THUMB CPY instruction (argument parse). */
10141 if (inst.size_req == 4)
10143 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10144 inst.instruction |= inst.operands[0].reg << 8;
10145 inst.instruction |= inst.operands[1].reg;
10149 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10150 inst.instruction |= (inst.operands[0].reg & 0x7);
10151 inst.instruction |= inst.operands[1].reg << 3;
10158 set_it_insn_type (OUTSIDE_IT_INSN);
10159 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10160 inst.instruction |= inst.operands[0].reg;
10161 inst.reloc.pc_rel = 1;
10162 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10168 inst.instruction |= inst.operands[0].imm;
10174 unsigned Rd, Rn, Rm;
10176 Rd = inst.operands[0].reg;
10177 Rn = (inst.operands[1].present
10178 ? inst.operands[1].reg : Rd);
10179 Rm = inst.operands[2].reg;
10181 reject_bad_reg (Rd);
10182 reject_bad_reg (Rn);
10183 reject_bad_reg (Rm);
10185 inst.instruction |= Rd << 8;
10186 inst.instruction |= Rn << 16;
10187 inst.instruction |= Rm;
10193 if (unified_syntax && inst.size_req == 4)
10194 inst.instruction = THUMB_OP32 (inst.instruction);
10196 inst.instruction = THUMB_OP16 (inst.instruction);
10202 unsigned int cond = inst.operands[0].imm;
10204 set_it_insn_type (IT_INSN);
10205 now_it.mask = (inst.instruction & 0xf) | 0x10;
10208 /* If the condition is a negative condition, invert the mask. */
10209 if ((cond & 0x1) == 0x0)
10211 unsigned int mask = inst.instruction & 0x000f;
10213 if ((mask & 0x7) == 0)
10214 /* no conversion needed */;
10215 else if ((mask & 0x3) == 0)
10217 else if ((mask & 0x1) == 0)
10222 inst.instruction &= 0xfff0;
10223 inst.instruction |= mask;
10226 inst.instruction |= cond << 4;
10229 /* Helper function used for both push/pop and ldm/stm. */
10231 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10235 load = (inst.instruction & (1 << 20)) != 0;
10237 if (mask & (1 << 13))
10238 inst.error = _("SP not allowed in register list");
10240 if ((mask & (1 << base)) != 0
10242 inst.error = _("having the base register in the register list when "
10243 "using write back is UNPREDICTABLE");
10247 if (mask & (1 << 15))
10249 if (mask & (1 << 14))
10250 inst.error = _("LR and PC should not both be in register list");
10252 set_it_insn_type_last ();
10257 if (mask & (1 << 15))
10258 inst.error = _("PC not allowed in register list");
10261 if ((mask & (mask - 1)) == 0)
10263 /* Single register transfers implemented as str/ldr. */
10266 if (inst.instruction & (1 << 23))
10267 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10269 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10273 if (inst.instruction & (1 << 23))
10274 inst.instruction = 0x00800000; /* ia -> [base] */
10276 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10279 inst.instruction |= 0xf8400000;
10281 inst.instruction |= 0x00100000;
10283 mask = ffs (mask) - 1;
10286 else if (writeback)
10287 inst.instruction |= WRITE_BACK;
10289 inst.instruction |= mask;
10290 inst.instruction |= base << 16;
10296 /* This really doesn't seem worth it. */
10297 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10298 _("expression too complex"));
10299 constraint (inst.operands[1].writeback,
10300 _("Thumb load/store multiple does not support {reglist}^"));
10302 if (unified_syntax)
10304 bfd_boolean narrow;
10308 /* See if we can use a 16-bit instruction. */
10309 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10310 && inst.size_req != 4
10311 && !(inst.operands[1].imm & ~0xff))
10313 mask = 1 << inst.operands[0].reg;
10315 if (inst.operands[0].reg <= 7)
10317 if (inst.instruction == T_MNEM_stmia
10318 ? inst.operands[0].writeback
10319 : (inst.operands[0].writeback
10320 == !(inst.operands[1].imm & mask)))
10322 if (inst.instruction == T_MNEM_stmia
10323 && (inst.operands[1].imm & mask)
10324 && (inst.operands[1].imm & (mask - 1)))
10325 as_warn (_("value stored for r%d is UNKNOWN"),
10326 inst.operands[0].reg);
10328 inst.instruction = THUMB_OP16 (inst.instruction);
10329 inst.instruction |= inst.operands[0].reg << 8;
10330 inst.instruction |= inst.operands[1].imm;
10333 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10335 /* This means 1 register in reg list one of 3 situations:
10336 1. Instruction is stmia, but without writeback.
10337 2. lmdia without writeback, but with Rn not in
10339 3. ldmia with writeback, but with Rn in reglist.
10340 Case 3 is UNPREDICTABLE behaviour, so we handle
10341 case 1 and 2 which can be converted into a 16-bit
10342 str or ldr. The SP cases are handled below. */
10343 unsigned long opcode;
10344 /* First, record an error for Case 3. */
10345 if (inst.operands[1].imm & mask
10346 && inst.operands[0].writeback)
10348 _("having the base register in the register list when "
10349 "using write back is UNPREDICTABLE");
10351 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10353 inst.instruction = THUMB_OP16 (opcode);
10354 inst.instruction |= inst.operands[0].reg << 3;
10355 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10359 else if (inst.operands[0] .reg == REG_SP)
10361 if (inst.operands[0].writeback)
10364 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10365 ? T_MNEM_push : T_MNEM_pop);
10366 inst.instruction |= inst.operands[1].imm;
10369 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10372 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10373 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10374 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10382 if (inst.instruction < 0xffff)
10383 inst.instruction = THUMB_OP32 (inst.instruction);
10385 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10386 inst.operands[0].writeback);
10391 constraint (inst.operands[0].reg > 7
10392 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10393 constraint (inst.instruction != T_MNEM_ldmia
10394 && inst.instruction != T_MNEM_stmia,
10395 _("Thumb-2 instruction only valid in unified syntax"));
10396 if (inst.instruction == T_MNEM_stmia)
10398 if (!inst.operands[0].writeback)
10399 as_warn (_("this instruction will write back the base register"));
10400 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10401 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10402 as_warn (_("value stored for r%d is UNKNOWN"),
10403 inst.operands[0].reg);
10407 if (!inst.operands[0].writeback
10408 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10409 as_warn (_("this instruction will write back the base register"));
10410 else if (inst.operands[0].writeback
10411 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10412 as_warn (_("this instruction will not write back the base register"));
10415 inst.instruction = THUMB_OP16 (inst.instruction);
10416 inst.instruction |= inst.operands[0].reg << 8;
10417 inst.instruction |= inst.operands[1].imm;
10424 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10425 || inst.operands[1].postind || inst.operands[1].writeback
10426 || inst.operands[1].immisreg || inst.operands[1].shifted
10427 || inst.operands[1].negative,
10430 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10432 inst.instruction |= inst.operands[0].reg << 12;
10433 inst.instruction |= inst.operands[1].reg << 16;
10434 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10440 if (!inst.operands[1].present)
10442 constraint (inst.operands[0].reg == REG_LR,
10443 _("r14 not allowed as first register "
10444 "when second register is omitted"));
10445 inst.operands[1].reg = inst.operands[0].reg + 1;
10447 constraint (inst.operands[0].reg == inst.operands[1].reg,
10450 inst.instruction |= inst.operands[0].reg << 12;
10451 inst.instruction |= inst.operands[1].reg << 8;
10452 inst.instruction |= inst.operands[2].reg << 16;
10458 unsigned long opcode;
10461 if (inst.operands[0].isreg
10462 && !inst.operands[0].preind
10463 && inst.operands[0].reg == REG_PC)
10464 set_it_insn_type_last ();
10466 opcode = inst.instruction;
10467 if (unified_syntax)
10469 if (!inst.operands[1].isreg)
10471 if (opcode <= 0xffff)
10472 inst.instruction = THUMB_OP32 (opcode);
10473 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10476 if (inst.operands[1].isreg
10477 && !inst.operands[1].writeback
10478 && !inst.operands[1].shifted && !inst.operands[1].postind
10479 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10480 && opcode <= 0xffff
10481 && inst.size_req != 4)
10483 /* Insn may have a 16-bit form. */
10484 Rn = inst.operands[1].reg;
10485 if (inst.operands[1].immisreg)
10487 inst.instruction = THUMB_OP16 (opcode);
10489 if (Rn <= 7 && inst.operands[1].imm <= 7)
10491 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10492 reject_bad_reg (inst.operands[1].imm);
10494 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10495 && opcode != T_MNEM_ldrsb)
10496 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10497 || (Rn == REG_SP && opcode == T_MNEM_str))
10504 if (inst.reloc.pc_rel)
10505 opcode = T_MNEM_ldr_pc2;
10507 opcode = T_MNEM_ldr_pc;
10511 if (opcode == T_MNEM_ldr)
10512 opcode = T_MNEM_ldr_sp;
10514 opcode = T_MNEM_str_sp;
10516 inst.instruction = inst.operands[0].reg << 8;
10520 inst.instruction = inst.operands[0].reg;
10521 inst.instruction |= inst.operands[1].reg << 3;
10523 inst.instruction |= THUMB_OP16 (opcode);
10524 if (inst.size_req == 2)
10525 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10527 inst.relax = opcode;
10531 /* Definitely a 32-bit variant. */
10533 /* Warning for Erratum 752419. */
10534 if (opcode == T_MNEM_ldr
10535 && inst.operands[0].reg == REG_SP
10536 && inst.operands[1].writeback == 1
10537 && !inst.operands[1].immisreg)
10539 if (no_cpu_selected ()
10540 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10541 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10542 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10543 as_warn (_("This instruction may be unpredictable "
10544 "if executed on M-profile cores "
10545 "with interrupts enabled."));
10548 /* Do some validations regarding addressing modes. */
10549 if (inst.operands[1].immisreg)
10550 reject_bad_reg (inst.operands[1].imm);
10552 constraint (inst.operands[1].writeback == 1
10553 && inst.operands[0].reg == inst.operands[1].reg,
10556 inst.instruction = THUMB_OP32 (opcode);
10557 inst.instruction |= inst.operands[0].reg << 12;
10558 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10559 check_ldr_r15_aligned ();
10563 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10565 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10567 /* Only [Rn,Rm] is acceptable. */
10568 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10569 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10570 || inst.operands[1].postind || inst.operands[1].shifted
10571 || inst.operands[1].negative,
10572 _("Thumb does not support this addressing mode"));
10573 inst.instruction = THUMB_OP16 (inst.instruction);
10577 inst.instruction = THUMB_OP16 (inst.instruction);
10578 if (!inst.operands[1].isreg)
10579 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10582 constraint (!inst.operands[1].preind
10583 || inst.operands[1].shifted
10584 || inst.operands[1].writeback,
10585 _("Thumb does not support this addressing mode"));
10586 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10588 constraint (inst.instruction & 0x0600,
10589 _("byte or halfword not valid for base register"));
10590 constraint (inst.operands[1].reg == REG_PC
10591 && !(inst.instruction & THUMB_LOAD_BIT),
10592 _("r15 based store not allowed"));
10593 constraint (inst.operands[1].immisreg,
10594 _("invalid base register for register offset"));
10596 if (inst.operands[1].reg == REG_PC)
10597 inst.instruction = T_OPCODE_LDR_PC;
10598 else if (inst.instruction & THUMB_LOAD_BIT)
10599 inst.instruction = T_OPCODE_LDR_SP;
10601 inst.instruction = T_OPCODE_STR_SP;
10603 inst.instruction |= inst.operands[0].reg << 8;
10604 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10608 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10609 if (!inst.operands[1].immisreg)
10611 /* Immediate offset. */
10612 inst.instruction |= inst.operands[0].reg;
10613 inst.instruction |= inst.operands[1].reg << 3;
10614 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10618 /* Register offset. */
10619 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10620 constraint (inst.operands[1].negative,
10621 _("Thumb does not support this addressing mode"));
10624 switch (inst.instruction)
10626 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10627 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10628 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10629 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10630 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10631 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10632 case 0x5600 /* ldrsb */:
10633 case 0x5e00 /* ldrsh */: break;
10637 inst.instruction |= inst.operands[0].reg;
10638 inst.instruction |= inst.operands[1].reg << 3;
10639 inst.instruction |= inst.operands[1].imm << 6;
10645 if (!inst.operands[1].present)
10647 inst.operands[1].reg = inst.operands[0].reg + 1;
10648 constraint (inst.operands[0].reg == REG_LR,
10649 _("r14 not allowed here"));
10651 inst.instruction |= inst.operands[0].reg << 12;
10652 inst.instruction |= inst.operands[1].reg << 8;
10653 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10659 inst.instruction |= inst.operands[0].reg << 12;
10660 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10666 unsigned Rd, Rn, Rm, Ra;
10668 Rd = inst.operands[0].reg;
10669 Rn = inst.operands[1].reg;
10670 Rm = inst.operands[2].reg;
10671 Ra = inst.operands[3].reg;
10673 reject_bad_reg (Rd);
10674 reject_bad_reg (Rn);
10675 reject_bad_reg (Rm);
10676 reject_bad_reg (Ra);
10678 inst.instruction |= Rd << 8;
10679 inst.instruction |= Rn << 16;
10680 inst.instruction |= Rm;
10681 inst.instruction |= Ra << 12;
10687 unsigned RdLo, RdHi, Rn, Rm;
10689 RdLo = inst.operands[0].reg;
10690 RdHi = inst.operands[1].reg;
10691 Rn = inst.operands[2].reg;
10692 Rm = inst.operands[3].reg;
10694 reject_bad_reg (RdLo);
10695 reject_bad_reg (RdHi);
10696 reject_bad_reg (Rn);
10697 reject_bad_reg (Rm);
10699 inst.instruction |= RdLo << 12;
10700 inst.instruction |= RdHi << 8;
10701 inst.instruction |= Rn << 16;
10702 inst.instruction |= Rm;
10706 do_t_mov_cmp (void)
10710 Rn = inst.operands[0].reg;
10711 Rm = inst.operands[1].reg;
10714 set_it_insn_type_last ();
10716 if (unified_syntax)
10718 int r0off = (inst.instruction == T_MNEM_mov
10719 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10720 unsigned long opcode;
10721 bfd_boolean narrow;
10722 bfd_boolean low_regs;
10724 low_regs = (Rn <= 7 && Rm <= 7);
10725 opcode = inst.instruction;
10726 if (in_it_block ())
10727 narrow = opcode != T_MNEM_movs;
10729 narrow = opcode != T_MNEM_movs || low_regs;
10730 if (inst.size_req == 4
10731 || inst.operands[1].shifted)
10734 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10735 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10736 && !inst.operands[1].shifted
10740 inst.instruction = T2_SUBS_PC_LR;
10744 if (opcode == T_MNEM_cmp)
10746 constraint (Rn == REG_PC, BAD_PC);
10749 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10751 warn_deprecated_sp (Rm);
10752 /* R15 was documented as a valid choice for Rm in ARMv6,
10753 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10754 tools reject R15, so we do too. */
10755 constraint (Rm == REG_PC, BAD_PC);
10758 reject_bad_reg (Rm);
10760 else if (opcode == T_MNEM_mov
10761 || opcode == T_MNEM_movs)
10763 if (inst.operands[1].isreg)
10765 if (opcode == T_MNEM_movs)
10767 reject_bad_reg (Rn);
10768 reject_bad_reg (Rm);
10772 /* This is mov.n. */
10773 if ((Rn == REG_SP || Rn == REG_PC)
10774 && (Rm == REG_SP || Rm == REG_PC))
10776 as_warn (_("Use of r%u as a source register is "
10777 "deprecated when r%u is the destination "
10778 "register."), Rm, Rn);
10783 /* This is mov.w. */
10784 constraint (Rn == REG_PC, BAD_PC);
10785 constraint (Rm == REG_PC, BAD_PC);
10786 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10790 reject_bad_reg (Rn);
10793 if (!inst.operands[1].isreg)
10795 /* Immediate operand. */
10796 if (!in_it_block () && opcode == T_MNEM_mov)
10798 if (low_regs && narrow)
10800 inst.instruction = THUMB_OP16 (opcode);
10801 inst.instruction |= Rn << 8;
10802 if (inst.size_req == 2)
10803 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10805 inst.relax = opcode;
10809 inst.instruction = THUMB_OP32 (inst.instruction);
10810 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10811 inst.instruction |= Rn << r0off;
10812 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10815 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10816 && (inst.instruction == T_MNEM_mov
10817 || inst.instruction == T_MNEM_movs))
10819 /* Register shifts are encoded as separate shift instructions. */
10820 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10822 if (in_it_block ())
10827 if (inst.size_req == 4)
10830 if (!low_regs || inst.operands[1].imm > 7)
10836 switch (inst.operands[1].shift_kind)
10839 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10842 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10845 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10848 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10854 inst.instruction = opcode;
10857 inst.instruction |= Rn;
10858 inst.instruction |= inst.operands[1].imm << 3;
10863 inst.instruction |= CONDS_BIT;
10865 inst.instruction |= Rn << 8;
10866 inst.instruction |= Rm << 16;
10867 inst.instruction |= inst.operands[1].imm;
10872 /* Some mov with immediate shift have narrow variants.
10873 Register shifts are handled above. */
10874 if (low_regs && inst.operands[1].shifted
10875 && (inst.instruction == T_MNEM_mov
10876 || inst.instruction == T_MNEM_movs))
10878 if (in_it_block ())
10879 narrow = (inst.instruction == T_MNEM_mov);
10881 narrow = (inst.instruction == T_MNEM_movs);
10886 switch (inst.operands[1].shift_kind)
10888 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10889 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10890 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10891 default: narrow = FALSE; break;
10897 inst.instruction |= Rn;
10898 inst.instruction |= Rm << 3;
10899 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10903 inst.instruction = THUMB_OP32 (inst.instruction);
10904 inst.instruction |= Rn << r0off;
10905 encode_thumb32_shifted_operand (1);
10909 switch (inst.instruction)
10912 inst.instruction = T_OPCODE_MOV_HR;
10913 inst.instruction |= (Rn & 0x8) << 4;
10914 inst.instruction |= (Rn & 0x7);
10915 inst.instruction |= Rm << 3;
10919 /* We know we have low registers at this point.
10920 Generate LSLS Rd, Rs, #0. */
10921 inst.instruction = T_OPCODE_LSL_I;
10922 inst.instruction |= Rn;
10923 inst.instruction |= Rm << 3;
10929 inst.instruction = T_OPCODE_CMP_LR;
10930 inst.instruction |= Rn;
10931 inst.instruction |= Rm << 3;
10935 inst.instruction = T_OPCODE_CMP_HR;
10936 inst.instruction |= (Rn & 0x8) << 4;
10937 inst.instruction |= (Rn & 0x7);
10938 inst.instruction |= Rm << 3;
10945 inst.instruction = THUMB_OP16 (inst.instruction);
10947 /* PR 10443: Do not silently ignore shifted operands. */
10948 constraint (inst.operands[1].shifted,
10949 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10951 if (inst.operands[1].isreg)
10953 if (Rn < 8 && Rm < 8)
10955 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10956 since a MOV instruction produces unpredictable results. */
10957 if (inst.instruction == T_OPCODE_MOV_I8)
10958 inst.instruction = T_OPCODE_ADD_I3;
10960 inst.instruction = T_OPCODE_CMP_LR;
10962 inst.instruction |= Rn;
10963 inst.instruction |= Rm << 3;
10967 if (inst.instruction == T_OPCODE_MOV_I8)
10968 inst.instruction = T_OPCODE_MOV_HR;
10970 inst.instruction = T_OPCODE_CMP_HR;
10976 constraint (Rn > 7,
10977 _("only lo regs allowed with immediate"));
10978 inst.instruction |= Rn << 8;
10979 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10990 top = (inst.instruction & 0x00800000) != 0;
10991 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
10993 constraint (top, _(":lower16: not allowed this instruction"));
10994 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
10996 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
10998 constraint (!top, _(":upper16: not allowed this instruction"));
10999 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11002 Rd = inst.operands[0].reg;
11003 reject_bad_reg (Rd);
11005 inst.instruction |= Rd << 8;
11006 if (inst.reloc.type == BFD_RELOC_UNUSED)
11008 imm = inst.reloc.exp.X_add_number;
11009 inst.instruction |= (imm & 0xf000) << 4;
11010 inst.instruction |= (imm & 0x0800) << 15;
11011 inst.instruction |= (imm & 0x0700) << 4;
11012 inst.instruction |= (imm & 0x00ff);
11017 do_t_mvn_tst (void)
11021 Rn = inst.operands[0].reg;
11022 Rm = inst.operands[1].reg;
11024 if (inst.instruction == T_MNEM_cmp
11025 || inst.instruction == T_MNEM_cmn)
11026 constraint (Rn == REG_PC, BAD_PC);
11028 reject_bad_reg (Rn);
11029 reject_bad_reg (Rm);
11031 if (unified_syntax)
11033 int r0off = (inst.instruction == T_MNEM_mvn
11034 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11035 bfd_boolean narrow;
11037 if (inst.size_req == 4
11038 || inst.instruction > 0xffff
11039 || inst.operands[1].shifted
11040 || Rn > 7 || Rm > 7)
11042 else if (inst.instruction == T_MNEM_cmn)
11044 else if (THUMB_SETS_FLAGS (inst.instruction))
11045 narrow = !in_it_block ();
11047 narrow = in_it_block ();
11049 if (!inst.operands[1].isreg)
11051 /* For an immediate, we always generate a 32-bit opcode;
11052 section relaxation will shrink it later if possible. */
11053 if (inst.instruction < 0xffff)
11054 inst.instruction = THUMB_OP32 (inst.instruction);
11055 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11056 inst.instruction |= Rn << r0off;
11057 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11061 /* See if we can do this with a 16-bit instruction. */
11064 inst.instruction = THUMB_OP16 (inst.instruction);
11065 inst.instruction |= Rn;
11066 inst.instruction |= Rm << 3;
11070 constraint (inst.operands[1].shifted
11071 && inst.operands[1].immisreg,
11072 _("shift must be constant"));
11073 if (inst.instruction < 0xffff)
11074 inst.instruction = THUMB_OP32 (inst.instruction);
11075 inst.instruction |= Rn << r0off;
11076 encode_thumb32_shifted_operand (1);
11082 constraint (inst.instruction > 0xffff
11083 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11084 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11085 _("unshifted register required"));
11086 constraint (Rn > 7 || Rm > 7,
11089 inst.instruction = THUMB_OP16 (inst.instruction);
11090 inst.instruction |= Rn;
11091 inst.instruction |= Rm << 3;
11100 if (do_vfp_nsyn_mrs () == SUCCESS)
11103 Rd = inst.operands[0].reg;
11104 reject_bad_reg (Rd);
11105 inst.instruction |= Rd << 8;
11107 if (inst.operands[1].isreg)
11109 unsigned br = inst.operands[1].reg;
11110 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11111 as_bad (_("bad register for mrs"));
11113 inst.instruction |= br & (0xf << 16);
11114 inst.instruction |= (br & 0x300) >> 4;
11115 inst.instruction |= (br & SPSR_BIT) >> 2;
11119 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11121 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11122 constraint (flags != 0, _("selected processor does not support "
11123 "requested special purpose register"));
11125 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11127 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11128 _("'APSR', 'CPSR' or 'SPSR' expected"));
11130 inst.instruction |= (flags & SPSR_BIT) >> 2;
11131 inst.instruction |= inst.operands[1].imm & 0xff;
11132 inst.instruction |= 0xf0000;
11142 if (do_vfp_nsyn_msr () == SUCCESS)
11145 constraint (!inst.operands[1].isreg,
11146 _("Thumb encoding does not support an immediate here"));
11148 if (inst.operands[0].isreg)
11149 flags = (int)(inst.operands[0].reg);
11151 flags = inst.operands[0].imm;
11153 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11155 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11157 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11158 && (bits & ~(PSR_s | PSR_f)) != 0)
11159 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11161 _("selected processor does not support requested special "
11162 "purpose register"));
11165 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11166 "requested special purpose register"));
11168 Rn = inst.operands[1].reg;
11169 reject_bad_reg (Rn);
11171 inst.instruction |= (flags & SPSR_BIT) >> 2;
11172 inst.instruction |= (flags & 0xf0000) >> 8;
11173 inst.instruction |= (flags & 0x300) >> 4;
11174 inst.instruction |= (flags & 0xff);
11175 inst.instruction |= Rn << 16;
11181 bfd_boolean narrow;
11182 unsigned Rd, Rn, Rm;
11184 if (!inst.operands[2].present)
11185 inst.operands[2].reg = inst.operands[0].reg;
11187 Rd = inst.operands[0].reg;
11188 Rn = inst.operands[1].reg;
11189 Rm = inst.operands[2].reg;
11191 if (unified_syntax)
11193 if (inst.size_req == 4
11199 else if (inst.instruction == T_MNEM_muls)
11200 narrow = !in_it_block ();
11202 narrow = in_it_block ();
11206 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11207 constraint (Rn > 7 || Rm > 7,
11214 /* 16-bit MULS/Conditional MUL. */
11215 inst.instruction = THUMB_OP16 (inst.instruction);
11216 inst.instruction |= Rd;
11219 inst.instruction |= Rm << 3;
11221 inst.instruction |= Rn << 3;
11223 constraint (1, _("dest must overlap one source register"));
11227 constraint (inst.instruction != T_MNEM_mul,
11228 _("Thumb-2 MUL must not set flags"));
11230 inst.instruction = THUMB_OP32 (inst.instruction);
11231 inst.instruction |= Rd << 8;
11232 inst.instruction |= Rn << 16;
11233 inst.instruction |= Rm << 0;
11235 reject_bad_reg (Rd);
11236 reject_bad_reg (Rn);
11237 reject_bad_reg (Rm);
11244 unsigned RdLo, RdHi, Rn, Rm;
11246 RdLo = inst.operands[0].reg;
11247 RdHi = inst.operands[1].reg;
11248 Rn = inst.operands[2].reg;
11249 Rm = inst.operands[3].reg;
11251 reject_bad_reg (RdLo);
11252 reject_bad_reg (RdHi);
11253 reject_bad_reg (Rn);
11254 reject_bad_reg (Rm);
11256 inst.instruction |= RdLo << 12;
11257 inst.instruction |= RdHi << 8;
11258 inst.instruction |= Rn << 16;
11259 inst.instruction |= Rm;
11262 as_tsktsk (_("rdhi and rdlo must be different"));
11268 set_it_insn_type (NEUTRAL_IT_INSN);
11270 if (unified_syntax)
11272 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11274 inst.instruction = THUMB_OP32 (inst.instruction);
11275 inst.instruction |= inst.operands[0].imm;
11279 /* PR9722: Check for Thumb2 availability before
11280 generating a thumb2 nop instruction. */
11281 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11283 inst.instruction = THUMB_OP16 (inst.instruction);
11284 inst.instruction |= inst.operands[0].imm << 4;
11287 inst.instruction = 0x46c0;
11292 constraint (inst.operands[0].present,
11293 _("Thumb does not support NOP with hints"));
11294 inst.instruction = 0x46c0;
11301 if (unified_syntax)
11303 bfd_boolean narrow;
11305 if (THUMB_SETS_FLAGS (inst.instruction))
11306 narrow = !in_it_block ();
11308 narrow = in_it_block ();
11309 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11311 if (inst.size_req == 4)
11316 inst.instruction = THUMB_OP32 (inst.instruction);
11317 inst.instruction |= inst.operands[0].reg << 8;
11318 inst.instruction |= inst.operands[1].reg << 16;
11322 inst.instruction = THUMB_OP16 (inst.instruction);
11323 inst.instruction |= inst.operands[0].reg;
11324 inst.instruction |= inst.operands[1].reg << 3;
11329 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11331 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11333 inst.instruction = THUMB_OP16 (inst.instruction);
11334 inst.instruction |= inst.operands[0].reg;
11335 inst.instruction |= inst.operands[1].reg << 3;
11344 Rd = inst.operands[0].reg;
11345 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11347 reject_bad_reg (Rd);
11348 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11349 reject_bad_reg (Rn);
11351 inst.instruction |= Rd << 8;
11352 inst.instruction |= Rn << 16;
11354 if (!inst.operands[2].isreg)
11356 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11357 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11363 Rm = inst.operands[2].reg;
11364 reject_bad_reg (Rm);
11366 constraint (inst.operands[2].shifted
11367 && inst.operands[2].immisreg,
11368 _("shift must be constant"));
11369 encode_thumb32_shifted_operand (2);
11376 unsigned Rd, Rn, Rm;
11378 Rd = inst.operands[0].reg;
11379 Rn = inst.operands[1].reg;
11380 Rm = inst.operands[2].reg;
11382 reject_bad_reg (Rd);
11383 reject_bad_reg (Rn);
11384 reject_bad_reg (Rm);
11386 inst.instruction |= Rd << 8;
11387 inst.instruction |= Rn << 16;
11388 inst.instruction |= Rm;
11389 if (inst.operands[3].present)
11391 unsigned int val = inst.reloc.exp.X_add_number;
11392 constraint (inst.reloc.exp.X_op != O_constant,
11393 _("expression too complex"));
11394 inst.instruction |= (val & 0x1c) << 10;
11395 inst.instruction |= (val & 0x03) << 6;
11402 if (!inst.operands[3].present)
11406 inst.instruction &= ~0x00000020;
11408 /* PR 10168. Swap the Rm and Rn registers. */
11409 Rtmp = inst.operands[1].reg;
11410 inst.operands[1].reg = inst.operands[2].reg;
11411 inst.operands[2].reg = Rtmp;
11419 if (inst.operands[0].immisreg)
11420 reject_bad_reg (inst.operands[0].imm);
11422 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11426 do_t_push_pop (void)
11430 constraint (inst.operands[0].writeback,
11431 _("push/pop do not support {reglist}^"));
11432 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11433 _("expression too complex"));
11435 mask = inst.operands[0].imm;
11436 if ((mask & ~0xff) == 0)
11437 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11438 else if ((inst.instruction == T_MNEM_push
11439 && (mask & ~0xff) == 1 << REG_LR)
11440 || (inst.instruction == T_MNEM_pop
11441 && (mask & ~0xff) == 1 << REG_PC))
11443 inst.instruction = THUMB_OP16 (inst.instruction);
11444 inst.instruction |= THUMB_PP_PC_LR;
11445 inst.instruction |= mask & 0xff;
11447 else if (unified_syntax)
11449 inst.instruction = THUMB_OP32 (inst.instruction);
11450 encode_thumb2_ldmstm (13, mask, TRUE);
11454 inst.error = _("invalid register list to push/pop instruction");
11464 Rd = inst.operands[0].reg;
11465 Rm = inst.operands[1].reg;
11467 reject_bad_reg (Rd);
11468 reject_bad_reg (Rm);
11470 inst.instruction |= Rd << 8;
11471 inst.instruction |= Rm << 16;
11472 inst.instruction |= Rm;
11480 Rd = inst.operands[0].reg;
11481 Rm = inst.operands[1].reg;
11483 reject_bad_reg (Rd);
11484 reject_bad_reg (Rm);
11486 if (Rd <= 7 && Rm <= 7
11487 && inst.size_req != 4)
11489 inst.instruction = THUMB_OP16 (inst.instruction);
11490 inst.instruction |= Rd;
11491 inst.instruction |= Rm << 3;
11493 else if (unified_syntax)
11495 inst.instruction = THUMB_OP32 (inst.instruction);
11496 inst.instruction |= Rd << 8;
11497 inst.instruction |= Rm << 16;
11498 inst.instruction |= Rm;
11501 inst.error = BAD_HIREG;
11509 Rd = inst.operands[0].reg;
11510 Rm = inst.operands[1].reg;
11512 reject_bad_reg (Rd);
11513 reject_bad_reg (Rm);
11515 inst.instruction |= Rd << 8;
11516 inst.instruction |= Rm;
11524 Rd = inst.operands[0].reg;
11525 Rs = (inst.operands[1].present
11526 ? inst.operands[1].reg /* Rd, Rs, foo */
11527 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11529 reject_bad_reg (Rd);
11530 reject_bad_reg (Rs);
11531 if (inst.operands[2].isreg)
11532 reject_bad_reg (inst.operands[2].reg);
11534 inst.instruction |= Rd << 8;
11535 inst.instruction |= Rs << 16;
11536 if (!inst.operands[2].isreg)
11538 bfd_boolean narrow;
11540 if ((inst.instruction & 0x00100000) != 0)
11541 narrow = !in_it_block ();
11543 narrow = in_it_block ();
11545 if (Rd > 7 || Rs > 7)
11548 if (inst.size_req == 4 || !unified_syntax)
11551 if (inst.reloc.exp.X_op != O_constant
11552 || inst.reloc.exp.X_add_number != 0)
11555 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11556 relaxation, but it doesn't seem worth the hassle. */
11559 inst.reloc.type = BFD_RELOC_UNUSED;
11560 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11561 inst.instruction |= Rs << 3;
11562 inst.instruction |= Rd;
11566 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11567 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11571 encode_thumb32_shifted_operand (2);
11577 set_it_insn_type (OUTSIDE_IT_INSN);
11578 if (inst.operands[0].imm)
11579 inst.instruction |= 0x8;
11585 if (!inst.operands[1].present)
11586 inst.operands[1].reg = inst.operands[0].reg;
11588 if (unified_syntax)
11590 bfd_boolean narrow;
11593 switch (inst.instruction)
11596 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11598 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11600 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11602 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11606 if (THUMB_SETS_FLAGS (inst.instruction))
11607 narrow = !in_it_block ();
11609 narrow = in_it_block ();
11610 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11612 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11614 if (inst.operands[2].isreg
11615 && (inst.operands[1].reg != inst.operands[0].reg
11616 || inst.operands[2].reg > 7))
11618 if (inst.size_req == 4)
11621 reject_bad_reg (inst.operands[0].reg);
11622 reject_bad_reg (inst.operands[1].reg);
11626 if (inst.operands[2].isreg)
11628 reject_bad_reg (inst.operands[2].reg);
11629 inst.instruction = THUMB_OP32 (inst.instruction);
11630 inst.instruction |= inst.operands[0].reg << 8;
11631 inst.instruction |= inst.operands[1].reg << 16;
11632 inst.instruction |= inst.operands[2].reg;
11634 /* PR 12854: Error on extraneous shifts. */
11635 constraint (inst.operands[2].shifted,
11636 _("extraneous shift as part of operand to shift insn"));
11640 inst.operands[1].shifted = 1;
11641 inst.operands[1].shift_kind = shift_kind;
11642 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11643 ? T_MNEM_movs : T_MNEM_mov);
11644 inst.instruction |= inst.operands[0].reg << 8;
11645 encode_thumb32_shifted_operand (1);
11646 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11647 inst.reloc.type = BFD_RELOC_UNUSED;
11652 if (inst.operands[2].isreg)
11654 switch (shift_kind)
11656 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11657 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11658 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11659 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11663 inst.instruction |= inst.operands[0].reg;
11664 inst.instruction |= inst.operands[2].reg << 3;
11666 /* PR 12854: Error on extraneous shifts. */
11667 constraint (inst.operands[2].shifted,
11668 _("extraneous shift as part of operand to shift insn"));
11672 switch (shift_kind)
11674 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11675 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11676 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11679 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11680 inst.instruction |= inst.operands[0].reg;
11681 inst.instruction |= inst.operands[1].reg << 3;
11687 constraint (inst.operands[0].reg > 7
11688 || inst.operands[1].reg > 7, BAD_HIREG);
11689 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11691 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11693 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11694 constraint (inst.operands[0].reg != inst.operands[1].reg,
11695 _("source1 and dest must be same register"));
11697 switch (inst.instruction)
11699 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11700 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11701 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11702 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11706 inst.instruction |= inst.operands[0].reg;
11707 inst.instruction |= inst.operands[2].reg << 3;
11709 /* PR 12854: Error on extraneous shifts. */
11710 constraint (inst.operands[2].shifted,
11711 _("extraneous shift as part of operand to shift insn"));
11715 switch (inst.instruction)
11717 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11718 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11719 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11720 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11723 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11724 inst.instruction |= inst.operands[0].reg;
11725 inst.instruction |= inst.operands[1].reg << 3;
11733 unsigned Rd, Rn, Rm;
11735 Rd = inst.operands[0].reg;
11736 Rn = inst.operands[1].reg;
11737 Rm = inst.operands[2].reg;
11739 reject_bad_reg (Rd);
11740 reject_bad_reg (Rn);
11741 reject_bad_reg (Rm);
11743 inst.instruction |= Rd << 8;
11744 inst.instruction |= Rn << 16;
11745 inst.instruction |= Rm;
11751 unsigned Rd, Rn, Rm;
11753 Rd = inst.operands[0].reg;
11754 Rm = inst.operands[1].reg;
11755 Rn = inst.operands[2].reg;
11757 reject_bad_reg (Rd);
11758 reject_bad_reg (Rn);
11759 reject_bad_reg (Rm);
11761 inst.instruction |= Rd << 8;
11762 inst.instruction |= Rn << 16;
11763 inst.instruction |= Rm;
11769 unsigned int value = inst.reloc.exp.X_add_number;
11770 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11771 _("SMC is not permitted on this architecture"));
11772 constraint (inst.reloc.exp.X_op != O_constant,
11773 _("expression too complex"));
11774 inst.reloc.type = BFD_RELOC_UNUSED;
11775 inst.instruction |= (value & 0xf000) >> 12;
11776 inst.instruction |= (value & 0x0ff0);
11777 inst.instruction |= (value & 0x000f) << 16;
11783 unsigned int value = inst.reloc.exp.X_add_number;
11785 inst.reloc.type = BFD_RELOC_UNUSED;
11786 inst.instruction |= (value & 0x0fff);
11787 inst.instruction |= (value & 0xf000) << 4;
11791 do_t_ssat_usat (int bias)
11795 Rd = inst.operands[0].reg;
11796 Rn = inst.operands[2].reg;
11798 reject_bad_reg (Rd);
11799 reject_bad_reg (Rn);
11801 inst.instruction |= Rd << 8;
11802 inst.instruction |= inst.operands[1].imm - bias;
11803 inst.instruction |= Rn << 16;
11805 if (inst.operands[3].present)
11807 offsetT shift_amount = inst.reloc.exp.X_add_number;
11809 inst.reloc.type = BFD_RELOC_UNUSED;
11811 constraint (inst.reloc.exp.X_op != O_constant,
11812 _("expression too complex"));
11814 if (shift_amount != 0)
11816 constraint (shift_amount > 31,
11817 _("shift expression is too large"));
11819 if (inst.operands[3].shift_kind == SHIFT_ASR)
11820 inst.instruction |= 0x00200000; /* sh bit. */
11822 inst.instruction |= (shift_amount & 0x1c) << 10;
11823 inst.instruction |= (shift_amount & 0x03) << 6;
11831 do_t_ssat_usat (1);
11839 Rd = inst.operands[0].reg;
11840 Rn = inst.operands[2].reg;
11842 reject_bad_reg (Rd);
11843 reject_bad_reg (Rn);
11845 inst.instruction |= Rd << 8;
11846 inst.instruction |= inst.operands[1].imm - 1;
11847 inst.instruction |= Rn << 16;
11853 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11854 || inst.operands[2].postind || inst.operands[2].writeback
11855 || inst.operands[2].immisreg || inst.operands[2].shifted
11856 || inst.operands[2].negative,
11859 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11861 inst.instruction |= inst.operands[0].reg << 8;
11862 inst.instruction |= inst.operands[1].reg << 12;
11863 inst.instruction |= inst.operands[2].reg << 16;
11864 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11870 if (!inst.operands[2].present)
11871 inst.operands[2].reg = inst.operands[1].reg + 1;
11873 constraint (inst.operands[0].reg == inst.operands[1].reg
11874 || inst.operands[0].reg == inst.operands[2].reg
11875 || inst.operands[0].reg == inst.operands[3].reg,
11878 inst.instruction |= inst.operands[0].reg;
11879 inst.instruction |= inst.operands[1].reg << 12;
11880 inst.instruction |= inst.operands[2].reg << 8;
11881 inst.instruction |= inst.operands[3].reg << 16;
11887 unsigned Rd, Rn, Rm;
11889 Rd = inst.operands[0].reg;
11890 Rn = inst.operands[1].reg;
11891 Rm = inst.operands[2].reg;
11893 reject_bad_reg (Rd);
11894 reject_bad_reg (Rn);
11895 reject_bad_reg (Rm);
11897 inst.instruction |= Rd << 8;
11898 inst.instruction |= Rn << 16;
11899 inst.instruction |= Rm;
11900 inst.instruction |= inst.operands[3].imm << 4;
11908 Rd = inst.operands[0].reg;
11909 Rm = inst.operands[1].reg;
11911 reject_bad_reg (Rd);
11912 reject_bad_reg (Rm);
11914 if (inst.instruction <= 0xffff
11915 && inst.size_req != 4
11916 && Rd <= 7 && Rm <= 7
11917 && (!inst.operands[2].present || inst.operands[2].imm == 0))
11919 inst.instruction = THUMB_OP16 (inst.instruction);
11920 inst.instruction |= Rd;
11921 inst.instruction |= Rm << 3;
11923 else if (unified_syntax)
11925 if (inst.instruction <= 0xffff)
11926 inst.instruction = THUMB_OP32 (inst.instruction);
11927 inst.instruction |= Rd << 8;
11928 inst.instruction |= Rm;
11929 inst.instruction |= inst.operands[2].imm << 4;
11933 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
11934 _("Thumb encoding does not support rotation"));
11935 constraint (1, BAD_HIREG);
11942 /* We have to do the following check manually as ARM_EXT_OS only applies
11944 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
11946 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
11947 /* This only applies to the v6m howver, not later architectures. */
11948 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
11949 as_bad (_("SVC is not permitted on this architecture"));
11950 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
11953 inst.reloc.type = BFD_RELOC_ARM_SWI;
11962 half = (inst.instruction & 0x10) != 0;
11963 set_it_insn_type_last ();
11964 constraint (inst.operands[0].immisreg,
11965 _("instruction requires register index"));
11967 Rn = inst.operands[0].reg;
11968 Rm = inst.operands[0].imm;
11970 constraint (Rn == REG_SP, BAD_SP);
11971 reject_bad_reg (Rm);
11973 constraint (!half && inst.operands[0].shifted,
11974 _("instruction does not allow shifted index"));
11975 inst.instruction |= (Rn << 16) | Rm;
11981 do_t_ssat_usat (0);
11989 Rd = inst.operands[0].reg;
11990 Rn = inst.operands[2].reg;
11992 reject_bad_reg (Rd);
11993 reject_bad_reg (Rn);
11995 inst.instruction |= Rd << 8;
11996 inst.instruction |= inst.operands[1].imm;
11997 inst.instruction |= Rn << 16;
12000 /* Neon instruction encoder helpers. */
12002 /* Encodings for the different types for various Neon opcodes. */
12004 /* An "invalid" code for the following tables. */
12007 struct neon_tab_entry
12010 unsigned float_or_poly;
12011 unsigned scalar_or_imm;
12014 /* Map overloaded Neon opcodes to their respective encodings. */
12015 #define NEON_ENC_TAB \
12016 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12017 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12018 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12019 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12020 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12021 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12022 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12023 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12024 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12025 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12026 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12027 /* Register variants of the following two instructions are encoded as
12028 vcge / vcgt with the operands reversed. */ \
12029 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12030 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12031 X(vfma, N_INV, 0x0000c10, N_INV), \
12032 X(vfms, N_INV, 0x0200c10, N_INV), \
12033 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12034 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12035 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12036 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12037 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12038 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12039 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12040 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12041 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12042 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12043 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12044 X(vshl, 0x0000400, N_INV, 0x0800510), \
12045 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12046 X(vand, 0x0000110, N_INV, 0x0800030), \
12047 X(vbic, 0x0100110, N_INV, 0x0800030), \
12048 X(veor, 0x1000110, N_INV, N_INV), \
12049 X(vorn, 0x0300110, N_INV, 0x0800010), \
12050 X(vorr, 0x0200110, N_INV, 0x0800010), \
12051 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12052 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12053 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12054 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12055 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12056 X(vst1, 0x0000000, 0x0800000, N_INV), \
12057 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12058 X(vst2, 0x0000100, 0x0800100, N_INV), \
12059 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12060 X(vst3, 0x0000200, 0x0800200, N_INV), \
12061 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12062 X(vst4, 0x0000300, 0x0800300, N_INV), \
12063 X(vmovn, 0x1b20200, N_INV, N_INV), \
12064 X(vtrn, 0x1b20080, N_INV, N_INV), \
12065 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12066 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12067 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12068 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12069 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12070 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12071 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12072 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12073 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12074 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12075 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12079 #define X(OPC,I,F,S) N_MNEM_##OPC
12084 static const struct neon_tab_entry neon_enc_tab[] =
12086 #define X(OPC,I,F,S) { (I), (F), (S) }
12091 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12092 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12093 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12094 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12095 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12096 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12097 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12098 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12099 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12100 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12101 #define NEON_ENC_SINGLE_(X) \
12102 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12103 #define NEON_ENC_DOUBLE_(X) \
12104 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12106 #define NEON_ENCODE(type, inst) \
12109 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12110 inst.is_neon = 1; \
12114 #define check_neon_suffixes \
12117 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12119 as_bad (_("invalid neon suffix for non neon instruction")); \
12125 /* Define shapes for instruction operands. The following mnemonic characters
12126 are used in this table:
12128 F - VFP S<n> register
12129 D - Neon D<n> register
12130 Q - Neon Q<n> register
12134 L - D<n> register list
12136 This table is used to generate various data:
12137 - enumerations of the form NS_DDR to be used as arguments to
12139 - a table classifying shapes into single, double, quad, mixed.
12140 - a table used to drive neon_select_shape. */
12142 #define NEON_SHAPE_DEF \
12143 X(3, (D, D, D), DOUBLE), \
12144 X(3, (Q, Q, Q), QUAD), \
12145 X(3, (D, D, I), DOUBLE), \
12146 X(3, (Q, Q, I), QUAD), \
12147 X(3, (D, D, S), DOUBLE), \
12148 X(3, (Q, Q, S), QUAD), \
12149 X(2, (D, D), DOUBLE), \
12150 X(2, (Q, Q), QUAD), \
12151 X(2, (D, S), DOUBLE), \
12152 X(2, (Q, S), QUAD), \
12153 X(2, (D, R), DOUBLE), \
12154 X(2, (Q, R), QUAD), \
12155 X(2, (D, I), DOUBLE), \
12156 X(2, (Q, I), QUAD), \
12157 X(3, (D, L, D), DOUBLE), \
12158 X(2, (D, Q), MIXED), \
12159 X(2, (Q, D), MIXED), \
12160 X(3, (D, Q, I), MIXED), \
12161 X(3, (Q, D, I), MIXED), \
12162 X(3, (Q, D, D), MIXED), \
12163 X(3, (D, Q, Q), MIXED), \
12164 X(3, (Q, Q, D), MIXED), \
12165 X(3, (Q, D, S), MIXED), \
12166 X(3, (D, Q, S), MIXED), \
12167 X(4, (D, D, D, I), DOUBLE), \
12168 X(4, (Q, Q, Q, I), QUAD), \
12169 X(2, (F, F), SINGLE), \
12170 X(3, (F, F, F), SINGLE), \
12171 X(2, (F, I), SINGLE), \
12172 X(2, (F, D), MIXED), \
12173 X(2, (D, F), MIXED), \
12174 X(3, (F, F, I), MIXED), \
12175 X(4, (R, R, F, F), SINGLE), \
12176 X(4, (F, F, R, R), SINGLE), \
12177 X(3, (D, R, R), DOUBLE), \
12178 X(3, (R, R, D), DOUBLE), \
12179 X(2, (S, R), SINGLE), \
12180 X(2, (R, S), SINGLE), \
12181 X(2, (F, R), SINGLE), \
12182 X(2, (R, F), SINGLE)
12184 #define S2(A,B) NS_##A##B
12185 #define S3(A,B,C) NS_##A##B##C
12186 #define S4(A,B,C,D) NS_##A##B##C##D
12188 #define X(N, L, C) S##N L
12201 enum neon_shape_class
12209 #define X(N, L, C) SC_##C
12211 static enum neon_shape_class neon_shape_class[] =
12229 /* Register widths of above. */
12230 static unsigned neon_shape_el_size[] =
12241 struct neon_shape_info
12244 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12247 #define S2(A,B) { SE_##A, SE_##B }
12248 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12249 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12251 #define X(N, L, C) { N, S##N L }
12253 static struct neon_shape_info neon_shape_tab[] =
12263 /* Bit masks used in type checking given instructions.
12264 'N_EQK' means the type must be the same as (or based on in some way) the key
12265 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12266 set, various other bits can be set as well in order to modify the meaning of
12267 the type constraint. */
12269 enum neon_type_mask
12292 N_KEY = 0x1000000, /* Key element (main type specifier). */
12293 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12294 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12295 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12296 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12297 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12298 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12299 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12300 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12301 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12303 N_MAX_NONSPECIAL = N_F64
12306 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12308 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12309 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12310 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12311 #define N_SUF_32 (N_SU_32 | N_F32)
12312 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12313 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12315 /* Pass this as the first type argument to neon_check_type to ignore types
12317 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12319 /* Select a "shape" for the current instruction (describing register types or
12320 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12321 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12322 function of operand parsing, so this function doesn't need to be called.
12323 Shapes should be listed in order of decreasing length. */
12325 static enum neon_shape
12326 neon_select_shape (enum neon_shape shape, ...)
12329 enum neon_shape first_shape = shape;
12331 /* Fix missing optional operands. FIXME: we don't know at this point how
12332 many arguments we should have, so this makes the assumption that we have
12333 > 1. This is true of all current Neon opcodes, I think, but may not be
12334 true in the future. */
12335 if (!inst.operands[1].present)
12336 inst.operands[1] = inst.operands[0];
12338 va_start (ap, shape);
12340 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12345 for (j = 0; j < neon_shape_tab[shape].els; j++)
12347 if (!inst.operands[j].present)
12353 switch (neon_shape_tab[shape].el[j])
12356 if (!(inst.operands[j].isreg
12357 && inst.operands[j].isvec
12358 && inst.operands[j].issingle
12359 && !inst.operands[j].isquad))
12364 if (!(inst.operands[j].isreg
12365 && inst.operands[j].isvec
12366 && !inst.operands[j].isquad
12367 && !inst.operands[j].issingle))
12372 if (!(inst.operands[j].isreg
12373 && !inst.operands[j].isvec))
12378 if (!(inst.operands[j].isreg
12379 && inst.operands[j].isvec
12380 && inst.operands[j].isquad
12381 && !inst.operands[j].issingle))
12386 if (!(!inst.operands[j].isreg
12387 && !inst.operands[j].isscalar))
12392 if (!(!inst.operands[j].isreg
12393 && inst.operands[j].isscalar))
12409 if (shape == NS_NULL && first_shape != NS_NULL)
12410 first_error (_("invalid instruction shape"));
12415 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12416 means the Q bit should be set). */
12419 neon_quad (enum neon_shape shape)
12421 return neon_shape_class[shape] == SC_QUAD;
12425 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12428 /* Allow modification to be made to types which are constrained to be
12429 based on the key element, based on bits set alongside N_EQK. */
12430 if ((typebits & N_EQK) != 0)
12432 if ((typebits & N_HLF) != 0)
12434 else if ((typebits & N_DBL) != 0)
12436 if ((typebits & N_SGN) != 0)
12437 *g_type = NT_signed;
12438 else if ((typebits & N_UNS) != 0)
12439 *g_type = NT_unsigned;
12440 else if ((typebits & N_INT) != 0)
12441 *g_type = NT_integer;
12442 else if ((typebits & N_FLT) != 0)
12443 *g_type = NT_float;
12444 else if ((typebits & N_SIZ) != 0)
12445 *g_type = NT_untyped;
12449 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12450 operand type, i.e. the single type specified in a Neon instruction when it
12451 is the only one given. */
12453 static struct neon_type_el
12454 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12456 struct neon_type_el dest = *key;
12458 gas_assert ((thisarg & N_EQK) != 0);
12460 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12465 /* Convert Neon type and size into compact bitmask representation. */
12467 static enum neon_type_mask
12468 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12475 case 8: return N_8;
12476 case 16: return N_16;
12477 case 32: return N_32;
12478 case 64: return N_64;
12486 case 8: return N_I8;
12487 case 16: return N_I16;
12488 case 32: return N_I32;
12489 case 64: return N_I64;
12497 case 16: return N_F16;
12498 case 32: return N_F32;
12499 case 64: return N_F64;
12507 case 8: return N_P8;
12508 case 16: return N_P16;
12516 case 8: return N_S8;
12517 case 16: return N_S16;
12518 case 32: return N_S32;
12519 case 64: return N_S64;
12527 case 8: return N_U8;
12528 case 16: return N_U16;
12529 case 32: return N_U32;
12530 case 64: return N_U64;
12541 /* Convert compact Neon bitmask type representation to a type and size. Only
12542 handles the case where a single bit is set in the mask. */
12545 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12546 enum neon_type_mask mask)
12548 if ((mask & N_EQK) != 0)
12551 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12553 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12555 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12557 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12562 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12564 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12565 *type = NT_unsigned;
12566 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12567 *type = NT_integer;
12568 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12569 *type = NT_untyped;
12570 else if ((mask & (N_P8 | N_P16)) != 0)
12572 else if ((mask & (N_F32 | N_F64)) != 0)
12580 /* Modify a bitmask of allowed types. This is only needed for type
12584 modify_types_allowed (unsigned allowed, unsigned mods)
12587 enum neon_el_type type;
12593 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12595 if (el_type_of_type_chk (&type, &size,
12596 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12598 neon_modify_type_size (mods, &type, &size);
12599 destmask |= type_chk_of_el_type (type, size);
12606 /* Check type and return type classification.
12607 The manual states (paraphrase): If one datatype is given, it indicates the
12609 - the second operand, if there is one
12610 - the operand, if there is no second operand
12611 - the result, if there are no operands.
12612 This isn't quite good enough though, so we use a concept of a "key" datatype
12613 which is set on a per-instruction basis, which is the one which matters when
12614 only one data type is written.
12615 Note: this function has side-effects (e.g. filling in missing operands). All
12616 Neon instructions should call it before performing bit encoding. */
12618 static struct neon_type_el
12619 neon_check_type (unsigned els, enum neon_shape ns, ...)
12622 unsigned i, pass, key_el = 0;
12623 unsigned types[NEON_MAX_TYPE_ELS];
12624 enum neon_el_type k_type = NT_invtype;
12625 unsigned k_size = -1u;
12626 struct neon_type_el badtype = {NT_invtype, -1};
12627 unsigned key_allowed = 0;
12629 /* Optional registers in Neon instructions are always (not) in operand 1.
12630 Fill in the missing operand here, if it was omitted. */
12631 if (els > 1 && !inst.operands[1].present)
12632 inst.operands[1] = inst.operands[0];
12634 /* Suck up all the varargs. */
12636 for (i = 0; i < els; i++)
12638 unsigned thisarg = va_arg (ap, unsigned);
12639 if (thisarg == N_IGNORE_TYPE)
12644 types[i] = thisarg;
12645 if ((thisarg & N_KEY) != 0)
12650 if (inst.vectype.elems > 0)
12651 for (i = 0; i < els; i++)
12652 if (inst.operands[i].vectype.type != NT_invtype)
12654 first_error (_("types specified in both the mnemonic and operands"));
12658 /* Duplicate inst.vectype elements here as necessary.
12659 FIXME: No idea if this is exactly the same as the ARM assembler,
12660 particularly when an insn takes one register and one non-register
12662 if (inst.vectype.elems == 1 && els > 1)
12665 inst.vectype.elems = els;
12666 inst.vectype.el[key_el] = inst.vectype.el[0];
12667 for (j = 0; j < els; j++)
12669 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12672 else if (inst.vectype.elems == 0 && els > 0)
12675 /* No types were given after the mnemonic, so look for types specified
12676 after each operand. We allow some flexibility here; as long as the
12677 "key" operand has a type, we can infer the others. */
12678 for (j = 0; j < els; j++)
12679 if (inst.operands[j].vectype.type != NT_invtype)
12680 inst.vectype.el[j] = inst.operands[j].vectype;
12682 if (inst.operands[key_el].vectype.type != NT_invtype)
12684 for (j = 0; j < els; j++)
12685 if (inst.operands[j].vectype.type == NT_invtype)
12686 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12691 first_error (_("operand types can't be inferred"));
12695 else if (inst.vectype.elems != els)
12697 first_error (_("type specifier has the wrong number of parts"));
12701 for (pass = 0; pass < 2; pass++)
12703 for (i = 0; i < els; i++)
12705 unsigned thisarg = types[i];
12706 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12707 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12708 enum neon_el_type g_type = inst.vectype.el[i].type;
12709 unsigned g_size = inst.vectype.el[i].size;
12711 /* Decay more-specific signed & unsigned types to sign-insensitive
12712 integer types if sign-specific variants are unavailable. */
12713 if ((g_type == NT_signed || g_type == NT_unsigned)
12714 && (types_allowed & N_SU_ALL) == 0)
12715 g_type = NT_integer;
12717 /* If only untyped args are allowed, decay any more specific types to
12718 them. Some instructions only care about signs for some element
12719 sizes, so handle that properly. */
12720 if ((g_size == 8 && (types_allowed & N_8) != 0)
12721 || (g_size == 16 && (types_allowed & N_16) != 0)
12722 || (g_size == 32 && (types_allowed & N_32) != 0)
12723 || (g_size == 64 && (types_allowed & N_64) != 0))
12724 g_type = NT_untyped;
12728 if ((thisarg & N_KEY) != 0)
12732 key_allowed = thisarg & ~N_KEY;
12737 if ((thisarg & N_VFP) != 0)
12739 enum neon_shape_el regshape;
12740 unsigned regwidth, match;
12742 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12745 first_error (_("invalid instruction shape"));
12748 regshape = neon_shape_tab[ns].el[i];
12749 regwidth = neon_shape_el_size[regshape];
12751 /* In VFP mode, operands must match register widths. If we
12752 have a key operand, use its width, else use the width of
12753 the current operand. */
12759 if (regwidth != match)
12761 first_error (_("operand size must match register width"));
12766 if ((thisarg & N_EQK) == 0)
12768 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12770 if ((given_type & types_allowed) == 0)
12772 first_error (_("bad type in Neon instruction"));
12778 enum neon_el_type mod_k_type = k_type;
12779 unsigned mod_k_size = k_size;
12780 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12781 if (g_type != mod_k_type || g_size != mod_k_size)
12783 first_error (_("inconsistent types in Neon instruction"));
12791 return inst.vectype.el[key_el];
12794 /* Neon-style VFP instruction forwarding. */
12796 /* Thumb VFP instructions have 0xE in the condition field. */
12799 do_vfp_cond_or_thumb (void)
12804 inst.instruction |= 0xe0000000;
12806 inst.instruction |= inst.cond << 28;
12809 /* Look up and encode a simple mnemonic, for use as a helper function for the
12810 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12811 etc. It is assumed that operand parsing has already been done, and that the
12812 operands are in the form expected by the given opcode (this isn't necessarily
12813 the same as the form in which they were parsed, hence some massaging must
12814 take place before this function is called).
12815 Checks current arch version against that in the looked-up opcode. */
12818 do_vfp_nsyn_opcode (const char *opname)
12820 const struct asm_opcode *opcode;
12822 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12827 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12828 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12835 inst.instruction = opcode->tvalue;
12836 opcode->tencode ();
12840 inst.instruction = (inst.cond << 28) | opcode->avalue;
12841 opcode->aencode ();
12846 do_vfp_nsyn_add_sub (enum neon_shape rs)
12848 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12853 do_vfp_nsyn_opcode ("fadds");
12855 do_vfp_nsyn_opcode ("fsubs");
12860 do_vfp_nsyn_opcode ("faddd");
12862 do_vfp_nsyn_opcode ("fsubd");
12866 /* Check operand types to see if this is a VFP instruction, and if so call
12870 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12872 enum neon_shape rs;
12873 struct neon_type_el et;
12878 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12879 et = neon_check_type (2, rs,
12880 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12884 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12885 et = neon_check_type (3, rs,
12886 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12893 if (et.type != NT_invtype)
12904 do_vfp_nsyn_mla_mls (enum neon_shape rs)
12906 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
12911 do_vfp_nsyn_opcode ("fmacs");
12913 do_vfp_nsyn_opcode ("fnmacs");
12918 do_vfp_nsyn_opcode ("fmacd");
12920 do_vfp_nsyn_opcode ("fnmacd");
12925 do_vfp_nsyn_fma_fms (enum neon_shape rs)
12927 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
12932 do_vfp_nsyn_opcode ("ffmas");
12934 do_vfp_nsyn_opcode ("ffnmas");
12939 do_vfp_nsyn_opcode ("ffmad");
12941 do_vfp_nsyn_opcode ("ffnmad");
12946 do_vfp_nsyn_mul (enum neon_shape rs)
12949 do_vfp_nsyn_opcode ("fmuls");
12951 do_vfp_nsyn_opcode ("fmuld");
12955 do_vfp_nsyn_abs_neg (enum neon_shape rs)
12957 int is_neg = (inst.instruction & 0x80) != 0;
12958 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
12963 do_vfp_nsyn_opcode ("fnegs");
12965 do_vfp_nsyn_opcode ("fabss");
12970 do_vfp_nsyn_opcode ("fnegd");
12972 do_vfp_nsyn_opcode ("fabsd");
12976 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12977 insns belong to Neon, and are handled elsewhere. */
12980 do_vfp_nsyn_ldm_stm (int is_dbmode)
12982 int is_ldm = (inst.instruction & (1 << 20)) != 0;
12986 do_vfp_nsyn_opcode ("fldmdbs");
12988 do_vfp_nsyn_opcode ("fldmias");
12993 do_vfp_nsyn_opcode ("fstmdbs");
12995 do_vfp_nsyn_opcode ("fstmias");
13000 do_vfp_nsyn_sqrt (void)
13002 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13003 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13006 do_vfp_nsyn_opcode ("fsqrts");
13008 do_vfp_nsyn_opcode ("fsqrtd");
13012 do_vfp_nsyn_div (void)
13014 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13015 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13016 N_F32 | N_F64 | N_KEY | N_VFP);
13019 do_vfp_nsyn_opcode ("fdivs");
13021 do_vfp_nsyn_opcode ("fdivd");
13025 do_vfp_nsyn_nmul (void)
13027 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13028 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13029 N_F32 | N_F64 | N_KEY | N_VFP);
13033 NEON_ENCODE (SINGLE, inst);
13034 do_vfp_sp_dyadic ();
13038 NEON_ENCODE (DOUBLE, inst);
13039 do_vfp_dp_rd_rn_rm ();
13041 do_vfp_cond_or_thumb ();
13045 do_vfp_nsyn_cmp (void)
13047 if (inst.operands[1].isreg)
13049 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13050 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13054 NEON_ENCODE (SINGLE, inst);
13055 do_vfp_sp_monadic ();
13059 NEON_ENCODE (DOUBLE, inst);
13060 do_vfp_dp_rd_rm ();
13065 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13066 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13068 switch (inst.instruction & 0x0fffffff)
13071 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13074 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13082 NEON_ENCODE (SINGLE, inst);
13083 do_vfp_sp_compare_z ();
13087 NEON_ENCODE (DOUBLE, inst);
13091 do_vfp_cond_or_thumb ();
13095 nsyn_insert_sp (void)
13097 inst.operands[1] = inst.operands[0];
13098 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13099 inst.operands[0].reg = REG_SP;
13100 inst.operands[0].isreg = 1;
13101 inst.operands[0].writeback = 1;
13102 inst.operands[0].present = 1;
13106 do_vfp_nsyn_push (void)
13109 if (inst.operands[1].issingle)
13110 do_vfp_nsyn_opcode ("fstmdbs");
13112 do_vfp_nsyn_opcode ("fstmdbd");
13116 do_vfp_nsyn_pop (void)
13119 if (inst.operands[1].issingle)
13120 do_vfp_nsyn_opcode ("fldmias");
13122 do_vfp_nsyn_opcode ("fldmiad");
13125 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13126 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13129 neon_dp_fixup (struct arm_it* insn)
13131 unsigned int i = insn->instruction;
13136 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13147 insn->instruction = i;
13150 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13154 neon_logbits (unsigned x)
13156 return ffs (x) - 4;
13159 #define LOW4(R) ((R) & 0xf)
13160 #define HI1(R) (((R) >> 4) & 1)
13162 /* Encode insns with bit pattern:
13164 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13165 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13167 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13168 different meaning for some instruction. */
13171 neon_three_same (int isquad, int ubit, int size)
13173 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13174 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13175 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13176 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13177 inst.instruction |= LOW4 (inst.operands[2].reg);
13178 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13179 inst.instruction |= (isquad != 0) << 6;
13180 inst.instruction |= (ubit != 0) << 24;
13182 inst.instruction |= neon_logbits (size) << 20;
13184 neon_dp_fixup (&inst);
13187 /* Encode instructions of the form:
13189 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13190 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13192 Don't write size if SIZE == -1. */
13195 neon_two_same (int qbit, int ubit, int size)
13197 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13198 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13199 inst.instruction |= LOW4 (inst.operands[1].reg);
13200 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13201 inst.instruction |= (qbit != 0) << 6;
13202 inst.instruction |= (ubit != 0) << 24;
13205 inst.instruction |= neon_logbits (size) << 18;
13207 neon_dp_fixup (&inst);
13210 /* Neon instruction encoders, in approximate order of appearance. */
13213 do_neon_dyadic_i_su (void)
13215 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13216 struct neon_type_el et = neon_check_type (3, rs,
13217 N_EQK, N_EQK, N_SU_32 | N_KEY);
13218 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13222 do_neon_dyadic_i64_su (void)
13224 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13225 struct neon_type_el et = neon_check_type (3, rs,
13226 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13227 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13231 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13234 unsigned size = et.size >> 3;
13235 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13236 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13237 inst.instruction |= LOW4 (inst.operands[1].reg);
13238 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13239 inst.instruction |= (isquad != 0) << 6;
13240 inst.instruction |= immbits << 16;
13241 inst.instruction |= (size >> 3) << 7;
13242 inst.instruction |= (size & 0x7) << 19;
13244 inst.instruction |= (uval != 0) << 24;
13246 neon_dp_fixup (&inst);
13250 do_neon_shl_imm (void)
13252 if (!inst.operands[2].isreg)
13254 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13255 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13256 NEON_ENCODE (IMMED, inst);
13257 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13261 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13262 struct neon_type_el et = neon_check_type (3, rs,
13263 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13266 /* VSHL/VQSHL 3-register variants have syntax such as:
13268 whereas other 3-register operations encoded by neon_three_same have
13271 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13273 tmp = inst.operands[2].reg;
13274 inst.operands[2].reg = inst.operands[1].reg;
13275 inst.operands[1].reg = tmp;
13276 NEON_ENCODE (INTEGER, inst);
13277 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13282 do_neon_qshl_imm (void)
13284 if (!inst.operands[2].isreg)
13286 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13287 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13289 NEON_ENCODE (IMMED, inst);
13290 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13291 inst.operands[2].imm);
13295 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13296 struct neon_type_el et = neon_check_type (3, rs,
13297 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13300 /* See note in do_neon_shl_imm. */
13301 tmp = inst.operands[2].reg;
13302 inst.operands[2].reg = inst.operands[1].reg;
13303 inst.operands[1].reg = tmp;
13304 NEON_ENCODE (INTEGER, inst);
13305 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13310 do_neon_rshl (void)
13312 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13313 struct neon_type_el et = neon_check_type (3, rs,
13314 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13317 tmp = inst.operands[2].reg;
13318 inst.operands[2].reg = inst.operands[1].reg;
13319 inst.operands[1].reg = tmp;
13320 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13324 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13326 /* Handle .I8 pseudo-instructions. */
13329 /* Unfortunately, this will make everything apart from zero out-of-range.
13330 FIXME is this the intended semantics? There doesn't seem much point in
13331 accepting .I8 if so. */
13332 immediate |= immediate << 8;
13338 if (immediate == (immediate & 0x000000ff))
13340 *immbits = immediate;
13343 else if (immediate == (immediate & 0x0000ff00))
13345 *immbits = immediate >> 8;
13348 else if (immediate == (immediate & 0x00ff0000))
13350 *immbits = immediate >> 16;
13353 else if (immediate == (immediate & 0xff000000))
13355 *immbits = immediate >> 24;
13358 if ((immediate & 0xffff) != (immediate >> 16))
13359 goto bad_immediate;
13360 immediate &= 0xffff;
13363 if (immediate == (immediate & 0x000000ff))
13365 *immbits = immediate;
13368 else if (immediate == (immediate & 0x0000ff00))
13370 *immbits = immediate >> 8;
13375 first_error (_("immediate value out of range"));
13379 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13383 neon_bits_same_in_bytes (unsigned imm)
13385 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13386 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13387 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13388 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13391 /* For immediate of above form, return 0bABCD. */
13394 neon_squash_bits (unsigned imm)
13396 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13397 | ((imm & 0x01000000) >> 21);
13400 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13403 neon_qfloat_bits (unsigned imm)
13405 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13408 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13409 the instruction. *OP is passed as the initial value of the op field, and
13410 may be set to a different value depending on the constant (i.e.
13411 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13412 MVN). If the immediate looks like a repeated pattern then also
13413 try smaller element sizes. */
13416 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13417 unsigned *immbits, int *op, int size,
13418 enum neon_el_type type)
13420 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13422 if (type == NT_float && !float_p)
13425 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13427 if (size != 32 || *op == 1)
13429 *immbits = neon_qfloat_bits (immlo);
13435 if (neon_bits_same_in_bytes (immhi)
13436 && neon_bits_same_in_bytes (immlo))
13440 *immbits = (neon_squash_bits (immhi) << 4)
13441 | neon_squash_bits (immlo);
13446 if (immhi != immlo)
13452 if (immlo == (immlo & 0x000000ff))
13457 else if (immlo == (immlo & 0x0000ff00))
13459 *immbits = immlo >> 8;
13462 else if (immlo == (immlo & 0x00ff0000))
13464 *immbits = immlo >> 16;
13467 else if (immlo == (immlo & 0xff000000))
13469 *immbits = immlo >> 24;
13472 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13474 *immbits = (immlo >> 8) & 0xff;
13477 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13479 *immbits = (immlo >> 16) & 0xff;
13483 if ((immlo & 0xffff) != (immlo >> 16))
13490 if (immlo == (immlo & 0x000000ff))
13495 else if (immlo == (immlo & 0x0000ff00))
13497 *immbits = immlo >> 8;
13501 if ((immlo & 0xff) != (immlo >> 8))
13506 if (immlo == (immlo & 0x000000ff))
13508 /* Don't allow MVN with 8-bit immediate. */
13518 /* Write immediate bits [7:0] to the following locations:
13520 |28/24|23 19|18 16|15 4|3 0|
13521 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13523 This function is used by VMOV/VMVN/VORR/VBIC. */
13526 neon_write_immbits (unsigned immbits)
13528 inst.instruction |= immbits & 0xf;
13529 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13530 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13533 /* Invert low-order SIZE bits of XHI:XLO. */
13536 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13538 unsigned immlo = xlo ? *xlo : 0;
13539 unsigned immhi = xhi ? *xhi : 0;
13544 immlo = (~immlo) & 0xff;
13548 immlo = (~immlo) & 0xffff;
13552 immhi = (~immhi) & 0xffffffff;
13553 /* fall through. */
13556 immlo = (~immlo) & 0xffffffff;
13571 do_neon_logic (void)
13573 if (inst.operands[2].present && inst.operands[2].isreg)
13575 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13576 neon_check_type (3, rs, N_IGNORE_TYPE);
13577 /* U bit and size field were set as part of the bitmask. */
13578 NEON_ENCODE (INTEGER, inst);
13579 neon_three_same (neon_quad (rs), 0, -1);
13583 const int three_ops_form = (inst.operands[2].present
13584 && !inst.operands[2].isreg);
13585 const int immoperand = (three_ops_form ? 2 : 1);
13586 enum neon_shape rs = (three_ops_form
13587 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13588 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13589 struct neon_type_el et = neon_check_type (2, rs,
13590 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13591 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13595 if (et.type == NT_invtype)
13598 if (three_ops_form)
13599 constraint (inst.operands[0].reg != inst.operands[1].reg,
13600 _("first and second operands shall be the same register"));
13602 NEON_ENCODE (IMMED, inst);
13604 immbits = inst.operands[immoperand].imm;
13607 /* .i64 is a pseudo-op, so the immediate must be a repeating
13609 if (immbits != (inst.operands[immoperand].regisimm ?
13610 inst.operands[immoperand].reg : 0))
13612 /* Set immbits to an invalid constant. */
13613 immbits = 0xdeadbeef;
13620 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13624 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13628 /* Pseudo-instruction for VBIC. */
13629 neon_invert_size (&immbits, 0, et.size);
13630 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13634 /* Pseudo-instruction for VORR. */
13635 neon_invert_size (&immbits, 0, et.size);
13636 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13646 inst.instruction |= neon_quad (rs) << 6;
13647 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13648 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13649 inst.instruction |= cmode << 8;
13650 neon_write_immbits (immbits);
13652 neon_dp_fixup (&inst);
13657 do_neon_bitfield (void)
13659 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13660 neon_check_type (3, rs, N_IGNORE_TYPE);
13661 neon_three_same (neon_quad (rs), 0, -1);
13665 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13668 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13669 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13671 if (et.type == NT_float)
13673 NEON_ENCODE (FLOAT, inst);
13674 neon_three_same (neon_quad (rs), 0, -1);
13678 NEON_ENCODE (INTEGER, inst);
13679 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13684 do_neon_dyadic_if_su (void)
13686 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13690 do_neon_dyadic_if_su_d (void)
13692 /* This version only allow D registers, but that constraint is enforced during
13693 operand parsing so we don't need to do anything extra here. */
13694 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13698 do_neon_dyadic_if_i_d (void)
13700 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13701 affected if we specify unsigned args. */
13702 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13705 enum vfp_or_neon_is_neon_bits
13708 NEON_CHECK_ARCH = 2
13711 /* Call this function if an instruction which may have belonged to the VFP or
13712 Neon instruction sets, but turned out to be a Neon instruction (due to the
13713 operand types involved, etc.). We have to check and/or fix-up a couple of
13716 - Make sure the user hasn't attempted to make a Neon instruction
13718 - Alter the value in the condition code field if necessary.
13719 - Make sure that the arch supports Neon instructions.
13721 Which of these operations take place depends on bits from enum
13722 vfp_or_neon_is_neon_bits.
13724 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13725 current instruction's condition is COND_ALWAYS, the condition field is
13726 changed to inst.uncond_value. This is necessary because instructions shared
13727 between VFP and Neon may be conditional for the VFP variants only, and the
13728 unconditional Neon version must have, e.g., 0xF in the condition field. */
13731 vfp_or_neon_is_neon (unsigned check)
13733 /* Conditions are always legal in Thumb mode (IT blocks). */
13734 if (!thumb_mode && (check & NEON_CHECK_CC))
13736 if (inst.cond != COND_ALWAYS)
13738 first_error (_(BAD_COND));
13741 if (inst.uncond_value != -1)
13742 inst.instruction |= inst.uncond_value << 28;
13745 if ((check & NEON_CHECK_ARCH)
13746 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13748 first_error (_(BAD_FPU));
13756 do_neon_addsub_if_i (void)
13758 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13761 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13764 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13765 affected if we specify unsigned args. */
13766 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13769 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13771 V<op> A,B (A is operand 0, B is operand 2)
13776 so handle that case specially. */
13779 neon_exchange_operands (void)
13781 void *scratch = alloca (sizeof (inst.operands[0]));
13782 if (inst.operands[1].present)
13784 /* Swap operands[1] and operands[2]. */
13785 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13786 inst.operands[1] = inst.operands[2];
13787 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13791 inst.operands[1] = inst.operands[2];
13792 inst.operands[2] = inst.operands[0];
13797 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13799 if (inst.operands[2].isreg)
13802 neon_exchange_operands ();
13803 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13807 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13808 struct neon_type_el et = neon_check_type (2, rs,
13809 N_EQK | N_SIZ, immtypes | N_KEY);
13811 NEON_ENCODE (IMMED, inst);
13812 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13813 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13814 inst.instruction |= LOW4 (inst.operands[1].reg);
13815 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13816 inst.instruction |= neon_quad (rs) << 6;
13817 inst.instruction |= (et.type == NT_float) << 10;
13818 inst.instruction |= neon_logbits (et.size) << 18;
13820 neon_dp_fixup (&inst);
13827 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13831 do_neon_cmp_inv (void)
13833 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13839 neon_compare (N_IF_32, N_IF_32, FALSE);
13842 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13843 scalars, which are encoded in 5 bits, M : Rm.
13844 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13845 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13849 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13851 unsigned regno = NEON_SCALAR_REG (scalar);
13852 unsigned elno = NEON_SCALAR_INDEX (scalar);
13857 if (regno > 7 || elno > 3)
13859 return regno | (elno << 3);
13862 if (regno > 15 || elno > 1)
13864 return regno | (elno << 4);
13868 first_error (_("scalar out of range for multiply instruction"));
13874 /* Encode multiply / multiply-accumulate scalar instructions. */
13877 neon_mul_mac (struct neon_type_el et, int ubit)
13881 /* Give a more helpful error message if we have an invalid type. */
13882 if (et.type == NT_invtype)
13885 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
13886 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13887 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13888 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13889 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13890 inst.instruction |= LOW4 (scalar);
13891 inst.instruction |= HI1 (scalar) << 5;
13892 inst.instruction |= (et.type == NT_float) << 8;
13893 inst.instruction |= neon_logbits (et.size) << 20;
13894 inst.instruction |= (ubit != 0) << 24;
13896 neon_dp_fixup (&inst);
13900 do_neon_mac_maybe_scalar (void)
13902 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
13905 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13908 if (inst.operands[2].isscalar)
13910 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13911 struct neon_type_el et = neon_check_type (3, rs,
13912 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
13913 NEON_ENCODE (SCALAR, inst);
13914 neon_mul_mac (et, neon_quad (rs));
13918 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13919 affected if we specify unsigned args. */
13920 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13925 do_neon_fmac (void)
13927 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
13930 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13933 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13939 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13940 struct neon_type_el et = neon_check_type (3, rs,
13941 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
13942 neon_three_same (neon_quad (rs), 0, et.size);
13945 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13946 same types as the MAC equivalents. The polynomial type for this instruction
13947 is encoded the same as the integer type. */
13952 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
13955 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13958 if (inst.operands[2].isscalar)
13959 do_neon_mac_maybe_scalar ();
13961 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
13965 do_neon_qdmulh (void)
13967 if (inst.operands[2].isscalar)
13969 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13970 struct neon_type_el et = neon_check_type (3, rs,
13971 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13972 NEON_ENCODE (SCALAR, inst);
13973 neon_mul_mac (et, neon_quad (rs));
13977 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13978 struct neon_type_el et = neon_check_type (3, rs,
13979 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13980 NEON_ENCODE (INTEGER, inst);
13981 /* The U bit (rounding) comes from bit mask. */
13982 neon_three_same (neon_quad (rs), 0, et.size);
13987 do_neon_fcmp_absolute (void)
13989 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13990 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
13991 /* Size field comes from bit mask. */
13992 neon_three_same (neon_quad (rs), 1, -1);
13996 do_neon_fcmp_absolute_inv (void)
13998 neon_exchange_operands ();
13999 do_neon_fcmp_absolute ();
14003 do_neon_step (void)
14005 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14006 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14007 neon_three_same (neon_quad (rs), 0, -1);
14011 do_neon_abs_neg (void)
14013 enum neon_shape rs;
14014 struct neon_type_el et;
14016 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14019 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14022 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14023 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14025 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14026 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14027 inst.instruction |= LOW4 (inst.operands[1].reg);
14028 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14029 inst.instruction |= neon_quad (rs) << 6;
14030 inst.instruction |= (et.type == NT_float) << 10;
14031 inst.instruction |= neon_logbits (et.size) << 18;
14033 neon_dp_fixup (&inst);
14039 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14040 struct neon_type_el et = neon_check_type (2, rs,
14041 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14042 int imm = inst.operands[2].imm;
14043 constraint (imm < 0 || (unsigned)imm >= et.size,
14044 _("immediate out of range for insert"));
14045 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14051 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14052 struct neon_type_el et = neon_check_type (2, rs,
14053 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14054 int imm = inst.operands[2].imm;
14055 constraint (imm < 1 || (unsigned)imm > et.size,
14056 _("immediate out of range for insert"));
14057 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14061 do_neon_qshlu_imm (void)
14063 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14064 struct neon_type_el et = neon_check_type (2, rs,
14065 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14066 int imm = inst.operands[2].imm;
14067 constraint (imm < 0 || (unsigned)imm >= et.size,
14068 _("immediate out of range for shift"));
14069 /* Only encodes the 'U present' variant of the instruction.
14070 In this case, signed types have OP (bit 8) set to 0.
14071 Unsigned types have OP set to 1. */
14072 inst.instruction |= (et.type == NT_unsigned) << 8;
14073 /* The rest of the bits are the same as other immediate shifts. */
14074 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14078 do_neon_qmovn (void)
14080 struct neon_type_el et = neon_check_type (2, NS_DQ,
14081 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14082 /* Saturating move where operands can be signed or unsigned, and the
14083 destination has the same signedness. */
14084 NEON_ENCODE (INTEGER, inst);
14085 if (et.type == NT_unsigned)
14086 inst.instruction |= 0xc0;
14088 inst.instruction |= 0x80;
14089 neon_two_same (0, 1, et.size / 2);
14093 do_neon_qmovun (void)
14095 struct neon_type_el et = neon_check_type (2, NS_DQ,
14096 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14097 /* Saturating move with unsigned results. Operands must be signed. */
14098 NEON_ENCODE (INTEGER, inst);
14099 neon_two_same (0, 1, et.size / 2);
14103 do_neon_rshift_sat_narrow (void)
14105 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14106 or unsigned. If operands are unsigned, results must also be unsigned. */
14107 struct neon_type_el et = neon_check_type (2, NS_DQI,
14108 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14109 int imm = inst.operands[2].imm;
14110 /* This gets the bounds check, size encoding and immediate bits calculation
14114 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14115 VQMOVN.I<size> <Dd>, <Qm>. */
14118 inst.operands[2].present = 0;
14119 inst.instruction = N_MNEM_vqmovn;
14124 constraint (imm < 1 || (unsigned)imm > et.size,
14125 _("immediate out of range"));
14126 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14130 do_neon_rshift_sat_narrow_u (void)
14132 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14133 or unsigned. If operands are unsigned, results must also be unsigned. */
14134 struct neon_type_el et = neon_check_type (2, NS_DQI,
14135 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14136 int imm = inst.operands[2].imm;
14137 /* This gets the bounds check, size encoding and immediate bits calculation
14141 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14142 VQMOVUN.I<size> <Dd>, <Qm>. */
14145 inst.operands[2].present = 0;
14146 inst.instruction = N_MNEM_vqmovun;
14151 constraint (imm < 1 || (unsigned)imm > et.size,
14152 _("immediate out of range"));
14153 /* FIXME: The manual is kind of unclear about what value U should have in
14154 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14156 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14160 do_neon_movn (void)
14162 struct neon_type_el et = neon_check_type (2, NS_DQ,
14163 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14164 NEON_ENCODE (INTEGER, inst);
14165 neon_two_same (0, 1, et.size / 2);
14169 do_neon_rshift_narrow (void)
14171 struct neon_type_el et = neon_check_type (2, NS_DQI,
14172 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14173 int imm = inst.operands[2].imm;
14174 /* This gets the bounds check, size encoding and immediate bits calculation
14178 /* If immediate is zero then we are a pseudo-instruction for
14179 VMOVN.I<size> <Dd>, <Qm> */
14182 inst.operands[2].present = 0;
14183 inst.instruction = N_MNEM_vmovn;
14188 constraint (imm < 1 || (unsigned)imm > et.size,
14189 _("immediate out of range for narrowing operation"));
14190 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14194 do_neon_shll (void)
14196 /* FIXME: Type checking when lengthening. */
14197 struct neon_type_el et = neon_check_type (2, NS_QDI,
14198 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14199 unsigned imm = inst.operands[2].imm;
14201 if (imm == et.size)
14203 /* Maximum shift variant. */
14204 NEON_ENCODE (INTEGER, inst);
14205 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14206 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14207 inst.instruction |= LOW4 (inst.operands[1].reg);
14208 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14209 inst.instruction |= neon_logbits (et.size) << 18;
14211 neon_dp_fixup (&inst);
14215 /* A more-specific type check for non-max versions. */
14216 et = neon_check_type (2, NS_QDI,
14217 N_EQK | N_DBL, N_SU_32 | N_KEY);
14218 NEON_ENCODE (IMMED, inst);
14219 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14223 /* Check the various types for the VCVT instruction, and return which version
14224 the current instruction is. */
14227 neon_cvt_flavour (enum neon_shape rs)
14229 #define CVT_VAR(C,X,Y) \
14230 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14231 if (et.type != NT_invtype) \
14233 inst.error = NULL; \
14236 struct neon_type_el et;
14237 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14238 || rs == NS_FF) ? N_VFP : 0;
14239 /* The instruction versions which take an immediate take one register
14240 argument, which is extended to the width of the full register. Thus the
14241 "source" and "destination" registers must have the same width. Hack that
14242 here by making the size equal to the key (wider, in this case) operand. */
14243 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14245 CVT_VAR (0, N_S32, N_F32);
14246 CVT_VAR (1, N_U32, N_F32);
14247 CVT_VAR (2, N_F32, N_S32);
14248 CVT_VAR (3, N_F32, N_U32);
14249 /* Half-precision conversions. */
14250 CVT_VAR (4, N_F32, N_F16);
14251 CVT_VAR (5, N_F16, N_F32);
14255 /* VFP instructions. */
14256 CVT_VAR (6, N_F32, N_F64);
14257 CVT_VAR (7, N_F64, N_F32);
14258 CVT_VAR (8, N_S32, N_F64 | key);
14259 CVT_VAR (9, N_U32, N_F64 | key);
14260 CVT_VAR (10, N_F64 | key, N_S32);
14261 CVT_VAR (11, N_F64 | key, N_U32);
14262 /* VFP instructions with bitshift. */
14263 CVT_VAR (12, N_F32 | key, N_S16);
14264 CVT_VAR (13, N_F32 | key, N_U16);
14265 CVT_VAR (14, N_F64 | key, N_S16);
14266 CVT_VAR (15, N_F64 | key, N_U16);
14267 CVT_VAR (16, N_S16, N_F32 | key);
14268 CVT_VAR (17, N_U16, N_F32 | key);
14269 CVT_VAR (18, N_S16, N_F64 | key);
14270 CVT_VAR (19, N_U16, N_F64 | key);
14276 /* Neon-syntax VFP conversions. */
14279 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14281 const char *opname = 0;
14283 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14285 /* Conversions with immediate bitshift. */
14286 const char *enc[] =
14310 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14312 opname = enc[flavour];
14313 constraint (inst.operands[0].reg != inst.operands[1].reg,
14314 _("operands 0 and 1 must be the same register"));
14315 inst.operands[1] = inst.operands[2];
14316 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14321 /* Conversions without bitshift. */
14322 const char *enc[] =
14338 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14339 opname = enc[flavour];
14343 do_vfp_nsyn_opcode (opname);
14347 do_vfp_nsyn_cvtz (void)
14349 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14350 int flavour = neon_cvt_flavour (rs);
14351 const char *enc[] =
14365 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14366 do_vfp_nsyn_opcode (enc[flavour]);
14370 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14372 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14373 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14374 int flavour = neon_cvt_flavour (rs);
14376 /* PR11109: Handle round-to-zero for VCVT conversions. */
14378 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14379 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14380 && (rs == NS_FD || rs == NS_FF))
14382 do_vfp_nsyn_cvtz ();
14386 /* VFP rather than Neon conversions. */
14389 do_vfp_nsyn_cvt (rs, flavour);
14399 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14401 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14404 /* Fixed-point conversion with #0 immediate is encoded as an
14405 integer conversion. */
14406 if (inst.operands[2].present && inst.operands[2].imm == 0)
14408 immbits = 32 - inst.operands[2].imm;
14409 NEON_ENCODE (IMMED, inst);
14411 inst.instruction |= enctab[flavour];
14412 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14413 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14414 inst.instruction |= LOW4 (inst.operands[1].reg);
14415 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14416 inst.instruction |= neon_quad (rs) << 6;
14417 inst.instruction |= 1 << 21;
14418 inst.instruction |= immbits << 16;
14420 neon_dp_fixup (&inst);
14428 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14430 NEON_ENCODE (INTEGER, inst);
14432 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14436 inst.instruction |= enctab[flavour];
14438 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14439 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14440 inst.instruction |= LOW4 (inst.operands[1].reg);
14441 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14442 inst.instruction |= neon_quad (rs) << 6;
14443 inst.instruction |= 2 << 18;
14445 neon_dp_fixup (&inst);
14449 /* Half-precision conversions for Advanced SIMD -- neon. */
14454 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14456 as_bad (_("operand size must match register width"));
14461 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14463 as_bad (_("operand size must match register width"));
14468 inst.instruction = 0x3b60600;
14470 inst.instruction = 0x3b60700;
14472 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14473 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14474 inst.instruction |= LOW4 (inst.operands[1].reg);
14475 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14476 neon_dp_fixup (&inst);
14480 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14481 do_vfp_nsyn_cvt (rs, flavour);
14486 do_neon_cvtr (void)
14488 do_neon_cvt_1 (FALSE);
14494 do_neon_cvt_1 (TRUE);
14498 do_neon_cvtb (void)
14500 inst.instruction = 0xeb20a40;
14502 /* The sizes are attached to the mnemonic. */
14503 if (inst.vectype.el[0].type != NT_invtype
14504 && inst.vectype.el[0].size == 16)
14505 inst.instruction |= 0x00010000;
14507 /* Programmer's syntax: the sizes are attached to the operands. */
14508 else if (inst.operands[0].vectype.type != NT_invtype
14509 && inst.operands[0].vectype.size == 16)
14510 inst.instruction |= 0x00010000;
14512 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14513 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14514 do_vfp_cond_or_thumb ();
14519 do_neon_cvtt (void)
14522 inst.instruction |= 0x80;
14526 neon_move_immediate (void)
14528 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14529 struct neon_type_el et = neon_check_type (2, rs,
14530 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14531 unsigned immlo, immhi = 0, immbits;
14532 int op, cmode, float_p;
14534 constraint (et.type == NT_invtype,
14535 _("operand size must be specified for immediate VMOV"));
14537 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14538 op = (inst.instruction & (1 << 5)) != 0;
14540 immlo = inst.operands[1].imm;
14541 if (inst.operands[1].regisimm)
14542 immhi = inst.operands[1].reg;
14544 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14545 _("immediate has bits set outside the operand size"));
14547 float_p = inst.operands[1].immisfloat;
14549 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14550 et.size, et.type)) == FAIL)
14552 /* Invert relevant bits only. */
14553 neon_invert_size (&immlo, &immhi, et.size);
14554 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14555 with one or the other; those cases are caught by
14556 neon_cmode_for_move_imm. */
14558 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14559 &op, et.size, et.type)) == FAIL)
14561 first_error (_("immediate out of range"));
14566 inst.instruction &= ~(1 << 5);
14567 inst.instruction |= op << 5;
14569 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14570 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14571 inst.instruction |= neon_quad (rs) << 6;
14572 inst.instruction |= cmode << 8;
14574 neon_write_immbits (immbits);
14580 if (inst.operands[1].isreg)
14582 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14584 NEON_ENCODE (INTEGER, inst);
14585 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14586 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14587 inst.instruction |= LOW4 (inst.operands[1].reg);
14588 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14589 inst.instruction |= neon_quad (rs) << 6;
14593 NEON_ENCODE (IMMED, inst);
14594 neon_move_immediate ();
14597 neon_dp_fixup (&inst);
14600 /* Encode instructions of form:
14602 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14603 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14606 neon_mixed_length (struct neon_type_el et, unsigned size)
14608 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14609 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14610 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14611 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14612 inst.instruction |= LOW4 (inst.operands[2].reg);
14613 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14614 inst.instruction |= (et.type == NT_unsigned) << 24;
14615 inst.instruction |= neon_logbits (size) << 20;
14617 neon_dp_fixup (&inst);
14621 do_neon_dyadic_long (void)
14623 /* FIXME: Type checking for lengthening op. */
14624 struct neon_type_el et = neon_check_type (3, NS_QDD,
14625 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14626 neon_mixed_length (et, et.size);
14630 do_neon_abal (void)
14632 struct neon_type_el et = neon_check_type (3, NS_QDD,
14633 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14634 neon_mixed_length (et, et.size);
14638 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14640 if (inst.operands[2].isscalar)
14642 struct neon_type_el et = neon_check_type (3, NS_QDS,
14643 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14644 NEON_ENCODE (SCALAR, inst);
14645 neon_mul_mac (et, et.type == NT_unsigned);
14649 struct neon_type_el et = neon_check_type (3, NS_QDD,
14650 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14651 NEON_ENCODE (INTEGER, inst);
14652 neon_mixed_length (et, et.size);
14657 do_neon_mac_maybe_scalar_long (void)
14659 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14663 do_neon_dyadic_wide (void)
14665 struct neon_type_el et = neon_check_type (3, NS_QQD,
14666 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14667 neon_mixed_length (et, et.size);
14671 do_neon_dyadic_narrow (void)
14673 struct neon_type_el et = neon_check_type (3, NS_QDD,
14674 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14675 /* Operand sign is unimportant, and the U bit is part of the opcode,
14676 so force the operand type to integer. */
14677 et.type = NT_integer;
14678 neon_mixed_length (et, et.size / 2);
14682 do_neon_mul_sat_scalar_long (void)
14684 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14688 do_neon_vmull (void)
14690 if (inst.operands[2].isscalar)
14691 do_neon_mac_maybe_scalar_long ();
14694 struct neon_type_el et = neon_check_type (3, NS_QDD,
14695 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14696 if (et.type == NT_poly)
14697 NEON_ENCODE (POLY, inst);
14699 NEON_ENCODE (INTEGER, inst);
14700 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14701 zero. Should be OK as-is. */
14702 neon_mixed_length (et, et.size);
14709 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14710 struct neon_type_el et = neon_check_type (3, rs,
14711 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14712 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14714 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14715 _("shift out of range"));
14716 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14717 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14718 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14719 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14720 inst.instruction |= LOW4 (inst.operands[2].reg);
14721 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14722 inst.instruction |= neon_quad (rs) << 6;
14723 inst.instruction |= imm << 8;
14725 neon_dp_fixup (&inst);
14731 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14732 struct neon_type_el et = neon_check_type (2, rs,
14733 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14734 unsigned op = (inst.instruction >> 7) & 3;
14735 /* N (width of reversed regions) is encoded as part of the bitmask. We
14736 extract it here to check the elements to be reversed are smaller.
14737 Otherwise we'd get a reserved instruction. */
14738 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14739 gas_assert (elsize != 0);
14740 constraint (et.size >= elsize,
14741 _("elements must be smaller than reversal region"));
14742 neon_two_same (neon_quad (rs), 1, et.size);
14748 if (inst.operands[1].isscalar)
14750 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14751 struct neon_type_el et = neon_check_type (2, rs,
14752 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14753 unsigned sizebits = et.size >> 3;
14754 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14755 int logsize = neon_logbits (et.size);
14756 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14758 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14761 NEON_ENCODE (SCALAR, inst);
14762 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14763 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14764 inst.instruction |= LOW4 (dm);
14765 inst.instruction |= HI1 (dm) << 5;
14766 inst.instruction |= neon_quad (rs) << 6;
14767 inst.instruction |= x << 17;
14768 inst.instruction |= sizebits << 16;
14770 neon_dp_fixup (&inst);
14774 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14775 struct neon_type_el et = neon_check_type (2, rs,
14776 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14777 /* Duplicate ARM register to lanes of vector. */
14778 NEON_ENCODE (ARMREG, inst);
14781 case 8: inst.instruction |= 0x400000; break;
14782 case 16: inst.instruction |= 0x000020; break;
14783 case 32: inst.instruction |= 0x000000; break;
14786 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14787 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14788 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14789 inst.instruction |= neon_quad (rs) << 21;
14790 /* The encoding for this instruction is identical for the ARM and Thumb
14791 variants, except for the condition field. */
14792 do_vfp_cond_or_thumb ();
14796 /* VMOV has particularly many variations. It can be one of:
14797 0. VMOV<c><q> <Qd>, <Qm>
14798 1. VMOV<c><q> <Dd>, <Dm>
14799 (Register operations, which are VORR with Rm = Rn.)
14800 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14801 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14803 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14804 (ARM register to scalar.)
14805 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14806 (Two ARM registers to vector.)
14807 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14808 (Scalar to ARM register.)
14809 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14810 (Vector to two ARM registers.)
14811 8. VMOV.F32 <Sd>, <Sm>
14812 9. VMOV.F64 <Dd>, <Dm>
14813 (VFP register moves.)
14814 10. VMOV.F32 <Sd>, #imm
14815 11. VMOV.F64 <Dd>, #imm
14816 (VFP float immediate load.)
14817 12. VMOV <Rd>, <Sm>
14818 (VFP single to ARM reg.)
14819 13. VMOV <Sd>, <Rm>
14820 (ARM reg to VFP single.)
14821 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14822 (Two ARM regs to two VFP singles.)
14823 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14824 (Two VFP singles to two ARM regs.)
14826 These cases can be disambiguated using neon_select_shape, except cases 1/9
14827 and 3/11 which depend on the operand type too.
14829 All the encoded bits are hardcoded by this function.
14831 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14832 Cases 5, 7 may be used with VFPv2 and above.
14834 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14835 can specify a type where it doesn't make sense to, and is ignored). */
14840 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14841 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14843 struct neon_type_el et;
14844 const char *ldconst = 0;
14848 case NS_DD: /* case 1/9. */
14849 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14850 /* It is not an error here if no type is given. */
14852 if (et.type == NT_float && et.size == 64)
14854 do_vfp_nsyn_opcode ("fcpyd");
14857 /* fall through. */
14859 case NS_QQ: /* case 0/1. */
14861 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14863 /* The architecture manual I have doesn't explicitly state which
14864 value the U bit should have for register->register moves, but
14865 the equivalent VORR instruction has U = 0, so do that. */
14866 inst.instruction = 0x0200110;
14867 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14868 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14869 inst.instruction |= LOW4 (inst.operands[1].reg);
14870 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14871 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14872 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14873 inst.instruction |= neon_quad (rs) << 6;
14875 neon_dp_fixup (&inst);
14879 case NS_DI: /* case 3/11. */
14880 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14882 if (et.type == NT_float && et.size == 64)
14884 /* case 11 (fconstd). */
14885 ldconst = "fconstd";
14886 goto encode_fconstd;
14888 /* fall through. */
14890 case NS_QI: /* case 2/3. */
14891 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14893 inst.instruction = 0x0800010;
14894 neon_move_immediate ();
14895 neon_dp_fixup (&inst);
14898 case NS_SR: /* case 4. */
14900 unsigned bcdebits = 0;
14902 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
14903 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
14905 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
14906 logsize = neon_logbits (et.size);
14908 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14910 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14911 && et.size != 32, _(BAD_FPU));
14912 constraint (et.type == NT_invtype, _("bad type for scalar"));
14913 constraint (x >= 64 / et.size, _("scalar index out of range"));
14917 case 8: bcdebits = 0x8; break;
14918 case 16: bcdebits = 0x1; break;
14919 case 32: bcdebits = 0x0; break;
14923 bcdebits |= x << logsize;
14925 inst.instruction = 0xe000b10;
14926 do_vfp_cond_or_thumb ();
14927 inst.instruction |= LOW4 (dn) << 16;
14928 inst.instruction |= HI1 (dn) << 7;
14929 inst.instruction |= inst.operands[1].reg << 12;
14930 inst.instruction |= (bcdebits & 3) << 5;
14931 inst.instruction |= (bcdebits >> 2) << 21;
14935 case NS_DRR: /* case 5 (fmdrr). */
14936 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14939 inst.instruction = 0xc400b10;
14940 do_vfp_cond_or_thumb ();
14941 inst.instruction |= LOW4 (inst.operands[0].reg);
14942 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
14943 inst.instruction |= inst.operands[1].reg << 12;
14944 inst.instruction |= inst.operands[2].reg << 16;
14947 case NS_RS: /* case 6. */
14950 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
14951 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
14952 unsigned abcdebits = 0;
14954 et = neon_check_type (2, NS_NULL,
14955 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
14956 logsize = neon_logbits (et.size);
14958 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14960 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14961 && et.size != 32, _(BAD_FPU));
14962 constraint (et.type == NT_invtype, _("bad type for scalar"));
14963 constraint (x >= 64 / et.size, _("scalar index out of range"));
14967 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
14968 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
14969 case 32: abcdebits = 0x00; break;
14973 abcdebits |= x << logsize;
14974 inst.instruction = 0xe100b10;
14975 do_vfp_cond_or_thumb ();
14976 inst.instruction |= LOW4 (dn) << 16;
14977 inst.instruction |= HI1 (dn) << 7;
14978 inst.instruction |= inst.operands[0].reg << 12;
14979 inst.instruction |= (abcdebits & 3) << 5;
14980 inst.instruction |= (abcdebits >> 2) << 21;
14984 case NS_RRD: /* case 7 (fmrrd). */
14985 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14988 inst.instruction = 0xc500b10;
14989 do_vfp_cond_or_thumb ();
14990 inst.instruction |= inst.operands[0].reg << 12;
14991 inst.instruction |= inst.operands[1].reg << 16;
14992 inst.instruction |= LOW4 (inst.operands[2].reg);
14993 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14996 case NS_FF: /* case 8 (fcpys). */
14997 do_vfp_nsyn_opcode ("fcpys");
15000 case NS_FI: /* case 10 (fconsts). */
15001 ldconst = "fconsts";
15003 if (is_quarter_float (inst.operands[1].imm))
15005 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15006 do_vfp_nsyn_opcode (ldconst);
15009 first_error (_("immediate out of range"));
15012 case NS_RF: /* case 12 (fmrs). */
15013 do_vfp_nsyn_opcode ("fmrs");
15016 case NS_FR: /* case 13 (fmsr). */
15017 do_vfp_nsyn_opcode ("fmsr");
15020 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15021 (one of which is a list), but we have parsed four. Do some fiddling to
15022 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15024 case NS_RRFF: /* case 14 (fmrrs). */
15025 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15026 _("VFP registers must be adjacent"));
15027 inst.operands[2].imm = 2;
15028 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15029 do_vfp_nsyn_opcode ("fmrrs");
15032 case NS_FFRR: /* case 15 (fmsrr). */
15033 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15034 _("VFP registers must be adjacent"));
15035 inst.operands[1] = inst.operands[2];
15036 inst.operands[2] = inst.operands[3];
15037 inst.operands[0].imm = 2;
15038 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15039 do_vfp_nsyn_opcode ("fmsrr");
15048 do_neon_rshift_round_imm (void)
15050 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15051 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15052 int imm = inst.operands[2].imm;
15054 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15057 inst.operands[2].present = 0;
15062 constraint (imm < 1 || (unsigned)imm > et.size,
15063 _("immediate out of range for shift"));
15064 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15069 do_neon_movl (void)
15071 struct neon_type_el et = neon_check_type (2, NS_QD,
15072 N_EQK | N_DBL, N_SU_32 | N_KEY);
15073 unsigned sizebits = et.size >> 3;
15074 inst.instruction |= sizebits << 19;
15075 neon_two_same (0, et.type == NT_unsigned, -1);
15081 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15082 struct neon_type_el et = neon_check_type (2, rs,
15083 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15084 NEON_ENCODE (INTEGER, inst);
15085 neon_two_same (neon_quad (rs), 1, et.size);
15089 do_neon_zip_uzp (void)
15091 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15092 struct neon_type_el et = neon_check_type (2, rs,
15093 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15094 if (rs == NS_DD && et.size == 32)
15096 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15097 inst.instruction = N_MNEM_vtrn;
15101 neon_two_same (neon_quad (rs), 1, et.size);
15105 do_neon_sat_abs_neg (void)
15107 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15108 struct neon_type_el et = neon_check_type (2, rs,
15109 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15110 neon_two_same (neon_quad (rs), 1, et.size);
15114 do_neon_pair_long (void)
15116 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15117 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15118 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15119 inst.instruction |= (et.type == NT_unsigned) << 7;
15120 neon_two_same (neon_quad (rs), 1, et.size);
15124 do_neon_recip_est (void)
15126 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15127 struct neon_type_el et = neon_check_type (2, rs,
15128 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15129 inst.instruction |= (et.type == NT_float) << 8;
15130 neon_two_same (neon_quad (rs), 1, et.size);
15136 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15137 struct neon_type_el et = neon_check_type (2, rs,
15138 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15139 neon_two_same (neon_quad (rs), 1, et.size);
15145 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15146 struct neon_type_el et = neon_check_type (2, rs,
15147 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15148 neon_two_same (neon_quad (rs), 1, et.size);
15154 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15155 struct neon_type_el et = neon_check_type (2, rs,
15156 N_EQK | N_INT, N_8 | N_KEY);
15157 neon_two_same (neon_quad (rs), 1, et.size);
15163 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15164 neon_two_same (neon_quad (rs), 1, -1);
15168 do_neon_tbl_tbx (void)
15170 unsigned listlenbits;
15171 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15173 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15175 first_error (_("bad list length for table lookup"));
15179 listlenbits = inst.operands[1].imm - 1;
15180 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15181 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15182 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15183 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15184 inst.instruction |= LOW4 (inst.operands[2].reg);
15185 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15186 inst.instruction |= listlenbits << 8;
15188 neon_dp_fixup (&inst);
15192 do_neon_ldm_stm (void)
15194 /* P, U and L bits are part of bitmask. */
15195 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15196 unsigned offsetbits = inst.operands[1].imm * 2;
15198 if (inst.operands[1].issingle)
15200 do_vfp_nsyn_ldm_stm (is_dbmode);
15204 constraint (is_dbmode && !inst.operands[0].writeback,
15205 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15207 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15208 _("register list must contain at least 1 and at most 16 "
15211 inst.instruction |= inst.operands[0].reg << 16;
15212 inst.instruction |= inst.operands[0].writeback << 21;
15213 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15214 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15216 inst.instruction |= offsetbits;
15218 do_vfp_cond_or_thumb ();
15222 do_neon_ldr_str (void)
15224 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15226 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15227 And is UNPREDICTABLE in thumb mode. */
15229 && inst.operands[1].reg == REG_PC
15230 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15232 if (!thumb_mode && warn_on_deprecated)
15233 as_warn (_("Use of PC here is deprecated"));
15235 inst.error = _("Use of PC here is UNPREDICTABLE");
15238 if (inst.operands[0].issingle)
15241 do_vfp_nsyn_opcode ("flds");
15243 do_vfp_nsyn_opcode ("fsts");
15248 do_vfp_nsyn_opcode ("fldd");
15250 do_vfp_nsyn_opcode ("fstd");
15254 /* "interleave" version also handles non-interleaving register VLD1/VST1
15258 do_neon_ld_st_interleave (void)
15260 struct neon_type_el et = neon_check_type (1, NS_NULL,
15261 N_8 | N_16 | N_32 | N_64);
15262 unsigned alignbits = 0;
15264 /* The bits in this table go:
15265 0: register stride of one (0) or two (1)
15266 1,2: register list length, minus one (1, 2, 3, 4).
15267 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15268 We use -1 for invalid entries. */
15269 const int typetable[] =
15271 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15272 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15273 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15274 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15278 if (et.type == NT_invtype)
15281 if (inst.operands[1].immisalign)
15282 switch (inst.operands[1].imm >> 8)
15284 case 64: alignbits = 1; break;
15286 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15287 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15288 goto bad_alignment;
15292 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15293 goto bad_alignment;
15298 first_error (_("bad alignment"));
15302 inst.instruction |= alignbits << 4;
15303 inst.instruction |= neon_logbits (et.size) << 6;
15305 /* Bits [4:6] of the immediate in a list specifier encode register stride
15306 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15307 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15308 up the right value for "type" in a table based on this value and the given
15309 list style, then stick it back. */
15310 idx = ((inst.operands[0].imm >> 4) & 7)
15311 | (((inst.instruction >> 8) & 3) << 3);
15313 typebits = typetable[idx];
15315 constraint (typebits == -1, _("bad list type for instruction"));
15317 inst.instruction &= ~0xf00;
15318 inst.instruction |= typebits << 8;
15321 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15322 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15323 otherwise. The variable arguments are a list of pairs of legal (size, align)
15324 values, terminated with -1. */
15327 neon_alignment_bit (int size, int align, int *do_align, ...)
15330 int result = FAIL, thissize, thisalign;
15332 if (!inst.operands[1].immisalign)
15338 va_start (ap, do_align);
15342 thissize = va_arg (ap, int);
15343 if (thissize == -1)
15345 thisalign = va_arg (ap, int);
15347 if (size == thissize && align == thisalign)
15350 while (result != SUCCESS);
15354 if (result == SUCCESS)
15357 first_error (_("unsupported alignment for instruction"));
15363 do_neon_ld_st_lane (void)
15365 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15366 int align_good, do_align = 0;
15367 int logsize = neon_logbits (et.size);
15368 int align = inst.operands[1].imm >> 8;
15369 int n = (inst.instruction >> 8) & 3;
15370 int max_el = 64 / et.size;
15372 if (et.type == NT_invtype)
15375 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15376 _("bad list length"));
15377 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15378 _("scalar index out of range"));
15379 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15381 _("stride of 2 unavailable when element size is 8"));
15385 case 0: /* VLD1 / VST1. */
15386 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15388 if (align_good == FAIL)
15392 unsigned alignbits = 0;
15395 case 16: alignbits = 0x1; break;
15396 case 32: alignbits = 0x3; break;
15399 inst.instruction |= alignbits << 4;
15403 case 1: /* VLD2 / VST2. */
15404 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15406 if (align_good == FAIL)
15409 inst.instruction |= 1 << 4;
15412 case 2: /* VLD3 / VST3. */
15413 constraint (inst.operands[1].immisalign,
15414 _("can't use alignment with this instruction"));
15417 case 3: /* VLD4 / VST4. */
15418 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15419 16, 64, 32, 64, 32, 128, -1);
15420 if (align_good == FAIL)
15424 unsigned alignbits = 0;
15427 case 8: alignbits = 0x1; break;
15428 case 16: alignbits = 0x1; break;
15429 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15432 inst.instruction |= alignbits << 4;
15439 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15440 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15441 inst.instruction |= 1 << (4 + logsize);
15443 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15444 inst.instruction |= logsize << 10;
15447 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15450 do_neon_ld_dup (void)
15452 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15453 int align_good, do_align = 0;
15455 if (et.type == NT_invtype)
15458 switch ((inst.instruction >> 8) & 3)
15460 case 0: /* VLD1. */
15461 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15462 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15463 &do_align, 16, 16, 32, 32, -1);
15464 if (align_good == FAIL)
15466 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15469 case 2: inst.instruction |= 1 << 5; break;
15470 default: first_error (_("bad list length")); return;
15472 inst.instruction |= neon_logbits (et.size) << 6;
15475 case 1: /* VLD2. */
15476 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15477 &do_align, 8, 16, 16, 32, 32, 64, -1);
15478 if (align_good == FAIL)
15480 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15481 _("bad list length"));
15482 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15483 inst.instruction |= 1 << 5;
15484 inst.instruction |= neon_logbits (et.size) << 6;
15487 case 2: /* VLD3. */
15488 constraint (inst.operands[1].immisalign,
15489 _("can't use alignment with this instruction"));
15490 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15491 _("bad list length"));
15492 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15493 inst.instruction |= 1 << 5;
15494 inst.instruction |= neon_logbits (et.size) << 6;
15497 case 3: /* VLD4. */
15499 int align = inst.operands[1].imm >> 8;
15500 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15501 16, 64, 32, 64, 32, 128, -1);
15502 if (align_good == FAIL)
15504 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15505 _("bad list length"));
15506 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15507 inst.instruction |= 1 << 5;
15508 if (et.size == 32 && align == 128)
15509 inst.instruction |= 0x3 << 6;
15511 inst.instruction |= neon_logbits (et.size) << 6;
15518 inst.instruction |= do_align << 4;
15521 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15522 apart from bits [11:4]. */
15525 do_neon_ldx_stx (void)
15527 if (inst.operands[1].isreg)
15528 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15530 switch (NEON_LANE (inst.operands[0].imm))
15532 case NEON_INTERLEAVE_LANES:
15533 NEON_ENCODE (INTERLV, inst);
15534 do_neon_ld_st_interleave ();
15537 case NEON_ALL_LANES:
15538 NEON_ENCODE (DUP, inst);
15543 NEON_ENCODE (LANE, inst);
15544 do_neon_ld_st_lane ();
15547 /* L bit comes from bit mask. */
15548 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15549 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15550 inst.instruction |= inst.operands[1].reg << 16;
15552 if (inst.operands[1].postind)
15554 int postreg = inst.operands[1].imm & 0xf;
15555 constraint (!inst.operands[1].immisreg,
15556 _("post-index must be a register"));
15557 constraint (postreg == 0xd || postreg == 0xf,
15558 _("bad register for post-index"));
15559 inst.instruction |= postreg;
15561 else if (inst.operands[1].writeback)
15563 inst.instruction |= 0xd;
15566 inst.instruction |= 0xf;
15569 inst.instruction |= 0xf9000000;
15571 inst.instruction |= 0xf4000000;
15574 /* Overall per-instruction processing. */
15576 /* We need to be able to fix up arbitrary expressions in some statements.
15577 This is so that we can handle symbols that are an arbitrary distance from
15578 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15579 which returns part of an address in a form which will be valid for
15580 a data instruction. We do this by pushing the expression into a symbol
15581 in the expr_section, and creating a fix for that. */
15584 fix_new_arm (fragS * frag,
15598 /* Create an absolute valued symbol, so we have something to
15599 refer to in the object file. Unfortunately for us, gas's
15600 generic expression parsing will already have folded out
15601 any use of .set foo/.type foo %function that may have
15602 been used to set type information of the target location,
15603 that's being specified symbolically. We have to presume
15604 the user knows what they are doing. */
15608 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15610 symbol = symbol_find_or_make (name);
15611 S_SET_SEGMENT (symbol, absolute_section);
15612 symbol_set_frag (symbol, &zero_address_frag);
15613 S_SET_VALUE (symbol, exp->X_add_number);
15614 exp->X_op = O_symbol;
15615 exp->X_add_symbol = symbol;
15616 exp->X_add_number = 0;
15622 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15623 (enum bfd_reloc_code_real) reloc);
15627 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15628 pc_rel, (enum bfd_reloc_code_real) reloc);
15632 /* Mark whether the fix is to a THUMB instruction, or an ARM
15634 new_fix->tc_fix_data = thumb_mode;
15637 /* Create a frg for an instruction requiring relaxation. */
15639 output_relax_insn (void)
15645 /* The size of the instruction is unknown, so tie the debug info to the
15646 start of the instruction. */
15647 dwarf2_emit_insn (0);
15649 switch (inst.reloc.exp.X_op)
15652 sym = inst.reloc.exp.X_add_symbol;
15653 offset = inst.reloc.exp.X_add_number;
15657 offset = inst.reloc.exp.X_add_number;
15660 sym = make_expr_symbol (&inst.reloc.exp);
15664 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15665 inst.relax, sym, offset, NULL/*offset, opcode*/);
15666 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15669 /* Write a 32-bit thumb instruction to buf. */
15671 put_thumb32_insn (char * buf, unsigned long insn)
15673 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15674 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15678 output_inst (const char * str)
15684 as_bad ("%s -- `%s'", inst.error, str);
15689 output_relax_insn ();
15692 if (inst.size == 0)
15695 to = frag_more (inst.size);
15696 /* PR 9814: Record the thumb mode into the current frag so that we know
15697 what type of NOP padding to use, if necessary. We override any previous
15698 setting so that if the mode has changed then the NOPS that we use will
15699 match the encoding of the last instruction in the frag. */
15700 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15702 if (thumb_mode && (inst.size > THUMB_SIZE))
15704 gas_assert (inst.size == (2 * THUMB_SIZE));
15705 put_thumb32_insn (to, inst.instruction);
15707 else if (inst.size > INSN_SIZE)
15709 gas_assert (inst.size == (2 * INSN_SIZE));
15710 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15711 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15714 md_number_to_chars (to, inst.instruction, inst.size);
15716 if (inst.reloc.type != BFD_RELOC_UNUSED)
15717 fix_new_arm (frag_now, to - frag_now->fr_literal,
15718 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15721 dwarf2_emit_insn (inst.size);
15725 output_it_inst (int cond, int mask, char * to)
15727 unsigned long instruction = 0xbf00;
15730 instruction |= mask;
15731 instruction |= cond << 4;
15735 to = frag_more (2);
15737 dwarf2_emit_insn (2);
15741 md_number_to_chars (to, instruction, 2);
15746 /* Tag values used in struct asm_opcode's tag field. */
15749 OT_unconditional, /* Instruction cannot be conditionalized.
15750 The ARM condition field is still 0xE. */
15751 OT_unconditionalF, /* Instruction cannot be conditionalized
15752 and carries 0xF in its ARM condition field. */
15753 OT_csuffix, /* Instruction takes a conditional suffix. */
15754 OT_csuffixF, /* Some forms of the instruction take a conditional
15755 suffix, others place 0xF where the condition field
15757 OT_cinfix3, /* Instruction takes a conditional infix,
15758 beginning at character index 3. (In
15759 unified mode, it becomes a suffix.) */
15760 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15761 tsts, cmps, cmns, and teqs. */
15762 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15763 character index 3, even in unified mode. Used for
15764 legacy instructions where suffix and infix forms
15765 may be ambiguous. */
15766 OT_csuf_or_in3, /* Instruction takes either a conditional
15767 suffix or an infix at character index 3. */
15768 OT_odd_infix_unc, /* This is the unconditional variant of an
15769 instruction that takes a conditional infix
15770 at an unusual position. In unified mode,
15771 this variant will accept a suffix. */
15772 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15773 are the conditional variants of instructions that
15774 take conditional infixes in unusual positions.
15775 The infix appears at character index
15776 (tag - OT_odd_infix_0). These are not accepted
15777 in unified mode. */
15780 /* Subroutine of md_assemble, responsible for looking up the primary
15781 opcode from the mnemonic the user wrote. STR points to the
15782 beginning of the mnemonic.
15784 This is not simply a hash table lookup, because of conditional
15785 variants. Most instructions have conditional variants, which are
15786 expressed with a _conditional affix_ to the mnemonic. If we were
15787 to encode each conditional variant as a literal string in the opcode
15788 table, it would have approximately 20,000 entries.
15790 Most mnemonics take this affix as a suffix, and in unified syntax,
15791 'most' is upgraded to 'all'. However, in the divided syntax, some
15792 instructions take the affix as an infix, notably the s-variants of
15793 the arithmetic instructions. Of those instructions, all but six
15794 have the infix appear after the third character of the mnemonic.
15796 Accordingly, the algorithm for looking up primary opcodes given
15799 1. Look up the identifier in the opcode table.
15800 If we find a match, go to step U.
15802 2. Look up the last two characters of the identifier in the
15803 conditions table. If we find a match, look up the first N-2
15804 characters of the identifier in the opcode table. If we
15805 find a match, go to step CE.
15807 3. Look up the fourth and fifth characters of the identifier in
15808 the conditions table. If we find a match, extract those
15809 characters from the identifier, and look up the remaining
15810 characters in the opcode table. If we find a match, go
15815 U. Examine the tag field of the opcode structure, in case this is
15816 one of the six instructions with its conditional infix in an
15817 unusual place. If it is, the tag tells us where to find the
15818 infix; look it up in the conditions table and set inst.cond
15819 accordingly. Otherwise, this is an unconditional instruction.
15820 Again set inst.cond accordingly. Return the opcode structure.
15822 CE. Examine the tag field to make sure this is an instruction that
15823 should receive a conditional suffix. If it is not, fail.
15824 Otherwise, set inst.cond from the suffix we already looked up,
15825 and return the opcode structure.
15827 CM. Examine the tag field to make sure this is an instruction that
15828 should receive a conditional infix after the third character.
15829 If it is not, fail. Otherwise, undo the edits to the current
15830 line of input and proceed as for case CE. */
15832 static const struct asm_opcode *
15833 opcode_lookup (char **str)
15837 const struct asm_opcode *opcode;
15838 const struct asm_cond *cond;
15841 /* Scan up to the end of the mnemonic, which must end in white space,
15842 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15843 for (base = end = *str; *end != '\0'; end++)
15844 if (*end == ' ' || *end == '.')
15850 /* Handle a possible width suffix and/or Neon type suffix. */
15855 /* The .w and .n suffixes are only valid if the unified syntax is in
15857 if (unified_syntax && end[1] == 'w')
15859 else if (unified_syntax && end[1] == 'n')
15864 inst.vectype.elems = 0;
15866 *str = end + offset;
15868 if (end[offset] == '.')
15870 /* See if we have a Neon type suffix (possible in either unified or
15871 non-unified ARM syntax mode). */
15872 if (parse_neon_type (&inst.vectype, str) == FAIL)
15875 else if (end[offset] != '\0' && end[offset] != ' ')
15881 /* Look for unaffixed or special-case affixed mnemonic. */
15882 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15887 if (opcode->tag < OT_odd_infix_0)
15889 inst.cond = COND_ALWAYS;
15893 if (warn_on_deprecated && unified_syntax)
15894 as_warn (_("conditional infixes are deprecated in unified syntax"));
15895 affix = base + (opcode->tag - OT_odd_infix_0);
15896 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15899 inst.cond = cond->value;
15903 /* Cannot have a conditional suffix on a mnemonic of less than two
15905 if (end - base < 3)
15908 /* Look for suffixed mnemonic. */
15910 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15911 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15913 if (opcode && cond)
15916 switch (opcode->tag)
15918 case OT_cinfix3_legacy:
15919 /* Ignore conditional suffixes matched on infix only mnemonics. */
15923 case OT_cinfix3_deprecated:
15924 case OT_odd_infix_unc:
15925 if (!unified_syntax)
15927 /* else fall through */
15931 case OT_csuf_or_in3:
15932 inst.cond = cond->value;
15935 case OT_unconditional:
15936 case OT_unconditionalF:
15938 inst.cond = cond->value;
15941 /* Delayed diagnostic. */
15942 inst.error = BAD_COND;
15943 inst.cond = COND_ALWAYS;
15952 /* Cannot have a usual-position infix on a mnemonic of less than
15953 six characters (five would be a suffix). */
15954 if (end - base < 6)
15957 /* Look for infixed mnemonic in the usual position. */
15959 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15963 memcpy (save, affix, 2);
15964 memmove (affix, affix + 2, (end - affix) - 2);
15965 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15967 memmove (affix + 2, affix, (end - affix) - 2);
15968 memcpy (affix, save, 2);
15971 && (opcode->tag == OT_cinfix3
15972 || opcode->tag == OT_cinfix3_deprecated
15973 || opcode->tag == OT_csuf_or_in3
15974 || opcode->tag == OT_cinfix3_legacy))
15977 if (warn_on_deprecated && unified_syntax
15978 && (opcode->tag == OT_cinfix3
15979 || opcode->tag == OT_cinfix3_deprecated))
15980 as_warn (_("conditional infixes are deprecated in unified syntax"));
15982 inst.cond = cond->value;
15989 /* This function generates an initial IT instruction, leaving its block
15990 virtually open for the new instructions. Eventually,
15991 the mask will be updated by now_it_add_mask () each time
15992 a new instruction needs to be included in the IT block.
15993 Finally, the block is closed with close_automatic_it_block ().
15994 The block closure can be requested either from md_assemble (),
15995 a tencode (), or due to a label hook. */
15998 new_automatic_it_block (int cond)
16000 now_it.state = AUTOMATIC_IT_BLOCK;
16001 now_it.mask = 0x18;
16003 now_it.block_length = 1;
16004 mapping_state (MAP_THUMB);
16005 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16008 /* Close an automatic IT block.
16009 See comments in new_automatic_it_block (). */
16012 close_automatic_it_block (void)
16014 now_it.mask = 0x10;
16015 now_it.block_length = 0;
16018 /* Update the mask of the current automatically-generated IT
16019 instruction. See comments in new_automatic_it_block (). */
16022 now_it_add_mask (int cond)
16024 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16025 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16026 | ((bitvalue) << (nbit)))
16027 const int resulting_bit = (cond & 1);
16029 now_it.mask &= 0xf;
16030 now_it.mask = SET_BIT_VALUE (now_it.mask,
16032 (5 - now_it.block_length));
16033 now_it.mask = SET_BIT_VALUE (now_it.mask,
16035 ((5 - now_it.block_length) - 1) );
16036 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16039 #undef SET_BIT_VALUE
16042 /* The IT blocks handling machinery is accessed through the these functions:
16043 it_fsm_pre_encode () from md_assemble ()
16044 set_it_insn_type () optional, from the tencode functions
16045 set_it_insn_type_last () ditto
16046 in_it_block () ditto
16047 it_fsm_post_encode () from md_assemble ()
16048 force_automatic_it_block_close () from label habdling functions
16051 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16052 initializing the IT insn type with a generic initial value depending
16053 on the inst.condition.
16054 2) During the tencode function, two things may happen:
16055 a) The tencode function overrides the IT insn type by
16056 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16057 b) The tencode function queries the IT block state by
16058 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16060 Both set_it_insn_type and in_it_block run the internal FSM state
16061 handling function (handle_it_state), because: a) setting the IT insn
16062 type may incur in an invalid state (exiting the function),
16063 and b) querying the state requires the FSM to be updated.
16064 Specifically we want to avoid creating an IT block for conditional
16065 branches, so it_fsm_pre_encode is actually a guess and we can't
16066 determine whether an IT block is required until the tencode () routine
16067 has decided what type of instruction this actually it.
16068 Because of this, if set_it_insn_type and in_it_block have to be used,
16069 set_it_insn_type has to be called first.
16071 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16072 determines the insn IT type depending on the inst.cond code.
16073 When a tencode () routine encodes an instruction that can be
16074 either outside an IT block, or, in the case of being inside, has to be
16075 the last one, set_it_insn_type_last () will determine the proper
16076 IT instruction type based on the inst.cond code. Otherwise,
16077 set_it_insn_type can be called for overriding that logic or
16078 for covering other cases.
16080 Calling handle_it_state () may not transition the IT block state to
16081 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16082 still queried. Instead, if the FSM determines that the state should
16083 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16084 after the tencode () function: that's what it_fsm_post_encode () does.
16086 Since in_it_block () calls the state handling function to get an
16087 updated state, an error may occur (due to invalid insns combination).
16088 In that case, inst.error is set.
16089 Therefore, inst.error has to be checked after the execution of
16090 the tencode () routine.
16092 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16093 any pending state change (if any) that didn't take place in
16094 handle_it_state () as explained above. */
16097 it_fsm_pre_encode (void)
16099 if (inst.cond != COND_ALWAYS)
16100 inst.it_insn_type = INSIDE_IT_INSN;
16102 inst.it_insn_type = OUTSIDE_IT_INSN;
16104 now_it.state_handled = 0;
16107 /* IT state FSM handling function. */
16110 handle_it_state (void)
16112 now_it.state_handled = 1;
16114 switch (now_it.state)
16116 case OUTSIDE_IT_BLOCK:
16117 switch (inst.it_insn_type)
16119 case OUTSIDE_IT_INSN:
16122 case INSIDE_IT_INSN:
16123 case INSIDE_IT_LAST_INSN:
16124 if (thumb_mode == 0)
16127 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16128 as_tsktsk (_("Warning: conditional outside an IT block"\
16133 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16134 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16136 /* Automatically generate the IT instruction. */
16137 new_automatic_it_block (inst.cond);
16138 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16139 close_automatic_it_block ();
16143 inst.error = BAD_OUT_IT;
16149 case IF_INSIDE_IT_LAST_INSN:
16150 case NEUTRAL_IT_INSN:
16154 now_it.state = MANUAL_IT_BLOCK;
16155 now_it.block_length = 0;
16160 case AUTOMATIC_IT_BLOCK:
16161 /* Three things may happen now:
16162 a) We should increment current it block size;
16163 b) We should close current it block (closing insn or 4 insns);
16164 c) We should close current it block and start a new one (due
16165 to incompatible conditions or
16166 4 insns-length block reached). */
16168 switch (inst.it_insn_type)
16170 case OUTSIDE_IT_INSN:
16171 /* The closure of the block shall happen immediatelly,
16172 so any in_it_block () call reports the block as closed. */
16173 force_automatic_it_block_close ();
16176 case INSIDE_IT_INSN:
16177 case INSIDE_IT_LAST_INSN:
16178 case IF_INSIDE_IT_LAST_INSN:
16179 now_it.block_length++;
16181 if (now_it.block_length > 4
16182 || !now_it_compatible (inst.cond))
16184 force_automatic_it_block_close ();
16185 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16186 new_automatic_it_block (inst.cond);
16190 now_it_add_mask (inst.cond);
16193 if (now_it.state == AUTOMATIC_IT_BLOCK
16194 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16195 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16196 close_automatic_it_block ();
16199 case NEUTRAL_IT_INSN:
16200 now_it.block_length++;
16202 if (now_it.block_length > 4)
16203 force_automatic_it_block_close ();
16205 now_it_add_mask (now_it.cc & 1);
16209 close_automatic_it_block ();
16210 now_it.state = MANUAL_IT_BLOCK;
16215 case MANUAL_IT_BLOCK:
16217 /* Check conditional suffixes. */
16218 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16221 now_it.mask &= 0x1f;
16222 is_last = (now_it.mask == 0x10);
16224 switch (inst.it_insn_type)
16226 case OUTSIDE_IT_INSN:
16227 inst.error = BAD_NOT_IT;
16230 case INSIDE_IT_INSN:
16231 if (cond != inst.cond)
16233 inst.error = BAD_IT_COND;
16238 case INSIDE_IT_LAST_INSN:
16239 case IF_INSIDE_IT_LAST_INSN:
16240 if (cond != inst.cond)
16242 inst.error = BAD_IT_COND;
16247 inst.error = BAD_BRANCH;
16252 case NEUTRAL_IT_INSN:
16253 /* The BKPT instruction is unconditional even in an IT block. */
16257 inst.error = BAD_IT_IT;
16268 it_fsm_post_encode (void)
16272 if (!now_it.state_handled)
16273 handle_it_state ();
16275 is_last = (now_it.mask == 0x10);
16278 now_it.state = OUTSIDE_IT_BLOCK;
16284 force_automatic_it_block_close (void)
16286 if (now_it.state == AUTOMATIC_IT_BLOCK)
16288 close_automatic_it_block ();
16289 now_it.state = OUTSIDE_IT_BLOCK;
16297 if (!now_it.state_handled)
16298 handle_it_state ();
16300 return now_it.state != OUTSIDE_IT_BLOCK;
16304 md_assemble (char *str)
16307 const struct asm_opcode * opcode;
16309 /* Align the previous label if needed. */
16310 if (last_label_seen != NULL)
16312 symbol_set_frag (last_label_seen, frag_now);
16313 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16314 S_SET_SEGMENT (last_label_seen, now_seg);
16317 memset (&inst, '\0', sizeof (inst));
16318 inst.reloc.type = BFD_RELOC_UNUSED;
16320 opcode = opcode_lookup (&p);
16323 /* It wasn't an instruction, but it might be a register alias of
16324 the form alias .req reg, or a Neon .dn/.qn directive. */
16325 if (! create_register_alias (str, p)
16326 && ! create_neon_reg_alias (str, p))
16327 as_bad (_("bad instruction `%s'"), str);
16332 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16333 as_warn (_("s suffix on comparison instruction is deprecated"));
16335 /* The value which unconditional instructions should have in place of the
16336 condition field. */
16337 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16341 arm_feature_set variant;
16343 variant = cpu_variant;
16344 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16345 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16346 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16347 /* Check that this instruction is supported for this CPU. */
16348 if (!opcode->tvariant
16349 || (thumb_mode == 1
16350 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16352 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16355 if (inst.cond != COND_ALWAYS && !unified_syntax
16356 && opcode->tencode != do_t_branch)
16358 as_bad (_("Thumb does not support conditional execution"));
16362 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16364 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16365 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16366 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16368 /* Two things are addressed here.
16369 1) Implicit require narrow instructions on Thumb-1.
16370 This avoids relaxation accidentally introducing Thumb-2
16372 2) Reject wide instructions in non Thumb-2 cores. */
16373 if (inst.size_req == 0)
16375 else if (inst.size_req == 4)
16377 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16383 inst.instruction = opcode->tvalue;
16385 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16387 /* Prepare the it_insn_type for those encodings that don't set
16389 it_fsm_pre_encode ();
16391 opcode->tencode ();
16393 it_fsm_post_encode ();
16396 if (!(inst.error || inst.relax))
16398 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16399 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16400 if (inst.size_req && inst.size_req != inst.size)
16402 as_bad (_("cannot honor width suffix -- `%s'"), str);
16407 /* Something has gone badly wrong if we try to relax a fixed size
16409 gas_assert (inst.size_req == 0 || !inst.relax);
16411 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16412 *opcode->tvariant);
16413 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16414 set those bits when Thumb-2 32-bit instructions are seen. ie.
16415 anything other than bl/blx and v6-M instructions.
16416 This is overly pessimistic for relaxable instructions. */
16417 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16419 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16420 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16421 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16424 check_neon_suffixes;
16428 mapping_state (MAP_THUMB);
16431 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16435 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16436 is_bx = (opcode->aencode == do_bx);
16438 /* Check that this instruction is supported for this CPU. */
16439 if (!(is_bx && fix_v4bx)
16440 && !(opcode->avariant &&
16441 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16443 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16448 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16452 inst.instruction = opcode->avalue;
16453 if (opcode->tag == OT_unconditionalF)
16454 inst.instruction |= 0xF << 28;
16456 inst.instruction |= inst.cond << 28;
16457 inst.size = INSN_SIZE;
16458 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16460 it_fsm_pre_encode ();
16461 opcode->aencode ();
16462 it_fsm_post_encode ();
16464 /* Arm mode bx is marked as both v4T and v5 because it's still required
16465 on a hypothetical non-thumb v5 core. */
16467 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16469 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16470 *opcode->avariant);
16472 check_neon_suffixes;
16476 mapping_state (MAP_ARM);
16481 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16489 check_it_blocks_finished (void)
16494 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16495 if (seg_info (sect)->tc_segment_info_data.current_it.state
16496 == MANUAL_IT_BLOCK)
16498 as_warn (_("section '%s' finished with an open IT block."),
16502 if (now_it.state == MANUAL_IT_BLOCK)
16503 as_warn (_("file finished with an open IT block."));
16507 /* Various frobbings of labels and their addresses. */
16510 arm_start_line_hook (void)
16512 last_label_seen = NULL;
16516 arm_frob_label (symbolS * sym)
16518 last_label_seen = sym;
16520 ARM_SET_THUMB (sym, thumb_mode);
16522 #if defined OBJ_COFF || defined OBJ_ELF
16523 ARM_SET_INTERWORK (sym, support_interwork);
16526 force_automatic_it_block_close ();
16528 /* Note - do not allow local symbols (.Lxxx) to be labelled
16529 as Thumb functions. This is because these labels, whilst
16530 they exist inside Thumb code, are not the entry points for
16531 possible ARM->Thumb calls. Also, these labels can be used
16532 as part of a computed goto or switch statement. eg gcc
16533 can generate code that looks like this:
16535 ldr r2, [pc, .Laaa]
16545 The first instruction loads the address of the jump table.
16546 The second instruction converts a table index into a byte offset.
16547 The third instruction gets the jump address out of the table.
16548 The fourth instruction performs the jump.
16550 If the address stored at .Laaa is that of a symbol which has the
16551 Thumb_Func bit set, then the linker will arrange for this address
16552 to have the bottom bit set, which in turn would mean that the
16553 address computation performed by the third instruction would end
16554 up with the bottom bit set. Since the ARM is capable of unaligned
16555 word loads, the instruction would then load the incorrect address
16556 out of the jump table, and chaos would ensue. */
16557 if (label_is_thumb_function_name
16558 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16559 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16561 /* When the address of a Thumb function is taken the bottom
16562 bit of that address should be set. This will allow
16563 interworking between Arm and Thumb functions to work
16566 THUMB_SET_FUNC (sym, 1);
16568 label_is_thumb_function_name = FALSE;
16571 dwarf2_emit_label (sym);
16575 arm_data_in_code (void)
16577 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16579 *input_line_pointer = '/';
16580 input_line_pointer += 5;
16581 *input_line_pointer = 0;
16589 arm_canonicalize_symbol_name (char * name)
16593 if (thumb_mode && (len = strlen (name)) > 5
16594 && streq (name + len - 5, "/data"))
16595 *(name + len - 5) = 0;
16600 /* Table of all register names defined by default. The user can
16601 define additional names with .req. Note that all register names
16602 should appear in both upper and lowercase variants. Some registers
16603 also have mixed-case names. */
16605 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16606 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16607 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16608 #define REGSET(p,t) \
16609 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16610 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16611 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16612 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16613 #define REGSETH(p,t) \
16614 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16615 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16616 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16617 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16618 #define REGSET2(p,t) \
16619 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16620 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16621 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16622 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16623 #define SPLRBANK(base,bank,t) \
16624 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16625 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16626 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16627 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16628 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16629 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16631 static const struct reg_entry reg_names[] =
16633 /* ARM integer registers. */
16634 REGSET(r, RN), REGSET(R, RN),
16636 /* ATPCS synonyms. */
16637 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16638 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16639 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16641 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16642 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16643 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16645 /* Well-known aliases. */
16646 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16647 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16649 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16650 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16652 /* Coprocessor numbers. */
16653 REGSET(p, CP), REGSET(P, CP),
16655 /* Coprocessor register numbers. The "cr" variants are for backward
16657 REGSET(c, CN), REGSET(C, CN),
16658 REGSET(cr, CN), REGSET(CR, CN),
16660 /* ARM banked registers. */
16661 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16662 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16663 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16664 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16665 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16666 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16667 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16669 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16670 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16671 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16672 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16673 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16674 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16675 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16676 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16678 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16679 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16680 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16681 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16682 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16683 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16684 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16685 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16686 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16688 /* FPA registers. */
16689 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16690 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16692 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16693 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16695 /* VFP SP registers. */
16696 REGSET(s,VFS), REGSET(S,VFS),
16697 REGSETH(s,VFS), REGSETH(S,VFS),
16699 /* VFP DP Registers. */
16700 REGSET(d,VFD), REGSET(D,VFD),
16701 /* Extra Neon DP registers. */
16702 REGSETH(d,VFD), REGSETH(D,VFD),
16704 /* Neon QP registers. */
16705 REGSET2(q,NQ), REGSET2(Q,NQ),
16707 /* VFP control registers. */
16708 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16709 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16710 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16711 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16712 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16713 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16715 /* Maverick DSP coprocessor registers. */
16716 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16717 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16719 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16720 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16721 REGDEF(dspsc,0,DSPSC),
16723 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16724 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16725 REGDEF(DSPSC,0,DSPSC),
16727 /* iWMMXt data registers - p0, c0-15. */
16728 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16730 /* iWMMXt control registers - p1, c0-3. */
16731 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16732 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16733 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16734 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16736 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16737 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16738 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16739 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16740 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16742 /* XScale accumulator registers. */
16743 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16749 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16750 within psr_required_here. */
16751 static const struct asm_psr psrs[] =
16753 /* Backward compatibility notation. Note that "all" is no longer
16754 truly all possible PSR bits. */
16755 {"all", PSR_c | PSR_f},
16759 /* Individual flags. */
16765 /* Combinations of flags. */
16766 {"fs", PSR_f | PSR_s},
16767 {"fx", PSR_f | PSR_x},
16768 {"fc", PSR_f | PSR_c},
16769 {"sf", PSR_s | PSR_f},
16770 {"sx", PSR_s | PSR_x},
16771 {"sc", PSR_s | PSR_c},
16772 {"xf", PSR_x | PSR_f},
16773 {"xs", PSR_x | PSR_s},
16774 {"xc", PSR_x | PSR_c},
16775 {"cf", PSR_c | PSR_f},
16776 {"cs", PSR_c | PSR_s},
16777 {"cx", PSR_c | PSR_x},
16778 {"fsx", PSR_f | PSR_s | PSR_x},
16779 {"fsc", PSR_f | PSR_s | PSR_c},
16780 {"fxs", PSR_f | PSR_x | PSR_s},
16781 {"fxc", PSR_f | PSR_x | PSR_c},
16782 {"fcs", PSR_f | PSR_c | PSR_s},
16783 {"fcx", PSR_f | PSR_c | PSR_x},
16784 {"sfx", PSR_s | PSR_f | PSR_x},
16785 {"sfc", PSR_s | PSR_f | PSR_c},
16786 {"sxf", PSR_s | PSR_x | PSR_f},
16787 {"sxc", PSR_s | PSR_x | PSR_c},
16788 {"scf", PSR_s | PSR_c | PSR_f},
16789 {"scx", PSR_s | PSR_c | PSR_x},
16790 {"xfs", PSR_x | PSR_f | PSR_s},
16791 {"xfc", PSR_x | PSR_f | PSR_c},
16792 {"xsf", PSR_x | PSR_s | PSR_f},
16793 {"xsc", PSR_x | PSR_s | PSR_c},
16794 {"xcf", PSR_x | PSR_c | PSR_f},
16795 {"xcs", PSR_x | PSR_c | PSR_s},
16796 {"cfs", PSR_c | PSR_f | PSR_s},
16797 {"cfx", PSR_c | PSR_f | PSR_x},
16798 {"csf", PSR_c | PSR_s | PSR_f},
16799 {"csx", PSR_c | PSR_s | PSR_x},
16800 {"cxf", PSR_c | PSR_x | PSR_f},
16801 {"cxs", PSR_c | PSR_x | PSR_s},
16802 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16803 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16804 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16805 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16806 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16807 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16808 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16809 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16810 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16811 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16812 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16813 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16814 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16815 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16816 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16817 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16818 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16819 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16820 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16821 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16822 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16823 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16824 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16825 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16828 /* Table of V7M psr names. */
16829 static const struct asm_psr v7m_psrs[] =
16831 {"apsr", 0 }, {"APSR", 0 },
16832 {"iapsr", 1 }, {"IAPSR", 1 },
16833 {"eapsr", 2 }, {"EAPSR", 2 },
16834 {"psr", 3 }, {"PSR", 3 },
16835 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16836 {"ipsr", 5 }, {"IPSR", 5 },
16837 {"epsr", 6 }, {"EPSR", 6 },
16838 {"iepsr", 7 }, {"IEPSR", 7 },
16839 {"msp", 8 }, {"MSP", 8 },
16840 {"psp", 9 }, {"PSP", 9 },
16841 {"primask", 16}, {"PRIMASK", 16},
16842 {"basepri", 17}, {"BASEPRI", 17},
16843 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16844 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16845 {"faultmask", 19}, {"FAULTMASK", 19},
16846 {"control", 20}, {"CONTROL", 20}
16849 /* Table of all shift-in-operand names. */
16850 static const struct asm_shift_name shift_names [] =
16852 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16853 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16854 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16855 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16856 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16857 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16860 /* Table of all explicit relocation names. */
16862 static struct reloc_entry reloc_names[] =
16864 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16865 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16866 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16867 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16868 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16869 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16870 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16871 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16872 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16873 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16874 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16875 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
16876 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
16877 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
16878 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
16879 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
16880 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
16881 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
16885 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16886 static const struct asm_cond conds[] =
16890 {"cs", 0x2}, {"hs", 0x2},
16891 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16905 static struct asm_barrier_opt barrier_opt_names[] =
16907 { "sy", 0xf }, { "SY", 0xf },
16908 { "un", 0x7 }, { "UN", 0x7 },
16909 { "st", 0xe }, { "ST", 0xe },
16910 { "unst", 0x6 }, { "UNST", 0x6 },
16911 { "ish", 0xb }, { "ISH", 0xb },
16912 { "sh", 0xb }, { "SH", 0xb },
16913 { "ishst", 0xa }, { "ISHST", 0xa },
16914 { "shst", 0xa }, { "SHST", 0xa },
16915 { "nsh", 0x7 }, { "NSH", 0x7 },
16916 { "nshst", 0x6 }, { "NSHST", 0x6 },
16917 { "osh", 0x3 }, { "OSH", 0x3 },
16918 { "oshst", 0x2 }, { "OSHST", 0x2 }
16921 /* Table of ARM-format instructions. */
16923 /* Macros for gluing together operand strings. N.B. In all cases
16924 other than OPS0, the trailing OP_stop comes from default
16925 zero-initialization of the unspecified elements of the array. */
16926 #define OPS0() { OP_stop, }
16927 #define OPS1(a) { OP_##a, }
16928 #define OPS2(a,b) { OP_##a,OP_##b, }
16929 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16930 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16931 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16932 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16934 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16935 This is useful when mixing operands for ARM and THUMB, i.e. using the
16936 MIX_ARM_THUMB_OPERANDS macro.
16937 In order to use these macros, prefix the number of operands with _
16939 #define OPS_1(a) { a, }
16940 #define OPS_2(a,b) { a,b, }
16941 #define OPS_3(a,b,c) { a,b,c, }
16942 #define OPS_4(a,b,c,d) { a,b,c,d, }
16943 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16944 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16946 /* These macros abstract out the exact format of the mnemonic table and
16947 save some repeated characters. */
16949 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16950 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16951 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16952 THUMB_VARIANT, do_##ae, do_##te }
16954 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16955 a T_MNEM_xyz enumerator. */
16956 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16957 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16958 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16959 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16961 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16962 infix after the third character. */
16963 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16964 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16965 THUMB_VARIANT, do_##ae, do_##te }
16966 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16967 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16968 THUMB_VARIANT, do_##ae, do_##te }
16969 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16970 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16971 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16972 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16973 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16974 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16975 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16976 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16978 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16979 appear in the condition table. */
16980 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16981 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16982 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16984 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16985 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16986 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16987 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16988 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16989 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16990 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16991 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16992 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16993 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16994 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16995 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16996 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16997 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16998 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16999 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17000 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17001 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17002 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17003 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17005 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17006 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17007 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17008 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17010 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17011 field is still 0xE. Many of the Thumb variants can be executed
17012 conditionally, so this is checked separately. */
17013 #define TUE(mnem, op, top, nops, ops, ae, te) \
17014 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17015 THUMB_VARIANT, do_##ae, do_##te }
17017 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17018 condition code field. */
17019 #define TUF(mnem, op, top, nops, ops, ae, te) \
17020 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17021 THUMB_VARIANT, do_##ae, do_##te }
17023 /* ARM-only variants of all the above. */
17024 #define CE(mnem, op, nops, ops, ae) \
17025 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17027 #define C3(mnem, op, nops, ops, ae) \
17028 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17030 /* Legacy mnemonics that always have conditional infix after the third
17032 #define CL(mnem, op, nops, ops, ae) \
17033 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17034 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17036 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17037 #define cCE(mnem, op, nops, ops, ae) \
17038 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17040 /* Legacy coprocessor instructions where conditional infix and conditional
17041 suffix are ambiguous. For consistency this includes all FPA instructions,
17042 not just the potentially ambiguous ones. */
17043 #define cCL(mnem, op, nops, ops, ae) \
17044 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17045 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17047 /* Coprocessor, takes either a suffix or a position-3 infix
17048 (for an FPA corner case). */
17049 #define C3E(mnem, op, nops, ops, ae) \
17050 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17051 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17053 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17054 { m1 #m2 m3, OPS##nops ops, \
17055 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17056 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17058 #define CM(m1, m2, op, nops, ops, ae) \
17059 xCM_ (m1, , m2, op, nops, ops, ae), \
17060 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17061 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17062 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17063 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17064 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17065 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17066 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17067 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17068 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17069 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17070 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17071 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17072 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17073 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17074 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17075 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17076 xCM_ (m1, le, m2, op, nops, ops, ae), \
17077 xCM_ (m1, al, m2, op, nops, ops, ae)
17079 #define UE(mnem, op, nops, ops, ae) \
17080 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17082 #define UF(mnem, op, nops, ops, ae) \
17083 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17085 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17086 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17087 use the same encoding function for each. */
17088 #define NUF(mnem, op, nops, ops, enc) \
17089 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17090 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17092 /* Neon data processing, version which indirects through neon_enc_tab for
17093 the various overloaded versions of opcodes. */
17094 #define nUF(mnem, op, nops, ops, enc) \
17095 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17096 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17098 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17100 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17101 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17102 THUMB_VARIANT, do_##enc, do_##enc }
17104 #define NCE(mnem, op, nops, ops, enc) \
17105 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17107 #define NCEF(mnem, op, nops, ops, enc) \
17108 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17110 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17111 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17112 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17113 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17115 #define nCE(mnem, op, nops, ops, enc) \
17116 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17118 #define nCEF(mnem, op, nops, ops, enc) \
17119 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17123 static const struct asm_opcode insns[] =
17125 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17126 #define THUMB_VARIANT &arm_ext_v4t
17127 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17128 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17129 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17130 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17131 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17132 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17133 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17134 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17135 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17136 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17137 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17138 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17139 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17140 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17141 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17142 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17144 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17145 for setting PSR flag bits. They are obsolete in V6 and do not
17146 have Thumb equivalents. */
17147 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17148 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17149 CL("tstp", 110f000, 2, (RR, SH), cmp),
17150 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17151 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17152 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17153 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17154 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17155 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17157 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17158 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17159 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17160 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17162 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17163 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17164 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17166 OP_ADDRGLDR),ldst, t_ldst),
17167 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17169 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17170 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17171 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17172 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17173 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17174 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17176 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17177 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17178 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17179 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17182 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17183 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17184 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17186 /* Thumb-compatibility pseudo ops. */
17187 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17188 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17189 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17190 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17191 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17192 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17193 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17194 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17195 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17196 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17197 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17198 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17200 /* These may simplify to neg. */
17201 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17202 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17204 #undef THUMB_VARIANT
17205 #define THUMB_VARIANT & arm_ext_v6
17207 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17209 /* V1 instructions with no Thumb analogue prior to V6T2. */
17210 #undef THUMB_VARIANT
17211 #define THUMB_VARIANT & arm_ext_v6t2
17213 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17214 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17215 CL("teqp", 130f000, 2, (RR, SH), cmp),
17217 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17218 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17219 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17220 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17222 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17223 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17225 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17226 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17228 /* V1 instructions with no Thumb analogue at all. */
17229 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17230 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17232 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17233 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17234 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17235 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17236 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17237 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17238 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17239 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17242 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17243 #undef THUMB_VARIANT
17244 #define THUMB_VARIANT & arm_ext_v4t
17246 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17247 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17249 #undef THUMB_VARIANT
17250 #define THUMB_VARIANT & arm_ext_v6t2
17252 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17253 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17255 /* Generic coprocessor instructions. */
17256 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17257 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17258 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17259 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17260 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17261 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17262 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17265 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17267 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17268 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17271 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17272 #undef THUMB_VARIANT
17273 #define THUMB_VARIANT & arm_ext_msr
17275 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17276 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17279 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17280 #undef THUMB_VARIANT
17281 #define THUMB_VARIANT & arm_ext_v6t2
17283 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17284 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17285 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17286 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17287 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17288 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17289 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17290 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17293 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17294 #undef THUMB_VARIANT
17295 #define THUMB_VARIANT & arm_ext_v4t
17297 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17298 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17299 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17300 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17301 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17302 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17305 #define ARM_VARIANT & arm_ext_v4t_5
17307 /* ARM Architecture 4T. */
17308 /* Note: bx (and blx) are required on V5, even if the processor does
17309 not support Thumb. */
17310 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17313 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17314 #undef THUMB_VARIANT
17315 #define THUMB_VARIANT & arm_ext_v5t
17317 /* Note: blx has 2 variants; the .value coded here is for
17318 BLX(2). Only this variant has conditional execution. */
17319 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17320 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17322 #undef THUMB_VARIANT
17323 #define THUMB_VARIANT & arm_ext_v6t2
17325 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17326 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17327 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17328 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17329 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17330 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17331 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17332 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17335 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17336 #undef THUMB_VARIANT
17337 #define THUMB_VARIANT &arm_ext_v5exp
17339 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17340 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17341 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17342 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17344 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17345 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17347 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17348 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17349 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17350 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17352 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17353 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17354 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17355 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17357 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17358 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17360 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17361 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17362 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17363 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17366 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17367 #undef THUMB_VARIANT
17368 #define THUMB_VARIANT &arm_ext_v6t2
17370 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17371 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17373 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17374 ADDRGLDRS), ldrd, t_ldstd),
17376 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17377 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17380 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17382 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17385 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17386 #undef THUMB_VARIANT
17387 #define THUMB_VARIANT & arm_ext_v6
17389 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17390 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17391 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17392 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17393 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17394 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17395 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17396 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17397 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17398 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17400 #undef THUMB_VARIANT
17401 #define THUMB_VARIANT & arm_ext_v6t2
17403 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17404 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17406 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17407 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17409 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17410 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17412 /* ARM V6 not included in V7M. */
17413 #undef THUMB_VARIANT
17414 #define THUMB_VARIANT & arm_ext_v6_notm
17415 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17416 UF(rfeib, 9900a00, 1, (RRw), rfe),
17417 UF(rfeda, 8100a00, 1, (RRw), rfe),
17418 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17419 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17420 UF(rfefa, 9900a00, 1, (RRw), rfe),
17421 UF(rfeea, 8100a00, 1, (RRw), rfe),
17422 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17423 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17424 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17425 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17426 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17428 /* ARM V6 not included in V7M (eg. integer SIMD). */
17429 #undef THUMB_VARIANT
17430 #define THUMB_VARIANT & arm_ext_v6_dsp
17431 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17432 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17433 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17434 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17435 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17436 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17437 /* Old name for QASX. */
17438 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17439 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17440 /* Old name for QSAX. */
17441 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17442 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17443 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17444 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17445 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17446 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17447 /* Old name for SASX. */
17448 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17449 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17450 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17451 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17452 /* Old name for SHASX. */
17453 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17454 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17455 /* Old name for SHSAX. */
17456 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17457 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17458 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17459 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17460 /* Old name for SSAX. */
17461 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17462 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17463 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17464 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17465 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17466 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17467 /* Old name for UASX. */
17468 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17469 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17470 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17471 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17472 /* Old name for UHASX. */
17473 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17474 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17475 /* Old name for UHSAX. */
17476 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17477 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17478 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17479 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17480 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17481 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17482 /* Old name for UQASX. */
17483 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17484 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17485 /* Old name for UQSAX. */
17486 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17487 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17488 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17489 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17490 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17491 /* Old name for USAX. */
17492 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17493 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17494 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17495 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17496 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17497 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17498 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17499 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17500 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17501 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17502 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17503 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17504 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17505 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17506 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17507 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17508 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17509 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17510 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17511 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17512 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17513 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17514 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17515 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17516 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17517 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17518 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17519 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17520 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17521 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17522 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17523 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17524 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17525 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17528 #define ARM_VARIANT & arm_ext_v6k
17529 #undef THUMB_VARIANT
17530 #define THUMB_VARIANT & arm_ext_v6k
17532 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17533 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17534 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17535 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17537 #undef THUMB_VARIANT
17538 #define THUMB_VARIANT & arm_ext_v6_notm
17539 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17541 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17542 RRnpcb), strexd, t_strexd),
17544 #undef THUMB_VARIANT
17545 #define THUMB_VARIANT & arm_ext_v6t2
17546 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17548 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17550 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17552 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17554 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17557 #define ARM_VARIANT & arm_ext_sec
17558 #undef THUMB_VARIANT
17559 #define THUMB_VARIANT & arm_ext_sec
17561 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17564 #define ARM_VARIANT & arm_ext_virt
17565 #undef THUMB_VARIANT
17566 #define THUMB_VARIANT & arm_ext_virt
17568 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17569 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17572 #define ARM_VARIANT & arm_ext_v6t2
17573 #undef THUMB_VARIANT
17574 #define THUMB_VARIANT & arm_ext_v6t2
17576 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17577 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17578 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17579 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17581 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17582 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17583 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17584 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17586 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17587 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17588 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17589 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17591 /* Thumb-only instructions. */
17593 #define ARM_VARIANT NULL
17594 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17595 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17597 /* ARM does not really have an IT instruction, so always allow it.
17598 The opcode is copied from Thumb in order to allow warnings in
17599 -mimplicit-it=[never | arm] modes. */
17601 #define ARM_VARIANT & arm_ext_v1
17603 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17604 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17605 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17606 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17607 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17608 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17609 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17610 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17611 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17612 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17613 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17614 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17615 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17616 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17617 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17618 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17619 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17620 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17622 /* Thumb2 only instructions. */
17624 #define ARM_VARIANT NULL
17626 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17627 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17628 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17629 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17630 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17631 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17633 /* Hardware division instructions. */
17635 #define ARM_VARIANT & arm_ext_adiv
17636 #undef THUMB_VARIANT
17637 #define THUMB_VARIANT & arm_ext_div
17639 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17640 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17642 /* ARM V6M/V7 instructions. */
17644 #define ARM_VARIANT & arm_ext_barrier
17645 #undef THUMB_VARIANT
17646 #define THUMB_VARIANT & arm_ext_barrier
17648 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17649 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17650 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17652 /* ARM V7 instructions. */
17654 #define ARM_VARIANT & arm_ext_v7
17655 #undef THUMB_VARIANT
17656 #define THUMB_VARIANT & arm_ext_v7
17658 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17659 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17662 #define ARM_VARIANT & arm_ext_mp
17663 #undef THUMB_VARIANT
17664 #define THUMB_VARIANT & arm_ext_mp
17666 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17669 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17671 cCE("wfs", e200110, 1, (RR), rd),
17672 cCE("rfs", e300110, 1, (RR), rd),
17673 cCE("wfc", e400110, 1, (RR), rd),
17674 cCE("rfc", e500110, 1, (RR), rd),
17676 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17677 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17678 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17679 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17681 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17682 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17683 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17684 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17686 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17687 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17688 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17689 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17690 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17691 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17692 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17693 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17694 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17695 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17696 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17697 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17699 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17700 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17701 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17702 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17703 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17704 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17705 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17706 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17707 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17708 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17709 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17710 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17712 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17713 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17714 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17715 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17716 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17717 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17718 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17719 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17720 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17721 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17722 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17723 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17725 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17726 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17727 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17728 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17729 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17730 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17731 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17732 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17733 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17734 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17735 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17736 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17738 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17739 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17740 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17741 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17742 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17743 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17744 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17745 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17746 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17747 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17748 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17749 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17751 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17752 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17753 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17754 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17755 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17756 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17757 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17758 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17759 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17760 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17761 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17762 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17764 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17765 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17766 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17767 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17768 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17769 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17770 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17771 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17772 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17773 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17774 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17775 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17777 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17778 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17779 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17780 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17781 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17782 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17783 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17784 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17785 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17786 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17787 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17788 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17790 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17791 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17792 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17793 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17794 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17795 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17796 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17797 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17798 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17799 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17800 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17801 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17803 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17804 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17805 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17806 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17807 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17808 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17809 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17810 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17811 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17812 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17813 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17814 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17816 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17817 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17818 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17819 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17820 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17821 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17822 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17823 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17824 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17825 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17826 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17827 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17829 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17830 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17831 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17832 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17833 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17834 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17835 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17836 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17837 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17838 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17839 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17840 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17842 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17843 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17844 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17845 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17846 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17847 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17848 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17849 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17850 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17851 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17852 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17853 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17855 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17856 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17857 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17858 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17859 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17860 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17861 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17862 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17863 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17864 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17865 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17866 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17868 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17869 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17870 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17871 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17872 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17873 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17874 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17875 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17876 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17877 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17878 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17879 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17881 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17882 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17883 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17884 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17885 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17886 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17887 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17888 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17889 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17890 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17891 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17892 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17894 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17895 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17896 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17897 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17898 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17899 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17900 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17901 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17902 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
17903 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
17904 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
17905 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
17907 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
17908 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
17909 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
17910 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
17911 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
17912 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17913 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17914 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17915 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
17916 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
17917 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
17918 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
17920 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
17921 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
17922 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
17923 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
17924 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
17925 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17926 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17927 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17928 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
17929 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
17930 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
17931 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
17933 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
17934 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
17935 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
17936 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
17937 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
17938 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17939 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17940 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17941 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
17942 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
17943 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
17944 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
17946 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
17947 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
17948 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
17949 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
17950 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
17951 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17952 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17953 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17954 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
17955 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
17956 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
17957 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
17959 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
17960 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
17961 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
17962 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
17963 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
17964 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17965 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17966 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17967 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
17968 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
17969 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
17970 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
17972 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
17973 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
17974 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
17975 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
17976 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
17977 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17978 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17979 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17980 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
17981 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
17982 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
17983 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
17985 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
17986 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
17987 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
17988 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
17989 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
17990 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17991 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17992 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17993 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
17994 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
17995 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
17996 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
17998 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
17999 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18000 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18001 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18002 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18003 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18004 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18005 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18006 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18007 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18008 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18009 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18011 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18012 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18013 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18014 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18015 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18016 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18017 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18018 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18019 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18020 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18021 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18022 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18024 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18025 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18026 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18027 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18028 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18029 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18030 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18031 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18032 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18033 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18034 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18035 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18037 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18038 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18039 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18040 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18041 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18042 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18043 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18044 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18045 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18046 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18047 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18048 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18050 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18051 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18052 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18053 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18054 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18055 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18056 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18057 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18058 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18059 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18060 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18061 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18063 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18064 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18065 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18066 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18068 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18069 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18070 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18071 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18072 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18073 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18074 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18075 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18076 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18077 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18078 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18079 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18081 /* The implementation of the FIX instruction is broken on some
18082 assemblers, in that it accepts a precision specifier as well as a
18083 rounding specifier, despite the fact that this is meaningless.
18084 To be more compatible, we accept it as well, though of course it
18085 does not set any bits. */
18086 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18087 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18088 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18089 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18090 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18091 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18092 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18093 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18094 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18095 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18096 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18097 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18098 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18100 /* Instructions that were new with the real FPA, call them V2. */
18102 #define ARM_VARIANT & fpu_fpa_ext_v2
18104 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18105 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18106 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18107 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18108 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18109 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18112 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18114 /* Moves and type conversions. */
18115 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18116 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18117 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18118 cCE("fmstat", ef1fa10, 0, (), noargs),
18119 cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
18120 cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
18121 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18122 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18123 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18124 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18125 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18126 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18127 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18128 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18130 /* Memory operations. */
18131 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18132 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18133 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18134 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18135 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18136 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18137 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18138 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18139 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18140 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18141 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18142 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18143 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18144 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18145 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18146 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18147 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18148 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18150 /* Monadic operations. */
18151 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18152 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18153 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18155 /* Dyadic operations. */
18156 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18157 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18158 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18159 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18160 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18161 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18162 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18163 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18164 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18167 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18168 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18169 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18170 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18172 /* Double precision load/store are still present on single precision
18173 implementations. */
18174 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18175 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18176 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18177 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18178 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18179 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18180 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18181 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18182 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18183 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18186 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18188 /* Moves and type conversions. */
18189 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18190 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18191 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18192 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18193 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18194 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18195 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18196 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18197 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18198 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18199 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18200 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18201 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18203 /* Monadic operations. */
18204 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18205 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18206 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18208 /* Dyadic operations. */
18209 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18210 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18211 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18212 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18213 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18214 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18215 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18216 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18217 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18220 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18221 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18222 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18223 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18226 #define ARM_VARIANT & fpu_vfp_ext_v2
18228 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18229 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18230 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18231 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18233 /* Instructions which may belong to either the Neon or VFP instruction sets.
18234 Individual encoder functions perform additional architecture checks. */
18236 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18237 #undef THUMB_VARIANT
18238 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18240 /* These mnemonics are unique to VFP. */
18241 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18242 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18243 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18244 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18245 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18246 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18247 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18248 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18249 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18250 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18252 /* Mnemonics shared by Neon and VFP. */
18253 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18254 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18255 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18257 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18258 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18260 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18261 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18263 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18264 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18265 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18266 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18267 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18268 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18269 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18270 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18272 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18273 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18274 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18275 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18278 /* NOTE: All VMOV encoding is special-cased! */
18279 NCE(vmov, 0, 1, (VMOV), neon_mov),
18280 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18282 #undef THUMB_VARIANT
18283 #define THUMB_VARIANT & fpu_neon_ext_v1
18285 #define ARM_VARIANT & fpu_neon_ext_v1
18287 /* Data processing with three registers of the same length. */
18288 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18289 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18290 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18291 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18292 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18293 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18294 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18295 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18296 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18297 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18298 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18299 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18300 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18301 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18302 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18303 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18304 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18305 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18306 /* If not immediate, fall back to neon_dyadic_i64_su.
18307 shl_imm should accept I8 I16 I32 I64,
18308 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18309 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18310 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18311 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18312 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18313 /* Logic ops, types optional & ignored. */
18314 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18315 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18316 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18317 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18318 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18319 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18320 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18321 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18322 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18323 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18324 /* Bitfield ops, untyped. */
18325 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18326 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18327 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18328 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18329 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18330 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18331 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18332 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18333 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18334 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18335 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18336 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18337 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18338 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18339 back to neon_dyadic_if_su. */
18340 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18341 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18342 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18343 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18344 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18345 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18346 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18347 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18348 /* Comparison. Type I8 I16 I32 F32. */
18349 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18350 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18351 /* As above, D registers only. */
18352 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18353 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18354 /* Int and float variants, signedness unimportant. */
18355 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18356 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18357 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18358 /* Add/sub take types I8 I16 I32 I64 F32. */
18359 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18360 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18361 /* vtst takes sizes 8, 16, 32. */
18362 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18363 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18364 /* VMUL takes I8 I16 I32 F32 P8. */
18365 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18366 /* VQD{R}MULH takes S16 S32. */
18367 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18368 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18369 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18370 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18371 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18372 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18373 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18374 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18375 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18376 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18377 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18378 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18379 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18380 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18381 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18382 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18384 /* Two address, int/float. Types S8 S16 S32 F32. */
18385 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18386 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18388 /* Data processing with two registers and a shift amount. */
18389 /* Right shifts, and variants with rounding.
18390 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18391 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18392 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18393 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18394 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18395 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18396 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18397 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18398 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18399 /* Shift and insert. Sizes accepted 8 16 32 64. */
18400 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18401 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18402 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18403 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18404 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18405 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18406 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18407 /* Right shift immediate, saturating & narrowing, with rounding variants.
18408 Types accepted S16 S32 S64 U16 U32 U64. */
18409 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18410 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18411 /* As above, unsigned. Types accepted S16 S32 S64. */
18412 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18413 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18414 /* Right shift narrowing. Types accepted I16 I32 I64. */
18415 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18416 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18417 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18418 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18419 /* CVT with optional immediate for fixed-point variant. */
18420 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18422 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18423 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18425 /* Data processing, three registers of different lengths. */
18426 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18427 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18428 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18429 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18430 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18431 /* If not scalar, fall back to neon_dyadic_long.
18432 Vector types as above, scalar types S16 S32 U16 U32. */
18433 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18434 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18435 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18436 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18437 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18438 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18439 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18440 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18441 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18442 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18443 /* Saturating doubling multiplies. Types S16 S32. */
18444 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18445 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18446 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18447 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18448 S16 S32 U16 U32. */
18449 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18451 /* Extract. Size 8. */
18452 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18453 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18455 /* Two registers, miscellaneous. */
18456 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18457 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18458 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18459 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18460 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18461 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18462 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18463 /* Vector replicate. Sizes 8 16 32. */
18464 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18465 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18466 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18467 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18468 /* VMOVN. Types I16 I32 I64. */
18469 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18470 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18471 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18472 /* VQMOVUN. Types S16 S32 S64. */
18473 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18474 /* VZIP / VUZP. Sizes 8 16 32. */
18475 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18476 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18477 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18478 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18479 /* VQABS / VQNEG. Types S8 S16 S32. */
18480 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18481 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18482 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18483 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18484 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18485 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18486 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18487 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18488 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18489 /* Reciprocal estimates. Types U32 F32. */
18490 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18491 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18492 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18493 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18494 /* VCLS. Types S8 S16 S32. */
18495 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18496 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18497 /* VCLZ. Types I8 I16 I32. */
18498 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18499 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18500 /* VCNT. Size 8. */
18501 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18502 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18503 /* Two address, untyped. */
18504 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18505 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18506 /* VTRN. Sizes 8 16 32. */
18507 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18508 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18510 /* Table lookup. Size 8. */
18511 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18512 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18514 #undef THUMB_VARIANT
18515 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18517 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18519 /* Neon element/structure load/store. */
18520 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18521 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18522 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18523 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18524 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18525 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18526 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18527 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18529 #undef THUMB_VARIANT
18530 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18532 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18533 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18534 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18535 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18536 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18537 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18538 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18539 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18540 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18541 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18543 #undef THUMB_VARIANT
18544 #define THUMB_VARIANT & fpu_vfp_ext_v3
18546 #define ARM_VARIANT & fpu_vfp_ext_v3
18548 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18549 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18550 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18551 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18552 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18553 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18554 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18555 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18556 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18559 #define ARM_VARIANT &fpu_vfp_ext_fma
18560 #undef THUMB_VARIANT
18561 #define THUMB_VARIANT &fpu_vfp_ext_fma
18562 /* Mnemonics shared by Neon and VFP. These are included in the
18563 VFP FMA variant; NEON and VFP FMA always includes the NEON
18564 FMA instructions. */
18565 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18566 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18567 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18568 the v form should always be used. */
18569 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18570 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18571 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18572 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18573 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18574 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18576 #undef THUMB_VARIANT
18578 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18580 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18581 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18582 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18583 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18584 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18585 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18586 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18587 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18590 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18592 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18593 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18594 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18595 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18596 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18597 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18598 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18599 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18600 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18601 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18602 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18603 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18604 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18605 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18606 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18607 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18608 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18609 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18610 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18611 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18612 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18613 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18614 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18615 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18616 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18617 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18618 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18619 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18620 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18621 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18622 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18623 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18624 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18625 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18626 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18627 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18628 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18629 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18630 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18631 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18632 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18633 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18634 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18635 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18636 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18637 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18638 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18639 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18640 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18641 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18642 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18643 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18644 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18645 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18646 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18647 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18648 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18649 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18650 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18651 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18652 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18653 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18654 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18655 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18656 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18657 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18658 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18659 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18660 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18661 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18662 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18663 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18664 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18665 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18666 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18667 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18668 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18669 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18670 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18671 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18672 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18673 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18674 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18675 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18676 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18677 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18678 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18679 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18680 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18681 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18682 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18683 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18684 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18685 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18686 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18687 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18688 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18689 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18690 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18691 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18692 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18693 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18694 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18695 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18696 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18697 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18698 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18699 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18700 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18701 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18702 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18703 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18704 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18705 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18706 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18707 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18708 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18709 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18710 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18711 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18712 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18713 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18714 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18715 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18716 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18717 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18718 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18719 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18720 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18721 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18722 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18723 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18724 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18725 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18726 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18727 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18728 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18729 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18730 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18731 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18732 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18733 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18734 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18735 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18736 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18737 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18738 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18739 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18740 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18741 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18742 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18743 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18744 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18745 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18746 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18747 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18748 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18749 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18750 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18751 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18752 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18753 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18756 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18758 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18759 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18760 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18761 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18762 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18763 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18764 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18765 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18766 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18767 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18768 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18769 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18770 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18771 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18772 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18773 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18774 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18775 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18776 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18777 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18778 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18779 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18780 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18781 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18782 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18783 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18784 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18785 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18786 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18787 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18788 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18789 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18790 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18791 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18792 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18793 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18794 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18795 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18796 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18797 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18798 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18799 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18800 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18801 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18802 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18803 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18804 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18805 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18806 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18807 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18808 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18809 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18810 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18811 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18812 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18813 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18814 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18817 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18819 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18820 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18821 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18822 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18823 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18824 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18825 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18826 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18827 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18828 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18829 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18830 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18831 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18832 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18833 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18834 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18835 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18836 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18837 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18838 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18839 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18840 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18841 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18842 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18843 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18844 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18845 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18846 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18847 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18848 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18849 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18850 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18851 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18852 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18853 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18854 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18855 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18856 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18857 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18858 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18859 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18860 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18861 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18862 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18863 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18864 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18865 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18866 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18867 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18868 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18869 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18870 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18871 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18872 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18873 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18874 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18875 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18876 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18877 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18878 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18879 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18880 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18881 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18882 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18883 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18884 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18885 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18886 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18887 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18888 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18889 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18890 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18891 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18892 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18893 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18894 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18897 #undef THUMB_VARIANT
18924 /* MD interface: bits in the object file. */
18926 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18927 for use in the a.out file, and stores them in the array pointed to by buf.
18928 This knows about the endian-ness of the target machine and does
18929 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18930 2 (short) and 4 (long) Floating numbers are put out as a series of
18931 LITTLENUMS (shorts, here at least). */
18934 md_number_to_chars (char * buf, valueT val, int n)
18936 if (target_big_endian)
18937 number_to_chars_bigendian (buf, val, n);
18939 number_to_chars_littleendian (buf, val, n);
18943 md_chars_to_number (char * buf, int n)
18946 unsigned char * where = (unsigned char *) buf;
18948 if (target_big_endian)
18953 result |= (*where++ & 255);
18961 result |= (where[n] & 255);
18968 /* MD interface: Sections. */
18970 /* Estimate the size of a frag before relaxing. Assume everything fits in
18974 md_estimate_size_before_relax (fragS * fragp,
18975 segT segtype ATTRIBUTE_UNUSED)
18981 /* Convert a machine dependent frag. */
18984 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
18986 unsigned long insn;
18987 unsigned long old_op;
18995 buf = fragp->fr_literal + fragp->fr_fix;
18997 old_op = bfd_get_16(abfd, buf);
18998 if (fragp->fr_symbol)
19000 exp.X_op = O_symbol;
19001 exp.X_add_symbol = fragp->fr_symbol;
19005 exp.X_op = O_constant;
19007 exp.X_add_number = fragp->fr_offset;
19008 opcode = fragp->fr_subtype;
19011 case T_MNEM_ldr_pc:
19012 case T_MNEM_ldr_pc2:
19013 case T_MNEM_ldr_sp:
19014 case T_MNEM_str_sp:
19021 if (fragp->fr_var == 4)
19023 insn = THUMB_OP32 (opcode);
19024 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19026 insn |= (old_op & 0x700) << 4;
19030 insn |= (old_op & 7) << 12;
19031 insn |= (old_op & 0x38) << 13;
19033 insn |= 0x00000c00;
19034 put_thumb32_insn (buf, insn);
19035 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19039 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19041 pc_rel = (opcode == T_MNEM_ldr_pc2);
19044 if (fragp->fr_var == 4)
19046 insn = THUMB_OP32 (opcode);
19047 insn |= (old_op & 0xf0) << 4;
19048 put_thumb32_insn (buf, insn);
19049 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19053 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19054 exp.X_add_number -= 4;
19062 if (fragp->fr_var == 4)
19064 int r0off = (opcode == T_MNEM_mov
19065 || opcode == T_MNEM_movs) ? 0 : 8;
19066 insn = THUMB_OP32 (opcode);
19067 insn = (insn & 0xe1ffffff) | 0x10000000;
19068 insn |= (old_op & 0x700) << r0off;
19069 put_thumb32_insn (buf, insn);
19070 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19074 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19079 if (fragp->fr_var == 4)
19081 insn = THUMB_OP32(opcode);
19082 put_thumb32_insn (buf, insn);
19083 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19086 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19090 if (fragp->fr_var == 4)
19092 insn = THUMB_OP32(opcode);
19093 insn |= (old_op & 0xf00) << 14;
19094 put_thumb32_insn (buf, insn);
19095 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19098 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19101 case T_MNEM_add_sp:
19102 case T_MNEM_add_pc:
19103 case T_MNEM_inc_sp:
19104 case T_MNEM_dec_sp:
19105 if (fragp->fr_var == 4)
19107 /* ??? Choose between add and addw. */
19108 insn = THUMB_OP32 (opcode);
19109 insn |= (old_op & 0xf0) << 4;
19110 put_thumb32_insn (buf, insn);
19111 if (opcode == T_MNEM_add_pc)
19112 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19114 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19117 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19125 if (fragp->fr_var == 4)
19127 insn = THUMB_OP32 (opcode);
19128 insn |= (old_op & 0xf0) << 4;
19129 insn |= (old_op & 0xf) << 16;
19130 put_thumb32_insn (buf, insn);
19131 if (insn & (1 << 20))
19132 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19134 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19137 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19143 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19144 (enum bfd_reloc_code_real) reloc_type);
19145 fixp->fx_file = fragp->fr_file;
19146 fixp->fx_line = fragp->fr_line;
19147 fragp->fr_fix += fragp->fr_var;
19150 /* Return the size of a relaxable immediate operand instruction.
19151 SHIFT and SIZE specify the form of the allowable immediate. */
19153 relax_immediate (fragS *fragp, int size, int shift)
19159 /* ??? Should be able to do better than this. */
19160 if (fragp->fr_symbol)
19163 low = (1 << shift) - 1;
19164 mask = (1 << (shift + size)) - (1 << shift);
19165 offset = fragp->fr_offset;
19166 /* Force misaligned offsets to 32-bit variant. */
19169 if (offset & ~mask)
19174 /* Get the address of a symbol during relaxation. */
19176 relaxed_symbol_addr (fragS *fragp, long stretch)
19182 sym = fragp->fr_symbol;
19183 sym_frag = symbol_get_frag (sym);
19184 know (S_GET_SEGMENT (sym) != absolute_section
19185 || sym_frag == &zero_address_frag);
19186 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19188 /* If frag has yet to be reached on this pass, assume it will
19189 move by STRETCH just as we did. If this is not so, it will
19190 be because some frag between grows, and that will force
19194 && sym_frag->relax_marker != fragp->relax_marker)
19198 /* Adjust stretch for any alignment frag. Note that if have
19199 been expanding the earlier code, the symbol may be
19200 defined in what appears to be an earlier frag. FIXME:
19201 This doesn't handle the fr_subtype field, which specifies
19202 a maximum number of bytes to skip when doing an
19204 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19206 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19209 stretch = - ((- stretch)
19210 & ~ ((1 << (int) f->fr_offset) - 1));
19212 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19224 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19227 relax_adr (fragS *fragp, asection *sec, long stretch)
19232 /* Assume worst case for symbols not known to be in the same section. */
19233 if (fragp->fr_symbol == NULL
19234 || !S_IS_DEFINED (fragp->fr_symbol)
19235 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19236 || S_IS_WEAK (fragp->fr_symbol))
19239 val = relaxed_symbol_addr (fragp, stretch);
19240 addr = fragp->fr_address + fragp->fr_fix;
19241 addr = (addr + 4) & ~3;
19242 /* Force misaligned targets to 32-bit variant. */
19246 if (val < 0 || val > 1020)
19251 /* Return the size of a relaxable add/sub immediate instruction. */
19253 relax_addsub (fragS *fragp, asection *sec)
19258 buf = fragp->fr_literal + fragp->fr_fix;
19259 op = bfd_get_16(sec->owner, buf);
19260 if ((op & 0xf) == ((op >> 4) & 0xf))
19261 return relax_immediate (fragp, 8, 0);
19263 return relax_immediate (fragp, 3, 0);
19267 /* Return the size of a relaxable branch instruction. BITS is the
19268 size of the offset field in the narrow instruction. */
19271 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19277 /* Assume worst case for symbols not known to be in the same section. */
19278 if (!S_IS_DEFINED (fragp->fr_symbol)
19279 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19280 || S_IS_WEAK (fragp->fr_symbol))
19284 if (S_IS_DEFINED (fragp->fr_symbol)
19285 && ARM_IS_FUNC (fragp->fr_symbol))
19288 /* PR 12532. Global symbols with default visibility might
19289 be preempted, so do not relax relocations to them. */
19290 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19291 && (! S_IS_LOCAL (fragp->fr_symbol)))
19295 val = relaxed_symbol_addr (fragp, stretch);
19296 addr = fragp->fr_address + fragp->fr_fix + 4;
19299 /* Offset is a signed value *2 */
19301 if (val >= limit || val < -limit)
19307 /* Relax a machine dependent frag. This returns the amount by which
19308 the current size of the frag should change. */
19311 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19316 oldsize = fragp->fr_var;
19317 switch (fragp->fr_subtype)
19319 case T_MNEM_ldr_pc2:
19320 newsize = relax_adr (fragp, sec, stretch);
19322 case T_MNEM_ldr_pc:
19323 case T_MNEM_ldr_sp:
19324 case T_MNEM_str_sp:
19325 newsize = relax_immediate (fragp, 8, 2);
19329 newsize = relax_immediate (fragp, 5, 2);
19333 newsize = relax_immediate (fragp, 5, 1);
19337 newsize = relax_immediate (fragp, 5, 0);
19340 newsize = relax_adr (fragp, sec, stretch);
19346 newsize = relax_immediate (fragp, 8, 0);
19349 newsize = relax_branch (fragp, sec, 11, stretch);
19352 newsize = relax_branch (fragp, sec, 8, stretch);
19354 case T_MNEM_add_sp:
19355 case T_MNEM_add_pc:
19356 newsize = relax_immediate (fragp, 8, 2);
19358 case T_MNEM_inc_sp:
19359 case T_MNEM_dec_sp:
19360 newsize = relax_immediate (fragp, 7, 2);
19366 newsize = relax_addsub (fragp, sec);
19372 fragp->fr_var = newsize;
19373 /* Freeze wide instructions that are at or before the same location as
19374 in the previous pass. This avoids infinite loops.
19375 Don't freeze them unconditionally because targets may be artificially
19376 misaligned by the expansion of preceding frags. */
19377 if (stretch <= 0 && newsize > 2)
19379 md_convert_frag (sec->owner, sec, fragp);
19383 return newsize - oldsize;
19386 /* Round up a section size to the appropriate boundary. */
19389 md_section_align (segT segment ATTRIBUTE_UNUSED,
19392 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19393 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19395 /* For a.out, force the section size to be aligned. If we don't do
19396 this, BFD will align it for us, but it will not write out the
19397 final bytes of the section. This may be a bug in BFD, but it is
19398 easier to fix it here since that is how the other a.out targets
19402 align = bfd_get_section_alignment (stdoutput, segment);
19403 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19410 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19411 of an rs_align_code fragment. */
19414 arm_handle_align (fragS * fragP)
19416 static char const arm_noop[2][2][4] =
19419 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19420 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19423 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19424 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19427 static char const thumb_noop[2][2][2] =
19430 {0xc0, 0x46}, /* LE */
19431 {0x46, 0xc0}, /* BE */
19434 {0x00, 0xbf}, /* LE */
19435 {0xbf, 0x00} /* BE */
19438 static char const wide_thumb_noop[2][4] =
19439 { /* Wide Thumb-2 */
19440 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19441 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19444 unsigned bytes, fix, noop_size;
19447 const char *narrow_noop = NULL;
19452 if (fragP->fr_type != rs_align_code)
19455 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19456 p = fragP->fr_literal + fragP->fr_fix;
19459 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19460 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19462 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19464 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19466 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19468 narrow_noop = thumb_noop[1][target_big_endian];
19469 noop = wide_thumb_noop[target_big_endian];
19472 noop = thumb_noop[0][target_big_endian];
19480 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19481 [target_big_endian];
19488 fragP->fr_var = noop_size;
19490 if (bytes & (noop_size - 1))
19492 fix = bytes & (noop_size - 1);
19494 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19496 memset (p, 0, fix);
19503 if (bytes & noop_size)
19505 /* Insert a narrow noop. */
19506 memcpy (p, narrow_noop, noop_size);
19508 bytes -= noop_size;
19512 /* Use wide noops for the remainder */
19516 while (bytes >= noop_size)
19518 memcpy (p, noop, noop_size);
19520 bytes -= noop_size;
19524 fragP->fr_fix += fix;
19527 /* Called from md_do_align. Used to create an alignment
19528 frag in a code section. */
19531 arm_frag_align_code (int n, int max)
19535 /* We assume that there will never be a requirement
19536 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19537 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19542 _("alignments greater than %d bytes not supported in .text sections."),
19543 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19544 as_fatal ("%s", err_msg);
19547 p = frag_var (rs_align_code,
19548 MAX_MEM_FOR_RS_ALIGN_CODE,
19550 (relax_substateT) max,
19557 /* Perform target specific initialisation of a frag.
19558 Note - despite the name this initialisation is not done when the frag
19559 is created, but only when its type is assigned. A frag can be created
19560 and used a long time before its type is set, so beware of assuming that
19561 this initialisationis performed first. */
19565 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19567 /* Record whether this frag is in an ARM or a THUMB area. */
19568 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19571 #else /* OBJ_ELF is defined. */
19573 arm_init_frag (fragS * fragP, int max_chars)
19575 /* If the current ARM vs THUMB mode has not already
19576 been recorded into this frag then do so now. */
19577 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19579 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19581 /* Record a mapping symbol for alignment frags. We will delete this
19582 later if the alignment ends up empty. */
19583 switch (fragP->fr_type)
19586 case rs_align_test:
19588 mapping_state_2 (MAP_DATA, max_chars);
19590 case rs_align_code:
19591 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19599 /* When we change sections we need to issue a new mapping symbol. */
19602 arm_elf_change_section (void)
19604 /* Link an unlinked unwind index table section to the .text section. */
19605 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19606 && elf_linked_to_section (now_seg) == NULL)
19607 elf_linked_to_section (now_seg) = text_section;
19611 arm_elf_section_type (const char * str, size_t len)
19613 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19614 return SHT_ARM_EXIDX;
19619 /* Code to deal with unwinding tables. */
19621 static void add_unwind_adjustsp (offsetT);
19623 /* Generate any deferred unwind frame offset. */
19626 flush_pending_unwind (void)
19630 offset = unwind.pending_offset;
19631 unwind.pending_offset = 0;
19633 add_unwind_adjustsp (offset);
19636 /* Add an opcode to this list for this function. Two-byte opcodes should
19637 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19641 add_unwind_opcode (valueT op, int length)
19643 /* Add any deferred stack adjustment. */
19644 if (unwind.pending_offset)
19645 flush_pending_unwind ();
19647 unwind.sp_restored = 0;
19649 if (unwind.opcode_count + length > unwind.opcode_alloc)
19651 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19652 if (unwind.opcodes)
19653 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19654 unwind.opcode_alloc);
19656 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19661 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19663 unwind.opcode_count++;
19667 /* Add unwind opcodes to adjust the stack pointer. */
19670 add_unwind_adjustsp (offsetT offset)
19674 if (offset > 0x200)
19676 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19681 /* Long form: 0xb2, uleb128. */
19682 /* This might not fit in a word so add the individual bytes,
19683 remembering the list is built in reverse order. */
19684 o = (valueT) ((offset - 0x204) >> 2);
19686 add_unwind_opcode (0, 1);
19688 /* Calculate the uleb128 encoding of the offset. */
19692 bytes[n] = o & 0x7f;
19698 /* Add the insn. */
19700 add_unwind_opcode (bytes[n - 1], 1);
19701 add_unwind_opcode (0xb2, 1);
19703 else if (offset > 0x100)
19705 /* Two short opcodes. */
19706 add_unwind_opcode (0x3f, 1);
19707 op = (offset - 0x104) >> 2;
19708 add_unwind_opcode (op, 1);
19710 else if (offset > 0)
19712 /* Short opcode. */
19713 op = (offset - 4) >> 2;
19714 add_unwind_opcode (op, 1);
19716 else if (offset < 0)
19719 while (offset > 0x100)
19721 add_unwind_opcode (0x7f, 1);
19724 op = ((offset - 4) >> 2) | 0x40;
19725 add_unwind_opcode (op, 1);
19729 /* Finish the list of unwind opcodes for this function. */
19731 finish_unwind_opcodes (void)
19735 if (unwind.fp_used)
19737 /* Adjust sp as necessary. */
19738 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19739 flush_pending_unwind ();
19741 /* After restoring sp from the frame pointer. */
19742 op = 0x90 | unwind.fp_reg;
19743 add_unwind_opcode (op, 1);
19746 flush_pending_unwind ();
19750 /* Start an exception table entry. If idx is nonzero this is an index table
19754 start_unwind_section (const segT text_seg, int idx)
19756 const char * text_name;
19757 const char * prefix;
19758 const char * prefix_once;
19759 const char * group_name;
19763 size_t sec_name_len;
19770 prefix = ELF_STRING_ARM_unwind;
19771 prefix_once = ELF_STRING_ARM_unwind_once;
19772 type = SHT_ARM_EXIDX;
19776 prefix = ELF_STRING_ARM_unwind_info;
19777 prefix_once = ELF_STRING_ARM_unwind_info_once;
19778 type = SHT_PROGBITS;
19781 text_name = segment_name (text_seg);
19782 if (streq (text_name, ".text"))
19785 if (strncmp (text_name, ".gnu.linkonce.t.",
19786 strlen (".gnu.linkonce.t.")) == 0)
19788 prefix = prefix_once;
19789 text_name += strlen (".gnu.linkonce.t.");
19792 prefix_len = strlen (prefix);
19793 text_len = strlen (text_name);
19794 sec_name_len = prefix_len + text_len;
19795 sec_name = (char *) xmalloc (sec_name_len + 1);
19796 memcpy (sec_name, prefix, prefix_len);
19797 memcpy (sec_name + prefix_len, text_name, text_len);
19798 sec_name[prefix_len + text_len] = '\0';
19804 /* Handle COMDAT group. */
19805 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19807 group_name = elf_group_name (text_seg);
19808 if (group_name == NULL)
19810 as_bad (_("Group section `%s' has no group signature"),
19811 segment_name (text_seg));
19812 ignore_rest_of_line ();
19815 flags |= SHF_GROUP;
19819 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19821 /* Set the section link for index tables. */
19823 elf_linked_to_section (now_seg) = text_seg;
19827 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19828 personality routine data. Returns zero, or the index table value for
19829 and inline entry. */
19832 create_unwind_entry (int have_data)
19837 /* The current word of data. */
19839 /* The number of bytes left in this word. */
19842 finish_unwind_opcodes ();
19844 /* Remember the current text section. */
19845 unwind.saved_seg = now_seg;
19846 unwind.saved_subseg = now_subseg;
19848 start_unwind_section (now_seg, 0);
19850 if (unwind.personality_routine == NULL)
19852 if (unwind.personality_index == -2)
19855 as_bad (_("handlerdata in cantunwind frame"));
19856 return 1; /* EXIDX_CANTUNWIND. */
19859 /* Use a default personality routine if none is specified. */
19860 if (unwind.personality_index == -1)
19862 if (unwind.opcode_count > 3)
19863 unwind.personality_index = 1;
19865 unwind.personality_index = 0;
19868 /* Space for the personality routine entry. */
19869 if (unwind.personality_index == 0)
19871 if (unwind.opcode_count > 3)
19872 as_bad (_("too many unwind opcodes for personality routine 0"));
19876 /* All the data is inline in the index table. */
19879 while (unwind.opcode_count > 0)
19881 unwind.opcode_count--;
19882 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19886 /* Pad with "finish" opcodes. */
19888 data = (data << 8) | 0xb0;
19895 /* We get two opcodes "free" in the first word. */
19896 size = unwind.opcode_count - 2;
19899 /* An extra byte is required for the opcode count. */
19900 size = unwind.opcode_count + 1;
19902 size = (size + 3) >> 2;
19904 as_bad (_("too many unwind opcodes"));
19906 frag_align (2, 0, 0);
19907 record_alignment (now_seg, 2);
19908 unwind.table_entry = expr_build_dot ();
19910 /* Allocate the table entry. */
19911 ptr = frag_more ((size << 2) + 4);
19912 where = frag_now_fix () - ((size << 2) + 4);
19914 switch (unwind.personality_index)
19917 /* ??? Should this be a PLT generating relocation? */
19918 /* Custom personality routine. */
19919 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
19920 BFD_RELOC_ARM_PREL31);
19925 /* Set the first byte to the number of additional words. */
19930 /* ABI defined personality routines. */
19932 /* Three opcodes bytes are packed into the first word. */
19939 /* The size and first two opcode bytes go in the first word. */
19940 data = ((0x80 + unwind.personality_index) << 8) | size;
19945 /* Should never happen. */
19949 /* Pack the opcodes into words (MSB first), reversing the list at the same
19951 while (unwind.opcode_count > 0)
19955 md_number_to_chars (ptr, data, 4);
19960 unwind.opcode_count--;
19962 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19965 /* Finish off the last word. */
19968 /* Pad with "finish" opcodes. */
19970 data = (data << 8) | 0xb0;
19972 md_number_to_chars (ptr, data, 4);
19977 /* Add an empty descriptor if there is no user-specified data. */
19978 ptr = frag_more (4);
19979 md_number_to_chars (ptr, 0, 4);
19986 /* Initialize the DWARF-2 unwind information for this procedure. */
19989 tc_arm_frame_initial_instructions (void)
19991 cfi_add_CFA_def_cfa (REG_SP, 0);
19993 #endif /* OBJ_ELF */
19995 /* Convert REGNAME to a DWARF-2 register number. */
19998 tc_arm_regname_to_dw2regnum (char *regname)
20000 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20010 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20014 exp.X_op = O_secrel;
20015 exp.X_add_symbol = symbol;
20016 exp.X_add_number = 0;
20017 emit_expr (&exp, size);
20021 /* MD interface: Symbol and relocation handling. */
20023 /* Return the address within the segment that a PC-relative fixup is
20024 relative to. For ARM, PC-relative fixups applied to instructions
20025 are generally relative to the location of the fixup plus 8 bytes.
20026 Thumb branches are offset by 4, and Thumb loads relative to PC
20027 require special handling. */
20030 md_pcrel_from_section (fixS * fixP, segT seg)
20032 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20034 /* If this is pc-relative and we are going to emit a relocation
20035 then we just want to put out any pipeline compensation that the linker
20036 will need. Otherwise we want to use the calculated base.
20037 For WinCE we skip the bias for externals as well, since this
20038 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20040 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20041 || (arm_force_relocation (fixP)
20043 && !S_IS_EXTERNAL (fixP->fx_addsy)
20049 switch (fixP->fx_r_type)
20051 /* PC relative addressing on the Thumb is slightly odd as the
20052 bottom two bits of the PC are forced to zero for the
20053 calculation. This happens *after* application of the
20054 pipeline offset. However, Thumb adrl already adjusts for
20055 this, so we need not do it again. */
20056 case BFD_RELOC_ARM_THUMB_ADD:
20059 case BFD_RELOC_ARM_THUMB_OFFSET:
20060 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20061 case BFD_RELOC_ARM_T32_ADD_PC12:
20062 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20063 return (base + 4) & ~3;
20065 /* Thumb branches are simply offset by +4. */
20066 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20067 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20068 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20069 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20070 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20073 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20075 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20076 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20077 && ARM_IS_FUNC (fixP->fx_addsy)
20078 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20079 base = fixP->fx_where + fixP->fx_frag->fr_address;
20082 /* BLX is like branches above, but forces the low two bits of PC to
20084 case BFD_RELOC_THUMB_PCREL_BLX:
20086 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20087 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20088 && THUMB_IS_FUNC (fixP->fx_addsy)
20089 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20090 base = fixP->fx_where + fixP->fx_frag->fr_address;
20091 return (base + 4) & ~3;
20093 /* ARM mode branches are offset by +8. However, the Windows CE
20094 loader expects the relocation not to take this into account. */
20095 case BFD_RELOC_ARM_PCREL_BLX:
20097 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20098 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20099 && ARM_IS_FUNC (fixP->fx_addsy)
20100 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20101 base = fixP->fx_where + fixP->fx_frag->fr_address;
20104 case BFD_RELOC_ARM_PCREL_CALL:
20106 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20107 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20108 && THUMB_IS_FUNC (fixP->fx_addsy)
20109 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20110 base = fixP->fx_where + fixP->fx_frag->fr_address;
20113 case BFD_RELOC_ARM_PCREL_BRANCH:
20114 case BFD_RELOC_ARM_PCREL_JUMP:
20115 case BFD_RELOC_ARM_PLT32:
20117 /* When handling fixups immediately, because we have already
20118 discovered the value of a symbol, or the address of the frag involved
20119 we must account for the offset by +8, as the OS loader will never see the reloc.
20120 see fixup_segment() in write.c
20121 The S_IS_EXTERNAL test handles the case of global symbols.
20122 Those need the calculated base, not just the pipe compensation the linker will need. */
20124 && fixP->fx_addsy != NULL
20125 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20126 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20134 /* ARM mode loads relative to PC are also offset by +8. Unlike
20135 branches, the Windows CE loader *does* expect the relocation
20136 to take this into account. */
20137 case BFD_RELOC_ARM_OFFSET_IMM:
20138 case BFD_RELOC_ARM_OFFSET_IMM8:
20139 case BFD_RELOC_ARM_HWLITERAL:
20140 case BFD_RELOC_ARM_LITERAL:
20141 case BFD_RELOC_ARM_CP_OFF_IMM:
20145 /* Other PC-relative relocations are un-offset. */
20151 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20152 Otherwise we have no need to default values of symbols. */
20155 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20158 if (name[0] == '_' && name[1] == 'G'
20159 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20163 if (symbol_find (name))
20164 as_bad (_("GOT already in the symbol table"));
20166 GOT_symbol = symbol_new (name, undefined_section,
20167 (valueT) 0, & zero_address_frag);
20177 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20178 computed as two separate immediate values, added together. We
20179 already know that this value cannot be computed by just one ARM
20182 static unsigned int
20183 validate_immediate_twopart (unsigned int val,
20184 unsigned int * highpart)
20189 for (i = 0; i < 32; i += 2)
20190 if (((a = rotate_left (val, i)) & 0xff) != 0)
20196 * highpart = (a >> 8) | ((i + 24) << 7);
20198 else if (a & 0xff0000)
20200 if (a & 0xff000000)
20202 * highpart = (a >> 16) | ((i + 16) << 7);
20206 gas_assert (a & 0xff000000);
20207 * highpart = (a >> 24) | ((i + 8) << 7);
20210 return (a & 0xff) | (i << 7);
20217 validate_offset_imm (unsigned int val, int hwse)
20219 if ((hwse && val > 255) || val > 4095)
20224 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20225 negative immediate constant by altering the instruction. A bit of
20230 by inverting the second operand, and
20233 by negating the second operand. */
20236 negate_data_op (unsigned long * instruction,
20237 unsigned long value)
20240 unsigned long negated, inverted;
20242 negated = encode_arm_immediate (-value);
20243 inverted = encode_arm_immediate (~value);
20245 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20248 /* First negates. */
20249 case OPCODE_SUB: /* ADD <-> SUB */
20250 new_inst = OPCODE_ADD;
20255 new_inst = OPCODE_SUB;
20259 case OPCODE_CMP: /* CMP <-> CMN */
20260 new_inst = OPCODE_CMN;
20265 new_inst = OPCODE_CMP;
20269 /* Now Inverted ops. */
20270 case OPCODE_MOV: /* MOV <-> MVN */
20271 new_inst = OPCODE_MVN;
20276 new_inst = OPCODE_MOV;
20280 case OPCODE_AND: /* AND <-> BIC */
20281 new_inst = OPCODE_BIC;
20286 new_inst = OPCODE_AND;
20290 case OPCODE_ADC: /* ADC <-> SBC */
20291 new_inst = OPCODE_SBC;
20296 new_inst = OPCODE_ADC;
20300 /* We cannot do anything. */
20305 if (value == (unsigned) FAIL)
20308 *instruction &= OPCODE_MASK;
20309 *instruction |= new_inst << DATA_OP_SHIFT;
20313 /* Like negate_data_op, but for Thumb-2. */
20315 static unsigned int
20316 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20320 unsigned int negated, inverted;
20322 negated = encode_thumb32_immediate (-value);
20323 inverted = encode_thumb32_immediate (~value);
20325 rd = (*instruction >> 8) & 0xf;
20326 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20329 /* ADD <-> SUB. Includes CMP <-> CMN. */
20330 case T2_OPCODE_SUB:
20331 new_inst = T2_OPCODE_ADD;
20335 case T2_OPCODE_ADD:
20336 new_inst = T2_OPCODE_SUB;
20340 /* ORR <-> ORN. Includes MOV <-> MVN. */
20341 case T2_OPCODE_ORR:
20342 new_inst = T2_OPCODE_ORN;
20346 case T2_OPCODE_ORN:
20347 new_inst = T2_OPCODE_ORR;
20351 /* AND <-> BIC. TST has no inverted equivalent. */
20352 case T2_OPCODE_AND:
20353 new_inst = T2_OPCODE_BIC;
20360 case T2_OPCODE_BIC:
20361 new_inst = T2_OPCODE_AND;
20366 case T2_OPCODE_ADC:
20367 new_inst = T2_OPCODE_SBC;
20371 case T2_OPCODE_SBC:
20372 new_inst = T2_OPCODE_ADC;
20376 /* We cannot do anything. */
20381 if (value == (unsigned int)FAIL)
20384 *instruction &= T2_OPCODE_MASK;
20385 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20389 /* Read a 32-bit thumb instruction from buf. */
20390 static unsigned long
20391 get_thumb32_insn (char * buf)
20393 unsigned long insn;
20394 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20395 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20401 /* We usually want to set the low bit on the address of thumb function
20402 symbols. In particular .word foo - . should have the low bit set.
20403 Generic code tries to fold the difference of two symbols to
20404 a constant. Prevent this and force a relocation when the first symbols
20405 is a thumb function. */
20408 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20410 if (op == O_subtract
20411 && l->X_op == O_symbol
20412 && r->X_op == O_symbol
20413 && THUMB_IS_FUNC (l->X_add_symbol))
20415 l->X_op = O_subtract;
20416 l->X_op_symbol = r->X_add_symbol;
20417 l->X_add_number -= r->X_add_number;
20421 /* Process as normal. */
20425 /* Encode Thumb2 unconditional branches and calls. The encoding
20426 for the 2 are identical for the immediate values. */
20429 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20431 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20434 addressT S, I1, I2, lo, hi;
20436 S = (value >> 24) & 0x01;
20437 I1 = (value >> 23) & 0x01;
20438 I2 = (value >> 22) & 0x01;
20439 hi = (value >> 12) & 0x3ff;
20440 lo = (value >> 1) & 0x7ff;
20441 newval = md_chars_to_number (buf, THUMB_SIZE);
20442 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20443 newval |= (S << 10) | hi;
20444 newval2 &= ~T2I1I2MASK;
20445 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20446 md_number_to_chars (buf, newval, THUMB_SIZE);
20447 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20451 md_apply_fix (fixS * fixP,
20455 offsetT value = * valP;
20457 unsigned int newimm;
20458 unsigned long temp;
20460 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20462 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20464 /* Note whether this will delete the relocation. */
20466 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20469 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20470 consistency with the behaviour on 32-bit hosts. Remember value
20472 value &= 0xffffffff;
20473 value ^= 0x80000000;
20474 value -= 0x80000000;
20477 fixP->fx_addnumber = value;
20479 /* Same treatment for fixP->fx_offset. */
20480 fixP->fx_offset &= 0xffffffff;
20481 fixP->fx_offset ^= 0x80000000;
20482 fixP->fx_offset -= 0x80000000;
20484 switch (fixP->fx_r_type)
20486 case BFD_RELOC_NONE:
20487 /* This will need to go in the object file. */
20491 case BFD_RELOC_ARM_IMMEDIATE:
20492 /* We claim that this fixup has been processed here,
20493 even if in fact we generate an error because we do
20494 not have a reloc for it, so tc_gen_reloc will reject it. */
20497 if (fixP->fx_addsy)
20499 const char *msg = 0;
20501 if (! S_IS_DEFINED (fixP->fx_addsy))
20502 msg = _("undefined symbol %s used as an immediate value");
20503 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20504 msg = _("symbol %s is in a different section");
20505 else if (S_IS_WEAK (fixP->fx_addsy))
20506 msg = _("symbol %s is weak and may be overridden later");
20510 as_bad_where (fixP->fx_file, fixP->fx_line,
20511 msg, S_GET_NAME (fixP->fx_addsy));
20516 newimm = encode_arm_immediate (value);
20517 temp = md_chars_to_number (buf, INSN_SIZE);
20519 /* If the instruction will fail, see if we can fix things up by
20520 changing the opcode. */
20521 if (newimm == (unsigned int) FAIL
20522 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
20524 as_bad_where (fixP->fx_file, fixP->fx_line,
20525 _("invalid constant (%lx) after fixup"),
20526 (unsigned long) value);
20530 newimm |= (temp & 0xfffff000);
20531 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20534 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20536 unsigned int highpart = 0;
20537 unsigned int newinsn = 0xe1a00000; /* nop. */
20539 if (fixP->fx_addsy)
20541 const char *msg = 0;
20543 if (! S_IS_DEFINED (fixP->fx_addsy))
20544 msg = _("undefined symbol %s used as an immediate value");
20545 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20546 msg = _("symbol %s is in a different section");
20547 else if (S_IS_WEAK (fixP->fx_addsy))
20548 msg = _("symbol %s is weak and may be overridden later");
20552 as_bad_where (fixP->fx_file, fixP->fx_line,
20553 msg, S_GET_NAME (fixP->fx_addsy));
20558 newimm = encode_arm_immediate (value);
20559 temp = md_chars_to_number (buf, INSN_SIZE);
20561 /* If the instruction will fail, see if we can fix things up by
20562 changing the opcode. */
20563 if (newimm == (unsigned int) FAIL
20564 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20566 /* No ? OK - try using two ADD instructions to generate
20568 newimm = validate_immediate_twopart (value, & highpart);
20570 /* Yes - then make sure that the second instruction is
20572 if (newimm != (unsigned int) FAIL)
20574 /* Still No ? Try using a negated value. */
20575 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20576 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20577 /* Otherwise - give up. */
20580 as_bad_where (fixP->fx_file, fixP->fx_line,
20581 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20586 /* Replace the first operand in the 2nd instruction (which
20587 is the PC) with the destination register. We have
20588 already added in the PC in the first instruction and we
20589 do not want to do it again. */
20590 newinsn &= ~ 0xf0000;
20591 newinsn |= ((newinsn & 0x0f000) << 4);
20594 newimm |= (temp & 0xfffff000);
20595 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20597 highpart |= (newinsn & 0xfffff000);
20598 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20602 case BFD_RELOC_ARM_OFFSET_IMM:
20603 if (!fixP->fx_done && seg->use_rela_p)
20606 case BFD_RELOC_ARM_LITERAL:
20612 if (validate_offset_imm (value, 0) == FAIL)
20614 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20615 as_bad_where (fixP->fx_file, fixP->fx_line,
20616 _("invalid literal constant: pool needs to be closer"));
20618 as_bad_where (fixP->fx_file, fixP->fx_line,
20619 _("bad immediate value for offset (%ld)"),
20624 newval = md_chars_to_number (buf, INSN_SIZE);
20626 newval &= 0xfffff000;
20629 newval &= 0xff7ff000;
20630 newval |= value | (sign ? INDEX_UP : 0);
20632 md_number_to_chars (buf, newval, INSN_SIZE);
20635 case BFD_RELOC_ARM_OFFSET_IMM8:
20636 case BFD_RELOC_ARM_HWLITERAL:
20642 if (validate_offset_imm (value, 1) == FAIL)
20644 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20645 as_bad_where (fixP->fx_file, fixP->fx_line,
20646 _("invalid literal constant: pool needs to be closer"));
20648 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20653 newval = md_chars_to_number (buf, INSN_SIZE);
20655 newval &= 0xfffff0f0;
20658 newval &= 0xff7ff0f0;
20659 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20661 md_number_to_chars (buf, newval, INSN_SIZE);
20664 case BFD_RELOC_ARM_T32_OFFSET_U8:
20665 if (value < 0 || value > 1020 || value % 4 != 0)
20666 as_bad_where (fixP->fx_file, fixP->fx_line,
20667 _("bad immediate value for offset (%ld)"), (long) value);
20670 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20672 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20675 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20676 /* This is a complicated relocation used for all varieties of Thumb32
20677 load/store instruction with immediate offset:
20679 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20680 *4, optional writeback(W)
20681 (doubleword load/store)
20683 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20684 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20685 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20686 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20687 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20689 Uppercase letters indicate bits that are already encoded at
20690 this point. Lowercase letters are our problem. For the
20691 second block of instructions, the secondary opcode nybble
20692 (bits 8..11) is present, and bit 23 is zero, even if this is
20693 a PC-relative operation. */
20694 newval = md_chars_to_number (buf, THUMB_SIZE);
20696 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20698 if ((newval & 0xf0000000) == 0xe0000000)
20700 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20702 newval |= (1 << 23);
20705 if (value % 4 != 0)
20707 as_bad_where (fixP->fx_file, fixP->fx_line,
20708 _("offset not a multiple of 4"));
20714 as_bad_where (fixP->fx_file, fixP->fx_line,
20715 _("offset out of range"));
20720 else if ((newval & 0x000f0000) == 0x000f0000)
20722 /* PC-relative, 12-bit offset. */
20724 newval |= (1 << 23);
20729 as_bad_where (fixP->fx_file, fixP->fx_line,
20730 _("offset out of range"));
20735 else if ((newval & 0x00000100) == 0x00000100)
20737 /* Writeback: 8-bit, +/- offset. */
20739 newval |= (1 << 9);
20744 as_bad_where (fixP->fx_file, fixP->fx_line,
20745 _("offset out of range"));
20750 else if ((newval & 0x00000f00) == 0x00000e00)
20752 /* T-instruction: positive 8-bit offset. */
20753 if (value < 0 || value > 0xff)
20755 as_bad_where (fixP->fx_file, fixP->fx_line,
20756 _("offset out of range"));
20764 /* Positive 12-bit or negative 8-bit offset. */
20768 newval |= (1 << 23);
20778 as_bad_where (fixP->fx_file, fixP->fx_line,
20779 _("offset out of range"));
20786 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20787 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20790 case BFD_RELOC_ARM_SHIFT_IMM:
20791 newval = md_chars_to_number (buf, INSN_SIZE);
20792 if (((unsigned long) value) > 32
20794 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20796 as_bad_where (fixP->fx_file, fixP->fx_line,
20797 _("shift expression is too large"));
20802 /* Shifts of zero must be done as lsl. */
20804 else if (value == 32)
20806 newval &= 0xfffff07f;
20807 newval |= (value & 0x1f) << 7;
20808 md_number_to_chars (buf, newval, INSN_SIZE);
20811 case BFD_RELOC_ARM_T32_IMMEDIATE:
20812 case BFD_RELOC_ARM_T32_ADD_IMM:
20813 case BFD_RELOC_ARM_T32_IMM12:
20814 case BFD_RELOC_ARM_T32_ADD_PC12:
20815 /* We claim that this fixup has been processed here,
20816 even if in fact we generate an error because we do
20817 not have a reloc for it, so tc_gen_reloc will reject it. */
20821 && ! S_IS_DEFINED (fixP->fx_addsy))
20823 as_bad_where (fixP->fx_file, fixP->fx_line,
20824 _("undefined symbol %s used as an immediate value"),
20825 S_GET_NAME (fixP->fx_addsy));
20829 newval = md_chars_to_number (buf, THUMB_SIZE);
20831 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20834 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20835 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20837 newimm = encode_thumb32_immediate (value);
20838 if (newimm == (unsigned int) FAIL)
20839 newimm = thumb32_negate_data_op (&newval, value);
20841 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20842 && newimm == (unsigned int) FAIL)
20844 /* Turn add/sum into addw/subw. */
20845 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20846 newval = (newval & 0xfeffffff) | 0x02000000;
20847 /* No flat 12-bit imm encoding for addsw/subsw. */
20848 if ((newval & 0x00100000) == 0)
20850 /* 12 bit immediate for addw/subw. */
20854 newval ^= 0x00a00000;
20857 newimm = (unsigned int) FAIL;
20863 if (newimm == (unsigned int)FAIL)
20865 as_bad_where (fixP->fx_file, fixP->fx_line,
20866 _("invalid constant (%lx) after fixup"),
20867 (unsigned long) value);
20871 newval |= (newimm & 0x800) << 15;
20872 newval |= (newimm & 0x700) << 4;
20873 newval |= (newimm & 0x0ff);
20875 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
20876 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
20879 case BFD_RELOC_ARM_SMC:
20880 if (((unsigned long) value) > 0xffff)
20881 as_bad_where (fixP->fx_file, fixP->fx_line,
20882 _("invalid smc expression"));
20883 newval = md_chars_to_number (buf, INSN_SIZE);
20884 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20885 md_number_to_chars (buf, newval, INSN_SIZE);
20888 case BFD_RELOC_ARM_HVC:
20889 if (((unsigned long) value) > 0xffff)
20890 as_bad_where (fixP->fx_file, fixP->fx_line,
20891 _("invalid hvc expression"));
20892 newval = md_chars_to_number (buf, INSN_SIZE);
20893 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20894 md_number_to_chars (buf, newval, INSN_SIZE);
20897 case BFD_RELOC_ARM_SWI:
20898 if (fixP->tc_fix_data != 0)
20900 if (((unsigned long) value) > 0xff)
20901 as_bad_where (fixP->fx_file, fixP->fx_line,
20902 _("invalid swi expression"));
20903 newval = md_chars_to_number (buf, THUMB_SIZE);
20905 md_number_to_chars (buf, newval, THUMB_SIZE);
20909 if (((unsigned long) value) > 0x00ffffff)
20910 as_bad_where (fixP->fx_file, fixP->fx_line,
20911 _("invalid swi expression"));
20912 newval = md_chars_to_number (buf, INSN_SIZE);
20914 md_number_to_chars (buf, newval, INSN_SIZE);
20918 case BFD_RELOC_ARM_MULTI:
20919 if (((unsigned long) value) > 0xffff)
20920 as_bad_where (fixP->fx_file, fixP->fx_line,
20921 _("invalid expression in load/store multiple"));
20922 newval = value | md_chars_to_number (buf, INSN_SIZE);
20923 md_number_to_chars (buf, newval, INSN_SIZE);
20927 case BFD_RELOC_ARM_PCREL_CALL:
20929 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20931 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20932 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20933 && THUMB_IS_FUNC (fixP->fx_addsy))
20934 /* Flip the bl to blx. This is a simple flip
20935 bit here because we generate PCREL_CALL for
20936 unconditional bls. */
20938 newval = md_chars_to_number (buf, INSN_SIZE);
20939 newval = newval | 0x10000000;
20940 md_number_to_chars (buf, newval, INSN_SIZE);
20946 goto arm_branch_common;
20948 case BFD_RELOC_ARM_PCREL_JUMP:
20949 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20951 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20952 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20953 && THUMB_IS_FUNC (fixP->fx_addsy))
20955 /* This would map to a bl<cond>, b<cond>,
20956 b<always> to a Thumb function. We
20957 need to force a relocation for this particular
20959 newval = md_chars_to_number (buf, INSN_SIZE);
20963 case BFD_RELOC_ARM_PLT32:
20965 case BFD_RELOC_ARM_PCREL_BRANCH:
20967 goto arm_branch_common;
20969 case BFD_RELOC_ARM_PCREL_BLX:
20972 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20974 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20975 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20976 && ARM_IS_FUNC (fixP->fx_addsy))
20978 /* Flip the blx to a bl and warn. */
20979 const char *name = S_GET_NAME (fixP->fx_addsy);
20980 newval = 0xeb000000;
20981 as_warn_where (fixP->fx_file, fixP->fx_line,
20982 _("blx to '%s' an ARM ISA state function changed to bl"),
20984 md_number_to_chars (buf, newval, INSN_SIZE);
20990 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
20991 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
20995 /* We are going to store value (shifted right by two) in the
20996 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20997 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20998 also be be clear. */
21000 as_bad_where (fixP->fx_file, fixP->fx_line,
21001 _("misaligned branch destination"));
21002 if ((value & (offsetT)0xfe000000) != (offsetT)0
21003 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21004 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21006 if (fixP->fx_done || !seg->use_rela_p)
21008 newval = md_chars_to_number (buf, INSN_SIZE);
21009 newval |= (value >> 2) & 0x00ffffff;
21010 /* Set the H bit on BLX instructions. */
21014 newval |= 0x01000000;
21016 newval &= ~0x01000000;
21018 md_number_to_chars (buf, newval, INSN_SIZE);
21022 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21023 /* CBZ can only branch forward. */
21025 /* Attempts to use CBZ to branch to the next instruction
21026 (which, strictly speaking, are prohibited) will be turned into
21029 FIXME: It may be better to remove the instruction completely and
21030 perform relaxation. */
21033 newval = md_chars_to_number (buf, THUMB_SIZE);
21034 newval = 0xbf00; /* NOP encoding T1 */
21035 md_number_to_chars (buf, newval, THUMB_SIZE);
21040 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21042 if (fixP->fx_done || !seg->use_rela_p)
21044 newval = md_chars_to_number (buf, THUMB_SIZE);
21045 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21046 md_number_to_chars (buf, newval, THUMB_SIZE);
21051 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21052 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21053 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21055 if (fixP->fx_done || !seg->use_rela_p)
21057 newval = md_chars_to_number (buf, THUMB_SIZE);
21058 newval |= (value & 0x1ff) >> 1;
21059 md_number_to_chars (buf, newval, THUMB_SIZE);
21063 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21064 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21065 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21067 if (fixP->fx_done || !seg->use_rela_p)
21069 newval = md_chars_to_number (buf, THUMB_SIZE);
21070 newval |= (value & 0xfff) >> 1;
21071 md_number_to_chars (buf, newval, THUMB_SIZE);
21075 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21077 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21078 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21079 && ARM_IS_FUNC (fixP->fx_addsy)
21080 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21082 /* Force a relocation for a branch 20 bits wide. */
21085 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21086 as_bad_where (fixP->fx_file, fixP->fx_line,
21087 _("conditional branch out of range"));
21089 if (fixP->fx_done || !seg->use_rela_p)
21092 addressT S, J1, J2, lo, hi;
21094 S = (value & 0x00100000) >> 20;
21095 J2 = (value & 0x00080000) >> 19;
21096 J1 = (value & 0x00040000) >> 18;
21097 hi = (value & 0x0003f000) >> 12;
21098 lo = (value & 0x00000ffe) >> 1;
21100 newval = md_chars_to_number (buf, THUMB_SIZE);
21101 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21102 newval |= (S << 10) | hi;
21103 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21104 md_number_to_chars (buf, newval, THUMB_SIZE);
21105 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21109 case BFD_RELOC_THUMB_PCREL_BLX:
21110 /* If there is a blx from a thumb state function to
21111 another thumb function flip this to a bl and warn
21115 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21116 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21117 && THUMB_IS_FUNC (fixP->fx_addsy))
21119 const char *name = S_GET_NAME (fixP->fx_addsy);
21120 as_warn_where (fixP->fx_file, fixP->fx_line,
21121 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21123 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21124 newval = newval | 0x1000;
21125 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21126 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21131 goto thumb_bl_common;
21133 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21134 /* A bl from Thumb state ISA to an internal ARM state function
21135 is converted to a blx. */
21137 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21138 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21139 && ARM_IS_FUNC (fixP->fx_addsy)
21140 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21142 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21143 newval = newval & ~0x1000;
21144 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21145 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21152 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
21153 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21154 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21157 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21158 /* For a BLX instruction, make sure that the relocation is rounded up
21159 to a word boundary. This follows the semantics of the instruction
21160 which specifies that bit 1 of the target address will come from bit
21161 1 of the base address. */
21162 value = (value + 1) & ~ 1;
21164 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21166 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21167 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21168 else if ((value & ~0x1ffffff)
21169 && ((value & ~0x1ffffff) != ~0x1ffffff))
21170 as_bad_where (fixP->fx_file, fixP->fx_line,
21171 _("Thumb2 branch out of range"));
21174 if (fixP->fx_done || !seg->use_rela_p)
21175 encode_thumb2_b_bl_offset (buf, value);
21179 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21180 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21181 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21183 if (fixP->fx_done || !seg->use_rela_p)
21184 encode_thumb2_b_bl_offset (buf, value);
21189 if (fixP->fx_done || !seg->use_rela_p)
21190 md_number_to_chars (buf, value, 1);
21194 if (fixP->fx_done || !seg->use_rela_p)
21195 md_number_to_chars (buf, value, 2);
21199 case BFD_RELOC_ARM_TLS_CALL:
21200 case BFD_RELOC_ARM_THM_TLS_CALL:
21201 case BFD_RELOC_ARM_TLS_DESCSEQ:
21202 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21203 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21206 case BFD_RELOC_ARM_TLS_GOTDESC:
21207 case BFD_RELOC_ARM_TLS_GD32:
21208 case BFD_RELOC_ARM_TLS_LE32:
21209 case BFD_RELOC_ARM_TLS_IE32:
21210 case BFD_RELOC_ARM_TLS_LDM32:
21211 case BFD_RELOC_ARM_TLS_LDO32:
21212 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21215 case BFD_RELOC_ARM_GOT32:
21216 case BFD_RELOC_ARM_GOTOFF:
21217 if (fixP->fx_done || !seg->use_rela_p)
21218 md_number_to_chars (buf, 0, 4);
21221 case BFD_RELOC_ARM_GOT_PREL:
21222 if (fixP->fx_done || !seg->use_rela_p)
21223 md_number_to_chars (buf, value, 4);
21226 case BFD_RELOC_ARM_TARGET2:
21227 /* TARGET2 is not partial-inplace, so we need to write the
21228 addend here for REL targets, because it won't be written out
21229 during reloc processing later. */
21230 if (fixP->fx_done || !seg->use_rela_p)
21231 md_number_to_chars (buf, fixP->fx_offset, 4);
21235 case BFD_RELOC_RVA:
21237 case BFD_RELOC_ARM_TARGET1:
21238 case BFD_RELOC_ARM_ROSEGREL32:
21239 case BFD_RELOC_ARM_SBREL32:
21240 case BFD_RELOC_32_PCREL:
21242 case BFD_RELOC_32_SECREL:
21244 if (fixP->fx_done || !seg->use_rela_p)
21246 /* For WinCE we only do this for pcrel fixups. */
21247 if (fixP->fx_done || fixP->fx_pcrel)
21249 md_number_to_chars (buf, value, 4);
21253 case BFD_RELOC_ARM_PREL31:
21254 if (fixP->fx_done || !seg->use_rela_p)
21256 newval = md_chars_to_number (buf, 4) & 0x80000000;
21257 if ((value ^ (value >> 1)) & 0x40000000)
21259 as_bad_where (fixP->fx_file, fixP->fx_line,
21260 _("rel31 relocation overflow"));
21262 newval |= value & 0x7fffffff;
21263 md_number_to_chars (buf, newval, 4);
21268 case BFD_RELOC_ARM_CP_OFF_IMM:
21269 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21270 if (value < -1023 || value > 1023 || (value & 3))
21271 as_bad_where (fixP->fx_file, fixP->fx_line,
21272 _("co-processor offset out of range"));
21277 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21278 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21279 newval = md_chars_to_number (buf, INSN_SIZE);
21281 newval = get_thumb32_insn (buf);
21283 newval &= 0xffffff00;
21286 newval &= 0xff7fff00;
21287 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21289 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21290 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21291 md_number_to_chars (buf, newval, INSN_SIZE);
21293 put_thumb32_insn (buf, newval);
21296 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21297 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21298 if (value < -255 || value > 255)
21299 as_bad_where (fixP->fx_file, fixP->fx_line,
21300 _("co-processor offset out of range"));
21302 goto cp_off_common;
21304 case BFD_RELOC_ARM_THUMB_OFFSET:
21305 newval = md_chars_to_number (buf, THUMB_SIZE);
21306 /* Exactly what ranges, and where the offset is inserted depends
21307 on the type of instruction, we can establish this from the
21309 switch (newval >> 12)
21311 case 4: /* PC load. */
21312 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21313 forced to zero for these loads; md_pcrel_from has already
21314 compensated for this. */
21316 as_bad_where (fixP->fx_file, fixP->fx_line,
21317 _("invalid offset, target not word aligned (0x%08lX)"),
21318 (((unsigned long) fixP->fx_frag->fr_address
21319 + (unsigned long) fixP->fx_where) & ~3)
21320 + (unsigned long) value);
21322 if (value & ~0x3fc)
21323 as_bad_where (fixP->fx_file, fixP->fx_line,
21324 _("invalid offset, value too big (0x%08lX)"),
21327 newval |= value >> 2;
21330 case 9: /* SP load/store. */
21331 if (value & ~0x3fc)
21332 as_bad_where (fixP->fx_file, fixP->fx_line,
21333 _("invalid offset, value too big (0x%08lX)"),
21335 newval |= value >> 2;
21338 case 6: /* Word load/store. */
21340 as_bad_where (fixP->fx_file, fixP->fx_line,
21341 _("invalid offset, value too big (0x%08lX)"),
21343 newval |= value << 4; /* 6 - 2. */
21346 case 7: /* Byte load/store. */
21348 as_bad_where (fixP->fx_file, fixP->fx_line,
21349 _("invalid offset, value too big (0x%08lX)"),
21351 newval |= value << 6;
21354 case 8: /* Halfword load/store. */
21356 as_bad_where (fixP->fx_file, fixP->fx_line,
21357 _("invalid offset, value too big (0x%08lX)"),
21359 newval |= value << 5; /* 6 - 1. */
21363 as_bad_where (fixP->fx_file, fixP->fx_line,
21364 "Unable to process relocation for thumb opcode: %lx",
21365 (unsigned long) newval);
21368 md_number_to_chars (buf, newval, THUMB_SIZE);
21371 case BFD_RELOC_ARM_THUMB_ADD:
21372 /* This is a complicated relocation, since we use it for all of
21373 the following immediate relocations:
21377 9bit ADD/SUB SP word-aligned
21378 10bit ADD PC/SP word-aligned
21380 The type of instruction being processed is encoded in the
21387 newval = md_chars_to_number (buf, THUMB_SIZE);
21389 int rd = (newval >> 4) & 0xf;
21390 int rs = newval & 0xf;
21391 int subtract = !!(newval & 0x8000);
21393 /* Check for HI regs, only very restricted cases allowed:
21394 Adjusting SP, and using PC or SP to get an address. */
21395 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21396 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21397 as_bad_where (fixP->fx_file, fixP->fx_line,
21398 _("invalid Hi register with immediate"));
21400 /* If value is negative, choose the opposite instruction. */
21404 subtract = !subtract;
21406 as_bad_where (fixP->fx_file, fixP->fx_line,
21407 _("immediate value out of range"));
21412 if (value & ~0x1fc)
21413 as_bad_where (fixP->fx_file, fixP->fx_line,
21414 _("invalid immediate for stack address calculation"));
21415 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21416 newval |= value >> 2;
21418 else if (rs == REG_PC || rs == REG_SP)
21420 if (subtract || value & ~0x3fc)
21421 as_bad_where (fixP->fx_file, fixP->fx_line,
21422 _("invalid immediate for address calculation (value = 0x%08lX)"),
21423 (unsigned long) value);
21424 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21426 newval |= value >> 2;
21431 as_bad_where (fixP->fx_file, fixP->fx_line,
21432 _("immediate value out of range"));
21433 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21434 newval |= (rd << 8) | value;
21439 as_bad_where (fixP->fx_file, fixP->fx_line,
21440 _("immediate value out of range"));
21441 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21442 newval |= rd | (rs << 3) | (value << 6);
21445 md_number_to_chars (buf, newval, THUMB_SIZE);
21448 case BFD_RELOC_ARM_THUMB_IMM:
21449 newval = md_chars_to_number (buf, THUMB_SIZE);
21450 if (value < 0 || value > 255)
21451 as_bad_where (fixP->fx_file, fixP->fx_line,
21452 _("invalid immediate: %ld is out of range"),
21455 md_number_to_chars (buf, newval, THUMB_SIZE);
21458 case BFD_RELOC_ARM_THUMB_SHIFT:
21459 /* 5bit shift value (0..32). LSL cannot take 32. */
21460 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21461 temp = newval & 0xf800;
21462 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21463 as_bad_where (fixP->fx_file, fixP->fx_line,
21464 _("invalid shift value: %ld"), (long) value);
21465 /* Shifts of zero must be encoded as LSL. */
21467 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21468 /* Shifts of 32 are encoded as zero. */
21469 else if (value == 32)
21471 newval |= value << 6;
21472 md_number_to_chars (buf, newval, THUMB_SIZE);
21475 case BFD_RELOC_VTABLE_INHERIT:
21476 case BFD_RELOC_VTABLE_ENTRY:
21480 case BFD_RELOC_ARM_MOVW:
21481 case BFD_RELOC_ARM_MOVT:
21482 case BFD_RELOC_ARM_THUMB_MOVW:
21483 case BFD_RELOC_ARM_THUMB_MOVT:
21484 if (fixP->fx_done || !seg->use_rela_p)
21486 /* REL format relocations are limited to a 16-bit addend. */
21487 if (!fixP->fx_done)
21489 if (value < -0x8000 || value > 0x7fff)
21490 as_bad_where (fixP->fx_file, fixP->fx_line,
21491 _("offset out of range"));
21493 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21494 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21499 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21500 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21502 newval = get_thumb32_insn (buf);
21503 newval &= 0xfbf08f00;
21504 newval |= (value & 0xf000) << 4;
21505 newval |= (value & 0x0800) << 15;
21506 newval |= (value & 0x0700) << 4;
21507 newval |= (value & 0x00ff);
21508 put_thumb32_insn (buf, newval);
21512 newval = md_chars_to_number (buf, 4);
21513 newval &= 0xfff0f000;
21514 newval |= value & 0x0fff;
21515 newval |= (value & 0xf000) << 4;
21516 md_number_to_chars (buf, newval, 4);
21521 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21522 case BFD_RELOC_ARM_ALU_PC_G0:
21523 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21524 case BFD_RELOC_ARM_ALU_PC_G1:
21525 case BFD_RELOC_ARM_ALU_PC_G2:
21526 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21527 case BFD_RELOC_ARM_ALU_SB_G0:
21528 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21529 case BFD_RELOC_ARM_ALU_SB_G1:
21530 case BFD_RELOC_ARM_ALU_SB_G2:
21531 gas_assert (!fixP->fx_done);
21532 if (!seg->use_rela_p)
21535 bfd_vma encoded_addend;
21536 bfd_vma addend_abs = abs (value);
21538 /* Check that the absolute value of the addend can be
21539 expressed as an 8-bit constant plus a rotation. */
21540 encoded_addend = encode_arm_immediate (addend_abs);
21541 if (encoded_addend == (unsigned int) FAIL)
21542 as_bad_where (fixP->fx_file, fixP->fx_line,
21543 _("the offset 0x%08lX is not representable"),
21544 (unsigned long) addend_abs);
21546 /* Extract the instruction. */
21547 insn = md_chars_to_number (buf, INSN_SIZE);
21549 /* If the addend is positive, use an ADD instruction.
21550 Otherwise use a SUB. Take care not to destroy the S bit. */
21551 insn &= 0xff1fffff;
21557 /* Place the encoded addend into the first 12 bits of the
21559 insn &= 0xfffff000;
21560 insn |= encoded_addend;
21562 /* Update the instruction. */
21563 md_number_to_chars (buf, insn, INSN_SIZE);
21567 case BFD_RELOC_ARM_LDR_PC_G0:
21568 case BFD_RELOC_ARM_LDR_PC_G1:
21569 case BFD_RELOC_ARM_LDR_PC_G2:
21570 case BFD_RELOC_ARM_LDR_SB_G0:
21571 case BFD_RELOC_ARM_LDR_SB_G1:
21572 case BFD_RELOC_ARM_LDR_SB_G2:
21573 gas_assert (!fixP->fx_done);
21574 if (!seg->use_rela_p)
21577 bfd_vma addend_abs = abs (value);
21579 /* Check that the absolute value of the addend can be
21580 encoded in 12 bits. */
21581 if (addend_abs >= 0x1000)
21582 as_bad_where (fixP->fx_file, fixP->fx_line,
21583 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21584 (unsigned long) addend_abs);
21586 /* Extract the instruction. */
21587 insn = md_chars_to_number (buf, INSN_SIZE);
21589 /* If the addend is negative, clear bit 23 of the instruction.
21590 Otherwise set it. */
21592 insn &= ~(1 << 23);
21596 /* Place the absolute value of the addend into the first 12 bits
21597 of the instruction. */
21598 insn &= 0xfffff000;
21599 insn |= addend_abs;
21601 /* Update the instruction. */
21602 md_number_to_chars (buf, insn, INSN_SIZE);
21606 case BFD_RELOC_ARM_LDRS_PC_G0:
21607 case BFD_RELOC_ARM_LDRS_PC_G1:
21608 case BFD_RELOC_ARM_LDRS_PC_G2:
21609 case BFD_RELOC_ARM_LDRS_SB_G0:
21610 case BFD_RELOC_ARM_LDRS_SB_G1:
21611 case BFD_RELOC_ARM_LDRS_SB_G2:
21612 gas_assert (!fixP->fx_done);
21613 if (!seg->use_rela_p)
21616 bfd_vma addend_abs = abs (value);
21618 /* Check that the absolute value of the addend can be
21619 encoded in 8 bits. */
21620 if (addend_abs >= 0x100)
21621 as_bad_where (fixP->fx_file, fixP->fx_line,
21622 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21623 (unsigned long) addend_abs);
21625 /* Extract the instruction. */
21626 insn = md_chars_to_number (buf, INSN_SIZE);
21628 /* If the addend is negative, clear bit 23 of the instruction.
21629 Otherwise set it. */
21631 insn &= ~(1 << 23);
21635 /* Place the first four bits of the absolute value of the addend
21636 into the first 4 bits of the instruction, and the remaining
21637 four into bits 8 .. 11. */
21638 insn &= 0xfffff0f0;
21639 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21641 /* Update the instruction. */
21642 md_number_to_chars (buf, insn, INSN_SIZE);
21646 case BFD_RELOC_ARM_LDC_PC_G0:
21647 case BFD_RELOC_ARM_LDC_PC_G1:
21648 case BFD_RELOC_ARM_LDC_PC_G2:
21649 case BFD_RELOC_ARM_LDC_SB_G0:
21650 case BFD_RELOC_ARM_LDC_SB_G1:
21651 case BFD_RELOC_ARM_LDC_SB_G2:
21652 gas_assert (!fixP->fx_done);
21653 if (!seg->use_rela_p)
21656 bfd_vma addend_abs = abs (value);
21658 /* Check that the absolute value of the addend is a multiple of
21659 four and, when divided by four, fits in 8 bits. */
21660 if (addend_abs & 0x3)
21661 as_bad_where (fixP->fx_file, fixP->fx_line,
21662 _("bad offset 0x%08lX (must be word-aligned)"),
21663 (unsigned long) addend_abs);
21665 if ((addend_abs >> 2) > 0xff)
21666 as_bad_where (fixP->fx_file, fixP->fx_line,
21667 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21668 (unsigned long) addend_abs);
21670 /* Extract the instruction. */
21671 insn = md_chars_to_number (buf, INSN_SIZE);
21673 /* If the addend is negative, clear bit 23 of the instruction.
21674 Otherwise set it. */
21676 insn &= ~(1 << 23);
21680 /* Place the addend (divided by four) into the first eight
21681 bits of the instruction. */
21682 insn &= 0xfffffff0;
21683 insn |= addend_abs >> 2;
21685 /* Update the instruction. */
21686 md_number_to_chars (buf, insn, INSN_SIZE);
21690 case BFD_RELOC_ARM_V4BX:
21691 /* This will need to go in the object file. */
21695 case BFD_RELOC_UNUSED:
21697 as_bad_where (fixP->fx_file, fixP->fx_line,
21698 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21702 /* Translate internal representation of relocation info to BFD target
21706 tc_gen_reloc (asection *section, fixS *fixp)
21709 bfd_reloc_code_real_type code;
21711 reloc = (arelent *) xmalloc (sizeof (arelent));
21713 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21714 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21715 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21717 if (fixp->fx_pcrel)
21719 if (section->use_rela_p)
21720 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21722 fixp->fx_offset = reloc->address;
21724 reloc->addend = fixp->fx_offset;
21726 switch (fixp->fx_r_type)
21729 if (fixp->fx_pcrel)
21731 code = BFD_RELOC_8_PCREL;
21736 if (fixp->fx_pcrel)
21738 code = BFD_RELOC_16_PCREL;
21743 if (fixp->fx_pcrel)
21745 code = BFD_RELOC_32_PCREL;
21749 case BFD_RELOC_ARM_MOVW:
21750 if (fixp->fx_pcrel)
21752 code = BFD_RELOC_ARM_MOVW_PCREL;
21756 case BFD_RELOC_ARM_MOVT:
21757 if (fixp->fx_pcrel)
21759 code = BFD_RELOC_ARM_MOVT_PCREL;
21763 case BFD_RELOC_ARM_THUMB_MOVW:
21764 if (fixp->fx_pcrel)
21766 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21770 case BFD_RELOC_ARM_THUMB_MOVT:
21771 if (fixp->fx_pcrel)
21773 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21777 case BFD_RELOC_NONE:
21778 case BFD_RELOC_ARM_PCREL_BRANCH:
21779 case BFD_RELOC_ARM_PCREL_BLX:
21780 case BFD_RELOC_RVA:
21781 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21782 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21783 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21784 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21785 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21786 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21787 case BFD_RELOC_VTABLE_ENTRY:
21788 case BFD_RELOC_VTABLE_INHERIT:
21790 case BFD_RELOC_32_SECREL:
21792 code = fixp->fx_r_type;
21795 case BFD_RELOC_THUMB_PCREL_BLX:
21797 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21798 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21801 code = BFD_RELOC_THUMB_PCREL_BLX;
21804 case BFD_RELOC_ARM_LITERAL:
21805 case BFD_RELOC_ARM_HWLITERAL:
21806 /* If this is called then the a literal has
21807 been referenced across a section boundary. */
21808 as_bad_where (fixp->fx_file, fixp->fx_line,
21809 _("literal referenced across section boundary"));
21813 case BFD_RELOC_ARM_TLS_CALL:
21814 case BFD_RELOC_ARM_THM_TLS_CALL:
21815 case BFD_RELOC_ARM_TLS_DESCSEQ:
21816 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21817 case BFD_RELOC_ARM_GOT32:
21818 case BFD_RELOC_ARM_GOTOFF:
21819 case BFD_RELOC_ARM_GOT_PREL:
21820 case BFD_RELOC_ARM_PLT32:
21821 case BFD_RELOC_ARM_TARGET1:
21822 case BFD_RELOC_ARM_ROSEGREL32:
21823 case BFD_RELOC_ARM_SBREL32:
21824 case BFD_RELOC_ARM_PREL31:
21825 case BFD_RELOC_ARM_TARGET2:
21826 case BFD_RELOC_ARM_TLS_LE32:
21827 case BFD_RELOC_ARM_TLS_LDO32:
21828 case BFD_RELOC_ARM_PCREL_CALL:
21829 case BFD_RELOC_ARM_PCREL_JUMP:
21830 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21831 case BFD_RELOC_ARM_ALU_PC_G0:
21832 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21833 case BFD_RELOC_ARM_ALU_PC_G1:
21834 case BFD_RELOC_ARM_ALU_PC_G2:
21835 case BFD_RELOC_ARM_LDR_PC_G0:
21836 case BFD_RELOC_ARM_LDR_PC_G1:
21837 case BFD_RELOC_ARM_LDR_PC_G2:
21838 case BFD_RELOC_ARM_LDRS_PC_G0:
21839 case BFD_RELOC_ARM_LDRS_PC_G1:
21840 case BFD_RELOC_ARM_LDRS_PC_G2:
21841 case BFD_RELOC_ARM_LDC_PC_G0:
21842 case BFD_RELOC_ARM_LDC_PC_G1:
21843 case BFD_RELOC_ARM_LDC_PC_G2:
21844 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21845 case BFD_RELOC_ARM_ALU_SB_G0:
21846 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21847 case BFD_RELOC_ARM_ALU_SB_G1:
21848 case BFD_RELOC_ARM_ALU_SB_G2:
21849 case BFD_RELOC_ARM_LDR_SB_G0:
21850 case BFD_RELOC_ARM_LDR_SB_G1:
21851 case BFD_RELOC_ARM_LDR_SB_G2:
21852 case BFD_RELOC_ARM_LDRS_SB_G0:
21853 case BFD_RELOC_ARM_LDRS_SB_G1:
21854 case BFD_RELOC_ARM_LDRS_SB_G2:
21855 case BFD_RELOC_ARM_LDC_SB_G0:
21856 case BFD_RELOC_ARM_LDC_SB_G1:
21857 case BFD_RELOC_ARM_LDC_SB_G2:
21858 case BFD_RELOC_ARM_V4BX:
21859 code = fixp->fx_r_type;
21862 case BFD_RELOC_ARM_TLS_GOTDESC:
21863 case BFD_RELOC_ARM_TLS_GD32:
21864 case BFD_RELOC_ARM_TLS_IE32:
21865 case BFD_RELOC_ARM_TLS_LDM32:
21866 /* BFD will include the symbol's address in the addend.
21867 But we don't want that, so subtract it out again here. */
21868 if (!S_IS_COMMON (fixp->fx_addsy))
21869 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21870 code = fixp->fx_r_type;
21874 case BFD_RELOC_ARM_IMMEDIATE:
21875 as_bad_where (fixp->fx_file, fixp->fx_line,
21876 _("internal relocation (type: IMMEDIATE) not fixed up"));
21879 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21880 as_bad_where (fixp->fx_file, fixp->fx_line,
21881 _("ADRL used for a symbol not defined in the same file"));
21884 case BFD_RELOC_ARM_OFFSET_IMM:
21885 if (section->use_rela_p)
21887 code = fixp->fx_r_type;
21891 if (fixp->fx_addsy != NULL
21892 && !S_IS_DEFINED (fixp->fx_addsy)
21893 && S_IS_LOCAL (fixp->fx_addsy))
21895 as_bad_where (fixp->fx_file, fixp->fx_line,
21896 _("undefined local label `%s'"),
21897 S_GET_NAME (fixp->fx_addsy));
21901 as_bad_where (fixp->fx_file, fixp->fx_line,
21902 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21909 switch (fixp->fx_r_type)
21911 case BFD_RELOC_NONE: type = "NONE"; break;
21912 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
21913 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
21914 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
21915 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
21916 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
21917 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
21918 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
21919 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
21920 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
21921 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
21922 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
21923 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
21924 default: type = _("<unknown>"); break;
21926 as_bad_where (fixp->fx_file, fixp->fx_line,
21927 _("cannot represent %s relocation in this object file format"),
21934 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
21936 && fixp->fx_addsy == GOT_symbol)
21938 code = BFD_RELOC_ARM_GOTPC;
21939 reloc->addend = fixp->fx_offset = reloc->address;
21943 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
21945 if (reloc->howto == NULL)
21947 as_bad_where (fixp->fx_file, fixp->fx_line,
21948 _("cannot represent %s relocation in this object file format"),
21949 bfd_get_reloc_code_name (code));
21953 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21954 vtable entry to be used in the relocation's section offset. */
21955 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
21956 reloc->address = fixp->fx_offset;
21961 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21964 cons_fix_new_arm (fragS * frag,
21969 bfd_reloc_code_real_type type;
21973 FIXME: @@ Should look at CPU word size. */
21977 type = BFD_RELOC_8;
21980 type = BFD_RELOC_16;
21984 type = BFD_RELOC_32;
21987 type = BFD_RELOC_64;
21992 if (exp->X_op == O_secrel)
21994 exp->X_op = O_symbol;
21995 type = BFD_RELOC_32_SECREL;
21999 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22002 #if defined (OBJ_COFF)
22004 arm_validate_fix (fixS * fixP)
22006 /* If the destination of the branch is a defined symbol which does not have
22007 the THUMB_FUNC attribute, then we must be calling a function which has
22008 the (interfacearm) attribute. We look for the Thumb entry point to that
22009 function and change the branch to refer to that function instead. */
22010 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22011 && fixP->fx_addsy != NULL
22012 && S_IS_DEFINED (fixP->fx_addsy)
22013 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22015 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22022 arm_force_relocation (struct fix * fixp)
22024 #if defined (OBJ_COFF) && defined (TE_PE)
22025 if (fixp->fx_r_type == BFD_RELOC_RVA)
22029 /* In case we have a call or a branch to a function in ARM ISA mode from
22030 a thumb function or vice-versa force the relocation. These relocations
22031 are cleared off for some cores that might have blx and simple transformations
22035 switch (fixp->fx_r_type)
22037 case BFD_RELOC_ARM_PCREL_JUMP:
22038 case BFD_RELOC_ARM_PCREL_CALL:
22039 case BFD_RELOC_THUMB_PCREL_BLX:
22040 if (THUMB_IS_FUNC (fixp->fx_addsy))
22044 case BFD_RELOC_ARM_PCREL_BLX:
22045 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22046 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22047 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22048 if (ARM_IS_FUNC (fixp->fx_addsy))
22057 /* Resolve these relocations even if the symbol is extern or weak.
22058 Technically this is probably wrong due to symbol preemption.
22059 In practice these relocations do not have enough range to be useful
22060 at dynamic link time, and some code (e.g. in the Linux kernel)
22061 expects these references to be resolved. */
22062 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22063 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22064 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22065 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22066 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22067 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22068 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22069 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22070 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22071 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22072 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22073 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22074 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22075 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22078 /* Always leave these relocations for the linker. */
22079 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22080 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22081 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22084 /* Always generate relocations against function symbols. */
22085 if (fixp->fx_r_type == BFD_RELOC_32
22087 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22090 return generic_force_reloc (fixp);
22093 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22094 /* Relocations against function names must be left unadjusted,
22095 so that the linker can use this information to generate interworking
22096 stubs. The MIPS version of this function
22097 also prevents relocations that are mips-16 specific, but I do not
22098 know why it does this.
22101 There is one other problem that ought to be addressed here, but
22102 which currently is not: Taking the address of a label (rather
22103 than a function) and then later jumping to that address. Such
22104 addresses also ought to have their bottom bit set (assuming that
22105 they reside in Thumb code), but at the moment they will not. */
22108 arm_fix_adjustable (fixS * fixP)
22110 if (fixP->fx_addsy == NULL)
22113 /* Preserve relocations against symbols with function type. */
22114 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22117 if (THUMB_IS_FUNC (fixP->fx_addsy)
22118 && fixP->fx_subsy == NULL)
22121 /* We need the symbol name for the VTABLE entries. */
22122 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22123 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22126 /* Don't allow symbols to be discarded on GOT related relocs. */
22127 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22128 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22129 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22130 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22131 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22132 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22133 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22134 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22135 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22136 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22137 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22138 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22139 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22140 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22143 /* Similarly for group relocations. */
22144 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22145 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22146 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22149 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22150 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22151 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22152 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22153 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22154 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22155 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22156 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22157 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22162 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22167 elf32_arm_target_format (void)
22170 return (target_big_endian
22171 ? "elf32-bigarm-symbian"
22172 : "elf32-littlearm-symbian");
22173 #elif defined (TE_VXWORKS)
22174 return (target_big_endian
22175 ? "elf32-bigarm-vxworks"
22176 : "elf32-littlearm-vxworks");
22178 if (target_big_endian)
22179 return "elf32-bigarm";
22181 return "elf32-littlearm";
22186 armelf_frob_symbol (symbolS * symp,
22189 elf_frob_symbol (symp, puntp);
22193 /* MD interface: Finalization. */
22198 literal_pool * pool;
22200 /* Ensure that all the IT blocks are properly closed. */
22201 check_it_blocks_finished ();
22203 for (pool = list_of_pools; pool; pool = pool->next)
22205 /* Put it at the end of the relevant section. */
22206 subseg_set (pool->section, pool->sub_section);
22208 arm_elf_change_section ();
22215 /* Remove any excess mapping symbols generated for alignment frags in
22216 SEC. We may have created a mapping symbol before a zero byte
22217 alignment; remove it if there's a mapping symbol after the
22220 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22221 void *dummy ATTRIBUTE_UNUSED)
22223 segment_info_type *seginfo = seg_info (sec);
22226 if (seginfo == NULL || seginfo->frchainP == NULL)
22229 for (fragp = seginfo->frchainP->frch_root;
22231 fragp = fragp->fr_next)
22233 symbolS *sym = fragp->tc_frag_data.last_map;
22234 fragS *next = fragp->fr_next;
22236 /* Variable-sized frags have been converted to fixed size by
22237 this point. But if this was variable-sized to start with,
22238 there will be a fixed-size frag after it. So don't handle
22240 if (sym == NULL || next == NULL)
22243 if (S_GET_VALUE (sym) < next->fr_address)
22244 /* Not at the end of this frag. */
22246 know (S_GET_VALUE (sym) == next->fr_address);
22250 if (next->tc_frag_data.first_map != NULL)
22252 /* Next frag starts with a mapping symbol. Discard this
22254 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22258 if (next->fr_next == NULL)
22260 /* This mapping symbol is at the end of the section. Discard
22262 know (next->fr_fix == 0 && next->fr_var == 0);
22263 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22267 /* As long as we have empty frags without any mapping symbols,
22269 /* If the next frag is non-empty and does not start with a
22270 mapping symbol, then this mapping symbol is required. */
22271 if (next->fr_address != next->fr_next->fr_address)
22274 next = next->fr_next;
22276 while (next != NULL);
22281 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22285 arm_adjust_symtab (void)
22290 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22292 if (ARM_IS_THUMB (sym))
22294 if (THUMB_IS_FUNC (sym))
22296 /* Mark the symbol as a Thumb function. */
22297 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22298 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22299 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22301 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22302 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22304 as_bad (_("%s: unexpected function type: %d"),
22305 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22307 else switch (S_GET_STORAGE_CLASS (sym))
22310 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22313 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22316 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22324 if (ARM_IS_INTERWORK (sym))
22325 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22332 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22334 if (ARM_IS_THUMB (sym))
22336 elf_symbol_type * elf_sym;
22338 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22339 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22341 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22342 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22344 /* If it's a .thumb_func, declare it as so,
22345 otherwise tag label as .code 16. */
22346 if (THUMB_IS_FUNC (sym))
22347 elf_sym->internal_elf_sym.st_target_internal
22348 = ST_BRANCH_TO_THUMB;
22349 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22350 elf_sym->internal_elf_sym.st_info =
22351 ELF_ST_INFO (bind, STT_ARM_16BIT);
22356 /* Remove any overlapping mapping symbols generated by alignment frags. */
22357 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22358 /* Now do generic ELF adjustments. */
22359 elf_adjust_symtab ();
22363 /* MD interface: Initialization. */
22366 set_constant_flonums (void)
22370 for (i = 0; i < NUM_FLOAT_VALS; i++)
22371 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22375 /* Auto-select Thumb mode if it's the only available instruction set for the
22376 given architecture. */
22379 autoselect_thumb_from_cpu_variant (void)
22381 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22382 opcode_select (16);
22391 if ( (arm_ops_hsh = hash_new ()) == NULL
22392 || (arm_cond_hsh = hash_new ()) == NULL
22393 || (arm_shift_hsh = hash_new ()) == NULL
22394 || (arm_psr_hsh = hash_new ()) == NULL
22395 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22396 || (arm_reg_hsh = hash_new ()) == NULL
22397 || (arm_reloc_hsh = hash_new ()) == NULL
22398 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22399 as_fatal (_("virtual memory exhausted"));
22401 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22402 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22403 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22404 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22405 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22406 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22407 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22408 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22409 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22410 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22411 (void *) (v7m_psrs + i));
22412 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22413 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22415 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22417 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22418 (void *) (barrier_opt_names + i));
22420 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
22421 hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i));
22424 set_constant_flonums ();
22426 /* Set the cpu variant based on the command-line options. We prefer
22427 -mcpu= over -march= if both are set (as for GCC); and we prefer
22428 -mfpu= over any other way of setting the floating point unit.
22429 Use of legacy options with new options are faulted. */
22432 if (mcpu_cpu_opt || march_cpu_opt)
22433 as_bad (_("use of old and new-style options to set CPU type"));
22435 mcpu_cpu_opt = legacy_cpu;
22437 else if (!mcpu_cpu_opt)
22438 mcpu_cpu_opt = march_cpu_opt;
22443 as_bad (_("use of old and new-style options to set FPU type"));
22445 mfpu_opt = legacy_fpu;
22447 else if (!mfpu_opt)
22449 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22450 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22451 /* Some environments specify a default FPU. If they don't, infer it
22452 from the processor. */
22454 mfpu_opt = mcpu_fpu_opt;
22456 mfpu_opt = march_fpu_opt;
22458 mfpu_opt = &fpu_default;
22464 if (mcpu_cpu_opt != NULL)
22465 mfpu_opt = &fpu_default;
22466 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22467 mfpu_opt = &fpu_arch_vfp_v2;
22469 mfpu_opt = &fpu_arch_fpa;
22475 mcpu_cpu_opt = &cpu_default;
22476 selected_cpu = cpu_default;
22480 selected_cpu = *mcpu_cpu_opt;
22482 mcpu_cpu_opt = &arm_arch_any;
22485 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22487 autoselect_thumb_from_cpu_variant ();
22489 arm_arch_used = thumb_arch_used = arm_arch_none;
22491 #if defined OBJ_COFF || defined OBJ_ELF
22493 unsigned int flags = 0;
22495 #if defined OBJ_ELF
22496 flags = meabi_flags;
22498 switch (meabi_flags)
22500 case EF_ARM_EABI_UNKNOWN:
22502 /* Set the flags in the private structure. */
22503 if (uses_apcs_26) flags |= F_APCS26;
22504 if (support_interwork) flags |= F_INTERWORK;
22505 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22506 if (pic_code) flags |= F_PIC;
22507 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22508 flags |= F_SOFT_FLOAT;
22510 switch (mfloat_abi_opt)
22512 case ARM_FLOAT_ABI_SOFT:
22513 case ARM_FLOAT_ABI_SOFTFP:
22514 flags |= F_SOFT_FLOAT;
22517 case ARM_FLOAT_ABI_HARD:
22518 if (flags & F_SOFT_FLOAT)
22519 as_bad (_("hard-float conflicts with specified fpu"));
22523 /* Using pure-endian doubles (even if soft-float). */
22524 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22525 flags |= F_VFP_FLOAT;
22527 #if defined OBJ_ELF
22528 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22529 flags |= EF_ARM_MAVERICK_FLOAT;
22532 case EF_ARM_EABI_VER4:
22533 case EF_ARM_EABI_VER5:
22534 /* No additional flags to set. */
22541 bfd_set_private_flags (stdoutput, flags);
22543 /* We have run out flags in the COFF header to encode the
22544 status of ATPCS support, so instead we create a dummy,
22545 empty, debug section called .arm.atpcs. */
22550 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22554 bfd_set_section_flags
22555 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22556 bfd_set_section_size (stdoutput, sec, 0);
22557 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22563 /* Record the CPU type as well. */
22564 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22565 mach = bfd_mach_arm_iWMMXt2;
22566 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22567 mach = bfd_mach_arm_iWMMXt;
22568 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22569 mach = bfd_mach_arm_XScale;
22570 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22571 mach = bfd_mach_arm_ep9312;
22572 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22573 mach = bfd_mach_arm_5TE;
22574 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22576 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22577 mach = bfd_mach_arm_5T;
22579 mach = bfd_mach_arm_5;
22581 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22583 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22584 mach = bfd_mach_arm_4T;
22586 mach = bfd_mach_arm_4;
22588 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22589 mach = bfd_mach_arm_3M;
22590 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22591 mach = bfd_mach_arm_3;
22592 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22593 mach = bfd_mach_arm_2a;
22594 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22595 mach = bfd_mach_arm_2;
22597 mach = bfd_mach_arm_unknown;
22599 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22602 /* Command line processing. */
22605 Invocation line includes a switch not recognized by the base assembler.
22606 See if it's a processor-specific option.
22608 This routine is somewhat complicated by the need for backwards
22609 compatibility (since older releases of gcc can't be changed).
22610 The new options try to make the interface as compatible as
22613 New options (supported) are:
22615 -mcpu=<cpu name> Assemble for selected processor
22616 -march=<architecture name> Assemble for selected architecture
22617 -mfpu=<fpu architecture> Assemble for selected FPU.
22618 -EB/-mbig-endian Big-endian
22619 -EL/-mlittle-endian Little-endian
22620 -k Generate PIC code
22621 -mthumb Start in Thumb mode
22622 -mthumb-interwork Code supports ARM/Thumb interworking
22624 -m[no-]warn-deprecated Warn about deprecated features
22626 For now we will also provide support for:
22628 -mapcs-32 32-bit Program counter
22629 -mapcs-26 26-bit Program counter
22630 -macps-float Floats passed in FP registers
22631 -mapcs-reentrant Reentrant code
22633 (sometime these will probably be replaced with -mapcs=<list of options>
22634 and -matpcs=<list of options>)
22636 The remaining options are only supported for back-wards compatibility.
22637 Cpu variants, the arm part is optional:
22638 -m[arm]1 Currently not supported.
22639 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22640 -m[arm]3 Arm 3 processor
22641 -m[arm]6[xx], Arm 6 processors
22642 -m[arm]7[xx][t][[d]m] Arm 7 processors
22643 -m[arm]8[10] Arm 8 processors
22644 -m[arm]9[20][tdmi] Arm 9 processors
22645 -mstrongarm[110[0]] StrongARM processors
22646 -mxscale XScale processors
22647 -m[arm]v[2345[t[e]]] Arm architectures
22648 -mall All (except the ARM1)
22650 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22651 -mfpe-old (No float load/store multiples)
22652 -mvfpxd VFP Single precision
22654 -mno-fpu Disable all floating point instructions
22656 The following CPU names are recognized:
22657 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22658 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22659 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22660 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22661 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22662 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22663 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22667 const char * md_shortopts = "m:k";
22669 #ifdef ARM_BI_ENDIAN
22670 #define OPTION_EB (OPTION_MD_BASE + 0)
22671 #define OPTION_EL (OPTION_MD_BASE + 1)
22673 #if TARGET_BYTES_BIG_ENDIAN
22674 #define OPTION_EB (OPTION_MD_BASE + 0)
22676 #define OPTION_EL (OPTION_MD_BASE + 1)
22679 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22681 struct option md_longopts[] =
22684 {"EB", no_argument, NULL, OPTION_EB},
22687 {"EL", no_argument, NULL, OPTION_EL},
22689 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22690 {NULL, no_argument, NULL, 0}
22693 size_t md_longopts_size = sizeof (md_longopts);
22695 struct arm_option_table
22697 char *option; /* Option name to match. */
22698 char *help; /* Help information. */
22699 int *var; /* Variable to change. */
22700 int value; /* What to change it to. */
22701 char *deprecated; /* If non-null, print this message. */
22704 struct arm_option_table arm_opts[] =
22706 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22707 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22708 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22709 &support_interwork, 1, NULL},
22710 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22711 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22712 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22714 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22715 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22716 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22717 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22720 /* These are recognized by the assembler, but have no affect on code. */
22721 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22722 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22724 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22725 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22726 &warn_on_deprecated, 0, NULL},
22727 {NULL, NULL, NULL, 0, NULL}
22730 struct arm_legacy_option_table
22732 char *option; /* Option name to match. */
22733 const arm_feature_set **var; /* Variable to change. */
22734 const arm_feature_set value; /* What to change it to. */
22735 char *deprecated; /* If non-null, print this message. */
22738 const struct arm_legacy_option_table arm_legacy_opts[] =
22740 /* DON'T add any new processors to this list -- we want the whole list
22741 to go away... Add them to the processors table instead. */
22742 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22743 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22744 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22745 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22746 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22747 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22748 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22749 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22750 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22751 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22752 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22753 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22754 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22755 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22756 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22757 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22758 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22759 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22760 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22761 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22762 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22763 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22764 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22765 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22766 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22767 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22768 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22769 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22770 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22771 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22772 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22773 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22774 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22775 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22776 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22777 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22778 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22779 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22780 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22781 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22782 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22783 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22784 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22785 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22786 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22787 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22788 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22789 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22790 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22791 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22792 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22793 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22794 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22795 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22796 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22797 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22798 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22799 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22800 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22801 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22802 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22803 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22804 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22805 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22806 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22807 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22808 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22809 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22810 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22811 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22812 N_("use -mcpu=strongarm110")},
22813 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22814 N_("use -mcpu=strongarm1100")},
22815 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22816 N_("use -mcpu=strongarm1110")},
22817 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22818 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22819 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22821 /* Architecture variants -- don't add any more to this list either. */
22822 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22823 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22824 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22825 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22826 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22827 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22828 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22829 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22830 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22831 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22832 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22833 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22834 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22835 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22836 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22837 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22838 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22839 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22841 /* Floating point variants -- don't add any more to this list either. */
22842 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22843 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22844 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22845 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
22846 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22848 {NULL, NULL, ARM_ARCH_NONE, NULL}
22851 struct arm_cpu_option_table
22854 const arm_feature_set value;
22855 /* For some CPUs we assume an FPU unless the user explicitly sets
22857 const arm_feature_set default_fpu;
22858 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22860 const char *canonical_name;
22863 /* This list should, at a minimum, contain all the cpu names
22864 recognized by GCC. */
22865 static const struct arm_cpu_option_table arm_cpus[] =
22867 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
22868 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
22869 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
22870 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22871 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22872 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22873 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22874 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22875 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22876 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22877 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22878 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22879 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22880 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22881 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22882 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22883 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22884 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22885 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22886 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22887 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22888 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22889 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22890 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22891 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22892 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22893 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22894 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22895 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22896 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22897 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22898 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22899 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22900 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22901 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22902 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22903 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22904 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22905 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22906 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
22907 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22908 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22909 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22910 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22911 {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22912 {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22913 /* For V5 or later processors we default to using VFP; but the user
22914 should really set the FPU type explicitly. */
22915 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22916 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22917 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22918 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22919 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22920 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22921 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
22922 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22923 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22924 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
22925 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22926 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22927 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22928 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22929 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22930 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
22931 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22932 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22933 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22934 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
22935 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22936 {"fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22937 {"fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22938 {"fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22939 {"fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22940 {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22941 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
22942 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
22943 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
22944 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
22945 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"},
22946 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"},
22947 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
22948 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
22949 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
22950 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
22951 {"cortex-a5", ARM_ARCH_V7A_MP_SEC,
22952 FPU_NONE, "Cortex-A5"},
22953 {"cortex-a8", ARM_ARCH_V7A_SEC,
22954 ARM_FEATURE (0, FPU_VFP_V3
22955 | FPU_NEON_EXT_V1),
22957 {"cortex-a9", ARM_ARCH_V7A_MP_SEC,
22958 ARM_FEATURE (0, FPU_VFP_V3
22959 | FPU_NEON_EXT_V1),
22961 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
22962 FPU_ARCH_NEON_VFP_V4,
22964 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
22965 {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
22967 {"cortex-r5", ARM_ARCH_V7R_IDIV,
22968 FPU_NONE, "Cortex-R5"},
22969 {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"},
22970 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"},
22971 {"cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"},
22972 {"cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"},
22973 /* ??? XSCALE is really an architecture. */
22974 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
22975 /* ??? iwmmxt is not a processor. */
22976 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
22977 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
22978 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
22980 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
22981 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
22984 struct arm_arch_option_table
22987 const arm_feature_set value;
22988 const arm_feature_set default_fpu;
22991 /* This list should, at a minimum, contain all the architecture names
22992 recognized by GCC. */
22993 static const struct arm_arch_option_table arm_archs[] =
22995 {"all", ARM_ANY, FPU_ARCH_FPA},
22996 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
22997 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
22998 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
22999 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
23000 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
23001 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
23002 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
23003 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
23004 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
23005 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
23006 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
23007 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
23008 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
23009 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
23010 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
23011 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
23012 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
23013 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
23014 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
23015 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
23016 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
23017 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
23018 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
23019 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
23020 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
23021 {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP},
23022 {"armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP},
23023 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
23024 /* The official spelling of the ARMv7 profile variants is the dashed form.
23025 Accept the non-dashed form for compatibility with old toolchains. */
23026 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
23027 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
23028 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
23029 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
23030 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
23031 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
23032 {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP},
23033 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
23034 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
23035 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
23036 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
23039 /* ISA extensions in the co-processor and main instruction set space. */
23040 struct arm_option_extension_value_table
23043 const arm_feature_set value;
23044 const arm_feature_set allowed_archs;
23047 /* The following table must be in alphabetical order with a NULL last entry.
23049 static const struct arm_option_extension_value_table arm_extensions[] =
23051 {"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23052 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
23053 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
23054 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
23055 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
23056 {"mp", ARM_FEATURE (ARM_EXT_MP, 0),
23057 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
23058 {"os", ARM_FEATURE (ARM_EXT_OS, 0),
23059 ARM_FEATURE (ARM_EXT_V6M, 0)},
23060 {"sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23061 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)},
23062 {"virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23063 ARM_FEATURE (ARM_EXT_V7A, 0)},
23064 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY},
23065 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
23068 /* ISA floating-point and Advanced SIMD extensions. */
23069 struct arm_option_fpu_value_table
23072 const arm_feature_set value;
23075 /* This list should, at a minimum, contain all the fpu names
23076 recognized by GCC. */
23077 static const struct arm_option_fpu_value_table arm_fpus[] =
23079 {"softfpa", FPU_NONE},
23080 {"fpe", FPU_ARCH_FPE},
23081 {"fpe2", FPU_ARCH_FPE},
23082 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23083 {"fpa", FPU_ARCH_FPA},
23084 {"fpa10", FPU_ARCH_FPA},
23085 {"fpa11", FPU_ARCH_FPA},
23086 {"arm7500fe", FPU_ARCH_FPA},
23087 {"softvfp", FPU_ARCH_VFP},
23088 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23089 {"vfp", FPU_ARCH_VFP_V2},
23090 {"vfp9", FPU_ARCH_VFP_V2},
23091 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23092 {"vfp10", FPU_ARCH_VFP_V2},
23093 {"vfp10-r0", FPU_ARCH_VFP_V1},
23094 {"vfpxd", FPU_ARCH_VFP_V1xD},
23095 {"vfpv2", FPU_ARCH_VFP_V2},
23096 {"vfpv3", FPU_ARCH_VFP_V3},
23097 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23098 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23099 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23100 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23101 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23102 {"arm1020t", FPU_ARCH_VFP_V1},
23103 {"arm1020e", FPU_ARCH_VFP_V2},
23104 {"arm1136jfs", FPU_ARCH_VFP_V2},
23105 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23106 {"maverick", FPU_ARCH_MAVERICK},
23107 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23108 {"neon-fp16", FPU_ARCH_NEON_FP16},
23109 {"vfpv4", FPU_ARCH_VFP_V4},
23110 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23111 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23112 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23113 {NULL, ARM_ARCH_NONE}
23116 struct arm_option_value_table
23122 static const struct arm_option_value_table arm_float_abis[] =
23124 {"hard", ARM_FLOAT_ABI_HARD},
23125 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23126 {"soft", ARM_FLOAT_ABI_SOFT},
23131 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23132 static const struct arm_option_value_table arm_eabis[] =
23134 {"gnu", EF_ARM_EABI_UNKNOWN},
23135 {"4", EF_ARM_EABI_VER4},
23136 {"5", EF_ARM_EABI_VER5},
23141 struct arm_long_option_table
23143 char * option; /* Substring to match. */
23144 char * help; /* Help information. */
23145 int (* func) (char * subopt); /* Function to decode sub-option. */
23146 char * deprecated; /* If non-null, print this message. */
23150 arm_parse_extension (char * str, const arm_feature_set **opt_p)
23152 arm_feature_set *ext_set = (arm_feature_set *)
23153 xmalloc (sizeof (arm_feature_set));
23155 /* We insist on extensions being specified in alphabetical order, and with
23156 extensions being added before being removed. We achieve this by having
23157 the global ARM_EXTENSIONS table in alphabetical order, and using the
23158 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23159 or removing it (0) and only allowing it to change in the order
23161 const struct arm_option_extension_value_table * opt = NULL;
23162 int adding_value = -1;
23164 /* Copy the feature set, so that we can modify it. */
23165 *ext_set = **opt_p;
23168 while (str != NULL && *str != 0)
23175 as_bad (_("invalid architectural extension"));
23180 ext = strchr (str, '+');
23183 optlen = ext - str;
23185 optlen = strlen (str);
23188 && strncmp (str, "no", 2) == 0)
23190 if (adding_value != 0)
23193 opt = arm_extensions;
23199 else if (optlen > 0)
23201 if (adding_value == -1)
23204 opt = arm_extensions;
23206 else if (adding_value != 1)
23208 as_bad (_("must specify extensions to add before specifying "
23209 "those to remove"));
23216 as_bad (_("missing architectural extension"));
23220 gas_assert (adding_value != -1);
23221 gas_assert (opt != NULL);
23223 /* Scan over the options table trying to find an exact match. */
23224 for (; opt->name != NULL; opt++)
23225 if (strncmp (opt->name, str, optlen) == 0
23226 && strlen (opt->name) == optlen)
23228 /* Check we can apply the extension to this architecture. */
23229 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23231 as_bad (_("extension does not apply to the base architecture"));
23235 /* Add or remove the extension. */
23237 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23239 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23244 if (opt->name == NULL)
23246 /* Did we fail to find an extension because it wasn't specified in
23247 alphabetical order, or because it does not exist? */
23249 for (opt = arm_extensions; opt->name != NULL; opt++)
23250 if (strncmp (opt->name, str, optlen) == 0)
23253 if (opt->name == NULL)
23254 as_bad (_("unknown architectural extension `%s'"), str);
23256 as_bad (_("architectural extensions must be specified in "
23257 "alphabetical order"));
23263 /* We should skip the extension we've just matched the next time
23275 arm_parse_cpu (char * str)
23277 const struct arm_cpu_option_table * opt;
23278 char * ext = strchr (str, '+');
23282 optlen = ext - str;
23284 optlen = strlen (str);
23288 as_bad (_("missing cpu name `%s'"), str);
23292 for (opt = arm_cpus; opt->name != NULL; opt++)
23293 if (strncmp (opt->name, str, optlen) == 0)
23295 mcpu_cpu_opt = &opt->value;
23296 mcpu_fpu_opt = &opt->default_fpu;
23297 if (opt->canonical_name)
23298 strcpy (selected_cpu_name, opt->canonical_name);
23303 for (i = 0; i < optlen; i++)
23304 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23305 selected_cpu_name[i] = 0;
23309 return arm_parse_extension (ext, &mcpu_cpu_opt);
23314 as_bad (_("unknown cpu `%s'"), str);
23319 arm_parse_arch (char * str)
23321 const struct arm_arch_option_table *opt;
23322 char *ext = strchr (str, '+');
23326 optlen = ext - str;
23328 optlen = strlen (str);
23332 as_bad (_("missing architecture name `%s'"), str);
23336 for (opt = arm_archs; opt->name != NULL; opt++)
23337 if (strncmp (opt->name, str, optlen) == 0)
23339 march_cpu_opt = &opt->value;
23340 march_fpu_opt = &opt->default_fpu;
23341 strcpy (selected_cpu_name, opt->name);
23344 return arm_parse_extension (ext, &march_cpu_opt);
23349 as_bad (_("unknown architecture `%s'\n"), str);
23354 arm_parse_fpu (char * str)
23356 const struct arm_option_fpu_value_table * opt;
23358 for (opt = arm_fpus; opt->name != NULL; opt++)
23359 if (streq (opt->name, str))
23361 mfpu_opt = &opt->value;
23365 as_bad (_("unknown floating point format `%s'\n"), str);
23370 arm_parse_float_abi (char * str)
23372 const struct arm_option_value_table * opt;
23374 for (opt = arm_float_abis; opt->name != NULL; opt++)
23375 if (streq (opt->name, str))
23377 mfloat_abi_opt = opt->value;
23381 as_bad (_("unknown floating point abi `%s'\n"), str);
23387 arm_parse_eabi (char * str)
23389 const struct arm_option_value_table *opt;
23391 for (opt = arm_eabis; opt->name != NULL; opt++)
23392 if (streq (opt->name, str))
23394 meabi_flags = opt->value;
23397 as_bad (_("unknown EABI `%s'\n"), str);
23403 arm_parse_it_mode (char * str)
23405 bfd_boolean ret = TRUE;
23407 if (streq ("arm", str))
23408 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23409 else if (streq ("thumb", str))
23410 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23411 else if (streq ("always", str))
23412 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23413 else if (streq ("never", str))
23414 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23417 as_bad (_("unknown implicit IT mode `%s', should be "\
23418 "arm, thumb, always, or never."), str);
23425 struct arm_long_option_table arm_long_opts[] =
23427 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23428 arm_parse_cpu, NULL},
23429 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23430 arm_parse_arch, NULL},
23431 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23432 arm_parse_fpu, NULL},
23433 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23434 arm_parse_float_abi, NULL},
23436 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23437 arm_parse_eabi, NULL},
23439 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23440 arm_parse_it_mode, NULL},
23441 {NULL, NULL, 0, NULL}
23445 md_parse_option (int c, char * arg)
23447 struct arm_option_table *opt;
23448 const struct arm_legacy_option_table *fopt;
23449 struct arm_long_option_table *lopt;
23455 target_big_endian = 1;
23461 target_big_endian = 0;
23465 case OPTION_FIX_V4BX:
23470 /* Listing option. Just ignore these, we don't support additional
23475 for (opt = arm_opts; opt->option != NULL; opt++)
23477 if (c == opt->option[0]
23478 && ((arg == NULL && opt->option[1] == 0)
23479 || streq (arg, opt->option + 1)))
23481 /* If the option is deprecated, tell the user. */
23482 if (warn_on_deprecated && opt->deprecated != NULL)
23483 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23484 arg ? arg : "", _(opt->deprecated));
23486 if (opt->var != NULL)
23487 *opt->var = opt->value;
23493 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23495 if (c == fopt->option[0]
23496 && ((arg == NULL && fopt->option[1] == 0)
23497 || streq (arg, fopt->option + 1)))
23499 /* If the option is deprecated, tell the user. */
23500 if (warn_on_deprecated && fopt->deprecated != NULL)
23501 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23502 arg ? arg : "", _(fopt->deprecated));
23504 if (fopt->var != NULL)
23505 *fopt->var = &fopt->value;
23511 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23513 /* These options are expected to have an argument. */
23514 if (c == lopt->option[0]
23516 && strncmp (arg, lopt->option + 1,
23517 strlen (lopt->option + 1)) == 0)
23519 /* If the option is deprecated, tell the user. */
23520 if (warn_on_deprecated && lopt->deprecated != NULL)
23521 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23522 _(lopt->deprecated));
23524 /* Call the sup-option parser. */
23525 return lopt->func (arg + strlen (lopt->option) - 1);
23536 md_show_usage (FILE * fp)
23538 struct arm_option_table *opt;
23539 struct arm_long_option_table *lopt;
23541 fprintf (fp, _(" ARM-specific assembler options:\n"));
23543 for (opt = arm_opts; opt->option != NULL; opt++)
23544 if (opt->help != NULL)
23545 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23547 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23548 if (lopt->help != NULL)
23549 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23553 -EB assemble code for a big-endian cpu\n"));
23558 -EL assemble code for a little-endian cpu\n"));
23562 --fix-v4bx Allow BX in ARMv4 code\n"));
23570 arm_feature_set flags;
23571 } cpu_arch_ver_table;
23573 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23574 least features first. */
23575 static const cpu_arch_ver_table cpu_arch_ver[] =
23581 {4, ARM_ARCH_V5TE},
23582 {5, ARM_ARCH_V5TEJ},
23586 {11, ARM_ARCH_V6M},
23587 {12, ARM_ARCH_V6SM},
23588 {8, ARM_ARCH_V6T2},
23589 {10, ARM_ARCH_V7A},
23590 {10, ARM_ARCH_V7R},
23591 {10, ARM_ARCH_V7M},
23595 /* Set an attribute if it has not already been set by the user. */
23597 aeabi_set_attribute_int (int tag, int value)
23600 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23601 || !attributes_set_explicitly[tag])
23602 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23606 aeabi_set_attribute_string (int tag, const char *value)
23609 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23610 || !attributes_set_explicitly[tag])
23611 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23614 /* Set the public EABI object attributes. */
23616 aeabi_set_public_attributes (void)
23620 arm_feature_set flags;
23621 arm_feature_set tmp;
23622 const cpu_arch_ver_table *p;
23624 /* Choose the architecture based on the capabilities of the requested cpu
23625 (if any) and/or the instructions actually used. */
23626 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23627 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23628 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23629 /*Allow the user to override the reported architecture. */
23632 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23633 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23636 /* We need to make sure that the attributes do not identify us as v6S-M
23637 when the only v6S-M feature in use is the Operating System Extensions. */
23638 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23639 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23640 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23644 for (p = cpu_arch_ver; p->val; p++)
23646 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23649 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23653 /* The table lookup above finds the last architecture to contribute
23654 a new feature. Unfortunately, Tag13 is a subset of the union of
23655 v6T2 and v7-M, so it is never seen as contributing a new feature.
23656 We can not search for the last entry which is entirely used,
23657 because if no CPU is specified we build up only those flags
23658 actually used. Perhaps we should separate out the specified
23659 and implicit cases. Avoid taking this path for -march=all by
23660 checking for contradictory v7-A / v7-M features. */
23662 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23663 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23664 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23667 /* Tag_CPU_name. */
23668 if (selected_cpu_name[0])
23672 q = selected_cpu_name;
23673 if (strncmp (q, "armv", 4) == 0)
23678 for (i = 0; q[i]; i++)
23679 q[i] = TOUPPER (q[i]);
23681 aeabi_set_attribute_string (Tag_CPU_name, q);
23684 /* Tag_CPU_arch. */
23685 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23687 /* Tag_CPU_arch_profile. */
23688 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23689 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A');
23690 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23691 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R');
23692 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23693 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M');
23695 /* Tag_ARM_ISA_use. */
23696 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23698 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23700 /* Tag_THUMB_ISA_use. */
23701 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23703 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23704 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23706 /* Tag_VFP_arch. */
23707 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23708 aeabi_set_attribute_int (Tag_VFP_arch,
23709 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23711 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23712 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23713 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23714 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23715 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23716 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23717 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23718 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23719 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23721 /* Tag_ABI_HardFP_use. */
23722 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23723 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23724 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23726 /* Tag_WMMX_arch. */
23727 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23728 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23729 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23730 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23732 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23733 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23734 aeabi_set_attribute_int
23735 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
23738 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23739 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
23740 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23743 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
23744 aeabi_set_attribute_int (Tag_DIV_use, 2);
23745 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
23746 aeabi_set_attribute_int (Tag_DIV_use, 0);
23748 aeabi_set_attribute_int (Tag_DIV_use, 1);
23750 /* Tag_MP_extension_use. */
23751 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23752 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23754 /* Tag Virtualization_use. */
23755 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
23757 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
23760 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
23763 /* Add the default contents for the .ARM.attributes section. */
23767 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23770 aeabi_set_public_attributes ();
23772 #endif /* OBJ_ELF */
23775 /* Parse a .cpu directive. */
23778 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
23780 const struct arm_cpu_option_table *opt;
23784 name = input_line_pointer;
23785 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23786 input_line_pointer++;
23787 saved_char = *input_line_pointer;
23788 *input_line_pointer = 0;
23790 /* Skip the first "all" entry. */
23791 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
23792 if (streq (opt->name, name))
23794 mcpu_cpu_opt = &opt->value;
23795 selected_cpu = opt->value;
23796 if (opt->canonical_name)
23797 strcpy (selected_cpu_name, opt->canonical_name);
23801 for (i = 0; opt->name[i]; i++)
23802 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23803 selected_cpu_name[i] = 0;
23805 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23806 *input_line_pointer = saved_char;
23807 demand_empty_rest_of_line ();
23810 as_bad (_("unknown cpu `%s'"), name);
23811 *input_line_pointer = saved_char;
23812 ignore_rest_of_line ();
23816 /* Parse a .arch directive. */
23819 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
23821 const struct arm_arch_option_table *opt;
23825 name = input_line_pointer;
23826 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23827 input_line_pointer++;
23828 saved_char = *input_line_pointer;
23829 *input_line_pointer = 0;
23831 /* Skip the first "all" entry. */
23832 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23833 if (streq (opt->name, name))
23835 mcpu_cpu_opt = &opt->value;
23836 selected_cpu = opt->value;
23837 strcpy (selected_cpu_name, opt->name);
23838 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23839 *input_line_pointer = saved_char;
23840 demand_empty_rest_of_line ();
23844 as_bad (_("unknown architecture `%s'\n"), name);
23845 *input_line_pointer = saved_char;
23846 ignore_rest_of_line ();
23850 /* Parse a .object_arch directive. */
23853 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
23855 const struct arm_arch_option_table *opt;
23859 name = input_line_pointer;
23860 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23861 input_line_pointer++;
23862 saved_char = *input_line_pointer;
23863 *input_line_pointer = 0;
23865 /* Skip the first "all" entry. */
23866 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23867 if (streq (opt->name, name))
23869 object_arch = &opt->value;
23870 *input_line_pointer = saved_char;
23871 demand_empty_rest_of_line ();
23875 as_bad (_("unknown architecture `%s'\n"), name);
23876 *input_line_pointer = saved_char;
23877 ignore_rest_of_line ();
23880 /* Parse a .arch_extension directive. */
23883 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
23885 const struct arm_option_extension_value_table *opt;
23888 int adding_value = 1;
23890 name = input_line_pointer;
23891 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23892 input_line_pointer++;
23893 saved_char = *input_line_pointer;
23894 *input_line_pointer = 0;
23896 if (strlen (name) >= 2
23897 && strncmp (name, "no", 2) == 0)
23903 for (opt = arm_extensions; opt->name != NULL; opt++)
23904 if (streq (opt->name, name))
23906 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
23908 as_bad (_("architectural extension `%s' is not allowed for the "
23909 "current base architecture"), name);
23914 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
23916 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
23918 mcpu_cpu_opt = &selected_cpu;
23919 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23920 *input_line_pointer = saved_char;
23921 demand_empty_rest_of_line ();
23925 if (opt->name == NULL)
23926 as_bad (_("unknown architecture `%s'\n"), name);
23928 *input_line_pointer = saved_char;
23929 ignore_rest_of_line ();
23932 /* Parse a .fpu directive. */
23935 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
23937 const struct arm_option_fpu_value_table *opt;
23941 name = input_line_pointer;
23942 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23943 input_line_pointer++;
23944 saved_char = *input_line_pointer;
23945 *input_line_pointer = 0;
23947 for (opt = arm_fpus; opt->name != NULL; opt++)
23948 if (streq (opt->name, name))
23950 mfpu_opt = &opt->value;
23951 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23952 *input_line_pointer = saved_char;
23953 demand_empty_rest_of_line ();
23957 as_bad (_("unknown floating point format `%s'\n"), name);
23958 *input_line_pointer = saved_char;
23959 ignore_rest_of_line ();
23962 /* Copy symbol information. */
23965 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
23967 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
23971 /* Given a symbolic attribute NAME, return the proper integer value.
23972 Returns -1 if the attribute is not known. */
23975 arm_convert_symbolic_attribute (const char *name)
23977 static const struct
23982 attribute_table[] =
23984 /* When you modify this table you should
23985 also modify the list in doc/c-arm.texi. */
23986 #define T(tag) {#tag, tag}
23987 T (Tag_CPU_raw_name),
23990 T (Tag_CPU_arch_profile),
23991 T (Tag_ARM_ISA_use),
23992 T (Tag_THUMB_ISA_use),
23996 T (Tag_Advanced_SIMD_arch),
23997 T (Tag_PCS_config),
23998 T (Tag_ABI_PCS_R9_use),
23999 T (Tag_ABI_PCS_RW_data),
24000 T (Tag_ABI_PCS_RO_data),
24001 T (Tag_ABI_PCS_GOT_use),
24002 T (Tag_ABI_PCS_wchar_t),
24003 T (Tag_ABI_FP_rounding),
24004 T (Tag_ABI_FP_denormal),
24005 T (Tag_ABI_FP_exceptions),
24006 T (Tag_ABI_FP_user_exceptions),
24007 T (Tag_ABI_FP_number_model),
24008 T (Tag_ABI_align_needed),
24009 T (Tag_ABI_align8_needed),
24010 T (Tag_ABI_align_preserved),
24011 T (Tag_ABI_align8_preserved),
24012 T (Tag_ABI_enum_size),
24013 T (Tag_ABI_HardFP_use),
24014 T (Tag_ABI_VFP_args),
24015 T (Tag_ABI_WMMX_args),
24016 T (Tag_ABI_optimization_goals),
24017 T (Tag_ABI_FP_optimization_goals),
24018 T (Tag_compatibility),
24019 T (Tag_CPU_unaligned_access),
24020 T (Tag_FP_HP_extension),
24021 T (Tag_VFP_HP_extension),
24022 T (Tag_ABI_FP_16bit_format),
24023 T (Tag_MPextension_use),
24025 T (Tag_nodefaults),
24026 T (Tag_also_compatible_with),
24027 T (Tag_conformance),
24029 T (Tag_Virtualization_use),
24030 /* We deliberately do not include Tag_MPextension_use_legacy. */
24038 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24039 if (streq (name, attribute_table[i].name))
24040 return attribute_table[i].tag;
24046 /* Apply sym value for relocations only in the case that
24047 they are for local symbols and you have the respective
24048 architectural feature for blx and simple switches. */
24050 arm_apply_sym_value (struct fix * fixP)
24053 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24054 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24056 switch (fixP->fx_r_type)
24058 case BFD_RELOC_ARM_PCREL_BLX:
24059 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24060 if (ARM_IS_FUNC (fixP->fx_addsy))
24064 case BFD_RELOC_ARM_PCREL_CALL:
24065 case BFD_RELOC_THUMB_PCREL_BLX:
24066 if (THUMB_IS_FUNC (fixP->fx_addsy))
24077 #endif /* OBJ_ELF */