1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
201 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
202 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
203 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
204 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
206 static const arm_feature_set arm_arch_any = ARM_ANY;
207 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
209 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
210 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
212 static const arm_feature_set arm_cext_iwmmxt2 =
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
214 static const arm_feature_set arm_cext_iwmmxt =
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
216 static const arm_feature_set arm_cext_xscale =
217 ARM_FEATURE (0, ARM_CEXT_XSCALE);
218 static const arm_feature_set arm_cext_maverick =
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
220 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
221 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
222 static const arm_feature_set fpu_vfp_ext_v1xd =
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
224 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
225 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
226 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
227 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
228 static const arm_feature_set fpu_vfp_ext_d32 =
229 ARM_FEATURE (0, FPU_VFP_EXT_D32);
230 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
233 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
234 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static int mfloat_abi_opt = -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu.core == arm_arch_none.core
248 && selected_cpu.coproc == arm_arch_none.coproc;
253 static int meabi_flags = EABI_DEFAULT;
255 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
258 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
263 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS * GOT_symbol;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode = 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER = 0x00,
286 IMPLICIT_IT_MODE_ARM = 0x01,
287 IMPLICIT_IT_MODE_THUMB = 0x02,
288 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
290 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax = FALSE;
330 enum neon_el_type type;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el[NEON_MAX_TYPE_ELS];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN /* The IT insn has been parsed. */
354 /* The maximum number of operands we need. */
355 #define ARM_IT_MAX_OPERANDS 6
360 unsigned long instruction;
364 /* "uncond_value" is set to the value in place of the conditional field in
365 unconditional versions of the instruction, or -1 if nothing is
368 struct neon_type vectype;
369 /* This does not indicate an actual NEON instruction, only that
370 the mnemonic accepts neon-style type suffixes. */
372 /* Set to the opcode if the instruction needs relaxation.
373 Zero if the instruction is not relaxed. */
377 bfd_reloc_code_real_type type;
382 enum it_instruction_type it_insn_type;
388 struct neon_type_el vectype;
389 unsigned present : 1; /* Operand present. */
390 unsigned isreg : 1; /* Operand was a register. */
391 unsigned immisreg : 1; /* .imm field is a second register. */
392 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
393 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
394 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
395 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
396 instructions. This allows us to disambiguate ARM <-> vector insns. */
397 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
398 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
399 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
400 unsigned issingle : 1; /* Operand is VFP single-precision register. */
401 unsigned hasreloc : 1; /* Operand has relocation suffix. */
402 unsigned writeback : 1; /* Operand has trailing ! */
403 unsigned preind : 1; /* Preindexed address. */
404 unsigned postind : 1; /* Postindexed address. */
405 unsigned negative : 1; /* Index register was negated. */
406 unsigned shifted : 1; /* Shift applied to operation. */
407 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
408 } operands[ARM_IT_MAX_OPERANDS];
411 static struct arm_it inst;
413 #define NUM_FLOAT_VALS 8
415 const char * fp_const[] =
417 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
420 /* Number of littlenums required to hold an extended precision number. */
421 #define MAX_LITTLENUMS 6
423 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
433 #define CP_T_X 0x00008000
434 #define CP_T_Y 0x00400000
436 #define CONDS_BIT 0x00100000
437 #define LOAD_BIT 0x00100000
439 #define DOUBLE_LOAD_FLAG 0x00000001
443 const char * template_name;
447 #define COND_ALWAYS 0xE
451 const char * template_name;
455 struct asm_barrier_opt
457 const char * template_name;
461 /* The bit that distinguishes CPSR and SPSR. */
462 #define SPSR_BIT (1 << 22)
464 /* The individual PSR flag bits. */
465 #define PSR_c (1 << 16)
466 #define PSR_x (1 << 17)
467 #define PSR_s (1 << 18)
468 #define PSR_f (1 << 19)
473 bfd_reloc_code_real_type reloc;
478 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
479 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
484 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
487 /* Bits for DEFINED field in neon_typed_alias. */
488 #define NTA_HASTYPE 1
489 #define NTA_HASINDEX 2
491 struct neon_typed_alias
493 unsigned char defined;
495 struct neon_type_el eltype;
498 /* ARM register categories. This includes coprocessor numbers and various
499 architecture extensions' registers. */
526 /* Structure for a hash table entry for a register.
527 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
528 information which states whether a vector type or index is specified (for a
529 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
535 unsigned char builtin;
536 struct neon_typed_alias * neon;
539 /* Diagnostics used when we don't get a register of the expected type. */
540 const char * const reg_expected_msgs[] =
542 N_("ARM register expected"),
543 N_("bad or missing co-processor number"),
544 N_("co-processor register expected"),
545 N_("FPA register expected"),
546 N_("VFP single precision register expected"),
547 N_("VFP/Neon double precision register expected"),
548 N_("Neon quad precision register expected"),
549 N_("VFP single or double precision register expected"),
550 N_("Neon double or quad precision register expected"),
551 N_("VFP single, double or Neon quad precision register expected"),
552 N_("VFP system register expected"),
553 N_("Maverick MVF register expected"),
554 N_("Maverick MVD register expected"),
555 N_("Maverick MVFX register expected"),
556 N_("Maverick MVDX register expected"),
557 N_("Maverick MVAX register expected"),
558 N_("Maverick DSPSC register expected"),
559 N_("iWMMXt data register expected"),
560 N_("iWMMXt control register expected"),
561 N_("iWMMXt scalar register expected"),
562 N_("XScale accumulator register expected"),
565 /* Some well known registers that we refer to directly elsewhere. */
571 /* ARM instructions take 4bytes in the object file, Thumb instructions
577 /* Basic string to match. */
578 const char * template_name;
580 /* Parameters to instruction. */
581 unsigned int operands[8];
583 /* Conditional tag - see opcode_lookup. */
584 unsigned int tag : 4;
586 /* Basic instruction code. */
587 unsigned int avalue : 28;
589 /* Thumb-format instruction code. */
592 /* Which architecture variant provides this instruction. */
593 const arm_feature_set * avariant;
594 const arm_feature_set * tvariant;
596 /* Function to call to encode instruction in ARM format. */
597 void (* aencode) (void);
599 /* Function to call to encode instruction in Thumb format. */
600 void (* tencode) (void);
603 /* Defines for various bits that we will want to toggle. */
604 #define INST_IMMEDIATE 0x02000000
605 #define OFFSET_REG 0x02000000
606 #define HWOFFSET_IMM 0x00400000
607 #define SHIFT_BY_REG 0x00000010
608 #define PRE_INDEX 0x01000000
609 #define INDEX_UP 0x00800000
610 #define WRITE_BACK 0x00200000
611 #define LDM_TYPE_2_OR_3 0x00400000
612 #define CPSI_MMOD 0x00020000
614 #define LITERAL_MASK 0xf000f000
615 #define OPCODE_MASK 0xfe1fffff
616 #define V4_STR_BIT 0x00000020
618 #define T2_SUBS_PC_LR 0xf3de8f00
620 #define DATA_OP_SHIFT 21
622 #define T2_OPCODE_MASK 0xfe1fffff
623 #define T2_DATA_OP_SHIFT 21
625 #define A_COND_MASK 0xf0000000
626 #define A_PUSH_POP_OP_MASK 0x0fff0000
628 /* Opcodes for pushing/poping registers to/from the stack. */
629 #define A1_OPCODE_PUSH 0x092d0000
630 #define A2_OPCODE_PUSH 0x052d0004
631 #define A2_OPCODE_POP 0x049d0004
633 /* Codes to distinguish the arithmetic instructions. */
644 #define OPCODE_CMP 10
645 #define OPCODE_CMN 11
646 #define OPCODE_ORR 12
647 #define OPCODE_MOV 13
648 #define OPCODE_BIC 14
649 #define OPCODE_MVN 15
651 #define T2_OPCODE_AND 0
652 #define T2_OPCODE_BIC 1
653 #define T2_OPCODE_ORR 2
654 #define T2_OPCODE_ORN 3
655 #define T2_OPCODE_EOR 4
656 #define T2_OPCODE_ADD 8
657 #define T2_OPCODE_ADC 10
658 #define T2_OPCODE_SBC 11
659 #define T2_OPCODE_SUB 13
660 #define T2_OPCODE_RSB 14
662 #define T_OPCODE_MUL 0x4340
663 #define T_OPCODE_TST 0x4200
664 #define T_OPCODE_CMN 0x42c0
665 #define T_OPCODE_NEG 0x4240
666 #define T_OPCODE_MVN 0x43c0
668 #define T_OPCODE_ADD_R3 0x1800
669 #define T_OPCODE_SUB_R3 0x1a00
670 #define T_OPCODE_ADD_HI 0x4400
671 #define T_OPCODE_ADD_ST 0xb000
672 #define T_OPCODE_SUB_ST 0xb080
673 #define T_OPCODE_ADD_SP 0xa800
674 #define T_OPCODE_ADD_PC 0xa000
675 #define T_OPCODE_ADD_I8 0x3000
676 #define T_OPCODE_SUB_I8 0x3800
677 #define T_OPCODE_ADD_I3 0x1c00
678 #define T_OPCODE_SUB_I3 0x1e00
680 #define T_OPCODE_ASR_R 0x4100
681 #define T_OPCODE_LSL_R 0x4080
682 #define T_OPCODE_LSR_R 0x40c0
683 #define T_OPCODE_ROR_R 0x41c0
684 #define T_OPCODE_ASR_I 0x1000
685 #define T_OPCODE_LSL_I 0x0000
686 #define T_OPCODE_LSR_I 0x0800
688 #define T_OPCODE_MOV_I8 0x2000
689 #define T_OPCODE_CMP_I8 0x2800
690 #define T_OPCODE_CMP_LR 0x4280
691 #define T_OPCODE_MOV_HR 0x4600
692 #define T_OPCODE_CMP_HR 0x4500
694 #define T_OPCODE_LDR_PC 0x4800
695 #define T_OPCODE_LDR_SP 0x9800
696 #define T_OPCODE_STR_SP 0x9000
697 #define T_OPCODE_LDR_IW 0x6800
698 #define T_OPCODE_STR_IW 0x6000
699 #define T_OPCODE_LDR_IH 0x8800
700 #define T_OPCODE_STR_IH 0x8000
701 #define T_OPCODE_LDR_IB 0x7800
702 #define T_OPCODE_STR_IB 0x7000
703 #define T_OPCODE_LDR_RW 0x5800
704 #define T_OPCODE_STR_RW 0x5000
705 #define T_OPCODE_LDR_RH 0x5a00
706 #define T_OPCODE_STR_RH 0x5200
707 #define T_OPCODE_LDR_RB 0x5c00
708 #define T_OPCODE_STR_RB 0x5400
710 #define T_OPCODE_PUSH 0xb400
711 #define T_OPCODE_POP 0xbc00
713 #define T_OPCODE_BRANCH 0xe000
715 #define THUMB_SIZE 2 /* Size of thumb instruction. */
716 #define THUMB_PP_PC_LR 0x0100
717 #define THUMB_LOAD_BIT 0x0800
718 #define THUMB2_LOAD_BIT 0x00100000
720 #define BAD_ARGS _("bad arguments to instruction")
721 #define BAD_SP _("r13 not allowed here")
722 #define BAD_PC _("r15 not allowed here")
723 #define BAD_COND _("instruction cannot be conditional")
724 #define BAD_OVERLAP _("registers may not be the same")
725 #define BAD_HIREG _("lo register required")
726 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
727 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
728 #define BAD_BRANCH _("branch must be last instruction in IT block")
729 #define BAD_NOT_IT _("instruction not allowed in IT block")
730 #define BAD_FPU _("selected FPU does not support instruction")
731 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
732 #define BAD_IT_COND _("incorrect condition in IT block")
733 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
734 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
735 #define BAD_PC_ADDRESSING \
736 _("cannot use register index with PC-relative addressing")
737 #define BAD_PC_WRITEBACK \
738 _("cannot use writeback with PC-relative addressing")
739 #define BAD_RANGE _("branch out of range")
741 static struct hash_control * arm_ops_hsh;
742 static struct hash_control * arm_cond_hsh;
743 static struct hash_control * arm_shift_hsh;
744 static struct hash_control * arm_psr_hsh;
745 static struct hash_control * arm_v7m_psr_hsh;
746 static struct hash_control * arm_reg_hsh;
747 static struct hash_control * arm_reloc_hsh;
748 static struct hash_control * arm_barrier_opt_hsh;
750 /* Stuff needed to resolve the label ambiguity
759 symbolS * last_label_seen;
760 static int label_is_thumb_function_name = FALSE;
762 /* Literal pool structure. Held on a per-section
763 and per-sub-section basis. */
765 #define MAX_LITERAL_POOL_SIZE 1024
766 typedef struct literal_pool
768 expressionS literals [MAX_LITERAL_POOL_SIZE];
769 unsigned int next_free_entry;
775 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
777 struct literal_pool * next;
780 /* Pointer to a linked list of literal pools. */
781 literal_pool * list_of_pools = NULL;
784 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
786 static struct current_it now_it;
790 now_it_compatible (int cond)
792 return (cond & ~1) == (now_it.cc & ~1);
796 conditional_insn (void)
798 return inst.cond != COND_ALWAYS;
801 static int in_it_block (void);
803 static int handle_it_state (void);
805 static void force_automatic_it_block_close (void);
807 static void it_fsm_post_encode (void);
809 #define set_it_insn_type(type) \
812 inst.it_insn_type = type; \
813 if (handle_it_state () == FAIL) \
818 #define set_it_insn_type_nonvoid(type, failret) \
821 inst.it_insn_type = type; \
822 if (handle_it_state () == FAIL) \
827 #define set_it_insn_type_last() \
830 if (inst.cond == COND_ALWAYS) \
831 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
833 set_it_insn_type (INSIDE_IT_LAST_INSN); \
839 /* This array holds the chars that always start a comment. If the
840 pre-processor is disabled, these aren't very useful. */
841 const char comment_chars[] = "@";
843 /* This array holds the chars that only start a comment at the beginning of
844 a line. If the line seems to have the form '# 123 filename'
845 .line and .file directives will appear in the pre-processed output. */
846 /* Note that input_file.c hand checks for '#' at the beginning of the
847 first line of the input file. This is because the compiler outputs
848 #NO_APP at the beginning of its output. */
849 /* Also note that comments like this one will always work. */
850 const char line_comment_chars[] = "#";
852 const char line_separator_chars[] = ";";
854 /* Chars that can be used to separate mant
855 from exp in floating point numbers. */
856 const char EXP_CHARS[] = "eE";
858 /* Chars that mean this number is a floating point constant. */
862 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
864 /* Prefix characters that indicate the start of an immediate
866 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
868 /* Separator character handling. */
870 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
873 skip_past_char (char ** str, char c)
884 #define skip_past_comma(str) skip_past_char (str, ',')
886 /* Arithmetic expressions (possibly involving symbols). */
888 /* Return TRUE if anything in the expression is a bignum. */
891 walk_no_bignums (symbolS * sp)
893 if (symbol_get_value_expression (sp)->X_op == O_big)
896 if (symbol_get_value_expression (sp)->X_add_symbol)
898 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
899 || (symbol_get_value_expression (sp)->X_op_symbol
900 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
906 static int in_my_get_expression = 0;
908 /* Third argument to my_get_expression. */
909 #define GE_NO_PREFIX 0
910 #define GE_IMM_PREFIX 1
911 #define GE_OPT_PREFIX 2
912 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
913 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
914 #define GE_OPT_PREFIX_BIG 3
917 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
922 /* In unified syntax, all prefixes are optional. */
924 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
929 case GE_NO_PREFIX: break;
931 if (!is_immediate_prefix (**str))
933 inst.error = _("immediate expression requires a # prefix");
939 case GE_OPT_PREFIX_BIG:
940 if (is_immediate_prefix (**str))
946 memset (ep, 0, sizeof (expressionS));
948 save_in = input_line_pointer;
949 input_line_pointer = *str;
950 in_my_get_expression = 1;
951 seg = expression (ep);
952 in_my_get_expression = 0;
954 if (ep->X_op == O_illegal || ep->X_op == O_absent)
956 /* We found a bad or missing expression in md_operand(). */
957 *str = input_line_pointer;
958 input_line_pointer = save_in;
959 if (inst.error == NULL)
960 inst.error = (ep->X_op == O_absent
961 ? _("missing expression") :_("bad expression"));
966 if (seg != absolute_section
967 && seg != text_section
968 && seg != data_section
969 && seg != bss_section
970 && seg != undefined_section)
972 inst.error = _("bad segment");
973 *str = input_line_pointer;
974 input_line_pointer = save_in;
981 /* Get rid of any bignums now, so that we don't generate an error for which
982 we can't establish a line number later on. Big numbers are never valid
983 in instructions, which is where this routine is always called. */
984 if (prefix_mode != GE_OPT_PREFIX_BIG
985 && (ep->X_op == O_big
987 && (walk_no_bignums (ep->X_add_symbol)
989 && walk_no_bignums (ep->X_op_symbol))))))
991 inst.error = _("invalid constant");
992 *str = input_line_pointer;
993 input_line_pointer = save_in;
997 *str = input_line_pointer;
998 input_line_pointer = save_in;
1002 /* Turn a string in input_line_pointer into a floating point constant
1003 of type TYPE, and store the appropriate bytes in *LITP. The number
1004 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1005 returned, or NULL on OK.
1007 Note that fp constants aren't represent in the normal way on the ARM.
1008 In big endian mode, things are as expected. However, in little endian
1009 mode fp constants are big-endian word-wise, and little-endian byte-wise
1010 within the words. For example, (double) 1.1 in big endian mode is
1011 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1012 the byte sequence 99 99 f1 3f 9a 99 99 99.
1014 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1017 md_atof (int type, char * litP, int * sizeP)
1020 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1052 return _("Unrecognized or unsupported floating point constant");
1055 t = atof_ieee (input_line_pointer, type, words);
1057 input_line_pointer = t;
1058 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1060 if (target_big_endian)
1062 for (i = 0; i < prec; i++)
1064 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1065 litP += sizeof (LITTLENUM_TYPE);
1070 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1071 for (i = prec - 1; i >= 0; i--)
1073 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1074 litP += sizeof (LITTLENUM_TYPE);
1077 /* For a 4 byte float the order of elements in `words' is 1 0.
1078 For an 8 byte float the order is 1 0 3 2. */
1079 for (i = 0; i < prec; i += 2)
1081 md_number_to_chars (litP, (valueT) words[i + 1],
1082 sizeof (LITTLENUM_TYPE));
1083 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1084 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1085 litP += 2 * sizeof (LITTLENUM_TYPE);
1092 /* We handle all bad expressions here, so that we can report the faulty
1093 instruction in the error message. */
1095 md_operand (expressionS * exp)
1097 if (in_my_get_expression)
1098 exp->X_op = O_illegal;
1101 /* Immediate values. */
1103 /* Generic immediate-value read function for use in directives.
1104 Accepts anything that 'expression' can fold to a constant.
1105 *val receives the number. */
1108 immediate_for_directive (int *val)
1111 exp.X_op = O_illegal;
1113 if (is_immediate_prefix (*input_line_pointer))
1115 input_line_pointer++;
1119 if (exp.X_op != O_constant)
1121 as_bad (_("expected #constant"));
1122 ignore_rest_of_line ();
1125 *val = exp.X_add_number;
1130 /* Register parsing. */
1132 /* Generic register parser. CCP points to what should be the
1133 beginning of a register name. If it is indeed a valid register
1134 name, advance CCP over it and return the reg_entry structure;
1135 otherwise return NULL. Does not issue diagnostics. */
1137 static struct reg_entry *
1138 arm_reg_parse_multi (char **ccp)
1142 struct reg_entry *reg;
1144 #ifdef REGISTER_PREFIX
1145 if (*start != REGISTER_PREFIX)
1149 #ifdef OPTIONAL_REGISTER_PREFIX
1150 if (*start == OPTIONAL_REGISTER_PREFIX)
1155 if (!ISALPHA (*p) || !is_name_beginner (*p))
1160 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1162 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1172 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1173 enum arm_reg_type type)
1175 /* Alternative syntaxes are accepted for a few register classes. */
1182 /* Generic coprocessor register names are allowed for these. */
1183 if (reg && reg->type == REG_TYPE_CN)
1188 /* For backward compatibility, a bare number is valid here. */
1190 unsigned long processor = strtoul (start, ccp, 10);
1191 if (*ccp != start && processor <= 15)
1195 case REG_TYPE_MMXWC:
1196 /* WC includes WCG. ??? I'm not sure this is true for all
1197 instructions that take WC registers. */
1198 if (reg && reg->type == REG_TYPE_MMXWCG)
1209 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1210 return value is the register number or FAIL. */
1213 arm_reg_parse (char **ccp, enum arm_reg_type type)
1216 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1219 /* Do not allow a scalar (reg+index) to parse as a register. */
1220 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1223 if (reg && reg->type == type)
1226 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1233 /* Parse a Neon type specifier. *STR should point at the leading '.'
1234 character. Does no verification at this stage that the type fits the opcode
1241 Can all be legally parsed by this function.
1243 Fills in neon_type struct pointer with parsed information, and updates STR
1244 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1245 type, FAIL if not. */
1248 parse_neon_type (struct neon_type *type, char **str)
1255 while (type->elems < NEON_MAX_TYPE_ELS)
1257 enum neon_el_type thistype = NT_untyped;
1258 unsigned thissize = -1u;
1265 /* Just a size without an explicit type. */
1269 switch (TOLOWER (*ptr))
1271 case 'i': thistype = NT_integer; break;
1272 case 'f': thistype = NT_float; break;
1273 case 'p': thistype = NT_poly; break;
1274 case 's': thistype = NT_signed; break;
1275 case 'u': thistype = NT_unsigned; break;
1277 thistype = NT_float;
1282 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1288 /* .f is an abbreviation for .f32. */
1289 if (thistype == NT_float && !ISDIGIT (*ptr))
1294 thissize = strtoul (ptr, &ptr, 10);
1296 if (thissize != 8 && thissize != 16 && thissize != 32
1299 as_bad (_("bad size %d in type specifier"), thissize);
1307 type->el[type->elems].type = thistype;
1308 type->el[type->elems].size = thissize;
1313 /* Empty/missing type is not a successful parse. */
1314 if (type->elems == 0)
1322 /* Errors may be set multiple times during parsing or bit encoding
1323 (particularly in the Neon bits), but usually the earliest error which is set
1324 will be the most meaningful. Avoid overwriting it with later (cascading)
1325 errors by calling this function. */
1328 first_error (const char *err)
1334 /* Parse a single type, e.g. ".s32", leading period included. */
1336 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1339 struct neon_type optype;
1343 if (parse_neon_type (&optype, &str) == SUCCESS)
1345 if (optype.elems == 1)
1346 *vectype = optype.el[0];
1349 first_error (_("only one type should be specified for operand"));
1355 first_error (_("vector type expected"));
1367 /* Special meanings for indices (which have a range of 0-7), which will fit into
1370 #define NEON_ALL_LANES 15
1371 #define NEON_INTERLEAVE_LANES 14
1373 /* Parse either a register or a scalar, with an optional type. Return the
1374 register number, and optionally fill in the actual type of the register
1375 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1376 type/index information in *TYPEINFO. */
1379 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1380 enum arm_reg_type *rtype,
1381 struct neon_typed_alias *typeinfo)
1384 struct reg_entry *reg = arm_reg_parse_multi (&str);
1385 struct neon_typed_alias atype;
1386 struct neon_type_el parsetype;
1390 atype.eltype.type = NT_invtype;
1391 atype.eltype.size = -1;
1393 /* Try alternate syntax for some types of register. Note these are mutually
1394 exclusive with the Neon syntax extensions. */
1397 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1405 /* Undo polymorphism when a set of register types may be accepted. */
1406 if ((type == REG_TYPE_NDQ
1407 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1408 || (type == REG_TYPE_VFSD
1409 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1410 || (type == REG_TYPE_NSDQ
1411 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1412 || reg->type == REG_TYPE_NQ))
1413 || (type == REG_TYPE_MMXWC
1414 && (reg->type == REG_TYPE_MMXWCG)))
1415 type = (enum arm_reg_type) reg->type;
1417 if (type != reg->type)
1423 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1425 if ((atype.defined & NTA_HASTYPE) != 0)
1427 first_error (_("can't redefine type for operand"));
1430 atype.defined |= NTA_HASTYPE;
1431 atype.eltype = parsetype;
1434 if (skip_past_char (&str, '[') == SUCCESS)
1436 if (type != REG_TYPE_VFD)
1438 first_error (_("only D registers may be indexed"));
1442 if ((atype.defined & NTA_HASINDEX) != 0)
1444 first_error (_("can't change index for operand"));
1448 atype.defined |= NTA_HASINDEX;
1450 if (skip_past_char (&str, ']') == SUCCESS)
1451 atype.index = NEON_ALL_LANES;
1456 my_get_expression (&exp, &str, GE_NO_PREFIX);
1458 if (exp.X_op != O_constant)
1460 first_error (_("constant expression required"));
1464 if (skip_past_char (&str, ']') == FAIL)
1467 atype.index = exp.X_add_number;
1482 /* Like arm_reg_parse, but allow allow the following extra features:
1483 - If RTYPE is non-zero, return the (possibly restricted) type of the
1484 register (e.g. Neon double or quad reg when either has been requested).
1485 - If this is a Neon vector type with additional type information, fill
1486 in the struct pointed to by VECTYPE (if non-NULL).
1487 This function will fault on encountering a scalar. */
1490 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1491 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1493 struct neon_typed_alias atype;
1495 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1500 /* Do not allow regname(... to parse as a register. */
1504 /* Do not allow a scalar (reg+index) to parse as a register. */
1505 if ((atype.defined & NTA_HASINDEX) != 0)
1507 first_error (_("register operand expected, but got scalar"));
1512 *vectype = atype.eltype;
1519 #define NEON_SCALAR_REG(X) ((X) >> 4)
1520 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1522 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1523 have enough information to be able to do a good job bounds-checking. So, we
1524 just do easy checks here, and do further checks later. */
1527 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1531 struct neon_typed_alias atype;
1533 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1535 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1538 if (atype.index == NEON_ALL_LANES)
1540 first_error (_("scalar must have an index"));
1543 else if (atype.index >= 64 / elsize)
1545 first_error (_("scalar index out of range"));
1550 *type = atype.eltype;
1554 return reg * 16 + atype.index;
1557 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1560 parse_reg_list (char ** strp)
1562 char * str = * strp;
1566 /* We come back here if we get ranges concatenated by '+' or '|'. */
1581 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1583 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1593 first_error (_("bad range in register list"));
1597 for (i = cur_reg + 1; i < reg; i++)
1599 if (range & (1 << i))
1601 (_("Warning: duplicated register (r%d) in register list"),
1609 if (range & (1 << reg))
1610 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1612 else if (reg <= cur_reg)
1613 as_tsktsk (_("Warning: register range not in ascending order"));
1618 while (skip_past_comma (&str) != FAIL
1619 || (in_range = 1, *str++ == '-'));
1624 first_error (_("missing `}'"));
1632 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1635 if (exp.X_op == O_constant)
1637 if (exp.X_add_number
1638 != (exp.X_add_number & 0x0000ffff))
1640 inst.error = _("invalid register mask");
1644 if ((range & exp.X_add_number) != 0)
1646 int regno = range & exp.X_add_number;
1649 regno = (1 << regno) - 1;
1651 (_("Warning: duplicated register (r%d) in register list"),
1655 range |= exp.X_add_number;
1659 if (inst.reloc.type != 0)
1661 inst.error = _("expression too complex");
1665 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1666 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1667 inst.reloc.pc_rel = 0;
1671 if (*str == '|' || *str == '+')
1677 while (another_range);
1683 /* Types of registers in a list. */
1692 /* Parse a VFP register list. If the string is invalid return FAIL.
1693 Otherwise return the number of registers, and set PBASE to the first
1694 register. Parses registers of type ETYPE.
1695 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1696 - Q registers can be used to specify pairs of D registers
1697 - { } can be omitted from around a singleton register list
1698 FIXME: This is not implemented, as it would require backtracking in
1701 This could be done (the meaning isn't really ambiguous), but doesn't
1702 fit in well with the current parsing framework.
1703 - 32 D registers may be used (also true for VFPv3).
1704 FIXME: Types are ignored in these register lists, which is probably a
1708 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1713 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1717 unsigned long mask = 0;
1722 inst.error = _("expecting {");
1731 regtype = REG_TYPE_VFS;
1736 regtype = REG_TYPE_VFD;
1739 case REGLIST_NEON_D:
1740 regtype = REG_TYPE_NDQ;
1744 if (etype != REGLIST_VFP_S)
1746 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1747 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1751 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1754 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1761 base_reg = max_regs;
1765 int setmask = 1, addregs = 1;
1767 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1769 if (new_base == FAIL)
1771 first_error (_(reg_expected_msgs[regtype]));
1775 if (new_base >= max_regs)
1777 first_error (_("register out of range in list"));
1781 /* Note: a value of 2 * n is returned for the register Q<n>. */
1782 if (regtype == REG_TYPE_NQ)
1788 if (new_base < base_reg)
1789 base_reg = new_base;
1791 if (mask & (setmask << new_base))
1793 first_error (_("invalid register list"));
1797 if ((mask >> new_base) != 0 && ! warned)
1799 as_tsktsk (_("register list not in ascending order"));
1803 mask |= setmask << new_base;
1806 if (*str == '-') /* We have the start of a range expression */
1812 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1815 inst.error = gettext (reg_expected_msgs[regtype]);
1819 if (high_range >= max_regs)
1821 first_error (_("register out of range in list"));
1825 if (regtype == REG_TYPE_NQ)
1826 high_range = high_range + 1;
1828 if (high_range <= new_base)
1830 inst.error = _("register range not in ascending order");
1834 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1836 if (mask & (setmask << new_base))
1838 inst.error = _("invalid register list");
1842 mask |= setmask << new_base;
1847 while (skip_past_comma (&str) != FAIL);
1851 /* Sanity check -- should have raised a parse error above. */
1852 if (count == 0 || count > max_regs)
1857 /* Final test -- the registers must be consecutive. */
1859 for (i = 0; i < count; i++)
1861 if ((mask & (1u << i)) == 0)
1863 inst.error = _("non-contiguous register range");
1873 /* True if two alias types are the same. */
1876 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1884 if (a->defined != b->defined)
1887 if ((a->defined & NTA_HASTYPE) != 0
1888 && (a->eltype.type != b->eltype.type
1889 || a->eltype.size != b->eltype.size))
1892 if ((a->defined & NTA_HASINDEX) != 0
1893 && (a->index != b->index))
1899 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1900 The base register is put in *PBASE.
1901 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1903 The register stride (minus one) is put in bit 4 of the return value.
1904 Bits [6:5] encode the list length (minus one).
1905 The type of the list elements is put in *ELTYPE, if non-NULL. */
1907 #define NEON_LANE(X) ((X) & 0xf)
1908 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1909 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1912 parse_neon_el_struct_list (char **str, unsigned *pbase,
1913 struct neon_type_el *eltype)
1920 int leading_brace = 0;
1921 enum arm_reg_type rtype = REG_TYPE_NDQ;
1922 const char *const incr_error = _("register stride must be 1 or 2");
1923 const char *const type_error = _("mismatched element/structure types in list");
1924 struct neon_typed_alias firsttype;
1926 if (skip_past_char (&ptr, '{') == SUCCESS)
1931 struct neon_typed_alias atype;
1932 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1936 first_error (_(reg_expected_msgs[rtype]));
1943 if (rtype == REG_TYPE_NQ)
1949 else if (reg_incr == -1)
1951 reg_incr = getreg - base_reg;
1952 if (reg_incr < 1 || reg_incr > 2)
1954 first_error (_(incr_error));
1958 else if (getreg != base_reg + reg_incr * count)
1960 first_error (_(incr_error));
1964 if (! neon_alias_types_same (&atype, &firsttype))
1966 first_error (_(type_error));
1970 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1974 struct neon_typed_alias htype;
1975 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1977 lane = NEON_INTERLEAVE_LANES;
1978 else if (lane != NEON_INTERLEAVE_LANES)
1980 first_error (_(type_error));
1985 else if (reg_incr != 1)
1987 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1991 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1994 first_error (_(reg_expected_msgs[rtype]));
1997 if (! neon_alias_types_same (&htype, &firsttype))
1999 first_error (_(type_error));
2002 count += hireg + dregs - getreg;
2006 /* If we're using Q registers, we can't use [] or [n] syntax. */
2007 if (rtype == REG_TYPE_NQ)
2013 if ((atype.defined & NTA_HASINDEX) != 0)
2017 else if (lane != atype.index)
2019 first_error (_(type_error));
2023 else if (lane == -1)
2024 lane = NEON_INTERLEAVE_LANES;
2025 else if (lane != NEON_INTERLEAVE_LANES)
2027 first_error (_(type_error));
2032 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2034 /* No lane set by [x]. We must be interleaving structures. */
2036 lane = NEON_INTERLEAVE_LANES;
2039 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2040 || (count > 1 && reg_incr == -1))
2042 first_error (_("error parsing element/structure list"));
2046 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2048 first_error (_("expected }"));
2056 *eltype = firsttype.eltype;
2061 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2064 /* Parse an explicit relocation suffix on an expression. This is
2065 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2066 arm_reloc_hsh contains no entries, so this function can only
2067 succeed if there is no () after the word. Returns -1 on error,
2068 BFD_RELOC_UNUSED if there wasn't any suffix. */
2071 parse_reloc (char **str)
2073 struct reloc_entry *r;
2077 return BFD_RELOC_UNUSED;
2082 while (*q && *q != ')' && *q != ',')
2087 if ((r = (struct reloc_entry *)
2088 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2095 /* Directives: register aliases. */
2097 static struct reg_entry *
2098 insert_reg_alias (char *str, unsigned number, int type)
2100 struct reg_entry *new_reg;
2103 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2105 if (new_reg->builtin)
2106 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2108 /* Only warn about a redefinition if it's not defined as the
2110 else if (new_reg->number != number || new_reg->type != type)
2111 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2116 name = xstrdup (str);
2117 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2119 new_reg->name = name;
2120 new_reg->number = number;
2121 new_reg->type = type;
2122 new_reg->builtin = FALSE;
2123 new_reg->neon = NULL;
2125 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2132 insert_neon_reg_alias (char *str, int number, int type,
2133 struct neon_typed_alias *atype)
2135 struct reg_entry *reg = insert_reg_alias (str, number, type);
2139 first_error (_("attempt to redefine typed alias"));
2145 reg->neon = (struct neon_typed_alias *)
2146 xmalloc (sizeof (struct neon_typed_alias));
2147 *reg->neon = *atype;
2151 /* Look for the .req directive. This is of the form:
2153 new_register_name .req existing_register_name
2155 If we find one, or if it looks sufficiently like one that we want to
2156 handle any error here, return TRUE. Otherwise return FALSE. */
2159 create_register_alias (char * newname, char *p)
2161 struct reg_entry *old;
2162 char *oldname, *nbuf;
2165 /* The input scrubber ensures that whitespace after the mnemonic is
2166 collapsed to single spaces. */
2168 if (strncmp (oldname, " .req ", 6) != 0)
2172 if (*oldname == '\0')
2175 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2178 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2182 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2183 the desired alias name, and p points to its end. If not, then
2184 the desired alias name is in the global original_case_string. */
2185 #ifdef TC_CASE_SENSITIVE
2188 newname = original_case_string;
2189 nlen = strlen (newname);
2192 nbuf = (char *) alloca (nlen + 1);
2193 memcpy (nbuf, newname, nlen);
2196 /* Create aliases under the new name as stated; an all-lowercase
2197 version of the new name; and an all-uppercase version of the new
2199 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2201 for (p = nbuf; *p; p++)
2204 if (strncmp (nbuf, newname, nlen))
2206 /* If this attempt to create an additional alias fails, do not bother
2207 trying to create the all-lower case alias. We will fail and issue
2208 a second, duplicate error message. This situation arises when the
2209 programmer does something like:
2212 The second .req creates the "Foo" alias but then fails to create
2213 the artificial FOO alias because it has already been created by the
2215 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2219 for (p = nbuf; *p; p++)
2222 if (strncmp (nbuf, newname, nlen))
2223 insert_reg_alias (nbuf, old->number, old->type);
2229 /* Create a Neon typed/indexed register alias using directives, e.g.:
2234 These typed registers can be used instead of the types specified after the
2235 Neon mnemonic, so long as all operands given have types. Types can also be
2236 specified directly, e.g.:
2237 vadd d0.s32, d1.s32, d2.s32 */
2240 create_neon_reg_alias (char *newname, char *p)
2242 enum arm_reg_type basetype;
2243 struct reg_entry *basereg;
2244 struct reg_entry mybasereg;
2245 struct neon_type ntype;
2246 struct neon_typed_alias typeinfo;
2247 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2250 typeinfo.defined = 0;
2251 typeinfo.eltype.type = NT_invtype;
2252 typeinfo.eltype.size = -1;
2253 typeinfo.index = -1;
2257 if (strncmp (p, " .dn ", 5) == 0)
2258 basetype = REG_TYPE_VFD;
2259 else if (strncmp (p, " .qn ", 5) == 0)
2260 basetype = REG_TYPE_NQ;
2269 basereg = arm_reg_parse_multi (&p);
2271 if (basereg && basereg->type != basetype)
2273 as_bad (_("bad type for register"));
2277 if (basereg == NULL)
2280 /* Try parsing as an integer. */
2281 my_get_expression (&exp, &p, GE_NO_PREFIX);
2282 if (exp.X_op != O_constant)
2284 as_bad (_("expression must be constant"));
2287 basereg = &mybasereg;
2288 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2294 typeinfo = *basereg->neon;
2296 if (parse_neon_type (&ntype, &p) == SUCCESS)
2298 /* We got a type. */
2299 if (typeinfo.defined & NTA_HASTYPE)
2301 as_bad (_("can't redefine the type of a register alias"));
2305 typeinfo.defined |= NTA_HASTYPE;
2306 if (ntype.elems != 1)
2308 as_bad (_("you must specify a single type only"));
2311 typeinfo.eltype = ntype.el[0];
2314 if (skip_past_char (&p, '[') == SUCCESS)
2317 /* We got a scalar index. */
2319 if (typeinfo.defined & NTA_HASINDEX)
2321 as_bad (_("can't redefine the index of a scalar alias"));
2325 my_get_expression (&exp, &p, GE_NO_PREFIX);
2327 if (exp.X_op != O_constant)
2329 as_bad (_("scalar index must be constant"));
2333 typeinfo.defined |= NTA_HASINDEX;
2334 typeinfo.index = exp.X_add_number;
2336 if (skip_past_char (&p, ']') == FAIL)
2338 as_bad (_("expecting ]"));
2343 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2344 the desired alias name, and p points to its end. If not, then
2345 the desired alias name is in the global original_case_string. */
2346 #ifdef TC_CASE_SENSITIVE
2347 namelen = nameend - newname;
2349 newname = original_case_string;
2350 namelen = strlen (newname);
2353 namebuf = (char *) alloca (namelen + 1);
2354 strncpy (namebuf, newname, namelen);
2355 namebuf[namelen] = '\0';
2357 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2358 typeinfo.defined != 0 ? &typeinfo : NULL);
2360 /* Insert name in all uppercase. */
2361 for (p = namebuf; *p; p++)
2364 if (strncmp (namebuf, newname, namelen))
2365 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2366 typeinfo.defined != 0 ? &typeinfo : NULL);
2368 /* Insert name in all lowercase. */
2369 for (p = namebuf; *p; p++)
2372 if (strncmp (namebuf, newname, namelen))
2373 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2374 typeinfo.defined != 0 ? &typeinfo : NULL);
2379 /* Should never be called, as .req goes between the alias and the
2380 register name, not at the beginning of the line. */
2383 s_req (int a ATTRIBUTE_UNUSED)
2385 as_bad (_("invalid syntax for .req directive"));
2389 s_dn (int a ATTRIBUTE_UNUSED)
2391 as_bad (_("invalid syntax for .dn directive"));
2395 s_qn (int a ATTRIBUTE_UNUSED)
2397 as_bad (_("invalid syntax for .qn directive"));
2400 /* The .unreq directive deletes an alias which was previously defined
2401 by .req. For example:
2407 s_unreq (int a ATTRIBUTE_UNUSED)
2412 name = input_line_pointer;
2414 while (*input_line_pointer != 0
2415 && *input_line_pointer != ' '
2416 && *input_line_pointer != '\n')
2417 ++input_line_pointer;
2419 saved_char = *input_line_pointer;
2420 *input_line_pointer = 0;
2423 as_bad (_("invalid syntax for .unreq directive"));
2426 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2430 as_bad (_("unknown register alias '%s'"), name);
2431 else if (reg->builtin)
2432 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2439 hash_delete (arm_reg_hsh, name, FALSE);
2440 free ((char *) reg->name);
2445 /* Also locate the all upper case and all lower case versions.
2446 Do not complain if we cannot find one or the other as it
2447 was probably deleted above. */
2449 nbuf = strdup (name);
2450 for (p = nbuf; *p; p++)
2452 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2455 hash_delete (arm_reg_hsh, nbuf, FALSE);
2456 free ((char *) reg->name);
2462 for (p = nbuf; *p; p++)
2464 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2467 hash_delete (arm_reg_hsh, nbuf, FALSE);
2468 free ((char *) reg->name);
2478 *input_line_pointer = saved_char;
2479 demand_empty_rest_of_line ();
2482 /* Directives: Instruction set selection. */
2485 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2486 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2487 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2488 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2490 /* Create a new mapping symbol for the transition to STATE. */
2493 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2496 const char * symname;
2503 type = BSF_NO_FLAGS;
2507 type = BSF_NO_FLAGS;
2511 type = BSF_NO_FLAGS;
2517 symbolP = symbol_new (symname, now_seg, value, frag);
2518 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2523 THUMB_SET_FUNC (symbolP, 0);
2524 ARM_SET_THUMB (symbolP, 0);
2525 ARM_SET_INTERWORK (symbolP, support_interwork);
2529 THUMB_SET_FUNC (symbolP, 1);
2530 ARM_SET_THUMB (symbolP, 1);
2531 ARM_SET_INTERWORK (symbolP, support_interwork);
2539 /* Save the mapping symbols for future reference. Also check that
2540 we do not place two mapping symbols at the same offset within a
2541 frag. We'll handle overlap between frags in
2542 check_mapping_symbols.
2544 If .fill or other data filling directive generates zero sized data,
2545 the mapping symbol for the following code will have the same value
2546 as the one generated for the data filling directive. In this case,
2547 we replace the old symbol with the new one at the same address. */
2550 if (frag->tc_frag_data.first_map != NULL)
2552 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2553 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2555 frag->tc_frag_data.first_map = symbolP;
2557 if (frag->tc_frag_data.last_map != NULL)
2559 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2560 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2561 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2563 frag->tc_frag_data.last_map = symbolP;
2566 /* We must sometimes convert a region marked as code to data during
2567 code alignment, if an odd number of bytes have to be padded. The
2568 code mapping symbol is pushed to an aligned address. */
2571 insert_data_mapping_symbol (enum mstate state,
2572 valueT value, fragS *frag, offsetT bytes)
2574 /* If there was already a mapping symbol, remove it. */
2575 if (frag->tc_frag_data.last_map != NULL
2576 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2578 symbolS *symp = frag->tc_frag_data.last_map;
2582 know (frag->tc_frag_data.first_map == symp);
2583 frag->tc_frag_data.first_map = NULL;
2585 frag->tc_frag_data.last_map = NULL;
2586 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2589 make_mapping_symbol (MAP_DATA, value, frag);
2590 make_mapping_symbol (state, value + bytes, frag);
2593 static void mapping_state_2 (enum mstate state, int max_chars);
2595 /* Set the mapping state to STATE. Only call this when about to
2596 emit some STATE bytes to the file. */
2599 mapping_state (enum mstate state)
2601 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2603 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2605 if (mapstate == state)
2606 /* The mapping symbol has already been emitted.
2607 There is nothing else to do. */
2610 if (state == MAP_ARM || state == MAP_THUMB)
2612 All ARM instructions require 4-byte alignment.
2613 (Almost) all Thumb instructions require 2-byte alignment.
2615 When emitting instructions into any section, mark the section
2618 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2619 but themselves require 2-byte alignment; this applies to some
2620 PC- relative forms. However, these cases will invovle implicit
2621 literal pool generation or an explicit .align >=2, both of
2622 which will cause the section to me marked with sufficient
2623 alignment. Thus, we don't handle those cases here. */
2624 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2626 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2627 /* This case will be evaluated later in the next else. */
2629 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2630 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2632 /* Only add the symbol if the offset is > 0:
2633 if we're at the first frag, check it's size > 0;
2634 if we're not at the first frag, then for sure
2635 the offset is > 0. */
2636 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2637 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2640 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2643 mapping_state_2 (state, 0);
2647 /* Same as mapping_state, but MAX_CHARS bytes have already been
2648 allocated. Put the mapping symbol that far back. */
2651 mapping_state_2 (enum mstate state, int max_chars)
2653 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2655 if (!SEG_NORMAL (now_seg))
2658 if (mapstate == state)
2659 /* The mapping symbol has already been emitted.
2660 There is nothing else to do. */
2663 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2664 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2667 #define mapping_state(x) ((void)0)
2668 #define mapping_state_2(x, y) ((void)0)
2671 /* Find the real, Thumb encoded start of a Thumb function. */
2675 find_real_start (symbolS * symbolP)
2678 const char * name = S_GET_NAME (symbolP);
2679 symbolS * new_target;
2681 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2682 #define STUB_NAME ".real_start_of"
2687 /* The compiler may generate BL instructions to local labels because
2688 it needs to perform a branch to a far away location. These labels
2689 do not have a corresponding ".real_start_of" label. We check
2690 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2691 the ".real_start_of" convention for nonlocal branches. */
2692 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2695 real_start = ACONCAT ((STUB_NAME, name, NULL));
2696 new_target = symbol_find (real_start);
2698 if (new_target == NULL)
2700 as_warn (_("Failed to find real start of function: %s\n"), name);
2701 new_target = symbolP;
2709 opcode_select (int width)
2716 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2717 as_bad (_("selected processor does not support THUMB opcodes"));
2720 /* No need to force the alignment, since we will have been
2721 coming from ARM mode, which is word-aligned. */
2722 record_alignment (now_seg, 1);
2729 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2730 as_bad (_("selected processor does not support ARM opcodes"));
2735 frag_align (2, 0, 0);
2737 record_alignment (now_seg, 1);
2742 as_bad (_("invalid instruction size selected (%d)"), width);
2747 s_arm (int ignore ATTRIBUTE_UNUSED)
2750 demand_empty_rest_of_line ();
2754 s_thumb (int ignore ATTRIBUTE_UNUSED)
2757 demand_empty_rest_of_line ();
2761 s_code (int unused ATTRIBUTE_UNUSED)
2765 temp = get_absolute_expression ();
2770 opcode_select (temp);
2774 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2779 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2781 /* If we are not already in thumb mode go into it, EVEN if
2782 the target processor does not support thumb instructions.
2783 This is used by gcc/config/arm/lib1funcs.asm for example
2784 to compile interworking support functions even if the
2785 target processor should not support interworking. */
2789 record_alignment (now_seg, 1);
2792 demand_empty_rest_of_line ();
2796 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2800 /* The following label is the name/address of the start of a Thumb function.
2801 We need to know this for the interworking support. */
2802 label_is_thumb_function_name = TRUE;
2805 /* Perform a .set directive, but also mark the alias as
2806 being a thumb function. */
2809 s_thumb_set (int equiv)
2811 /* XXX the following is a duplicate of the code for s_set() in read.c
2812 We cannot just call that code as we need to get at the symbol that
2819 /* Especial apologies for the random logic:
2820 This just grew, and could be parsed much more simply!
2822 name = input_line_pointer;
2823 delim = get_symbol_end ();
2824 end_name = input_line_pointer;
2827 if (*input_line_pointer != ',')
2830 as_bad (_("expected comma after name \"%s\""), name);
2832 ignore_rest_of_line ();
2836 input_line_pointer++;
2839 if (name[0] == '.' && name[1] == '\0')
2841 /* XXX - this should not happen to .thumb_set. */
2845 if ((symbolP = symbol_find (name)) == NULL
2846 && (symbolP = md_undefined_symbol (name)) == NULL)
2849 /* When doing symbol listings, play games with dummy fragments living
2850 outside the normal fragment chain to record the file and line info
2852 if (listing & LISTING_SYMBOLS)
2854 extern struct list_info_struct * listing_tail;
2855 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2857 memset (dummy_frag, 0, sizeof (fragS));
2858 dummy_frag->fr_type = rs_fill;
2859 dummy_frag->line = listing_tail;
2860 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2861 dummy_frag->fr_symbol = symbolP;
2865 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2868 /* "set" symbols are local unless otherwise specified. */
2869 SF_SET_LOCAL (symbolP);
2870 #endif /* OBJ_COFF */
2871 } /* Make a new symbol. */
2873 symbol_table_insert (symbolP);
2878 && S_IS_DEFINED (symbolP)
2879 && S_GET_SEGMENT (symbolP) != reg_section)
2880 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2882 pseudo_set (symbolP);
2884 demand_empty_rest_of_line ();
2886 /* XXX Now we come to the Thumb specific bit of code. */
2888 THUMB_SET_FUNC (symbolP, 1);
2889 ARM_SET_THUMB (symbolP, 1);
2890 #if defined OBJ_ELF || defined OBJ_COFF
2891 ARM_SET_INTERWORK (symbolP, support_interwork);
2895 /* Directives: Mode selection. */
2897 /* .syntax [unified|divided] - choose the new unified syntax
2898 (same for Arm and Thumb encoding, modulo slight differences in what
2899 can be represented) or the old divergent syntax for each mode. */
2901 s_syntax (int unused ATTRIBUTE_UNUSED)
2905 name = input_line_pointer;
2906 delim = get_symbol_end ();
2908 if (!strcasecmp (name, "unified"))
2909 unified_syntax = TRUE;
2910 else if (!strcasecmp (name, "divided"))
2911 unified_syntax = FALSE;
2914 as_bad (_("unrecognized syntax mode \"%s\""), name);
2917 *input_line_pointer = delim;
2918 demand_empty_rest_of_line ();
2921 /* Directives: sectioning and alignment. */
2923 /* Same as s_align_ptwo but align 0 => align 2. */
2926 s_align (int unused ATTRIBUTE_UNUSED)
2931 long max_alignment = 15;
2933 temp = get_absolute_expression ();
2934 if (temp > max_alignment)
2935 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2938 as_bad (_("alignment negative. 0 assumed."));
2942 if (*input_line_pointer == ',')
2944 input_line_pointer++;
2945 temp_fill = get_absolute_expression ();
2957 /* Only make a frag if we HAVE to. */
2958 if (temp && !need_pass_2)
2960 if (!fill_p && subseg_text_p (now_seg))
2961 frag_align_code (temp, 0);
2963 frag_align (temp, (int) temp_fill, 0);
2965 demand_empty_rest_of_line ();
2967 record_alignment (now_seg, temp);
2971 s_bss (int ignore ATTRIBUTE_UNUSED)
2973 /* We don't support putting frags in the BSS segment, we fake it by
2974 marking in_bss, then looking at s_skip for clues. */
2975 subseg_set (bss_section, 0);
2976 demand_empty_rest_of_line ();
2978 #ifdef md_elf_section_change_hook
2979 md_elf_section_change_hook ();
2984 s_even (int ignore ATTRIBUTE_UNUSED)
2986 /* Never make frag if expect extra pass. */
2988 frag_align (1, 0, 0);
2990 record_alignment (now_seg, 1);
2992 demand_empty_rest_of_line ();
2995 /* Directives: Literal pools. */
2997 static literal_pool *
2998 find_literal_pool (void)
3000 literal_pool * pool;
3002 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3004 if (pool->section == now_seg
3005 && pool->sub_section == now_subseg)
3012 static literal_pool *
3013 find_or_make_literal_pool (void)
3015 /* Next literal pool ID number. */
3016 static unsigned int latest_pool_num = 1;
3017 literal_pool * pool;
3019 pool = find_literal_pool ();
3023 /* Create a new pool. */
3024 pool = (literal_pool *) xmalloc (sizeof (* pool));
3028 pool->next_free_entry = 0;
3029 pool->section = now_seg;
3030 pool->sub_section = now_subseg;
3031 pool->next = list_of_pools;
3032 pool->symbol = NULL;
3034 /* Add it to the list. */
3035 list_of_pools = pool;
3038 /* New pools, and emptied pools, will have a NULL symbol. */
3039 if (pool->symbol == NULL)
3041 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3042 (valueT) 0, &zero_address_frag);
3043 pool->id = latest_pool_num ++;
3050 /* Add the literal in the global 'inst'
3051 structure to the relevant literal pool. */
3054 add_to_lit_pool (void)
3056 literal_pool * pool;
3059 pool = find_or_make_literal_pool ();
3061 /* Check if this literal value is already in the pool. */
3062 for (entry = 0; entry < pool->next_free_entry; entry ++)
3064 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3065 && (inst.reloc.exp.X_op == O_constant)
3066 && (pool->literals[entry].X_add_number
3067 == inst.reloc.exp.X_add_number)
3068 && (pool->literals[entry].X_unsigned
3069 == inst.reloc.exp.X_unsigned))
3072 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3073 && (inst.reloc.exp.X_op == O_symbol)
3074 && (pool->literals[entry].X_add_number
3075 == inst.reloc.exp.X_add_number)
3076 && (pool->literals[entry].X_add_symbol
3077 == inst.reloc.exp.X_add_symbol)
3078 && (pool->literals[entry].X_op_symbol
3079 == inst.reloc.exp.X_op_symbol))
3083 /* Do we need to create a new entry? */
3084 if (entry == pool->next_free_entry)
3086 if (entry >= MAX_LITERAL_POOL_SIZE)
3088 inst.error = _("literal pool overflow");
3092 pool->literals[entry] = inst.reloc.exp;
3094 /* PR ld/12974: Record the location of the first source line to reference
3095 this entry in the literal pool. If it turns out during linking that the
3096 symbol does not exist we will be able to give an accurate line number for
3097 the (first use of the) missing reference. */
3098 if (debug_type == DEBUG_DWARF2)
3099 dwarf2_where (pool->locs + entry);
3101 pool->next_free_entry += 1;
3104 inst.reloc.exp.X_op = O_symbol;
3105 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3106 inst.reloc.exp.X_add_symbol = pool->symbol;
3111 /* Can't use symbol_new here, so have to create a symbol and then at
3112 a later date assign it a value. Thats what these functions do. */
3115 symbol_locate (symbolS * symbolP,
3116 const char * name, /* It is copied, the caller can modify. */
3117 segT segment, /* Segment identifier (SEG_<something>). */
3118 valueT valu, /* Symbol value. */
3119 fragS * frag) /* Associated fragment. */
3121 unsigned int name_length;
3122 char * preserved_copy_of_name;
3124 name_length = strlen (name) + 1; /* +1 for \0. */
3125 obstack_grow (¬es, name, name_length);
3126 preserved_copy_of_name = (char *) obstack_finish (¬es);
3128 #ifdef tc_canonicalize_symbol_name
3129 preserved_copy_of_name =
3130 tc_canonicalize_symbol_name (preserved_copy_of_name);
3133 S_SET_NAME (symbolP, preserved_copy_of_name);
3135 S_SET_SEGMENT (symbolP, segment);
3136 S_SET_VALUE (symbolP, valu);
3137 symbol_clear_list_pointers (symbolP);
3139 symbol_set_frag (symbolP, frag);
3141 /* Link to end of symbol chain. */
3143 extern int symbol_table_frozen;
3145 if (symbol_table_frozen)
3149 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3151 obj_symbol_new_hook (symbolP);
3153 #ifdef tc_symbol_new_hook
3154 tc_symbol_new_hook (symbolP);
3158 verify_symbol_chain (symbol_rootP, symbol_lastP);
3159 #endif /* DEBUG_SYMS */
3164 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3167 literal_pool * pool;
3170 pool = find_literal_pool ();
3172 || pool->symbol == NULL
3173 || pool->next_free_entry == 0)
3176 mapping_state (MAP_DATA);
3178 /* Align pool as you have word accesses.
3179 Only make a frag if we have to. */
3181 frag_align (2, 0, 0);
3183 record_alignment (now_seg, 2);
3185 sprintf (sym_name, "$$lit_\002%x", pool->id);
3187 symbol_locate (pool->symbol, sym_name, now_seg,
3188 (valueT) frag_now_fix (), frag_now);
3189 symbol_table_insert (pool->symbol);
3191 ARM_SET_THUMB (pool->symbol, thumb_mode);
3193 #if defined OBJ_COFF || defined OBJ_ELF
3194 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3197 for (entry = 0; entry < pool->next_free_entry; entry ++)
3200 if (debug_type == DEBUG_DWARF2)
3201 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3203 /* First output the expression in the instruction to the pool. */
3204 emit_expr (&(pool->literals[entry]), 4); /* .word */
3207 /* Mark the pool as empty. */
3208 pool->next_free_entry = 0;
3209 pool->symbol = NULL;
3213 /* Forward declarations for functions below, in the MD interface
3215 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3216 static valueT create_unwind_entry (int);
3217 static void start_unwind_section (const segT, int);
3218 static void add_unwind_opcode (valueT, int);
3219 static void flush_pending_unwind (void);
3221 /* Directives: Data. */
3224 s_arm_elf_cons (int nbytes)
3228 #ifdef md_flush_pending_output
3229 md_flush_pending_output ();
3232 if (is_it_end_of_statement ())
3234 demand_empty_rest_of_line ();
3238 #ifdef md_cons_align
3239 md_cons_align (nbytes);
3242 mapping_state (MAP_DATA);
3246 char *base = input_line_pointer;
3250 if (exp.X_op != O_symbol)
3251 emit_expr (&exp, (unsigned int) nbytes);
3254 char *before_reloc = input_line_pointer;
3255 reloc = parse_reloc (&input_line_pointer);
3258 as_bad (_("unrecognized relocation suffix"));
3259 ignore_rest_of_line ();
3262 else if (reloc == BFD_RELOC_UNUSED)
3263 emit_expr (&exp, (unsigned int) nbytes);
3266 reloc_howto_type *howto = (reloc_howto_type *)
3267 bfd_reloc_type_lookup (stdoutput,
3268 (bfd_reloc_code_real_type) reloc);
3269 int size = bfd_get_reloc_size (howto);
3271 if (reloc == BFD_RELOC_ARM_PLT32)
3273 as_bad (_("(plt) is only valid on branch targets"));
3274 reloc = BFD_RELOC_UNUSED;
3279 as_bad (_("%s relocations do not fit in %d bytes"),
3280 howto->name, nbytes);
3283 /* We've parsed an expression stopping at O_symbol.
3284 But there may be more expression left now that we
3285 have parsed the relocation marker. Parse it again.
3286 XXX Surely there is a cleaner way to do this. */
3287 char *p = input_line_pointer;
3289 char *save_buf = (char *) alloca (input_line_pointer - base);
3290 memcpy (save_buf, base, input_line_pointer - base);
3291 memmove (base + (input_line_pointer - before_reloc),
3292 base, before_reloc - base);
3294 input_line_pointer = base + (input_line_pointer-before_reloc);
3296 memcpy (base, save_buf, p - base);
3298 offset = nbytes - size;
3299 p = frag_more ((int) nbytes);
3300 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3301 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3306 while (*input_line_pointer++ == ',');
3308 /* Put terminator back into stream. */
3309 input_line_pointer --;
3310 demand_empty_rest_of_line ();
3313 /* Emit an expression containing a 32-bit thumb instruction.
3314 Implementation based on put_thumb32_insn. */
3317 emit_thumb32_expr (expressionS * exp)
3319 expressionS exp_high = *exp;
3321 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3322 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3323 exp->X_add_number &= 0xffff;
3324 emit_expr (exp, (unsigned int) THUMB_SIZE);
3327 /* Guess the instruction size based on the opcode. */
3330 thumb_insn_size (int opcode)
3332 if ((unsigned int) opcode < 0xe800u)
3334 else if ((unsigned int) opcode >= 0xe8000000u)
3341 emit_insn (expressionS *exp, int nbytes)
3345 if (exp->X_op == O_constant)
3350 size = thumb_insn_size (exp->X_add_number);
3354 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3356 as_bad (_(".inst.n operand too big. "\
3357 "Use .inst.w instead"));
3362 if (now_it.state == AUTOMATIC_IT_BLOCK)
3363 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3365 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3367 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3368 emit_thumb32_expr (exp);
3370 emit_expr (exp, (unsigned int) size);
3372 it_fsm_post_encode ();
3376 as_bad (_("cannot determine Thumb instruction size. " \
3377 "Use .inst.n/.inst.w instead"));
3380 as_bad (_("constant expression required"));
3385 /* Like s_arm_elf_cons but do not use md_cons_align and
3386 set the mapping state to MAP_ARM/MAP_THUMB. */
3389 s_arm_elf_inst (int nbytes)
3391 if (is_it_end_of_statement ())
3393 demand_empty_rest_of_line ();
3397 /* Calling mapping_state () here will not change ARM/THUMB,
3398 but will ensure not to be in DATA state. */
3401 mapping_state (MAP_THUMB);
3406 as_bad (_("width suffixes are invalid in ARM mode"));
3407 ignore_rest_of_line ();
3413 mapping_state (MAP_ARM);
3422 if (! emit_insn (& exp, nbytes))
3424 ignore_rest_of_line ();
3428 while (*input_line_pointer++ == ',');
3430 /* Put terminator back into stream. */
3431 input_line_pointer --;
3432 demand_empty_rest_of_line ();
3435 /* Parse a .rel31 directive. */
3438 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3445 if (*input_line_pointer == '1')
3446 highbit = 0x80000000;
3447 else if (*input_line_pointer != '0')
3448 as_bad (_("expected 0 or 1"));
3450 input_line_pointer++;
3451 if (*input_line_pointer != ',')
3452 as_bad (_("missing comma"));
3453 input_line_pointer++;
3455 #ifdef md_flush_pending_output
3456 md_flush_pending_output ();
3459 #ifdef md_cons_align
3463 mapping_state (MAP_DATA);
3468 md_number_to_chars (p, highbit, 4);
3469 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3470 BFD_RELOC_ARM_PREL31);
3472 demand_empty_rest_of_line ();
3475 /* Directives: AEABI stack-unwind tables. */
3477 /* Parse an unwind_fnstart directive. Simply records the current location. */
3480 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3482 demand_empty_rest_of_line ();
3483 if (unwind.proc_start)
3485 as_bad (_("duplicate .fnstart directive"));
3489 /* Mark the start of the function. */
3490 unwind.proc_start = expr_build_dot ();
3492 /* Reset the rest of the unwind info. */
3493 unwind.opcode_count = 0;
3494 unwind.table_entry = NULL;
3495 unwind.personality_routine = NULL;
3496 unwind.personality_index = -1;
3497 unwind.frame_size = 0;
3498 unwind.fp_offset = 0;
3499 unwind.fp_reg = REG_SP;
3501 unwind.sp_restored = 0;
3505 /* Parse a handlerdata directive. Creates the exception handling table entry
3506 for the function. */
3509 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3511 demand_empty_rest_of_line ();
3512 if (!unwind.proc_start)
3513 as_bad (MISSING_FNSTART);
3515 if (unwind.table_entry)
3516 as_bad (_("duplicate .handlerdata directive"));
3518 create_unwind_entry (1);
3521 /* Parse an unwind_fnend directive. Generates the index table entry. */
3524 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3529 unsigned int marked_pr_dependency;
3531 demand_empty_rest_of_line ();
3533 if (!unwind.proc_start)
3535 as_bad (_(".fnend directive without .fnstart"));
3539 /* Add eh table entry. */
3540 if (unwind.table_entry == NULL)
3541 val = create_unwind_entry (0);
3545 /* Add index table entry. This is two words. */
3546 start_unwind_section (unwind.saved_seg, 1);
3547 frag_align (2, 0, 0);
3548 record_alignment (now_seg, 2);
3550 ptr = frag_more (8);
3552 where = frag_now_fix () - 8;
3554 /* Self relative offset of the function start. */
3555 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3556 BFD_RELOC_ARM_PREL31);
3558 /* Indicate dependency on EHABI-defined personality routines to the
3559 linker, if it hasn't been done already. */
3560 marked_pr_dependency
3561 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3562 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3563 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3565 static const char *const name[] =
3567 "__aeabi_unwind_cpp_pr0",
3568 "__aeabi_unwind_cpp_pr1",
3569 "__aeabi_unwind_cpp_pr2"
3571 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3572 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3573 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3574 |= 1 << unwind.personality_index;
3578 /* Inline exception table entry. */
3579 md_number_to_chars (ptr + 4, val, 4);
3581 /* Self relative offset of the table entry. */
3582 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3583 BFD_RELOC_ARM_PREL31);
3585 /* Restore the original section. */
3586 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3588 unwind.proc_start = NULL;
3592 /* Parse an unwind_cantunwind directive. */
3595 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3597 demand_empty_rest_of_line ();
3598 if (!unwind.proc_start)
3599 as_bad (MISSING_FNSTART);
3601 if (unwind.personality_routine || unwind.personality_index != -1)
3602 as_bad (_("personality routine specified for cantunwind frame"));
3604 unwind.personality_index = -2;
3608 /* Parse a personalityindex directive. */
3611 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3615 if (!unwind.proc_start)
3616 as_bad (MISSING_FNSTART);
3618 if (unwind.personality_routine || unwind.personality_index != -1)
3619 as_bad (_("duplicate .personalityindex directive"));
3623 if (exp.X_op != O_constant
3624 || exp.X_add_number < 0 || exp.X_add_number > 15)
3626 as_bad (_("bad personality routine number"));
3627 ignore_rest_of_line ();
3631 unwind.personality_index = exp.X_add_number;
3633 demand_empty_rest_of_line ();
3637 /* Parse a personality directive. */
3640 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3644 if (!unwind.proc_start)
3645 as_bad (MISSING_FNSTART);
3647 if (unwind.personality_routine || unwind.personality_index != -1)
3648 as_bad (_("duplicate .personality directive"));
3650 name = input_line_pointer;
3651 c = get_symbol_end ();
3652 p = input_line_pointer;
3653 unwind.personality_routine = symbol_find_or_make (name);
3655 demand_empty_rest_of_line ();
3659 /* Parse a directive saving core registers. */
3662 s_arm_unwind_save_core (void)
3668 range = parse_reg_list (&input_line_pointer);
3671 as_bad (_("expected register list"));
3672 ignore_rest_of_line ();
3676 demand_empty_rest_of_line ();
3678 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3679 into .unwind_save {..., sp...}. We aren't bothered about the value of
3680 ip because it is clobbered by calls. */
3681 if (unwind.sp_restored && unwind.fp_reg == 12
3682 && (range & 0x3000) == 0x1000)
3684 unwind.opcode_count--;
3685 unwind.sp_restored = 0;
3686 range = (range | 0x2000) & ~0x1000;
3687 unwind.pending_offset = 0;
3693 /* See if we can use the short opcodes. These pop a block of up to 8
3694 registers starting with r4, plus maybe r14. */
3695 for (n = 0; n < 8; n++)
3697 /* Break at the first non-saved register. */
3698 if ((range & (1 << (n + 4))) == 0)
3701 /* See if there are any other bits set. */
3702 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3704 /* Use the long form. */
3705 op = 0x8000 | ((range >> 4) & 0xfff);
3706 add_unwind_opcode (op, 2);
3710 /* Use the short form. */
3712 op = 0xa8; /* Pop r14. */
3714 op = 0xa0; /* Do not pop r14. */
3716 add_unwind_opcode (op, 1);
3723 op = 0xb100 | (range & 0xf);
3724 add_unwind_opcode (op, 2);
3727 /* Record the number of bytes pushed. */
3728 for (n = 0; n < 16; n++)
3730 if (range & (1 << n))
3731 unwind.frame_size += 4;
3736 /* Parse a directive saving FPA registers. */
3739 s_arm_unwind_save_fpa (int reg)
3745 /* Get Number of registers to transfer. */
3746 if (skip_past_comma (&input_line_pointer) != FAIL)
3749 exp.X_op = O_illegal;
3751 if (exp.X_op != O_constant)
3753 as_bad (_("expected , <constant>"));
3754 ignore_rest_of_line ();
3758 num_regs = exp.X_add_number;
3760 if (num_regs < 1 || num_regs > 4)
3762 as_bad (_("number of registers must be in the range [1:4]"));
3763 ignore_rest_of_line ();
3767 demand_empty_rest_of_line ();
3772 op = 0xb4 | (num_regs - 1);
3773 add_unwind_opcode (op, 1);
3778 op = 0xc800 | (reg << 4) | (num_regs - 1);
3779 add_unwind_opcode (op, 2);
3781 unwind.frame_size += num_regs * 12;
3785 /* Parse a directive saving VFP registers for ARMv6 and above. */
3788 s_arm_unwind_save_vfp_armv6 (void)
3793 int num_vfpv3_regs = 0;
3794 int num_regs_below_16;
3796 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3799 as_bad (_("expected register list"));
3800 ignore_rest_of_line ();
3804 demand_empty_rest_of_line ();
3806 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3807 than FSTMX/FLDMX-style ones). */
3809 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3811 num_vfpv3_regs = count;
3812 else if (start + count > 16)
3813 num_vfpv3_regs = start + count - 16;
3815 if (num_vfpv3_regs > 0)
3817 int start_offset = start > 16 ? start - 16 : 0;
3818 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3819 add_unwind_opcode (op, 2);
3822 /* Generate opcode for registers numbered in the range 0 .. 15. */
3823 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3824 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3825 if (num_regs_below_16 > 0)
3827 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3828 add_unwind_opcode (op, 2);
3831 unwind.frame_size += count * 8;
3835 /* Parse a directive saving VFP registers for pre-ARMv6. */
3838 s_arm_unwind_save_vfp (void)
3844 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3847 as_bad (_("expected register list"));
3848 ignore_rest_of_line ();
3852 demand_empty_rest_of_line ();
3857 op = 0xb8 | (count - 1);
3858 add_unwind_opcode (op, 1);
3863 op = 0xb300 | (reg << 4) | (count - 1);
3864 add_unwind_opcode (op, 2);
3866 unwind.frame_size += count * 8 + 4;
3870 /* Parse a directive saving iWMMXt data registers. */
3873 s_arm_unwind_save_mmxwr (void)
3881 if (*input_line_pointer == '{')
3882 input_line_pointer++;
3886 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3890 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3895 as_tsktsk (_("register list not in ascending order"));
3898 if (*input_line_pointer == '-')
3900 input_line_pointer++;
3901 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3904 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3907 else if (reg >= hi_reg)
3909 as_bad (_("bad register range"));
3912 for (; reg < hi_reg; reg++)
3916 while (skip_past_comma (&input_line_pointer) != FAIL);
3918 if (*input_line_pointer == '}')
3919 input_line_pointer++;
3921 demand_empty_rest_of_line ();
3923 /* Generate any deferred opcodes because we're going to be looking at
3925 flush_pending_unwind ();
3927 for (i = 0; i < 16; i++)
3929 if (mask & (1 << i))
3930 unwind.frame_size += 8;
3933 /* Attempt to combine with a previous opcode. We do this because gcc
3934 likes to output separate unwind directives for a single block of
3936 if (unwind.opcode_count > 0)
3938 i = unwind.opcodes[unwind.opcode_count - 1];
3939 if ((i & 0xf8) == 0xc0)
3942 /* Only merge if the blocks are contiguous. */
3945 if ((mask & 0xfe00) == (1 << 9))
3947 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3948 unwind.opcode_count--;
3951 else if (i == 6 && unwind.opcode_count >= 2)
3953 i = unwind.opcodes[unwind.opcode_count - 2];
3957 op = 0xffff << (reg - 1);
3959 && ((mask & op) == (1u << (reg - 1))))
3961 op = (1 << (reg + i + 1)) - 1;
3962 op &= ~((1 << reg) - 1);
3964 unwind.opcode_count -= 2;
3971 /* We want to generate opcodes in the order the registers have been
3972 saved, ie. descending order. */
3973 for (reg = 15; reg >= -1; reg--)
3975 /* Save registers in blocks. */
3977 || !(mask & (1 << reg)))
3979 /* We found an unsaved reg. Generate opcodes to save the
3986 op = 0xc0 | (hi_reg - 10);
3987 add_unwind_opcode (op, 1);
3992 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3993 add_unwind_opcode (op, 2);
4002 ignore_rest_of_line ();
4006 s_arm_unwind_save_mmxwcg (void)
4013 if (*input_line_pointer == '{')
4014 input_line_pointer++;
4018 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4022 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4028 as_tsktsk (_("register list not in ascending order"));
4031 if (*input_line_pointer == '-')
4033 input_line_pointer++;
4034 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4037 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4040 else if (reg >= hi_reg)
4042 as_bad (_("bad register range"));
4045 for (; reg < hi_reg; reg++)
4049 while (skip_past_comma (&input_line_pointer) != FAIL);
4051 if (*input_line_pointer == '}')
4052 input_line_pointer++;
4054 demand_empty_rest_of_line ();
4056 /* Generate any deferred opcodes because we're going to be looking at
4058 flush_pending_unwind ();
4060 for (reg = 0; reg < 16; reg++)
4062 if (mask & (1 << reg))
4063 unwind.frame_size += 4;
4066 add_unwind_opcode (op, 2);
4069 ignore_rest_of_line ();
4073 /* Parse an unwind_save directive.
4074 If the argument is non-zero, this is a .vsave directive. */
4077 s_arm_unwind_save (int arch_v6)
4080 struct reg_entry *reg;
4081 bfd_boolean had_brace = FALSE;
4083 if (!unwind.proc_start)
4084 as_bad (MISSING_FNSTART);
4086 /* Figure out what sort of save we have. */
4087 peek = input_line_pointer;
4095 reg = arm_reg_parse_multi (&peek);
4099 as_bad (_("register expected"));
4100 ignore_rest_of_line ();
4109 as_bad (_("FPA .unwind_save does not take a register list"));
4110 ignore_rest_of_line ();
4113 input_line_pointer = peek;
4114 s_arm_unwind_save_fpa (reg->number);
4117 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4120 s_arm_unwind_save_vfp_armv6 ();
4122 s_arm_unwind_save_vfp ();
4124 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4125 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4128 as_bad (_(".unwind_save does not support this kind of register"));
4129 ignore_rest_of_line ();
4134 /* Parse an unwind_movsp directive. */
4137 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4143 if (!unwind.proc_start)
4144 as_bad (MISSING_FNSTART);
4146 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4149 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4150 ignore_rest_of_line ();
4154 /* Optional constant. */
4155 if (skip_past_comma (&input_line_pointer) != FAIL)
4157 if (immediate_for_directive (&offset) == FAIL)
4163 demand_empty_rest_of_line ();
4165 if (reg == REG_SP || reg == REG_PC)
4167 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4171 if (unwind.fp_reg != REG_SP)
4172 as_bad (_("unexpected .unwind_movsp directive"));
4174 /* Generate opcode to restore the value. */
4176 add_unwind_opcode (op, 1);
4178 /* Record the information for later. */
4179 unwind.fp_reg = reg;
4180 unwind.fp_offset = unwind.frame_size - offset;
4181 unwind.sp_restored = 1;
4184 /* Parse an unwind_pad directive. */
4187 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4191 if (!unwind.proc_start)
4192 as_bad (MISSING_FNSTART);
4194 if (immediate_for_directive (&offset) == FAIL)
4199 as_bad (_("stack increment must be multiple of 4"));
4200 ignore_rest_of_line ();
4204 /* Don't generate any opcodes, just record the details for later. */
4205 unwind.frame_size += offset;
4206 unwind.pending_offset += offset;
4208 demand_empty_rest_of_line ();
4211 /* Parse an unwind_setfp directive. */
4214 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4220 if (!unwind.proc_start)
4221 as_bad (MISSING_FNSTART);
4223 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4224 if (skip_past_comma (&input_line_pointer) == FAIL)
4227 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4229 if (fp_reg == FAIL || sp_reg == FAIL)
4231 as_bad (_("expected <reg>, <reg>"));
4232 ignore_rest_of_line ();
4236 /* Optional constant. */
4237 if (skip_past_comma (&input_line_pointer) != FAIL)
4239 if (immediate_for_directive (&offset) == FAIL)
4245 demand_empty_rest_of_line ();
4247 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4249 as_bad (_("register must be either sp or set by a previous"
4250 "unwind_movsp directive"));
4254 /* Don't generate any opcodes, just record the information for later. */
4255 unwind.fp_reg = fp_reg;
4257 if (sp_reg == REG_SP)
4258 unwind.fp_offset = unwind.frame_size - offset;
4260 unwind.fp_offset -= offset;
4263 /* Parse an unwind_raw directive. */
4266 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4269 /* This is an arbitrary limit. */
4270 unsigned char op[16];
4273 if (!unwind.proc_start)
4274 as_bad (MISSING_FNSTART);
4277 if (exp.X_op == O_constant
4278 && skip_past_comma (&input_line_pointer) != FAIL)
4280 unwind.frame_size += exp.X_add_number;
4284 exp.X_op = O_illegal;
4286 if (exp.X_op != O_constant)
4288 as_bad (_("expected <offset>, <opcode>"));
4289 ignore_rest_of_line ();
4295 /* Parse the opcode. */
4300 as_bad (_("unwind opcode too long"));
4301 ignore_rest_of_line ();
4303 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4305 as_bad (_("invalid unwind opcode"));
4306 ignore_rest_of_line ();
4309 op[count++] = exp.X_add_number;
4311 /* Parse the next byte. */
4312 if (skip_past_comma (&input_line_pointer) == FAIL)
4318 /* Add the opcode bytes in reverse order. */
4320 add_unwind_opcode (op[count], 1);
4322 demand_empty_rest_of_line ();
4326 /* Parse a .eabi_attribute directive. */
4329 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4331 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4333 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4334 attributes_set_explicitly[tag] = 1;
4337 /* Emit a tls fix for the symbol. */
4340 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4344 #ifdef md_flush_pending_output
4345 md_flush_pending_output ();
4348 #ifdef md_cons_align
4352 /* Since we're just labelling the code, there's no need to define a
4355 p = obstack_next_free (&frchain_now->frch_obstack);
4356 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4357 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4358 : BFD_RELOC_ARM_TLS_DESCSEQ);
4360 #endif /* OBJ_ELF */
4362 static void s_arm_arch (int);
4363 static void s_arm_object_arch (int);
4364 static void s_arm_cpu (int);
4365 static void s_arm_fpu (int);
4366 static void s_arm_arch_extension (int);
4371 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4378 if (exp.X_op == O_symbol)
4379 exp.X_op = O_secrel;
4381 emit_expr (&exp, 4);
4383 while (*input_line_pointer++ == ',');
4385 input_line_pointer--;
4386 demand_empty_rest_of_line ();
4390 /* This table describes all the machine specific pseudo-ops the assembler
4391 has to support. The fields are:
4392 pseudo-op name without dot
4393 function to call to execute this pseudo-op
4394 Integer arg to pass to the function. */
4396 const pseudo_typeS md_pseudo_table[] =
4398 /* Never called because '.req' does not start a line. */
4399 { "req", s_req, 0 },
4400 /* Following two are likewise never called. */
4403 { "unreq", s_unreq, 0 },
4404 { "bss", s_bss, 0 },
4405 { "align", s_align, 0 },
4406 { "arm", s_arm, 0 },
4407 { "thumb", s_thumb, 0 },
4408 { "code", s_code, 0 },
4409 { "force_thumb", s_force_thumb, 0 },
4410 { "thumb_func", s_thumb_func, 0 },
4411 { "thumb_set", s_thumb_set, 0 },
4412 { "even", s_even, 0 },
4413 { "ltorg", s_ltorg, 0 },
4414 { "pool", s_ltorg, 0 },
4415 { "syntax", s_syntax, 0 },
4416 { "cpu", s_arm_cpu, 0 },
4417 { "arch", s_arm_arch, 0 },
4418 { "object_arch", s_arm_object_arch, 0 },
4419 { "fpu", s_arm_fpu, 0 },
4420 { "arch_extension", s_arm_arch_extension, 0 },
4422 { "word", s_arm_elf_cons, 4 },
4423 { "long", s_arm_elf_cons, 4 },
4424 { "inst.n", s_arm_elf_inst, 2 },
4425 { "inst.w", s_arm_elf_inst, 4 },
4426 { "inst", s_arm_elf_inst, 0 },
4427 { "rel31", s_arm_rel31, 0 },
4428 { "fnstart", s_arm_unwind_fnstart, 0 },
4429 { "fnend", s_arm_unwind_fnend, 0 },
4430 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4431 { "personality", s_arm_unwind_personality, 0 },
4432 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4433 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4434 { "save", s_arm_unwind_save, 0 },
4435 { "vsave", s_arm_unwind_save, 1 },
4436 { "movsp", s_arm_unwind_movsp, 0 },
4437 { "pad", s_arm_unwind_pad, 0 },
4438 { "setfp", s_arm_unwind_setfp, 0 },
4439 { "unwind_raw", s_arm_unwind_raw, 0 },
4440 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4441 { "tlsdescseq", s_arm_tls_descseq, 0 },
4445 /* These are used for dwarf. */
4449 /* These are used for dwarf2. */
4450 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4451 { "loc", dwarf2_directive_loc, 0 },
4452 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4454 { "extend", float_cons, 'x' },
4455 { "ldouble", float_cons, 'x' },
4456 { "packed", float_cons, 'p' },
4458 {"secrel32", pe_directive_secrel, 0},
4463 /* Parser functions used exclusively in instruction operands. */
4465 /* Generic immediate-value read function for use in insn parsing.
4466 STR points to the beginning of the immediate (the leading #);
4467 VAL receives the value; if the value is outside [MIN, MAX]
4468 issue an error. PREFIX_OPT is true if the immediate prefix is
4472 parse_immediate (char **str, int *val, int min, int max,
4473 bfd_boolean prefix_opt)
4476 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4477 if (exp.X_op != O_constant)
4479 inst.error = _("constant expression required");
4483 if (exp.X_add_number < min || exp.X_add_number > max)
4485 inst.error = _("immediate value out of range");
4489 *val = exp.X_add_number;
4493 /* Less-generic immediate-value read function with the possibility of loading a
4494 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4495 instructions. Puts the result directly in inst.operands[i]. */
4498 parse_big_immediate (char **str, int i)
4503 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4505 if (exp.X_op == O_constant)
4507 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4508 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4509 O_constant. We have to be careful not to break compilation for
4510 32-bit X_add_number, though. */
4511 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4513 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4514 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4515 inst.operands[i].regisimm = 1;
4518 else if (exp.X_op == O_big
4519 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4521 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4523 /* Bignums have their least significant bits in
4524 generic_bignum[0]. Make sure we put 32 bits in imm and
4525 32 bits in reg, in a (hopefully) portable way. */
4526 gas_assert (parts != 0);
4528 /* Make sure that the number is not too big.
4529 PR 11972: Bignums can now be sign-extended to the
4530 size of a .octa so check that the out of range bits
4531 are all zero or all one. */
4532 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4534 LITTLENUM_TYPE m = -1;
4536 if (generic_bignum[parts * 2] != 0
4537 && generic_bignum[parts * 2] != m)
4540 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4541 if (generic_bignum[j] != generic_bignum[j-1])
4545 inst.operands[i].imm = 0;
4546 for (j = 0; j < parts; j++, idx++)
4547 inst.operands[i].imm |= generic_bignum[idx]
4548 << (LITTLENUM_NUMBER_OF_BITS * j);
4549 inst.operands[i].reg = 0;
4550 for (j = 0; j < parts; j++, idx++)
4551 inst.operands[i].reg |= generic_bignum[idx]
4552 << (LITTLENUM_NUMBER_OF_BITS * j);
4553 inst.operands[i].regisimm = 1;
4563 /* Returns the pseudo-register number of an FPA immediate constant,
4564 or FAIL if there isn't a valid constant here. */
4567 parse_fpa_immediate (char ** str)
4569 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4575 /* First try and match exact strings, this is to guarantee
4576 that some formats will work even for cross assembly. */
4578 for (i = 0; fp_const[i]; i++)
4580 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4584 *str += strlen (fp_const[i]);
4585 if (is_end_of_line[(unsigned char) **str])
4591 /* Just because we didn't get a match doesn't mean that the constant
4592 isn't valid, just that it is in a format that we don't
4593 automatically recognize. Try parsing it with the standard
4594 expression routines. */
4596 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4598 /* Look for a raw floating point number. */
4599 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4600 && is_end_of_line[(unsigned char) *save_in])
4602 for (i = 0; i < NUM_FLOAT_VALS; i++)
4604 for (j = 0; j < MAX_LITTLENUMS; j++)
4606 if (words[j] != fp_values[i][j])
4610 if (j == MAX_LITTLENUMS)
4618 /* Try and parse a more complex expression, this will probably fail
4619 unless the code uses a floating point prefix (eg "0f"). */
4620 save_in = input_line_pointer;
4621 input_line_pointer = *str;
4622 if (expression (&exp) == absolute_section
4623 && exp.X_op == O_big
4624 && exp.X_add_number < 0)
4626 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4628 if (gen_to_words (words, 5, (long) 15) == 0)
4630 for (i = 0; i < NUM_FLOAT_VALS; i++)
4632 for (j = 0; j < MAX_LITTLENUMS; j++)
4634 if (words[j] != fp_values[i][j])
4638 if (j == MAX_LITTLENUMS)
4640 *str = input_line_pointer;
4641 input_line_pointer = save_in;
4648 *str = input_line_pointer;
4649 input_line_pointer = save_in;
4650 inst.error = _("invalid FPA immediate expression");
4654 /* Returns 1 if a number has "quarter-precision" float format
4655 0baBbbbbbc defgh000 00000000 00000000. */
4658 is_quarter_float (unsigned imm)
4660 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4661 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4664 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4665 0baBbbbbbc defgh000 00000000 00000000.
4666 The zero and minus-zero cases need special handling, since they can't be
4667 encoded in the "quarter-precision" float format, but can nonetheless be
4668 loaded as integer constants. */
4671 parse_qfloat_immediate (char **ccp, int *immed)
4675 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4676 int found_fpchar = 0;
4678 skip_past_char (&str, '#');
4680 /* We must not accidentally parse an integer as a floating-point number. Make
4681 sure that the value we parse is not an integer by checking for special
4682 characters '.' or 'e'.
4683 FIXME: This is a horrible hack, but doing better is tricky because type
4684 information isn't in a very usable state at parse time. */
4686 skip_whitespace (fpnum);
4688 if (strncmp (fpnum, "0x", 2) == 0)
4692 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4693 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4703 if ((str = atof_ieee (str, 's', words)) != NULL)
4705 unsigned fpword = 0;
4708 /* Our FP word must be 32 bits (single-precision FP). */
4709 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4711 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4715 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4728 /* Shift operands. */
4731 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4734 struct asm_shift_name
4737 enum shift_kind kind;
4740 /* Third argument to parse_shift. */
4741 enum parse_shift_mode
4743 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4744 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4745 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4746 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4747 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4750 /* Parse a <shift> specifier on an ARM data processing instruction.
4751 This has three forms:
4753 (LSL|LSR|ASL|ASR|ROR) Rs
4754 (LSL|LSR|ASL|ASR|ROR) #imm
4757 Note that ASL is assimilated to LSL in the instruction encoding, and
4758 RRX to ROR #0 (which cannot be written as such). */
4761 parse_shift (char **str, int i, enum parse_shift_mode mode)
4763 const struct asm_shift_name *shift_name;
4764 enum shift_kind shift;
4769 for (p = *str; ISALPHA (*p); p++)
4774 inst.error = _("shift expression expected");
4778 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4781 if (shift_name == NULL)
4783 inst.error = _("shift expression expected");
4787 shift = shift_name->kind;
4791 case NO_SHIFT_RESTRICT:
4792 case SHIFT_IMMEDIATE: break;
4794 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4795 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4797 inst.error = _("'LSL' or 'ASR' required");
4802 case SHIFT_LSL_IMMEDIATE:
4803 if (shift != SHIFT_LSL)
4805 inst.error = _("'LSL' required");
4810 case SHIFT_ASR_IMMEDIATE:
4811 if (shift != SHIFT_ASR)
4813 inst.error = _("'ASR' required");
4821 if (shift != SHIFT_RRX)
4823 /* Whitespace can appear here if the next thing is a bare digit. */
4824 skip_whitespace (p);
4826 if (mode == NO_SHIFT_RESTRICT
4827 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4829 inst.operands[i].imm = reg;
4830 inst.operands[i].immisreg = 1;
4832 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4835 inst.operands[i].shift_kind = shift;
4836 inst.operands[i].shifted = 1;
4841 /* Parse a <shifter_operand> for an ARM data processing instruction:
4844 #<immediate>, <rotate>
4848 where <shift> is defined by parse_shift above, and <rotate> is a
4849 multiple of 2 between 0 and 30. Validation of immediate operands
4850 is deferred to md_apply_fix. */
4853 parse_shifter_operand (char **str, int i)
4858 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4860 inst.operands[i].reg = value;
4861 inst.operands[i].isreg = 1;
4863 /* parse_shift will override this if appropriate */
4864 inst.reloc.exp.X_op = O_constant;
4865 inst.reloc.exp.X_add_number = 0;
4867 if (skip_past_comma (str) == FAIL)
4870 /* Shift operation on register. */
4871 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4874 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4877 if (skip_past_comma (str) == SUCCESS)
4879 /* #x, y -- ie explicit rotation by Y. */
4880 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4883 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4885 inst.error = _("constant expression expected");
4889 value = exp.X_add_number;
4890 if (value < 0 || value > 30 || value % 2 != 0)
4892 inst.error = _("invalid rotation");
4895 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4897 inst.error = _("invalid constant");
4901 /* Encode as specified. */
4902 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4906 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4907 inst.reloc.pc_rel = 0;
4911 /* Group relocation information. Each entry in the table contains the
4912 textual name of the relocation as may appear in assembler source
4913 and must end with a colon.
4914 Along with this textual name are the relocation codes to be used if
4915 the corresponding instruction is an ALU instruction (ADD or SUB only),
4916 an LDR, an LDRS, or an LDC. */
4918 struct group_reloc_table_entry
4929 /* Varieties of non-ALU group relocation. */
4936 static struct group_reloc_table_entry group_reloc_table[] =
4937 { /* Program counter relative: */
4939 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4944 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4945 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4946 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4947 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4949 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4954 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4955 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4956 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4957 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4959 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4960 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4961 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4962 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4963 /* Section base relative */
4965 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4970 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4971 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4972 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4973 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4975 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4980 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4981 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4982 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4983 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4985 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4986 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4987 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4988 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4990 /* Given the address of a pointer pointing to the textual name of a group
4991 relocation as may appear in assembler source, attempt to find its details
4992 in group_reloc_table. The pointer will be updated to the character after
4993 the trailing colon. On failure, FAIL will be returned; SUCCESS
4994 otherwise. On success, *entry will be updated to point at the relevant
4995 group_reloc_table entry. */
4998 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5001 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5003 int length = strlen (group_reloc_table[i].name);
5005 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5006 && (*str)[length] == ':')
5008 *out = &group_reloc_table[i];
5009 *str += (length + 1);
5017 /* Parse a <shifter_operand> for an ARM data processing instruction
5018 (as for parse_shifter_operand) where group relocations are allowed:
5021 #<immediate>, <rotate>
5022 #:<group_reloc>:<expression>
5026 where <group_reloc> is one of the strings defined in group_reloc_table.
5027 The hashes are optional.
5029 Everything else is as for parse_shifter_operand. */
5031 static parse_operand_result
5032 parse_shifter_operand_group_reloc (char **str, int i)
5034 /* Determine if we have the sequence of characters #: or just :
5035 coming next. If we do, then we check for a group relocation.
5036 If we don't, punt the whole lot to parse_shifter_operand. */
5038 if (((*str)[0] == '#' && (*str)[1] == ':')
5039 || (*str)[0] == ':')
5041 struct group_reloc_table_entry *entry;
5043 if ((*str)[0] == '#')
5048 /* Try to parse a group relocation. Anything else is an error. */
5049 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5051 inst.error = _("unknown group relocation");
5052 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5055 /* We now have the group relocation table entry corresponding to
5056 the name in the assembler source. Next, we parse the expression. */
5057 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5058 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5060 /* Record the relocation type (always the ALU variant here). */
5061 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5062 gas_assert (inst.reloc.type != 0);
5064 return PARSE_OPERAND_SUCCESS;
5067 return parse_shifter_operand (str, i) == SUCCESS
5068 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5070 /* Never reached. */
5073 /* Parse a Neon alignment expression. Information is written to
5074 inst.operands[i]. We assume the initial ':' has been skipped.
5076 align .imm = align << 8, .immisalign=1, .preind=0 */
5077 static parse_operand_result
5078 parse_neon_alignment (char **str, int i)
5083 my_get_expression (&exp, &p, GE_NO_PREFIX);
5085 if (exp.X_op != O_constant)
5087 inst.error = _("alignment must be constant");
5088 return PARSE_OPERAND_FAIL;
5091 inst.operands[i].imm = exp.X_add_number << 8;
5092 inst.operands[i].immisalign = 1;
5093 /* Alignments are not pre-indexes. */
5094 inst.operands[i].preind = 0;
5097 return PARSE_OPERAND_SUCCESS;
5100 /* Parse all forms of an ARM address expression. Information is written
5101 to inst.operands[i] and/or inst.reloc.
5103 Preindexed addressing (.preind=1):
5105 [Rn, #offset] .reg=Rn .reloc.exp=offset
5106 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5107 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5108 .shift_kind=shift .reloc.exp=shift_imm
5110 These three may have a trailing ! which causes .writeback to be set also.
5112 Postindexed addressing (.postind=1, .writeback=1):
5114 [Rn], #offset .reg=Rn .reloc.exp=offset
5115 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5116 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5117 .shift_kind=shift .reloc.exp=shift_imm
5119 Unindexed addressing (.preind=0, .postind=0):
5121 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5125 [Rn]{!} shorthand for [Rn,#0]{!}
5126 =immediate .isreg=0 .reloc.exp=immediate
5127 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5129 It is the caller's responsibility to check for addressing modes not
5130 supported by the instruction, and to set inst.reloc.type. */
5132 static parse_operand_result
5133 parse_address_main (char **str, int i, int group_relocations,
5134 group_reloc_type group_type)
5139 if (skip_past_char (&p, '[') == FAIL)
5141 if (skip_past_char (&p, '=') == FAIL)
5143 /* Bare address - translate to PC-relative offset. */
5144 inst.reloc.pc_rel = 1;
5145 inst.operands[i].reg = REG_PC;
5146 inst.operands[i].isreg = 1;
5147 inst.operands[i].preind = 1;
5149 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5151 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5152 return PARSE_OPERAND_FAIL;
5155 return PARSE_OPERAND_SUCCESS;
5158 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5160 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5161 return PARSE_OPERAND_FAIL;
5163 inst.operands[i].reg = reg;
5164 inst.operands[i].isreg = 1;
5166 if (skip_past_comma (&p) == SUCCESS)
5168 inst.operands[i].preind = 1;
5171 else if (*p == '-') p++, inst.operands[i].negative = 1;
5173 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5175 inst.operands[i].imm = reg;
5176 inst.operands[i].immisreg = 1;
5178 if (skip_past_comma (&p) == SUCCESS)
5179 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5180 return PARSE_OPERAND_FAIL;
5182 else if (skip_past_char (&p, ':') == SUCCESS)
5184 /* FIXME: '@' should be used here, but it's filtered out by generic
5185 code before we get to see it here. This may be subject to
5187 parse_operand_result result = parse_neon_alignment (&p, i);
5189 if (result != PARSE_OPERAND_SUCCESS)
5194 if (inst.operands[i].negative)
5196 inst.operands[i].negative = 0;
5200 if (group_relocations
5201 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5203 struct group_reloc_table_entry *entry;
5205 /* Skip over the #: or : sequence. */
5211 /* Try to parse a group relocation. Anything else is an
5213 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5215 inst.error = _("unknown group relocation");
5216 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5219 /* We now have the group relocation table entry corresponding to
5220 the name in the assembler source. Next, we parse the
5222 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5223 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5225 /* Record the relocation type. */
5229 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5233 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5237 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5244 if (inst.reloc.type == 0)
5246 inst.error = _("this group relocation is not allowed on this instruction");
5247 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5253 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5254 return PARSE_OPERAND_FAIL;
5255 /* If the offset is 0, find out if it's a +0 or -0. */
5256 if (inst.reloc.exp.X_op == O_constant
5257 && inst.reloc.exp.X_add_number == 0)
5259 skip_whitespace (q);
5263 skip_whitespace (q);
5266 inst.operands[i].negative = 1;
5271 else if (skip_past_char (&p, ':') == SUCCESS)
5273 /* FIXME: '@' should be used here, but it's filtered out by generic code
5274 before we get to see it here. This may be subject to change. */
5275 parse_operand_result result = parse_neon_alignment (&p, i);
5277 if (result != PARSE_OPERAND_SUCCESS)
5281 if (skip_past_char (&p, ']') == FAIL)
5283 inst.error = _("']' expected");
5284 return PARSE_OPERAND_FAIL;
5287 if (skip_past_char (&p, '!') == SUCCESS)
5288 inst.operands[i].writeback = 1;
5290 else if (skip_past_comma (&p) == SUCCESS)
5292 if (skip_past_char (&p, '{') == SUCCESS)
5294 /* [Rn], {expr} - unindexed, with option */
5295 if (parse_immediate (&p, &inst.operands[i].imm,
5296 0, 255, TRUE) == FAIL)
5297 return PARSE_OPERAND_FAIL;
5299 if (skip_past_char (&p, '}') == FAIL)
5301 inst.error = _("'}' expected at end of 'option' field");
5302 return PARSE_OPERAND_FAIL;
5304 if (inst.operands[i].preind)
5306 inst.error = _("cannot combine index with option");
5307 return PARSE_OPERAND_FAIL;
5310 return PARSE_OPERAND_SUCCESS;
5314 inst.operands[i].postind = 1;
5315 inst.operands[i].writeback = 1;
5317 if (inst.operands[i].preind)
5319 inst.error = _("cannot combine pre- and post-indexing");
5320 return PARSE_OPERAND_FAIL;
5324 else if (*p == '-') p++, inst.operands[i].negative = 1;
5326 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5328 /* We might be using the immediate for alignment already. If we
5329 are, OR the register number into the low-order bits. */
5330 if (inst.operands[i].immisalign)
5331 inst.operands[i].imm |= reg;
5333 inst.operands[i].imm = reg;
5334 inst.operands[i].immisreg = 1;
5336 if (skip_past_comma (&p) == SUCCESS)
5337 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5338 return PARSE_OPERAND_FAIL;
5343 if (inst.operands[i].negative)
5345 inst.operands[i].negative = 0;
5348 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5349 return PARSE_OPERAND_FAIL;
5350 /* If the offset is 0, find out if it's a +0 or -0. */
5351 if (inst.reloc.exp.X_op == O_constant
5352 && inst.reloc.exp.X_add_number == 0)
5354 skip_whitespace (q);
5358 skip_whitespace (q);
5361 inst.operands[i].negative = 1;
5367 /* If at this point neither .preind nor .postind is set, we have a
5368 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5369 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5371 inst.operands[i].preind = 1;
5372 inst.reloc.exp.X_op = O_constant;
5373 inst.reloc.exp.X_add_number = 0;
5376 return PARSE_OPERAND_SUCCESS;
5380 parse_address (char **str, int i)
5382 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5386 static parse_operand_result
5387 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5389 return parse_address_main (str, i, 1, type);
5392 /* Parse an operand for a MOVW or MOVT instruction. */
5394 parse_half (char **str)
5399 skip_past_char (&p, '#');
5400 if (strncasecmp (p, ":lower16:", 9) == 0)
5401 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5402 else if (strncasecmp (p, ":upper16:", 9) == 0)
5403 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5405 if (inst.reloc.type != BFD_RELOC_UNUSED)
5408 skip_whitespace (p);
5411 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5414 if (inst.reloc.type == BFD_RELOC_UNUSED)
5416 if (inst.reloc.exp.X_op != O_constant)
5418 inst.error = _("constant expression expected");
5421 if (inst.reloc.exp.X_add_number < 0
5422 || inst.reloc.exp.X_add_number > 0xffff)
5424 inst.error = _("immediate value out of range");
5432 /* Miscellaneous. */
5434 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5435 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5437 parse_psr (char **str, bfd_boolean lhs)
5440 unsigned long psr_field;
5441 const struct asm_psr *psr;
5443 bfd_boolean is_apsr = FALSE;
5444 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5446 /* PR gas/12698: If the user has specified -march=all then m_profile will
5447 be TRUE, but we want to ignore it in this case as we are building for any
5448 CPU type, including non-m variants. */
5449 if (selected_cpu.core == arm_arch_any.core)
5452 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5453 feature for ease of use and backwards compatibility. */
5455 if (strncasecmp (p, "SPSR", 4) == 0)
5458 goto unsupported_psr;
5460 psr_field = SPSR_BIT;
5462 else if (strncasecmp (p, "CPSR", 4) == 0)
5465 goto unsupported_psr;
5469 else if (strncasecmp (p, "APSR", 4) == 0)
5471 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5472 and ARMv7-R architecture CPUs. */
5481 while (ISALNUM (*p) || *p == '_');
5483 if (strncasecmp (start, "iapsr", 5) == 0
5484 || strncasecmp (start, "eapsr", 5) == 0
5485 || strncasecmp (start, "xpsr", 4) == 0
5486 || strncasecmp (start, "psr", 3) == 0)
5487 p = start + strcspn (start, "rR") + 1;
5489 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5495 /* If APSR is being written, a bitfield may be specified. Note that
5496 APSR itself is handled above. */
5497 if (psr->field <= 3)
5499 psr_field = psr->field;
5505 /* M-profile MSR instructions have the mask field set to "10", except
5506 *PSR variants which modify APSR, which may use a different mask (and
5507 have been handled already). Do that by setting the PSR_f field
5509 return psr->field | (lhs ? PSR_f : 0);
5512 goto unsupported_psr;
5518 /* A suffix follows. */
5524 while (ISALNUM (*p) || *p == '_');
5528 /* APSR uses a notation for bits, rather than fields. */
5529 unsigned int nzcvq_bits = 0;
5530 unsigned int g_bit = 0;
5533 for (bit = start; bit != p; bit++)
5535 switch (TOLOWER (*bit))
5538 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5542 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5546 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5550 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5554 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5558 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5562 inst.error = _("unexpected bit specified after APSR");
5567 if (nzcvq_bits == 0x1f)
5572 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5574 inst.error = _("selected processor does not "
5575 "support DSP extension");
5582 if ((nzcvq_bits & 0x20) != 0
5583 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5584 || (g_bit & 0x2) != 0)
5586 inst.error = _("bad bitmask specified after APSR");
5592 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5597 psr_field |= psr->field;
5603 goto error; /* Garbage after "[CS]PSR". */
5605 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5606 is deprecated, but allow it anyway. */
5610 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5613 else if (!m_profile)
5614 /* These bits are never right for M-profile devices: don't set them
5615 (only code paths which read/write APSR reach here). */
5616 psr_field |= (PSR_c | PSR_f);
5622 inst.error = _("selected processor does not support requested special "
5623 "purpose register");
5627 inst.error = _("flag for {c}psr instruction expected");
5631 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5632 value suitable for splatting into the AIF field of the instruction. */
5635 parse_cps_flags (char **str)
5644 case '\0': case ',':
5647 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5648 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5649 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5652 inst.error = _("unrecognized CPS flag");
5657 if (saw_a_flag == 0)
5659 inst.error = _("missing CPS flags");
5667 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5668 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5671 parse_endian_specifier (char **str)
5676 if (strncasecmp (s, "BE", 2))
5678 else if (strncasecmp (s, "LE", 2))
5682 inst.error = _("valid endian specifiers are be or le");
5686 if (ISALNUM (s[2]) || s[2] == '_')
5688 inst.error = _("valid endian specifiers are be or le");
5693 return little_endian;
5696 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5697 value suitable for poking into the rotate field of an sxt or sxta
5698 instruction, or FAIL on error. */
5701 parse_ror (char **str)
5706 if (strncasecmp (s, "ROR", 3) == 0)
5710 inst.error = _("missing rotation field after comma");
5714 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5719 case 0: *str = s; return 0x0;
5720 case 8: *str = s; return 0x1;
5721 case 16: *str = s; return 0x2;
5722 case 24: *str = s; return 0x3;
5725 inst.error = _("rotation can only be 0, 8, 16, or 24");
5730 /* Parse a conditional code (from conds[] below). The value returned is in the
5731 range 0 .. 14, or FAIL. */
5733 parse_cond (char **str)
5736 const struct asm_cond *c;
5738 /* Condition codes are always 2 characters, so matching up to
5739 3 characters is sufficient. */
5744 while (ISALPHA (*q) && n < 3)
5746 cond[n] = TOLOWER (*q);
5751 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5754 inst.error = _("condition required");
5762 /* Parse an option for a barrier instruction. Returns the encoding for the
5765 parse_barrier (char **str)
5768 const struct asm_barrier_opt *o;
5771 while (ISALPHA (*q))
5774 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5783 /* Parse the operands of a table branch instruction. Similar to a memory
5786 parse_tb (char **str)
5791 if (skip_past_char (&p, '[') == FAIL)
5793 inst.error = _("'[' expected");
5797 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5799 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5802 inst.operands[0].reg = reg;
5804 if (skip_past_comma (&p) == FAIL)
5806 inst.error = _("',' expected");
5810 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5812 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5815 inst.operands[0].imm = reg;
5817 if (skip_past_comma (&p) == SUCCESS)
5819 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5821 if (inst.reloc.exp.X_add_number != 1)
5823 inst.error = _("invalid shift");
5826 inst.operands[0].shifted = 1;
5829 if (skip_past_char (&p, ']') == FAIL)
5831 inst.error = _("']' expected");
5838 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5839 information on the types the operands can take and how they are encoded.
5840 Up to four operands may be read; this function handles setting the
5841 ".present" field for each read operand itself.
5842 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5843 else returns FAIL. */
5846 parse_neon_mov (char **str, int *which_operand)
5848 int i = *which_operand, val;
5849 enum arm_reg_type rtype;
5851 struct neon_type_el optype;
5853 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5855 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5856 inst.operands[i].reg = val;
5857 inst.operands[i].isscalar = 1;
5858 inst.operands[i].vectype = optype;
5859 inst.operands[i++].present = 1;
5861 if (skip_past_comma (&ptr) == FAIL)
5864 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5867 inst.operands[i].reg = val;
5868 inst.operands[i].isreg = 1;
5869 inst.operands[i].present = 1;
5871 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5874 /* Cases 0, 1, 2, 3, 5 (D only). */
5875 if (skip_past_comma (&ptr) == FAIL)
5878 inst.operands[i].reg = val;
5879 inst.operands[i].isreg = 1;
5880 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5881 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5882 inst.operands[i].isvec = 1;
5883 inst.operands[i].vectype = optype;
5884 inst.operands[i++].present = 1;
5886 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5888 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5889 Case 13: VMOV <Sd>, <Rm> */
5890 inst.operands[i].reg = val;
5891 inst.operands[i].isreg = 1;
5892 inst.operands[i].present = 1;
5894 if (rtype == REG_TYPE_NQ)
5896 first_error (_("can't use Neon quad register here"));
5899 else if (rtype != REG_TYPE_VFS)
5902 if (skip_past_comma (&ptr) == FAIL)
5904 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5906 inst.operands[i].reg = val;
5907 inst.operands[i].isreg = 1;
5908 inst.operands[i].present = 1;
5911 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5914 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5915 Case 1: VMOV<c><q> <Dd>, <Dm>
5916 Case 8: VMOV.F32 <Sd>, <Sm>
5917 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5919 inst.operands[i].reg = val;
5920 inst.operands[i].isreg = 1;
5921 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5922 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5923 inst.operands[i].isvec = 1;
5924 inst.operands[i].vectype = optype;
5925 inst.operands[i].present = 1;
5927 if (skip_past_comma (&ptr) == SUCCESS)
5932 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5935 inst.operands[i].reg = val;
5936 inst.operands[i].isreg = 1;
5937 inst.operands[i++].present = 1;
5939 if (skip_past_comma (&ptr) == FAIL)
5942 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5945 inst.operands[i].reg = val;
5946 inst.operands[i].isreg = 1;
5947 inst.operands[i].present = 1;
5950 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5951 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5952 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5953 Case 10: VMOV.F32 <Sd>, #<imm>
5954 Case 11: VMOV.F64 <Dd>, #<imm> */
5955 inst.operands[i].immisfloat = 1;
5956 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5957 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5958 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5962 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5966 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5969 inst.operands[i].reg = val;
5970 inst.operands[i].isreg = 1;
5971 inst.operands[i++].present = 1;
5973 if (skip_past_comma (&ptr) == FAIL)
5976 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5978 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5979 inst.operands[i].reg = val;
5980 inst.operands[i].isscalar = 1;
5981 inst.operands[i].present = 1;
5982 inst.operands[i].vectype = optype;
5984 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5986 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5987 inst.operands[i].reg = val;
5988 inst.operands[i].isreg = 1;
5989 inst.operands[i++].present = 1;
5991 if (skip_past_comma (&ptr) == FAIL)
5994 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5997 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6001 inst.operands[i].reg = val;
6002 inst.operands[i].isreg = 1;
6003 inst.operands[i].isvec = 1;
6004 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6005 inst.operands[i].vectype = optype;
6006 inst.operands[i].present = 1;
6008 if (rtype == REG_TYPE_VFS)
6012 if (skip_past_comma (&ptr) == FAIL)
6014 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6017 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6020 inst.operands[i].reg = val;
6021 inst.operands[i].isreg = 1;
6022 inst.operands[i].isvec = 1;
6023 inst.operands[i].issingle = 1;
6024 inst.operands[i].vectype = optype;
6025 inst.operands[i].present = 1;
6028 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6032 inst.operands[i].reg = val;
6033 inst.operands[i].isreg = 1;
6034 inst.operands[i].isvec = 1;
6035 inst.operands[i].issingle = 1;
6036 inst.operands[i].vectype = optype;
6037 inst.operands[i].present = 1;
6042 first_error (_("parse error"));
6046 /* Successfully parsed the operands. Update args. */
6052 first_error (_("expected comma"));
6056 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6060 /* Use this macro when the operand constraints are different
6061 for ARM and THUMB (e.g. ldrd). */
6062 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6063 ((arm_operand) | ((thumb_operand) << 16))
6065 /* Matcher codes for parse_operands. */
6066 enum operand_parse_code
6068 OP_stop, /* end of line */
6070 OP_RR, /* ARM register */
6071 OP_RRnpc, /* ARM register, not r15 */
6072 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6073 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6074 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6075 optional trailing ! */
6076 OP_RRw, /* ARM register, not r15, optional trailing ! */
6077 OP_RCP, /* Coprocessor number */
6078 OP_RCN, /* Coprocessor register */
6079 OP_RF, /* FPA register */
6080 OP_RVS, /* VFP single precision register */
6081 OP_RVD, /* VFP double precision register (0..15) */
6082 OP_RND, /* Neon double precision register (0..31) */
6083 OP_RNQ, /* Neon quad precision register */
6084 OP_RVSD, /* VFP single or double precision register */
6085 OP_RNDQ, /* Neon double or quad precision register */
6086 OP_RNSDQ, /* Neon single, double or quad precision register */
6087 OP_RNSC, /* Neon scalar D[X] */
6088 OP_RVC, /* VFP control register */
6089 OP_RMF, /* Maverick F register */
6090 OP_RMD, /* Maverick D register */
6091 OP_RMFX, /* Maverick FX register */
6092 OP_RMDX, /* Maverick DX register */
6093 OP_RMAX, /* Maverick AX register */
6094 OP_RMDS, /* Maverick DSPSC register */
6095 OP_RIWR, /* iWMMXt wR register */
6096 OP_RIWC, /* iWMMXt wC register */
6097 OP_RIWG, /* iWMMXt wCG register */
6098 OP_RXA, /* XScale accumulator register */
6100 OP_REGLST, /* ARM register list */
6101 OP_VRSLST, /* VFP single-precision register list */
6102 OP_VRDLST, /* VFP double-precision register list */
6103 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6104 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6105 OP_NSTRLST, /* Neon element/structure list */
6107 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6108 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6109 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6110 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6111 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6112 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6113 OP_VMOV, /* Neon VMOV operands. */
6114 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6115 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6116 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6118 OP_I0, /* immediate zero */
6119 OP_I7, /* immediate value 0 .. 7 */
6120 OP_I15, /* 0 .. 15 */
6121 OP_I16, /* 1 .. 16 */
6122 OP_I16z, /* 0 .. 16 */
6123 OP_I31, /* 0 .. 31 */
6124 OP_I31w, /* 0 .. 31, optional trailing ! */
6125 OP_I32, /* 1 .. 32 */
6126 OP_I32z, /* 0 .. 32 */
6127 OP_I63, /* 0 .. 63 */
6128 OP_I63s, /* -64 .. 63 */
6129 OP_I64, /* 1 .. 64 */
6130 OP_I64z, /* 0 .. 64 */
6131 OP_I255, /* 0 .. 255 */
6133 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6134 OP_I7b, /* 0 .. 7 */
6135 OP_I15b, /* 0 .. 15 */
6136 OP_I31b, /* 0 .. 31 */
6138 OP_SH, /* shifter operand */
6139 OP_SHG, /* shifter operand with possible group relocation */
6140 OP_ADDR, /* Memory address expression (any mode) */
6141 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6142 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6143 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6144 OP_EXP, /* arbitrary expression */
6145 OP_EXPi, /* same, with optional immediate prefix */
6146 OP_EXPr, /* same, with optional relocation suffix */
6147 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6149 OP_CPSF, /* CPS flags */
6150 OP_ENDI, /* Endianness specifier */
6151 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6152 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6153 OP_COND, /* conditional code */
6154 OP_TB, /* Table branch. */
6156 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6158 OP_RRnpc_I0, /* ARM register or literal 0 */
6159 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6160 OP_RR_EXi, /* ARM register or expression with imm prefix */
6161 OP_RF_IF, /* FPA register or immediate */
6162 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6163 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6165 /* Optional operands. */
6166 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6167 OP_oI31b, /* 0 .. 31 */
6168 OP_oI32b, /* 1 .. 32 */
6169 OP_oI32z, /* 0 .. 32 */
6170 OP_oIffffb, /* 0 .. 65535 */
6171 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6173 OP_oRR, /* ARM register */
6174 OP_oRRnpc, /* ARM register, not the PC */
6175 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6176 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6177 OP_oRND, /* Optional Neon double precision register */
6178 OP_oRNQ, /* Optional Neon quad precision register */
6179 OP_oRNDQ, /* Optional Neon double or quad precision register */
6180 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6181 OP_oSHll, /* LSL immediate */
6182 OP_oSHar, /* ASR immediate */
6183 OP_oSHllar, /* LSL or ASR immediate */
6184 OP_oROR, /* ROR 0/8/16/24 */
6185 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6187 /* Some pre-defined mixed (ARM/THUMB) operands. */
6188 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6189 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6190 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6192 OP_FIRST_OPTIONAL = OP_oI7b
6195 /* Generic instruction operand parser. This does no encoding and no
6196 semantic validation; it merely squirrels values away in the inst
6197 structure. Returns SUCCESS or FAIL depending on whether the
6198 specified grammar matched. */
6200 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6202 unsigned const int *upat = pattern;
6203 char *backtrack_pos = 0;
6204 const char *backtrack_error = 0;
6205 int i, val, backtrack_index = 0;
6206 enum arm_reg_type rtype;
6207 parse_operand_result result;
6208 unsigned int op_parse_code;
6210 #define po_char_or_fail(chr) \
6213 if (skip_past_char (&str, chr) == FAIL) \
6218 #define po_reg_or_fail(regtype) \
6221 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6222 & inst.operands[i].vectype); \
6225 first_error (_(reg_expected_msgs[regtype])); \
6228 inst.operands[i].reg = val; \
6229 inst.operands[i].isreg = 1; \
6230 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6231 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6232 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6233 || rtype == REG_TYPE_VFD \
6234 || rtype == REG_TYPE_NQ); \
6238 #define po_reg_or_goto(regtype, label) \
6241 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6242 & inst.operands[i].vectype); \
6246 inst.operands[i].reg = val; \
6247 inst.operands[i].isreg = 1; \
6248 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6249 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6250 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6251 || rtype == REG_TYPE_VFD \
6252 || rtype == REG_TYPE_NQ); \
6256 #define po_imm_or_fail(min, max, popt) \
6259 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6261 inst.operands[i].imm = val; \
6265 #define po_scalar_or_goto(elsz, label) \
6268 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6271 inst.operands[i].reg = val; \
6272 inst.operands[i].isscalar = 1; \
6276 #define po_misc_or_fail(expr) \
6284 #define po_misc_or_fail_no_backtrack(expr) \
6288 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6289 backtrack_pos = 0; \
6290 if (result != PARSE_OPERAND_SUCCESS) \
6295 #define po_barrier_or_imm(str) \
6298 val = parse_barrier (&str); \
6301 if (ISALPHA (*str)) \
6308 if ((inst.instruction & 0xf0) == 0x60 \
6311 /* ISB can only take SY as an option. */ \
6312 inst.error = _("invalid barrier type"); \
6319 skip_whitespace (str);
6321 for (i = 0; upat[i] != OP_stop; i++)
6323 op_parse_code = upat[i];
6324 if (op_parse_code >= 1<<16)
6325 op_parse_code = thumb ? (op_parse_code >> 16)
6326 : (op_parse_code & ((1<<16)-1));
6328 if (op_parse_code >= OP_FIRST_OPTIONAL)
6330 /* Remember where we are in case we need to backtrack. */
6331 gas_assert (!backtrack_pos);
6332 backtrack_pos = str;
6333 backtrack_error = inst.error;
6334 backtrack_index = i;
6337 if (i > 0 && (i > 1 || inst.operands[0].present))
6338 po_char_or_fail (',');
6340 switch (op_parse_code)
6348 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6349 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6350 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6351 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6352 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6353 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6355 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6357 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6359 /* Also accept generic coprocessor regs for unknown registers. */
6361 po_reg_or_fail (REG_TYPE_CN);
6363 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6364 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6365 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6366 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6367 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6368 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6369 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6370 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6371 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6372 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6374 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6376 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6377 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6379 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6381 /* Neon scalar. Using an element size of 8 means that some invalid
6382 scalars are accepted here, so deal with those in later code. */
6383 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6387 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6390 po_imm_or_fail (0, 0, TRUE);
6395 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6400 po_scalar_or_goto (8, try_rr);
6403 po_reg_or_fail (REG_TYPE_RN);
6409 po_scalar_or_goto (8, try_nsdq);
6412 po_reg_or_fail (REG_TYPE_NSDQ);
6418 po_scalar_or_goto (8, try_ndq);
6421 po_reg_or_fail (REG_TYPE_NDQ);
6427 po_scalar_or_goto (8, try_vfd);
6430 po_reg_or_fail (REG_TYPE_VFD);
6435 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6436 not careful then bad things might happen. */
6437 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6442 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6445 /* There's a possibility of getting a 64-bit immediate here, so
6446 we need special handling. */
6447 if (parse_big_immediate (&str, i) == FAIL)
6449 inst.error = _("immediate value is out of range");
6457 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6460 po_imm_or_fail (0, 63, TRUE);
6465 po_char_or_fail ('[');
6466 po_reg_or_fail (REG_TYPE_RN);
6467 po_char_or_fail (']');
6473 po_reg_or_fail (REG_TYPE_RN);
6474 if (skip_past_char (&str, '!') == SUCCESS)
6475 inst.operands[i].writeback = 1;
6479 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6480 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6481 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6482 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6483 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6484 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6485 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6486 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6487 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6488 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6489 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6490 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6492 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6494 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6495 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6497 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6498 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6499 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6500 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6502 /* Immediate variants */
6504 po_char_or_fail ('{');
6505 po_imm_or_fail (0, 255, TRUE);
6506 po_char_or_fail ('}');
6510 /* The expression parser chokes on a trailing !, so we have
6511 to find it first and zap it. */
6514 while (*s && *s != ',')
6519 inst.operands[i].writeback = 1;
6521 po_imm_or_fail (0, 31, TRUE);
6529 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6534 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6539 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6541 if (inst.reloc.exp.X_op == O_symbol)
6543 val = parse_reloc (&str);
6546 inst.error = _("unrecognized relocation suffix");
6549 else if (val != BFD_RELOC_UNUSED)
6551 inst.operands[i].imm = val;
6552 inst.operands[i].hasreloc = 1;
6557 /* Operand for MOVW or MOVT. */
6559 po_misc_or_fail (parse_half (&str));
6562 /* Register or expression. */
6563 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6564 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6566 /* Register or immediate. */
6567 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6568 I0: po_imm_or_fail (0, 0, FALSE); break;
6570 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6572 if (!is_immediate_prefix (*str))
6575 val = parse_fpa_immediate (&str);
6578 /* FPA immediates are encoded as registers 8-15.
6579 parse_fpa_immediate has already applied the offset. */
6580 inst.operands[i].reg = val;
6581 inst.operands[i].isreg = 1;
6584 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6585 I32z: po_imm_or_fail (0, 32, FALSE); break;
6587 /* Two kinds of register. */
6590 struct reg_entry *rege = arm_reg_parse_multi (&str);
6592 || (rege->type != REG_TYPE_MMXWR
6593 && rege->type != REG_TYPE_MMXWC
6594 && rege->type != REG_TYPE_MMXWCG))
6596 inst.error = _("iWMMXt data or control register expected");
6599 inst.operands[i].reg = rege->number;
6600 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6606 struct reg_entry *rege = arm_reg_parse_multi (&str);
6608 || (rege->type != REG_TYPE_MMXWC
6609 && rege->type != REG_TYPE_MMXWCG))
6611 inst.error = _("iWMMXt control register expected");
6614 inst.operands[i].reg = rege->number;
6615 inst.operands[i].isreg = 1;
6620 case OP_CPSF: val = parse_cps_flags (&str); break;
6621 case OP_ENDI: val = parse_endian_specifier (&str); break;
6622 case OP_oROR: val = parse_ror (&str); break;
6623 case OP_COND: val = parse_cond (&str); break;
6624 case OP_oBARRIER_I15:
6625 po_barrier_or_imm (str); break;
6627 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6633 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6634 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6636 inst.error = _("Banked registers are not available with this "
6642 val = parse_psr (&str, op_parse_code == OP_wPSR);
6646 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6649 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6651 if (strncasecmp (str, "APSR_", 5) == 0)
6658 case 'c': found = (found & 1) ? 16 : found | 1; break;
6659 case 'n': found = (found & 2) ? 16 : found | 2; break;
6660 case 'z': found = (found & 4) ? 16 : found | 4; break;
6661 case 'v': found = (found & 8) ? 16 : found | 8; break;
6662 default: found = 16;
6666 inst.operands[i].isvec = 1;
6667 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6668 inst.operands[i].reg = REG_PC;
6675 po_misc_or_fail (parse_tb (&str));
6678 /* Register lists. */
6680 val = parse_reg_list (&str);
6683 inst.operands[1].writeback = 1;
6689 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6693 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6697 /* Allow Q registers too. */
6698 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6703 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6705 inst.operands[i].issingle = 1;
6710 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6715 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6716 &inst.operands[i].vectype);
6719 /* Addressing modes */
6721 po_misc_or_fail (parse_address (&str, i));
6725 po_misc_or_fail_no_backtrack (
6726 parse_address_group_reloc (&str, i, GROUP_LDR));
6730 po_misc_or_fail_no_backtrack (
6731 parse_address_group_reloc (&str, i, GROUP_LDRS));
6735 po_misc_or_fail_no_backtrack (
6736 parse_address_group_reloc (&str, i, GROUP_LDC));
6740 po_misc_or_fail (parse_shifter_operand (&str, i));
6744 po_misc_or_fail_no_backtrack (
6745 parse_shifter_operand_group_reloc (&str, i));
6749 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6753 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6757 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6761 as_fatal (_("unhandled operand code %d"), op_parse_code);
6764 /* Various value-based sanity checks and shared operations. We
6765 do not signal immediate failures for the register constraints;
6766 this allows a syntax error to take precedence. */
6767 switch (op_parse_code)
6775 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6776 inst.error = BAD_PC;
6781 if (inst.operands[i].isreg)
6783 if (inst.operands[i].reg == REG_PC)
6784 inst.error = BAD_PC;
6785 else if (inst.operands[i].reg == REG_SP)
6786 inst.error = BAD_SP;
6791 if (inst.operands[i].isreg
6792 && inst.operands[i].reg == REG_PC
6793 && (inst.operands[i].writeback || thumb))
6794 inst.error = BAD_PC;
6803 case OP_oBARRIER_I15:
6812 inst.operands[i].imm = val;
6819 /* If we get here, this operand was successfully parsed. */
6820 inst.operands[i].present = 1;
6824 inst.error = BAD_ARGS;
6829 /* The parse routine should already have set inst.error, but set a
6830 default here just in case. */
6832 inst.error = _("syntax error");
6836 /* Do not backtrack over a trailing optional argument that
6837 absorbed some text. We will only fail again, with the
6838 'garbage following instruction' error message, which is
6839 probably less helpful than the current one. */
6840 if (backtrack_index == i && backtrack_pos != str
6841 && upat[i+1] == OP_stop)
6844 inst.error = _("syntax error");
6848 /* Try again, skipping the optional argument at backtrack_pos. */
6849 str = backtrack_pos;
6850 inst.error = backtrack_error;
6851 inst.operands[backtrack_index].present = 0;
6852 i = backtrack_index;
6856 /* Check that we have parsed all the arguments. */
6857 if (*str != '\0' && !inst.error)
6858 inst.error = _("garbage following instruction");
6860 return inst.error ? FAIL : SUCCESS;
6863 #undef po_char_or_fail
6864 #undef po_reg_or_fail
6865 #undef po_reg_or_goto
6866 #undef po_imm_or_fail
6867 #undef po_scalar_or_fail
6868 #undef po_barrier_or_imm
6870 /* Shorthand macro for instruction encoding functions issuing errors. */
6871 #define constraint(expr, err) \
6882 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6883 instructions are unpredictable if these registers are used. This
6884 is the BadReg predicate in ARM's Thumb-2 documentation. */
6885 #define reject_bad_reg(reg) \
6887 if (reg == REG_SP || reg == REG_PC) \
6889 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6894 /* If REG is R13 (the stack pointer), warn that its use is
6896 #define warn_deprecated_sp(reg) \
6898 if (warn_on_deprecated && reg == REG_SP) \
6899 as_warn (_("use of r13 is deprecated")); \
6902 /* Functions for operand encoding. ARM, then Thumb. */
6904 #define rotate_left(v, n) (v << n | v >> (32 - n))
6906 /* If VAL can be encoded in the immediate field of an ARM instruction,
6907 return the encoded form. Otherwise, return FAIL. */
6910 encode_arm_immediate (unsigned int val)
6914 for (i = 0; i < 32; i += 2)
6915 if ((a = rotate_left (val, i)) <= 0xff)
6916 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6921 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6922 return the encoded form. Otherwise, return FAIL. */
6924 encode_thumb32_immediate (unsigned int val)
6931 for (i = 1; i <= 24; i++)
6934 if ((val & ~(0xff << i)) == 0)
6935 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6939 if (val == ((a << 16) | a))
6941 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6945 if (val == ((a << 16) | a))
6946 return 0x200 | (a >> 8);
6950 /* Encode a VFP SP or DP register number into inst.instruction. */
6953 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6955 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6958 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6961 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6964 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6969 first_error (_("D register out of range for selected VFP version"));
6977 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6981 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6985 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6989 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6993 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6997 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7005 /* Encode a <shift> in an ARM-format instruction. The immediate,
7006 if any, is handled by md_apply_fix. */
7008 encode_arm_shift (int i)
7010 if (inst.operands[i].shift_kind == SHIFT_RRX)
7011 inst.instruction |= SHIFT_ROR << 5;
7014 inst.instruction |= inst.operands[i].shift_kind << 5;
7015 if (inst.operands[i].immisreg)
7017 inst.instruction |= SHIFT_BY_REG;
7018 inst.instruction |= inst.operands[i].imm << 8;
7021 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7026 encode_arm_shifter_operand (int i)
7028 if (inst.operands[i].isreg)
7030 inst.instruction |= inst.operands[i].reg;
7031 encode_arm_shift (i);
7035 inst.instruction |= INST_IMMEDIATE;
7036 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7037 inst.instruction |= inst.operands[i].imm;
7041 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7043 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7045 gas_assert (inst.operands[i].isreg);
7046 inst.instruction |= inst.operands[i].reg << 16;
7048 if (inst.operands[i].preind)
7052 inst.error = _("instruction does not accept preindexed addressing");
7055 inst.instruction |= PRE_INDEX;
7056 if (inst.operands[i].writeback)
7057 inst.instruction |= WRITE_BACK;
7060 else if (inst.operands[i].postind)
7062 gas_assert (inst.operands[i].writeback);
7064 inst.instruction |= WRITE_BACK;
7066 else /* unindexed - only for coprocessor */
7068 inst.error = _("instruction does not accept unindexed addressing");
7072 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7073 && (((inst.instruction & 0x000f0000) >> 16)
7074 == ((inst.instruction & 0x0000f000) >> 12)))
7075 as_warn ((inst.instruction & LOAD_BIT)
7076 ? _("destination register same as write-back base")
7077 : _("source register same as write-back base"));
7080 /* inst.operands[i] was set up by parse_address. Encode it into an
7081 ARM-format mode 2 load or store instruction. If is_t is true,
7082 reject forms that cannot be used with a T instruction (i.e. not
7085 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7087 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7089 encode_arm_addr_mode_common (i, is_t);
7091 if (inst.operands[i].immisreg)
7093 constraint ((inst.operands[i].imm == REG_PC
7094 || (is_pc && inst.operands[i].writeback)),
7096 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7097 inst.instruction |= inst.operands[i].imm;
7098 if (!inst.operands[i].negative)
7099 inst.instruction |= INDEX_UP;
7100 if (inst.operands[i].shifted)
7102 if (inst.operands[i].shift_kind == SHIFT_RRX)
7103 inst.instruction |= SHIFT_ROR << 5;
7106 inst.instruction |= inst.operands[i].shift_kind << 5;
7107 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7111 else /* immediate offset in inst.reloc */
7113 if (is_pc && !inst.reloc.pc_rel)
7115 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7117 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7118 cannot use PC in addressing.
7119 PC cannot be used in writeback addressing, either. */
7120 constraint ((is_t || inst.operands[i].writeback),
7123 /* Use of PC in str is deprecated for ARMv7. */
7124 if (warn_on_deprecated
7126 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7127 as_warn (_("use of PC in this instruction is deprecated"));
7130 if (inst.reloc.type == BFD_RELOC_UNUSED)
7132 /* Prefer + for zero encoded value. */
7133 if (!inst.operands[i].negative)
7134 inst.instruction |= INDEX_UP;
7135 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7140 /* inst.operands[i] was set up by parse_address. Encode it into an
7141 ARM-format mode 3 load or store instruction. Reject forms that
7142 cannot be used with such instructions. If is_t is true, reject
7143 forms that cannot be used with a T instruction (i.e. not
7146 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7148 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7150 inst.error = _("instruction does not accept scaled register index");
7154 encode_arm_addr_mode_common (i, is_t);
7156 if (inst.operands[i].immisreg)
7158 constraint ((inst.operands[i].imm == REG_PC
7159 || inst.operands[i].reg == REG_PC),
7161 inst.instruction |= inst.operands[i].imm;
7162 if (!inst.operands[i].negative)
7163 inst.instruction |= INDEX_UP;
7165 else /* immediate offset in inst.reloc */
7167 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7168 && inst.operands[i].writeback),
7170 inst.instruction |= HWOFFSET_IMM;
7171 if (inst.reloc.type == BFD_RELOC_UNUSED)
7173 /* Prefer + for zero encoded value. */
7174 if (!inst.operands[i].negative)
7175 inst.instruction |= INDEX_UP;
7177 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7182 /* inst.operands[i] was set up by parse_address. Encode it into an
7183 ARM-format instruction. Reject all forms which cannot be encoded
7184 into a coprocessor load/store instruction. If wb_ok is false,
7185 reject use of writeback; if unind_ok is false, reject use of
7186 unindexed addressing. If reloc_override is not 0, use it instead
7187 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7188 (in which case it is preserved). */
7191 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7193 inst.instruction |= inst.operands[i].reg << 16;
7195 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7197 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7199 gas_assert (!inst.operands[i].writeback);
7202 inst.error = _("instruction does not support unindexed addressing");
7205 inst.instruction |= inst.operands[i].imm;
7206 inst.instruction |= INDEX_UP;
7210 if (inst.operands[i].preind)
7211 inst.instruction |= PRE_INDEX;
7213 if (inst.operands[i].writeback)
7215 if (inst.operands[i].reg == REG_PC)
7217 inst.error = _("pc may not be used with write-back");
7222 inst.error = _("instruction does not support writeback");
7225 inst.instruction |= WRITE_BACK;
7229 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7230 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7231 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7232 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7235 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7237 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7240 /* Prefer + for zero encoded value. */
7241 if (!inst.operands[i].negative)
7242 inst.instruction |= INDEX_UP;
7247 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7248 Determine whether it can be performed with a move instruction; if
7249 it can, convert inst.instruction to that move instruction and
7250 return TRUE; if it can't, convert inst.instruction to a literal-pool
7251 load and return FALSE. If this is not a valid thing to do in the
7252 current context, set inst.error and return TRUE.
7254 inst.operands[i] describes the destination register. */
7257 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7262 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7266 if ((inst.instruction & tbit) == 0)
7268 inst.error = _("invalid pseudo operation");
7271 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7273 inst.error = _("constant expression expected");
7276 if (inst.reloc.exp.X_op == O_constant)
7280 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7282 /* This can be done with a mov(1) instruction. */
7283 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7284 inst.instruction |= inst.reloc.exp.X_add_number;
7290 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7293 /* This can be done with a mov instruction. */
7294 inst.instruction &= LITERAL_MASK;
7295 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7296 inst.instruction |= value & 0xfff;
7300 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7303 /* This can be done with a mvn instruction. */
7304 inst.instruction &= LITERAL_MASK;
7305 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7306 inst.instruction |= value & 0xfff;
7312 if (add_to_lit_pool () == FAIL)
7314 inst.error = _("literal pool insertion failed");
7317 inst.operands[1].reg = REG_PC;
7318 inst.operands[1].isreg = 1;
7319 inst.operands[1].preind = 1;
7320 inst.reloc.pc_rel = 1;
7321 inst.reloc.type = (thumb_p
7322 ? BFD_RELOC_ARM_THUMB_OFFSET
7324 ? BFD_RELOC_ARM_HWLITERAL
7325 : BFD_RELOC_ARM_LITERAL));
7329 /* Functions for instruction encoding, sorted by sub-architecture.
7330 First some generics; their names are taken from the conventional
7331 bit positions for register arguments in ARM format instructions. */
7341 inst.instruction |= inst.operands[0].reg << 12;
7347 inst.instruction |= inst.operands[0].reg << 12;
7348 inst.instruction |= inst.operands[1].reg;
7354 inst.instruction |= inst.operands[0].reg << 12;
7355 inst.instruction |= inst.operands[1].reg << 16;
7361 inst.instruction |= inst.operands[0].reg << 16;
7362 inst.instruction |= inst.operands[1].reg << 12;
7368 unsigned Rn = inst.operands[2].reg;
7369 /* Enforce restrictions on SWP instruction. */
7370 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7372 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7373 _("Rn must not overlap other operands"));
7375 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7376 if (warn_on_deprecated
7377 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7378 as_warn (_("swp{b} use is deprecated for this architecture"));
7381 inst.instruction |= inst.operands[0].reg << 12;
7382 inst.instruction |= inst.operands[1].reg;
7383 inst.instruction |= Rn << 16;
7389 inst.instruction |= inst.operands[0].reg << 12;
7390 inst.instruction |= inst.operands[1].reg << 16;
7391 inst.instruction |= inst.operands[2].reg;
7397 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7398 constraint (((inst.reloc.exp.X_op != O_constant
7399 && inst.reloc.exp.X_op != O_illegal)
7400 || inst.reloc.exp.X_add_number != 0),
7402 inst.instruction |= inst.operands[0].reg;
7403 inst.instruction |= inst.operands[1].reg << 12;
7404 inst.instruction |= inst.operands[2].reg << 16;
7410 inst.instruction |= inst.operands[0].imm;
7416 inst.instruction |= inst.operands[0].reg << 12;
7417 encode_arm_cp_address (1, TRUE, TRUE, 0);
7420 /* ARM instructions, in alphabetical order by function name (except
7421 that wrapper functions appear immediately after the function they
7424 /* This is a pseudo-op of the form "adr rd, label" to be converted
7425 into a relative address of the form "add rd, pc, #label-.-8". */
7430 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7432 /* Frag hacking will turn this into a sub instruction if the offset turns
7433 out to be negative. */
7434 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7435 inst.reloc.pc_rel = 1;
7436 inst.reloc.exp.X_add_number -= 8;
7439 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7440 into a relative address of the form:
7441 add rd, pc, #low(label-.-8)"
7442 add rd, rd, #high(label-.-8)" */
7447 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7449 /* Frag hacking will turn this into a sub instruction if the offset turns
7450 out to be negative. */
7451 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7452 inst.reloc.pc_rel = 1;
7453 inst.size = INSN_SIZE * 2;
7454 inst.reloc.exp.X_add_number -= 8;
7460 if (!inst.operands[1].present)
7461 inst.operands[1].reg = inst.operands[0].reg;
7462 inst.instruction |= inst.operands[0].reg << 12;
7463 inst.instruction |= inst.operands[1].reg << 16;
7464 encode_arm_shifter_operand (2);
7470 if (inst.operands[0].present)
7472 constraint ((inst.instruction & 0xf0) != 0x40
7473 && inst.operands[0].imm > 0xf
7474 && inst.operands[0].imm < 0x0,
7475 _("bad barrier type"));
7476 inst.instruction |= inst.operands[0].imm;
7479 inst.instruction |= 0xf;
7485 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7486 constraint (msb > 32, _("bit-field extends past end of register"));
7487 /* The instruction encoding stores the LSB and MSB,
7488 not the LSB and width. */
7489 inst.instruction |= inst.operands[0].reg << 12;
7490 inst.instruction |= inst.operands[1].imm << 7;
7491 inst.instruction |= (msb - 1) << 16;
7499 /* #0 in second position is alternative syntax for bfc, which is
7500 the same instruction but with REG_PC in the Rm field. */
7501 if (!inst.operands[1].isreg)
7502 inst.operands[1].reg = REG_PC;
7504 msb = inst.operands[2].imm + inst.operands[3].imm;
7505 constraint (msb > 32, _("bit-field extends past end of register"));
7506 /* The instruction encoding stores the LSB and MSB,
7507 not the LSB and width. */
7508 inst.instruction |= inst.operands[0].reg << 12;
7509 inst.instruction |= inst.operands[1].reg;
7510 inst.instruction |= inst.operands[2].imm << 7;
7511 inst.instruction |= (msb - 1) << 16;
7517 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7518 _("bit-field extends past end of register"));
7519 inst.instruction |= inst.operands[0].reg << 12;
7520 inst.instruction |= inst.operands[1].reg;
7521 inst.instruction |= inst.operands[2].imm << 7;
7522 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7525 /* ARM V5 breakpoint instruction (argument parse)
7526 BKPT <16 bit unsigned immediate>
7527 Instruction is not conditional.
7528 The bit pattern given in insns[] has the COND_ALWAYS condition,
7529 and it is an error if the caller tried to override that. */
7534 /* Top 12 of 16 bits to bits 19:8. */
7535 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7537 /* Bottom 4 of 16 bits to bits 3:0. */
7538 inst.instruction |= inst.operands[0].imm & 0xf;
7542 encode_branch (int default_reloc)
7544 if (inst.operands[0].hasreloc)
7546 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7547 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7548 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7549 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7550 ? BFD_RELOC_ARM_PLT32
7551 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7554 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7555 inst.reloc.pc_rel = 1;
7562 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7563 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7566 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7573 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7575 if (inst.cond == COND_ALWAYS)
7576 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7578 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7582 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7585 /* ARM V5 branch-link-exchange instruction (argument parse)
7586 BLX <target_addr> ie BLX(1)
7587 BLX{<condition>} <Rm> ie BLX(2)
7588 Unfortunately, there are two different opcodes for this mnemonic.
7589 So, the insns[].value is not used, and the code here zaps values
7590 into inst.instruction.
7591 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7596 if (inst.operands[0].isreg)
7598 /* Arg is a register; the opcode provided by insns[] is correct.
7599 It is not illegal to do "blx pc", just useless. */
7600 if (inst.operands[0].reg == REG_PC)
7601 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7603 inst.instruction |= inst.operands[0].reg;
7607 /* Arg is an address; this instruction cannot be executed
7608 conditionally, and the opcode must be adjusted.
7609 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7610 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7611 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7612 inst.instruction = 0xfa000000;
7613 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7620 bfd_boolean want_reloc;
7622 if (inst.operands[0].reg == REG_PC)
7623 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7625 inst.instruction |= inst.operands[0].reg;
7626 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7627 it is for ARMv4t or earlier. */
7628 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7629 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7633 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7638 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7642 /* ARM v5TEJ. Jump to Jazelle code. */
7647 if (inst.operands[0].reg == REG_PC)
7648 as_tsktsk (_("use of r15 in bxj is not really useful"));
7650 inst.instruction |= inst.operands[0].reg;
7653 /* Co-processor data operation:
7654 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7655 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7659 inst.instruction |= inst.operands[0].reg << 8;
7660 inst.instruction |= inst.operands[1].imm << 20;
7661 inst.instruction |= inst.operands[2].reg << 12;
7662 inst.instruction |= inst.operands[3].reg << 16;
7663 inst.instruction |= inst.operands[4].reg;
7664 inst.instruction |= inst.operands[5].imm << 5;
7670 inst.instruction |= inst.operands[0].reg << 16;
7671 encode_arm_shifter_operand (1);
7674 /* Transfer between coprocessor and ARM registers.
7675 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7680 No special properties. */
7687 Rd = inst.operands[2].reg;
7690 if (inst.instruction == 0xee000010
7691 || inst.instruction == 0xfe000010)
7693 reject_bad_reg (Rd);
7696 constraint (Rd == REG_SP, BAD_SP);
7701 if (inst.instruction == 0xe000010)
7702 constraint (Rd == REG_PC, BAD_PC);
7706 inst.instruction |= inst.operands[0].reg << 8;
7707 inst.instruction |= inst.operands[1].imm << 21;
7708 inst.instruction |= Rd << 12;
7709 inst.instruction |= inst.operands[3].reg << 16;
7710 inst.instruction |= inst.operands[4].reg;
7711 inst.instruction |= inst.operands[5].imm << 5;
7714 /* Transfer between coprocessor register and pair of ARM registers.
7715 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7720 Two XScale instructions are special cases of these:
7722 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7723 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7725 Result unpredictable if Rd or Rn is R15. */
7732 Rd = inst.operands[2].reg;
7733 Rn = inst.operands[3].reg;
7737 reject_bad_reg (Rd);
7738 reject_bad_reg (Rn);
7742 constraint (Rd == REG_PC, BAD_PC);
7743 constraint (Rn == REG_PC, BAD_PC);
7746 inst.instruction |= inst.operands[0].reg << 8;
7747 inst.instruction |= inst.operands[1].imm << 4;
7748 inst.instruction |= Rd << 12;
7749 inst.instruction |= Rn << 16;
7750 inst.instruction |= inst.operands[4].reg;
7756 inst.instruction |= inst.operands[0].imm << 6;
7757 if (inst.operands[1].present)
7759 inst.instruction |= CPSI_MMOD;
7760 inst.instruction |= inst.operands[1].imm;
7767 inst.instruction |= inst.operands[0].imm;
7773 unsigned Rd, Rn, Rm;
7775 Rd = inst.operands[0].reg;
7776 Rn = (inst.operands[1].present
7777 ? inst.operands[1].reg : Rd);
7778 Rm = inst.operands[2].reg;
7780 constraint ((Rd == REG_PC), BAD_PC);
7781 constraint ((Rn == REG_PC), BAD_PC);
7782 constraint ((Rm == REG_PC), BAD_PC);
7784 inst.instruction |= Rd << 16;
7785 inst.instruction |= Rn << 0;
7786 inst.instruction |= Rm << 8;
7792 /* There is no IT instruction in ARM mode. We
7793 process it to do the validation as if in
7794 thumb mode, just in case the code gets
7795 assembled for thumb using the unified syntax. */
7800 set_it_insn_type (IT_INSN);
7801 now_it.mask = (inst.instruction & 0xf) | 0x10;
7802 now_it.cc = inst.operands[0].imm;
7806 /* If there is only one register in the register list,
7807 then return its register number. Otherwise return -1. */
7809 only_one_reg_in_list (int range)
7811 int i = ffs (range) - 1;
7812 return (i > 15 || range != (1 << i)) ? -1 : i;
7816 encode_ldmstm(int from_push_pop_mnem)
7818 int base_reg = inst.operands[0].reg;
7819 int range = inst.operands[1].imm;
7822 inst.instruction |= base_reg << 16;
7823 inst.instruction |= range;
7825 if (inst.operands[1].writeback)
7826 inst.instruction |= LDM_TYPE_2_OR_3;
7828 if (inst.operands[0].writeback)
7830 inst.instruction |= WRITE_BACK;
7831 /* Check for unpredictable uses of writeback. */
7832 if (inst.instruction & LOAD_BIT)
7834 /* Not allowed in LDM type 2. */
7835 if ((inst.instruction & LDM_TYPE_2_OR_3)
7836 && ((range & (1 << REG_PC)) == 0))
7837 as_warn (_("writeback of base register is UNPREDICTABLE"));
7838 /* Only allowed if base reg not in list for other types. */
7839 else if (range & (1 << base_reg))
7840 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7844 /* Not allowed for type 2. */
7845 if (inst.instruction & LDM_TYPE_2_OR_3)
7846 as_warn (_("writeback of base register is UNPREDICTABLE"));
7847 /* Only allowed if base reg not in list, or first in list. */
7848 else if ((range & (1 << base_reg))
7849 && (range & ((1 << base_reg) - 1)))
7850 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7854 /* If PUSH/POP has only one register, then use the A2 encoding. */
7855 one_reg = only_one_reg_in_list (range);
7856 if (from_push_pop_mnem && one_reg >= 0)
7858 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7860 inst.instruction &= A_COND_MASK;
7861 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7862 inst.instruction |= one_reg << 12;
7869 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
7872 /* ARMv5TE load-consecutive (argument parse)
7881 constraint (inst.operands[0].reg % 2 != 0,
7882 _("first transfer register must be even"));
7883 constraint (inst.operands[1].present
7884 && inst.operands[1].reg != inst.operands[0].reg + 1,
7885 _("can only transfer two consecutive registers"));
7886 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7887 constraint (!inst.operands[2].isreg, _("'[' expected"));
7889 if (!inst.operands[1].present)
7890 inst.operands[1].reg = inst.operands[0].reg + 1;
7892 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7893 register and the first register written; we have to diagnose
7894 overlap between the base and the second register written here. */
7896 if (inst.operands[2].reg == inst.operands[1].reg
7897 && (inst.operands[2].writeback || inst.operands[2].postind))
7898 as_warn (_("base register written back, and overlaps "
7899 "second transfer register"));
7901 if (!(inst.instruction & V4_STR_BIT))
7903 /* For an index-register load, the index register must not overlap the
7904 destination (even if not write-back). */
7905 if (inst.operands[2].immisreg
7906 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7907 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7908 as_warn (_("index register overlaps transfer register"));
7910 inst.instruction |= inst.operands[0].reg << 12;
7911 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7917 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7918 || inst.operands[1].postind || inst.operands[1].writeback
7919 || inst.operands[1].immisreg || inst.operands[1].shifted
7920 || inst.operands[1].negative
7921 /* This can arise if the programmer has written
7923 or if they have mistakenly used a register name as the last
7926 It is very difficult to distinguish between these two cases
7927 because "rX" might actually be a label. ie the register
7928 name has been occluded by a symbol of the same name. So we
7929 just generate a general 'bad addressing mode' type error
7930 message and leave it up to the programmer to discover the
7931 true cause and fix their mistake. */
7932 || (inst.operands[1].reg == REG_PC),
7935 constraint (inst.reloc.exp.X_op != O_constant
7936 || inst.reloc.exp.X_add_number != 0,
7937 _("offset must be zero in ARM encoding"));
7939 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7941 inst.instruction |= inst.operands[0].reg << 12;
7942 inst.instruction |= inst.operands[1].reg << 16;
7943 inst.reloc.type = BFD_RELOC_UNUSED;
7949 constraint (inst.operands[0].reg % 2 != 0,
7950 _("even register required"));
7951 constraint (inst.operands[1].present
7952 && inst.operands[1].reg != inst.operands[0].reg + 1,
7953 _("can only load two consecutive registers"));
7954 /* If op 1 were present and equal to PC, this function wouldn't
7955 have been called in the first place. */
7956 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7958 inst.instruction |= inst.operands[0].reg << 12;
7959 inst.instruction |= inst.operands[2].reg << 16;
7962 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
7963 which is not a multiple of four is UNPREDICTABLE. */
7965 check_ldr_r15_aligned (void)
7967 constraint (!(inst.operands[1].immisreg)
7968 && (inst.operands[0].reg == REG_PC
7969 && inst.operands[1].reg == REG_PC
7970 && (inst.reloc.exp.X_add_number & 0x3)),
7971 _("ldr to register 15 must be 4-byte alligned"));
7977 inst.instruction |= inst.operands[0].reg << 12;
7978 if (!inst.operands[1].isreg)
7979 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
7981 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
7982 check_ldr_r15_aligned ();
7988 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7990 if (inst.operands[1].preind)
7992 constraint (inst.reloc.exp.X_op != O_constant
7993 || inst.reloc.exp.X_add_number != 0,
7994 _("this instruction requires a post-indexed address"));
7996 inst.operands[1].preind = 0;
7997 inst.operands[1].postind = 1;
7998 inst.operands[1].writeback = 1;
8000 inst.instruction |= inst.operands[0].reg << 12;
8001 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8004 /* Halfword and signed-byte load/store operations. */
8009 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8010 inst.instruction |= inst.operands[0].reg << 12;
8011 if (!inst.operands[1].isreg)
8012 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8014 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8020 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8022 if (inst.operands[1].preind)
8024 constraint (inst.reloc.exp.X_op != O_constant
8025 || inst.reloc.exp.X_add_number != 0,
8026 _("this instruction requires a post-indexed address"));
8028 inst.operands[1].preind = 0;
8029 inst.operands[1].postind = 1;
8030 inst.operands[1].writeback = 1;
8032 inst.instruction |= inst.operands[0].reg << 12;
8033 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8036 /* Co-processor register load/store.
8037 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8041 inst.instruction |= inst.operands[0].reg << 8;
8042 inst.instruction |= inst.operands[1].reg << 12;
8043 encode_arm_cp_address (2, TRUE, TRUE, 0);
8049 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8050 if (inst.operands[0].reg == inst.operands[1].reg
8051 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8052 && !(inst.instruction & 0x00400000))
8053 as_tsktsk (_("Rd and Rm should be different in mla"));
8055 inst.instruction |= inst.operands[0].reg << 16;
8056 inst.instruction |= inst.operands[1].reg;
8057 inst.instruction |= inst.operands[2].reg << 8;
8058 inst.instruction |= inst.operands[3].reg << 12;
8064 inst.instruction |= inst.operands[0].reg << 12;
8065 encode_arm_shifter_operand (1);
8068 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8075 top = (inst.instruction & 0x00400000) != 0;
8076 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8077 _(":lower16: not allowed this instruction"));
8078 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8079 _(":upper16: not allowed instruction"));
8080 inst.instruction |= inst.operands[0].reg << 12;
8081 if (inst.reloc.type == BFD_RELOC_UNUSED)
8083 imm = inst.reloc.exp.X_add_number;
8084 /* The value is in two pieces: 0:11, 16:19. */
8085 inst.instruction |= (imm & 0x00000fff);
8086 inst.instruction |= (imm & 0x0000f000) << 4;
8090 static void do_vfp_nsyn_opcode (const char *);
8093 do_vfp_nsyn_mrs (void)
8095 if (inst.operands[0].isvec)
8097 if (inst.operands[1].reg != 1)
8098 first_error (_("operand 1 must be FPSCR"));
8099 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8100 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8101 do_vfp_nsyn_opcode ("fmstat");
8103 else if (inst.operands[1].isvec)
8104 do_vfp_nsyn_opcode ("fmrx");
8112 do_vfp_nsyn_msr (void)
8114 if (inst.operands[0].isvec)
8115 do_vfp_nsyn_opcode ("fmxr");
8125 unsigned Rt = inst.operands[0].reg;
8127 if (thumb_mode && inst.operands[0].reg == REG_SP)
8129 inst.error = BAD_SP;
8133 /* APSR_ sets isvec. All other refs to PC are illegal. */
8134 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8136 inst.error = BAD_PC;
8140 switch (inst.operands[1].reg)
8147 inst.instruction |= (inst.operands[1].reg << 16);
8150 first_error (_("operand 1 must be a VFP extension System Register"));
8153 inst.instruction |= (Rt << 12);
8159 unsigned Rt = inst.operands[1].reg;
8162 reject_bad_reg (Rt);
8163 else if (Rt == REG_PC)
8165 inst.error = BAD_PC;
8169 switch (inst.operands[0].reg)
8174 inst.instruction |= (inst.operands[0].reg << 16);
8177 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8180 inst.instruction |= (Rt << 12);
8188 if (do_vfp_nsyn_mrs () == SUCCESS)
8191 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8192 inst.instruction |= inst.operands[0].reg << 12;
8194 if (inst.operands[1].isreg)
8196 br = inst.operands[1].reg;
8197 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8198 as_bad (_("bad register for mrs"));
8202 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8203 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8205 _("'APSR', 'CPSR' or 'SPSR' expected"));
8206 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8209 inst.instruction |= br;
8212 /* Two possible forms:
8213 "{C|S}PSR_<field>, Rm",
8214 "{C|S}PSR_f, #expression". */
8219 if (do_vfp_nsyn_msr () == SUCCESS)
8222 inst.instruction |= inst.operands[0].imm;
8223 if (inst.operands[1].isreg)
8224 inst.instruction |= inst.operands[1].reg;
8227 inst.instruction |= INST_IMMEDIATE;
8228 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8229 inst.reloc.pc_rel = 0;
8236 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8238 if (!inst.operands[2].present)
8239 inst.operands[2].reg = inst.operands[0].reg;
8240 inst.instruction |= inst.operands[0].reg << 16;
8241 inst.instruction |= inst.operands[1].reg;
8242 inst.instruction |= inst.operands[2].reg << 8;
8244 if (inst.operands[0].reg == inst.operands[1].reg
8245 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8246 as_tsktsk (_("Rd and Rm should be different in mul"));
8249 /* Long Multiply Parser
8250 UMULL RdLo, RdHi, Rm, Rs
8251 SMULL RdLo, RdHi, Rm, Rs
8252 UMLAL RdLo, RdHi, Rm, Rs
8253 SMLAL RdLo, RdHi, Rm, Rs. */
8258 inst.instruction |= inst.operands[0].reg << 12;
8259 inst.instruction |= inst.operands[1].reg << 16;
8260 inst.instruction |= inst.operands[2].reg;
8261 inst.instruction |= inst.operands[3].reg << 8;
8263 /* rdhi and rdlo must be different. */
8264 if (inst.operands[0].reg == inst.operands[1].reg)
8265 as_tsktsk (_("rdhi and rdlo must be different"));
8267 /* rdhi, rdlo and rm must all be different before armv6. */
8268 if ((inst.operands[0].reg == inst.operands[2].reg
8269 || inst.operands[1].reg == inst.operands[2].reg)
8270 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8271 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8277 if (inst.operands[0].present
8278 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8280 /* Architectural NOP hints are CPSR sets with no bits selected. */
8281 inst.instruction &= 0xf0000000;
8282 inst.instruction |= 0x0320f000;
8283 if (inst.operands[0].present)
8284 inst.instruction |= inst.operands[0].imm;
8288 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8289 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8290 Condition defaults to COND_ALWAYS.
8291 Error if Rd, Rn or Rm are R15. */
8296 inst.instruction |= inst.operands[0].reg << 12;
8297 inst.instruction |= inst.operands[1].reg << 16;
8298 inst.instruction |= inst.operands[2].reg;
8299 if (inst.operands[3].present)
8300 encode_arm_shift (3);
8303 /* ARM V6 PKHTB (Argument Parse). */
8308 if (!inst.operands[3].present)
8310 /* If the shift specifier is omitted, turn the instruction
8311 into pkhbt rd, rm, rn. */
8312 inst.instruction &= 0xfff00010;
8313 inst.instruction |= inst.operands[0].reg << 12;
8314 inst.instruction |= inst.operands[1].reg;
8315 inst.instruction |= inst.operands[2].reg << 16;
8319 inst.instruction |= inst.operands[0].reg << 12;
8320 inst.instruction |= inst.operands[1].reg << 16;
8321 inst.instruction |= inst.operands[2].reg;
8322 encode_arm_shift (3);
8326 /* ARMv5TE: Preload-Cache
8327 MP Extensions: Preload for write
8331 Syntactically, like LDR with B=1, W=0, L=1. */
8336 constraint (!inst.operands[0].isreg,
8337 _("'[' expected after PLD mnemonic"));
8338 constraint (inst.operands[0].postind,
8339 _("post-indexed expression used in preload instruction"));
8340 constraint (inst.operands[0].writeback,
8341 _("writeback used in preload instruction"));
8342 constraint (!inst.operands[0].preind,
8343 _("unindexed addressing used in preload instruction"));
8344 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8347 /* ARMv7: PLI <addr_mode> */
8351 constraint (!inst.operands[0].isreg,
8352 _("'[' expected after PLI mnemonic"));
8353 constraint (inst.operands[0].postind,
8354 _("post-indexed expression used in preload instruction"));
8355 constraint (inst.operands[0].writeback,
8356 _("writeback used in preload instruction"));
8357 constraint (!inst.operands[0].preind,
8358 _("unindexed addressing used in preload instruction"));
8359 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8360 inst.instruction &= ~PRE_INDEX;
8366 inst.operands[1] = inst.operands[0];
8367 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8368 inst.operands[0].isreg = 1;
8369 inst.operands[0].writeback = 1;
8370 inst.operands[0].reg = REG_SP;
8371 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8374 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8375 word at the specified address and the following word
8377 Unconditionally executed.
8378 Error if Rn is R15. */
8383 inst.instruction |= inst.operands[0].reg << 16;
8384 if (inst.operands[0].writeback)
8385 inst.instruction |= WRITE_BACK;
8388 /* ARM V6 ssat (argument parse). */
8393 inst.instruction |= inst.operands[0].reg << 12;
8394 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8395 inst.instruction |= inst.operands[2].reg;
8397 if (inst.operands[3].present)
8398 encode_arm_shift (3);
8401 /* ARM V6 usat (argument parse). */
8406 inst.instruction |= inst.operands[0].reg << 12;
8407 inst.instruction |= inst.operands[1].imm << 16;
8408 inst.instruction |= inst.operands[2].reg;
8410 if (inst.operands[3].present)
8411 encode_arm_shift (3);
8414 /* ARM V6 ssat16 (argument parse). */
8419 inst.instruction |= inst.operands[0].reg << 12;
8420 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8421 inst.instruction |= inst.operands[2].reg;
8427 inst.instruction |= inst.operands[0].reg << 12;
8428 inst.instruction |= inst.operands[1].imm << 16;
8429 inst.instruction |= inst.operands[2].reg;
8432 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8433 preserving the other bits.
8435 setend <endian_specifier>, where <endian_specifier> is either
8441 if (inst.operands[0].imm)
8442 inst.instruction |= 0x200;
8448 unsigned int Rm = (inst.operands[1].present
8449 ? inst.operands[1].reg
8450 : inst.operands[0].reg);
8452 inst.instruction |= inst.operands[0].reg << 12;
8453 inst.instruction |= Rm;
8454 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8456 inst.instruction |= inst.operands[2].reg << 8;
8457 inst.instruction |= SHIFT_BY_REG;
8458 /* PR 12854: Error on extraneous shifts. */
8459 constraint (inst.operands[2].shifted,
8460 _("extraneous shift as part of operand to shift insn"));
8463 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8469 inst.reloc.type = BFD_RELOC_ARM_SMC;
8470 inst.reloc.pc_rel = 0;
8476 inst.reloc.type = BFD_RELOC_ARM_HVC;
8477 inst.reloc.pc_rel = 0;
8483 inst.reloc.type = BFD_RELOC_ARM_SWI;
8484 inst.reloc.pc_rel = 0;
8487 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8488 SMLAxy{cond} Rd,Rm,Rs,Rn
8489 SMLAWy{cond} Rd,Rm,Rs,Rn
8490 Error if any register is R15. */
8495 inst.instruction |= inst.operands[0].reg << 16;
8496 inst.instruction |= inst.operands[1].reg;
8497 inst.instruction |= inst.operands[2].reg << 8;
8498 inst.instruction |= inst.operands[3].reg << 12;
8501 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8502 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8503 Error if any register is R15.
8504 Warning if Rdlo == Rdhi. */
8509 inst.instruction |= inst.operands[0].reg << 12;
8510 inst.instruction |= inst.operands[1].reg << 16;
8511 inst.instruction |= inst.operands[2].reg;
8512 inst.instruction |= inst.operands[3].reg << 8;
8514 if (inst.operands[0].reg == inst.operands[1].reg)
8515 as_tsktsk (_("rdhi and rdlo must be different"));
8518 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8519 SMULxy{cond} Rd,Rm,Rs
8520 Error if any register is R15. */
8525 inst.instruction |= inst.operands[0].reg << 16;
8526 inst.instruction |= inst.operands[1].reg;
8527 inst.instruction |= inst.operands[2].reg << 8;
8530 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8531 the same for both ARM and Thumb-2. */
8538 if (inst.operands[0].present)
8540 reg = inst.operands[0].reg;
8541 constraint (reg != REG_SP, _("SRS base register must be r13"));
8546 inst.instruction |= reg << 16;
8547 inst.instruction |= inst.operands[1].imm;
8548 if (inst.operands[0].writeback || inst.operands[1].writeback)
8549 inst.instruction |= WRITE_BACK;
8552 /* ARM V6 strex (argument parse). */
8557 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8558 || inst.operands[2].postind || inst.operands[2].writeback
8559 || inst.operands[2].immisreg || inst.operands[2].shifted
8560 || inst.operands[2].negative
8561 /* See comment in do_ldrex(). */
8562 || (inst.operands[2].reg == REG_PC),
8565 constraint (inst.operands[0].reg == inst.operands[1].reg
8566 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8568 constraint (inst.reloc.exp.X_op != O_constant
8569 || inst.reloc.exp.X_add_number != 0,
8570 _("offset must be zero in ARM encoding"));
8572 inst.instruction |= inst.operands[0].reg << 12;
8573 inst.instruction |= inst.operands[1].reg;
8574 inst.instruction |= inst.operands[2].reg << 16;
8575 inst.reloc.type = BFD_RELOC_UNUSED;
8581 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8582 || inst.operands[2].postind || inst.operands[2].writeback
8583 || inst.operands[2].immisreg || inst.operands[2].shifted
8584 || inst.operands[2].negative,
8587 constraint (inst.operands[0].reg == inst.operands[1].reg
8588 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8596 constraint (inst.operands[1].reg % 2 != 0,
8597 _("even register required"));
8598 constraint (inst.operands[2].present
8599 && inst.operands[2].reg != inst.operands[1].reg + 1,
8600 _("can only store two consecutive registers"));
8601 /* If op 2 were present and equal to PC, this function wouldn't
8602 have been called in the first place. */
8603 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8605 constraint (inst.operands[0].reg == inst.operands[1].reg
8606 || inst.operands[0].reg == inst.operands[1].reg + 1
8607 || inst.operands[0].reg == inst.operands[3].reg,
8610 inst.instruction |= inst.operands[0].reg << 12;
8611 inst.instruction |= inst.operands[1].reg;
8612 inst.instruction |= inst.operands[3].reg << 16;
8615 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8616 extends it to 32-bits, and adds the result to a value in another
8617 register. You can specify a rotation by 0, 8, 16, or 24 bits
8618 before extracting the 16-bit value.
8619 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8620 Condition defaults to COND_ALWAYS.
8621 Error if any register uses R15. */
8626 inst.instruction |= inst.operands[0].reg << 12;
8627 inst.instruction |= inst.operands[1].reg << 16;
8628 inst.instruction |= inst.operands[2].reg;
8629 inst.instruction |= inst.operands[3].imm << 10;
8634 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8635 Condition defaults to COND_ALWAYS.
8636 Error if any register uses R15. */
8641 inst.instruction |= inst.operands[0].reg << 12;
8642 inst.instruction |= inst.operands[1].reg;
8643 inst.instruction |= inst.operands[2].imm << 10;
8646 /* VFP instructions. In a logical order: SP variant first, monad
8647 before dyad, arithmetic then move then load/store. */
8650 do_vfp_sp_monadic (void)
8652 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8653 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8657 do_vfp_sp_dyadic (void)
8659 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8660 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8661 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8665 do_vfp_sp_compare_z (void)
8667 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8671 do_vfp_dp_sp_cvt (void)
8673 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8674 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8678 do_vfp_sp_dp_cvt (void)
8680 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8681 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8685 do_vfp_reg_from_sp (void)
8687 inst.instruction |= inst.operands[0].reg << 12;
8688 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8692 do_vfp_reg2_from_sp2 (void)
8694 constraint (inst.operands[2].imm != 2,
8695 _("only two consecutive VFP SP registers allowed here"));
8696 inst.instruction |= inst.operands[0].reg << 12;
8697 inst.instruction |= inst.operands[1].reg << 16;
8698 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8702 do_vfp_sp_from_reg (void)
8704 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8705 inst.instruction |= inst.operands[1].reg << 12;
8709 do_vfp_sp2_from_reg2 (void)
8711 constraint (inst.operands[0].imm != 2,
8712 _("only two consecutive VFP SP registers allowed here"));
8713 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8714 inst.instruction |= inst.operands[1].reg << 12;
8715 inst.instruction |= inst.operands[2].reg << 16;
8719 do_vfp_sp_ldst (void)
8721 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8722 encode_arm_cp_address (1, FALSE, TRUE, 0);
8726 do_vfp_dp_ldst (void)
8728 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8729 encode_arm_cp_address (1, FALSE, TRUE, 0);
8734 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8736 if (inst.operands[0].writeback)
8737 inst.instruction |= WRITE_BACK;
8739 constraint (ldstm_type != VFP_LDSTMIA,
8740 _("this addressing mode requires base-register writeback"));
8741 inst.instruction |= inst.operands[0].reg << 16;
8742 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8743 inst.instruction |= inst.operands[1].imm;
8747 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8751 if (inst.operands[0].writeback)
8752 inst.instruction |= WRITE_BACK;
8754 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8755 _("this addressing mode requires base-register writeback"));
8757 inst.instruction |= inst.operands[0].reg << 16;
8758 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8760 count = inst.operands[1].imm << 1;
8761 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8764 inst.instruction |= count;
8768 do_vfp_sp_ldstmia (void)
8770 vfp_sp_ldstm (VFP_LDSTMIA);
8774 do_vfp_sp_ldstmdb (void)
8776 vfp_sp_ldstm (VFP_LDSTMDB);
8780 do_vfp_dp_ldstmia (void)
8782 vfp_dp_ldstm (VFP_LDSTMIA);
8786 do_vfp_dp_ldstmdb (void)
8788 vfp_dp_ldstm (VFP_LDSTMDB);
8792 do_vfp_xp_ldstmia (void)
8794 vfp_dp_ldstm (VFP_LDSTMIAX);
8798 do_vfp_xp_ldstmdb (void)
8800 vfp_dp_ldstm (VFP_LDSTMDBX);
8804 do_vfp_dp_rd_rm (void)
8806 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8807 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8811 do_vfp_dp_rn_rd (void)
8813 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8814 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8818 do_vfp_dp_rd_rn (void)
8820 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8821 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8825 do_vfp_dp_rd_rn_rm (void)
8827 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8828 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8829 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8835 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8839 do_vfp_dp_rm_rd_rn (void)
8841 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8842 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8843 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8846 /* VFPv3 instructions. */
8848 do_vfp_sp_const (void)
8850 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8851 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8852 inst.instruction |= (inst.operands[1].imm & 0x0f);
8856 do_vfp_dp_const (void)
8858 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8859 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8860 inst.instruction |= (inst.operands[1].imm & 0x0f);
8864 vfp_conv (int srcsize)
8866 int immbits = srcsize - inst.operands[1].imm;
8868 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8870 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8871 i.e. immbits must be in range 0 - 16. */
8872 inst.error = _("immediate value out of range, expected range [0, 16]");
8875 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
8877 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8878 i.e. immbits must be in range 0 - 31. */
8879 inst.error = _("immediate value out of range, expected range [1, 32]");
8883 inst.instruction |= (immbits & 1) << 5;
8884 inst.instruction |= (immbits >> 1);
8888 do_vfp_sp_conv_16 (void)
8890 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8895 do_vfp_dp_conv_16 (void)
8897 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8902 do_vfp_sp_conv_32 (void)
8904 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8909 do_vfp_dp_conv_32 (void)
8911 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8915 /* FPA instructions. Also in a logical order. */
8920 inst.instruction |= inst.operands[0].reg << 16;
8921 inst.instruction |= inst.operands[1].reg;
8925 do_fpa_ldmstm (void)
8927 inst.instruction |= inst.operands[0].reg << 12;
8928 switch (inst.operands[1].imm)
8930 case 1: inst.instruction |= CP_T_X; break;
8931 case 2: inst.instruction |= CP_T_Y; break;
8932 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8937 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8939 /* The instruction specified "ea" or "fd", so we can only accept
8940 [Rn]{!}. The instruction does not really support stacking or
8941 unstacking, so we have to emulate these by setting appropriate
8942 bits and offsets. */
8943 constraint (inst.reloc.exp.X_op != O_constant
8944 || inst.reloc.exp.X_add_number != 0,
8945 _("this instruction does not support indexing"));
8947 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8948 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8950 if (!(inst.instruction & INDEX_UP))
8951 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8953 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8955 inst.operands[2].preind = 0;
8956 inst.operands[2].postind = 1;
8960 encode_arm_cp_address (2, TRUE, TRUE, 0);
8963 /* iWMMXt instructions: strictly in alphabetical order. */
8966 do_iwmmxt_tandorc (void)
8968 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8972 do_iwmmxt_textrc (void)
8974 inst.instruction |= inst.operands[0].reg << 12;
8975 inst.instruction |= inst.operands[1].imm;
8979 do_iwmmxt_textrm (void)
8981 inst.instruction |= inst.operands[0].reg << 12;
8982 inst.instruction |= inst.operands[1].reg << 16;
8983 inst.instruction |= inst.operands[2].imm;
8987 do_iwmmxt_tinsr (void)
8989 inst.instruction |= inst.operands[0].reg << 16;
8990 inst.instruction |= inst.operands[1].reg << 12;
8991 inst.instruction |= inst.operands[2].imm;
8995 do_iwmmxt_tmia (void)
8997 inst.instruction |= inst.operands[0].reg << 5;
8998 inst.instruction |= inst.operands[1].reg;
8999 inst.instruction |= inst.operands[2].reg << 12;
9003 do_iwmmxt_waligni (void)
9005 inst.instruction |= inst.operands[0].reg << 12;
9006 inst.instruction |= inst.operands[1].reg << 16;
9007 inst.instruction |= inst.operands[2].reg;
9008 inst.instruction |= inst.operands[3].imm << 20;
9012 do_iwmmxt_wmerge (void)
9014 inst.instruction |= inst.operands[0].reg << 12;
9015 inst.instruction |= inst.operands[1].reg << 16;
9016 inst.instruction |= inst.operands[2].reg;
9017 inst.instruction |= inst.operands[3].imm << 21;
9021 do_iwmmxt_wmov (void)
9023 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9024 inst.instruction |= inst.operands[0].reg << 12;
9025 inst.instruction |= inst.operands[1].reg << 16;
9026 inst.instruction |= inst.operands[1].reg;
9030 do_iwmmxt_wldstbh (void)
9033 inst.instruction |= inst.operands[0].reg << 12;
9035 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9037 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9038 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9042 do_iwmmxt_wldstw (void)
9044 /* RIWR_RIWC clears .isreg for a control register. */
9045 if (!inst.operands[0].isreg)
9047 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9048 inst.instruction |= 0xf0000000;
9051 inst.instruction |= inst.operands[0].reg << 12;
9052 encode_arm_cp_address (1, TRUE, TRUE, 0);
9056 do_iwmmxt_wldstd (void)
9058 inst.instruction |= inst.operands[0].reg << 12;
9059 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9060 && inst.operands[1].immisreg)
9062 inst.instruction &= ~0x1a000ff;
9063 inst.instruction |= (0xf << 28);
9064 if (inst.operands[1].preind)
9065 inst.instruction |= PRE_INDEX;
9066 if (!inst.operands[1].negative)
9067 inst.instruction |= INDEX_UP;
9068 if (inst.operands[1].writeback)
9069 inst.instruction |= WRITE_BACK;
9070 inst.instruction |= inst.operands[1].reg << 16;
9071 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9072 inst.instruction |= inst.operands[1].imm;
9075 encode_arm_cp_address (1, TRUE, FALSE, 0);
9079 do_iwmmxt_wshufh (void)
9081 inst.instruction |= inst.operands[0].reg << 12;
9082 inst.instruction |= inst.operands[1].reg << 16;
9083 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9084 inst.instruction |= (inst.operands[2].imm & 0x0f);
9088 do_iwmmxt_wzero (void)
9090 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9091 inst.instruction |= inst.operands[0].reg;
9092 inst.instruction |= inst.operands[0].reg << 12;
9093 inst.instruction |= inst.operands[0].reg << 16;
9097 do_iwmmxt_wrwrwr_or_imm5 (void)
9099 if (inst.operands[2].isreg)
9102 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9103 _("immediate operand requires iWMMXt2"));
9105 if (inst.operands[2].imm == 0)
9107 switch ((inst.instruction >> 20) & 0xf)
9113 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9114 inst.operands[2].imm = 16;
9115 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9121 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9122 inst.operands[2].imm = 32;
9123 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9130 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9132 wrn = (inst.instruction >> 16) & 0xf;
9133 inst.instruction &= 0xff0fff0f;
9134 inst.instruction |= wrn;
9135 /* Bail out here; the instruction is now assembled. */
9140 /* Map 32 -> 0, etc. */
9141 inst.operands[2].imm &= 0x1f;
9142 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9146 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9147 operations first, then control, shift, and load/store. */
9149 /* Insns like "foo X,Y,Z". */
9152 do_mav_triple (void)
9154 inst.instruction |= inst.operands[0].reg << 16;
9155 inst.instruction |= inst.operands[1].reg;
9156 inst.instruction |= inst.operands[2].reg << 12;
9159 /* Insns like "foo W,X,Y,Z".
9160 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9165 inst.instruction |= inst.operands[0].reg << 5;
9166 inst.instruction |= inst.operands[1].reg << 12;
9167 inst.instruction |= inst.operands[2].reg << 16;
9168 inst.instruction |= inst.operands[3].reg;
9171 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9175 inst.instruction |= inst.operands[1].reg << 12;
9178 /* Maverick shift immediate instructions.
9179 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9180 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9185 int imm = inst.operands[2].imm;
9187 inst.instruction |= inst.operands[0].reg << 12;
9188 inst.instruction |= inst.operands[1].reg << 16;
9190 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9191 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9192 Bit 4 should be 0. */
9193 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9195 inst.instruction |= imm;
9198 /* XScale instructions. Also sorted arithmetic before move. */
9200 /* Xscale multiply-accumulate (argument parse)
9203 MIAxycc acc0,Rm,Rs. */
9208 inst.instruction |= inst.operands[1].reg;
9209 inst.instruction |= inst.operands[2].reg << 12;
9212 /* Xscale move-accumulator-register (argument parse)
9214 MARcc acc0,RdLo,RdHi. */
9219 inst.instruction |= inst.operands[1].reg << 12;
9220 inst.instruction |= inst.operands[2].reg << 16;
9223 /* Xscale move-register-accumulator (argument parse)
9225 MRAcc RdLo,RdHi,acc0. */
9230 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9231 inst.instruction |= inst.operands[0].reg << 12;
9232 inst.instruction |= inst.operands[1].reg << 16;
9235 /* Encoding functions relevant only to Thumb. */
9237 /* inst.operands[i] is a shifted-register operand; encode
9238 it into inst.instruction in the format used by Thumb32. */
9241 encode_thumb32_shifted_operand (int i)
9243 unsigned int value = inst.reloc.exp.X_add_number;
9244 unsigned int shift = inst.operands[i].shift_kind;
9246 constraint (inst.operands[i].immisreg,
9247 _("shift by register not allowed in thumb mode"));
9248 inst.instruction |= inst.operands[i].reg;
9249 if (shift == SHIFT_RRX)
9250 inst.instruction |= SHIFT_ROR << 4;
9253 constraint (inst.reloc.exp.X_op != O_constant,
9254 _("expression too complex"));
9256 constraint (value > 32
9257 || (value == 32 && (shift == SHIFT_LSL
9258 || shift == SHIFT_ROR)),
9259 _("shift expression is too large"));
9263 else if (value == 32)
9266 inst.instruction |= shift << 4;
9267 inst.instruction |= (value & 0x1c) << 10;
9268 inst.instruction |= (value & 0x03) << 6;
9273 /* inst.operands[i] was set up by parse_address. Encode it into a
9274 Thumb32 format load or store instruction. Reject forms that cannot
9275 be used with such instructions. If is_t is true, reject forms that
9276 cannot be used with a T instruction; if is_d is true, reject forms
9277 that cannot be used with a D instruction. If it is a store insn,
9281 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9283 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9285 constraint (!inst.operands[i].isreg,
9286 _("Instruction does not support =N addresses"));
9288 inst.instruction |= inst.operands[i].reg << 16;
9289 if (inst.operands[i].immisreg)
9291 constraint (is_pc, BAD_PC_ADDRESSING);
9292 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9293 constraint (inst.operands[i].negative,
9294 _("Thumb does not support negative register indexing"));
9295 constraint (inst.operands[i].postind,
9296 _("Thumb does not support register post-indexing"));
9297 constraint (inst.operands[i].writeback,
9298 _("Thumb does not support register indexing with writeback"));
9299 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9300 _("Thumb supports only LSL in shifted register indexing"));
9302 inst.instruction |= inst.operands[i].imm;
9303 if (inst.operands[i].shifted)
9305 constraint (inst.reloc.exp.X_op != O_constant,
9306 _("expression too complex"));
9307 constraint (inst.reloc.exp.X_add_number < 0
9308 || inst.reloc.exp.X_add_number > 3,
9309 _("shift out of range"));
9310 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9312 inst.reloc.type = BFD_RELOC_UNUSED;
9314 else if (inst.operands[i].preind)
9316 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9317 constraint (is_t && inst.operands[i].writeback,
9318 _("cannot use writeback with this instruction"));
9319 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9320 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9324 inst.instruction |= 0x01000000;
9325 if (inst.operands[i].writeback)
9326 inst.instruction |= 0x00200000;
9330 inst.instruction |= 0x00000c00;
9331 if (inst.operands[i].writeback)
9332 inst.instruction |= 0x00000100;
9334 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9336 else if (inst.operands[i].postind)
9338 gas_assert (inst.operands[i].writeback);
9339 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9340 constraint (is_t, _("cannot use post-indexing with this instruction"));
9343 inst.instruction |= 0x00200000;
9345 inst.instruction |= 0x00000900;
9346 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9348 else /* unindexed - only for coprocessor */
9349 inst.error = _("instruction does not accept unindexed addressing");
9352 /* Table of Thumb instructions which exist in both 16- and 32-bit
9353 encodings (the latter only in post-V6T2 cores). The index is the
9354 value used in the insns table below. When there is more than one
9355 possible 16-bit encoding for the instruction, this table always
9357 Also contains several pseudo-instructions used during relaxation. */
9358 #define T16_32_TAB \
9359 X(_adc, 4140, eb400000), \
9360 X(_adcs, 4140, eb500000), \
9361 X(_add, 1c00, eb000000), \
9362 X(_adds, 1c00, eb100000), \
9363 X(_addi, 0000, f1000000), \
9364 X(_addis, 0000, f1100000), \
9365 X(_add_pc,000f, f20f0000), \
9366 X(_add_sp,000d, f10d0000), \
9367 X(_adr, 000f, f20f0000), \
9368 X(_and, 4000, ea000000), \
9369 X(_ands, 4000, ea100000), \
9370 X(_asr, 1000, fa40f000), \
9371 X(_asrs, 1000, fa50f000), \
9372 X(_b, e000, f000b000), \
9373 X(_bcond, d000, f0008000), \
9374 X(_bic, 4380, ea200000), \
9375 X(_bics, 4380, ea300000), \
9376 X(_cmn, 42c0, eb100f00), \
9377 X(_cmp, 2800, ebb00f00), \
9378 X(_cpsie, b660, f3af8400), \
9379 X(_cpsid, b670, f3af8600), \
9380 X(_cpy, 4600, ea4f0000), \
9381 X(_dec_sp,80dd, f1ad0d00), \
9382 X(_eor, 4040, ea800000), \
9383 X(_eors, 4040, ea900000), \
9384 X(_inc_sp,00dd, f10d0d00), \
9385 X(_ldmia, c800, e8900000), \
9386 X(_ldr, 6800, f8500000), \
9387 X(_ldrb, 7800, f8100000), \
9388 X(_ldrh, 8800, f8300000), \
9389 X(_ldrsb, 5600, f9100000), \
9390 X(_ldrsh, 5e00, f9300000), \
9391 X(_ldr_pc,4800, f85f0000), \
9392 X(_ldr_pc2,4800, f85f0000), \
9393 X(_ldr_sp,9800, f85d0000), \
9394 X(_lsl, 0000, fa00f000), \
9395 X(_lsls, 0000, fa10f000), \
9396 X(_lsr, 0800, fa20f000), \
9397 X(_lsrs, 0800, fa30f000), \
9398 X(_mov, 2000, ea4f0000), \
9399 X(_movs, 2000, ea5f0000), \
9400 X(_mul, 4340, fb00f000), \
9401 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9402 X(_mvn, 43c0, ea6f0000), \
9403 X(_mvns, 43c0, ea7f0000), \
9404 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9405 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9406 X(_orr, 4300, ea400000), \
9407 X(_orrs, 4300, ea500000), \
9408 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9409 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9410 X(_rev, ba00, fa90f080), \
9411 X(_rev16, ba40, fa90f090), \
9412 X(_revsh, bac0, fa90f0b0), \
9413 X(_ror, 41c0, fa60f000), \
9414 X(_rors, 41c0, fa70f000), \
9415 X(_sbc, 4180, eb600000), \
9416 X(_sbcs, 4180, eb700000), \
9417 X(_stmia, c000, e8800000), \
9418 X(_str, 6000, f8400000), \
9419 X(_strb, 7000, f8000000), \
9420 X(_strh, 8000, f8200000), \
9421 X(_str_sp,9000, f84d0000), \
9422 X(_sub, 1e00, eba00000), \
9423 X(_subs, 1e00, ebb00000), \
9424 X(_subi, 8000, f1a00000), \
9425 X(_subis, 8000, f1b00000), \
9426 X(_sxtb, b240, fa4ff080), \
9427 X(_sxth, b200, fa0ff080), \
9428 X(_tst, 4200, ea100f00), \
9429 X(_uxtb, b2c0, fa5ff080), \
9430 X(_uxth, b280, fa1ff080), \
9431 X(_nop, bf00, f3af8000), \
9432 X(_yield, bf10, f3af8001), \
9433 X(_wfe, bf20, f3af8002), \
9434 X(_wfi, bf30, f3af8003), \
9435 X(_sev, bf40, f3af8004),
9437 /* To catch errors in encoding functions, the codes are all offset by
9438 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9439 as 16-bit instructions. */
9440 #define X(a,b,c) T_MNEM##a
9441 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9444 #define X(a,b,c) 0x##b
9445 static const unsigned short thumb_op16[] = { T16_32_TAB };
9446 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9449 #define X(a,b,c) 0x##c
9450 static const unsigned int thumb_op32[] = { T16_32_TAB };
9451 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9452 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9456 /* Thumb instruction encoders, in alphabetical order. */
9461 do_t_add_sub_w (void)
9465 Rd = inst.operands[0].reg;
9466 Rn = inst.operands[1].reg;
9468 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9469 is the SP-{plus,minus}-immediate form of the instruction. */
9471 constraint (Rd == REG_PC, BAD_PC);
9473 reject_bad_reg (Rd);
9475 inst.instruction |= (Rn << 16) | (Rd << 8);
9476 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9479 /* Parse an add or subtract instruction. We get here with inst.instruction
9480 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9487 Rd = inst.operands[0].reg;
9488 Rs = (inst.operands[1].present
9489 ? inst.operands[1].reg /* Rd, Rs, foo */
9490 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9493 set_it_insn_type_last ();
9501 flags = (inst.instruction == T_MNEM_adds
9502 || inst.instruction == T_MNEM_subs);
9504 narrow = !in_it_block ();
9506 narrow = in_it_block ();
9507 if (!inst.operands[2].isreg)
9511 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9513 add = (inst.instruction == T_MNEM_add
9514 || inst.instruction == T_MNEM_adds);
9516 if (inst.size_req != 4)
9518 /* Attempt to use a narrow opcode, with relaxation if
9520 if (Rd == REG_SP && Rs == REG_SP && !flags)
9521 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9522 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9523 opcode = T_MNEM_add_sp;
9524 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9525 opcode = T_MNEM_add_pc;
9526 else if (Rd <= 7 && Rs <= 7 && narrow)
9529 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9531 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9535 inst.instruction = THUMB_OP16(opcode);
9536 inst.instruction |= (Rd << 4) | Rs;
9537 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9538 if (inst.size_req != 2)
9539 inst.relax = opcode;
9542 constraint (inst.size_req == 2, BAD_HIREG);
9544 if (inst.size_req == 4
9545 || (inst.size_req != 2 && !opcode))
9549 constraint (add, BAD_PC);
9550 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9551 _("only SUBS PC, LR, #const allowed"));
9552 constraint (inst.reloc.exp.X_op != O_constant,
9553 _("expression too complex"));
9554 constraint (inst.reloc.exp.X_add_number < 0
9555 || inst.reloc.exp.X_add_number > 0xff,
9556 _("immediate value out of range"));
9557 inst.instruction = T2_SUBS_PC_LR
9558 | inst.reloc.exp.X_add_number;
9559 inst.reloc.type = BFD_RELOC_UNUSED;
9562 else if (Rs == REG_PC)
9564 /* Always use addw/subw. */
9565 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9566 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9570 inst.instruction = THUMB_OP32 (inst.instruction);
9571 inst.instruction = (inst.instruction & 0xe1ffffff)
9574 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9576 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9578 inst.instruction |= Rd << 8;
9579 inst.instruction |= Rs << 16;
9584 unsigned int value = inst.reloc.exp.X_add_number;
9585 unsigned int shift = inst.operands[2].shift_kind;
9587 Rn = inst.operands[2].reg;
9588 /* See if we can do this with a 16-bit instruction. */
9589 if (!inst.operands[2].shifted && inst.size_req != 4)
9591 if (Rd > 7 || Rs > 7 || Rn > 7)
9596 inst.instruction = ((inst.instruction == T_MNEM_adds
9597 || inst.instruction == T_MNEM_add)
9600 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9604 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9606 /* Thumb-1 cores (except v6-M) require at least one high
9607 register in a narrow non flag setting add. */
9608 if (Rd > 7 || Rn > 7
9609 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9610 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9617 inst.instruction = T_OPCODE_ADD_HI;
9618 inst.instruction |= (Rd & 8) << 4;
9619 inst.instruction |= (Rd & 7);
9620 inst.instruction |= Rn << 3;
9626 constraint (Rd == REG_PC, BAD_PC);
9627 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9628 constraint (Rs == REG_PC, BAD_PC);
9629 reject_bad_reg (Rn);
9631 /* If we get here, it can't be done in 16 bits. */
9632 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9633 _("shift must be constant"));
9634 inst.instruction = THUMB_OP32 (inst.instruction);
9635 inst.instruction |= Rd << 8;
9636 inst.instruction |= Rs << 16;
9637 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9638 _("shift value over 3 not allowed in thumb mode"));
9639 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9640 _("only LSL shift allowed in thumb mode"));
9641 encode_thumb32_shifted_operand (2);
9646 constraint (inst.instruction == T_MNEM_adds
9647 || inst.instruction == T_MNEM_subs,
9650 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9652 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9653 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9656 inst.instruction = (inst.instruction == T_MNEM_add
9658 inst.instruction |= (Rd << 4) | Rs;
9659 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9663 Rn = inst.operands[2].reg;
9664 constraint (inst.operands[2].shifted, _("unshifted register required"));
9666 /* We now have Rd, Rs, and Rn set to registers. */
9667 if (Rd > 7 || Rs > 7 || Rn > 7)
9669 /* Can't do this for SUB. */
9670 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9671 inst.instruction = T_OPCODE_ADD_HI;
9672 inst.instruction |= (Rd & 8) << 4;
9673 inst.instruction |= (Rd & 7);
9675 inst.instruction |= Rn << 3;
9677 inst.instruction |= Rs << 3;
9679 constraint (1, _("dest must overlap one source register"));
9683 inst.instruction = (inst.instruction == T_MNEM_add
9684 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9685 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9695 Rd = inst.operands[0].reg;
9696 reject_bad_reg (Rd);
9698 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9700 /* Defer to section relaxation. */
9701 inst.relax = inst.instruction;
9702 inst.instruction = THUMB_OP16 (inst.instruction);
9703 inst.instruction |= Rd << 4;
9705 else if (unified_syntax && inst.size_req != 2)
9707 /* Generate a 32-bit opcode. */
9708 inst.instruction = THUMB_OP32 (inst.instruction);
9709 inst.instruction |= Rd << 8;
9710 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9711 inst.reloc.pc_rel = 1;
9715 /* Generate a 16-bit opcode. */
9716 inst.instruction = THUMB_OP16 (inst.instruction);
9717 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9718 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9719 inst.reloc.pc_rel = 1;
9721 inst.instruction |= Rd << 4;
9725 /* Arithmetic instructions for which there is just one 16-bit
9726 instruction encoding, and it allows only two low registers.
9727 For maximal compatibility with ARM syntax, we allow three register
9728 operands even when Thumb-32 instructions are not available, as long
9729 as the first two are identical. For instance, both "sbc r0,r1" and
9730 "sbc r0,r0,r1" are allowed. */
9736 Rd = inst.operands[0].reg;
9737 Rs = (inst.operands[1].present
9738 ? inst.operands[1].reg /* Rd, Rs, foo */
9739 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9740 Rn = inst.operands[2].reg;
9742 reject_bad_reg (Rd);
9743 reject_bad_reg (Rs);
9744 if (inst.operands[2].isreg)
9745 reject_bad_reg (Rn);
9749 if (!inst.operands[2].isreg)
9751 /* For an immediate, we always generate a 32-bit opcode;
9752 section relaxation will shrink it later if possible. */
9753 inst.instruction = THUMB_OP32 (inst.instruction);
9754 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9755 inst.instruction |= Rd << 8;
9756 inst.instruction |= Rs << 16;
9757 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9763 /* See if we can do this with a 16-bit instruction. */
9764 if (THUMB_SETS_FLAGS (inst.instruction))
9765 narrow = !in_it_block ();
9767 narrow = in_it_block ();
9769 if (Rd > 7 || Rn > 7 || Rs > 7)
9771 if (inst.operands[2].shifted)
9773 if (inst.size_req == 4)
9779 inst.instruction = THUMB_OP16 (inst.instruction);
9780 inst.instruction |= Rd;
9781 inst.instruction |= Rn << 3;
9785 /* If we get here, it can't be done in 16 bits. */
9786 constraint (inst.operands[2].shifted
9787 && inst.operands[2].immisreg,
9788 _("shift must be constant"));
9789 inst.instruction = THUMB_OP32 (inst.instruction);
9790 inst.instruction |= Rd << 8;
9791 inst.instruction |= Rs << 16;
9792 encode_thumb32_shifted_operand (2);
9797 /* On its face this is a lie - the instruction does set the
9798 flags. However, the only supported mnemonic in this mode
9800 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9802 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9803 _("unshifted register required"));
9804 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9805 constraint (Rd != Rs,
9806 _("dest and source1 must be the same register"));
9808 inst.instruction = THUMB_OP16 (inst.instruction);
9809 inst.instruction |= Rd;
9810 inst.instruction |= Rn << 3;
9814 /* Similarly, but for instructions where the arithmetic operation is
9815 commutative, so we can allow either of them to be different from
9816 the destination operand in a 16-bit instruction. For instance, all
9817 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9824 Rd = inst.operands[0].reg;
9825 Rs = (inst.operands[1].present
9826 ? inst.operands[1].reg /* Rd, Rs, foo */
9827 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9828 Rn = inst.operands[2].reg;
9830 reject_bad_reg (Rd);
9831 reject_bad_reg (Rs);
9832 if (inst.operands[2].isreg)
9833 reject_bad_reg (Rn);
9837 if (!inst.operands[2].isreg)
9839 /* For an immediate, we always generate a 32-bit opcode;
9840 section relaxation will shrink it later if possible. */
9841 inst.instruction = THUMB_OP32 (inst.instruction);
9842 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9843 inst.instruction |= Rd << 8;
9844 inst.instruction |= Rs << 16;
9845 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9851 /* See if we can do this with a 16-bit instruction. */
9852 if (THUMB_SETS_FLAGS (inst.instruction))
9853 narrow = !in_it_block ();
9855 narrow = in_it_block ();
9857 if (Rd > 7 || Rn > 7 || Rs > 7)
9859 if (inst.operands[2].shifted)
9861 if (inst.size_req == 4)
9868 inst.instruction = THUMB_OP16 (inst.instruction);
9869 inst.instruction |= Rd;
9870 inst.instruction |= Rn << 3;
9875 inst.instruction = THUMB_OP16 (inst.instruction);
9876 inst.instruction |= Rd;
9877 inst.instruction |= Rs << 3;
9882 /* If we get here, it can't be done in 16 bits. */
9883 constraint (inst.operands[2].shifted
9884 && inst.operands[2].immisreg,
9885 _("shift must be constant"));
9886 inst.instruction = THUMB_OP32 (inst.instruction);
9887 inst.instruction |= Rd << 8;
9888 inst.instruction |= Rs << 16;
9889 encode_thumb32_shifted_operand (2);
9894 /* On its face this is a lie - the instruction does set the
9895 flags. However, the only supported mnemonic in this mode
9897 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9899 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9900 _("unshifted register required"));
9901 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9903 inst.instruction = THUMB_OP16 (inst.instruction);
9904 inst.instruction |= Rd;
9907 inst.instruction |= Rn << 3;
9909 inst.instruction |= Rs << 3;
9911 constraint (1, _("dest must overlap one source register"));
9918 if (inst.operands[0].present)
9920 constraint ((inst.instruction & 0xf0) != 0x40
9921 && inst.operands[0].imm > 0xf
9922 && inst.operands[0].imm < 0x0,
9923 _("bad barrier type"));
9924 inst.instruction |= inst.operands[0].imm;
9927 inst.instruction |= 0xf;
9934 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9935 constraint (msb > 32, _("bit-field extends past end of register"));
9936 /* The instruction encoding stores the LSB and MSB,
9937 not the LSB and width. */
9938 Rd = inst.operands[0].reg;
9939 reject_bad_reg (Rd);
9940 inst.instruction |= Rd << 8;
9941 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9942 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9943 inst.instruction |= msb - 1;
9952 Rd = inst.operands[0].reg;
9953 reject_bad_reg (Rd);
9955 /* #0 in second position is alternative syntax for bfc, which is
9956 the same instruction but with REG_PC in the Rm field. */
9957 if (!inst.operands[1].isreg)
9961 Rn = inst.operands[1].reg;
9962 reject_bad_reg (Rn);
9965 msb = inst.operands[2].imm + inst.operands[3].imm;
9966 constraint (msb > 32, _("bit-field extends past end of register"));
9967 /* The instruction encoding stores the LSB and MSB,
9968 not the LSB and width. */
9969 inst.instruction |= Rd << 8;
9970 inst.instruction |= Rn << 16;
9971 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9972 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9973 inst.instruction |= msb - 1;
9981 Rd = inst.operands[0].reg;
9982 Rn = inst.operands[1].reg;
9984 reject_bad_reg (Rd);
9985 reject_bad_reg (Rn);
9987 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9988 _("bit-field extends past end of register"));
9989 inst.instruction |= Rd << 8;
9990 inst.instruction |= Rn << 16;
9991 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9992 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9993 inst.instruction |= inst.operands[3].imm - 1;
9996 /* ARM V5 Thumb BLX (argument parse)
9997 BLX <target_addr> which is BLX(1)
9998 BLX <Rm> which is BLX(2)
9999 Unfortunately, there are two different opcodes for this mnemonic.
10000 So, the insns[].value is not used, and the code here zaps values
10001 into inst.instruction.
10003 ??? How to take advantage of the additional two bits of displacement
10004 available in Thumb32 mode? Need new relocation? */
10009 set_it_insn_type_last ();
10011 if (inst.operands[0].isreg)
10013 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10014 /* We have a register, so this is BLX(2). */
10015 inst.instruction |= inst.operands[0].reg << 3;
10019 /* No register. This must be BLX(1). */
10020 inst.instruction = 0xf000e800;
10021 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10033 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10035 if (in_it_block ())
10037 /* Conditional branches inside IT blocks are encoded as unconditional
10039 cond = COND_ALWAYS;
10044 if (cond != COND_ALWAYS)
10045 opcode = T_MNEM_bcond;
10047 opcode = inst.instruction;
10050 && (inst.size_req == 4
10051 || (inst.size_req != 2
10052 && (inst.operands[0].hasreloc
10053 || inst.reloc.exp.X_op == O_constant))))
10055 inst.instruction = THUMB_OP32(opcode);
10056 if (cond == COND_ALWAYS)
10057 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10060 gas_assert (cond != 0xF);
10061 inst.instruction |= cond << 22;
10062 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10067 inst.instruction = THUMB_OP16(opcode);
10068 if (cond == COND_ALWAYS)
10069 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10072 inst.instruction |= cond << 8;
10073 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10075 /* Allow section relaxation. */
10076 if (unified_syntax && inst.size_req != 2)
10077 inst.relax = opcode;
10079 inst.reloc.type = reloc;
10080 inst.reloc.pc_rel = 1;
10086 constraint (inst.cond != COND_ALWAYS,
10087 _("instruction is always unconditional"));
10088 if (inst.operands[0].present)
10090 constraint (inst.operands[0].imm > 255,
10091 _("immediate value out of range"));
10092 inst.instruction |= inst.operands[0].imm;
10093 set_it_insn_type (NEUTRAL_IT_INSN);
10098 do_t_branch23 (void)
10100 set_it_insn_type_last ();
10101 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10103 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10104 this file. We used to simply ignore the PLT reloc type here --
10105 the branch encoding is now needed to deal with TLSCALL relocs.
10106 So if we see a PLT reloc now, put it back to how it used to be to
10107 keep the preexisting behaviour. */
10108 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10109 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10111 #if defined(OBJ_COFF)
10112 /* If the destination of the branch is a defined symbol which does not have
10113 the THUMB_FUNC attribute, then we must be calling a function which has
10114 the (interfacearm) attribute. We look for the Thumb entry point to that
10115 function and change the branch to refer to that function instead. */
10116 if ( inst.reloc.exp.X_op == O_symbol
10117 && inst.reloc.exp.X_add_symbol != NULL
10118 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10119 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10120 inst.reloc.exp.X_add_symbol =
10121 find_real_start (inst.reloc.exp.X_add_symbol);
10128 set_it_insn_type_last ();
10129 inst.instruction |= inst.operands[0].reg << 3;
10130 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10131 should cause the alignment to be checked once it is known. This is
10132 because BX PC only works if the instruction is word aligned. */
10140 set_it_insn_type_last ();
10141 Rm = inst.operands[0].reg;
10142 reject_bad_reg (Rm);
10143 inst.instruction |= Rm << 16;
10152 Rd = inst.operands[0].reg;
10153 Rm = inst.operands[1].reg;
10155 reject_bad_reg (Rd);
10156 reject_bad_reg (Rm);
10158 inst.instruction |= Rd << 8;
10159 inst.instruction |= Rm << 16;
10160 inst.instruction |= Rm;
10166 set_it_insn_type (OUTSIDE_IT_INSN);
10167 inst.instruction |= inst.operands[0].imm;
10173 set_it_insn_type (OUTSIDE_IT_INSN);
10175 && (inst.operands[1].present || inst.size_req == 4)
10176 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10178 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10179 inst.instruction = 0xf3af8000;
10180 inst.instruction |= imod << 9;
10181 inst.instruction |= inst.operands[0].imm << 5;
10182 if (inst.operands[1].present)
10183 inst.instruction |= 0x100 | inst.operands[1].imm;
10187 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10188 && (inst.operands[0].imm & 4),
10189 _("selected processor does not support 'A' form "
10190 "of this instruction"));
10191 constraint (inst.operands[1].present || inst.size_req == 4,
10192 _("Thumb does not support the 2-argument "
10193 "form of this instruction"));
10194 inst.instruction |= inst.operands[0].imm;
10198 /* THUMB CPY instruction (argument parse). */
10203 if (inst.size_req == 4)
10205 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10206 inst.instruction |= inst.operands[0].reg << 8;
10207 inst.instruction |= inst.operands[1].reg;
10211 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10212 inst.instruction |= (inst.operands[0].reg & 0x7);
10213 inst.instruction |= inst.operands[1].reg << 3;
10220 set_it_insn_type (OUTSIDE_IT_INSN);
10221 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10222 inst.instruction |= inst.operands[0].reg;
10223 inst.reloc.pc_rel = 1;
10224 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10230 inst.instruction |= inst.operands[0].imm;
10236 unsigned Rd, Rn, Rm;
10238 Rd = inst.operands[0].reg;
10239 Rn = (inst.operands[1].present
10240 ? inst.operands[1].reg : Rd);
10241 Rm = inst.operands[2].reg;
10243 reject_bad_reg (Rd);
10244 reject_bad_reg (Rn);
10245 reject_bad_reg (Rm);
10247 inst.instruction |= Rd << 8;
10248 inst.instruction |= Rn << 16;
10249 inst.instruction |= Rm;
10255 if (unified_syntax && inst.size_req == 4)
10256 inst.instruction = THUMB_OP32 (inst.instruction);
10258 inst.instruction = THUMB_OP16 (inst.instruction);
10264 unsigned int cond = inst.operands[0].imm;
10266 set_it_insn_type (IT_INSN);
10267 now_it.mask = (inst.instruction & 0xf) | 0x10;
10270 /* If the condition is a negative condition, invert the mask. */
10271 if ((cond & 0x1) == 0x0)
10273 unsigned int mask = inst.instruction & 0x000f;
10275 if ((mask & 0x7) == 0)
10276 /* no conversion needed */;
10277 else if ((mask & 0x3) == 0)
10279 else if ((mask & 0x1) == 0)
10284 inst.instruction &= 0xfff0;
10285 inst.instruction |= mask;
10288 inst.instruction |= cond << 4;
10291 /* Helper function used for both push/pop and ldm/stm. */
10293 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10297 load = (inst.instruction & (1 << 20)) != 0;
10299 if (mask & (1 << 13))
10300 inst.error = _("SP not allowed in register list");
10302 if ((mask & (1 << base)) != 0
10304 inst.error = _("having the base register in the register list when "
10305 "using write back is UNPREDICTABLE");
10309 if (mask & (1 << 15))
10311 if (mask & (1 << 14))
10312 inst.error = _("LR and PC should not both be in register list");
10314 set_it_insn_type_last ();
10319 if (mask & (1 << 15))
10320 inst.error = _("PC not allowed in register list");
10323 if ((mask & (mask - 1)) == 0)
10325 /* Single register transfers implemented as str/ldr. */
10328 if (inst.instruction & (1 << 23))
10329 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10331 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10335 if (inst.instruction & (1 << 23))
10336 inst.instruction = 0x00800000; /* ia -> [base] */
10338 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10341 inst.instruction |= 0xf8400000;
10343 inst.instruction |= 0x00100000;
10345 mask = ffs (mask) - 1;
10348 else if (writeback)
10349 inst.instruction |= WRITE_BACK;
10351 inst.instruction |= mask;
10352 inst.instruction |= base << 16;
10358 /* This really doesn't seem worth it. */
10359 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10360 _("expression too complex"));
10361 constraint (inst.operands[1].writeback,
10362 _("Thumb load/store multiple does not support {reglist}^"));
10364 if (unified_syntax)
10366 bfd_boolean narrow;
10370 /* See if we can use a 16-bit instruction. */
10371 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10372 && inst.size_req != 4
10373 && !(inst.operands[1].imm & ~0xff))
10375 mask = 1 << inst.operands[0].reg;
10377 if (inst.operands[0].reg <= 7)
10379 if (inst.instruction == T_MNEM_stmia
10380 ? inst.operands[0].writeback
10381 : (inst.operands[0].writeback
10382 == !(inst.operands[1].imm & mask)))
10384 if (inst.instruction == T_MNEM_stmia
10385 && (inst.operands[1].imm & mask)
10386 && (inst.operands[1].imm & (mask - 1)))
10387 as_warn (_("value stored for r%d is UNKNOWN"),
10388 inst.operands[0].reg);
10390 inst.instruction = THUMB_OP16 (inst.instruction);
10391 inst.instruction |= inst.operands[0].reg << 8;
10392 inst.instruction |= inst.operands[1].imm;
10395 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10397 /* This means 1 register in reg list one of 3 situations:
10398 1. Instruction is stmia, but without writeback.
10399 2. lmdia without writeback, but with Rn not in
10401 3. ldmia with writeback, but with Rn in reglist.
10402 Case 3 is UNPREDICTABLE behaviour, so we handle
10403 case 1 and 2 which can be converted into a 16-bit
10404 str or ldr. The SP cases are handled below. */
10405 unsigned long opcode;
10406 /* First, record an error for Case 3. */
10407 if (inst.operands[1].imm & mask
10408 && inst.operands[0].writeback)
10410 _("having the base register in the register list when "
10411 "using write back is UNPREDICTABLE");
10413 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10415 inst.instruction = THUMB_OP16 (opcode);
10416 inst.instruction |= inst.operands[0].reg << 3;
10417 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10421 else if (inst.operands[0] .reg == REG_SP)
10423 if (inst.operands[0].writeback)
10426 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10427 ? T_MNEM_push : T_MNEM_pop);
10428 inst.instruction |= inst.operands[1].imm;
10431 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10434 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10435 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10436 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10444 if (inst.instruction < 0xffff)
10445 inst.instruction = THUMB_OP32 (inst.instruction);
10447 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10448 inst.operands[0].writeback);
10453 constraint (inst.operands[0].reg > 7
10454 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10455 constraint (inst.instruction != T_MNEM_ldmia
10456 && inst.instruction != T_MNEM_stmia,
10457 _("Thumb-2 instruction only valid in unified syntax"));
10458 if (inst.instruction == T_MNEM_stmia)
10460 if (!inst.operands[0].writeback)
10461 as_warn (_("this instruction will write back the base register"));
10462 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10463 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10464 as_warn (_("value stored for r%d is UNKNOWN"),
10465 inst.operands[0].reg);
10469 if (!inst.operands[0].writeback
10470 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10471 as_warn (_("this instruction will write back the base register"));
10472 else if (inst.operands[0].writeback
10473 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10474 as_warn (_("this instruction will not write back the base register"));
10477 inst.instruction = THUMB_OP16 (inst.instruction);
10478 inst.instruction |= inst.operands[0].reg << 8;
10479 inst.instruction |= inst.operands[1].imm;
10486 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10487 || inst.operands[1].postind || inst.operands[1].writeback
10488 || inst.operands[1].immisreg || inst.operands[1].shifted
10489 || inst.operands[1].negative,
10492 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10494 inst.instruction |= inst.operands[0].reg << 12;
10495 inst.instruction |= inst.operands[1].reg << 16;
10496 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10502 if (!inst.operands[1].present)
10504 constraint (inst.operands[0].reg == REG_LR,
10505 _("r14 not allowed as first register "
10506 "when second register is omitted"));
10507 inst.operands[1].reg = inst.operands[0].reg + 1;
10509 constraint (inst.operands[0].reg == inst.operands[1].reg,
10512 inst.instruction |= inst.operands[0].reg << 12;
10513 inst.instruction |= inst.operands[1].reg << 8;
10514 inst.instruction |= inst.operands[2].reg << 16;
10520 unsigned long opcode;
10523 if (inst.operands[0].isreg
10524 && !inst.operands[0].preind
10525 && inst.operands[0].reg == REG_PC)
10526 set_it_insn_type_last ();
10528 opcode = inst.instruction;
10529 if (unified_syntax)
10531 if (!inst.operands[1].isreg)
10533 if (opcode <= 0xffff)
10534 inst.instruction = THUMB_OP32 (opcode);
10535 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10538 if (inst.operands[1].isreg
10539 && !inst.operands[1].writeback
10540 && !inst.operands[1].shifted && !inst.operands[1].postind
10541 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10542 && opcode <= 0xffff
10543 && inst.size_req != 4)
10545 /* Insn may have a 16-bit form. */
10546 Rn = inst.operands[1].reg;
10547 if (inst.operands[1].immisreg)
10549 inst.instruction = THUMB_OP16 (opcode);
10551 if (Rn <= 7 && inst.operands[1].imm <= 7)
10553 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10554 reject_bad_reg (inst.operands[1].imm);
10556 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10557 && opcode != T_MNEM_ldrsb)
10558 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10559 || (Rn == REG_SP && opcode == T_MNEM_str))
10566 if (inst.reloc.pc_rel)
10567 opcode = T_MNEM_ldr_pc2;
10569 opcode = T_MNEM_ldr_pc;
10573 if (opcode == T_MNEM_ldr)
10574 opcode = T_MNEM_ldr_sp;
10576 opcode = T_MNEM_str_sp;
10578 inst.instruction = inst.operands[0].reg << 8;
10582 inst.instruction = inst.operands[0].reg;
10583 inst.instruction |= inst.operands[1].reg << 3;
10585 inst.instruction |= THUMB_OP16 (opcode);
10586 if (inst.size_req == 2)
10587 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10589 inst.relax = opcode;
10593 /* Definitely a 32-bit variant. */
10595 /* Warning for Erratum 752419. */
10596 if (opcode == T_MNEM_ldr
10597 && inst.operands[0].reg == REG_SP
10598 && inst.operands[1].writeback == 1
10599 && !inst.operands[1].immisreg)
10601 if (no_cpu_selected ()
10602 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10603 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10604 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10605 as_warn (_("This instruction may be unpredictable "
10606 "if executed on M-profile cores "
10607 "with interrupts enabled."));
10610 /* Do some validations regarding addressing modes. */
10611 if (inst.operands[1].immisreg)
10612 reject_bad_reg (inst.operands[1].imm);
10614 constraint (inst.operands[1].writeback == 1
10615 && inst.operands[0].reg == inst.operands[1].reg,
10618 inst.instruction = THUMB_OP32 (opcode);
10619 inst.instruction |= inst.operands[0].reg << 12;
10620 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10621 check_ldr_r15_aligned ();
10625 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10627 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10629 /* Only [Rn,Rm] is acceptable. */
10630 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10631 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10632 || inst.operands[1].postind || inst.operands[1].shifted
10633 || inst.operands[1].negative,
10634 _("Thumb does not support this addressing mode"));
10635 inst.instruction = THUMB_OP16 (inst.instruction);
10639 inst.instruction = THUMB_OP16 (inst.instruction);
10640 if (!inst.operands[1].isreg)
10641 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10644 constraint (!inst.operands[1].preind
10645 || inst.operands[1].shifted
10646 || inst.operands[1].writeback,
10647 _("Thumb does not support this addressing mode"));
10648 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10650 constraint (inst.instruction & 0x0600,
10651 _("byte or halfword not valid for base register"));
10652 constraint (inst.operands[1].reg == REG_PC
10653 && !(inst.instruction & THUMB_LOAD_BIT),
10654 _("r15 based store not allowed"));
10655 constraint (inst.operands[1].immisreg,
10656 _("invalid base register for register offset"));
10658 if (inst.operands[1].reg == REG_PC)
10659 inst.instruction = T_OPCODE_LDR_PC;
10660 else if (inst.instruction & THUMB_LOAD_BIT)
10661 inst.instruction = T_OPCODE_LDR_SP;
10663 inst.instruction = T_OPCODE_STR_SP;
10665 inst.instruction |= inst.operands[0].reg << 8;
10666 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10670 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10671 if (!inst.operands[1].immisreg)
10673 /* Immediate offset. */
10674 inst.instruction |= inst.operands[0].reg;
10675 inst.instruction |= inst.operands[1].reg << 3;
10676 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10680 /* Register offset. */
10681 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10682 constraint (inst.operands[1].negative,
10683 _("Thumb does not support this addressing mode"));
10686 switch (inst.instruction)
10688 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10689 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10690 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10691 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10692 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10693 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10694 case 0x5600 /* ldrsb */:
10695 case 0x5e00 /* ldrsh */: break;
10699 inst.instruction |= inst.operands[0].reg;
10700 inst.instruction |= inst.operands[1].reg << 3;
10701 inst.instruction |= inst.operands[1].imm << 6;
10707 if (!inst.operands[1].present)
10709 inst.operands[1].reg = inst.operands[0].reg + 1;
10710 constraint (inst.operands[0].reg == REG_LR,
10711 _("r14 not allowed here"));
10712 constraint (inst.operands[0].reg == REG_R12,
10713 _("r12 not allowed here"));
10716 if (inst.operands[2].writeback
10717 && (inst.operands[0].reg == inst.operands[2].reg
10718 || inst.operands[1].reg == inst.operands[2].reg))
10719 as_warn (_("base register written back, and overlaps "
10720 "one of transfer registers"));
10722 inst.instruction |= inst.operands[0].reg << 12;
10723 inst.instruction |= inst.operands[1].reg << 8;
10724 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10730 inst.instruction |= inst.operands[0].reg << 12;
10731 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10737 unsigned Rd, Rn, Rm, Ra;
10739 Rd = inst.operands[0].reg;
10740 Rn = inst.operands[1].reg;
10741 Rm = inst.operands[2].reg;
10742 Ra = inst.operands[3].reg;
10744 reject_bad_reg (Rd);
10745 reject_bad_reg (Rn);
10746 reject_bad_reg (Rm);
10747 reject_bad_reg (Ra);
10749 inst.instruction |= Rd << 8;
10750 inst.instruction |= Rn << 16;
10751 inst.instruction |= Rm;
10752 inst.instruction |= Ra << 12;
10758 unsigned RdLo, RdHi, Rn, Rm;
10760 RdLo = inst.operands[0].reg;
10761 RdHi = inst.operands[1].reg;
10762 Rn = inst.operands[2].reg;
10763 Rm = inst.operands[3].reg;
10765 reject_bad_reg (RdLo);
10766 reject_bad_reg (RdHi);
10767 reject_bad_reg (Rn);
10768 reject_bad_reg (Rm);
10770 inst.instruction |= RdLo << 12;
10771 inst.instruction |= RdHi << 8;
10772 inst.instruction |= Rn << 16;
10773 inst.instruction |= Rm;
10777 do_t_mov_cmp (void)
10781 Rn = inst.operands[0].reg;
10782 Rm = inst.operands[1].reg;
10785 set_it_insn_type_last ();
10787 if (unified_syntax)
10789 int r0off = (inst.instruction == T_MNEM_mov
10790 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10791 unsigned long opcode;
10792 bfd_boolean narrow;
10793 bfd_boolean low_regs;
10795 low_regs = (Rn <= 7 && Rm <= 7);
10796 opcode = inst.instruction;
10797 if (in_it_block ())
10798 narrow = opcode != T_MNEM_movs;
10800 narrow = opcode != T_MNEM_movs || low_regs;
10801 if (inst.size_req == 4
10802 || inst.operands[1].shifted)
10805 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10806 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10807 && !inst.operands[1].shifted
10811 inst.instruction = T2_SUBS_PC_LR;
10815 if (opcode == T_MNEM_cmp)
10817 constraint (Rn == REG_PC, BAD_PC);
10820 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10822 warn_deprecated_sp (Rm);
10823 /* R15 was documented as a valid choice for Rm in ARMv6,
10824 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10825 tools reject R15, so we do too. */
10826 constraint (Rm == REG_PC, BAD_PC);
10829 reject_bad_reg (Rm);
10831 else if (opcode == T_MNEM_mov
10832 || opcode == T_MNEM_movs)
10834 if (inst.operands[1].isreg)
10836 if (opcode == T_MNEM_movs)
10838 reject_bad_reg (Rn);
10839 reject_bad_reg (Rm);
10843 /* This is mov.n. */
10844 if ((Rn == REG_SP || Rn == REG_PC)
10845 && (Rm == REG_SP || Rm == REG_PC))
10847 as_warn (_("Use of r%u as a source register is "
10848 "deprecated when r%u is the destination "
10849 "register."), Rm, Rn);
10854 /* This is mov.w. */
10855 constraint (Rn == REG_PC, BAD_PC);
10856 constraint (Rm == REG_PC, BAD_PC);
10857 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10861 reject_bad_reg (Rn);
10864 if (!inst.operands[1].isreg)
10866 /* Immediate operand. */
10867 if (!in_it_block () && opcode == T_MNEM_mov)
10869 if (low_regs && narrow)
10871 inst.instruction = THUMB_OP16 (opcode);
10872 inst.instruction |= Rn << 8;
10873 if (inst.size_req == 2)
10874 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10876 inst.relax = opcode;
10880 inst.instruction = THUMB_OP32 (inst.instruction);
10881 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10882 inst.instruction |= Rn << r0off;
10883 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10886 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10887 && (inst.instruction == T_MNEM_mov
10888 || inst.instruction == T_MNEM_movs))
10890 /* Register shifts are encoded as separate shift instructions. */
10891 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10893 if (in_it_block ())
10898 if (inst.size_req == 4)
10901 if (!low_regs || inst.operands[1].imm > 7)
10907 switch (inst.operands[1].shift_kind)
10910 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10913 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10916 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10919 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10925 inst.instruction = opcode;
10928 inst.instruction |= Rn;
10929 inst.instruction |= inst.operands[1].imm << 3;
10934 inst.instruction |= CONDS_BIT;
10936 inst.instruction |= Rn << 8;
10937 inst.instruction |= Rm << 16;
10938 inst.instruction |= inst.operands[1].imm;
10943 /* Some mov with immediate shift have narrow variants.
10944 Register shifts are handled above. */
10945 if (low_regs && inst.operands[1].shifted
10946 && (inst.instruction == T_MNEM_mov
10947 || inst.instruction == T_MNEM_movs))
10949 if (in_it_block ())
10950 narrow = (inst.instruction == T_MNEM_mov);
10952 narrow = (inst.instruction == T_MNEM_movs);
10957 switch (inst.operands[1].shift_kind)
10959 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10960 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10961 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10962 default: narrow = FALSE; break;
10968 inst.instruction |= Rn;
10969 inst.instruction |= Rm << 3;
10970 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10974 inst.instruction = THUMB_OP32 (inst.instruction);
10975 inst.instruction |= Rn << r0off;
10976 encode_thumb32_shifted_operand (1);
10980 switch (inst.instruction)
10983 /* In v4t or v5t a move of two lowregs produces unpredictable
10984 results. Don't allow this. */
10987 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
10988 "MOV Rd, Rs with two low registers is not "
10989 "permitted on this architecture");
10990 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
10994 inst.instruction = T_OPCODE_MOV_HR;
10995 inst.instruction |= (Rn & 0x8) << 4;
10996 inst.instruction |= (Rn & 0x7);
10997 inst.instruction |= Rm << 3;
11001 /* We know we have low registers at this point.
11002 Generate LSLS Rd, Rs, #0. */
11003 inst.instruction = T_OPCODE_LSL_I;
11004 inst.instruction |= Rn;
11005 inst.instruction |= Rm << 3;
11011 inst.instruction = T_OPCODE_CMP_LR;
11012 inst.instruction |= Rn;
11013 inst.instruction |= Rm << 3;
11017 inst.instruction = T_OPCODE_CMP_HR;
11018 inst.instruction |= (Rn & 0x8) << 4;
11019 inst.instruction |= (Rn & 0x7);
11020 inst.instruction |= Rm << 3;
11027 inst.instruction = THUMB_OP16 (inst.instruction);
11029 /* PR 10443: Do not silently ignore shifted operands. */
11030 constraint (inst.operands[1].shifted,
11031 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11033 if (inst.operands[1].isreg)
11035 if (Rn < 8 && Rm < 8)
11037 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11038 since a MOV instruction produces unpredictable results. */
11039 if (inst.instruction == T_OPCODE_MOV_I8)
11040 inst.instruction = T_OPCODE_ADD_I3;
11042 inst.instruction = T_OPCODE_CMP_LR;
11044 inst.instruction |= Rn;
11045 inst.instruction |= Rm << 3;
11049 if (inst.instruction == T_OPCODE_MOV_I8)
11050 inst.instruction = T_OPCODE_MOV_HR;
11052 inst.instruction = T_OPCODE_CMP_HR;
11058 constraint (Rn > 7,
11059 _("only lo regs allowed with immediate"));
11060 inst.instruction |= Rn << 8;
11061 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11072 top = (inst.instruction & 0x00800000) != 0;
11073 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11075 constraint (top, _(":lower16: not allowed this instruction"));
11076 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11078 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11080 constraint (!top, _(":upper16: not allowed this instruction"));
11081 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11084 Rd = inst.operands[0].reg;
11085 reject_bad_reg (Rd);
11087 inst.instruction |= Rd << 8;
11088 if (inst.reloc.type == BFD_RELOC_UNUSED)
11090 imm = inst.reloc.exp.X_add_number;
11091 inst.instruction |= (imm & 0xf000) << 4;
11092 inst.instruction |= (imm & 0x0800) << 15;
11093 inst.instruction |= (imm & 0x0700) << 4;
11094 inst.instruction |= (imm & 0x00ff);
11099 do_t_mvn_tst (void)
11103 Rn = inst.operands[0].reg;
11104 Rm = inst.operands[1].reg;
11106 if (inst.instruction == T_MNEM_cmp
11107 || inst.instruction == T_MNEM_cmn)
11108 constraint (Rn == REG_PC, BAD_PC);
11110 reject_bad_reg (Rn);
11111 reject_bad_reg (Rm);
11113 if (unified_syntax)
11115 int r0off = (inst.instruction == T_MNEM_mvn
11116 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11117 bfd_boolean narrow;
11119 if (inst.size_req == 4
11120 || inst.instruction > 0xffff
11121 || inst.operands[1].shifted
11122 || Rn > 7 || Rm > 7)
11124 else if (inst.instruction == T_MNEM_cmn)
11126 else if (THUMB_SETS_FLAGS (inst.instruction))
11127 narrow = !in_it_block ();
11129 narrow = in_it_block ();
11131 if (!inst.operands[1].isreg)
11133 /* For an immediate, we always generate a 32-bit opcode;
11134 section relaxation will shrink it later if possible. */
11135 if (inst.instruction < 0xffff)
11136 inst.instruction = THUMB_OP32 (inst.instruction);
11137 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11138 inst.instruction |= Rn << r0off;
11139 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11143 /* See if we can do this with a 16-bit instruction. */
11146 inst.instruction = THUMB_OP16 (inst.instruction);
11147 inst.instruction |= Rn;
11148 inst.instruction |= Rm << 3;
11152 constraint (inst.operands[1].shifted
11153 && inst.operands[1].immisreg,
11154 _("shift must be constant"));
11155 if (inst.instruction < 0xffff)
11156 inst.instruction = THUMB_OP32 (inst.instruction);
11157 inst.instruction |= Rn << r0off;
11158 encode_thumb32_shifted_operand (1);
11164 constraint (inst.instruction > 0xffff
11165 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11166 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11167 _("unshifted register required"));
11168 constraint (Rn > 7 || Rm > 7,
11171 inst.instruction = THUMB_OP16 (inst.instruction);
11172 inst.instruction |= Rn;
11173 inst.instruction |= Rm << 3;
11182 if (do_vfp_nsyn_mrs () == SUCCESS)
11185 Rd = inst.operands[0].reg;
11186 reject_bad_reg (Rd);
11187 inst.instruction |= Rd << 8;
11189 if (inst.operands[1].isreg)
11191 unsigned br = inst.operands[1].reg;
11192 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11193 as_bad (_("bad register for mrs"));
11195 inst.instruction |= br & (0xf << 16);
11196 inst.instruction |= (br & 0x300) >> 4;
11197 inst.instruction |= (br & SPSR_BIT) >> 2;
11201 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11203 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11205 /* PR gas/12698: The constraint is only applied for m_profile.
11206 If the user has specified -march=all, we want to ignore it as
11207 we are building for any CPU type, including non-m variants. */
11208 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11209 constraint ((flags != 0) && m_profile, _("selected processor does "
11210 "not support requested special purpose register"));
11213 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11215 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11216 _("'APSR', 'CPSR' or 'SPSR' expected"));
11218 inst.instruction |= (flags & SPSR_BIT) >> 2;
11219 inst.instruction |= inst.operands[1].imm & 0xff;
11220 inst.instruction |= 0xf0000;
11230 if (do_vfp_nsyn_msr () == SUCCESS)
11233 constraint (!inst.operands[1].isreg,
11234 _("Thumb encoding does not support an immediate here"));
11236 if (inst.operands[0].isreg)
11237 flags = (int)(inst.operands[0].reg);
11239 flags = inst.operands[0].imm;
11241 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11243 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11245 /* PR gas/12698: The constraint is only applied for m_profile.
11246 If the user has specified -march=all, we want to ignore it as
11247 we are building for any CPU type, including non-m variants. */
11248 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11249 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11250 && (bits & ~(PSR_s | PSR_f)) != 0)
11251 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11252 && bits != PSR_f)) && m_profile,
11253 _("selected processor does not support requested special "
11254 "purpose register"));
11257 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11258 "requested special purpose register"));
11260 Rn = inst.operands[1].reg;
11261 reject_bad_reg (Rn);
11263 inst.instruction |= (flags & SPSR_BIT) >> 2;
11264 inst.instruction |= (flags & 0xf0000) >> 8;
11265 inst.instruction |= (flags & 0x300) >> 4;
11266 inst.instruction |= (flags & 0xff);
11267 inst.instruction |= Rn << 16;
11273 bfd_boolean narrow;
11274 unsigned Rd, Rn, Rm;
11276 if (!inst.operands[2].present)
11277 inst.operands[2].reg = inst.operands[0].reg;
11279 Rd = inst.operands[0].reg;
11280 Rn = inst.operands[1].reg;
11281 Rm = inst.operands[2].reg;
11283 if (unified_syntax)
11285 if (inst.size_req == 4
11291 else if (inst.instruction == T_MNEM_muls)
11292 narrow = !in_it_block ();
11294 narrow = in_it_block ();
11298 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11299 constraint (Rn > 7 || Rm > 7,
11306 /* 16-bit MULS/Conditional MUL. */
11307 inst.instruction = THUMB_OP16 (inst.instruction);
11308 inst.instruction |= Rd;
11311 inst.instruction |= Rm << 3;
11313 inst.instruction |= Rn << 3;
11315 constraint (1, _("dest must overlap one source register"));
11319 constraint (inst.instruction != T_MNEM_mul,
11320 _("Thumb-2 MUL must not set flags"));
11322 inst.instruction = THUMB_OP32 (inst.instruction);
11323 inst.instruction |= Rd << 8;
11324 inst.instruction |= Rn << 16;
11325 inst.instruction |= Rm << 0;
11327 reject_bad_reg (Rd);
11328 reject_bad_reg (Rn);
11329 reject_bad_reg (Rm);
11336 unsigned RdLo, RdHi, Rn, Rm;
11338 RdLo = inst.operands[0].reg;
11339 RdHi = inst.operands[1].reg;
11340 Rn = inst.operands[2].reg;
11341 Rm = inst.operands[3].reg;
11343 reject_bad_reg (RdLo);
11344 reject_bad_reg (RdHi);
11345 reject_bad_reg (Rn);
11346 reject_bad_reg (Rm);
11348 inst.instruction |= RdLo << 12;
11349 inst.instruction |= RdHi << 8;
11350 inst.instruction |= Rn << 16;
11351 inst.instruction |= Rm;
11354 as_tsktsk (_("rdhi and rdlo must be different"));
11360 set_it_insn_type (NEUTRAL_IT_INSN);
11362 if (unified_syntax)
11364 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11366 inst.instruction = THUMB_OP32 (inst.instruction);
11367 inst.instruction |= inst.operands[0].imm;
11371 /* PR9722: Check for Thumb2 availability before
11372 generating a thumb2 nop instruction. */
11373 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11375 inst.instruction = THUMB_OP16 (inst.instruction);
11376 inst.instruction |= inst.operands[0].imm << 4;
11379 inst.instruction = 0x46c0;
11384 constraint (inst.operands[0].present,
11385 _("Thumb does not support NOP with hints"));
11386 inst.instruction = 0x46c0;
11393 if (unified_syntax)
11395 bfd_boolean narrow;
11397 if (THUMB_SETS_FLAGS (inst.instruction))
11398 narrow = !in_it_block ();
11400 narrow = in_it_block ();
11401 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11403 if (inst.size_req == 4)
11408 inst.instruction = THUMB_OP32 (inst.instruction);
11409 inst.instruction |= inst.operands[0].reg << 8;
11410 inst.instruction |= inst.operands[1].reg << 16;
11414 inst.instruction = THUMB_OP16 (inst.instruction);
11415 inst.instruction |= inst.operands[0].reg;
11416 inst.instruction |= inst.operands[1].reg << 3;
11421 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11423 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11425 inst.instruction = THUMB_OP16 (inst.instruction);
11426 inst.instruction |= inst.operands[0].reg;
11427 inst.instruction |= inst.operands[1].reg << 3;
11436 Rd = inst.operands[0].reg;
11437 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11439 reject_bad_reg (Rd);
11440 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11441 reject_bad_reg (Rn);
11443 inst.instruction |= Rd << 8;
11444 inst.instruction |= Rn << 16;
11446 if (!inst.operands[2].isreg)
11448 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11449 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11455 Rm = inst.operands[2].reg;
11456 reject_bad_reg (Rm);
11458 constraint (inst.operands[2].shifted
11459 && inst.operands[2].immisreg,
11460 _("shift must be constant"));
11461 encode_thumb32_shifted_operand (2);
11468 unsigned Rd, Rn, Rm;
11470 Rd = inst.operands[0].reg;
11471 Rn = inst.operands[1].reg;
11472 Rm = inst.operands[2].reg;
11474 reject_bad_reg (Rd);
11475 reject_bad_reg (Rn);
11476 reject_bad_reg (Rm);
11478 inst.instruction |= Rd << 8;
11479 inst.instruction |= Rn << 16;
11480 inst.instruction |= Rm;
11481 if (inst.operands[3].present)
11483 unsigned int val = inst.reloc.exp.X_add_number;
11484 constraint (inst.reloc.exp.X_op != O_constant,
11485 _("expression too complex"));
11486 inst.instruction |= (val & 0x1c) << 10;
11487 inst.instruction |= (val & 0x03) << 6;
11494 if (!inst.operands[3].present)
11498 inst.instruction &= ~0x00000020;
11500 /* PR 10168. Swap the Rm and Rn registers. */
11501 Rtmp = inst.operands[1].reg;
11502 inst.operands[1].reg = inst.operands[2].reg;
11503 inst.operands[2].reg = Rtmp;
11511 if (inst.operands[0].immisreg)
11512 reject_bad_reg (inst.operands[0].imm);
11514 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11518 do_t_push_pop (void)
11522 constraint (inst.operands[0].writeback,
11523 _("push/pop do not support {reglist}^"));
11524 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11525 _("expression too complex"));
11527 mask = inst.operands[0].imm;
11528 if ((mask & ~0xff) == 0)
11529 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11530 else if ((inst.instruction == T_MNEM_push
11531 && (mask & ~0xff) == 1 << REG_LR)
11532 || (inst.instruction == T_MNEM_pop
11533 && (mask & ~0xff) == 1 << REG_PC))
11535 inst.instruction = THUMB_OP16 (inst.instruction);
11536 inst.instruction |= THUMB_PP_PC_LR;
11537 inst.instruction |= mask & 0xff;
11539 else if (unified_syntax)
11541 inst.instruction = THUMB_OP32 (inst.instruction);
11542 encode_thumb2_ldmstm (13, mask, TRUE);
11546 inst.error = _("invalid register list to push/pop instruction");
11556 Rd = inst.operands[0].reg;
11557 Rm = inst.operands[1].reg;
11559 reject_bad_reg (Rd);
11560 reject_bad_reg (Rm);
11562 inst.instruction |= Rd << 8;
11563 inst.instruction |= Rm << 16;
11564 inst.instruction |= Rm;
11572 Rd = inst.operands[0].reg;
11573 Rm = inst.operands[1].reg;
11575 reject_bad_reg (Rd);
11576 reject_bad_reg (Rm);
11578 if (Rd <= 7 && Rm <= 7
11579 && inst.size_req != 4)
11581 inst.instruction = THUMB_OP16 (inst.instruction);
11582 inst.instruction |= Rd;
11583 inst.instruction |= Rm << 3;
11585 else if (unified_syntax)
11587 inst.instruction = THUMB_OP32 (inst.instruction);
11588 inst.instruction |= Rd << 8;
11589 inst.instruction |= Rm << 16;
11590 inst.instruction |= Rm;
11593 inst.error = BAD_HIREG;
11601 Rd = inst.operands[0].reg;
11602 Rm = inst.operands[1].reg;
11604 reject_bad_reg (Rd);
11605 reject_bad_reg (Rm);
11607 inst.instruction |= Rd << 8;
11608 inst.instruction |= Rm;
11616 Rd = inst.operands[0].reg;
11617 Rs = (inst.operands[1].present
11618 ? inst.operands[1].reg /* Rd, Rs, foo */
11619 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11621 reject_bad_reg (Rd);
11622 reject_bad_reg (Rs);
11623 if (inst.operands[2].isreg)
11624 reject_bad_reg (inst.operands[2].reg);
11626 inst.instruction |= Rd << 8;
11627 inst.instruction |= Rs << 16;
11628 if (!inst.operands[2].isreg)
11630 bfd_boolean narrow;
11632 if ((inst.instruction & 0x00100000) != 0)
11633 narrow = !in_it_block ();
11635 narrow = in_it_block ();
11637 if (Rd > 7 || Rs > 7)
11640 if (inst.size_req == 4 || !unified_syntax)
11643 if (inst.reloc.exp.X_op != O_constant
11644 || inst.reloc.exp.X_add_number != 0)
11647 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11648 relaxation, but it doesn't seem worth the hassle. */
11651 inst.reloc.type = BFD_RELOC_UNUSED;
11652 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11653 inst.instruction |= Rs << 3;
11654 inst.instruction |= Rd;
11658 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11659 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11663 encode_thumb32_shifted_operand (2);
11669 set_it_insn_type (OUTSIDE_IT_INSN);
11670 if (inst.operands[0].imm)
11671 inst.instruction |= 0x8;
11677 if (!inst.operands[1].present)
11678 inst.operands[1].reg = inst.operands[0].reg;
11680 if (unified_syntax)
11682 bfd_boolean narrow;
11685 switch (inst.instruction)
11688 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11690 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11692 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11694 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11698 if (THUMB_SETS_FLAGS (inst.instruction))
11699 narrow = !in_it_block ();
11701 narrow = in_it_block ();
11702 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11704 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11706 if (inst.operands[2].isreg
11707 && (inst.operands[1].reg != inst.operands[0].reg
11708 || inst.operands[2].reg > 7))
11710 if (inst.size_req == 4)
11713 reject_bad_reg (inst.operands[0].reg);
11714 reject_bad_reg (inst.operands[1].reg);
11718 if (inst.operands[2].isreg)
11720 reject_bad_reg (inst.operands[2].reg);
11721 inst.instruction = THUMB_OP32 (inst.instruction);
11722 inst.instruction |= inst.operands[0].reg << 8;
11723 inst.instruction |= inst.operands[1].reg << 16;
11724 inst.instruction |= inst.operands[2].reg;
11726 /* PR 12854: Error on extraneous shifts. */
11727 constraint (inst.operands[2].shifted,
11728 _("extraneous shift as part of operand to shift insn"));
11732 inst.operands[1].shifted = 1;
11733 inst.operands[1].shift_kind = shift_kind;
11734 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11735 ? T_MNEM_movs : T_MNEM_mov);
11736 inst.instruction |= inst.operands[0].reg << 8;
11737 encode_thumb32_shifted_operand (1);
11738 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11739 inst.reloc.type = BFD_RELOC_UNUSED;
11744 if (inst.operands[2].isreg)
11746 switch (shift_kind)
11748 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11749 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11750 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11751 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11755 inst.instruction |= inst.operands[0].reg;
11756 inst.instruction |= inst.operands[2].reg << 3;
11758 /* PR 12854: Error on extraneous shifts. */
11759 constraint (inst.operands[2].shifted,
11760 _("extraneous shift as part of operand to shift insn"));
11764 switch (shift_kind)
11766 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11767 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11768 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11771 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11772 inst.instruction |= inst.operands[0].reg;
11773 inst.instruction |= inst.operands[1].reg << 3;
11779 constraint (inst.operands[0].reg > 7
11780 || inst.operands[1].reg > 7, BAD_HIREG);
11781 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11783 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11785 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11786 constraint (inst.operands[0].reg != inst.operands[1].reg,
11787 _("source1 and dest must be same register"));
11789 switch (inst.instruction)
11791 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11792 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11793 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11794 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11798 inst.instruction |= inst.operands[0].reg;
11799 inst.instruction |= inst.operands[2].reg << 3;
11801 /* PR 12854: Error on extraneous shifts. */
11802 constraint (inst.operands[2].shifted,
11803 _("extraneous shift as part of operand to shift insn"));
11807 switch (inst.instruction)
11809 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11810 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11811 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11812 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11815 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11816 inst.instruction |= inst.operands[0].reg;
11817 inst.instruction |= inst.operands[1].reg << 3;
11825 unsigned Rd, Rn, Rm;
11827 Rd = inst.operands[0].reg;
11828 Rn = inst.operands[1].reg;
11829 Rm = inst.operands[2].reg;
11831 reject_bad_reg (Rd);
11832 reject_bad_reg (Rn);
11833 reject_bad_reg (Rm);
11835 inst.instruction |= Rd << 8;
11836 inst.instruction |= Rn << 16;
11837 inst.instruction |= Rm;
11843 unsigned Rd, Rn, Rm;
11845 Rd = inst.operands[0].reg;
11846 Rm = inst.operands[1].reg;
11847 Rn = inst.operands[2].reg;
11849 reject_bad_reg (Rd);
11850 reject_bad_reg (Rn);
11851 reject_bad_reg (Rm);
11853 inst.instruction |= Rd << 8;
11854 inst.instruction |= Rn << 16;
11855 inst.instruction |= Rm;
11861 unsigned int value = inst.reloc.exp.X_add_number;
11862 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11863 _("SMC is not permitted on this architecture"));
11864 constraint (inst.reloc.exp.X_op != O_constant,
11865 _("expression too complex"));
11866 inst.reloc.type = BFD_RELOC_UNUSED;
11867 inst.instruction |= (value & 0xf000) >> 12;
11868 inst.instruction |= (value & 0x0ff0);
11869 inst.instruction |= (value & 0x000f) << 16;
11875 unsigned int value = inst.reloc.exp.X_add_number;
11877 inst.reloc.type = BFD_RELOC_UNUSED;
11878 inst.instruction |= (value & 0x0fff);
11879 inst.instruction |= (value & 0xf000) << 4;
11883 do_t_ssat_usat (int bias)
11887 Rd = inst.operands[0].reg;
11888 Rn = inst.operands[2].reg;
11890 reject_bad_reg (Rd);
11891 reject_bad_reg (Rn);
11893 inst.instruction |= Rd << 8;
11894 inst.instruction |= inst.operands[1].imm - bias;
11895 inst.instruction |= Rn << 16;
11897 if (inst.operands[3].present)
11899 offsetT shift_amount = inst.reloc.exp.X_add_number;
11901 inst.reloc.type = BFD_RELOC_UNUSED;
11903 constraint (inst.reloc.exp.X_op != O_constant,
11904 _("expression too complex"));
11906 if (shift_amount != 0)
11908 constraint (shift_amount > 31,
11909 _("shift expression is too large"));
11911 if (inst.operands[3].shift_kind == SHIFT_ASR)
11912 inst.instruction |= 0x00200000; /* sh bit. */
11914 inst.instruction |= (shift_amount & 0x1c) << 10;
11915 inst.instruction |= (shift_amount & 0x03) << 6;
11923 do_t_ssat_usat (1);
11931 Rd = inst.operands[0].reg;
11932 Rn = inst.operands[2].reg;
11934 reject_bad_reg (Rd);
11935 reject_bad_reg (Rn);
11937 inst.instruction |= Rd << 8;
11938 inst.instruction |= inst.operands[1].imm - 1;
11939 inst.instruction |= Rn << 16;
11945 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11946 || inst.operands[2].postind || inst.operands[2].writeback
11947 || inst.operands[2].immisreg || inst.operands[2].shifted
11948 || inst.operands[2].negative,
11951 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11953 inst.instruction |= inst.operands[0].reg << 8;
11954 inst.instruction |= inst.operands[1].reg << 12;
11955 inst.instruction |= inst.operands[2].reg << 16;
11956 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11962 if (!inst.operands[2].present)
11963 inst.operands[2].reg = inst.operands[1].reg + 1;
11965 constraint (inst.operands[0].reg == inst.operands[1].reg
11966 || inst.operands[0].reg == inst.operands[2].reg
11967 || inst.operands[0].reg == inst.operands[3].reg,
11970 inst.instruction |= inst.operands[0].reg;
11971 inst.instruction |= inst.operands[1].reg << 12;
11972 inst.instruction |= inst.operands[2].reg << 8;
11973 inst.instruction |= inst.operands[3].reg << 16;
11979 unsigned Rd, Rn, Rm;
11981 Rd = inst.operands[0].reg;
11982 Rn = inst.operands[1].reg;
11983 Rm = inst.operands[2].reg;
11985 reject_bad_reg (Rd);
11986 reject_bad_reg (Rn);
11987 reject_bad_reg (Rm);
11989 inst.instruction |= Rd << 8;
11990 inst.instruction |= Rn << 16;
11991 inst.instruction |= Rm;
11992 inst.instruction |= inst.operands[3].imm << 4;
12000 Rd = inst.operands[0].reg;
12001 Rm = inst.operands[1].reg;
12003 reject_bad_reg (Rd);
12004 reject_bad_reg (Rm);
12006 if (inst.instruction <= 0xffff
12007 && inst.size_req != 4
12008 && Rd <= 7 && Rm <= 7
12009 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12011 inst.instruction = THUMB_OP16 (inst.instruction);
12012 inst.instruction |= Rd;
12013 inst.instruction |= Rm << 3;
12015 else if (unified_syntax)
12017 if (inst.instruction <= 0xffff)
12018 inst.instruction = THUMB_OP32 (inst.instruction);
12019 inst.instruction |= Rd << 8;
12020 inst.instruction |= Rm;
12021 inst.instruction |= inst.operands[2].imm << 4;
12025 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12026 _("Thumb encoding does not support rotation"));
12027 constraint (1, BAD_HIREG);
12034 /* We have to do the following check manually as ARM_EXT_OS only applies
12036 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12038 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12039 /* This only applies to the v6m howver, not later architectures. */
12040 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12041 as_bad (_("SVC is not permitted on this architecture"));
12042 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12045 inst.reloc.type = BFD_RELOC_ARM_SWI;
12054 half = (inst.instruction & 0x10) != 0;
12055 set_it_insn_type_last ();
12056 constraint (inst.operands[0].immisreg,
12057 _("instruction requires register index"));
12059 Rn = inst.operands[0].reg;
12060 Rm = inst.operands[0].imm;
12062 constraint (Rn == REG_SP, BAD_SP);
12063 reject_bad_reg (Rm);
12065 constraint (!half && inst.operands[0].shifted,
12066 _("instruction does not allow shifted index"));
12067 inst.instruction |= (Rn << 16) | Rm;
12073 do_t_ssat_usat (0);
12081 Rd = inst.operands[0].reg;
12082 Rn = inst.operands[2].reg;
12084 reject_bad_reg (Rd);
12085 reject_bad_reg (Rn);
12087 inst.instruction |= Rd << 8;
12088 inst.instruction |= inst.operands[1].imm;
12089 inst.instruction |= Rn << 16;
12092 /* Neon instruction encoder helpers. */
12094 /* Encodings for the different types for various Neon opcodes. */
12096 /* An "invalid" code for the following tables. */
12099 struct neon_tab_entry
12102 unsigned float_or_poly;
12103 unsigned scalar_or_imm;
12106 /* Map overloaded Neon opcodes to their respective encodings. */
12107 #define NEON_ENC_TAB \
12108 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12109 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12110 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12111 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12112 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12113 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12114 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12115 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12116 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12117 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12118 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12119 /* Register variants of the following two instructions are encoded as
12120 vcge / vcgt with the operands reversed. */ \
12121 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12122 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12123 X(vfma, N_INV, 0x0000c10, N_INV), \
12124 X(vfms, N_INV, 0x0200c10, N_INV), \
12125 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12126 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12127 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12128 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12129 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12130 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12131 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12132 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12133 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12134 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12135 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12136 X(vshl, 0x0000400, N_INV, 0x0800510), \
12137 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12138 X(vand, 0x0000110, N_INV, 0x0800030), \
12139 X(vbic, 0x0100110, N_INV, 0x0800030), \
12140 X(veor, 0x1000110, N_INV, N_INV), \
12141 X(vorn, 0x0300110, N_INV, 0x0800010), \
12142 X(vorr, 0x0200110, N_INV, 0x0800010), \
12143 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12144 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12145 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12146 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12147 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12148 X(vst1, 0x0000000, 0x0800000, N_INV), \
12149 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12150 X(vst2, 0x0000100, 0x0800100, N_INV), \
12151 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12152 X(vst3, 0x0000200, 0x0800200, N_INV), \
12153 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12154 X(vst4, 0x0000300, 0x0800300, N_INV), \
12155 X(vmovn, 0x1b20200, N_INV, N_INV), \
12156 X(vtrn, 0x1b20080, N_INV, N_INV), \
12157 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12158 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12159 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12160 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12161 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12162 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12163 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12164 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12165 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12166 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12167 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12171 #define X(OPC,I,F,S) N_MNEM_##OPC
12176 static const struct neon_tab_entry neon_enc_tab[] =
12178 #define X(OPC,I,F,S) { (I), (F), (S) }
12183 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12184 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12185 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12186 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12187 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12188 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12189 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12190 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12191 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12192 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12193 #define NEON_ENC_SINGLE_(X) \
12194 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12195 #define NEON_ENC_DOUBLE_(X) \
12196 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12198 #define NEON_ENCODE(type, inst) \
12201 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12202 inst.is_neon = 1; \
12206 #define check_neon_suffixes \
12209 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12211 as_bad (_("invalid neon suffix for non neon instruction")); \
12217 /* Define shapes for instruction operands. The following mnemonic characters
12218 are used in this table:
12220 F - VFP S<n> register
12221 D - Neon D<n> register
12222 Q - Neon Q<n> register
12226 L - D<n> register list
12228 This table is used to generate various data:
12229 - enumerations of the form NS_DDR to be used as arguments to
12231 - a table classifying shapes into single, double, quad, mixed.
12232 - a table used to drive neon_select_shape. */
12234 #define NEON_SHAPE_DEF \
12235 X(3, (D, D, D), DOUBLE), \
12236 X(3, (Q, Q, Q), QUAD), \
12237 X(3, (D, D, I), DOUBLE), \
12238 X(3, (Q, Q, I), QUAD), \
12239 X(3, (D, D, S), DOUBLE), \
12240 X(3, (Q, Q, S), QUAD), \
12241 X(2, (D, D), DOUBLE), \
12242 X(2, (Q, Q), QUAD), \
12243 X(2, (D, S), DOUBLE), \
12244 X(2, (Q, S), QUAD), \
12245 X(2, (D, R), DOUBLE), \
12246 X(2, (Q, R), QUAD), \
12247 X(2, (D, I), DOUBLE), \
12248 X(2, (Q, I), QUAD), \
12249 X(3, (D, L, D), DOUBLE), \
12250 X(2, (D, Q), MIXED), \
12251 X(2, (Q, D), MIXED), \
12252 X(3, (D, Q, I), MIXED), \
12253 X(3, (Q, D, I), MIXED), \
12254 X(3, (Q, D, D), MIXED), \
12255 X(3, (D, Q, Q), MIXED), \
12256 X(3, (Q, Q, D), MIXED), \
12257 X(3, (Q, D, S), MIXED), \
12258 X(3, (D, Q, S), MIXED), \
12259 X(4, (D, D, D, I), DOUBLE), \
12260 X(4, (Q, Q, Q, I), QUAD), \
12261 X(2, (F, F), SINGLE), \
12262 X(3, (F, F, F), SINGLE), \
12263 X(2, (F, I), SINGLE), \
12264 X(2, (F, D), MIXED), \
12265 X(2, (D, F), MIXED), \
12266 X(3, (F, F, I), MIXED), \
12267 X(4, (R, R, F, F), SINGLE), \
12268 X(4, (F, F, R, R), SINGLE), \
12269 X(3, (D, R, R), DOUBLE), \
12270 X(3, (R, R, D), DOUBLE), \
12271 X(2, (S, R), SINGLE), \
12272 X(2, (R, S), SINGLE), \
12273 X(2, (F, R), SINGLE), \
12274 X(2, (R, F), SINGLE)
12276 #define S2(A,B) NS_##A##B
12277 #define S3(A,B,C) NS_##A##B##C
12278 #define S4(A,B,C,D) NS_##A##B##C##D
12280 #define X(N, L, C) S##N L
12293 enum neon_shape_class
12301 #define X(N, L, C) SC_##C
12303 static enum neon_shape_class neon_shape_class[] =
12321 /* Register widths of above. */
12322 static unsigned neon_shape_el_size[] =
12333 struct neon_shape_info
12336 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12339 #define S2(A,B) { SE_##A, SE_##B }
12340 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12341 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12343 #define X(N, L, C) { N, S##N L }
12345 static struct neon_shape_info neon_shape_tab[] =
12355 /* Bit masks used in type checking given instructions.
12356 'N_EQK' means the type must be the same as (or based on in some way) the key
12357 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12358 set, various other bits can be set as well in order to modify the meaning of
12359 the type constraint. */
12361 enum neon_type_mask
12384 N_KEY = 0x1000000, /* Key element (main type specifier). */
12385 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12386 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12387 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12388 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12389 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12390 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12391 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12392 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12393 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12395 N_MAX_NONSPECIAL = N_F64
12398 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12400 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12401 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12402 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12403 #define N_SUF_32 (N_SU_32 | N_F32)
12404 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12405 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12407 /* Pass this as the first type argument to neon_check_type to ignore types
12409 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12411 /* Select a "shape" for the current instruction (describing register types or
12412 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12413 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12414 function of operand parsing, so this function doesn't need to be called.
12415 Shapes should be listed in order of decreasing length. */
12417 static enum neon_shape
12418 neon_select_shape (enum neon_shape shape, ...)
12421 enum neon_shape first_shape = shape;
12423 /* Fix missing optional operands. FIXME: we don't know at this point how
12424 many arguments we should have, so this makes the assumption that we have
12425 > 1. This is true of all current Neon opcodes, I think, but may not be
12426 true in the future. */
12427 if (!inst.operands[1].present)
12428 inst.operands[1] = inst.operands[0];
12430 va_start (ap, shape);
12432 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12437 for (j = 0; j < neon_shape_tab[shape].els; j++)
12439 if (!inst.operands[j].present)
12445 switch (neon_shape_tab[shape].el[j])
12448 if (!(inst.operands[j].isreg
12449 && inst.operands[j].isvec
12450 && inst.operands[j].issingle
12451 && !inst.operands[j].isquad))
12456 if (!(inst.operands[j].isreg
12457 && inst.operands[j].isvec
12458 && !inst.operands[j].isquad
12459 && !inst.operands[j].issingle))
12464 if (!(inst.operands[j].isreg
12465 && !inst.operands[j].isvec))
12470 if (!(inst.operands[j].isreg
12471 && inst.operands[j].isvec
12472 && inst.operands[j].isquad
12473 && !inst.operands[j].issingle))
12478 if (!(!inst.operands[j].isreg
12479 && !inst.operands[j].isscalar))
12484 if (!(!inst.operands[j].isreg
12485 && inst.operands[j].isscalar))
12495 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12496 /* We've matched all the entries in the shape table, and we don't
12497 have any left over operands which have not been matched. */
12503 if (shape == NS_NULL && first_shape != NS_NULL)
12504 first_error (_("invalid instruction shape"));
12509 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12510 means the Q bit should be set). */
12513 neon_quad (enum neon_shape shape)
12515 return neon_shape_class[shape] == SC_QUAD;
12519 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12522 /* Allow modification to be made to types which are constrained to be
12523 based on the key element, based on bits set alongside N_EQK. */
12524 if ((typebits & N_EQK) != 0)
12526 if ((typebits & N_HLF) != 0)
12528 else if ((typebits & N_DBL) != 0)
12530 if ((typebits & N_SGN) != 0)
12531 *g_type = NT_signed;
12532 else if ((typebits & N_UNS) != 0)
12533 *g_type = NT_unsigned;
12534 else if ((typebits & N_INT) != 0)
12535 *g_type = NT_integer;
12536 else if ((typebits & N_FLT) != 0)
12537 *g_type = NT_float;
12538 else if ((typebits & N_SIZ) != 0)
12539 *g_type = NT_untyped;
12543 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12544 operand type, i.e. the single type specified in a Neon instruction when it
12545 is the only one given. */
12547 static struct neon_type_el
12548 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12550 struct neon_type_el dest = *key;
12552 gas_assert ((thisarg & N_EQK) != 0);
12554 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12559 /* Convert Neon type and size into compact bitmask representation. */
12561 static enum neon_type_mask
12562 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12569 case 8: return N_8;
12570 case 16: return N_16;
12571 case 32: return N_32;
12572 case 64: return N_64;
12580 case 8: return N_I8;
12581 case 16: return N_I16;
12582 case 32: return N_I32;
12583 case 64: return N_I64;
12591 case 16: return N_F16;
12592 case 32: return N_F32;
12593 case 64: return N_F64;
12601 case 8: return N_P8;
12602 case 16: return N_P16;
12610 case 8: return N_S8;
12611 case 16: return N_S16;
12612 case 32: return N_S32;
12613 case 64: return N_S64;
12621 case 8: return N_U8;
12622 case 16: return N_U16;
12623 case 32: return N_U32;
12624 case 64: return N_U64;
12635 /* Convert compact Neon bitmask type representation to a type and size. Only
12636 handles the case where a single bit is set in the mask. */
12639 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12640 enum neon_type_mask mask)
12642 if ((mask & N_EQK) != 0)
12645 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12647 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12649 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12651 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12656 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12658 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12659 *type = NT_unsigned;
12660 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12661 *type = NT_integer;
12662 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12663 *type = NT_untyped;
12664 else if ((mask & (N_P8 | N_P16)) != 0)
12666 else if ((mask & (N_F32 | N_F64)) != 0)
12674 /* Modify a bitmask of allowed types. This is only needed for type
12678 modify_types_allowed (unsigned allowed, unsigned mods)
12681 enum neon_el_type type;
12687 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12689 if (el_type_of_type_chk (&type, &size,
12690 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12692 neon_modify_type_size (mods, &type, &size);
12693 destmask |= type_chk_of_el_type (type, size);
12700 /* Check type and return type classification.
12701 The manual states (paraphrase): If one datatype is given, it indicates the
12703 - the second operand, if there is one
12704 - the operand, if there is no second operand
12705 - the result, if there are no operands.
12706 This isn't quite good enough though, so we use a concept of a "key" datatype
12707 which is set on a per-instruction basis, which is the one which matters when
12708 only one data type is written.
12709 Note: this function has side-effects (e.g. filling in missing operands). All
12710 Neon instructions should call it before performing bit encoding. */
12712 static struct neon_type_el
12713 neon_check_type (unsigned els, enum neon_shape ns, ...)
12716 unsigned i, pass, key_el = 0;
12717 unsigned types[NEON_MAX_TYPE_ELS];
12718 enum neon_el_type k_type = NT_invtype;
12719 unsigned k_size = -1u;
12720 struct neon_type_el badtype = {NT_invtype, -1};
12721 unsigned key_allowed = 0;
12723 /* Optional registers in Neon instructions are always (not) in operand 1.
12724 Fill in the missing operand here, if it was omitted. */
12725 if (els > 1 && !inst.operands[1].present)
12726 inst.operands[1] = inst.operands[0];
12728 /* Suck up all the varargs. */
12730 for (i = 0; i < els; i++)
12732 unsigned thisarg = va_arg (ap, unsigned);
12733 if (thisarg == N_IGNORE_TYPE)
12738 types[i] = thisarg;
12739 if ((thisarg & N_KEY) != 0)
12744 if (inst.vectype.elems > 0)
12745 for (i = 0; i < els; i++)
12746 if (inst.operands[i].vectype.type != NT_invtype)
12748 first_error (_("types specified in both the mnemonic and operands"));
12752 /* Duplicate inst.vectype elements here as necessary.
12753 FIXME: No idea if this is exactly the same as the ARM assembler,
12754 particularly when an insn takes one register and one non-register
12756 if (inst.vectype.elems == 1 && els > 1)
12759 inst.vectype.elems = els;
12760 inst.vectype.el[key_el] = inst.vectype.el[0];
12761 for (j = 0; j < els; j++)
12763 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12766 else if (inst.vectype.elems == 0 && els > 0)
12769 /* No types were given after the mnemonic, so look for types specified
12770 after each operand. We allow some flexibility here; as long as the
12771 "key" operand has a type, we can infer the others. */
12772 for (j = 0; j < els; j++)
12773 if (inst.operands[j].vectype.type != NT_invtype)
12774 inst.vectype.el[j] = inst.operands[j].vectype;
12776 if (inst.operands[key_el].vectype.type != NT_invtype)
12778 for (j = 0; j < els; j++)
12779 if (inst.operands[j].vectype.type == NT_invtype)
12780 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12785 first_error (_("operand types can't be inferred"));
12789 else if (inst.vectype.elems != els)
12791 first_error (_("type specifier has the wrong number of parts"));
12795 for (pass = 0; pass < 2; pass++)
12797 for (i = 0; i < els; i++)
12799 unsigned thisarg = types[i];
12800 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12801 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12802 enum neon_el_type g_type = inst.vectype.el[i].type;
12803 unsigned g_size = inst.vectype.el[i].size;
12805 /* Decay more-specific signed & unsigned types to sign-insensitive
12806 integer types if sign-specific variants are unavailable. */
12807 if ((g_type == NT_signed || g_type == NT_unsigned)
12808 && (types_allowed & N_SU_ALL) == 0)
12809 g_type = NT_integer;
12811 /* If only untyped args are allowed, decay any more specific types to
12812 them. Some instructions only care about signs for some element
12813 sizes, so handle that properly. */
12814 if ((g_size == 8 && (types_allowed & N_8) != 0)
12815 || (g_size == 16 && (types_allowed & N_16) != 0)
12816 || (g_size == 32 && (types_allowed & N_32) != 0)
12817 || (g_size == 64 && (types_allowed & N_64) != 0))
12818 g_type = NT_untyped;
12822 if ((thisarg & N_KEY) != 0)
12826 key_allowed = thisarg & ~N_KEY;
12831 if ((thisarg & N_VFP) != 0)
12833 enum neon_shape_el regshape;
12834 unsigned regwidth, match;
12836 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12839 first_error (_("invalid instruction shape"));
12842 regshape = neon_shape_tab[ns].el[i];
12843 regwidth = neon_shape_el_size[regshape];
12845 /* In VFP mode, operands must match register widths. If we
12846 have a key operand, use its width, else use the width of
12847 the current operand. */
12853 if (regwidth != match)
12855 first_error (_("operand size must match register width"));
12860 if ((thisarg & N_EQK) == 0)
12862 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12864 if ((given_type & types_allowed) == 0)
12866 first_error (_("bad type in Neon instruction"));
12872 enum neon_el_type mod_k_type = k_type;
12873 unsigned mod_k_size = k_size;
12874 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12875 if (g_type != mod_k_type || g_size != mod_k_size)
12877 first_error (_("inconsistent types in Neon instruction"));
12885 return inst.vectype.el[key_el];
12888 /* Neon-style VFP instruction forwarding. */
12890 /* Thumb VFP instructions have 0xE in the condition field. */
12893 do_vfp_cond_or_thumb (void)
12898 inst.instruction |= 0xe0000000;
12900 inst.instruction |= inst.cond << 28;
12903 /* Look up and encode a simple mnemonic, for use as a helper function for the
12904 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12905 etc. It is assumed that operand parsing has already been done, and that the
12906 operands are in the form expected by the given opcode (this isn't necessarily
12907 the same as the form in which they were parsed, hence some massaging must
12908 take place before this function is called).
12909 Checks current arch version against that in the looked-up opcode. */
12912 do_vfp_nsyn_opcode (const char *opname)
12914 const struct asm_opcode *opcode;
12916 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12921 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12922 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12929 inst.instruction = opcode->tvalue;
12930 opcode->tencode ();
12934 inst.instruction = (inst.cond << 28) | opcode->avalue;
12935 opcode->aencode ();
12940 do_vfp_nsyn_add_sub (enum neon_shape rs)
12942 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12947 do_vfp_nsyn_opcode ("fadds");
12949 do_vfp_nsyn_opcode ("fsubs");
12954 do_vfp_nsyn_opcode ("faddd");
12956 do_vfp_nsyn_opcode ("fsubd");
12960 /* Check operand types to see if this is a VFP instruction, and if so call
12964 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12966 enum neon_shape rs;
12967 struct neon_type_el et;
12972 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12973 et = neon_check_type (2, rs,
12974 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12978 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12979 et = neon_check_type (3, rs,
12980 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12987 if (et.type != NT_invtype)
12998 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13000 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13005 do_vfp_nsyn_opcode ("fmacs");
13007 do_vfp_nsyn_opcode ("fnmacs");
13012 do_vfp_nsyn_opcode ("fmacd");
13014 do_vfp_nsyn_opcode ("fnmacd");
13019 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13021 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13026 do_vfp_nsyn_opcode ("ffmas");
13028 do_vfp_nsyn_opcode ("ffnmas");
13033 do_vfp_nsyn_opcode ("ffmad");
13035 do_vfp_nsyn_opcode ("ffnmad");
13040 do_vfp_nsyn_mul (enum neon_shape rs)
13043 do_vfp_nsyn_opcode ("fmuls");
13045 do_vfp_nsyn_opcode ("fmuld");
13049 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13051 int is_neg = (inst.instruction & 0x80) != 0;
13052 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13057 do_vfp_nsyn_opcode ("fnegs");
13059 do_vfp_nsyn_opcode ("fabss");
13064 do_vfp_nsyn_opcode ("fnegd");
13066 do_vfp_nsyn_opcode ("fabsd");
13070 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13071 insns belong to Neon, and are handled elsewhere. */
13074 do_vfp_nsyn_ldm_stm (int is_dbmode)
13076 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13080 do_vfp_nsyn_opcode ("fldmdbs");
13082 do_vfp_nsyn_opcode ("fldmias");
13087 do_vfp_nsyn_opcode ("fstmdbs");
13089 do_vfp_nsyn_opcode ("fstmias");
13094 do_vfp_nsyn_sqrt (void)
13096 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13097 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13100 do_vfp_nsyn_opcode ("fsqrts");
13102 do_vfp_nsyn_opcode ("fsqrtd");
13106 do_vfp_nsyn_div (void)
13108 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13109 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13110 N_F32 | N_F64 | N_KEY | N_VFP);
13113 do_vfp_nsyn_opcode ("fdivs");
13115 do_vfp_nsyn_opcode ("fdivd");
13119 do_vfp_nsyn_nmul (void)
13121 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13122 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13123 N_F32 | N_F64 | N_KEY | N_VFP);
13127 NEON_ENCODE (SINGLE, inst);
13128 do_vfp_sp_dyadic ();
13132 NEON_ENCODE (DOUBLE, inst);
13133 do_vfp_dp_rd_rn_rm ();
13135 do_vfp_cond_or_thumb ();
13139 do_vfp_nsyn_cmp (void)
13141 if (inst.operands[1].isreg)
13143 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13144 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13148 NEON_ENCODE (SINGLE, inst);
13149 do_vfp_sp_monadic ();
13153 NEON_ENCODE (DOUBLE, inst);
13154 do_vfp_dp_rd_rm ();
13159 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13160 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13162 switch (inst.instruction & 0x0fffffff)
13165 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13168 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13176 NEON_ENCODE (SINGLE, inst);
13177 do_vfp_sp_compare_z ();
13181 NEON_ENCODE (DOUBLE, inst);
13185 do_vfp_cond_or_thumb ();
13189 nsyn_insert_sp (void)
13191 inst.operands[1] = inst.operands[0];
13192 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13193 inst.operands[0].reg = REG_SP;
13194 inst.operands[0].isreg = 1;
13195 inst.operands[0].writeback = 1;
13196 inst.operands[0].present = 1;
13200 do_vfp_nsyn_push (void)
13203 if (inst.operands[1].issingle)
13204 do_vfp_nsyn_opcode ("fstmdbs");
13206 do_vfp_nsyn_opcode ("fstmdbd");
13210 do_vfp_nsyn_pop (void)
13213 if (inst.operands[1].issingle)
13214 do_vfp_nsyn_opcode ("fldmias");
13216 do_vfp_nsyn_opcode ("fldmiad");
13219 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13220 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13223 neon_dp_fixup (struct arm_it* insn)
13225 unsigned int i = insn->instruction;
13230 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13241 insn->instruction = i;
13244 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13248 neon_logbits (unsigned x)
13250 return ffs (x) - 4;
13253 #define LOW4(R) ((R) & 0xf)
13254 #define HI1(R) (((R) >> 4) & 1)
13256 /* Encode insns with bit pattern:
13258 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13259 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13261 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13262 different meaning for some instruction. */
13265 neon_three_same (int isquad, int ubit, int size)
13267 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13268 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13269 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13270 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13271 inst.instruction |= LOW4 (inst.operands[2].reg);
13272 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13273 inst.instruction |= (isquad != 0) << 6;
13274 inst.instruction |= (ubit != 0) << 24;
13276 inst.instruction |= neon_logbits (size) << 20;
13278 neon_dp_fixup (&inst);
13281 /* Encode instructions of the form:
13283 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13284 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13286 Don't write size if SIZE == -1. */
13289 neon_two_same (int qbit, int ubit, int size)
13291 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13292 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13293 inst.instruction |= LOW4 (inst.operands[1].reg);
13294 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13295 inst.instruction |= (qbit != 0) << 6;
13296 inst.instruction |= (ubit != 0) << 24;
13299 inst.instruction |= neon_logbits (size) << 18;
13301 neon_dp_fixup (&inst);
13304 /* Neon instruction encoders, in approximate order of appearance. */
13307 do_neon_dyadic_i_su (void)
13309 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13310 struct neon_type_el et = neon_check_type (3, rs,
13311 N_EQK, N_EQK, N_SU_32 | N_KEY);
13312 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13316 do_neon_dyadic_i64_su (void)
13318 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13319 struct neon_type_el et = neon_check_type (3, rs,
13320 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13321 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13325 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13328 unsigned size = et.size >> 3;
13329 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13330 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13331 inst.instruction |= LOW4 (inst.operands[1].reg);
13332 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13333 inst.instruction |= (isquad != 0) << 6;
13334 inst.instruction |= immbits << 16;
13335 inst.instruction |= (size >> 3) << 7;
13336 inst.instruction |= (size & 0x7) << 19;
13338 inst.instruction |= (uval != 0) << 24;
13340 neon_dp_fixup (&inst);
13344 do_neon_shl_imm (void)
13346 if (!inst.operands[2].isreg)
13348 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13349 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13350 NEON_ENCODE (IMMED, inst);
13351 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13355 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13356 struct neon_type_el et = neon_check_type (3, rs,
13357 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13360 /* VSHL/VQSHL 3-register variants have syntax such as:
13362 whereas other 3-register operations encoded by neon_three_same have
13365 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13367 tmp = inst.operands[2].reg;
13368 inst.operands[2].reg = inst.operands[1].reg;
13369 inst.operands[1].reg = tmp;
13370 NEON_ENCODE (INTEGER, inst);
13371 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13376 do_neon_qshl_imm (void)
13378 if (!inst.operands[2].isreg)
13380 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13381 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13383 NEON_ENCODE (IMMED, inst);
13384 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13385 inst.operands[2].imm);
13389 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13390 struct neon_type_el et = neon_check_type (3, rs,
13391 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13394 /* See note in do_neon_shl_imm. */
13395 tmp = inst.operands[2].reg;
13396 inst.operands[2].reg = inst.operands[1].reg;
13397 inst.operands[1].reg = tmp;
13398 NEON_ENCODE (INTEGER, inst);
13399 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13404 do_neon_rshl (void)
13406 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13407 struct neon_type_el et = neon_check_type (3, rs,
13408 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13411 tmp = inst.operands[2].reg;
13412 inst.operands[2].reg = inst.operands[1].reg;
13413 inst.operands[1].reg = tmp;
13414 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13418 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13420 /* Handle .I8 pseudo-instructions. */
13423 /* Unfortunately, this will make everything apart from zero out-of-range.
13424 FIXME is this the intended semantics? There doesn't seem much point in
13425 accepting .I8 if so. */
13426 immediate |= immediate << 8;
13432 if (immediate == (immediate & 0x000000ff))
13434 *immbits = immediate;
13437 else if (immediate == (immediate & 0x0000ff00))
13439 *immbits = immediate >> 8;
13442 else if (immediate == (immediate & 0x00ff0000))
13444 *immbits = immediate >> 16;
13447 else if (immediate == (immediate & 0xff000000))
13449 *immbits = immediate >> 24;
13452 if ((immediate & 0xffff) != (immediate >> 16))
13453 goto bad_immediate;
13454 immediate &= 0xffff;
13457 if (immediate == (immediate & 0x000000ff))
13459 *immbits = immediate;
13462 else if (immediate == (immediate & 0x0000ff00))
13464 *immbits = immediate >> 8;
13469 first_error (_("immediate value out of range"));
13473 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13477 neon_bits_same_in_bytes (unsigned imm)
13479 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13480 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13481 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13482 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13485 /* For immediate of above form, return 0bABCD. */
13488 neon_squash_bits (unsigned imm)
13490 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13491 | ((imm & 0x01000000) >> 21);
13494 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13497 neon_qfloat_bits (unsigned imm)
13499 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13502 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13503 the instruction. *OP is passed as the initial value of the op field, and
13504 may be set to a different value depending on the constant (i.e.
13505 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13506 MVN). If the immediate looks like a repeated pattern then also
13507 try smaller element sizes. */
13510 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13511 unsigned *immbits, int *op, int size,
13512 enum neon_el_type type)
13514 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13516 if (type == NT_float && !float_p)
13519 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13521 if (size != 32 || *op == 1)
13523 *immbits = neon_qfloat_bits (immlo);
13529 if (neon_bits_same_in_bytes (immhi)
13530 && neon_bits_same_in_bytes (immlo))
13534 *immbits = (neon_squash_bits (immhi) << 4)
13535 | neon_squash_bits (immlo);
13540 if (immhi != immlo)
13546 if (immlo == (immlo & 0x000000ff))
13551 else if (immlo == (immlo & 0x0000ff00))
13553 *immbits = immlo >> 8;
13556 else if (immlo == (immlo & 0x00ff0000))
13558 *immbits = immlo >> 16;
13561 else if (immlo == (immlo & 0xff000000))
13563 *immbits = immlo >> 24;
13566 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13568 *immbits = (immlo >> 8) & 0xff;
13571 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13573 *immbits = (immlo >> 16) & 0xff;
13577 if ((immlo & 0xffff) != (immlo >> 16))
13584 if (immlo == (immlo & 0x000000ff))
13589 else if (immlo == (immlo & 0x0000ff00))
13591 *immbits = immlo >> 8;
13595 if ((immlo & 0xff) != (immlo >> 8))
13600 if (immlo == (immlo & 0x000000ff))
13602 /* Don't allow MVN with 8-bit immediate. */
13612 /* Write immediate bits [7:0] to the following locations:
13614 |28/24|23 19|18 16|15 4|3 0|
13615 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13617 This function is used by VMOV/VMVN/VORR/VBIC. */
13620 neon_write_immbits (unsigned immbits)
13622 inst.instruction |= immbits & 0xf;
13623 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13624 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13627 /* Invert low-order SIZE bits of XHI:XLO. */
13630 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13632 unsigned immlo = xlo ? *xlo : 0;
13633 unsigned immhi = xhi ? *xhi : 0;
13638 immlo = (~immlo) & 0xff;
13642 immlo = (~immlo) & 0xffff;
13646 immhi = (~immhi) & 0xffffffff;
13647 /* fall through. */
13650 immlo = (~immlo) & 0xffffffff;
13665 do_neon_logic (void)
13667 if (inst.operands[2].present && inst.operands[2].isreg)
13669 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13670 neon_check_type (3, rs, N_IGNORE_TYPE);
13671 /* U bit and size field were set as part of the bitmask. */
13672 NEON_ENCODE (INTEGER, inst);
13673 neon_three_same (neon_quad (rs), 0, -1);
13677 const int three_ops_form = (inst.operands[2].present
13678 && !inst.operands[2].isreg);
13679 const int immoperand = (three_ops_form ? 2 : 1);
13680 enum neon_shape rs = (three_ops_form
13681 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13682 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13683 struct neon_type_el et = neon_check_type (2, rs,
13684 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13685 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13689 if (et.type == NT_invtype)
13692 if (three_ops_form)
13693 constraint (inst.operands[0].reg != inst.operands[1].reg,
13694 _("first and second operands shall be the same register"));
13696 NEON_ENCODE (IMMED, inst);
13698 immbits = inst.operands[immoperand].imm;
13701 /* .i64 is a pseudo-op, so the immediate must be a repeating
13703 if (immbits != (inst.operands[immoperand].regisimm ?
13704 inst.operands[immoperand].reg : 0))
13706 /* Set immbits to an invalid constant. */
13707 immbits = 0xdeadbeef;
13714 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13718 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13722 /* Pseudo-instruction for VBIC. */
13723 neon_invert_size (&immbits, 0, et.size);
13724 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13728 /* Pseudo-instruction for VORR. */
13729 neon_invert_size (&immbits, 0, et.size);
13730 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13740 inst.instruction |= neon_quad (rs) << 6;
13741 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13742 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13743 inst.instruction |= cmode << 8;
13744 neon_write_immbits (immbits);
13746 neon_dp_fixup (&inst);
13751 do_neon_bitfield (void)
13753 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13754 neon_check_type (3, rs, N_IGNORE_TYPE);
13755 neon_three_same (neon_quad (rs), 0, -1);
13759 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13762 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13763 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13765 if (et.type == NT_float)
13767 NEON_ENCODE (FLOAT, inst);
13768 neon_three_same (neon_quad (rs), 0, -1);
13772 NEON_ENCODE (INTEGER, inst);
13773 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13778 do_neon_dyadic_if_su (void)
13780 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13784 do_neon_dyadic_if_su_d (void)
13786 /* This version only allow D registers, but that constraint is enforced during
13787 operand parsing so we don't need to do anything extra here. */
13788 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13792 do_neon_dyadic_if_i_d (void)
13794 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13795 affected if we specify unsigned args. */
13796 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13799 enum vfp_or_neon_is_neon_bits
13802 NEON_CHECK_ARCH = 2
13805 /* Call this function if an instruction which may have belonged to the VFP or
13806 Neon instruction sets, but turned out to be a Neon instruction (due to the
13807 operand types involved, etc.). We have to check and/or fix-up a couple of
13810 - Make sure the user hasn't attempted to make a Neon instruction
13812 - Alter the value in the condition code field if necessary.
13813 - Make sure that the arch supports Neon instructions.
13815 Which of these operations take place depends on bits from enum
13816 vfp_or_neon_is_neon_bits.
13818 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13819 current instruction's condition is COND_ALWAYS, the condition field is
13820 changed to inst.uncond_value. This is necessary because instructions shared
13821 between VFP and Neon may be conditional for the VFP variants only, and the
13822 unconditional Neon version must have, e.g., 0xF in the condition field. */
13825 vfp_or_neon_is_neon (unsigned check)
13827 /* Conditions are always legal in Thumb mode (IT blocks). */
13828 if (!thumb_mode && (check & NEON_CHECK_CC))
13830 if (inst.cond != COND_ALWAYS)
13832 first_error (_(BAD_COND));
13835 if (inst.uncond_value != -1)
13836 inst.instruction |= inst.uncond_value << 28;
13839 if ((check & NEON_CHECK_ARCH)
13840 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13842 first_error (_(BAD_FPU));
13850 do_neon_addsub_if_i (void)
13852 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13855 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13858 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13859 affected if we specify unsigned args. */
13860 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13863 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13865 V<op> A,B (A is operand 0, B is operand 2)
13870 so handle that case specially. */
13873 neon_exchange_operands (void)
13875 void *scratch = alloca (sizeof (inst.operands[0]));
13876 if (inst.operands[1].present)
13878 /* Swap operands[1] and operands[2]. */
13879 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13880 inst.operands[1] = inst.operands[2];
13881 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13885 inst.operands[1] = inst.operands[2];
13886 inst.operands[2] = inst.operands[0];
13891 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13893 if (inst.operands[2].isreg)
13896 neon_exchange_operands ();
13897 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13901 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13902 struct neon_type_el et = neon_check_type (2, rs,
13903 N_EQK | N_SIZ, immtypes | N_KEY);
13905 NEON_ENCODE (IMMED, inst);
13906 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13907 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13908 inst.instruction |= LOW4 (inst.operands[1].reg);
13909 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13910 inst.instruction |= neon_quad (rs) << 6;
13911 inst.instruction |= (et.type == NT_float) << 10;
13912 inst.instruction |= neon_logbits (et.size) << 18;
13914 neon_dp_fixup (&inst);
13921 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13925 do_neon_cmp_inv (void)
13927 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13933 neon_compare (N_IF_32, N_IF_32, FALSE);
13936 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13937 scalars, which are encoded in 5 bits, M : Rm.
13938 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13939 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13943 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13945 unsigned regno = NEON_SCALAR_REG (scalar);
13946 unsigned elno = NEON_SCALAR_INDEX (scalar);
13951 if (regno > 7 || elno > 3)
13953 return regno | (elno << 3);
13956 if (regno > 15 || elno > 1)
13958 return regno | (elno << 4);
13962 first_error (_("scalar out of range for multiply instruction"));
13968 /* Encode multiply / multiply-accumulate scalar instructions. */
13971 neon_mul_mac (struct neon_type_el et, int ubit)
13975 /* Give a more helpful error message if we have an invalid type. */
13976 if (et.type == NT_invtype)
13979 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
13980 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13981 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13982 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13983 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13984 inst.instruction |= LOW4 (scalar);
13985 inst.instruction |= HI1 (scalar) << 5;
13986 inst.instruction |= (et.type == NT_float) << 8;
13987 inst.instruction |= neon_logbits (et.size) << 20;
13988 inst.instruction |= (ubit != 0) << 24;
13990 neon_dp_fixup (&inst);
13994 do_neon_mac_maybe_scalar (void)
13996 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
13999 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14002 if (inst.operands[2].isscalar)
14004 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14005 struct neon_type_el et = neon_check_type (3, rs,
14006 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14007 NEON_ENCODE (SCALAR, inst);
14008 neon_mul_mac (et, neon_quad (rs));
14012 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14013 affected if we specify unsigned args. */
14014 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14019 do_neon_fmac (void)
14021 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14024 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14027 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14033 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14034 struct neon_type_el et = neon_check_type (3, rs,
14035 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14036 neon_three_same (neon_quad (rs), 0, et.size);
14039 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14040 same types as the MAC equivalents. The polynomial type for this instruction
14041 is encoded the same as the integer type. */
14046 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14049 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14052 if (inst.operands[2].isscalar)
14053 do_neon_mac_maybe_scalar ();
14055 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14059 do_neon_qdmulh (void)
14061 if (inst.operands[2].isscalar)
14063 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14064 struct neon_type_el et = neon_check_type (3, rs,
14065 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14066 NEON_ENCODE (SCALAR, inst);
14067 neon_mul_mac (et, neon_quad (rs));
14071 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14072 struct neon_type_el et = neon_check_type (3, rs,
14073 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14074 NEON_ENCODE (INTEGER, inst);
14075 /* The U bit (rounding) comes from bit mask. */
14076 neon_three_same (neon_quad (rs), 0, et.size);
14081 do_neon_fcmp_absolute (void)
14083 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14084 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14085 /* Size field comes from bit mask. */
14086 neon_three_same (neon_quad (rs), 1, -1);
14090 do_neon_fcmp_absolute_inv (void)
14092 neon_exchange_operands ();
14093 do_neon_fcmp_absolute ();
14097 do_neon_step (void)
14099 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14100 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14101 neon_three_same (neon_quad (rs), 0, -1);
14105 do_neon_abs_neg (void)
14107 enum neon_shape rs;
14108 struct neon_type_el et;
14110 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14113 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14116 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14117 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14119 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14120 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14121 inst.instruction |= LOW4 (inst.operands[1].reg);
14122 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14123 inst.instruction |= neon_quad (rs) << 6;
14124 inst.instruction |= (et.type == NT_float) << 10;
14125 inst.instruction |= neon_logbits (et.size) << 18;
14127 neon_dp_fixup (&inst);
14133 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14134 struct neon_type_el et = neon_check_type (2, rs,
14135 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14136 int imm = inst.operands[2].imm;
14137 constraint (imm < 0 || (unsigned)imm >= et.size,
14138 _("immediate out of range for insert"));
14139 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14145 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14146 struct neon_type_el et = neon_check_type (2, rs,
14147 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14148 int imm = inst.operands[2].imm;
14149 constraint (imm < 1 || (unsigned)imm > et.size,
14150 _("immediate out of range for insert"));
14151 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14155 do_neon_qshlu_imm (void)
14157 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14158 struct neon_type_el et = neon_check_type (2, rs,
14159 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14160 int imm = inst.operands[2].imm;
14161 constraint (imm < 0 || (unsigned)imm >= et.size,
14162 _("immediate out of range for shift"));
14163 /* Only encodes the 'U present' variant of the instruction.
14164 In this case, signed types have OP (bit 8) set to 0.
14165 Unsigned types have OP set to 1. */
14166 inst.instruction |= (et.type == NT_unsigned) << 8;
14167 /* The rest of the bits are the same as other immediate shifts. */
14168 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14172 do_neon_qmovn (void)
14174 struct neon_type_el et = neon_check_type (2, NS_DQ,
14175 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14176 /* Saturating move where operands can be signed or unsigned, and the
14177 destination has the same signedness. */
14178 NEON_ENCODE (INTEGER, inst);
14179 if (et.type == NT_unsigned)
14180 inst.instruction |= 0xc0;
14182 inst.instruction |= 0x80;
14183 neon_two_same (0, 1, et.size / 2);
14187 do_neon_qmovun (void)
14189 struct neon_type_el et = neon_check_type (2, NS_DQ,
14190 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14191 /* Saturating move with unsigned results. Operands must be signed. */
14192 NEON_ENCODE (INTEGER, inst);
14193 neon_two_same (0, 1, et.size / 2);
14197 do_neon_rshift_sat_narrow (void)
14199 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14200 or unsigned. If operands are unsigned, results must also be unsigned. */
14201 struct neon_type_el et = neon_check_type (2, NS_DQI,
14202 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14203 int imm = inst.operands[2].imm;
14204 /* This gets the bounds check, size encoding and immediate bits calculation
14208 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14209 VQMOVN.I<size> <Dd>, <Qm>. */
14212 inst.operands[2].present = 0;
14213 inst.instruction = N_MNEM_vqmovn;
14218 constraint (imm < 1 || (unsigned)imm > et.size,
14219 _("immediate out of range"));
14220 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14224 do_neon_rshift_sat_narrow_u (void)
14226 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14227 or unsigned. If operands are unsigned, results must also be unsigned. */
14228 struct neon_type_el et = neon_check_type (2, NS_DQI,
14229 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14230 int imm = inst.operands[2].imm;
14231 /* This gets the bounds check, size encoding and immediate bits calculation
14235 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14236 VQMOVUN.I<size> <Dd>, <Qm>. */
14239 inst.operands[2].present = 0;
14240 inst.instruction = N_MNEM_vqmovun;
14245 constraint (imm < 1 || (unsigned)imm > et.size,
14246 _("immediate out of range"));
14247 /* FIXME: The manual is kind of unclear about what value U should have in
14248 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14250 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14254 do_neon_movn (void)
14256 struct neon_type_el et = neon_check_type (2, NS_DQ,
14257 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14258 NEON_ENCODE (INTEGER, inst);
14259 neon_two_same (0, 1, et.size / 2);
14263 do_neon_rshift_narrow (void)
14265 struct neon_type_el et = neon_check_type (2, NS_DQI,
14266 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14267 int imm = inst.operands[2].imm;
14268 /* This gets the bounds check, size encoding and immediate bits calculation
14272 /* If immediate is zero then we are a pseudo-instruction for
14273 VMOVN.I<size> <Dd>, <Qm> */
14276 inst.operands[2].present = 0;
14277 inst.instruction = N_MNEM_vmovn;
14282 constraint (imm < 1 || (unsigned)imm > et.size,
14283 _("immediate out of range for narrowing operation"));
14284 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14288 do_neon_shll (void)
14290 /* FIXME: Type checking when lengthening. */
14291 struct neon_type_el et = neon_check_type (2, NS_QDI,
14292 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14293 unsigned imm = inst.operands[2].imm;
14295 if (imm == et.size)
14297 /* Maximum shift variant. */
14298 NEON_ENCODE (INTEGER, inst);
14299 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14300 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14301 inst.instruction |= LOW4 (inst.operands[1].reg);
14302 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14303 inst.instruction |= neon_logbits (et.size) << 18;
14305 neon_dp_fixup (&inst);
14309 /* A more-specific type check for non-max versions. */
14310 et = neon_check_type (2, NS_QDI,
14311 N_EQK | N_DBL, N_SU_32 | N_KEY);
14312 NEON_ENCODE (IMMED, inst);
14313 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14317 /* Check the various types for the VCVT instruction, and return which version
14318 the current instruction is. */
14321 neon_cvt_flavour (enum neon_shape rs)
14323 #define CVT_VAR(C,X,Y) \
14324 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14325 if (et.type != NT_invtype) \
14327 inst.error = NULL; \
14330 struct neon_type_el et;
14331 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14332 || rs == NS_FF) ? N_VFP : 0;
14333 /* The instruction versions which take an immediate take one register
14334 argument, which is extended to the width of the full register. Thus the
14335 "source" and "destination" registers must have the same width. Hack that
14336 here by making the size equal to the key (wider, in this case) operand. */
14337 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14339 CVT_VAR (0, N_S32, N_F32);
14340 CVT_VAR (1, N_U32, N_F32);
14341 CVT_VAR (2, N_F32, N_S32);
14342 CVT_VAR (3, N_F32, N_U32);
14343 /* Half-precision conversions. */
14344 CVT_VAR (4, N_F32, N_F16);
14345 CVT_VAR (5, N_F16, N_F32);
14349 /* VFP instructions. */
14350 CVT_VAR (6, N_F32, N_F64);
14351 CVT_VAR (7, N_F64, N_F32);
14352 CVT_VAR (8, N_S32, N_F64 | key);
14353 CVT_VAR (9, N_U32, N_F64 | key);
14354 CVT_VAR (10, N_F64 | key, N_S32);
14355 CVT_VAR (11, N_F64 | key, N_U32);
14356 /* VFP instructions with bitshift. */
14357 CVT_VAR (12, N_F32 | key, N_S16);
14358 CVT_VAR (13, N_F32 | key, N_U16);
14359 CVT_VAR (14, N_F64 | key, N_S16);
14360 CVT_VAR (15, N_F64 | key, N_U16);
14361 CVT_VAR (16, N_S16, N_F32 | key);
14362 CVT_VAR (17, N_U16, N_F32 | key);
14363 CVT_VAR (18, N_S16, N_F64 | key);
14364 CVT_VAR (19, N_U16, N_F64 | key);
14370 /* Neon-syntax VFP conversions. */
14373 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14375 const char *opname = 0;
14377 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14379 /* Conversions with immediate bitshift. */
14380 const char *enc[] =
14404 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14406 opname = enc[flavour];
14407 constraint (inst.operands[0].reg != inst.operands[1].reg,
14408 _("operands 0 and 1 must be the same register"));
14409 inst.operands[1] = inst.operands[2];
14410 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14415 /* Conversions without bitshift. */
14416 const char *enc[] =
14432 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14433 opname = enc[flavour];
14437 do_vfp_nsyn_opcode (opname);
14441 do_vfp_nsyn_cvtz (void)
14443 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14444 int flavour = neon_cvt_flavour (rs);
14445 const char *enc[] =
14459 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14460 do_vfp_nsyn_opcode (enc[flavour]);
14464 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14466 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14467 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14468 int flavour = neon_cvt_flavour (rs);
14470 /* PR11109: Handle round-to-zero for VCVT conversions. */
14472 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14473 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14474 && (rs == NS_FD || rs == NS_FF))
14476 do_vfp_nsyn_cvtz ();
14480 /* VFP rather than Neon conversions. */
14483 do_vfp_nsyn_cvt (rs, flavour);
14493 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14495 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14498 /* Fixed-point conversion with #0 immediate is encoded as an
14499 integer conversion. */
14500 if (inst.operands[2].present && inst.operands[2].imm == 0)
14502 immbits = 32 - inst.operands[2].imm;
14503 NEON_ENCODE (IMMED, inst);
14505 inst.instruction |= enctab[flavour];
14506 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14507 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14508 inst.instruction |= LOW4 (inst.operands[1].reg);
14509 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14510 inst.instruction |= neon_quad (rs) << 6;
14511 inst.instruction |= 1 << 21;
14512 inst.instruction |= immbits << 16;
14514 neon_dp_fixup (&inst);
14522 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14524 NEON_ENCODE (INTEGER, inst);
14526 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14530 inst.instruction |= enctab[flavour];
14532 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14533 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14534 inst.instruction |= LOW4 (inst.operands[1].reg);
14535 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14536 inst.instruction |= neon_quad (rs) << 6;
14537 inst.instruction |= 2 << 18;
14539 neon_dp_fixup (&inst);
14543 /* Half-precision conversions for Advanced SIMD -- neon. */
14548 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14550 as_bad (_("operand size must match register width"));
14555 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14557 as_bad (_("operand size must match register width"));
14562 inst.instruction = 0x3b60600;
14564 inst.instruction = 0x3b60700;
14566 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14567 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14568 inst.instruction |= LOW4 (inst.operands[1].reg);
14569 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14570 neon_dp_fixup (&inst);
14574 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14575 do_vfp_nsyn_cvt (rs, flavour);
14580 do_neon_cvtr (void)
14582 do_neon_cvt_1 (FALSE);
14588 do_neon_cvt_1 (TRUE);
14592 do_neon_cvtb (void)
14594 inst.instruction = 0xeb20a40;
14596 /* The sizes are attached to the mnemonic. */
14597 if (inst.vectype.el[0].type != NT_invtype
14598 && inst.vectype.el[0].size == 16)
14599 inst.instruction |= 0x00010000;
14601 /* Programmer's syntax: the sizes are attached to the operands. */
14602 else if (inst.operands[0].vectype.type != NT_invtype
14603 && inst.operands[0].vectype.size == 16)
14604 inst.instruction |= 0x00010000;
14606 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14607 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14608 do_vfp_cond_or_thumb ();
14613 do_neon_cvtt (void)
14616 inst.instruction |= 0x80;
14620 neon_move_immediate (void)
14622 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14623 struct neon_type_el et = neon_check_type (2, rs,
14624 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14625 unsigned immlo, immhi = 0, immbits;
14626 int op, cmode, float_p;
14628 constraint (et.type == NT_invtype,
14629 _("operand size must be specified for immediate VMOV"));
14631 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14632 op = (inst.instruction & (1 << 5)) != 0;
14634 immlo = inst.operands[1].imm;
14635 if (inst.operands[1].regisimm)
14636 immhi = inst.operands[1].reg;
14638 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14639 _("immediate has bits set outside the operand size"));
14641 float_p = inst.operands[1].immisfloat;
14643 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14644 et.size, et.type)) == FAIL)
14646 /* Invert relevant bits only. */
14647 neon_invert_size (&immlo, &immhi, et.size);
14648 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14649 with one or the other; those cases are caught by
14650 neon_cmode_for_move_imm. */
14652 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14653 &op, et.size, et.type)) == FAIL)
14655 first_error (_("immediate out of range"));
14660 inst.instruction &= ~(1 << 5);
14661 inst.instruction |= op << 5;
14663 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14664 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14665 inst.instruction |= neon_quad (rs) << 6;
14666 inst.instruction |= cmode << 8;
14668 neon_write_immbits (immbits);
14674 if (inst.operands[1].isreg)
14676 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14678 NEON_ENCODE (INTEGER, inst);
14679 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14680 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14681 inst.instruction |= LOW4 (inst.operands[1].reg);
14682 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14683 inst.instruction |= neon_quad (rs) << 6;
14687 NEON_ENCODE (IMMED, inst);
14688 neon_move_immediate ();
14691 neon_dp_fixup (&inst);
14694 /* Encode instructions of form:
14696 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14697 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14700 neon_mixed_length (struct neon_type_el et, unsigned size)
14702 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14703 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14704 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14705 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14706 inst.instruction |= LOW4 (inst.operands[2].reg);
14707 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14708 inst.instruction |= (et.type == NT_unsigned) << 24;
14709 inst.instruction |= neon_logbits (size) << 20;
14711 neon_dp_fixup (&inst);
14715 do_neon_dyadic_long (void)
14717 /* FIXME: Type checking for lengthening op. */
14718 struct neon_type_el et = neon_check_type (3, NS_QDD,
14719 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14720 neon_mixed_length (et, et.size);
14724 do_neon_abal (void)
14726 struct neon_type_el et = neon_check_type (3, NS_QDD,
14727 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14728 neon_mixed_length (et, et.size);
14732 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14734 if (inst.operands[2].isscalar)
14736 struct neon_type_el et = neon_check_type (3, NS_QDS,
14737 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14738 NEON_ENCODE (SCALAR, inst);
14739 neon_mul_mac (et, et.type == NT_unsigned);
14743 struct neon_type_el et = neon_check_type (3, NS_QDD,
14744 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14745 NEON_ENCODE (INTEGER, inst);
14746 neon_mixed_length (et, et.size);
14751 do_neon_mac_maybe_scalar_long (void)
14753 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14757 do_neon_dyadic_wide (void)
14759 struct neon_type_el et = neon_check_type (3, NS_QQD,
14760 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14761 neon_mixed_length (et, et.size);
14765 do_neon_dyadic_narrow (void)
14767 struct neon_type_el et = neon_check_type (3, NS_QDD,
14768 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14769 /* Operand sign is unimportant, and the U bit is part of the opcode,
14770 so force the operand type to integer. */
14771 et.type = NT_integer;
14772 neon_mixed_length (et, et.size / 2);
14776 do_neon_mul_sat_scalar_long (void)
14778 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14782 do_neon_vmull (void)
14784 if (inst.operands[2].isscalar)
14785 do_neon_mac_maybe_scalar_long ();
14788 struct neon_type_el et = neon_check_type (3, NS_QDD,
14789 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14790 if (et.type == NT_poly)
14791 NEON_ENCODE (POLY, inst);
14793 NEON_ENCODE (INTEGER, inst);
14794 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14795 zero. Should be OK as-is. */
14796 neon_mixed_length (et, et.size);
14803 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14804 struct neon_type_el et = neon_check_type (3, rs,
14805 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14806 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14808 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14809 _("shift out of range"));
14810 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14811 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14812 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14813 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14814 inst.instruction |= LOW4 (inst.operands[2].reg);
14815 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14816 inst.instruction |= neon_quad (rs) << 6;
14817 inst.instruction |= imm << 8;
14819 neon_dp_fixup (&inst);
14825 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14826 struct neon_type_el et = neon_check_type (2, rs,
14827 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14828 unsigned op = (inst.instruction >> 7) & 3;
14829 /* N (width of reversed regions) is encoded as part of the bitmask. We
14830 extract it here to check the elements to be reversed are smaller.
14831 Otherwise we'd get a reserved instruction. */
14832 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14833 gas_assert (elsize != 0);
14834 constraint (et.size >= elsize,
14835 _("elements must be smaller than reversal region"));
14836 neon_two_same (neon_quad (rs), 1, et.size);
14842 if (inst.operands[1].isscalar)
14844 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14845 struct neon_type_el et = neon_check_type (2, rs,
14846 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14847 unsigned sizebits = et.size >> 3;
14848 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14849 int logsize = neon_logbits (et.size);
14850 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14852 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14855 NEON_ENCODE (SCALAR, inst);
14856 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14857 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14858 inst.instruction |= LOW4 (dm);
14859 inst.instruction |= HI1 (dm) << 5;
14860 inst.instruction |= neon_quad (rs) << 6;
14861 inst.instruction |= x << 17;
14862 inst.instruction |= sizebits << 16;
14864 neon_dp_fixup (&inst);
14868 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14869 struct neon_type_el et = neon_check_type (2, rs,
14870 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14871 /* Duplicate ARM register to lanes of vector. */
14872 NEON_ENCODE (ARMREG, inst);
14875 case 8: inst.instruction |= 0x400000; break;
14876 case 16: inst.instruction |= 0x000020; break;
14877 case 32: inst.instruction |= 0x000000; break;
14880 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14881 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14882 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14883 inst.instruction |= neon_quad (rs) << 21;
14884 /* The encoding for this instruction is identical for the ARM and Thumb
14885 variants, except for the condition field. */
14886 do_vfp_cond_or_thumb ();
14890 /* VMOV has particularly many variations. It can be one of:
14891 0. VMOV<c><q> <Qd>, <Qm>
14892 1. VMOV<c><q> <Dd>, <Dm>
14893 (Register operations, which are VORR with Rm = Rn.)
14894 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14895 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14897 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14898 (ARM register to scalar.)
14899 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14900 (Two ARM registers to vector.)
14901 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14902 (Scalar to ARM register.)
14903 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14904 (Vector to two ARM registers.)
14905 8. VMOV.F32 <Sd>, <Sm>
14906 9. VMOV.F64 <Dd>, <Dm>
14907 (VFP register moves.)
14908 10. VMOV.F32 <Sd>, #imm
14909 11. VMOV.F64 <Dd>, #imm
14910 (VFP float immediate load.)
14911 12. VMOV <Rd>, <Sm>
14912 (VFP single to ARM reg.)
14913 13. VMOV <Sd>, <Rm>
14914 (ARM reg to VFP single.)
14915 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14916 (Two ARM regs to two VFP singles.)
14917 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14918 (Two VFP singles to two ARM regs.)
14920 These cases can be disambiguated using neon_select_shape, except cases 1/9
14921 and 3/11 which depend on the operand type too.
14923 All the encoded bits are hardcoded by this function.
14925 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14926 Cases 5, 7 may be used with VFPv2 and above.
14928 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14929 can specify a type where it doesn't make sense to, and is ignored). */
14934 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14935 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14937 struct neon_type_el et;
14938 const char *ldconst = 0;
14942 case NS_DD: /* case 1/9. */
14943 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14944 /* It is not an error here if no type is given. */
14946 if (et.type == NT_float && et.size == 64)
14948 do_vfp_nsyn_opcode ("fcpyd");
14951 /* fall through. */
14953 case NS_QQ: /* case 0/1. */
14955 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14957 /* The architecture manual I have doesn't explicitly state which
14958 value the U bit should have for register->register moves, but
14959 the equivalent VORR instruction has U = 0, so do that. */
14960 inst.instruction = 0x0200110;
14961 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14962 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14963 inst.instruction |= LOW4 (inst.operands[1].reg);
14964 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14965 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14966 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14967 inst.instruction |= neon_quad (rs) << 6;
14969 neon_dp_fixup (&inst);
14973 case NS_DI: /* case 3/11. */
14974 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14976 if (et.type == NT_float && et.size == 64)
14978 /* case 11 (fconstd). */
14979 ldconst = "fconstd";
14980 goto encode_fconstd;
14982 /* fall through. */
14984 case NS_QI: /* case 2/3. */
14985 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14987 inst.instruction = 0x0800010;
14988 neon_move_immediate ();
14989 neon_dp_fixup (&inst);
14992 case NS_SR: /* case 4. */
14994 unsigned bcdebits = 0;
14996 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
14997 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
14999 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15000 logsize = neon_logbits (et.size);
15002 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15004 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15005 && et.size != 32, _(BAD_FPU));
15006 constraint (et.type == NT_invtype, _("bad type for scalar"));
15007 constraint (x >= 64 / et.size, _("scalar index out of range"));
15011 case 8: bcdebits = 0x8; break;
15012 case 16: bcdebits = 0x1; break;
15013 case 32: bcdebits = 0x0; break;
15017 bcdebits |= x << logsize;
15019 inst.instruction = 0xe000b10;
15020 do_vfp_cond_or_thumb ();
15021 inst.instruction |= LOW4 (dn) << 16;
15022 inst.instruction |= HI1 (dn) << 7;
15023 inst.instruction |= inst.operands[1].reg << 12;
15024 inst.instruction |= (bcdebits & 3) << 5;
15025 inst.instruction |= (bcdebits >> 2) << 21;
15029 case NS_DRR: /* case 5 (fmdrr). */
15030 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15033 inst.instruction = 0xc400b10;
15034 do_vfp_cond_or_thumb ();
15035 inst.instruction |= LOW4 (inst.operands[0].reg);
15036 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15037 inst.instruction |= inst.operands[1].reg << 12;
15038 inst.instruction |= inst.operands[2].reg << 16;
15041 case NS_RS: /* case 6. */
15044 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15045 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15046 unsigned abcdebits = 0;
15048 et = neon_check_type (2, NS_NULL,
15049 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15050 logsize = neon_logbits (et.size);
15052 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15054 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15055 && et.size != 32, _(BAD_FPU));
15056 constraint (et.type == NT_invtype, _("bad type for scalar"));
15057 constraint (x >= 64 / et.size, _("scalar index out of range"));
15061 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15062 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15063 case 32: abcdebits = 0x00; break;
15067 abcdebits |= x << logsize;
15068 inst.instruction = 0xe100b10;
15069 do_vfp_cond_or_thumb ();
15070 inst.instruction |= LOW4 (dn) << 16;
15071 inst.instruction |= HI1 (dn) << 7;
15072 inst.instruction |= inst.operands[0].reg << 12;
15073 inst.instruction |= (abcdebits & 3) << 5;
15074 inst.instruction |= (abcdebits >> 2) << 21;
15078 case NS_RRD: /* case 7 (fmrrd). */
15079 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15082 inst.instruction = 0xc500b10;
15083 do_vfp_cond_or_thumb ();
15084 inst.instruction |= inst.operands[0].reg << 12;
15085 inst.instruction |= inst.operands[1].reg << 16;
15086 inst.instruction |= LOW4 (inst.operands[2].reg);
15087 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15090 case NS_FF: /* case 8 (fcpys). */
15091 do_vfp_nsyn_opcode ("fcpys");
15094 case NS_FI: /* case 10 (fconsts). */
15095 ldconst = "fconsts";
15097 if (is_quarter_float (inst.operands[1].imm))
15099 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15100 do_vfp_nsyn_opcode (ldconst);
15103 first_error (_("immediate out of range"));
15106 case NS_RF: /* case 12 (fmrs). */
15107 do_vfp_nsyn_opcode ("fmrs");
15110 case NS_FR: /* case 13 (fmsr). */
15111 do_vfp_nsyn_opcode ("fmsr");
15114 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15115 (one of which is a list), but we have parsed four. Do some fiddling to
15116 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15118 case NS_RRFF: /* case 14 (fmrrs). */
15119 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15120 _("VFP registers must be adjacent"));
15121 inst.operands[2].imm = 2;
15122 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15123 do_vfp_nsyn_opcode ("fmrrs");
15126 case NS_FFRR: /* case 15 (fmsrr). */
15127 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15128 _("VFP registers must be adjacent"));
15129 inst.operands[1] = inst.operands[2];
15130 inst.operands[2] = inst.operands[3];
15131 inst.operands[0].imm = 2;
15132 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15133 do_vfp_nsyn_opcode ("fmsrr");
15142 do_neon_rshift_round_imm (void)
15144 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15145 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15146 int imm = inst.operands[2].imm;
15148 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15151 inst.operands[2].present = 0;
15156 constraint (imm < 1 || (unsigned)imm > et.size,
15157 _("immediate out of range for shift"));
15158 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15163 do_neon_movl (void)
15165 struct neon_type_el et = neon_check_type (2, NS_QD,
15166 N_EQK | N_DBL, N_SU_32 | N_KEY);
15167 unsigned sizebits = et.size >> 3;
15168 inst.instruction |= sizebits << 19;
15169 neon_two_same (0, et.type == NT_unsigned, -1);
15175 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15176 struct neon_type_el et = neon_check_type (2, rs,
15177 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15178 NEON_ENCODE (INTEGER, inst);
15179 neon_two_same (neon_quad (rs), 1, et.size);
15183 do_neon_zip_uzp (void)
15185 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15186 struct neon_type_el et = neon_check_type (2, rs,
15187 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15188 if (rs == NS_DD && et.size == 32)
15190 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15191 inst.instruction = N_MNEM_vtrn;
15195 neon_two_same (neon_quad (rs), 1, et.size);
15199 do_neon_sat_abs_neg (void)
15201 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15202 struct neon_type_el et = neon_check_type (2, rs,
15203 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15204 neon_two_same (neon_quad (rs), 1, et.size);
15208 do_neon_pair_long (void)
15210 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15211 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15212 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15213 inst.instruction |= (et.type == NT_unsigned) << 7;
15214 neon_two_same (neon_quad (rs), 1, et.size);
15218 do_neon_recip_est (void)
15220 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15221 struct neon_type_el et = neon_check_type (2, rs,
15222 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15223 inst.instruction |= (et.type == NT_float) << 8;
15224 neon_two_same (neon_quad (rs), 1, et.size);
15230 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15231 struct neon_type_el et = neon_check_type (2, rs,
15232 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15233 neon_two_same (neon_quad (rs), 1, et.size);
15239 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15240 struct neon_type_el et = neon_check_type (2, rs,
15241 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15242 neon_two_same (neon_quad (rs), 1, et.size);
15248 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15249 struct neon_type_el et = neon_check_type (2, rs,
15250 N_EQK | N_INT, N_8 | N_KEY);
15251 neon_two_same (neon_quad (rs), 1, et.size);
15257 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15258 neon_two_same (neon_quad (rs), 1, -1);
15262 do_neon_tbl_tbx (void)
15264 unsigned listlenbits;
15265 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15267 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15269 first_error (_("bad list length for table lookup"));
15273 listlenbits = inst.operands[1].imm - 1;
15274 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15275 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15276 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15277 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15278 inst.instruction |= LOW4 (inst.operands[2].reg);
15279 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15280 inst.instruction |= listlenbits << 8;
15282 neon_dp_fixup (&inst);
15286 do_neon_ldm_stm (void)
15288 /* P, U and L bits are part of bitmask. */
15289 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15290 unsigned offsetbits = inst.operands[1].imm * 2;
15292 if (inst.operands[1].issingle)
15294 do_vfp_nsyn_ldm_stm (is_dbmode);
15298 constraint (is_dbmode && !inst.operands[0].writeback,
15299 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15301 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15302 _("register list must contain at least 1 and at most 16 "
15305 inst.instruction |= inst.operands[0].reg << 16;
15306 inst.instruction |= inst.operands[0].writeback << 21;
15307 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15308 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15310 inst.instruction |= offsetbits;
15312 do_vfp_cond_or_thumb ();
15316 do_neon_ldr_str (void)
15318 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15320 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15321 And is UNPREDICTABLE in thumb mode. */
15323 && inst.operands[1].reg == REG_PC
15324 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15326 if (!thumb_mode && warn_on_deprecated)
15327 as_warn (_("Use of PC here is deprecated"));
15329 inst.error = _("Use of PC here is UNPREDICTABLE");
15332 if (inst.operands[0].issingle)
15335 do_vfp_nsyn_opcode ("flds");
15337 do_vfp_nsyn_opcode ("fsts");
15342 do_vfp_nsyn_opcode ("fldd");
15344 do_vfp_nsyn_opcode ("fstd");
15348 /* "interleave" version also handles non-interleaving register VLD1/VST1
15352 do_neon_ld_st_interleave (void)
15354 struct neon_type_el et = neon_check_type (1, NS_NULL,
15355 N_8 | N_16 | N_32 | N_64);
15356 unsigned alignbits = 0;
15358 /* The bits in this table go:
15359 0: register stride of one (0) or two (1)
15360 1,2: register list length, minus one (1, 2, 3, 4).
15361 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15362 We use -1 for invalid entries. */
15363 const int typetable[] =
15365 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15366 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15367 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15368 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15372 if (et.type == NT_invtype)
15375 if (inst.operands[1].immisalign)
15376 switch (inst.operands[1].imm >> 8)
15378 case 64: alignbits = 1; break;
15380 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15381 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15382 goto bad_alignment;
15386 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15387 goto bad_alignment;
15392 first_error (_("bad alignment"));
15396 inst.instruction |= alignbits << 4;
15397 inst.instruction |= neon_logbits (et.size) << 6;
15399 /* Bits [4:6] of the immediate in a list specifier encode register stride
15400 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15401 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15402 up the right value for "type" in a table based on this value and the given
15403 list style, then stick it back. */
15404 idx = ((inst.operands[0].imm >> 4) & 7)
15405 | (((inst.instruction >> 8) & 3) << 3);
15407 typebits = typetable[idx];
15409 constraint (typebits == -1, _("bad list type for instruction"));
15411 inst.instruction &= ~0xf00;
15412 inst.instruction |= typebits << 8;
15415 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15416 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15417 otherwise. The variable arguments are a list of pairs of legal (size, align)
15418 values, terminated with -1. */
15421 neon_alignment_bit (int size, int align, int *do_align, ...)
15424 int result = FAIL, thissize, thisalign;
15426 if (!inst.operands[1].immisalign)
15432 va_start (ap, do_align);
15436 thissize = va_arg (ap, int);
15437 if (thissize == -1)
15439 thisalign = va_arg (ap, int);
15441 if (size == thissize && align == thisalign)
15444 while (result != SUCCESS);
15448 if (result == SUCCESS)
15451 first_error (_("unsupported alignment for instruction"));
15457 do_neon_ld_st_lane (void)
15459 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15460 int align_good, do_align = 0;
15461 int logsize = neon_logbits (et.size);
15462 int align = inst.operands[1].imm >> 8;
15463 int n = (inst.instruction >> 8) & 3;
15464 int max_el = 64 / et.size;
15466 if (et.type == NT_invtype)
15469 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15470 _("bad list length"));
15471 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15472 _("scalar index out of range"));
15473 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15475 _("stride of 2 unavailable when element size is 8"));
15479 case 0: /* VLD1 / VST1. */
15480 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15482 if (align_good == FAIL)
15486 unsigned alignbits = 0;
15489 case 16: alignbits = 0x1; break;
15490 case 32: alignbits = 0x3; break;
15493 inst.instruction |= alignbits << 4;
15497 case 1: /* VLD2 / VST2. */
15498 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15500 if (align_good == FAIL)
15503 inst.instruction |= 1 << 4;
15506 case 2: /* VLD3 / VST3. */
15507 constraint (inst.operands[1].immisalign,
15508 _("can't use alignment with this instruction"));
15511 case 3: /* VLD4 / VST4. */
15512 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15513 16, 64, 32, 64, 32, 128, -1);
15514 if (align_good == FAIL)
15518 unsigned alignbits = 0;
15521 case 8: alignbits = 0x1; break;
15522 case 16: alignbits = 0x1; break;
15523 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15526 inst.instruction |= alignbits << 4;
15533 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15534 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15535 inst.instruction |= 1 << (4 + logsize);
15537 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15538 inst.instruction |= logsize << 10;
15541 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15544 do_neon_ld_dup (void)
15546 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15547 int align_good, do_align = 0;
15549 if (et.type == NT_invtype)
15552 switch ((inst.instruction >> 8) & 3)
15554 case 0: /* VLD1. */
15555 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15556 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15557 &do_align, 16, 16, 32, 32, -1);
15558 if (align_good == FAIL)
15560 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15563 case 2: inst.instruction |= 1 << 5; break;
15564 default: first_error (_("bad list length")); return;
15566 inst.instruction |= neon_logbits (et.size) << 6;
15569 case 1: /* VLD2. */
15570 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15571 &do_align, 8, 16, 16, 32, 32, 64, -1);
15572 if (align_good == FAIL)
15574 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15575 _("bad list length"));
15576 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15577 inst.instruction |= 1 << 5;
15578 inst.instruction |= neon_logbits (et.size) << 6;
15581 case 2: /* VLD3. */
15582 constraint (inst.operands[1].immisalign,
15583 _("can't use alignment with this instruction"));
15584 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15585 _("bad list length"));
15586 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15587 inst.instruction |= 1 << 5;
15588 inst.instruction |= neon_logbits (et.size) << 6;
15591 case 3: /* VLD4. */
15593 int align = inst.operands[1].imm >> 8;
15594 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15595 16, 64, 32, 64, 32, 128, -1);
15596 if (align_good == FAIL)
15598 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15599 _("bad list length"));
15600 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15601 inst.instruction |= 1 << 5;
15602 if (et.size == 32 && align == 128)
15603 inst.instruction |= 0x3 << 6;
15605 inst.instruction |= neon_logbits (et.size) << 6;
15612 inst.instruction |= do_align << 4;
15615 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15616 apart from bits [11:4]. */
15619 do_neon_ldx_stx (void)
15621 if (inst.operands[1].isreg)
15622 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15624 switch (NEON_LANE (inst.operands[0].imm))
15626 case NEON_INTERLEAVE_LANES:
15627 NEON_ENCODE (INTERLV, inst);
15628 do_neon_ld_st_interleave ();
15631 case NEON_ALL_LANES:
15632 NEON_ENCODE (DUP, inst);
15637 NEON_ENCODE (LANE, inst);
15638 do_neon_ld_st_lane ();
15641 /* L bit comes from bit mask. */
15642 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15643 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15644 inst.instruction |= inst.operands[1].reg << 16;
15646 if (inst.operands[1].postind)
15648 int postreg = inst.operands[1].imm & 0xf;
15649 constraint (!inst.operands[1].immisreg,
15650 _("post-index must be a register"));
15651 constraint (postreg == 0xd || postreg == 0xf,
15652 _("bad register for post-index"));
15653 inst.instruction |= postreg;
15655 else if (inst.operands[1].writeback)
15657 inst.instruction |= 0xd;
15660 inst.instruction |= 0xf;
15663 inst.instruction |= 0xf9000000;
15665 inst.instruction |= 0xf4000000;
15668 /* Overall per-instruction processing. */
15670 /* We need to be able to fix up arbitrary expressions in some statements.
15671 This is so that we can handle symbols that are an arbitrary distance from
15672 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15673 which returns part of an address in a form which will be valid for
15674 a data instruction. We do this by pushing the expression into a symbol
15675 in the expr_section, and creating a fix for that. */
15678 fix_new_arm (fragS * frag,
15692 /* Create an absolute valued symbol, so we have something to
15693 refer to in the object file. Unfortunately for us, gas's
15694 generic expression parsing will already have folded out
15695 any use of .set foo/.type foo %function that may have
15696 been used to set type information of the target location,
15697 that's being specified symbolically. We have to presume
15698 the user knows what they are doing. */
15702 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15704 symbol = symbol_find_or_make (name);
15705 S_SET_SEGMENT (symbol, absolute_section);
15706 symbol_set_frag (symbol, &zero_address_frag);
15707 S_SET_VALUE (symbol, exp->X_add_number);
15708 exp->X_op = O_symbol;
15709 exp->X_add_symbol = symbol;
15710 exp->X_add_number = 0;
15716 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15717 (enum bfd_reloc_code_real) reloc);
15721 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15722 pc_rel, (enum bfd_reloc_code_real) reloc);
15726 /* Mark whether the fix is to a THUMB instruction, or an ARM
15728 new_fix->tc_fix_data = thumb_mode;
15731 /* Create a frg for an instruction requiring relaxation. */
15733 output_relax_insn (void)
15739 /* The size of the instruction is unknown, so tie the debug info to the
15740 start of the instruction. */
15741 dwarf2_emit_insn (0);
15743 switch (inst.reloc.exp.X_op)
15746 sym = inst.reloc.exp.X_add_symbol;
15747 offset = inst.reloc.exp.X_add_number;
15751 offset = inst.reloc.exp.X_add_number;
15754 sym = make_expr_symbol (&inst.reloc.exp);
15758 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15759 inst.relax, sym, offset, NULL/*offset, opcode*/);
15760 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15763 /* Write a 32-bit thumb instruction to buf. */
15765 put_thumb32_insn (char * buf, unsigned long insn)
15767 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15768 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15772 output_inst (const char * str)
15778 as_bad ("%s -- `%s'", inst.error, str);
15783 output_relax_insn ();
15786 if (inst.size == 0)
15789 to = frag_more (inst.size);
15790 /* PR 9814: Record the thumb mode into the current frag so that we know
15791 what type of NOP padding to use, if necessary. We override any previous
15792 setting so that if the mode has changed then the NOPS that we use will
15793 match the encoding of the last instruction in the frag. */
15794 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15796 if (thumb_mode && (inst.size > THUMB_SIZE))
15798 gas_assert (inst.size == (2 * THUMB_SIZE));
15799 put_thumb32_insn (to, inst.instruction);
15801 else if (inst.size > INSN_SIZE)
15803 gas_assert (inst.size == (2 * INSN_SIZE));
15804 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15805 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15808 md_number_to_chars (to, inst.instruction, inst.size);
15810 if (inst.reloc.type != BFD_RELOC_UNUSED)
15811 fix_new_arm (frag_now, to - frag_now->fr_literal,
15812 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15815 dwarf2_emit_insn (inst.size);
15819 output_it_inst (int cond, int mask, char * to)
15821 unsigned long instruction = 0xbf00;
15824 instruction |= mask;
15825 instruction |= cond << 4;
15829 to = frag_more (2);
15831 dwarf2_emit_insn (2);
15835 md_number_to_chars (to, instruction, 2);
15840 /* Tag values used in struct asm_opcode's tag field. */
15843 OT_unconditional, /* Instruction cannot be conditionalized.
15844 The ARM condition field is still 0xE. */
15845 OT_unconditionalF, /* Instruction cannot be conditionalized
15846 and carries 0xF in its ARM condition field. */
15847 OT_csuffix, /* Instruction takes a conditional suffix. */
15848 OT_csuffixF, /* Some forms of the instruction take a conditional
15849 suffix, others place 0xF where the condition field
15851 OT_cinfix3, /* Instruction takes a conditional infix,
15852 beginning at character index 3. (In
15853 unified mode, it becomes a suffix.) */
15854 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15855 tsts, cmps, cmns, and teqs. */
15856 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15857 character index 3, even in unified mode. Used for
15858 legacy instructions where suffix and infix forms
15859 may be ambiguous. */
15860 OT_csuf_or_in3, /* Instruction takes either a conditional
15861 suffix or an infix at character index 3. */
15862 OT_odd_infix_unc, /* This is the unconditional variant of an
15863 instruction that takes a conditional infix
15864 at an unusual position. In unified mode,
15865 this variant will accept a suffix. */
15866 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15867 are the conditional variants of instructions that
15868 take conditional infixes in unusual positions.
15869 The infix appears at character index
15870 (tag - OT_odd_infix_0). These are not accepted
15871 in unified mode. */
15874 /* Subroutine of md_assemble, responsible for looking up the primary
15875 opcode from the mnemonic the user wrote. STR points to the
15876 beginning of the mnemonic.
15878 This is not simply a hash table lookup, because of conditional
15879 variants. Most instructions have conditional variants, which are
15880 expressed with a _conditional affix_ to the mnemonic. If we were
15881 to encode each conditional variant as a literal string in the opcode
15882 table, it would have approximately 20,000 entries.
15884 Most mnemonics take this affix as a suffix, and in unified syntax,
15885 'most' is upgraded to 'all'. However, in the divided syntax, some
15886 instructions take the affix as an infix, notably the s-variants of
15887 the arithmetic instructions. Of those instructions, all but six
15888 have the infix appear after the third character of the mnemonic.
15890 Accordingly, the algorithm for looking up primary opcodes given
15893 1. Look up the identifier in the opcode table.
15894 If we find a match, go to step U.
15896 2. Look up the last two characters of the identifier in the
15897 conditions table. If we find a match, look up the first N-2
15898 characters of the identifier in the opcode table. If we
15899 find a match, go to step CE.
15901 3. Look up the fourth and fifth characters of the identifier in
15902 the conditions table. If we find a match, extract those
15903 characters from the identifier, and look up the remaining
15904 characters in the opcode table. If we find a match, go
15909 U. Examine the tag field of the opcode structure, in case this is
15910 one of the six instructions with its conditional infix in an
15911 unusual place. If it is, the tag tells us where to find the
15912 infix; look it up in the conditions table and set inst.cond
15913 accordingly. Otherwise, this is an unconditional instruction.
15914 Again set inst.cond accordingly. Return the opcode structure.
15916 CE. Examine the tag field to make sure this is an instruction that
15917 should receive a conditional suffix. If it is not, fail.
15918 Otherwise, set inst.cond from the suffix we already looked up,
15919 and return the opcode structure.
15921 CM. Examine the tag field to make sure this is an instruction that
15922 should receive a conditional infix after the third character.
15923 If it is not, fail. Otherwise, undo the edits to the current
15924 line of input and proceed as for case CE. */
15926 static const struct asm_opcode *
15927 opcode_lookup (char **str)
15931 const struct asm_opcode *opcode;
15932 const struct asm_cond *cond;
15935 /* Scan up to the end of the mnemonic, which must end in white space,
15936 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15937 for (base = end = *str; *end != '\0'; end++)
15938 if (*end == ' ' || *end == '.')
15944 /* Handle a possible width suffix and/or Neon type suffix. */
15949 /* The .w and .n suffixes are only valid if the unified syntax is in
15951 if (unified_syntax && end[1] == 'w')
15953 else if (unified_syntax && end[1] == 'n')
15958 inst.vectype.elems = 0;
15960 *str = end + offset;
15962 if (end[offset] == '.')
15964 /* See if we have a Neon type suffix (possible in either unified or
15965 non-unified ARM syntax mode). */
15966 if (parse_neon_type (&inst.vectype, str) == FAIL)
15969 else if (end[offset] != '\0' && end[offset] != ' ')
15975 /* Look for unaffixed or special-case affixed mnemonic. */
15976 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15981 if (opcode->tag < OT_odd_infix_0)
15983 inst.cond = COND_ALWAYS;
15987 if (warn_on_deprecated && unified_syntax)
15988 as_warn (_("conditional infixes are deprecated in unified syntax"));
15989 affix = base + (opcode->tag - OT_odd_infix_0);
15990 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15993 inst.cond = cond->value;
15997 /* Cannot have a conditional suffix on a mnemonic of less than two
15999 if (end - base < 3)
16002 /* Look for suffixed mnemonic. */
16004 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16005 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16007 if (opcode && cond)
16010 switch (opcode->tag)
16012 case OT_cinfix3_legacy:
16013 /* Ignore conditional suffixes matched on infix only mnemonics. */
16017 case OT_cinfix3_deprecated:
16018 case OT_odd_infix_unc:
16019 if (!unified_syntax)
16021 /* else fall through */
16025 case OT_csuf_or_in3:
16026 inst.cond = cond->value;
16029 case OT_unconditional:
16030 case OT_unconditionalF:
16032 inst.cond = cond->value;
16035 /* Delayed diagnostic. */
16036 inst.error = BAD_COND;
16037 inst.cond = COND_ALWAYS;
16046 /* Cannot have a usual-position infix on a mnemonic of less than
16047 six characters (five would be a suffix). */
16048 if (end - base < 6)
16051 /* Look for infixed mnemonic in the usual position. */
16053 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16057 memcpy (save, affix, 2);
16058 memmove (affix, affix + 2, (end - affix) - 2);
16059 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16061 memmove (affix + 2, affix, (end - affix) - 2);
16062 memcpy (affix, save, 2);
16065 && (opcode->tag == OT_cinfix3
16066 || opcode->tag == OT_cinfix3_deprecated
16067 || opcode->tag == OT_csuf_or_in3
16068 || opcode->tag == OT_cinfix3_legacy))
16071 if (warn_on_deprecated && unified_syntax
16072 && (opcode->tag == OT_cinfix3
16073 || opcode->tag == OT_cinfix3_deprecated))
16074 as_warn (_("conditional infixes are deprecated in unified syntax"));
16076 inst.cond = cond->value;
16083 /* This function generates an initial IT instruction, leaving its block
16084 virtually open for the new instructions. Eventually,
16085 the mask will be updated by now_it_add_mask () each time
16086 a new instruction needs to be included in the IT block.
16087 Finally, the block is closed with close_automatic_it_block ().
16088 The block closure can be requested either from md_assemble (),
16089 a tencode (), or due to a label hook. */
16092 new_automatic_it_block (int cond)
16094 now_it.state = AUTOMATIC_IT_BLOCK;
16095 now_it.mask = 0x18;
16097 now_it.block_length = 1;
16098 mapping_state (MAP_THUMB);
16099 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16102 /* Close an automatic IT block.
16103 See comments in new_automatic_it_block (). */
16106 close_automatic_it_block (void)
16108 now_it.mask = 0x10;
16109 now_it.block_length = 0;
16112 /* Update the mask of the current automatically-generated IT
16113 instruction. See comments in new_automatic_it_block (). */
16116 now_it_add_mask (int cond)
16118 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16119 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16120 | ((bitvalue) << (nbit)))
16121 const int resulting_bit = (cond & 1);
16123 now_it.mask &= 0xf;
16124 now_it.mask = SET_BIT_VALUE (now_it.mask,
16126 (5 - now_it.block_length));
16127 now_it.mask = SET_BIT_VALUE (now_it.mask,
16129 ((5 - now_it.block_length) - 1) );
16130 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16133 #undef SET_BIT_VALUE
16136 /* The IT blocks handling machinery is accessed through the these functions:
16137 it_fsm_pre_encode () from md_assemble ()
16138 set_it_insn_type () optional, from the tencode functions
16139 set_it_insn_type_last () ditto
16140 in_it_block () ditto
16141 it_fsm_post_encode () from md_assemble ()
16142 force_automatic_it_block_close () from label habdling functions
16145 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16146 initializing the IT insn type with a generic initial value depending
16147 on the inst.condition.
16148 2) During the tencode function, two things may happen:
16149 a) The tencode function overrides the IT insn type by
16150 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16151 b) The tencode function queries the IT block state by
16152 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16154 Both set_it_insn_type and in_it_block run the internal FSM state
16155 handling function (handle_it_state), because: a) setting the IT insn
16156 type may incur in an invalid state (exiting the function),
16157 and b) querying the state requires the FSM to be updated.
16158 Specifically we want to avoid creating an IT block for conditional
16159 branches, so it_fsm_pre_encode is actually a guess and we can't
16160 determine whether an IT block is required until the tencode () routine
16161 has decided what type of instruction this actually it.
16162 Because of this, if set_it_insn_type and in_it_block have to be used,
16163 set_it_insn_type has to be called first.
16165 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16166 determines the insn IT type depending on the inst.cond code.
16167 When a tencode () routine encodes an instruction that can be
16168 either outside an IT block, or, in the case of being inside, has to be
16169 the last one, set_it_insn_type_last () will determine the proper
16170 IT instruction type based on the inst.cond code. Otherwise,
16171 set_it_insn_type can be called for overriding that logic or
16172 for covering other cases.
16174 Calling handle_it_state () may not transition the IT block state to
16175 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16176 still queried. Instead, if the FSM determines that the state should
16177 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16178 after the tencode () function: that's what it_fsm_post_encode () does.
16180 Since in_it_block () calls the state handling function to get an
16181 updated state, an error may occur (due to invalid insns combination).
16182 In that case, inst.error is set.
16183 Therefore, inst.error has to be checked after the execution of
16184 the tencode () routine.
16186 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16187 any pending state change (if any) that didn't take place in
16188 handle_it_state () as explained above. */
16191 it_fsm_pre_encode (void)
16193 if (inst.cond != COND_ALWAYS)
16194 inst.it_insn_type = INSIDE_IT_INSN;
16196 inst.it_insn_type = OUTSIDE_IT_INSN;
16198 now_it.state_handled = 0;
16201 /* IT state FSM handling function. */
16204 handle_it_state (void)
16206 now_it.state_handled = 1;
16208 switch (now_it.state)
16210 case OUTSIDE_IT_BLOCK:
16211 switch (inst.it_insn_type)
16213 case OUTSIDE_IT_INSN:
16216 case INSIDE_IT_INSN:
16217 case INSIDE_IT_LAST_INSN:
16218 if (thumb_mode == 0)
16221 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16222 as_tsktsk (_("Warning: conditional outside an IT block"\
16227 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16228 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16230 /* Automatically generate the IT instruction. */
16231 new_automatic_it_block (inst.cond);
16232 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16233 close_automatic_it_block ();
16237 inst.error = BAD_OUT_IT;
16243 case IF_INSIDE_IT_LAST_INSN:
16244 case NEUTRAL_IT_INSN:
16248 now_it.state = MANUAL_IT_BLOCK;
16249 now_it.block_length = 0;
16254 case AUTOMATIC_IT_BLOCK:
16255 /* Three things may happen now:
16256 a) We should increment current it block size;
16257 b) We should close current it block (closing insn or 4 insns);
16258 c) We should close current it block and start a new one (due
16259 to incompatible conditions or
16260 4 insns-length block reached). */
16262 switch (inst.it_insn_type)
16264 case OUTSIDE_IT_INSN:
16265 /* The closure of the block shall happen immediatelly,
16266 so any in_it_block () call reports the block as closed. */
16267 force_automatic_it_block_close ();
16270 case INSIDE_IT_INSN:
16271 case INSIDE_IT_LAST_INSN:
16272 case IF_INSIDE_IT_LAST_INSN:
16273 now_it.block_length++;
16275 if (now_it.block_length > 4
16276 || !now_it_compatible (inst.cond))
16278 force_automatic_it_block_close ();
16279 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16280 new_automatic_it_block (inst.cond);
16284 now_it_add_mask (inst.cond);
16287 if (now_it.state == AUTOMATIC_IT_BLOCK
16288 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16289 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16290 close_automatic_it_block ();
16293 case NEUTRAL_IT_INSN:
16294 now_it.block_length++;
16296 if (now_it.block_length > 4)
16297 force_automatic_it_block_close ();
16299 now_it_add_mask (now_it.cc & 1);
16303 close_automatic_it_block ();
16304 now_it.state = MANUAL_IT_BLOCK;
16309 case MANUAL_IT_BLOCK:
16311 /* Check conditional suffixes. */
16312 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16315 now_it.mask &= 0x1f;
16316 is_last = (now_it.mask == 0x10);
16318 switch (inst.it_insn_type)
16320 case OUTSIDE_IT_INSN:
16321 inst.error = BAD_NOT_IT;
16324 case INSIDE_IT_INSN:
16325 if (cond != inst.cond)
16327 inst.error = BAD_IT_COND;
16332 case INSIDE_IT_LAST_INSN:
16333 case IF_INSIDE_IT_LAST_INSN:
16334 if (cond != inst.cond)
16336 inst.error = BAD_IT_COND;
16341 inst.error = BAD_BRANCH;
16346 case NEUTRAL_IT_INSN:
16347 /* The BKPT instruction is unconditional even in an IT block. */
16351 inst.error = BAD_IT_IT;
16362 it_fsm_post_encode (void)
16366 if (!now_it.state_handled)
16367 handle_it_state ();
16369 is_last = (now_it.mask == 0x10);
16372 now_it.state = OUTSIDE_IT_BLOCK;
16378 force_automatic_it_block_close (void)
16380 if (now_it.state == AUTOMATIC_IT_BLOCK)
16382 close_automatic_it_block ();
16383 now_it.state = OUTSIDE_IT_BLOCK;
16391 if (!now_it.state_handled)
16392 handle_it_state ();
16394 return now_it.state != OUTSIDE_IT_BLOCK;
16398 md_assemble (char *str)
16401 const struct asm_opcode * opcode;
16403 /* Align the previous label if needed. */
16404 if (last_label_seen != NULL)
16406 symbol_set_frag (last_label_seen, frag_now);
16407 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16408 S_SET_SEGMENT (last_label_seen, now_seg);
16411 memset (&inst, '\0', sizeof (inst));
16412 inst.reloc.type = BFD_RELOC_UNUSED;
16414 opcode = opcode_lookup (&p);
16417 /* It wasn't an instruction, but it might be a register alias of
16418 the form alias .req reg, or a Neon .dn/.qn directive. */
16419 if (! create_register_alias (str, p)
16420 && ! create_neon_reg_alias (str, p))
16421 as_bad (_("bad instruction `%s'"), str);
16426 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16427 as_warn (_("s suffix on comparison instruction is deprecated"));
16429 /* The value which unconditional instructions should have in place of the
16430 condition field. */
16431 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16435 arm_feature_set variant;
16437 variant = cpu_variant;
16438 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16439 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16440 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16441 /* Check that this instruction is supported for this CPU. */
16442 if (!opcode->tvariant
16443 || (thumb_mode == 1
16444 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16446 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16449 if (inst.cond != COND_ALWAYS && !unified_syntax
16450 && opcode->tencode != do_t_branch)
16452 as_bad (_("Thumb does not support conditional execution"));
16456 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16458 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16459 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16460 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16462 /* Two things are addressed here.
16463 1) Implicit require narrow instructions on Thumb-1.
16464 This avoids relaxation accidentally introducing Thumb-2
16466 2) Reject wide instructions in non Thumb-2 cores. */
16467 if (inst.size_req == 0)
16469 else if (inst.size_req == 4)
16471 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16477 inst.instruction = opcode->tvalue;
16479 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16481 /* Prepare the it_insn_type for those encodings that don't set
16483 it_fsm_pre_encode ();
16485 opcode->tencode ();
16487 it_fsm_post_encode ();
16490 if (!(inst.error || inst.relax))
16492 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16493 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16494 if (inst.size_req && inst.size_req != inst.size)
16496 as_bad (_("cannot honor width suffix -- `%s'"), str);
16501 /* Something has gone badly wrong if we try to relax a fixed size
16503 gas_assert (inst.size_req == 0 || !inst.relax);
16505 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16506 *opcode->tvariant);
16507 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16508 set those bits when Thumb-2 32-bit instructions are seen. ie.
16509 anything other than bl/blx and v6-M instructions.
16510 This is overly pessimistic for relaxable instructions. */
16511 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16513 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16514 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16515 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16518 check_neon_suffixes;
16522 mapping_state (MAP_THUMB);
16525 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16529 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16530 is_bx = (opcode->aencode == do_bx);
16532 /* Check that this instruction is supported for this CPU. */
16533 if (!(is_bx && fix_v4bx)
16534 && !(opcode->avariant &&
16535 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16537 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16542 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16546 inst.instruction = opcode->avalue;
16547 if (opcode->tag == OT_unconditionalF)
16548 inst.instruction |= 0xF << 28;
16550 inst.instruction |= inst.cond << 28;
16551 inst.size = INSN_SIZE;
16552 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16554 it_fsm_pre_encode ();
16555 opcode->aencode ();
16556 it_fsm_post_encode ();
16558 /* Arm mode bx is marked as both v4T and v5 because it's still required
16559 on a hypothetical non-thumb v5 core. */
16561 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16563 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16564 *opcode->avariant);
16566 check_neon_suffixes;
16570 mapping_state (MAP_ARM);
16575 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16583 check_it_blocks_finished (void)
16588 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16589 if (seg_info (sect)->tc_segment_info_data.current_it.state
16590 == MANUAL_IT_BLOCK)
16592 as_warn (_("section '%s' finished with an open IT block."),
16596 if (now_it.state == MANUAL_IT_BLOCK)
16597 as_warn (_("file finished with an open IT block."));
16601 /* Various frobbings of labels and their addresses. */
16604 arm_start_line_hook (void)
16606 last_label_seen = NULL;
16610 arm_frob_label (symbolS * sym)
16612 last_label_seen = sym;
16614 ARM_SET_THUMB (sym, thumb_mode);
16616 #if defined OBJ_COFF || defined OBJ_ELF
16617 ARM_SET_INTERWORK (sym, support_interwork);
16620 force_automatic_it_block_close ();
16622 /* Note - do not allow local symbols (.Lxxx) to be labelled
16623 as Thumb functions. This is because these labels, whilst
16624 they exist inside Thumb code, are not the entry points for
16625 possible ARM->Thumb calls. Also, these labels can be used
16626 as part of a computed goto or switch statement. eg gcc
16627 can generate code that looks like this:
16629 ldr r2, [pc, .Laaa]
16639 The first instruction loads the address of the jump table.
16640 The second instruction converts a table index into a byte offset.
16641 The third instruction gets the jump address out of the table.
16642 The fourth instruction performs the jump.
16644 If the address stored at .Laaa is that of a symbol which has the
16645 Thumb_Func bit set, then the linker will arrange for this address
16646 to have the bottom bit set, which in turn would mean that the
16647 address computation performed by the third instruction would end
16648 up with the bottom bit set. Since the ARM is capable of unaligned
16649 word loads, the instruction would then load the incorrect address
16650 out of the jump table, and chaos would ensue. */
16651 if (label_is_thumb_function_name
16652 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16653 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16655 /* When the address of a Thumb function is taken the bottom
16656 bit of that address should be set. This will allow
16657 interworking between Arm and Thumb functions to work
16660 THUMB_SET_FUNC (sym, 1);
16662 label_is_thumb_function_name = FALSE;
16665 dwarf2_emit_label (sym);
16669 arm_data_in_code (void)
16671 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16673 *input_line_pointer = '/';
16674 input_line_pointer += 5;
16675 *input_line_pointer = 0;
16683 arm_canonicalize_symbol_name (char * name)
16687 if (thumb_mode && (len = strlen (name)) > 5
16688 && streq (name + len - 5, "/data"))
16689 *(name + len - 5) = 0;
16694 /* Table of all register names defined by default. The user can
16695 define additional names with .req. Note that all register names
16696 should appear in both upper and lowercase variants. Some registers
16697 also have mixed-case names. */
16699 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16700 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16701 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16702 #define REGSET(p,t) \
16703 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16704 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16705 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16706 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16707 #define REGSETH(p,t) \
16708 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16709 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16710 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16711 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16712 #define REGSET2(p,t) \
16713 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16714 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16715 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16716 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16717 #define SPLRBANK(base,bank,t) \
16718 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16719 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16720 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16721 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16722 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16723 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16725 static const struct reg_entry reg_names[] =
16727 /* ARM integer registers. */
16728 REGSET(r, RN), REGSET(R, RN),
16730 /* ATPCS synonyms. */
16731 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16732 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16733 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16735 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16736 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16737 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16739 /* Well-known aliases. */
16740 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16741 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16743 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16744 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16746 /* Coprocessor numbers. */
16747 REGSET(p, CP), REGSET(P, CP),
16749 /* Coprocessor register numbers. The "cr" variants are for backward
16751 REGSET(c, CN), REGSET(C, CN),
16752 REGSET(cr, CN), REGSET(CR, CN),
16754 /* ARM banked registers. */
16755 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16756 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16757 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16758 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16759 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16760 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16761 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16763 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16764 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16765 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16766 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16767 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16768 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16769 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16770 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16772 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16773 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16774 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16775 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16776 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16777 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16778 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16779 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16780 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16782 /* FPA registers. */
16783 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16784 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16786 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16787 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16789 /* VFP SP registers. */
16790 REGSET(s,VFS), REGSET(S,VFS),
16791 REGSETH(s,VFS), REGSETH(S,VFS),
16793 /* VFP DP Registers. */
16794 REGSET(d,VFD), REGSET(D,VFD),
16795 /* Extra Neon DP registers. */
16796 REGSETH(d,VFD), REGSETH(D,VFD),
16798 /* Neon QP registers. */
16799 REGSET2(q,NQ), REGSET2(Q,NQ),
16801 /* VFP control registers. */
16802 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16803 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16804 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16805 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16806 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16807 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16809 /* Maverick DSP coprocessor registers. */
16810 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16811 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16813 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16814 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16815 REGDEF(dspsc,0,DSPSC),
16817 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16818 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16819 REGDEF(DSPSC,0,DSPSC),
16821 /* iWMMXt data registers - p0, c0-15. */
16822 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16824 /* iWMMXt control registers - p1, c0-3. */
16825 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16826 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16827 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16828 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16830 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16831 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16832 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16833 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16834 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16836 /* XScale accumulator registers. */
16837 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16843 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16844 within psr_required_here. */
16845 static const struct asm_psr psrs[] =
16847 /* Backward compatibility notation. Note that "all" is no longer
16848 truly all possible PSR bits. */
16849 {"all", PSR_c | PSR_f},
16853 /* Individual flags. */
16859 /* Combinations of flags. */
16860 {"fs", PSR_f | PSR_s},
16861 {"fx", PSR_f | PSR_x},
16862 {"fc", PSR_f | PSR_c},
16863 {"sf", PSR_s | PSR_f},
16864 {"sx", PSR_s | PSR_x},
16865 {"sc", PSR_s | PSR_c},
16866 {"xf", PSR_x | PSR_f},
16867 {"xs", PSR_x | PSR_s},
16868 {"xc", PSR_x | PSR_c},
16869 {"cf", PSR_c | PSR_f},
16870 {"cs", PSR_c | PSR_s},
16871 {"cx", PSR_c | PSR_x},
16872 {"fsx", PSR_f | PSR_s | PSR_x},
16873 {"fsc", PSR_f | PSR_s | PSR_c},
16874 {"fxs", PSR_f | PSR_x | PSR_s},
16875 {"fxc", PSR_f | PSR_x | PSR_c},
16876 {"fcs", PSR_f | PSR_c | PSR_s},
16877 {"fcx", PSR_f | PSR_c | PSR_x},
16878 {"sfx", PSR_s | PSR_f | PSR_x},
16879 {"sfc", PSR_s | PSR_f | PSR_c},
16880 {"sxf", PSR_s | PSR_x | PSR_f},
16881 {"sxc", PSR_s | PSR_x | PSR_c},
16882 {"scf", PSR_s | PSR_c | PSR_f},
16883 {"scx", PSR_s | PSR_c | PSR_x},
16884 {"xfs", PSR_x | PSR_f | PSR_s},
16885 {"xfc", PSR_x | PSR_f | PSR_c},
16886 {"xsf", PSR_x | PSR_s | PSR_f},
16887 {"xsc", PSR_x | PSR_s | PSR_c},
16888 {"xcf", PSR_x | PSR_c | PSR_f},
16889 {"xcs", PSR_x | PSR_c | PSR_s},
16890 {"cfs", PSR_c | PSR_f | PSR_s},
16891 {"cfx", PSR_c | PSR_f | PSR_x},
16892 {"csf", PSR_c | PSR_s | PSR_f},
16893 {"csx", PSR_c | PSR_s | PSR_x},
16894 {"cxf", PSR_c | PSR_x | PSR_f},
16895 {"cxs", PSR_c | PSR_x | PSR_s},
16896 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16897 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16898 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16899 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16900 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16901 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16902 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16903 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16904 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16905 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16906 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16907 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16908 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16909 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16910 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16911 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16912 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16913 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16914 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16915 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16916 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16917 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16918 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16919 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16922 /* Table of V7M psr names. */
16923 static const struct asm_psr v7m_psrs[] =
16925 {"apsr", 0 }, {"APSR", 0 },
16926 {"iapsr", 1 }, {"IAPSR", 1 },
16927 {"eapsr", 2 }, {"EAPSR", 2 },
16928 {"psr", 3 }, {"PSR", 3 },
16929 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16930 {"ipsr", 5 }, {"IPSR", 5 },
16931 {"epsr", 6 }, {"EPSR", 6 },
16932 {"iepsr", 7 }, {"IEPSR", 7 },
16933 {"msp", 8 }, {"MSP", 8 },
16934 {"psp", 9 }, {"PSP", 9 },
16935 {"primask", 16}, {"PRIMASK", 16},
16936 {"basepri", 17}, {"BASEPRI", 17},
16937 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16938 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16939 {"faultmask", 19}, {"FAULTMASK", 19},
16940 {"control", 20}, {"CONTROL", 20}
16943 /* Table of all shift-in-operand names. */
16944 static const struct asm_shift_name shift_names [] =
16946 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16947 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16948 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16949 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16950 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16951 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16954 /* Table of all explicit relocation names. */
16956 static struct reloc_entry reloc_names[] =
16958 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16959 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16960 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16961 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16962 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16963 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16964 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16965 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16966 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16967 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16968 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16969 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
16970 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
16971 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
16972 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
16973 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
16974 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
16975 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
16979 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16980 static const struct asm_cond conds[] =
16984 {"cs", 0x2}, {"hs", 0x2},
16985 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16999 static struct asm_barrier_opt barrier_opt_names[] =
17001 { "sy", 0xf }, { "SY", 0xf },
17002 { "un", 0x7 }, { "UN", 0x7 },
17003 { "st", 0xe }, { "ST", 0xe },
17004 { "unst", 0x6 }, { "UNST", 0x6 },
17005 { "ish", 0xb }, { "ISH", 0xb },
17006 { "sh", 0xb }, { "SH", 0xb },
17007 { "ishst", 0xa }, { "ISHST", 0xa },
17008 { "shst", 0xa }, { "SHST", 0xa },
17009 { "nsh", 0x7 }, { "NSH", 0x7 },
17010 { "nshst", 0x6 }, { "NSHST", 0x6 },
17011 { "osh", 0x3 }, { "OSH", 0x3 },
17012 { "oshst", 0x2 }, { "OSHST", 0x2 }
17015 /* Table of ARM-format instructions. */
17017 /* Macros for gluing together operand strings. N.B. In all cases
17018 other than OPS0, the trailing OP_stop comes from default
17019 zero-initialization of the unspecified elements of the array. */
17020 #define OPS0() { OP_stop, }
17021 #define OPS1(a) { OP_##a, }
17022 #define OPS2(a,b) { OP_##a,OP_##b, }
17023 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17024 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17025 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17026 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17028 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17029 This is useful when mixing operands for ARM and THUMB, i.e. using the
17030 MIX_ARM_THUMB_OPERANDS macro.
17031 In order to use these macros, prefix the number of operands with _
17033 #define OPS_1(a) { a, }
17034 #define OPS_2(a,b) { a,b, }
17035 #define OPS_3(a,b,c) { a,b,c, }
17036 #define OPS_4(a,b,c,d) { a,b,c,d, }
17037 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17038 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17040 /* These macros abstract out the exact format of the mnemonic table and
17041 save some repeated characters. */
17043 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17044 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17045 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17046 THUMB_VARIANT, do_##ae, do_##te }
17048 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17049 a T_MNEM_xyz enumerator. */
17050 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17051 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17052 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17053 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17055 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17056 infix after the third character. */
17057 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17058 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17059 THUMB_VARIANT, do_##ae, do_##te }
17060 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17061 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17062 THUMB_VARIANT, do_##ae, do_##te }
17063 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17064 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17065 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17066 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17067 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17068 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17069 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17070 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17072 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
17073 appear in the condition table. */
17074 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17075 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17076 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17078 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17079 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17080 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17081 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17082 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17083 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17084 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17085 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17086 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17087 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17088 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17089 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17090 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17091 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17092 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17093 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17094 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17095 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17096 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17097 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17099 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17100 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17101 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17102 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17104 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17105 field is still 0xE. Many of the Thumb variants can be executed
17106 conditionally, so this is checked separately. */
17107 #define TUE(mnem, op, top, nops, ops, ae, te) \
17108 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17109 THUMB_VARIANT, do_##ae, do_##te }
17111 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17112 condition code field. */
17113 #define TUF(mnem, op, top, nops, ops, ae, te) \
17114 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17115 THUMB_VARIANT, do_##ae, do_##te }
17117 /* ARM-only variants of all the above. */
17118 #define CE(mnem, op, nops, ops, ae) \
17119 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17121 #define C3(mnem, op, nops, ops, ae) \
17122 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17124 /* Legacy mnemonics that always have conditional infix after the third
17126 #define CL(mnem, op, nops, ops, ae) \
17127 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17128 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17130 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17131 #define cCE(mnem, op, nops, ops, ae) \
17132 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17134 /* Legacy coprocessor instructions where conditional infix and conditional
17135 suffix are ambiguous. For consistency this includes all FPA instructions,
17136 not just the potentially ambiguous ones. */
17137 #define cCL(mnem, op, nops, ops, ae) \
17138 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17139 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17141 /* Coprocessor, takes either a suffix or a position-3 infix
17142 (for an FPA corner case). */
17143 #define C3E(mnem, op, nops, ops, ae) \
17144 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17145 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17147 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17148 { m1 #m2 m3, OPS##nops ops, \
17149 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17150 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17152 #define CM(m1, m2, op, nops, ops, ae) \
17153 xCM_ (m1, , m2, op, nops, ops, ae), \
17154 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17155 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17156 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17157 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17158 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17159 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17160 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17161 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17162 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17163 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17164 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17165 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17166 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17167 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17168 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17169 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17170 xCM_ (m1, le, m2, op, nops, ops, ae), \
17171 xCM_ (m1, al, m2, op, nops, ops, ae)
17173 #define UE(mnem, op, nops, ops, ae) \
17174 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17176 #define UF(mnem, op, nops, ops, ae) \
17177 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17179 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17180 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17181 use the same encoding function for each. */
17182 #define NUF(mnem, op, nops, ops, enc) \
17183 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17184 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17186 /* Neon data processing, version which indirects through neon_enc_tab for
17187 the various overloaded versions of opcodes. */
17188 #define nUF(mnem, op, nops, ops, enc) \
17189 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17190 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17192 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17194 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17195 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17196 THUMB_VARIANT, do_##enc, do_##enc }
17198 #define NCE(mnem, op, nops, ops, enc) \
17199 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17201 #define NCEF(mnem, op, nops, ops, enc) \
17202 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17204 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17205 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17206 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17207 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17209 #define nCE(mnem, op, nops, ops, enc) \
17210 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17212 #define nCEF(mnem, op, nops, ops, enc) \
17213 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17217 static const struct asm_opcode insns[] =
17219 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17220 #define THUMB_VARIANT &arm_ext_v4t
17221 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17222 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17223 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17224 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17225 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17226 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17227 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17228 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17229 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17230 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17231 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17232 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17233 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17234 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17235 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17236 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17238 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17239 for setting PSR flag bits. They are obsolete in V6 and do not
17240 have Thumb equivalents. */
17241 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17242 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17243 CL("tstp", 110f000, 2, (RR, SH), cmp),
17244 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17245 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17246 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17247 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17248 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17249 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17251 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17252 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17253 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17254 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17256 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17257 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17258 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17260 OP_ADDRGLDR),ldst, t_ldst),
17261 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17263 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17264 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17265 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17266 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17267 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17268 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17270 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17271 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17272 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17273 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17276 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17277 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17278 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17280 /* Thumb-compatibility pseudo ops. */
17281 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17282 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17283 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17284 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17285 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17286 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17287 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17288 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17289 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17290 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17291 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17292 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17294 /* These may simplify to neg. */
17295 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17296 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17298 #undef THUMB_VARIANT
17299 #define THUMB_VARIANT & arm_ext_v6
17301 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17303 /* V1 instructions with no Thumb analogue prior to V6T2. */
17304 #undef THUMB_VARIANT
17305 #define THUMB_VARIANT & arm_ext_v6t2
17307 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17308 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17309 CL("teqp", 130f000, 2, (RR, SH), cmp),
17311 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17312 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17313 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17314 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17316 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17317 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17319 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17320 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17322 /* V1 instructions with no Thumb analogue at all. */
17323 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17324 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17326 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17327 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17328 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17329 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17330 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17331 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17332 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17333 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17336 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17337 #undef THUMB_VARIANT
17338 #define THUMB_VARIANT & arm_ext_v4t
17340 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17341 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17343 #undef THUMB_VARIANT
17344 #define THUMB_VARIANT & arm_ext_v6t2
17346 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17347 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17349 /* Generic coprocessor instructions. */
17350 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17351 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17352 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17353 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17354 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17355 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17356 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17359 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17361 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17362 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17365 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17366 #undef THUMB_VARIANT
17367 #define THUMB_VARIANT & arm_ext_msr
17369 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17370 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17373 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17374 #undef THUMB_VARIANT
17375 #define THUMB_VARIANT & arm_ext_v6t2
17377 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17378 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17379 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17380 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17381 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17382 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17383 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17384 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17387 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17388 #undef THUMB_VARIANT
17389 #define THUMB_VARIANT & arm_ext_v4t
17391 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17392 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17393 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17394 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17395 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17396 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17399 #define ARM_VARIANT & arm_ext_v4t_5
17401 /* ARM Architecture 4T. */
17402 /* Note: bx (and blx) are required on V5, even if the processor does
17403 not support Thumb. */
17404 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17407 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17408 #undef THUMB_VARIANT
17409 #define THUMB_VARIANT & arm_ext_v5t
17411 /* Note: blx has 2 variants; the .value coded here is for
17412 BLX(2). Only this variant has conditional execution. */
17413 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17414 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17416 #undef THUMB_VARIANT
17417 #define THUMB_VARIANT & arm_ext_v6t2
17419 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17420 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17421 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17422 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17423 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17424 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17425 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17426 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17429 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17430 #undef THUMB_VARIANT
17431 #define THUMB_VARIANT &arm_ext_v5exp
17433 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17434 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17435 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17436 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17438 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17439 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17441 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17442 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17443 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17444 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17446 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17447 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17448 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17449 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17451 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17452 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17454 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17455 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17456 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17457 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17460 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17461 #undef THUMB_VARIANT
17462 #define THUMB_VARIANT &arm_ext_v6t2
17464 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17465 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17467 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17468 ADDRGLDRS), ldrd, t_ldstd),
17470 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17471 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17474 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17476 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17479 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17480 #undef THUMB_VARIANT
17481 #define THUMB_VARIANT & arm_ext_v6
17483 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17484 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17485 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17486 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17487 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17488 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17489 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17490 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17491 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17492 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17494 #undef THUMB_VARIANT
17495 #define THUMB_VARIANT & arm_ext_v6t2
17497 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17498 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17500 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17501 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17503 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17504 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17506 /* ARM V6 not included in V7M. */
17507 #undef THUMB_VARIANT
17508 #define THUMB_VARIANT & arm_ext_v6_notm
17509 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17510 UF(rfeib, 9900a00, 1, (RRw), rfe),
17511 UF(rfeda, 8100a00, 1, (RRw), rfe),
17512 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17513 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17514 UF(rfefa, 9900a00, 1, (RRw), rfe),
17515 UF(rfeea, 8100a00, 1, (RRw), rfe),
17516 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17517 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17518 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17519 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17520 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17522 /* ARM V6 not included in V7M (eg. integer SIMD). */
17523 #undef THUMB_VARIANT
17524 #define THUMB_VARIANT & arm_ext_v6_dsp
17525 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17526 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17527 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17528 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17529 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17530 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17531 /* Old name for QASX. */
17532 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17533 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17534 /* Old name for QSAX. */
17535 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17536 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17537 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17538 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17539 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17540 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17541 /* Old name for SASX. */
17542 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17543 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17544 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17545 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17546 /* Old name for SHASX. */
17547 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17548 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17549 /* Old name for SHSAX. */
17550 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17551 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17552 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17553 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17554 /* Old name for SSAX. */
17555 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17556 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17557 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17558 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17559 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17560 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17561 /* Old name for UASX. */
17562 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17563 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17564 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17565 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17566 /* Old name for UHASX. */
17567 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17568 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17569 /* Old name for UHSAX. */
17570 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17571 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17572 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17573 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17574 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17575 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17576 /* Old name for UQASX. */
17577 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17578 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17579 /* Old name for UQSAX. */
17580 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17581 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17582 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17583 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17584 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17585 /* Old name for USAX. */
17586 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17587 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17588 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17589 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17590 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17591 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17592 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17593 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17594 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17595 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17596 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17597 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17598 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17599 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17600 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17601 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17602 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17603 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17604 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17605 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17606 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17607 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17608 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17609 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17610 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17611 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17612 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17613 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17614 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17615 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17616 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17617 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17618 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17619 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17622 #define ARM_VARIANT & arm_ext_v6k
17623 #undef THUMB_VARIANT
17624 #define THUMB_VARIANT & arm_ext_v6k
17626 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17627 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17628 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17629 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17631 #undef THUMB_VARIANT
17632 #define THUMB_VARIANT & arm_ext_v6_notm
17633 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17635 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17636 RRnpcb), strexd, t_strexd),
17638 #undef THUMB_VARIANT
17639 #define THUMB_VARIANT & arm_ext_v6t2
17640 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17642 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17644 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17646 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17648 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17651 #define ARM_VARIANT & arm_ext_sec
17652 #undef THUMB_VARIANT
17653 #define THUMB_VARIANT & arm_ext_sec
17655 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17658 #define ARM_VARIANT & arm_ext_virt
17659 #undef THUMB_VARIANT
17660 #define THUMB_VARIANT & arm_ext_virt
17662 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17663 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17666 #define ARM_VARIANT & arm_ext_v6t2
17667 #undef THUMB_VARIANT
17668 #define THUMB_VARIANT & arm_ext_v6t2
17670 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17671 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17672 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17673 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17675 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17676 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17677 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17678 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17680 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17681 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17682 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17683 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17685 /* Thumb-only instructions. */
17687 #define ARM_VARIANT NULL
17688 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17689 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17691 /* ARM does not really have an IT instruction, so always allow it.
17692 The opcode is copied from Thumb in order to allow warnings in
17693 -mimplicit-it=[never | arm] modes. */
17695 #define ARM_VARIANT & arm_ext_v1
17697 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17698 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17699 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17700 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17701 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17702 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17703 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17704 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17705 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17706 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17707 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17708 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17709 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17710 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17711 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17712 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17713 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17714 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17716 /* Thumb2 only instructions. */
17718 #define ARM_VARIANT NULL
17720 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17721 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17722 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17723 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17724 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17725 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17727 /* Hardware division instructions. */
17729 #define ARM_VARIANT & arm_ext_adiv
17730 #undef THUMB_VARIANT
17731 #define THUMB_VARIANT & arm_ext_div
17733 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17734 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17736 /* ARM V6M/V7 instructions. */
17738 #define ARM_VARIANT & arm_ext_barrier
17739 #undef THUMB_VARIANT
17740 #define THUMB_VARIANT & arm_ext_barrier
17742 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17743 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17744 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17746 /* ARM V7 instructions. */
17748 #define ARM_VARIANT & arm_ext_v7
17749 #undef THUMB_VARIANT
17750 #define THUMB_VARIANT & arm_ext_v7
17752 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17753 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17756 #define ARM_VARIANT & arm_ext_mp
17757 #undef THUMB_VARIANT
17758 #define THUMB_VARIANT & arm_ext_mp
17760 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17763 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17765 cCE("wfs", e200110, 1, (RR), rd),
17766 cCE("rfs", e300110, 1, (RR), rd),
17767 cCE("wfc", e400110, 1, (RR), rd),
17768 cCE("rfc", e500110, 1, (RR), rd),
17770 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17771 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17772 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17773 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17775 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17776 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17777 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17778 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17780 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17781 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17782 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17783 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17784 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17785 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17786 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17787 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17788 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17789 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17790 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17791 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17793 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17794 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17795 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17796 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17797 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17798 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17799 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17800 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17801 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17802 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17803 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17804 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17806 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17807 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17808 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17809 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17810 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17811 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17812 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17813 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17814 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17815 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17816 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17817 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17819 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17820 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17821 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17822 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17823 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17824 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17825 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17826 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17827 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17828 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17829 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17830 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17832 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17833 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17834 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17835 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17836 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17837 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17838 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17839 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17840 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17841 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17842 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17843 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17845 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17846 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17847 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17848 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17849 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17850 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17851 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17852 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17853 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17854 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17855 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17856 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17858 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17859 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17860 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17861 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17862 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17863 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17864 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17865 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17866 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17867 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17868 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17869 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17871 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17872 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17873 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17874 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17875 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17876 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17877 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17878 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17879 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17880 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17881 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17882 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17884 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17885 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17886 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17887 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17888 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17889 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17890 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17891 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17892 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17893 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17894 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17895 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17897 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17898 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17899 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17900 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17901 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17902 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17903 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17904 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17905 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17906 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17907 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17908 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17910 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17911 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17912 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17913 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17914 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17915 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17916 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17917 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17918 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17919 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17920 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17921 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17923 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17924 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17925 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17926 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17927 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17928 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17929 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17930 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17931 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17932 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17933 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17934 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17936 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17937 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17938 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17939 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17940 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17941 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17942 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17943 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17944 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17945 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17946 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17947 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17949 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17950 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17951 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17952 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17953 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17954 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17955 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17956 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17957 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17958 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17959 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17960 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17962 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17963 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17964 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17965 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17966 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17967 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17968 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17969 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17970 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17971 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17972 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17973 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17975 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17976 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17977 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17978 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17979 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17980 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17981 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17982 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17983 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17984 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17985 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17986 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17988 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17989 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17990 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17991 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17992 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17993 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17994 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17995 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17996 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
17997 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
17998 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
17999 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18001 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18002 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18003 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18004 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18005 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18006 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18007 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18008 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18009 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18010 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18011 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18012 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18014 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18015 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18016 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18017 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18018 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18019 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18020 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18021 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18022 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18023 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18024 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18025 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18027 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18028 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18029 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18030 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18031 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18032 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18033 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18034 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18035 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18036 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18037 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18038 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18040 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18041 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18042 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18043 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18044 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18045 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18046 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18047 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18048 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18049 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18050 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18051 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18053 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18054 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18055 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18056 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18057 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18058 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18059 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18060 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18061 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18062 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18063 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18064 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18066 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18067 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18068 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18069 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18070 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18071 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18072 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18073 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18074 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18075 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18076 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18077 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18079 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18080 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18081 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18082 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18083 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18084 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18085 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18086 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18087 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18088 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18089 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18090 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18092 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18093 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18094 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18095 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18096 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18097 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18098 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18099 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18100 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18101 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18102 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18103 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18105 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18106 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18107 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18108 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18109 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18110 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18111 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18112 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18113 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18114 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18115 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18116 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18118 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18119 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18120 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18121 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18122 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18123 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18124 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18125 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18126 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18127 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18128 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18129 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18131 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18132 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18133 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18134 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18135 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18136 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18137 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18138 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18139 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18140 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18141 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18142 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18144 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18145 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18146 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18147 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18148 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18149 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18150 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18151 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18152 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18153 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18154 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18155 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18157 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18158 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18159 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18160 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18162 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18163 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18164 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18165 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18166 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18167 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18168 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18169 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18170 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18171 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18172 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18173 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18175 /* The implementation of the FIX instruction is broken on some
18176 assemblers, in that it accepts a precision specifier as well as a
18177 rounding specifier, despite the fact that this is meaningless.
18178 To be more compatible, we accept it as well, though of course it
18179 does not set any bits. */
18180 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18181 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18182 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18183 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18184 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18185 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18186 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18187 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18188 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18189 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18190 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18191 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18192 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18194 /* Instructions that were new with the real FPA, call them V2. */
18196 #define ARM_VARIANT & fpu_fpa_ext_v2
18198 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18199 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18200 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18201 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18202 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18203 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18206 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18208 /* Moves and type conversions. */
18209 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18210 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18211 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18212 cCE("fmstat", ef1fa10, 0, (), noargs),
18213 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
18214 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
18215 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18216 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18217 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18218 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18219 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18220 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18221 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18222 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18224 /* Memory operations. */
18225 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18226 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18227 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18228 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18229 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18230 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18231 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18232 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18233 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18234 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18235 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18236 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18237 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18238 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18239 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18240 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18241 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18242 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18244 /* Monadic operations. */
18245 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18246 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18247 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18249 /* Dyadic operations. */
18250 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18251 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18252 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18253 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18254 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18255 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18256 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18257 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18258 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18261 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18262 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18263 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18264 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18266 /* Double precision load/store are still present on single precision
18267 implementations. */
18268 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18269 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18270 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18271 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18272 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18273 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18274 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18275 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18276 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18277 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18280 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18282 /* Moves and type conversions. */
18283 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18284 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18285 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18286 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18287 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18288 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18289 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18290 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18291 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18292 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18293 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18294 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18295 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18297 /* Monadic operations. */
18298 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18299 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18300 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18302 /* Dyadic operations. */
18303 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18304 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18305 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18306 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18307 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18308 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18309 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18310 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18311 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18314 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18315 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18316 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18317 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18320 #define ARM_VARIANT & fpu_vfp_ext_v2
18322 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18323 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18324 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18325 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18327 /* Instructions which may belong to either the Neon or VFP instruction sets.
18328 Individual encoder functions perform additional architecture checks. */
18330 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18331 #undef THUMB_VARIANT
18332 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18334 /* These mnemonics are unique to VFP. */
18335 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18336 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18337 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18338 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18339 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18340 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18341 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18342 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18343 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18344 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18346 /* Mnemonics shared by Neon and VFP. */
18347 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18348 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18349 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18351 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18352 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18354 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18355 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18357 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18358 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18359 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18360 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18361 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18362 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18363 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18364 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18366 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18367 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18368 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18369 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18372 /* NOTE: All VMOV encoding is special-cased! */
18373 NCE(vmov, 0, 1, (VMOV), neon_mov),
18374 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18376 #undef THUMB_VARIANT
18377 #define THUMB_VARIANT & fpu_neon_ext_v1
18379 #define ARM_VARIANT & fpu_neon_ext_v1
18381 /* Data processing with three registers of the same length. */
18382 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18383 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18384 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18385 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18386 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18387 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18388 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18389 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18390 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18391 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18392 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18393 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18394 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18395 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18396 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18397 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18398 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18399 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18400 /* If not immediate, fall back to neon_dyadic_i64_su.
18401 shl_imm should accept I8 I16 I32 I64,
18402 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18403 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18404 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18405 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18406 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18407 /* Logic ops, types optional & ignored. */
18408 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18409 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18410 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18411 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18412 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18413 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18414 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18415 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18416 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18417 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18418 /* Bitfield ops, untyped. */
18419 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18420 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18421 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18422 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18423 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18424 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18425 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18426 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18427 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18428 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18429 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18430 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18431 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18432 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18433 back to neon_dyadic_if_su. */
18434 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18435 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18436 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18437 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18438 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18439 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18440 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18441 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18442 /* Comparison. Type I8 I16 I32 F32. */
18443 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18444 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18445 /* As above, D registers only. */
18446 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18447 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18448 /* Int and float variants, signedness unimportant. */
18449 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18450 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18451 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18452 /* Add/sub take types I8 I16 I32 I64 F32. */
18453 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18454 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18455 /* vtst takes sizes 8, 16, 32. */
18456 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18457 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18458 /* VMUL takes I8 I16 I32 F32 P8. */
18459 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18460 /* VQD{R}MULH takes S16 S32. */
18461 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18462 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18463 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18464 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18465 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18466 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18467 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18468 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18469 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18470 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18471 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18472 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18473 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18474 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18475 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18476 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18478 /* Two address, int/float. Types S8 S16 S32 F32. */
18479 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18480 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18482 /* Data processing with two registers and a shift amount. */
18483 /* Right shifts, and variants with rounding.
18484 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18485 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18486 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18487 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18488 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18489 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18490 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18491 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18492 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18493 /* Shift and insert. Sizes accepted 8 16 32 64. */
18494 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18495 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18496 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18497 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18498 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18499 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18500 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18501 /* Right shift immediate, saturating & narrowing, with rounding variants.
18502 Types accepted S16 S32 S64 U16 U32 U64. */
18503 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18504 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18505 /* As above, unsigned. Types accepted S16 S32 S64. */
18506 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18507 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18508 /* Right shift narrowing. Types accepted I16 I32 I64. */
18509 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18510 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18511 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18512 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18513 /* CVT with optional immediate for fixed-point variant. */
18514 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18516 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18517 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18519 /* Data processing, three registers of different lengths. */
18520 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18521 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18522 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18523 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18524 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18525 /* If not scalar, fall back to neon_dyadic_long.
18526 Vector types as above, scalar types S16 S32 U16 U32. */
18527 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18528 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18529 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18530 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18531 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18532 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18533 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18534 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18535 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18536 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18537 /* Saturating doubling multiplies. Types S16 S32. */
18538 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18539 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18540 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18541 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18542 S16 S32 U16 U32. */
18543 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18545 /* Extract. Size 8. */
18546 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18547 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18549 /* Two registers, miscellaneous. */
18550 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18551 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18552 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18553 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18554 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18555 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18556 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18557 /* Vector replicate. Sizes 8 16 32. */
18558 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18559 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18560 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18561 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18562 /* VMOVN. Types I16 I32 I64. */
18563 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18564 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18565 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18566 /* VQMOVUN. Types S16 S32 S64. */
18567 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18568 /* VZIP / VUZP. Sizes 8 16 32. */
18569 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18570 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18571 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18572 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18573 /* VQABS / VQNEG. Types S8 S16 S32. */
18574 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18575 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18576 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18577 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18578 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18579 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18580 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18581 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18582 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18583 /* Reciprocal estimates. Types U32 F32. */
18584 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18585 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18586 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18587 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18588 /* VCLS. Types S8 S16 S32. */
18589 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18590 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18591 /* VCLZ. Types I8 I16 I32. */
18592 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18593 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18594 /* VCNT. Size 8. */
18595 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18596 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18597 /* Two address, untyped. */
18598 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18599 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18600 /* VTRN. Sizes 8 16 32. */
18601 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18602 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18604 /* Table lookup. Size 8. */
18605 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18606 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18608 #undef THUMB_VARIANT
18609 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18611 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18613 /* Neon element/structure load/store. */
18614 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18615 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18616 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18617 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18618 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18619 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18620 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18621 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18623 #undef THUMB_VARIANT
18624 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18626 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18627 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18628 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18629 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18630 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18631 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18632 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18633 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18634 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18635 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18637 #undef THUMB_VARIANT
18638 #define THUMB_VARIANT & fpu_vfp_ext_v3
18640 #define ARM_VARIANT & fpu_vfp_ext_v3
18642 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18643 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18644 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18645 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18646 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18647 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18648 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18649 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18650 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18653 #define ARM_VARIANT &fpu_vfp_ext_fma
18654 #undef THUMB_VARIANT
18655 #define THUMB_VARIANT &fpu_vfp_ext_fma
18656 /* Mnemonics shared by Neon and VFP. These are included in the
18657 VFP FMA variant; NEON and VFP FMA always includes the NEON
18658 FMA instructions. */
18659 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18660 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18661 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18662 the v form should always be used. */
18663 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18664 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18665 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18666 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18667 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18668 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18670 #undef THUMB_VARIANT
18672 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18674 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18675 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18676 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18677 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18678 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18679 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18680 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18681 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18684 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18686 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18687 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18688 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18689 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18690 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18691 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18692 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18693 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18694 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18695 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18696 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18697 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18698 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18699 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18700 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18701 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18702 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18703 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18704 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18705 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18706 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18707 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18708 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18709 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18710 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18711 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18712 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18713 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18714 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18715 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18716 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18717 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18718 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18719 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18720 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18721 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18722 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18723 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18724 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18725 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18726 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18727 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18728 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18729 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18730 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18731 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18732 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18733 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18734 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18735 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18736 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18737 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18738 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18739 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18740 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18741 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18742 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18743 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18744 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18745 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18746 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18747 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18748 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18749 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18750 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18751 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18752 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18753 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18754 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18755 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18756 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18757 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18758 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18759 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18760 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18761 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18762 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18763 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18764 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18765 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18766 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18767 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18768 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18769 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18770 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18771 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18772 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18773 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18774 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18775 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18776 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18777 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18778 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18779 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18780 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18781 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18782 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18783 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18784 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18785 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18786 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18787 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18788 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18789 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18790 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18791 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18792 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18793 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18794 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18795 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18796 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18797 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18798 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18799 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18800 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18801 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18802 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18803 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18804 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18805 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18806 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18807 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18808 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18809 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18810 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18811 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18812 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18813 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18814 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18815 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18816 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18817 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18818 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18819 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18820 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18821 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18822 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18823 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18824 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18825 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18826 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18827 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18828 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18829 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18830 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18831 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18832 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18833 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18834 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18835 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18836 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18837 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18838 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18839 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18840 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18841 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18842 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18843 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18844 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18845 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18846 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18847 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18850 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18852 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18853 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18854 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18855 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18856 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18857 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18858 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18859 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18860 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18861 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18862 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18863 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18864 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18865 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18866 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18867 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18868 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18869 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18870 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18871 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18872 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18873 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18874 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18875 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18876 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18877 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18878 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18879 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18880 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18881 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18882 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18883 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18884 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18885 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18886 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18887 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18888 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18889 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18890 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18891 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18892 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18893 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18894 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18895 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18896 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18897 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18898 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18899 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18900 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18901 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18902 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18903 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18904 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18905 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18906 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18907 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18908 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18911 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18913 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18914 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18915 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18916 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18917 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18918 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18919 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18920 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18921 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18922 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18923 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18924 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18925 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18926 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18927 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18928 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18929 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18930 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18931 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18932 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18933 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18934 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18935 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18936 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18937 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18938 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18939 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18940 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18941 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18942 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18943 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18944 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18945 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18946 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18947 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18948 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18949 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18950 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18951 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18952 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18953 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18954 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18955 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18956 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18957 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18958 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18959 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18960 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18961 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18962 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18963 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18964 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18965 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18966 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18967 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18968 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18969 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18970 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18971 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18972 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18973 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18974 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18975 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18976 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18977 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18978 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18979 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18980 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18981 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18982 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18983 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18984 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18985 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18986 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18987 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18988 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18991 #undef THUMB_VARIANT
19018 /* MD interface: bits in the object file. */
19020 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19021 for use in the a.out file, and stores them in the array pointed to by buf.
19022 This knows about the endian-ness of the target machine and does
19023 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19024 2 (short) and 4 (long) Floating numbers are put out as a series of
19025 LITTLENUMS (shorts, here at least). */
19028 md_number_to_chars (char * buf, valueT val, int n)
19030 if (target_big_endian)
19031 number_to_chars_bigendian (buf, val, n);
19033 number_to_chars_littleendian (buf, val, n);
19037 md_chars_to_number (char * buf, int n)
19040 unsigned char * where = (unsigned char *) buf;
19042 if (target_big_endian)
19047 result |= (*where++ & 255);
19055 result |= (where[n] & 255);
19062 /* MD interface: Sections. */
19064 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19065 that an rs_machine_dependent frag may reach. */
19068 arm_frag_max_var (fragS *fragp)
19070 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19071 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19073 Note that we generate relaxable instructions even for cases that don't
19074 really need it, like an immediate that's a trivial constant. So we're
19075 overestimating the instruction size for some of those cases. Rather
19076 than putting more intelligence here, it would probably be better to
19077 avoid generating a relaxation frag in the first place when it can be
19078 determined up front that a short instruction will suffice. */
19080 gas_assert (fragp->fr_type == rs_machine_dependent);
19084 /* Estimate the size of a frag before relaxing. Assume everything fits in
19088 md_estimate_size_before_relax (fragS * fragp,
19089 segT segtype ATTRIBUTE_UNUSED)
19095 /* Convert a machine dependent frag. */
19098 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19100 unsigned long insn;
19101 unsigned long old_op;
19109 buf = fragp->fr_literal + fragp->fr_fix;
19111 old_op = bfd_get_16(abfd, buf);
19112 if (fragp->fr_symbol)
19114 exp.X_op = O_symbol;
19115 exp.X_add_symbol = fragp->fr_symbol;
19119 exp.X_op = O_constant;
19121 exp.X_add_number = fragp->fr_offset;
19122 opcode = fragp->fr_subtype;
19125 case T_MNEM_ldr_pc:
19126 case T_MNEM_ldr_pc2:
19127 case T_MNEM_ldr_sp:
19128 case T_MNEM_str_sp:
19135 if (fragp->fr_var == 4)
19137 insn = THUMB_OP32 (opcode);
19138 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19140 insn |= (old_op & 0x700) << 4;
19144 insn |= (old_op & 7) << 12;
19145 insn |= (old_op & 0x38) << 13;
19147 insn |= 0x00000c00;
19148 put_thumb32_insn (buf, insn);
19149 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19153 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19155 pc_rel = (opcode == T_MNEM_ldr_pc2);
19158 if (fragp->fr_var == 4)
19160 insn = THUMB_OP32 (opcode);
19161 insn |= (old_op & 0xf0) << 4;
19162 put_thumb32_insn (buf, insn);
19163 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19167 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19168 exp.X_add_number -= 4;
19176 if (fragp->fr_var == 4)
19178 int r0off = (opcode == T_MNEM_mov
19179 || opcode == T_MNEM_movs) ? 0 : 8;
19180 insn = THUMB_OP32 (opcode);
19181 insn = (insn & 0xe1ffffff) | 0x10000000;
19182 insn |= (old_op & 0x700) << r0off;
19183 put_thumb32_insn (buf, insn);
19184 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19188 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19193 if (fragp->fr_var == 4)
19195 insn = THUMB_OP32(opcode);
19196 put_thumb32_insn (buf, insn);
19197 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19200 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19204 if (fragp->fr_var == 4)
19206 insn = THUMB_OP32(opcode);
19207 insn |= (old_op & 0xf00) << 14;
19208 put_thumb32_insn (buf, insn);
19209 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19212 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19215 case T_MNEM_add_sp:
19216 case T_MNEM_add_pc:
19217 case T_MNEM_inc_sp:
19218 case T_MNEM_dec_sp:
19219 if (fragp->fr_var == 4)
19221 /* ??? Choose between add and addw. */
19222 insn = THUMB_OP32 (opcode);
19223 insn |= (old_op & 0xf0) << 4;
19224 put_thumb32_insn (buf, insn);
19225 if (opcode == T_MNEM_add_pc)
19226 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19228 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19231 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19239 if (fragp->fr_var == 4)
19241 insn = THUMB_OP32 (opcode);
19242 insn |= (old_op & 0xf0) << 4;
19243 insn |= (old_op & 0xf) << 16;
19244 put_thumb32_insn (buf, insn);
19245 if (insn & (1 << 20))
19246 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19248 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19251 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19257 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19258 (enum bfd_reloc_code_real) reloc_type);
19259 fixp->fx_file = fragp->fr_file;
19260 fixp->fx_line = fragp->fr_line;
19261 fragp->fr_fix += fragp->fr_var;
19264 /* Return the size of a relaxable immediate operand instruction.
19265 SHIFT and SIZE specify the form of the allowable immediate. */
19267 relax_immediate (fragS *fragp, int size, int shift)
19273 /* ??? Should be able to do better than this. */
19274 if (fragp->fr_symbol)
19277 low = (1 << shift) - 1;
19278 mask = (1 << (shift + size)) - (1 << shift);
19279 offset = fragp->fr_offset;
19280 /* Force misaligned offsets to 32-bit variant. */
19283 if (offset & ~mask)
19288 /* Get the address of a symbol during relaxation. */
19290 relaxed_symbol_addr (fragS *fragp, long stretch)
19296 sym = fragp->fr_symbol;
19297 sym_frag = symbol_get_frag (sym);
19298 know (S_GET_SEGMENT (sym) != absolute_section
19299 || sym_frag == &zero_address_frag);
19300 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19302 /* If frag has yet to be reached on this pass, assume it will
19303 move by STRETCH just as we did. If this is not so, it will
19304 be because some frag between grows, and that will force
19308 && sym_frag->relax_marker != fragp->relax_marker)
19312 /* Adjust stretch for any alignment frag. Note that if have
19313 been expanding the earlier code, the symbol may be
19314 defined in what appears to be an earlier frag. FIXME:
19315 This doesn't handle the fr_subtype field, which specifies
19316 a maximum number of bytes to skip when doing an
19318 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19320 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19323 stretch = - ((- stretch)
19324 & ~ ((1 << (int) f->fr_offset) - 1));
19326 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19338 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19341 relax_adr (fragS *fragp, asection *sec, long stretch)
19346 /* Assume worst case for symbols not known to be in the same section. */
19347 if (fragp->fr_symbol == NULL
19348 || !S_IS_DEFINED (fragp->fr_symbol)
19349 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19350 || S_IS_WEAK (fragp->fr_symbol))
19353 val = relaxed_symbol_addr (fragp, stretch);
19354 addr = fragp->fr_address + fragp->fr_fix;
19355 addr = (addr + 4) & ~3;
19356 /* Force misaligned targets to 32-bit variant. */
19360 if (val < 0 || val > 1020)
19365 /* Return the size of a relaxable add/sub immediate instruction. */
19367 relax_addsub (fragS *fragp, asection *sec)
19372 buf = fragp->fr_literal + fragp->fr_fix;
19373 op = bfd_get_16(sec->owner, buf);
19374 if ((op & 0xf) == ((op >> 4) & 0xf))
19375 return relax_immediate (fragp, 8, 0);
19377 return relax_immediate (fragp, 3, 0);
19381 /* Return the size of a relaxable branch instruction. BITS is the
19382 size of the offset field in the narrow instruction. */
19385 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19391 /* Assume worst case for symbols not known to be in the same section. */
19392 if (!S_IS_DEFINED (fragp->fr_symbol)
19393 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19394 || S_IS_WEAK (fragp->fr_symbol))
19398 if (S_IS_DEFINED (fragp->fr_symbol)
19399 && ARM_IS_FUNC (fragp->fr_symbol))
19402 /* PR 12532. Global symbols with default visibility might
19403 be preempted, so do not relax relocations to them. */
19404 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19405 && (! S_IS_LOCAL (fragp->fr_symbol)))
19409 val = relaxed_symbol_addr (fragp, stretch);
19410 addr = fragp->fr_address + fragp->fr_fix + 4;
19413 /* Offset is a signed value *2 */
19415 if (val >= limit || val < -limit)
19421 /* Relax a machine dependent frag. This returns the amount by which
19422 the current size of the frag should change. */
19425 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19430 oldsize = fragp->fr_var;
19431 switch (fragp->fr_subtype)
19433 case T_MNEM_ldr_pc2:
19434 newsize = relax_adr (fragp, sec, stretch);
19436 case T_MNEM_ldr_pc:
19437 case T_MNEM_ldr_sp:
19438 case T_MNEM_str_sp:
19439 newsize = relax_immediate (fragp, 8, 2);
19443 newsize = relax_immediate (fragp, 5, 2);
19447 newsize = relax_immediate (fragp, 5, 1);
19451 newsize = relax_immediate (fragp, 5, 0);
19454 newsize = relax_adr (fragp, sec, stretch);
19460 newsize = relax_immediate (fragp, 8, 0);
19463 newsize = relax_branch (fragp, sec, 11, stretch);
19466 newsize = relax_branch (fragp, sec, 8, stretch);
19468 case T_MNEM_add_sp:
19469 case T_MNEM_add_pc:
19470 newsize = relax_immediate (fragp, 8, 2);
19472 case T_MNEM_inc_sp:
19473 case T_MNEM_dec_sp:
19474 newsize = relax_immediate (fragp, 7, 2);
19480 newsize = relax_addsub (fragp, sec);
19486 fragp->fr_var = newsize;
19487 /* Freeze wide instructions that are at or before the same location as
19488 in the previous pass. This avoids infinite loops.
19489 Don't freeze them unconditionally because targets may be artificially
19490 misaligned by the expansion of preceding frags. */
19491 if (stretch <= 0 && newsize > 2)
19493 md_convert_frag (sec->owner, sec, fragp);
19497 return newsize - oldsize;
19500 /* Round up a section size to the appropriate boundary. */
19503 md_section_align (segT segment ATTRIBUTE_UNUSED,
19506 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19507 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19509 /* For a.out, force the section size to be aligned. If we don't do
19510 this, BFD will align it for us, but it will not write out the
19511 final bytes of the section. This may be a bug in BFD, but it is
19512 easier to fix it here since that is how the other a.out targets
19516 align = bfd_get_section_alignment (stdoutput, segment);
19517 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19524 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19525 of an rs_align_code fragment. */
19528 arm_handle_align (fragS * fragP)
19530 static char const arm_noop[2][2][4] =
19533 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19534 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19537 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19538 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19541 static char const thumb_noop[2][2][2] =
19544 {0xc0, 0x46}, /* LE */
19545 {0x46, 0xc0}, /* BE */
19548 {0x00, 0xbf}, /* LE */
19549 {0xbf, 0x00} /* BE */
19552 static char const wide_thumb_noop[2][4] =
19553 { /* Wide Thumb-2 */
19554 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19555 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19558 unsigned bytes, fix, noop_size;
19561 const char *narrow_noop = NULL;
19566 if (fragP->fr_type != rs_align_code)
19569 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19570 p = fragP->fr_literal + fragP->fr_fix;
19573 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19574 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19576 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19578 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19580 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19582 narrow_noop = thumb_noop[1][target_big_endian];
19583 noop = wide_thumb_noop[target_big_endian];
19586 noop = thumb_noop[0][target_big_endian];
19594 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19595 [target_big_endian];
19602 fragP->fr_var = noop_size;
19604 if (bytes & (noop_size - 1))
19606 fix = bytes & (noop_size - 1);
19608 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19610 memset (p, 0, fix);
19617 if (bytes & noop_size)
19619 /* Insert a narrow noop. */
19620 memcpy (p, narrow_noop, noop_size);
19622 bytes -= noop_size;
19626 /* Use wide noops for the remainder */
19630 while (bytes >= noop_size)
19632 memcpy (p, noop, noop_size);
19634 bytes -= noop_size;
19638 fragP->fr_fix += fix;
19641 /* Called from md_do_align. Used to create an alignment
19642 frag in a code section. */
19645 arm_frag_align_code (int n, int max)
19649 /* We assume that there will never be a requirement
19650 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19651 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19656 _("alignments greater than %d bytes not supported in .text sections."),
19657 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19658 as_fatal ("%s", err_msg);
19661 p = frag_var (rs_align_code,
19662 MAX_MEM_FOR_RS_ALIGN_CODE,
19664 (relax_substateT) max,
19671 /* Perform target specific initialisation of a frag.
19672 Note - despite the name this initialisation is not done when the frag
19673 is created, but only when its type is assigned. A frag can be created
19674 and used a long time before its type is set, so beware of assuming that
19675 this initialisationis performed first. */
19679 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19681 /* Record whether this frag is in an ARM or a THUMB area. */
19682 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19685 #else /* OBJ_ELF is defined. */
19687 arm_init_frag (fragS * fragP, int max_chars)
19689 /* If the current ARM vs THUMB mode has not already
19690 been recorded into this frag then do so now. */
19691 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19693 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19695 /* Record a mapping symbol for alignment frags. We will delete this
19696 later if the alignment ends up empty. */
19697 switch (fragP->fr_type)
19700 case rs_align_test:
19702 mapping_state_2 (MAP_DATA, max_chars);
19704 case rs_align_code:
19705 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19713 /* When we change sections we need to issue a new mapping symbol. */
19716 arm_elf_change_section (void)
19718 /* Link an unlinked unwind index table section to the .text section. */
19719 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19720 && elf_linked_to_section (now_seg) == NULL)
19721 elf_linked_to_section (now_seg) = text_section;
19725 arm_elf_section_type (const char * str, size_t len)
19727 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19728 return SHT_ARM_EXIDX;
19733 /* Code to deal with unwinding tables. */
19735 static void add_unwind_adjustsp (offsetT);
19737 /* Generate any deferred unwind frame offset. */
19740 flush_pending_unwind (void)
19744 offset = unwind.pending_offset;
19745 unwind.pending_offset = 0;
19747 add_unwind_adjustsp (offset);
19750 /* Add an opcode to this list for this function. Two-byte opcodes should
19751 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19755 add_unwind_opcode (valueT op, int length)
19757 /* Add any deferred stack adjustment. */
19758 if (unwind.pending_offset)
19759 flush_pending_unwind ();
19761 unwind.sp_restored = 0;
19763 if (unwind.opcode_count + length > unwind.opcode_alloc)
19765 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19766 if (unwind.opcodes)
19767 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19768 unwind.opcode_alloc);
19770 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19775 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19777 unwind.opcode_count++;
19781 /* Add unwind opcodes to adjust the stack pointer. */
19784 add_unwind_adjustsp (offsetT offset)
19788 if (offset > 0x200)
19790 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19795 /* Long form: 0xb2, uleb128. */
19796 /* This might not fit in a word so add the individual bytes,
19797 remembering the list is built in reverse order. */
19798 o = (valueT) ((offset - 0x204) >> 2);
19800 add_unwind_opcode (0, 1);
19802 /* Calculate the uleb128 encoding of the offset. */
19806 bytes[n] = o & 0x7f;
19812 /* Add the insn. */
19814 add_unwind_opcode (bytes[n - 1], 1);
19815 add_unwind_opcode (0xb2, 1);
19817 else if (offset > 0x100)
19819 /* Two short opcodes. */
19820 add_unwind_opcode (0x3f, 1);
19821 op = (offset - 0x104) >> 2;
19822 add_unwind_opcode (op, 1);
19824 else if (offset > 0)
19826 /* Short opcode. */
19827 op = (offset - 4) >> 2;
19828 add_unwind_opcode (op, 1);
19830 else if (offset < 0)
19833 while (offset > 0x100)
19835 add_unwind_opcode (0x7f, 1);
19838 op = ((offset - 4) >> 2) | 0x40;
19839 add_unwind_opcode (op, 1);
19843 /* Finish the list of unwind opcodes for this function. */
19845 finish_unwind_opcodes (void)
19849 if (unwind.fp_used)
19851 /* Adjust sp as necessary. */
19852 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19853 flush_pending_unwind ();
19855 /* After restoring sp from the frame pointer. */
19856 op = 0x90 | unwind.fp_reg;
19857 add_unwind_opcode (op, 1);
19860 flush_pending_unwind ();
19864 /* Start an exception table entry. If idx is nonzero this is an index table
19868 start_unwind_section (const segT text_seg, int idx)
19870 const char * text_name;
19871 const char * prefix;
19872 const char * prefix_once;
19873 const char * group_name;
19877 size_t sec_name_len;
19884 prefix = ELF_STRING_ARM_unwind;
19885 prefix_once = ELF_STRING_ARM_unwind_once;
19886 type = SHT_ARM_EXIDX;
19890 prefix = ELF_STRING_ARM_unwind_info;
19891 prefix_once = ELF_STRING_ARM_unwind_info_once;
19892 type = SHT_PROGBITS;
19895 text_name = segment_name (text_seg);
19896 if (streq (text_name, ".text"))
19899 if (strncmp (text_name, ".gnu.linkonce.t.",
19900 strlen (".gnu.linkonce.t.")) == 0)
19902 prefix = prefix_once;
19903 text_name += strlen (".gnu.linkonce.t.");
19906 prefix_len = strlen (prefix);
19907 text_len = strlen (text_name);
19908 sec_name_len = prefix_len + text_len;
19909 sec_name = (char *) xmalloc (sec_name_len + 1);
19910 memcpy (sec_name, prefix, prefix_len);
19911 memcpy (sec_name + prefix_len, text_name, text_len);
19912 sec_name[prefix_len + text_len] = '\0';
19918 /* Handle COMDAT group. */
19919 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19921 group_name = elf_group_name (text_seg);
19922 if (group_name == NULL)
19924 as_bad (_("Group section `%s' has no group signature"),
19925 segment_name (text_seg));
19926 ignore_rest_of_line ();
19929 flags |= SHF_GROUP;
19933 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19935 /* Set the section link for index tables. */
19937 elf_linked_to_section (now_seg) = text_seg;
19941 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19942 personality routine data. Returns zero, or the index table value for
19943 and inline entry. */
19946 create_unwind_entry (int have_data)
19951 /* The current word of data. */
19953 /* The number of bytes left in this word. */
19956 finish_unwind_opcodes ();
19958 /* Remember the current text section. */
19959 unwind.saved_seg = now_seg;
19960 unwind.saved_subseg = now_subseg;
19962 start_unwind_section (now_seg, 0);
19964 if (unwind.personality_routine == NULL)
19966 if (unwind.personality_index == -2)
19969 as_bad (_("handlerdata in cantunwind frame"));
19970 return 1; /* EXIDX_CANTUNWIND. */
19973 /* Use a default personality routine if none is specified. */
19974 if (unwind.personality_index == -1)
19976 if (unwind.opcode_count > 3)
19977 unwind.personality_index = 1;
19979 unwind.personality_index = 0;
19982 /* Space for the personality routine entry. */
19983 if (unwind.personality_index == 0)
19985 if (unwind.opcode_count > 3)
19986 as_bad (_("too many unwind opcodes for personality routine 0"));
19990 /* All the data is inline in the index table. */
19993 while (unwind.opcode_count > 0)
19995 unwind.opcode_count--;
19996 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20000 /* Pad with "finish" opcodes. */
20002 data = (data << 8) | 0xb0;
20009 /* We get two opcodes "free" in the first word. */
20010 size = unwind.opcode_count - 2;
20014 gas_assert (unwind.personality_index == -1);
20016 /* An extra byte is required for the opcode count. */
20017 size = unwind.opcode_count + 1;
20020 size = (size + 3) >> 2;
20022 as_bad (_("too many unwind opcodes"));
20024 frag_align (2, 0, 0);
20025 record_alignment (now_seg, 2);
20026 unwind.table_entry = expr_build_dot ();
20028 /* Allocate the table entry. */
20029 ptr = frag_more ((size << 2) + 4);
20030 /* PR 13449: Zero the table entries in case some of them are not used. */
20031 memset (ptr, 0, (size << 2) + 4);
20032 where = frag_now_fix () - ((size << 2) + 4);
20034 switch (unwind.personality_index)
20037 /* ??? Should this be a PLT generating relocation? */
20038 /* Custom personality routine. */
20039 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20040 BFD_RELOC_ARM_PREL31);
20045 /* Set the first byte to the number of additional words. */
20046 data = size > 0 ? size - 1 : 0;
20050 /* ABI defined personality routines. */
20052 /* Three opcodes bytes are packed into the first word. */
20059 /* The size and first two opcode bytes go in the first word. */
20060 data = ((0x80 + unwind.personality_index) << 8) | size;
20065 /* Should never happen. */
20069 /* Pack the opcodes into words (MSB first), reversing the list at the same
20071 while (unwind.opcode_count > 0)
20075 md_number_to_chars (ptr, data, 4);
20080 unwind.opcode_count--;
20082 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20085 /* Finish off the last word. */
20088 /* Pad with "finish" opcodes. */
20090 data = (data << 8) | 0xb0;
20092 md_number_to_chars (ptr, data, 4);
20097 /* Add an empty descriptor if there is no user-specified data. */
20098 ptr = frag_more (4);
20099 md_number_to_chars (ptr, 0, 4);
20106 /* Initialize the DWARF-2 unwind information for this procedure. */
20109 tc_arm_frame_initial_instructions (void)
20111 cfi_add_CFA_def_cfa (REG_SP, 0);
20113 #endif /* OBJ_ELF */
20115 /* Convert REGNAME to a DWARF-2 register number. */
20118 tc_arm_regname_to_dw2regnum (char *regname)
20120 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20130 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20134 exp.X_op = O_secrel;
20135 exp.X_add_symbol = symbol;
20136 exp.X_add_number = 0;
20137 emit_expr (&exp, size);
20141 /* MD interface: Symbol and relocation handling. */
20143 /* Return the address within the segment that a PC-relative fixup is
20144 relative to. For ARM, PC-relative fixups applied to instructions
20145 are generally relative to the location of the fixup plus 8 bytes.
20146 Thumb branches are offset by 4, and Thumb loads relative to PC
20147 require special handling. */
20150 md_pcrel_from_section (fixS * fixP, segT seg)
20152 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20154 /* If this is pc-relative and we are going to emit a relocation
20155 then we just want to put out any pipeline compensation that the linker
20156 will need. Otherwise we want to use the calculated base.
20157 For WinCE we skip the bias for externals as well, since this
20158 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20160 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20161 || (arm_force_relocation (fixP)
20163 && !S_IS_EXTERNAL (fixP->fx_addsy)
20169 switch (fixP->fx_r_type)
20171 /* PC relative addressing on the Thumb is slightly odd as the
20172 bottom two bits of the PC are forced to zero for the
20173 calculation. This happens *after* application of the
20174 pipeline offset. However, Thumb adrl already adjusts for
20175 this, so we need not do it again. */
20176 case BFD_RELOC_ARM_THUMB_ADD:
20179 case BFD_RELOC_ARM_THUMB_OFFSET:
20180 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20181 case BFD_RELOC_ARM_T32_ADD_PC12:
20182 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20183 return (base + 4) & ~3;
20185 /* Thumb branches are simply offset by +4. */
20186 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20187 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20188 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20189 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20190 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20193 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20195 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20196 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20197 && ARM_IS_FUNC (fixP->fx_addsy)
20198 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20199 base = fixP->fx_where + fixP->fx_frag->fr_address;
20202 /* BLX is like branches above, but forces the low two bits of PC to
20204 case BFD_RELOC_THUMB_PCREL_BLX:
20206 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20207 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20208 && THUMB_IS_FUNC (fixP->fx_addsy)
20209 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20210 base = fixP->fx_where + fixP->fx_frag->fr_address;
20211 return (base + 4) & ~3;
20213 /* ARM mode branches are offset by +8. However, the Windows CE
20214 loader expects the relocation not to take this into account. */
20215 case BFD_RELOC_ARM_PCREL_BLX:
20217 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20218 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20219 && ARM_IS_FUNC (fixP->fx_addsy)
20220 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20221 base = fixP->fx_where + fixP->fx_frag->fr_address;
20224 case BFD_RELOC_ARM_PCREL_CALL:
20226 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20227 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20228 && THUMB_IS_FUNC (fixP->fx_addsy)
20229 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20230 base = fixP->fx_where + fixP->fx_frag->fr_address;
20233 case BFD_RELOC_ARM_PCREL_BRANCH:
20234 case BFD_RELOC_ARM_PCREL_JUMP:
20235 case BFD_RELOC_ARM_PLT32:
20237 /* When handling fixups immediately, because we have already
20238 discovered the value of a symbol, or the address of the frag involved
20239 we must account for the offset by +8, as the OS loader will never see the reloc.
20240 see fixup_segment() in write.c
20241 The S_IS_EXTERNAL test handles the case of global symbols.
20242 Those need the calculated base, not just the pipe compensation the linker will need. */
20244 && fixP->fx_addsy != NULL
20245 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20246 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20254 /* ARM mode loads relative to PC are also offset by +8. Unlike
20255 branches, the Windows CE loader *does* expect the relocation
20256 to take this into account. */
20257 case BFD_RELOC_ARM_OFFSET_IMM:
20258 case BFD_RELOC_ARM_OFFSET_IMM8:
20259 case BFD_RELOC_ARM_HWLITERAL:
20260 case BFD_RELOC_ARM_LITERAL:
20261 case BFD_RELOC_ARM_CP_OFF_IMM:
20265 /* Other PC-relative relocations are un-offset. */
20271 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20272 Otherwise we have no need to default values of symbols. */
20275 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20278 if (name[0] == '_' && name[1] == 'G'
20279 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20283 if (symbol_find (name))
20284 as_bad (_("GOT already in the symbol table"));
20286 GOT_symbol = symbol_new (name, undefined_section,
20287 (valueT) 0, & zero_address_frag);
20297 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20298 computed as two separate immediate values, added together. We
20299 already know that this value cannot be computed by just one ARM
20302 static unsigned int
20303 validate_immediate_twopart (unsigned int val,
20304 unsigned int * highpart)
20309 for (i = 0; i < 32; i += 2)
20310 if (((a = rotate_left (val, i)) & 0xff) != 0)
20316 * highpart = (a >> 8) | ((i + 24) << 7);
20318 else if (a & 0xff0000)
20320 if (a & 0xff000000)
20322 * highpart = (a >> 16) | ((i + 16) << 7);
20326 gas_assert (a & 0xff000000);
20327 * highpart = (a >> 24) | ((i + 8) << 7);
20330 return (a & 0xff) | (i << 7);
20337 validate_offset_imm (unsigned int val, int hwse)
20339 if ((hwse && val > 255) || val > 4095)
20344 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20345 negative immediate constant by altering the instruction. A bit of
20350 by inverting the second operand, and
20353 by negating the second operand. */
20356 negate_data_op (unsigned long * instruction,
20357 unsigned long value)
20360 unsigned long negated, inverted;
20362 negated = encode_arm_immediate (-value);
20363 inverted = encode_arm_immediate (~value);
20365 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20368 /* First negates. */
20369 case OPCODE_SUB: /* ADD <-> SUB */
20370 new_inst = OPCODE_ADD;
20375 new_inst = OPCODE_SUB;
20379 case OPCODE_CMP: /* CMP <-> CMN */
20380 new_inst = OPCODE_CMN;
20385 new_inst = OPCODE_CMP;
20389 /* Now Inverted ops. */
20390 case OPCODE_MOV: /* MOV <-> MVN */
20391 new_inst = OPCODE_MVN;
20396 new_inst = OPCODE_MOV;
20400 case OPCODE_AND: /* AND <-> BIC */
20401 new_inst = OPCODE_BIC;
20406 new_inst = OPCODE_AND;
20410 case OPCODE_ADC: /* ADC <-> SBC */
20411 new_inst = OPCODE_SBC;
20416 new_inst = OPCODE_ADC;
20420 /* We cannot do anything. */
20425 if (value == (unsigned) FAIL)
20428 *instruction &= OPCODE_MASK;
20429 *instruction |= new_inst << DATA_OP_SHIFT;
20433 /* Like negate_data_op, but for Thumb-2. */
20435 static unsigned int
20436 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20440 unsigned int negated, inverted;
20442 negated = encode_thumb32_immediate (-value);
20443 inverted = encode_thumb32_immediate (~value);
20445 rd = (*instruction >> 8) & 0xf;
20446 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20449 /* ADD <-> SUB. Includes CMP <-> CMN. */
20450 case T2_OPCODE_SUB:
20451 new_inst = T2_OPCODE_ADD;
20455 case T2_OPCODE_ADD:
20456 new_inst = T2_OPCODE_SUB;
20460 /* ORR <-> ORN. Includes MOV <-> MVN. */
20461 case T2_OPCODE_ORR:
20462 new_inst = T2_OPCODE_ORN;
20466 case T2_OPCODE_ORN:
20467 new_inst = T2_OPCODE_ORR;
20471 /* AND <-> BIC. TST has no inverted equivalent. */
20472 case T2_OPCODE_AND:
20473 new_inst = T2_OPCODE_BIC;
20480 case T2_OPCODE_BIC:
20481 new_inst = T2_OPCODE_AND;
20486 case T2_OPCODE_ADC:
20487 new_inst = T2_OPCODE_SBC;
20491 case T2_OPCODE_SBC:
20492 new_inst = T2_OPCODE_ADC;
20496 /* We cannot do anything. */
20501 if (value == (unsigned int)FAIL)
20504 *instruction &= T2_OPCODE_MASK;
20505 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20509 /* Read a 32-bit thumb instruction from buf. */
20510 static unsigned long
20511 get_thumb32_insn (char * buf)
20513 unsigned long insn;
20514 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20515 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20521 /* We usually want to set the low bit on the address of thumb function
20522 symbols. In particular .word foo - . should have the low bit set.
20523 Generic code tries to fold the difference of two symbols to
20524 a constant. Prevent this and force a relocation when the first symbols
20525 is a thumb function. */
20528 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20530 if (op == O_subtract
20531 && l->X_op == O_symbol
20532 && r->X_op == O_symbol
20533 && THUMB_IS_FUNC (l->X_add_symbol))
20535 l->X_op = O_subtract;
20536 l->X_op_symbol = r->X_add_symbol;
20537 l->X_add_number -= r->X_add_number;
20541 /* Process as normal. */
20545 /* Encode Thumb2 unconditional branches and calls. The encoding
20546 for the 2 are identical for the immediate values. */
20549 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20551 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20554 addressT S, I1, I2, lo, hi;
20556 S = (value >> 24) & 0x01;
20557 I1 = (value >> 23) & 0x01;
20558 I2 = (value >> 22) & 0x01;
20559 hi = (value >> 12) & 0x3ff;
20560 lo = (value >> 1) & 0x7ff;
20561 newval = md_chars_to_number (buf, THUMB_SIZE);
20562 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20563 newval |= (S << 10) | hi;
20564 newval2 &= ~T2I1I2MASK;
20565 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20566 md_number_to_chars (buf, newval, THUMB_SIZE);
20567 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20571 md_apply_fix (fixS * fixP,
20575 offsetT value = * valP;
20577 unsigned int newimm;
20578 unsigned long temp;
20580 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20582 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20584 /* Note whether this will delete the relocation. */
20586 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20589 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20590 consistency with the behaviour on 32-bit hosts. Remember value
20592 value &= 0xffffffff;
20593 value ^= 0x80000000;
20594 value -= 0x80000000;
20597 fixP->fx_addnumber = value;
20599 /* Same treatment for fixP->fx_offset. */
20600 fixP->fx_offset &= 0xffffffff;
20601 fixP->fx_offset ^= 0x80000000;
20602 fixP->fx_offset -= 0x80000000;
20604 switch (fixP->fx_r_type)
20606 case BFD_RELOC_NONE:
20607 /* This will need to go in the object file. */
20611 case BFD_RELOC_ARM_IMMEDIATE:
20612 /* We claim that this fixup has been processed here,
20613 even if in fact we generate an error because we do
20614 not have a reloc for it, so tc_gen_reloc will reject it. */
20617 if (fixP->fx_addsy)
20619 const char *msg = 0;
20621 if (! S_IS_DEFINED (fixP->fx_addsy))
20622 msg = _("undefined symbol %s used as an immediate value");
20623 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20624 msg = _("symbol %s is in a different section");
20625 else if (S_IS_WEAK (fixP->fx_addsy))
20626 msg = _("symbol %s is weak and may be overridden later");
20630 as_bad_where (fixP->fx_file, fixP->fx_line,
20631 msg, S_GET_NAME (fixP->fx_addsy));
20636 newimm = encode_arm_immediate (value);
20637 temp = md_chars_to_number (buf, INSN_SIZE);
20639 /* If the instruction will fail, see if we can fix things up by
20640 changing the opcode. */
20641 if (newimm == (unsigned int) FAIL
20642 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
20644 as_bad_where (fixP->fx_file, fixP->fx_line,
20645 _("invalid constant (%lx) after fixup"),
20646 (unsigned long) value);
20650 newimm |= (temp & 0xfffff000);
20651 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20654 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20656 unsigned int highpart = 0;
20657 unsigned int newinsn = 0xe1a00000; /* nop. */
20659 if (fixP->fx_addsy)
20661 const char *msg = 0;
20663 if (! S_IS_DEFINED (fixP->fx_addsy))
20664 msg = _("undefined symbol %s used as an immediate value");
20665 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20666 msg = _("symbol %s is in a different section");
20667 else if (S_IS_WEAK (fixP->fx_addsy))
20668 msg = _("symbol %s is weak and may be overridden later");
20672 as_bad_where (fixP->fx_file, fixP->fx_line,
20673 msg, S_GET_NAME (fixP->fx_addsy));
20678 newimm = encode_arm_immediate (value);
20679 temp = md_chars_to_number (buf, INSN_SIZE);
20681 /* If the instruction will fail, see if we can fix things up by
20682 changing the opcode. */
20683 if (newimm == (unsigned int) FAIL
20684 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20686 /* No ? OK - try using two ADD instructions to generate
20688 newimm = validate_immediate_twopart (value, & highpart);
20690 /* Yes - then make sure that the second instruction is
20692 if (newimm != (unsigned int) FAIL)
20694 /* Still No ? Try using a negated value. */
20695 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20696 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20697 /* Otherwise - give up. */
20700 as_bad_where (fixP->fx_file, fixP->fx_line,
20701 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20706 /* Replace the first operand in the 2nd instruction (which
20707 is the PC) with the destination register. We have
20708 already added in the PC in the first instruction and we
20709 do not want to do it again. */
20710 newinsn &= ~ 0xf0000;
20711 newinsn |= ((newinsn & 0x0f000) << 4);
20714 newimm |= (temp & 0xfffff000);
20715 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20717 highpart |= (newinsn & 0xfffff000);
20718 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20722 case BFD_RELOC_ARM_OFFSET_IMM:
20723 if (!fixP->fx_done && seg->use_rela_p)
20726 case BFD_RELOC_ARM_LITERAL:
20732 if (validate_offset_imm (value, 0) == FAIL)
20734 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20735 as_bad_where (fixP->fx_file, fixP->fx_line,
20736 _("invalid literal constant: pool needs to be closer"));
20738 as_bad_where (fixP->fx_file, fixP->fx_line,
20739 _("bad immediate value for offset (%ld)"),
20744 newval = md_chars_to_number (buf, INSN_SIZE);
20746 newval &= 0xfffff000;
20749 newval &= 0xff7ff000;
20750 newval |= value | (sign ? INDEX_UP : 0);
20752 md_number_to_chars (buf, newval, INSN_SIZE);
20755 case BFD_RELOC_ARM_OFFSET_IMM8:
20756 case BFD_RELOC_ARM_HWLITERAL:
20762 if (validate_offset_imm (value, 1) == FAIL)
20764 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20765 as_bad_where (fixP->fx_file, fixP->fx_line,
20766 _("invalid literal constant: pool needs to be closer"));
20768 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20773 newval = md_chars_to_number (buf, INSN_SIZE);
20775 newval &= 0xfffff0f0;
20778 newval &= 0xff7ff0f0;
20779 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20781 md_number_to_chars (buf, newval, INSN_SIZE);
20784 case BFD_RELOC_ARM_T32_OFFSET_U8:
20785 if (value < 0 || value > 1020 || value % 4 != 0)
20786 as_bad_where (fixP->fx_file, fixP->fx_line,
20787 _("bad immediate value for offset (%ld)"), (long) value);
20790 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20792 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20795 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20796 /* This is a complicated relocation used for all varieties of Thumb32
20797 load/store instruction with immediate offset:
20799 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20800 *4, optional writeback(W)
20801 (doubleword load/store)
20803 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20804 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20805 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20806 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20807 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20809 Uppercase letters indicate bits that are already encoded at
20810 this point. Lowercase letters are our problem. For the
20811 second block of instructions, the secondary opcode nybble
20812 (bits 8..11) is present, and bit 23 is zero, even if this is
20813 a PC-relative operation. */
20814 newval = md_chars_to_number (buf, THUMB_SIZE);
20816 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20818 if ((newval & 0xf0000000) == 0xe0000000)
20820 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20822 newval |= (1 << 23);
20825 if (value % 4 != 0)
20827 as_bad_where (fixP->fx_file, fixP->fx_line,
20828 _("offset not a multiple of 4"));
20834 as_bad_where (fixP->fx_file, fixP->fx_line,
20835 _("offset out of range"));
20840 else if ((newval & 0x000f0000) == 0x000f0000)
20842 /* PC-relative, 12-bit offset. */
20844 newval |= (1 << 23);
20849 as_bad_where (fixP->fx_file, fixP->fx_line,
20850 _("offset out of range"));
20855 else if ((newval & 0x00000100) == 0x00000100)
20857 /* Writeback: 8-bit, +/- offset. */
20859 newval |= (1 << 9);
20864 as_bad_where (fixP->fx_file, fixP->fx_line,
20865 _("offset out of range"));
20870 else if ((newval & 0x00000f00) == 0x00000e00)
20872 /* T-instruction: positive 8-bit offset. */
20873 if (value < 0 || value > 0xff)
20875 as_bad_where (fixP->fx_file, fixP->fx_line,
20876 _("offset out of range"));
20884 /* Positive 12-bit or negative 8-bit offset. */
20888 newval |= (1 << 23);
20898 as_bad_where (fixP->fx_file, fixP->fx_line,
20899 _("offset out of range"));
20906 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20907 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20910 case BFD_RELOC_ARM_SHIFT_IMM:
20911 newval = md_chars_to_number (buf, INSN_SIZE);
20912 if (((unsigned long) value) > 32
20914 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20916 as_bad_where (fixP->fx_file, fixP->fx_line,
20917 _("shift expression is too large"));
20922 /* Shifts of zero must be done as lsl. */
20924 else if (value == 32)
20926 newval &= 0xfffff07f;
20927 newval |= (value & 0x1f) << 7;
20928 md_number_to_chars (buf, newval, INSN_SIZE);
20931 case BFD_RELOC_ARM_T32_IMMEDIATE:
20932 case BFD_RELOC_ARM_T32_ADD_IMM:
20933 case BFD_RELOC_ARM_T32_IMM12:
20934 case BFD_RELOC_ARM_T32_ADD_PC12:
20935 /* We claim that this fixup has been processed here,
20936 even if in fact we generate an error because we do
20937 not have a reloc for it, so tc_gen_reloc will reject it. */
20941 && ! S_IS_DEFINED (fixP->fx_addsy))
20943 as_bad_where (fixP->fx_file, fixP->fx_line,
20944 _("undefined symbol %s used as an immediate value"),
20945 S_GET_NAME (fixP->fx_addsy));
20949 newval = md_chars_to_number (buf, THUMB_SIZE);
20951 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20954 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20955 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20957 newimm = encode_thumb32_immediate (value);
20958 if (newimm == (unsigned int) FAIL)
20959 newimm = thumb32_negate_data_op (&newval, value);
20961 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20962 && newimm == (unsigned int) FAIL)
20964 /* Turn add/sum into addw/subw. */
20965 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20966 newval = (newval & 0xfeffffff) | 0x02000000;
20967 /* No flat 12-bit imm encoding for addsw/subsw. */
20968 if ((newval & 0x00100000) == 0)
20970 /* 12 bit immediate for addw/subw. */
20974 newval ^= 0x00a00000;
20977 newimm = (unsigned int) FAIL;
20983 if (newimm == (unsigned int)FAIL)
20985 as_bad_where (fixP->fx_file, fixP->fx_line,
20986 _("invalid constant (%lx) after fixup"),
20987 (unsigned long) value);
20991 newval |= (newimm & 0x800) << 15;
20992 newval |= (newimm & 0x700) << 4;
20993 newval |= (newimm & 0x0ff);
20995 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
20996 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
20999 case BFD_RELOC_ARM_SMC:
21000 if (((unsigned long) value) > 0xffff)
21001 as_bad_where (fixP->fx_file, fixP->fx_line,
21002 _("invalid smc expression"));
21003 newval = md_chars_to_number (buf, INSN_SIZE);
21004 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21005 md_number_to_chars (buf, newval, INSN_SIZE);
21008 case BFD_RELOC_ARM_HVC:
21009 if (((unsigned long) value) > 0xffff)
21010 as_bad_where (fixP->fx_file, fixP->fx_line,
21011 _("invalid hvc expression"));
21012 newval = md_chars_to_number (buf, INSN_SIZE);
21013 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21014 md_number_to_chars (buf, newval, INSN_SIZE);
21017 case BFD_RELOC_ARM_SWI:
21018 if (fixP->tc_fix_data != 0)
21020 if (((unsigned long) value) > 0xff)
21021 as_bad_where (fixP->fx_file, fixP->fx_line,
21022 _("invalid swi expression"));
21023 newval = md_chars_to_number (buf, THUMB_SIZE);
21025 md_number_to_chars (buf, newval, THUMB_SIZE);
21029 if (((unsigned long) value) > 0x00ffffff)
21030 as_bad_where (fixP->fx_file, fixP->fx_line,
21031 _("invalid swi expression"));
21032 newval = md_chars_to_number (buf, INSN_SIZE);
21034 md_number_to_chars (buf, newval, INSN_SIZE);
21038 case BFD_RELOC_ARM_MULTI:
21039 if (((unsigned long) value) > 0xffff)
21040 as_bad_where (fixP->fx_file, fixP->fx_line,
21041 _("invalid expression in load/store multiple"));
21042 newval = value | md_chars_to_number (buf, INSN_SIZE);
21043 md_number_to_chars (buf, newval, INSN_SIZE);
21047 case BFD_RELOC_ARM_PCREL_CALL:
21049 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21051 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21052 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21053 && THUMB_IS_FUNC (fixP->fx_addsy))
21054 /* Flip the bl to blx. This is a simple flip
21055 bit here because we generate PCREL_CALL for
21056 unconditional bls. */
21058 newval = md_chars_to_number (buf, INSN_SIZE);
21059 newval = newval | 0x10000000;
21060 md_number_to_chars (buf, newval, INSN_SIZE);
21066 goto arm_branch_common;
21068 case BFD_RELOC_ARM_PCREL_JUMP:
21069 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21071 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21072 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21073 && THUMB_IS_FUNC (fixP->fx_addsy))
21075 /* This would map to a bl<cond>, b<cond>,
21076 b<always> to a Thumb function. We
21077 need to force a relocation for this particular
21079 newval = md_chars_to_number (buf, INSN_SIZE);
21083 case BFD_RELOC_ARM_PLT32:
21085 case BFD_RELOC_ARM_PCREL_BRANCH:
21087 goto arm_branch_common;
21089 case BFD_RELOC_ARM_PCREL_BLX:
21092 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21094 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21095 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21096 && ARM_IS_FUNC (fixP->fx_addsy))
21098 /* Flip the blx to a bl and warn. */
21099 const char *name = S_GET_NAME (fixP->fx_addsy);
21100 newval = 0xeb000000;
21101 as_warn_where (fixP->fx_file, fixP->fx_line,
21102 _("blx to '%s' an ARM ISA state function changed to bl"),
21104 md_number_to_chars (buf, newval, INSN_SIZE);
21110 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21111 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21115 /* We are going to store value (shifted right by two) in the
21116 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21117 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21118 also be be clear. */
21120 as_bad_where (fixP->fx_file, fixP->fx_line,
21121 _("misaligned branch destination"));
21122 if ((value & (offsetT)0xfe000000) != (offsetT)0
21123 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21124 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21126 if (fixP->fx_done || !seg->use_rela_p)
21128 newval = md_chars_to_number (buf, INSN_SIZE);
21129 newval |= (value >> 2) & 0x00ffffff;
21130 /* Set the H bit on BLX instructions. */
21134 newval |= 0x01000000;
21136 newval &= ~0x01000000;
21138 md_number_to_chars (buf, newval, INSN_SIZE);
21142 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21143 /* CBZ can only branch forward. */
21145 /* Attempts to use CBZ to branch to the next instruction
21146 (which, strictly speaking, are prohibited) will be turned into
21149 FIXME: It may be better to remove the instruction completely and
21150 perform relaxation. */
21153 newval = md_chars_to_number (buf, THUMB_SIZE);
21154 newval = 0xbf00; /* NOP encoding T1 */
21155 md_number_to_chars (buf, newval, THUMB_SIZE);
21160 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21162 if (fixP->fx_done || !seg->use_rela_p)
21164 newval = md_chars_to_number (buf, THUMB_SIZE);
21165 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21166 md_number_to_chars (buf, newval, THUMB_SIZE);
21171 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21172 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21173 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21175 if (fixP->fx_done || !seg->use_rela_p)
21177 newval = md_chars_to_number (buf, THUMB_SIZE);
21178 newval |= (value & 0x1ff) >> 1;
21179 md_number_to_chars (buf, newval, THUMB_SIZE);
21183 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21184 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21185 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21187 if (fixP->fx_done || !seg->use_rela_p)
21189 newval = md_chars_to_number (buf, THUMB_SIZE);
21190 newval |= (value & 0xfff) >> 1;
21191 md_number_to_chars (buf, newval, THUMB_SIZE);
21195 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21197 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21198 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21199 && ARM_IS_FUNC (fixP->fx_addsy)
21200 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21202 /* Force a relocation for a branch 20 bits wide. */
21205 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21206 as_bad_where (fixP->fx_file, fixP->fx_line,
21207 _("conditional branch out of range"));
21209 if (fixP->fx_done || !seg->use_rela_p)
21212 addressT S, J1, J2, lo, hi;
21214 S = (value & 0x00100000) >> 20;
21215 J2 = (value & 0x00080000) >> 19;
21216 J1 = (value & 0x00040000) >> 18;
21217 hi = (value & 0x0003f000) >> 12;
21218 lo = (value & 0x00000ffe) >> 1;
21220 newval = md_chars_to_number (buf, THUMB_SIZE);
21221 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21222 newval |= (S << 10) | hi;
21223 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21224 md_number_to_chars (buf, newval, THUMB_SIZE);
21225 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21229 case BFD_RELOC_THUMB_PCREL_BLX:
21230 /* If there is a blx from a thumb state function to
21231 another thumb function flip this to a bl and warn
21235 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21236 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21237 && THUMB_IS_FUNC (fixP->fx_addsy))
21239 const char *name = S_GET_NAME (fixP->fx_addsy);
21240 as_warn_where (fixP->fx_file, fixP->fx_line,
21241 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21243 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21244 newval = newval | 0x1000;
21245 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21246 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21251 goto thumb_bl_common;
21253 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21254 /* A bl from Thumb state ISA to an internal ARM state function
21255 is converted to a blx. */
21257 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21258 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21259 && ARM_IS_FUNC (fixP->fx_addsy)
21260 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21262 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21263 newval = newval & ~0x1000;
21264 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21265 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21272 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
21273 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21274 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21277 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21278 /* For a BLX instruction, make sure that the relocation is rounded up
21279 to a word boundary. This follows the semantics of the instruction
21280 which specifies that bit 1 of the target address will come from bit
21281 1 of the base address. */
21282 value = (value + 1) & ~ 1;
21284 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21286 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21287 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21288 else if ((value & ~0x1ffffff)
21289 && ((value & ~0x1ffffff) != ~0x1ffffff))
21290 as_bad_where (fixP->fx_file, fixP->fx_line,
21291 _("Thumb2 branch out of range"));
21294 if (fixP->fx_done || !seg->use_rela_p)
21295 encode_thumb2_b_bl_offset (buf, value);
21299 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21300 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21301 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21303 if (fixP->fx_done || !seg->use_rela_p)
21304 encode_thumb2_b_bl_offset (buf, value);
21309 if (fixP->fx_done || !seg->use_rela_p)
21310 md_number_to_chars (buf, value, 1);
21314 if (fixP->fx_done || !seg->use_rela_p)
21315 md_number_to_chars (buf, value, 2);
21319 case BFD_RELOC_ARM_TLS_CALL:
21320 case BFD_RELOC_ARM_THM_TLS_CALL:
21321 case BFD_RELOC_ARM_TLS_DESCSEQ:
21322 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21323 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21326 case BFD_RELOC_ARM_TLS_GOTDESC:
21327 case BFD_RELOC_ARM_TLS_GD32:
21328 case BFD_RELOC_ARM_TLS_LE32:
21329 case BFD_RELOC_ARM_TLS_IE32:
21330 case BFD_RELOC_ARM_TLS_LDM32:
21331 case BFD_RELOC_ARM_TLS_LDO32:
21332 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21335 case BFD_RELOC_ARM_GOT32:
21336 case BFD_RELOC_ARM_GOTOFF:
21337 if (fixP->fx_done || !seg->use_rela_p)
21338 md_number_to_chars (buf, 0, 4);
21341 case BFD_RELOC_ARM_GOT_PREL:
21342 if (fixP->fx_done || !seg->use_rela_p)
21343 md_number_to_chars (buf, value, 4);
21346 case BFD_RELOC_ARM_TARGET2:
21347 /* TARGET2 is not partial-inplace, so we need to write the
21348 addend here for REL targets, because it won't be written out
21349 during reloc processing later. */
21350 if (fixP->fx_done || !seg->use_rela_p)
21351 md_number_to_chars (buf, fixP->fx_offset, 4);
21355 case BFD_RELOC_RVA:
21357 case BFD_RELOC_ARM_TARGET1:
21358 case BFD_RELOC_ARM_ROSEGREL32:
21359 case BFD_RELOC_ARM_SBREL32:
21360 case BFD_RELOC_32_PCREL:
21362 case BFD_RELOC_32_SECREL:
21364 if (fixP->fx_done || !seg->use_rela_p)
21366 /* For WinCE we only do this for pcrel fixups. */
21367 if (fixP->fx_done || fixP->fx_pcrel)
21369 md_number_to_chars (buf, value, 4);
21373 case BFD_RELOC_ARM_PREL31:
21374 if (fixP->fx_done || !seg->use_rela_p)
21376 newval = md_chars_to_number (buf, 4) & 0x80000000;
21377 if ((value ^ (value >> 1)) & 0x40000000)
21379 as_bad_where (fixP->fx_file, fixP->fx_line,
21380 _("rel31 relocation overflow"));
21382 newval |= value & 0x7fffffff;
21383 md_number_to_chars (buf, newval, 4);
21388 case BFD_RELOC_ARM_CP_OFF_IMM:
21389 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21390 if (value < -1023 || value > 1023 || (value & 3))
21391 as_bad_where (fixP->fx_file, fixP->fx_line,
21392 _("co-processor offset out of range"));
21397 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21398 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21399 newval = md_chars_to_number (buf, INSN_SIZE);
21401 newval = get_thumb32_insn (buf);
21403 newval &= 0xffffff00;
21406 newval &= 0xff7fff00;
21407 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21409 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21410 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21411 md_number_to_chars (buf, newval, INSN_SIZE);
21413 put_thumb32_insn (buf, newval);
21416 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21417 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21418 if (value < -255 || value > 255)
21419 as_bad_where (fixP->fx_file, fixP->fx_line,
21420 _("co-processor offset out of range"));
21422 goto cp_off_common;
21424 case BFD_RELOC_ARM_THUMB_OFFSET:
21425 newval = md_chars_to_number (buf, THUMB_SIZE);
21426 /* Exactly what ranges, and where the offset is inserted depends
21427 on the type of instruction, we can establish this from the
21429 switch (newval >> 12)
21431 case 4: /* PC load. */
21432 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21433 forced to zero for these loads; md_pcrel_from has already
21434 compensated for this. */
21436 as_bad_where (fixP->fx_file, fixP->fx_line,
21437 _("invalid offset, target not word aligned (0x%08lX)"),
21438 (((unsigned long) fixP->fx_frag->fr_address
21439 + (unsigned long) fixP->fx_where) & ~3)
21440 + (unsigned long) value);
21442 if (value & ~0x3fc)
21443 as_bad_where (fixP->fx_file, fixP->fx_line,
21444 _("invalid offset, value too big (0x%08lX)"),
21447 newval |= value >> 2;
21450 case 9: /* SP load/store. */
21451 if (value & ~0x3fc)
21452 as_bad_where (fixP->fx_file, fixP->fx_line,
21453 _("invalid offset, value too big (0x%08lX)"),
21455 newval |= value >> 2;
21458 case 6: /* Word load/store. */
21460 as_bad_where (fixP->fx_file, fixP->fx_line,
21461 _("invalid offset, value too big (0x%08lX)"),
21463 newval |= value << 4; /* 6 - 2. */
21466 case 7: /* Byte load/store. */
21468 as_bad_where (fixP->fx_file, fixP->fx_line,
21469 _("invalid offset, value too big (0x%08lX)"),
21471 newval |= value << 6;
21474 case 8: /* Halfword load/store. */
21476 as_bad_where (fixP->fx_file, fixP->fx_line,
21477 _("invalid offset, value too big (0x%08lX)"),
21479 newval |= value << 5; /* 6 - 1. */
21483 as_bad_where (fixP->fx_file, fixP->fx_line,
21484 "Unable to process relocation for thumb opcode: %lx",
21485 (unsigned long) newval);
21488 md_number_to_chars (buf, newval, THUMB_SIZE);
21491 case BFD_RELOC_ARM_THUMB_ADD:
21492 /* This is a complicated relocation, since we use it for all of
21493 the following immediate relocations:
21497 9bit ADD/SUB SP word-aligned
21498 10bit ADD PC/SP word-aligned
21500 The type of instruction being processed is encoded in the
21507 newval = md_chars_to_number (buf, THUMB_SIZE);
21509 int rd = (newval >> 4) & 0xf;
21510 int rs = newval & 0xf;
21511 int subtract = !!(newval & 0x8000);
21513 /* Check for HI regs, only very restricted cases allowed:
21514 Adjusting SP, and using PC or SP to get an address. */
21515 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21516 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21517 as_bad_where (fixP->fx_file, fixP->fx_line,
21518 _("invalid Hi register with immediate"));
21520 /* If value is negative, choose the opposite instruction. */
21524 subtract = !subtract;
21526 as_bad_where (fixP->fx_file, fixP->fx_line,
21527 _("immediate value out of range"));
21532 if (value & ~0x1fc)
21533 as_bad_where (fixP->fx_file, fixP->fx_line,
21534 _("invalid immediate for stack address calculation"));
21535 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21536 newval |= value >> 2;
21538 else if (rs == REG_PC || rs == REG_SP)
21540 if (subtract || value & ~0x3fc)
21541 as_bad_where (fixP->fx_file, fixP->fx_line,
21542 _("invalid immediate for address calculation (value = 0x%08lX)"),
21543 (unsigned long) value);
21544 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21546 newval |= value >> 2;
21551 as_bad_where (fixP->fx_file, fixP->fx_line,
21552 _("immediate value out of range"));
21553 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21554 newval |= (rd << 8) | value;
21559 as_bad_where (fixP->fx_file, fixP->fx_line,
21560 _("immediate value out of range"));
21561 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21562 newval |= rd | (rs << 3) | (value << 6);
21565 md_number_to_chars (buf, newval, THUMB_SIZE);
21568 case BFD_RELOC_ARM_THUMB_IMM:
21569 newval = md_chars_to_number (buf, THUMB_SIZE);
21570 if (value < 0 || value > 255)
21571 as_bad_where (fixP->fx_file, fixP->fx_line,
21572 _("invalid immediate: %ld is out of range"),
21575 md_number_to_chars (buf, newval, THUMB_SIZE);
21578 case BFD_RELOC_ARM_THUMB_SHIFT:
21579 /* 5bit shift value (0..32). LSL cannot take 32. */
21580 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21581 temp = newval & 0xf800;
21582 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21583 as_bad_where (fixP->fx_file, fixP->fx_line,
21584 _("invalid shift value: %ld"), (long) value);
21585 /* Shifts of zero must be encoded as LSL. */
21587 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21588 /* Shifts of 32 are encoded as zero. */
21589 else if (value == 32)
21591 newval |= value << 6;
21592 md_number_to_chars (buf, newval, THUMB_SIZE);
21595 case BFD_RELOC_VTABLE_INHERIT:
21596 case BFD_RELOC_VTABLE_ENTRY:
21600 case BFD_RELOC_ARM_MOVW:
21601 case BFD_RELOC_ARM_MOVT:
21602 case BFD_RELOC_ARM_THUMB_MOVW:
21603 case BFD_RELOC_ARM_THUMB_MOVT:
21604 if (fixP->fx_done || !seg->use_rela_p)
21606 /* REL format relocations are limited to a 16-bit addend. */
21607 if (!fixP->fx_done)
21609 if (value < -0x8000 || value > 0x7fff)
21610 as_bad_where (fixP->fx_file, fixP->fx_line,
21611 _("offset out of range"));
21613 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21614 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21619 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21620 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21622 newval = get_thumb32_insn (buf);
21623 newval &= 0xfbf08f00;
21624 newval |= (value & 0xf000) << 4;
21625 newval |= (value & 0x0800) << 15;
21626 newval |= (value & 0x0700) << 4;
21627 newval |= (value & 0x00ff);
21628 put_thumb32_insn (buf, newval);
21632 newval = md_chars_to_number (buf, 4);
21633 newval &= 0xfff0f000;
21634 newval |= value & 0x0fff;
21635 newval |= (value & 0xf000) << 4;
21636 md_number_to_chars (buf, newval, 4);
21641 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21642 case BFD_RELOC_ARM_ALU_PC_G0:
21643 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21644 case BFD_RELOC_ARM_ALU_PC_G1:
21645 case BFD_RELOC_ARM_ALU_PC_G2:
21646 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21647 case BFD_RELOC_ARM_ALU_SB_G0:
21648 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21649 case BFD_RELOC_ARM_ALU_SB_G1:
21650 case BFD_RELOC_ARM_ALU_SB_G2:
21651 gas_assert (!fixP->fx_done);
21652 if (!seg->use_rela_p)
21655 bfd_vma encoded_addend;
21656 bfd_vma addend_abs = abs (value);
21658 /* Check that the absolute value of the addend can be
21659 expressed as an 8-bit constant plus a rotation. */
21660 encoded_addend = encode_arm_immediate (addend_abs);
21661 if (encoded_addend == (unsigned int) FAIL)
21662 as_bad_where (fixP->fx_file, fixP->fx_line,
21663 _("the offset 0x%08lX is not representable"),
21664 (unsigned long) addend_abs);
21666 /* Extract the instruction. */
21667 insn = md_chars_to_number (buf, INSN_SIZE);
21669 /* If the addend is positive, use an ADD instruction.
21670 Otherwise use a SUB. Take care not to destroy the S bit. */
21671 insn &= 0xff1fffff;
21677 /* Place the encoded addend into the first 12 bits of the
21679 insn &= 0xfffff000;
21680 insn |= encoded_addend;
21682 /* Update the instruction. */
21683 md_number_to_chars (buf, insn, INSN_SIZE);
21687 case BFD_RELOC_ARM_LDR_PC_G0:
21688 case BFD_RELOC_ARM_LDR_PC_G1:
21689 case BFD_RELOC_ARM_LDR_PC_G2:
21690 case BFD_RELOC_ARM_LDR_SB_G0:
21691 case BFD_RELOC_ARM_LDR_SB_G1:
21692 case BFD_RELOC_ARM_LDR_SB_G2:
21693 gas_assert (!fixP->fx_done);
21694 if (!seg->use_rela_p)
21697 bfd_vma addend_abs = abs (value);
21699 /* Check that the absolute value of the addend can be
21700 encoded in 12 bits. */
21701 if (addend_abs >= 0x1000)
21702 as_bad_where (fixP->fx_file, fixP->fx_line,
21703 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21704 (unsigned long) addend_abs);
21706 /* Extract the instruction. */
21707 insn = md_chars_to_number (buf, INSN_SIZE);
21709 /* If the addend is negative, clear bit 23 of the instruction.
21710 Otherwise set it. */
21712 insn &= ~(1 << 23);
21716 /* Place the absolute value of the addend into the first 12 bits
21717 of the instruction. */
21718 insn &= 0xfffff000;
21719 insn |= addend_abs;
21721 /* Update the instruction. */
21722 md_number_to_chars (buf, insn, INSN_SIZE);
21726 case BFD_RELOC_ARM_LDRS_PC_G0:
21727 case BFD_RELOC_ARM_LDRS_PC_G1:
21728 case BFD_RELOC_ARM_LDRS_PC_G2:
21729 case BFD_RELOC_ARM_LDRS_SB_G0:
21730 case BFD_RELOC_ARM_LDRS_SB_G1:
21731 case BFD_RELOC_ARM_LDRS_SB_G2:
21732 gas_assert (!fixP->fx_done);
21733 if (!seg->use_rela_p)
21736 bfd_vma addend_abs = abs (value);
21738 /* Check that the absolute value of the addend can be
21739 encoded in 8 bits. */
21740 if (addend_abs >= 0x100)
21741 as_bad_where (fixP->fx_file, fixP->fx_line,
21742 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21743 (unsigned long) addend_abs);
21745 /* Extract the instruction. */
21746 insn = md_chars_to_number (buf, INSN_SIZE);
21748 /* If the addend is negative, clear bit 23 of the instruction.
21749 Otherwise set it. */
21751 insn &= ~(1 << 23);
21755 /* Place the first four bits of the absolute value of the addend
21756 into the first 4 bits of the instruction, and the remaining
21757 four into bits 8 .. 11. */
21758 insn &= 0xfffff0f0;
21759 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21761 /* Update the instruction. */
21762 md_number_to_chars (buf, insn, INSN_SIZE);
21766 case BFD_RELOC_ARM_LDC_PC_G0:
21767 case BFD_RELOC_ARM_LDC_PC_G1:
21768 case BFD_RELOC_ARM_LDC_PC_G2:
21769 case BFD_RELOC_ARM_LDC_SB_G0:
21770 case BFD_RELOC_ARM_LDC_SB_G1:
21771 case BFD_RELOC_ARM_LDC_SB_G2:
21772 gas_assert (!fixP->fx_done);
21773 if (!seg->use_rela_p)
21776 bfd_vma addend_abs = abs (value);
21778 /* Check that the absolute value of the addend is a multiple of
21779 four and, when divided by four, fits in 8 bits. */
21780 if (addend_abs & 0x3)
21781 as_bad_where (fixP->fx_file, fixP->fx_line,
21782 _("bad offset 0x%08lX (must be word-aligned)"),
21783 (unsigned long) addend_abs);
21785 if ((addend_abs >> 2) > 0xff)
21786 as_bad_where (fixP->fx_file, fixP->fx_line,
21787 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21788 (unsigned long) addend_abs);
21790 /* Extract the instruction. */
21791 insn = md_chars_to_number (buf, INSN_SIZE);
21793 /* If the addend is negative, clear bit 23 of the instruction.
21794 Otherwise set it. */
21796 insn &= ~(1 << 23);
21800 /* Place the addend (divided by four) into the first eight
21801 bits of the instruction. */
21802 insn &= 0xfffffff0;
21803 insn |= addend_abs >> 2;
21805 /* Update the instruction. */
21806 md_number_to_chars (buf, insn, INSN_SIZE);
21810 case BFD_RELOC_ARM_V4BX:
21811 /* This will need to go in the object file. */
21815 case BFD_RELOC_UNUSED:
21817 as_bad_where (fixP->fx_file, fixP->fx_line,
21818 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21822 /* Translate internal representation of relocation info to BFD target
21826 tc_gen_reloc (asection *section, fixS *fixp)
21829 bfd_reloc_code_real_type code;
21831 reloc = (arelent *) xmalloc (sizeof (arelent));
21833 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21834 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21835 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21837 if (fixp->fx_pcrel)
21839 if (section->use_rela_p)
21840 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21842 fixp->fx_offset = reloc->address;
21844 reloc->addend = fixp->fx_offset;
21846 switch (fixp->fx_r_type)
21849 if (fixp->fx_pcrel)
21851 code = BFD_RELOC_8_PCREL;
21856 if (fixp->fx_pcrel)
21858 code = BFD_RELOC_16_PCREL;
21863 if (fixp->fx_pcrel)
21865 code = BFD_RELOC_32_PCREL;
21869 case BFD_RELOC_ARM_MOVW:
21870 if (fixp->fx_pcrel)
21872 code = BFD_RELOC_ARM_MOVW_PCREL;
21876 case BFD_RELOC_ARM_MOVT:
21877 if (fixp->fx_pcrel)
21879 code = BFD_RELOC_ARM_MOVT_PCREL;
21883 case BFD_RELOC_ARM_THUMB_MOVW:
21884 if (fixp->fx_pcrel)
21886 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21890 case BFD_RELOC_ARM_THUMB_MOVT:
21891 if (fixp->fx_pcrel)
21893 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21897 case BFD_RELOC_NONE:
21898 case BFD_RELOC_ARM_PCREL_BRANCH:
21899 case BFD_RELOC_ARM_PCREL_BLX:
21900 case BFD_RELOC_RVA:
21901 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21902 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21903 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21904 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21905 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21906 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21907 case BFD_RELOC_VTABLE_ENTRY:
21908 case BFD_RELOC_VTABLE_INHERIT:
21910 case BFD_RELOC_32_SECREL:
21912 code = fixp->fx_r_type;
21915 case BFD_RELOC_THUMB_PCREL_BLX:
21917 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21918 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21921 code = BFD_RELOC_THUMB_PCREL_BLX;
21924 case BFD_RELOC_ARM_LITERAL:
21925 case BFD_RELOC_ARM_HWLITERAL:
21926 /* If this is called then the a literal has
21927 been referenced across a section boundary. */
21928 as_bad_where (fixp->fx_file, fixp->fx_line,
21929 _("literal referenced across section boundary"));
21933 case BFD_RELOC_ARM_TLS_CALL:
21934 case BFD_RELOC_ARM_THM_TLS_CALL:
21935 case BFD_RELOC_ARM_TLS_DESCSEQ:
21936 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21937 case BFD_RELOC_ARM_GOT32:
21938 case BFD_RELOC_ARM_GOTOFF:
21939 case BFD_RELOC_ARM_GOT_PREL:
21940 case BFD_RELOC_ARM_PLT32:
21941 case BFD_RELOC_ARM_TARGET1:
21942 case BFD_RELOC_ARM_ROSEGREL32:
21943 case BFD_RELOC_ARM_SBREL32:
21944 case BFD_RELOC_ARM_PREL31:
21945 case BFD_RELOC_ARM_TARGET2:
21946 case BFD_RELOC_ARM_TLS_LE32:
21947 case BFD_RELOC_ARM_TLS_LDO32:
21948 case BFD_RELOC_ARM_PCREL_CALL:
21949 case BFD_RELOC_ARM_PCREL_JUMP:
21950 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21951 case BFD_RELOC_ARM_ALU_PC_G0:
21952 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21953 case BFD_RELOC_ARM_ALU_PC_G1:
21954 case BFD_RELOC_ARM_ALU_PC_G2:
21955 case BFD_RELOC_ARM_LDR_PC_G0:
21956 case BFD_RELOC_ARM_LDR_PC_G1:
21957 case BFD_RELOC_ARM_LDR_PC_G2:
21958 case BFD_RELOC_ARM_LDRS_PC_G0:
21959 case BFD_RELOC_ARM_LDRS_PC_G1:
21960 case BFD_RELOC_ARM_LDRS_PC_G2:
21961 case BFD_RELOC_ARM_LDC_PC_G0:
21962 case BFD_RELOC_ARM_LDC_PC_G1:
21963 case BFD_RELOC_ARM_LDC_PC_G2:
21964 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21965 case BFD_RELOC_ARM_ALU_SB_G0:
21966 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21967 case BFD_RELOC_ARM_ALU_SB_G1:
21968 case BFD_RELOC_ARM_ALU_SB_G2:
21969 case BFD_RELOC_ARM_LDR_SB_G0:
21970 case BFD_RELOC_ARM_LDR_SB_G1:
21971 case BFD_RELOC_ARM_LDR_SB_G2:
21972 case BFD_RELOC_ARM_LDRS_SB_G0:
21973 case BFD_RELOC_ARM_LDRS_SB_G1:
21974 case BFD_RELOC_ARM_LDRS_SB_G2:
21975 case BFD_RELOC_ARM_LDC_SB_G0:
21976 case BFD_RELOC_ARM_LDC_SB_G1:
21977 case BFD_RELOC_ARM_LDC_SB_G2:
21978 case BFD_RELOC_ARM_V4BX:
21979 code = fixp->fx_r_type;
21982 case BFD_RELOC_ARM_TLS_GOTDESC:
21983 case BFD_RELOC_ARM_TLS_GD32:
21984 case BFD_RELOC_ARM_TLS_IE32:
21985 case BFD_RELOC_ARM_TLS_LDM32:
21986 /* BFD will include the symbol's address in the addend.
21987 But we don't want that, so subtract it out again here. */
21988 if (!S_IS_COMMON (fixp->fx_addsy))
21989 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21990 code = fixp->fx_r_type;
21994 case BFD_RELOC_ARM_IMMEDIATE:
21995 as_bad_where (fixp->fx_file, fixp->fx_line,
21996 _("internal relocation (type: IMMEDIATE) not fixed up"));
21999 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22000 as_bad_where (fixp->fx_file, fixp->fx_line,
22001 _("ADRL used for a symbol not defined in the same file"));
22004 case BFD_RELOC_ARM_OFFSET_IMM:
22005 if (section->use_rela_p)
22007 code = fixp->fx_r_type;
22011 if (fixp->fx_addsy != NULL
22012 && !S_IS_DEFINED (fixp->fx_addsy)
22013 && S_IS_LOCAL (fixp->fx_addsy))
22015 as_bad_where (fixp->fx_file, fixp->fx_line,
22016 _("undefined local label `%s'"),
22017 S_GET_NAME (fixp->fx_addsy));
22021 as_bad_where (fixp->fx_file, fixp->fx_line,
22022 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22029 switch (fixp->fx_r_type)
22031 case BFD_RELOC_NONE: type = "NONE"; break;
22032 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22033 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22034 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22035 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22036 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22037 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22038 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22039 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22040 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22041 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22042 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22043 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22044 default: type = _("<unknown>"); break;
22046 as_bad_where (fixp->fx_file, fixp->fx_line,
22047 _("cannot represent %s relocation in this object file format"),
22054 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22056 && fixp->fx_addsy == GOT_symbol)
22058 code = BFD_RELOC_ARM_GOTPC;
22059 reloc->addend = fixp->fx_offset = reloc->address;
22063 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22065 if (reloc->howto == NULL)
22067 as_bad_where (fixp->fx_file, fixp->fx_line,
22068 _("cannot represent %s relocation in this object file format"),
22069 bfd_get_reloc_code_name (code));
22073 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22074 vtable entry to be used in the relocation's section offset. */
22075 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22076 reloc->address = fixp->fx_offset;
22081 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22084 cons_fix_new_arm (fragS * frag,
22089 bfd_reloc_code_real_type type;
22093 FIXME: @@ Should look at CPU word size. */
22097 type = BFD_RELOC_8;
22100 type = BFD_RELOC_16;
22104 type = BFD_RELOC_32;
22107 type = BFD_RELOC_64;
22112 if (exp->X_op == O_secrel)
22114 exp->X_op = O_symbol;
22115 type = BFD_RELOC_32_SECREL;
22119 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22122 #if defined (OBJ_COFF)
22124 arm_validate_fix (fixS * fixP)
22126 /* If the destination of the branch is a defined symbol which does not have
22127 the THUMB_FUNC attribute, then we must be calling a function which has
22128 the (interfacearm) attribute. We look for the Thumb entry point to that
22129 function and change the branch to refer to that function instead. */
22130 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22131 && fixP->fx_addsy != NULL
22132 && S_IS_DEFINED (fixP->fx_addsy)
22133 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22135 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22142 arm_force_relocation (struct fix * fixp)
22144 #if defined (OBJ_COFF) && defined (TE_PE)
22145 if (fixp->fx_r_type == BFD_RELOC_RVA)
22149 /* In case we have a call or a branch to a function in ARM ISA mode from
22150 a thumb function or vice-versa force the relocation. These relocations
22151 are cleared off for some cores that might have blx and simple transformations
22155 switch (fixp->fx_r_type)
22157 case BFD_RELOC_ARM_PCREL_JUMP:
22158 case BFD_RELOC_ARM_PCREL_CALL:
22159 case BFD_RELOC_THUMB_PCREL_BLX:
22160 if (THUMB_IS_FUNC (fixp->fx_addsy))
22164 case BFD_RELOC_ARM_PCREL_BLX:
22165 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22166 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22167 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22168 if (ARM_IS_FUNC (fixp->fx_addsy))
22177 /* Resolve these relocations even if the symbol is extern or weak.
22178 Technically this is probably wrong due to symbol preemption.
22179 In practice these relocations do not have enough range to be useful
22180 at dynamic link time, and some code (e.g. in the Linux kernel)
22181 expects these references to be resolved. */
22182 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22183 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22184 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22185 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22186 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22187 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22188 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22189 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22190 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22191 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22192 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22193 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22194 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22195 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22198 /* Always leave these relocations for the linker. */
22199 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22200 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22201 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22204 /* Always generate relocations against function symbols. */
22205 if (fixp->fx_r_type == BFD_RELOC_32
22207 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22210 return generic_force_reloc (fixp);
22213 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22214 /* Relocations against function names must be left unadjusted,
22215 so that the linker can use this information to generate interworking
22216 stubs. The MIPS version of this function
22217 also prevents relocations that are mips-16 specific, but I do not
22218 know why it does this.
22221 There is one other problem that ought to be addressed here, but
22222 which currently is not: Taking the address of a label (rather
22223 than a function) and then later jumping to that address. Such
22224 addresses also ought to have their bottom bit set (assuming that
22225 they reside in Thumb code), but at the moment they will not. */
22228 arm_fix_adjustable (fixS * fixP)
22230 if (fixP->fx_addsy == NULL)
22233 /* Preserve relocations against symbols with function type. */
22234 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22237 if (THUMB_IS_FUNC (fixP->fx_addsy)
22238 && fixP->fx_subsy == NULL)
22241 /* We need the symbol name for the VTABLE entries. */
22242 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22243 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22246 /* Don't allow symbols to be discarded on GOT related relocs. */
22247 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22248 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22249 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22250 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22251 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22252 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22253 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22254 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22255 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22256 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22257 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22258 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22259 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22260 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22263 /* Similarly for group relocations. */
22264 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22265 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22266 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22269 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22270 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22271 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22272 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22273 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22274 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22275 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22276 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22277 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22282 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22287 elf32_arm_target_format (void)
22290 return (target_big_endian
22291 ? "elf32-bigarm-symbian"
22292 : "elf32-littlearm-symbian");
22293 #elif defined (TE_VXWORKS)
22294 return (target_big_endian
22295 ? "elf32-bigarm-vxworks"
22296 : "elf32-littlearm-vxworks");
22297 #elif defined (TE_NACL)
22298 return (target_big_endian
22299 ? "elf32-bigarm-nacl"
22300 : "elf32-littlearm-nacl");
22302 if (target_big_endian)
22303 return "elf32-bigarm";
22305 return "elf32-littlearm";
22310 armelf_frob_symbol (symbolS * symp,
22313 elf_frob_symbol (symp, puntp);
22317 /* MD interface: Finalization. */
22322 literal_pool * pool;
22324 /* Ensure that all the IT blocks are properly closed. */
22325 check_it_blocks_finished ();
22327 for (pool = list_of_pools; pool; pool = pool->next)
22329 /* Put it at the end of the relevant section. */
22330 subseg_set (pool->section, pool->sub_section);
22332 arm_elf_change_section ();
22339 /* Remove any excess mapping symbols generated for alignment frags in
22340 SEC. We may have created a mapping symbol before a zero byte
22341 alignment; remove it if there's a mapping symbol after the
22344 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22345 void *dummy ATTRIBUTE_UNUSED)
22347 segment_info_type *seginfo = seg_info (sec);
22350 if (seginfo == NULL || seginfo->frchainP == NULL)
22353 for (fragp = seginfo->frchainP->frch_root;
22355 fragp = fragp->fr_next)
22357 symbolS *sym = fragp->tc_frag_data.last_map;
22358 fragS *next = fragp->fr_next;
22360 /* Variable-sized frags have been converted to fixed size by
22361 this point. But if this was variable-sized to start with,
22362 there will be a fixed-size frag after it. So don't handle
22364 if (sym == NULL || next == NULL)
22367 if (S_GET_VALUE (sym) < next->fr_address)
22368 /* Not at the end of this frag. */
22370 know (S_GET_VALUE (sym) == next->fr_address);
22374 if (next->tc_frag_data.first_map != NULL)
22376 /* Next frag starts with a mapping symbol. Discard this
22378 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22382 if (next->fr_next == NULL)
22384 /* This mapping symbol is at the end of the section. Discard
22386 know (next->fr_fix == 0 && next->fr_var == 0);
22387 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22391 /* As long as we have empty frags without any mapping symbols,
22393 /* If the next frag is non-empty and does not start with a
22394 mapping symbol, then this mapping symbol is required. */
22395 if (next->fr_address != next->fr_next->fr_address)
22398 next = next->fr_next;
22400 while (next != NULL);
22405 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22409 arm_adjust_symtab (void)
22414 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22416 if (ARM_IS_THUMB (sym))
22418 if (THUMB_IS_FUNC (sym))
22420 /* Mark the symbol as a Thumb function. */
22421 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22422 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22423 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22425 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22426 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22428 as_bad (_("%s: unexpected function type: %d"),
22429 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22431 else switch (S_GET_STORAGE_CLASS (sym))
22434 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22437 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22440 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22448 if (ARM_IS_INTERWORK (sym))
22449 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22456 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22458 if (ARM_IS_THUMB (sym))
22460 elf_symbol_type * elf_sym;
22462 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22463 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22465 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22466 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22468 /* If it's a .thumb_func, declare it as so,
22469 otherwise tag label as .code 16. */
22470 if (THUMB_IS_FUNC (sym))
22471 elf_sym->internal_elf_sym.st_target_internal
22472 = ST_BRANCH_TO_THUMB;
22473 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22474 elf_sym->internal_elf_sym.st_info =
22475 ELF_ST_INFO (bind, STT_ARM_16BIT);
22480 /* Remove any overlapping mapping symbols generated by alignment frags. */
22481 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22482 /* Now do generic ELF adjustments. */
22483 elf_adjust_symtab ();
22487 /* MD interface: Initialization. */
22490 set_constant_flonums (void)
22494 for (i = 0; i < NUM_FLOAT_VALS; i++)
22495 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22499 /* Auto-select Thumb mode if it's the only available instruction set for the
22500 given architecture. */
22503 autoselect_thumb_from_cpu_variant (void)
22505 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22506 opcode_select (16);
22515 if ( (arm_ops_hsh = hash_new ()) == NULL
22516 || (arm_cond_hsh = hash_new ()) == NULL
22517 || (arm_shift_hsh = hash_new ()) == NULL
22518 || (arm_psr_hsh = hash_new ()) == NULL
22519 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22520 || (arm_reg_hsh = hash_new ()) == NULL
22521 || (arm_reloc_hsh = hash_new ()) == NULL
22522 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22523 as_fatal (_("virtual memory exhausted"));
22525 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22526 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22527 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22528 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22529 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22530 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22531 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22532 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22533 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22534 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22535 (void *) (v7m_psrs + i));
22536 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22537 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22539 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22541 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22542 (void *) (barrier_opt_names + i));
22544 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
22546 struct reloc_entry * entry = reloc_names + i;
22548 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
22549 /* This makes encode_branch() use the EABI versions of this relocation. */
22550 entry->reloc = BFD_RELOC_UNUSED;
22552 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
22556 set_constant_flonums ();
22558 /* Set the cpu variant based on the command-line options. We prefer
22559 -mcpu= over -march= if both are set (as for GCC); and we prefer
22560 -mfpu= over any other way of setting the floating point unit.
22561 Use of legacy options with new options are faulted. */
22564 if (mcpu_cpu_opt || march_cpu_opt)
22565 as_bad (_("use of old and new-style options to set CPU type"));
22567 mcpu_cpu_opt = legacy_cpu;
22569 else if (!mcpu_cpu_opt)
22570 mcpu_cpu_opt = march_cpu_opt;
22575 as_bad (_("use of old and new-style options to set FPU type"));
22577 mfpu_opt = legacy_fpu;
22579 else if (!mfpu_opt)
22581 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22582 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22583 /* Some environments specify a default FPU. If they don't, infer it
22584 from the processor. */
22586 mfpu_opt = mcpu_fpu_opt;
22588 mfpu_opt = march_fpu_opt;
22590 mfpu_opt = &fpu_default;
22596 if (mcpu_cpu_opt != NULL)
22597 mfpu_opt = &fpu_default;
22598 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22599 mfpu_opt = &fpu_arch_vfp_v2;
22601 mfpu_opt = &fpu_arch_fpa;
22607 mcpu_cpu_opt = &cpu_default;
22608 selected_cpu = cpu_default;
22612 selected_cpu = *mcpu_cpu_opt;
22614 mcpu_cpu_opt = &arm_arch_any;
22617 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22619 autoselect_thumb_from_cpu_variant ();
22621 arm_arch_used = thumb_arch_used = arm_arch_none;
22623 #if defined OBJ_COFF || defined OBJ_ELF
22625 unsigned int flags = 0;
22627 #if defined OBJ_ELF
22628 flags = meabi_flags;
22630 switch (meabi_flags)
22632 case EF_ARM_EABI_UNKNOWN:
22634 /* Set the flags in the private structure. */
22635 if (uses_apcs_26) flags |= F_APCS26;
22636 if (support_interwork) flags |= F_INTERWORK;
22637 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22638 if (pic_code) flags |= F_PIC;
22639 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22640 flags |= F_SOFT_FLOAT;
22642 switch (mfloat_abi_opt)
22644 case ARM_FLOAT_ABI_SOFT:
22645 case ARM_FLOAT_ABI_SOFTFP:
22646 flags |= F_SOFT_FLOAT;
22649 case ARM_FLOAT_ABI_HARD:
22650 if (flags & F_SOFT_FLOAT)
22651 as_bad (_("hard-float conflicts with specified fpu"));
22655 /* Using pure-endian doubles (even if soft-float). */
22656 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22657 flags |= F_VFP_FLOAT;
22659 #if defined OBJ_ELF
22660 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22661 flags |= EF_ARM_MAVERICK_FLOAT;
22664 case EF_ARM_EABI_VER4:
22665 case EF_ARM_EABI_VER5:
22666 /* No additional flags to set. */
22673 bfd_set_private_flags (stdoutput, flags);
22675 /* We have run out flags in the COFF header to encode the
22676 status of ATPCS support, so instead we create a dummy,
22677 empty, debug section called .arm.atpcs. */
22682 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22686 bfd_set_section_flags
22687 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22688 bfd_set_section_size (stdoutput, sec, 0);
22689 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22695 /* Record the CPU type as well. */
22696 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22697 mach = bfd_mach_arm_iWMMXt2;
22698 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22699 mach = bfd_mach_arm_iWMMXt;
22700 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22701 mach = bfd_mach_arm_XScale;
22702 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22703 mach = bfd_mach_arm_ep9312;
22704 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22705 mach = bfd_mach_arm_5TE;
22706 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22708 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22709 mach = bfd_mach_arm_5T;
22711 mach = bfd_mach_arm_5;
22713 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22715 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22716 mach = bfd_mach_arm_4T;
22718 mach = bfd_mach_arm_4;
22720 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22721 mach = bfd_mach_arm_3M;
22722 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22723 mach = bfd_mach_arm_3;
22724 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22725 mach = bfd_mach_arm_2a;
22726 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22727 mach = bfd_mach_arm_2;
22729 mach = bfd_mach_arm_unknown;
22731 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22734 /* Command line processing. */
22737 Invocation line includes a switch not recognized by the base assembler.
22738 See if it's a processor-specific option.
22740 This routine is somewhat complicated by the need for backwards
22741 compatibility (since older releases of gcc can't be changed).
22742 The new options try to make the interface as compatible as
22745 New options (supported) are:
22747 -mcpu=<cpu name> Assemble for selected processor
22748 -march=<architecture name> Assemble for selected architecture
22749 -mfpu=<fpu architecture> Assemble for selected FPU.
22750 -EB/-mbig-endian Big-endian
22751 -EL/-mlittle-endian Little-endian
22752 -k Generate PIC code
22753 -mthumb Start in Thumb mode
22754 -mthumb-interwork Code supports ARM/Thumb interworking
22756 -m[no-]warn-deprecated Warn about deprecated features
22758 For now we will also provide support for:
22760 -mapcs-32 32-bit Program counter
22761 -mapcs-26 26-bit Program counter
22762 -macps-float Floats passed in FP registers
22763 -mapcs-reentrant Reentrant code
22765 (sometime these will probably be replaced with -mapcs=<list of options>
22766 and -matpcs=<list of options>)
22768 The remaining options are only supported for back-wards compatibility.
22769 Cpu variants, the arm part is optional:
22770 -m[arm]1 Currently not supported.
22771 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22772 -m[arm]3 Arm 3 processor
22773 -m[arm]6[xx], Arm 6 processors
22774 -m[arm]7[xx][t][[d]m] Arm 7 processors
22775 -m[arm]8[10] Arm 8 processors
22776 -m[arm]9[20][tdmi] Arm 9 processors
22777 -mstrongarm[110[0]] StrongARM processors
22778 -mxscale XScale processors
22779 -m[arm]v[2345[t[e]]] Arm architectures
22780 -mall All (except the ARM1)
22782 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22783 -mfpe-old (No float load/store multiples)
22784 -mvfpxd VFP Single precision
22786 -mno-fpu Disable all floating point instructions
22788 The following CPU names are recognized:
22789 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22790 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22791 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22792 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22793 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22794 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22795 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22799 const char * md_shortopts = "m:k";
22801 #ifdef ARM_BI_ENDIAN
22802 #define OPTION_EB (OPTION_MD_BASE + 0)
22803 #define OPTION_EL (OPTION_MD_BASE + 1)
22805 #if TARGET_BYTES_BIG_ENDIAN
22806 #define OPTION_EB (OPTION_MD_BASE + 0)
22808 #define OPTION_EL (OPTION_MD_BASE + 1)
22811 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22813 struct option md_longopts[] =
22816 {"EB", no_argument, NULL, OPTION_EB},
22819 {"EL", no_argument, NULL, OPTION_EL},
22821 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22822 {NULL, no_argument, NULL, 0}
22825 size_t md_longopts_size = sizeof (md_longopts);
22827 struct arm_option_table
22829 char *option; /* Option name to match. */
22830 char *help; /* Help information. */
22831 int *var; /* Variable to change. */
22832 int value; /* What to change it to. */
22833 char *deprecated; /* If non-null, print this message. */
22836 struct arm_option_table arm_opts[] =
22838 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22839 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22840 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22841 &support_interwork, 1, NULL},
22842 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22843 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22844 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22846 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22847 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22848 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22849 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22852 /* These are recognized by the assembler, but have no affect on code. */
22853 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22854 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22856 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22857 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22858 &warn_on_deprecated, 0, NULL},
22859 {NULL, NULL, NULL, 0, NULL}
22862 struct arm_legacy_option_table
22864 char *option; /* Option name to match. */
22865 const arm_feature_set **var; /* Variable to change. */
22866 const arm_feature_set value; /* What to change it to. */
22867 char *deprecated; /* If non-null, print this message. */
22870 const struct arm_legacy_option_table arm_legacy_opts[] =
22872 /* DON'T add any new processors to this list -- we want the whole list
22873 to go away... Add them to the processors table instead. */
22874 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22875 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22876 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22877 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22878 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22879 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22880 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22881 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22882 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22883 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22884 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22885 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22886 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22887 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22888 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22889 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22890 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22891 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22892 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22893 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22894 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22895 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22896 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22897 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22898 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22899 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22900 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22901 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22902 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22903 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22904 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22905 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22906 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22907 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22908 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22909 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22910 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22911 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22912 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22913 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22914 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22915 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22916 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22917 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22918 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22919 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22920 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22921 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22922 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22923 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22924 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22925 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22926 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22927 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22928 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22929 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22930 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22931 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22932 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22933 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22934 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22935 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22936 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22937 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22938 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22939 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22940 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22941 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22942 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22943 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22944 N_("use -mcpu=strongarm110")},
22945 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22946 N_("use -mcpu=strongarm1100")},
22947 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22948 N_("use -mcpu=strongarm1110")},
22949 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22950 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22951 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22953 /* Architecture variants -- don't add any more to this list either. */
22954 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22955 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22956 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22957 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22958 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22959 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22960 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22961 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22962 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22963 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22964 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22965 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22966 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22967 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22968 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22969 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22970 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22971 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22973 /* Floating point variants -- don't add any more to this list either. */
22974 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22975 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22976 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22977 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
22978 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22980 {NULL, NULL, ARM_ARCH_NONE, NULL}
22983 struct arm_cpu_option_table
22987 const arm_feature_set value;
22988 /* For some CPUs we assume an FPU unless the user explicitly sets
22990 const arm_feature_set default_fpu;
22991 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22993 const char *canonical_name;
22996 /* This list should, at a minimum, contain all the cpu names
22997 recognized by GCC. */
22998 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
22999 static const struct arm_cpu_option_table arm_cpus[] =
23001 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23002 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23003 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23004 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23005 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23006 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23007 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23008 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23009 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23010 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23011 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23012 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23013 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23014 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23015 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23016 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23017 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23018 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23019 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23020 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23021 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23022 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23023 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23024 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23025 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23026 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23027 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23028 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23029 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23030 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23031 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23032 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23033 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23034 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23035 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23036 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23037 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23038 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23039 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23040 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23041 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23042 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23043 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23044 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23045 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23046 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23047 /* For V5 or later processors we default to using VFP; but the user
23048 should really set the FPU type explicitly. */
23049 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23050 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23051 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23052 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23053 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23054 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23055 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23056 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23057 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23058 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23059 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23060 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23061 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23062 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23063 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23064 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23065 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23066 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23067 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23068 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23070 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23071 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23072 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23073 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23074 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23075 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23076 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23077 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23078 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23080 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23081 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23082 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23083 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23084 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23085 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23086 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23087 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23088 FPU_NONE, "Cortex-A5"),
23089 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23090 FPU_ARCH_NEON_VFP_V4,
23092 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23093 ARM_FEATURE (0, FPU_VFP_V3
23094 | FPU_NEON_EXT_V1),
23096 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23097 ARM_FEATURE (0, FPU_VFP_V3
23098 | FPU_NEON_EXT_V1),
23100 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23101 FPU_ARCH_NEON_VFP_V4,
23103 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23104 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23106 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23107 FPU_NONE, "Cortex-R5"),
23108 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23109 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23110 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23111 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23112 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
23113 /* ??? XSCALE is really an architecture. */
23114 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23115 /* ??? iwmmxt is not a processor. */
23116 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23117 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23118 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23120 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23123 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23127 struct arm_arch_option_table
23131 const arm_feature_set value;
23132 const arm_feature_set default_fpu;
23135 /* This list should, at a minimum, contain all the architecture names
23136 recognized by GCC. */
23137 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23138 static const struct arm_arch_option_table arm_archs[] =
23140 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23141 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23142 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23143 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
23144 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
23145 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
23146 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
23147 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
23148 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
23149 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
23150 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
23151 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
23152 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
23153 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
23154 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
23155 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
23156 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
23157 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
23158 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
23159 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
23160 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
23161 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
23162 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
23163 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
23164 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
23165 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
23166 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
23167 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
23168 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
23169 /* The official spelling of the ARMv7 profile variants is the dashed form.
23170 Accept the non-dashed form for compatibility with old toolchains. */
23171 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23172 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23173 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23174 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23175 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23176 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23177 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
23178 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
23179 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
23180 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
23181 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23183 #undef ARM_ARCH_OPT
23185 /* ISA extensions in the co-processor and main instruction set space. */
23186 struct arm_option_extension_value_table
23190 const arm_feature_set value;
23191 const arm_feature_set allowed_archs;
23194 /* The following table must be in alphabetical order with a NULL last entry.
23196 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23197 static const struct arm_option_extension_value_table arm_extensions[] =
23199 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23200 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23201 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
23202 ARM_EXT_OPT ("iwmmxt2",
23203 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
23204 ARM_EXT_OPT ("maverick",
23205 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
23206 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
23207 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23208 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
23209 ARM_FEATURE (ARM_EXT_V6M, 0)),
23210 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23211 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
23212 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
23214 ARM_FEATURE (ARM_EXT_V7A, 0)),
23215 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
23216 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23220 /* ISA floating-point and Advanced SIMD extensions. */
23221 struct arm_option_fpu_value_table
23224 const arm_feature_set value;
23227 /* This list should, at a minimum, contain all the fpu names
23228 recognized by GCC. */
23229 static const struct arm_option_fpu_value_table arm_fpus[] =
23231 {"softfpa", FPU_NONE},
23232 {"fpe", FPU_ARCH_FPE},
23233 {"fpe2", FPU_ARCH_FPE},
23234 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23235 {"fpa", FPU_ARCH_FPA},
23236 {"fpa10", FPU_ARCH_FPA},
23237 {"fpa11", FPU_ARCH_FPA},
23238 {"arm7500fe", FPU_ARCH_FPA},
23239 {"softvfp", FPU_ARCH_VFP},
23240 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23241 {"vfp", FPU_ARCH_VFP_V2},
23242 {"vfp9", FPU_ARCH_VFP_V2},
23243 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23244 {"vfp10", FPU_ARCH_VFP_V2},
23245 {"vfp10-r0", FPU_ARCH_VFP_V1},
23246 {"vfpxd", FPU_ARCH_VFP_V1xD},
23247 {"vfpv2", FPU_ARCH_VFP_V2},
23248 {"vfpv3", FPU_ARCH_VFP_V3},
23249 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23250 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23251 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23252 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23253 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23254 {"arm1020t", FPU_ARCH_VFP_V1},
23255 {"arm1020e", FPU_ARCH_VFP_V2},
23256 {"arm1136jfs", FPU_ARCH_VFP_V2},
23257 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23258 {"maverick", FPU_ARCH_MAVERICK},
23259 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23260 {"neon-fp16", FPU_ARCH_NEON_FP16},
23261 {"vfpv4", FPU_ARCH_VFP_V4},
23262 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23263 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23264 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23265 {NULL, ARM_ARCH_NONE}
23268 struct arm_option_value_table
23274 static const struct arm_option_value_table arm_float_abis[] =
23276 {"hard", ARM_FLOAT_ABI_HARD},
23277 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23278 {"soft", ARM_FLOAT_ABI_SOFT},
23283 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23284 static const struct arm_option_value_table arm_eabis[] =
23286 {"gnu", EF_ARM_EABI_UNKNOWN},
23287 {"4", EF_ARM_EABI_VER4},
23288 {"5", EF_ARM_EABI_VER5},
23293 struct arm_long_option_table
23295 char * option; /* Substring to match. */
23296 char * help; /* Help information. */
23297 int (* func) (char * subopt); /* Function to decode sub-option. */
23298 char * deprecated; /* If non-null, print this message. */
23302 arm_parse_extension (char *str, const arm_feature_set **opt_p)
23304 arm_feature_set *ext_set = (arm_feature_set *)
23305 xmalloc (sizeof (arm_feature_set));
23307 /* We insist on extensions being specified in alphabetical order, and with
23308 extensions being added before being removed. We achieve this by having
23309 the global ARM_EXTENSIONS table in alphabetical order, and using the
23310 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23311 or removing it (0) and only allowing it to change in the order
23313 const struct arm_option_extension_value_table * opt = NULL;
23314 int adding_value = -1;
23316 /* Copy the feature set, so that we can modify it. */
23317 *ext_set = **opt_p;
23320 while (str != NULL && *str != 0)
23327 as_bad (_("invalid architectural extension"));
23332 ext = strchr (str, '+');
23337 len = strlen (str);
23339 if (len >= 2 && strncmp (str, "no", 2) == 0)
23341 if (adding_value != 0)
23344 opt = arm_extensions;
23352 if (adding_value == -1)
23355 opt = arm_extensions;
23357 else if (adding_value != 1)
23359 as_bad (_("must specify extensions to add before specifying "
23360 "those to remove"));
23367 as_bad (_("missing architectural extension"));
23371 gas_assert (adding_value != -1);
23372 gas_assert (opt != NULL);
23374 /* Scan over the options table trying to find an exact match. */
23375 for (; opt->name != NULL; opt++)
23376 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23378 /* Check we can apply the extension to this architecture. */
23379 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23381 as_bad (_("extension does not apply to the base architecture"));
23385 /* Add or remove the extension. */
23387 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23389 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23394 if (opt->name == NULL)
23396 /* Did we fail to find an extension because it wasn't specified in
23397 alphabetical order, or because it does not exist? */
23399 for (opt = arm_extensions; opt->name != NULL; opt++)
23400 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23403 if (opt->name == NULL)
23404 as_bad (_("unknown architectural extension `%s'"), str);
23406 as_bad (_("architectural extensions must be specified in "
23407 "alphabetical order"));
23413 /* We should skip the extension we've just matched the next time
23425 arm_parse_cpu (char *str)
23427 const struct arm_cpu_option_table *opt;
23428 char *ext = strchr (str, '+');
23434 len = strlen (str);
23438 as_bad (_("missing cpu name `%s'"), str);
23442 for (opt = arm_cpus; opt->name != NULL; opt++)
23443 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23445 mcpu_cpu_opt = &opt->value;
23446 mcpu_fpu_opt = &opt->default_fpu;
23447 if (opt->canonical_name)
23448 strcpy (selected_cpu_name, opt->canonical_name);
23453 for (i = 0; i < len; i++)
23454 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23455 selected_cpu_name[i] = 0;
23459 return arm_parse_extension (ext, &mcpu_cpu_opt);
23464 as_bad (_("unknown cpu `%s'"), str);
23469 arm_parse_arch (char *str)
23471 const struct arm_arch_option_table *opt;
23472 char *ext = strchr (str, '+');
23478 len = strlen (str);
23482 as_bad (_("missing architecture name `%s'"), str);
23486 for (opt = arm_archs; opt->name != NULL; opt++)
23487 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23489 march_cpu_opt = &opt->value;
23490 march_fpu_opt = &opt->default_fpu;
23491 strcpy (selected_cpu_name, opt->name);
23494 return arm_parse_extension (ext, &march_cpu_opt);
23499 as_bad (_("unknown architecture `%s'\n"), str);
23504 arm_parse_fpu (char * str)
23506 const struct arm_option_fpu_value_table * opt;
23508 for (opt = arm_fpus; opt->name != NULL; opt++)
23509 if (streq (opt->name, str))
23511 mfpu_opt = &opt->value;
23515 as_bad (_("unknown floating point format `%s'\n"), str);
23520 arm_parse_float_abi (char * str)
23522 const struct arm_option_value_table * opt;
23524 for (opt = arm_float_abis; opt->name != NULL; opt++)
23525 if (streq (opt->name, str))
23527 mfloat_abi_opt = opt->value;
23531 as_bad (_("unknown floating point abi `%s'\n"), str);
23537 arm_parse_eabi (char * str)
23539 const struct arm_option_value_table *opt;
23541 for (opt = arm_eabis; opt->name != NULL; opt++)
23542 if (streq (opt->name, str))
23544 meabi_flags = opt->value;
23547 as_bad (_("unknown EABI `%s'\n"), str);
23553 arm_parse_it_mode (char * str)
23555 bfd_boolean ret = TRUE;
23557 if (streq ("arm", str))
23558 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23559 else if (streq ("thumb", str))
23560 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23561 else if (streq ("always", str))
23562 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23563 else if (streq ("never", str))
23564 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23567 as_bad (_("unknown implicit IT mode `%s', should be "\
23568 "arm, thumb, always, or never."), str);
23575 struct arm_long_option_table arm_long_opts[] =
23577 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23578 arm_parse_cpu, NULL},
23579 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23580 arm_parse_arch, NULL},
23581 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23582 arm_parse_fpu, NULL},
23583 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23584 arm_parse_float_abi, NULL},
23586 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23587 arm_parse_eabi, NULL},
23589 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23590 arm_parse_it_mode, NULL},
23591 {NULL, NULL, 0, NULL}
23595 md_parse_option (int c, char * arg)
23597 struct arm_option_table *opt;
23598 const struct arm_legacy_option_table *fopt;
23599 struct arm_long_option_table *lopt;
23605 target_big_endian = 1;
23611 target_big_endian = 0;
23615 case OPTION_FIX_V4BX:
23620 /* Listing option. Just ignore these, we don't support additional
23625 for (opt = arm_opts; opt->option != NULL; opt++)
23627 if (c == opt->option[0]
23628 && ((arg == NULL && opt->option[1] == 0)
23629 || streq (arg, opt->option + 1)))
23631 /* If the option is deprecated, tell the user. */
23632 if (warn_on_deprecated && opt->deprecated != NULL)
23633 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23634 arg ? arg : "", _(opt->deprecated));
23636 if (opt->var != NULL)
23637 *opt->var = opt->value;
23643 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23645 if (c == fopt->option[0]
23646 && ((arg == NULL && fopt->option[1] == 0)
23647 || streq (arg, fopt->option + 1)))
23649 /* If the option is deprecated, tell the user. */
23650 if (warn_on_deprecated && fopt->deprecated != NULL)
23651 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23652 arg ? arg : "", _(fopt->deprecated));
23654 if (fopt->var != NULL)
23655 *fopt->var = &fopt->value;
23661 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23663 /* These options are expected to have an argument. */
23664 if (c == lopt->option[0]
23666 && strncmp (arg, lopt->option + 1,
23667 strlen (lopt->option + 1)) == 0)
23669 /* If the option is deprecated, tell the user. */
23670 if (warn_on_deprecated && lopt->deprecated != NULL)
23671 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23672 _(lopt->deprecated));
23674 /* Call the sup-option parser. */
23675 return lopt->func (arg + strlen (lopt->option) - 1);
23686 md_show_usage (FILE * fp)
23688 struct arm_option_table *opt;
23689 struct arm_long_option_table *lopt;
23691 fprintf (fp, _(" ARM-specific assembler options:\n"));
23693 for (opt = arm_opts; opt->option != NULL; opt++)
23694 if (opt->help != NULL)
23695 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23697 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23698 if (lopt->help != NULL)
23699 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23703 -EB assemble code for a big-endian cpu\n"));
23708 -EL assemble code for a little-endian cpu\n"));
23712 --fix-v4bx Allow BX in ARMv4 code\n"));
23720 arm_feature_set flags;
23721 } cpu_arch_ver_table;
23723 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23724 least features first. */
23725 static const cpu_arch_ver_table cpu_arch_ver[] =
23731 {4, ARM_ARCH_V5TE},
23732 {5, ARM_ARCH_V5TEJ},
23736 {11, ARM_ARCH_V6M},
23737 {12, ARM_ARCH_V6SM},
23738 {8, ARM_ARCH_V6T2},
23739 {10, ARM_ARCH_V7A},
23740 {10, ARM_ARCH_V7R},
23741 {10, ARM_ARCH_V7M},
23745 /* Set an attribute if it has not already been set by the user. */
23747 aeabi_set_attribute_int (int tag, int value)
23750 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23751 || !attributes_set_explicitly[tag])
23752 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23756 aeabi_set_attribute_string (int tag, const char *value)
23759 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23760 || !attributes_set_explicitly[tag])
23761 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23764 /* Set the public EABI object attributes. */
23766 aeabi_set_public_attributes (void)
23771 arm_feature_set flags;
23772 arm_feature_set tmp;
23773 const cpu_arch_ver_table *p;
23775 /* Choose the architecture based on the capabilities of the requested cpu
23776 (if any) and/or the instructions actually used. */
23777 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23778 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23779 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23781 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
23782 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
23784 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
23785 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
23787 /* Allow the user to override the reported architecture. */
23790 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23791 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23794 /* We need to make sure that the attributes do not identify us as v6S-M
23795 when the only v6S-M feature in use is the Operating System Extensions. */
23796 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23797 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23798 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23802 for (p = cpu_arch_ver; p->val; p++)
23804 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23807 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23811 /* The table lookup above finds the last architecture to contribute
23812 a new feature. Unfortunately, Tag13 is a subset of the union of
23813 v6T2 and v7-M, so it is never seen as contributing a new feature.
23814 We can not search for the last entry which is entirely used,
23815 because if no CPU is specified we build up only those flags
23816 actually used. Perhaps we should separate out the specified
23817 and implicit cases. Avoid taking this path for -march=all by
23818 checking for contradictory v7-A / v7-M features. */
23820 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23821 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23822 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23825 /* Tag_CPU_name. */
23826 if (selected_cpu_name[0])
23830 q = selected_cpu_name;
23831 if (strncmp (q, "armv", 4) == 0)
23836 for (i = 0; q[i]; i++)
23837 q[i] = TOUPPER (q[i]);
23839 aeabi_set_attribute_string (Tag_CPU_name, q);
23842 /* Tag_CPU_arch. */
23843 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23845 /* Tag_CPU_arch_profile. */
23846 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23848 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23850 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23855 if (profile != '\0')
23856 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
23858 /* Tag_ARM_ISA_use. */
23859 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23861 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23863 /* Tag_THUMB_ISA_use. */
23864 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23866 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23867 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23869 /* Tag_VFP_arch. */
23870 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23871 aeabi_set_attribute_int (Tag_VFP_arch,
23872 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23874 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23875 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23876 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23877 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23878 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23879 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23880 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23881 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23882 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23884 /* Tag_ABI_HardFP_use. */
23885 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23886 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23887 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23889 /* Tag_WMMX_arch. */
23890 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23891 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23892 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23893 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23895 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23896 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23897 aeabi_set_attribute_int
23898 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
23901 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23902 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
23903 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23907 We set Tag_DIV_use to two when integer divide instructions have been used
23908 in ARM state, or when Thumb integer divide instructions have been used,
23909 but we have no architecture profile set, nor have we any ARM instructions.
23911 For new architectures we will have to check these tests. */
23912 gas_assert (arch <= TAG_CPU_ARCH_V7E_M);
23913 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
23914 || (profile == '\0'
23915 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
23916 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
23917 aeabi_set_attribute_int (Tag_DIV_use, 2);
23919 /* Tag_MP_extension_use. */
23920 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23921 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23923 /* Tag Virtualization_use. */
23924 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
23926 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
23929 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
23932 /* Add the default contents for the .ARM.attributes section. */
23936 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23939 aeabi_set_public_attributes ();
23941 #endif /* OBJ_ELF */
23944 /* Parse a .cpu directive. */
23947 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
23949 const struct arm_cpu_option_table *opt;
23953 name = input_line_pointer;
23954 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23955 input_line_pointer++;
23956 saved_char = *input_line_pointer;
23957 *input_line_pointer = 0;
23959 /* Skip the first "all" entry. */
23960 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
23961 if (streq (opt->name, name))
23963 mcpu_cpu_opt = &opt->value;
23964 selected_cpu = opt->value;
23965 if (opt->canonical_name)
23966 strcpy (selected_cpu_name, opt->canonical_name);
23970 for (i = 0; opt->name[i]; i++)
23971 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23973 selected_cpu_name[i] = 0;
23975 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23976 *input_line_pointer = saved_char;
23977 demand_empty_rest_of_line ();
23980 as_bad (_("unknown cpu `%s'"), name);
23981 *input_line_pointer = saved_char;
23982 ignore_rest_of_line ();
23986 /* Parse a .arch directive. */
23989 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
23991 const struct arm_arch_option_table *opt;
23995 name = input_line_pointer;
23996 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23997 input_line_pointer++;
23998 saved_char = *input_line_pointer;
23999 *input_line_pointer = 0;
24001 /* Skip the first "all" entry. */
24002 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24003 if (streq (opt->name, name))
24005 mcpu_cpu_opt = &opt->value;
24006 selected_cpu = opt->value;
24007 strcpy (selected_cpu_name, opt->name);
24008 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24009 *input_line_pointer = saved_char;
24010 demand_empty_rest_of_line ();
24014 as_bad (_("unknown architecture `%s'\n"), name);
24015 *input_line_pointer = saved_char;
24016 ignore_rest_of_line ();
24020 /* Parse a .object_arch directive. */
24023 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24025 const struct arm_arch_option_table *opt;
24029 name = input_line_pointer;
24030 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24031 input_line_pointer++;
24032 saved_char = *input_line_pointer;
24033 *input_line_pointer = 0;
24035 /* Skip the first "all" entry. */
24036 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24037 if (streq (opt->name, name))
24039 object_arch = &opt->value;
24040 *input_line_pointer = saved_char;
24041 demand_empty_rest_of_line ();
24045 as_bad (_("unknown architecture `%s'\n"), name);
24046 *input_line_pointer = saved_char;
24047 ignore_rest_of_line ();
24050 /* Parse a .arch_extension directive. */
24053 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24055 const struct arm_option_extension_value_table *opt;
24058 int adding_value = 1;
24060 name = input_line_pointer;
24061 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24062 input_line_pointer++;
24063 saved_char = *input_line_pointer;
24064 *input_line_pointer = 0;
24066 if (strlen (name) >= 2
24067 && strncmp (name, "no", 2) == 0)
24073 for (opt = arm_extensions; opt->name != NULL; opt++)
24074 if (streq (opt->name, name))
24076 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
24078 as_bad (_("architectural extension `%s' is not allowed for the "
24079 "current base architecture"), name);
24084 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
24086 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
24088 mcpu_cpu_opt = &selected_cpu;
24089 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24090 *input_line_pointer = saved_char;
24091 demand_empty_rest_of_line ();
24095 if (opt->name == NULL)
24096 as_bad (_("unknown architecture `%s'\n"), name);
24098 *input_line_pointer = saved_char;
24099 ignore_rest_of_line ();
24102 /* Parse a .fpu directive. */
24105 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
24107 const struct arm_option_fpu_value_table *opt;
24111 name = input_line_pointer;
24112 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24113 input_line_pointer++;
24114 saved_char = *input_line_pointer;
24115 *input_line_pointer = 0;
24117 for (opt = arm_fpus; opt->name != NULL; opt++)
24118 if (streq (opt->name, name))
24120 mfpu_opt = &opt->value;
24121 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24122 *input_line_pointer = saved_char;
24123 demand_empty_rest_of_line ();
24127 as_bad (_("unknown floating point format `%s'\n"), name);
24128 *input_line_pointer = saved_char;
24129 ignore_rest_of_line ();
24132 /* Copy symbol information. */
24135 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
24137 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
24141 /* Given a symbolic attribute NAME, return the proper integer value.
24142 Returns -1 if the attribute is not known. */
24145 arm_convert_symbolic_attribute (const char *name)
24147 static const struct
24152 attribute_table[] =
24154 /* When you modify this table you should
24155 also modify the list in doc/c-arm.texi. */
24156 #define T(tag) {#tag, tag}
24157 T (Tag_CPU_raw_name),
24160 T (Tag_CPU_arch_profile),
24161 T (Tag_ARM_ISA_use),
24162 T (Tag_THUMB_ISA_use),
24166 T (Tag_Advanced_SIMD_arch),
24167 T (Tag_PCS_config),
24168 T (Tag_ABI_PCS_R9_use),
24169 T (Tag_ABI_PCS_RW_data),
24170 T (Tag_ABI_PCS_RO_data),
24171 T (Tag_ABI_PCS_GOT_use),
24172 T (Tag_ABI_PCS_wchar_t),
24173 T (Tag_ABI_FP_rounding),
24174 T (Tag_ABI_FP_denormal),
24175 T (Tag_ABI_FP_exceptions),
24176 T (Tag_ABI_FP_user_exceptions),
24177 T (Tag_ABI_FP_number_model),
24178 T (Tag_ABI_align_needed),
24179 T (Tag_ABI_align8_needed),
24180 T (Tag_ABI_align_preserved),
24181 T (Tag_ABI_align8_preserved),
24182 T (Tag_ABI_enum_size),
24183 T (Tag_ABI_HardFP_use),
24184 T (Tag_ABI_VFP_args),
24185 T (Tag_ABI_WMMX_args),
24186 T (Tag_ABI_optimization_goals),
24187 T (Tag_ABI_FP_optimization_goals),
24188 T (Tag_compatibility),
24189 T (Tag_CPU_unaligned_access),
24190 T (Tag_FP_HP_extension),
24191 T (Tag_VFP_HP_extension),
24192 T (Tag_ABI_FP_16bit_format),
24193 T (Tag_MPextension_use),
24195 T (Tag_nodefaults),
24196 T (Tag_also_compatible_with),
24197 T (Tag_conformance),
24199 T (Tag_Virtualization_use),
24200 /* We deliberately do not include Tag_MPextension_use_legacy. */
24208 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24209 if (streq (name, attribute_table[i].name))
24210 return attribute_table[i].tag;
24216 /* Apply sym value for relocations only in the case that
24217 they are for local symbols and you have the respective
24218 architectural feature for blx and simple switches. */
24220 arm_apply_sym_value (struct fix * fixP)
24223 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24224 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24226 switch (fixP->fx_r_type)
24228 case BFD_RELOC_ARM_PCREL_BLX:
24229 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24230 if (ARM_IS_FUNC (fixP->fx_addsy))
24234 case BFD_RELOC_ARM_PCREL_CALL:
24235 case BFD_RELOC_THUMB_PCREL_BLX:
24236 if (THUMB_IS_FUNC (fixP->fx_addsy))
24247 #endif /* OBJ_ELF */