1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
40 #include "opcode/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
60 symbolS * table_entry;
61 symbolS * personality_routine;
62 int personality_index;
63 /* The segment containing the function. */
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes;
70 /* The number of bytes pushed to the stack. */
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
80 /* Nonzero if an unwind_setfp directive has been seen. */
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored:1;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency = 0;
100 /* Types of processor to assemble for. */
101 #define ARM_1 ARM_ARCH_V1
102 #define ARM_2 ARM_ARCH_V2
103 #define ARM_3 ARM_ARCH_V2S
104 #define ARM_250 ARM_ARCH_V2S
105 #define ARM_6 ARM_ARCH_V3
106 #define ARM_7 ARM_ARCH_V3
107 #define ARM_8 ARM_ARCH_V4
108 #define ARM_9 ARM_ARCH_V4T
109 #define ARM_STRONG ARM_ARCH_V4
110 #define ARM_CPU_MASK 0x0000000f /* XXX? */
113 #if defined __XSCALE__
114 #define CPU_DEFAULT (ARM_ARCH_XSCALE)
116 #if defined __thumb__
117 #define CPU_DEFAULT (ARM_ARCH_V5T)
119 #define CPU_DEFAULT ARM_ANY
126 # define FPU_DEFAULT FPU_ARCH_FPA
127 # elif defined (TE_NetBSD)
129 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
131 /* Legacy a.out format. */
132 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
134 # elif defined (TE_VXWORKS)
135 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
137 /* For backwards compatibility, default to FPA. */
138 # define FPU_DEFAULT FPU_ARCH_FPA
140 #endif /* ifndef FPU_DEFAULT */
142 #define streq(a, b) (strcmp (a, b) == 0)
144 static unsigned long cpu_variant;
146 /* Flags stored in private area of BFD structure. */
147 static int uses_apcs_26 = FALSE;
148 static int atpcs = FALSE;
149 static int support_interwork = FALSE;
150 static int uses_apcs_float = FALSE;
151 static int pic_code = FALSE;
153 /* Variables that we set while parsing command-line options. Once all
154 options have been read we re-process these values to set the real
156 static int legacy_cpu = -1;
157 static int legacy_fpu = -1;
159 static int mcpu_cpu_opt = -1;
160 static int mcpu_fpu_opt = -1;
161 static int march_cpu_opt = -1;
162 static int march_fpu_opt = -1;
163 static int mfpu_opt = -1;
164 static int mfloat_abi_opt = -1;
167 static int meabi_flags = EABI_DEFAULT;
169 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
174 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
175 symbolS * GOT_symbol;
178 /* Size of relocation record. */
179 const int md_reloc_size = 8;
181 /* 0: assemble for ARM,
182 1: assemble for Thumb,
183 2: assemble for Thumb even though target CPU does not support thumb
185 static int thumb_mode = 0;
187 /* If unified_syntax is true, we are processing the new unified
188 ARM/Thumb syntax. Important differences from the old ARM mode:
190 - Immediate operands do not require a # prefix.
191 - Conditional affixes always appear at the end of the
192 instruction. (For backward compatibility, those instructions
193 that formerly had them in the middle, continue to accept them
195 - The IT instruction may appear, and if it does is validated
196 against subsequent conditional affixes. It does not generate
199 Important differences from the old Thumb mode:
201 - Immediate operands do not require a # prefix.
202 - Most of the V6T2 instructions are only available in unified mode.
203 - The .N and .W suffixes are recognized and honored (it is an error
204 if they cannot be honored).
205 - All instructions set the flags if and only if they have an 's' affix.
206 - Conditional affixes may be used. They are validated against
207 preceding IT instructions. Unlike ARM mode, you cannot use a
208 conditional affix except in the scope of an IT instruction. */
210 static bfd_boolean unified_syntax = FALSE;
215 unsigned long instruction;
221 bfd_reloc_code_real_type type;
230 unsigned present : 1; /* operand present */
231 unsigned isreg : 1; /* operand was a register */
232 unsigned immisreg : 1; /* .imm field is a second register */
233 unsigned hasreloc : 1; /* operand has relocation suffix */
234 unsigned writeback : 1; /* operand has trailing ! */
235 unsigned preind : 1; /* preindexed address */
236 unsigned postind : 1; /* postindexed address */
237 unsigned negative : 1; /* index register was negated */
238 unsigned shifted : 1; /* shift applied to operation */
239 unsigned shift_kind : 3; /* shift operation (enum shift_kind) */
243 static struct arm_it inst;
245 #define NUM_FLOAT_VALS 8
247 const char * fp_const[] =
249 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
252 /* Number of littlenums required to hold an extended precision number. */
253 #define MAX_LITTLENUMS 6
255 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
265 #define CP_T_X 0x00008000
266 #define CP_T_Y 0x00400000
268 #define CONDS_BIT 0x00100000
269 #define LOAD_BIT 0x00100000
271 #define DOUBLE_LOAD_FLAG 0x00000001
275 const char * template;
279 #define COND_ALWAYS 0xE
283 const char *template;
287 /* The bit that distinguishes CPSR and SPSR. */
288 #define SPSR_BIT (1 << 22)
290 /* The individual PSR flag bits. */
291 #define PSR_c (1 << 16)
292 #define PSR_x (1 << 17)
293 #define PSR_s (1 << 18)
294 #define PSR_f (1 << 19)
299 bfd_reloc_code_real_type reloc;
304 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
309 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
312 /* ARM register categories. This includes coprocessor numbers and various
313 architecture extensions' registers. */
335 /* Structure for a hash table entry for a register. */
339 unsigned char number;
341 unsigned char builtin;
344 /* Diagnostics used when we don't get a register of the expected type. */
345 const char *const reg_expected_msgs[] =
347 N_("ARM register expected"),
348 N_("bad or missing co-processor number"),
349 N_("co-processor register expected"),
350 N_("FPA register expected"),
351 N_("VFP single precision register expected"),
352 N_("VFP double precision register expected"),
353 N_("VFP system register expected"),
354 N_("Maverick MVF register expected"),
355 N_("Maverick MVD register expected"),
356 N_("Maverick MVFX register expected"),
357 N_("Maverick MVDX register expected"),
358 N_("Maverick MVAX register expected"),
359 N_("Maverick DSPSC register expected"),
360 N_("iWMMXt data register expected"),
361 N_("iWMMXt control register expected"),
362 N_("iWMMXt scalar register expected"),
363 N_("XScale accumulator register expected"),
366 /* Some well known registers that we refer to directly elsewhere. */
371 /* ARM instructions take 4bytes in the object file, Thumb instructions
377 /* Basic string to match. */
378 const char *template;
380 /* Parameters to instruction. */
381 unsigned char operands[8];
383 /* Conditional tag - see opcode_lookup. */
384 unsigned int tag : 4;
386 /* Basic instruction code. */
387 unsigned int avalue : 28;
389 /* Thumb-format instruction code. */
392 /* Which architecture variant provides this instruction. */
393 unsigned long avariant;
394 unsigned long tvariant;
396 /* Function to call to encode instruction in ARM format. */
397 void (* aencode) (void);
399 /* Function to call to encode instruction in Thumb format. */
400 void (* tencode) (void);
403 /* Defines for various bits that we will want to toggle. */
404 #define INST_IMMEDIATE 0x02000000
405 #define OFFSET_REG 0x02000000
406 #define HWOFFSET_IMM 0x00400000
407 #define SHIFT_BY_REG 0x00000010
408 #define PRE_INDEX 0x01000000
409 #define INDEX_UP 0x00800000
410 #define WRITE_BACK 0x00200000
411 #define LDM_TYPE_2_OR_3 0x00400000
413 #define LITERAL_MASK 0xf000f000
414 #define OPCODE_MASK 0xfe1fffff
415 #define V4_STR_BIT 0x00000020
417 #define DATA_OP_SHIFT 21
419 /* Codes to distinguish the arithmetic instructions. */
430 #define OPCODE_CMP 10
431 #define OPCODE_CMN 11
432 #define OPCODE_ORR 12
433 #define OPCODE_MOV 13
434 #define OPCODE_BIC 14
435 #define OPCODE_MVN 15
437 #define T_OPCODE_MUL 0x4340
438 #define T_OPCODE_TST 0x4200
439 #define T_OPCODE_CMN 0x42c0
440 #define T_OPCODE_NEG 0x4240
441 #define T_OPCODE_MVN 0x43c0
443 #define T_OPCODE_ADD_R3 0x1800
444 #define T_OPCODE_SUB_R3 0x1a00
445 #define T_OPCODE_ADD_HI 0x4400
446 #define T_OPCODE_ADD_ST 0xb000
447 #define T_OPCODE_SUB_ST 0xb080
448 #define T_OPCODE_ADD_SP 0xa800
449 #define T_OPCODE_ADD_PC 0xa000
450 #define T_OPCODE_ADD_I8 0x3000
451 #define T_OPCODE_SUB_I8 0x3800
452 #define T_OPCODE_ADD_I3 0x1c00
453 #define T_OPCODE_SUB_I3 0x1e00
455 #define T_OPCODE_ASR_R 0x4100
456 #define T_OPCODE_LSL_R 0x4080
457 #define T_OPCODE_LSR_R 0x40c0
458 #define T_OPCODE_ROR_R 0x41c0
459 #define T_OPCODE_ASR_I 0x1000
460 #define T_OPCODE_LSL_I 0x0000
461 #define T_OPCODE_LSR_I 0x0800
463 #define T_OPCODE_MOV_I8 0x2000
464 #define T_OPCODE_CMP_I8 0x2800
465 #define T_OPCODE_CMP_LR 0x4280
466 #define T_OPCODE_MOV_HR 0x4600
467 #define T_OPCODE_CMP_HR 0x4500
469 #define T_OPCODE_LDR_PC 0x4800
470 #define T_OPCODE_LDR_SP 0x9800
471 #define T_OPCODE_STR_SP 0x9000
472 #define T_OPCODE_LDR_IW 0x6800
473 #define T_OPCODE_STR_IW 0x6000
474 #define T_OPCODE_LDR_IH 0x8800
475 #define T_OPCODE_STR_IH 0x8000
476 #define T_OPCODE_LDR_IB 0x7800
477 #define T_OPCODE_STR_IB 0x7000
478 #define T_OPCODE_LDR_RW 0x5800
479 #define T_OPCODE_STR_RW 0x5000
480 #define T_OPCODE_LDR_RH 0x5a00
481 #define T_OPCODE_STR_RH 0x5200
482 #define T_OPCODE_LDR_RB 0x5c00
483 #define T_OPCODE_STR_RB 0x5400
485 #define T_OPCODE_PUSH 0xb400
486 #define T_OPCODE_POP 0xbc00
488 #define T_OPCODE_BRANCH 0xe7fe
490 #define THUMB_SIZE 2 /* Size of thumb instruction. */
491 #define THUMB_PP_PC_LR 0x0100
492 #define THUMB_LOAD_BIT 0x0800
494 #define BAD_ARGS _("bad arguments to instruction")
495 #define BAD_PC _("r15 not allowed here")
496 #define BAD_COND _("instruction cannot be conditional")
497 #define BAD_OVERLAP _("registers may not be the same")
498 #define BAD_HIREG _("lo register required")
499 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
501 static struct hash_control *arm_ops_hsh;
502 static struct hash_control *arm_cond_hsh;
503 static struct hash_control *arm_shift_hsh;
504 static struct hash_control *arm_psr_hsh;
505 static struct hash_control *arm_reg_hsh;
506 static struct hash_control *arm_reloc_hsh;
508 /* Stuff needed to resolve the label ambiguity
518 symbolS * last_label_seen;
519 static int label_is_thumb_function_name = FALSE;
521 /* Literal pool structure. Held on a per-section
522 and per-sub-section basis. */
524 #define MAX_LITERAL_POOL_SIZE 1024
525 typedef struct literal_pool
527 expressionS literals [MAX_LITERAL_POOL_SIZE];
528 unsigned int next_free_entry;
533 struct literal_pool * next;
536 /* Pointer to a linked list of literal pools. */
537 literal_pool * list_of_pools = NULL;
541 /* This array holds the chars that always start a comment. If the
542 pre-processor is disabled, these aren't very useful. */
543 const char comment_chars[] = "@";
545 /* This array holds the chars that only start a comment at the beginning of
546 a line. If the line seems to have the form '# 123 filename'
547 .line and .file directives will appear in the pre-processed output. */
548 /* Note that input_file.c hand checks for '#' at the beginning of the
549 first line of the input file. This is because the compiler outputs
550 #NO_APP at the beginning of its output. */
551 /* Also note that comments like this one will always work. */
552 const char line_comment_chars[] = "#";
554 const char line_separator_chars[] = ";";
556 /* Chars that can be used to separate mant
557 from exp in floating point numbers. */
558 const char EXP_CHARS[] = "eE";
560 /* Chars that mean this number is a floating point constant. */
564 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
566 /* Prefix characters that indicate the start of an immediate
568 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
570 /* Separator character handling. */
572 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
575 skip_past_char (char ** str, char c)
585 #define skip_past_comma(str) skip_past_char (str, ',')
587 /* Arithmetic expressions (possibly involving symbols). */
589 /* Return TRUE if anything in the expression is a bignum. */
592 walk_no_bignums (symbolS * sp)
594 if (symbol_get_value_expression (sp)->X_op == O_big)
597 if (symbol_get_value_expression (sp)->X_add_symbol)
599 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
600 || (symbol_get_value_expression (sp)->X_op_symbol
601 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
607 static int in_my_get_expression = 0;
609 /* Third argument to my_get_expression. */
610 #define GE_NO_PREFIX 0
611 #define GE_IMM_PREFIX 1
612 #define GE_OPT_PREFIX 2
615 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
620 /* In unified syntax, all prefixes are optional. */
622 prefix_mode = GE_OPT_PREFIX;
626 case GE_NO_PREFIX: break;
628 if (!is_immediate_prefix (**str))
630 inst.error = _("immediate expression requires a # prefix");
636 if (is_immediate_prefix (**str))
642 memset (ep, 0, sizeof (expressionS));
644 save_in = input_line_pointer;
645 input_line_pointer = *str;
646 in_my_get_expression = 1;
647 seg = expression (ep);
648 in_my_get_expression = 0;
650 if (ep->X_op == O_illegal)
652 /* We found a bad expression in md_operand(). */
653 *str = input_line_pointer;
654 input_line_pointer = save_in;
655 if (inst.error == NULL)
656 inst.error = _("bad expression");
661 if (seg != absolute_section
662 && seg != text_section
663 && seg != data_section
664 && seg != bss_section
665 && seg != undefined_section)
667 inst.error = _("bad segment");
668 *str = input_line_pointer;
669 input_line_pointer = save_in;
674 /* Get rid of any bignums now, so that we don't generate an error for which
675 we can't establish a line number later on. Big numbers are never valid
676 in instructions, which is where this routine is always called. */
677 if (ep->X_op == O_big
679 && (walk_no_bignums (ep->X_add_symbol)
681 && walk_no_bignums (ep->X_op_symbol)))))
683 inst.error = _("invalid constant");
684 *str = input_line_pointer;
685 input_line_pointer = save_in;
689 *str = input_line_pointer;
690 input_line_pointer = save_in;
694 /* Turn a string in input_line_pointer into a floating point constant
695 of type TYPE, and store the appropriate bytes in *LITP. The number
696 of LITTLENUMS emitted is stored in *SIZEP. An error message is
697 returned, or NULL on OK.
699 Note that fp constants aren't represent in the normal way on the ARM.
700 In big endian mode, things are as expected. However, in little endian
701 mode fp constants are big-endian word-wise, and little-endian byte-wise
702 within the words. For example, (double) 1.1 in big endian mode is
703 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
704 the byte sequence 99 99 f1 3f 9a 99 99 99.
706 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
709 md_atof (int type, char * litP, int * sizeP)
712 LITTLENUM_TYPE words[MAX_LITTLENUMS];
744 return _("bad call to MD_ATOF()");
747 t = atof_ieee (input_line_pointer, type, words);
749 input_line_pointer = t;
752 if (target_big_endian)
754 for (i = 0; i < prec; i++)
756 md_number_to_chars (litP, (valueT) words[i], 2);
762 if (cpu_variant & FPU_ARCH_VFP)
763 for (i = prec - 1; i >= 0; i--)
765 md_number_to_chars (litP, (valueT) words[i], 2);
769 /* For a 4 byte float the order of elements in `words' is 1 0.
770 For an 8 byte float the order is 1 0 3 2. */
771 for (i = 0; i < prec; i += 2)
773 md_number_to_chars (litP, (valueT) words[i + 1], 2);
774 md_number_to_chars (litP + 2, (valueT) words[i], 2);
782 /* We handle all bad expressions here, so that we can report the faulty
783 instruction in the error message. */
785 md_operand (expressionS * expr)
787 if (in_my_get_expression)
788 expr->X_op = O_illegal;
791 /* Immediate values. */
793 /* Generic immediate-value read function for use in directives.
794 Accepts anything that 'expression' can fold to a constant.
795 *val receives the number. */
798 immediate_for_directive (int *val)
801 exp.X_op = O_illegal;
803 if (is_immediate_prefix (*input_line_pointer))
805 input_line_pointer++;
809 if (exp.X_op != O_constant)
811 as_bad (_("expected #constant"));
812 ignore_rest_of_line ();
815 *val = exp.X_add_number;
820 /* Register parsing. */
822 /* Generic register parser. CCP points to what should be the
823 beginning of a register name. If it is indeed a valid register
824 name, advance CCP over it and return the reg_entry structure;
825 otherwise return NULL. Does not issue diagnostics. */
827 static struct reg_entry *
828 arm_reg_parse_multi (char **ccp)
832 struct reg_entry *reg;
834 #ifdef REGISTER_PREFIX
835 if (*start != REGISTER_PREFIX)
839 #ifdef OPTIONAL_REGISTER_PREFIX
840 if (*start == OPTIONAL_REGISTER_PREFIX)
845 if (!ISALPHA (*p) || !is_name_beginner (*p))
850 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
852 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
861 /* As above, but the register must be of type TYPE, and the return
862 value is the register number or NULL. */
865 arm_reg_parse (char **ccp, enum arm_reg_type type)
868 struct reg_entry *reg = arm_reg_parse_multi (ccp);
870 if (reg && reg->type == type)
873 /* Alternative syntaxes are accepted for a few register classes. */
880 /* Generic coprocessor register names are allowed for these. */
881 if (reg->type == REG_TYPE_CN)
886 /* For backward compatibility, a bare number is valid here. */
888 unsigned long processor = strtoul (start, ccp, 10);
889 if (*ccp != start && processor <= 15)
894 /* WC includes WCG. ??? I'm not sure this is true for all
895 instructions that take WC registers. */
896 if (reg->type == REG_TYPE_MMXWCG)
908 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
910 parse_reg_list (char ** strp)
916 /* We come back here if we get ranges concatenated by '+' or '|'. */
931 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
933 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
943 inst.error = _("bad range in register list");
947 for (i = cur_reg + 1; i < reg; i++)
949 if (range & (1 << i))
951 (_("Warning: duplicated register (r%d) in register list"),
959 if (range & (1 << reg))
960 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
962 else if (reg <= cur_reg)
963 as_tsktsk (_("Warning: register range not in ascending order"));
968 while (skip_past_comma (&str) != FAIL
969 || (in_range = 1, *str++ == '-'));
974 inst.error = _("missing `}'");
982 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
985 if (expr.X_op == O_constant)
987 if (expr.X_add_number
988 != (expr.X_add_number & 0x0000ffff))
990 inst.error = _("invalid register mask");
994 if ((range & expr.X_add_number) != 0)
996 int regno = range & expr.X_add_number;
999 regno = (1 << regno) - 1;
1001 (_("Warning: duplicated register (r%d) in register list"),
1005 range |= expr.X_add_number;
1009 if (inst.reloc.type != 0)
1011 inst.error = _("expression too complex");
1015 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1016 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1017 inst.reloc.pc_rel = 0;
1021 if (*str == '|' || *str == '+')
1027 while (another_range);
1033 /* Parse a VFP register list. If the string is invalid return FAIL.
1034 Otherwise return the number of registers, and set PBASE to the first
1035 register. Double precision registers are matched if DP is nonzero. */
1038 parse_vfp_reg_list (char **str, int *pbase, int dp)
1046 unsigned long mask = 0;
1056 regtype = REG_TYPE_VFD;
1061 regtype = REG_TYPE_VFS;
1065 base_reg = max_regs;
1069 new_base = arm_reg_parse (str, regtype);
1070 if (new_base == FAIL)
1072 inst.error = gettext (reg_expected_msgs[regtype]);
1076 if (new_base < base_reg)
1077 base_reg = new_base;
1079 if (mask & (1 << new_base))
1081 inst.error = _("invalid register list");
1085 if ((mask >> new_base) != 0 && ! warned)
1087 as_tsktsk (_("register list not in ascending order"));
1091 mask |= 1 << new_base;
1094 if (**str == '-') /* We have the start of a range expression */
1100 if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
1102 inst.error = gettext (reg_expected_msgs[regtype]);
1106 if (high_range <= new_base)
1108 inst.error = _("register range not in ascending order");
1112 for (new_base++; new_base <= high_range; new_base++)
1114 if (mask & (1 << new_base))
1116 inst.error = _("invalid register list");
1120 mask |= 1 << new_base;
1125 while (skip_past_comma (str) != FAIL);
1129 /* Sanity check -- should have raised a parse error above. */
1130 if (count == 0 || count > max_regs)
1135 /* Final test -- the registers must be consecutive. */
1137 for (i = 0; i < count; i++)
1139 if ((mask & (1u << i)) == 0)
1141 inst.error = _("non-contiguous register range");
1149 /* Parse an explicit relocation suffix on an expression. This is
1150 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1151 arm_reloc_hsh contains no entries, so this function can only
1152 succeed if there is no () after the word. Returns -1 on error,
1153 BFD_RELOC_UNUSED if there wasn't any suffix. */
1155 parse_reloc (char **str)
1157 struct reloc_entry *r;
1161 return BFD_RELOC_UNUSED;
1166 while (*q && *q != ')' && *q != ',')
1171 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1178 /* Directives: register aliases. */
1181 insert_reg_alias (char *str, int number, int type)
1183 struct reg_entry *new;
1186 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1189 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1191 /* Only warn about a redefinition if it's not defined as the
1193 else if (new->number != number || new->type != type)
1194 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1199 name = xstrdup (str);
1200 new = xmalloc (sizeof (struct reg_entry));
1203 new->number = number;
1205 new->builtin = FALSE;
1207 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1211 /* Look for the .req directive. This is of the form:
1213 new_register_name .req existing_register_name
1215 If we find one, or if it looks sufficiently like one that we want to
1216 handle any error here, return non-zero. Otherwise return zero. */
1219 create_register_alias (char * newname, char *p)
1221 struct reg_entry *old;
1222 char *oldname, *nbuf;
1225 /* The input scrubber ensures that whitespace after the mnemonic is
1226 collapsed to single spaces. */
1228 if (strncmp (oldname, " .req ", 6) != 0)
1232 if (*oldname == '\0')
1235 old = hash_find (arm_reg_hsh, oldname);
1238 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1242 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1243 the desired alias name, and p points to its end. If not, then
1244 the desired alias name is in the global original_case_string. */
1245 #ifdef TC_CASE_SENSITIVE
1248 newname = original_case_string;
1249 nlen = strlen (newname);
1252 nbuf = alloca (nlen + 1);
1253 memcpy (nbuf, newname, nlen);
1256 /* Create aliases under the new name as stated; an all-lowercase
1257 version of the new name; and an all-uppercase version of the new
1259 insert_reg_alias (nbuf, old->number, old->type);
1261 for (p = nbuf; *p; p++)
1264 if (strncmp (nbuf, newname, nlen))
1265 insert_reg_alias (nbuf, old->number, old->type);
1267 for (p = nbuf; *p; p++)
1270 if (strncmp (nbuf, newname, nlen))
1271 insert_reg_alias (nbuf, old->number, old->type);
1276 /* Should never be called, as .req goes between the alias and the
1277 register name, not at the beginning of the line. */
1279 s_req (int a ATTRIBUTE_UNUSED)
1281 as_bad (_("invalid syntax for .req directive"));
1284 /* The .unreq directive deletes an alias which was previously defined
1285 by .req. For example:
1291 s_unreq (int a ATTRIBUTE_UNUSED)
1296 name = input_line_pointer;
1298 while (*input_line_pointer != 0
1299 && *input_line_pointer != ' '
1300 && *input_line_pointer != '\n')
1301 ++input_line_pointer;
1303 saved_char = *input_line_pointer;
1304 *input_line_pointer = 0;
1307 as_bad (_("invalid syntax for .unreq directive"));
1310 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
1313 as_bad (_("unknown register alias '%s'"), name);
1314 else if (reg->builtin)
1315 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1319 hash_delete (arm_reg_hsh, name);
1320 free ((char *) reg->name);
1325 *input_line_pointer = saved_char;
1326 demand_empty_rest_of_line ();
1329 /* Directives: Instruction set selection. */
1332 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1333 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1334 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1335 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1337 static enum mstate mapstate = MAP_UNDEFINED;
1340 mapping_state (enum mstate state)
1343 const char * symname;
1346 if (mapstate == state)
1347 /* The mapping symbol has already been emitted.
1348 There is nothing else to do. */
1357 type = BSF_NO_FLAGS;
1361 type = BSF_NO_FLAGS;
1365 type = BSF_NO_FLAGS;
1373 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1375 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
1376 symbol_table_insert (symbolP);
1377 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1382 THUMB_SET_FUNC (symbolP, 0);
1383 ARM_SET_THUMB (symbolP, 0);
1384 ARM_SET_INTERWORK (symbolP, support_interwork);
1388 THUMB_SET_FUNC (symbolP, 1);
1389 ARM_SET_THUMB (symbolP, 1);
1390 ARM_SET_INTERWORK (symbolP, support_interwork);
1399 #define mapping_state(x) /* nothing */
1402 /* Find the real, Thumb encoded start of a Thumb function. */
1405 find_real_start (symbolS * symbolP)
1408 const char * name = S_GET_NAME (symbolP);
1409 symbolS * new_target;
1411 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1412 #define STUB_NAME ".real_start_of"
1417 /* Names that start with '.' are local labels, not function entry points.
1418 The compiler may generate BL instructions to these labels because it
1419 needs to perform a branch to a far away location. */
1423 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
1424 sprintf (real_start, "%s%s", STUB_NAME, name);
1426 new_target = symbol_find (real_start);
1428 if (new_target == NULL)
1430 as_warn ("Failed to find real start of function: %s\n", name);
1431 new_target = symbolP;
1440 opcode_select (int width)
1447 if (! (cpu_variant & ARM_EXT_V4T))
1448 as_bad (_("selected processor does not support THUMB opcodes"));
1451 /* No need to force the alignment, since we will have been
1452 coming from ARM mode, which is word-aligned. */
1453 record_alignment (now_seg, 1);
1455 mapping_state (MAP_THUMB);
1461 if ((cpu_variant & ARM_ALL) == ARM_EXT_V4T)
1462 as_bad (_("selected processor does not support ARM opcodes"));
1467 frag_align (2, 0, 0);
1469 record_alignment (now_seg, 1);
1471 mapping_state (MAP_ARM);
1475 as_bad (_("invalid instruction size selected (%d)"), width);
1480 s_arm (int ignore ATTRIBUTE_UNUSED)
1483 demand_empty_rest_of_line ();
1487 s_thumb (int ignore ATTRIBUTE_UNUSED)
1490 demand_empty_rest_of_line ();
1494 s_code (int unused ATTRIBUTE_UNUSED)
1498 temp = get_absolute_expression ();
1503 opcode_select (temp);
1507 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1512 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
1514 /* If we are not already in thumb mode go into it, EVEN if
1515 the target processor does not support thumb instructions.
1516 This is used by gcc/config/arm/lib1funcs.asm for example
1517 to compile interworking support functions even if the
1518 target processor should not support interworking. */
1522 record_alignment (now_seg, 1);
1525 demand_empty_rest_of_line ();
1529 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
1533 /* The following label is the name/address of the start of a Thumb function.
1534 We need to know this for the interworking support. */
1535 label_is_thumb_function_name = TRUE;
1538 /* Perform a .set directive, but also mark the alias as
1539 being a thumb function. */
1542 s_thumb_set (int equiv)
1544 /* XXX the following is a duplicate of the code for s_set() in read.c
1545 We cannot just call that code as we need to get at the symbol that
1552 /* Especial apologies for the random logic:
1553 This just grew, and could be parsed much more simply!
1555 name = input_line_pointer;
1556 delim = get_symbol_end ();
1557 end_name = input_line_pointer;
1560 if (*input_line_pointer != ',')
1563 as_bad (_("expected comma after name \"%s\""), name);
1565 ignore_rest_of_line ();
1569 input_line_pointer++;
1572 if (name[0] == '.' && name[1] == '\0')
1574 /* XXX - this should not happen to .thumb_set. */
1578 if ((symbolP = symbol_find (name)) == NULL
1579 && (symbolP = md_undefined_symbol (name)) == NULL)
1582 /* When doing symbol listings, play games with dummy fragments living
1583 outside the normal fragment chain to record the file and line info
1585 if (listing & LISTING_SYMBOLS)
1587 extern struct list_info_struct * listing_tail;
1588 fragS * dummy_frag = xmalloc (sizeof (fragS));
1590 memset (dummy_frag, 0, sizeof (fragS));
1591 dummy_frag->fr_type = rs_fill;
1592 dummy_frag->line = listing_tail;
1593 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1594 dummy_frag->fr_symbol = symbolP;
1598 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1601 /* "set" symbols are local unless otherwise specified. */
1602 SF_SET_LOCAL (symbolP);
1603 #endif /* OBJ_COFF */
1604 } /* Make a new symbol. */
1606 symbol_table_insert (symbolP);
1611 && S_IS_DEFINED (symbolP)
1612 && S_GET_SEGMENT (symbolP) != reg_section)
1613 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1615 pseudo_set (symbolP);
1617 demand_empty_rest_of_line ();
1619 /* XXX Now we come to the Thumb specific bit of code. */
1621 THUMB_SET_FUNC (symbolP, 1);
1622 ARM_SET_THUMB (symbolP, 1);
1623 #if defined OBJ_ELF || defined OBJ_COFF
1624 ARM_SET_INTERWORK (symbolP, support_interwork);
1628 /* Directives: Mode selection. */
1630 /* .syntax [unified|divided] - choose the new unified syntax
1631 (same for Arm and Thumb encoding, modulo slight differences in what
1632 can be represented) or the old divergent syntax for each mode. */
1634 s_syntax (int unused ATTRIBUTE_UNUSED)
1638 name = input_line_pointer;
1639 delim = get_symbol_end ();
1641 if (!strcasecmp (name, "unified"))
1642 unified_syntax = TRUE;
1643 else if (!strcasecmp (name, "divided"))
1644 unified_syntax = FALSE;
1647 as_bad (_("unrecognized syntax mode \"%s\""), name);
1650 *input_line_pointer = delim;
1651 demand_empty_rest_of_line ();
1654 /* Directives: sectioning and alignment. */
1656 /* Same as s_align_ptwo but align 0 => align 2. */
1659 s_align (int unused ATTRIBUTE_UNUSED)
1663 long max_alignment = 15;
1665 temp = get_absolute_expression ();
1666 if (temp > max_alignment)
1667 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
1670 as_bad (_("alignment negative. 0 assumed."));
1674 if (*input_line_pointer == ',')
1676 input_line_pointer++;
1677 temp_fill = get_absolute_expression ();
1685 /* Only make a frag if we HAVE to. */
1686 if (temp && !need_pass_2)
1687 frag_align (temp, (int) temp_fill, 0);
1688 demand_empty_rest_of_line ();
1690 record_alignment (now_seg, temp);
1694 s_bss (int ignore ATTRIBUTE_UNUSED)
1696 /* We don't support putting frags in the BSS segment, we fake it by
1697 marking in_bss, then looking at s_skip for clues. */
1698 subseg_set (bss_section, 0);
1699 demand_empty_rest_of_line ();
1700 mapping_state (MAP_DATA);
1704 s_even (int ignore ATTRIBUTE_UNUSED)
1706 /* Never make frag if expect extra pass. */
1708 frag_align (1, 0, 0);
1710 record_alignment (now_seg, 1);
1712 demand_empty_rest_of_line ();
1715 /* Directives: Literal pools. */
1717 static literal_pool *
1718 find_literal_pool (void)
1720 literal_pool * pool;
1722 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1724 if (pool->section == now_seg
1725 && pool->sub_section == now_subseg)
1732 static literal_pool *
1733 find_or_make_literal_pool (void)
1735 /* Next literal pool ID number. */
1736 static unsigned int latest_pool_num = 1;
1737 literal_pool * pool;
1739 pool = find_literal_pool ();
1743 /* Create a new pool. */
1744 pool = xmalloc (sizeof (* pool));
1748 pool->next_free_entry = 0;
1749 pool->section = now_seg;
1750 pool->sub_section = now_subseg;
1751 pool->next = list_of_pools;
1752 pool->symbol = NULL;
1754 /* Add it to the list. */
1755 list_of_pools = pool;
1758 /* New pools, and emptied pools, will have a NULL symbol. */
1759 if (pool->symbol == NULL)
1761 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1762 (valueT) 0, &zero_address_frag);
1763 pool->id = latest_pool_num ++;
1770 /* Add the literal in the global 'inst'
1771 structure to the relevent literal pool. */
1774 add_to_lit_pool (void)
1776 literal_pool * pool;
1779 pool = find_or_make_literal_pool ();
1781 /* Check if this literal value is already in the pool. */
1782 for (entry = 0; entry < pool->next_free_entry; entry ++)
1784 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1785 && (inst.reloc.exp.X_op == O_constant)
1786 && (pool->literals[entry].X_add_number
1787 == inst.reloc.exp.X_add_number)
1788 && (pool->literals[entry].X_unsigned
1789 == inst.reloc.exp.X_unsigned))
1792 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1793 && (inst.reloc.exp.X_op == O_symbol)
1794 && (pool->literals[entry].X_add_number
1795 == inst.reloc.exp.X_add_number)
1796 && (pool->literals[entry].X_add_symbol
1797 == inst.reloc.exp.X_add_symbol)
1798 && (pool->literals[entry].X_op_symbol
1799 == inst.reloc.exp.X_op_symbol))
1803 /* Do we need to create a new entry? */
1804 if (entry == pool->next_free_entry)
1806 if (entry >= MAX_LITERAL_POOL_SIZE)
1808 inst.error = _("literal pool overflow");
1812 pool->literals[entry] = inst.reloc.exp;
1813 pool->next_free_entry += 1;
1816 inst.reloc.exp.X_op = O_symbol;
1817 inst.reloc.exp.X_add_number = ((int) entry) * 4;
1818 inst.reloc.exp.X_add_symbol = pool->symbol;
1823 /* Can't use symbol_new here, so have to create a symbol and then at
1824 a later date assign it a value. Thats what these functions do. */
1827 symbol_locate (symbolS * symbolP,
1828 const char * name, /* It is copied, the caller can modify. */
1829 segT segment, /* Segment identifier (SEG_<something>). */
1830 valueT valu, /* Symbol value. */
1831 fragS * frag) /* Associated fragment. */
1833 unsigned int name_length;
1834 char * preserved_copy_of_name;
1836 name_length = strlen (name) + 1; /* +1 for \0. */
1837 obstack_grow (¬es, name, name_length);
1838 preserved_copy_of_name = obstack_finish (¬es);
1840 #ifdef tc_canonicalize_symbol_name
1841 preserved_copy_of_name =
1842 tc_canonicalize_symbol_name (preserved_copy_of_name);
1845 S_SET_NAME (symbolP, preserved_copy_of_name);
1847 S_SET_SEGMENT (symbolP, segment);
1848 S_SET_VALUE (symbolP, valu);
1849 symbol_clear_list_pointers (symbolP);
1851 symbol_set_frag (symbolP, frag);
1853 /* Link to end of symbol chain. */
1855 extern int symbol_table_frozen;
1857 if (symbol_table_frozen)
1861 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1863 obj_symbol_new_hook (symbolP);
1865 #ifdef tc_symbol_new_hook
1866 tc_symbol_new_hook (symbolP);
1870 verify_symbol_chain (symbol_rootP, symbol_lastP);
1871 #endif /* DEBUG_SYMS */
1876 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1879 literal_pool * pool;
1882 pool = find_literal_pool ();
1884 || pool->symbol == NULL
1885 || pool->next_free_entry == 0)
1888 mapping_state (MAP_DATA);
1890 /* Align pool as you have word accesses.
1891 Only make a frag if we have to. */
1893 frag_align (2, 0, 0);
1895 record_alignment (now_seg, 2);
1897 sprintf (sym_name, "$$lit_\002%x", pool->id);
1899 symbol_locate (pool->symbol, sym_name, now_seg,
1900 (valueT) frag_now_fix (), frag_now);
1901 symbol_table_insert (pool->symbol);
1903 ARM_SET_THUMB (pool->symbol, thumb_mode);
1905 #if defined OBJ_COFF || defined OBJ_ELF
1906 ARM_SET_INTERWORK (pool->symbol, support_interwork);
1909 for (entry = 0; entry < pool->next_free_entry; entry ++)
1910 /* First output the expression in the instruction to the pool. */
1911 emit_expr (&(pool->literals[entry]), 4); /* .word */
1913 /* Mark the pool as empty. */
1914 pool->next_free_entry = 0;
1915 pool->symbol = NULL;
1919 /* Forward declarations for functions below, in the MD interface
1921 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
1922 static valueT create_unwind_entry (int);
1923 static void start_unwind_section (const segT, int);
1924 static void add_unwind_opcode (valueT, int);
1925 static void flush_pending_unwind (void);
1927 /* Directives: Data. */
1930 s_arm_elf_cons (int nbytes)
1934 #ifdef md_flush_pending_output
1935 md_flush_pending_output ();
1938 if (is_it_end_of_statement ())
1940 demand_empty_rest_of_line ();
1944 #ifdef md_cons_align
1945 md_cons_align (nbytes);
1948 mapping_state (MAP_DATA);
1952 char *base = input_line_pointer;
1956 if (exp.X_op != O_symbol)
1957 emit_expr (&exp, (unsigned int) nbytes);
1960 char *before_reloc = input_line_pointer;
1961 reloc = parse_reloc (&input_line_pointer);
1964 as_bad (_("unrecognized relocation suffix"));
1965 ignore_rest_of_line ();
1968 else if (reloc == BFD_RELOC_UNUSED)
1969 emit_expr (&exp, (unsigned int) nbytes);
1972 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
1973 int size = bfd_get_reloc_size (howto);
1976 as_bad ("%s relocations do not fit in %d bytes",
1977 howto->name, nbytes);
1980 /* We've parsed an expression stopping at O_symbol.
1981 But there may be more expression left now that we
1982 have parsed the relocation marker. Parse it again.
1983 XXX Surely there is a cleaner way to do this. */
1984 char *p = input_line_pointer;
1986 char *save_buf = alloca (input_line_pointer - base);
1987 memcpy (save_buf, base, input_line_pointer - base);
1988 memmove (base + (input_line_pointer - before_reloc),
1989 base, before_reloc - base);
1991 input_line_pointer = base + (input_line_pointer-before_reloc);
1993 memcpy (base, save_buf, p - base);
1995 offset = nbytes - size;
1996 p = frag_more ((int) nbytes);
1997 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
1998 size, &exp, 0, reloc);
2003 while (*input_line_pointer++ == ',');
2005 /* Put terminator back into stream. */
2006 input_line_pointer --;
2007 demand_empty_rest_of_line ();
2011 /* Parse a .rel31 directive. */
2014 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2021 if (*input_line_pointer == '1')
2022 highbit = 0x80000000;
2023 else if (*input_line_pointer != '0')
2024 as_bad (_("expected 0 or 1"));
2026 input_line_pointer++;
2027 if (*input_line_pointer != ',')
2028 as_bad (_("missing comma"));
2029 input_line_pointer++;
2031 #ifdef md_flush_pending_output
2032 md_flush_pending_output ();
2035 #ifdef md_cons_align
2039 mapping_state (MAP_DATA);
2044 md_number_to_chars (p, highbit, 4);
2045 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
2046 BFD_RELOC_ARM_PREL31);
2048 demand_empty_rest_of_line ();
2051 /* Directives: AEABI stack-unwind tables. */
2053 /* Parse an unwind_fnstart directive. Simply records the current location. */
2056 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
2058 demand_empty_rest_of_line ();
2059 /* Mark the start of the function. */
2060 unwind.proc_start = expr_build_dot ();
2062 /* Reset the rest of the unwind info. */
2063 unwind.opcode_count = 0;
2064 unwind.table_entry = NULL;
2065 unwind.personality_routine = NULL;
2066 unwind.personality_index = -1;
2067 unwind.frame_size = 0;
2068 unwind.fp_offset = 0;
2071 unwind.sp_restored = 0;
2075 /* Parse a handlerdata directive. Creates the exception handling table entry
2076 for the function. */
2079 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
2081 demand_empty_rest_of_line ();
2082 if (unwind.table_entry)
2083 as_bad (_("dupicate .handlerdata directive"));
2085 create_unwind_entry (1);
2088 /* Parse an unwind_fnend directive. Generates the index table entry. */
2091 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
2097 demand_empty_rest_of_line ();
2099 /* Add eh table entry. */
2100 if (unwind.table_entry == NULL)
2101 val = create_unwind_entry (0);
2105 /* Add index table entry. This is two words. */
2106 start_unwind_section (unwind.saved_seg, 1);
2107 frag_align (2, 0, 0);
2108 record_alignment (now_seg, 2);
2110 ptr = frag_more (8);
2111 where = frag_now_fix () - 8;
2113 /* Self relative offset of the function start. */
2114 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
2115 BFD_RELOC_ARM_PREL31);
2117 /* Indicate dependency on EHABI-defined personality routines to the
2118 linker, if it hasn't been done already. */
2119 if (unwind.personality_index >= 0 && unwind.personality_index < 3
2120 && !(marked_pr_dependency & (1 << unwind.personality_index)))
2122 static const char *const name[] = {
2123 "__aeabi_unwind_cpp_pr0",
2124 "__aeabi_unwind_cpp_pr1",
2125 "__aeabi_unwind_cpp_pr2"
2127 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
2128 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
2129 marked_pr_dependency |= 1 << unwind.personality_index;
2130 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
2131 = marked_pr_dependency;
2135 /* Inline exception table entry. */
2136 md_number_to_chars (ptr + 4, val, 4);
2138 /* Self relative offset of the table entry. */
2139 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
2140 BFD_RELOC_ARM_PREL31);
2142 /* Restore the original section. */
2143 subseg_set (unwind.saved_seg, unwind.saved_subseg);
2147 /* Parse an unwind_cantunwind directive. */
2150 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
2152 demand_empty_rest_of_line ();
2153 if (unwind.personality_routine || unwind.personality_index != -1)
2154 as_bad (_("personality routine specified for cantunwind frame"));
2156 unwind.personality_index = -2;
2160 /* Parse a personalityindex directive. */
2163 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
2167 if (unwind.personality_routine || unwind.personality_index != -1)
2168 as_bad (_("duplicate .personalityindex directive"));
2172 if (exp.X_op != O_constant
2173 || exp.X_add_number < 0 || exp.X_add_number > 15)
2175 as_bad (_("bad personality routine number"));
2176 ignore_rest_of_line ();
2180 unwind.personality_index = exp.X_add_number;
2182 demand_empty_rest_of_line ();
2186 /* Parse a personality directive. */
2189 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
2193 if (unwind.personality_routine || unwind.personality_index != -1)
2194 as_bad (_("duplicate .personality directive"));
2196 name = input_line_pointer;
2197 c = get_symbol_end ();
2198 p = input_line_pointer;
2199 unwind.personality_routine = symbol_find_or_make (name);
2201 demand_empty_rest_of_line ();
2205 /* Parse a directive saving core registers. */
2208 s_arm_unwind_save_core (void)
2214 range = parse_reg_list (&input_line_pointer);
2217 as_bad (_("expected register list"));
2218 ignore_rest_of_line ();
2222 demand_empty_rest_of_line ();
2224 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2225 into .unwind_save {..., sp...}. We aren't bothered about the value of
2226 ip because it is clobbered by calls. */
2227 if (unwind.sp_restored && unwind.fp_reg == 12
2228 && (range & 0x3000) == 0x1000)
2230 unwind.opcode_count--;
2231 unwind.sp_restored = 0;
2232 range = (range | 0x2000) & ~0x1000;
2233 unwind.pending_offset = 0;
2236 /* See if we can use the short opcodes. These pop a block of upto 8
2237 registers starting with r4, plus maybe r14. */
2238 for (n = 0; n < 8; n++)
2240 /* Break at the first non-saved register. */
2241 if ((range & (1 << (n + 4))) == 0)
2244 /* See if there are any other bits set. */
2245 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
2247 /* Use the long form. */
2248 op = 0x8000 | ((range >> 4) & 0xfff);
2249 add_unwind_opcode (op, 2);
2253 /* Use the short form. */
2255 op = 0xa8; /* Pop r14. */
2257 op = 0xa0; /* Do not pop r14. */
2259 add_unwind_opcode (op, 1);
2265 op = 0xb100 | (range & 0xf);
2266 add_unwind_opcode (op, 2);
2269 /* Record the number of bytes pushed. */
2270 for (n = 0; n < 16; n++)
2272 if (range & (1 << n))
2273 unwind.frame_size += 4;
2278 /* Parse a directive saving FPA registers. */
2281 s_arm_unwind_save_fpa (int reg)
2287 /* Get Number of registers to transfer. */
2288 if (skip_past_comma (&input_line_pointer) != FAIL)
2291 exp.X_op = O_illegal;
2293 if (exp.X_op != O_constant)
2295 as_bad (_("expected , <constant>"));
2296 ignore_rest_of_line ();
2300 num_regs = exp.X_add_number;
2302 if (num_regs < 1 || num_regs > 4)
2304 as_bad (_("number of registers must be in the range [1:4]"));
2305 ignore_rest_of_line ();
2309 demand_empty_rest_of_line ();
2314 op = 0xb4 | (num_regs - 1);
2315 add_unwind_opcode (op, 1);
2320 op = 0xc800 | (reg << 4) | (num_regs - 1);
2321 add_unwind_opcode (op, 2);
2323 unwind.frame_size += num_regs * 12;
2327 /* Parse a directive saving VFP registers. */
2330 s_arm_unwind_save_vfp (void)
2336 count = parse_vfp_reg_list (&input_line_pointer, ®, 1);
2339 as_bad (_("expected register list"));
2340 ignore_rest_of_line ();
2344 demand_empty_rest_of_line ();
2349 op = 0xb8 | (count - 1);
2350 add_unwind_opcode (op, 1);
2355 op = 0xb300 | (reg << 4) | (count - 1);
2356 add_unwind_opcode (op, 2);
2358 unwind.frame_size += count * 8 + 4;
2362 /* Parse a directive saving iWMMXt data registers. */
2365 s_arm_unwind_save_mmxwr (void)
2373 if (*input_line_pointer == '{')
2374 input_line_pointer++;
2378 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2382 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2387 as_tsktsk (_("register list not in ascending order"));
2390 if (*input_line_pointer == '-')
2392 input_line_pointer++;
2393 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2396 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2399 else if (reg >= hi_reg)
2401 as_bad (_("bad register range"));
2404 for (; reg < hi_reg; reg++)
2408 while (skip_past_comma (&input_line_pointer) != FAIL);
2410 if (*input_line_pointer == '}')
2411 input_line_pointer++;
2413 demand_empty_rest_of_line ();
2415 /* Generate any deferred opcodes becuuse we're going to be looking at
2417 flush_pending_unwind ();
2419 for (i = 0; i < 16; i++)
2421 if (mask & (1 << i))
2422 unwind.frame_size += 8;
2425 /* Attempt to combine with a previous opcode. We do this because gcc
2426 likes to output separate unwind directives for a single block of
2428 if (unwind.opcode_count > 0)
2430 i = unwind.opcodes[unwind.opcode_count - 1];
2431 if ((i & 0xf8) == 0xc0)
2434 /* Only merge if the blocks are contiguous. */
2437 if ((mask & 0xfe00) == (1 << 9))
2439 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
2440 unwind.opcode_count--;
2443 else if (i == 6 && unwind.opcode_count >= 2)
2445 i = unwind.opcodes[unwind.opcode_count - 2];
2449 op = 0xffff << (reg - 1);
2451 || ((mask & op) == (1u << (reg - 1))))
2453 op = (1 << (reg + i + 1)) - 1;
2454 op &= ~((1 << reg) - 1);
2456 unwind.opcode_count -= 2;
2463 /* We want to generate opcodes in the order the registers have been
2464 saved, ie. descending order. */
2465 for (reg = 15; reg >= -1; reg--)
2467 /* Save registers in blocks. */
2469 || !(mask & (1 << reg)))
2471 /* We found an unsaved reg. Generate opcodes to save the
2472 preceeding block. */
2478 op = 0xc0 | (hi_reg - 10);
2479 add_unwind_opcode (op, 1);
2484 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
2485 add_unwind_opcode (op, 2);
2494 ignore_rest_of_line ();
2498 s_arm_unwind_save_mmxwcg (void)
2505 if (*input_line_pointer == '{')
2506 input_line_pointer++;
2510 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2514 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2520 as_tsktsk (_("register list not in ascending order"));
2523 if (*input_line_pointer == '-')
2525 input_line_pointer++;
2526 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2529 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2532 else if (reg >= hi_reg)
2534 as_bad (_("bad register range"));
2537 for (; reg < hi_reg; reg++)
2541 while (skip_past_comma (&input_line_pointer) != FAIL);
2543 if (*input_line_pointer == '}')
2544 input_line_pointer++;
2546 demand_empty_rest_of_line ();
2548 /* Generate any deferred opcodes becuuse we're going to be looking at
2550 flush_pending_unwind ();
2552 for (reg = 0; reg < 16; reg++)
2554 if (mask & (1 << reg))
2555 unwind.frame_size += 4;
2558 add_unwind_opcode (op, 2);
2561 ignore_rest_of_line ();
2565 /* Parse an unwind_save directive. */
2568 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
2571 struct reg_entry *reg;
2572 bfd_boolean had_brace = FALSE;
2574 /* Figure out what sort of save we have. */
2575 peek = input_line_pointer;
2583 reg = arm_reg_parse_multi (&peek);
2587 as_bad (_("register expected"));
2588 ignore_rest_of_line ();
2597 as_bad (_("FPA .unwind_save does not take a register list"));
2598 ignore_rest_of_line ();
2601 s_arm_unwind_save_fpa (reg->number);
2604 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
2605 case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
2606 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
2607 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
2610 as_bad (_(".unwind_save does not support this kind of register"));
2611 ignore_rest_of_line ();
2616 /* Parse an unwind_movsp directive. */
2619 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
2624 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2627 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
2628 ignore_rest_of_line ();
2631 demand_empty_rest_of_line ();
2633 if (reg == REG_SP || reg == REG_PC)
2635 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2639 if (unwind.fp_reg != REG_SP)
2640 as_bad (_("unexpected .unwind_movsp directive"));
2642 /* Generate opcode to restore the value. */
2644 add_unwind_opcode (op, 1);
2646 /* Record the information for later. */
2647 unwind.fp_reg = reg;
2648 unwind.fp_offset = unwind.frame_size;
2649 unwind.sp_restored = 1;
2652 /* Parse an unwind_pad directive. */
2655 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
2659 if (immediate_for_directive (&offset) == FAIL)
2664 as_bad (_("stack increment must be multiple of 4"));
2665 ignore_rest_of_line ();
2669 /* Don't generate any opcodes, just record the details for later. */
2670 unwind.frame_size += offset;
2671 unwind.pending_offset += offset;
2673 demand_empty_rest_of_line ();
2676 /* Parse an unwind_setfp directive. */
2679 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
2685 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2686 if (skip_past_comma (&input_line_pointer) == FAIL)
2689 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2691 if (fp_reg == FAIL || sp_reg == FAIL)
2693 as_bad (_("expected <reg>, <reg>"));
2694 ignore_rest_of_line ();
2698 /* Optional constant. */
2699 if (skip_past_comma (&input_line_pointer) != FAIL)
2701 if (immediate_for_directive (&offset) == FAIL)
2707 demand_empty_rest_of_line ();
2709 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
2711 as_bad (_("register must be either sp or set by a previous"
2712 "unwind_movsp directive"));
2716 /* Don't generate any opcodes, just record the information for later. */
2717 unwind.fp_reg = fp_reg;
2720 unwind.fp_offset = unwind.frame_size - offset;
2722 unwind.fp_offset -= offset;
2725 /* Parse an unwind_raw directive. */
2728 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
2731 /* This is an arbitary limit. */
2732 unsigned char op[16];
2736 if (exp.X_op == O_constant
2737 && skip_past_comma (&input_line_pointer) != FAIL)
2739 unwind.frame_size += exp.X_add_number;
2743 exp.X_op = O_illegal;
2745 if (exp.X_op != O_constant)
2747 as_bad (_("expected <offset>, <opcode>"));
2748 ignore_rest_of_line ();
2754 /* Parse the opcode. */
2759 as_bad (_("unwind opcode too long"));
2760 ignore_rest_of_line ();
2762 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
2764 as_bad (_("invalid unwind opcode"));
2765 ignore_rest_of_line ();
2768 op[count++] = exp.X_add_number;
2770 /* Parse the next byte. */
2771 if (skip_past_comma (&input_line_pointer) == FAIL)
2777 /* Add the opcode bytes in reverse order. */
2779 add_unwind_opcode (op[count], 1);
2781 demand_empty_rest_of_line ();
2783 #endif /* OBJ_ELF */
2785 /* This table describes all the machine specific pseudo-ops the assembler
2786 has to support. The fields are:
2787 pseudo-op name without dot
2788 function to call to execute this pseudo-op
2789 Integer arg to pass to the function. */
2791 const pseudo_typeS md_pseudo_table[] =
2793 /* Never called because '.req' does not start a line. */
2794 { "req", s_req, 0 },
2795 { "unreq", s_unreq, 0 },
2796 { "bss", s_bss, 0 },
2797 { "align", s_align, 0 },
2798 { "arm", s_arm, 0 },
2799 { "thumb", s_thumb, 0 },
2800 { "code", s_code, 0 },
2801 { "force_thumb", s_force_thumb, 0 },
2802 { "thumb_func", s_thumb_func, 0 },
2803 { "thumb_set", s_thumb_set, 0 },
2804 { "even", s_even, 0 },
2805 { "ltorg", s_ltorg, 0 },
2806 { "pool", s_ltorg, 0 },
2807 { "syntax", s_syntax, 0 },
2809 { "word", s_arm_elf_cons, 4 },
2810 { "long", s_arm_elf_cons, 4 },
2811 { "rel31", s_arm_rel31, 0 },
2812 { "fnstart", s_arm_unwind_fnstart, 0 },
2813 { "fnend", s_arm_unwind_fnend, 0 },
2814 { "cantunwind", s_arm_unwind_cantunwind, 0 },
2815 { "personality", s_arm_unwind_personality, 0 },
2816 { "personalityindex", s_arm_unwind_personalityindex, 0 },
2817 { "handlerdata", s_arm_unwind_handlerdata, 0 },
2818 { "save", s_arm_unwind_save, 0 },
2819 { "movsp", s_arm_unwind_movsp, 0 },
2820 { "pad", s_arm_unwind_pad, 0 },
2821 { "setfp", s_arm_unwind_setfp, 0 },
2822 { "unwind_raw", s_arm_unwind_raw, 0 },
2826 { "extend", float_cons, 'x' },
2827 { "ldouble", float_cons, 'x' },
2828 { "packed", float_cons, 'p' },
2832 /* Parser functions used exclusively in instruction operands. */
2834 /* Generic immediate-value read function for use in insn parsing.
2835 STR points to the beginning of the immediate (the leading #);
2836 VAL receives the value; if the value is outside [MIN, MAX]
2837 issue an error. PREFIX_OPT is true if the immediate prefix is
2841 parse_immediate (char **str, int *val, int min, int max,
2842 bfd_boolean prefix_opt)
2845 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
2846 if (exp.X_op != O_constant)
2848 inst.error = _("constant expression required");
2852 if (exp.X_add_number < min || exp.X_add_number > max)
2854 inst.error = _("immediate value out of range");
2858 *val = exp.X_add_number;
2862 /* Returns the pseudo-register number of an FPA immediate constant,
2863 or FAIL if there isn't a valid constant here. */
2866 parse_fpa_immediate (char ** str)
2868 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2874 /* First try and match exact strings, this is to guarantee
2875 that some formats will work even for cross assembly. */
2877 for (i = 0; fp_const[i]; i++)
2879 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2883 *str += strlen (fp_const[i]);
2884 if (is_end_of_line[(unsigned char) **str])
2890 /* Just because we didn't get a match doesn't mean that the constant
2891 isn't valid, just that it is in a format that we don't
2892 automatically recognize. Try parsing it with the standard
2893 expression routines. */
2895 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2897 /* Look for a raw floating point number. */
2898 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2899 && is_end_of_line[(unsigned char) *save_in])
2901 for (i = 0; i < NUM_FLOAT_VALS; i++)
2903 for (j = 0; j < MAX_LITTLENUMS; j++)
2905 if (words[j] != fp_values[i][j])
2909 if (j == MAX_LITTLENUMS)
2917 /* Try and parse a more complex expression, this will probably fail
2918 unless the code uses a floating point prefix (eg "0f"). */
2919 save_in = input_line_pointer;
2920 input_line_pointer = *str;
2921 if (expression (&exp) == absolute_section
2922 && exp.X_op == O_big
2923 && exp.X_add_number < 0)
2925 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2927 if (gen_to_words (words, 5, (long) 15) == 0)
2929 for (i = 0; i < NUM_FLOAT_VALS; i++)
2931 for (j = 0; j < MAX_LITTLENUMS; j++)
2933 if (words[j] != fp_values[i][j])
2937 if (j == MAX_LITTLENUMS)
2939 *str = input_line_pointer;
2940 input_line_pointer = save_in;
2947 *str = input_line_pointer;
2948 input_line_pointer = save_in;
2949 inst.error = _("invalid FPA immediate expression");
2953 /* Shift operands. */
2956 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
2959 struct asm_shift_name
2962 enum shift_kind kind;
2965 /* Third argument to parse_shift. */
2966 enum parse_shift_mode
2968 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
2969 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
2970 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
2971 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
2972 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
2975 /* Parse a <shift> specifier on an ARM data processing instruction.
2976 This has three forms:
2978 (LSL|LSR|ASL|ASR|ROR) Rs
2979 (LSL|LSR|ASL|ASR|ROR) #imm
2982 Note that ASL is assimilated to LSL in the instruction encoding, and
2983 RRX to ROR #0 (which cannot be written as such). */
2986 parse_shift (char **str, int i, enum parse_shift_mode mode)
2988 const struct asm_shift_name *shift_name;
2989 enum shift_kind shift;
2994 for (p = *str; ISALPHA (*p); p++)
2999 inst.error = _("shift expression expected");
3003 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
3005 if (shift_name == NULL)
3007 inst.error = _("shift expression expected");
3011 shift = shift_name->kind;
3015 case NO_SHIFT_RESTRICT:
3016 case SHIFT_IMMEDIATE: break;
3018 case SHIFT_LSL_OR_ASR_IMMEDIATE:
3019 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
3021 inst.error = _("'LSL' or 'ASR' required");
3026 case SHIFT_LSL_IMMEDIATE:
3027 if (shift != SHIFT_LSL)
3029 inst.error = _("'LSL' required");
3034 case SHIFT_ASR_IMMEDIATE:
3035 if (shift != SHIFT_ASR)
3037 inst.error = _("'ASR' required");
3045 if (shift != SHIFT_RRX)
3047 /* Whitespace can appear here if the next thing is a bare digit. */
3048 skip_whitespace (p);
3050 if (mode == NO_SHIFT_RESTRICT
3051 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3053 inst.operands[i].imm = reg;
3054 inst.operands[i].immisreg = 1;
3056 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3059 inst.operands[i].shift_kind = shift;
3060 inst.operands[i].shifted = 1;
3065 /* Parse a <shifter_operand> for an ARM data processing instruction:
3068 #<immediate>, <rotate>
3072 where <shift> is defined by parse_shift above, and <rotate> is a
3073 multiple of 2 between 0 and 30. Validation of immediate operands
3074 is deferred to md_apply_fix3. */
3077 parse_shifter_operand (char **str, int i)
3082 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
3084 inst.operands[i].reg = value;
3085 inst.operands[i].isreg = 1;
3087 /* parse_shift will override this if appropriate */
3088 inst.reloc.exp.X_op = O_constant;
3089 inst.reloc.exp.X_add_number = 0;
3091 if (skip_past_comma (str) == FAIL)
3094 /* Shift operation on register. */
3095 return parse_shift (str, i, NO_SHIFT_RESTRICT);
3098 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
3101 if (skip_past_comma (str) == SUCCESS)
3103 /* #x, y -- ie explicit rotation by Y. */
3104 if (my_get_expression (&expr, str, GE_NO_PREFIX))
3107 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
3109 inst.error = _("constant expression expected");
3113 value = expr.X_add_number;
3114 if (value < 0 || value > 30 || value % 2 != 0)
3116 inst.error = _("invalid rotation");
3119 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
3121 inst.error = _("invalid constant");
3125 /* Convert to decoded value. md_apply_fix3 will put it back. */
3126 inst.reloc.exp.X_add_number
3127 = (((inst.reloc.exp.X_add_number << (32 - value))
3128 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
3131 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3132 inst.reloc.pc_rel = 0;
3136 /* Parse all forms of an ARM address expression. Information is written
3137 to inst.operands[i] and/or inst.reloc.
3139 Preindexed addressing (.preind=1):
3141 [Rn, #offset] .reg=Rn .reloc.exp=offset
3142 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3143 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3144 .shift_kind=shift .reloc.exp=shift_imm
3146 These three may have a trailing ! which causes .writeback to be set also.
3148 Postindexed addressing (.postind=1, .writeback=1):
3150 [Rn], #offset .reg=Rn .reloc.exp=offset
3151 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3152 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3153 .shift_kind=shift .reloc.exp=shift_imm
3155 Unindexed addressing (.preind=0, .postind=0):
3157 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3161 [Rn]{!} shorthand for [Rn,#0]{!}
3162 =immediate .isreg=0 .reloc.exp=immediate
3163 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3165 It is the caller's responsibility to check for addressing modes not
3166 supported by the instruction, and to set inst.reloc.type. */
3169 parse_address (char **str, int i)
3174 if (skip_past_char (&p, '[') == FAIL)
3176 if (skip_past_char (&p, '=') == FAIL)
3178 /* bare address - translate to PC-relative offset */
3179 inst.reloc.pc_rel = 1;
3180 inst.operands[i].reg = REG_PC;
3181 inst.operands[i].isreg = 1;
3182 inst.operands[i].preind = 1;
3184 /* else a load-constant pseudo op, no special treatment needed here */
3186 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
3193 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3195 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3198 inst.operands[i].reg = reg;
3199 inst.operands[i].isreg = 1;
3201 if (skip_past_comma (&p) == SUCCESS)
3203 inst.operands[i].preind = 1;
3206 else if (*p == '-') p++, inst.operands[i].negative = 1;
3208 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3210 inst.operands[i].imm = reg;
3211 inst.operands[i].immisreg = 1;
3213 if (skip_past_comma (&p) == SUCCESS)
3214 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3219 if (inst.operands[i].negative)
3221 inst.operands[i].negative = 0;
3224 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3229 if (skip_past_char (&p, ']') == FAIL)
3231 inst.error = _("']' expected");
3235 if (skip_past_char (&p, '!') == SUCCESS)
3236 inst.operands[i].writeback = 1;
3238 else if (skip_past_comma (&p) == SUCCESS)
3240 if (skip_past_char (&p, '{') == SUCCESS)
3242 /* [Rn], {expr} - unindexed, with option */
3243 if (parse_immediate (&p, &inst.operands[i].imm,
3244 0, 255, TRUE) == FAIL)
3247 if (skip_past_char (&p, '}') == FAIL)
3249 inst.error = _("'}' expected at end of 'option' field");
3252 if (inst.operands[i].preind)
3254 inst.error = _("cannot combine index with option");
3262 inst.operands[i].postind = 1;
3263 inst.operands[i].writeback = 1;
3265 if (inst.operands[i].preind)
3267 inst.error = _("cannot combine pre- and post-indexing");
3272 else if (*p == '-') p++, inst.operands[i].negative = 1;
3274 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3276 inst.operands[i].imm = reg;
3277 inst.operands[i].immisreg = 1;
3279 if (skip_past_comma (&p) == SUCCESS)
3280 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3285 if (inst.operands[i].negative)
3287 inst.operands[i].negative = 0;
3290 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3296 /* If at this point neither .preind nor .postind is set, we have a
3297 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3298 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
3300 inst.operands[i].preind = 1;
3301 inst.reloc.exp.X_op = O_constant;
3302 inst.reloc.exp.X_add_number = 0;
3308 /* Miscellaneous. */
3310 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3311 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3313 parse_psr (char **str)
3316 unsigned long psr_field;
3318 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3319 feature for ease of use and backwards compatibility. */
3321 if (*p == 's' || *p == 'S')
3322 psr_field = SPSR_BIT;
3323 else if (*p == 'c' || *p == 'C')
3329 if (strncasecmp (p, "PSR", 3) != 0)
3335 /* A suffix follows. */
3336 const struct asm_psr *psr;
3344 while (ISALNUM (*p) || *p == '_');
3346 psr = hash_find_n (arm_psr_hsh, start, p - start);
3350 psr_field |= psr->field;
3355 goto error; /* Garbage after "[CS]PSR". */
3357 psr_field |= (PSR_c | PSR_f);
3363 inst.error = _("flag for {c}psr instruction expected");
3367 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3368 value suitable for splatting into the AIF field of the instruction. */
3371 parse_cps_flags (char **str)
3380 case '\0': case ',':
3383 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
3384 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
3385 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
3388 inst.error = _("unrecognized CPS flag");
3393 if (saw_a_flag == 0)
3395 inst.error = _("missing CPS flags");
3403 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3404 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3407 parse_endian_specifier (char **str)
3412 if (strncasecmp (s, "BE", 2))
3414 else if (strncasecmp (s, "LE", 2))
3418 inst.error = _("valid endian specifiers are be or le");
3422 if (ISALNUM (s[2]) || s[2] == '_')
3424 inst.error = _("valid endian specifiers are be or le");
3429 return little_endian;
3432 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3433 value suitable for poking into the rotate field of an sxt or sxta
3434 instruction, or FAIL on error. */
3437 parse_ror (char **str)
3442 if (strncasecmp (s, "ROR", 3) == 0)
3446 inst.error = _("missing rotation field after comma");
3450 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
3455 case 0: *str = s; return 0x0;
3456 case 8: *str = s; return 0x1;
3457 case 16: *str = s; return 0x2;
3458 case 24: *str = s; return 0x3;
3461 inst.error = _("rotation can only be 0, 8, 16, or 24");
3466 /* Parse a conditional code (from conds[] below). The value returned is in the
3467 range 0 .. 14, or FAIL. */
3469 parse_cond (char **str)
3472 const struct asm_cond *c;
3475 while (ISALPHA (*q))
3478 c = hash_find_n (arm_cond_hsh, p, q - p);
3481 inst.error = _("condition required");
3489 /* Matcher codes for parse_operands. */
3490 enum operand_parse_code
3492 OP_stop, /* end of line */
3494 OP_RR, /* ARM register */
3495 OP_RRnpc, /* ARM register, not r15 */
3496 OP_RRnpcb, /* ARM register, not r15, in square brackets */
3497 OP_RRw, /* ARM register, not r15, optional trailing ! */
3498 OP_RCP, /* Coprocessor number */
3499 OP_RCN, /* Coprocessor register */
3500 OP_RF, /* FPA register */
3501 OP_RVS, /* VFP single precision register */
3502 OP_RVD, /* VFP double precision register */
3503 OP_RVC, /* VFP control register */
3504 OP_RMF, /* Maverick F register */
3505 OP_RMD, /* Maverick D register */
3506 OP_RMFX, /* Maverick FX register */
3507 OP_RMDX, /* Maverick DX register */
3508 OP_RMAX, /* Maverick AX register */
3509 OP_RMDS, /* Maverick DSPSC register */
3510 OP_RIWR, /* iWMMXt wR register */
3511 OP_RIWC, /* iWMMXt wC register */
3512 OP_RIWG, /* iWMMXt wCG register */
3513 OP_RXA, /* XScale accumulator register */
3515 OP_REGLST, /* ARM register list */
3516 OP_VRSLST, /* VFP single-precision register list */
3517 OP_VRDLST, /* VFP double-precision register list */
3519 OP_I7, /* immediate value 0 .. 7 */
3520 OP_I15, /* 0 .. 15 */
3521 OP_I16, /* 1 .. 16 */
3522 OP_I31, /* 0 .. 31 */
3523 OP_I31w, /* 0 .. 31, optional trailing ! */
3524 OP_I32, /* 1 .. 32 */
3525 OP_I63s, /* -64 .. 63 */
3526 OP_I255, /* 0 .. 255 */
3527 OP_Iffff, /* 0 .. 65535 */
3529 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
3530 OP_I7b, /* 0 .. 7 */
3531 OP_I15b, /* 0 .. 15 */
3532 OP_I31b, /* 0 .. 31 */
3534 OP_SH, /* shifter operand */
3535 OP_ADDR, /* Memory address expression (any mode) */
3536 OP_EXP, /* arbitrary expression */
3537 OP_EXPi, /* same, with optional immediate prefix */
3538 OP_EXPr, /* same, with optional relocation suffix */
3540 OP_CPSF, /* CPS flags */
3541 OP_ENDI, /* Endianness specifier */
3542 OP_PSR, /* CPSR/SPSR mask for msr */
3543 OP_COND, /* conditional code */
3545 OP_RRnpc_I0, /* ARM register or literal 0 */
3546 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
3547 OP_RR_EXi, /* ARM register or expression with imm prefix */
3548 OP_RF_IF, /* FPA register or immediate */
3549 OP_RIWR_RIWC, /* iWMMXt R or C reg */
3551 /* Optional operands. */
3552 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
3553 OP_oI31b, /* 0 .. 31 */
3554 OP_oIffffb, /* 0 .. 65535 */
3555 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
3557 OP_oRR, /* ARM register */
3558 OP_oRRnpc, /* ARM register, not the PC */
3559 OP_oSHll, /* LSL immediate */
3560 OP_oSHar, /* ASR immediate */
3561 OP_oSHllar, /* LSL or ASR immediate */
3562 OP_oROR, /* ROR 0/8/16/24 */
3564 OP_FIRST_OPTIONAL = OP_oI7b
3567 /* Generic instruction operand parser. This does no encoding and no
3568 semantic validation; it merely squirrels values away in the inst
3569 structure. Returns SUCCESS or FAIL depending on whether the
3570 specified grammar matched. */
3572 parse_operands (char *str, const char *pattern)
3574 unsigned const char *upat = pattern;
3575 char *backtrack_pos = 0;
3576 const char *backtrack_error = 0;
3577 int i, val, backtrack_index = 0;
3579 #define po_char_or_fail(chr) do { \
3580 if (skip_past_char (&str, chr) == FAIL) \
3584 #define po_reg_or_fail(regtype) do { \
3585 val = arm_reg_parse (&str, regtype); \
3588 inst.error = _(reg_expected_msgs[regtype]); \
3591 inst.operands[i].reg = val; \
3592 inst.operands[i].isreg = 1; \
3595 #define po_reg_or_goto(regtype, label) do { \
3596 val = arm_reg_parse (&str, regtype); \
3600 inst.operands[i].reg = val; \
3601 inst.operands[i].isreg = 1; \
3604 #define po_imm_or_fail(min, max, popt) do { \
3605 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3607 inst.operands[i].imm = val; \
3610 #define po_misc_or_fail(expr) do { \
3615 skip_whitespace (str);
3617 for (i = 0; upat[i] != OP_stop; i++)
3619 if (upat[i] >= OP_FIRST_OPTIONAL)
3621 /* Remember where we are in case we need to backtrack. */
3622 assert (!backtrack_pos);
3623 backtrack_pos = str;
3624 backtrack_error = inst.error;
3625 backtrack_index = i;
3629 po_char_or_fail (',');
3637 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
3638 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
3639 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
3640 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
3641 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
3642 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
3643 case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
3644 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
3645 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
3646 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
3647 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
3648 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
3649 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
3650 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
3651 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
3652 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
3653 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
3656 po_char_or_fail ('[');
3657 po_reg_or_fail (REG_TYPE_RN);
3658 po_char_or_fail (']');
3662 po_reg_or_fail (REG_TYPE_RN);
3663 if (skip_past_char (&str, '!') == SUCCESS)
3664 inst.operands[i].writeback = 1;
3668 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
3669 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
3670 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
3671 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
3672 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
3673 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
3674 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
3675 case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
3677 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
3679 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
3680 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
3682 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
3683 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
3685 /* Immediate variants */
3687 po_char_or_fail ('{');
3688 po_imm_or_fail (0, 255, TRUE);
3689 po_char_or_fail ('}');
3693 /* The expression parser chokes on a trailing !, so we have
3694 to find it first and zap it. */
3697 while (*s && *s != ',')
3702 inst.operands[i].writeback = 1;
3704 po_imm_or_fail (0, 31, TRUE);
3712 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3717 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3722 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3724 if (inst.reloc.exp.X_op == O_symbol)
3726 val = parse_reloc (&str);
3729 inst.error = _("unrecognized relocation suffix");
3732 else if (val != BFD_RELOC_UNUSED)
3734 inst.operands[i].imm = val;
3735 inst.operands[i].hasreloc = 1;
3740 /* Register or expression */
3741 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
3742 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
3744 /* Register or immediate */
3745 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
3746 I0: po_imm_or_fail (0, 0, FALSE); break;
3748 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
3750 if (!is_immediate_prefix (*str))
3753 val = parse_fpa_immediate (&str);
3756 /* FPA immediates are encoded as registers 8-15.
3757 parse_fpa_immediate has already applied the offset. */
3758 inst.operands[i].reg = val;
3759 inst.operands[i].isreg = 1;
3762 /* Two kinds of register */
3765 struct reg_entry *rege = arm_reg_parse_multi (&str);
3766 if (rege->type != REG_TYPE_MMXWR
3767 && rege->type != REG_TYPE_MMXWC
3768 && rege->type != REG_TYPE_MMXWCG)
3770 inst.error = _("iWMMXt data or control register expected");
3773 inst.operands[i].reg = rege->number;
3774 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
3779 case OP_CPSF: val = parse_cps_flags (&str); break;
3780 case OP_ENDI: val = parse_endian_specifier (&str); break;
3781 case OP_oROR: val = parse_ror (&str); break;
3782 case OP_PSR: val = parse_psr (&str); break;
3783 case OP_COND: val = parse_cond (&str); break;
3785 /* Register lists */
3787 val = parse_reg_list (&str);
3790 inst.operands[1].writeback = 1;
3796 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
3800 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
3803 /* Addressing modes */
3805 po_misc_or_fail (parse_address (&str, i));
3809 po_misc_or_fail (parse_shifter_operand (&str, i));
3813 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
3817 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
3821 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
3825 as_fatal ("unhandled operand code %d", upat[i]);
3828 /* Various value-based sanity checks and shared operations. We
3829 do not signal immediate failures for the register constraints;
3830 this allows a syntax error to take precedence. */
3838 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
3839 inst.error = BAD_PC;
3852 inst.operands[i].imm = val;
3859 /* If we get here, this operand was successfully parsed. */
3860 inst.operands[i].present = 1;
3864 inst.error = BAD_ARGS;
3870 /* Do not backtrack over a trailing optional argument that
3871 absorbed some text. We will only fail again, with the
3872 'garbage following instruction' error message, which is
3873 probably less helpful than the current one. */
3874 if (backtrack_index == i && backtrack_pos != str
3875 && upat[i+1] == OP_stop)
3878 /* Try again, skipping the optional argument at backtrack_pos. */
3879 str = backtrack_pos;
3880 inst.error = backtrack_error;
3881 inst.operands[backtrack_index].present = 0;
3882 i = backtrack_index;
3886 /* Check that we have parsed all the arguments. */
3887 if (*str != '\0' && !inst.error)
3888 inst.error = _("garbage following instruction");
3890 return inst.error ? FAIL : SUCCESS;
3893 #undef po_char_or_fail
3894 #undef po_reg_or_fail
3895 #undef po_reg_or_goto
3896 #undef po_imm_or_fail
3898 /* Shorthand macro for instruction encoding functions issuing errors. */
3899 #define constraint(expr, err) do { \
3907 /* Functions for operand encoding. ARM, then Thumb. */
3909 #define rotate_left(v, n) (v << n | v >> (32 - n))
3911 /* If VAL can be encoded in the immediate field of an ARM instruction,
3912 return the encoded form. Otherwise, return FAIL. */
3915 encode_arm_immediate (unsigned int val)
3919 for (i = 0; i < 32; i += 2)
3920 if ((a = rotate_left (val, i)) <= 0xff)
3921 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
3926 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
3927 return the encoded form. Otherwise, return FAIL. */
3929 encode_thumb32_immediate (unsigned int val)
3936 for (i = 0; i < 32; i++)
3938 a = rotate_left (val, i);
3939 if (a >= 128 && a <= 255)
3940 return (a & 0x7f) | (i << 7);
3944 if (val == ((a << 16) | a))
3946 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
3950 if (val == ((a << 16) | a))
3951 return 0x200 | (a >> 8);
3955 /* Encode a VFP SP register number into inst.instruction. */
3958 encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
3963 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
3967 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
3971 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
3979 /* Encode a <shift> in an ARM-format instruction. The immediate,
3980 if any, is handled by md_apply_fix3. */
3982 encode_arm_shift (int i)
3984 if (inst.operands[i].shift_kind == SHIFT_RRX)
3985 inst.instruction |= SHIFT_ROR << 5;
3988 inst.instruction |= inst.operands[i].shift_kind << 5;
3989 if (inst.operands[i].immisreg)
3991 inst.instruction |= SHIFT_BY_REG;
3992 inst.instruction |= inst.operands[i].imm << 8;
3995 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4000 encode_arm_shifter_operand (int i)
4002 if (inst.operands[i].isreg)
4004 inst.instruction |= inst.operands[i].reg;
4005 encode_arm_shift (i);
4008 inst.instruction |= INST_IMMEDIATE;
4011 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4013 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
4015 assert (inst.operands[i].isreg);
4016 inst.instruction |= inst.operands[i].reg << 16;
4018 if (inst.operands[i].preind)
4022 inst.error = _("instruction does not accept preindexed addressing");
4025 inst.instruction |= PRE_INDEX;
4026 if (inst.operands[i].writeback)
4027 inst.instruction |= WRITE_BACK;
4030 else if (inst.operands[i].postind)
4032 assert (inst.operands[i].writeback);
4034 inst.instruction |= WRITE_BACK;
4036 else /* unindexed - only for coprocessor */
4038 inst.error = _("instruction does not accept unindexed addressing");
4042 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
4043 && (((inst.instruction & 0x000f0000) >> 16)
4044 == ((inst.instruction & 0x0000f000) >> 12)))
4045 as_warn ((inst.instruction & LOAD_BIT)
4046 ? _("destination register same as write-back base")
4047 : _("source register same as write-back base"));
4050 /* inst.operands[i] was set up by parse_address. Encode it into an
4051 ARM-format mode 2 load or store instruction. If is_t is true,
4052 reject forms that cannot be used with a T instruction (i.e. not
4055 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
4057 encode_arm_addr_mode_common (i, is_t);
4059 if (inst.operands[i].immisreg)
4061 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
4062 inst.instruction |= inst.operands[i].imm;
4063 if (!inst.operands[i].negative)
4064 inst.instruction |= INDEX_UP;
4065 if (inst.operands[i].shifted)
4067 if (inst.operands[i].shift_kind == SHIFT_RRX)
4068 inst.instruction |= SHIFT_ROR << 5;
4071 inst.instruction |= inst.operands[i].shift_kind << 5;
4072 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4076 else /* immediate offset in inst.reloc */
4078 if (inst.reloc.type == BFD_RELOC_UNUSED)
4079 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4080 if (inst.reloc.pc_rel)
4081 inst.reloc.exp.X_add_number -= 8; /* pipeline offset */
4085 /* inst.operands[i] was set up by parse_address. Encode it into an
4086 ARM-format mode 3 load or store instruction. Reject forms that
4087 cannot be used with such instructions. If is_t is true, reject
4088 forms that cannot be used with a T instruction (i.e. not
4091 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
4093 if (inst.operands[i].immisreg && inst.operands[i].shifted)
4095 inst.error = _("instruction does not accept scaled register index");
4099 encode_arm_addr_mode_common (i, is_t);
4101 if (inst.operands[i].immisreg)
4103 inst.instruction |= inst.operands[i].imm;
4104 if (!inst.operands[i].negative)
4105 inst.instruction |= INDEX_UP;
4107 else /* immediate offset in inst.reloc */
4109 inst.instruction |= HWOFFSET_IMM;
4110 if (inst.reloc.type == BFD_RELOC_UNUSED)
4111 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4112 if (inst.reloc.pc_rel)
4113 inst.reloc.exp.X_add_number -= 8; /* pipeline offset */
4117 /* inst.operands[i] was set up by parse_address. Encode it into an
4118 ARM-format instruction. Reject all forms which cannot be encoded
4119 into a coprocessor load/store instruction. If wb_ok is false,
4120 reject use of writeback; if unind_ok is false, reject use of
4121 unindexed addressing. If reloc_override is not 0, use it instead
4122 of BFD_ARM_CP_OFF_IMM. */
4125 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
4127 inst.instruction |= inst.operands[i].reg << 16;
4129 assert (!(inst.operands[i].preind && inst.operands[i].postind));
4131 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
4133 assert (!inst.operands[i].writeback);
4136 inst.error = _("instruction does not support unindexed addressing");
4139 inst.instruction |= inst.operands[i].imm;
4140 inst.instruction |= INDEX_UP;
4144 if (inst.operands[i].preind)
4145 inst.instruction |= PRE_INDEX;
4147 if (inst.operands[i].writeback)
4149 if (inst.operands[i].reg == REG_PC)
4151 inst.error = _("pc may not be used with write-back");
4156 inst.error = _("instruction does not support writeback");
4159 inst.instruction |= WRITE_BACK;
4163 inst.reloc.type = reloc_override;
4165 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
4166 if (inst.reloc.pc_rel)
4167 inst.reloc.exp.X_add_number -= 8;
4171 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4172 Determine whether it can be performed with a move instruction; if
4173 it can, convert inst.instruction to that move instruction and
4174 return 1; if it can't, convert inst.instruction to a literal-pool
4175 load and return 0. If this is not a valid thing to do in the
4176 current context, set inst.error and return 1.
4178 inst.operands[i] describes the destination register. */
4181 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
4183 if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0)
4185 inst.error = _("invalid pseudo operation");
4188 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
4190 inst.error = _("constant expression expected");
4193 if (inst.reloc.exp.X_op == O_constant)
4197 if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
4199 /* This can be done with a mov(1) instruction. */
4200 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
4201 inst.instruction |= inst.reloc.exp.X_add_number;
4207 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
4210 /* This can be done with a mov instruction. */
4211 inst.instruction &= LITERAL_MASK;
4212 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4213 inst.instruction |= value & 0xfff;
4217 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
4220 /* This can be done with a mvn instruction. */
4221 inst.instruction &= LITERAL_MASK;
4222 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4223 inst.instruction |= value & 0xfff;
4229 if (add_to_lit_pool () == FAIL)
4231 inst.error = _("literal pool insertion failed");
4234 inst.operands[1].reg = REG_PC;
4235 inst.operands[1].isreg = 1;
4236 inst.operands[1].preind = 1;
4237 inst.reloc.pc_rel = 1;
4238 inst.reloc.type = (thumb_p
4239 ? BFD_RELOC_ARM_THUMB_OFFSET
4241 ? BFD_RELOC_ARM_HWLITERAL
4242 : BFD_RELOC_ARM_LITERAL));
4246 /* Functions for instruction encoding, sorted by subarchitecture.
4247 First some generics; their names are taken from the conventional
4248 bit positions for register arguments in ARM format instructions. */
4258 inst.instruction |= inst.operands[0].reg << 12;
4264 inst.instruction |= inst.operands[0].reg << 12;
4265 inst.instruction |= inst.operands[1].reg;
4271 inst.instruction |= inst.operands[0].reg << 12;
4272 inst.instruction |= inst.operands[1].reg << 16;
4278 inst.instruction |= inst.operands[0].reg << 16;
4279 inst.instruction |= inst.operands[1].reg << 12;
4285 inst.instruction |= inst.operands[0].reg << 12;
4286 inst.instruction |= inst.operands[1].reg;
4287 inst.instruction |= inst.operands[2].reg << 16;
4293 inst.instruction |= inst.operands[0].reg << 12;
4294 inst.instruction |= inst.operands[1].reg << 16;
4295 inst.instruction |= inst.operands[2].reg;
4301 inst.instruction |= inst.operands[0].reg;
4302 inst.instruction |= inst.operands[1].reg << 12;
4303 inst.instruction |= inst.operands[2].reg << 16;
4309 inst.instruction |= inst.operands[0].imm;
4315 inst.instruction |= inst.operands[0].reg << 12;
4316 encode_arm_cp_address (1, TRUE, TRUE, 0);
4319 /* ARM instructions, in alphabetical order by function name (except
4320 that wrapper functions appear immediately after the function they
4323 /* This is a pseudo-op of the form "adr rd, label" to be converted
4324 into a relative address of the form "add rd, pc, #label-.-8". */
4329 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4331 /* Frag hacking will turn this into a sub instruction if the offset turns
4332 out to be negative. */
4333 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4335 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
4337 inst.reloc.pc_rel = 1;
4340 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4341 into a relative address of the form:
4342 add rd, pc, #low(label-.-8)"
4343 add rd, rd, #high(label-.-8)" */
4348 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4350 /* Frag hacking will turn this into a sub instruction if the offset turns
4351 out to be negative. */
4352 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4354 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
4356 inst.reloc.pc_rel = 1;
4357 inst.size = INSN_SIZE * 2;
4363 if (!inst.operands[1].present)
4364 inst.operands[1].reg = inst.operands[0].reg;
4365 inst.instruction |= inst.operands[0].reg << 12;
4366 inst.instruction |= inst.operands[1].reg << 16;
4367 encode_arm_shifter_operand (2);
4373 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
4374 constraint (msb > 32, _("bit-field extends past end of register"));
4375 /* The instruction encoding stores the LSB and MSB,
4376 not the LSB and width. */
4377 inst.instruction |= inst.operands[0].reg << 12;
4378 inst.instruction |= inst.operands[1].imm << 7;
4379 inst.instruction |= (msb - 1) << 16;
4387 /* #0 in second position is alternative syntax for bfc, which is
4388 the same instruction but with REG_PC in the Rm field. */
4389 if (!inst.operands[1].isreg)
4390 inst.operands[1].reg = REG_PC;
4392 msb = inst.operands[2].imm + inst.operands[3].imm;
4393 constraint (msb > 32, _("bit-field extends past end of register"));
4394 /* The instruction encoding stores the LSB and MSB,
4395 not the LSB and width. */
4396 inst.instruction |= inst.operands[0].reg << 12;
4397 inst.instruction |= inst.operands[1].reg;
4398 inst.instruction |= inst.operands[2].imm << 7;
4399 inst.instruction |= (msb - 1) << 16;
4405 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
4406 _("bit-field extends past end of register"));
4407 inst.instruction |= inst.operands[0].reg << 12;
4408 inst.instruction |= inst.operands[1].reg;
4409 inst.instruction |= inst.operands[2].imm << 7;
4410 inst.instruction |= (inst.operands[3].imm - 1) << 16;
4413 /* ARM V5 breakpoint instruction (argument parse)
4414 BKPT <16 bit unsigned immediate>
4415 Instruction is not conditional.
4416 The bit pattern given in insns[] has the COND_ALWAYS condition,
4417 and it is an error if the caller tried to override that. */
4422 /* Top 12 of 16 bits to bits 19:8. */
4423 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
4425 /* Bottom 4 of 16 bits to bits 3:0. */
4426 inst.instruction |= inst.operands[0].imm & 0xf;
4430 encode_branch (int default_reloc)
4432 if (inst.operands[0].hasreloc)
4434 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
4435 _("the only suffix valid here is '(plt)'"));
4436 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4437 inst.reloc.pc_rel = 0;
4441 inst.reloc.type = default_reloc;
4442 inst.reloc.pc_rel = 1;
4449 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4452 /* ARM V5 branch-link-exchange instruction (argument parse)
4453 BLX <target_addr> ie BLX(1)
4454 BLX{<condition>} <Rm> ie BLX(2)
4455 Unfortunately, there are two different opcodes for this mnemonic.
4456 So, the insns[].value is not used, and the code here zaps values
4457 into inst.instruction.
4458 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4463 if (inst.operands[0].isreg)
4465 /* Arg is a register; the opcode provided by insns[] is correct.
4466 It is not illegal to do "blx pc", just useless. */
4467 if (inst.operands[0].reg == REG_PC)
4468 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4470 inst.instruction |= inst.operands[0].reg;
4474 /* Arg is an address; this instruction cannot be executed
4475 conditionally, and the opcode must be adjusted. */
4476 constraint (inst.cond != COND_ALWAYS, BAD_COND);
4477 inst.instruction = 0xfafffffe;
4478 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
4485 if (inst.operands[0].reg == REG_PC)
4486 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4488 inst.instruction |= inst.operands[0].reg;
4492 /* ARM v5TEJ. Jump to Jazelle code. */
4497 if (inst.operands[0].reg == REG_PC)
4498 as_tsktsk (_("use of r15 in bxj is not really useful"));
4500 inst.instruction |= inst.operands[0].reg;
4503 /* Co-processor data operation:
4504 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4505 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4509 inst.instruction |= inst.operands[0].reg << 8;
4510 inst.instruction |= inst.operands[1].imm << 20;
4511 inst.instruction |= inst.operands[2].reg << 12;
4512 inst.instruction |= inst.operands[3].reg << 16;
4513 inst.instruction |= inst.operands[4].reg;
4514 inst.instruction |= inst.operands[5].imm << 5;
4520 inst.instruction |= inst.operands[0].reg << 16;
4521 encode_arm_shifter_operand (1);
4524 /* Transfer between coprocessor and ARM registers.
4525 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4530 No special properties. */
4535 inst.instruction |= inst.operands[0].reg << 8;
4536 inst.instruction |= inst.operands[1].imm << 21;
4537 inst.instruction |= inst.operands[2].reg << 12;
4538 inst.instruction |= inst.operands[3].reg << 16;
4539 inst.instruction |= inst.operands[4].reg;
4540 inst.instruction |= inst.operands[5].imm << 5;
4543 /* Transfer between coprocessor register and pair of ARM registers.
4544 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4549 Two XScale instructions are special cases of these:
4551 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4552 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4554 Result unpredicatable if Rd or Rn is R15. */
4559 inst.instruction |= inst.operands[0].reg << 8;
4560 inst.instruction |= inst.operands[1].imm << 4;
4561 inst.instruction |= inst.operands[2].reg << 12;
4562 inst.instruction |= inst.operands[3].reg << 16;
4563 inst.instruction |= inst.operands[4].reg;
4569 inst.instruction |= inst.operands[0].imm << 6;
4570 inst.instruction |= inst.operands[1].imm;
4576 /* There is no IT instruction in ARM mode. We
4577 process it but do not generate code for it. */
4584 int base_reg = inst.operands[0].reg;
4585 int range = inst.operands[1].imm;
4587 inst.instruction |= base_reg << 16;
4588 inst.instruction |= range;
4590 if (inst.operands[1].writeback)
4591 inst.instruction |= LDM_TYPE_2_OR_3;
4593 if (inst.operands[0].writeback)
4595 inst.instruction |= WRITE_BACK;
4596 /* Check for unpredictable uses of writeback. */
4597 if (inst.instruction & LOAD_BIT)
4599 /* Not allowed in LDM type 2. */
4600 if ((inst.instruction & LDM_TYPE_2_OR_3)
4601 && ((range & (1 << REG_PC)) == 0))
4602 as_warn (_("writeback of base register is UNPREDICTABLE"));
4603 /* Only allowed if base reg not in list for other types. */
4604 else if (range & (1 << base_reg))
4605 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4609 /* Not allowed for type 2. */
4610 if (inst.instruction & LDM_TYPE_2_OR_3)
4611 as_warn (_("writeback of base register is UNPREDICTABLE"));
4612 /* Only allowed if base reg not in list, or first in list. */
4613 else if ((range & (1 << base_reg))
4614 && (range & ((1 << base_reg) - 1)))
4615 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4620 /* ARMv5TE load-consecutive (argument parse)
4629 constraint (inst.operands[0].reg % 2 != 0,
4630 _("first destination register must be even"));
4631 constraint (inst.operands[1].present
4632 && inst.operands[1].reg != inst.operands[0].reg + 1,
4633 _("can only load two consecutive registers"));
4634 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4635 constraint (!inst.operands[2].isreg, _("'[' expected"));
4637 if (!inst.operands[1].present)
4638 inst.operands[1].reg = inst.operands[0].reg + 1;
4640 if (inst.instruction & LOAD_BIT)
4642 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4643 register and the first register written; we have to diagnose
4644 overlap between the base and the second register written here. */
4646 if (inst.operands[2].reg == inst.operands[1].reg
4647 && (inst.operands[2].writeback || inst.operands[2].postind))
4648 as_warn (_("base register written back, and overlaps "
4649 "second destination register"));
4651 /* For an index-register load, the index register must not overlap the
4652 destination (even if not write-back). */
4653 else if (inst.operands[2].immisreg
4654 && (inst.operands[2].imm == inst.operands[0].reg
4655 || inst.operands[2].imm == inst.operands[1].reg))
4656 as_warn (_("index register overlaps destination register"));
4659 inst.instruction |= inst.operands[0].reg << 12;
4660 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
4666 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
4667 || inst.operands[1].postind || inst.operands[1].writeback
4668 || inst.operands[1].immisreg || inst.operands[1].shifted
4669 || inst.operands[1].negative,
4670 _("instruction does not accept this addressing mode"));
4672 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
4674 constraint (inst.reloc.exp.X_op != O_constant
4675 || inst.reloc.exp.X_add_number != 0,
4676 _("offset must be zero in ARM encoding"));
4678 inst.instruction |= inst.operands[0].reg << 12;
4679 inst.instruction |= inst.operands[1].reg << 16;
4680 inst.reloc.type = BFD_RELOC_UNUSED;
4686 constraint (inst.operands[0].reg % 2 != 0,
4687 _("even register required"));
4688 constraint (inst.operands[1].present
4689 && inst.operands[1].reg != inst.operands[0].reg + 1,
4690 _("can only load two consecutive registers"));
4691 /* If op 1 were present and equal to PC, this function wouldn't
4692 have been called in the first place. */
4693 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4695 inst.instruction |= inst.operands[0].reg << 12;
4696 inst.instruction |= inst.operands[2].reg << 16;
4702 inst.instruction |= inst.operands[0].reg << 12;
4703 if (!inst.operands[1].isreg)
4704 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
4706 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
4712 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4714 if (inst.operands[1].preind)
4716 constraint (inst.reloc.exp.X_op != O_constant ||
4717 inst.reloc.exp.X_add_number != 0,
4718 _("this instruction requires a post-indexed address"));
4720 inst.operands[1].preind = 0;
4721 inst.operands[1].postind = 1;
4722 inst.operands[1].writeback = 1;
4724 inst.instruction |= inst.operands[0].reg << 12;
4725 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
4728 /* Halfword and signed-byte load/store operations. */
4733 inst.instruction |= inst.operands[0].reg << 12;
4734 if (!inst.operands[1].isreg)
4735 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
4737 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
4743 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4745 if (inst.operands[1].preind)
4747 constraint (inst.reloc.exp.X_op != O_constant ||
4748 inst.reloc.exp.X_add_number != 0,
4749 _("this instruction requires a post-indexed address"));
4751 inst.operands[1].preind = 0;
4752 inst.operands[1].postind = 1;
4753 inst.operands[1].writeback = 1;
4755 inst.instruction |= inst.operands[0].reg << 12;
4756 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
4759 /* Co-processor register load/store.
4760 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
4764 inst.instruction |= inst.operands[0].reg << 8;
4765 inst.instruction |= inst.operands[1].reg << 12;
4766 encode_arm_cp_address (2, TRUE, TRUE, 0);
4772 /* This restriction does not apply to mls (nor to mla in v6, but
4773 that's hard to detect at present). */
4774 if (inst.operands[0].reg == inst.operands[1].reg
4775 && !(inst.instruction & 0x00400000))
4776 as_tsktsk (_("rd and rm should be different in mla"));
4778 inst.instruction |= inst.operands[0].reg << 16;
4779 inst.instruction |= inst.operands[1].reg;
4780 inst.instruction |= inst.operands[2].reg << 8;
4781 inst.instruction |= inst.operands[3].reg << 12;
4788 inst.instruction |= inst.operands[0].reg << 12;
4789 encode_arm_shifter_operand (1);
4792 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
4796 inst.instruction |= inst.operands[0].reg << 12;
4797 /* The value is in two pieces: 0:11, 16:19. */
4798 inst.instruction |= (inst.operands[1].imm & 0x00000fff);
4799 inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
4805 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
4806 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
4808 _("'CPSR' or 'SPSR' expected"));
4809 inst.instruction |= inst.operands[0].reg << 12;
4810 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
4813 /* Two possible forms:
4814 "{C|S}PSR_<field>, Rm",
4815 "{C|S}PSR_f, #expression". */
4820 inst.instruction |= inst.operands[0].imm;
4821 if (inst.operands[1].isreg)
4822 inst.instruction |= inst.operands[1].reg;
4825 inst.instruction |= INST_IMMEDIATE;
4826 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4827 inst.reloc.pc_rel = 0;
4834 if (!inst.operands[2].present)
4835 inst.operands[2].reg = inst.operands[0].reg;
4836 inst.instruction |= inst.operands[0].reg << 16;
4837 inst.instruction |= inst.operands[1].reg;
4838 inst.instruction |= inst.operands[2].reg << 8;
4840 if (inst.operands[0].reg == inst.operands[1].reg)
4841 as_tsktsk (_("rd and rm should be different in mul"));
4844 /* Long Multiply Parser
4845 UMULL RdLo, RdHi, Rm, Rs
4846 SMULL RdLo, RdHi, Rm, Rs
4847 UMLAL RdLo, RdHi, Rm, Rs
4848 SMLAL RdLo, RdHi, Rm, Rs. */
4853 inst.instruction |= inst.operands[0].reg << 12;
4854 inst.instruction |= inst.operands[1].reg << 16;
4855 inst.instruction |= inst.operands[2].reg;
4856 inst.instruction |= inst.operands[3].reg << 8;
4858 /* rdhi, rdlo and rm must all be different. */
4859 if (inst.operands[0].reg == inst.operands[1].reg
4860 || inst.operands[0].reg == inst.operands[2].reg
4861 || inst.operands[1].reg == inst.operands[2].reg)
4862 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
4868 if (inst.operands[0].present)
4870 /* Architectural NOP hints are CPSR sets with no bits selected. */
4871 inst.instruction &= 0xf0000000;
4872 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
4876 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
4877 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
4878 Condition defaults to COND_ALWAYS.
4879 Error if Rd, Rn or Rm are R15. */
4884 inst.instruction |= inst.operands[0].reg << 12;
4885 inst.instruction |= inst.operands[1].reg << 16;
4886 inst.instruction |= inst.operands[2].reg;
4887 if (inst.operands[3].present)
4888 encode_arm_shift (3);
4891 /* ARM V6 PKHTB (Argument Parse). */
4896 if (!inst.operands[3].present)
4898 /* If the shift specifier is omitted, turn the instruction
4899 into pkhbt rd, rm, rn. */
4900 inst.instruction &= 0xfff00010;
4901 inst.instruction |= inst.operands[0].reg << 12;
4902 inst.instruction |= inst.operands[1].reg;
4903 inst.instruction |= inst.operands[2].reg << 16;
4907 inst.instruction |= inst.operands[0].reg << 12;
4908 inst.instruction |= inst.operands[1].reg << 16;
4909 inst.instruction |= inst.operands[2].reg;
4910 encode_arm_shift (3);
4914 /* ARMv5TE: Preload-Cache
4918 Syntactically, like LDR with B=1, W=0, L=1. */
4923 constraint (!inst.operands[0].isreg,
4924 _("'[' expected after PLD mnemonic"));
4925 constraint (inst.operands[0].postind,
4926 _("post-indexed expression used in preload instruction"));
4927 constraint (inst.operands[0].writeback,
4928 _("writeback used in preload instruction"));
4929 constraint (!inst.operands[0].preind,
4930 _("unindexed addressing used in preload instruction"));
4931 inst.instruction |= inst.operands[0].reg;
4932 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
4938 inst.operands[1] = inst.operands[0];
4939 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
4940 inst.operands[0].isreg = 1;
4941 inst.operands[0].writeback = 1;
4942 inst.operands[0].reg = REG_SP;
4946 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
4947 word at the specified address and the following word
4949 Unconditionally executed.
4950 Error if Rn is R15. */
4955 inst.instruction |= inst.operands[0].reg << 16;
4956 if (inst.operands[0].writeback)
4957 inst.instruction |= WRITE_BACK;
4960 /* ARM V6 ssat (argument parse). */
4965 inst.instruction |= inst.operands[0].reg << 12;
4966 inst.instruction |= (inst.operands[1].imm - 1) << 16;
4967 inst.instruction |= inst.operands[2].reg;
4969 if (inst.operands[3].present)
4970 encode_arm_shift (3);
4973 /* ARM V6 usat (argument parse). */
4978 inst.instruction |= inst.operands[0].reg << 12;
4979 inst.instruction |= inst.operands[1].imm << 16;
4980 inst.instruction |= inst.operands[2].reg;
4982 if (inst.operands[3].present)
4983 encode_arm_shift (3);
4986 /* ARM V6 ssat16 (argument parse). */
4991 inst.instruction |= inst.operands[0].reg << 12;
4992 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
4993 inst.instruction |= inst.operands[2].reg;
4999 inst.instruction |= inst.operands[0].reg << 12;
5000 inst.instruction |= inst.operands[1].imm << 16;
5001 inst.instruction |= inst.operands[2].reg;
5004 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5005 preserving the other bits.
5007 setend <endian_specifier>, where <endian_specifier> is either
5013 if (inst.operands[0].imm)
5014 inst.instruction |= 0x200;
5020 unsigned int Rm = (inst.operands[1].present
5021 ? inst.operands[1].reg
5022 : inst.operands[0].reg);
5024 inst.instruction |= inst.operands[0].reg << 12;
5025 inst.instruction |= Rm;
5026 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
5028 constraint (inst.operands[0].reg != Rm,
5029 _("source1 and dest must be same register"));
5030 inst.instruction |= inst.operands[2].reg << 8;
5031 inst.instruction |= SHIFT_BY_REG;
5034 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
5040 inst.reloc.type = BFD_RELOC_ARM_SMI;
5041 inst.reloc.pc_rel = 0;
5047 inst.reloc.type = BFD_RELOC_ARM_SWI;
5048 inst.reloc.pc_rel = 0;
5051 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5052 SMLAxy{cond} Rd,Rm,Rs,Rn
5053 SMLAWy{cond} Rd,Rm,Rs,Rn
5054 Error if any register is R15. */
5059 inst.instruction |= inst.operands[0].reg << 16;
5060 inst.instruction |= inst.operands[1].reg;
5061 inst.instruction |= inst.operands[2].reg << 8;
5062 inst.instruction |= inst.operands[3].reg << 12;
5065 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5066 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5067 Error if any register is R15.
5068 Warning if Rdlo == Rdhi. */
5073 inst.instruction |= inst.operands[0].reg << 12;
5074 inst.instruction |= inst.operands[1].reg << 16;
5075 inst.instruction |= inst.operands[2].reg;
5076 inst.instruction |= inst.operands[3].reg << 8;
5078 if (inst.operands[0].reg == inst.operands[1].reg)
5079 as_tsktsk (_("rdhi and rdlo must be different"));
5082 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5083 SMULxy{cond} Rd,Rm,Rs
5084 Error if any register is R15. */
5089 inst.instruction |= inst.operands[0].reg << 16;
5090 inst.instruction |= inst.operands[1].reg;
5091 inst.instruction |= inst.operands[2].reg << 8;
5094 /* ARM V6 srs (argument parse). */
5099 inst.instruction |= inst.operands[0].imm;
5100 if (inst.operands[0].writeback)
5101 inst.instruction |= WRITE_BACK;
5104 /* ARM V6 strex (argument parse). */
5109 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
5110 || inst.operands[2].postind || inst.operands[2].writeback
5111 || inst.operands[2].immisreg || inst.operands[2].shifted
5112 || inst.operands[2].negative,
5113 _("instruction does not accept this addressing mode"));
5115 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
5117 constraint (inst.operands[0].reg == inst.operands[1].reg
5118 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
5120 constraint (inst.reloc.exp.X_op != O_constant
5121 || inst.reloc.exp.X_add_number != 0,
5122 _("offset must be zero in ARM encoding"));
5124 inst.instruction |= inst.operands[0].reg << 12;
5125 inst.instruction |= inst.operands[1].reg;
5126 inst.instruction |= inst.operands[2].reg << 16;
5127 inst.reloc.type = BFD_RELOC_UNUSED;
5133 constraint (inst.operands[1].reg % 2 != 0,
5134 _("even register required"));
5135 constraint (inst.operands[2].present
5136 && inst.operands[2].reg != inst.operands[1].reg + 1,
5137 _("can only store two consecutive registers"));
5138 /* If op 2 were present and equal to PC, this function wouldn't
5139 have been called in the first place. */
5140 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
5142 constraint (inst.operands[0].reg == inst.operands[1].reg
5143 || inst.operands[0].reg == inst.operands[1].reg + 1
5144 || inst.operands[0].reg == inst.operands[3].reg,
5147 inst.instruction |= inst.operands[0].reg << 12;
5148 inst.instruction |= inst.operands[1].reg;
5149 inst.instruction |= inst.operands[3].reg << 16;
5152 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5153 extends it to 32-bits, and adds the result to a value in another
5154 register. You can specify a rotation by 0, 8, 16, or 24 bits
5155 before extracting the 16-bit value.
5156 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5157 Condition defaults to COND_ALWAYS.
5158 Error if any register uses R15. */
5163 inst.instruction |= inst.operands[0].reg << 12;
5164 inst.instruction |= inst.operands[1].reg << 16;
5165 inst.instruction |= inst.operands[2].reg;
5166 inst.instruction |= inst.operands[3].imm << 10;
5171 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5172 Condition defaults to COND_ALWAYS.
5173 Error if any register uses R15. */
5178 inst.instruction |= inst.operands[0].reg << 12;
5179 inst.instruction |= inst.operands[1].reg;
5180 inst.instruction |= inst.operands[2].imm << 10;
5183 /* VFP instructions. In a logical order: SP variant first, monad
5184 before dyad, arithmetic then move then load/store. */
5187 do_vfp_sp_monadic (void)
5189 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5190 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5194 do_vfp_sp_dyadic (void)
5196 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5197 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5198 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5202 do_vfp_sp_compare_z (void)
5204 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5208 do_vfp_dp_sp_cvt (void)
5210 inst.instruction |= inst.operands[0].reg << 12;
5211 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5215 do_vfp_sp_dp_cvt (void)
5217 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5218 inst.instruction |= inst.operands[1].reg;
5222 do_vfp_reg_from_sp (void)
5224 inst.instruction |= inst.operands[0].reg << 12;
5225 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5229 do_vfp_reg2_from_sp2 (void)
5231 constraint (inst.operands[2].imm != 2,
5232 _("only two consecutive VFP SP registers allowed here"));
5233 inst.instruction |= inst.operands[0].reg << 12;
5234 inst.instruction |= inst.operands[1].reg << 16;
5235 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5239 do_vfp_sp_from_reg (void)
5241 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
5242 inst.instruction |= inst.operands[1].reg << 12;
5246 do_vfp_sp2_from_reg2 (void)
5248 constraint (inst.operands[0].imm != 2,
5249 _("only two consecutive VFP SP registers allowed here"));
5250 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
5251 inst.instruction |= inst.operands[1].reg << 12;
5252 inst.instruction |= inst.operands[2].reg << 16;
5256 do_vfp_sp_ldst (void)
5258 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5259 encode_arm_cp_address (1, FALSE, TRUE, 0);
5263 do_vfp_dp_ldst (void)
5265 inst.instruction |= inst.operands[0].reg << 12;
5266 encode_arm_cp_address (1, FALSE, TRUE, 0);
5271 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
5273 if (inst.operands[0].writeback)
5274 inst.instruction |= WRITE_BACK;
5276 constraint (ldstm_type != VFP_LDSTMIA,
5277 _("this addressing mode requires base-register writeback"));
5278 inst.instruction |= inst.operands[0].reg << 16;
5279 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
5280 inst.instruction |= inst.operands[1].imm;
5284 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
5288 if (inst.operands[0].writeback)
5289 inst.instruction |= WRITE_BACK;
5291 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
5292 _("this addressing mode requires base-register writeback"));
5294 inst.instruction |= inst.operands[0].reg << 16;
5295 inst.instruction |= inst.operands[1].reg << 12;
5297 count = inst.operands[1].imm << 1;
5298 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
5301 inst.instruction |= count;
5305 do_vfp_sp_ldstmia (void)
5307 vfp_sp_ldstm (VFP_LDSTMIA);
5311 do_vfp_sp_ldstmdb (void)
5313 vfp_sp_ldstm (VFP_LDSTMDB);
5317 do_vfp_dp_ldstmia (void)
5319 vfp_dp_ldstm (VFP_LDSTMIA);
5323 do_vfp_dp_ldstmdb (void)
5325 vfp_dp_ldstm (VFP_LDSTMDB);
5329 do_vfp_xp_ldstmia (void)
5331 vfp_dp_ldstm (VFP_LDSTMIAX);
5335 do_vfp_xp_ldstmdb (void)
5337 vfp_dp_ldstm (VFP_LDSTMDBX);
5340 /* FPA instructions. Also in a logical order. */
5345 inst.instruction |= inst.operands[0].reg << 16;
5346 inst.instruction |= inst.operands[1].reg;
5350 do_fpa_ldmstm (void)
5352 inst.instruction |= inst.operands[0].reg << 12;
5353 switch (inst.operands[1].imm)
5355 case 1: inst.instruction |= CP_T_X; break;
5356 case 2: inst.instruction |= CP_T_Y; break;
5357 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
5362 if (inst.instruction & (PRE_INDEX | INDEX_UP))
5364 /* The instruction specified "ea" or "fd", so we can only accept
5365 [Rn]{!}. The instruction does not really support stacking or
5366 unstacking, so we have to emulate these by setting appropriate
5367 bits and offsets. */
5368 constraint (inst.reloc.exp.X_op != O_constant
5369 || inst.reloc.exp.X_add_number != 0,
5370 _("this instruction does not support indexing"));
5372 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
5373 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
5375 if (!(inst.instruction & INDEX_UP))
5376 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
5378 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
5380 inst.operands[2].preind = 0;
5381 inst.operands[2].postind = 1;
5385 encode_arm_cp_address (2, TRUE, TRUE, 0);
5388 /* iWMMXt instructions: strictly in alphabetical order. */
5391 do_iwmmxt_tandorc (void)
5393 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
5397 do_iwmmxt_textrc (void)
5399 inst.instruction |= inst.operands[0].reg << 12;
5400 inst.instruction |= inst.operands[1].imm;
5404 do_iwmmxt_textrm (void)
5406 inst.instruction |= inst.operands[0].reg << 12;
5407 inst.instruction |= inst.operands[1].reg << 16;
5408 inst.instruction |= inst.operands[2].imm;
5412 do_iwmmxt_tinsr (void)
5414 inst.instruction |= inst.operands[0].reg << 16;
5415 inst.instruction |= inst.operands[1].reg << 12;
5416 inst.instruction |= inst.operands[2].imm;
5420 do_iwmmxt_tmia (void)
5422 inst.instruction |= inst.operands[0].reg << 5;
5423 inst.instruction |= inst.operands[1].reg;
5424 inst.instruction |= inst.operands[2].reg << 12;
5428 do_iwmmxt_waligni (void)
5430 inst.instruction |= inst.operands[0].reg << 12;
5431 inst.instruction |= inst.operands[1].reg << 16;
5432 inst.instruction |= inst.operands[2].reg;
5433 inst.instruction |= inst.operands[3].imm << 20;
5437 do_iwmmxt_wmov (void)
5439 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5440 inst.instruction |= inst.operands[0].reg << 12;
5441 inst.instruction |= inst.operands[1].reg << 16;
5442 inst.instruction |= inst.operands[1].reg;
5446 do_iwmmxt_wldstbh (void)
5448 inst.instruction |= inst.operands[0].reg << 12;
5449 inst.reloc.exp.X_add_number *= 4;
5450 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
5454 do_iwmmxt_wldstw (void)
5456 /* RIWR_RIWC clears .isreg for a control register. */
5457 if (!inst.operands[0].isreg)
5459 constraint (inst.cond != COND_ALWAYS, BAD_COND);
5460 inst.instruction |= 0xf0000000;
5463 inst.instruction |= inst.operands[0].reg << 12;
5464 encode_arm_cp_address (1, TRUE, TRUE, 0);
5468 do_iwmmxt_wldstd (void)
5470 inst.instruction |= inst.operands[0].reg << 12;
5471 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
5475 do_iwmmxt_wshufh (void)
5477 inst.instruction |= inst.operands[0].reg << 12;
5478 inst.instruction |= inst.operands[1].reg << 16;
5479 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
5480 inst.instruction |= (inst.operands[2].imm & 0x0f);
5484 do_iwmmxt_wzero (void)
5486 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5487 inst.instruction |= inst.operands[0].reg;
5488 inst.instruction |= inst.operands[0].reg << 12;
5489 inst.instruction |= inst.operands[0].reg << 16;
5492 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5493 operations first, then control, shift, and load/store. */
5495 /* Insns like "foo X,Y,Z". */
5498 do_mav_triple (void)
5500 inst.instruction |= inst.operands[0].reg << 16;
5501 inst.instruction |= inst.operands[1].reg;
5502 inst.instruction |= inst.operands[2].reg << 12;
5505 /* Insns like "foo W,X,Y,Z".
5506 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5511 inst.instruction |= inst.operands[0].reg << 5;
5512 inst.instruction |= inst.operands[1].reg << 12;
5513 inst.instruction |= inst.operands[2].reg << 16;
5514 inst.instruction |= inst.operands[3].reg;
5517 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5521 inst.instruction |= inst.operands[1].reg << 12;
5524 /* Maverick shift immediate instructions.
5525 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5526 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5531 int imm = inst.operands[2].imm;
5533 inst.instruction |= inst.operands[0].reg << 12;
5534 inst.instruction |= inst.operands[1].reg << 16;
5536 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5537 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5538 Bit 4 should be 0. */
5539 imm = (imm & 0xf) | ((imm & 0x70) << 1);
5541 inst.instruction |= imm;
5544 /* XScale instructions. Also sorted arithmetic before move. */
5546 /* Xscale multiply-accumulate (argument parse)
5549 MIAxycc acc0,Rm,Rs. */
5554 inst.instruction |= inst.operands[1].reg;
5555 inst.instruction |= inst.operands[2].reg << 12;
5558 /* Xscale move-accumulator-register (argument parse)
5560 MARcc acc0,RdLo,RdHi. */
5565 inst.instruction |= inst.operands[1].reg << 12;
5566 inst.instruction |= inst.operands[2].reg << 16;
5569 /* Xscale move-register-accumulator (argument parse)
5571 MRAcc RdLo,RdHi,acc0. */
5576 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
5577 inst.instruction |= inst.operands[0].reg << 12;
5578 inst.instruction |= inst.operands[1].reg << 16;
5581 /* Encoding functions relevant only to Thumb. */
5583 /* inst.operands[i] is a shifted-register operand; encode
5584 it into inst.instruction in the format used by Thumb32. */
5587 encode_thumb32_shifted_operand (int i)
5589 unsigned int value = inst.reloc.exp.X_add_number;
5590 unsigned int shift = inst.operands[i].shift_kind;
5592 inst.instruction |= inst.operands[i].reg;
5593 if (shift == SHIFT_RRX)
5594 inst.instruction |= SHIFT_ROR << 4;
5597 constraint (inst.reloc.exp.X_op != O_constant,
5598 _("expression too complex"));
5600 constraint (value > 32
5601 || (value == 32 && (shift == SHIFT_LSL
5602 || shift == SHIFT_ROR)),
5603 _("shift expression is too large"));
5607 else if (value == 32)
5610 inst.instruction |= shift << 4;
5611 inst.instruction |= (value & 0x1c) << 10;
5612 inst.instruction |= (value & 0x03) << 6;
5617 /* inst.operands[i] was set up by parse_address. Encode it into a
5618 Thumb32 format load or store instruction. Reject forms that cannot
5619 be used with such instructions. If is_t is true, reject forms that
5620 cannot be used with a T instruction; if is_d is true, reject forms
5621 that cannot be used with a D instruction. */
5624 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
5626 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
5628 constraint (!inst.operands[i].isreg,
5629 _("Thumb does not support the ldr =N pseudo-operation"));
5631 inst.instruction |= inst.operands[i].reg << 16;
5632 if (inst.operands[i].immisreg)
5634 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
5635 constraint (is_t || is_d, _("cannot use register index with this instruction"));
5636 constraint (inst.operands[i].negative,
5637 _("Thumb does not support negative register indexing"));
5638 constraint (inst.operands[i].postind,
5639 _("Thumb does not support register post-indexing"));
5640 constraint (inst.operands[i].writeback,
5641 _("Thumb does not support register indexing with writeback"));
5642 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
5643 _("Thumb supports only LSL in shifted register indexing"));
5645 inst.instruction |= inst.operands[1].imm;
5646 if (inst.operands[i].shifted)
5648 constraint (inst.reloc.exp.X_op != O_constant,
5649 _("expression too complex"));
5650 constraint (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 3,
5651 _("shift out of range"));
5652 inst.instruction |= inst.reloc.exp.X_op << 4;
5654 inst.reloc.type = BFD_RELOC_UNUSED;
5656 else if (inst.operands[i].preind)
5658 constraint (is_pc && inst.operands[i].writeback,
5659 _("cannot use writeback with PC-relative addressing"));
5660 constraint (is_t && inst.operands[1].writeback,
5661 _("cannot use writeback with this instruction"));
5665 inst.instruction |= 0x01000000;
5666 if (inst.operands[i].writeback)
5667 inst.instruction |= 0x00200000;
5671 inst.instruction |= 0x00000c00;
5672 if (inst.operands[i].writeback)
5673 inst.instruction |= 0x00000100;
5675 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5676 inst.reloc.pc_rel = is_pc;
5678 else if (inst.operands[i].postind)
5680 assert (inst.operands[i].writeback);
5681 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
5682 constraint (is_t, _("cannot use post-indexing with this instruction"));
5685 inst.instruction |= 0x00200000;
5687 inst.instruction |= 0x00000900;
5688 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5690 else /* unindexed - only for coprocessor */
5691 inst.error = _("instruction does not accept unindexed addressing");
5694 /* Table of Thumb instructions which exist in both 16- and 32-bit
5695 encodings (the latter only in post-V6T2 cores). The index is the
5696 value used in the insns table below. When there is more than one
5697 possible 16-bit encoding for the instruction, this table always
5698 holds variant (1). */
5699 #define T16_32_TAB \
5700 X(adc, 4140, eb400000), \
5701 X(adcs, 4140, eb500000), \
5702 X(add, 1c00, eb000000), \
5703 X(adds, 1c00, eb100000), \
5704 X(and, 4000, ea000000), \
5705 X(ands, 4000, ea100000), \
5706 X(asr, 1000, fa40f000), \
5707 X(asrs, 1000, fa50f000), \
5708 X(bic, 4380, ea200000), \
5709 X(bics, 4380, ea300000), \
5710 X(cmn, 42c0, eb100f00), \
5711 X(cmp, 2800, ebb00f00), \
5712 X(cpsie, b660, f3af8400), \
5713 X(cpsid, b670, f3af8600), \
5714 X(cpy, 4600, ea4f0000), \
5715 X(eor, 4040, ea800000), \
5716 X(eors, 4040, ea900000), \
5717 X(ldmia, c800, e8900000), \
5718 X(ldr, 6800, f8500000), \
5719 X(ldrb, 7800, f8100000), \
5720 X(ldrh, 8800, f8300000), \
5721 X(ldrsb, 5600, f9100000), \
5722 X(ldrsh, 5e00, f9300000), \
5723 X(lsl, 0000, fa00f000), \
5724 X(lsls, 0000, fa10f000), \
5725 X(lsr, 0800, fa20f000), \
5726 X(lsrs, 0800, fa30f000), \
5727 X(mov, 2000, ea4f0000), \
5728 X(movs, 2000, ea5f0000), \
5729 X(mul, 4340, fb00f000), \
5730 X(muls, 4340, ffffffff), /* no 32b muls */ \
5731 X(mvn, 43c0, ea6f0000), \
5732 X(mvns, 43c0, ea7f0000), \
5733 X(neg, 4240, f1c00000), /* rsb #0 */ \
5734 X(negs, 4240, f1d00000), /* rsbs #0 */ \
5735 X(orr, 4300, ea400000), \
5736 X(orrs, 4300, ea500000), \
5737 X(pop, bc00, e8ad0000), /* ldmia sp!,... */ \
5738 X(push, b400, e8bd0000), /* stmia sp!,... */ \
5739 X(rev, ba00, fa90f080), \
5740 X(rev16, ba40, fa90f090), \
5741 X(revsh, bac0, fa90f0b0), \
5742 X(ror, 41c0, fa60f000), \
5743 X(rors, 41c0, fa70f000), \
5744 X(sbc, 4180, eb600000), \
5745 X(sbcs, 4180, eb700000), \
5746 X(stmia, c000, e8800000), \
5747 X(str, 6000, f8400000), \
5748 X(strb, 7000, f8000000), \
5749 X(strh, 8000, f8200000), \
5750 X(sub, 1e00, eba00000), \
5751 X(subs, 1e00, ebb00000), \
5752 X(sxtb, b240, fa4ff080), \
5753 X(sxth, b200, fa0ff080), \
5754 X(tst, 4200, ea100f00), \
5755 X(uxtb, b2c0, fa5ff080), \
5756 X(uxth, b280, fa1ff080), \
5757 X(nop, bf00, f3af8000), \
5758 X(yield, bf10, f3af8001), \
5759 X(wfe, bf20, f3af8002), \
5760 X(wfi, bf30, f3af8003), \
5761 X(sev, bf40, f3af9004), /* typo, 8004? */
5763 /* To catch errors in encoding functions, the codes are all offset by
5764 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
5765 as 16-bit instructions. */
5766 #define X(a,b,c) T_MNEM_##a
5767 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
5770 #define X(a,b,c) 0x##b
5771 static const unsigned short thumb_op16[] = { T16_32_TAB };
5772 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
5775 #define X(a,b,c) 0x##c
5776 static const unsigned int thumb_op32[] = { T16_32_TAB };
5777 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
5778 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
5782 /* Thumb instruction encoders, in alphabetical order. */
5784 /* Parse an add or subtract instruction. We get here with inst.instruction
5785 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
5792 Rd = inst.operands[0].reg;
5793 Rs = (inst.operands[1].present
5794 ? inst.operands[1].reg /* Rd, Rs, foo */
5795 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
5799 if (!inst.operands[2].isreg)
5801 /* For an immediate, we always generate a 32-bit opcode;
5802 section relaxation will shrink it later if possible. */
5803 inst.instruction = THUMB_OP32 (inst.instruction);
5804 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
5805 inst.instruction |= inst.operands[0].reg << 8;
5806 inst.instruction |= inst.operands[1].reg << 16;
5807 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
5811 Rn = inst.operands[2].reg;
5812 /* See if we can do this with a 16-bit instruction. */
5813 if (!inst.operands[2].shifted && inst.size_req != 4)
5815 if (Rd <= 7 && Rn <= 7 && Rn <= 7
5816 && (inst.instruction == T_MNEM_adds
5817 || inst.instruction == T_MNEM_subs))
5819 inst.instruction = (inst.instruction == T_MNEM_adds
5822 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5826 if (inst.instruction == T_MNEM_add)
5830 inst.instruction = T_OPCODE_ADD_HI;
5831 inst.instruction |= (Rd & 8) << 4;
5832 inst.instruction |= (Rd & 7);
5833 inst.instruction |= Rn << 3;
5836 /* ... because addition is commutative! */
5839 inst.instruction = T_OPCODE_ADD_HI;
5840 inst.instruction |= (Rd & 8) << 4;
5841 inst.instruction |= (Rd & 7);
5842 inst.instruction |= Rs << 3;
5847 /* If we get here, it can't be done in 16 bits. */
5848 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
5849 _("shift must be constant"));
5850 inst.instruction = THUMB_OP32 (inst.instruction);
5851 inst.instruction |= Rd << 8;
5852 inst.instruction |= Rs << 16;
5853 encode_thumb32_shifted_operand (2);
5858 constraint (inst.instruction == T_MNEM_adds
5859 || inst.instruction == T_MNEM_subs,
5862 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
5864 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
5865 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
5868 inst.instruction = (inst.instruction == T_MNEM_add
5870 inst.instruction |= (Rd << 4) | Rs;
5871 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5875 Rn = inst.operands[2].reg;
5876 constraint (inst.operands[2].shifted, _("unshifted register required"));
5878 /* We now have Rd, Rs, and Rn set to registers. */
5879 if (Rd > 7 || Rs > 7 || Rn > 7)
5881 /* Can't do this for SUB. */
5882 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
5883 inst.instruction = T_OPCODE_ADD_HI;
5884 inst.instruction |= (Rd & 8) << 4;
5885 inst.instruction |= (Rd & 7);
5887 inst.instruction |= Rn << 3;
5889 inst.instruction |= Rs << 3;
5891 constraint (1, _("dest must overlap one source register"));
5895 inst.instruction = (inst.instruction == T_MNEM_add
5896 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
5897 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5905 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5906 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
5907 inst.reloc.pc_rel = 1;
5909 inst.instruction |= inst.operands[0].reg << 4;
5912 /* Arithmetic instructions for which there is just one 16-bit
5913 instruction encoding, and it allows only two low registers.
5914 For maximal compatibility with ARM syntax, we allow three register
5915 operands even when Thumb-32 instructions are not available, as long
5916 as the first two are identical. For instance, both "sbc r0,r1" and
5917 "sbc r0,r0,r1" are allowed. */
5923 Rd = inst.operands[0].reg;
5924 Rs = (inst.operands[1].present
5925 ? inst.operands[1].reg /* Rd, Rs, foo */
5926 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
5927 Rn = inst.operands[2].reg;
5931 if (!inst.operands[2].isreg)
5933 /* For an immediate, we always generate a 32-bit opcode;
5934 section relaxation will shrink it later if possible. */
5935 inst.instruction = THUMB_OP32 (inst.instruction);
5936 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
5937 inst.instruction |= Rd << 8;
5938 inst.instruction |= Rs << 16;
5939 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
5943 /* See if we can do this with a 16-bit instruction. */
5944 if (THUMB_SETS_FLAGS (inst.instruction)
5945 && !inst.operands[2].shifted
5946 && inst.size_req != 4
5949 inst.instruction = THUMB_OP16 (inst.instruction);
5950 inst.instruction |= Rd;
5951 inst.instruction |= Rn << 3;
5955 /* If we get here, it can't be done in 16 bits. */
5956 constraint (inst.operands[2].shifted
5957 && inst.operands[2].immisreg,
5958 _("shift must be constant"));
5959 inst.instruction = THUMB_OP32 (inst.instruction);
5960 inst.instruction |= Rd << 8;
5961 inst.instruction |= Rs << 16;
5962 encode_thumb32_shifted_operand (2);
5967 /* On its face this is a lie - the instruction does set the
5968 flags. However, the only supported mnemonic in this mode
5970 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
5972 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
5973 _("unshifted register required"));
5974 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
5975 constraint (Rd != Rs,
5976 _("dest and source1 must be the same register"));
5978 inst.instruction = THUMB_OP16 (inst.instruction);
5979 inst.instruction |= Rd;
5980 inst.instruction |= Rn << 3;
5984 /* Similarly, but for instructions where the arithmetic operation is
5985 commutative, so we can allow either of them to be different from
5986 the destination operand in a 16-bit instruction. For instance, all
5987 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
5994 Rd = inst.operands[0].reg;
5995 Rs = (inst.operands[1].present
5996 ? inst.operands[1].reg /* Rd, Rs, foo */
5997 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
5998 Rn = inst.operands[2].reg;
6002 if (!inst.operands[2].isreg)
6004 /* For an immediate, we always generate a 32-bit opcode;
6005 section relaxation will shrink it later if possible. */
6006 inst.instruction = THUMB_OP32 (inst.instruction);
6007 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6008 inst.instruction |= Rd << 8;
6009 inst.instruction |= Rs << 16;
6010 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6014 /* See if we can do this with a 16-bit instruction. */
6015 if (THUMB_SETS_FLAGS (inst.instruction)
6016 && !inst.operands[2].shifted
6017 && inst.size_req != 4)
6021 inst.instruction = THUMB_OP16 (inst.instruction);
6022 inst.instruction |= Rd;
6023 inst.instruction |= Rn << 3;
6028 inst.instruction = THUMB_OP16 (inst.instruction);
6029 inst.instruction |= Rd;
6030 inst.instruction |= Rs << 3;
6035 /* If we get here, it can't be done in 16 bits. */
6036 constraint (inst.operands[2].shifted
6037 && inst.operands[2].immisreg,
6038 _("shift must be constant"));
6039 inst.instruction = THUMB_OP32 (inst.instruction);
6040 inst.instruction |= Rd << 8;
6041 inst.instruction |= Rs << 16;
6042 encode_thumb32_shifted_operand (2);
6047 /* On its face this is a lie - the instruction does set the
6048 flags. However, the only supported mnemonic in this mode
6050 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6052 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6053 _("unshifted register required"));
6054 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6056 inst.instruction = THUMB_OP16 (inst.instruction);
6057 inst.instruction |= Rd;
6060 inst.instruction |= Rn << 3;
6062 inst.instruction |= Rs << 3;
6064 constraint (1, _("dest must overlap one source register"));
6071 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6072 constraint (msb > 32, _("bit-field extends past end of register"));
6073 /* The instruction encoding stores the LSB and MSB,
6074 not the LSB and width. */
6075 inst.instruction |= inst.operands[0].reg << 8;
6076 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
6077 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
6078 inst.instruction |= msb - 1;
6086 /* #0 in second position is alternative syntax for bfc, which is
6087 the same instruction but with REG_PC in the Rm field. */
6088 if (!inst.operands[1].isreg)
6089 inst.operands[1].reg = REG_PC;
6091 msb = inst.operands[2].imm + inst.operands[3].imm;
6092 constraint (msb > 32, _("bit-field extends past end of register"));
6093 /* The instruction encoding stores the LSB and MSB,
6094 not the LSB and width. */
6095 inst.instruction |= inst.operands[0].reg << 8;
6096 inst.instruction |= inst.operands[1].reg << 16;
6097 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6098 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6099 inst.instruction |= msb - 1;
6105 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6106 _("bit-field extends past end of register"));
6107 inst.instruction |= inst.operands[0].reg << 8;
6108 inst.instruction |= inst.operands[1].reg << 16;
6109 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6110 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6111 inst.instruction |= inst.operands[3].imm - 1;
6114 /* ARM V5 Thumb BLX (argument parse)
6115 BLX <target_addr> which is BLX(1)
6116 BLX <Rm> which is BLX(2)
6117 Unfortunately, there are two different opcodes for this mnemonic.
6118 So, the insns[].value is not used, and the code here zaps values
6119 into inst.instruction.
6121 ??? How to take advantage of the additional two bits of displacement
6122 available in Thumb32 mode? Need new relocation? */
6127 if (inst.operands[0].isreg)
6128 /* We have a register, so this is BLX(2). */
6129 inst.instruction |= inst.operands[0].reg << 3;
6132 /* No register. This must be BLX(1). */
6133 inst.instruction = 0xf7ffeffe;
6134 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
6135 inst.reloc.pc_rel = 1;
6142 if (unified_syntax && inst.size_req != 2)
6144 if (inst.cond == COND_ALWAYS)
6146 inst.instruction = 0xf7ffbffe;
6147 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
6151 assert (inst.cond != 0xF);
6152 inst.instruction = (inst.cond << 22) | 0xf43faffe;
6153 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
6158 if (inst.cond == COND_ALWAYS)
6159 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6162 inst.instruction = 0xd0fe | (inst.cond << 8);
6163 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6167 inst.reloc.pc_rel = 1;
6173 if (inst.operands[0].present)
6175 constraint (inst.operands[0].imm > 255,
6176 _("immediate value out of range"));
6177 inst.instruction |= inst.operands[0].imm;
6182 do_t_branch23 (void)
6184 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6185 inst.reloc.pc_rel = 1;
6187 /* If the destination of the branch is a defined symbol which does not have
6188 the THUMB_FUNC attribute, then we must be calling a function which has
6189 the (interfacearm) attribute. We look for the Thumb entry point to that
6190 function and change the branch to refer to that function instead. */
6191 if ( inst.reloc.exp.X_op == O_symbol
6192 && inst.reloc.exp.X_add_symbol != NULL
6193 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6194 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6195 inst.reloc.exp.X_add_symbol =
6196 find_real_start (inst.reloc.exp.X_add_symbol);
6202 inst.instruction |= inst.operands[0].reg << 3;
6203 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6204 should cause the alignment to be checked once it is known. This is
6205 because BX PC only works if the instruction is word aligned. */
6211 if (inst.operands[0].reg == REG_PC)
6212 as_tsktsk (_("use of r15 in bxj is not really useful"));
6214 inst.instruction |= inst.operands[0].reg << 16;
6220 inst.instruction |= inst.operands[0].reg << 8;
6221 inst.instruction |= inst.operands[1].reg << 16;
6222 inst.instruction |= inst.operands[1].reg;
6229 && (inst.operands[1].present || inst.size_req == 4))
6231 unsigned int imod = (inst.instruction & 0x0030) >> 4;
6232 inst.instruction = 0xf3af8000;
6233 inst.instruction |= imod << 9;
6234 inst.instruction |= inst.operands[0].imm << 5;
6235 if (inst.operands[1].present)
6236 inst.instruction |= 0x100 | inst.operands[1].imm;
6240 constraint (inst.operands[1].present,
6241 _("Thumb does not support the 2-argument "
6242 "form of this instruction"));
6243 inst.instruction |= inst.operands[0].imm;
6247 /* THUMB CPY instruction (argument parse). */
6252 if (inst.size_req == 4)
6254 inst.instruction = THUMB_OP32 (T_MNEM_mov);
6255 inst.instruction |= inst.operands[0].reg << 8;
6256 inst.instruction |= inst.operands[1].reg;
6260 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6261 inst.instruction |= (inst.operands[0].reg & 0x7);
6262 inst.instruction |= inst.operands[1].reg << 3;
6269 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6270 inst.instruction |= inst.operands[0].reg;
6271 inst.reloc.pc_rel = 1;
6272 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
6278 if (unified_syntax && inst.size_req == 4)
6279 inst.instruction = THUMB_OP32 (inst.instruction);
6281 inst.instruction = THUMB_OP16 (inst.instruction);
6287 unsigned int cond = inst.operands[0].imm;
6288 if ((cond & 0x1) == 0x0)
6290 unsigned int mask = inst.instruction & 0x000f;
6291 inst.instruction &= 0xfff0;
6293 if ((mask & 0x7) == 0)
6294 /* no conversion needed */;
6295 else if ((mask & 0x3) == 0)
6296 mask = (~(mask & 0x8) & 0x8) | 0x4;
6297 else if ((mask & 1) == 0)
6298 mask = (~(mask & 0xC) & 0xC) | 0x2;
6300 mask = (~(mask & 0xE) & 0xE) | 0x1;
6302 inst.instruction |= (mask & 0xF);
6305 inst.instruction |= cond << 4;
6311 /* This really doesn't seem worth it. */
6312 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6313 _("expression too complex"));
6314 constraint (inst.operands[1].writeback,
6315 _("Thumb load/store multiple does not support {reglist}^"));
6319 /* See if we can use a 16-bit instruction. */
6320 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
6321 && inst.size_req != 4
6322 && inst.operands[0].reg <= 7
6323 && !(inst.operands[1].imm & ~0xff)
6324 && (inst.instruction == T_MNEM_stmia
6325 ? inst.operands[0].writeback
6326 : (inst.operands[0].writeback
6327 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
6329 if (inst.instruction == T_MNEM_stmia
6330 && (inst.operands[1].imm & (1 << inst.operands[0].reg))
6331 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6332 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6333 inst.operands[0].reg);
6335 inst.instruction = THUMB_OP16 (inst.instruction);
6336 inst.instruction |= inst.operands[0].reg << 8;
6337 inst.instruction |= inst.operands[1].imm;
6341 if (inst.operands[1].imm & (1 << 13))
6342 as_warn (_("SP should not be in register list"));
6343 if (inst.instruction == T_MNEM_stmia)
6345 if (inst.operands[1].imm & (1 << 15))
6346 as_warn (_("PC should not be in register list"));
6347 if (inst.operands[1].imm & (1 << inst.operands[0].reg))
6348 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6349 inst.operands[0].reg);
6353 if (inst.operands[1].imm & (1 << 14)
6354 && inst.operands[1].imm & (1 << 15))
6355 as_warn (_("LR and PC should not both be in register list"));
6356 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6357 && inst.operands[0].writeback)
6358 as_warn (_("base register should not be in register list "
6359 "when written back"));
6361 if (inst.instruction < 0xffff)
6362 inst.instruction = THUMB_OP32 (inst.instruction);
6363 inst.instruction |= inst.operands[0].reg << 16;
6364 inst.instruction |= inst.operands[1].imm;
6365 if (inst.operands[0].writeback)
6366 inst.instruction |= WRITE_BACK;
6371 constraint (inst.operands[0].reg > 7
6372 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
6373 if (inst.instruction == T_MNEM_stmia)
6375 if (!inst.operands[0].writeback)
6376 as_warn (_("this instruction will write back the base register"));
6377 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6378 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6379 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6380 inst.operands[0].reg);
6384 if (!inst.operands[0].writeback
6385 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
6386 as_warn (_("this instruction will write back the base register"));
6387 else if (inst.operands[0].writeback
6388 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
6389 as_warn (_("this instruction will not write back the base register"));
6392 inst.instruction = THUMB_OP16 (inst.instruction);
6393 inst.instruction |= inst.operands[0].reg << 8;
6394 inst.instruction |= inst.operands[1].imm;
6401 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6402 || inst.operands[1].postind || inst.operands[1].writeback
6403 || inst.operands[1].immisreg || inst.operands[1].shifted
6404 || inst.operands[1].negative,
6405 _("instruction does not accept this addressing mode"));
6407 inst.instruction |= inst.operands[0].reg << 12;
6408 inst.instruction |= inst.operands[1].reg << 16;
6409 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
6415 if (!inst.operands[1].present)
6417 constraint (inst.operands[0].reg == REG_LR,
6418 _("r14 not allowed as first register "
6419 "when second register is omitted"));
6420 inst.operands[1].reg = inst.operands[0].reg + 1;
6422 constraint (inst.operands[0].reg == inst.operands[1].reg,
6425 inst.instruction |= inst.operands[0].reg << 12;
6426 inst.instruction |= inst.operands[1].reg << 8;
6427 inst.instruction |= inst.operands[2].reg << 16;
6435 /* Generation of 16-bit instructions for anything other than
6436 Rd, [Rn, Ri] is deferred to section relaxation time. */
6437 if (inst.operands[1].isreg && inst.operands[1].immisreg
6438 && !inst.operands[1].shifted && !inst.operands[1].postind
6439 && !inst.operands[1].negative && inst.operands[0].reg <= 7
6440 && inst.operands[1].reg <= 7 && inst.operands[1].imm <= 7
6441 && inst.instruction <= 0xffff)
6443 inst.instruction = THUMB_OP16 (inst.instruction);
6447 inst.instruction = THUMB_OP32 (inst.instruction);
6448 inst.instruction |= inst.operands[0].reg << 12;
6449 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
6453 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6455 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
6457 /* Only [Rn,Rm] is acceptable. */
6458 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
6459 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
6460 || inst.operands[1].postind || inst.operands[1].shifted
6461 || inst.operands[1].negative,
6462 _("Thumb does not support this addressing mode"));
6463 inst.instruction = THUMB_OP16 (inst.instruction);
6467 inst.instruction = THUMB_OP16 (inst.instruction);
6468 if (!inst.operands[1].isreg)
6469 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
6472 constraint (!inst.operands[1].preind
6473 || inst.operands[1].shifted
6474 || inst.operands[1].writeback,
6475 _("Thumb does not support this addressing mode"));
6476 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
6478 constraint (inst.instruction & 0x0600,
6479 _("byte or halfword not valid for base register"));
6480 constraint (inst.operands[1].reg == REG_PC
6481 && !(inst.instruction & THUMB_LOAD_BIT),
6482 _("r15 based store not allowed"));
6483 constraint (inst.operands[1].immisreg,
6484 _("invalid base register for register offset"));
6486 if (inst.operands[1].reg == REG_PC)
6487 inst.instruction = T_OPCODE_LDR_PC;
6488 else if (inst.instruction & THUMB_LOAD_BIT)
6489 inst.instruction = T_OPCODE_LDR_SP;
6491 inst.instruction = T_OPCODE_STR_SP;
6493 inst.instruction |= inst.operands[0].reg << 8;
6494 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6498 constraint (inst.operands[1].reg > 7, BAD_HIREG);
6499 if (!inst.operands[1].immisreg)
6501 /* Immediate offset. */
6502 inst.instruction |= inst.operands[0].reg;
6503 inst.instruction |= inst.operands[1].reg << 3;
6504 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6508 /* Register offset. */
6509 constraint (inst.operands[1].imm > 7, BAD_HIREG);
6510 constraint (inst.operands[1].negative,
6511 _("Thumb does not support this addressing mode"));
6514 switch (inst.instruction)
6516 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
6517 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
6518 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
6519 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
6520 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
6521 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
6522 case 0x5600 /* ldrsb */:
6523 case 0x5e00 /* ldrsh */: break;
6527 inst.instruction |= inst.operands[0].reg;
6528 inst.instruction |= inst.operands[1].reg << 3;
6529 inst.instruction |= inst.operands[1].imm << 6;
6535 if (!inst.operands[1].present)
6537 inst.operands[1].reg = inst.operands[0].reg + 1;
6538 constraint (inst.operands[0].reg == REG_LR,
6539 _("r14 not allowed here"));
6541 inst.instruction |= inst.operands[0].reg << 12;
6542 inst.instruction |= inst.operands[1].reg << 8;
6543 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
6550 inst.instruction |= inst.operands[0].reg << 12;
6551 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
6557 inst.instruction |= inst.operands[0].reg << 8;
6558 inst.instruction |= inst.operands[1].reg << 16;
6559 inst.instruction |= inst.operands[2].reg;
6560 inst.instruction |= inst.operands[3].reg << 12;
6566 inst.instruction |= inst.operands[0].reg << 12;
6567 inst.instruction |= inst.operands[1].reg << 8;
6568 inst.instruction |= inst.operands[2].reg << 16;
6569 inst.instruction |= inst.operands[3].reg;
6577 int r0off = (inst.instruction == T_MNEM_mov
6578 || inst.instruction == T_MNEM_movs) ? 8 : 16;
6579 if (!inst.operands[1].isreg)
6581 /* For an immediate, we always generate a 32-bit opcode;
6582 section relaxation will shrink it later if possible. */
6583 inst.instruction = THUMB_OP32 (inst.instruction);
6584 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6585 inst.instruction |= inst.operands[0].reg << r0off;
6586 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6588 else if (inst.size_req == 4
6589 || inst.operands[1].shifted
6590 || (inst.instruction == T_MNEM_movs
6591 && (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)))
6593 inst.instruction = THUMB_OP32 (inst.instruction);
6594 inst.instruction |= inst.operands[0].reg << r0off;
6595 encode_thumb32_shifted_operand (1);
6598 switch (inst.instruction)
6601 inst.instruction = T_OPCODE_MOV_HR;
6602 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6603 inst.instruction |= (inst.operands[0].reg & 0x7);
6604 inst.instruction |= inst.operands[1].reg << 3;
6608 /* We know we have low registers at this point.
6609 Generate ADD Rd, Rs, #0. */
6610 inst.instruction = T_OPCODE_ADD_I3;
6611 inst.instruction |= inst.operands[0].reg;
6612 inst.instruction |= inst.operands[1].reg << 3;
6616 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7)
6618 inst.instruction = T_OPCODE_CMP_LR;
6619 inst.instruction |= inst.operands[0].reg;
6620 inst.instruction |= inst.operands[1].reg << 3;
6624 inst.instruction = T_OPCODE_CMP_HR;
6625 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6626 inst.instruction |= (inst.operands[0].reg & 0x7);
6627 inst.instruction |= inst.operands[1].reg << 3;
6634 inst.instruction = THUMB_OP16 (inst.instruction);
6635 if (inst.operands[1].isreg)
6637 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
6639 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
6640 since a MOV instruction produces unpredictable results. */
6641 if (inst.instruction == T_OPCODE_MOV_I8)
6642 inst.instruction = T_OPCODE_ADD_I3;
6644 inst.instruction = T_OPCODE_CMP_LR;
6646 inst.instruction |= inst.operands[0].reg;
6647 inst.instruction |= inst.operands[1].reg << 3;
6651 if (inst.instruction == T_OPCODE_MOV_I8)
6652 inst.instruction = T_OPCODE_MOV_HR;
6654 inst.instruction = T_OPCODE_CMP_HR;
6660 constraint (inst.operands[0].reg > 7,
6661 _("only lo regs allowed with immediate"));
6662 inst.instruction |= inst.operands[0].reg << 8;
6663 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
6670 inst.instruction |= inst.operands[0].reg << 8;
6671 inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
6672 inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
6673 inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
6674 inst.instruction |= (inst.operands[1].imm & 0x00ff);
6682 int r0off = (inst.instruction == T_MNEM_mvn
6683 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
6684 if (!inst.operands[1].isreg)
6686 /* For an immediate, we always generate a 32-bit opcode;
6687 section relaxation will shrink it later if possible. */
6688 if (inst.instruction < 0xffff)
6689 inst.instruction = THUMB_OP32 (inst.instruction);
6690 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6691 inst.instruction |= inst.operands[0].reg << r0off;
6692 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6696 /* See if we can do this with a 16-bit instruction. */
6697 if (inst.instruction < 0xffff
6698 && THUMB_SETS_FLAGS (inst.instruction)
6699 && !inst.operands[1].shifted
6700 && inst.operands[0].reg <= 7
6701 && inst.operands[1].reg <= 7
6702 && inst.size_req != 4)
6704 inst.instruction = THUMB_OP16 (inst.instruction);
6705 inst.instruction |= inst.operands[0].reg;
6706 inst.instruction |= inst.operands[1].reg << 3;
6710 constraint (inst.operands[1].shifted
6711 && inst.operands[1].immisreg,
6712 _("shift must be constant"));
6713 if (inst.instruction < 0xffff)
6714 inst.instruction = THUMB_OP32 (inst.instruction);
6715 inst.instruction |= inst.operands[0].reg << r0off;
6716 encode_thumb32_shifted_operand (1);
6722 constraint (inst.instruction > 0xffff
6723 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
6724 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
6725 _("unshifted register required"));
6726 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6729 inst.instruction = THUMB_OP16 (inst.instruction);
6730 inst.instruction |= inst.operands[0].reg;
6731 inst.instruction |= inst.operands[1].reg << 3;
6738 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
6739 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
6741 _("'CPSR' or 'SPSR' expected"));
6742 inst.instruction |= inst.operands[0].reg << 8;
6743 inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2;
6749 constraint (!inst.operands[1].isreg,
6750 _("Thumb encoding does not support an immediate here"));
6751 inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2;
6752 inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8;
6753 inst.instruction |= inst.operands[1].reg << 16;
6759 if (!inst.operands[2].present)
6760 inst.operands[2].reg = inst.operands[0].reg;
6762 /* There is no 32-bit MULS and no 16-bit MUL. */
6763 if (unified_syntax && inst.instruction == T_MNEM_mul)
6765 inst.instruction = THUMB_OP32 (inst.instruction);
6766 inst.instruction |= inst.operands[0].reg << 8;
6767 inst.instruction |= inst.operands[1].reg << 16;
6768 inst.instruction |= inst.operands[2].reg << 0;
6772 constraint (!unified_syntax
6773 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
6774 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6777 inst.instruction = THUMB_OP16 (inst.instruction);
6778 inst.instruction |= inst.operands[0].reg;
6780 if (inst.operands[0].reg == inst.operands[1].reg)
6781 inst.instruction |= inst.operands[2].reg << 3;
6782 else if (inst.operands[0].reg == inst.operands[2].reg)
6783 inst.instruction |= inst.operands[1].reg << 3;
6785 constraint (1, _("dest must overlap one source register"));
6792 inst.instruction |= inst.operands[0].reg << 12;
6793 inst.instruction |= inst.operands[1].reg << 8;
6794 inst.instruction |= inst.operands[2].reg << 16;
6795 inst.instruction |= inst.operands[3].reg;
6797 if (inst.operands[0].reg == inst.operands[1].reg)
6798 as_tsktsk (_("rdhi and rdlo must be different"));
6806 if (inst.size_req == 4 || inst.operands[0].imm > 15)
6808 inst.instruction = THUMB_OP32 (inst.instruction);
6809 inst.instruction |= inst.operands[0].imm;
6813 inst.instruction = THUMB_OP16 (inst.instruction);
6814 inst.instruction |= inst.operands[0].imm << 4;
6819 constraint (inst.operands[0].present,
6820 _("Thumb does not support NOP with hints"));
6821 inst.instruction = 0x46c0;
6830 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7
6831 || !THUMB_SETS_FLAGS (inst.instruction)
6832 || inst.size_req == 4)
6834 inst.instruction = THUMB_OP32 (inst.instruction);
6835 inst.instruction |= inst.operands[0].reg << 8;
6836 inst.instruction |= inst.operands[1].reg << 16;
6840 inst.instruction = THUMB_OP16 (inst.instruction);
6841 inst.instruction |= inst.operands[0].reg;
6842 inst.instruction |= inst.operands[1].reg << 3;
6847 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6849 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6851 inst.instruction = THUMB_OP16 (inst.instruction);
6852 inst.instruction |= inst.operands[0].reg;
6853 inst.instruction |= inst.operands[1].reg << 3;
6860 inst.instruction |= inst.operands[0].reg << 8;
6861 inst.instruction |= inst.operands[1].reg << 16;
6862 inst.instruction |= inst.operands[2].reg;
6863 if (inst.operands[3].present)
6865 unsigned int val = inst.reloc.exp.X_add_number;
6866 constraint (inst.reloc.exp.X_op != O_constant,
6867 _("expression too complex"));
6868 inst.instruction |= (val & 0x1c) << 10;
6869 inst.instruction |= (val & 0x03) << 6;
6876 if (!inst.operands[3].present)
6877 inst.instruction &= ~0x00000020;
6884 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
6888 do_t_push_pop (void)
6890 constraint (inst.operands[0].writeback,
6891 _("push/pop do not support {reglist}^"));
6892 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6893 _("expression too complex"));
6895 if ((inst.operands[0].imm & ~0xff) == 0)
6896 inst.instruction = THUMB_OP16 (inst.instruction);
6897 else if ((inst.instruction == T_MNEM_push
6898 && (inst.operands[0].imm & ~0xff) == 1 << REG_LR)
6899 || (inst.instruction == T_MNEM_pop
6900 && (inst.operands[0].imm & ~0xff) == 1 << REG_PC))
6902 inst.instruction = THUMB_OP16 (inst.instruction);
6903 inst.instruction |= THUMB_PP_PC_LR;
6904 inst.operands[0].imm &= 0xff;
6906 else if (unified_syntax)
6908 if (inst.operands[1].imm & (1 << 13))
6909 as_warn (_("SP should not be in register list"));
6910 if (inst.instruction == T_MNEM_push)
6912 if (inst.operands[1].imm & (1 << 15))
6913 as_warn (_("PC should not be in register list"));
6917 if (inst.operands[1].imm & (1 << 14)
6918 && inst.operands[1].imm & (1 << 15))
6919 as_warn (_("LR and PC should not both be in register list"));
6922 inst.instruction = THUMB_OP32 (inst.instruction);
6926 inst.error = _("invalid register list to push/pop instruction");
6930 inst.instruction |= inst.operands[0].imm;
6936 inst.instruction |= inst.operands[0].reg << 8;
6937 inst.instruction |= inst.operands[1].reg << 16;
6943 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
6944 && inst.size_req != 4)
6946 inst.instruction = THUMB_OP16 (inst.instruction);
6947 inst.instruction |= inst.operands[0].reg;
6948 inst.instruction |= inst.operands[1].reg << 3;
6950 else if (unified_syntax)
6952 inst.instruction = THUMB_OP32 (inst.instruction);
6953 inst.instruction |= inst.operands[0].reg << 8;
6954 inst.instruction |= inst.operands[1].reg << 16;
6955 inst.instruction |= inst.operands[1].reg;
6958 inst.error = BAD_HIREG;
6966 Rd = inst.operands[0].reg;
6967 Rs = (inst.operands[1].present
6968 ? inst.operands[1].reg /* Rd, Rs, foo */
6969 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6971 inst.instruction |= Rd << 8;
6972 inst.instruction |= Rs << 16;
6973 if (!inst.operands[2].isreg)
6975 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6976 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6979 encode_thumb32_shifted_operand (2);
6985 if (inst.operands[0].imm)
6986 inst.instruction |= 0x8;
6992 if (!inst.operands[1].present)
6993 inst.operands[1].reg = inst.operands[0].reg;
6997 if (inst.operands[0].reg > 7
6998 || inst.operands[1].reg > 7
6999 || !THUMB_SETS_FLAGS (inst.instruction)
7000 || (!inst.operands[2].isreg && inst.instruction == T_MNEM_rors)
7001 || (inst.operands[2].isreg && inst.operands[1].reg != inst.operands[0].reg)
7002 || inst.size_req == 4)
7004 if (inst.operands[2].isreg)
7006 inst.instruction = THUMB_OP32 (inst.instruction);
7007 inst.instruction |= inst.operands[0].reg << 8;
7008 inst.instruction |= inst.operands[1].reg << 16;
7009 inst.instruction |= inst.operands[2].reg;
7013 inst.operands[1].shifted = 1;
7014 switch (inst.instruction)
7017 case T_MNEM_asrs: inst.operands[1].shift_kind = SHIFT_ASR; break;
7019 case T_MNEM_lsls: inst.operands[1].shift_kind = SHIFT_LSL; break;
7021 case T_MNEM_lsrs: inst.operands[1].shift_kind = SHIFT_LSR; break;
7023 case T_MNEM_rors: inst.operands[1].shift_kind = SHIFT_ROR; break;
7027 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
7028 ? T_MNEM_movs : T_MNEM_mov);
7029 inst.instruction |= inst.operands[0].reg << 8;
7030 encode_thumb32_shifted_operand (1);
7031 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7032 inst.reloc.type = BFD_RELOC_UNUSED;
7037 if (inst.operands[2].isreg)
7039 switch (inst.instruction)
7041 case T_MNEM_asrs: inst.instruction = T_OPCODE_ASR_R; break;
7042 case T_MNEM_lsls: inst.instruction = T_OPCODE_LSL_R; break;
7043 case T_MNEM_lsrs: inst.instruction = T_OPCODE_LSR_R; break;
7044 case T_MNEM_rors: inst.instruction = T_OPCODE_ROR_R; break;
7048 inst.instruction |= inst.operands[0].reg;
7049 inst.instruction |= inst.operands[2].reg << 3;
7053 switch (inst.instruction)
7055 case T_MNEM_asrs: inst.instruction = T_OPCODE_ASR_I; break;
7056 case T_MNEM_lsls: inst.instruction = T_OPCODE_LSL_I; break;
7057 case T_MNEM_lsrs: inst.instruction = T_OPCODE_LSR_I; break;
7060 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7061 inst.instruction |= inst.operands[0].reg;
7062 inst.instruction |= inst.operands[1].reg << 3;
7068 constraint (inst.operands[0].reg > 7
7069 || inst.operands[1].reg > 7, BAD_HIREG);
7070 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7072 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
7074 constraint (inst.operands[2].reg > 7, BAD_HIREG);
7075 constraint (inst.operands[0].reg != inst.operands[1].reg,
7076 _("source1 and dest must be same register"));
7078 switch (inst.instruction)
7080 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
7081 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
7082 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
7083 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
7087 inst.instruction |= inst.operands[0].reg;
7088 inst.instruction |= inst.operands[2].reg << 3;
7092 switch (inst.instruction)
7094 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
7095 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
7096 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
7097 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
7100 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7101 inst.instruction |= inst.operands[0].reg;
7102 inst.instruction |= inst.operands[1].reg << 3;
7110 inst.instruction |= inst.operands[0].reg << 8;
7111 inst.instruction |= inst.operands[1].reg << 16;
7112 inst.instruction |= inst.operands[2].reg;
7118 unsigned int value = inst.reloc.exp.X_add_number;
7119 constraint (inst.reloc.exp.X_op != O_constant,
7120 _("expression too complex"));
7121 inst.reloc.type = BFD_RELOC_UNUSED;
7122 inst.instruction |= (value & 0xf000) >> 12;
7123 inst.instruction |= (value & 0x0ff0);
7124 inst.instruction |= (value & 0x000f) << 16;
7130 inst.instruction |= inst.operands[0].reg << 8;
7131 inst.instruction |= inst.operands[1].imm - 1;
7132 inst.instruction |= inst.operands[2].reg << 16;
7134 if (inst.operands[3].present)
7136 constraint (inst.reloc.exp.X_op != O_constant,
7137 _("expression too complex"));
7139 if (inst.reloc.exp.X_add_number != 0)
7141 if (inst.operands[3].shift_kind == SHIFT_ASR)
7142 inst.instruction |= 0x00200000; /* sh bit */
7143 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7144 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7146 inst.reloc.type = BFD_RELOC_UNUSED;
7153 inst.instruction |= inst.operands[0].reg << 8;
7154 inst.instruction |= inst.operands[1].imm - 1;
7155 inst.instruction |= inst.operands[2].reg << 16;
7161 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7162 || inst.operands[2].postind || inst.operands[2].writeback
7163 || inst.operands[2].immisreg || inst.operands[2].shifted
7164 || inst.operands[2].negative,
7165 _("instruction does not accept this addressing mode"));
7167 inst.instruction |= inst.operands[0].reg << 8;
7168 inst.instruction |= inst.operands[1].reg << 12;
7169 inst.instruction |= inst.operands[2].reg << 16;
7170 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
7176 if (!inst.operands[2].present)
7177 inst.operands[2].reg = inst.operands[1].reg + 1;
7179 constraint (inst.operands[0].reg == inst.operands[1].reg
7180 || inst.operands[0].reg == inst.operands[2].reg
7181 || inst.operands[0].reg == inst.operands[3].reg
7182 || inst.operands[1].reg == inst.operands[2].reg,
7185 inst.instruction |= inst.operands[0].reg;
7186 inst.instruction |= inst.operands[1].reg << 12;
7187 inst.instruction |= inst.operands[2].reg << 8;
7188 inst.instruction |= inst.operands[3].reg << 16;
7194 inst.instruction |= inst.operands[0].reg << 8;
7195 inst.instruction |= inst.operands[1].reg << 16;
7196 inst.instruction |= inst.operands[2].reg;
7197 inst.instruction |= inst.operands[3].imm << 4;
7203 if (inst.instruction <= 0xffff && inst.size_req != 4
7204 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7205 && (!inst.operands[2].present || inst.operands[2].imm == 0))
7207 inst.instruction = THUMB_OP16 (inst.instruction);
7208 inst.instruction |= inst.operands[0].reg;
7209 inst.instruction |= inst.operands[1].reg << 3;
7211 else if (unified_syntax)
7213 if (inst.instruction <= 0xffff)
7214 inst.instruction = THUMB_OP32 (inst.instruction);
7215 inst.instruction |= inst.operands[0].reg << 8;
7216 inst.instruction |= inst.operands[1].reg;
7217 inst.instruction |= inst.operands[2].imm << 4;
7221 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
7222 _("Thumb encoding does not support rotation"));
7223 constraint (1, BAD_HIREG);
7230 inst.reloc.type = BFD_RELOC_ARM_SWI;
7236 inst.instruction |= inst.operands[0].reg << 8;
7237 inst.instruction |= inst.operands[1].imm;
7238 inst.instruction |= inst.operands[2].reg << 16;
7240 if (inst.operands[3].present)
7242 constraint (inst.reloc.exp.X_op != O_constant,
7243 _("expression too complex"));
7244 if (inst.reloc.exp.X_add_number != 0)
7246 if (inst.operands[3].shift_kind == SHIFT_ASR)
7247 inst.instruction |= 0x00200000; /* sh bit */
7249 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7250 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7252 inst.reloc.type = BFD_RELOC_UNUSED;
7259 inst.instruction |= inst.operands[0].reg << 8;
7260 inst.instruction |= inst.operands[1].imm;
7261 inst.instruction |= inst.operands[2].reg << 16;
7264 /* Overall per-instruction processing. */
7266 /* We need to be able to fix up arbitrary expressions in some statements.
7267 This is so that we can handle symbols that are an arbitrary distance from
7268 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7269 which returns part of an address in a form which will be valid for
7270 a data instruction. We do this by pushing the expression into a symbol
7271 in the expr_section, and creating a fix for that. */
7274 fix_new_arm (fragS * frag,
7289 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7293 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7298 /* Mark whether the fix is to a THUMB instruction, or an ARM
7300 new_fix->tc_fix_data = thumb_mode;
7304 output_inst (const char * str)
7310 as_bad ("%s -- `%s'", inst.error, str);
7316 to = frag_more (inst.size);
7318 if (thumb_mode && (inst.size > THUMB_SIZE))
7320 assert (inst.size == (2 * THUMB_SIZE));
7321 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
7322 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
7324 else if (inst.size > INSN_SIZE)
7326 assert (inst.size == (2 * INSN_SIZE));
7327 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7328 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
7331 md_number_to_chars (to, inst.instruction, inst.size);
7333 if (inst.reloc.type != BFD_RELOC_UNUSED)
7334 fix_new_arm (frag_now, to - frag_now->fr_literal,
7335 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7339 dwarf2_emit_insn (inst.size);
7343 /* Tag values used in struct asm_opcode's tag field. */
7346 OT_unconditional, /* Instruction cannot be conditionalized.
7347 The ARM condition field is still 0xE. */
7348 OT_unconditionalF, /* Instruction cannot be conditionalized
7349 and carries 0xF in its ARM condition field. */
7350 OT_csuffix, /* Instruction takes a conditional suffix. */
7351 OT_cinfix3, /* Instruction takes a conditional infix,
7352 beginning at character index 3. (In
7353 unified mode, it becomes a suffix.) */
7354 OT_csuf_or_in3, /* Instruction takes either a conditional
7355 suffix or an infix at character index 3.
7356 (In unified mode, a suffix only. */
7357 OT_odd_infix_unc, /* This is the unconditional variant of an
7358 instruction that takes a conditional infix
7359 at an unusual position. In unified mode,
7360 this variant will accept a suffix. */
7361 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
7362 are the conditional variants of instructions that
7363 take conditional infixes in unusual positions.
7364 The infix appears at character index
7365 (tag - OT_odd_infix_0). These are not accepted
7369 /* Subroutine of md_assemble, responsible for looking up the primary
7370 opcode from the mnemonic the user wrote. STR points to the
7371 beginning of the mnemonic.
7373 This is not simply a hash table lookup, because of conditional
7374 variants. Most instructions have conditional variants, which are
7375 expressed with a _conditional affix_ to the mnemonic. If we were
7376 to encode each conditional variant as a literal string in the opcode
7377 table, it would have approximately 20,000 entries.
7379 Most mnemonics take this affix as a suffix, and in unified syntax,
7380 'most' is upgraded to 'all'. However, in the divided syntax, some
7381 instructions take the affix as an infix, notably the s-variants of
7382 the arithmetic instructions. Of those instructions, all but six
7383 have the infix appear after the third character of the mnemonic.
7385 Accordingly, the algorithm for looking up primary opcodes given
7388 1. Look up the identifier in the opcode table.
7389 If we find a match, go to step U.
7391 2. Look up the last two characters of the identifier in the
7392 conditions table. If we find a match, look up the first N-2
7393 characters of the identifier in the opcode table. If we
7394 find a match, go to step CE.
7396 3. Look up the fourth and fifth characters of the identifier in
7397 the conditions table. If we find a match, extract those
7398 characters from the identifier, and look up the remaining
7399 characters in the opcode table. If we find a match, go
7404 U. Examine the tag field of the opcode structure, in case this is
7405 one of the six instructions with its conditional infix in an
7406 unusual place. If it is, the tag tells us where to find the
7407 infix; look it up in the conditions table and set inst.cond
7408 accordingly. Otherwise, this is an unconditional instruction.
7409 Again set inst.cond accordingly. Return the opcode structure.
7411 CE. Examine the tag field to make sure this is an instruction that
7412 should receive a conditional suffix. If it is not, fail.
7413 Otherwise, set inst.cond from the suffix we already looked up,
7414 and return the opcode structure.
7416 CM. Examine the tag field to make sure this is an instruction that
7417 should receive a conditional infix after the third character.
7418 If it is not, fail. Otherwise, undo the edits to the current
7419 line of input and proceed as for case CE. */
7421 static const struct asm_opcode *
7422 opcode_lookup (char **str)
7426 const struct asm_opcode *opcode;
7427 const struct asm_cond *cond;
7429 /* Scan up to the end of the mnemonic, which must end in white space,
7430 '.' (in unified mode only), or end of string. */
7431 for (base = end = *str; *end != '\0'; end++)
7432 if (*end == ' ' || (unified_syntax && *end == '.'))
7438 /* Handle a possible width suffix. */
7441 if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
7443 else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
7453 /* Look for unaffixed or special-case affixed mnemonic. */
7454 opcode = hash_find_n (arm_ops_hsh, base, end - base);
7458 if (opcode->tag < OT_odd_infix_0)
7460 inst.cond = COND_ALWAYS;
7465 as_warn (_("conditional infixes are deprecated in unified syntax"));
7466 affix = base + (opcode->tag - OT_odd_infix_0);
7467 cond = hash_find_n (arm_cond_hsh, affix, 2);
7470 inst.cond = cond->value;
7474 /* Cannot have a conditional suffix on a mnemonic of less than two
7479 /* Look for suffixed mnemonic. */
7481 cond = hash_find_n (arm_cond_hsh, affix, 2);
7482 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
7486 switch (opcode->tag)
7489 case OT_odd_infix_unc:
7490 if (!unified_syntax)
7492 /* else fall through */
7495 case OT_csuf_or_in3:
7496 inst.cond = cond->value;
7499 case OT_unconditional:
7500 case OT_unconditionalF:
7501 /* delayed diagnostic */
7502 inst.error = BAD_COND;
7503 inst.cond = COND_ALWAYS;
7511 /* Cannot have a usual-position infix on a mnemonic of less than
7512 six characters (five would be a suffix). */
7516 /* Look for infixed mnemonic in the usual position. */
7518 cond = hash_find_n (arm_cond_hsh, affix, 2);
7522 memcpy (save, affix, 2);
7523 memmove (affix, affix + 2, (end - affix) - 2);
7524 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
7525 memmove (affix + 2, affix, (end - affix) - 2);
7526 memcpy (affix, save, 2);
7528 if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3))
7532 as_warn (_("conditional infixes are deprecated in unified syntax"));
7534 inst.cond = cond->value;
7542 md_assemble (char *str)
7545 const struct asm_opcode * opcode;
7547 /* Align the previous label if needed. */
7548 if (last_label_seen != NULL)
7550 symbol_set_frag (last_label_seen, frag_now);
7551 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
7552 S_SET_SEGMENT (last_label_seen, now_seg);
7555 memset (&inst, '\0', sizeof (inst));
7556 inst.reloc.type = BFD_RELOC_UNUSED;
7558 opcode = opcode_lookup (&p);
7561 /* It wasn't an instruction, but it might be a register alias of
7562 the form alias .req reg. */
7563 if (!create_register_alias (str, p))
7564 as_bad (_("bad instruction `%s'"), str);
7571 /* Check that this instruction is supported for this CPU. */
7572 if (thumb_mode == 1 && (opcode->tvariant & cpu_variant) == 0)
7574 as_bad (_("selected processor does not support `%s'"), str);
7577 if (inst.cond != COND_ALWAYS && !unified_syntax
7578 && opcode->tencode != do_t_branch)
7580 as_bad (_("Thumb does not support conditional execution"));
7584 mapping_state (MAP_THUMB);
7585 inst.instruction = opcode->tvalue;
7587 if (!parse_operands (p, opcode->operands))
7592 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
7593 inst.size = (inst.instruction > 0xffff ? 4 : 2);
7594 if (inst.size_req && inst.size_req != inst.size)
7596 as_bad (_("cannot honor width suffix -- `%s'"), str);
7603 /* Check that this instruction is supported for this CPU. */
7604 if ((opcode->avariant & cpu_variant) == 0)
7606 as_bad (_("selected processor does not support `%s'"), str);
7611 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
7615 mapping_state (MAP_ARM);
7616 inst.instruction = opcode->avalue;
7617 if (opcode->tag == OT_unconditionalF)
7618 inst.instruction |= 0xF << 28;
7620 inst.instruction |= inst.cond << 28;
7621 inst.size = INSN_SIZE;
7622 if (!parse_operands (p, opcode->operands))
7628 /* Various frobbings of labels and their addresses. */
7631 arm_start_line_hook (void)
7633 last_label_seen = NULL;
7637 arm_frob_label (symbolS * sym)
7639 last_label_seen = sym;
7641 ARM_SET_THUMB (sym, thumb_mode);
7643 #if defined OBJ_COFF || defined OBJ_ELF
7644 ARM_SET_INTERWORK (sym, support_interwork);
7647 /* Note - do not allow local symbols (.Lxxx) to be labeled
7648 as Thumb functions. This is because these labels, whilst
7649 they exist inside Thumb code, are not the entry points for
7650 possible ARM->Thumb calls. Also, these labels can be used
7651 as part of a computed goto or switch statement. eg gcc
7652 can generate code that looks like this:
7664 The first instruction loads the address of the jump table.
7665 The second instruction converts a table index into a byte offset.
7666 The third instruction gets the jump address out of the table.
7667 The fourth instruction performs the jump.
7669 If the address stored at .Laaa is that of a symbol which has the
7670 Thumb_Func bit set, then the linker will arrange for this address
7671 to have the bottom bit set, which in turn would mean that the
7672 address computation performed by the third instruction would end
7673 up with the bottom bit set. Since the ARM is capable of unaligned
7674 word loads, the instruction would then load the incorrect address
7675 out of the jump table, and chaos would ensue. */
7676 if (label_is_thumb_function_name
7677 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
7678 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
7680 /* When the address of a Thumb function is taken the bottom
7681 bit of that address should be set. This will allow
7682 interworking between Arm and Thumb functions to work
7685 THUMB_SET_FUNC (sym, 1);
7687 label_is_thumb_function_name = FALSE;
7692 arm_data_in_code (void)
7694 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7696 *input_line_pointer = '/';
7697 input_line_pointer += 5;
7698 *input_line_pointer = 0;
7706 arm_canonicalize_symbol_name (char * name)
7710 if (thumb_mode && (len = strlen (name)) > 5
7711 && streq (name + len - 5, "/data"))
7712 *(name + len - 5) = 0;
7717 /* Table of all register names defined by default. The user can
7718 define additional names with .req. Note that all register names
7719 should appear in both upper and lowercase variants. Some registers
7720 also have mixed-case names. */
7722 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7723 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7724 #define REGSET(p,t) \
7725 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7726 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7727 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7728 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7730 static const struct reg_entry reg_names[] =
7732 /* ARM integer registers. */
7733 REGSET(r, RN), REGSET(R, RN),
7735 /* ATPCS synonyms. */
7736 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
7737 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
7738 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7740 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
7741 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
7742 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7744 /* Well-known aliases. */
7745 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
7746 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
7748 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
7749 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
7751 /* Coprocessor numbers. */
7752 REGSET(p, CP), REGSET(P, CP),
7754 /* Coprocessor register numbers. The "cr" variants are for backward
7756 REGSET(c, CN), REGSET(C, CN),
7757 REGSET(cr, CN), REGSET(CR, CN),
7759 /* FPA registers. */
7760 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
7761 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
7763 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
7764 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
7766 /* VFP SP registers. */
7768 REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
7769 REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
7770 REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
7771 REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
7774 REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
7775 REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
7776 REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
7777 REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
7779 /* VFP DP Registers. */
7780 REGSET(d,VFD), REGSET(D,VFS),
7782 /* VFP control registers. */
7783 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
7784 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
7786 /* Maverick DSP coprocessor registers. */
7787 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
7788 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
7790 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
7791 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
7792 REGDEF(dspsc,0,DSPSC),
7794 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
7795 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
7796 REGDEF(DSPSC,0,DSPSC),
7798 /* iWMMXt data registers - p0, c0-15. */
7799 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
7801 /* iWMMXt control registers - p1, c0-3. */
7802 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
7803 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
7804 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
7805 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
7807 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
7808 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
7809 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
7810 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
7811 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
7813 /* XScale accumulator registers. */
7814 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
7820 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
7821 within psr_required_here. */
7822 static const struct asm_psr psrs[] =
7824 /* Backward compatibility notation. Note that "all" is no longer
7825 truly all possible PSR bits. */
7826 {"all", PSR_c | PSR_f},
7830 /* Individual flags. */
7835 /* Combinations of flags. */
7836 {"fs", PSR_f | PSR_s},
7837 {"fx", PSR_f | PSR_x},
7838 {"fc", PSR_f | PSR_c},
7839 {"sf", PSR_s | PSR_f},
7840 {"sx", PSR_s | PSR_x},
7841 {"sc", PSR_s | PSR_c},
7842 {"xf", PSR_x | PSR_f},
7843 {"xs", PSR_x | PSR_s},
7844 {"xc", PSR_x | PSR_c},
7845 {"cf", PSR_c | PSR_f},
7846 {"cs", PSR_c | PSR_s},
7847 {"cx", PSR_c | PSR_x},
7848 {"fsx", PSR_f | PSR_s | PSR_x},
7849 {"fsc", PSR_f | PSR_s | PSR_c},
7850 {"fxs", PSR_f | PSR_x | PSR_s},
7851 {"fxc", PSR_f | PSR_x | PSR_c},
7852 {"fcs", PSR_f | PSR_c | PSR_s},
7853 {"fcx", PSR_f | PSR_c | PSR_x},
7854 {"sfx", PSR_s | PSR_f | PSR_x},
7855 {"sfc", PSR_s | PSR_f | PSR_c},
7856 {"sxf", PSR_s | PSR_x | PSR_f},
7857 {"sxc", PSR_s | PSR_x | PSR_c},
7858 {"scf", PSR_s | PSR_c | PSR_f},
7859 {"scx", PSR_s | PSR_c | PSR_x},
7860 {"xfs", PSR_x | PSR_f | PSR_s},
7861 {"xfc", PSR_x | PSR_f | PSR_c},
7862 {"xsf", PSR_x | PSR_s | PSR_f},
7863 {"xsc", PSR_x | PSR_s | PSR_c},
7864 {"xcf", PSR_x | PSR_c | PSR_f},
7865 {"xcs", PSR_x | PSR_c | PSR_s},
7866 {"cfs", PSR_c | PSR_f | PSR_s},
7867 {"cfx", PSR_c | PSR_f | PSR_x},
7868 {"csf", PSR_c | PSR_s | PSR_f},
7869 {"csx", PSR_c | PSR_s | PSR_x},
7870 {"cxf", PSR_c | PSR_x | PSR_f},
7871 {"cxs", PSR_c | PSR_x | PSR_s},
7872 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
7873 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
7874 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
7875 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
7876 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
7877 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
7878 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
7879 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
7880 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
7881 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
7882 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
7883 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
7884 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
7885 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
7886 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
7887 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
7888 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
7889 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
7890 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
7891 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
7892 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
7893 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
7894 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
7895 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
7898 /* Table of all shift-in-operand names. */
7899 static const struct asm_shift_name shift_names [] =
7901 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
7902 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
7903 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
7904 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
7905 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
7906 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
7909 /* Table of all explicit relocation names. */
7911 static struct reloc_entry reloc_names[] =
7913 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
7914 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
7915 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
7916 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
7917 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
7918 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
7919 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
7920 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
7921 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
7922 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
7923 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
7927 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
7928 static const struct asm_cond conds[] =
7932 {"cs", 0x2}, {"hs", 0x2},
7933 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
7947 /* Table of ARM-format instructions. */
7949 /* Macros for gluing together operand strings. N.B. In all cases
7950 other than OPS0, the trailing OP_stop comes from default
7951 zero-initialization of the unspecified elements of the array. */
7952 #define OPS0() { OP_stop, }
7953 #define OPS1(a) { OP_##a, }
7954 #define OPS2(a,b) { OP_##a,OP_##b, }
7955 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
7956 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
7957 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
7958 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
7960 /* These macros abstract out the exact format of the mnemonic table and
7961 save some repeated characters. */
7963 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
7964 #define TxCE(mnem, op, top, nops, ops, ae, te) \
7965 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
7966 THUMB_VARIANT, do_##ae, do_##te }
7968 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
7969 a T_MNEM_xyz enumerator. */
7970 #define TCE(mnem, aop, top, nops, ops, ae, te) \
7971 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
7972 #define tCE(mnem, aop, top, nops, ops, ae, te) \
7973 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
7975 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
7976 infix after the third character. */
7977 #define TxC3(mnem, op, top, nops, ops, ae, te) \
7978 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
7979 THUMB_VARIANT, do_##ae, do_##te }
7980 #define TC3(mnem, aop, top, nops, ops, ae, te) \
7981 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
7982 #define tC3(mnem, aop, top, nops, ops, ae, te) \
7983 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
7985 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
7986 appear in the condition table. */
7987 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
7988 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
7989 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
7991 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
7992 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
7993 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
7994 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
7995 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
7996 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
7997 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
7998 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
7999 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8000 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8001 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8002 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8003 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8004 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8005 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8006 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8007 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8008 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8009 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8010 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8012 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8013 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8014 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8015 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8017 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8018 field is still 0xE. */
8019 #define TUE(mnem, op, top, nops, ops, ae, te) \
8020 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8021 THUMB_VARIANT, do_##ae, do_##te }
8023 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8024 condition code field. */
8025 #define TUF(mnem, op, top, nops, ops, ae, te) \
8026 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8027 THUMB_VARIANT, do_##ae, do_##te }
8029 /* ARM-only variants of all the above. */
8030 #define CE(mnem, op, nops, ops, ae) TCE(mnem, op, 0, nops, ops, ae, 0)
8031 #define C3(mnem, op, nops, ops, ae) TC3(mnem, op, 0, nops, ops, ae, 0)
8032 #define CM(m1,m2, op, nops, ops, ae) TCM(m1,m2, op, 0, nops, ops, ae, 0)
8033 #define UE(mnem, op, nops, ops, ae) TUE(mnem, op, 0, nops, ops, ae, 0)
8034 #define UF(mnem, op, nops, ops, ae) TUF(mnem, op, 0, nops, ops, ae, 0)
8037 /* Thumb-only, unconditional. */
8038 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8040 /* ARM-only, takes either a suffix or a position-3 infix
8041 (for an FPA corner case). */
8042 #define C3E(mnem, op, nops, ops, ae) \
8043 { #mnem, OPS##nops ops, OT_csuf_or_in3, 0x##op, 0, ARM_VARIANT, 0, do_##ae, 0 }
8045 static const struct asm_opcode insns[] =
8047 #define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
8048 #define THUMB_VARIANT ARM_EXT_V4T
8049 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
8050 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
8051 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
8052 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
8053 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
8054 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
8055 tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
8056 tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
8057 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
8058 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
8059 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
8060 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
8061 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
8062 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
8063 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
8064 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
8066 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8067 for setting PSR flag bits. They are obsolete in V6 and do not
8068 have Thumb equivalents. */
8069 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8070 tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8071 C3(tstp, 110f000, 2, (RR, SH), cmp),
8072 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8073 tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8074 C3(cmpp, 150f000, 2, (RR, SH), cmp),
8075 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8076 tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8077 C3(cmnp, 170f000, 2, (RR, SH), cmp),
8079 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
8080 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
8081 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
8082 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
8084 tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
8085 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
8086 tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
8087 tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
8089 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8090 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8091 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8092 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8094 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
8096 /* XXX This is the wrong place to do this. Think multi-arch. */
8097 TCE(b, a000000, e7fe, 1, (EXPr), branch, t_branch),
8098 TCE(bl, b000000, f7fffffe, 1, (EXPr), branch, t_branch23),
8100 TCE(b, afffffe, e7fe, 1, (EXPr), branch, t_branch),
8101 TCE(bl, bfffffe, f7fffffe, 1, (EXPr), branch, t_branch23),
8105 TCE(adr, 28f0000, 000f, 2, (RR, EXP), adr, t_adr),
8106 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
8107 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
8109 /* Thumb-compatibility pseudo ops. */
8110 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
8111 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
8112 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
8113 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
8114 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
8115 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
8116 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
8117 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
8118 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
8119 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
8120 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
8121 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
8123 #undef THUMB_VARIANT
8124 #define THUMB_VARIANT ARM_EXT_V6
8125 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
8127 /* V1 instructions with no Thumb analogue prior to V6T2. */
8128 #undef THUMB_VARIANT
8129 #define THUMB_VARIANT ARM_EXT_V6T2
8130 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
8131 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
8132 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8133 TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8134 C3(teqp, 130f000, 2, (RR, SH), cmp),
8136 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
8137 TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt),
8138 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
8139 TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt),
8141 TC3(stmdb, 9000000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8142 TC3(stmfd, 9000000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8144 TC3(ldmdb, 9100000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8145 TC3(ldmea, 9100000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8147 /* V1 instructions with no Thumb analogue at all. */
8148 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
8149 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
8151 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
8152 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
8153 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
8154 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
8155 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
8156 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
8157 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
8158 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
8161 #define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
8162 #undef THUMB_VARIANT
8163 #define THUMB_VARIANT ARM_EXT_V4T
8164 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8165 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8167 #undef THUMB_VARIANT
8168 #define THUMB_VARIANT ARM_EXT_V6T2
8169 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8170 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
8172 /* Generic coprocessor instructions. */
8173 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8174 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8175 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8176 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8177 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8178 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8179 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8182 #define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
8183 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8184 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8187 #define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
8188 TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs),
8189 TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
8192 #define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
8193 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8194 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8195 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8196 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8197 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8198 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8199 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8200 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8203 #define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
8204 #undef THUMB_VARIANT
8205 #define THUMB_VARIANT ARM_EXT_V4T
8206 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
8207 tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
8208 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8209 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8210 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8211 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8214 #define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
8215 /* ARM Architecture 4T. */
8216 /* Note: bx (and blx) are required on V5, even if the processor does
8217 not support Thumb. */
8218 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
8221 #define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
8222 #undef THUMB_VARIANT
8223 #define THUMB_VARIANT ARM_EXT_V5T
8224 /* Note: blx has 2 variants; the .value coded here is for
8225 BLX(2). Only this variant has conditional execution. */
8226 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
8227 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
8229 #undef THUMB_VARIANT
8230 #define THUMB_VARIANT ARM_EXT_V6T2
8231 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
8232 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8233 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8234 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8235 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8236 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8237 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8238 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8241 #define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
8242 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8243 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8244 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8245 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8247 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8248 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8250 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8251 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8252 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8253 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8255 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8256 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8257 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8258 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8260 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8261 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8263 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8264 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8265 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8266 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8269 #define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
8270 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
8271 TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8272 TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8274 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8275 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8278 #define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
8279 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
8282 #define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
8283 #undef THUMB_VARIANT
8284 #define THUMB_VARIANT ARM_EXT_V6
8285 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
8286 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
8287 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8288 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8289 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8290 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8291 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8292 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8293 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8294 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
8296 #undef THUMB_VARIANT
8297 #define THUMB_VARIANT ARM_EXT_V6T2
8298 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0),
8299 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
8300 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8301 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8302 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
8303 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
8304 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8305 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8306 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8307 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8308 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8309 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8310 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8311 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8312 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8313 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8314 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8315 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8316 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8317 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8318 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8319 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8320 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8321 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8322 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8323 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8324 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8325 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8326 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8327 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8328 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8329 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8330 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8331 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8332 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8333 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8334 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8335 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8336 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8337 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8338 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8339 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8340 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8341 UF(rfeib, 9900a00, 1, (RRw), rfe),
8342 UF(rfeda, 8100a00, 1, (RRw), rfe),
8343 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8344 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8345 UF(rfefa, 9900a00, 1, (RRw), rfe),
8346 UF(rfeea, 8100a00, 1, (RRw), rfe),
8347 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8348 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8349 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8350 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8351 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8352 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8353 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8354 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8355 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8356 TCE(sel, 68000b0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8357 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8358 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8359 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8360 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8361 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8362 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8363 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8364 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8365 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8366 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8367 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8368 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8369 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8370 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8371 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8372 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8373 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8374 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8375 TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs),
8376 UF(srsib, 9cd0500, 1, (I31w), srs),
8377 UF(srsda, 84d0500, 1, (I31w), srs),
8378 TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs),
8379 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
8380 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
8381 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
8382 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
8383 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8384 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8385 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
8386 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
8389 #define ARM_VARIANT ARM_EXT_V6K
8390 #undef THUMB_VARIANT
8391 #define THUMB_VARIANT ARM_EXT_V6K
8392 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
8393 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
8394 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
8395 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
8397 #undef THUMB_VARIANT
8398 #define THUMB_VARIANT ARM_EXT_V6T2
8399 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
8400 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
8401 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
8402 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
8403 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
8404 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
8405 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
8408 #define ARM_VARIANT ARM_EXT_V6Z
8409 TCE(smi, 1600070, f7f08000, 1, (EXPi), smi, t_smi),
8412 #define ARM_VARIANT ARM_EXT_V6T2
8413 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
8414 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
8415 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
8416 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
8418 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8419 TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16),
8420 TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16),
8421 TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
8423 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8424 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8425 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8426 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8428 UT(cbnz, b900, 2, (RR, EXP), t_czb),
8429 UT(cbz, b100, 2, (RR, EXP), t_czb),
8430 /* ARM does not really have an IT instruction. */
8431 TUE(it, 0, bf08, 1, (COND), it, t_it),
8432 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
8433 TUE(ite, 0, bf04, 1, (COND), it, t_it),
8434 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
8435 TUE(itet, 0, bf06, 1, (COND), it, t_it),
8436 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
8437 TUE(itee, 0, bf02, 1, (COND), it, t_it),
8438 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
8439 TUE(itett, 0, bf07, 1, (COND), it, t_it),
8440 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
8441 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
8442 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
8443 TUE(itete, 0, bf05, 1, (COND), it, t_it),
8444 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
8445 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
8448 #define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
8449 CE(wfs, e200110, 1, (RR), rd),
8450 CE(rfs, e300110, 1, (RR), rd),
8451 CE(wfc, e400110, 1, (RR), rd),
8452 CE(rfc, e500110, 1, (RR), rd),
8454 C3(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
8455 C3(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
8456 C3(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
8457 C3(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
8459 C3(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
8460 C3(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
8461 C3(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
8462 C3(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
8464 C3(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
8465 C3(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
8466 C3(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
8467 C3(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
8468 C3(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
8469 C3(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
8470 C3(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
8471 C3(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
8472 C3(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
8473 C3(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
8474 C3(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
8475 C3(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
8477 C3(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
8478 C3(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
8479 C3(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
8480 C3(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
8481 C3(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
8482 C3(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
8483 C3(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
8484 C3(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
8485 C3(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
8486 C3(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
8487 C3(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
8488 C3(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
8490 C3(abss, e208100, 2, (RF, RF_IF), rd_rm),
8491 C3(abssp, e208120, 2, (RF, RF_IF), rd_rm),
8492 C3(abssm, e208140, 2, (RF, RF_IF), rd_rm),
8493 C3(abssz, e208160, 2, (RF, RF_IF), rd_rm),
8494 C3(absd, e208180, 2, (RF, RF_IF), rd_rm),
8495 C3(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
8496 C3(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
8497 C3(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
8498 C3(abse, e288100, 2, (RF, RF_IF), rd_rm),
8499 C3(absep, e288120, 2, (RF, RF_IF), rd_rm),
8500 C3(absem, e288140, 2, (RF, RF_IF), rd_rm),
8501 C3(absez, e288160, 2, (RF, RF_IF), rd_rm),
8503 C3(rnds, e308100, 2, (RF, RF_IF), rd_rm),
8504 C3(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
8505 C3(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
8506 C3(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
8507 C3(rndd, e308180, 2, (RF, RF_IF), rd_rm),
8508 C3(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
8509 C3(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
8510 C3(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
8511 C3(rnde, e388100, 2, (RF, RF_IF), rd_rm),
8512 C3(rndep, e388120, 2, (RF, RF_IF), rd_rm),
8513 C3(rndem, e388140, 2, (RF, RF_IF), rd_rm),
8514 C3(rndez, e388160, 2, (RF, RF_IF), rd_rm),
8516 C3(sqts, e408100, 2, (RF, RF_IF), rd_rm),
8517 C3(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
8518 C3(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
8519 C3(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
8520 C3(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
8521 C3(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
8522 C3(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
8523 C3(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
8524 C3(sqte, e488100, 2, (RF, RF_IF), rd_rm),
8525 C3(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
8526 C3(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
8527 C3(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
8529 C3(logs, e508100, 2, (RF, RF_IF), rd_rm),
8530 C3(logsp, e508120, 2, (RF, RF_IF), rd_rm),
8531 C3(logsm, e508140, 2, (RF, RF_IF), rd_rm),
8532 C3(logsz, e508160, 2, (RF, RF_IF), rd_rm),
8533 C3(logd, e508180, 2, (RF, RF_IF), rd_rm),
8534 C3(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
8535 C3(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
8536 C3(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
8537 C3(loge, e588100, 2, (RF, RF_IF), rd_rm),
8538 C3(logep, e588120, 2, (RF, RF_IF), rd_rm),
8539 C3(logem, e588140, 2, (RF, RF_IF), rd_rm),
8540 C3(logez, e588160, 2, (RF, RF_IF), rd_rm),
8542 C3(lgns, e608100, 2, (RF, RF_IF), rd_rm),
8543 C3(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
8544 C3(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
8545 C3(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
8546 C3(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
8547 C3(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
8548 C3(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
8549 C3(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
8550 C3(lgne, e688100, 2, (RF, RF_IF), rd_rm),
8551 C3(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
8552 C3(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
8553 C3(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
8555 C3(exps, e708100, 2, (RF, RF_IF), rd_rm),
8556 C3(expsp, e708120, 2, (RF, RF_IF), rd_rm),
8557 C3(expsm, e708140, 2, (RF, RF_IF), rd_rm),
8558 C3(expsz, e708160, 2, (RF, RF_IF), rd_rm),
8559 C3(expd, e708180, 2, (RF, RF_IF), rd_rm),
8560 C3(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
8561 C3(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
8562 C3(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
8563 C3(expe, e788100, 2, (RF, RF_IF), rd_rm),
8564 C3(expep, e788120, 2, (RF, RF_IF), rd_rm),
8565 C3(expem, e788140, 2, (RF, RF_IF), rd_rm),
8566 C3(expdz, e788160, 2, (RF, RF_IF), rd_rm),
8568 C3(sins, e808100, 2, (RF, RF_IF), rd_rm),
8569 C3(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
8570 C3(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
8571 C3(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
8572 C3(sind, e808180, 2, (RF, RF_IF), rd_rm),
8573 C3(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
8574 C3(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
8575 C3(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
8576 C3(sine, e888100, 2, (RF, RF_IF), rd_rm),
8577 C3(sinep, e888120, 2, (RF, RF_IF), rd_rm),
8578 C3(sinem, e888140, 2, (RF, RF_IF), rd_rm),
8579 C3(sinez, e888160, 2, (RF, RF_IF), rd_rm),
8581 C3(coss, e908100, 2, (RF, RF_IF), rd_rm),
8582 C3(cossp, e908120, 2, (RF, RF_IF), rd_rm),
8583 C3(cossm, e908140, 2, (RF, RF_IF), rd_rm),
8584 C3(cossz, e908160, 2, (RF, RF_IF), rd_rm),
8585 C3(cosd, e908180, 2, (RF, RF_IF), rd_rm),
8586 C3(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
8587 C3(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
8588 C3(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
8589 C3(cose, e988100, 2, (RF, RF_IF), rd_rm),
8590 C3(cosep, e988120, 2, (RF, RF_IF), rd_rm),
8591 C3(cosem, e988140, 2, (RF, RF_IF), rd_rm),
8592 C3(cosez, e988160, 2, (RF, RF_IF), rd_rm),
8594 C3(tans, ea08100, 2, (RF, RF_IF), rd_rm),
8595 C3(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
8596 C3(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
8597 C3(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
8598 C3(tand, ea08180, 2, (RF, RF_IF), rd_rm),
8599 C3(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
8600 C3(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
8601 C3(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
8602 C3(tane, ea88100, 2, (RF, RF_IF), rd_rm),
8603 C3(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
8604 C3(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
8605 C3(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
8607 C3(asns, eb08100, 2, (RF, RF_IF), rd_rm),
8608 C3(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
8609 C3(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
8610 C3(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
8611 C3(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
8612 C3(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
8613 C3(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
8614 C3(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
8615 C3(asne, eb88100, 2, (RF, RF_IF), rd_rm),
8616 C3(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
8617 C3(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
8618 C3(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
8620 C3(acss, ec08100, 2, (RF, RF_IF), rd_rm),
8621 C3(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
8622 C3(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
8623 C3(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
8624 C3(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
8625 C3(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
8626 C3(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
8627 C3(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
8628 C3(acse, ec88100, 2, (RF, RF_IF), rd_rm),
8629 C3(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
8630 C3(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
8631 C3(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
8633 C3(atns, ed08100, 2, (RF, RF_IF), rd_rm),
8634 C3(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
8635 C3(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
8636 C3(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
8637 C3(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
8638 C3(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
8639 C3(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
8640 C3(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
8641 C3(atne, ed88100, 2, (RF, RF_IF), rd_rm),
8642 C3(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
8643 C3(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
8644 C3(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
8646 C3(urds, ee08100, 2, (RF, RF_IF), rd_rm),
8647 C3(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
8648 C3(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
8649 C3(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
8650 C3(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
8651 C3(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
8652 C3(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
8653 C3(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
8654 C3(urde, ee88100, 2, (RF, RF_IF), rd_rm),
8655 C3(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
8656 C3(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
8657 C3(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
8659 C3(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
8660 C3(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
8661 C3(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
8662 C3(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
8663 C3(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
8664 C3(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
8665 C3(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
8666 C3(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
8667 C3(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
8668 C3(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
8669 C3(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
8670 C3(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
8672 C3(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
8673 C3(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
8674 C3(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
8675 C3(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
8676 C3(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
8677 C3(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8678 C3(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8679 C3(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8680 C3(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
8681 C3(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
8682 C3(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
8683 C3(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
8685 C3(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
8686 C3(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
8687 C3(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
8688 C3(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
8689 C3(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
8690 C3(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8691 C3(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8692 C3(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8693 C3(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
8694 C3(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
8695 C3(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
8696 C3(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
8698 C3(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
8699 C3(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
8700 C3(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
8701 C3(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
8702 C3(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
8703 C3(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8704 C3(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8705 C3(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8706 C3(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
8707 C3(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
8708 C3(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
8709 C3(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
8711 C3(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
8712 C3(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
8713 C3(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
8714 C3(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
8715 C3(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
8716 C3(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8717 C3(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8718 C3(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8719 C3(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
8720 C3(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
8721 C3(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
8722 C3(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
8724 C3(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
8725 C3(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
8726 C3(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
8727 C3(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
8728 C3(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
8729 C3(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8730 C3(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8731 C3(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8732 C3(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
8733 C3(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
8734 C3(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
8735 C3(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
8737 C3(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
8738 C3(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
8739 C3(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
8740 C3(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
8741 C3(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
8742 C3(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8743 C3(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8744 C3(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8745 C3(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
8746 C3(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
8747 C3(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
8748 C3(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
8750 C3(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
8751 C3(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
8752 C3(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
8753 C3(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
8754 C3(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
8755 C3(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8756 C3(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8757 C3(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8758 C3(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
8759 C3(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
8760 C3(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
8761 C3(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
8763 C3(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
8764 C3(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
8765 C3(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
8766 C3(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
8767 C3(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
8768 C3(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8769 C3(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8770 C3(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8771 C3(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
8772 C3(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
8773 C3(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
8774 C3(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
8776 C3(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
8777 C3(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
8778 C3(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
8779 C3(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
8780 C3(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
8781 C3(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8782 C3(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8783 C3(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8784 C3(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
8785 C3(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
8786 C3(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
8787 C3(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
8789 C3(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
8790 C3(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
8791 C3(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
8792 C3(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
8793 C3(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
8794 C3(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8795 C3(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8796 C3(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8797 C3(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
8798 C3(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
8799 C3(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
8800 C3(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
8802 C3(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
8803 C3(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
8804 C3(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
8805 C3(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
8806 C3(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
8807 C3(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8808 C3(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8809 C3(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8810 C3(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
8811 C3(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
8812 C3(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
8813 C3(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8815 C3(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
8816 C3(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
8817 C3(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
8818 C3(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
8819 C3(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
8820 C3(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8821 C3(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8822 C3(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8823 C3(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
8824 C3(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
8825 C3(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
8826 C3(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8828 C3(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
8829 C3(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
8830 C3(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
8831 C3(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
8832 C3(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
8833 C3(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8834 C3(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8835 C3(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8836 C3(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
8837 C3(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
8838 C3(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
8839 C3(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8841 CE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
8842 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
8843 CE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
8844 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
8846 C3(flts, e000110, 2, (RF, RR), rn_rd),
8847 C3(fltsp, e000130, 2, (RF, RR), rn_rd),
8848 C3(fltsm, e000150, 2, (RF, RR), rn_rd),
8849 C3(fltsz, e000170, 2, (RF, RR), rn_rd),
8850 C3(fltd, e000190, 2, (RF, RR), rn_rd),
8851 C3(fltdp, e0001b0, 2, (RF, RR), rn_rd),
8852 C3(fltdm, e0001d0, 2, (RF, RR), rn_rd),
8853 C3(fltdz, e0001f0, 2, (RF, RR), rn_rd),
8854 C3(flte, e080110, 2, (RF, RR), rn_rd),
8855 C3(fltep, e080130, 2, (RF, RR), rn_rd),
8856 C3(fltem, e080150, 2, (RF, RR), rn_rd),
8857 C3(fltez, e080170, 2, (RF, RR), rn_rd),
8859 /* The implementation of the FIX instruction is broken on some
8860 assemblers, in that it accepts a precision specifier as well as a
8861 rounding specifier, despite the fact that this is meaningless.
8862 To be more compatible, we accept it as well, though of course it
8863 does not set any bits. */
8864 CE(fix, e100110, 2, (RR, RF), rd_rm),
8865 C3(fixp, e100130, 2, (RR, RF), rd_rm),
8866 C3(fixm, e100150, 2, (RR, RF), rd_rm),
8867 C3(fixz, e100170, 2, (RR, RF), rd_rm),
8868 C3(fixsp, e100130, 2, (RR, RF), rd_rm),
8869 C3(fixsm, e100150, 2, (RR, RF), rd_rm),
8870 C3(fixsz, e100170, 2, (RR, RF), rd_rm),
8871 C3(fixdp, e100130, 2, (RR, RF), rd_rm),
8872 C3(fixdm, e100150, 2, (RR, RF), rd_rm),
8873 C3(fixdz, e100170, 2, (RR, RF), rd_rm),
8874 C3(fixep, e100130, 2, (RR, RF), rd_rm),
8875 C3(fixem, e100150, 2, (RR, RF), rd_rm),
8876 C3(fixez, e100170, 2, (RR, RF), rd_rm),
8878 /* Instructions that were new with the real FPA, call them V2. */
8880 #define ARM_VARIANT FPU_FPA_EXT_V2
8881 CE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8882 C3(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8883 C3(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8884 CE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8885 C3(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8886 C3(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
8889 #define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
8890 /* Moves and type conversions. */
8891 CE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
8892 CE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
8893 CE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
8894 CE(fmstat, ef1fa10, 0, (), noargs),
8895 CE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
8896 CE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
8897 CE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
8898 CE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
8899 CE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
8900 CE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
8901 CE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
8902 CE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
8904 /* Memory operations. */
8905 CE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
8906 CE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
8907 CE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
8908 CE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
8909 CE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
8910 CE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
8911 CE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
8912 CE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
8913 CE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
8914 CE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
8915 CE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
8916 CE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
8917 CE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
8918 CE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
8919 CE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
8920 CE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
8921 CE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
8922 CE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
8924 /* Monadic operations. */
8925 CE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
8926 CE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
8927 CE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
8929 /* Dyadic operations. */
8930 CE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8931 CE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8932 CE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8933 CE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8934 CE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8935 CE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8936 CE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8937 CE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8938 CE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
8941 CE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
8942 CE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
8943 CE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
8944 CE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
8947 #define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
8948 /* Moves and type conversions. */
8949 CE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
8950 CE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
8951 CE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
8952 CE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
8953 CE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
8954 CE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
8955 CE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
8956 CE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
8957 CE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
8958 CE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
8959 CE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
8960 CE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
8961 CE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
8963 /* Memory operations. */
8964 CE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
8965 CE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
8966 CE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
8967 CE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
8968 CE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
8969 CE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
8970 CE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
8971 CE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
8972 CE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
8973 CE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
8975 /* Monadic operations. */
8976 CE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
8977 CE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
8978 CE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
8980 /* Dyadic operations. */
8981 CE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
8982 CE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
8983 CE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
8984 CE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
8985 CE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
8986 CE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
8987 CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
8988 CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
8989 CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
8992 CE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
8993 CE(fcmpzd, eb50b40, 1, (RVD), rd),
8994 CE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
8995 CE(fcmpezd, eb50bc0, 1, (RVD), rd),
8998 #define ARM_VARIANT FPU_VFP_EXT_V2
8999 CE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
9000 CE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
9001 CE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
9002 CE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
9005 #define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
9006 CE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9007 CE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9008 CE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9009 CE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9010 CE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9011 CE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9012 CE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
9013 CE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
9016 #define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
9017 CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
9018 CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
9019 CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
9020 CE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
9021 CE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
9022 CE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
9023 CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
9024 CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
9025 CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
9026 CE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9027 CE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9028 CE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9029 CE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9030 CE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9031 CE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9032 CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9033 CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9034 CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9035 CE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
9036 CE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
9037 CE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9038 CE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9039 CE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9040 CE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9041 CE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9042 CE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9043 CE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
9044 CE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
9045 CE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
9046 CE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
9047 CE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
9048 CE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
9049 CE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
9050 CE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
9051 CE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
9052 CE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
9053 CE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
9054 CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9055 CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9056 CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9057 CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9058 CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9059 CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9060 CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9061 CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9062 CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9063 CE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
9064 CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9065 CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9066 CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9067 CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9068 CE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9069 CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9070 CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9071 CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9072 CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9073 CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9074 CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9075 CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9076 CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9077 CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9078 CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9079 CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9080 CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9081 CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9082 CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9083 CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9084 CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9085 CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9086 CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9087 CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9088 CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9089 CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9090 CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9091 CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9092 CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9093 CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9094 CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9095 CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9096 CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9097 CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9098 CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9099 CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9100 CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9101 CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9102 CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9103 CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9104 CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9105 CE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
9106 CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9107 CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9108 CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9109 CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9110 CE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9111 CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9112 CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9113 CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9114 CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9115 CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9116 CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9117 CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9118 CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9119 CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9120 CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9121 CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9122 CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9123 CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9124 CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9125 CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9126 CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9127 CE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
9128 CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9129 CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9130 CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9131 CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9132 CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9133 CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9134 CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9135 CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9136 CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9137 CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9138 CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9139 CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9140 CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9141 CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9142 CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9143 CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9144 CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9145 CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9146 CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9147 CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9148 CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9149 CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9150 CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9151 CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9152 CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9153 CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9154 CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9155 CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9156 CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9157 CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9158 CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9159 CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
9160 CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
9161 CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
9162 CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
9163 CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
9164 CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
9165 CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9166 CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9167 CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9168 CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
9169 CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
9170 CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
9171 CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
9172 CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
9173 CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
9174 CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9175 CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9176 CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9177 CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9178 CE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
9181 #define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
9182 CE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
9183 CE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
9184 CE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
9185 CE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
9186 CE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
9187 CE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
9188 CE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
9189 CE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
9190 CE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
9191 CE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
9192 CE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
9193 CE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
9194 CE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
9195 CE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
9196 CE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
9197 CE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
9198 CE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
9199 CE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
9200 CE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
9201 CE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
9202 CE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
9203 CE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
9204 CE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
9205 CE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
9206 CE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
9207 CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
9208 CE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
9209 CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
9210 CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
9211 CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
9212 CE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
9213 CE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
9214 CE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
9215 CE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
9216 CE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
9217 CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
9218 CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
9219 CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
9220 CE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
9221 CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
9222 CE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
9223 CE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
9224 CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
9225 CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
9226 CE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
9227 CE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
9228 CE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
9229 CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
9230 CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
9231 CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
9232 CE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
9233 CE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
9234 CE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
9235 CE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
9236 CE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
9237 CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
9238 CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
9239 CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
9240 CE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
9241 CE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
9242 CE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
9243 CE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
9244 CE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
9245 CE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
9246 CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9247 CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9248 CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9249 CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9250 CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9251 CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9252 CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9253 CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9254 CE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9255 CE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9256 CE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9257 CE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9260 #undef THUMB_VARIANT
9280 /* MD interface: bits in the object file. */
9282 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9283 for use in the a.out file, and stores them in the array pointed to by buf.
9284 This knows about the endian-ness of the target machine and does
9285 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9286 2 (short) and 4 (long) Floating numbers are put out as a series of
9287 LITTLENUMS (shorts, here at least). */
9290 md_number_to_chars (char * buf, valueT val, int n)
9292 if (target_big_endian)
9293 number_to_chars_bigendian (buf, val, n);
9295 number_to_chars_littleendian (buf, val, n);
9299 md_chars_to_number (char * buf, int n)
9302 unsigned char * where = (unsigned char *) buf;
9304 if (target_big_endian)
9309 result |= (*where++ & 255);
9317 result |= (where[n] & 255);
9324 /* MD interface: Sections. */
9327 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
9328 segT segtype ATTRIBUTE_UNUSED)
9330 as_fatal (_("md_estimate_size_before_relax\n"));
9334 /* Round up a section size to the appropriate boundary. */
9337 md_section_align (segT segment ATTRIBUTE_UNUSED,
9343 /* Round all sects to multiple of 4. */
9344 return (size + 3) & ~3;
9348 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
9349 of an rs_align_code fragment. */
9352 arm_handle_align (fragS * fragP)
9354 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
9355 static char const thumb_noop[2] = { 0xc0, 0x46 };
9356 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
9357 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
9359 int bytes, fix, noop_size;
9363 if (fragP->fr_type != rs_align_code)
9366 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
9367 p = fragP->fr_literal + fragP->fr_fix;
9370 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
9371 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
9373 if (fragP->tc_frag_data)
9375 if (target_big_endian)
9376 noop = thumb_bigend_noop;
9379 noop_size = sizeof (thumb_noop);
9383 if (target_big_endian)
9384 noop = arm_bigend_noop;
9387 noop_size = sizeof (arm_noop);
9390 if (bytes & (noop_size - 1))
9392 fix = bytes & (noop_size - 1);
9398 while (bytes >= noop_size)
9400 memcpy (p, noop, noop_size);
9406 fragP->fr_fix += fix;
9407 fragP->fr_var = noop_size;
9410 /* Called from md_do_align. Used to create an alignment
9411 frag in a code section. */
9414 arm_frag_align_code (int n, int max)
9418 /* We assume that there will never be a requirement
9419 to support alignments greater than 32 bytes. */
9420 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
9421 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
9423 p = frag_var (rs_align_code,
9424 MAX_MEM_FOR_RS_ALIGN_CODE,
9426 (relax_substateT) max,
9433 /* Perform target specific initialisation of a frag. */
9436 arm_init_frag (fragS * fragP)
9438 /* Record whether this frag is in an ARM or a THUMB area. */
9439 fragP->tc_frag_data = thumb_mode;
9443 /* When we change sections we need to issue a new mapping symbol. */
9446 arm_elf_change_section (void)
9449 segment_info_type *seginfo;
9451 /* Link an unlinked unwind index table section to the .text section. */
9452 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
9453 && elf_linked_to_section (now_seg) == NULL)
9454 elf_linked_to_section (now_seg) = text_section;
9456 if (!SEG_NORMAL (now_seg))
9459 flags = bfd_get_section_flags (stdoutput, now_seg);
9461 /* We can ignore sections that only contain debug info. */
9462 if ((flags & SEC_ALLOC) == 0)
9465 seginfo = seg_info (now_seg);
9466 mapstate = seginfo->tc_segment_info_data.mapstate;
9467 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
9471 arm_elf_section_type (const char * str, size_t len)
9473 if (len == 5 && strncmp (str, "exidx", 5) == 0)
9474 return SHT_ARM_EXIDX;
9479 /* Code to deal with unwinding tables. */
9481 static void add_unwind_adjustsp (offsetT);
9483 /* Cenerate and deferred unwind frame offset. */
9486 flush_pending_unwind (void)
9490 offset = unwind.pending_offset;
9491 unwind.pending_offset = 0;
9493 add_unwind_adjustsp (offset);
9496 /* Add an opcode to this list for this function. Two-byte opcodes should
9497 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
9501 add_unwind_opcode (valueT op, int length)
9503 /* Add any deferred stack adjustment. */
9504 if (unwind.pending_offset)
9505 flush_pending_unwind ();
9507 unwind.sp_restored = 0;
9509 if (unwind.opcode_count + length > unwind.opcode_alloc)
9511 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
9513 unwind.opcodes = xrealloc (unwind.opcodes,
9514 unwind.opcode_alloc);
9516 unwind.opcodes = xmalloc (unwind.opcode_alloc);
9521 unwind.opcodes[unwind.opcode_count] = op & 0xff;
9523 unwind.opcode_count++;
9527 /* Add unwind opcodes to adjust the stack pointer. */
9530 add_unwind_adjustsp (offsetT offset)
9536 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
9541 /* Long form: 0xb2, uleb128. */
9542 /* This might not fit in a word so add the individual bytes,
9543 remembering the list is built in reverse order. */
9544 o = (valueT) ((offset - 0x204) >> 2);
9546 add_unwind_opcode (0, 1);
9548 /* Calculate the uleb128 encoding of the offset. */
9552 bytes[n] = o & 0x7f;
9560 add_unwind_opcode (bytes[n - 1], 1);
9561 add_unwind_opcode (0xb2, 1);
9563 else if (offset > 0x100)
9565 /* Two short opcodes. */
9566 add_unwind_opcode (0x3f, 1);
9567 op = (offset - 0x104) >> 2;
9568 add_unwind_opcode (op, 1);
9570 else if (offset > 0)
9573 op = (offset - 4) >> 2;
9574 add_unwind_opcode (op, 1);
9576 else if (offset < 0)
9579 while (offset > 0x100)
9581 add_unwind_opcode (0x7f, 1);
9584 op = ((offset - 4) >> 2) | 0x40;
9585 add_unwind_opcode (op, 1);
9589 /* Finish the list of unwind opcodes for this function. */
9591 finish_unwind_opcodes (void)
9597 /* Adjust sp as neccessary. */
9598 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
9599 flush_pending_unwind ();
9601 /* After restoring sp from the frame pointer. */
9602 op = 0x90 | unwind.fp_reg;
9603 add_unwind_opcode (op, 1);
9606 flush_pending_unwind ();
9610 /* Start an exception table entry. If idx is nonzero this is an index table
9614 start_unwind_section (const segT text_seg, int idx)
9616 const char * text_name;
9617 const char * prefix;
9618 const char * prefix_once;
9619 const char * group_name;
9623 size_t sec_name_len;
9630 prefix = ELF_STRING_ARM_unwind;
9631 prefix_once = ELF_STRING_ARM_unwind_once;
9632 type = SHT_ARM_EXIDX;
9636 prefix = ELF_STRING_ARM_unwind_info;
9637 prefix_once = ELF_STRING_ARM_unwind_info_once;
9638 type = SHT_PROGBITS;
9641 text_name = segment_name (text_seg);
9642 if (streq (text_name, ".text"))
9645 if (strncmp (text_name, ".gnu.linkonce.t.",
9646 strlen (".gnu.linkonce.t.")) == 0)
9648 prefix = prefix_once;
9649 text_name += strlen (".gnu.linkonce.t.");
9652 prefix_len = strlen (prefix);
9653 text_len = strlen (text_name);
9654 sec_name_len = prefix_len + text_len;
9655 sec_name = xmalloc (sec_name_len + 1);
9656 memcpy (sec_name, prefix, prefix_len);
9657 memcpy (sec_name + prefix_len, text_name, text_len);
9658 sec_name[prefix_len + text_len] = '\0';
9664 /* Handle COMDAT group. */
9665 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
9667 group_name = elf_group_name (text_seg);
9668 if (group_name == NULL)
9670 as_bad ("Group section `%s' has no group signature",
9671 segment_name (text_seg));
9672 ignore_rest_of_line ();
9679 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
9681 /* Set the setion link for index tables. */
9683 elf_linked_to_section (now_seg) = text_seg;
9687 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
9688 personality routine data. Returns zero, or the index table value for
9689 and inline entry. */
9692 create_unwind_entry (int have_data)
9697 /* The current word of data. */
9699 /* The number of bytes left in this word. */
9702 finish_unwind_opcodes ();
9704 /* Remember the current text section. */
9705 unwind.saved_seg = now_seg;
9706 unwind.saved_subseg = now_subseg;
9708 start_unwind_section (now_seg, 0);
9710 if (unwind.personality_routine == NULL)
9712 if (unwind.personality_index == -2)
9715 as_bad (_("handerdata in cantunwind frame"));
9716 return 1; /* EXIDX_CANTUNWIND. */
9719 /* Use a default personality routine if none is specified. */
9720 if (unwind.personality_index == -1)
9722 if (unwind.opcode_count > 3)
9723 unwind.personality_index = 1;
9725 unwind.personality_index = 0;
9728 /* Space for the personality routine entry. */
9729 if (unwind.personality_index == 0)
9731 if (unwind.opcode_count > 3)
9732 as_bad (_("too many unwind opcodes for personality routine 0"));
9736 /* All the data is inline in the index table. */
9739 while (unwind.opcode_count > 0)
9741 unwind.opcode_count--;
9742 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
9746 /* Pad with "finish" opcodes. */
9748 data = (data << 8) | 0xb0;
9755 /* We get two opcodes "free" in the first word. */
9756 size = unwind.opcode_count - 2;
9759 /* An extra byte is required for the opcode count. */
9760 size = unwind.opcode_count + 1;
9762 size = (size + 3) >> 2;
9764 as_bad (_("too many unwind opcodes"));
9766 frag_align (2, 0, 0);
9767 record_alignment (now_seg, 2);
9768 unwind.table_entry = expr_build_dot ();
9770 /* Allocate the table entry. */
9771 ptr = frag_more ((size << 2) + 4);
9772 where = frag_now_fix () - ((size << 2) + 4);
9774 switch (unwind.personality_index)
9777 /* ??? Should this be a PLT generating relocation? */
9778 /* Custom personality routine. */
9779 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
9780 BFD_RELOC_ARM_PREL31);
9785 /* Set the first byte to the number of additional words. */
9790 /* ABI defined personality routines. */
9792 /* Three opcodes bytes are packed into the first word. */
9799 /* The size and first two opcode bytes go in the first word. */
9800 data = ((0x80 + unwind.personality_index) << 8) | size;
9805 /* Should never happen. */
9809 /* Pack the opcodes into words (MSB first), reversing the list at the same
9811 while (unwind.opcode_count > 0)
9815 md_number_to_chars (ptr, data, 4);
9820 unwind.opcode_count--;
9822 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
9825 /* Finish off the last word. */
9828 /* Pad with "finish" opcodes. */
9830 data = (data << 8) | 0xb0;
9832 md_number_to_chars (ptr, data, 4);
9837 /* Add an empty descriptor if there is no user-specified data. */
9838 ptr = frag_more (4);
9839 md_number_to_chars (ptr, 0, 4);
9845 /* Convert REGNAME to a DWARF-2 register number. */
9848 tc_arm_regname_to_dw2regnum (const char *regname)
9850 int reg = arm_reg_parse ((char **) ®name, REG_TYPE_RN);
9858 /* Initialize the DWARF-2 unwind information for this procedure. */
9861 tc_arm_frame_initial_instructions (void)
9863 cfi_add_CFA_def_cfa (REG_SP, 0);
9865 #endif /* OBJ_ELF */
9868 /* MD interface: Symbol and relocation handling. */
9870 /* The knowledge of the PC's pipeline offset is built into the insns
9874 md_pcrel_from (fixS * fixP)
9877 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
9878 && fixP->fx_subsy == NULL)
9881 /* PC relative addressing on the Thumb is slightly odd as the bottom
9882 two bits of the PC are forced to zero for the calculation. This
9883 happens *after* application of the pipeline offset. However,
9884 Thumb adrl already adjusts for this, so we need not do it again. */
9885 switch (fixP->fx_r_type)
9887 case BFD_RELOC_ARM_THUMB_ADD:
9888 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
9890 case BFD_RELOC_ARM_THUMB_OFFSET:
9891 case BFD_RELOC_ARM_T32_OFFSET_IMM:
9892 return (fixP->fx_where + fixP->fx_frag->fr_address + 4) & ~3;
9899 /* The pattern was adjusted to accommodate CE's off-by-one fixups,
9900 so we un-adjust here to compensate for the accommodation. */
9901 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
9903 return fixP->fx_where + fixP->fx_frag->fr_address;
9907 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
9908 Otherwise we have no need to default values of symbols. */
9911 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
9914 if (name[0] == '_' && name[1] == 'G'
9915 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
9919 if (symbol_find (name))
9920 as_bad ("GOT already in the symbol table");
9922 GOT_symbol = symbol_new (name, undefined_section,
9923 (valueT) 0, & zero_address_frag);
9933 /* Subroutine of md_apply_fix3. Check to see if an immediate can be
9934 computed as two separate immediate values, added together. We
9935 already know that this value cannot be computed by just one ARM
9939 validate_immediate_twopart (unsigned int val,
9940 unsigned int * highpart)
9945 for (i = 0; i < 32; i += 2)
9946 if (((a = rotate_left (val, i)) & 0xff) != 0)
9952 * highpart = (a >> 8) | ((i + 24) << 7);
9954 else if (a & 0xff0000)
9958 * highpart = (a >> 16) | ((i + 16) << 7);
9962 assert (a & 0xff000000);
9963 * highpart = (a >> 24) | ((i + 8) << 7);
9966 return (a & 0xff) | (i << 7);
9973 validate_offset_imm (unsigned int val, int hwse)
9975 if ((hwse && val > 255) || val > 4095)
9980 /* Subroutine of md_apply_fix3. Do those data_ops which can take a
9981 negative immediate constant by altering the instruction. A bit of
9986 by inverting the second operand, and
9989 by negating the second operand. */
9992 negate_data_op (unsigned long * instruction,
9993 unsigned long value)
9996 unsigned long negated, inverted;
9998 negated = encode_arm_immediate (-value);
9999 inverted = encode_arm_immediate (~value);
10001 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
10004 /* First negates. */
10005 case OPCODE_SUB: /* ADD <-> SUB */
10006 new_inst = OPCODE_ADD;
10011 new_inst = OPCODE_SUB;
10015 case OPCODE_CMP: /* CMP <-> CMN */
10016 new_inst = OPCODE_CMN;
10021 new_inst = OPCODE_CMP;
10025 /* Now Inverted ops. */
10026 case OPCODE_MOV: /* MOV <-> MVN */
10027 new_inst = OPCODE_MVN;
10032 new_inst = OPCODE_MOV;
10036 case OPCODE_AND: /* AND <-> BIC */
10037 new_inst = OPCODE_BIC;
10042 new_inst = OPCODE_AND;
10046 case OPCODE_ADC: /* ADC <-> SBC */
10047 new_inst = OPCODE_SBC;
10052 new_inst = OPCODE_ADC;
10056 /* We cannot do anything. */
10061 if (value == (unsigned) FAIL)
10064 *instruction &= OPCODE_MASK;
10065 *instruction |= new_inst << DATA_OP_SHIFT;
10070 md_apply_fix3 (fixS * fixP,
10074 offsetT value = * valP;
10076 unsigned int newimm;
10077 unsigned long temp;
10079 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
10081 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
10083 /* Note whether this will delete the relocation. */
10084 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
10087 /* If this symbol is in a different section then we need to leave it for
10088 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
10089 so we have to undo its effects here. */
10090 if (fixP->fx_pcrel)
10092 if (fixP->fx_addsy != NULL
10093 && S_IS_DEFINED (fixP->fx_addsy)
10094 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
10095 value += md_pcrel_from (fixP);
10098 /* On a 64-bit host, silently truncate 'value' to 32 bits for
10099 consistency with the behavior on 32-bit hosts. Remember value
10101 value &= 0xffffffff;
10102 value ^= 0x80000000;
10103 value -= 0x80000000;
10106 fixP->fx_addnumber = value;
10108 /* Same treatment for fixP->fx_offset. */
10109 fixP->fx_offset &= 0xffffffff;
10110 fixP->fx_offset ^= 0x80000000;
10111 fixP->fx_offset -= 0x80000000;
10113 switch (fixP->fx_r_type)
10115 case BFD_RELOC_NONE:
10116 /* This will need to go in the object file. */
10120 case BFD_RELOC_ARM_IMMEDIATE:
10121 /* We claim that this fixup has been processed here,
10122 even if in fact we generate an error because we do
10123 not have a reloc for it, so tc_gen_reloc will reject it. */
10127 && ! S_IS_DEFINED (fixP->fx_addsy))
10129 as_bad_where (fixP->fx_file, fixP->fx_line,
10130 _("undefined symbol %s used as an immediate value"),
10131 S_GET_NAME (fixP->fx_addsy));
10135 newimm = encode_arm_immediate (value);
10136 temp = md_chars_to_number (buf, INSN_SIZE);
10138 /* If the instruction will fail, see if we can fix things up by
10139 changing the opcode. */
10140 if (newimm == (unsigned int) FAIL
10141 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
10143 as_bad_where (fixP->fx_file, fixP->fx_line,
10144 _("invalid constant (%lx) after fixup"),
10145 (unsigned long) value);
10149 newimm |= (temp & 0xfffff000);
10150 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
10153 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
10155 unsigned int highpart = 0;
10156 unsigned int newinsn = 0xe1a00000; /* nop. */
10158 newimm = encode_arm_immediate (value);
10159 temp = md_chars_to_number (buf, INSN_SIZE);
10161 /* If the instruction will fail, see if we can fix things up by
10162 changing the opcode. */
10163 if (newimm == (unsigned int) FAIL
10164 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
10166 /* No ? OK - try using two ADD instructions to generate
10168 newimm = validate_immediate_twopart (value, & highpart);
10170 /* Yes - then make sure that the second instruction is
10172 if (newimm != (unsigned int) FAIL)
10174 /* Still No ? Try using a negated value. */
10175 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
10176 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
10177 /* Otherwise - give up. */
10180 as_bad_where (fixP->fx_file, fixP->fx_line,
10181 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
10186 /* Replace the first operand in the 2nd instruction (which
10187 is the PC) with the destination register. We have
10188 already added in the PC in the first instruction and we
10189 do not want to do it again. */
10190 newinsn &= ~ 0xf0000;
10191 newinsn |= ((newinsn & 0x0f000) << 4);
10194 newimm |= (temp & 0xfffff000);
10195 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
10197 highpart |= (newinsn & 0xfffff000);
10198 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
10202 case BFD_RELOC_ARM_OFFSET_IMM:
10203 case BFD_RELOC_ARM_LITERAL:
10209 if (validate_offset_imm (value, 0) == FAIL)
10211 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
10212 as_bad_where (fixP->fx_file, fixP->fx_line,
10213 _("invalid literal constant: pool needs to be closer"));
10215 as_bad_where (fixP->fx_file, fixP->fx_line,
10216 _("bad immediate value for offset (%ld)"),
10221 newval = md_chars_to_number (buf, INSN_SIZE);
10222 newval &= 0xff7ff000;
10223 newval |= value | (sign ? INDEX_UP : 0);
10224 md_number_to_chars (buf, newval, INSN_SIZE);
10227 case BFD_RELOC_ARM_OFFSET_IMM8:
10228 case BFD_RELOC_ARM_HWLITERAL:
10234 if (validate_offset_imm (value, 1) == FAIL)
10236 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
10237 as_bad_where (fixP->fx_file, fixP->fx_line,
10238 _("invalid literal constant: pool needs to be closer"));
10240 as_bad (_("bad immediate value for half-word offset (%ld)"),
10245 newval = md_chars_to_number (buf, INSN_SIZE);
10246 newval &= 0xff7ff0f0;
10247 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
10248 md_number_to_chars (buf, newval, INSN_SIZE);
10251 case BFD_RELOC_ARM_T32_OFFSET_U8:
10252 if (value < 0 || value > 1020 || value % 4 != 0)
10253 as_bad_where (fixP->fx_file, fixP->fx_line,
10254 _("bad immediate value for offset (%ld)"), (long) value);
10257 newval = md_chars_to_number (buf+2, THUMB_SIZE);
10260 md_number_to_chars (buf+2, newval, THUMB_SIZE);
10263 case BFD_RELOC_ARM_T32_OFFSET_IMM:
10264 /* This is a complicated relocation used for all varieties of Thumb32
10265 load/store instruction with immediate offset:
10267 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
10268 *4, optional writeback(W)
10269 (doubleword load/store)
10271 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
10272 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
10273 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
10274 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
10275 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
10277 Uppercase letters indicate bits that are already encoded at
10278 this point. Lowercase letters are our problem. For the
10279 second block of instructions, the secondary opcode nybble
10280 (bits 8..11) is present, and bit 23 is zero, even if this is
10281 a PC-relative operation. */
10282 newval = md_chars_to_number (buf, THUMB_SIZE);
10284 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
10286 if ((newval & 0xf0000000) == 0xe0000000)
10288 /* Doubleword load/store: 8-bit offset, scaled by 4. */
10290 newval |= (1 << 23);
10293 if (value % 4 != 0)
10295 as_bad_where (fixP->fx_file, fixP->fx_line,
10296 _("offset not a multiple of 4"));
10302 as_bad_where (fixP->fx_file, fixP->fx_line,
10303 _("offset out of range"));
10308 else if ((newval & 0x000f0000) == 0x000f0000)
10310 /* PC-relative, 12-bit offset. */
10312 newval |= (1 << 23);
10315 if (value >= 0xfff)
10317 as_bad_where (fixP->fx_file, fixP->fx_line,
10318 _("offset out of range"));
10323 else if ((newval & 0x00000100) == 0x00000100)
10325 /* Writeback: 8-bit, +/- offset. */
10327 newval |= (1 << 9);
10332 as_bad_where (fixP->fx_file, fixP->fx_line,
10333 _("offset out of range"));
10338 else if ((newval & 0x00000f00) == 0x00000e00)
10340 /* T-instruction: positive 8-bit offset. */
10341 if (value < 0 || value >= 0xff)
10343 as_bad_where (fixP->fx_file, fixP->fx_line,
10344 _("offset out of range"));
10352 /* Positive 12-bit or negative 8-bit offset. */
10356 newval |= (1 << 23);
10366 as_bad_where (fixP->fx_file, fixP->fx_line,
10367 _("offset out of range"));
10374 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
10375 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
10378 case BFD_RELOC_ARM_SHIFT_IMM:
10379 newval = md_chars_to_number (buf, INSN_SIZE);
10380 if (((unsigned long) value) > 32
10382 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
10384 as_bad_where (fixP->fx_file, fixP->fx_line,
10385 _("shift expression is too large"));
10390 /* Shifts of zero must be done as lsl. */
10392 else if (value == 32)
10394 newval &= 0xfffff07f;
10395 newval |= (value & 0x1f) << 7;
10396 md_number_to_chars (buf, newval, INSN_SIZE);
10399 case BFD_RELOC_ARM_T32_IMMEDIATE:
10400 /* We claim that this fixup has been processed here,
10401 even if in fact we generate an error because we do
10402 not have a reloc for it, so tc_gen_reloc will reject it. */
10406 && ! S_IS_DEFINED (fixP->fx_addsy))
10408 as_bad_where (fixP->fx_file, fixP->fx_line,
10409 _("undefined symbol %s used as an immediate value"),
10410 S_GET_NAME (fixP->fx_addsy));
10414 newval = md_chars_to_number (buf, THUMB_SIZE);
10416 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
10418 newimm = encode_thumb32_immediate (value);
10420 /* FUTURE: Implement analogue of negate_data_op for T32. */
10421 if (newimm == (unsigned int)FAIL)
10423 as_bad_where (fixP->fx_file, fixP->fx_line,
10424 _("invalid constant (%lx) after fixup"),
10425 (unsigned long) value);
10429 newval &= 0xfbff8f00;
10430 newval |= (newimm & 0x800) << 15;
10431 newval |= (newimm & 0x700) << 4;
10432 newval |= (newimm & 0x0ff);
10434 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
10435 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
10438 case BFD_RELOC_ARM_SMI:
10439 if (((unsigned long) value) > 0xffff)
10440 as_bad_where (fixP->fx_file, fixP->fx_line,
10441 _("invalid smi expression"));
10442 newval = md_chars_to_number (buf, INSN_SIZE) & 0xfff000f0;
10443 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
10444 md_number_to_chars (buf, newval, INSN_SIZE);
10447 case BFD_RELOC_ARM_SWI:
10448 if (fixP->tc_fix_data != 0)
10450 if (((unsigned long) value) > 0xff)
10451 as_bad_where (fixP->fx_file, fixP->fx_line,
10452 _("invalid swi expression"));
10453 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
10455 md_number_to_chars (buf, newval, THUMB_SIZE);
10459 if (((unsigned long) value) > 0x00ffffff)
10460 as_bad_where (fixP->fx_file, fixP->fx_line,
10461 _("invalid swi expression"));
10462 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
10464 md_number_to_chars (buf, newval, INSN_SIZE);
10468 case BFD_RELOC_ARM_MULTI:
10469 if (((unsigned long) value) > 0xffff)
10470 as_bad_where (fixP->fx_file, fixP->fx_line,
10471 _("invalid expression in load/store multiple"));
10472 newval = value | md_chars_to_number (buf, INSN_SIZE);
10473 md_number_to_chars (buf, newval, INSN_SIZE);
10476 case BFD_RELOC_ARM_PCREL_BRANCH:
10477 newval = md_chars_to_number (buf, INSN_SIZE);
10479 /* Sign-extend a 24-bit number. */
10480 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
10483 value = fixP->fx_offset;
10486 /* We are going to store value (shifted right by two) in the
10487 instruction, in a 24 bit, signed field Thus we need to check
10488 that none of the top 8 bits of the shifted value (top 7 bits of
10489 the unshifted, unsigned value) are set, or that they are all set. */
10490 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
10491 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
10494 /* Normally we would be stuck at this point, since we cannot store
10495 the absolute address that is the destination of the branch in the
10496 24 bits of the branch instruction. If however, we happen to know
10497 that the destination of the branch is in the same section as the
10498 branch instruction itself, then we can compute the relocation for
10499 ourselves and not have to bother the linker with it.
10501 FIXME: The test for OBJ_ELF is only here because I have not
10502 worked out how to do this for OBJ_COFF. */
10503 if (fixP->fx_addsy != NULL
10504 && S_IS_DEFINED (fixP->fx_addsy)
10505 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
10507 /* Get pc relative value to go into the branch. */
10510 /* Permit a backward branch provided that enough bits
10511 are set. Allow a forwards branch, provided that
10512 enough bits are clear. */
10513 if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
10514 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
10518 if (! fixP->fx_done)
10520 as_bad_where (fixP->fx_file, fixP->fx_line,
10521 _("GAS can't handle same-section branch dest >= 0x04000000"));
10525 value += SEXT24 (newval);
10527 if ( (value & ~ ((offsetT) 0xffffff)) != 0
10528 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
10529 as_bad_where (fixP->fx_file, fixP->fx_line,
10530 _("out of range branch"));
10532 if (seg->use_rela_p && !fixP->fx_done)
10534 /* Must unshift the value before storing it in the addend. */
10537 fixP->fx_offset = value;
10539 fixP->fx_addnumber = value;
10540 newval = newval & 0xff000000;
10543 newval = (value & 0x00ffffff) | (newval & 0xff000000);
10544 md_number_to_chars (buf, newval, INSN_SIZE);
10547 case BFD_RELOC_ARM_PCREL_BLX:
10550 newval = md_chars_to_number (buf, INSN_SIZE);
10553 value = fixP->fx_offset;
10555 hbit = (value >> 1) & 1;
10556 value = (value >> 2) & 0x00ffffff;
10557 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
10559 if (seg->use_rela_p && !fixP->fx_done)
10561 /* Must sign-extend and unshift the value before storing
10562 it in the addend. */
10563 value = SEXT24 (value);
10564 value = (value << 2) | hbit;
10566 fixP->fx_offset = value;
10568 fixP->fx_addnumber = value;
10569 newval = newval & 0xfe000000;
10572 newval = value | (newval & 0xfe000000) | (hbit << 24);
10573 md_number_to_chars (buf, newval, INSN_SIZE);
10577 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
10578 newval = md_chars_to_number (buf, THUMB_SIZE);
10580 addressT diff = ((newval & 0x00f8) >> 2) | (newval & 0x0200) >> 3;
10581 /* This one does not have the offset encoded in the pattern. */
10582 value = value + diff - 4;
10583 /* CZB can only branch forward. */
10585 as_bad_where (fixP->fx_file, fixP->fx_line,
10586 _("branch out of range"));
10589 if (seg->use_rela_p && !fixP->fx_done)
10592 fixP->fx_offset = value;
10594 fixP->fx_addnumber = value;
10597 newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3);
10599 md_number_to_chars (buf, newval, THUMB_SIZE);
10602 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
10603 newval = md_chars_to_number (buf, THUMB_SIZE);
10605 addressT diff = (newval & 0xff) << 1;
10610 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
10611 as_bad_where (fixP->fx_file, fixP->fx_line,
10612 _("branch out of range"));
10613 if (seg->use_rela_p && !fixP->fx_done)
10616 fixP->fx_offset = value;
10618 fixP->fx_addnumber = value;
10619 newval = newval & 0xff00;
10622 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
10624 md_number_to_chars (buf, newval, THUMB_SIZE);
10627 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
10628 newval = md_chars_to_number (buf, THUMB_SIZE);
10630 addressT diff = (newval & 0x7ff) << 1;
10635 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
10636 as_bad_where (fixP->fx_file, fixP->fx_line,
10637 _("branch out of range"));
10638 if (seg->use_rela_p && !fixP->fx_done)
10641 fixP->fx_offset = value;
10643 fixP->fx_addnumber = value;
10644 newval = newval & 0xf800;
10647 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
10649 md_number_to_chars (buf, newval, THUMB_SIZE);
10652 case BFD_RELOC_THUMB_PCREL_BRANCH20:
10655 addressT diff, S, J1, J2, lo, hi;
10657 newval = md_chars_to_number (buf, THUMB_SIZE);
10658 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10660 S = !(newval & 0x0400); /* flipped - 0=negative */
10661 hi = (newval & 0x003f);
10662 J1 = (newval2 & 0x2000) >> 13;
10663 J2 = (newval2 & 0x0800) >> 11;
10664 lo = (newval2 & 0x07ff);
10666 diff = ((S << 20) | (J2 << 19) | (J1 << 18) | (hi << 12) | (lo << 1));
10667 diff -= (1 << 20); /* sign extend */
10670 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
10671 as_bad_where (fixP->fx_file, fixP->fx_line,
10672 _("conditional branch out of range"));
10674 newval = newval & 0xfbc0;
10675 newval2 = newval2 & 0xd000;
10676 if (seg->use_rela_p && !fixP->fx_done)
10679 fixP->fx_offset = value;
10681 fixP->fx_addnumber = value;
10685 S = (value & 0x00100000) >> 20;
10686 J2 = (value & 0x00080000) >> 19;
10687 J1 = (value & 0x00040000) >> 18;
10688 hi = (value & 0x0003f000) >> 12;
10689 lo = (value & 0x00000ffe) >> 1;
10691 newval = newval | (S << 10) | hi;
10692 newval2 = newval2 | (J1 << 13) | (J2 << 11) | lo;
10695 md_number_to_chars (buf, newval, THUMB_SIZE);
10696 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10700 case BFD_RELOC_THUMB_PCREL_BLX:
10701 case BFD_RELOC_THUMB_PCREL_BRANCH23:
10706 newval = md_chars_to_number (buf, THUMB_SIZE);
10707 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10708 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
10709 if (diff & 0x400000)
10712 value = fixP->fx_offset;
10716 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
10717 as_bad_where (fixP->fx_file, fixP->fx_line,
10718 _("branch with link out of range"));
10720 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
10721 /* For a BLX instruction, make sure that the relocation is rounded up
10722 to a word boundary. This follows the semantics of the instruction
10723 which specifies that bit 1 of the target address will come from bit
10724 1 of the base address. */
10725 value = (value + 1) & ~ 1;
10727 if (seg->use_rela_p && !fixP->fx_done)
10730 fixP->fx_offset = value;
10732 fixP->fx_addnumber = value;
10733 newval = newval & 0xf800;
10734 newval2 = newval2 & 0xf800;
10738 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
10739 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
10741 md_number_to_chars (buf, newval, THUMB_SIZE);
10742 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10747 if (seg->use_rela_p && !fixP->fx_done)
10749 if (fixP->fx_done || fixP->fx_pcrel)
10750 md_number_to_chars (buf, value, 1);
10754 value = fixP->fx_offset;
10755 md_number_to_chars (buf, value, 1);
10760 case BFD_RELOC_THUMB_PCREL_BRANCH25:
10763 addressT diff, S, I1, I2, lo, hi;
10765 newval = md_chars_to_number (buf, THUMB_SIZE);
10766 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10768 S = (newval & 0x0400) >> 10;
10769 hi = (newval & 0x03ff);
10770 I1 = (newval2 & 0x2000) >> 13;
10771 I2 = (newval2 & 0x0800) >> 11;
10772 lo = (newval2 & 0x07ff);
10778 diff = ((S << 24) | (I1 << 23) | (I2 << 22) | (hi << 12) | (lo << 1));
10779 diff -= (1 << 24); /* sign extend */
10782 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
10783 as_bad_where (fixP->fx_file, fixP->fx_line,
10784 _("branch out of range"));
10786 newval = newval & 0xf800;
10787 newval2 = newval2 & 0xd000;
10788 if (seg->use_rela_p && !fixP->fx_done)
10791 fixP->fx_offset = value;
10793 fixP->fx_addnumber = value;
10797 S = (value & 0x01000000) >> 24;
10798 I1 = (value & 0x00800000) >> 23;
10799 I2 = (value & 0x00400000) >> 22;
10800 hi = (value & 0x003ff000) >> 12;
10801 lo = (value & 0x00000ffe) >> 1;
10806 newval = newval | (S << 10) | hi;
10807 newval2 = newval2 | (I1 << 13) | (I2 << 11) | lo;
10809 md_number_to_chars (buf, newval, THUMB_SIZE);
10810 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10815 if (seg->use_rela_p && !fixP->fx_done)
10817 if (fixP->fx_done || fixP->fx_pcrel)
10818 md_number_to_chars (buf, value, 2);
10822 value = fixP->fx_offset;
10823 md_number_to_chars (buf, value, 2);
10829 case BFD_RELOC_ARM_TLS_GD32:
10830 case BFD_RELOC_ARM_TLS_LE32:
10831 case BFD_RELOC_ARM_TLS_IE32:
10832 case BFD_RELOC_ARM_TLS_LDM32:
10833 case BFD_RELOC_ARM_TLS_LDO32:
10834 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10837 case BFD_RELOC_ARM_GOT32:
10838 case BFD_RELOC_ARM_GOTOFF:
10839 case BFD_RELOC_ARM_TARGET2:
10840 if (seg->use_rela_p && !fixP->fx_done)
10842 md_number_to_chars (buf, 0, 4);
10846 case BFD_RELOC_RVA:
10848 case BFD_RELOC_ARM_TARGET1:
10849 case BFD_RELOC_ARM_ROSEGREL32:
10850 case BFD_RELOC_ARM_SBREL32:
10851 case BFD_RELOC_32_PCREL:
10852 if (seg->use_rela_p && !fixP->fx_done)
10854 if (fixP->fx_done || fixP->fx_pcrel)
10855 md_number_to_chars (buf, value, 4);
10859 value = fixP->fx_offset;
10860 md_number_to_chars (buf, value, 4);
10866 case BFD_RELOC_ARM_PREL31:
10867 if (fixP->fx_done || fixP->fx_pcrel)
10869 newval = md_chars_to_number (buf, 4) & 0x80000000;
10870 if ((value ^ (value >> 1)) & 0x40000000)
10872 as_bad_where (fixP->fx_file, fixP->fx_line,
10873 _("rel31 relocation overflow"));
10875 newval |= value & 0x7fffffff;
10876 md_number_to_chars (buf, newval, 4);
10880 case BFD_RELOC_ARM_PLT32:
10881 /* It appears the instruction is fully prepared at this point. */
10885 case BFD_RELOC_ARM_CP_OFF_IMM:
10886 if (value < -1023 || value > 1023 || (value & 3))
10887 as_bad_where (fixP->fx_file, fixP->fx_line,
10888 _("co-processor offset out of range"));
10893 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
10894 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
10896 newval &= ~WRITE_BACK;
10897 md_number_to_chars (buf, newval, INSN_SIZE);
10900 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
10901 if (value < -255 || value > 255)
10902 as_bad_where (fixP->fx_file, fixP->fx_line,
10903 _("co-processor offset out of range"));
10904 goto cp_off_common;
10906 case BFD_RELOC_ARM_THUMB_OFFSET:
10907 newval = md_chars_to_number (buf, THUMB_SIZE);
10908 /* Exactly what ranges, and where the offset is inserted depends
10909 on the type of instruction, we can establish this from the
10911 switch (newval >> 12)
10913 case 4: /* PC load. */
10914 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
10915 forced to zero for these loads; md_pcrel_from has already
10916 compensated for this. */
10918 as_bad_where (fixP->fx_file, fixP->fx_line,
10919 _("invalid offset, target not word aligned (0x%08lX)"),
10920 (((unsigned int) fixP->fx_frag->fr_address
10921 + (unsigned int) fixP->fx_where) & ~3) + value);
10923 if (value & ~0x3fc)
10924 as_bad_where (fixP->fx_file, fixP->fx_line,
10925 _("invalid offset, value too big (0x%08lX)"),
10928 newval |= value >> 2;
10931 case 9: /* SP load/store. */
10932 if (value & ~0x3fc)
10933 as_bad_where (fixP->fx_file, fixP->fx_line,
10934 _("invalid offset, value too big (0x%08lX)"),
10936 newval |= value >> 2;
10939 case 6: /* Word load/store. */
10941 as_bad_where (fixP->fx_file, fixP->fx_line,
10942 _("invalid offset, value too big (0x%08lX)"),
10944 newval |= value << 4; /* 6 - 2. */
10947 case 7: /* Byte load/store. */
10949 as_bad_where (fixP->fx_file, fixP->fx_line,
10950 _("invalid offset, value too big (0x%08lX)"),
10952 newval |= value << 6;
10955 case 8: /* Halfword load/store. */
10957 as_bad_where (fixP->fx_file, fixP->fx_line,
10958 _("invalid offset, value too big (0x%08lX)"),
10960 newval |= value << 5; /* 6 - 1. */
10964 as_bad_where (fixP->fx_file, fixP->fx_line,
10965 "Unable to process relocation for thumb opcode: %lx",
10966 (unsigned long) newval);
10969 md_number_to_chars (buf, newval, THUMB_SIZE);
10972 case BFD_RELOC_ARM_THUMB_ADD:
10973 /* This is a complicated relocation, since we use it for all of
10974 the following immediate relocations:
10978 9bit ADD/SUB SP word-aligned
10979 10bit ADD PC/SP word-aligned
10981 The type of instruction being processed is encoded in the
10988 newval = md_chars_to_number (buf, THUMB_SIZE);
10990 int rd = (newval >> 4) & 0xf;
10991 int rs = newval & 0xf;
10992 int subtract = !!(newval & 0x8000);
10994 /* Check for HI regs, only very restricted cases allowed:
10995 Adjusting SP, and using PC or SP to get an address. */
10996 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
10997 || (rs > 7 && rs != REG_SP && rs != REG_PC))
10998 as_bad_where (fixP->fx_file, fixP->fx_line,
10999 _("invalid Hi register with immediate"));
11001 /* If value is negative, choose the opposite instruction. */
11005 subtract = !subtract;
11007 as_bad_where (fixP->fx_file, fixP->fx_line,
11008 _("immediate value out of range"));
11013 if (value & ~0x1fc)
11014 as_bad_where (fixP->fx_file, fixP->fx_line,
11015 _("invalid immediate for stack address calculation"));
11016 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
11017 newval |= value >> 2;
11019 else if (rs == REG_PC || rs == REG_SP)
11021 if (subtract || value & ~0x3fc)
11022 as_bad_where (fixP->fx_file, fixP->fx_line,
11023 _("invalid immediate for address calculation (value = 0x%08lX)"),
11024 (unsigned long) value);
11025 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
11027 newval |= value >> 2;
11032 as_bad_where (fixP->fx_file, fixP->fx_line,
11033 _("immediate value out of range"));
11034 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
11035 newval |= (rd << 8) | value;
11040 as_bad_where (fixP->fx_file, fixP->fx_line,
11041 _("immediate value out of range"));
11042 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
11043 newval |= rd | (rs << 3) | (value << 6);
11046 md_number_to_chars (buf, newval, THUMB_SIZE);
11049 case BFD_RELOC_ARM_THUMB_IMM:
11050 newval = md_chars_to_number (buf, THUMB_SIZE);
11051 if (value < 0 || value > 255)
11052 as_bad_where (fixP->fx_file, fixP->fx_line,
11053 _("invalid immediate: %ld is too large"),
11056 md_number_to_chars (buf, newval, THUMB_SIZE);
11059 case BFD_RELOC_ARM_THUMB_SHIFT:
11060 /* 5bit shift value (0..32). LSL cannot take 32. */
11061 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
11062 temp = newval & 0xf800;
11063 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
11064 as_bad_where (fixP->fx_file, fixP->fx_line,
11065 _("invalid shift value: %ld"), (long) value);
11066 /* Shifts of zero must be encoded as LSL. */
11068 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
11069 /* Shifts of 32 are encoded as zero. */
11070 else if (value == 32)
11072 newval |= value << 6;
11073 md_number_to_chars (buf, newval, THUMB_SIZE);
11076 case BFD_RELOC_VTABLE_INHERIT:
11077 case BFD_RELOC_VTABLE_ENTRY:
11081 case BFD_RELOC_UNUSED:
11083 as_bad_where (fixP->fx_file, fixP->fx_line,
11084 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
11088 /* Translate internal representation of relocation info to BFD target
11092 tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
11096 bfd_reloc_code_real_type code;
11098 reloc = xmalloc (sizeof (arelent));
11100 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
11101 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11102 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
11104 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
11106 if (fixp->fx_pcrel == 0)
11107 reloc->addend = fixp->fx_offset;
11109 reloc->addend = fixp->fx_offset = reloc->address;
11110 #else /* OBJ_ELF */
11111 reloc->addend = fixp->fx_offset;
11114 switch (fixp->fx_r_type)
11117 if (fixp->fx_pcrel)
11119 code = BFD_RELOC_8_PCREL;
11124 if (fixp->fx_pcrel)
11126 code = BFD_RELOC_16_PCREL;
11131 if (fixp->fx_pcrel)
11133 code = BFD_RELOC_32_PCREL;
11137 case BFD_RELOC_NONE:
11138 case BFD_RELOC_ARM_PCREL_BRANCH:
11139 case BFD_RELOC_ARM_PCREL_BLX:
11140 case BFD_RELOC_RVA:
11141 case BFD_RELOC_THUMB_PCREL_BRANCH7:
11142 case BFD_RELOC_THUMB_PCREL_BRANCH9:
11143 case BFD_RELOC_THUMB_PCREL_BRANCH12:
11144 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11145 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11146 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11147 case BFD_RELOC_THUMB_PCREL_BLX:
11148 case BFD_RELOC_VTABLE_ENTRY:
11149 case BFD_RELOC_VTABLE_INHERIT:
11150 code = fixp->fx_r_type;
11153 case BFD_RELOC_ARM_LITERAL:
11154 case BFD_RELOC_ARM_HWLITERAL:
11155 /* If this is called then the a literal has
11156 been referenced across a section boundary. */
11157 as_bad_where (fixp->fx_file, fixp->fx_line,
11158 _("literal referenced across section boundary"));
11162 case BFD_RELOC_ARM_GOT32:
11163 case BFD_RELOC_ARM_GOTOFF:
11164 case BFD_RELOC_ARM_PLT32:
11165 case BFD_RELOC_ARM_TARGET1:
11166 case BFD_RELOC_ARM_ROSEGREL32:
11167 case BFD_RELOC_ARM_SBREL32:
11168 case BFD_RELOC_ARM_PREL31:
11169 case BFD_RELOC_ARM_TARGET2:
11170 case BFD_RELOC_ARM_TLS_LE32:
11171 case BFD_RELOC_ARM_TLS_LDO32:
11172 code = fixp->fx_r_type;
11175 case BFD_RELOC_ARM_TLS_GD32:
11176 case BFD_RELOC_ARM_TLS_IE32:
11177 case BFD_RELOC_ARM_TLS_LDM32:
11178 /* BFD will include the symbol's address in the addend.
11179 But we don't want that, so subtract it out again here. */
11180 if (!S_IS_COMMON (fixp->fx_addsy))
11181 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
11182 code = fixp->fx_r_type;
11186 case BFD_RELOC_ARM_IMMEDIATE:
11187 as_bad_where (fixp->fx_file, fixp->fx_line,
11188 _("internal relocation (type: IMMEDIATE) not fixed up"));
11191 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
11192 as_bad_where (fixp->fx_file, fixp->fx_line,
11193 _("ADRL used for a symbol not defined in the same file"));
11196 case BFD_RELOC_ARM_OFFSET_IMM:
11197 if (fixp->fx_addsy != NULL
11198 && !S_IS_DEFINED (fixp->fx_addsy)
11199 && S_IS_LOCAL (fixp->fx_addsy))
11201 as_bad_where (fixp->fx_file, fixp->fx_line,
11202 _("undefined local label `%s'"),
11203 S_GET_NAME (fixp->fx_addsy));
11207 as_bad_where (fixp->fx_file, fixp->fx_line,
11208 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
11215 switch (fixp->fx_r_type)
11217 case BFD_RELOC_NONE: type = "NONE"; break;
11218 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
11219 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
11220 case BFD_RELOC_ARM_SMI: type = "SMI"; break;
11221 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
11222 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
11223 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
11224 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
11225 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
11226 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
11227 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
11228 default: type = _("<unknown>"); break;
11230 as_bad_where (fixp->fx_file, fixp->fx_line,
11231 _("cannot represent %s relocation in this object file format"),
11238 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
11240 && fixp->fx_addsy == GOT_symbol)
11242 code = BFD_RELOC_ARM_GOTPC;
11243 reloc->addend = fixp->fx_offset = reloc->address;
11247 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
11249 if (reloc->howto == NULL)
11251 as_bad_where (fixp->fx_file, fixp->fx_line,
11252 _("cannot represent %s relocation in this object file format"),
11253 bfd_get_reloc_code_name (code));
11257 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
11258 vtable entry to be used in the relocation's section offset. */
11259 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11260 reloc->address = fixp->fx_offset;
11265 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
11268 cons_fix_new_arm (fragS * frag,
11273 bfd_reloc_code_real_type type;
11277 FIXME: @@ Should look at CPU word size. */
11281 type = BFD_RELOC_8;
11284 type = BFD_RELOC_16;
11288 type = BFD_RELOC_32;
11291 type = BFD_RELOC_64;
11295 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
11298 #if defined OBJ_COFF || defined OBJ_ELF
11300 arm_validate_fix (fixS * fixP)
11302 /* If the destination of the branch is a defined symbol which does not have
11303 the THUMB_FUNC attribute, then we must be calling a function which has
11304 the (interfacearm) attribute. We look for the Thumb entry point to that
11305 function and change the branch to refer to that function instead. */
11306 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
11307 && fixP->fx_addsy != NULL
11308 && S_IS_DEFINED (fixP->fx_addsy)
11309 && ! THUMB_IS_FUNC (fixP->fx_addsy))
11311 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
11317 arm_force_relocation (struct fix * fixp)
11319 #if defined (OBJ_COFF) && defined (TE_PE)
11320 if (fixp->fx_r_type == BFD_RELOC_RVA)
11324 if (fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
11325 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
11326 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
11327 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
11331 /* Resolve these relocations even if the symbol is extern or weak. */
11332 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
11333 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
11334 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
11337 return generic_force_reloc (fixp);
11341 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
11342 local labels from being added to the output symbol table when they
11343 are used with the ADRL pseudo op. The ADRL relocation should always
11344 be resolved before the binbary is emitted, so it is safe to say that
11345 it is adjustable. */
11348 arm_fix_adjustable (fixS * fixP)
11350 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
11357 /* Relocations against Thumb function names must be left unadjusted,
11358 so that the linker can use this information to correctly set the
11359 bottom bit of their addresses. The MIPS version of this function
11360 also prevents relocations that are mips-16 specific, but I do not
11361 know why it does this.
11364 There is one other problem that ought to be addressed here, but
11365 which currently is not: Taking the address of a label (rather
11366 than a function) and then later jumping to that address. Such
11367 addresses also ought to have their bottom bit set (assuming that
11368 they reside in Thumb code), but at the moment they will not. */
11371 arm_fix_adjustable (fixS * fixP)
11373 if (fixP->fx_addsy == NULL)
11376 if (THUMB_IS_FUNC (fixP->fx_addsy)
11377 && fixP->fx_subsy == NULL)
11380 /* We need the symbol name for the VTABLE entries. */
11381 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11382 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11385 /* Don't allow symbols to be discarded on GOT related relocs. */
11386 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
11387 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
11388 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
11389 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
11390 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
11391 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
11392 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
11393 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
11394 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
11401 elf32_arm_target_format (void)
11404 return (target_big_endian
11405 ? "elf32-bigarm-symbian"
11406 : "elf32-littlearm-symbian");
11407 #elif defined (TE_VXWORKS)
11408 return (target_big_endian
11409 ? "elf32-bigarm-vxworks"
11410 : "elf32-littlearm-vxworks");
11412 if (target_big_endian)
11413 return "elf32-bigarm";
11415 return "elf32-littlearm";
11420 armelf_frob_symbol (symbolS * symp,
11423 elf_frob_symbol (symp, puntp);
11427 /* MD interface: Finalization. */
11429 /* A good place to do this, although this was probably not intended
11430 for this kind of use. We need to dump the literal pool before
11431 references are made to a null symbol pointer. */
11436 literal_pool * pool;
11438 for (pool = list_of_pools; pool; pool = pool->next)
11440 /* Put it at the end of the relevent section. */
11441 subseg_set (pool->section, pool->sub_section);
11443 arm_elf_change_section ();
11449 /* Adjust the symbol table. This marks Thumb symbols as distinct from
11453 arm_adjust_symtab (void)
11458 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
11460 if (ARM_IS_THUMB (sym))
11462 if (THUMB_IS_FUNC (sym))
11464 /* Mark the symbol as a Thumb function. */
11465 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
11466 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
11467 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
11469 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
11470 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
11472 as_bad (_("%s: unexpected function type: %d"),
11473 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
11475 else switch (S_GET_STORAGE_CLASS (sym))
11478 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
11481 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
11484 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
11492 if (ARM_IS_INTERWORK (sym))
11493 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
11500 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
11502 if (ARM_IS_THUMB (sym))
11504 elf_symbol_type * elf_sym;
11506 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
11507 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
11509 if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
11511 /* If it's a .thumb_func, declare it as so,
11512 otherwise tag label as .code 16. */
11513 if (THUMB_IS_FUNC (sym))
11514 elf_sym->internal_elf_sym.st_info =
11515 ELF_ST_INFO (bind, STT_ARM_TFUNC);
11517 elf_sym->internal_elf_sym.st_info =
11518 ELF_ST_INFO (bind, STT_ARM_16BIT);
11525 /* MD interface: Initialization. */
11528 set_constant_flonums (void)
11532 for (i = 0; i < NUM_FLOAT_VALS; i++)
11533 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
11543 if ( (arm_ops_hsh = hash_new ()) == NULL
11544 || (arm_cond_hsh = hash_new ()) == NULL
11545 || (arm_shift_hsh = hash_new ()) == NULL
11546 || (arm_psr_hsh = hash_new ()) == NULL
11547 || (arm_reg_hsh = hash_new ()) == NULL
11548 || (arm_reloc_hsh = hash_new ()) == NULL)
11549 as_fatal (_("virtual memory exhausted"));
11551 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
11552 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
11553 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
11554 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
11555 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
11556 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
11557 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
11558 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
11559 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
11560 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
11562 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
11563 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
11566 set_constant_flonums ();
11568 /* Set the cpu variant based on the command-line options. We prefer
11569 -mcpu= over -march= if both are set (as for GCC); and we prefer
11570 -mfpu= over any other way of setting the floating point unit.
11571 Use of legacy options with new options are faulted. */
11572 if (legacy_cpu != -1)
11574 if (mcpu_cpu_opt != -1 || march_cpu_opt != -1)
11575 as_bad (_("use of old and new-style options to set CPU type"));
11577 mcpu_cpu_opt = legacy_cpu;
11579 else if (mcpu_cpu_opt == -1)
11580 mcpu_cpu_opt = march_cpu_opt;
11582 if (legacy_fpu != -1)
11584 if (mfpu_opt != -1)
11585 as_bad (_("use of old and new-style options to set FPU type"));
11587 mfpu_opt = legacy_fpu;
11589 else if (mfpu_opt == -1)
11591 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
11592 /* Some environments specify a default FPU. If they don't, infer it
11593 from the processor. */
11594 if (mcpu_fpu_opt != -1)
11595 mfpu_opt = mcpu_fpu_opt;
11597 mfpu_opt = march_fpu_opt;
11599 mfpu_opt = FPU_DEFAULT;
11603 if (mfpu_opt == -1)
11605 if (mcpu_cpu_opt == -1)
11606 mfpu_opt = FPU_DEFAULT;
11607 else if (mcpu_cpu_opt & ARM_EXT_V5)
11608 mfpu_opt = FPU_ARCH_VFP_V2;
11610 mfpu_opt = FPU_ARCH_FPA;
11613 if (mcpu_cpu_opt == -1)
11614 mcpu_cpu_opt = CPU_DEFAULT;
11616 cpu_variant = mcpu_cpu_opt | mfpu_opt;
11618 #if defined OBJ_COFF || defined OBJ_ELF
11620 unsigned int flags = 0;
11622 #if defined OBJ_ELF
11623 flags = meabi_flags;
11625 switch (meabi_flags)
11627 case EF_ARM_EABI_UNKNOWN:
11629 /* Set the flags in the private structure. */
11630 if (uses_apcs_26) flags |= F_APCS26;
11631 if (support_interwork) flags |= F_INTERWORK;
11632 if (uses_apcs_float) flags |= F_APCS_FLOAT;
11633 if (pic_code) flags |= F_PIC;
11634 if ((cpu_variant & FPU_ANY) == FPU_NONE
11635 || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
11636 flags |= F_SOFT_FLOAT;
11638 switch (mfloat_abi_opt)
11640 case ARM_FLOAT_ABI_SOFT:
11641 case ARM_FLOAT_ABI_SOFTFP:
11642 flags |= F_SOFT_FLOAT;
11645 case ARM_FLOAT_ABI_HARD:
11646 if (flags & F_SOFT_FLOAT)
11647 as_bad (_("hard-float conflicts with specified fpu"));
11651 /* Using VFP conventions (even if soft-float). */
11652 if (cpu_variant & FPU_VFP_EXT_NONE)
11653 flags |= F_VFP_FLOAT;
11655 #if defined OBJ_ELF
11656 if (cpu_variant & FPU_ARCH_MAVERICK)
11657 flags |= EF_ARM_MAVERICK_FLOAT;
11660 case EF_ARM_EABI_VER4:
11661 /* No additional flags to set. */
11668 bfd_set_private_flags (stdoutput, flags);
11670 /* We have run out flags in the COFF header to encode the
11671 status of ATPCS support, so instead we create a dummy,
11672 empty, debug section called .arm.atpcs. */
11677 sec = bfd_make_section (stdoutput, ".arm.atpcs");
11681 bfd_set_section_flags
11682 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
11683 bfd_set_section_size (stdoutput, sec, 0);
11684 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
11690 /* Record the CPU type as well. */
11691 switch (cpu_variant & ARM_CPU_MASK)
11694 mach = bfd_mach_arm_2;
11697 case ARM_3: /* Also ARM_250. */
11698 mach = bfd_mach_arm_2a;
11701 case ARM_6: /* Also ARM_7. */
11702 mach = bfd_mach_arm_3;
11706 mach = bfd_mach_arm_unknown;
11710 /* Catch special cases. */
11711 if (cpu_variant & ARM_CEXT_IWMMXT)
11712 mach = bfd_mach_arm_iWMMXt;
11713 else if (cpu_variant & ARM_CEXT_XSCALE)
11714 mach = bfd_mach_arm_XScale;
11715 else if (cpu_variant & ARM_CEXT_MAVERICK)
11716 mach = bfd_mach_arm_ep9312;
11717 else if (cpu_variant & ARM_EXT_V5E)
11718 mach = bfd_mach_arm_5TE;
11719 else if (cpu_variant & ARM_EXT_V5)
11721 if (cpu_variant & ARM_EXT_V4T)
11722 mach = bfd_mach_arm_5T;
11724 mach = bfd_mach_arm_5;
11726 else if (cpu_variant & ARM_EXT_V4)
11728 if (cpu_variant & ARM_EXT_V4T)
11729 mach = bfd_mach_arm_4T;
11731 mach = bfd_mach_arm_4;
11733 else if (cpu_variant & ARM_EXT_V3M)
11734 mach = bfd_mach_arm_3M;
11736 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
11739 /* Command line processing. */
11742 Invocation line includes a switch not recognized by the base assembler.
11743 See if it's a processor-specific option.
11745 This routine is somewhat complicated by the need for backwards
11746 compatibility (since older releases of gcc can't be changed).
11747 The new options try to make the interface as compatible as
11750 New options (supported) are:
11752 -mcpu=<cpu name> Assemble for selected processor
11753 -march=<architecture name> Assemble for selected architecture
11754 -mfpu=<fpu architecture> Assemble for selected FPU.
11755 -EB/-mbig-endian Big-endian
11756 -EL/-mlittle-endian Little-endian
11757 -k Generate PIC code
11758 -mthumb Start in Thumb mode
11759 -mthumb-interwork Code supports ARM/Thumb interworking
11761 For now we will also provide support for:
11763 -mapcs-32 32-bit Program counter
11764 -mapcs-26 26-bit Program counter
11765 -macps-float Floats passed in FP registers
11766 -mapcs-reentrant Reentrant code
11768 (sometime these will probably be replaced with -mapcs=<list of options>
11769 and -matpcs=<list of options>)
11771 The remaining options are only supported for back-wards compatibility.
11772 Cpu variants, the arm part is optional:
11773 -m[arm]1 Currently not supported.
11774 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
11775 -m[arm]3 Arm 3 processor
11776 -m[arm]6[xx], Arm 6 processors
11777 -m[arm]7[xx][t][[d]m] Arm 7 processors
11778 -m[arm]8[10] Arm 8 processors
11779 -m[arm]9[20][tdmi] Arm 9 processors
11780 -mstrongarm[110[0]] StrongARM processors
11781 -mxscale XScale processors
11782 -m[arm]v[2345[t[e]]] Arm architectures
11783 -mall All (except the ARM1)
11785 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
11786 -mfpe-old (No float load/store multiples)
11787 -mvfpxd VFP Single precision
11789 -mno-fpu Disable all floating point instructions
11791 The following CPU names are recognized:
11792 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
11793 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
11794 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
11795 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
11796 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
11797 arm10t arm10e, arm1020t, arm1020e, arm10200e,
11798 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
11802 const char * md_shortopts = "m:k";
11804 #ifdef ARM_BI_ENDIAN
11805 #define OPTION_EB (OPTION_MD_BASE + 0)
11806 #define OPTION_EL (OPTION_MD_BASE + 1)
11808 #if TARGET_BYTES_BIG_ENDIAN
11809 #define OPTION_EB (OPTION_MD_BASE + 0)
11811 #define OPTION_EL (OPTION_MD_BASE + 1)
11815 struct option md_longopts[] =
11818 {"EB", no_argument, NULL, OPTION_EB},
11821 {"EL", no_argument, NULL, OPTION_EL},
11823 {NULL, no_argument, NULL, 0}
11826 size_t md_longopts_size = sizeof (md_longopts);
11828 struct arm_option_table
11830 char *option; /* Option name to match. */
11831 char *help; /* Help information. */
11832 int *var; /* Variable to change. */
11833 int value; /* What to change it to. */
11834 char *deprecated; /* If non-null, print this message. */
11837 struct arm_option_table arm_opts[] =
11839 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
11840 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
11841 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
11842 &support_interwork, 1, NULL},
11843 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
11844 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
11845 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
11847 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
11848 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
11849 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
11850 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
11853 /* These are recognized by the assembler, but have no affect on code. */
11854 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
11855 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
11857 /* DON'T add any new processors to this list -- we want the whole list
11858 to go away... Add them to the processors table instead. */
11859 {"marm1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
11860 {"m1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
11861 {"marm2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
11862 {"m2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
11863 {"marm250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
11864 {"m250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
11865 {"marm3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
11866 {"m3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
11867 {"marm6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
11868 {"m6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
11869 {"marm600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
11870 {"m600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
11871 {"marm610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
11872 {"m610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
11873 {"marm620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
11874 {"m620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
11875 {"marm7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
11876 {"m7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
11877 {"marm70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
11878 {"m70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
11879 {"marm700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
11880 {"m700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
11881 {"marm700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
11882 {"m700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
11883 {"marm710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
11884 {"m710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
11885 {"marm710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
11886 {"m710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
11887 {"marm720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
11888 {"m720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
11889 {"marm7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
11890 {"m7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
11891 {"marm7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
11892 {"m7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
11893 {"marm7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
11894 {"m7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
11895 {"marm7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
11896 {"m7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
11897 {"marm7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
11898 {"m7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
11899 {"marm7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
11900 {"m7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
11901 {"marm7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
11902 {"m7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
11903 {"marm7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
11904 {"m7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
11905 {"marm7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11906 {"m7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11907 {"marm7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11908 {"m7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11909 {"marm710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
11910 {"m710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
11911 {"marm720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
11912 {"m720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
11913 {"marm740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
11914 {"m740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
11915 {"marm8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
11916 {"m8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
11917 {"marm810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
11918 {"m810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
11919 {"marm9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
11920 {"m9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
11921 {"marm9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
11922 {"m9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
11923 {"marm920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
11924 {"m920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
11925 {"marm940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
11926 {"m940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
11927 {"mstrongarm", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
11928 {"mstrongarm110", NULL, &legacy_cpu, ARM_ARCH_V4,
11929 N_("use -mcpu=strongarm110")},
11930 {"mstrongarm1100", NULL, &legacy_cpu, ARM_ARCH_V4,
11931 N_("use -mcpu=strongarm1100")},
11932 {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4,
11933 N_("use -mcpu=strongarm1110")},
11934 {"mxscale", NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
11935 {"miwmmxt", NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
11936 {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
11938 /* Architecture variants -- don't add any more to this list either. */
11939 {"mv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
11940 {"marmv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
11941 {"mv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
11942 {"marmv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
11943 {"mv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
11944 {"marmv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
11945 {"mv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
11946 {"marmv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
11947 {"mv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
11948 {"marmv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
11949 {"mv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
11950 {"marmv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
11951 {"mv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
11952 {"marmv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
11953 {"mv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
11954 {"marmv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
11955 {"mv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
11956 {"marmv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
11958 /* Floating point variants -- don't add any more to this list either. */
11959 {"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
11960 {"mfpa10", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
11961 {"mfpa11", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
11962 {"mno-fpu", NULL, &legacy_fpu, 0,
11963 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
11965 {NULL, NULL, NULL, 0, NULL}
11968 struct arm_cpu_option_table
11972 /* For some CPUs we assume an FPU unless the user explicitly sets
11977 /* This list should, at a minimum, contain all the cpu names
11978 recognized by GCC. */
11979 static struct arm_cpu_option_table arm_cpus[] =
11981 {"all", ARM_ANY, FPU_ARCH_FPA},
11982 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA},
11983 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA},
11984 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA},
11985 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA},
11986 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA},
11987 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA},
11988 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA},
11989 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA},
11990 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA},
11991 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA},
11992 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA},
11993 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA},
11994 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA},
11995 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA},
11996 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA},
11997 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA},
11998 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA},
11999 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA},
12000 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA},
12001 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12002 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA},
12003 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12004 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12005 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA},
12006 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA},
12007 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA},
12008 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA},
12009 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12010 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
12011 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA},
12012 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA},
12013 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA},
12014 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA},
12015 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA},
12016 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA},
12017 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA},
12018 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA},
12019 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA},
12020 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA},
12021 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12022 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12023 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12024 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
12025 /* For V5 or later processors we default to using VFP; but the user
12026 should really set the FPU type explicitly. */
12027 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12028 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12029 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12030 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12031 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12032 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12033 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12034 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12035 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12036 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
12037 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12038 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12039 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
12040 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12041 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12042 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12043 {"arm1136js", ARM_ARCH_V6, FPU_NONE},
12044 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE},
12045 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
12046 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
12047 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2},
12048 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE},
12049 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE},
12050 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2},
12051 /* ??? XSCALE is really an architecture. */
12052 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
12053 /* ??? iwmmxt is not a processor. */
12054 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2},
12055 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
12057 {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK},
12061 struct arm_arch_option_table
12068 /* This list should, at a minimum, contain all the architecture names
12069 recognized by GCC. */
12070 static struct arm_arch_option_table arm_archs[] =
12072 {"all", ARM_ANY, FPU_ARCH_FPA},
12073 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
12074 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
12075 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
12076 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
12077 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
12078 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
12079 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
12080 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
12081 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12082 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
12083 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
12084 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
12085 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
12086 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
12087 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
12088 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
12089 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
12090 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
12091 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
12092 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
12093 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
12094 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
12095 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
12096 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
12097 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
12098 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
12099 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
12103 /* ISA extensions in the co-processor space. */
12104 struct arm_option_value_table
12110 static struct arm_option_value_table arm_extensions[] =
12112 {"maverick", ARM_CEXT_MAVERICK},
12113 {"xscale", ARM_CEXT_XSCALE},
12114 {"iwmmxt", ARM_CEXT_IWMMXT},
12118 /* This list should, at a minimum, contain all the fpu names
12119 recognized by GCC. */
12120 static struct arm_option_value_table arm_fpus[] =
12122 {"softfpa", FPU_NONE},
12123 {"fpe", FPU_ARCH_FPE},
12124 {"fpe2", FPU_ARCH_FPE},
12125 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
12126 {"fpa", FPU_ARCH_FPA},
12127 {"fpa10", FPU_ARCH_FPA},
12128 {"fpa11", FPU_ARCH_FPA},
12129 {"arm7500fe", FPU_ARCH_FPA},
12130 {"softvfp", FPU_ARCH_VFP},
12131 {"softvfp+vfp", FPU_ARCH_VFP_V2},
12132 {"vfp", FPU_ARCH_VFP_V2},
12133 {"vfp9", FPU_ARCH_VFP_V2},
12134 {"vfp10", FPU_ARCH_VFP_V2},
12135 {"vfp10-r0", FPU_ARCH_VFP_V1},
12136 {"vfpxd", FPU_ARCH_VFP_V1xD},
12137 {"arm1020t", FPU_ARCH_VFP_V1},
12138 {"arm1020e", FPU_ARCH_VFP_V2},
12139 {"arm1136jfs", FPU_ARCH_VFP_V2},
12140 {"arm1136jf-s", FPU_ARCH_VFP_V2},
12141 {"maverick", FPU_ARCH_MAVERICK},
12145 static struct arm_option_value_table arm_float_abis[] =
12147 {"hard", ARM_FLOAT_ABI_HARD},
12148 {"softfp", ARM_FLOAT_ABI_SOFTFP},
12149 {"soft", ARM_FLOAT_ABI_SOFT},
12154 /* We only know how to output GNU and ver 4 (AAELF) formats. */
12155 static struct arm_option_value_table arm_eabis[] =
12157 {"gnu", EF_ARM_EABI_UNKNOWN},
12158 {"4", EF_ARM_EABI_VER4},
12163 struct arm_long_option_table
12165 char * option; /* Substring to match. */
12166 char * help; /* Help information. */
12167 int (* func) (char * subopt); /* Function to decode sub-option. */
12168 char * deprecated; /* If non-null, print this message. */
12172 arm_parse_extension (char * str, int * opt_p)
12174 while (str != NULL && *str != 0)
12176 struct arm_option_value_table * opt;
12182 as_bad (_("invalid architectural extension"));
12187 ext = strchr (str, '+');
12190 optlen = ext - str;
12192 optlen = strlen (str);
12196 as_bad (_("missing architectural extension"));
12200 for (opt = arm_extensions; opt->name != NULL; opt++)
12201 if (strncmp (opt->name, str, optlen) == 0)
12203 *opt_p |= opt->value;
12207 if (opt->name == NULL)
12209 as_bad (_("unknown architectural extnsion `%s'"), str);
12220 arm_parse_cpu (char * str)
12222 struct arm_cpu_option_table * opt;
12223 char * ext = strchr (str, '+');
12227 optlen = ext - str;
12229 optlen = strlen (str);
12233 as_bad (_("missing cpu name `%s'"), str);
12237 for (opt = arm_cpus; opt->name != NULL; opt++)
12238 if (strncmp (opt->name, str, optlen) == 0)
12240 mcpu_cpu_opt = opt->value;
12241 mcpu_fpu_opt = opt->default_fpu;
12244 return arm_parse_extension (ext, &mcpu_cpu_opt);
12249 as_bad (_("unknown cpu `%s'"), str);
12254 arm_parse_arch (char * str)
12256 struct arm_arch_option_table *opt;
12257 char *ext = strchr (str, '+');
12261 optlen = ext - str;
12263 optlen = strlen (str);
12267 as_bad (_("missing architecture name `%s'"), str);
12272 for (opt = arm_archs; opt->name != NULL; opt++)
12273 if (streq (opt->name, str))
12275 march_cpu_opt = opt->value;
12276 march_fpu_opt = opt->default_fpu;
12279 return arm_parse_extension (ext, &march_cpu_opt);
12284 as_bad (_("unknown architecture `%s'\n"), str);
12289 arm_parse_fpu (char * str)
12291 struct arm_option_value_table * opt;
12293 for (opt = arm_fpus; opt->name != NULL; opt++)
12294 if (streq (opt->name, str))
12296 mfpu_opt = opt->value;
12300 as_bad (_("unknown floating point format `%s'\n"), str);
12305 arm_parse_float_abi (char * str)
12307 struct arm_option_value_table * opt;
12309 for (opt = arm_float_abis; opt->name != NULL; opt++)
12310 if (streq (opt->name, str))
12312 mfloat_abi_opt = opt->value;
12316 as_bad (_("unknown floating point abi `%s'\n"), str);
12322 arm_parse_eabi (char * str)
12324 struct arm_option_value_table *opt;
12326 for (opt = arm_eabis; opt->name != NULL; opt++)
12327 if (streq (opt->name, str))
12329 meabi_flags = opt->value;
12332 as_bad (_("unknown EABI `%s'\n"), str);
12337 struct arm_long_option_table arm_long_opts[] =
12339 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
12340 arm_parse_cpu, NULL},
12341 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
12342 arm_parse_arch, NULL},
12343 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
12344 arm_parse_fpu, NULL},
12345 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
12346 arm_parse_float_abi, NULL},
12348 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
12349 arm_parse_eabi, NULL},
12351 {NULL, NULL, 0, NULL}
12355 md_parse_option (int c, char * arg)
12357 struct arm_option_table *opt;
12358 struct arm_long_option_table *lopt;
12364 target_big_endian = 1;
12370 target_big_endian = 0;
12375 /* Listing option. Just ignore these, we don't support additional
12380 for (opt = arm_opts; opt->option != NULL; opt++)
12382 if (c == opt->option[0]
12383 && ((arg == NULL && opt->option[1] == 0)
12384 || streq (arg, opt->option + 1)))
12386 #if WARN_DEPRECATED
12387 /* If the option is deprecated, tell the user. */
12388 if (opt->deprecated != NULL)
12389 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
12390 arg ? arg : "", _(opt->deprecated));
12393 if (opt->var != NULL)
12394 *opt->var = opt->value;
12400 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
12402 /* These options are expected to have an argument. */
12403 if (c == lopt->option[0]
12405 && strncmp (arg, lopt->option + 1,
12406 strlen (lopt->option + 1)) == 0)
12408 #if WARN_DEPRECATED
12409 /* If the option is deprecated, tell the user. */
12410 if (lopt->deprecated != NULL)
12411 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
12412 _(lopt->deprecated));
12415 /* Call the sup-option parser. */
12416 return lopt->func (arg + strlen (lopt->option) - 1);
12427 md_show_usage (FILE * fp)
12429 struct arm_option_table *opt;
12430 struct arm_long_option_table *lopt;
12432 fprintf (fp, _(" ARM-specific assembler options:\n"));
12434 for (opt = arm_opts; opt->option != NULL; opt++)
12435 if (opt->help != NULL)
12436 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
12438 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
12439 if (lopt->help != NULL)
12440 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
12444 -EB assemble code for a big-endian cpu\n"));
12449 -EL assemble code for a little-endian cpu\n"));