1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modified by David Taylor (dtaylor@armltd.co.uk)
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 /* Need TARGET_CPU. */
38 #include "dwarf2dbg.h"
41 /* Types of processor to assemble for. */
42 #define ARM_1 0x00000001
43 #define ARM_2 0x00000002
44 #define ARM_3 0x00000004
46 #define ARM_6 0x00000008
47 #define ARM_7 ARM_6 /* Same core instruction set. */
48 #define ARM_8 ARM_6 /* Same core instruction set. */
49 #define ARM_9 ARM_6 /* Same core instruction set. */
50 #define ARM_CPU_MASK 0x0000000f
52 /* The following bitmasks control CPU extensions (ARM7 onwards): */
53 #define ARM_EXT_LONGMUL 0x00000010 /* Allow long multiplies. */
54 #define ARM_EXT_HALFWORD 0x00000020 /* Allow half word loads. */
55 #define ARM_EXT_THUMB 0x00000040 /* Allow BX instruction. */
56 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
57 #define ARM_EXT_V5E 0x00000100 /* "El Segundo". */
58 #define ARM_EXT_XSCALE 0x00000200 /* Allow MIA etc. */
60 /* Architectures are the sum of the base and extensions. */
61 #define ARM_ARCH_V3M ARM_EXT_LONGMUL
62 #define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_HALFWORD)
63 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_THUMB)
64 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
65 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_THUMB)
66 #define ARM_ARCH_V5TE (ARM_ARCH_V5T | ARM_EXT_V5E)
67 #define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_EXT_XSCALE)
69 /* Some useful combinations: */
70 #define ARM_ANY 0x00ffffff
71 #define ARM_2UP (ARM_ANY - ARM_1)
72 #define ARM_ALL ARM_2UP /* Not arm1 only. */
73 #define ARM_3UP 0x00fffffc
74 #define ARM_6UP 0x00fffff8 /* Includes ARM7. */
76 #define FPU_CORE 0x80000000
77 #define FPU_FPA10 0x40000000
78 #define FPU_FPA11 0x40000000
81 /* Some useful combinations. */
82 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
83 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
86 #if defined __XSCALE__
87 #define CPU_DEFAULT (ARM_9 | ARM_ARCH_XSCALE)
90 #define CPU_DEFAULT (ARM_7 | ARM_ARCH_V4T)
92 #define CPU_DEFAULT ARM_ALL
98 #define FPU_DEFAULT FPU_ALL
101 #define streq(a, b) (strcmp (a, b) == 0)
102 #define skip_whitespace(str) while (*(str) == ' ') ++(str)
104 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
105 static int target_oabi = 0;
107 #if defined OBJ_COFF || defined OBJ_ELF
108 /* Flags stored in private area of BFD structure. */
109 static boolean uses_apcs_26 = false;
110 static boolean atpcs = false;
111 static boolean support_interwork = false;
112 static boolean uses_apcs_float = false;
113 static boolean pic_code = false;
116 /* This array holds the chars that always start a comment. If the
117 pre-processor is disabled, these aren't very useful. */
118 CONST char comment_chars[] = "@";
120 /* This array holds the chars that only start a comment at the beginning of
121 a line. If the line seems to have the form '# 123 filename'
122 .line and .file directives will appear in the pre-processed output. */
123 /* Note that input_file.c hand checks for '#' at the beginning of the
124 first line of the input file. This is because the compiler outputs
125 #NO_APP at the beginning of its output. */
126 /* Also note that comments like this one will always work. */
127 CONST char line_comment_chars[] = "#";
129 CONST char line_separator_chars[] = ";";
131 /* Chars that can be used to separate mant
132 from exp in floating point numbers. */
133 CONST char EXP_CHARS[] = "eE";
135 /* Chars that mean this number is a floating point constant. */
139 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
141 /* Prefix characters that indicate the start of an immediate
143 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
146 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
147 symbolS * GOT_symbol;
150 /* Size of relocation record. */
151 CONST int md_reloc_size = 8;
153 /* 0: assemble for ARM,
154 1: assemble for Thumb,
155 2: assemble for Thumb even though target CPU does not support thumb
157 static int thumb_mode = 0;
159 typedef struct arm_fix
167 unsigned long instruction;
172 bfd_reloc_code_real_type type;
189 struct asm_shift_properties
191 enum asm_shift_index index;
192 unsigned long bit_field;
193 unsigned int allows_0 : 1;
194 unsigned int allows_32 : 1;
197 static const struct asm_shift_properties shift_properties [] =
199 { SHIFT_LSL, 0, 1, 0},
200 { SHIFT_LSR, 0x20, 0, 1},
201 { SHIFT_ASR, 0x40, 0, 1},
202 { SHIFT_ROR, 0x60, 0, 0},
203 { SHIFT_RRX, 0x60, 0, 0}
206 struct asm_shift_name
209 const struct asm_shift_properties * properties;
212 static const struct asm_shift_name shift_names [] =
214 { "asl", shift_properties + SHIFT_LSL },
215 { "lsl", shift_properties + SHIFT_LSL },
216 { "lsr", shift_properties + SHIFT_LSR },
217 { "asr", shift_properties + SHIFT_ASR },
218 { "ror", shift_properties + SHIFT_ROR },
219 { "rrx", shift_properties + SHIFT_RRX },
220 { "ASL", shift_properties + SHIFT_LSL },
221 { "LSL", shift_properties + SHIFT_LSL },
222 { "LSR", shift_properties + SHIFT_LSR },
223 { "ASR", shift_properties + SHIFT_ASR },
224 { "ROR", shift_properties + SHIFT_ROR },
225 { "RRX", shift_properties + SHIFT_RRX }
228 #define NO_SHIFT_RESTRICT 1
229 #define SHIFT_RESTRICT 0
231 #define NUM_FLOAT_VALS 8
233 CONST char * fp_const[] =
235 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
238 /* Number of littlenums required to hold an extended precision number. */
239 #define MAX_LITTLENUMS 6
241 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
251 #define CP_T_X 0x00008000
252 #define CP_T_Y 0x00400000
253 #define CP_T_Pre 0x01000000
254 #define CP_T_UD 0x00800000
255 #define CP_T_WB 0x00200000
257 #define CONDS_BIT 0x00100000
258 #define LOAD_BIT 0x00100000
259 #define TRANS_BIT 0x00200000
261 #define DOUBLE_LOAD_FLAG 0x00000001
265 CONST char * template;
269 /* This is to save a hash look-up in the common case. */
270 #define COND_ALWAYS 0xe0000000
272 static CONST struct asm_cond conds[] =
276 {"cs", 0x20000000}, {"hs", 0x20000000},
277 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
292 /* Warning: If the top bit of the set_bits is set, then the standard
293 instruction bitmask is ignored, and the new bitmask is taken from
297 CONST char * template; /* Basic flag string. */
298 unsigned long set_bits; /* Bits to set. */
301 static CONST struct asm_flg s_flag[] =
307 static CONST struct asm_flg ldr_flags[] =
309 {"d", DOUBLE_LOAD_FLAG},
312 {"bt", 0x00400000 | TRANS_BIT},
319 static CONST struct asm_flg str_flags[] =
321 {"d", DOUBLE_LOAD_FLAG},
324 {"bt", 0x00400000 | TRANS_BIT},
329 static CONST struct asm_flg byte_flag[] =
335 static CONST struct asm_flg cmp_flags[] =
342 static CONST struct asm_flg ldm_flags[] =
355 static CONST struct asm_flg stm_flags[] =
368 static CONST struct asm_flg lfm_flags[] =
375 static CONST struct asm_flg sfm_flags[] =
382 static CONST struct asm_flg round_flags[] =
390 /* The implementation of the FIX instruction is broken on some assemblers,
391 in that it accepts a precision specifier as well as a rounding specifier,
392 despite the fact that this is meaningless. To be more compatible, we
393 accept it as well, though of course it does not set any bits. */
394 static CONST struct asm_flg fix_flags[] =
411 static CONST struct asm_flg except_flag[] =
417 static CONST struct asm_flg cplong_flag[] =
425 CONST char * template;
430 /* The bit that distnguishes CPSR and SPSR. */
431 #define SPSR_BIT (1 << 22)
433 /* How many bits to shift the PSR_xxx bits up by. */
436 #define PSR_c (1 << 0)
437 #define PSR_x (1 << 1)
438 #define PSR_s (1 << 2)
439 #define PSR_f (1 << 3)
441 static CONST struct asm_psr psrs[] =
443 {"CPSR", true, PSR_c | PSR_f},
444 {"CPSR_all", true, PSR_c | PSR_f},
445 {"SPSR", false, PSR_c | PSR_f},
446 {"SPSR_all", false, PSR_c | PSR_f},
447 {"CPSR_flg", true, PSR_f},
448 {"CPSR_f", true, PSR_f},
449 {"SPSR_flg", false, PSR_f},
450 {"SPSR_f", false, PSR_f},
451 {"CPSR_c", true, PSR_c},
452 {"CPSR_ctl", true, PSR_c},
453 {"SPSR_c", false, PSR_c},
454 {"SPSR_ctl", false, PSR_c},
455 {"CPSR_x", true, PSR_x},
456 {"CPSR_s", true, PSR_s},
457 {"SPSR_x", false, PSR_x},
458 {"SPSR_s", false, PSR_s},
459 /* Combinations of flags. */
460 {"CPSR_fs", true, PSR_f | PSR_s},
461 {"CPSR_fx", true, PSR_f | PSR_x},
462 {"CPSR_fc", true, PSR_f | PSR_c},
463 {"CPSR_sf", true, PSR_s | PSR_f},
464 {"CPSR_sx", true, PSR_s | PSR_x},
465 {"CPSR_sc", true, PSR_s | PSR_c},
466 {"CPSR_xf", true, PSR_x | PSR_f},
467 {"CPSR_xs", true, PSR_x | PSR_s},
468 {"CPSR_xc", true, PSR_x | PSR_c},
469 {"CPSR_cf", true, PSR_c | PSR_f},
470 {"CPSR_cs", true, PSR_c | PSR_s},
471 {"CPSR_cx", true, PSR_c | PSR_x},
472 {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x},
473 {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c},
474 {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s},
475 {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c},
476 {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s},
477 {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x},
478 {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x},
479 {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c},
480 {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f},
481 {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c},
482 {"CPSR_scf", true, PSR_s | PSR_c | PSR_f},
483 {"CPSR_scx", true, PSR_s | PSR_c | PSR_x},
484 {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s},
485 {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c},
486 {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f},
487 {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c},
488 {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f},
489 {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s},
490 {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s},
491 {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x},
492 {"CPSR_csf", true, PSR_c | PSR_s | PSR_f},
493 {"CPSR_csx", true, PSR_c | PSR_s | PSR_x},
494 {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f},
495 {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s},
496 {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c},
497 {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x},
498 {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c},
499 {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s},
500 {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x},
501 {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s},
502 {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c},
503 {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x},
504 {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c},
505 {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f},
506 {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x},
507 {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f},
508 {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c},
509 {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s},
510 {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c},
511 {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f},
512 {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s},
513 {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f},
514 {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x},
515 {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s},
516 {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x},
517 {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f},
518 {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s},
519 {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f},
520 {"SPSR_fs", false, PSR_f | PSR_s},
521 {"SPSR_fx", false, PSR_f | PSR_x},
522 {"SPSR_fc", false, PSR_f | PSR_c},
523 {"SPSR_sf", false, PSR_s | PSR_f},
524 {"SPSR_sx", false, PSR_s | PSR_x},
525 {"SPSR_sc", false, PSR_s | PSR_c},
526 {"SPSR_xf", false, PSR_x | PSR_f},
527 {"SPSR_xs", false, PSR_x | PSR_s},
528 {"SPSR_xc", false, PSR_x | PSR_c},
529 {"SPSR_cf", false, PSR_c | PSR_f},
530 {"SPSR_cs", false, PSR_c | PSR_s},
531 {"SPSR_cx", false, PSR_c | PSR_x},
532 {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x},
533 {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c},
534 {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s},
535 {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c},
536 {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s},
537 {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x},
538 {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x},
539 {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c},
540 {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f},
541 {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c},
542 {"SPSR_scf", false, PSR_s | PSR_c | PSR_f},
543 {"SPSR_scx", false, PSR_s | PSR_c | PSR_x},
544 {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s},
545 {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c},
546 {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f},
547 {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c},
548 {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f},
549 {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s},
550 {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s},
551 {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x},
552 {"SPSR_csf", false, PSR_c | PSR_s | PSR_f},
553 {"SPSR_csx", false, PSR_c | PSR_s | PSR_x},
554 {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f},
555 {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s},
556 {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c},
557 {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x},
558 {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c},
559 {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s},
560 {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x},
561 {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s},
562 {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c},
563 {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x},
564 {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c},
565 {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f},
566 {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x},
567 {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f},
568 {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c},
569 {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s},
570 {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c},
571 {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f},
572 {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s},
573 {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f},
574 {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x},
575 {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s},
576 {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x},
577 {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f},
578 {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s},
579 {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
582 /* Functions called by parser. */
583 /* ARM instructions. */
584 static void do_arit PARAMS ((char *, unsigned long));
585 static void do_cmp PARAMS ((char *, unsigned long));
586 static void do_mov PARAMS ((char *, unsigned long));
587 static void do_ldst PARAMS ((char *, unsigned long));
588 static void do_ldmstm PARAMS ((char *, unsigned long));
589 static void do_branch PARAMS ((char *, unsigned long));
590 static void do_swi PARAMS ((char *, unsigned long));
591 /* Pseudo Op codes. */
592 static void do_adr PARAMS ((char *, unsigned long));
593 static void do_adrl PARAMS ((char *, unsigned long));
594 static void do_nop PARAMS ((char *, unsigned long));
596 static void do_mul PARAMS ((char *, unsigned long));
597 static void do_mla PARAMS ((char *, unsigned long));
599 static void do_swap PARAMS ((char *, unsigned long));
601 static void do_msr PARAMS ((char *, unsigned long));
602 static void do_mrs PARAMS ((char *, unsigned long));
604 static void do_mull PARAMS ((char *, unsigned long));
606 static void do_bx PARAMS ((char *, unsigned long));
608 /* ARM_EXT_XScale. */
609 static void do_mia PARAMS ((char *, unsigned long));
610 static void do_mar PARAMS ((char *, unsigned long));
611 static void do_mra PARAMS ((char *, unsigned long));
612 static void do_pld PARAMS ((char *, unsigned long));
613 static void do_ldrd PARAMS ((char *, unsigned long));
616 static void do_blx PARAMS ((char *, unsigned long));
617 static void do_bkpt PARAMS ((char *, unsigned long));
618 static void do_clz PARAMS ((char *, unsigned long));
619 static void do_lstc2 PARAMS ((char *, unsigned long));
620 static void do_cdp2 PARAMS ((char *, unsigned long));
621 static void do_co_reg2 PARAMS ((char *, unsigned long));
623 static void do_t_blx PARAMS ((char *));
624 static void do_t_bkpt PARAMS ((char *));
627 static void do_smla PARAMS ((char *, unsigned long));
628 static void do_smlal PARAMS ((char *, unsigned long));
629 static void do_smul PARAMS ((char *, unsigned long));
630 static void do_qadd PARAMS ((char *, unsigned long));
631 static void do_co_reg2c PARAMS ((char *, unsigned long));
633 /* Coprocessor Instructions. */
634 static void do_cdp PARAMS ((char *, unsigned long));
635 static void do_lstc PARAMS ((char *, unsigned long));
636 static void do_co_reg PARAMS ((char *, unsigned long));
637 static void do_fp_ctrl PARAMS ((char *, unsigned long));
638 static void do_fp_ldst PARAMS ((char *, unsigned long));
639 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
640 static void do_fp_dyadic PARAMS ((char *, unsigned long));
641 static void do_fp_monadic PARAMS ((char *, unsigned long));
642 static void do_fp_cmp PARAMS ((char *, unsigned long));
643 static void do_fp_from_reg PARAMS ((char *, unsigned long));
644 static void do_fp_to_reg PARAMS ((char *, unsigned long));
646 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
647 static int arm_reg_parse PARAMS ((char **));
648 static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
649 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
650 static int add_to_lit_pool PARAMS ((void));
651 static unsigned validate_immediate PARAMS ((unsigned));
652 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
653 static int validate_offset_imm PARAMS ((unsigned int, int));
654 static void opcode_select PARAMS ((int));
655 static void end_of_line PARAMS ((char *));
656 static int reg_required_here PARAMS ((char **, int));
657 static int psr_required_here PARAMS ((char **));
658 static int co_proc_number PARAMS ((char **));
659 static int cp_opc_expr PARAMS ((char **, int, int));
660 static int cp_reg_required_here PARAMS ((char **, int));
661 static int fp_reg_required_here PARAMS ((char **, int));
662 static int cp_address_offset PARAMS ((char **));
663 static int cp_address_required_here PARAMS ((char **));
664 static int my_get_float_expression PARAMS ((char **));
665 static int skip_past_comma PARAMS ((char **));
666 static int walk_no_bignums PARAMS ((symbolS *));
667 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
668 static int data_op2 PARAMS ((char **));
669 static int fp_op2 PARAMS ((char **));
670 static long reg_list PARAMS ((char **));
671 static void thumb_load_store PARAMS ((char *, int, int));
672 static int decode_shift PARAMS ((char **, int));
673 static int ldst_extend PARAMS ((char **, int));
674 static void thumb_add_sub PARAMS ((char *, int));
675 static void insert_reg PARAMS ((int));
676 static void thumb_shift PARAMS ((char *, int));
677 static void thumb_mov_compare PARAMS ((char *, int));
678 static void set_constant_flonums PARAMS ((void));
679 static valueT md_chars_to_number PARAMS ((char *, int));
680 static void insert_reg_alias PARAMS ((char *, int));
681 static void output_inst PARAMS ((void));
683 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
686 /* ARM instructions take 4bytes in the object file, Thumb instructions
690 /* LONGEST_INST is the longest basic instruction name without
691 conditions or flags. ARM7M has 4 of length 5. El Segundo
692 has one basic instruction name of length 7 (SMLALxy). */
693 #define LONGEST_INST 7
697 /* Basic string to match. */
698 CONST char * template;
700 /* Basic instruction code. */
703 /* Compulsory suffix that must follow conds. If "", then the
704 instruction is not conditional and must have no suffix. */
705 CONST char * comp_suffix;
707 /* Bits to toggle if flag 'n' set. */
708 CONST struct asm_flg * flags;
710 /* Which CPU variants this exists for. */
711 unsigned long variants;
713 /* Function to call to parse args. */
714 void (* parms) PARAMS ((char *, unsigned long));
717 static CONST struct asm_opcode insns[] =
719 /* Intel XScale extensions to ARM V5 ISA. */
720 {"mia", 0x0e200010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
721 {"miaph", 0x0e280010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
722 {"miabb", 0x0e2c0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
723 {"miabt", 0x0e2d0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
724 {"miatb", 0x0e2e0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
725 {"miatt", 0x0e2f0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
726 {"mar", 0x0c400000, NULL, NULL, ARM_EXT_XSCALE, do_mar},
727 {"mra", 0x0c500000, NULL, NULL, ARM_EXT_XSCALE, do_mra},
728 {"pld", 0xf450f000, "", NULL, ARM_EXT_XSCALE, do_pld},
729 {"ldr", 0x000000d0, NULL, ldr_flags, ARM_ANY, do_ldrd},
730 {"str", 0x000000f0, NULL, str_flags, ARM_ANY, do_ldrd},
732 /* ARM Instructions. */
733 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
734 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
735 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
736 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
737 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
738 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
739 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
740 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
741 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
742 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
743 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
744 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
745 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
746 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
747 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
748 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
749 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
750 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
751 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
752 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
753 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
755 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
756 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
758 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
759 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
763 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
764 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
765 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
767 /* ARM 2 multiplies. */
768 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
769 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
771 /* ARM 3 - swp instructions. */
772 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
774 /* ARM 6 Coprocessor instructions. */
775 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
776 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
777 /* ScottB: our code uses 0x0128f000 for msr.
778 NickC: but this is wrong because the bits 16 through 19 are
779 handled by the PSR_xxx defines above. */
781 /* ARM 7M long multiplies - need signed/unsigned flags! */
782 {"smull", 0x00c00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
783 {"umull", 0x00800090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
784 {"smlal", 0x00e00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
785 {"umlal", 0x00a00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
787 /* ARM THUMB interworking. */
788 {"bx", 0x012fff10, NULL, NULL, ARM_EXT_THUMB, do_bx},
790 /* Floating point instructions. */
791 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
792 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
793 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
794 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
795 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
796 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
797 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
798 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
799 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
800 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
801 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
802 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
803 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
804 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
805 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
806 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
807 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
808 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
809 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
810 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
811 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
812 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
813 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
814 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
815 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
816 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
817 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
818 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
819 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
820 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
821 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
822 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
823 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
824 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
825 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
826 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
827 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
828 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
829 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
830 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
831 be an optional suffix, but part of the instruction. To be compatible,
833 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
834 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
835 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
836 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
838 /* Generic copressor instructions. */
839 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
840 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
841 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
842 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
843 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
845 /* ARM ISA extension 5. */
846 /* Note: blx is actually 2 opcodes, so the .value is set dynamically.
847 And it's sometimes conditional and sometimes not. */
848 {"blx", 0, NULL, NULL, ARM_EXT_V5, do_blx},
849 {"clz", 0x016f0f10, NULL, NULL, ARM_EXT_V5, do_clz},
850 {"bkpt", 0xe1200070, "", NULL, ARM_EXT_V5, do_bkpt},
851 {"ldc2", 0xfc100000, "", cplong_flag, ARM_EXT_V5, do_lstc2},
852 {"stc2", 0xfc000000, "", cplong_flag, ARM_EXT_V5, do_lstc2},
853 {"cdp2", 0xfe000000, "", NULL, ARM_EXT_V5, do_cdp2},
854 {"mcr2", 0xfe000010, "", NULL, ARM_EXT_V5, do_co_reg2},
855 {"mrc2", 0xfe100010, "", NULL, ARM_EXT_V5, do_co_reg2},
857 /* ARM ISA extension 5E, El Segundo. */
858 {"smlabb", 0x01000080, NULL, NULL, ARM_EXT_V5E, do_smla},
859 {"smlatb", 0x010000a0, NULL, NULL, ARM_EXT_V5E, do_smla},
860 {"smlabt", 0x010000c0, NULL, NULL, ARM_EXT_V5E, do_smla},
861 {"smlatt", 0x010000e0, NULL, NULL, ARM_EXT_V5E, do_smla},
863 {"smlawb", 0x01200080, NULL, NULL, ARM_EXT_V5E, do_smla},
864 {"smlawt", 0x012000c0, NULL, NULL, ARM_EXT_V5E, do_smla},
866 {"smlalbb",0x01400080, NULL, NULL, ARM_EXT_V5E, do_smlal},
867 {"smlaltb",0x014000a0, NULL, NULL, ARM_EXT_V5E, do_smlal},
868 {"smlalbt",0x014000c0, NULL, NULL, ARM_EXT_V5E, do_smlal},
869 {"smlaltt",0x014000e0, NULL, NULL, ARM_EXT_V5E, do_smlal},
871 {"smulbb", 0x01600080, NULL, NULL, ARM_EXT_V5E, do_smul},
872 {"smultb", 0x016000a0, NULL, NULL, ARM_EXT_V5E, do_smul},
873 {"smulbt", 0x016000c0, NULL, NULL, ARM_EXT_V5E, do_smul},
874 {"smultt", 0x016000e0, NULL, NULL, ARM_EXT_V5E, do_smul},
876 {"smulwb", 0x012000a0, NULL, NULL, ARM_EXT_V5E, do_smul},
877 {"smulwt", 0x012000e0, NULL, NULL, ARM_EXT_V5E, do_smul},
879 {"qadd", 0x01000050, NULL, NULL, ARM_EXT_V5E, do_qadd},
880 {"qdadd", 0x01400050, NULL, NULL, ARM_EXT_V5E, do_qadd},
881 {"qsub", 0x01200050, NULL, NULL, ARM_EXT_V5E, do_qadd},
882 {"qdsub", 0x01600050, NULL, NULL, ARM_EXT_V5E, do_qadd},
884 {"mcrr", 0x0c400000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
885 {"mrrc", 0x0c500000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
888 /* Defines for various bits that we will want to toggle. */
889 #define INST_IMMEDIATE 0x02000000
890 #define OFFSET_REG 0x02000000
891 #define HWOFFSET_IMM 0x00400000
892 #define SHIFT_BY_REG 0x00000010
893 #define PRE_INDEX 0x01000000
894 #define INDEX_UP 0x00800000
895 #define WRITE_BACK 0x00200000
896 #define LDM_TYPE_2_OR_3 0x00400000
898 #define LITERAL_MASK 0xf000f000
899 #define COND_MASK 0xf0000000
900 #define OPCODE_MASK 0xfe1fffff
901 #define DATA_OP_SHIFT 21
903 /* Codes to distinguish the arithmetic instructions. */
914 #define OPCODE_CMP 10
915 #define OPCODE_CMN 11
916 #define OPCODE_ORR 12
917 #define OPCODE_MOV 13
918 #define OPCODE_BIC 14
919 #define OPCODE_MVN 15
921 static void do_t_nop PARAMS ((char *));
922 static void do_t_arit PARAMS ((char *));
923 static void do_t_add PARAMS ((char *));
924 static void do_t_asr PARAMS ((char *));
925 static void do_t_branch9 PARAMS ((char *));
926 static void do_t_branch12 PARAMS ((char *));
927 static void do_t_branch23 PARAMS ((char *));
928 static void do_t_bx PARAMS ((char *));
929 static void do_t_compare PARAMS ((char *));
930 static void do_t_ldmstm PARAMS ((char *));
931 static void do_t_ldr PARAMS ((char *));
932 static void do_t_ldrb PARAMS ((char *));
933 static void do_t_ldrh PARAMS ((char *));
934 static void do_t_lds PARAMS ((char *));
935 static void do_t_lsl PARAMS ((char *));
936 static void do_t_lsr PARAMS ((char *));
937 static void do_t_mov PARAMS ((char *));
938 static void do_t_push_pop PARAMS ((char *));
939 static void do_t_str PARAMS ((char *));
940 static void do_t_strb PARAMS ((char *));
941 static void do_t_strh PARAMS ((char *));
942 static void do_t_sub PARAMS ((char *));
943 static void do_t_swi PARAMS ((char *));
944 static void do_t_adr PARAMS ((char *));
946 #define T_OPCODE_MUL 0x4340
947 #define T_OPCODE_TST 0x4200
948 #define T_OPCODE_CMN 0x42c0
949 #define T_OPCODE_NEG 0x4240
950 #define T_OPCODE_MVN 0x43c0
952 #define T_OPCODE_ADD_R3 0x1800
953 #define T_OPCODE_SUB_R3 0x1a00
954 #define T_OPCODE_ADD_HI 0x4400
955 #define T_OPCODE_ADD_ST 0xb000
956 #define T_OPCODE_SUB_ST 0xb080
957 #define T_OPCODE_ADD_SP 0xa800
958 #define T_OPCODE_ADD_PC 0xa000
959 #define T_OPCODE_ADD_I8 0x3000
960 #define T_OPCODE_SUB_I8 0x3800
961 #define T_OPCODE_ADD_I3 0x1c00
962 #define T_OPCODE_SUB_I3 0x1e00
964 #define T_OPCODE_ASR_R 0x4100
965 #define T_OPCODE_LSL_R 0x4080
966 #define T_OPCODE_LSR_R 0x40c0
967 #define T_OPCODE_ASR_I 0x1000
968 #define T_OPCODE_LSL_I 0x0000
969 #define T_OPCODE_LSR_I 0x0800
971 #define T_OPCODE_MOV_I8 0x2000
972 #define T_OPCODE_CMP_I8 0x2800
973 #define T_OPCODE_CMP_LR 0x4280
974 #define T_OPCODE_MOV_HR 0x4600
975 #define T_OPCODE_CMP_HR 0x4500
977 #define T_OPCODE_LDR_PC 0x4800
978 #define T_OPCODE_LDR_SP 0x9800
979 #define T_OPCODE_STR_SP 0x9000
980 #define T_OPCODE_LDR_IW 0x6800
981 #define T_OPCODE_STR_IW 0x6000
982 #define T_OPCODE_LDR_IH 0x8800
983 #define T_OPCODE_STR_IH 0x8000
984 #define T_OPCODE_LDR_IB 0x7800
985 #define T_OPCODE_STR_IB 0x7000
986 #define T_OPCODE_LDR_RW 0x5800
987 #define T_OPCODE_STR_RW 0x5000
988 #define T_OPCODE_LDR_RH 0x5a00
989 #define T_OPCODE_STR_RH 0x5200
990 #define T_OPCODE_LDR_RB 0x5c00
991 #define T_OPCODE_STR_RB 0x5400
993 #define T_OPCODE_PUSH 0xb400
994 #define T_OPCODE_POP 0xbc00
996 #define T_OPCODE_BRANCH 0xe7fe
998 static int thumb_reg PARAMS ((char ** str, int hi_lo));
1000 #define THUMB_SIZE 2 /* Size of thumb instruction. */
1001 #define THUMB_REG_LO 0x1
1002 #define THUMB_REG_HI 0x2
1003 #define THUMB_REG_ANY 0x3
1005 #define THUMB_H1 0x0080
1006 #define THUMB_H2 0x0040
1012 #define THUMB_MOVE 0
1013 #define THUMB_COMPARE 1
1015 #define THUMB_LOAD 0
1016 #define THUMB_STORE 1
1018 #define THUMB_PP_PC_LR 0x0100
1020 /* These three are used for immediate shifts, do not alter. */
1021 #define THUMB_WORD 2
1022 #define THUMB_HALFWORD 1
1023 #define THUMB_BYTE 0
1027 /* Basic string to match. */
1028 CONST char * template;
1030 /* Basic instruction code. */
1031 unsigned long value;
1035 /* Which CPU variants this exists for. */
1036 unsigned long variants;
1038 /* Function to call to parse args. */
1039 void (* parms) PARAMS ((char *));
1042 static CONST struct thumb_opcode tinsns[] =
1044 {"adc", 0x4140, 2, ARM_EXT_THUMB, do_t_arit},
1045 {"add", 0x0000, 2, ARM_EXT_THUMB, do_t_add},
1046 {"and", 0x4000, 2, ARM_EXT_THUMB, do_t_arit},
1047 {"asr", 0x0000, 2, ARM_EXT_THUMB, do_t_asr},
1048 {"b", T_OPCODE_BRANCH, 2, ARM_EXT_THUMB, do_t_branch12},
1049 {"beq", 0xd0fe, 2, ARM_EXT_THUMB, do_t_branch9},
1050 {"bne", 0xd1fe, 2, ARM_EXT_THUMB, do_t_branch9},
1051 {"bcs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9},
1052 {"bhs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9},
1053 {"bcc", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
1054 {"bul", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
1055 {"blo", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
1056 {"bmi", 0xd4fe, 2, ARM_EXT_THUMB, do_t_branch9},
1057 {"bpl", 0xd5fe, 2, ARM_EXT_THUMB, do_t_branch9},
1058 {"bvs", 0xd6fe, 2, ARM_EXT_THUMB, do_t_branch9},
1059 {"bvc", 0xd7fe, 2, ARM_EXT_THUMB, do_t_branch9},
1060 {"bhi", 0xd8fe, 2, ARM_EXT_THUMB, do_t_branch9},
1061 {"bls", 0xd9fe, 2, ARM_EXT_THUMB, do_t_branch9},
1062 {"bge", 0xdafe, 2, ARM_EXT_THUMB, do_t_branch9},
1063 {"blt", 0xdbfe, 2, ARM_EXT_THUMB, do_t_branch9},
1064 {"bgt", 0xdcfe, 2, ARM_EXT_THUMB, do_t_branch9},
1065 {"ble", 0xddfe, 2, ARM_EXT_THUMB, do_t_branch9},
1066 {"bal", 0xdefe, 2, ARM_EXT_THUMB, do_t_branch9},
1067 {"bic", 0x4380, 2, ARM_EXT_THUMB, do_t_arit},
1068 {"bl", 0xf7fffffe, 4, ARM_EXT_THUMB, do_t_branch23},
1069 {"blx", 0, 0, ARM_EXT_V5, do_t_blx},
1070 {"bkpt", 0xbe00, 2, ARM_EXT_V5, do_t_bkpt},
1071 {"bx", 0x4700, 2, ARM_EXT_THUMB, do_t_bx},
1072 {"cmn", T_OPCODE_CMN, 2, ARM_EXT_THUMB, do_t_arit},
1073 {"cmp", 0x0000, 2, ARM_EXT_THUMB, do_t_compare},
1074 {"eor", 0x4040, 2, ARM_EXT_THUMB, do_t_arit},
1075 {"ldmia", 0xc800, 2, ARM_EXT_THUMB, do_t_ldmstm},
1076 {"ldr", 0x0000, 2, ARM_EXT_THUMB, do_t_ldr},
1077 {"ldrb", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrb},
1078 {"ldrh", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrh},
1079 {"ldrsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds},
1080 {"ldrsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds},
1081 {"ldsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds},
1082 {"ldsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds},
1083 {"lsl", 0x0000, 2, ARM_EXT_THUMB, do_t_lsl},
1084 {"lsr", 0x0000, 2, ARM_EXT_THUMB, do_t_lsr},
1085 {"mov", 0x0000, 2, ARM_EXT_THUMB, do_t_mov},
1086 {"mul", T_OPCODE_MUL, 2, ARM_EXT_THUMB, do_t_arit},
1087 {"mvn", T_OPCODE_MVN, 2, ARM_EXT_THUMB, do_t_arit},
1088 {"neg", T_OPCODE_NEG, 2, ARM_EXT_THUMB, do_t_arit},
1089 {"orr", 0x4300, 2, ARM_EXT_THUMB, do_t_arit},
1090 {"pop", 0xbc00, 2, ARM_EXT_THUMB, do_t_push_pop},
1091 {"push", 0xb400, 2, ARM_EXT_THUMB, do_t_push_pop},
1092 {"ror", 0x41c0, 2, ARM_EXT_THUMB, do_t_arit},
1093 {"sbc", 0x4180, 2, ARM_EXT_THUMB, do_t_arit},
1094 {"stmia", 0xc000, 2, ARM_EXT_THUMB, do_t_ldmstm},
1095 {"str", 0x0000, 2, ARM_EXT_THUMB, do_t_str},
1096 {"strb", 0x0000, 2, ARM_EXT_THUMB, do_t_strb},
1097 {"strh", 0x0000, 2, ARM_EXT_THUMB, do_t_strh},
1098 {"swi", 0xdf00, 2, ARM_EXT_THUMB, do_t_swi},
1099 {"sub", 0x0000, 2, ARM_EXT_THUMB, do_t_sub},
1100 {"tst", T_OPCODE_TST, 2, ARM_EXT_THUMB, do_t_arit},
1102 {"adr", 0x0000, 2, ARM_EXT_THUMB, do_t_adr},
1103 {"nop", 0x46C0, 2, ARM_EXT_THUMB, do_t_nop}, /* mov r8,r8 */
1112 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
1113 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
1114 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
1120 /* These are the standard names. Users can add aliases with .req. */
1121 static CONST struct reg_entry reg_table[] =
1123 /* Processor Register Numbers. */
1124 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
1125 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
1126 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
1127 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
1128 /* APCS conventions. */
1129 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
1130 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
1131 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
1132 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
1133 /* ATPCS additions to APCS conventions. */
1134 {"wr", 7}, {"v8", 11},
1136 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
1137 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
1138 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
1139 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
1140 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
1141 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
1142 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
1143 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
1144 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
1145 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
1146 /* ATPCS additions to float register names. */
1147 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
1148 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
1149 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
1150 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
1151 /* FIXME: At some point we need to add VFP register names. */
1152 /* Array terminator. */
1156 #define BAD_ARGS _("Bad arguments to instruction")
1157 #define BAD_PC _("r15 not allowed here")
1158 #define BAD_FLAGS _("Instruction should not have flags")
1159 #define BAD_COND _("Instruction is not conditional")
1160 #define ERR_NO_ACCUM _("acc0 expected")
1162 static struct hash_control * arm_ops_hsh = NULL;
1163 static struct hash_control * arm_tops_hsh = NULL;
1164 static struct hash_control * arm_cond_hsh = NULL;
1165 static struct hash_control * arm_shift_hsh = NULL;
1166 static struct hash_control * arm_reg_hsh = NULL;
1167 static struct hash_control * arm_psr_hsh = NULL;
1169 /* This table describes all the machine specific pseudo-ops the assembler
1170 has to support. The fields are:
1171 pseudo-op name without dot
1172 function to call to execute this pseudo-op
1173 Integer arg to pass to the function. */
1175 static void s_req PARAMS ((int));
1176 static void s_align PARAMS ((int));
1177 static void s_bss PARAMS ((int));
1178 static void s_even PARAMS ((int));
1179 static void s_ltorg PARAMS ((int));
1180 static void s_arm PARAMS ((int));
1181 static void s_thumb PARAMS ((int));
1182 static void s_code PARAMS ((int));
1183 static void s_force_thumb PARAMS ((int));
1184 static void s_thumb_func PARAMS ((int));
1185 static void s_thumb_set PARAMS ((int));
1186 static void arm_s_text PARAMS ((int));
1187 static void arm_s_data PARAMS ((int));
1189 static void arm_s_section PARAMS ((int));
1190 static void s_arm_elf_cons PARAMS ((int));
1193 static int my_get_expression PARAMS ((expressionS *, char **));
1195 CONST pseudo_typeS md_pseudo_table[] =
1197 /* Never called becasue '.req' does not start line. */
1198 { "req", s_req, 0 },
1199 { "bss", s_bss, 0 },
1200 { "align", s_align, 0 },
1201 { "arm", s_arm, 0 },
1202 { "thumb", s_thumb, 0 },
1203 { "code", s_code, 0 },
1204 { "force_thumb", s_force_thumb, 0 },
1205 { "thumb_func", s_thumb_func, 0 },
1206 { "thumb_set", s_thumb_set, 0 },
1207 { "even", s_even, 0 },
1208 { "ltorg", s_ltorg, 0 },
1209 { "pool", s_ltorg, 0 },
1210 /* Allow for the effect of section changes. */
1211 { "text", arm_s_text, 0 },
1212 { "data", arm_s_data, 0 },
1214 { "section", arm_s_section, 0 },
1215 { "section.s", arm_s_section, 0 },
1216 { "sect", arm_s_section, 0 },
1217 { "sect.s", arm_s_section, 0 },
1218 { "word", s_arm_elf_cons, 4 },
1219 { "long", s_arm_elf_cons, 4 },
1220 { "file", dwarf2_directive_file, 0 },
1221 { "loc", dwarf2_directive_loc, 0 },
1225 { "extend", float_cons, 'x' },
1226 { "ldouble", float_cons, 'x' },
1227 { "packed", float_cons, 'p' },
1231 /* Stuff needed to resolve the label ambiguity
1241 symbolS * last_label_seen;
1242 static int label_is_thumb_function_name = false;
1244 /* Literal stuff. */
1246 #define MAX_LITERAL_POOL_SIZE 1024
1248 typedef struct literalS
1250 struct expressionS exp;
1251 struct arm_it * inst;
1254 literalT literals[MAX_LITERAL_POOL_SIZE];
1256 /* Next free entry in the pool. */
1257 int next_literal_pool_place = 0;
1259 /* Next literal pool number. */
1260 int lit_pool_num = 1;
1262 symbolS * current_poolP = NULL;
1269 if (current_poolP == NULL)
1270 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1271 (valueT) 0, &zero_address_frag);
1273 /* Check if this literal value is already in the pool: */
1274 while (lit_count < next_literal_pool_place)
1276 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1277 && inst.reloc.exp.X_op == O_constant
1278 && (literals[lit_count].exp.X_add_number
1279 == inst.reloc.exp.X_add_number)
1280 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1285 if (lit_count == next_literal_pool_place) /* New entry. */
1287 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1289 inst.error = _("Literal Pool Overflow");
1293 literals[next_literal_pool_place].exp = inst.reloc.exp;
1294 lit_count = next_literal_pool_place++;
1297 inst.reloc.exp.X_op = O_symbol;
1298 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1299 inst.reloc.exp.X_add_symbol = current_poolP;
1304 /* Can't use symbol_new here, so have to create a symbol and then at
1305 a later date assign it a value. Thats what these functions do. */
1308 symbol_locate (symbolP, name, segment, valu, frag)
1310 CONST char * name; /* It is copied, the caller can modify. */
1311 segT segment; /* Segment identifier (SEG_<something>). */
1312 valueT valu; /* Symbol value. */
1313 fragS * frag; /* Associated fragment. */
1315 unsigned int name_length;
1316 char * preserved_copy_of_name;
1318 name_length = strlen (name) + 1; /* +1 for \0. */
1319 obstack_grow (¬es, name, name_length);
1320 preserved_copy_of_name = obstack_finish (¬es);
1321 #ifdef STRIP_UNDERSCORE
1322 if (preserved_copy_of_name[0] == '_')
1323 preserved_copy_of_name++;
1326 #ifdef tc_canonicalize_symbol_name
1327 preserved_copy_of_name =
1328 tc_canonicalize_symbol_name (preserved_copy_of_name);
1331 S_SET_NAME (symbolP, preserved_copy_of_name);
1333 S_SET_SEGMENT (symbolP, segment);
1334 S_SET_VALUE (symbolP, valu);
1335 symbol_clear_list_pointers(symbolP);
1337 symbol_set_frag (symbolP, frag);
1339 /* Link to end of symbol chain. */
1341 extern int symbol_table_frozen;
1342 if (symbol_table_frozen)
1346 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1348 obj_symbol_new_hook (symbolP);
1350 #ifdef tc_symbol_new_hook
1351 tc_symbol_new_hook (symbolP);
1355 verify_symbol_chain (symbol_rootP, symbol_lastP);
1356 #endif /* DEBUG_SYMS */
1359 /* Check that an immediate is valid.
1360 If so, convert it to the right format. */
1363 validate_immediate (val)
1369 #define rotate_left(v, n) (v << n | v >> (32 - n))
1371 for (i = 0; i < 32; i += 2)
1372 if ((a = rotate_left (val, i)) <= 0xff)
1373 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
1378 /* Check to see if an immediate can be computed as two seperate immediate
1379 values, added together. We already know that this value cannot be
1380 computed by just one ARM instruction. */
1383 validate_immediate_twopart (val, highpart)
1385 unsigned int * highpart;
1390 for (i = 0; i < 32; i += 2)
1391 if (((a = rotate_left (val, i)) & 0xff) != 0)
1397 * highpart = (a >> 8) | ((i + 24) << 7);
1399 else if (a & 0xff0000)
1403 * highpart = (a >> 16) | ((i + 16) << 7);
1407 assert (a & 0xff000000);
1408 * highpart = (a >> 24) | ((i + 8) << 7);
1411 return (a & 0xff) | (i << 7);
1418 validate_offset_imm (val, hwse)
1422 if ((hwse && val > 255) || val > 4095)
1429 int a ATTRIBUTE_UNUSED;
1431 as_bad (_("Invalid syntax for .req directive."));
1436 int ignore ATTRIBUTE_UNUSED;
1438 /* We don't support putting frags in the BSS segment, we fake it by
1439 marking in_bss, then looking at s_skip for clues. */
1440 subseg_set (bss_section, 0);
1441 demand_empty_rest_of_line ();
1446 int ignore ATTRIBUTE_UNUSED;
1448 /* Never make frag if expect extra pass. */
1450 frag_align (1, 0, 0);
1452 record_alignment (now_seg, 1);
1454 demand_empty_rest_of_line ();
1459 int ignored ATTRIBUTE_UNUSED;
1464 if (current_poolP == NULL)
1467 /* Align pool as you have word accesses.
1468 Only make a frag if we have to. */
1470 frag_align (2, 0, 0);
1472 record_alignment (now_seg, 2);
1474 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1476 symbol_locate (current_poolP, sym_name, now_seg,
1477 (valueT) frag_now_fix (), frag_now);
1478 symbol_table_insert (current_poolP);
1480 ARM_SET_THUMB (current_poolP, thumb_mode);
1482 #if defined OBJ_COFF || defined OBJ_ELF
1483 ARM_SET_INTERWORK (current_poolP, support_interwork);
1486 while (lit_count < next_literal_pool_place)
1487 /* First output the expression in the instruction to the pool. */
1488 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1490 next_literal_pool_place = 0;
1491 current_poolP = NULL;
1494 /* Same as s_align_ptwo but align 0 => align 2. */
1498 int unused ATTRIBUTE_UNUSED;
1501 register long temp_fill;
1502 long max_alignment = 15;
1504 temp = get_absolute_expression ();
1505 if (temp > max_alignment)
1506 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1509 as_bad (_("Alignment negative. 0 assumed."));
1513 if (*input_line_pointer == ',')
1515 input_line_pointer++;
1516 temp_fill = get_absolute_expression ();
1524 /* Only make a frag if we HAVE to. */
1525 if (temp && !need_pass_2)
1526 frag_align (temp, (int) temp_fill, 0);
1527 demand_empty_rest_of_line ();
1529 record_alignment (now_seg, temp);
1533 s_force_thumb (ignore)
1534 int ignore ATTRIBUTE_UNUSED;
1536 /* If we are not already in thumb mode go into it, EVEN if
1537 the target processor does not support thumb instructions.
1538 This is used by gcc/config/arm/lib1funcs.asm for example
1539 to compile interworking support functions even if the
1540 target processor should not support interworking. */
1545 record_alignment (now_seg, 1);
1548 demand_empty_rest_of_line ();
1552 s_thumb_func (ignore)
1553 int ignore ATTRIBUTE_UNUSED;
1558 /* The following label is the name/address of the start of a Thumb function.
1559 We need to know this for the interworking support. */
1560 label_is_thumb_function_name = true;
1562 demand_empty_rest_of_line ();
1565 /* Perform a .set directive, but also mark the alias as
1566 being a thumb function. */
1572 /* XXX the following is a duplicate of the code for s_set() in read.c
1573 We cannot just call that code as we need to get at the symbol that
1575 register char * name;
1576 register char delim;
1577 register char * end_name;
1578 register symbolS * symbolP;
1580 /* Especial apologies for the random logic:
1581 This just grew, and could be parsed much more simply!
1583 name = input_line_pointer;
1584 delim = get_symbol_end ();
1585 end_name = input_line_pointer;
1590 if (*input_line_pointer != ',')
1593 as_bad (_("Expected comma after name \"%s\""), name);
1595 ignore_rest_of_line ();
1599 input_line_pointer++;
1602 if (name[0] == '.' && name[1] == '\0')
1604 /* XXX - this should not happen to .thumb_set. */
1608 if ((symbolP = symbol_find (name)) == NULL
1609 && (symbolP = md_undefined_symbol (name)) == NULL)
1612 /* When doing symbol listings, play games with dummy fragments living
1613 outside the normal fragment chain to record the file and line info
1615 if (listing & LISTING_SYMBOLS)
1617 extern struct list_info_struct * listing_tail;
1618 fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS));
1620 memset (dummy_frag, 0, sizeof (fragS));
1621 dummy_frag->fr_type = rs_fill;
1622 dummy_frag->line = listing_tail;
1623 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1624 dummy_frag->fr_symbol = symbolP;
1628 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1631 /* "set" symbols are local unless otherwise specified. */
1632 SF_SET_LOCAL (symbolP);
1633 #endif /* OBJ_COFF */
1634 } /* Make a new symbol. */
1636 symbol_table_insert (symbolP);
1641 && S_IS_DEFINED (symbolP)
1642 && S_GET_SEGMENT (symbolP) != reg_section)
1643 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1645 pseudo_set (symbolP);
1647 demand_empty_rest_of_line ();
1649 /* XXX Now we come to the Thumb specific bit of code. */
1651 THUMB_SET_FUNC (symbolP, 1);
1652 ARM_SET_THUMB (symbolP, 1);
1653 #if defined OBJ_ELF || defined OBJ_COFF
1654 ARM_SET_INTERWORK (symbolP, support_interwork);
1658 /* If we change section we must dump the literal pool first. */
1664 if (now_seg != text_section)
1668 obj_elf_text (ignore);
1678 if (flag_readonly_data_in_text)
1680 if (now_seg != text_section)
1683 else if (now_seg != data_section)
1687 obj_elf_data (ignore);
1695 arm_s_section (ignore)
1700 obj_elf_section (ignore);
1705 opcode_select (width)
1713 if (! (cpu_variant & ARM_EXT_THUMB))
1714 as_bad (_("selected processor does not support THUMB opcodes"));
1717 /* No need to force the alignment, since we will have been
1718 coming from ARM mode, which is word-aligned. */
1719 record_alignment (now_seg, 1);
1726 if ((cpu_variant & ARM_ANY) == ARM_EXT_THUMB)
1727 as_bad (_("selected processor does not support ARM opcodes"));
1732 frag_align (2, 0, 0);
1734 record_alignment (now_seg, 1);
1739 as_bad (_("invalid instruction size selected (%d)"), width);
1745 int ignore ATTRIBUTE_UNUSED;
1748 demand_empty_rest_of_line ();
1753 int ignore ATTRIBUTE_UNUSED;
1756 demand_empty_rest_of_line ();
1761 int unused ATTRIBUTE_UNUSED;
1765 temp = get_absolute_expression ();
1770 opcode_select (temp);
1774 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1782 skip_whitespace (str);
1785 inst.error = _("Garbage following instruction");
1789 skip_past_comma (str)
1792 char * p = * str, c;
1795 while ((c = *p) == ' ' || c == ',')
1798 if (c == ',' && comma++)
1806 return comma ? SUCCESS : FAIL;
1809 /* A standard register must be given at this point.
1810 SHIFT is the place to put it in inst.instruction.
1811 Restores input start point on error.
1812 Returns the reg#, or FAIL. */
1815 reg_required_here (str, shift)
1819 static char buff [128]; /* XXX */
1821 char * start = * str;
1823 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1826 inst.instruction |= reg << shift;
1830 /* Restore the start point, we may have got a reg of the wrong class. */
1833 /* In the few cases where we might be able to accept something else
1834 this error can be overridden. */
1835 sprintf (buff, _("Register expected, not '%.100s'"), start);
1841 static CONST struct asm_psr *
1843 register char ** ccp;
1845 char * start = * ccp;
1848 CONST struct asm_psr * psr;
1852 /* Skip to the end of the next word in the input stream. */
1857 while (isalpha (c) || c == '_');
1859 /* Terminate the word. */
1862 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
1863 feature for ease of use and backwards compatibility. */
1864 if (!strncmp (start, "cpsr", 4))
1865 strncpy (start, "CPSR", 4);
1866 else if (!strncmp (start, "spsr", 4))
1867 strncpy (start, "SPSR", 4);
1869 /* Now locate the word in the psr hash table. */
1870 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
1872 /* Restore the input stream. */
1875 /* If we found a valid match, advance the
1876 stream pointer past the end of the word. */
1882 /* Parse the input looking for a PSR flag. */
1885 psr_required_here (str)
1888 char * start = * str;
1889 CONST struct asm_psr * psr;
1891 psr = arm_psr_parse (str);
1895 /* If this is the SPSR that is being modified, set the R bit. */
1897 inst.instruction |= SPSR_BIT;
1899 /* Set the psr flags in the MSR instruction. */
1900 inst.instruction |= psr->field << PSR_SHIFT;
1905 /* In the few cases where we might be able to accept
1906 something else this error can be overridden. */
1907 inst.error = _("flag for {c}psr instruction expected");
1909 /* Restore the start point. */
1915 co_proc_number (str)
1918 int processor, pchar;
1920 skip_whitespace (* str);
1922 /* The data sheet seems to imply that just a number on its own is valid
1923 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1925 if (**str == 'p' || **str == 'P')
1929 if (pchar >= '0' && pchar <= '9')
1931 processor = pchar - '0';
1932 if (**str >= '0' && **str <= '9')
1934 processor = processor * 10 + *(*str)++ - '0';
1937 inst.error = _("Illegal co-processor number");
1944 inst.error = _("Bad or missing co-processor number");
1948 inst.instruction |= processor << 8;
1953 cp_opc_expr (str, where, length)
1960 skip_whitespace (* str);
1962 memset (&expr, '\0', sizeof (expr));
1964 if (my_get_expression (&expr, str))
1966 if (expr.X_op != O_constant)
1968 inst.error = _("bad or missing expression");
1972 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1974 inst.error = _("immediate co-processor expression too large");
1978 inst.instruction |= expr.X_add_number << where;
1983 cp_reg_required_here (str, where)
1988 char * start = *str;
1990 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1993 inst.instruction |= reg << where;
1997 /* In the few cases where we might be able to accept something else
1998 this error can be overridden. */
1999 inst.error = _("Co-processor register expected");
2001 /* Restore the start point. */
2007 fp_reg_required_here (str, where)
2012 char * start = * str;
2014 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
2017 inst.instruction |= reg << where;
2021 /* In the few cases where we might be able to accept something else
2022 this error can be overridden. */
2023 inst.error = _("Floating point register expected");
2025 /* Restore the start point. */
2031 cp_address_offset (str)
2036 skip_whitespace (* str);
2038 if (! is_immediate_prefix (**str))
2040 inst.error = _("immediate expression expected");
2046 if (my_get_expression (& inst.reloc.exp, str))
2049 if (inst.reloc.exp.X_op == O_constant)
2051 offset = inst.reloc.exp.X_add_number;
2055 inst.error = _("co-processor address must be word aligned");
2059 if (offset > 1023 || offset < -1023)
2061 inst.error = _("offset too large");
2066 inst.instruction |= INDEX_UP;
2070 inst.instruction |= offset >> 2;
2073 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
2079 cp_address_required_here (str)
2091 skip_whitespace (p);
2093 if ((reg = reg_required_here (& p, 16)) == FAIL)
2096 skip_whitespace (p);
2102 if (skip_past_comma (& p) == SUCCESS)
2105 write_back = WRITE_BACK;
2109 inst.error = _("pc may not be used in post-increment");
2113 if (cp_address_offset (& p) == FAIL)
2117 pre_inc = PRE_INDEX | INDEX_UP;
2121 /* '['Rn, #expr']'[!] */
2123 if (skip_past_comma (& p) == FAIL)
2125 inst.error = _("pre-indexed expression expected");
2129 pre_inc = PRE_INDEX;
2131 if (cp_address_offset (& p) == FAIL)
2134 skip_whitespace (p);
2138 inst.error = _("missing ]");
2142 skip_whitespace (p);
2148 inst.error = _("pc may not be used with write-back");
2153 write_back = WRITE_BACK;
2159 if (my_get_expression (&inst.reloc.exp, &p))
2162 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
2163 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
2164 inst.reloc.pc_rel = 1;
2165 inst.instruction |= (REG_PC << 16);
2166 pre_inc = PRE_INDEX;
2169 inst.instruction |= write_back | pre_inc;
2177 unsigned long flags;
2179 /* Do nothing really. */
2180 inst.instruction |= flags; /* This is pointless. */
2188 unsigned long flags;
2192 /* Only one syntax. */
2193 skip_whitespace (str);
2195 if (reg_required_here (&str, 12) == FAIL)
2197 inst.error = BAD_ARGS;
2201 if (skip_past_comma (&str) == FAIL)
2203 inst.error = _("comma expected after register name");
2207 skip_whitespace (str);
2209 if ( strcmp (str, "CPSR") == 0
2210 || strcmp (str, "SPSR") == 0
2211 /* Lower case versions for backwards compatability. */
2212 || strcmp (str, "cpsr") == 0
2213 || strcmp (str, "spsr") == 0)
2216 /* This is for backwards compatability with older toolchains. */
2217 else if ( strcmp (str, "cpsr_all") == 0
2218 || strcmp (str, "spsr_all") == 0)
2222 inst.error = _("{C|S}PSR expected");
2226 if (* str == 's' || * str == 'S')
2227 inst.instruction |= SPSR_BIT;
2230 inst.instruction |= flags;
2234 /* Two possible forms:
2235 "{C|S}PSR_<field>, Rm",
2236 "{C|S}PSR_f, #expression". */
2241 unsigned long flags;
2243 skip_whitespace (str);
2245 if (psr_required_here (& str) == FAIL)
2248 if (skip_past_comma (& str) == FAIL)
2250 inst.error = _("comma missing after psr flags");
2254 skip_whitespace (str);
2256 if (reg_required_here (& str, 0) != FAIL)
2259 inst.instruction |= flags;
2264 if (! is_immediate_prefix (* str))
2267 _("only a register or immediate value can follow a psr flag");
2274 if (my_get_expression (& inst.reloc.exp, & str))
2277 _("only a register or immediate value can follow a psr flag");
2281 if ((cpu_variant & ARM_EXT_V5) != ARM_EXT_V5
2282 && inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
2284 inst.error = _("immediate value cannot be used to set this field");
2288 flags |= INST_IMMEDIATE;
2290 if (inst.reloc.exp.X_add_symbol)
2292 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2293 inst.reloc.pc_rel = 0;
2297 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
2299 if (value == (unsigned) FAIL)
2301 inst.error = _("Invalid constant");
2305 inst.instruction |= value;
2309 inst.instruction |= flags;
2313 /* Long Multiply Parser
2314 UMULL RdLo, RdHi, Rm, Rs
2315 SMULL RdLo, RdHi, Rm, Rs
2316 UMLAL RdLo, RdHi, Rm, Rs
2317 SMLAL RdLo, RdHi, Rm, Rs. */
2320 do_mull (str, flags)
2322 unsigned long flags;
2324 int rdlo, rdhi, rm, rs;
2326 /* Only one format "rdlo, rdhi, rm, rs". */
2327 skip_whitespace (str);
2329 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
2331 inst.error = BAD_ARGS;
2335 if (skip_past_comma (&str) == FAIL
2336 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2338 inst.error = BAD_ARGS;
2342 if (skip_past_comma (&str) == FAIL
2343 || (rm = reg_required_here (&str, 0)) == FAIL)
2345 inst.error = BAD_ARGS;
2349 /* rdhi, rdlo and rm must all be different. */
2350 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2351 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2353 if (skip_past_comma (&str) == FAIL
2354 || (rs = reg_required_here (&str, 8)) == FAIL)
2356 inst.error = BAD_ARGS;
2360 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2362 inst.error = BAD_PC;
2366 inst.instruction |= flags;
2374 unsigned long flags;
2378 /* Only one format "rd, rm, rs". */
2379 skip_whitespace (str);
2381 if ((rd = reg_required_here (&str, 16)) == FAIL)
2383 inst.error = BAD_ARGS;
2389 inst.error = BAD_PC;
2393 if (skip_past_comma (&str) == FAIL
2394 || (rm = reg_required_here (&str, 0)) == FAIL)
2396 inst.error = BAD_ARGS;
2402 inst.error = BAD_PC;
2407 as_tsktsk (_("rd and rm should be different in mul"));
2409 if (skip_past_comma (&str) == FAIL
2410 || (rm = reg_required_here (&str, 8)) == FAIL)
2412 inst.error = BAD_ARGS;
2418 inst.error = BAD_PC;
2422 inst.instruction |= flags;
2430 unsigned long flags;
2434 /* Only one format "rd, rm, rs, rn". */
2435 skip_whitespace (str);
2437 if ((rd = reg_required_here (&str, 16)) == FAIL)
2439 inst.error = BAD_ARGS;
2445 inst.error = BAD_PC;
2449 if (skip_past_comma (&str) == FAIL
2450 || (rm = reg_required_here (&str, 0)) == FAIL)
2452 inst.error = BAD_ARGS;
2458 inst.error = BAD_PC;
2463 as_tsktsk (_("rd and rm should be different in mla"));
2465 if (skip_past_comma (&str) == FAIL
2466 || (rd = reg_required_here (&str, 8)) == FAIL
2467 || skip_past_comma (&str) == FAIL
2468 || (rm = reg_required_here (&str, 12)) == FAIL)
2470 inst.error = BAD_ARGS;
2474 if (rd == REG_PC || rm == REG_PC)
2476 inst.error = BAD_PC;
2480 inst.instruction |= flags;
2485 /* Expects *str -> the characters "acc0", possibly with leading blanks.
2486 Advances *str to the next non-alphanumeric.
2487 Returns 0, or else FAIL (in which case sets inst.error).
2489 (In a future XScale, there may be accumulators other than zero.
2490 At that time this routine and its callers can be upgraded to suit.) */
2493 accum0_required_here (str)
2496 static char buff [128]; /* Note the address is taken. Hence, static. */
2499 int result = 0; /* The accum number. */
2501 skip_whitespace (p);
2503 *str = p; /* Advance caller's string pointer too. */
2508 *--p = 0; /* Aap nul into input buffer at non-alnum. */
2510 if (! ( streq (*str, "acc0") || streq (*str, "ACC0")))
2512 sprintf (buff, _("acc0 expected, not '%.100s'"), *str);
2517 *p = c; /* Unzap. */
2518 *str = p; /* Caller's string pointer to after match. */
2522 /* Expects **str -> after a comma. May be leading blanks.
2523 Advances *str, recognizing a load mode, and setting inst.instruction.
2524 Returns rn, or else FAIL (in which case may set inst.error
2525 and not advance str)
2527 Note: doesn't know Rd, so no err checks that require such knowledge. */
2530 ld_mode_required_here (string)
2533 char * str = * string;
2537 skip_whitespace (str);
2543 skip_whitespace (str);
2545 if ((rn = reg_required_here (& str, 16)) == FAIL)
2548 skip_whitespace (str);
2554 if (skip_past_comma (& str) == SUCCESS)
2556 /* [Rn],... (post inc) */
2557 if (ldst_extend (& str, 1) == FAIL)
2562 skip_whitespace (str);
2567 inst.instruction |= WRITE_BACK;
2570 inst.instruction |= INDEX_UP | HWOFFSET_IMM;
2576 if (skip_past_comma (& str) == FAIL)
2578 inst.error = _("pre-indexed expression expected");
2584 if (ldst_extend (& str, 1) == FAIL)
2587 skip_whitespace (str);
2589 if (* str ++ != ']')
2591 inst.error = _("missing ]");
2595 skip_whitespace (str);
2600 inst.instruction |= WRITE_BACK;
2604 else if (* str == '=') /* ldr's "r,=label" syntax */
2605 /* We should never reach here, because <text> = <expression> is
2606 caught gas/read.c read_a_source_file() as a .set operation. */
2608 else /* PC +- 8 bit immediate offset. */
2610 if (my_get_expression (& inst.reloc.exp, & str))
2613 inst.instruction |= HWOFFSET_IMM; /* The I bit. */
2614 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2615 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
2616 inst.reloc.pc_rel = 1;
2617 inst.instruction |= (REG_PC << 16);
2623 inst.instruction |= (pre_inc ? PRE_INDEX : 0);
2629 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
2630 SMLAxy{cond} Rd,Rm,Rs,Rn
2631 SMLAWy{cond} Rd,Rm,Rs,Rn
2632 Error if any register is R15. */
2635 do_smla (str, flags)
2637 unsigned long flags;
2641 skip_whitespace (str);
2643 if ((rd = reg_required_here (& str, 16)) == FAIL
2644 || skip_past_comma (& str) == FAIL
2645 || (rm = reg_required_here (& str, 0)) == FAIL
2646 || skip_past_comma (& str) == FAIL
2647 || (rs = reg_required_here (& str, 8)) == FAIL
2648 || skip_past_comma (& str) == FAIL
2649 || (rn = reg_required_here (& str, 12)) == FAIL)
2650 inst.error = BAD_ARGS;
2652 else if (rd == REG_PC || rm == REG_PC || rs == REG_PC || rn == REG_PC)
2653 inst.error = BAD_PC;
2656 inst.error = BAD_FLAGS;
2662 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
2663 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
2664 Error if any register is R15.
2665 Warning if Rdlo == Rdhi. */
2668 do_smlal (str, flags)
2670 unsigned long flags;
2672 int rdlo, rdhi, rm, rs;
2674 skip_whitespace (str);
2676 if ((rdlo = reg_required_here (& str, 12)) == FAIL
2677 || skip_past_comma (& str) == FAIL
2678 || (rdhi = reg_required_here (& str, 16)) == FAIL
2679 || skip_past_comma (& str) == FAIL
2680 || (rm = reg_required_here (& str, 0)) == FAIL
2681 || skip_past_comma (& str) == FAIL
2682 || (rs = reg_required_here (& str, 8)) == FAIL)
2684 inst.error = BAD_ARGS;
2688 if (rdlo == REG_PC || rdhi == REG_PC || rm == REG_PC || rs == REG_PC)
2690 inst.error = BAD_PC;
2695 as_tsktsk (_("rdhi and rdlo must be different"));
2698 inst.error = BAD_FLAGS;
2703 /* ARM V5E (El Segundo) signed-multiply (argument parse)
2704 SMULxy{cond} Rd,Rm,Rs
2705 Error if any register is R15. */
2708 do_smul (str, flags)
2710 unsigned long flags;
2714 skip_whitespace (str);
2716 if ((rd = reg_required_here (& str, 16)) == FAIL
2717 || skip_past_comma (& str) == FAIL
2718 || (rm = reg_required_here (& str, 0)) == FAIL
2719 || skip_past_comma (& str) == FAIL
2720 || (rs = reg_required_here (& str, 8)) == FAIL)
2721 inst.error = BAD_ARGS;
2723 else if (rd == REG_PC || rm == REG_PC || rs == REG_PC)
2724 inst.error = BAD_PC;
2727 inst.error = BAD_FLAGS;
2733 /* ARM V5E (El Segundo) saturating-add/subtract (argument parse)
2734 Q[D]{ADD,SUB}{cond} Rd,Rm,Rn
2735 Error if any register is R15. */
2738 do_qadd (str, flags)
2740 unsigned long flags;
2744 skip_whitespace (str);
2746 if ((rd = reg_required_here (& str, 12)) == FAIL
2747 || skip_past_comma (& str) == FAIL
2748 || (rm = reg_required_here (& str, 0)) == FAIL
2749 || skip_past_comma (& str) == FAIL
2750 || (rn = reg_required_here (& str, 16)) == FAIL)
2751 inst.error = BAD_ARGS;
2753 else if (rd == REG_PC || rm == REG_PC || rn == REG_PC)
2754 inst.error = BAD_PC;
2757 inst.error = BAD_FLAGS;
2763 /* ARM V5E (el Segundo)
2764 MCRRcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
2765 MRRCcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
2767 These are equivalent to the XScale instructions MAR and MRA,
2768 respectively, when coproc == 0, opcode == 0, and CRm == 0.
2770 Result unpredicatable if Rd or Rn is R15. */
2773 do_co_reg2c (str, flags)
2775 unsigned long flags;
2779 skip_whitespace (str);
2781 if (co_proc_number (& str) == FAIL)
2784 inst.error = BAD_ARGS;
2788 if (skip_past_comma (& str) == FAIL
2789 || cp_opc_expr (& str, 4, 4) == FAIL)
2792 inst.error = BAD_ARGS;
2796 if (skip_past_comma (& str) == FAIL
2797 || (rd = reg_required_here (& str, 12)) == FAIL)
2800 inst.error = BAD_ARGS;
2804 if (skip_past_comma (& str) == FAIL
2805 || (rn = reg_required_here (& str, 16)) == FAIL)
2808 inst.error = BAD_ARGS;
2812 /* Unpredictable result if rd or rn is R15. */
2813 if (rd == REG_PC || rn == REG_PC)
2815 (_("Warning: Instruction unpredictable when using r15"));
2817 if (skip_past_comma (& str) == FAIL
2818 || cp_reg_required_here (& str, 0) == FAIL)
2821 inst.error = BAD_ARGS;
2826 inst.error = BAD_COND;
2831 /* ARM V5 count-leading-zeroes instruction (argument parse)
2832 CLZ{<cond>} <Rd>, <Rm>
2833 Condition defaults to COND_ALWAYS.
2834 Error if Rd or Rm are R15. */
2839 unsigned long flags;
2849 skip_whitespace (str);
2851 if (((rd = reg_required_here (& str, 12)) == FAIL)
2852 || (skip_past_comma (& str) == FAIL)
2853 || ((rm = reg_required_here (& str, 0)) == FAIL))
2854 inst.error = BAD_ARGS;
2856 else if (rd == REG_PC || rm == REG_PC )
2857 inst.error = BAD_PC;
2863 /* ARM V5 (argument parse)
2864 LDC2{L} <coproc>, <CRd>, <addressing mode>
2865 STC2{L} <coproc>, <CRd>, <addressing mode>
2866 Instruction is not conditional, and has 0xf in the codition field.
2867 Otherwise, it's the same as LDC/STC. */
2870 do_lstc2 (str, flags)
2872 unsigned long flags;
2875 inst.error = BAD_COND;
2877 skip_whitespace (str);
2879 if (co_proc_number (& str) == FAIL)
2882 inst.error = BAD_ARGS;
2884 else if (skip_past_comma (& str) == FAIL
2885 || cp_reg_required_here (& str, 12) == FAIL)
2888 inst.error = BAD_ARGS;
2890 else if (skip_past_comma (& str) == FAIL
2891 || cp_address_required_here (& str) == FAIL)
2894 inst.error = BAD_ARGS;
2900 /* ARM V5 (argument parse)
2901 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
2902 Instruction is not conditional, and has 0xf in the condition field.
2903 Otherwise, it's the same as CDP. */
2906 do_cdp2 (str, flags)
2908 unsigned long flags;
2910 skip_whitespace (str);
2912 if (co_proc_number (& str) == FAIL)
2915 inst.error = BAD_ARGS;
2919 if (skip_past_comma (& str) == FAIL
2920 || cp_opc_expr (& str, 20,4) == FAIL)
2923 inst.error = BAD_ARGS;
2927 if (skip_past_comma (& str) == FAIL
2928 || cp_reg_required_here (& str, 12) == FAIL)
2931 inst.error = BAD_ARGS;
2935 if (skip_past_comma (& str) == FAIL
2936 || cp_reg_required_here (& str, 16) == FAIL)
2939 inst.error = BAD_ARGS;
2943 if (skip_past_comma (& str) == FAIL
2944 || cp_reg_required_here (& str, 0) == FAIL)
2947 inst.error = BAD_ARGS;
2951 if (skip_past_comma (& str) == SUCCESS)
2953 if (cp_opc_expr (& str, 5, 3) == FAIL)
2956 inst.error = BAD_ARGS;
2962 inst.error = BAD_FLAGS;
2967 /* ARM V5 (argument parse)
2968 MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
2969 MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
2970 Instruction is not conditional, and has 0xf in the condition field.
2971 Otherwise, it's the same as MCR/MRC. */
2974 do_co_reg2 (str, flags)
2976 unsigned long flags;
2978 skip_whitespace (str);
2980 if (co_proc_number (& str) == FAIL)
2983 inst.error = BAD_ARGS;
2987 if (skip_past_comma (& str) == FAIL
2988 || cp_opc_expr (& str, 21, 3) == FAIL)
2991 inst.error = BAD_ARGS;
2995 if (skip_past_comma (& str) == FAIL
2996 || reg_required_here (& str, 12) == FAIL)
2999 inst.error = BAD_ARGS;
3003 if (skip_past_comma (& str) == FAIL
3004 || cp_reg_required_here (& str, 16) == FAIL)
3007 inst.error = BAD_ARGS;
3011 if (skip_past_comma (& str) == FAIL
3012 || cp_reg_required_here (& str, 0) == FAIL)
3015 inst.error = BAD_ARGS;
3019 if (skip_past_comma (& str) == SUCCESS)
3021 if (cp_opc_expr (& str, 5, 3) == FAIL)
3024 inst.error = BAD_ARGS;
3030 inst.error = BAD_COND;
3035 /* THUMB V5 breakpoint instruction (argument parse)
3043 unsigned long number;
3045 skip_whitespace (str);
3047 /* Allow optional leading '#'. */
3048 if (is_immediate_prefix (*str))
3051 memset (& expr, '\0', sizeof (expr));
3052 if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
3054 inst.error = _("bad or missing expression");
3058 number = expr.X_add_number;
3060 /* Check it fits an 8 bit unsigned. */
3061 if (number != (number & 0xff))
3063 inst.error = _("immediate value out of range");
3067 inst.instruction |= number;
3072 /* ARM V5 branch-link-exchange (argument parse) for BLX(1) only.
3073 Expects inst.instruction is set for BLX(1).
3074 Note: this is cloned from do_branch, and the reloc changed to be a
3075 new one that can cope with setting one extra bit (the H bit). */
3078 do_branch25 (str, flags)
3080 unsigned long flags ATTRIBUTE_UNUSED;
3082 if (my_get_expression (& inst.reloc.exp, & str))
3089 /* ScottB: February 5, 1998 */
3090 /* Check to see of PLT32 reloc required for the instruction. */
3092 /* arm_parse_reloc() works on input_line_pointer.
3093 We actually want to parse the operands to the branch instruction
3094 passed in 'str'. Save the input pointer and restore it later. */
3095 save_in = input_line_pointer;
3096 input_line_pointer = str;
3098 if (inst.reloc.exp.X_op == O_symbol
3100 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3102 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3103 inst.reloc.pc_rel = 0;
3104 /* Modify str to point to after parsed operands, otherwise
3105 end_of_line() will complain about the (PLT) left in str. */
3106 str = input_line_pointer;
3110 inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
3111 inst.reloc.pc_rel = 1;
3114 input_line_pointer = save_in;
3117 inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
3118 inst.reloc.pc_rel = 1;
3119 #endif /* OBJ_ELF */
3124 /* ARM V5 branch-link-exchange instruction (argument parse)
3125 BLX <target_addr> ie BLX(1)
3126 BLX{<condition>} <Rm> ie BLX(2)
3127 Unfortunately, there are two different opcodes for this mnemonic.
3128 So, the insns[].value is not used, and the code here zaps values
3129 into inst.instruction.
3130 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
3135 unsigned long flags;
3146 skip_whitespace (mystr);
3147 rm = reg_required_here (& mystr, 0);
3149 /* The above may set inst.error. Ignore his opinion. */
3154 /* Arg is a register.
3155 Use the condition code our caller put in inst.instruction.
3156 Pass ourselves off as a BX with a funny opcode. */
3157 inst.instruction |= 0x012fff30;
3162 /* This must be is BLX <target address>, no condition allowed. */
3163 if (inst.instruction != COND_ALWAYS)
3165 inst.error = BAD_COND;
3169 inst.instruction = 0xfafffffe;
3171 /* Process like a B/BL, but with a different reloc.
3172 Note that B/BL expecte fffffe, not 0, offset in the opcode table. */
3173 do_branch25 (str, flags);
3177 /* ARM V5 Thumb BLX (argument parse)
3178 BLX <target_addr> which is BLX(1)
3179 BLX <Rm> which is BLX(2)
3180 Unfortunately, there are two different opcodes for this mnemonic.
3181 So, the tinsns[].value is not used, and the code here zaps values
3182 into inst.instruction. */
3191 skip_whitespace (mystr);
3192 inst.instruction = 0x4780;
3194 /* Note that this call is to the ARM register recognizer. BLX(2)
3195 uses the ARM register space, not the Thumb one, so a call to
3196 thumb_reg() would be wrong. */
3197 rm = reg_required_here (& mystr, 3);
3202 /* It's BLX(2). The .instruction was zapped with rm & is final. */
3207 /* No ARM register. This must be BLX(1). Change the .instruction. */
3208 inst.instruction = 0xf7ffeffe;
3211 if (my_get_expression (& inst.reloc.exp, & mystr))
3214 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
3215 inst.reloc.pc_rel = 1;
3218 end_of_line (mystr);
3221 /* ARM V5 breakpoint instruction (argument parse)
3222 BKPT <16 bit unsigned immediate>
3223 Instruction is not conditional.
3224 The bit pattern given in insns[] has the COND_ALWAYS condition,
3225 and it is an error if the caller tried to override that.
3226 Note "flags" is nonzero if a flag was supplied (which is an error). */
3229 do_bkpt (str, flags)
3231 unsigned long flags;
3234 unsigned long number;
3236 skip_whitespace (str);
3238 /* Allow optional leading '#'. */
3239 if (is_immediate_prefix (* str))
3242 memset (& expr, '\0', sizeof (expr));
3244 if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
3246 inst.error = _("bad or missing expression");
3250 number = expr.X_add_number;
3252 /* Check it fits a 16 bit unsigned. */
3253 if (number != (number & 0xffff))
3255 inst.error = _("immediate value out of range");
3259 /* Top 12 of 16 bits to bits 19:8. */
3260 inst.instruction |= (number & 0xfff0) << 4;
3262 /* Bottom 4 of 16 bits to bits 3:0. */
3263 inst.instruction |= number & 0xf;
3268 inst.error = BAD_FLAGS;
3271 /* Xscale multiply-accumulate (argument parse)
3274 MIAxycc acc0,Rm,Rs. */
3279 unsigned long flags;
3287 else if (accum0_required_here (& str) == FAIL)
3288 inst.error = ERR_NO_ACCUM;
3290 else if (skip_past_comma (& str) == FAIL
3291 || (rm = reg_required_here (& str, 0)) == FAIL)
3292 inst.error = BAD_ARGS;
3294 else if (skip_past_comma (& str) == FAIL
3295 || (rs = reg_required_here (& str, 12)) == FAIL)
3296 inst.error = BAD_ARGS;
3298 /* inst.instruction has now been zapped with both rm and rs. */
3299 else if (rm == REG_PC || rs == REG_PC)
3300 inst.error = BAD_PC; /* Undefined result if rm or rs is R15. */
3306 /* Xscale move-accumulator-register (argument parse)
3308 MARcc acc0,RdLo,RdHi. */
3313 unsigned long flags;
3320 else if (accum0_required_here (& str) == FAIL)
3321 inst.error = ERR_NO_ACCUM;
3323 else if (skip_past_comma (& str) == FAIL
3324 || (rdlo = reg_required_here (& str, 12)) == FAIL)
3325 inst.error = BAD_ARGS;
3327 else if (skip_past_comma (& str) == FAIL
3328 || (rdhi = reg_required_here (& str, 16)) == FAIL)
3329 inst.error = BAD_ARGS;
3331 /* inst.instruction has now been zapped with both rdlo and rdhi. */
3332 else if (rdlo == REG_PC || rdhi == REG_PC)
3333 inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
3339 /* Xscale move-register-accumulator (argument parse)
3341 MRAcc RdLo,RdHi,acc0. */
3346 unsigned long flags;
3357 skip_whitespace (str);
3359 if ((rdlo = reg_required_here (& str, 12)) == FAIL)
3360 inst.error = BAD_ARGS;
3362 else if (skip_past_comma (& str) == FAIL
3363 || (rdhi = reg_required_here (& str, 16)) == FAIL)
3364 inst.error = BAD_ARGS;
3366 else if (skip_past_comma (& str) == FAIL
3367 || accum0_required_here (& str) == FAIL)
3368 inst.error = ERR_NO_ACCUM;
3370 /* inst.instruction has now been zapped with both rdlo and rdhi. */
3371 else if (rdlo == rdhi)
3372 inst.error = BAD_ARGS; /* Undefined result if 2 writes to same reg. */
3374 else if (rdlo == REG_PC || rdhi == REG_PC)
3375 inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
3380 /* Xscale: Preload-Cache
3384 Syntactically, like LDR with B=1, W=0, L=1. */
3389 unsigned long flags;
3399 skip_whitespace (str);
3403 inst.error = _("'[' expected after PLD mnemonic");
3408 skip_whitespace (str);
3410 if ((rd = reg_required_here (& str, 16)) == FAIL)
3413 skip_whitespace (str);
3419 skip_whitespace (str);
3421 if (skip_past_comma (& str) == SUCCESS)
3423 if (ldst_extend (& str, 0) == FAIL)
3426 else if (* str == '!') /* [Rn]! */
3428 inst.error = _("writeback used in preload instruction");
3432 inst.instruction |= INDEX_UP | PRE_INDEX;
3434 else /* [Rn, ...] */
3436 if (skip_past_comma (& str) == FAIL)
3438 inst.error = _("pre-indexed expression expected");
3442 if (ldst_extend (& str, 0) == FAIL)
3445 skip_whitespace (str);
3449 inst.error = _("missing ]");
3454 skip_whitespace (str);
3456 if (* str == '!') /* [Rn]! */
3458 inst.error = _("writeback used in preload instruction");
3462 inst.instruction |= PRE_INDEX;
3468 /* Xscale load-consecutive (argument parse)
3475 do_ldrd (str, flags)
3477 unsigned long flags;
3482 if (flags != DOUBLE_LOAD_FLAG)
3484 /* Change instruction pattern to normal ldr/str. */
3485 if (inst.instruction & 0x20)
3486 inst.instruction = (inst.instruction & COND_MASK) | 0x04000000; /* str */
3488 inst.instruction = (inst.instruction & COND_MASK) | 0x04100000; /* ldr */
3490 /* Perform a normal load/store instruction parse. */
3491 do_ldst (str, flags);
3496 if ((cpu_variant & ARM_EXT_XSCALE) != ARM_EXT_XSCALE)
3498 static char buff[128];
3501 while (isspace (*str))
3505 /* Deny all knowledge. */
3506 sprintf (buff, _("bad instruction '%.100s'"), str);
3511 skip_whitespace (str);
3513 if ((rd = reg_required_here (& str, 12)) == FAIL)
3515 inst.error = BAD_ARGS;
3519 if (skip_past_comma (& str) == FAIL
3520 || (rn = ld_mode_required_here (& str)) == FAIL)
3523 inst.error = BAD_ARGS;
3527 /* inst.instruction has now been zapped with Rd and the addressing mode. */
3528 if (rd & 1) /* Unpredictable result if Rd is odd. */
3530 inst.error = _("Destination register must be even");
3534 if (rd == REG_LR || rd == 12)
3536 inst.error = _("r12 or r14 not allowed here");
3540 if (((rd == rn) || (rd + 1 == rn))
3542 ((inst.instruction & WRITE_BACK)
3543 || (!(inst.instruction & PRE_INDEX))))
3544 as_warn (_("pre/post-indexing used when modified address register is destination"));
3549 /* Returns the index into fp_values of a floating point number,
3550 or -1 if not in the table. */
3553 my_get_float_expression (str)
3556 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3562 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
3564 /* Look for a raw floating point number. */
3565 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
3566 && is_end_of_line[(unsigned char) *save_in])
3568 for (i = 0; i < NUM_FLOAT_VALS; i++)
3570 for (j = 0; j < MAX_LITTLENUMS; j++)
3572 if (words[j] != fp_values[i][j])
3576 if (j == MAX_LITTLENUMS)
3584 /* Try and parse a more complex expression, this will probably fail
3585 unless the code uses a floating point prefix (eg "0f"). */
3586 save_in = input_line_pointer;
3587 input_line_pointer = *str;
3588 if (expression (&exp) == absolute_section
3589 && exp.X_op == O_big
3590 && exp.X_add_number < 0)
3592 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3594 if (gen_to_words (words, 5, (long) 15) == 0)
3596 for (i = 0; i < NUM_FLOAT_VALS; i++)
3598 for (j = 0; j < MAX_LITTLENUMS; j++)
3600 if (words[j] != fp_values[i][j])
3604 if (j == MAX_LITTLENUMS)
3606 *str = input_line_pointer;
3607 input_line_pointer = save_in;
3614 *str = input_line_pointer;
3615 input_line_pointer = save_in;
3619 /* Return true if anything in the expression is a bignum. */
3622 walk_no_bignums (sp)
3625 if (symbol_get_value_expression (sp)->X_op == O_big)
3628 if (symbol_get_value_expression (sp)->X_add_symbol)
3630 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
3631 || (symbol_get_value_expression (sp)->X_op_symbol
3632 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3639 my_get_expression (ep, str)
3646 save_in = input_line_pointer;
3647 input_line_pointer = *str;
3648 seg = expression (ep);
3651 if (seg != absolute_section
3652 && seg != text_section
3653 && seg != data_section
3654 && seg != bss_section
3655 && seg != undefined_section)
3657 inst.error = _("bad_segment");
3658 *str = input_line_pointer;
3659 input_line_pointer = save_in;
3664 /* Get rid of any bignums now, so that we don't generate an error for which
3665 we can't establish a line number later on. Big numbers are never valid
3666 in instructions, which is where this routine is always called. */
3667 if (ep->X_op == O_big
3668 || (ep->X_add_symbol
3669 && (walk_no_bignums (ep->X_add_symbol)
3671 && walk_no_bignums (ep->X_op_symbol)))))
3673 inst.error = _("Invalid constant");
3674 *str = input_line_pointer;
3675 input_line_pointer = save_in;
3679 *str = input_line_pointer;
3680 input_line_pointer = save_in;
3684 /* UNRESTRICT should be one if <shift> <register> is permitted for this
3688 decode_shift (str, unrestrict)
3692 const struct asm_shift_name * shift;
3696 skip_whitespace (* str);
3698 for (p = * str; isalpha (* p); p ++)
3703 inst.error = _("Shift expression expected");
3709 shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
3714 inst.error = _("Shift expression expected");
3718 assert (shift->properties->index == shift_properties[shift->properties->index].index);
3720 if (shift->properties->index == SHIFT_RRX)
3723 inst.instruction |= shift->properties->bit_field;
3727 skip_whitespace (p);
3729 if (unrestrict && reg_required_here (& p, 8) != FAIL)
3731 inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
3735 else if (! is_immediate_prefix (* p))
3737 inst.error = (unrestrict
3738 ? _("shift requires register or #expression")
3739 : _("shift requires #expression"));
3747 if (my_get_expression (& inst.reloc.exp, & p))
3750 /* Validate some simple #expressions. */
3751 if (inst.reloc.exp.X_op == O_constant)
3753 unsigned num = inst.reloc.exp.X_add_number;
3755 /* Reject operations greater than 32. */
3757 /* Reject a shift of 0 unless the mode allows it. */
3758 || (num == 0 && shift->properties->allows_0 == 0)
3759 /* Reject a shift of 32 unless the mode allows it. */
3760 || (num == 32 && shift->properties->allows_32 == 0)
3763 /* As a special case we allow a shift of zero for
3764 modes that do not support it to be recoded as an
3765 logical shift left of zero (ie nothing). We warn
3766 about this though. */
3769 as_warn (_("Shift of 0 ignored."));
3770 shift = & shift_names[0];
3771 assert (shift->properties->index == SHIFT_LSL);
3775 inst.error = _("Invalid immediate shift");
3780 /* Shifts of 32 are encoded as 0, for those shifts that
3785 inst.instruction |= (num << 7) | shift->properties->bit_field;
3789 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
3790 inst.reloc.pc_rel = 0;
3791 inst.instruction |= shift->properties->bit_field;
3798 /* Do those data_ops which can take a negative immediate constant
3799 by altering the instuction. A bit of a hack really.
3803 by inverting the second operand, and
3806 by negating the second operand. */
3809 negate_data_op (instruction, value)
3810 unsigned long * instruction;
3811 unsigned long value;
3814 unsigned long negated, inverted;
3816 negated = validate_immediate (-value);
3817 inverted = validate_immediate (~value);
3819 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
3822 /* First negates. */
3823 case OPCODE_SUB: /* ADD <-> SUB */
3824 new_inst = OPCODE_ADD;
3829 new_inst = OPCODE_SUB;
3833 case OPCODE_CMP: /* CMP <-> CMN */
3834 new_inst = OPCODE_CMN;
3839 new_inst = OPCODE_CMP;
3843 /* Now Inverted ops. */
3844 case OPCODE_MOV: /* MOV <-> MVN */
3845 new_inst = OPCODE_MVN;
3850 new_inst = OPCODE_MOV;
3854 case OPCODE_AND: /* AND <-> BIC */
3855 new_inst = OPCODE_BIC;
3860 new_inst = OPCODE_AND;
3864 case OPCODE_ADC: /* ADC <-> SBC */
3865 new_inst = OPCODE_SBC;
3870 new_inst = OPCODE_ADC;
3874 /* We cannot do anything. */
3879 if (value == (unsigned) FAIL)
3882 *instruction &= OPCODE_MASK;
3883 *instruction |= new_inst << DATA_OP_SHIFT;
3894 skip_whitespace (* str);
3896 if (reg_required_here (str, 0) != FAIL)
3898 if (skip_past_comma (str) == SUCCESS)
3899 /* Shift operation on register. */
3900 return decode_shift (str, NO_SHIFT_RESTRICT);
3906 /* Immediate expression. */
3907 if (is_immediate_prefix (**str))
3912 if (my_get_expression (&inst.reloc.exp, str))
3915 if (inst.reloc.exp.X_add_symbol)
3917 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3918 inst.reloc.pc_rel = 0;
3922 if (skip_past_comma (str) == SUCCESS)
3924 /* #x, y -- ie explicit rotation by Y. */
3925 if (my_get_expression (&expr, str))
3928 if (expr.X_op != O_constant)
3930 inst.error = _("Constant expression expected");
3934 /* Rotate must be a multiple of 2. */
3935 if (((unsigned) expr.X_add_number) > 30
3936 || (expr.X_add_number & 1) != 0
3937 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
3939 inst.error = _("Invalid constant");
3942 inst.instruction |= INST_IMMEDIATE;
3943 inst.instruction |= inst.reloc.exp.X_add_number;
3944 inst.instruction |= expr.X_add_number << 7;
3948 /* Implicit rotation, select a suitable one. */
3949 value = validate_immediate (inst.reloc.exp.X_add_number);
3953 /* Can't be done. Perhaps the code reads something like
3954 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
3955 if ((value = negate_data_op (&inst.instruction,
3956 inst.reloc.exp.X_add_number))
3959 inst.error = _("Invalid constant");
3964 inst.instruction |= value;
3967 inst.instruction |= INST_IMMEDIATE;
3972 inst.error = _("Register or shift expression expected");
3981 skip_whitespace (* str);
3983 if (fp_reg_required_here (str, 0) != FAIL)
3987 /* Immediate expression. */
3988 if (*((*str)++) == '#')
3994 skip_whitespace (* str);
3996 /* First try and match exact strings, this is to guarantee
3997 that some formats will work even for cross assembly. */
3999 for (i = 0; fp_const[i]; i++)
4001 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4005 *str += strlen (fp_const[i]);
4006 if (is_end_of_line[(unsigned char) **str])
4008 inst.instruction |= i + 8;
4015 /* Just because we didn't get a match doesn't mean that the
4016 constant isn't valid, just that it is in a format that we
4017 don't automatically recognize. Try parsing it with
4018 the standard expression routines. */
4019 if ((i = my_get_float_expression (str)) >= 0)
4021 inst.instruction |= i + 8;
4025 inst.error = _("Invalid floating point immediate expression");
4029 _("Floating point register or immediate expression expected");
4035 do_arit (str, flags)
4037 unsigned long flags;
4039 skip_whitespace (str);
4041 if (reg_required_here (&str, 12) == FAIL
4042 || skip_past_comma (&str) == FAIL
4043 || reg_required_here (&str, 16) == FAIL
4044 || skip_past_comma (&str) == FAIL
4045 || data_op2 (&str) == FAIL)
4048 inst.error = BAD_ARGS;
4052 inst.instruction |= flags;
4060 unsigned long flags;
4062 /* This is a pseudo-op of the form "adr rd, label" to be converted
4063 into a relative address of the form "add rd, pc, #label-.-8". */
4064 skip_whitespace (str);
4066 if (reg_required_here (&str, 12) == FAIL
4067 || skip_past_comma (&str) == FAIL
4068 || my_get_expression (&inst.reloc.exp, &str))
4071 inst.error = BAD_ARGS;
4075 /* Frag hacking will turn this into a sub instruction if the offset turns
4076 out to be negative. */
4077 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4078 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
4079 inst.reloc.pc_rel = 1;
4080 inst.instruction |= flags;
4086 do_adrl (str, flags)
4088 unsigned long flags;
4090 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4091 into a relative address of the form:
4092 add rd, pc, #low(label-.-8)"
4093 add rd, rd, #high(label-.-8)" */
4095 skip_whitespace (str);
4097 if (reg_required_here (& str, 12) == FAIL
4098 || skip_past_comma (& str) == FAIL
4099 || my_get_expression (& inst.reloc.exp, & str))
4102 inst.error = BAD_ARGS;
4108 /* Frag hacking will turn this into a sub instruction if the offset turns
4109 out to be negative. */
4110 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4111 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
4112 inst.reloc.pc_rel = 1;
4113 inst.instruction |= flags;
4114 inst.size = INSN_SIZE * 2;
4122 unsigned long flags;
4124 skip_whitespace (str);
4126 if (reg_required_here (&str, 16) == FAIL)
4129 inst.error = BAD_ARGS;
4133 if (skip_past_comma (&str) == FAIL
4134 || data_op2 (&str) == FAIL)
4137 inst.error = BAD_ARGS;
4141 inst.instruction |= flags;
4142 if ((flags & 0x0000f000) == 0)
4143 inst.instruction |= CONDS_BIT;
4152 unsigned long flags;
4154 skip_whitespace (str);
4156 if (reg_required_here (&str, 12) == FAIL)
4159 inst.error = BAD_ARGS;
4163 if (skip_past_comma (&str) == FAIL
4164 || data_op2 (&str) == FAIL)
4167 inst.error = BAD_ARGS;
4171 inst.instruction |= flags;
4177 ldst_extend (str, hwse)
4188 if (my_get_expression (& inst.reloc.exp, str))
4191 if (inst.reloc.exp.X_op == O_constant)
4193 int value = inst.reloc.exp.X_add_number;
4195 if ((hwse && (value < -255 || value > 255))
4196 || (value < -4095 || value > 4095))
4198 inst.error = _("address offset too large");
4208 /* Halfword and signextension instructions have the
4209 immediate value split across bits 11..8 and bits 3..0. */
4211 inst.instruction |= (add | HWOFFSET_IMM
4212 | ((value >> 4) << 8) | (value & 0xF));
4214 inst.instruction |= add | value;
4220 inst.instruction |= HWOFFSET_IMM;
4221 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4224 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4225 inst.reloc.pc_rel = 0;
4238 if (reg_required_here (str, 0) == FAIL)
4242 inst.instruction |= add;
4245 inst.instruction |= add | OFFSET_REG;
4246 if (skip_past_comma (str) == SUCCESS)
4247 return decode_shift (str, SHIFT_RESTRICT);
4255 do_ldst (str, flags)
4257 unsigned long flags;
4264 /* This is not ideal, but it is the simplest way of dealing with the
4265 ARM7T halfword instructions (since they use a different
4266 encoding, but the same mnemonic): */
4267 halfword = (flags & 0x80000000) != 0;
4270 /* This is actually a load/store of a halfword, or a
4271 signed-extension load. */
4272 if ((cpu_variant & ARM_EXT_HALFWORD) == 0)
4275 = _("Processor does not support halfwords or signed bytes");
4279 inst.instruction = ((inst.instruction & COND_MASK)
4280 | (flags & ~COND_MASK));
4285 skip_whitespace (str);
4287 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
4290 inst.error = BAD_ARGS;
4294 if (skip_past_comma (& str) == FAIL)
4296 inst.error = _("Address expected");
4306 skip_whitespace (str);
4308 if ((reg = reg_required_here (&str, 16)) == FAIL)
4311 /* Conflicts can occur on stores as well as loads. */
4312 conflict_reg = (conflict_reg == reg);
4314 skip_whitespace (str);
4320 if (skip_past_comma (&str) == SUCCESS)
4322 /* [Rn],... (post inc) */
4323 if (ldst_extend (&str, halfword) == FAIL)
4327 if (flags & TRANS_BIT)
4328 as_warn (_("Rn and Rd must be different in %s"),
4329 ((inst.instruction & LOAD_BIT)
4330 ? "LDRT" : "STRT"));
4332 as_warn (_("%s register same as write-back base"),
4333 ((inst.instruction & LOAD_BIT)
4334 ? _("destination") : _("source")));
4341 inst.instruction |= HWOFFSET_IMM;
4343 skip_whitespace (str);
4348 as_warn (_("%s register same as write-back base"),
4349 ((inst.instruction & LOAD_BIT)
4350 ? _("destination") : _("source")));
4352 inst.instruction |= WRITE_BACK;
4356 if (flags & TRANS_BIT)
4359 as_warn (_("Rn and Rd must be different in %s"),
4360 ((inst.instruction & LOAD_BIT)
4361 ? "LDRT" : "STRT"));
4370 if (skip_past_comma (&str) == FAIL)
4372 inst.error = _("pre-indexed expression expected");
4377 if (ldst_extend (&str, halfword) == FAIL)
4380 skip_whitespace (str);
4384 inst.error = _("missing ]");
4388 skip_whitespace (str);
4393 as_warn (_("%s register same as write-back base"),
4394 ((inst.instruction & LOAD_BIT)
4395 ? _("destination") : _("source")));
4397 inst.instruction |= WRITE_BACK;
4401 else if (*str == '=')
4403 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
4406 skip_whitespace (str);
4408 if (my_get_expression (&inst.reloc.exp, &str))
4411 if (inst.reloc.exp.X_op != O_constant
4412 && inst.reloc.exp.X_op != O_symbol)
4414 inst.error = _("Constant expression expected");
4418 if (inst.reloc.exp.X_op == O_constant
4419 && (value = validate_immediate (inst.reloc.exp.X_add_number)) != FAIL)
4421 /* This can be done with a mov instruction. */
4422 inst.instruction &= LITERAL_MASK;
4423 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4424 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
4430 /* Insert into literal pool. */
4431 if (add_to_lit_pool () == FAIL)
4434 inst.error = _("literal pool insertion failed");
4438 /* Change the instruction exp to point to the pool. */
4441 inst.instruction |= HWOFFSET_IMM;
4442 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
4445 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
4446 inst.reloc.pc_rel = 1;
4447 inst.instruction |= (REG_PC << 16);
4453 if (my_get_expression (&inst.reloc.exp, &str))
4458 inst.instruction |= HWOFFSET_IMM;
4459 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4462 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4464 /* PC rel adjust. */
4465 inst.reloc.exp.X_add_number -= 8;
4467 inst.reloc.pc_rel = 1;
4468 inst.instruction |= (REG_PC << 16);
4472 if (pre_inc && (flags & TRANS_BIT))
4473 inst.error = _("Pre-increment instruction with translate");
4475 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
4484 char * str = * strp;
4488 /* We come back here if we get ranges concatenated by '+' or '|'. */
4503 skip_whitespace (str);
4505 if ((reg = reg_required_here (& str, -1)) == FAIL)
4514 inst.error = _("Bad range in register list");
4518 for (i = cur_reg + 1; i < reg; i++)
4520 if (range & (1 << i))
4522 (_("Warning: Duplicated register (r%d) in register list"),
4530 if (range & (1 << reg))
4531 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
4533 else if (reg <= cur_reg)
4534 as_tsktsk (_("Warning: Register range not in ascending order"));
4539 while (skip_past_comma (&str) != FAIL
4540 || (in_range = 1, *str++ == '-'));
4542 skip_whitespace (str);
4546 inst.error = _("Missing `}'");
4554 if (my_get_expression (&expr, &str))
4557 if (expr.X_op == O_constant)
4559 if (expr.X_add_number
4560 != (expr.X_add_number & 0x0000ffff))
4562 inst.error = _("invalid register mask");
4566 if ((range & expr.X_add_number) != 0)
4568 int regno = range & expr.X_add_number;
4571 regno = (1 << regno) - 1;
4573 (_("Warning: Duplicated register (r%d) in register list"),
4577 range |= expr.X_add_number;
4581 if (inst.reloc.type != 0)
4583 inst.error = _("expression too complex");
4587 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
4588 inst.reloc.type = BFD_RELOC_ARM_MULTI;
4589 inst.reloc.pc_rel = 0;
4593 skip_whitespace (str);
4595 if (*str == '|' || *str == '+')
4601 while (another_range);
4608 do_ldmstm (str, flags)
4610 unsigned long flags;
4615 skip_whitespace (str);
4617 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
4620 if (base_reg == REG_PC)
4622 inst.error = _("r15 not allowed as base register");
4626 skip_whitespace (str);
4630 flags |= WRITE_BACK;
4634 if (skip_past_comma (&str) == FAIL
4635 || (range = reg_list (&str)) == FAIL)
4638 inst.error = BAD_ARGS;
4645 flags |= LDM_TYPE_2_OR_3;
4648 inst.instruction |= flags | range;
4656 unsigned long flags;
4658 skip_whitespace (str);
4660 /* Allow optional leading '#'. */
4661 if (is_immediate_prefix (*str))
4664 if (my_get_expression (& inst.reloc.exp, & str))
4667 inst.reloc.type = BFD_RELOC_ARM_SWI;
4668 inst.reloc.pc_rel = 0;
4669 inst.instruction |= flags;
4677 do_swap (str, flags)
4679 unsigned long flags;
4683 skip_whitespace (str);
4685 if ((reg = reg_required_here (&str, 12)) == FAIL)
4690 inst.error = _("r15 not allowed in swap");
4694 if (skip_past_comma (&str) == FAIL
4695 || (reg = reg_required_here (&str, 0)) == FAIL)
4698 inst.error = BAD_ARGS;
4704 inst.error = _("r15 not allowed in swap");
4708 if (skip_past_comma (&str) == FAIL
4711 inst.error = BAD_ARGS;
4715 skip_whitespace (str);
4717 if ((reg = reg_required_here (&str, 16)) == FAIL)
4722 inst.error = BAD_PC;
4726 skip_whitespace (str);
4730 inst.error = _("missing ]");
4734 inst.instruction |= flags;
4740 do_branch (str, flags)
4742 unsigned long flags ATTRIBUTE_UNUSED;
4744 if (my_get_expression (&inst.reloc.exp, &str))
4751 /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
4752 required for the instruction. */
4754 /* arm_parse_reloc () works on input_line_pointer.
4755 We actually want to parse the operands to the branch instruction
4756 passed in 'str'. Save the input pointer and restore it later. */
4757 save_in = input_line_pointer;
4758 input_line_pointer = str;
4759 if (inst.reloc.exp.X_op == O_symbol
4761 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
4763 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4764 inst.reloc.pc_rel = 0;
4765 /* Modify str to point to after parsed operands, otherwise
4766 end_of_line() will complain about the (PLT) left in str. */
4767 str = input_line_pointer;
4771 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
4772 inst.reloc.pc_rel = 1;
4774 input_line_pointer = save_in;
4777 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
4778 inst.reloc.pc_rel = 1;
4779 #endif /* OBJ_ELF */
4788 unsigned long flags ATTRIBUTE_UNUSED;
4792 skip_whitespace (str);
4794 if ((reg = reg_required_here (&str, 0)) == FAIL)
4796 inst.error = BAD_ARGS;
4800 /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
4802 as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
4810 unsigned long flags ATTRIBUTE_UNUSED;
4812 /* Co-processor data operation.
4813 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
4814 skip_whitespace (str);
4816 if (co_proc_number (&str) == FAIL)
4819 inst.error = BAD_ARGS;
4823 if (skip_past_comma (&str) == FAIL
4824 || cp_opc_expr (&str, 20,4) == FAIL)
4827 inst.error = BAD_ARGS;
4831 if (skip_past_comma (&str) == FAIL
4832 || cp_reg_required_here (&str, 12) == FAIL)
4835 inst.error = BAD_ARGS;
4839 if (skip_past_comma (&str) == FAIL
4840 || cp_reg_required_here (&str, 16) == FAIL)
4843 inst.error = BAD_ARGS;
4847 if (skip_past_comma (&str) == FAIL
4848 || cp_reg_required_here (&str, 0) == FAIL)
4851 inst.error = BAD_ARGS;
4855 if (skip_past_comma (&str) == SUCCESS)
4857 if (cp_opc_expr (&str, 5, 3) == FAIL)
4860 inst.error = BAD_ARGS;
4870 do_lstc (str, flags)
4872 unsigned long flags;
4874 /* Co-processor register load/store.
4875 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
4877 skip_whitespace (str);
4879 if (co_proc_number (&str) == FAIL)
4882 inst.error = BAD_ARGS;
4886 if (skip_past_comma (&str) == FAIL
4887 || cp_reg_required_here (&str, 12) == FAIL)
4890 inst.error = BAD_ARGS;
4894 if (skip_past_comma (&str) == FAIL
4895 || cp_address_required_here (&str) == FAIL)
4898 inst.error = BAD_ARGS;
4902 inst.instruction |= flags;
4908 do_co_reg (str, flags)
4910 unsigned long flags;
4912 /* Co-processor register transfer.
4913 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
4915 skip_whitespace (str);
4917 if (co_proc_number (&str) == FAIL)
4920 inst.error = BAD_ARGS;
4924 if (skip_past_comma (&str) == FAIL
4925 || cp_opc_expr (&str, 21, 3) == FAIL)
4928 inst.error = BAD_ARGS;
4932 if (skip_past_comma (&str) == FAIL
4933 || reg_required_here (&str, 12) == FAIL)
4936 inst.error = BAD_ARGS;
4940 if (skip_past_comma (&str) == FAIL
4941 || cp_reg_required_here (&str, 16) == FAIL)
4944 inst.error = BAD_ARGS;
4948 if (skip_past_comma (&str) == FAIL
4949 || cp_reg_required_here (&str, 0) == FAIL)
4952 inst.error = BAD_ARGS;
4956 if (skip_past_comma (&str) == SUCCESS)
4958 if (cp_opc_expr (&str, 5, 3) == FAIL)
4961 inst.error = BAD_ARGS;
4967 inst.error = BAD_COND;
4975 do_fp_ctrl (str, flags)
4977 unsigned long flags ATTRIBUTE_UNUSED;
4979 /* FP control registers.
4980 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
4982 skip_whitespace (str);
4984 if (reg_required_here (&str, 12) == FAIL)
4987 inst.error = BAD_ARGS;
4996 do_fp_ldst (str, flags)
4998 unsigned long flags ATTRIBUTE_UNUSED;
5000 skip_whitespace (str);
5002 switch (inst.suffix)
5007 inst.instruction |= CP_T_X;
5010 inst.instruction |= CP_T_Y;
5013 inst.instruction |= CP_T_X | CP_T_Y;
5019 if (fp_reg_required_here (&str, 12) == FAIL)
5022 inst.error = BAD_ARGS;
5026 if (skip_past_comma (&str) == FAIL
5027 || cp_address_required_here (&str) == FAIL)
5030 inst.error = BAD_ARGS;
5038 do_fp_ldmstm (str, flags)
5040 unsigned long flags;
5044 skip_whitespace (str);
5046 if (fp_reg_required_here (&str, 12) == FAIL)
5049 inst.error = BAD_ARGS;
5053 /* Get Number of registers to transfer. */
5054 if (skip_past_comma (&str) == FAIL
5055 || my_get_expression (&inst.reloc.exp, &str))
5058 inst.error = _("constant expression expected");
5062 if (inst.reloc.exp.X_op != O_constant)
5064 inst.error = _("Constant value required for number of registers");
5068 num_regs = inst.reloc.exp.X_add_number;
5070 if (num_regs < 1 || num_regs > 4)
5072 inst.error = _("number of registers must be in the range [1:4]");
5079 inst.instruction |= CP_T_X;
5082 inst.instruction |= CP_T_Y;
5085 inst.instruction |= CP_T_Y | CP_T_X;
5099 /* The instruction specified "ea" or "fd", so we can only accept
5100 [Rn]{!}. The instruction does not really support stacking or
5101 unstacking, so we have to emulate these by setting appropriate
5102 bits and offsets. */
5103 if (skip_past_comma (&str) == FAIL
5107 inst.error = BAD_ARGS;
5112 skip_whitespace (str);
5114 if ((reg = reg_required_here (&str, 16)) == FAIL)
5117 skip_whitespace (str);
5121 inst.error = BAD_ARGS;
5133 _("R15 not allowed as base register with write-back");
5140 if (flags & CP_T_Pre)
5142 /* Pre-decrement. */
5143 offset = 3 * num_regs;
5149 /* Post-increment. */
5153 offset = 3 * num_regs;
5157 /* No write-back, so convert this into a standard pre-increment
5158 instruction -- aesthetically more pleasing. */
5159 flags = CP_T_Pre | CP_T_UD;
5164 inst.instruction |= flags | offset;
5166 else if (skip_past_comma (&str) == FAIL
5167 || cp_address_required_here (&str) == FAIL)
5170 inst.error = BAD_ARGS;
5178 do_fp_dyadic (str, flags)
5180 unsigned long flags;
5182 skip_whitespace (str);
5184 switch (inst.suffix)
5189 inst.instruction |= 0x00000080;
5192 inst.instruction |= 0x00080000;
5198 if (fp_reg_required_here (&str, 12) == FAIL)
5201 inst.error = BAD_ARGS;
5205 if (skip_past_comma (&str) == FAIL
5206 || fp_reg_required_here (&str, 16) == FAIL)
5209 inst.error = BAD_ARGS;
5213 if (skip_past_comma (&str) == FAIL
5214 || fp_op2 (&str) == FAIL)
5217 inst.error = BAD_ARGS;
5221 inst.instruction |= flags;
5227 do_fp_monadic (str, flags)
5229 unsigned long flags;
5231 skip_whitespace (str);
5233 switch (inst.suffix)
5238 inst.instruction |= 0x00000080;
5241 inst.instruction |= 0x00080000;
5247 if (fp_reg_required_here (&str, 12) == FAIL)
5250 inst.error = BAD_ARGS;
5254 if (skip_past_comma (&str) == FAIL
5255 || fp_op2 (&str) == FAIL)
5258 inst.error = BAD_ARGS;
5262 inst.instruction |= flags;
5268 do_fp_cmp (str, flags)
5270 unsigned long flags;
5272 skip_whitespace (str);
5274 if (fp_reg_required_here (&str, 16) == FAIL)
5277 inst.error = BAD_ARGS;
5281 if (skip_past_comma (&str) == FAIL
5282 || fp_op2 (&str) == FAIL)
5285 inst.error = BAD_ARGS;
5289 inst.instruction |= flags;
5295 do_fp_from_reg (str, flags)
5297 unsigned long flags;
5299 skip_whitespace (str);
5301 switch (inst.suffix)
5306 inst.instruction |= 0x00000080;
5309 inst.instruction |= 0x00080000;
5315 if (fp_reg_required_here (&str, 16) == FAIL)
5318 inst.error = BAD_ARGS;
5322 if (skip_past_comma (&str) == FAIL
5323 || reg_required_here (&str, 12) == FAIL)
5326 inst.error = BAD_ARGS;
5330 inst.instruction |= flags;
5336 do_fp_to_reg (str, flags)
5338 unsigned long flags;
5340 skip_whitespace (str);
5342 if (reg_required_here (&str, 12) == FAIL)
5345 if (skip_past_comma (&str) == FAIL
5346 || fp_reg_required_here (&str, 0) == FAIL)
5349 inst.error = BAD_ARGS;
5353 inst.instruction |= flags;
5358 /* Thumb specific routines. */
5360 /* Parse and validate that a register is of the right form, this saves
5361 repeated checking of this information in many similar cases.
5362 Unlike the 32-bit case we do not insert the register into the opcode
5363 here, since the position is often unknown until the full instruction
5367 thumb_reg (strp, hi_lo)
5373 if ((reg = reg_required_here (strp, -1)) == FAIL)
5381 inst.error = _("lo register required");
5389 inst.error = _("hi register required");
5401 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
5405 thumb_add_sub (str, subtract)
5409 int Rd, Rs, Rn = FAIL;
5411 skip_whitespace (str);
5413 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
5414 || skip_past_comma (&str) == FAIL)
5417 inst.error = BAD_ARGS;
5421 if (is_immediate_prefix (*str))
5425 if (my_get_expression (&inst.reloc.exp, &str))
5430 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5433 if (skip_past_comma (&str) == FAIL)
5435 /* Two operand format, shuffle the registers
5436 and pretend there are 3. */
5440 else if (is_immediate_prefix (*str))
5443 if (my_get_expression (&inst.reloc.exp, &str))
5446 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5450 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
5451 for the latter case, EXPR contains the immediate that was found. */
5454 /* All register format. */
5455 if (Rd > 7 || Rs > 7 || Rn > 7)
5459 inst.error = _("dest and source1 must be the same register");
5463 /* Can't do this for SUB. */
5466 inst.error = _("subtract valid only on lo regs");
5470 inst.instruction = (T_OPCODE_ADD_HI
5471 | (Rd > 7 ? THUMB_H1 : 0)
5472 | (Rn > 7 ? THUMB_H2 : 0));
5473 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
5477 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
5478 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5483 /* Immediate expression, now things start to get nasty. */
5485 /* First deal with HI regs, only very restricted cases allowed:
5486 Adjusting SP, and using PC or SP to get an address. */
5487 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
5488 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
5490 inst.error = _("invalid Hi register with immediate");
5494 if (inst.reloc.exp.X_op != O_constant)
5496 /* Value isn't known yet, all we can do is store all the fragments
5497 we know about in the instruction and let the reloc hacking
5499 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
5500 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5504 int offset = inst.reloc.exp.X_add_number;
5514 /* Quick check, in case offset is MIN_INT. */
5517 inst.error = _("immediate value out of range");
5526 if (offset & ~0x1fc)
5528 inst.error = _("invalid immediate value for stack adjust");
5531 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5532 inst.instruction |= offset >> 2;
5534 else if (Rs == REG_PC || Rs == REG_SP)
5537 || (offset & ~0x3fc))
5539 inst.error = _("invalid immediate for address calculation");
5542 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
5544 inst.instruction |= (Rd << 8) | (offset >> 2);
5550 inst.error = _("immediate value out of range");
5553 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5554 inst.instruction |= (Rd << 8) | offset;
5560 inst.error = _("immediate value out of range");
5563 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5564 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
5573 thumb_shift (str, shift)
5577 int Rd, Rs, Rn = FAIL;
5579 skip_whitespace (str);
5581 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5582 || skip_past_comma (&str) == FAIL)
5585 inst.error = BAD_ARGS;
5589 if (is_immediate_prefix (*str))
5591 /* Two operand immediate format, set Rs to Rd. */
5594 if (my_get_expression (&inst.reloc.exp, &str))
5599 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
5602 if (skip_past_comma (&str) == FAIL)
5604 /* Two operand format, shuffle the registers
5605 and pretend there are 3. */
5609 else if (is_immediate_prefix (*str))
5612 if (my_get_expression (&inst.reloc.exp, &str))
5615 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
5619 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
5620 for the latter case, EXPR contains the immediate that was found. */
5626 inst.error = _("source1 and dest must be same register");
5632 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
5633 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
5634 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
5637 inst.instruction |= Rd | (Rn << 3);
5643 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
5644 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
5645 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
5648 if (inst.reloc.exp.X_op != O_constant)
5650 /* Value isn't known yet, create a dummy reloc and let reloc
5651 hacking fix it up. */
5652 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
5656 unsigned shift_value = inst.reloc.exp.X_add_number;
5658 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
5660 inst.error = _("Invalid immediate for shift");
5664 /* Shifts of zero are handled by converting to LSL. */
5665 if (shift_value == 0)
5666 inst.instruction = T_OPCODE_LSL_I;
5668 /* Shifts of 32 are encoded as a shift of zero. */
5669 if (shift_value == 32)
5672 inst.instruction |= shift_value << 6;
5675 inst.instruction |= Rd | (Rs << 3);
5682 thumb_mov_compare (str, move)
5688 skip_whitespace (str);
5690 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
5691 || skip_past_comma (&str) == FAIL)
5694 inst.error = BAD_ARGS;
5698 if (is_immediate_prefix (*str))
5701 if (my_get_expression (&inst.reloc.exp, &str))
5704 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5709 if (Rs < 8 && Rd < 8)
5711 if (move == THUMB_MOVE)
5712 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
5713 since a MOV instruction produces unpredictable results. */
5714 inst.instruction = T_OPCODE_ADD_I3;
5716 inst.instruction = T_OPCODE_CMP_LR;
5717 inst.instruction |= Rd | (Rs << 3);
5721 if (move == THUMB_MOVE)
5722 inst.instruction = T_OPCODE_MOV_HR;
5724 inst.instruction = T_OPCODE_CMP_HR;
5727 inst.instruction |= THUMB_H1;
5730 inst.instruction |= THUMB_H2;
5732 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
5739 inst.error = _("only lo regs allowed with immediate");
5743 if (move == THUMB_MOVE)
5744 inst.instruction = T_OPCODE_MOV_I8;
5746 inst.instruction = T_OPCODE_CMP_I8;
5748 inst.instruction |= Rd << 8;
5750 if (inst.reloc.exp.X_op != O_constant)
5751 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
5754 unsigned value = inst.reloc.exp.X_add_number;
5758 inst.error = _("invalid immediate");
5762 inst.instruction |= value;
5770 thumb_load_store (str, load_store, size)
5775 int Rd, Rb, Ro = FAIL;
5777 skip_whitespace (str);
5779 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5780 || skip_past_comma (&str) == FAIL)
5783 inst.error = BAD_ARGS;
5790 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5793 if (skip_past_comma (&str) != FAIL)
5795 if (is_immediate_prefix (*str))
5798 if (my_get_expression (&inst.reloc.exp, &str))
5801 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
5806 inst.reloc.exp.X_op = O_constant;
5807 inst.reloc.exp.X_add_number = 0;
5812 inst.error = _("expected ']'");
5817 else if (*str == '=')
5819 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
5822 skip_whitespace (str);
5824 if (my_get_expression (& inst.reloc.exp, & str))
5829 if ( inst.reloc.exp.X_op != O_constant
5830 && inst.reloc.exp.X_op != O_symbol)
5832 inst.error = "Constant expression expected";
5836 if (inst.reloc.exp.X_op == O_constant
5837 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
5839 /* This can be done with a mov instruction. */
5841 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
5842 inst.instruction |= inst.reloc.exp.X_add_number;
5846 /* Insert into literal pool. */
5847 if (add_to_lit_pool () == FAIL)
5850 inst.error = "literal pool insertion failed";
5854 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5855 inst.reloc.pc_rel = 1;
5856 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
5857 /* Adjust ARM pipeline offset to Thumb. */
5858 inst.reloc.exp.X_add_number += 4;
5864 if (my_get_expression (&inst.reloc.exp, &str))
5867 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
5868 inst.reloc.pc_rel = 1;
5869 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */
5870 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5875 if (Rb == REG_PC || Rb == REG_SP)
5877 if (size != THUMB_WORD)
5879 inst.error = _("byte or halfword not valid for base register");
5882 else if (Rb == REG_PC && load_store != THUMB_LOAD)
5884 inst.error = _("R15 based store not allowed");
5887 else if (Ro != FAIL)
5889 inst.error = _("Invalid base register for register offset");
5894 inst.instruction = T_OPCODE_LDR_PC;
5895 else if (load_store == THUMB_LOAD)
5896 inst.instruction = T_OPCODE_LDR_SP;
5898 inst.instruction = T_OPCODE_STR_SP;
5900 inst.instruction |= Rd << 8;
5901 if (inst.reloc.exp.X_op == O_constant)
5903 unsigned offset = inst.reloc.exp.X_add_number;
5905 if (offset & ~0x3fc)
5907 inst.error = _("invalid offset");
5911 inst.instruction |= offset >> 2;
5914 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5918 inst.error = _("invalid base register in load/store");
5921 else if (Ro == FAIL)
5923 /* Immediate offset. */
5924 if (size == THUMB_WORD)
5925 inst.instruction = (load_store == THUMB_LOAD
5926 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
5927 else if (size == THUMB_HALFWORD)
5928 inst.instruction = (load_store == THUMB_LOAD
5929 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
5931 inst.instruction = (load_store == THUMB_LOAD
5932 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
5934 inst.instruction |= Rd | (Rb << 3);
5936 if (inst.reloc.exp.X_op == O_constant)
5938 unsigned offset = inst.reloc.exp.X_add_number;
5940 if (offset & ~(0x1f << size))
5942 inst.error = _("Invalid offset");
5945 inst.instruction |= (offset >> size) << 6;
5948 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5952 /* Register offset. */
5953 if (size == THUMB_WORD)
5954 inst.instruction = (load_store == THUMB_LOAD
5955 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
5956 else if (size == THUMB_HALFWORD)
5957 inst.instruction = (load_store == THUMB_LOAD
5958 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
5960 inst.instruction = (load_store == THUMB_LOAD
5961 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
5963 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
5978 /* Handle the Format 4 instructions that do not have equivalents in other
5979 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
5988 skip_whitespace (str);
5990 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5991 || skip_past_comma (&str) == FAIL
5992 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
5994 inst.error = BAD_ARGS;
5998 if (skip_past_comma (&str) != FAIL)
6000 /* Three operand format not allowed for TST, CMN, NEG and MVN.
6001 (It isn't allowed for CMP either, but that isn't handled by this
6003 if (inst.instruction == T_OPCODE_TST
6004 || inst.instruction == T_OPCODE_CMN
6005 || inst.instruction == T_OPCODE_NEG
6006 || inst.instruction == T_OPCODE_MVN)
6008 inst.error = BAD_ARGS;
6012 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
6017 inst.error = _("dest and source1 one must be the same register");
6023 if (inst.instruction == T_OPCODE_MUL
6025 as_tsktsk (_("Rs and Rd must be different in MUL"));
6027 inst.instruction |= Rd | (Rs << 3);
6035 thumb_add_sub (str, 0);
6042 thumb_shift (str, THUMB_ASR);
6049 if (my_get_expression (&inst.reloc.exp, &str))
6051 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6052 inst.reloc.pc_rel = 1;
6060 if (my_get_expression (&inst.reloc.exp, &str))
6062 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6063 inst.reloc.pc_rel = 1;
6067 /* Find the real, Thumb encoded start of a Thumb function. */
6070 find_real_start (symbolP)
6074 const char * name = S_GET_NAME (symbolP);
6075 symbolS * new_target;
6077 /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
6078 #define STUB_NAME ".real_start_of"
6083 /* Names that start with '.' are local labels, not function entry points.
6084 The compiler may generate BL instructions to these labels because it
6085 needs to perform a branch to a far away location. */
6089 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
6090 sprintf (real_start, "%s%s", STUB_NAME, name);
6092 new_target = symbol_find (real_start);
6094 if (new_target == NULL)
6096 as_warn ("Failed to find real start of function: %s\n", name);
6097 new_target = symbolP;
6109 if (my_get_expression (& inst.reloc.exp, & str))
6112 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6113 inst.reloc.pc_rel = 1;
6116 /* If the destination of the branch is a defined symbol which does not have
6117 the THUMB_FUNC attribute, then we must be calling a function which has
6118 the (interfacearm) attribute. We look for the Thumb entry point to that
6119 function and change the branch to refer to that function instead. */
6120 if ( inst.reloc.exp.X_op == O_symbol
6121 && inst.reloc.exp.X_add_symbol != NULL
6122 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6123 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6124 inst.reloc.exp.X_add_symbol =
6125 find_real_start (inst.reloc.exp.X_add_symbol);
6134 skip_whitespace (str);
6136 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
6139 /* This sets THUMB_H2 from the top bit of reg. */
6140 inst.instruction |= reg << 3;
6142 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6143 should cause the alignment to be checked once it is known. This is
6144 because BX PC only works if the instruction is word aligned. */
6153 thumb_mov_compare (str, THUMB_COMPARE);
6163 skip_whitespace (str);
6165 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
6169 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
6173 if (skip_past_comma (&str) == FAIL
6174 || (range = reg_list (&str)) == FAIL)
6177 inst.error = BAD_ARGS;
6181 if (inst.reloc.type != BFD_RELOC_NONE)
6183 /* This really doesn't seem worth it. */
6184 inst.reloc.type = BFD_RELOC_NONE;
6185 inst.error = _("Expression too complex");
6191 inst.error = _("only lo-regs valid in load/store multiple");
6195 inst.instruction |= (Rb << 8) | range;
6203 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
6210 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
6217 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
6226 skip_whitespace (str);
6228 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6229 || skip_past_comma (&str) == FAIL
6231 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6232 || skip_past_comma (&str) == FAIL
6233 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6237 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
6241 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
6249 thumb_shift (str, THUMB_LSL);
6256 thumb_shift (str, THUMB_LSR);
6263 thumb_mov_compare (str, THUMB_MOVE);
6272 skip_whitespace (str);
6274 if ((range = reg_list (&str)) == FAIL)
6277 inst.error = BAD_ARGS;
6281 if (inst.reloc.type != BFD_RELOC_NONE)
6283 /* This really doesn't seem worth it. */
6284 inst.reloc.type = BFD_RELOC_NONE;
6285 inst.error = _("Expression too complex");
6291 if ((inst.instruction == T_OPCODE_PUSH
6292 && (range & ~0xff) == 1 << REG_LR)
6293 || (inst.instruction == T_OPCODE_POP
6294 && (range & ~0xff) == 1 << REG_PC))
6296 inst.instruction |= THUMB_PP_PC_LR;
6301 inst.error = _("invalid register list to push/pop instruction");
6306 inst.instruction |= range;
6314 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
6321 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
6328 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
6335 thumb_add_sub (str, 1);
6342 skip_whitespace (str);
6344 if (my_get_expression (&inst.reloc.exp, &str))
6347 inst.reloc.type = BFD_RELOC_ARM_SWI;
6358 /* This is a pseudo-op of the form "adr rd, label" to be converted
6359 into a relative address of the form "add rd, pc, #label-.-4". */
6360 skip_whitespace (str);
6362 /* Store Rd in temporary location inside instruction. */
6363 if ((reg = reg_required_here (&str, 4)) == FAIL
6364 || (reg > 7) /* For Thumb reg must be r0..r7. */
6365 || skip_past_comma (&str) == FAIL
6366 || my_get_expression (&inst.reloc.exp, &str))
6369 inst.error = BAD_ARGS;
6373 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6374 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
6375 inst.reloc.pc_rel = 1;
6376 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
6385 int len = strlen (reg_table[entry].name) + 2;
6386 char * buf = (char *) xmalloc (len);
6387 char * buf2 = (char *) xmalloc (len);
6390 #ifdef REGISTER_PREFIX
6391 buf[i++] = REGISTER_PREFIX;
6394 strcpy (buf + i, reg_table[entry].name);
6396 for (i = 0; buf[i]; i++)
6397 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
6401 hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]);
6402 hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]);
6406 insert_reg_alias (str, regnum)
6410 struct reg_entry *new =
6411 (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
6412 char *name = xmalloc (strlen (str) + 1);
6416 new->number = regnum;
6418 hash_insert (arm_reg_hsh, name, (PTR) new);
6422 set_constant_flonums ()
6426 for (i = 0; i < NUM_FLOAT_VALS; i++)
6427 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
6437 if ( (arm_ops_hsh = hash_new ()) == NULL
6438 || (arm_tops_hsh = hash_new ()) == NULL
6439 || (arm_cond_hsh = hash_new ()) == NULL
6440 || (arm_shift_hsh = hash_new ()) == NULL
6441 || (arm_reg_hsh = hash_new ()) == NULL
6442 || (arm_psr_hsh = hash_new ()) == NULL)
6443 as_fatal (_("Virtual memory exhausted"));
6445 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
6446 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
6447 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
6448 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
6449 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
6450 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
6451 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
6452 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
6453 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
6454 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
6456 for (i = 0; reg_table[i].name; i++)
6459 set_constant_flonums ();
6461 #if defined OBJ_COFF || defined OBJ_ELF
6463 unsigned int flags = 0;
6465 /* Set the flags in the private structure. */
6466 if (uses_apcs_26) flags |= F_APCS26;
6467 if (support_interwork) flags |= F_INTERWORK;
6468 if (uses_apcs_float) flags |= F_APCS_FLOAT;
6469 if (pic_code) flags |= F_PIC;
6470 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
6472 bfd_set_private_flags (stdoutput, flags);
6474 /* We have run out flags in the COFF header to encode the
6475 status of ATPCS support, so instead we create a dummy,
6476 empty, debug section called .arm.atpcs. */
6481 sec = bfd_make_section (stdoutput, ".arm.atpcs");
6485 bfd_set_section_flags
6486 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
6487 bfd_set_section_size (stdoutput, sec, 0);
6488 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
6494 /* Record the CPU type as well. */
6495 switch (cpu_variant & ARM_CPU_MASK)
6498 mach = bfd_mach_arm_2;
6501 case ARM_3: /* Also ARM_250. */
6502 mach = bfd_mach_arm_2a;
6506 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
6507 mach = bfd_mach_arm_4;
6510 case ARM_7: /* Also ARM_6. */
6511 mach = bfd_mach_arm_3;
6515 /* Catch special cases. */
6516 if (cpu_variant & ARM_EXT_XSCALE)
6517 mach = bfd_mach_arm_XScale;
6518 else if (cpu_variant & ARM_EXT_V5E)
6519 mach = bfd_mach_arm_5TE;
6520 else if (cpu_variant & ARM_EXT_V5)
6522 if (cpu_variant & ARM_EXT_THUMB)
6523 mach = bfd_mach_arm_5T;
6525 mach = bfd_mach_arm_5;
6527 else if (cpu_variant & ARM_EXT_HALFWORD)
6529 if (cpu_variant & ARM_EXT_THUMB)
6530 mach = bfd_mach_arm_4T;
6532 mach = bfd_mach_arm_4;
6534 else if (cpu_variant & ARM_EXT_LONGMUL)
6535 mach = bfd_mach_arm_3M;
6537 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
6540 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6541 for use in the a.out file, and stores them in the array pointed to by buf.
6542 This knows about the endian-ness of the target machine and does
6543 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6544 2 (short) and 4 (long) Floating numbers are put out as a series of
6545 LITTLENUMS (shorts, here at least). */
6548 md_number_to_chars (buf, val, n)
6553 if (target_big_endian)
6554 number_to_chars_bigendian (buf, val, n);
6556 number_to_chars_littleendian (buf, val, n);
6560 md_chars_to_number (buf, n)
6565 unsigned char * where = (unsigned char *) buf;
6567 if (target_big_endian)
6572 result |= (*where++ & 255);
6580 result |= (where[n] & 255);
6587 /* Turn a string in input_line_pointer into a floating point constant
6588 of type TYPE, and store the appropriate bytes in *LITP. The number
6589 of LITTLENUMS emitted is stored in *SIZEP. An error message is
6590 returned, or NULL on OK.
6592 Note that fp constants aren't represent in the normal way on the ARM.
6593 In big endian mode, things are as expected. However, in little endian
6594 mode fp constants are big-endian word-wise, and little-endian byte-wise
6595 within the words. For example, (double) 1.1 in big endian mode is
6596 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
6597 the byte sequence 99 99 f1 3f 9a 99 99 99.
6599 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
6602 md_atof (type, litP, sizeP)
6608 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6640 return _("Bad call to MD_ATOF()");
6643 t = atof_ieee (input_line_pointer, type, words);
6645 input_line_pointer = t;
6648 if (target_big_endian)
6650 for (i = 0; i < prec; i++)
6652 md_number_to_chars (litP, (valueT) words[i], 2);
6658 /* For a 4 byte float the order of elements in `words' is 1 0. For an
6659 8 byte float the order is 1 0 3 2. */
6660 for (i = 0; i < prec; i += 2)
6662 md_number_to_chars (litP, (valueT) words[i + 1], 2);
6663 md_number_to_chars (litP + 2, (valueT) words[i], 2);
6671 /* The knowledge of the PC's pipeline offset is built into the insns
6675 md_pcrel_from (fixP)
6679 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
6680 && fixP->fx_subsy == NULL)
6683 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
6685 /* PC relative addressing on the Thumb is slightly odd
6686 as the bottom two bits of the PC are forced to zero
6687 for the calculation. */
6688 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
6692 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
6693 so we un-adjust here to compensate for the accomodation. */
6694 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
6696 return fixP->fx_where + fixP->fx_frag->fr_address;
6700 /* Round up a section size to the appropriate boundary. */
6703 md_section_align (segment, size)
6704 segT segment ATTRIBUTE_UNUSED;
6710 /* Round all sects to multiple of 4. */
6711 return (size + 3) & ~3;
6715 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6716 Otherwise we have no need to default values of symbols. */
6719 md_undefined_symbol (name)
6720 char * name ATTRIBUTE_UNUSED;
6723 if (name[0] == '_' && name[1] == 'G'
6724 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
6728 if (symbol_find (name))
6729 as_bad ("GOT already in the symbol table");
6731 GOT_symbol = symbol_new (name, undefined_section,
6732 (valueT) 0, & zero_address_frag);
6742 /* arm_reg_parse () := if it looks like a register, return its token and
6743 advance the pointer. */
6747 register char ** ccp;
6749 char * start = * ccp;
6752 struct reg_entry * reg;
6754 #ifdef REGISTER_PREFIX
6755 if (*start != REGISTER_PREFIX)
6760 #ifdef OPTIONAL_REGISTER_PREFIX
6761 if (*p == OPTIONAL_REGISTER_PREFIX)
6765 if (!isalpha (*p) || !is_name_beginner (*p))
6769 while (isalpha (c) || isdigit (c) || c == '_')
6773 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
6786 md_apply_fix3 (fixP, val, seg)
6791 offsetT value = * val;
6793 unsigned int newimm;
6796 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6797 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
6799 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
6801 /* Note whether this will delete the relocation. */
6803 /* Patch from REarnshaw to JDavis (disabled for the moment, since it
6804 doesn't work fully.) */
6805 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
6808 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
6812 /* If this symbol is in a different section then we need to leave it for
6813 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
6814 so we have to undo it's effects here. */
6817 if (fixP->fx_addsy != NULL
6818 && S_IS_DEFINED (fixP->fx_addsy)
6819 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
6822 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
6823 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
6827 value += md_pcrel_from (fixP);
6831 /* Remember value for emit_reloc. */
6832 fixP->fx_addnumber = value;
6834 switch (fixP->fx_r_type)
6836 case BFD_RELOC_ARM_IMMEDIATE:
6837 newimm = validate_immediate (value);
6838 temp = md_chars_to_number (buf, INSN_SIZE);
6840 /* If the instruction will fail, see if we can fix things up by
6841 changing the opcode. */
6842 if (newimm == (unsigned int) FAIL
6843 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
6845 as_bad_where (fixP->fx_file, fixP->fx_line,
6846 _("invalid constant (%lx) after fixup"),
6847 (unsigned long) value);
6851 newimm |= (temp & 0xfffff000);
6852 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
6855 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6857 unsigned int highpart = 0;
6858 unsigned int newinsn = 0xe1a00000; /* nop. */
6859 newimm = validate_immediate (value);
6860 temp = md_chars_to_number (buf, INSN_SIZE);
6862 /* If the instruction will fail, see if we can fix things up by
6863 changing the opcode. */
6864 if (newimm == (unsigned int) FAIL
6865 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
6867 /* No ? OK - try using two ADD instructions to generate
6869 newimm = validate_immediate_twopart (value, & highpart);
6871 /* Yes - then make sure that the second instruction is
6873 if (newimm != (unsigned int) FAIL)
6875 /* Still No ? Try using a negated value. */
6876 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
6877 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
6878 /* Otherwise - give up. */
6881 as_bad_where (fixP->fx_file, fixP->fx_line,
6882 _("Unable to compute ADRL instructions for PC offset of 0x%lx"),
6887 /* Replace the first operand in the 2nd instruction (which
6888 is the PC) with the destination register. We have
6889 already added in the PC in the first instruction and we
6890 do not want to do it again. */
6891 newinsn &= ~ 0xf0000;
6892 newinsn |= ((newinsn & 0x0f000) << 4);
6895 newimm |= (temp & 0xfffff000);
6896 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
6898 highpart |= (newinsn & 0xfffff000);
6899 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
6903 case BFD_RELOC_ARM_OFFSET_IMM:
6909 if (validate_offset_imm (value, 0) == FAIL)
6911 as_bad_where (fixP->fx_file, fixP->fx_line,
6912 _("bad immediate value for offset (%ld)"),
6917 newval = md_chars_to_number (buf, INSN_SIZE);
6918 newval &= 0xff7ff000;
6919 newval |= value | (sign ? INDEX_UP : 0);
6920 md_number_to_chars (buf, newval, INSN_SIZE);
6923 case BFD_RELOC_ARM_OFFSET_IMM8:
6924 case BFD_RELOC_ARM_HWLITERAL:
6930 if (validate_offset_imm (value, 1) == FAIL)
6932 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
6933 as_bad_where (fixP->fx_file, fixP->fx_line,
6934 _("invalid literal constant: pool needs to be closer"));
6936 as_bad (_("bad immediate value for half-word offset (%ld)"),
6941 newval = md_chars_to_number (buf, INSN_SIZE);
6942 newval &= 0xff7ff0f0;
6943 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
6944 md_number_to_chars (buf, newval, INSN_SIZE);
6947 case BFD_RELOC_ARM_LITERAL:
6953 if (validate_offset_imm (value, 0) == FAIL)
6955 as_bad_where (fixP->fx_file, fixP->fx_line,
6956 _("invalid literal constant: pool needs to be closer"));
6960 newval = md_chars_to_number (buf, INSN_SIZE);
6961 newval &= 0xff7ff000;
6962 newval |= value | (sign ? INDEX_UP : 0);
6963 md_number_to_chars (buf, newval, INSN_SIZE);
6966 case BFD_RELOC_ARM_SHIFT_IMM:
6967 newval = md_chars_to_number (buf, INSN_SIZE);
6968 if (((unsigned long) value) > 32
6970 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
6972 as_bad_where (fixP->fx_file, fixP->fx_line,
6973 _("shift expression is too large"));
6978 /* Shifts of zero must be done as lsl. */
6980 else if (value == 32)
6982 newval &= 0xfffff07f;
6983 newval |= (value & 0x1f) << 7;
6984 md_number_to_chars (buf, newval, INSN_SIZE);
6987 case BFD_RELOC_ARM_SWI:
6988 if (arm_data->thumb_mode)
6990 if (((unsigned long) value) > 0xff)
6991 as_bad_where (fixP->fx_file, fixP->fx_line,
6992 _("Invalid swi expression"));
6993 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
6995 md_number_to_chars (buf, newval, THUMB_SIZE);
6999 if (((unsigned long) value) > 0x00ffffff)
7000 as_bad_where (fixP->fx_file, fixP->fx_line,
7001 _("Invalid swi expression"));
7002 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
7004 md_number_to_chars (buf, newval, INSN_SIZE);
7008 case BFD_RELOC_ARM_MULTI:
7009 if (((unsigned long) value) > 0xffff)
7010 as_bad_where (fixP->fx_file, fixP->fx_line,
7011 _("Invalid expression in load/store multiple"));
7012 newval = value | md_chars_to_number (buf, INSN_SIZE);
7013 md_number_to_chars (buf, newval, INSN_SIZE);
7016 case BFD_RELOC_ARM_PCREL_BRANCH:
7017 newval = md_chars_to_number (buf, INSN_SIZE);
7019 /* Sign-extend a 24-bit number. */
7020 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
7024 value = fixP->fx_offset;
7027 /* We are going to store value (shifted right by two) in the
7028 instruction, in a 24 bit, signed field. Thus we need to check
7029 that none of the top 8 bits of the shifted value (top 7 bits of
7030 the unshifted, unsigned value) are set, or that they are all set. */
7031 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
7032 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
7035 /* Normally we would be stuck at this point, since we cannot store
7036 the absolute address that is the destination of the branch in the
7037 24 bits of the branch instruction. If however, we happen to know
7038 that the destination of the branch is in the same section as the
7039 branch instruciton itself, then we can compute the relocation for
7040 ourselves and not have to bother the linker with it.
7042 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
7043 because I have not worked out how to do this for OBJ_COFF or
7046 && fixP->fx_addsy != NULL
7047 && S_IS_DEFINED (fixP->fx_addsy)
7048 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
7050 /* Get pc relative value to go into the branch. */
7053 /* Permit a backward branch provided that enough bits
7054 are set. Allow a forwards branch, provided that
7055 enough bits are clear. */
7056 if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
7057 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
7061 if (! fixP->fx_done)
7063 as_bad_where (fixP->fx_file, fixP->fx_line,
7064 _("gas can't handle same-section branch dest >= 0x04000000"));
7068 value += SEXT24 (newval);
7070 if ( (value & ~ ((offsetT) 0xffffff)) != 0
7071 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
7072 as_bad_where (fixP->fx_file, fixP->fx_line,
7073 _("out of range branch"));
7075 newval = (value & 0x00ffffff) | (newval & 0xff000000);
7076 md_number_to_chars (buf, newval, INSN_SIZE);
7079 case BFD_RELOC_ARM_PCREL_BLX:
7082 newval = md_chars_to_number (buf, INSN_SIZE);
7086 value = fixP->fx_offset;
7088 hbit = (value >> 1) & 1;
7089 value = (value >> 2) & 0x00ffffff;
7090 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
7091 newval = value | (newval & 0xfe000000) | (hbit << 24);
7092 md_number_to_chars (buf, newval, INSN_SIZE);
7096 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
7097 newval = md_chars_to_number (buf, THUMB_SIZE);
7099 addressT diff = (newval & 0xff) << 1;
7104 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
7105 as_bad_where (fixP->fx_file, fixP->fx_line,
7106 _("Branch out of range"));
7107 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
7109 md_number_to_chars (buf, newval, THUMB_SIZE);
7112 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
7113 newval = md_chars_to_number (buf, THUMB_SIZE);
7115 addressT diff = (newval & 0x7ff) << 1;
7120 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
7121 as_bad_where (fixP->fx_file, fixP->fx_line,
7122 _("Branch out of range"));
7123 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
7125 md_number_to_chars (buf, newval, THUMB_SIZE);
7128 case BFD_RELOC_THUMB_PCREL_BLX:
7129 case BFD_RELOC_THUMB_PCREL_BRANCH23:
7134 newval = md_chars_to_number (buf, THUMB_SIZE);
7135 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
7136 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
7137 if (diff & 0x400000)
7140 value = fixP->fx_offset;
7143 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
7144 as_bad_where (fixP->fx_file, fixP->fx_line,
7145 _("Branch with link out of range"));
7147 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
7148 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
7149 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
7150 /* Remove bit zero of the adjusted offset. Bit zero can only be
7151 set if the upper insn is at a half-word boundary, since the
7152 destination address, an ARM instruction, must always be on a
7153 word boundary. The semantics of the BLX (1) instruction, however,
7154 are that bit zero in the offset must always be zero, and the
7155 corresponding bit one in the target address will be set from bit
7156 one of the source address. */
7158 md_number_to_chars (buf, newval, THUMB_SIZE);
7159 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
7164 if (fixP->fx_done || fixP->fx_pcrel)
7165 md_number_to_chars (buf, value, 1);
7167 else if (!target_oabi)
7169 value = fixP->fx_offset;
7170 md_number_to_chars (buf, value, 1);
7176 if (fixP->fx_done || fixP->fx_pcrel)
7177 md_number_to_chars (buf, value, 2);
7179 else if (!target_oabi)
7181 value = fixP->fx_offset;
7182 md_number_to_chars (buf, value, 2);
7188 case BFD_RELOC_ARM_GOT32:
7189 case BFD_RELOC_ARM_GOTOFF:
7190 md_number_to_chars (buf, 0, 4);
7196 if (fixP->fx_done || fixP->fx_pcrel)
7197 md_number_to_chars (buf, value, 4);
7199 else if (!target_oabi)
7201 value = fixP->fx_offset;
7202 md_number_to_chars (buf, value, 4);
7208 case BFD_RELOC_ARM_PLT32:
7209 /* It appears the instruction is fully prepared at this point. */
7213 case BFD_RELOC_ARM_GOTPC:
7214 md_number_to_chars (buf, value, 4);
7217 case BFD_RELOC_ARM_CP_OFF_IMM:
7219 if (value < -1023 || value > 1023 || (value & 3))
7220 as_bad_where (fixP->fx_file, fixP->fx_line,
7221 _("Illegal value for co-processor offset"));
7224 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
7225 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
7226 md_number_to_chars (buf, newval, INSN_SIZE);
7229 case BFD_RELOC_ARM_THUMB_OFFSET:
7230 newval = md_chars_to_number (buf, THUMB_SIZE);
7231 /* Exactly what ranges, and where the offset is inserted depends
7232 on the type of instruction, we can establish this from the
7234 switch (newval >> 12)
7236 case 4: /* PC load. */
7237 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
7238 forced to zero for these loads, so we will need to round
7239 up the offset if the instruction address is not word
7240 aligned (since the final address produced must be, and
7241 we can only describe word-aligned immediate offsets). */
7243 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
7244 as_bad_where (fixP->fx_file, fixP->fx_line,
7245 _("Invalid offset, target not word aligned (0x%08X)"),
7246 (unsigned int) (fixP->fx_frag->fr_address
7247 + fixP->fx_where + value));
7249 if ((value + 2) & ~0x3fe)
7250 as_bad_where (fixP->fx_file, fixP->fx_line,
7251 _("Invalid offset, value too big (0x%08lX)"), value);
7253 /* Round up, since pc will be rounded down. */
7254 newval |= (value + 2) >> 2;
7257 case 9: /* SP load/store. */
7259 as_bad_where (fixP->fx_file, fixP->fx_line,
7260 _("Invalid offset, value too big (0x%08lX)"), value);
7261 newval |= value >> 2;
7264 case 6: /* Word load/store. */
7266 as_bad_where (fixP->fx_file, fixP->fx_line,
7267 _("Invalid offset, value too big (0x%08lX)"), value);
7268 newval |= value << 4; /* 6 - 2. */
7271 case 7: /* Byte load/store. */
7273 as_bad_where (fixP->fx_file, fixP->fx_line,
7274 _("Invalid offset, value too big (0x%08lX)"), value);
7275 newval |= value << 6;
7278 case 8: /* Halfword load/store. */
7280 as_bad_where (fixP->fx_file, fixP->fx_line,
7281 _("Invalid offset, value too big (0x%08lX)"), value);
7282 newval |= value << 5; /* 6 - 1. */
7286 as_bad_where (fixP->fx_file, fixP->fx_line,
7287 "Unable to process relocation for thumb opcode: %lx",
7288 (unsigned long) newval);
7291 md_number_to_chars (buf, newval, THUMB_SIZE);
7294 case BFD_RELOC_ARM_THUMB_ADD:
7295 /* This is a complicated relocation, since we use it for all of
7296 the following immediate relocations:
7300 9bit ADD/SUB SP word-aligned
7301 10bit ADD PC/SP word-aligned
7303 The type of instruction being processed is encoded in the
7310 newval = md_chars_to_number (buf, THUMB_SIZE);
7312 int rd = (newval >> 4) & 0xf;
7313 int rs = newval & 0xf;
7314 int subtract = newval & 0x8000;
7319 as_bad_where (fixP->fx_file, fixP->fx_line,
7320 _("Invalid immediate for stack address calculation"));
7321 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
7322 newval |= value >> 2;
7324 else if (rs == REG_PC || rs == REG_SP)
7328 as_bad_where (fixP->fx_file, fixP->fx_line,
7329 _("Invalid immediate for address calculation (value = 0x%08lX)"),
7330 (unsigned long) value);
7331 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
7333 newval |= value >> 2;
7338 as_bad_where (fixP->fx_file, fixP->fx_line,
7339 _("Invalid 8bit immediate"));
7340 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
7341 newval |= (rd << 8) | value;
7346 as_bad_where (fixP->fx_file, fixP->fx_line,
7347 _("Invalid 3bit immediate"));
7348 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
7349 newval |= rd | (rs << 3) | (value << 6);
7352 md_number_to_chars (buf, newval, THUMB_SIZE);
7355 case BFD_RELOC_ARM_THUMB_IMM:
7356 newval = md_chars_to_number (buf, THUMB_SIZE);
7357 switch (newval >> 11)
7359 case 0x04: /* 8bit immediate MOV. */
7360 case 0x05: /* 8bit immediate CMP. */
7361 if (value < 0 || value > 255)
7362 as_bad_where (fixP->fx_file, fixP->fx_line,
7363 _("Invalid immediate: %ld is too large"),
7371 md_number_to_chars (buf, newval, THUMB_SIZE);
7374 case BFD_RELOC_ARM_THUMB_SHIFT:
7375 /* 5bit shift value (0..31). */
7376 if (value < 0 || value > 31)
7377 as_bad_where (fixP->fx_file, fixP->fx_line,
7378 _("Illegal Thumb shift value: %ld"), (long) value);
7379 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
7380 newval |= value << 6;
7381 md_number_to_chars (buf, newval, THUMB_SIZE);
7384 case BFD_RELOC_VTABLE_INHERIT:
7385 case BFD_RELOC_VTABLE_ENTRY:
7389 case BFD_RELOC_NONE:
7391 as_bad_where (fixP->fx_file, fixP->fx_line,
7392 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
7398 /* Translate internal representation of relocation info to BFD target
7402 tc_gen_reloc (section, fixp)
7403 asection * section ATTRIBUTE_UNUSED;
7407 bfd_reloc_code_real_type code;
7409 reloc = (arelent *) xmalloc (sizeof (arelent));
7411 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7412 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7413 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
7415 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
7417 if (fixp->fx_pcrel == 0)
7418 reloc->addend = fixp->fx_offset;
7420 reloc->addend = fixp->fx_offset = reloc->address;
7422 reloc->addend = fixp->fx_offset;
7425 switch (fixp->fx_r_type)
7430 code = BFD_RELOC_8_PCREL;
7437 code = BFD_RELOC_16_PCREL;
7444 code = BFD_RELOC_32_PCREL;
7448 case BFD_RELOC_ARM_PCREL_BRANCH:
7449 case BFD_RELOC_ARM_PCREL_BLX:
7451 case BFD_RELOC_THUMB_PCREL_BRANCH9:
7452 case BFD_RELOC_THUMB_PCREL_BRANCH12:
7453 case BFD_RELOC_THUMB_PCREL_BRANCH23:
7454 case BFD_RELOC_THUMB_PCREL_BLX:
7455 case BFD_RELOC_VTABLE_ENTRY:
7456 case BFD_RELOC_VTABLE_INHERIT:
7457 code = fixp->fx_r_type;
7460 case BFD_RELOC_ARM_LITERAL:
7461 case BFD_RELOC_ARM_HWLITERAL:
7462 /* If this is called then the a literal has been referenced across
7463 a section boundary - possibly due to an implicit dump. */
7464 as_bad_where (fixp->fx_file, fixp->fx_line,
7465 _("Literal referenced across section boundary (Implicit dump?)"));
7469 case BFD_RELOC_ARM_GOT32:
7470 case BFD_RELOC_ARM_GOTOFF:
7471 case BFD_RELOC_ARM_PLT32:
7472 code = fixp->fx_r_type;
7476 case BFD_RELOC_ARM_IMMEDIATE:
7477 as_bad_where (fixp->fx_file, fixp->fx_line,
7478 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
7482 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
7483 as_bad_where (fixp->fx_file, fixp->fx_line,
7484 _("ADRL used for a symbol not defined in the same file"));
7487 case BFD_RELOC_ARM_OFFSET_IMM:
7488 as_bad_where (fixp->fx_file, fixp->fx_line,
7489 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
7497 switch (fixp->fx_r_type)
7499 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
7500 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
7501 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
7502 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
7503 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
7504 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
7505 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
7506 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
7507 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
7508 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
7509 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
7510 default: type = _("<unknown>"); break;
7512 as_bad_where (fixp->fx_file, fixp->fx_line,
7513 _("Cannot represent %s relocation in this object file format"),
7520 if (code == BFD_RELOC_32_PCREL
7522 && fixp->fx_addsy == GOT_symbol)
7524 code = BFD_RELOC_ARM_GOTPC;
7525 reloc->addend = fixp->fx_offset = reloc->address;
7529 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
7531 if (reloc->howto == NULL)
7533 as_bad_where (fixp->fx_file, fixp->fx_line,
7534 _("Can not represent %s relocation in this object file format"),
7535 bfd_get_reloc_code_name (code));
7539 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
7540 vtable entry to be used in the relocation's section offset. */
7541 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7542 reloc->address = fixp->fx_offset;
7548 md_estimate_size_before_relax (fragP, segtype)
7549 fragS * fragP ATTRIBUTE_UNUSED;
7550 segT segtype ATTRIBUTE_UNUSED;
7552 as_fatal (_("md_estimate_size_before_relax\n"));
7557 output_inst PARAMS ((void))
7563 as_bad (inst.error);
7567 to = frag_more (inst.size);
7569 if (thumb_mode && (inst.size > THUMB_SIZE))
7571 assert (inst.size == (2 * THUMB_SIZE));
7572 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
7573 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
7575 else if (inst.size > INSN_SIZE)
7577 assert (inst.size == (2 * INSN_SIZE));
7578 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7579 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
7582 md_number_to_chars (to, inst.instruction, inst.size);
7584 if (inst.reloc.type != BFD_RELOC_NONE)
7585 fix_new_arm (frag_now, to - frag_now->fr_literal,
7586 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7590 dwarf2_emit_insn (inst.size);
7603 /* Align the instruction.
7604 This may not be the right thing to do but ... */
7608 listing_prev_line (); /* Defined in listing.h. */
7610 /* Align the previous label if needed. */
7611 if (last_label_seen != NULL)
7613 symbol_set_frag (last_label_seen, frag_now);
7614 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
7615 S_SET_SEGMENT (last_label_seen, now_seg);
7618 memset (&inst, '\0', sizeof (inst));
7619 inst.reloc.type = BFD_RELOC_NONE;
7621 skip_whitespace (str);
7623 /* Scan up to the end of the op-code, which must end in white space or
7625 for (start = p = str; *p != '\0'; p++)
7631 as_bad (_("No operator -- statement `%s'\n"), str);
7637 CONST struct thumb_opcode * opcode;
7641 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
7646 /* Check that this instruction is supported for this CPU. */
7647 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
7649 as_bad (_("selected processor does not support this opcode"));
7653 inst.instruction = opcode->value;
7654 inst.size = opcode->size;
7655 (*opcode->parms) (p);
7662 CONST struct asm_opcode * opcode;
7663 unsigned long cond_code;
7665 inst.size = INSN_SIZE;
7666 /* P now points to the end of the opcode, probably white space, but we
7667 have to break the opcode up in case it contains condionals and flags;
7668 keep trying with progressively smaller basic instructions until one
7669 matches, or we run out of opcode. */
7670 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
7672 for (; q != str; q--)
7677 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
7680 if (opcode && opcode->template)
7682 unsigned long flag_bits = 0;
7685 /* Check that this instruction is supported for this CPU. */
7686 if ((opcode->variants & cpu_variant) == 0)
7689 inst.instruction = opcode->value;
7690 if (q == p) /* Just a simple opcode. */
7692 if (opcode->comp_suffix)
7694 if (*opcode->comp_suffix != '\0')
7695 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
7696 str, opcode->comp_suffix);
7698 /* Not a conditional instruction. */
7699 (*opcode->parms) (q, 0);
7703 /* A conditional instruction with default condition. */
7704 inst.instruction |= COND_ALWAYS;
7705 (*opcode->parms) (q, 0);
7711 /* Not just a simple opcode. Check if extra is a
7716 CONST struct asm_cond *cond;
7720 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
7724 if (cond->value == 0xf0000000)
7726 _("Warning: Use of the 'nv' conditional is deprecated\n"));
7728 cond_code = cond->value;
7732 cond_code = COND_ALWAYS;
7735 cond_code = COND_ALWAYS;
7737 /* Apply the conditional, or complain it's not allowed. */
7738 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
7740 /* Instruction isn't conditional. */
7741 if (cond_code != COND_ALWAYS)
7743 as_bad (_("Opcode `%s' is unconditional\n"), str);
7748 /* Instruction is conditional: set the condition into it. */
7749 inst.instruction |= cond_code;
7751 /* If there is a compulsory suffix, it should come here
7752 before any optional flags. */
7753 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
7755 CONST char *s = opcode->comp_suffix;
7767 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
7768 str, opcode->comp_suffix);
7775 /* The remainder, if any should now be flags for the instruction;
7776 Scan these checking each one found with the opcode. */
7780 CONST struct asm_flg *flag = opcode->flags;
7789 for (flagno = 0; flag[flagno].template; flagno++)
7791 if (streq (r, flag[flagno].template))
7793 flag_bits |= flag[flagno].set_bits;
7799 if (! flag[flagno].template)
7806 (*opcode->parms) (p, flag_bits);
7816 /* It wasn't an instruction, but it might be a register alias of the form
7819 skip_whitespace (q);
7824 if (*q && !strncmp (q, ".req ", 4))
7830 #ifdef IGNORE_OPCODE_CASE
7831 str = original_case_string;
7836 skip_whitespace (q);
7838 for (r = q; *r != '\0'; r++)
7848 regnum = arm_reg_parse (& q);
7851 reg = arm_reg_parse (& str);
7856 insert_reg_alias (str, regnum);
7858 as_warn (_("register '%s' does not exist\n"), q);
7860 else if (regnum != FAIL)
7863 as_warn (_("ignoring redefinition of register alias '%s'"),
7866 /* Do not warn about redefinitions to the same alias. */
7869 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
7873 as_warn (_("ignoring incomplete .req pseuso op"));
7880 as_bad (_("bad instruction `%s'"), start);
7884 Invocation line includes a switch not recognized by the base assembler.
7885 See if it's a processor-specific option. These are:
7886 Cpu variants, the arm part is optional:
7887 -m[arm]1 Currently not supported.
7888 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
7889 -m[arm]3 Arm 3 processor
7890 -m[arm]6[xx], Arm 6 processors
7891 -m[arm]7[xx][t][[d]m] Arm 7 processors
7892 -m[arm]8[10] Arm 8 processors
7893 -m[arm]9[20][tdmi] Arm 9 processors
7894 -mstrongarm[110[0]] StrongARM processors
7895 -mxscale XScale processors
7896 -m[arm]v[2345[t[e]]] Arm architectures
7897 -mall All (except the ARM1)
7899 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
7900 -mfpe-old (No float load/store multiples)
7901 -mno-fpu Disable all floating point instructions
7902 Run-time endian selection:
7904 -EL little endian cpu
7905 ARM Procedure Calling Standard:
7906 -mapcs-32 32 bit APCS
7907 -mapcs-26 26 bit APCS
7908 -mapcs-float Pass floats in float regs
7909 -mapcs-reentrant Position independent code
7910 -mthumb-interwork Code supports Arm/Thumb interworking
7911 -matpcs ARM/Thumb Procedure Call Standard
7912 -moabi Old ELF ABI */
7914 CONST char * md_shortopts = "m:k";
7916 struct option md_longopts[] =
7918 #ifdef ARM_BI_ENDIAN
7919 #define OPTION_EB (OPTION_MD_BASE + 0)
7920 {"EB", no_argument, NULL, OPTION_EB},
7921 #define OPTION_EL (OPTION_MD_BASE + 1)
7922 {"EL", no_argument, NULL, OPTION_EL},
7924 #define OPTION_OABI (OPTION_MD_BASE +2)
7925 {"oabi", no_argument, NULL, OPTION_OABI},
7928 {NULL, no_argument, NULL, 0}
7931 size_t md_longopts_size = sizeof (md_longopts);
7934 md_parse_option (c, arg)
7942 #ifdef ARM_BI_ENDIAN
7944 target_big_endian = 1;
7947 target_big_endian = 0;
7955 if (streq (str, "fpa10"))
7956 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
7957 else if (streq (str, "fpa11"))
7958 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
7959 else if (streq (str, "fpe-old"))
7960 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
7966 if (streq (str, "no-fpu"))
7967 cpu_variant &= ~FPU_ALL;
7972 if (streq (str, "oabi"))
7978 /* Limit assembler to generating only Thumb instructions: */
7979 if (streq (str, "thumb"))
7981 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_EXT_THUMB;
7982 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
7985 else if (streq (str, "thumb-interwork"))
7987 if ((cpu_variant & ARM_EXT_THUMB) == 0)
7988 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
7989 #if defined OBJ_COFF || defined OBJ_ELF
7990 support_interwork = true;
7998 if (streq (str, "all"))
8000 cpu_variant = ARM_ALL | FPU_ALL;
8003 #if defined OBJ_COFF || defined OBJ_ELF
8004 if (! strncmp (str, "apcs-", 5))
8006 /* GCC passes on all command line options starting "-mapcs-..."
8007 to us, so we must parse them here. */
8011 if (streq (str, "32"))
8013 uses_apcs_26 = false;
8016 else if (streq (str, "26"))
8018 uses_apcs_26 = true;
8021 else if (streq (str, "frame"))
8023 /* Stack frames are being generated - does not affect
8027 else if (streq (str, "stack-check"))
8029 /* Stack checking is being performed - does not affect
8030 linkage, but does require that the functions
8031 __rt_stkovf_split_small and __rt_stkovf_split_big be
8032 present in the final link. */
8036 else if (streq (str, "float"))
8038 /* Floating point arguments are being passed in the floating
8039 point registers. This does affect linking, since this
8040 version of the APCS is incompatible with the version that
8041 passes floating points in the integer registers. */
8043 uses_apcs_float = true;
8046 else if (streq (str, "reentrant"))
8048 /* Reentrant code has been generated. This does affect
8049 linking, since there is no point in linking reentrant/
8050 position independent code with absolute position code. */
8055 as_bad (_("Unrecognised APCS switch -m%s"), arg);
8059 if (! strcmp (str, "atpcs"))
8065 /* Strip off optional "arm". */
8066 if (! strncmp (str, "arm", 3))
8072 if (streq (str, "1"))
8073 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
8079 if (streq (str, "2"))
8080 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
8081 else if (streq (str, "250"))
8082 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
8088 if (streq (str, "3"))
8089 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
8095 switch (strtol (str, NULL, 10))
8102 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
8110 /* Eat the processor name. */
8111 switch (strtol (str, & str, 10))
8124 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
8130 cpu_variant |= ARM_ARCH_V4T;
8134 cpu_variant |= ARM_EXT_LONGMUL;
8137 case 'f': /* fe => fp enabled cpu. */
8143 case 'c': /* Left over from 710c processor name. */
8144 case 'd': /* Debug. */
8145 case 'i': /* Embedded ICE. */
8146 /* Included for completeness in ARM processor naming. */
8156 if (streq (str, "8") || streq (str, "810"))
8157 cpu_variant = (cpu_variant & ~ARM_ANY)
8158 | ARM_8 | ARM_ARCH_V4;
8164 if (streq (str, "9"))
8165 cpu_variant = (cpu_variant & ~ARM_ANY)
8166 | ARM_9 | ARM_ARCH_V4T;
8167 else if (streq (str, "920"))
8168 cpu_variant = (cpu_variant & ~ARM_ANY)
8169 | ARM_9 | ARM_ARCH_V4;
8170 else if (streq (str, "920t"))
8171 cpu_variant = (cpu_variant & ~ARM_ANY)
8172 | ARM_9 | ARM_ARCH_V4T;
8173 else if (streq (str, "9tdmi"))
8174 cpu_variant = (cpu_variant & ~ARM_ANY)
8175 | ARM_9 | ARM_ARCH_V4T;
8181 if (streq (str, "strongarm")
8182 || streq (str, "strongarm110")
8183 || streq (str, "strongarm1100"))
8184 cpu_variant = (cpu_variant & ~ARM_ANY)
8185 | ARM_8 | ARM_ARCH_V4;
8191 if (streq (str, "xscale"))
8192 cpu_variant = ARM_9 | ARM_ARCH_XSCALE;
8198 /* Select variant based on architecture rather than
8206 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
8209 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
8212 as_bad (_("Invalid architecture variant -m%s"), arg);
8218 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
8222 case 'm': cpu_variant |= ARM_EXT_LONGMUL; break;
8225 as_bad (_("Invalid architecture variant -m%s"), arg);
8231 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCH_V4;
8235 case 't': cpu_variant |= ARM_EXT_THUMB; break;
8238 as_bad (_("Invalid architecture variant -m%s"), arg);
8244 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V5;
8247 case 't': cpu_variant |= ARM_EXT_THUMB; break;
8248 case 'e': cpu_variant |= ARM_EXT_V5E; break;
8251 as_bad (_("Invalid architecture variant -m%s"), arg);
8257 as_bad (_("Invalid architecture variant -m%s"), arg);
8264 as_bad (_("Invalid processor variant -m%s"), arg);
8270 #if defined OBJ_ELF || defined OBJ_COFF
8288 ARM Specific Assembler Options:\n\
8289 -m[arm][<processor name>] select processor variant\n\
8290 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
8291 -mthumb only allow Thumb instructions\n\
8292 -mthumb-interwork mark the assembled code as supporting interworking\n\
8293 -mall allow any instruction\n\
8294 -mfpa10, -mfpa11 select floating point architecture\n\
8295 -mfpe-old don't allow floating-point multiple instructions\n\
8296 -mno-fpu don't allow any floating-point instructions.\n\
8297 -k generate PIC code.\n"));
8298 #if defined OBJ_COFF || defined OBJ_ELF
8300 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
8301 -matpcs use ARM/Thumb Procedure Calling Standard\n\
8302 -mapcs-float floating point args are passed in FP regs\n\
8303 -mapcs-reentrant the code is position independent/reentrant\n"));
8307 -moabi support the old ELF ABI\n"));
8309 #ifdef ARM_BI_ENDIAN
8311 -EB assemble code for a big endian cpu\n\
8312 -EL assemble code for a little endian cpu\n"));
8316 /* We need to be able to fix up arbitrary expressions in some statements.
8317 This is so that we can handle symbols that are an arbitrary distance from
8318 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
8319 which returns part of an address in a form which will be valid for
8320 a data instruction. We do this by pushing the expression into a symbol
8321 in the expr_section, and creating a fix for that. */
8324 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
8333 arm_fix_data * arm_data;
8341 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
8345 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
8350 /* Mark whether the fix is to a THUMB instruction, or an ARM
8352 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
8353 new_fix->tc_fix_data = (PTR) arm_data;
8354 arm_data->thumb_mode = thumb_mode;
8359 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8362 cons_fix_new_arm (frag, where, size, exp)
8368 bfd_reloc_code_real_type type;
8372 FIXME: @@ Should look at CPU word size. */
8379 type = BFD_RELOC_16;
8383 type = BFD_RELOC_32;
8386 type = BFD_RELOC_64;
8390 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
8393 /* A good place to do this, although this was probably not intended
8394 for this kind of use. We need to dump the literal pool before
8395 references are made to a null symbol pointer. */
8400 if (current_poolP == NULL)
8403 /* Put it at the end of text section. */
8404 subseg_set (text_section, 0);
8406 listing_prev_line ();
8410 arm_start_line_hook ()
8412 last_label_seen = NULL;
8416 arm_frob_label (sym)
8419 last_label_seen = sym;
8421 ARM_SET_THUMB (sym, thumb_mode);
8423 #if defined OBJ_COFF || defined OBJ_ELF
8424 ARM_SET_INTERWORK (sym, support_interwork);
8427 /* Note - do not allow local symbols (.Lxxx) to be labeled
8428 as Thumb functions. This is because these labels, whilst
8429 they exist inside Thumb code, are not the entry points for
8430 possible ARM->Thumb calls. Also, these labels can be used
8431 as part of a computed goto or switch statement. eg gcc
8432 can generate code that looks like this:
8444 The first instruction loads the address of the jump table.
8445 The second instruction converts a table index into a byte offset.
8446 The third instruction gets the jump address out of the table.
8447 The fourth instruction performs the jump.
8449 If the address stored at .Laaa is that of a symbol which has the
8450 Thumb_Func bit set, then the linker will arrange for this address
8451 to have the bottom bit set, which in turn would mean that the
8452 address computation performed by the third instruction would end
8453 up with the bottom bit set. Since the ARM is capable of unaligned
8454 word loads, the instruction would then load the incorrect address
8455 out of the jump table, and chaos would ensue. */
8456 if (label_is_thumb_function_name
8457 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
8458 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
8460 /* When the address of a Thumb function is taken the bottom
8461 bit of that address should be set. This will allow
8462 interworking between Arm and Thumb functions to work
8465 THUMB_SET_FUNC (sym, 1);
8467 label_is_thumb_function_name = false;
8471 /* Adjust the symbol table. This marks Thumb symbols as distinct from
8475 arm_adjust_symtab ()
8480 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
8482 if (ARM_IS_THUMB (sym))
8484 if (THUMB_IS_FUNC (sym))
8486 /* Mark the symbol as a Thumb function. */
8487 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
8488 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
8489 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
8491 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
8492 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
8494 as_bad (_("%s: unexpected function type: %d"),
8495 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
8497 else switch (S_GET_STORAGE_CLASS (sym))
8500 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
8503 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
8506 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
8514 if (ARM_IS_INTERWORK (sym))
8515 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
8522 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
8524 if (ARM_IS_THUMB (sym))
8526 elf_symbol_type * elf_sym;
8528 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
8529 bind = ELF_ST_BIND (elf_sym);
8531 /* If it's a .thumb_func, declare it as so,
8532 otherwise tag label as .code 16. */
8533 if (THUMB_IS_FUNC (sym))
8534 elf_sym->internal_elf_sym.st_info =
8535 ELF_ST_INFO (bind, STT_ARM_TFUNC);
8537 elf_sym->internal_elf_sym.st_info =
8538 ELF_ST_INFO (bind, STT_ARM_16BIT);
8547 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
8549 *input_line_pointer = '/';
8550 input_line_pointer += 5;
8551 *input_line_pointer = 0;
8559 arm_canonicalize_symbol_name (name)
8564 if (thumb_mode && (len = strlen (name)) > 5
8565 && streq (name + len - 5, "/data"))
8566 *(name + len - 5) = 0;
8572 arm_validate_fix (fixP)
8575 /* If the destination of the branch is a defined symbol which does not have
8576 the THUMB_FUNC attribute, then we must be calling a function which has
8577 the (interfacearm) attribute. We look for the Thumb entry point to that
8578 function and change the branch to refer to that function instead. */
8579 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
8580 && fixP->fx_addsy != NULL
8581 && S_IS_DEFINED (fixP->fx_addsy)
8582 && ! THUMB_IS_FUNC (fixP->fx_addsy))
8584 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
8592 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
8593 local labels from being added to the output symbol table when they
8594 are used with the ADRL pseudo op. The ADRL relocation should always
8595 be resolved before the binbary is emitted, so it is safe to say that
8596 it is adjustable. */
8599 arm_fix_adjustable (fixP)
8602 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
8608 /* Relocations against Thumb function names must be left unadjusted,
8609 so that the linker can use this information to correctly set the
8610 bottom bit of their addresses. The MIPS version of this function
8611 also prevents relocations that are mips-16 specific, but I do not
8612 know why it does this.
8615 There is one other problem that ought to be addressed here, but
8616 which currently is not: Taking the address of a label (rather
8617 than a function) and then later jumping to that address. Such
8618 addresses also ought to have their bottom bit set (assuming that
8619 they reside in Thumb code), but at the moment they will not. */
8622 arm_fix_adjustable (fixP)
8625 if (fixP->fx_addsy == NULL)
8628 /* Prevent all adjustments to global symbols. */
8629 if (S_IS_EXTERN (fixP->fx_addsy))
8632 if (S_IS_WEAK (fixP->fx_addsy))
8635 if (THUMB_IS_FUNC (fixP->fx_addsy)
8636 && fixP->fx_subsy == NULL)
8639 /* We need the symbol name for the VTABLE entries. */
8640 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
8641 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8648 elf32_arm_target_format ()
8650 if (target_big_endian)
8653 return "elf32-bigarm-oabi";
8655 return "elf32-bigarm";
8660 return "elf32-littlearm-oabi";
8662 return "elf32-littlearm";
8667 armelf_frob_symbol (symp, puntp)
8671 elf_frob_symbol (symp, puntp);
8675 arm_force_relocation (fixp)
8678 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
8679 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
8680 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
8681 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
8682 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
8683 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
8689 static bfd_reloc_code_real_type
8699 bfd_reloc_code_real_type reloc;
8703 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
8704 MAP ("(got)", BFD_RELOC_ARM_GOT32),
8705 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
8706 /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
8707 branch instructions generated by GCC for PLT relocs. */
8708 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
8709 { NULL, 0, BFD_RELOC_UNUSED }
8713 for (i = 0, ip = input_line_pointer;
8714 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
8716 id[i] = tolower (*ip);
8718 for (i = 0; reloc_map[i].str; i++)
8719 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
8722 input_line_pointer += reloc_map[i].len;
8724 return reloc_map[i].reloc;
8728 s_arm_elf_cons (nbytes)
8733 #ifdef md_flush_pending_output
8734 md_flush_pending_output ();
8737 if (is_it_end_of_statement ())
8739 demand_empty_rest_of_line ();
8743 #ifdef md_cons_align
8744 md_cons_align (nbytes);
8749 bfd_reloc_code_real_type reloc;
8753 if (exp.X_op == O_symbol
8754 && * input_line_pointer == '('
8755 && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED)
8757 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
8758 int size = bfd_get_reloc_size (howto);
8761 as_bad ("%s relocations do not fit in %d bytes",
8762 howto->name, nbytes);
8765 register char *p = frag_more ((int) nbytes);
8766 int offset = nbytes - size;
8768 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8773 emit_expr (&exp, (unsigned int) nbytes);
8775 while (*input_line_pointer++ == ',');
8777 /* Put terminator back into stream. */
8778 input_line_pointer --;
8779 demand_empty_rest_of_line ();
8782 #endif /* OBJ_ELF */
8784 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8785 of an rs_align_code fragment. */
8788 arm_handle_align (fragp)
8791 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
8792 static char const thumb_noop[2] = { 0xc0, 0x46 };
8793 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
8794 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
8796 int bytes, fix, noop_size;
8800 if (fragp->fr_type != rs_align_code)
8803 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
8804 p = fragp->fr_literal + fragp->fr_fix;
8807 if (fragp->tc_frag_data)
8809 if (target_big_endian)
8810 noop = thumb_bigend_noop;
8813 noop_size = sizeof (thumb_noop);
8817 if (target_big_endian)
8818 noop = arm_bigend_noop;
8821 noop_size = sizeof (arm_noop);
8824 if (bytes & (noop_size - 1))
8826 fix = bytes & (noop_size - 1);
8832 while (bytes >= noop_size)
8834 memcpy (p, noop, noop_size);
8840 fragp->fr_fix += fix;
8841 fragp->fr_var = noop_size;
8844 /* Called from md_do_align. Used to create an alignment
8845 frag in a code section. */
8848 arm_frag_align_code (n, max)
8854 /* We assume that there will never be a requirment
8855 to support alignments greater than 32 bytes. */
8857 as_fatal (_("alignments in code section > 32 not supported."));
8859 p = frag_var (rs_align_code,
8862 (relax_substateT) max,
8870 /* Perform target specific initialisation of a frag. */
8873 arm_init_frag (fragp)
8876 /* Record whether this frag is in an ARM or a THUMB area. */
8877 fragp->tc_frag_data = thumb_mode;