1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant;
127 static arm_feature_set arm_arch_used;
128 static arm_feature_set thumb_arch_used;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26 = FALSE;
132 static int atpcs = FALSE;
133 static int support_interwork = FALSE;
134 static int uses_apcs_float = FALSE;
135 static int pic_code = FALSE;
136 static int fix_v4bx = FALSE;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated = TRUE;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax = FALSE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE_CORE_LOW (ARM_EXT_V6M);
189 static const arm_feature_set arm_ext_v6_notm =
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
191 static const arm_feature_set arm_ext_v6_dsp =
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
193 static const arm_feature_set arm_ext_barrier =
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
195 static const arm_feature_set arm_ext_msr =
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
197 static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
198 static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
199 static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
200 static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
201 static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
202 static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
203 static const arm_feature_set arm_ext_m =
204 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, ARM_EXT2_V8M);
205 static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
206 static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
207 static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
208 static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
209 static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
210 static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
211 static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
212 static const arm_feature_set arm_ext_v6t2_v8m =
213 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
214 /* Instructions shared between ARMv8-A and ARMv8-M. */
215 static const arm_feature_set arm_ext_atomics =
216 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
217 static const arm_feature_set arm_ext_v8_2 =
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
219 /* FP16 instructions. */
220 static const arm_feature_set arm_ext_fp16 =
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
223 static const arm_feature_set arm_arch_any = ARM_ANY;
224 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1, -1);
225 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
226 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
227 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
229 static const arm_feature_set arm_cext_iwmmxt2 =
230 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
231 static const arm_feature_set arm_cext_iwmmxt =
232 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
233 static const arm_feature_set arm_cext_xscale =
234 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
235 static const arm_feature_set arm_cext_maverick =
236 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
237 static const arm_feature_set fpu_fpa_ext_v1 =
238 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
239 static const arm_feature_set fpu_fpa_ext_v2 =
240 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
241 static const arm_feature_set fpu_vfp_ext_v1xd =
242 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
243 static const arm_feature_set fpu_vfp_ext_v1 =
244 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
245 static const arm_feature_set fpu_vfp_ext_v2 =
246 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
247 static const arm_feature_set fpu_vfp_ext_v3xd =
248 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
249 static const arm_feature_set fpu_vfp_ext_v3 =
250 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
251 static const arm_feature_set fpu_vfp_ext_d32 =
252 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
253 static const arm_feature_set fpu_neon_ext_v1 =
254 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
255 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
256 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
257 static const arm_feature_set fpu_vfp_fp16 =
258 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
259 static const arm_feature_set fpu_neon_ext_fma =
260 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
261 static const arm_feature_set fpu_vfp_ext_fma =
262 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
263 static const arm_feature_set fpu_vfp_ext_armv8 =
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
265 static const arm_feature_set fpu_vfp_ext_armv8xd =
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
267 static const arm_feature_set fpu_neon_ext_armv8 =
268 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
269 static const arm_feature_set fpu_crypto_ext_armv8 =
270 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
271 static const arm_feature_set crc_ext_armv8 =
272 ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
273 static const arm_feature_set fpu_neon_ext_v8_1 =
274 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
276 static int mfloat_abi_opt = -1;
277 /* Record user cpu selection for object attributes. */
278 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
279 /* Must be long enough to hold any of the names in arm_cpus. */
280 static char selected_cpu_name[20];
282 extern FLONUM_TYPE generic_floating_point_number;
284 /* Return if no cpu was selected on command-line. */
286 no_cpu_selected (void)
288 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
293 static int meabi_flags = EABI_DEFAULT;
295 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
298 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
303 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
308 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
309 symbolS * GOT_symbol;
312 /* 0: assemble for ARM,
313 1: assemble for Thumb,
314 2: assemble for Thumb even though target CPU does not support thumb
316 static int thumb_mode = 0;
317 /* A value distinct from the possible values for thumb_mode that we
318 can use to record whether thumb_mode has been copied into the
319 tc_frag_data field of a frag. */
320 #define MODE_RECORDED (1 << 4)
322 /* Specifies the intrinsic IT insn behavior mode. */
323 enum implicit_it_mode
325 IMPLICIT_IT_MODE_NEVER = 0x00,
326 IMPLICIT_IT_MODE_ARM = 0x01,
327 IMPLICIT_IT_MODE_THUMB = 0x02,
328 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
330 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
332 /* If unified_syntax is true, we are processing the new unified
333 ARM/Thumb syntax. Important differences from the old ARM mode:
335 - Immediate operands do not require a # prefix.
336 - Conditional affixes always appear at the end of the
337 instruction. (For backward compatibility, those instructions
338 that formerly had them in the middle, continue to accept them
340 - The IT instruction may appear, and if it does is validated
341 against subsequent conditional affixes. It does not generate
344 Important differences from the old Thumb mode:
346 - Immediate operands do not require a # prefix.
347 - Most of the V6T2 instructions are only available in unified mode.
348 - The .N and .W suffixes are recognized and honored (it is an error
349 if they cannot be honored).
350 - All instructions set the flags if and only if they have an 's' affix.
351 - Conditional affixes may be used. They are validated against
352 preceding IT instructions. Unlike ARM mode, you cannot use a
353 conditional affix except in the scope of an IT instruction. */
355 static bfd_boolean unified_syntax = FALSE;
357 /* An immediate operand can start with #, and ld*, st*, pld operands
358 can contain [ and ]. We need to tell APP not to elide whitespace
359 before a [, which can appear as the first operand for pld.
360 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
361 const char arm_symbol_chars[] = "#[]{}";
376 enum neon_el_type type;
380 #define NEON_MAX_TYPE_ELS 4
384 struct neon_type_el el[NEON_MAX_TYPE_ELS];
388 enum it_instruction_type
393 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
394 if inside, should be the last one. */
395 NEUTRAL_IT_INSN, /* This could be either inside or outside,
396 i.e. BKPT and NOP. */
397 IT_INSN /* The IT insn has been parsed. */
400 /* The maximum number of operands we need. */
401 #define ARM_IT_MAX_OPERANDS 6
406 unsigned long instruction;
410 /* "uncond_value" is set to the value in place of the conditional field in
411 unconditional versions of the instruction, or -1 if nothing is
414 struct neon_type vectype;
415 /* This does not indicate an actual NEON instruction, only that
416 the mnemonic accepts neon-style type suffixes. */
418 /* Set to the opcode if the instruction needs relaxation.
419 Zero if the instruction is not relaxed. */
423 bfd_reloc_code_real_type type;
428 enum it_instruction_type it_insn_type;
434 struct neon_type_el vectype;
435 unsigned present : 1; /* Operand present. */
436 unsigned isreg : 1; /* Operand was a register. */
437 unsigned immisreg : 1; /* .imm field is a second register. */
438 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
439 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
440 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
441 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
442 instructions. This allows us to disambiguate ARM <-> vector insns. */
443 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
444 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
445 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
446 unsigned issingle : 1; /* Operand is VFP single-precision register. */
447 unsigned hasreloc : 1; /* Operand has relocation suffix. */
448 unsigned writeback : 1; /* Operand has trailing ! */
449 unsigned preind : 1; /* Preindexed address. */
450 unsigned postind : 1; /* Postindexed address. */
451 unsigned negative : 1; /* Index register was negated. */
452 unsigned shifted : 1; /* Shift applied to operation. */
453 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
454 } operands[ARM_IT_MAX_OPERANDS];
457 static struct arm_it inst;
459 #define NUM_FLOAT_VALS 8
461 const char * fp_const[] =
463 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
466 /* Number of littlenums required to hold an extended precision number. */
467 #define MAX_LITTLENUMS 6
469 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
479 #define CP_T_X 0x00008000
480 #define CP_T_Y 0x00400000
482 #define CONDS_BIT 0x00100000
483 #define LOAD_BIT 0x00100000
485 #define DOUBLE_LOAD_FLAG 0x00000001
489 const char * template_name;
493 #define COND_ALWAYS 0xE
497 const char * template_name;
501 struct asm_barrier_opt
503 const char * template_name;
505 const arm_feature_set arch;
508 /* The bit that distinguishes CPSR and SPSR. */
509 #define SPSR_BIT (1 << 22)
511 /* The individual PSR flag bits. */
512 #define PSR_c (1 << 16)
513 #define PSR_x (1 << 17)
514 #define PSR_s (1 << 18)
515 #define PSR_f (1 << 19)
520 bfd_reloc_code_real_type reloc;
525 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
526 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
531 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
534 /* Bits for DEFINED field in neon_typed_alias. */
535 #define NTA_HASTYPE 1
536 #define NTA_HASINDEX 2
538 struct neon_typed_alias
540 unsigned char defined;
542 struct neon_type_el eltype;
545 /* ARM register categories. This includes coprocessor numbers and various
546 architecture extensions' registers. */
573 /* Structure for a hash table entry for a register.
574 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
575 information which states whether a vector type or index is specified (for a
576 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
582 unsigned char builtin;
583 struct neon_typed_alias * neon;
586 /* Diagnostics used when we don't get a register of the expected type. */
587 const char * const reg_expected_msgs[] =
589 N_("ARM register expected"),
590 N_("bad or missing co-processor number"),
591 N_("co-processor register expected"),
592 N_("FPA register expected"),
593 N_("VFP single precision register expected"),
594 N_("VFP/Neon double precision register expected"),
595 N_("Neon quad precision register expected"),
596 N_("VFP single or double precision register expected"),
597 N_("Neon double or quad precision register expected"),
598 N_("VFP single, double or Neon quad precision register expected"),
599 N_("VFP system register expected"),
600 N_("Maverick MVF register expected"),
601 N_("Maverick MVD register expected"),
602 N_("Maverick MVFX register expected"),
603 N_("Maverick MVDX register expected"),
604 N_("Maverick MVAX register expected"),
605 N_("Maverick DSPSC register expected"),
606 N_("iWMMXt data register expected"),
607 N_("iWMMXt control register expected"),
608 N_("iWMMXt scalar register expected"),
609 N_("XScale accumulator register expected"),
612 /* Some well known registers that we refer to directly elsewhere. */
618 /* ARM instructions take 4bytes in the object file, Thumb instructions
624 /* Basic string to match. */
625 const char * template_name;
627 /* Parameters to instruction. */
628 unsigned int operands[8];
630 /* Conditional tag - see opcode_lookup. */
631 unsigned int tag : 4;
633 /* Basic instruction code. */
634 unsigned int avalue : 28;
636 /* Thumb-format instruction code. */
639 /* Which architecture variant provides this instruction. */
640 const arm_feature_set * avariant;
641 const arm_feature_set * tvariant;
643 /* Function to call to encode instruction in ARM format. */
644 void (* aencode) (void);
646 /* Function to call to encode instruction in Thumb format. */
647 void (* tencode) (void);
650 /* Defines for various bits that we will want to toggle. */
651 #define INST_IMMEDIATE 0x02000000
652 #define OFFSET_REG 0x02000000
653 #define HWOFFSET_IMM 0x00400000
654 #define SHIFT_BY_REG 0x00000010
655 #define PRE_INDEX 0x01000000
656 #define INDEX_UP 0x00800000
657 #define WRITE_BACK 0x00200000
658 #define LDM_TYPE_2_OR_3 0x00400000
659 #define CPSI_MMOD 0x00020000
661 #define LITERAL_MASK 0xf000f000
662 #define OPCODE_MASK 0xfe1fffff
663 #define V4_STR_BIT 0x00000020
664 #define VLDR_VMOV_SAME 0x0040f000
666 #define T2_SUBS_PC_LR 0xf3de8f00
668 #define DATA_OP_SHIFT 21
670 #define T2_OPCODE_MASK 0xfe1fffff
671 #define T2_DATA_OP_SHIFT 21
673 #define A_COND_MASK 0xf0000000
674 #define A_PUSH_POP_OP_MASK 0x0fff0000
676 /* Opcodes for pushing/poping registers to/from the stack. */
677 #define A1_OPCODE_PUSH 0x092d0000
678 #define A2_OPCODE_PUSH 0x052d0004
679 #define A2_OPCODE_POP 0x049d0004
681 /* Codes to distinguish the arithmetic instructions. */
692 #define OPCODE_CMP 10
693 #define OPCODE_CMN 11
694 #define OPCODE_ORR 12
695 #define OPCODE_MOV 13
696 #define OPCODE_BIC 14
697 #define OPCODE_MVN 15
699 #define T2_OPCODE_AND 0
700 #define T2_OPCODE_BIC 1
701 #define T2_OPCODE_ORR 2
702 #define T2_OPCODE_ORN 3
703 #define T2_OPCODE_EOR 4
704 #define T2_OPCODE_ADD 8
705 #define T2_OPCODE_ADC 10
706 #define T2_OPCODE_SBC 11
707 #define T2_OPCODE_SUB 13
708 #define T2_OPCODE_RSB 14
710 #define T_OPCODE_MUL 0x4340
711 #define T_OPCODE_TST 0x4200
712 #define T_OPCODE_CMN 0x42c0
713 #define T_OPCODE_NEG 0x4240
714 #define T_OPCODE_MVN 0x43c0
716 #define T_OPCODE_ADD_R3 0x1800
717 #define T_OPCODE_SUB_R3 0x1a00
718 #define T_OPCODE_ADD_HI 0x4400
719 #define T_OPCODE_ADD_ST 0xb000
720 #define T_OPCODE_SUB_ST 0xb080
721 #define T_OPCODE_ADD_SP 0xa800
722 #define T_OPCODE_ADD_PC 0xa000
723 #define T_OPCODE_ADD_I8 0x3000
724 #define T_OPCODE_SUB_I8 0x3800
725 #define T_OPCODE_ADD_I3 0x1c00
726 #define T_OPCODE_SUB_I3 0x1e00
728 #define T_OPCODE_ASR_R 0x4100
729 #define T_OPCODE_LSL_R 0x4080
730 #define T_OPCODE_LSR_R 0x40c0
731 #define T_OPCODE_ROR_R 0x41c0
732 #define T_OPCODE_ASR_I 0x1000
733 #define T_OPCODE_LSL_I 0x0000
734 #define T_OPCODE_LSR_I 0x0800
736 #define T_OPCODE_MOV_I8 0x2000
737 #define T_OPCODE_CMP_I8 0x2800
738 #define T_OPCODE_CMP_LR 0x4280
739 #define T_OPCODE_MOV_HR 0x4600
740 #define T_OPCODE_CMP_HR 0x4500
742 #define T_OPCODE_LDR_PC 0x4800
743 #define T_OPCODE_LDR_SP 0x9800
744 #define T_OPCODE_STR_SP 0x9000
745 #define T_OPCODE_LDR_IW 0x6800
746 #define T_OPCODE_STR_IW 0x6000
747 #define T_OPCODE_LDR_IH 0x8800
748 #define T_OPCODE_STR_IH 0x8000
749 #define T_OPCODE_LDR_IB 0x7800
750 #define T_OPCODE_STR_IB 0x7000
751 #define T_OPCODE_LDR_RW 0x5800
752 #define T_OPCODE_STR_RW 0x5000
753 #define T_OPCODE_LDR_RH 0x5a00
754 #define T_OPCODE_STR_RH 0x5200
755 #define T_OPCODE_LDR_RB 0x5c00
756 #define T_OPCODE_STR_RB 0x5400
758 #define T_OPCODE_PUSH 0xb400
759 #define T_OPCODE_POP 0xbc00
761 #define T_OPCODE_BRANCH 0xe000
763 #define THUMB_SIZE 2 /* Size of thumb instruction. */
764 #define THUMB_PP_PC_LR 0x0100
765 #define THUMB_LOAD_BIT 0x0800
766 #define THUMB2_LOAD_BIT 0x00100000
768 #define BAD_ARGS _("bad arguments to instruction")
769 #define BAD_SP _("r13 not allowed here")
770 #define BAD_PC _("r15 not allowed here")
771 #define BAD_COND _("instruction cannot be conditional")
772 #define BAD_OVERLAP _("registers may not be the same")
773 #define BAD_HIREG _("lo register required")
774 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
775 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
776 #define BAD_BRANCH _("branch must be last instruction in IT block")
777 #define BAD_NOT_IT _("instruction not allowed in IT block")
778 #define BAD_FPU _("selected FPU does not support instruction")
779 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
780 #define BAD_IT_COND _("incorrect condition in IT block")
781 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
782 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
783 #define BAD_PC_ADDRESSING \
784 _("cannot use register index with PC-relative addressing")
785 #define BAD_PC_WRITEBACK \
786 _("cannot use writeback with PC-relative addressing")
787 #define BAD_RANGE _("branch out of range")
788 #define BAD_FP16 _("selected processor does not support fp16 instruction")
789 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
790 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
792 static struct hash_control * arm_ops_hsh;
793 static struct hash_control * arm_cond_hsh;
794 static struct hash_control * arm_shift_hsh;
795 static struct hash_control * arm_psr_hsh;
796 static struct hash_control * arm_v7m_psr_hsh;
797 static struct hash_control * arm_reg_hsh;
798 static struct hash_control * arm_reloc_hsh;
799 static struct hash_control * arm_barrier_opt_hsh;
801 /* Stuff needed to resolve the label ambiguity
810 symbolS * last_label_seen;
811 static int label_is_thumb_function_name = FALSE;
813 /* Literal pool structure. Held on a per-section
814 and per-sub-section basis. */
816 #define MAX_LITERAL_POOL_SIZE 1024
817 typedef struct literal_pool
819 expressionS literals [MAX_LITERAL_POOL_SIZE];
820 unsigned int next_free_entry;
826 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
828 struct literal_pool * next;
829 unsigned int alignment;
832 /* Pointer to a linked list of literal pools. */
833 literal_pool * list_of_pools = NULL;
835 typedef enum asmfunc_states
838 WAITING_ASMFUNC_NAME,
842 static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
845 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
847 static struct current_it now_it;
851 now_it_compatible (int cond)
853 return (cond & ~1) == (now_it.cc & ~1);
857 conditional_insn (void)
859 return inst.cond != COND_ALWAYS;
862 static int in_it_block (void);
864 static int handle_it_state (void);
866 static void force_automatic_it_block_close (void);
868 static void it_fsm_post_encode (void);
870 #define set_it_insn_type(type) \
873 inst.it_insn_type = type; \
874 if (handle_it_state () == FAIL) \
879 #define set_it_insn_type_nonvoid(type, failret) \
882 inst.it_insn_type = type; \
883 if (handle_it_state () == FAIL) \
888 #define set_it_insn_type_last() \
891 if (inst.cond == COND_ALWAYS) \
892 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
894 set_it_insn_type (INSIDE_IT_LAST_INSN); \
900 /* This array holds the chars that always start a comment. If the
901 pre-processor is disabled, these aren't very useful. */
902 char arm_comment_chars[] = "@";
904 /* This array holds the chars that only start a comment at the beginning of
905 a line. If the line seems to have the form '# 123 filename'
906 .line and .file directives will appear in the pre-processed output. */
907 /* Note that input_file.c hand checks for '#' at the beginning of the
908 first line of the input file. This is because the compiler outputs
909 #NO_APP at the beginning of its output. */
910 /* Also note that comments like this one will always work. */
911 const char line_comment_chars[] = "#";
913 char arm_line_separator_chars[] = ";";
915 /* Chars that can be used to separate mant
916 from exp in floating point numbers. */
917 const char EXP_CHARS[] = "eE";
919 /* Chars that mean this number is a floating point constant. */
923 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
925 /* Prefix characters that indicate the start of an immediate
927 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
929 /* Separator character handling. */
931 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
934 skip_past_char (char ** str, char c)
936 /* PR gas/14987: Allow for whitespace before the expected character. */
937 skip_whitespace (*str);
948 #define skip_past_comma(str) skip_past_char (str, ',')
950 /* Arithmetic expressions (possibly involving symbols). */
952 /* Return TRUE if anything in the expression is a bignum. */
955 walk_no_bignums (symbolS * sp)
957 if (symbol_get_value_expression (sp)->X_op == O_big)
960 if (symbol_get_value_expression (sp)->X_add_symbol)
962 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
963 || (symbol_get_value_expression (sp)->X_op_symbol
964 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
970 static int in_my_get_expression = 0;
972 /* Third argument to my_get_expression. */
973 #define GE_NO_PREFIX 0
974 #define GE_IMM_PREFIX 1
975 #define GE_OPT_PREFIX 2
976 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
977 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
978 #define GE_OPT_PREFIX_BIG 3
981 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
986 /* In unified syntax, all prefixes are optional. */
988 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
993 case GE_NO_PREFIX: break;
995 if (!is_immediate_prefix (**str))
997 inst.error = _("immediate expression requires a # prefix");
1003 case GE_OPT_PREFIX_BIG:
1004 if (is_immediate_prefix (**str))
1010 memset (ep, 0, sizeof (expressionS));
1012 save_in = input_line_pointer;
1013 input_line_pointer = *str;
1014 in_my_get_expression = 1;
1015 seg = expression (ep);
1016 in_my_get_expression = 0;
1018 if (ep->X_op == O_illegal || ep->X_op == O_absent)
1020 /* We found a bad or missing expression in md_operand(). */
1021 *str = input_line_pointer;
1022 input_line_pointer = save_in;
1023 if (inst.error == NULL)
1024 inst.error = (ep->X_op == O_absent
1025 ? _("missing expression") :_("bad expression"));
1030 if (seg != absolute_section
1031 && seg != text_section
1032 && seg != data_section
1033 && seg != bss_section
1034 && seg != undefined_section)
1036 inst.error = _("bad segment");
1037 *str = input_line_pointer;
1038 input_line_pointer = save_in;
1045 /* Get rid of any bignums now, so that we don't generate an error for which
1046 we can't establish a line number later on. Big numbers are never valid
1047 in instructions, which is where this routine is always called. */
1048 if (prefix_mode != GE_OPT_PREFIX_BIG
1049 && (ep->X_op == O_big
1050 || (ep->X_add_symbol
1051 && (walk_no_bignums (ep->X_add_symbol)
1053 && walk_no_bignums (ep->X_op_symbol))))))
1055 inst.error = _("invalid constant");
1056 *str = input_line_pointer;
1057 input_line_pointer = save_in;
1061 *str = input_line_pointer;
1062 input_line_pointer = save_in;
1066 /* Turn a string in input_line_pointer into a floating point constant
1067 of type TYPE, and store the appropriate bytes in *LITP. The number
1068 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1069 returned, or NULL on OK.
1071 Note that fp constants aren't represent in the normal way on the ARM.
1072 In big endian mode, things are as expected. However, in little endian
1073 mode fp constants are big-endian word-wise, and little-endian byte-wise
1074 within the words. For example, (double) 1.1 in big endian mode is
1075 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1076 the byte sequence 99 99 f1 3f 9a 99 99 99.
1078 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1081 md_atof (int type, char * litP, int * sizeP)
1084 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1116 return _("Unrecognized or unsupported floating point constant");
1119 t = atof_ieee (input_line_pointer, type, words);
1121 input_line_pointer = t;
1122 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1124 if (target_big_endian)
1126 for (i = 0; i < prec; i++)
1128 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1129 litP += sizeof (LITTLENUM_TYPE);
1134 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1135 for (i = prec - 1; i >= 0; i--)
1137 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1138 litP += sizeof (LITTLENUM_TYPE);
1141 /* For a 4 byte float the order of elements in `words' is 1 0.
1142 For an 8 byte float the order is 1 0 3 2. */
1143 for (i = 0; i < prec; i += 2)
1145 md_number_to_chars (litP, (valueT) words[i + 1],
1146 sizeof (LITTLENUM_TYPE));
1147 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1148 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1149 litP += 2 * sizeof (LITTLENUM_TYPE);
1156 /* We handle all bad expressions here, so that we can report the faulty
1157 instruction in the error message. */
1159 md_operand (expressionS * exp)
1161 if (in_my_get_expression)
1162 exp->X_op = O_illegal;
1165 /* Immediate values. */
1167 /* Generic immediate-value read function for use in directives.
1168 Accepts anything that 'expression' can fold to a constant.
1169 *val receives the number. */
1172 immediate_for_directive (int *val)
1175 exp.X_op = O_illegal;
1177 if (is_immediate_prefix (*input_line_pointer))
1179 input_line_pointer++;
1183 if (exp.X_op != O_constant)
1185 as_bad (_("expected #constant"));
1186 ignore_rest_of_line ();
1189 *val = exp.X_add_number;
1194 /* Register parsing. */
1196 /* Generic register parser. CCP points to what should be the
1197 beginning of a register name. If it is indeed a valid register
1198 name, advance CCP over it and return the reg_entry structure;
1199 otherwise return NULL. Does not issue diagnostics. */
1201 static struct reg_entry *
1202 arm_reg_parse_multi (char **ccp)
1206 struct reg_entry *reg;
1208 skip_whitespace (start);
1210 #ifdef REGISTER_PREFIX
1211 if (*start != REGISTER_PREFIX)
1215 #ifdef OPTIONAL_REGISTER_PREFIX
1216 if (*start == OPTIONAL_REGISTER_PREFIX)
1221 if (!ISALPHA (*p) || !is_name_beginner (*p))
1226 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1228 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1238 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1239 enum arm_reg_type type)
1241 /* Alternative syntaxes are accepted for a few register classes. */
1248 /* Generic coprocessor register names are allowed for these. */
1249 if (reg && reg->type == REG_TYPE_CN)
1254 /* For backward compatibility, a bare number is valid here. */
1256 unsigned long processor = strtoul (start, ccp, 10);
1257 if (*ccp != start && processor <= 15)
1261 case REG_TYPE_MMXWC:
1262 /* WC includes WCG. ??? I'm not sure this is true for all
1263 instructions that take WC registers. */
1264 if (reg && reg->type == REG_TYPE_MMXWCG)
1275 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1276 return value is the register number or FAIL. */
1279 arm_reg_parse (char **ccp, enum arm_reg_type type)
1282 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1285 /* Do not allow a scalar (reg+index) to parse as a register. */
1286 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1289 if (reg && reg->type == type)
1292 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1299 /* Parse a Neon type specifier. *STR should point at the leading '.'
1300 character. Does no verification at this stage that the type fits the opcode
1307 Can all be legally parsed by this function.
1309 Fills in neon_type struct pointer with parsed information, and updates STR
1310 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1311 type, FAIL if not. */
1314 parse_neon_type (struct neon_type *type, char **str)
1321 while (type->elems < NEON_MAX_TYPE_ELS)
1323 enum neon_el_type thistype = NT_untyped;
1324 unsigned thissize = -1u;
1331 /* Just a size without an explicit type. */
1335 switch (TOLOWER (*ptr))
1337 case 'i': thistype = NT_integer; break;
1338 case 'f': thistype = NT_float; break;
1339 case 'p': thistype = NT_poly; break;
1340 case 's': thistype = NT_signed; break;
1341 case 'u': thistype = NT_unsigned; break;
1343 thistype = NT_float;
1348 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1354 /* .f is an abbreviation for .f32. */
1355 if (thistype == NT_float && !ISDIGIT (*ptr))
1360 thissize = strtoul (ptr, &ptr, 10);
1362 if (thissize != 8 && thissize != 16 && thissize != 32
1365 as_bad (_("bad size %d in type specifier"), thissize);
1373 type->el[type->elems].type = thistype;
1374 type->el[type->elems].size = thissize;
1379 /* Empty/missing type is not a successful parse. */
1380 if (type->elems == 0)
1388 /* Errors may be set multiple times during parsing or bit encoding
1389 (particularly in the Neon bits), but usually the earliest error which is set
1390 will be the most meaningful. Avoid overwriting it with later (cascading)
1391 errors by calling this function. */
1394 first_error (const char *err)
1400 /* Parse a single type, e.g. ".s32", leading period included. */
1402 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1405 struct neon_type optype;
1409 if (parse_neon_type (&optype, &str) == SUCCESS)
1411 if (optype.elems == 1)
1412 *vectype = optype.el[0];
1415 first_error (_("only one type should be specified for operand"));
1421 first_error (_("vector type expected"));
1433 /* Special meanings for indices (which have a range of 0-7), which will fit into
1436 #define NEON_ALL_LANES 15
1437 #define NEON_INTERLEAVE_LANES 14
1439 /* Parse either a register or a scalar, with an optional type. Return the
1440 register number, and optionally fill in the actual type of the register
1441 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1442 type/index information in *TYPEINFO. */
1445 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1446 enum arm_reg_type *rtype,
1447 struct neon_typed_alias *typeinfo)
1450 struct reg_entry *reg = arm_reg_parse_multi (&str);
1451 struct neon_typed_alias atype;
1452 struct neon_type_el parsetype;
1456 atype.eltype.type = NT_invtype;
1457 atype.eltype.size = -1;
1459 /* Try alternate syntax for some types of register. Note these are mutually
1460 exclusive with the Neon syntax extensions. */
1463 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1471 /* Undo polymorphism when a set of register types may be accepted. */
1472 if ((type == REG_TYPE_NDQ
1473 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1474 || (type == REG_TYPE_VFSD
1475 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1476 || (type == REG_TYPE_NSDQ
1477 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1478 || reg->type == REG_TYPE_NQ))
1479 || (type == REG_TYPE_MMXWC
1480 && (reg->type == REG_TYPE_MMXWCG)))
1481 type = (enum arm_reg_type) reg->type;
1483 if (type != reg->type)
1489 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1491 if ((atype.defined & NTA_HASTYPE) != 0)
1493 first_error (_("can't redefine type for operand"));
1496 atype.defined |= NTA_HASTYPE;
1497 atype.eltype = parsetype;
1500 if (skip_past_char (&str, '[') == SUCCESS)
1502 if (type != REG_TYPE_VFD)
1504 first_error (_("only D registers may be indexed"));
1508 if ((atype.defined & NTA_HASINDEX) != 0)
1510 first_error (_("can't change index for operand"));
1514 atype.defined |= NTA_HASINDEX;
1516 if (skip_past_char (&str, ']') == SUCCESS)
1517 atype.index = NEON_ALL_LANES;
1522 my_get_expression (&exp, &str, GE_NO_PREFIX);
1524 if (exp.X_op != O_constant)
1526 first_error (_("constant expression required"));
1530 if (skip_past_char (&str, ']') == FAIL)
1533 atype.index = exp.X_add_number;
1548 /* Like arm_reg_parse, but allow allow the following extra features:
1549 - If RTYPE is non-zero, return the (possibly restricted) type of the
1550 register (e.g. Neon double or quad reg when either has been requested).
1551 - If this is a Neon vector type with additional type information, fill
1552 in the struct pointed to by VECTYPE (if non-NULL).
1553 This function will fault on encountering a scalar. */
1556 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1557 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1559 struct neon_typed_alias atype;
1561 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1566 /* Do not allow regname(... to parse as a register. */
1570 /* Do not allow a scalar (reg+index) to parse as a register. */
1571 if ((atype.defined & NTA_HASINDEX) != 0)
1573 first_error (_("register operand expected, but got scalar"));
1578 *vectype = atype.eltype;
1585 #define NEON_SCALAR_REG(X) ((X) >> 4)
1586 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1588 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1589 have enough information to be able to do a good job bounds-checking. So, we
1590 just do easy checks here, and do further checks later. */
1593 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1597 struct neon_typed_alias atype;
1599 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1601 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1604 if (atype.index == NEON_ALL_LANES)
1606 first_error (_("scalar must have an index"));
1609 else if (atype.index >= 64 / elsize)
1611 first_error (_("scalar index out of range"));
1616 *type = atype.eltype;
1620 return reg * 16 + atype.index;
1623 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1626 parse_reg_list (char ** strp)
1628 char * str = * strp;
1632 /* We come back here if we get ranges concatenated by '+' or '|'. */
1635 skip_whitespace (str);
1649 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1651 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1661 first_error (_("bad range in register list"));
1665 for (i = cur_reg + 1; i < reg; i++)
1667 if (range & (1 << i))
1669 (_("Warning: duplicated register (r%d) in register list"),
1677 if (range & (1 << reg))
1678 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1680 else if (reg <= cur_reg)
1681 as_tsktsk (_("Warning: register range not in ascending order"));
1686 while (skip_past_comma (&str) != FAIL
1687 || (in_range = 1, *str++ == '-'));
1690 if (skip_past_char (&str, '}') == FAIL)
1692 first_error (_("missing `}'"));
1700 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1703 if (exp.X_op == O_constant)
1705 if (exp.X_add_number
1706 != (exp.X_add_number & 0x0000ffff))
1708 inst.error = _("invalid register mask");
1712 if ((range & exp.X_add_number) != 0)
1714 int regno = range & exp.X_add_number;
1717 regno = (1 << regno) - 1;
1719 (_("Warning: duplicated register (r%d) in register list"),
1723 range |= exp.X_add_number;
1727 if (inst.reloc.type != 0)
1729 inst.error = _("expression too complex");
1733 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1734 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1735 inst.reloc.pc_rel = 0;
1739 if (*str == '|' || *str == '+')
1745 while (another_range);
1751 /* Types of registers in a list. */
1760 /* Parse a VFP register list. If the string is invalid return FAIL.
1761 Otherwise return the number of registers, and set PBASE to the first
1762 register. Parses registers of type ETYPE.
1763 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1764 - Q registers can be used to specify pairs of D registers
1765 - { } can be omitted from around a singleton register list
1766 FIXME: This is not implemented, as it would require backtracking in
1769 This could be done (the meaning isn't really ambiguous), but doesn't
1770 fit in well with the current parsing framework.
1771 - 32 D registers may be used (also true for VFPv3).
1772 FIXME: Types are ignored in these register lists, which is probably a
1776 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1781 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1785 unsigned long mask = 0;
1788 if (skip_past_char (&str, '{') == FAIL)
1790 inst.error = _("expecting {");
1797 regtype = REG_TYPE_VFS;
1802 regtype = REG_TYPE_VFD;
1805 case REGLIST_NEON_D:
1806 regtype = REG_TYPE_NDQ;
1810 if (etype != REGLIST_VFP_S)
1812 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1813 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1817 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1820 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1827 base_reg = max_regs;
1831 int setmask = 1, addregs = 1;
1833 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1835 if (new_base == FAIL)
1837 first_error (_(reg_expected_msgs[regtype]));
1841 if (new_base >= max_regs)
1843 first_error (_("register out of range in list"));
1847 /* Note: a value of 2 * n is returned for the register Q<n>. */
1848 if (regtype == REG_TYPE_NQ)
1854 if (new_base < base_reg)
1855 base_reg = new_base;
1857 if (mask & (setmask << new_base))
1859 first_error (_("invalid register list"));
1863 if ((mask >> new_base) != 0 && ! warned)
1865 as_tsktsk (_("register list not in ascending order"));
1869 mask |= setmask << new_base;
1872 if (*str == '-') /* We have the start of a range expression */
1878 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1881 inst.error = gettext (reg_expected_msgs[regtype]);
1885 if (high_range >= max_regs)
1887 first_error (_("register out of range in list"));
1891 if (regtype == REG_TYPE_NQ)
1892 high_range = high_range + 1;
1894 if (high_range <= new_base)
1896 inst.error = _("register range not in ascending order");
1900 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1902 if (mask & (setmask << new_base))
1904 inst.error = _("invalid register list");
1908 mask |= setmask << new_base;
1913 while (skip_past_comma (&str) != FAIL);
1917 /* Sanity check -- should have raised a parse error above. */
1918 if (count == 0 || count > max_regs)
1923 /* Final test -- the registers must be consecutive. */
1925 for (i = 0; i < count; i++)
1927 if ((mask & (1u << i)) == 0)
1929 inst.error = _("non-contiguous register range");
1939 /* True if two alias types are the same. */
1942 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1950 if (a->defined != b->defined)
1953 if ((a->defined & NTA_HASTYPE) != 0
1954 && (a->eltype.type != b->eltype.type
1955 || a->eltype.size != b->eltype.size))
1958 if ((a->defined & NTA_HASINDEX) != 0
1959 && (a->index != b->index))
1965 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1966 The base register is put in *PBASE.
1967 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1969 The register stride (minus one) is put in bit 4 of the return value.
1970 Bits [6:5] encode the list length (minus one).
1971 The type of the list elements is put in *ELTYPE, if non-NULL. */
1973 #define NEON_LANE(X) ((X) & 0xf)
1974 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1975 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1978 parse_neon_el_struct_list (char **str, unsigned *pbase,
1979 struct neon_type_el *eltype)
1986 int leading_brace = 0;
1987 enum arm_reg_type rtype = REG_TYPE_NDQ;
1988 const char *const incr_error = _("register stride must be 1 or 2");
1989 const char *const type_error = _("mismatched element/structure types in list");
1990 struct neon_typed_alias firsttype;
1992 if (skip_past_char (&ptr, '{') == SUCCESS)
1997 struct neon_typed_alias atype;
1998 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2002 first_error (_(reg_expected_msgs[rtype]));
2009 if (rtype == REG_TYPE_NQ)
2015 else if (reg_incr == -1)
2017 reg_incr = getreg - base_reg;
2018 if (reg_incr < 1 || reg_incr > 2)
2020 first_error (_(incr_error));
2024 else if (getreg != base_reg + reg_incr * count)
2026 first_error (_(incr_error));
2030 if (! neon_alias_types_same (&atype, &firsttype))
2032 first_error (_(type_error));
2036 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2040 struct neon_typed_alias htype;
2041 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2043 lane = NEON_INTERLEAVE_LANES;
2044 else if (lane != NEON_INTERLEAVE_LANES)
2046 first_error (_(type_error));
2051 else if (reg_incr != 1)
2053 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2057 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2060 first_error (_(reg_expected_msgs[rtype]));
2063 if (! neon_alias_types_same (&htype, &firsttype))
2065 first_error (_(type_error));
2068 count += hireg + dregs - getreg;
2072 /* If we're using Q registers, we can't use [] or [n] syntax. */
2073 if (rtype == REG_TYPE_NQ)
2079 if ((atype.defined & NTA_HASINDEX) != 0)
2083 else if (lane != atype.index)
2085 first_error (_(type_error));
2089 else if (lane == -1)
2090 lane = NEON_INTERLEAVE_LANES;
2091 else if (lane != NEON_INTERLEAVE_LANES)
2093 first_error (_(type_error));
2098 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2100 /* No lane set by [x]. We must be interleaving structures. */
2102 lane = NEON_INTERLEAVE_LANES;
2105 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2106 || (count > 1 && reg_incr == -1))
2108 first_error (_("error parsing element/structure list"));
2112 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2114 first_error (_("expected }"));
2122 *eltype = firsttype.eltype;
2127 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2130 /* Parse an explicit relocation suffix on an expression. This is
2131 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2132 arm_reloc_hsh contains no entries, so this function can only
2133 succeed if there is no () after the word. Returns -1 on error,
2134 BFD_RELOC_UNUSED if there wasn't any suffix. */
2137 parse_reloc (char **str)
2139 struct reloc_entry *r;
2143 return BFD_RELOC_UNUSED;
2148 while (*q && *q != ')' && *q != ',')
2153 if ((r = (struct reloc_entry *)
2154 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2161 /* Directives: register aliases. */
2163 static struct reg_entry *
2164 insert_reg_alias (char *str, unsigned number, int type)
2166 struct reg_entry *new_reg;
2169 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2171 if (new_reg->builtin)
2172 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2174 /* Only warn about a redefinition if it's not defined as the
2176 else if (new_reg->number != number || new_reg->type != type)
2177 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2182 name = xstrdup (str);
2183 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2185 new_reg->name = name;
2186 new_reg->number = number;
2187 new_reg->type = type;
2188 new_reg->builtin = FALSE;
2189 new_reg->neon = NULL;
2191 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2198 insert_neon_reg_alias (char *str, int number, int type,
2199 struct neon_typed_alias *atype)
2201 struct reg_entry *reg = insert_reg_alias (str, number, type);
2205 first_error (_("attempt to redefine typed alias"));
2211 reg->neon = (struct neon_typed_alias *)
2212 xmalloc (sizeof (struct neon_typed_alias));
2213 *reg->neon = *atype;
2217 /* Look for the .req directive. This is of the form:
2219 new_register_name .req existing_register_name
2221 If we find one, or if it looks sufficiently like one that we want to
2222 handle any error here, return TRUE. Otherwise return FALSE. */
2225 create_register_alias (char * newname, char *p)
2227 struct reg_entry *old;
2228 char *oldname, *nbuf;
2231 /* The input scrubber ensures that whitespace after the mnemonic is
2232 collapsed to single spaces. */
2234 if (strncmp (oldname, " .req ", 6) != 0)
2238 if (*oldname == '\0')
2241 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2244 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2248 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2249 the desired alias name, and p points to its end. If not, then
2250 the desired alias name is in the global original_case_string. */
2251 #ifdef TC_CASE_SENSITIVE
2254 newname = original_case_string;
2255 nlen = strlen (newname);
2258 nbuf = xmalloc (nlen + 1);
2259 memcpy (nbuf, newname, nlen);
2262 /* Create aliases under the new name as stated; an all-lowercase
2263 version of the new name; and an all-uppercase version of the new
2265 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2267 for (p = nbuf; *p; p++)
2270 if (strncmp (nbuf, newname, nlen))
2272 /* If this attempt to create an additional alias fails, do not bother
2273 trying to create the all-lower case alias. We will fail and issue
2274 a second, duplicate error message. This situation arises when the
2275 programmer does something like:
2278 The second .req creates the "Foo" alias but then fails to create
2279 the artificial FOO alias because it has already been created by the
2281 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2288 for (p = nbuf; *p; p++)
2291 if (strncmp (nbuf, newname, nlen))
2292 insert_reg_alias (nbuf, old->number, old->type);
2299 /* Create a Neon typed/indexed register alias using directives, e.g.:
2304 These typed registers can be used instead of the types specified after the
2305 Neon mnemonic, so long as all operands given have types. Types can also be
2306 specified directly, e.g.:
2307 vadd d0.s32, d1.s32, d2.s32 */
2310 create_neon_reg_alias (char *newname, char *p)
2312 enum arm_reg_type basetype;
2313 struct reg_entry *basereg;
2314 struct reg_entry mybasereg;
2315 struct neon_type ntype;
2316 struct neon_typed_alias typeinfo;
2317 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2320 typeinfo.defined = 0;
2321 typeinfo.eltype.type = NT_invtype;
2322 typeinfo.eltype.size = -1;
2323 typeinfo.index = -1;
2327 if (strncmp (p, " .dn ", 5) == 0)
2328 basetype = REG_TYPE_VFD;
2329 else if (strncmp (p, " .qn ", 5) == 0)
2330 basetype = REG_TYPE_NQ;
2339 basereg = arm_reg_parse_multi (&p);
2341 if (basereg && basereg->type != basetype)
2343 as_bad (_("bad type for register"));
2347 if (basereg == NULL)
2350 /* Try parsing as an integer. */
2351 my_get_expression (&exp, &p, GE_NO_PREFIX);
2352 if (exp.X_op != O_constant)
2354 as_bad (_("expression must be constant"));
2357 basereg = &mybasereg;
2358 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2364 typeinfo = *basereg->neon;
2366 if (parse_neon_type (&ntype, &p) == SUCCESS)
2368 /* We got a type. */
2369 if (typeinfo.defined & NTA_HASTYPE)
2371 as_bad (_("can't redefine the type of a register alias"));
2375 typeinfo.defined |= NTA_HASTYPE;
2376 if (ntype.elems != 1)
2378 as_bad (_("you must specify a single type only"));
2381 typeinfo.eltype = ntype.el[0];
2384 if (skip_past_char (&p, '[') == SUCCESS)
2387 /* We got a scalar index. */
2389 if (typeinfo.defined & NTA_HASINDEX)
2391 as_bad (_("can't redefine the index of a scalar alias"));
2395 my_get_expression (&exp, &p, GE_NO_PREFIX);
2397 if (exp.X_op != O_constant)
2399 as_bad (_("scalar index must be constant"));
2403 typeinfo.defined |= NTA_HASINDEX;
2404 typeinfo.index = exp.X_add_number;
2406 if (skip_past_char (&p, ']') == FAIL)
2408 as_bad (_("expecting ]"));
2413 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2414 the desired alias name, and p points to its end. If not, then
2415 the desired alias name is in the global original_case_string. */
2416 #ifdef TC_CASE_SENSITIVE
2417 namelen = nameend - newname;
2419 newname = original_case_string;
2420 namelen = strlen (newname);
2423 namebuf = xmalloc (namelen + 1);
2424 strncpy (namebuf, newname, namelen);
2425 namebuf[namelen] = '\0';
2427 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2428 typeinfo.defined != 0 ? &typeinfo : NULL);
2430 /* Insert name in all uppercase. */
2431 for (p = namebuf; *p; p++)
2434 if (strncmp (namebuf, newname, namelen))
2435 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2436 typeinfo.defined != 0 ? &typeinfo : NULL);
2438 /* Insert name in all lowercase. */
2439 for (p = namebuf; *p; p++)
2442 if (strncmp (namebuf, newname, namelen))
2443 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2444 typeinfo.defined != 0 ? &typeinfo : NULL);
2450 /* Should never be called, as .req goes between the alias and the
2451 register name, not at the beginning of the line. */
2454 s_req (int a ATTRIBUTE_UNUSED)
2456 as_bad (_("invalid syntax for .req directive"));
2460 s_dn (int a ATTRIBUTE_UNUSED)
2462 as_bad (_("invalid syntax for .dn directive"));
2466 s_qn (int a ATTRIBUTE_UNUSED)
2468 as_bad (_("invalid syntax for .qn directive"));
2471 /* The .unreq directive deletes an alias which was previously defined
2472 by .req. For example:
2478 s_unreq (int a ATTRIBUTE_UNUSED)
2483 name = input_line_pointer;
2485 while (*input_line_pointer != 0
2486 && *input_line_pointer != ' '
2487 && *input_line_pointer != '\n')
2488 ++input_line_pointer;
2490 saved_char = *input_line_pointer;
2491 *input_line_pointer = 0;
2494 as_bad (_("invalid syntax for .unreq directive"));
2497 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2501 as_bad (_("unknown register alias '%s'"), name);
2502 else if (reg->builtin)
2503 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2510 hash_delete (arm_reg_hsh, name, FALSE);
2511 free ((char *) reg->name);
2516 /* Also locate the all upper case and all lower case versions.
2517 Do not complain if we cannot find one or the other as it
2518 was probably deleted above. */
2520 nbuf = strdup (name);
2521 for (p = nbuf; *p; p++)
2523 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2526 hash_delete (arm_reg_hsh, nbuf, FALSE);
2527 free ((char *) reg->name);
2533 for (p = nbuf; *p; p++)
2535 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2538 hash_delete (arm_reg_hsh, nbuf, FALSE);
2539 free ((char *) reg->name);
2549 *input_line_pointer = saved_char;
2550 demand_empty_rest_of_line ();
2553 /* Directives: Instruction set selection. */
2556 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2557 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2558 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2559 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2561 /* Create a new mapping symbol for the transition to STATE. */
2564 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2567 const char * symname;
2574 type = BSF_NO_FLAGS;
2578 type = BSF_NO_FLAGS;
2582 type = BSF_NO_FLAGS;
2588 symbolP = symbol_new (symname, now_seg, value, frag);
2589 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2594 THUMB_SET_FUNC (symbolP, 0);
2595 ARM_SET_THUMB (symbolP, 0);
2596 ARM_SET_INTERWORK (symbolP, support_interwork);
2600 THUMB_SET_FUNC (symbolP, 1);
2601 ARM_SET_THUMB (symbolP, 1);
2602 ARM_SET_INTERWORK (symbolP, support_interwork);
2610 /* Save the mapping symbols for future reference. Also check that
2611 we do not place two mapping symbols at the same offset within a
2612 frag. We'll handle overlap between frags in
2613 check_mapping_symbols.
2615 If .fill or other data filling directive generates zero sized data,
2616 the mapping symbol for the following code will have the same value
2617 as the one generated for the data filling directive. In this case,
2618 we replace the old symbol with the new one at the same address. */
2621 if (frag->tc_frag_data.first_map != NULL)
2623 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2624 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2626 frag->tc_frag_data.first_map = symbolP;
2628 if (frag->tc_frag_data.last_map != NULL)
2630 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2631 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2632 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2634 frag->tc_frag_data.last_map = symbolP;
2637 /* We must sometimes convert a region marked as code to data during
2638 code alignment, if an odd number of bytes have to be padded. The
2639 code mapping symbol is pushed to an aligned address. */
2642 insert_data_mapping_symbol (enum mstate state,
2643 valueT value, fragS *frag, offsetT bytes)
2645 /* If there was already a mapping symbol, remove it. */
2646 if (frag->tc_frag_data.last_map != NULL
2647 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2649 symbolS *symp = frag->tc_frag_data.last_map;
2653 know (frag->tc_frag_data.first_map == symp);
2654 frag->tc_frag_data.first_map = NULL;
2656 frag->tc_frag_data.last_map = NULL;
2657 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2660 make_mapping_symbol (MAP_DATA, value, frag);
2661 make_mapping_symbol (state, value + bytes, frag);
2664 static void mapping_state_2 (enum mstate state, int max_chars);
2666 /* Set the mapping state to STATE. Only call this when about to
2667 emit some STATE bytes to the file. */
2669 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2671 mapping_state (enum mstate state)
2673 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2675 if (mapstate == state)
2676 /* The mapping symbol has already been emitted.
2677 There is nothing else to do. */
2680 if (state == MAP_ARM || state == MAP_THUMB)
2682 All ARM instructions require 4-byte alignment.
2683 (Almost) all Thumb instructions require 2-byte alignment.
2685 When emitting instructions into any section, mark the section
2688 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2689 but themselves require 2-byte alignment; this applies to some
2690 PC- relative forms. However, these cases will invovle implicit
2691 literal pool generation or an explicit .align >=2, both of
2692 which will cause the section to me marked with sufficient
2693 alignment. Thus, we don't handle those cases here. */
2694 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2696 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2697 /* This case will be evaluated later. */
2700 mapping_state_2 (state, 0);
2703 /* Same as mapping_state, but MAX_CHARS bytes have already been
2704 allocated. Put the mapping symbol that far back. */
2707 mapping_state_2 (enum mstate state, int max_chars)
2709 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2711 if (!SEG_NORMAL (now_seg))
2714 if (mapstate == state)
2715 /* The mapping symbol has already been emitted.
2716 There is nothing else to do. */
2719 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2720 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2722 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2723 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2726 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2729 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2730 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2734 #define mapping_state(x) ((void)0)
2735 #define mapping_state_2(x, y) ((void)0)
2738 /* Find the real, Thumb encoded start of a Thumb function. */
2742 find_real_start (symbolS * symbolP)
2745 const char * name = S_GET_NAME (symbolP);
2746 symbolS * new_target;
2748 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2749 #define STUB_NAME ".real_start_of"
2754 /* The compiler may generate BL instructions to local labels because
2755 it needs to perform a branch to a far away location. These labels
2756 do not have a corresponding ".real_start_of" label. We check
2757 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2758 the ".real_start_of" convention for nonlocal branches. */
2759 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2762 real_start = concat (STUB_NAME, name, NULL);
2763 new_target = symbol_find (real_start);
2766 if (new_target == NULL)
2768 as_warn (_("Failed to find real start of function: %s\n"), name);
2769 new_target = symbolP;
2777 opcode_select (int width)
2784 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2785 as_bad (_("selected processor does not support THUMB opcodes"));
2788 /* No need to force the alignment, since we will have been
2789 coming from ARM mode, which is word-aligned. */
2790 record_alignment (now_seg, 1);
2797 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2798 as_bad (_("selected processor does not support ARM opcodes"));
2803 frag_align (2, 0, 0);
2805 record_alignment (now_seg, 1);
2810 as_bad (_("invalid instruction size selected (%d)"), width);
2815 s_arm (int ignore ATTRIBUTE_UNUSED)
2818 demand_empty_rest_of_line ();
2822 s_thumb (int ignore ATTRIBUTE_UNUSED)
2825 demand_empty_rest_of_line ();
2829 s_code (int unused ATTRIBUTE_UNUSED)
2833 temp = get_absolute_expression ();
2838 opcode_select (temp);
2842 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2847 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2849 /* If we are not already in thumb mode go into it, EVEN if
2850 the target processor does not support thumb instructions.
2851 This is used by gcc/config/arm/lib1funcs.asm for example
2852 to compile interworking support functions even if the
2853 target processor should not support interworking. */
2857 record_alignment (now_seg, 1);
2860 demand_empty_rest_of_line ();
2864 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2868 /* The following label is the name/address of the start of a Thumb function.
2869 We need to know this for the interworking support. */
2870 label_is_thumb_function_name = TRUE;
2873 /* Perform a .set directive, but also mark the alias as
2874 being a thumb function. */
2877 s_thumb_set (int equiv)
2879 /* XXX the following is a duplicate of the code for s_set() in read.c
2880 We cannot just call that code as we need to get at the symbol that
2887 /* Especial apologies for the random logic:
2888 This just grew, and could be parsed much more simply!
2890 delim = get_symbol_name (& name);
2891 end_name = input_line_pointer;
2892 (void) restore_line_pointer (delim);
2894 if (*input_line_pointer != ',')
2897 as_bad (_("expected comma after name \"%s\""), name);
2899 ignore_rest_of_line ();
2903 input_line_pointer++;
2906 if (name[0] == '.' && name[1] == '\0')
2908 /* XXX - this should not happen to .thumb_set. */
2912 if ((symbolP = symbol_find (name)) == NULL
2913 && (symbolP = md_undefined_symbol (name)) == NULL)
2916 /* When doing symbol listings, play games with dummy fragments living
2917 outside the normal fragment chain to record the file and line info
2919 if (listing & LISTING_SYMBOLS)
2921 extern struct list_info_struct * listing_tail;
2922 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2924 memset (dummy_frag, 0, sizeof (fragS));
2925 dummy_frag->fr_type = rs_fill;
2926 dummy_frag->line = listing_tail;
2927 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2928 dummy_frag->fr_symbol = symbolP;
2932 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2935 /* "set" symbols are local unless otherwise specified. */
2936 SF_SET_LOCAL (symbolP);
2937 #endif /* OBJ_COFF */
2938 } /* Make a new symbol. */
2940 symbol_table_insert (symbolP);
2945 && S_IS_DEFINED (symbolP)
2946 && S_GET_SEGMENT (symbolP) != reg_section)
2947 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2949 pseudo_set (symbolP);
2951 demand_empty_rest_of_line ();
2953 /* XXX Now we come to the Thumb specific bit of code. */
2955 THUMB_SET_FUNC (symbolP, 1);
2956 ARM_SET_THUMB (symbolP, 1);
2957 #if defined OBJ_ELF || defined OBJ_COFF
2958 ARM_SET_INTERWORK (symbolP, support_interwork);
2962 /* Directives: Mode selection. */
2964 /* .syntax [unified|divided] - choose the new unified syntax
2965 (same for Arm and Thumb encoding, modulo slight differences in what
2966 can be represented) or the old divergent syntax for each mode. */
2968 s_syntax (int unused ATTRIBUTE_UNUSED)
2972 delim = get_symbol_name (& name);
2974 if (!strcasecmp (name, "unified"))
2975 unified_syntax = TRUE;
2976 else if (!strcasecmp (name, "divided"))
2977 unified_syntax = FALSE;
2980 as_bad (_("unrecognized syntax mode \"%s\""), name);
2983 (void) restore_line_pointer (delim);
2984 demand_empty_rest_of_line ();
2987 /* Directives: sectioning and alignment. */
2990 s_bss (int ignore ATTRIBUTE_UNUSED)
2992 /* We don't support putting frags in the BSS segment, we fake it by
2993 marking in_bss, then looking at s_skip for clues. */
2994 subseg_set (bss_section, 0);
2995 demand_empty_rest_of_line ();
2997 #ifdef md_elf_section_change_hook
2998 md_elf_section_change_hook ();
3003 s_even (int ignore ATTRIBUTE_UNUSED)
3005 /* Never make frag if expect extra pass. */
3007 frag_align (1, 0, 0);
3009 record_alignment (now_seg, 1);
3011 demand_empty_rest_of_line ();
3014 /* Directives: CodeComposer Studio. */
3016 /* .ref (for CodeComposer Studio syntax only). */
3018 s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3020 if (codecomposer_syntax)
3021 ignore_rest_of_line ();
3023 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3026 /* If name is not NULL, then it is used for marking the beginning of a
3027 function, wherease if it is NULL then it means the function end. */
3029 asmfunc_debug (const char * name)
3031 static const char * last_name = NULL;
3035 gas_assert (last_name == NULL);
3038 if (debug_type == DEBUG_STABS)
3039 stabs_generate_asm_func (name, name);
3043 gas_assert (last_name != NULL);
3045 if (debug_type == DEBUG_STABS)
3046 stabs_generate_asm_endfunc (last_name, last_name);
3053 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3055 if (codecomposer_syntax)
3057 switch (asmfunc_state)
3059 case OUTSIDE_ASMFUNC:
3060 asmfunc_state = WAITING_ASMFUNC_NAME;
3063 case WAITING_ASMFUNC_NAME:
3064 as_bad (_(".asmfunc repeated."));
3067 case WAITING_ENDASMFUNC:
3068 as_bad (_(".asmfunc without function."));
3071 demand_empty_rest_of_line ();
3074 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3078 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3080 if (codecomposer_syntax)
3082 switch (asmfunc_state)
3084 case OUTSIDE_ASMFUNC:
3085 as_bad (_(".endasmfunc without a .asmfunc."));
3088 case WAITING_ASMFUNC_NAME:
3089 as_bad (_(".endasmfunc without function."));
3092 case WAITING_ENDASMFUNC:
3093 asmfunc_state = OUTSIDE_ASMFUNC;
3094 asmfunc_debug (NULL);
3097 demand_empty_rest_of_line ();
3100 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3104 s_ccs_def (int name)
3106 if (codecomposer_syntax)
3109 as_bad (_(".def pseudo-op only available with -mccs flag."));
3112 /* Directives: Literal pools. */
3114 static literal_pool *
3115 find_literal_pool (void)
3117 literal_pool * pool;
3119 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3121 if (pool->section == now_seg
3122 && pool->sub_section == now_subseg)
3129 static literal_pool *
3130 find_or_make_literal_pool (void)
3132 /* Next literal pool ID number. */
3133 static unsigned int latest_pool_num = 1;
3134 literal_pool * pool;
3136 pool = find_literal_pool ();
3140 /* Create a new pool. */
3141 pool = (literal_pool *) xmalloc (sizeof (* pool));
3145 pool->next_free_entry = 0;
3146 pool->section = now_seg;
3147 pool->sub_section = now_subseg;
3148 pool->next = list_of_pools;
3149 pool->symbol = NULL;
3150 pool->alignment = 2;
3152 /* Add it to the list. */
3153 list_of_pools = pool;
3156 /* New pools, and emptied pools, will have a NULL symbol. */
3157 if (pool->symbol == NULL)
3159 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3160 (valueT) 0, &zero_address_frag);
3161 pool->id = latest_pool_num ++;
3168 /* Add the literal in the global 'inst'
3169 structure to the relevant literal pool. */
3172 add_to_lit_pool (unsigned int nbytes)
3174 #define PADDING_SLOT 0x1
3175 #define LIT_ENTRY_SIZE_MASK 0xFF
3176 literal_pool * pool;
3177 unsigned int entry, pool_size = 0;
3178 bfd_boolean padding_slot_p = FALSE;
3184 imm1 = inst.operands[1].imm;
3185 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3186 : inst.reloc.exp.X_unsigned ? 0
3187 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
3188 if (target_big_endian)
3191 imm2 = inst.operands[1].imm;
3195 pool = find_or_make_literal_pool ();
3197 /* Check if this literal value is already in the pool. */
3198 for (entry = 0; entry < pool->next_free_entry; entry ++)
3202 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3203 && (inst.reloc.exp.X_op == O_constant)
3204 && (pool->literals[entry].X_add_number
3205 == inst.reloc.exp.X_add_number)
3206 && (pool->literals[entry].X_md == nbytes)
3207 && (pool->literals[entry].X_unsigned
3208 == inst.reloc.exp.X_unsigned))
3211 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3212 && (inst.reloc.exp.X_op == O_symbol)
3213 && (pool->literals[entry].X_add_number
3214 == inst.reloc.exp.X_add_number)
3215 && (pool->literals[entry].X_add_symbol
3216 == inst.reloc.exp.X_add_symbol)
3217 && (pool->literals[entry].X_op_symbol
3218 == inst.reloc.exp.X_op_symbol)
3219 && (pool->literals[entry].X_md == nbytes))
3222 else if ((nbytes == 8)
3223 && !(pool_size & 0x7)
3224 && ((entry + 1) != pool->next_free_entry)
3225 && (pool->literals[entry].X_op == O_constant)
3226 && (pool->literals[entry].X_add_number == (offsetT) imm1)
3227 && (pool->literals[entry].X_unsigned
3228 == inst.reloc.exp.X_unsigned)
3229 && (pool->literals[entry + 1].X_op == O_constant)
3230 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
3231 && (pool->literals[entry + 1].X_unsigned
3232 == inst.reloc.exp.X_unsigned))
3235 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3236 if (padding_slot_p && (nbytes == 4))
3242 /* Do we need to create a new entry? */
3243 if (entry == pool->next_free_entry)
3245 if (entry >= MAX_LITERAL_POOL_SIZE)
3247 inst.error = _("literal pool overflow");
3253 /* For 8-byte entries, we align to an 8-byte boundary,
3254 and split it into two 4-byte entries, because on 32-bit
3255 host, 8-byte constants are treated as big num, thus
3256 saved in "generic_bignum" which will be overwritten
3257 by later assignments.
3259 We also need to make sure there is enough space for
3262 We also check to make sure the literal operand is a
3264 if (!(inst.reloc.exp.X_op == O_constant
3265 || inst.reloc.exp.X_op == O_big))
3267 inst.error = _("invalid type for literal pool");
3270 else if (pool_size & 0x7)
3272 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3274 inst.error = _("literal pool overflow");
3278 pool->literals[entry] = inst.reloc.exp;
3279 pool->literals[entry].X_add_number = 0;
3280 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3281 pool->next_free_entry += 1;
3284 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3286 inst.error = _("literal pool overflow");
3290 pool->literals[entry] = inst.reloc.exp;
3291 pool->literals[entry].X_op = O_constant;
3292 pool->literals[entry].X_add_number = imm1;
3293 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3294 pool->literals[entry++].X_md = 4;
3295 pool->literals[entry] = inst.reloc.exp;
3296 pool->literals[entry].X_op = O_constant;
3297 pool->literals[entry].X_add_number = imm2;
3298 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3299 pool->literals[entry].X_md = 4;
3300 pool->alignment = 3;
3301 pool->next_free_entry += 1;
3305 pool->literals[entry] = inst.reloc.exp;
3306 pool->literals[entry].X_md = 4;
3310 /* PR ld/12974: Record the location of the first source line to reference
3311 this entry in the literal pool. If it turns out during linking that the
3312 symbol does not exist we will be able to give an accurate line number for
3313 the (first use of the) missing reference. */
3314 if (debug_type == DEBUG_DWARF2)
3315 dwarf2_where (pool->locs + entry);
3317 pool->next_free_entry += 1;
3319 else if (padding_slot_p)
3321 pool->literals[entry] = inst.reloc.exp;
3322 pool->literals[entry].X_md = nbytes;
3325 inst.reloc.exp.X_op = O_symbol;
3326 inst.reloc.exp.X_add_number = pool_size;
3327 inst.reloc.exp.X_add_symbol = pool->symbol;
3333 tc_start_label_without_colon (void)
3335 bfd_boolean ret = TRUE;
3337 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3339 const char *label = input_line_pointer;
3341 while (!is_end_of_line[(int) label[-1]])
3346 as_bad (_("Invalid label '%s'"), label);
3350 asmfunc_debug (label);
3352 asmfunc_state = WAITING_ENDASMFUNC;
3358 /* Can't use symbol_new here, so have to create a symbol and then at
3359 a later date assign it a value. Thats what these functions do. */
3362 symbol_locate (symbolS * symbolP,
3363 const char * name, /* It is copied, the caller can modify. */
3364 segT segment, /* Segment identifier (SEG_<something>). */
3365 valueT valu, /* Symbol value. */
3366 fragS * frag) /* Associated fragment. */
3369 char * preserved_copy_of_name;
3371 name_length = strlen (name) + 1; /* +1 for \0. */
3372 obstack_grow (¬es, name, name_length);
3373 preserved_copy_of_name = (char *) obstack_finish (¬es);
3375 #ifdef tc_canonicalize_symbol_name
3376 preserved_copy_of_name =
3377 tc_canonicalize_symbol_name (preserved_copy_of_name);
3380 S_SET_NAME (symbolP, preserved_copy_of_name);
3382 S_SET_SEGMENT (symbolP, segment);
3383 S_SET_VALUE (symbolP, valu);
3384 symbol_clear_list_pointers (symbolP);
3386 symbol_set_frag (symbolP, frag);
3388 /* Link to end of symbol chain. */
3390 extern int symbol_table_frozen;
3392 if (symbol_table_frozen)
3396 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3398 obj_symbol_new_hook (symbolP);
3400 #ifdef tc_symbol_new_hook
3401 tc_symbol_new_hook (symbolP);
3405 verify_symbol_chain (symbol_rootP, symbol_lastP);
3406 #endif /* DEBUG_SYMS */
3410 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3413 literal_pool * pool;
3416 pool = find_literal_pool ();
3418 || pool->symbol == NULL
3419 || pool->next_free_entry == 0)
3422 /* Align pool as you have word accesses.
3423 Only make a frag if we have to. */
3425 frag_align (pool->alignment, 0, 0);
3427 record_alignment (now_seg, 2);
3430 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3431 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
3433 sprintf (sym_name, "$$lit_\002%x", pool->id);
3435 symbol_locate (pool->symbol, sym_name, now_seg,
3436 (valueT) frag_now_fix (), frag_now);
3437 symbol_table_insert (pool->symbol);
3439 ARM_SET_THUMB (pool->symbol, thumb_mode);
3441 #if defined OBJ_COFF || defined OBJ_ELF
3442 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3445 for (entry = 0; entry < pool->next_free_entry; entry ++)
3448 if (debug_type == DEBUG_DWARF2)
3449 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3451 /* First output the expression in the instruction to the pool. */
3452 emit_expr (&(pool->literals[entry]),
3453 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
3456 /* Mark the pool as empty. */
3457 pool->next_free_entry = 0;
3458 pool->symbol = NULL;
3462 /* Forward declarations for functions below, in the MD interface
3464 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3465 static valueT create_unwind_entry (int);
3466 static void start_unwind_section (const segT, int);
3467 static void add_unwind_opcode (valueT, int);
3468 static void flush_pending_unwind (void);
3470 /* Directives: Data. */
3473 s_arm_elf_cons (int nbytes)
3477 #ifdef md_flush_pending_output
3478 md_flush_pending_output ();
3481 if (is_it_end_of_statement ())
3483 demand_empty_rest_of_line ();
3487 #ifdef md_cons_align
3488 md_cons_align (nbytes);
3491 mapping_state (MAP_DATA);
3495 char *base = input_line_pointer;
3499 if (exp.X_op != O_symbol)
3500 emit_expr (&exp, (unsigned int) nbytes);
3503 char *before_reloc = input_line_pointer;
3504 reloc = parse_reloc (&input_line_pointer);
3507 as_bad (_("unrecognized relocation suffix"));
3508 ignore_rest_of_line ();
3511 else if (reloc == BFD_RELOC_UNUSED)
3512 emit_expr (&exp, (unsigned int) nbytes);
3515 reloc_howto_type *howto = (reloc_howto_type *)
3516 bfd_reloc_type_lookup (stdoutput,
3517 (bfd_reloc_code_real_type) reloc);
3518 int size = bfd_get_reloc_size (howto);
3520 if (reloc == BFD_RELOC_ARM_PLT32)
3522 as_bad (_("(plt) is only valid on branch targets"));
3523 reloc = BFD_RELOC_UNUSED;
3528 as_bad (_("%s relocations do not fit in %d bytes"),
3529 howto->name, nbytes);
3532 /* We've parsed an expression stopping at O_symbol.
3533 But there may be more expression left now that we
3534 have parsed the relocation marker. Parse it again.
3535 XXX Surely there is a cleaner way to do this. */
3536 char *p = input_line_pointer;
3538 char *save_buf = xmalloc (input_line_pointer - base);
3540 memcpy (save_buf, base, input_line_pointer - base);
3541 memmove (base + (input_line_pointer - before_reloc),
3542 base, before_reloc - base);
3544 input_line_pointer = base + (input_line_pointer-before_reloc);
3546 memcpy (base, save_buf, p - base);
3548 offset = nbytes - size;
3549 p = frag_more (nbytes);
3550 memset (p, 0, nbytes);
3551 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3552 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3558 while (*input_line_pointer++ == ',');
3560 /* Put terminator back into stream. */
3561 input_line_pointer --;
3562 demand_empty_rest_of_line ();
3565 /* Emit an expression containing a 32-bit thumb instruction.
3566 Implementation based on put_thumb32_insn. */
3569 emit_thumb32_expr (expressionS * exp)
3571 expressionS exp_high = *exp;
3573 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3574 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3575 exp->X_add_number &= 0xffff;
3576 emit_expr (exp, (unsigned int) THUMB_SIZE);
3579 /* Guess the instruction size based on the opcode. */
3582 thumb_insn_size (int opcode)
3584 if ((unsigned int) opcode < 0xe800u)
3586 else if ((unsigned int) opcode >= 0xe8000000u)
3593 emit_insn (expressionS *exp, int nbytes)
3597 if (exp->X_op == O_constant)
3602 size = thumb_insn_size (exp->X_add_number);
3606 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3608 as_bad (_(".inst.n operand too big. "\
3609 "Use .inst.w instead"));
3614 if (now_it.state == AUTOMATIC_IT_BLOCK)
3615 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3617 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3619 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3620 emit_thumb32_expr (exp);
3622 emit_expr (exp, (unsigned int) size);
3624 it_fsm_post_encode ();
3628 as_bad (_("cannot determine Thumb instruction size. " \
3629 "Use .inst.n/.inst.w instead"));
3632 as_bad (_("constant expression required"));
3637 /* Like s_arm_elf_cons but do not use md_cons_align and
3638 set the mapping state to MAP_ARM/MAP_THUMB. */
3641 s_arm_elf_inst (int nbytes)
3643 if (is_it_end_of_statement ())
3645 demand_empty_rest_of_line ();
3649 /* Calling mapping_state () here will not change ARM/THUMB,
3650 but will ensure not to be in DATA state. */
3653 mapping_state (MAP_THUMB);
3658 as_bad (_("width suffixes are invalid in ARM mode"));
3659 ignore_rest_of_line ();
3665 mapping_state (MAP_ARM);
3674 if (! emit_insn (& exp, nbytes))
3676 ignore_rest_of_line ();
3680 while (*input_line_pointer++ == ',');
3682 /* Put terminator back into stream. */
3683 input_line_pointer --;
3684 demand_empty_rest_of_line ();
3687 /* Parse a .rel31 directive. */
3690 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3697 if (*input_line_pointer == '1')
3698 highbit = 0x80000000;
3699 else if (*input_line_pointer != '0')
3700 as_bad (_("expected 0 or 1"));
3702 input_line_pointer++;
3703 if (*input_line_pointer != ',')
3704 as_bad (_("missing comma"));
3705 input_line_pointer++;
3707 #ifdef md_flush_pending_output
3708 md_flush_pending_output ();
3711 #ifdef md_cons_align
3715 mapping_state (MAP_DATA);
3720 md_number_to_chars (p, highbit, 4);
3721 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3722 BFD_RELOC_ARM_PREL31);
3724 demand_empty_rest_of_line ();
3727 /* Directives: AEABI stack-unwind tables. */
3729 /* Parse an unwind_fnstart directive. Simply records the current location. */
3732 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3734 demand_empty_rest_of_line ();
3735 if (unwind.proc_start)
3737 as_bad (_("duplicate .fnstart directive"));
3741 /* Mark the start of the function. */
3742 unwind.proc_start = expr_build_dot ();
3744 /* Reset the rest of the unwind info. */
3745 unwind.opcode_count = 0;
3746 unwind.table_entry = NULL;
3747 unwind.personality_routine = NULL;
3748 unwind.personality_index = -1;
3749 unwind.frame_size = 0;
3750 unwind.fp_offset = 0;
3751 unwind.fp_reg = REG_SP;
3753 unwind.sp_restored = 0;
3757 /* Parse a handlerdata directive. Creates the exception handling table entry
3758 for the function. */
3761 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3763 demand_empty_rest_of_line ();
3764 if (!unwind.proc_start)
3765 as_bad (MISSING_FNSTART);
3767 if (unwind.table_entry)
3768 as_bad (_("duplicate .handlerdata directive"));
3770 create_unwind_entry (1);
3773 /* Parse an unwind_fnend directive. Generates the index table entry. */
3776 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3781 unsigned int marked_pr_dependency;
3783 demand_empty_rest_of_line ();
3785 if (!unwind.proc_start)
3787 as_bad (_(".fnend directive without .fnstart"));
3791 /* Add eh table entry. */
3792 if (unwind.table_entry == NULL)
3793 val = create_unwind_entry (0);
3797 /* Add index table entry. This is two words. */
3798 start_unwind_section (unwind.saved_seg, 1);
3799 frag_align (2, 0, 0);
3800 record_alignment (now_seg, 2);
3802 ptr = frag_more (8);
3804 where = frag_now_fix () - 8;
3806 /* Self relative offset of the function start. */
3807 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3808 BFD_RELOC_ARM_PREL31);
3810 /* Indicate dependency on EHABI-defined personality routines to the
3811 linker, if it hasn't been done already. */
3812 marked_pr_dependency
3813 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3814 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3815 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3817 static const char *const name[] =
3819 "__aeabi_unwind_cpp_pr0",
3820 "__aeabi_unwind_cpp_pr1",
3821 "__aeabi_unwind_cpp_pr2"
3823 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3824 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3825 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3826 |= 1 << unwind.personality_index;
3830 /* Inline exception table entry. */
3831 md_number_to_chars (ptr + 4, val, 4);
3833 /* Self relative offset of the table entry. */
3834 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3835 BFD_RELOC_ARM_PREL31);
3837 /* Restore the original section. */
3838 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3840 unwind.proc_start = NULL;
3844 /* Parse an unwind_cantunwind directive. */
3847 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3849 demand_empty_rest_of_line ();
3850 if (!unwind.proc_start)
3851 as_bad (MISSING_FNSTART);
3853 if (unwind.personality_routine || unwind.personality_index != -1)
3854 as_bad (_("personality routine specified for cantunwind frame"));
3856 unwind.personality_index = -2;
3860 /* Parse a personalityindex directive. */
3863 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3867 if (!unwind.proc_start)
3868 as_bad (MISSING_FNSTART);
3870 if (unwind.personality_routine || unwind.personality_index != -1)
3871 as_bad (_("duplicate .personalityindex directive"));
3875 if (exp.X_op != O_constant
3876 || exp.X_add_number < 0 || exp.X_add_number > 15)
3878 as_bad (_("bad personality routine number"));
3879 ignore_rest_of_line ();
3883 unwind.personality_index = exp.X_add_number;
3885 demand_empty_rest_of_line ();
3889 /* Parse a personality directive. */
3892 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3896 if (!unwind.proc_start)
3897 as_bad (MISSING_FNSTART);
3899 if (unwind.personality_routine || unwind.personality_index != -1)
3900 as_bad (_("duplicate .personality directive"));
3902 c = get_symbol_name (& name);
3903 p = input_line_pointer;
3905 ++ input_line_pointer;
3906 unwind.personality_routine = symbol_find_or_make (name);
3908 demand_empty_rest_of_line ();
3912 /* Parse a directive saving core registers. */
3915 s_arm_unwind_save_core (void)
3921 range = parse_reg_list (&input_line_pointer);
3924 as_bad (_("expected register list"));
3925 ignore_rest_of_line ();
3929 demand_empty_rest_of_line ();
3931 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3932 into .unwind_save {..., sp...}. We aren't bothered about the value of
3933 ip because it is clobbered by calls. */
3934 if (unwind.sp_restored && unwind.fp_reg == 12
3935 && (range & 0x3000) == 0x1000)
3937 unwind.opcode_count--;
3938 unwind.sp_restored = 0;
3939 range = (range | 0x2000) & ~0x1000;
3940 unwind.pending_offset = 0;
3946 /* See if we can use the short opcodes. These pop a block of up to 8
3947 registers starting with r4, plus maybe r14. */
3948 for (n = 0; n < 8; n++)
3950 /* Break at the first non-saved register. */
3951 if ((range & (1 << (n + 4))) == 0)
3954 /* See if there are any other bits set. */
3955 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3957 /* Use the long form. */
3958 op = 0x8000 | ((range >> 4) & 0xfff);
3959 add_unwind_opcode (op, 2);
3963 /* Use the short form. */
3965 op = 0xa8; /* Pop r14. */
3967 op = 0xa0; /* Do not pop r14. */
3969 add_unwind_opcode (op, 1);
3976 op = 0xb100 | (range & 0xf);
3977 add_unwind_opcode (op, 2);
3980 /* Record the number of bytes pushed. */
3981 for (n = 0; n < 16; n++)
3983 if (range & (1 << n))
3984 unwind.frame_size += 4;
3989 /* Parse a directive saving FPA registers. */
3992 s_arm_unwind_save_fpa (int reg)
3998 /* Get Number of registers to transfer. */
3999 if (skip_past_comma (&input_line_pointer) != FAIL)
4002 exp.X_op = O_illegal;
4004 if (exp.X_op != O_constant)
4006 as_bad (_("expected , <constant>"));
4007 ignore_rest_of_line ();
4011 num_regs = exp.X_add_number;
4013 if (num_regs < 1 || num_regs > 4)
4015 as_bad (_("number of registers must be in the range [1:4]"));
4016 ignore_rest_of_line ();
4020 demand_empty_rest_of_line ();
4025 op = 0xb4 | (num_regs - 1);
4026 add_unwind_opcode (op, 1);
4031 op = 0xc800 | (reg << 4) | (num_regs - 1);
4032 add_unwind_opcode (op, 2);
4034 unwind.frame_size += num_regs * 12;
4038 /* Parse a directive saving VFP registers for ARMv6 and above. */
4041 s_arm_unwind_save_vfp_armv6 (void)
4046 int num_vfpv3_regs = 0;
4047 int num_regs_below_16;
4049 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
4052 as_bad (_("expected register list"));
4053 ignore_rest_of_line ();
4057 demand_empty_rest_of_line ();
4059 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4060 than FSTMX/FLDMX-style ones). */
4062 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4064 num_vfpv3_regs = count;
4065 else if (start + count > 16)
4066 num_vfpv3_regs = start + count - 16;
4068 if (num_vfpv3_regs > 0)
4070 int start_offset = start > 16 ? start - 16 : 0;
4071 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4072 add_unwind_opcode (op, 2);
4075 /* Generate opcode for registers numbered in the range 0 .. 15. */
4076 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
4077 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
4078 if (num_regs_below_16 > 0)
4080 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4081 add_unwind_opcode (op, 2);
4084 unwind.frame_size += count * 8;
4088 /* Parse a directive saving VFP registers for pre-ARMv6. */
4091 s_arm_unwind_save_vfp (void)
4097 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
4100 as_bad (_("expected register list"));
4101 ignore_rest_of_line ();
4105 demand_empty_rest_of_line ();
4110 op = 0xb8 | (count - 1);
4111 add_unwind_opcode (op, 1);
4116 op = 0xb300 | (reg << 4) | (count - 1);
4117 add_unwind_opcode (op, 2);
4119 unwind.frame_size += count * 8 + 4;
4123 /* Parse a directive saving iWMMXt data registers. */
4126 s_arm_unwind_save_mmxwr (void)
4134 if (*input_line_pointer == '{')
4135 input_line_pointer++;
4139 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4143 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4148 as_tsktsk (_("register list not in ascending order"));
4151 if (*input_line_pointer == '-')
4153 input_line_pointer++;
4154 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4157 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4160 else if (reg >= hi_reg)
4162 as_bad (_("bad register range"));
4165 for (; reg < hi_reg; reg++)
4169 while (skip_past_comma (&input_line_pointer) != FAIL);
4171 skip_past_char (&input_line_pointer, '}');
4173 demand_empty_rest_of_line ();
4175 /* Generate any deferred opcodes because we're going to be looking at
4177 flush_pending_unwind ();
4179 for (i = 0; i < 16; i++)
4181 if (mask & (1 << i))
4182 unwind.frame_size += 8;
4185 /* Attempt to combine with a previous opcode. We do this because gcc
4186 likes to output separate unwind directives for a single block of
4188 if (unwind.opcode_count > 0)
4190 i = unwind.opcodes[unwind.opcode_count - 1];
4191 if ((i & 0xf8) == 0xc0)
4194 /* Only merge if the blocks are contiguous. */
4197 if ((mask & 0xfe00) == (1 << 9))
4199 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4200 unwind.opcode_count--;
4203 else if (i == 6 && unwind.opcode_count >= 2)
4205 i = unwind.opcodes[unwind.opcode_count - 2];
4209 op = 0xffff << (reg - 1);
4211 && ((mask & op) == (1u << (reg - 1))))
4213 op = (1 << (reg + i + 1)) - 1;
4214 op &= ~((1 << reg) - 1);
4216 unwind.opcode_count -= 2;
4223 /* We want to generate opcodes in the order the registers have been
4224 saved, ie. descending order. */
4225 for (reg = 15; reg >= -1; reg--)
4227 /* Save registers in blocks. */
4229 || !(mask & (1 << reg)))
4231 /* We found an unsaved reg. Generate opcodes to save the
4238 op = 0xc0 | (hi_reg - 10);
4239 add_unwind_opcode (op, 1);
4244 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4245 add_unwind_opcode (op, 2);
4254 ignore_rest_of_line ();
4258 s_arm_unwind_save_mmxwcg (void)
4265 if (*input_line_pointer == '{')
4266 input_line_pointer++;
4268 skip_whitespace (input_line_pointer);
4272 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4276 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4282 as_tsktsk (_("register list not in ascending order"));
4285 if (*input_line_pointer == '-')
4287 input_line_pointer++;
4288 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4291 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4294 else if (reg >= hi_reg)
4296 as_bad (_("bad register range"));
4299 for (; reg < hi_reg; reg++)
4303 while (skip_past_comma (&input_line_pointer) != FAIL);
4305 skip_past_char (&input_line_pointer, '}');
4307 demand_empty_rest_of_line ();
4309 /* Generate any deferred opcodes because we're going to be looking at
4311 flush_pending_unwind ();
4313 for (reg = 0; reg < 16; reg++)
4315 if (mask & (1 << reg))
4316 unwind.frame_size += 4;
4319 add_unwind_opcode (op, 2);
4322 ignore_rest_of_line ();
4326 /* Parse an unwind_save directive.
4327 If the argument is non-zero, this is a .vsave directive. */
4330 s_arm_unwind_save (int arch_v6)
4333 struct reg_entry *reg;
4334 bfd_boolean had_brace = FALSE;
4336 if (!unwind.proc_start)
4337 as_bad (MISSING_FNSTART);
4339 /* Figure out what sort of save we have. */
4340 peek = input_line_pointer;
4348 reg = arm_reg_parse_multi (&peek);
4352 as_bad (_("register expected"));
4353 ignore_rest_of_line ();
4362 as_bad (_("FPA .unwind_save does not take a register list"));
4363 ignore_rest_of_line ();
4366 input_line_pointer = peek;
4367 s_arm_unwind_save_fpa (reg->number);
4371 s_arm_unwind_save_core ();
4376 s_arm_unwind_save_vfp_armv6 ();
4378 s_arm_unwind_save_vfp ();
4381 case REG_TYPE_MMXWR:
4382 s_arm_unwind_save_mmxwr ();
4385 case REG_TYPE_MMXWCG:
4386 s_arm_unwind_save_mmxwcg ();
4390 as_bad (_(".unwind_save does not support this kind of register"));
4391 ignore_rest_of_line ();
4396 /* Parse an unwind_movsp directive. */
4399 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4405 if (!unwind.proc_start)
4406 as_bad (MISSING_FNSTART);
4408 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4411 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4412 ignore_rest_of_line ();
4416 /* Optional constant. */
4417 if (skip_past_comma (&input_line_pointer) != FAIL)
4419 if (immediate_for_directive (&offset) == FAIL)
4425 demand_empty_rest_of_line ();
4427 if (reg == REG_SP || reg == REG_PC)
4429 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4433 if (unwind.fp_reg != REG_SP)
4434 as_bad (_("unexpected .unwind_movsp directive"));
4436 /* Generate opcode to restore the value. */
4438 add_unwind_opcode (op, 1);
4440 /* Record the information for later. */
4441 unwind.fp_reg = reg;
4442 unwind.fp_offset = unwind.frame_size - offset;
4443 unwind.sp_restored = 1;
4446 /* Parse an unwind_pad directive. */
4449 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4453 if (!unwind.proc_start)
4454 as_bad (MISSING_FNSTART);
4456 if (immediate_for_directive (&offset) == FAIL)
4461 as_bad (_("stack increment must be multiple of 4"));
4462 ignore_rest_of_line ();
4466 /* Don't generate any opcodes, just record the details for later. */
4467 unwind.frame_size += offset;
4468 unwind.pending_offset += offset;
4470 demand_empty_rest_of_line ();
4473 /* Parse an unwind_setfp directive. */
4476 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4482 if (!unwind.proc_start)
4483 as_bad (MISSING_FNSTART);
4485 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4486 if (skip_past_comma (&input_line_pointer) == FAIL)
4489 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4491 if (fp_reg == FAIL || sp_reg == FAIL)
4493 as_bad (_("expected <reg>, <reg>"));
4494 ignore_rest_of_line ();
4498 /* Optional constant. */
4499 if (skip_past_comma (&input_line_pointer) != FAIL)
4501 if (immediate_for_directive (&offset) == FAIL)
4507 demand_empty_rest_of_line ();
4509 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4511 as_bad (_("register must be either sp or set by a previous"
4512 "unwind_movsp directive"));
4516 /* Don't generate any opcodes, just record the information for later. */
4517 unwind.fp_reg = fp_reg;
4519 if (sp_reg == REG_SP)
4520 unwind.fp_offset = unwind.frame_size - offset;
4522 unwind.fp_offset -= offset;
4525 /* Parse an unwind_raw directive. */
4528 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4531 /* This is an arbitrary limit. */
4532 unsigned char op[16];
4535 if (!unwind.proc_start)
4536 as_bad (MISSING_FNSTART);
4539 if (exp.X_op == O_constant
4540 && skip_past_comma (&input_line_pointer) != FAIL)
4542 unwind.frame_size += exp.X_add_number;
4546 exp.X_op = O_illegal;
4548 if (exp.X_op != O_constant)
4550 as_bad (_("expected <offset>, <opcode>"));
4551 ignore_rest_of_line ();
4557 /* Parse the opcode. */
4562 as_bad (_("unwind opcode too long"));
4563 ignore_rest_of_line ();
4565 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4567 as_bad (_("invalid unwind opcode"));
4568 ignore_rest_of_line ();
4571 op[count++] = exp.X_add_number;
4573 /* Parse the next byte. */
4574 if (skip_past_comma (&input_line_pointer) == FAIL)
4580 /* Add the opcode bytes in reverse order. */
4582 add_unwind_opcode (op[count], 1);
4584 demand_empty_rest_of_line ();
4588 /* Parse a .eabi_attribute directive. */
4591 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4593 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4595 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4596 attributes_set_explicitly[tag] = 1;
4599 /* Emit a tls fix for the symbol. */
4602 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4606 #ifdef md_flush_pending_output
4607 md_flush_pending_output ();
4610 #ifdef md_cons_align
4614 /* Since we're just labelling the code, there's no need to define a
4617 p = obstack_next_free (&frchain_now->frch_obstack);
4618 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4619 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4620 : BFD_RELOC_ARM_TLS_DESCSEQ);
4622 #endif /* OBJ_ELF */
4624 static void s_arm_arch (int);
4625 static void s_arm_object_arch (int);
4626 static void s_arm_cpu (int);
4627 static void s_arm_fpu (int);
4628 static void s_arm_arch_extension (int);
4633 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4640 if (exp.X_op == O_symbol)
4641 exp.X_op = O_secrel;
4643 emit_expr (&exp, 4);
4645 while (*input_line_pointer++ == ',');
4647 input_line_pointer--;
4648 demand_empty_rest_of_line ();
4652 /* This table describes all the machine specific pseudo-ops the assembler
4653 has to support. The fields are:
4654 pseudo-op name without dot
4655 function to call to execute this pseudo-op
4656 Integer arg to pass to the function. */
4658 const pseudo_typeS md_pseudo_table[] =
4660 /* Never called because '.req' does not start a line. */
4661 { "req", s_req, 0 },
4662 /* Following two are likewise never called. */
4665 { "unreq", s_unreq, 0 },
4666 { "bss", s_bss, 0 },
4667 { "align", s_align_ptwo, 2 },
4668 { "arm", s_arm, 0 },
4669 { "thumb", s_thumb, 0 },
4670 { "code", s_code, 0 },
4671 { "force_thumb", s_force_thumb, 0 },
4672 { "thumb_func", s_thumb_func, 0 },
4673 { "thumb_set", s_thumb_set, 0 },
4674 { "even", s_even, 0 },
4675 { "ltorg", s_ltorg, 0 },
4676 { "pool", s_ltorg, 0 },
4677 { "syntax", s_syntax, 0 },
4678 { "cpu", s_arm_cpu, 0 },
4679 { "arch", s_arm_arch, 0 },
4680 { "object_arch", s_arm_object_arch, 0 },
4681 { "fpu", s_arm_fpu, 0 },
4682 { "arch_extension", s_arm_arch_extension, 0 },
4684 { "word", s_arm_elf_cons, 4 },
4685 { "long", s_arm_elf_cons, 4 },
4686 { "inst.n", s_arm_elf_inst, 2 },
4687 { "inst.w", s_arm_elf_inst, 4 },
4688 { "inst", s_arm_elf_inst, 0 },
4689 { "rel31", s_arm_rel31, 0 },
4690 { "fnstart", s_arm_unwind_fnstart, 0 },
4691 { "fnend", s_arm_unwind_fnend, 0 },
4692 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4693 { "personality", s_arm_unwind_personality, 0 },
4694 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4695 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4696 { "save", s_arm_unwind_save, 0 },
4697 { "vsave", s_arm_unwind_save, 1 },
4698 { "movsp", s_arm_unwind_movsp, 0 },
4699 { "pad", s_arm_unwind_pad, 0 },
4700 { "setfp", s_arm_unwind_setfp, 0 },
4701 { "unwind_raw", s_arm_unwind_raw, 0 },
4702 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4703 { "tlsdescseq", s_arm_tls_descseq, 0 },
4707 /* These are used for dwarf. */
4711 /* These are used for dwarf2. */
4712 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4713 { "loc", dwarf2_directive_loc, 0 },
4714 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4716 { "extend", float_cons, 'x' },
4717 { "ldouble", float_cons, 'x' },
4718 { "packed", float_cons, 'p' },
4720 {"secrel32", pe_directive_secrel, 0},
4723 /* These are for compatibility with CodeComposer Studio. */
4724 {"ref", s_ccs_ref, 0},
4725 {"def", s_ccs_def, 0},
4726 {"asmfunc", s_ccs_asmfunc, 0},
4727 {"endasmfunc", s_ccs_endasmfunc, 0},
4732 /* Parser functions used exclusively in instruction operands. */
4734 /* Generic immediate-value read function for use in insn parsing.
4735 STR points to the beginning of the immediate (the leading #);
4736 VAL receives the value; if the value is outside [MIN, MAX]
4737 issue an error. PREFIX_OPT is true if the immediate prefix is
4741 parse_immediate (char **str, int *val, int min, int max,
4742 bfd_boolean prefix_opt)
4745 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4746 if (exp.X_op != O_constant)
4748 inst.error = _("constant expression required");
4752 if (exp.X_add_number < min || exp.X_add_number > max)
4754 inst.error = _("immediate value out of range");
4758 *val = exp.X_add_number;
4762 /* Less-generic immediate-value read function with the possibility of loading a
4763 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4764 instructions. Puts the result directly in inst.operands[i]. */
4767 parse_big_immediate (char **str, int i, expressionS *in_exp,
4768 bfd_boolean allow_symbol_p)
4771 expressionS *exp_p = in_exp ? in_exp : &exp;
4774 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
4776 if (exp_p->X_op == O_constant)
4778 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
4779 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4780 O_constant. We have to be careful not to break compilation for
4781 32-bit X_add_number, though. */
4782 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4784 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4785 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
4787 inst.operands[i].regisimm = 1;
4790 else if (exp_p->X_op == O_big
4791 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
4793 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4795 /* Bignums have their least significant bits in
4796 generic_bignum[0]. Make sure we put 32 bits in imm and
4797 32 bits in reg, in a (hopefully) portable way. */
4798 gas_assert (parts != 0);
4800 /* Make sure that the number is not too big.
4801 PR 11972: Bignums can now be sign-extended to the
4802 size of a .octa so check that the out of range bits
4803 are all zero or all one. */
4804 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
4806 LITTLENUM_TYPE m = -1;
4808 if (generic_bignum[parts * 2] != 0
4809 && generic_bignum[parts * 2] != m)
4812 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
4813 if (generic_bignum[j] != generic_bignum[j-1])
4817 inst.operands[i].imm = 0;
4818 for (j = 0; j < parts; j++, idx++)
4819 inst.operands[i].imm |= generic_bignum[idx]
4820 << (LITTLENUM_NUMBER_OF_BITS * j);
4821 inst.operands[i].reg = 0;
4822 for (j = 0; j < parts; j++, idx++)
4823 inst.operands[i].reg |= generic_bignum[idx]
4824 << (LITTLENUM_NUMBER_OF_BITS * j);
4825 inst.operands[i].regisimm = 1;
4827 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
4835 /* Returns the pseudo-register number of an FPA immediate constant,
4836 or FAIL if there isn't a valid constant here. */
4839 parse_fpa_immediate (char ** str)
4841 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4847 /* First try and match exact strings, this is to guarantee
4848 that some formats will work even for cross assembly. */
4850 for (i = 0; fp_const[i]; i++)
4852 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4856 *str += strlen (fp_const[i]);
4857 if (is_end_of_line[(unsigned char) **str])
4863 /* Just because we didn't get a match doesn't mean that the constant
4864 isn't valid, just that it is in a format that we don't
4865 automatically recognize. Try parsing it with the standard
4866 expression routines. */
4868 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4870 /* Look for a raw floating point number. */
4871 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4872 && is_end_of_line[(unsigned char) *save_in])
4874 for (i = 0; i < NUM_FLOAT_VALS; i++)
4876 for (j = 0; j < MAX_LITTLENUMS; j++)
4878 if (words[j] != fp_values[i][j])
4882 if (j == MAX_LITTLENUMS)
4890 /* Try and parse a more complex expression, this will probably fail
4891 unless the code uses a floating point prefix (eg "0f"). */
4892 save_in = input_line_pointer;
4893 input_line_pointer = *str;
4894 if (expression (&exp) == absolute_section
4895 && exp.X_op == O_big
4896 && exp.X_add_number < 0)
4898 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4900 #define X_PRECISION 5
4901 #define E_PRECISION 15L
4902 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
4904 for (i = 0; i < NUM_FLOAT_VALS; i++)
4906 for (j = 0; j < MAX_LITTLENUMS; j++)
4908 if (words[j] != fp_values[i][j])
4912 if (j == MAX_LITTLENUMS)
4914 *str = input_line_pointer;
4915 input_line_pointer = save_in;
4922 *str = input_line_pointer;
4923 input_line_pointer = save_in;
4924 inst.error = _("invalid FPA immediate expression");
4928 /* Returns 1 if a number has "quarter-precision" float format
4929 0baBbbbbbc defgh000 00000000 00000000. */
4932 is_quarter_float (unsigned imm)
4934 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4935 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4939 /* Detect the presence of a floating point or integer zero constant,
4943 parse_ifimm_zero (char **in)
4947 if (!is_immediate_prefix (**in))
4952 /* Accept #0x0 as a synonym for #0. */
4953 if (strncmp (*in, "0x", 2) == 0)
4956 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
4961 error_code = atof_generic (in, ".", EXP_CHARS,
4962 &generic_floating_point_number);
4965 && generic_floating_point_number.sign == '+'
4966 && (generic_floating_point_number.low
4967 > generic_floating_point_number.leader))
4973 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4974 0baBbbbbbc defgh000 00000000 00000000.
4975 The zero and minus-zero cases need special handling, since they can't be
4976 encoded in the "quarter-precision" float format, but can nonetheless be
4977 loaded as integer constants. */
4980 parse_qfloat_immediate (char **ccp, int *immed)
4984 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4985 int found_fpchar = 0;
4987 skip_past_char (&str, '#');
4989 /* We must not accidentally parse an integer as a floating-point number. Make
4990 sure that the value we parse is not an integer by checking for special
4991 characters '.' or 'e'.
4992 FIXME: This is a horrible hack, but doing better is tricky because type
4993 information isn't in a very usable state at parse time. */
4995 skip_whitespace (fpnum);
4997 if (strncmp (fpnum, "0x", 2) == 0)
5001 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
5002 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5012 if ((str = atof_ieee (str, 's', words)) != NULL)
5014 unsigned fpword = 0;
5017 /* Our FP word must be 32 bits (single-precision FP). */
5018 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
5020 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5024 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
5037 /* Shift operands. */
5040 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
5043 struct asm_shift_name
5046 enum shift_kind kind;
5049 /* Third argument to parse_shift. */
5050 enum parse_shift_mode
5052 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5053 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5054 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5055 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5056 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
5059 /* Parse a <shift> specifier on an ARM data processing instruction.
5060 This has three forms:
5062 (LSL|LSR|ASL|ASR|ROR) Rs
5063 (LSL|LSR|ASL|ASR|ROR) #imm
5066 Note that ASL is assimilated to LSL in the instruction encoding, and
5067 RRX to ROR #0 (which cannot be written as such). */
5070 parse_shift (char **str, int i, enum parse_shift_mode mode)
5072 const struct asm_shift_name *shift_name;
5073 enum shift_kind shift;
5078 for (p = *str; ISALPHA (*p); p++)
5083 inst.error = _("shift expression expected");
5087 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
5090 if (shift_name == NULL)
5092 inst.error = _("shift expression expected");
5096 shift = shift_name->kind;
5100 case NO_SHIFT_RESTRICT:
5101 case SHIFT_IMMEDIATE: break;
5103 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5104 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5106 inst.error = _("'LSL' or 'ASR' required");
5111 case SHIFT_LSL_IMMEDIATE:
5112 if (shift != SHIFT_LSL)
5114 inst.error = _("'LSL' required");
5119 case SHIFT_ASR_IMMEDIATE:
5120 if (shift != SHIFT_ASR)
5122 inst.error = _("'ASR' required");
5130 if (shift != SHIFT_RRX)
5132 /* Whitespace can appear here if the next thing is a bare digit. */
5133 skip_whitespace (p);
5135 if (mode == NO_SHIFT_RESTRICT
5136 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5138 inst.operands[i].imm = reg;
5139 inst.operands[i].immisreg = 1;
5141 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5144 inst.operands[i].shift_kind = shift;
5145 inst.operands[i].shifted = 1;
5150 /* Parse a <shifter_operand> for an ARM data processing instruction:
5153 #<immediate>, <rotate>
5157 where <shift> is defined by parse_shift above, and <rotate> is a
5158 multiple of 2 between 0 and 30. Validation of immediate operands
5159 is deferred to md_apply_fix. */
5162 parse_shifter_operand (char **str, int i)
5167 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
5169 inst.operands[i].reg = value;
5170 inst.operands[i].isreg = 1;
5172 /* parse_shift will override this if appropriate */
5173 inst.reloc.exp.X_op = O_constant;
5174 inst.reloc.exp.X_add_number = 0;
5176 if (skip_past_comma (str) == FAIL)
5179 /* Shift operation on register. */
5180 return parse_shift (str, i, NO_SHIFT_RESTRICT);
5183 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
5186 if (skip_past_comma (str) == SUCCESS)
5188 /* #x, y -- ie explicit rotation by Y. */
5189 if (my_get_expression (&exp, str, GE_NO_PREFIX))
5192 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
5194 inst.error = _("constant expression expected");
5198 value = exp.X_add_number;
5199 if (value < 0 || value > 30 || value % 2 != 0)
5201 inst.error = _("invalid rotation");
5204 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
5206 inst.error = _("invalid constant");
5210 /* Encode as specified. */
5211 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
5215 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5216 inst.reloc.pc_rel = 0;
5220 /* Group relocation information. Each entry in the table contains the
5221 textual name of the relocation as may appear in assembler source
5222 and must end with a colon.
5223 Along with this textual name are the relocation codes to be used if
5224 the corresponding instruction is an ALU instruction (ADD or SUB only),
5225 an LDR, an LDRS, or an LDC. */
5227 struct group_reloc_table_entry
5238 /* Varieties of non-ALU group relocation. */
5245 static struct group_reloc_table_entry group_reloc_table[] =
5246 { /* Program counter relative: */
5248 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5253 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5254 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5255 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5256 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5258 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5263 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5264 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5265 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5266 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5268 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5269 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5270 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5271 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5272 /* Section base relative */
5274 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5279 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5280 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5281 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5282 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5284 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5289 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5290 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5291 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5292 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5294 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5295 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5296 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5297 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5298 /* Absolute thumb alu relocations. */
5300 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5305 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5310 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5315 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5320 /* Given the address of a pointer pointing to the textual name of a group
5321 relocation as may appear in assembler source, attempt to find its details
5322 in group_reloc_table. The pointer will be updated to the character after
5323 the trailing colon. On failure, FAIL will be returned; SUCCESS
5324 otherwise. On success, *entry will be updated to point at the relevant
5325 group_reloc_table entry. */
5328 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5331 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5333 int length = strlen (group_reloc_table[i].name);
5335 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5336 && (*str)[length] == ':')
5338 *out = &group_reloc_table[i];
5339 *str += (length + 1);
5347 /* Parse a <shifter_operand> for an ARM data processing instruction
5348 (as for parse_shifter_operand) where group relocations are allowed:
5351 #<immediate>, <rotate>
5352 #:<group_reloc>:<expression>
5356 where <group_reloc> is one of the strings defined in group_reloc_table.
5357 The hashes are optional.
5359 Everything else is as for parse_shifter_operand. */
5361 static parse_operand_result
5362 parse_shifter_operand_group_reloc (char **str, int i)
5364 /* Determine if we have the sequence of characters #: or just :
5365 coming next. If we do, then we check for a group relocation.
5366 If we don't, punt the whole lot to parse_shifter_operand. */
5368 if (((*str)[0] == '#' && (*str)[1] == ':')
5369 || (*str)[0] == ':')
5371 struct group_reloc_table_entry *entry;
5373 if ((*str)[0] == '#')
5378 /* Try to parse a group relocation. Anything else is an error. */
5379 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5381 inst.error = _("unknown group relocation");
5382 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5385 /* We now have the group relocation table entry corresponding to
5386 the name in the assembler source. Next, we parse the expression. */
5387 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5388 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5390 /* Record the relocation type (always the ALU variant here). */
5391 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5392 gas_assert (inst.reloc.type != 0);
5394 return PARSE_OPERAND_SUCCESS;
5397 return parse_shifter_operand (str, i) == SUCCESS
5398 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5400 /* Never reached. */
5403 /* Parse a Neon alignment expression. Information is written to
5404 inst.operands[i]. We assume the initial ':' has been skipped.
5406 align .imm = align << 8, .immisalign=1, .preind=0 */
5407 static parse_operand_result
5408 parse_neon_alignment (char **str, int i)
5413 my_get_expression (&exp, &p, GE_NO_PREFIX);
5415 if (exp.X_op != O_constant)
5417 inst.error = _("alignment must be constant");
5418 return PARSE_OPERAND_FAIL;
5421 inst.operands[i].imm = exp.X_add_number << 8;
5422 inst.operands[i].immisalign = 1;
5423 /* Alignments are not pre-indexes. */
5424 inst.operands[i].preind = 0;
5427 return PARSE_OPERAND_SUCCESS;
5430 /* Parse all forms of an ARM address expression. Information is written
5431 to inst.operands[i] and/or inst.reloc.
5433 Preindexed addressing (.preind=1):
5435 [Rn, #offset] .reg=Rn .reloc.exp=offset
5436 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5437 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5438 .shift_kind=shift .reloc.exp=shift_imm
5440 These three may have a trailing ! which causes .writeback to be set also.
5442 Postindexed addressing (.postind=1, .writeback=1):
5444 [Rn], #offset .reg=Rn .reloc.exp=offset
5445 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5446 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5447 .shift_kind=shift .reloc.exp=shift_imm
5449 Unindexed addressing (.preind=0, .postind=0):
5451 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5455 [Rn]{!} shorthand for [Rn,#0]{!}
5456 =immediate .isreg=0 .reloc.exp=immediate
5457 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5459 It is the caller's responsibility to check for addressing modes not
5460 supported by the instruction, and to set inst.reloc.type. */
5462 static parse_operand_result
5463 parse_address_main (char **str, int i, int group_relocations,
5464 group_reloc_type group_type)
5469 if (skip_past_char (&p, '[') == FAIL)
5471 if (skip_past_char (&p, '=') == FAIL)
5473 /* Bare address - translate to PC-relative offset. */
5474 inst.reloc.pc_rel = 1;
5475 inst.operands[i].reg = REG_PC;
5476 inst.operands[i].isreg = 1;
5477 inst.operands[i].preind = 1;
5479 if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG))
5480 return PARSE_OPERAND_FAIL;
5482 else if (parse_big_immediate (&p, i, &inst.reloc.exp,
5483 /*allow_symbol_p=*/TRUE))
5484 return PARSE_OPERAND_FAIL;
5487 return PARSE_OPERAND_SUCCESS;
5490 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5491 skip_whitespace (p);
5493 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5495 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5496 return PARSE_OPERAND_FAIL;
5498 inst.operands[i].reg = reg;
5499 inst.operands[i].isreg = 1;
5501 if (skip_past_comma (&p) == SUCCESS)
5503 inst.operands[i].preind = 1;
5506 else if (*p == '-') p++, inst.operands[i].negative = 1;
5508 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5510 inst.operands[i].imm = reg;
5511 inst.operands[i].immisreg = 1;
5513 if (skip_past_comma (&p) == SUCCESS)
5514 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5515 return PARSE_OPERAND_FAIL;
5517 else if (skip_past_char (&p, ':') == SUCCESS)
5519 /* FIXME: '@' should be used here, but it's filtered out by generic
5520 code before we get to see it here. This may be subject to
5522 parse_operand_result result = parse_neon_alignment (&p, i);
5524 if (result != PARSE_OPERAND_SUCCESS)
5529 if (inst.operands[i].negative)
5531 inst.operands[i].negative = 0;
5535 if (group_relocations
5536 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5538 struct group_reloc_table_entry *entry;
5540 /* Skip over the #: or : sequence. */
5546 /* Try to parse a group relocation. Anything else is an
5548 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5550 inst.error = _("unknown group relocation");
5551 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5554 /* We now have the group relocation table entry corresponding to
5555 the name in the assembler source. Next, we parse the
5557 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5558 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5560 /* Record the relocation type. */
5564 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5568 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5572 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5579 if (inst.reloc.type == 0)
5581 inst.error = _("this group relocation is not allowed on this instruction");
5582 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5588 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5589 return PARSE_OPERAND_FAIL;
5590 /* If the offset is 0, find out if it's a +0 or -0. */
5591 if (inst.reloc.exp.X_op == O_constant
5592 && inst.reloc.exp.X_add_number == 0)
5594 skip_whitespace (q);
5598 skip_whitespace (q);
5601 inst.operands[i].negative = 1;
5606 else if (skip_past_char (&p, ':') == SUCCESS)
5608 /* FIXME: '@' should be used here, but it's filtered out by generic code
5609 before we get to see it here. This may be subject to change. */
5610 parse_operand_result result = parse_neon_alignment (&p, i);
5612 if (result != PARSE_OPERAND_SUCCESS)
5616 if (skip_past_char (&p, ']') == FAIL)
5618 inst.error = _("']' expected");
5619 return PARSE_OPERAND_FAIL;
5622 if (skip_past_char (&p, '!') == SUCCESS)
5623 inst.operands[i].writeback = 1;
5625 else if (skip_past_comma (&p) == SUCCESS)
5627 if (skip_past_char (&p, '{') == SUCCESS)
5629 /* [Rn], {expr} - unindexed, with option */
5630 if (parse_immediate (&p, &inst.operands[i].imm,
5631 0, 255, TRUE) == FAIL)
5632 return PARSE_OPERAND_FAIL;
5634 if (skip_past_char (&p, '}') == FAIL)
5636 inst.error = _("'}' expected at end of 'option' field");
5637 return PARSE_OPERAND_FAIL;
5639 if (inst.operands[i].preind)
5641 inst.error = _("cannot combine index with option");
5642 return PARSE_OPERAND_FAIL;
5645 return PARSE_OPERAND_SUCCESS;
5649 inst.operands[i].postind = 1;
5650 inst.operands[i].writeback = 1;
5652 if (inst.operands[i].preind)
5654 inst.error = _("cannot combine pre- and post-indexing");
5655 return PARSE_OPERAND_FAIL;
5659 else if (*p == '-') p++, inst.operands[i].negative = 1;
5661 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5663 /* We might be using the immediate for alignment already. If we
5664 are, OR the register number into the low-order bits. */
5665 if (inst.operands[i].immisalign)
5666 inst.operands[i].imm |= reg;
5668 inst.operands[i].imm = reg;
5669 inst.operands[i].immisreg = 1;
5671 if (skip_past_comma (&p) == SUCCESS)
5672 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5673 return PARSE_OPERAND_FAIL;
5678 if (inst.operands[i].negative)
5680 inst.operands[i].negative = 0;
5683 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5684 return PARSE_OPERAND_FAIL;
5685 /* If the offset is 0, find out if it's a +0 or -0. */
5686 if (inst.reloc.exp.X_op == O_constant
5687 && inst.reloc.exp.X_add_number == 0)
5689 skip_whitespace (q);
5693 skip_whitespace (q);
5696 inst.operands[i].negative = 1;
5702 /* If at this point neither .preind nor .postind is set, we have a
5703 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5704 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5706 inst.operands[i].preind = 1;
5707 inst.reloc.exp.X_op = O_constant;
5708 inst.reloc.exp.X_add_number = 0;
5711 return PARSE_OPERAND_SUCCESS;
5715 parse_address (char **str, int i)
5717 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5721 static parse_operand_result
5722 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5724 return parse_address_main (str, i, 1, type);
5727 /* Parse an operand for a MOVW or MOVT instruction. */
5729 parse_half (char **str)
5734 skip_past_char (&p, '#');
5735 if (strncasecmp (p, ":lower16:", 9) == 0)
5736 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5737 else if (strncasecmp (p, ":upper16:", 9) == 0)
5738 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5740 if (inst.reloc.type != BFD_RELOC_UNUSED)
5743 skip_whitespace (p);
5746 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5749 if (inst.reloc.type == BFD_RELOC_UNUSED)
5751 if (inst.reloc.exp.X_op != O_constant)
5753 inst.error = _("constant expression expected");
5756 if (inst.reloc.exp.X_add_number < 0
5757 || inst.reloc.exp.X_add_number > 0xffff)
5759 inst.error = _("immediate value out of range");
5767 /* Miscellaneous. */
5769 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5770 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5772 parse_psr (char **str, bfd_boolean lhs)
5775 unsigned long psr_field;
5776 const struct asm_psr *psr;
5778 bfd_boolean is_apsr = FALSE;
5779 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5781 /* PR gas/12698: If the user has specified -march=all then m_profile will
5782 be TRUE, but we want to ignore it in this case as we are building for any
5783 CPU type, including non-m variants. */
5784 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
5787 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5788 feature for ease of use and backwards compatibility. */
5790 if (strncasecmp (p, "SPSR", 4) == 0)
5793 goto unsupported_psr;
5795 psr_field = SPSR_BIT;
5797 else if (strncasecmp (p, "CPSR", 4) == 0)
5800 goto unsupported_psr;
5804 else if (strncasecmp (p, "APSR", 4) == 0)
5806 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5807 and ARMv7-R architecture CPUs. */
5816 while (ISALNUM (*p) || *p == '_');
5818 if (strncasecmp (start, "iapsr", 5) == 0
5819 || strncasecmp (start, "eapsr", 5) == 0
5820 || strncasecmp (start, "xpsr", 4) == 0
5821 || strncasecmp (start, "psr", 3) == 0)
5822 p = start + strcspn (start, "rR") + 1;
5824 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5830 /* If APSR is being written, a bitfield may be specified. Note that
5831 APSR itself is handled above. */
5832 if (psr->field <= 3)
5834 psr_field = psr->field;
5840 /* M-profile MSR instructions have the mask field set to "10", except
5841 *PSR variants which modify APSR, which may use a different mask (and
5842 have been handled already). Do that by setting the PSR_f field
5844 return psr->field | (lhs ? PSR_f : 0);
5847 goto unsupported_psr;
5853 /* A suffix follows. */
5859 while (ISALNUM (*p) || *p == '_');
5863 /* APSR uses a notation for bits, rather than fields. */
5864 unsigned int nzcvq_bits = 0;
5865 unsigned int g_bit = 0;
5868 for (bit = start; bit != p; bit++)
5870 switch (TOLOWER (*bit))
5873 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5877 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5881 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5885 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5889 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5893 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5897 inst.error = _("unexpected bit specified after APSR");
5902 if (nzcvq_bits == 0x1f)
5907 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5909 inst.error = _("selected processor does not "
5910 "support DSP extension");
5917 if ((nzcvq_bits & 0x20) != 0
5918 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5919 || (g_bit & 0x2) != 0)
5921 inst.error = _("bad bitmask specified after APSR");
5927 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5932 psr_field |= psr->field;
5938 goto error; /* Garbage after "[CS]PSR". */
5940 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5941 is deprecated, but allow it anyway. */
5945 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5948 else if (!m_profile)
5949 /* These bits are never right for M-profile devices: don't set them
5950 (only code paths which read/write APSR reach here). */
5951 psr_field |= (PSR_c | PSR_f);
5957 inst.error = _("selected processor does not support requested special "
5958 "purpose register");
5962 inst.error = _("flag for {c}psr instruction expected");
5966 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5967 value suitable for splatting into the AIF field of the instruction. */
5970 parse_cps_flags (char **str)
5979 case '\0': case ',':
5982 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5983 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5984 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5987 inst.error = _("unrecognized CPS flag");
5992 if (saw_a_flag == 0)
5994 inst.error = _("missing CPS flags");
6002 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6003 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6006 parse_endian_specifier (char **str)
6011 if (strncasecmp (s, "BE", 2))
6013 else if (strncasecmp (s, "LE", 2))
6017 inst.error = _("valid endian specifiers are be or le");
6021 if (ISALNUM (s[2]) || s[2] == '_')
6023 inst.error = _("valid endian specifiers are be or le");
6028 return little_endian;
6031 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6032 value suitable for poking into the rotate field of an sxt or sxta
6033 instruction, or FAIL on error. */
6036 parse_ror (char **str)
6041 if (strncasecmp (s, "ROR", 3) == 0)
6045 inst.error = _("missing rotation field after comma");
6049 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6054 case 0: *str = s; return 0x0;
6055 case 8: *str = s; return 0x1;
6056 case 16: *str = s; return 0x2;
6057 case 24: *str = s; return 0x3;
6060 inst.error = _("rotation can only be 0, 8, 16, or 24");
6065 /* Parse a conditional code (from conds[] below). The value returned is in the
6066 range 0 .. 14, or FAIL. */
6068 parse_cond (char **str)
6071 const struct asm_cond *c;
6073 /* Condition codes are always 2 characters, so matching up to
6074 3 characters is sufficient. */
6079 while (ISALPHA (*q) && n < 3)
6081 cond[n] = TOLOWER (*q);
6086 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
6089 inst.error = _("condition required");
6097 /* Record a use of the given feature. */
6099 record_feature_use (const arm_feature_set *feature)
6102 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
6104 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
6107 /* If the given feature available in the selected CPU, mark it as used.
6108 Returns TRUE iff feature is available. */
6110 mark_feature_used (const arm_feature_set *feature)
6112 /* Ensure the option is valid on the current architecture. */
6113 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
6116 /* Add the appropriate architecture feature for the barrier option used.
6118 record_feature_use (feature);
6123 /* Parse an option for a barrier instruction. Returns the encoding for the
6126 parse_barrier (char **str)
6129 const struct asm_barrier_opt *o;
6132 while (ISALPHA (*q))
6135 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
6140 if (!mark_feature_used (&o->arch))
6147 /* Parse the operands of a table branch instruction. Similar to a memory
6150 parse_tb (char **str)
6155 if (skip_past_char (&p, '[') == FAIL)
6157 inst.error = _("'[' expected");
6161 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6163 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6166 inst.operands[0].reg = reg;
6168 if (skip_past_comma (&p) == FAIL)
6170 inst.error = _("',' expected");
6174 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6176 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6179 inst.operands[0].imm = reg;
6181 if (skip_past_comma (&p) == SUCCESS)
6183 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6185 if (inst.reloc.exp.X_add_number != 1)
6187 inst.error = _("invalid shift");
6190 inst.operands[0].shifted = 1;
6193 if (skip_past_char (&p, ']') == FAIL)
6195 inst.error = _("']' expected");
6202 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6203 information on the types the operands can take and how they are encoded.
6204 Up to four operands may be read; this function handles setting the
6205 ".present" field for each read operand itself.
6206 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6207 else returns FAIL. */
6210 parse_neon_mov (char **str, int *which_operand)
6212 int i = *which_operand, val;
6213 enum arm_reg_type rtype;
6215 struct neon_type_el optype;
6217 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6219 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6220 inst.operands[i].reg = val;
6221 inst.operands[i].isscalar = 1;
6222 inst.operands[i].vectype = optype;
6223 inst.operands[i++].present = 1;
6225 if (skip_past_comma (&ptr) == FAIL)
6228 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6231 inst.operands[i].reg = val;
6232 inst.operands[i].isreg = 1;
6233 inst.operands[i].present = 1;
6235 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6238 /* Cases 0, 1, 2, 3, 5 (D only). */
6239 if (skip_past_comma (&ptr) == FAIL)
6242 inst.operands[i].reg = val;
6243 inst.operands[i].isreg = 1;
6244 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6245 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6246 inst.operands[i].isvec = 1;
6247 inst.operands[i].vectype = optype;
6248 inst.operands[i++].present = 1;
6250 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6252 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6253 Case 13: VMOV <Sd>, <Rm> */
6254 inst.operands[i].reg = val;
6255 inst.operands[i].isreg = 1;
6256 inst.operands[i].present = 1;
6258 if (rtype == REG_TYPE_NQ)
6260 first_error (_("can't use Neon quad register here"));
6263 else if (rtype != REG_TYPE_VFS)
6266 if (skip_past_comma (&ptr) == FAIL)
6268 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6270 inst.operands[i].reg = val;
6271 inst.operands[i].isreg = 1;
6272 inst.operands[i].present = 1;
6275 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6278 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6279 Case 1: VMOV<c><q> <Dd>, <Dm>
6280 Case 8: VMOV.F32 <Sd>, <Sm>
6281 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6283 inst.operands[i].reg = val;
6284 inst.operands[i].isreg = 1;
6285 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6286 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6287 inst.operands[i].isvec = 1;
6288 inst.operands[i].vectype = optype;
6289 inst.operands[i].present = 1;
6291 if (skip_past_comma (&ptr) == SUCCESS)
6296 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6299 inst.operands[i].reg = val;
6300 inst.operands[i].isreg = 1;
6301 inst.operands[i++].present = 1;
6303 if (skip_past_comma (&ptr) == FAIL)
6306 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6309 inst.operands[i].reg = val;
6310 inst.operands[i].isreg = 1;
6311 inst.operands[i].present = 1;
6314 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6315 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6316 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6317 Case 10: VMOV.F32 <Sd>, #<imm>
6318 Case 11: VMOV.F64 <Dd>, #<imm> */
6319 inst.operands[i].immisfloat = 1;
6320 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6322 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6323 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6327 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6331 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6334 inst.operands[i].reg = val;
6335 inst.operands[i].isreg = 1;
6336 inst.operands[i++].present = 1;
6338 if (skip_past_comma (&ptr) == FAIL)
6341 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6343 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6344 inst.operands[i].reg = val;
6345 inst.operands[i].isscalar = 1;
6346 inst.operands[i].present = 1;
6347 inst.operands[i].vectype = optype;
6349 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6351 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6352 inst.operands[i].reg = val;
6353 inst.operands[i].isreg = 1;
6354 inst.operands[i++].present = 1;
6356 if (skip_past_comma (&ptr) == FAIL)
6359 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6362 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6366 inst.operands[i].reg = val;
6367 inst.operands[i].isreg = 1;
6368 inst.operands[i].isvec = 1;
6369 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6370 inst.operands[i].vectype = optype;
6371 inst.operands[i].present = 1;
6373 if (rtype == REG_TYPE_VFS)
6377 if (skip_past_comma (&ptr) == FAIL)
6379 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6382 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6385 inst.operands[i].reg = val;
6386 inst.operands[i].isreg = 1;
6387 inst.operands[i].isvec = 1;
6388 inst.operands[i].issingle = 1;
6389 inst.operands[i].vectype = optype;
6390 inst.operands[i].present = 1;
6393 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6397 inst.operands[i].reg = val;
6398 inst.operands[i].isreg = 1;
6399 inst.operands[i].isvec = 1;
6400 inst.operands[i].issingle = 1;
6401 inst.operands[i].vectype = optype;
6402 inst.operands[i].present = 1;
6407 first_error (_("parse error"));
6411 /* Successfully parsed the operands. Update args. */
6417 first_error (_("expected comma"));
6421 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6425 /* Use this macro when the operand constraints are different
6426 for ARM and THUMB (e.g. ldrd). */
6427 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6428 ((arm_operand) | ((thumb_operand) << 16))
6430 /* Matcher codes for parse_operands. */
6431 enum operand_parse_code
6433 OP_stop, /* end of line */
6435 OP_RR, /* ARM register */
6436 OP_RRnpc, /* ARM register, not r15 */
6437 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6438 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6439 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6440 optional trailing ! */
6441 OP_RRw, /* ARM register, not r15, optional trailing ! */
6442 OP_RCP, /* Coprocessor number */
6443 OP_RCN, /* Coprocessor register */
6444 OP_RF, /* FPA register */
6445 OP_RVS, /* VFP single precision register */
6446 OP_RVD, /* VFP double precision register (0..15) */
6447 OP_RND, /* Neon double precision register (0..31) */
6448 OP_RNQ, /* Neon quad precision register */
6449 OP_RVSD, /* VFP single or double precision register */
6450 OP_RNDQ, /* Neon double or quad precision register */
6451 OP_RNSDQ, /* Neon single, double or quad precision register */
6452 OP_RNSC, /* Neon scalar D[X] */
6453 OP_RVC, /* VFP control register */
6454 OP_RMF, /* Maverick F register */
6455 OP_RMD, /* Maverick D register */
6456 OP_RMFX, /* Maverick FX register */
6457 OP_RMDX, /* Maverick DX register */
6458 OP_RMAX, /* Maverick AX register */
6459 OP_RMDS, /* Maverick DSPSC register */
6460 OP_RIWR, /* iWMMXt wR register */
6461 OP_RIWC, /* iWMMXt wC register */
6462 OP_RIWG, /* iWMMXt wCG register */
6463 OP_RXA, /* XScale accumulator register */
6465 OP_REGLST, /* ARM register list */
6466 OP_VRSLST, /* VFP single-precision register list */
6467 OP_VRDLST, /* VFP double-precision register list */
6468 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6469 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6470 OP_NSTRLST, /* Neon element/structure list */
6472 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6473 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6474 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
6475 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6476 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6477 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6478 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6479 OP_VMOV, /* Neon VMOV operands. */
6480 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6481 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6482 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6484 OP_I0, /* immediate zero */
6485 OP_I7, /* immediate value 0 .. 7 */
6486 OP_I15, /* 0 .. 15 */
6487 OP_I16, /* 1 .. 16 */
6488 OP_I16z, /* 0 .. 16 */
6489 OP_I31, /* 0 .. 31 */
6490 OP_I31w, /* 0 .. 31, optional trailing ! */
6491 OP_I32, /* 1 .. 32 */
6492 OP_I32z, /* 0 .. 32 */
6493 OP_I63, /* 0 .. 63 */
6494 OP_I63s, /* -64 .. 63 */
6495 OP_I64, /* 1 .. 64 */
6496 OP_I64z, /* 0 .. 64 */
6497 OP_I255, /* 0 .. 255 */
6499 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6500 OP_I7b, /* 0 .. 7 */
6501 OP_I15b, /* 0 .. 15 */
6502 OP_I31b, /* 0 .. 31 */
6504 OP_SH, /* shifter operand */
6505 OP_SHG, /* shifter operand with possible group relocation */
6506 OP_ADDR, /* Memory address expression (any mode) */
6507 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6508 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6509 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6510 OP_EXP, /* arbitrary expression */
6511 OP_EXPi, /* same, with optional immediate prefix */
6512 OP_EXPr, /* same, with optional relocation suffix */
6513 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6515 OP_CPSF, /* CPS flags */
6516 OP_ENDI, /* Endianness specifier */
6517 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6518 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6519 OP_COND, /* conditional code */
6520 OP_TB, /* Table branch. */
6522 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6524 OP_RRnpc_I0, /* ARM register or literal 0 */
6525 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6526 OP_RR_EXi, /* ARM register or expression with imm prefix */
6527 OP_RF_IF, /* FPA register or immediate */
6528 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6529 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6531 /* Optional operands. */
6532 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6533 OP_oI31b, /* 0 .. 31 */
6534 OP_oI32b, /* 1 .. 32 */
6535 OP_oI32z, /* 0 .. 32 */
6536 OP_oIffffb, /* 0 .. 65535 */
6537 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6539 OP_oRR, /* ARM register */
6540 OP_oRRnpc, /* ARM register, not the PC */
6541 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6542 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6543 OP_oRND, /* Optional Neon double precision register */
6544 OP_oRNQ, /* Optional Neon quad precision register */
6545 OP_oRNDQ, /* Optional Neon double or quad precision register */
6546 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6547 OP_oSHll, /* LSL immediate */
6548 OP_oSHar, /* ASR immediate */
6549 OP_oSHllar, /* LSL or ASR immediate */
6550 OP_oROR, /* ROR 0/8/16/24 */
6551 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6553 /* Some pre-defined mixed (ARM/THUMB) operands. */
6554 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6555 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6556 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6558 OP_FIRST_OPTIONAL = OP_oI7b
6561 /* Generic instruction operand parser. This does no encoding and no
6562 semantic validation; it merely squirrels values away in the inst
6563 structure. Returns SUCCESS or FAIL depending on whether the
6564 specified grammar matched. */
6566 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6568 unsigned const int *upat = pattern;
6569 char *backtrack_pos = 0;
6570 const char *backtrack_error = 0;
6571 int i, val = 0, backtrack_index = 0;
6572 enum arm_reg_type rtype;
6573 parse_operand_result result;
6574 unsigned int op_parse_code;
6576 #define po_char_or_fail(chr) \
6579 if (skip_past_char (&str, chr) == FAIL) \
6584 #define po_reg_or_fail(regtype) \
6587 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6588 & inst.operands[i].vectype); \
6591 first_error (_(reg_expected_msgs[regtype])); \
6594 inst.operands[i].reg = val; \
6595 inst.operands[i].isreg = 1; \
6596 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6597 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6598 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6599 || rtype == REG_TYPE_VFD \
6600 || rtype == REG_TYPE_NQ); \
6604 #define po_reg_or_goto(regtype, label) \
6607 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6608 & inst.operands[i].vectype); \
6612 inst.operands[i].reg = val; \
6613 inst.operands[i].isreg = 1; \
6614 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6615 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6616 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6617 || rtype == REG_TYPE_VFD \
6618 || rtype == REG_TYPE_NQ); \
6622 #define po_imm_or_fail(min, max, popt) \
6625 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6627 inst.operands[i].imm = val; \
6631 #define po_scalar_or_goto(elsz, label) \
6634 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6637 inst.operands[i].reg = val; \
6638 inst.operands[i].isscalar = 1; \
6642 #define po_misc_or_fail(expr) \
6650 #define po_misc_or_fail_no_backtrack(expr) \
6654 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6655 backtrack_pos = 0; \
6656 if (result != PARSE_OPERAND_SUCCESS) \
6661 #define po_barrier_or_imm(str) \
6664 val = parse_barrier (&str); \
6665 if (val == FAIL && ! ISALPHA (*str)) \
6668 /* ISB can only take SY as an option. */ \
6669 || ((inst.instruction & 0xf0) == 0x60 \
6672 inst.error = _("invalid barrier type"); \
6673 backtrack_pos = 0; \
6679 skip_whitespace (str);
6681 for (i = 0; upat[i] != OP_stop; i++)
6683 op_parse_code = upat[i];
6684 if (op_parse_code >= 1<<16)
6685 op_parse_code = thumb ? (op_parse_code >> 16)
6686 : (op_parse_code & ((1<<16)-1));
6688 if (op_parse_code >= OP_FIRST_OPTIONAL)
6690 /* Remember where we are in case we need to backtrack. */
6691 gas_assert (!backtrack_pos);
6692 backtrack_pos = str;
6693 backtrack_error = inst.error;
6694 backtrack_index = i;
6697 if (i > 0 && (i > 1 || inst.operands[0].present))
6698 po_char_or_fail (',');
6700 switch (op_parse_code)
6708 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6709 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6710 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6711 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6712 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6713 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6715 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6717 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6719 /* Also accept generic coprocessor regs for unknown registers. */
6721 po_reg_or_fail (REG_TYPE_CN);
6723 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6724 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6725 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6726 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6727 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6728 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6729 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6730 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6731 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6732 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6734 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6736 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6737 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6739 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6741 /* Neon scalar. Using an element size of 8 means that some invalid
6742 scalars are accepted here, so deal with those in later code. */
6743 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6747 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6750 po_imm_or_fail (0, 0, TRUE);
6755 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6760 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
6763 if (parse_ifimm_zero (&str))
6764 inst.operands[i].imm = 0;
6768 = _("only floating point zero is allowed as immediate value");
6776 po_scalar_or_goto (8, try_rr);
6779 po_reg_or_fail (REG_TYPE_RN);
6785 po_scalar_or_goto (8, try_nsdq);
6788 po_reg_or_fail (REG_TYPE_NSDQ);
6794 po_scalar_or_goto (8, try_ndq);
6797 po_reg_or_fail (REG_TYPE_NDQ);
6803 po_scalar_or_goto (8, try_vfd);
6806 po_reg_or_fail (REG_TYPE_VFD);
6811 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6812 not careful then bad things might happen. */
6813 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6818 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6821 /* There's a possibility of getting a 64-bit immediate here, so
6822 we need special handling. */
6823 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
6826 inst.error = _("immediate value is out of range");
6834 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6837 po_imm_or_fail (0, 63, TRUE);
6842 po_char_or_fail ('[');
6843 po_reg_or_fail (REG_TYPE_RN);
6844 po_char_or_fail (']');
6850 po_reg_or_fail (REG_TYPE_RN);
6851 if (skip_past_char (&str, '!') == SUCCESS)
6852 inst.operands[i].writeback = 1;
6856 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6857 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6858 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6859 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6860 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6861 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6862 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6863 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6864 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6865 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6866 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6867 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6869 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6871 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6872 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6874 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6875 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6876 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6877 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6879 /* Immediate variants */
6881 po_char_or_fail ('{');
6882 po_imm_or_fail (0, 255, TRUE);
6883 po_char_or_fail ('}');
6887 /* The expression parser chokes on a trailing !, so we have
6888 to find it first and zap it. */
6891 while (*s && *s != ',')
6896 inst.operands[i].writeback = 1;
6898 po_imm_or_fail (0, 31, TRUE);
6906 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6911 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6916 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6918 if (inst.reloc.exp.X_op == O_symbol)
6920 val = parse_reloc (&str);
6923 inst.error = _("unrecognized relocation suffix");
6926 else if (val != BFD_RELOC_UNUSED)
6928 inst.operands[i].imm = val;
6929 inst.operands[i].hasreloc = 1;
6934 /* Operand for MOVW or MOVT. */
6936 po_misc_or_fail (parse_half (&str));
6939 /* Register or expression. */
6940 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6941 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6943 /* Register or immediate. */
6944 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6945 I0: po_imm_or_fail (0, 0, FALSE); break;
6947 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6949 if (!is_immediate_prefix (*str))
6952 val = parse_fpa_immediate (&str);
6955 /* FPA immediates are encoded as registers 8-15.
6956 parse_fpa_immediate has already applied the offset. */
6957 inst.operands[i].reg = val;
6958 inst.operands[i].isreg = 1;
6961 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6962 I32z: po_imm_or_fail (0, 32, FALSE); break;
6964 /* Two kinds of register. */
6967 struct reg_entry *rege = arm_reg_parse_multi (&str);
6969 || (rege->type != REG_TYPE_MMXWR
6970 && rege->type != REG_TYPE_MMXWC
6971 && rege->type != REG_TYPE_MMXWCG))
6973 inst.error = _("iWMMXt data or control register expected");
6976 inst.operands[i].reg = rege->number;
6977 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6983 struct reg_entry *rege = arm_reg_parse_multi (&str);
6985 || (rege->type != REG_TYPE_MMXWC
6986 && rege->type != REG_TYPE_MMXWCG))
6988 inst.error = _("iWMMXt control register expected");
6991 inst.operands[i].reg = rege->number;
6992 inst.operands[i].isreg = 1;
6997 case OP_CPSF: val = parse_cps_flags (&str); break;
6998 case OP_ENDI: val = parse_endian_specifier (&str); break;
6999 case OP_oROR: val = parse_ror (&str); break;
7000 case OP_COND: val = parse_cond (&str); break;
7001 case OP_oBARRIER_I15:
7002 po_barrier_or_imm (str); break;
7004 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
7010 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7011 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7013 inst.error = _("Banked registers are not available with this "
7019 val = parse_psr (&str, op_parse_code == OP_wPSR);
7023 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7026 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7028 if (strncasecmp (str, "APSR_", 5) == 0)
7035 case 'c': found = (found & 1) ? 16 : found | 1; break;
7036 case 'n': found = (found & 2) ? 16 : found | 2; break;
7037 case 'z': found = (found & 4) ? 16 : found | 4; break;
7038 case 'v': found = (found & 8) ? 16 : found | 8; break;
7039 default: found = 16;
7043 inst.operands[i].isvec = 1;
7044 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7045 inst.operands[i].reg = REG_PC;
7052 po_misc_or_fail (parse_tb (&str));
7055 /* Register lists. */
7057 val = parse_reg_list (&str);
7060 inst.operands[i].writeback = 1;
7066 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
7070 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
7074 /* Allow Q registers too. */
7075 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7080 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7082 inst.operands[i].issingle = 1;
7087 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7092 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7093 &inst.operands[i].vectype);
7096 /* Addressing modes */
7098 po_misc_or_fail (parse_address (&str, i));
7102 po_misc_or_fail_no_backtrack (
7103 parse_address_group_reloc (&str, i, GROUP_LDR));
7107 po_misc_or_fail_no_backtrack (
7108 parse_address_group_reloc (&str, i, GROUP_LDRS));
7112 po_misc_or_fail_no_backtrack (
7113 parse_address_group_reloc (&str, i, GROUP_LDC));
7117 po_misc_or_fail (parse_shifter_operand (&str, i));
7121 po_misc_or_fail_no_backtrack (
7122 parse_shifter_operand_group_reloc (&str, i));
7126 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7130 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7134 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7138 as_fatal (_("unhandled operand code %d"), op_parse_code);
7141 /* Various value-based sanity checks and shared operations. We
7142 do not signal immediate failures for the register constraints;
7143 this allows a syntax error to take precedence. */
7144 switch (op_parse_code)
7152 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7153 inst.error = BAD_PC;
7158 if (inst.operands[i].isreg)
7160 if (inst.operands[i].reg == REG_PC)
7161 inst.error = BAD_PC;
7162 else if (inst.operands[i].reg == REG_SP)
7163 inst.error = BAD_SP;
7168 if (inst.operands[i].isreg
7169 && inst.operands[i].reg == REG_PC
7170 && (inst.operands[i].writeback || thumb))
7171 inst.error = BAD_PC;
7180 case OP_oBARRIER_I15:
7189 inst.operands[i].imm = val;
7196 /* If we get here, this operand was successfully parsed. */
7197 inst.operands[i].present = 1;
7201 inst.error = BAD_ARGS;
7206 /* The parse routine should already have set inst.error, but set a
7207 default here just in case. */
7209 inst.error = _("syntax error");
7213 /* Do not backtrack over a trailing optional argument that
7214 absorbed some text. We will only fail again, with the
7215 'garbage following instruction' error message, which is
7216 probably less helpful than the current one. */
7217 if (backtrack_index == i && backtrack_pos != str
7218 && upat[i+1] == OP_stop)
7221 inst.error = _("syntax error");
7225 /* Try again, skipping the optional argument at backtrack_pos. */
7226 str = backtrack_pos;
7227 inst.error = backtrack_error;
7228 inst.operands[backtrack_index].present = 0;
7229 i = backtrack_index;
7233 /* Check that we have parsed all the arguments. */
7234 if (*str != '\0' && !inst.error)
7235 inst.error = _("garbage following instruction");
7237 return inst.error ? FAIL : SUCCESS;
7240 #undef po_char_or_fail
7241 #undef po_reg_or_fail
7242 #undef po_reg_or_goto
7243 #undef po_imm_or_fail
7244 #undef po_scalar_or_fail
7245 #undef po_barrier_or_imm
7247 /* Shorthand macro for instruction encoding functions issuing errors. */
7248 #define constraint(expr, err) \
7259 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7260 instructions are unpredictable if these registers are used. This
7261 is the BadReg predicate in ARM's Thumb-2 documentation. */
7262 #define reject_bad_reg(reg) \
7264 if (reg == REG_SP || reg == REG_PC) \
7266 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7271 /* If REG is R13 (the stack pointer), warn that its use is
7273 #define warn_deprecated_sp(reg) \
7275 if (warn_on_deprecated && reg == REG_SP) \
7276 as_tsktsk (_("use of r13 is deprecated")); \
7279 /* Functions for operand encoding. ARM, then Thumb. */
7281 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7283 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7285 The only binary encoding difference is the Coprocessor number. Coprocessor
7286 9 is used for half-precision calculations or conversions. The format of the
7287 instruction is the same as the equivalent Coprocessor 10 instuction that
7288 exists for Single-Precision operation. */
7291 do_scalar_fp16_v82_encode (void)
7293 if (inst.cond != COND_ALWAYS)
7294 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7295 " the behaviour is UNPREDICTABLE"));
7296 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
7299 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
7300 mark_feature_used (&arm_ext_fp16);
7303 /* If VAL can be encoded in the immediate field of an ARM instruction,
7304 return the encoded form. Otherwise, return FAIL. */
7307 encode_arm_immediate (unsigned int val)
7314 for (i = 2; i < 32; i += 2)
7315 if ((a = rotate_left (val, i)) <= 0xff)
7316 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
7321 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7322 return the encoded form. Otherwise, return FAIL. */
7324 encode_thumb32_immediate (unsigned int val)
7331 for (i = 1; i <= 24; i++)
7334 if ((val & ~(0xff << i)) == 0)
7335 return ((val >> i) & 0x7f) | ((32 - i) << 7);
7339 if (val == ((a << 16) | a))
7341 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
7345 if (val == ((a << 16) | a))
7346 return 0x200 | (a >> 8);
7350 /* Encode a VFP SP or DP register number into inst.instruction. */
7353 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
7355 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
7358 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
7361 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7364 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7369 first_error (_("D register out of range for selected VFP version"));
7377 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7381 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7385 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7389 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7393 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7397 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7405 /* Encode a <shift> in an ARM-format instruction. The immediate,
7406 if any, is handled by md_apply_fix. */
7408 encode_arm_shift (int i)
7410 if (inst.operands[i].shift_kind == SHIFT_RRX)
7411 inst.instruction |= SHIFT_ROR << 5;
7414 inst.instruction |= inst.operands[i].shift_kind << 5;
7415 if (inst.operands[i].immisreg)
7417 inst.instruction |= SHIFT_BY_REG;
7418 inst.instruction |= inst.operands[i].imm << 8;
7421 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7426 encode_arm_shifter_operand (int i)
7428 if (inst.operands[i].isreg)
7430 inst.instruction |= inst.operands[i].reg;
7431 encode_arm_shift (i);
7435 inst.instruction |= INST_IMMEDIATE;
7436 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7437 inst.instruction |= inst.operands[i].imm;
7441 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7443 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7446 Generate an error if the operand is not a register. */
7447 constraint (!inst.operands[i].isreg,
7448 _("Instruction does not support =N addresses"));
7450 inst.instruction |= inst.operands[i].reg << 16;
7452 if (inst.operands[i].preind)
7456 inst.error = _("instruction does not accept preindexed addressing");
7459 inst.instruction |= PRE_INDEX;
7460 if (inst.operands[i].writeback)
7461 inst.instruction |= WRITE_BACK;
7464 else if (inst.operands[i].postind)
7466 gas_assert (inst.operands[i].writeback);
7468 inst.instruction |= WRITE_BACK;
7470 else /* unindexed - only for coprocessor */
7472 inst.error = _("instruction does not accept unindexed addressing");
7476 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7477 && (((inst.instruction & 0x000f0000) >> 16)
7478 == ((inst.instruction & 0x0000f000) >> 12)))
7479 as_warn ((inst.instruction & LOAD_BIT)
7480 ? _("destination register same as write-back base")
7481 : _("source register same as write-back base"));
7484 /* inst.operands[i] was set up by parse_address. Encode it into an
7485 ARM-format mode 2 load or store instruction. If is_t is true,
7486 reject forms that cannot be used with a T instruction (i.e. not
7489 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7491 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7493 encode_arm_addr_mode_common (i, is_t);
7495 if (inst.operands[i].immisreg)
7497 constraint ((inst.operands[i].imm == REG_PC
7498 || (is_pc && inst.operands[i].writeback)),
7500 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7501 inst.instruction |= inst.operands[i].imm;
7502 if (!inst.operands[i].negative)
7503 inst.instruction |= INDEX_UP;
7504 if (inst.operands[i].shifted)
7506 if (inst.operands[i].shift_kind == SHIFT_RRX)
7507 inst.instruction |= SHIFT_ROR << 5;
7510 inst.instruction |= inst.operands[i].shift_kind << 5;
7511 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7515 else /* immediate offset in inst.reloc */
7517 if (is_pc && !inst.reloc.pc_rel)
7519 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7521 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7522 cannot use PC in addressing.
7523 PC cannot be used in writeback addressing, either. */
7524 constraint ((is_t || inst.operands[i].writeback),
7527 /* Use of PC in str is deprecated for ARMv7. */
7528 if (warn_on_deprecated
7530 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7531 as_tsktsk (_("use of PC in this instruction is deprecated"));
7534 if (inst.reloc.type == BFD_RELOC_UNUSED)
7536 /* Prefer + for zero encoded value. */
7537 if (!inst.operands[i].negative)
7538 inst.instruction |= INDEX_UP;
7539 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7544 /* inst.operands[i] was set up by parse_address. Encode it into an
7545 ARM-format mode 3 load or store instruction. Reject forms that
7546 cannot be used with such instructions. If is_t is true, reject
7547 forms that cannot be used with a T instruction (i.e. not
7550 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7552 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7554 inst.error = _("instruction does not accept scaled register index");
7558 encode_arm_addr_mode_common (i, is_t);
7560 if (inst.operands[i].immisreg)
7562 constraint ((inst.operands[i].imm == REG_PC
7563 || (is_t && inst.operands[i].reg == REG_PC)),
7565 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7567 inst.instruction |= inst.operands[i].imm;
7568 if (!inst.operands[i].negative)
7569 inst.instruction |= INDEX_UP;
7571 else /* immediate offset in inst.reloc */
7573 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7574 && inst.operands[i].writeback),
7576 inst.instruction |= HWOFFSET_IMM;
7577 if (inst.reloc.type == BFD_RELOC_UNUSED)
7579 /* Prefer + for zero encoded value. */
7580 if (!inst.operands[i].negative)
7581 inst.instruction |= INDEX_UP;
7583 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7588 /* Write immediate bits [7:0] to the following locations:
7590 |28/24|23 19|18 16|15 4|3 0|
7591 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7593 This function is used by VMOV/VMVN/VORR/VBIC. */
7596 neon_write_immbits (unsigned immbits)
7598 inst.instruction |= immbits & 0xf;
7599 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
7600 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
7603 /* Invert low-order SIZE bits of XHI:XLO. */
7606 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
7608 unsigned immlo = xlo ? *xlo : 0;
7609 unsigned immhi = xhi ? *xhi : 0;
7614 immlo = (~immlo) & 0xff;
7618 immlo = (~immlo) & 0xffff;
7622 immhi = (~immhi) & 0xffffffff;
7626 immlo = (~immlo) & 0xffffffff;
7640 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7644 neon_bits_same_in_bytes (unsigned imm)
7646 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
7647 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
7648 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
7649 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
7652 /* For immediate of above form, return 0bABCD. */
7655 neon_squash_bits (unsigned imm)
7657 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
7658 | ((imm & 0x01000000) >> 21);
7661 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7664 neon_qfloat_bits (unsigned imm)
7666 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
7669 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7670 the instruction. *OP is passed as the initial value of the op field, and
7671 may be set to a different value depending on the constant (i.e.
7672 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7673 MVN). If the immediate looks like a repeated pattern then also
7674 try smaller element sizes. */
7677 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
7678 unsigned *immbits, int *op, int size,
7679 enum neon_el_type type)
7681 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7683 if (type == NT_float && !float_p)
7686 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
7688 if (size != 32 || *op == 1)
7690 *immbits = neon_qfloat_bits (immlo);
7696 if (neon_bits_same_in_bytes (immhi)
7697 && neon_bits_same_in_bytes (immlo))
7701 *immbits = (neon_squash_bits (immhi) << 4)
7702 | neon_squash_bits (immlo);
7713 if (immlo == (immlo & 0x000000ff))
7718 else if (immlo == (immlo & 0x0000ff00))
7720 *immbits = immlo >> 8;
7723 else if (immlo == (immlo & 0x00ff0000))
7725 *immbits = immlo >> 16;
7728 else if (immlo == (immlo & 0xff000000))
7730 *immbits = immlo >> 24;
7733 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
7735 *immbits = (immlo >> 8) & 0xff;
7738 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
7740 *immbits = (immlo >> 16) & 0xff;
7744 if ((immlo & 0xffff) != (immlo >> 16))
7751 if (immlo == (immlo & 0x000000ff))
7756 else if (immlo == (immlo & 0x0000ff00))
7758 *immbits = immlo >> 8;
7762 if ((immlo & 0xff) != (immlo >> 8))
7767 if (immlo == (immlo & 0x000000ff))
7769 /* Don't allow MVN with 8-bit immediate. */
7779 #if defined BFD_HOST_64_BIT
7780 /* Returns TRUE if double precision value V may be cast
7781 to single precision without loss of accuracy. */
7784 is_double_a_single (bfd_int64_t v)
7786 int exp = (int)((v >> 52) & 0x7FF);
7787 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
7789 return (exp == 0 || exp == 0x7FF
7790 || (exp >= 1023 - 126 && exp <= 1023 + 127))
7791 && (mantissa & 0x1FFFFFFFl) == 0;
7794 /* Returns a double precision value casted to single precision
7795 (ignoring the least significant bits in exponent and mantissa). */
7798 double_to_single (bfd_int64_t v)
7800 int sign = (int) ((v >> 63) & 1l);
7801 int exp = (int) ((v >> 52) & 0x7FF);
7802 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
7808 exp = exp - 1023 + 127;
7817 /* No denormalized numbers. */
7823 return (sign << 31) | (exp << 23) | mantissa;
7825 #endif /* BFD_HOST_64_BIT */
7834 static void do_vfp_nsyn_opcode (const char *);
7836 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7837 Determine whether it can be performed with a move instruction; if
7838 it can, convert inst.instruction to that move instruction and
7839 return TRUE; if it can't, convert inst.instruction to a literal-pool
7840 load and return FALSE. If this is not a valid thing to do in the
7841 current context, set inst.error and return TRUE.
7843 inst.operands[i] describes the destination register. */
7846 move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
7849 bfd_boolean thumb_p = (t == CONST_THUMB);
7850 bfd_boolean arm_p = (t == CONST_ARM);
7853 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7857 if ((inst.instruction & tbit) == 0)
7859 inst.error = _("invalid pseudo operation");
7863 if (inst.reloc.exp.X_op != O_constant
7864 && inst.reloc.exp.X_op != O_symbol
7865 && inst.reloc.exp.X_op != O_big)
7867 inst.error = _("constant expression expected");
7871 if (inst.reloc.exp.X_op == O_constant
7872 || inst.reloc.exp.X_op == O_big)
7874 #if defined BFD_HOST_64_BIT
7879 if (inst.reloc.exp.X_op == O_big)
7881 LITTLENUM_TYPE w[X_PRECISION];
7884 if (inst.reloc.exp.X_add_number == -1)
7886 gen_to_words (w, X_PRECISION, E_PRECISION);
7888 /* FIXME: Should we check words w[2..5] ? */
7893 #if defined BFD_HOST_64_BIT
7895 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
7896 << LITTLENUM_NUMBER_OF_BITS)
7897 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
7898 << LITTLENUM_NUMBER_OF_BITS)
7899 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
7900 << LITTLENUM_NUMBER_OF_BITS)
7901 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
7903 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
7904 | (l[0] & LITTLENUM_MASK);
7908 v = inst.reloc.exp.X_add_number;
7910 if (!inst.operands[i].issingle)
7914 /* This can be encoded only for a low register. */
7915 if ((v & ~0xFF) == 0 && (inst.operands[i].reg < 8))
7917 /* This can be done with a mov(1) instruction. */
7918 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7919 inst.instruction |= v;
7923 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
7924 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
7926 /* Check if on thumb2 it can be done with a mov.w, mvn or
7927 movw instruction. */
7928 unsigned int newimm;
7929 bfd_boolean isNegated;
7931 newimm = encode_thumb32_immediate (v);
7932 if (newimm != (unsigned int) FAIL)
7936 newimm = encode_thumb32_immediate (~v);
7937 if (newimm != (unsigned int) FAIL)
7941 /* The number can be loaded with a mov.w or mvn
7943 if (newimm != (unsigned int) FAIL
7944 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
7946 inst.instruction = (0xf04f0000 /* MOV.W. */
7947 | (inst.operands[i].reg << 8));
7948 /* Change to MOVN. */
7949 inst.instruction |= (isNegated ? 0x200000 : 0);
7950 inst.instruction |= (newimm & 0x800) << 15;
7951 inst.instruction |= (newimm & 0x700) << 4;
7952 inst.instruction |= (newimm & 0x0ff);
7955 /* The number can be loaded with a movw instruction. */
7956 else if ((v & ~0xFFFF) == 0
7957 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
7959 int imm = v & 0xFFFF;
7961 inst.instruction = 0xf2400000; /* MOVW. */
7962 inst.instruction |= (inst.operands[i].reg << 8);
7963 inst.instruction |= (imm & 0xf000) << 4;
7964 inst.instruction |= (imm & 0x0800) << 15;
7965 inst.instruction |= (imm & 0x0700) << 4;
7966 inst.instruction |= (imm & 0x00ff);
7973 int value = encode_arm_immediate (v);
7977 /* This can be done with a mov instruction. */
7978 inst.instruction &= LITERAL_MASK;
7979 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7980 inst.instruction |= value & 0xfff;
7984 value = encode_arm_immediate (~ v);
7987 /* This can be done with a mvn instruction. */
7988 inst.instruction &= LITERAL_MASK;
7989 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7990 inst.instruction |= value & 0xfff;
7994 else if (t == CONST_VEC)
7997 unsigned immbits = 0;
7998 unsigned immlo = inst.operands[1].imm;
7999 unsigned immhi = inst.operands[1].regisimm
8000 ? inst.operands[1].reg
8001 : inst.reloc.exp.X_unsigned
8003 : ((bfd_int64_t)((int) immlo)) >> 32;
8004 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8005 &op, 64, NT_invtype);
8009 neon_invert_size (&immlo, &immhi, 64);
8011 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8012 &op, 64, NT_invtype);
8017 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8023 /* Fill other bits in vmov encoding for both thumb and arm. */
8025 inst.instruction |= (0x7U << 29) | (0xF << 24);
8027 inst.instruction |= (0xFU << 28) | (0x1 << 25);
8028 neon_write_immbits (immbits);
8036 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8037 if (inst.operands[i].issingle
8038 && is_quarter_float (inst.operands[1].imm)
8039 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
8041 inst.operands[1].imm =
8042 neon_qfloat_bits (v);
8043 do_vfp_nsyn_opcode ("fconsts");
8047 /* If our host does not support a 64-bit type then we cannot perform
8048 the following optimization. This mean that there will be a
8049 discrepancy between the output produced by an assembler built for
8050 a 32-bit-only host and the output produced from a 64-bit host, but
8051 this cannot be helped. */
8052 #if defined BFD_HOST_64_BIT
8053 else if (!inst.operands[1].issingle
8054 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
8056 if (is_double_a_single (v)
8057 && is_quarter_float (double_to_single (v)))
8059 inst.operands[1].imm =
8060 neon_qfloat_bits (double_to_single (v));
8061 do_vfp_nsyn_opcode ("fconstd");
8069 if (add_to_lit_pool ((!inst.operands[i].isvec
8070 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8073 inst.operands[1].reg = REG_PC;
8074 inst.operands[1].isreg = 1;
8075 inst.operands[1].preind = 1;
8076 inst.reloc.pc_rel = 1;
8077 inst.reloc.type = (thumb_p
8078 ? BFD_RELOC_ARM_THUMB_OFFSET
8080 ? BFD_RELOC_ARM_HWLITERAL
8081 : BFD_RELOC_ARM_LITERAL));
8085 /* inst.operands[i] was set up by parse_address. Encode it into an
8086 ARM-format instruction. Reject all forms which cannot be encoded
8087 into a coprocessor load/store instruction. If wb_ok is false,
8088 reject use of writeback; if unind_ok is false, reject use of
8089 unindexed addressing. If reloc_override is not 0, use it instead
8090 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8091 (in which case it is preserved). */
8094 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
8096 if (!inst.operands[i].isreg)
8099 if (! inst.operands[0].isvec)
8101 inst.error = _("invalid co-processor operand");
8104 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
8108 inst.instruction |= inst.operands[i].reg << 16;
8110 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8112 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8114 gas_assert (!inst.operands[i].writeback);
8117 inst.error = _("instruction does not support unindexed addressing");
8120 inst.instruction |= inst.operands[i].imm;
8121 inst.instruction |= INDEX_UP;
8125 if (inst.operands[i].preind)
8126 inst.instruction |= PRE_INDEX;
8128 if (inst.operands[i].writeback)
8130 if (inst.operands[i].reg == REG_PC)
8132 inst.error = _("pc may not be used with write-back");
8137 inst.error = _("instruction does not support writeback");
8140 inst.instruction |= WRITE_BACK;
8144 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
8145 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
8146 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
8147 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
8150 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8152 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
8155 /* Prefer + for zero encoded value. */
8156 if (!inst.operands[i].negative)
8157 inst.instruction |= INDEX_UP;
8162 /* Functions for instruction encoding, sorted by sub-architecture.
8163 First some generics; their names are taken from the conventional
8164 bit positions for register arguments in ARM format instructions. */
8174 inst.instruction |= inst.operands[0].reg << 12;
8180 inst.instruction |= inst.operands[0].reg << 12;
8181 inst.instruction |= inst.operands[1].reg;
8187 inst.instruction |= inst.operands[0].reg;
8188 inst.instruction |= inst.operands[1].reg << 16;
8194 inst.instruction |= inst.operands[0].reg << 12;
8195 inst.instruction |= inst.operands[1].reg << 16;
8201 inst.instruction |= inst.operands[0].reg << 16;
8202 inst.instruction |= inst.operands[1].reg << 12;
8208 inst.instruction |= inst.operands[0].reg << 8;
8209 inst.instruction |= inst.operands[1].reg << 16;
8213 check_obsolete (const arm_feature_set *feature, const char *msg)
8215 if (ARM_CPU_IS_ANY (cpu_variant))
8217 as_tsktsk ("%s", msg);
8220 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
8232 unsigned Rn = inst.operands[2].reg;
8233 /* Enforce restrictions on SWP instruction. */
8234 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
8236 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8237 _("Rn must not overlap other operands"));
8239 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8241 if (!check_obsolete (&arm_ext_v8,
8242 _("swp{b} use is obsoleted for ARMv8 and later"))
8243 && warn_on_deprecated
8244 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
8245 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8248 inst.instruction |= inst.operands[0].reg << 12;
8249 inst.instruction |= inst.operands[1].reg;
8250 inst.instruction |= Rn << 16;
8256 inst.instruction |= inst.operands[0].reg << 12;
8257 inst.instruction |= inst.operands[1].reg << 16;
8258 inst.instruction |= inst.operands[2].reg;
8264 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
8265 constraint (((inst.reloc.exp.X_op != O_constant
8266 && inst.reloc.exp.X_op != O_illegal)
8267 || inst.reloc.exp.X_add_number != 0),
8269 inst.instruction |= inst.operands[0].reg;
8270 inst.instruction |= inst.operands[1].reg << 12;
8271 inst.instruction |= inst.operands[2].reg << 16;
8277 inst.instruction |= inst.operands[0].imm;
8283 inst.instruction |= inst.operands[0].reg << 12;
8284 encode_arm_cp_address (1, TRUE, TRUE, 0);
8287 /* ARM instructions, in alphabetical order by function name (except
8288 that wrapper functions appear immediately after the function they
8291 /* This is a pseudo-op of the form "adr rd, label" to be converted
8292 into a relative address of the form "add rd, pc, #label-.-8". */
8297 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
8299 /* Frag hacking will turn this into a sub instruction if the offset turns
8300 out to be negative. */
8301 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8302 inst.reloc.pc_rel = 1;
8303 inst.reloc.exp.X_add_number -= 8;
8306 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8307 into a relative address of the form:
8308 add rd, pc, #low(label-.-8)"
8309 add rd, rd, #high(label-.-8)" */
8314 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
8316 /* Frag hacking will turn this into a sub instruction if the offset turns
8317 out to be negative. */
8318 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
8319 inst.reloc.pc_rel = 1;
8320 inst.size = INSN_SIZE * 2;
8321 inst.reloc.exp.X_add_number -= 8;
8327 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8328 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
8330 if (!inst.operands[1].present)
8331 inst.operands[1].reg = inst.operands[0].reg;
8332 inst.instruction |= inst.operands[0].reg << 12;
8333 inst.instruction |= inst.operands[1].reg << 16;
8334 encode_arm_shifter_operand (2);
8340 if (inst.operands[0].present)
8341 inst.instruction |= inst.operands[0].imm;
8343 inst.instruction |= 0xf;
8349 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8350 constraint (msb > 32, _("bit-field extends past end of register"));
8351 /* The instruction encoding stores the LSB and MSB,
8352 not the LSB and width. */
8353 inst.instruction |= inst.operands[0].reg << 12;
8354 inst.instruction |= inst.operands[1].imm << 7;
8355 inst.instruction |= (msb - 1) << 16;
8363 /* #0 in second position is alternative syntax for bfc, which is
8364 the same instruction but with REG_PC in the Rm field. */
8365 if (!inst.operands[1].isreg)
8366 inst.operands[1].reg = REG_PC;
8368 msb = inst.operands[2].imm + inst.operands[3].imm;
8369 constraint (msb > 32, _("bit-field extends past end of register"));
8370 /* The instruction encoding stores the LSB and MSB,
8371 not the LSB and width. */
8372 inst.instruction |= inst.operands[0].reg << 12;
8373 inst.instruction |= inst.operands[1].reg;
8374 inst.instruction |= inst.operands[2].imm << 7;
8375 inst.instruction |= (msb - 1) << 16;
8381 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8382 _("bit-field extends past end of register"));
8383 inst.instruction |= inst.operands[0].reg << 12;
8384 inst.instruction |= inst.operands[1].reg;
8385 inst.instruction |= inst.operands[2].imm << 7;
8386 inst.instruction |= (inst.operands[3].imm - 1) << 16;
8389 /* ARM V5 breakpoint instruction (argument parse)
8390 BKPT <16 bit unsigned immediate>
8391 Instruction is not conditional.
8392 The bit pattern given in insns[] has the COND_ALWAYS condition,
8393 and it is an error if the caller tried to override that. */
8398 /* Top 12 of 16 bits to bits 19:8. */
8399 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
8401 /* Bottom 4 of 16 bits to bits 3:0. */
8402 inst.instruction |= inst.operands[0].imm & 0xf;
8406 encode_branch (int default_reloc)
8408 if (inst.operands[0].hasreloc)
8410 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
8411 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
8412 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8413 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
8414 ? BFD_RELOC_ARM_PLT32
8415 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
8418 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
8419 inst.reloc.pc_rel = 1;
8426 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8427 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8430 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
8437 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8439 if (inst.cond == COND_ALWAYS)
8440 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
8442 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8446 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
8449 /* ARM V5 branch-link-exchange instruction (argument parse)
8450 BLX <target_addr> ie BLX(1)
8451 BLX{<condition>} <Rm> ie BLX(2)
8452 Unfortunately, there are two different opcodes for this mnemonic.
8453 So, the insns[].value is not used, and the code here zaps values
8454 into inst.instruction.
8455 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8460 if (inst.operands[0].isreg)
8462 /* Arg is a register; the opcode provided by insns[] is correct.
8463 It is not illegal to do "blx pc", just useless. */
8464 if (inst.operands[0].reg == REG_PC)
8465 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8467 inst.instruction |= inst.operands[0].reg;
8471 /* Arg is an address; this instruction cannot be executed
8472 conditionally, and the opcode must be adjusted.
8473 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8474 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8475 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8476 inst.instruction = 0xfa000000;
8477 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
8484 bfd_boolean want_reloc;
8486 if (inst.operands[0].reg == REG_PC)
8487 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8489 inst.instruction |= inst.operands[0].reg;
8490 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8491 it is for ARMv4t or earlier. */
8492 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
8493 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
8497 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
8502 inst.reloc.type = BFD_RELOC_ARM_V4BX;
8506 /* ARM v5TEJ. Jump to Jazelle code. */
8511 if (inst.operands[0].reg == REG_PC)
8512 as_tsktsk (_("use of r15 in bxj is not really useful"));
8514 inst.instruction |= inst.operands[0].reg;
8517 /* Co-processor data operation:
8518 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8519 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8523 inst.instruction |= inst.operands[0].reg << 8;
8524 inst.instruction |= inst.operands[1].imm << 20;
8525 inst.instruction |= inst.operands[2].reg << 12;
8526 inst.instruction |= inst.operands[3].reg << 16;
8527 inst.instruction |= inst.operands[4].reg;
8528 inst.instruction |= inst.operands[5].imm << 5;
8534 inst.instruction |= inst.operands[0].reg << 16;
8535 encode_arm_shifter_operand (1);
8538 /* Transfer between coprocessor and ARM registers.
8539 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8544 No special properties. */
8546 struct deprecated_coproc_regs_s
8553 arm_feature_set deprecated;
8554 arm_feature_set obsoleted;
8555 const char *dep_msg;
8556 const char *obs_msg;
8559 #define DEPR_ACCESS_V8 \
8560 N_("This coprocessor register access is deprecated in ARMv8")
8562 /* Table of all deprecated coprocessor registers. */
8563 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
8565 {15, 0, 7, 10, 5, /* CP15DMB. */
8566 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8567 DEPR_ACCESS_V8, NULL},
8568 {15, 0, 7, 10, 4, /* CP15DSB. */
8569 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8570 DEPR_ACCESS_V8, NULL},
8571 {15, 0, 7, 5, 4, /* CP15ISB. */
8572 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8573 DEPR_ACCESS_V8, NULL},
8574 {14, 6, 1, 0, 0, /* TEEHBR. */
8575 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8576 DEPR_ACCESS_V8, NULL},
8577 {14, 6, 0, 0, 0, /* TEECR. */
8578 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8579 DEPR_ACCESS_V8, NULL},
8582 #undef DEPR_ACCESS_V8
8584 static const size_t deprecated_coproc_reg_count =
8585 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
8593 Rd = inst.operands[2].reg;
8596 if (inst.instruction == 0xee000010
8597 || inst.instruction == 0xfe000010)
8599 reject_bad_reg (Rd);
8602 constraint (Rd == REG_SP, BAD_SP);
8607 if (inst.instruction == 0xe000010)
8608 constraint (Rd == REG_PC, BAD_PC);
8611 for (i = 0; i < deprecated_coproc_reg_count; ++i)
8613 const struct deprecated_coproc_regs_s *r =
8614 deprecated_coproc_regs + i;
8616 if (inst.operands[0].reg == r->cp
8617 && inst.operands[1].imm == r->opc1
8618 && inst.operands[3].reg == r->crn
8619 && inst.operands[4].reg == r->crm
8620 && inst.operands[5].imm == r->opc2)
8622 if (! ARM_CPU_IS_ANY (cpu_variant)
8623 && warn_on_deprecated
8624 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
8625 as_tsktsk ("%s", r->dep_msg);
8629 inst.instruction |= inst.operands[0].reg << 8;
8630 inst.instruction |= inst.operands[1].imm << 21;
8631 inst.instruction |= Rd << 12;
8632 inst.instruction |= inst.operands[3].reg << 16;
8633 inst.instruction |= inst.operands[4].reg;
8634 inst.instruction |= inst.operands[5].imm << 5;
8637 /* Transfer between coprocessor register and pair of ARM registers.
8638 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8643 Two XScale instructions are special cases of these:
8645 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8646 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8648 Result unpredictable if Rd or Rn is R15. */
8655 Rd = inst.operands[2].reg;
8656 Rn = inst.operands[3].reg;
8660 reject_bad_reg (Rd);
8661 reject_bad_reg (Rn);
8665 constraint (Rd == REG_PC, BAD_PC);
8666 constraint (Rn == REG_PC, BAD_PC);
8669 inst.instruction |= inst.operands[0].reg << 8;
8670 inst.instruction |= inst.operands[1].imm << 4;
8671 inst.instruction |= Rd << 12;
8672 inst.instruction |= Rn << 16;
8673 inst.instruction |= inst.operands[4].reg;
8679 inst.instruction |= inst.operands[0].imm << 6;
8680 if (inst.operands[1].present)
8682 inst.instruction |= CPSI_MMOD;
8683 inst.instruction |= inst.operands[1].imm;
8690 inst.instruction |= inst.operands[0].imm;
8696 unsigned Rd, Rn, Rm;
8698 Rd = inst.operands[0].reg;
8699 Rn = (inst.operands[1].present
8700 ? inst.operands[1].reg : Rd);
8701 Rm = inst.operands[2].reg;
8703 constraint ((Rd == REG_PC), BAD_PC);
8704 constraint ((Rn == REG_PC), BAD_PC);
8705 constraint ((Rm == REG_PC), BAD_PC);
8707 inst.instruction |= Rd << 16;
8708 inst.instruction |= Rn << 0;
8709 inst.instruction |= Rm << 8;
8715 /* There is no IT instruction in ARM mode. We
8716 process it to do the validation as if in
8717 thumb mode, just in case the code gets
8718 assembled for thumb using the unified syntax. */
8723 set_it_insn_type (IT_INSN);
8724 now_it.mask = (inst.instruction & 0xf) | 0x10;
8725 now_it.cc = inst.operands[0].imm;
8729 /* If there is only one register in the register list,
8730 then return its register number. Otherwise return -1. */
8732 only_one_reg_in_list (int range)
8734 int i = ffs (range) - 1;
8735 return (i > 15 || range != (1 << i)) ? -1 : i;
8739 encode_ldmstm(int from_push_pop_mnem)
8741 int base_reg = inst.operands[0].reg;
8742 int range = inst.operands[1].imm;
8745 inst.instruction |= base_reg << 16;
8746 inst.instruction |= range;
8748 if (inst.operands[1].writeback)
8749 inst.instruction |= LDM_TYPE_2_OR_3;
8751 if (inst.operands[0].writeback)
8753 inst.instruction |= WRITE_BACK;
8754 /* Check for unpredictable uses of writeback. */
8755 if (inst.instruction & LOAD_BIT)
8757 /* Not allowed in LDM type 2. */
8758 if ((inst.instruction & LDM_TYPE_2_OR_3)
8759 && ((range & (1 << REG_PC)) == 0))
8760 as_warn (_("writeback of base register is UNPREDICTABLE"));
8761 /* Only allowed if base reg not in list for other types. */
8762 else if (range & (1 << base_reg))
8763 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8767 /* Not allowed for type 2. */
8768 if (inst.instruction & LDM_TYPE_2_OR_3)
8769 as_warn (_("writeback of base register is UNPREDICTABLE"));
8770 /* Only allowed if base reg not in list, or first in list. */
8771 else if ((range & (1 << base_reg))
8772 && (range & ((1 << base_reg) - 1)))
8773 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8777 /* If PUSH/POP has only one register, then use the A2 encoding. */
8778 one_reg = only_one_reg_in_list (range);
8779 if (from_push_pop_mnem && one_reg >= 0)
8781 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
8783 inst.instruction &= A_COND_MASK;
8784 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
8785 inst.instruction |= one_reg << 12;
8792 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
8795 /* ARMv5TE load-consecutive (argument parse)
8804 constraint (inst.operands[0].reg % 2 != 0,
8805 _("first transfer register must be even"));
8806 constraint (inst.operands[1].present
8807 && inst.operands[1].reg != inst.operands[0].reg + 1,
8808 _("can only transfer two consecutive registers"));
8809 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8810 constraint (!inst.operands[2].isreg, _("'[' expected"));
8812 if (!inst.operands[1].present)
8813 inst.operands[1].reg = inst.operands[0].reg + 1;
8815 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8816 register and the first register written; we have to diagnose
8817 overlap between the base and the second register written here. */
8819 if (inst.operands[2].reg == inst.operands[1].reg
8820 && (inst.operands[2].writeback || inst.operands[2].postind))
8821 as_warn (_("base register written back, and overlaps "
8822 "second transfer register"));
8824 if (!(inst.instruction & V4_STR_BIT))
8826 /* For an index-register load, the index register must not overlap the
8827 destination (even if not write-back). */
8828 if (inst.operands[2].immisreg
8829 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8830 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8831 as_warn (_("index register overlaps transfer register"));
8833 inst.instruction |= inst.operands[0].reg << 12;
8834 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8840 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8841 || inst.operands[1].postind || inst.operands[1].writeback
8842 || inst.operands[1].immisreg || inst.operands[1].shifted
8843 || inst.operands[1].negative
8844 /* This can arise if the programmer has written
8846 or if they have mistakenly used a register name as the last
8849 It is very difficult to distinguish between these two cases
8850 because "rX" might actually be a label. ie the register
8851 name has been occluded by a symbol of the same name. So we
8852 just generate a general 'bad addressing mode' type error
8853 message and leave it up to the programmer to discover the
8854 true cause and fix their mistake. */
8855 || (inst.operands[1].reg == REG_PC),
8858 constraint (inst.reloc.exp.X_op != O_constant
8859 || inst.reloc.exp.X_add_number != 0,
8860 _("offset must be zero in ARM encoding"));
8862 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8864 inst.instruction |= inst.operands[0].reg << 12;
8865 inst.instruction |= inst.operands[1].reg << 16;
8866 inst.reloc.type = BFD_RELOC_UNUSED;
8872 constraint (inst.operands[0].reg % 2 != 0,
8873 _("even register required"));
8874 constraint (inst.operands[1].present
8875 && inst.operands[1].reg != inst.operands[0].reg + 1,
8876 _("can only load two consecutive registers"));
8877 /* If op 1 were present and equal to PC, this function wouldn't
8878 have been called in the first place. */
8879 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8881 inst.instruction |= inst.operands[0].reg << 12;
8882 inst.instruction |= inst.operands[2].reg << 16;
8885 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8886 which is not a multiple of four is UNPREDICTABLE. */
8888 check_ldr_r15_aligned (void)
8890 constraint (!(inst.operands[1].immisreg)
8891 && (inst.operands[0].reg == REG_PC
8892 && inst.operands[1].reg == REG_PC
8893 && (inst.reloc.exp.X_add_number & 0x3)),
8894 _("ldr to register 15 must be 4-byte alligned"));
8900 inst.instruction |= inst.operands[0].reg << 12;
8901 if (!inst.operands[1].isreg)
8902 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
8904 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8905 check_ldr_r15_aligned ();
8911 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8913 if (inst.operands[1].preind)
8915 constraint (inst.reloc.exp.X_op != O_constant
8916 || inst.reloc.exp.X_add_number != 0,
8917 _("this instruction requires a post-indexed address"));
8919 inst.operands[1].preind = 0;
8920 inst.operands[1].postind = 1;
8921 inst.operands[1].writeback = 1;
8923 inst.instruction |= inst.operands[0].reg << 12;
8924 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8927 /* Halfword and signed-byte load/store operations. */
8932 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8933 inst.instruction |= inst.operands[0].reg << 12;
8934 if (!inst.operands[1].isreg)
8935 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
8937 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8943 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8945 if (inst.operands[1].preind)
8947 constraint (inst.reloc.exp.X_op != O_constant
8948 || inst.reloc.exp.X_add_number != 0,
8949 _("this instruction requires a post-indexed address"));
8951 inst.operands[1].preind = 0;
8952 inst.operands[1].postind = 1;
8953 inst.operands[1].writeback = 1;
8955 inst.instruction |= inst.operands[0].reg << 12;
8956 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8959 /* Co-processor register load/store.
8960 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8964 inst.instruction |= inst.operands[0].reg << 8;
8965 inst.instruction |= inst.operands[1].reg << 12;
8966 encode_arm_cp_address (2, TRUE, TRUE, 0);
8972 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8973 if (inst.operands[0].reg == inst.operands[1].reg
8974 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8975 && !(inst.instruction & 0x00400000))
8976 as_tsktsk (_("Rd and Rm should be different in mla"));
8978 inst.instruction |= inst.operands[0].reg << 16;
8979 inst.instruction |= inst.operands[1].reg;
8980 inst.instruction |= inst.operands[2].reg << 8;
8981 inst.instruction |= inst.operands[3].reg << 12;
8987 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8988 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
8990 inst.instruction |= inst.operands[0].reg << 12;
8991 encode_arm_shifter_operand (1);
8994 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9001 top = (inst.instruction & 0x00400000) != 0;
9002 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
9003 _(":lower16: not allowed this instruction"));
9004 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
9005 _(":upper16: not allowed instruction"));
9006 inst.instruction |= inst.operands[0].reg << 12;
9007 if (inst.reloc.type == BFD_RELOC_UNUSED)
9009 imm = inst.reloc.exp.X_add_number;
9010 /* The value is in two pieces: 0:11, 16:19. */
9011 inst.instruction |= (imm & 0x00000fff);
9012 inst.instruction |= (imm & 0x0000f000) << 4;
9017 do_vfp_nsyn_mrs (void)
9019 if (inst.operands[0].isvec)
9021 if (inst.operands[1].reg != 1)
9022 first_error (_("operand 1 must be FPSCR"));
9023 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9024 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9025 do_vfp_nsyn_opcode ("fmstat");
9027 else if (inst.operands[1].isvec)
9028 do_vfp_nsyn_opcode ("fmrx");
9036 do_vfp_nsyn_msr (void)
9038 if (inst.operands[0].isvec)
9039 do_vfp_nsyn_opcode ("fmxr");
9049 unsigned Rt = inst.operands[0].reg;
9051 if (thumb_mode && Rt == REG_SP)
9053 inst.error = BAD_SP;
9057 /* APSR_ sets isvec. All other refs to PC are illegal. */
9058 if (!inst.operands[0].isvec && Rt == REG_PC)
9060 inst.error = BAD_PC;
9064 /* If we get through parsing the register name, we just insert the number
9065 generated into the instruction without further validation. */
9066 inst.instruction |= (inst.operands[1].reg << 16);
9067 inst.instruction |= (Rt << 12);
9073 unsigned Rt = inst.operands[1].reg;
9076 reject_bad_reg (Rt);
9077 else if (Rt == REG_PC)
9079 inst.error = BAD_PC;
9083 /* If we get through parsing the register name, we just insert the number
9084 generated into the instruction without further validation. */
9085 inst.instruction |= (inst.operands[0].reg << 16);
9086 inst.instruction |= (Rt << 12);
9094 if (do_vfp_nsyn_mrs () == SUCCESS)
9097 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9098 inst.instruction |= inst.operands[0].reg << 12;
9100 if (inst.operands[1].isreg)
9102 br = inst.operands[1].reg;
9103 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
9104 as_bad (_("bad register for mrs"));
9108 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9109 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
9111 _("'APSR', 'CPSR' or 'SPSR' expected"));
9112 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
9115 inst.instruction |= br;
9118 /* Two possible forms:
9119 "{C|S}PSR_<field>, Rm",
9120 "{C|S}PSR_f, #expression". */
9125 if (do_vfp_nsyn_msr () == SUCCESS)
9128 inst.instruction |= inst.operands[0].imm;
9129 if (inst.operands[1].isreg)
9130 inst.instruction |= inst.operands[1].reg;
9133 inst.instruction |= INST_IMMEDIATE;
9134 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
9135 inst.reloc.pc_rel = 0;
9142 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
9144 if (!inst.operands[2].present)
9145 inst.operands[2].reg = inst.operands[0].reg;
9146 inst.instruction |= inst.operands[0].reg << 16;
9147 inst.instruction |= inst.operands[1].reg;
9148 inst.instruction |= inst.operands[2].reg << 8;
9150 if (inst.operands[0].reg == inst.operands[1].reg
9151 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9152 as_tsktsk (_("Rd and Rm should be different in mul"));
9155 /* Long Multiply Parser
9156 UMULL RdLo, RdHi, Rm, Rs
9157 SMULL RdLo, RdHi, Rm, Rs
9158 UMLAL RdLo, RdHi, Rm, Rs
9159 SMLAL RdLo, RdHi, Rm, Rs. */
9164 inst.instruction |= inst.operands[0].reg << 12;
9165 inst.instruction |= inst.operands[1].reg << 16;
9166 inst.instruction |= inst.operands[2].reg;
9167 inst.instruction |= inst.operands[3].reg << 8;
9169 /* rdhi and rdlo must be different. */
9170 if (inst.operands[0].reg == inst.operands[1].reg)
9171 as_tsktsk (_("rdhi and rdlo must be different"));
9173 /* rdhi, rdlo and rm must all be different before armv6. */
9174 if ((inst.operands[0].reg == inst.operands[2].reg
9175 || inst.operands[1].reg == inst.operands[2].reg)
9176 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9177 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9183 if (inst.operands[0].present
9184 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
9186 /* Architectural NOP hints are CPSR sets with no bits selected. */
9187 inst.instruction &= 0xf0000000;
9188 inst.instruction |= 0x0320f000;
9189 if (inst.operands[0].present)
9190 inst.instruction |= inst.operands[0].imm;
9194 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9195 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9196 Condition defaults to COND_ALWAYS.
9197 Error if Rd, Rn or Rm are R15. */
9202 inst.instruction |= inst.operands[0].reg << 12;
9203 inst.instruction |= inst.operands[1].reg << 16;
9204 inst.instruction |= inst.operands[2].reg;
9205 if (inst.operands[3].present)
9206 encode_arm_shift (3);
9209 /* ARM V6 PKHTB (Argument Parse). */
9214 if (!inst.operands[3].present)
9216 /* If the shift specifier is omitted, turn the instruction
9217 into pkhbt rd, rm, rn. */
9218 inst.instruction &= 0xfff00010;
9219 inst.instruction |= inst.operands[0].reg << 12;
9220 inst.instruction |= inst.operands[1].reg;
9221 inst.instruction |= inst.operands[2].reg << 16;
9225 inst.instruction |= inst.operands[0].reg << 12;
9226 inst.instruction |= inst.operands[1].reg << 16;
9227 inst.instruction |= inst.operands[2].reg;
9228 encode_arm_shift (3);
9232 /* ARMv5TE: Preload-Cache
9233 MP Extensions: Preload for write
9237 Syntactically, like LDR with B=1, W=0, L=1. */
9242 constraint (!inst.operands[0].isreg,
9243 _("'[' expected after PLD mnemonic"));
9244 constraint (inst.operands[0].postind,
9245 _("post-indexed expression used in preload instruction"));
9246 constraint (inst.operands[0].writeback,
9247 _("writeback used in preload instruction"));
9248 constraint (!inst.operands[0].preind,
9249 _("unindexed addressing used in preload instruction"));
9250 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9253 /* ARMv7: PLI <addr_mode> */
9257 constraint (!inst.operands[0].isreg,
9258 _("'[' expected after PLI mnemonic"));
9259 constraint (inst.operands[0].postind,
9260 _("post-indexed expression used in preload instruction"));
9261 constraint (inst.operands[0].writeback,
9262 _("writeback used in preload instruction"));
9263 constraint (!inst.operands[0].preind,
9264 _("unindexed addressing used in preload instruction"));
9265 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9266 inst.instruction &= ~PRE_INDEX;
9272 constraint (inst.operands[0].writeback,
9273 _("push/pop do not support {reglist}^"));
9274 inst.operands[1] = inst.operands[0];
9275 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
9276 inst.operands[0].isreg = 1;
9277 inst.operands[0].writeback = 1;
9278 inst.operands[0].reg = REG_SP;
9279 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
9282 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9283 word at the specified address and the following word
9285 Unconditionally executed.
9286 Error if Rn is R15. */
9291 inst.instruction |= inst.operands[0].reg << 16;
9292 if (inst.operands[0].writeback)
9293 inst.instruction |= WRITE_BACK;
9296 /* ARM V6 ssat (argument parse). */
9301 inst.instruction |= inst.operands[0].reg << 12;
9302 inst.instruction |= (inst.operands[1].imm - 1) << 16;
9303 inst.instruction |= inst.operands[2].reg;
9305 if (inst.operands[3].present)
9306 encode_arm_shift (3);
9309 /* ARM V6 usat (argument parse). */
9314 inst.instruction |= inst.operands[0].reg << 12;
9315 inst.instruction |= inst.operands[1].imm << 16;
9316 inst.instruction |= inst.operands[2].reg;
9318 if (inst.operands[3].present)
9319 encode_arm_shift (3);
9322 /* ARM V6 ssat16 (argument parse). */
9327 inst.instruction |= inst.operands[0].reg << 12;
9328 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
9329 inst.instruction |= inst.operands[2].reg;
9335 inst.instruction |= inst.operands[0].reg << 12;
9336 inst.instruction |= inst.operands[1].imm << 16;
9337 inst.instruction |= inst.operands[2].reg;
9340 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9341 preserving the other bits.
9343 setend <endian_specifier>, where <endian_specifier> is either
9349 if (warn_on_deprecated
9350 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
9351 as_tsktsk (_("setend use is deprecated for ARMv8"));
9353 if (inst.operands[0].imm)
9354 inst.instruction |= 0x200;
9360 unsigned int Rm = (inst.operands[1].present
9361 ? inst.operands[1].reg
9362 : inst.operands[0].reg);
9364 inst.instruction |= inst.operands[0].reg << 12;
9365 inst.instruction |= Rm;
9366 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
9368 inst.instruction |= inst.operands[2].reg << 8;
9369 inst.instruction |= SHIFT_BY_REG;
9370 /* PR 12854: Error on extraneous shifts. */
9371 constraint (inst.operands[2].shifted,
9372 _("extraneous shift as part of operand to shift insn"));
9375 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
9381 inst.reloc.type = BFD_RELOC_ARM_SMC;
9382 inst.reloc.pc_rel = 0;
9388 inst.reloc.type = BFD_RELOC_ARM_HVC;
9389 inst.reloc.pc_rel = 0;
9395 inst.reloc.type = BFD_RELOC_ARM_SWI;
9396 inst.reloc.pc_rel = 0;
9402 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
9403 _("selected processor does not support SETPAN instruction"));
9405 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
9411 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
9412 _("selected processor does not support SETPAN instruction"));
9414 inst.instruction |= (inst.operands[0].imm << 3);
9417 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9418 SMLAxy{cond} Rd,Rm,Rs,Rn
9419 SMLAWy{cond} Rd,Rm,Rs,Rn
9420 Error if any register is R15. */
9425 inst.instruction |= inst.operands[0].reg << 16;
9426 inst.instruction |= inst.operands[1].reg;
9427 inst.instruction |= inst.operands[2].reg << 8;
9428 inst.instruction |= inst.operands[3].reg << 12;
9431 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9432 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9433 Error if any register is R15.
9434 Warning if Rdlo == Rdhi. */
9439 inst.instruction |= inst.operands[0].reg << 12;
9440 inst.instruction |= inst.operands[1].reg << 16;
9441 inst.instruction |= inst.operands[2].reg;
9442 inst.instruction |= inst.operands[3].reg << 8;
9444 if (inst.operands[0].reg == inst.operands[1].reg)
9445 as_tsktsk (_("rdhi and rdlo must be different"));
9448 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9449 SMULxy{cond} Rd,Rm,Rs
9450 Error if any register is R15. */
9455 inst.instruction |= inst.operands[0].reg << 16;
9456 inst.instruction |= inst.operands[1].reg;
9457 inst.instruction |= inst.operands[2].reg << 8;
9460 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9461 the same for both ARM and Thumb-2. */
9468 if (inst.operands[0].present)
9470 reg = inst.operands[0].reg;
9471 constraint (reg != REG_SP, _("SRS base register must be r13"));
9476 inst.instruction |= reg << 16;
9477 inst.instruction |= inst.operands[1].imm;
9478 if (inst.operands[0].writeback || inst.operands[1].writeback)
9479 inst.instruction |= WRITE_BACK;
9482 /* ARM V6 strex (argument parse). */
9487 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9488 || inst.operands[2].postind || inst.operands[2].writeback
9489 || inst.operands[2].immisreg || inst.operands[2].shifted
9490 || inst.operands[2].negative
9491 /* See comment in do_ldrex(). */
9492 || (inst.operands[2].reg == REG_PC),
9495 constraint (inst.operands[0].reg == inst.operands[1].reg
9496 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9498 constraint (inst.reloc.exp.X_op != O_constant
9499 || inst.reloc.exp.X_add_number != 0,
9500 _("offset must be zero in ARM encoding"));
9502 inst.instruction |= inst.operands[0].reg << 12;
9503 inst.instruction |= inst.operands[1].reg;
9504 inst.instruction |= inst.operands[2].reg << 16;
9505 inst.reloc.type = BFD_RELOC_UNUSED;
9511 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9512 || inst.operands[2].postind || inst.operands[2].writeback
9513 || inst.operands[2].immisreg || inst.operands[2].shifted
9514 || inst.operands[2].negative,
9517 constraint (inst.operands[0].reg == inst.operands[1].reg
9518 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9526 constraint (inst.operands[1].reg % 2 != 0,
9527 _("even register required"));
9528 constraint (inst.operands[2].present
9529 && inst.operands[2].reg != inst.operands[1].reg + 1,
9530 _("can only store two consecutive registers"));
9531 /* If op 2 were present and equal to PC, this function wouldn't
9532 have been called in the first place. */
9533 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
9535 constraint (inst.operands[0].reg == inst.operands[1].reg
9536 || inst.operands[0].reg == inst.operands[1].reg + 1
9537 || inst.operands[0].reg == inst.operands[3].reg,
9540 inst.instruction |= inst.operands[0].reg << 12;
9541 inst.instruction |= inst.operands[1].reg;
9542 inst.instruction |= inst.operands[3].reg << 16;
9549 constraint (inst.operands[0].reg == inst.operands[1].reg
9550 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9558 constraint (inst.operands[0].reg == inst.operands[1].reg
9559 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9564 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9565 extends it to 32-bits, and adds the result to a value in another
9566 register. You can specify a rotation by 0, 8, 16, or 24 bits
9567 before extracting the 16-bit value.
9568 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9569 Condition defaults to COND_ALWAYS.
9570 Error if any register uses R15. */
9575 inst.instruction |= inst.operands[0].reg << 12;
9576 inst.instruction |= inst.operands[1].reg << 16;
9577 inst.instruction |= inst.operands[2].reg;
9578 inst.instruction |= inst.operands[3].imm << 10;
9583 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9584 Condition defaults to COND_ALWAYS.
9585 Error if any register uses R15. */
9590 inst.instruction |= inst.operands[0].reg << 12;
9591 inst.instruction |= inst.operands[1].reg;
9592 inst.instruction |= inst.operands[2].imm << 10;
9595 /* VFP instructions. In a logical order: SP variant first, monad
9596 before dyad, arithmetic then move then load/store. */
9599 do_vfp_sp_monadic (void)
9601 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9602 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
9606 do_vfp_sp_dyadic (void)
9608 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9609 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
9610 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
9614 do_vfp_sp_compare_z (void)
9616 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9620 do_vfp_dp_sp_cvt (void)
9622 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9623 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
9627 do_vfp_sp_dp_cvt (void)
9629 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9630 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
9634 do_vfp_reg_from_sp (void)
9636 inst.instruction |= inst.operands[0].reg << 12;
9637 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
9641 do_vfp_reg2_from_sp2 (void)
9643 constraint (inst.operands[2].imm != 2,
9644 _("only two consecutive VFP SP registers allowed here"));
9645 inst.instruction |= inst.operands[0].reg << 12;
9646 inst.instruction |= inst.operands[1].reg << 16;
9647 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
9651 do_vfp_sp_from_reg (void)
9653 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
9654 inst.instruction |= inst.operands[1].reg << 12;
9658 do_vfp_sp2_from_reg2 (void)
9660 constraint (inst.operands[0].imm != 2,
9661 _("only two consecutive VFP SP registers allowed here"));
9662 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
9663 inst.instruction |= inst.operands[1].reg << 12;
9664 inst.instruction |= inst.operands[2].reg << 16;
9668 do_vfp_sp_ldst (void)
9670 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9671 encode_arm_cp_address (1, FALSE, TRUE, 0);
9675 do_vfp_dp_ldst (void)
9677 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9678 encode_arm_cp_address (1, FALSE, TRUE, 0);
9683 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
9685 if (inst.operands[0].writeback)
9686 inst.instruction |= WRITE_BACK;
9688 constraint (ldstm_type != VFP_LDSTMIA,
9689 _("this addressing mode requires base-register writeback"));
9690 inst.instruction |= inst.operands[0].reg << 16;
9691 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
9692 inst.instruction |= inst.operands[1].imm;
9696 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
9700 if (inst.operands[0].writeback)
9701 inst.instruction |= WRITE_BACK;
9703 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
9704 _("this addressing mode requires base-register writeback"));
9706 inst.instruction |= inst.operands[0].reg << 16;
9707 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9709 count = inst.operands[1].imm << 1;
9710 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
9713 inst.instruction |= count;
9717 do_vfp_sp_ldstmia (void)
9719 vfp_sp_ldstm (VFP_LDSTMIA);
9723 do_vfp_sp_ldstmdb (void)
9725 vfp_sp_ldstm (VFP_LDSTMDB);
9729 do_vfp_dp_ldstmia (void)
9731 vfp_dp_ldstm (VFP_LDSTMIA);
9735 do_vfp_dp_ldstmdb (void)
9737 vfp_dp_ldstm (VFP_LDSTMDB);
9741 do_vfp_xp_ldstmia (void)
9743 vfp_dp_ldstm (VFP_LDSTMIAX);
9747 do_vfp_xp_ldstmdb (void)
9749 vfp_dp_ldstm (VFP_LDSTMDBX);
9753 do_vfp_dp_rd_rm (void)
9755 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9756 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
9760 do_vfp_dp_rn_rd (void)
9762 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
9763 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9767 do_vfp_dp_rd_rn (void)
9769 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9770 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9774 do_vfp_dp_rd_rn_rm (void)
9776 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9777 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9778 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
9784 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9788 do_vfp_dp_rm_rd_rn (void)
9790 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
9791 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9792 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
9795 /* VFPv3 instructions. */
9797 do_vfp_sp_const (void)
9799 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9800 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9801 inst.instruction |= (inst.operands[1].imm & 0x0f);
9805 do_vfp_dp_const (void)
9807 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9808 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9809 inst.instruction |= (inst.operands[1].imm & 0x0f);
9813 vfp_conv (int srcsize)
9815 int immbits = srcsize - inst.operands[1].imm;
9817 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9819 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9820 i.e. immbits must be in range 0 - 16. */
9821 inst.error = _("immediate value out of range, expected range [0, 16]");
9824 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9826 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9827 i.e. immbits must be in range 0 - 31. */
9828 inst.error = _("immediate value out of range, expected range [1, 32]");
9832 inst.instruction |= (immbits & 1) << 5;
9833 inst.instruction |= (immbits >> 1);
9837 do_vfp_sp_conv_16 (void)
9839 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9844 do_vfp_dp_conv_16 (void)
9846 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9851 do_vfp_sp_conv_32 (void)
9853 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9858 do_vfp_dp_conv_32 (void)
9860 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9864 /* FPA instructions. Also in a logical order. */
9869 inst.instruction |= inst.operands[0].reg << 16;
9870 inst.instruction |= inst.operands[1].reg;
9874 do_fpa_ldmstm (void)
9876 inst.instruction |= inst.operands[0].reg << 12;
9877 switch (inst.operands[1].imm)
9879 case 1: inst.instruction |= CP_T_X; break;
9880 case 2: inst.instruction |= CP_T_Y; break;
9881 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9886 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9888 /* The instruction specified "ea" or "fd", so we can only accept
9889 [Rn]{!}. The instruction does not really support stacking or
9890 unstacking, so we have to emulate these by setting appropriate
9891 bits and offsets. */
9892 constraint (inst.reloc.exp.X_op != O_constant
9893 || inst.reloc.exp.X_add_number != 0,
9894 _("this instruction does not support indexing"));
9896 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9897 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9899 if (!(inst.instruction & INDEX_UP))
9900 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9902 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9904 inst.operands[2].preind = 0;
9905 inst.operands[2].postind = 1;
9909 encode_arm_cp_address (2, TRUE, TRUE, 0);
9912 /* iWMMXt instructions: strictly in alphabetical order. */
9915 do_iwmmxt_tandorc (void)
9917 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9921 do_iwmmxt_textrc (void)
9923 inst.instruction |= inst.operands[0].reg << 12;
9924 inst.instruction |= inst.operands[1].imm;
9928 do_iwmmxt_textrm (void)
9930 inst.instruction |= inst.operands[0].reg << 12;
9931 inst.instruction |= inst.operands[1].reg << 16;
9932 inst.instruction |= inst.operands[2].imm;
9936 do_iwmmxt_tinsr (void)
9938 inst.instruction |= inst.operands[0].reg << 16;
9939 inst.instruction |= inst.operands[1].reg << 12;
9940 inst.instruction |= inst.operands[2].imm;
9944 do_iwmmxt_tmia (void)
9946 inst.instruction |= inst.operands[0].reg << 5;
9947 inst.instruction |= inst.operands[1].reg;
9948 inst.instruction |= inst.operands[2].reg << 12;
9952 do_iwmmxt_waligni (void)
9954 inst.instruction |= inst.operands[0].reg << 12;
9955 inst.instruction |= inst.operands[1].reg << 16;
9956 inst.instruction |= inst.operands[2].reg;
9957 inst.instruction |= inst.operands[3].imm << 20;
9961 do_iwmmxt_wmerge (void)
9963 inst.instruction |= inst.operands[0].reg << 12;
9964 inst.instruction |= inst.operands[1].reg << 16;
9965 inst.instruction |= inst.operands[2].reg;
9966 inst.instruction |= inst.operands[3].imm << 21;
9970 do_iwmmxt_wmov (void)
9972 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9973 inst.instruction |= inst.operands[0].reg << 12;
9974 inst.instruction |= inst.operands[1].reg << 16;
9975 inst.instruction |= inst.operands[1].reg;
9979 do_iwmmxt_wldstbh (void)
9982 inst.instruction |= inst.operands[0].reg << 12;
9984 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9986 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9987 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9991 do_iwmmxt_wldstw (void)
9993 /* RIWR_RIWC clears .isreg for a control register. */
9994 if (!inst.operands[0].isreg)
9996 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9997 inst.instruction |= 0xf0000000;
10000 inst.instruction |= inst.operands[0].reg << 12;
10001 encode_arm_cp_address (1, TRUE, TRUE, 0);
10005 do_iwmmxt_wldstd (void)
10007 inst.instruction |= inst.operands[0].reg << 12;
10008 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
10009 && inst.operands[1].immisreg)
10011 inst.instruction &= ~0x1a000ff;
10012 inst.instruction |= (0xfU << 28);
10013 if (inst.operands[1].preind)
10014 inst.instruction |= PRE_INDEX;
10015 if (!inst.operands[1].negative)
10016 inst.instruction |= INDEX_UP;
10017 if (inst.operands[1].writeback)
10018 inst.instruction |= WRITE_BACK;
10019 inst.instruction |= inst.operands[1].reg << 16;
10020 inst.instruction |= inst.reloc.exp.X_add_number << 4;
10021 inst.instruction |= inst.operands[1].imm;
10024 encode_arm_cp_address (1, TRUE, FALSE, 0);
10028 do_iwmmxt_wshufh (void)
10030 inst.instruction |= inst.operands[0].reg << 12;
10031 inst.instruction |= inst.operands[1].reg << 16;
10032 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
10033 inst.instruction |= (inst.operands[2].imm & 0x0f);
10037 do_iwmmxt_wzero (void)
10039 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10040 inst.instruction |= inst.operands[0].reg;
10041 inst.instruction |= inst.operands[0].reg << 12;
10042 inst.instruction |= inst.operands[0].reg << 16;
10046 do_iwmmxt_wrwrwr_or_imm5 (void)
10048 if (inst.operands[2].isreg)
10051 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
10052 _("immediate operand requires iWMMXt2"));
10054 if (inst.operands[2].imm == 0)
10056 switch ((inst.instruction >> 20) & 0xf)
10062 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10063 inst.operands[2].imm = 16;
10064 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
10070 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10071 inst.operands[2].imm = 32;
10072 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
10079 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10081 wrn = (inst.instruction >> 16) & 0xf;
10082 inst.instruction &= 0xff0fff0f;
10083 inst.instruction |= wrn;
10084 /* Bail out here; the instruction is now assembled. */
10089 /* Map 32 -> 0, etc. */
10090 inst.operands[2].imm &= 0x1f;
10091 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
10095 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10096 operations first, then control, shift, and load/store. */
10098 /* Insns like "foo X,Y,Z". */
10101 do_mav_triple (void)
10103 inst.instruction |= inst.operands[0].reg << 16;
10104 inst.instruction |= inst.operands[1].reg;
10105 inst.instruction |= inst.operands[2].reg << 12;
10108 /* Insns like "foo W,X,Y,Z".
10109 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10114 inst.instruction |= inst.operands[0].reg << 5;
10115 inst.instruction |= inst.operands[1].reg << 12;
10116 inst.instruction |= inst.operands[2].reg << 16;
10117 inst.instruction |= inst.operands[3].reg;
10120 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10122 do_mav_dspsc (void)
10124 inst.instruction |= inst.operands[1].reg << 12;
10127 /* Maverick shift immediate instructions.
10128 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10129 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10132 do_mav_shift (void)
10134 int imm = inst.operands[2].imm;
10136 inst.instruction |= inst.operands[0].reg << 12;
10137 inst.instruction |= inst.operands[1].reg << 16;
10139 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10140 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10141 Bit 4 should be 0. */
10142 imm = (imm & 0xf) | ((imm & 0x70) << 1);
10144 inst.instruction |= imm;
10147 /* XScale instructions. Also sorted arithmetic before move. */
10149 /* Xscale multiply-accumulate (argument parse)
10152 MIAxycc acc0,Rm,Rs. */
10157 inst.instruction |= inst.operands[1].reg;
10158 inst.instruction |= inst.operands[2].reg << 12;
10161 /* Xscale move-accumulator-register (argument parse)
10163 MARcc acc0,RdLo,RdHi. */
10168 inst.instruction |= inst.operands[1].reg << 12;
10169 inst.instruction |= inst.operands[2].reg << 16;
10172 /* Xscale move-register-accumulator (argument parse)
10174 MRAcc RdLo,RdHi,acc0. */
10179 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
10180 inst.instruction |= inst.operands[0].reg << 12;
10181 inst.instruction |= inst.operands[1].reg << 16;
10184 /* Encoding functions relevant only to Thumb. */
10186 /* inst.operands[i] is a shifted-register operand; encode
10187 it into inst.instruction in the format used by Thumb32. */
10190 encode_thumb32_shifted_operand (int i)
10192 unsigned int value = inst.reloc.exp.X_add_number;
10193 unsigned int shift = inst.operands[i].shift_kind;
10195 constraint (inst.operands[i].immisreg,
10196 _("shift by register not allowed in thumb mode"));
10197 inst.instruction |= inst.operands[i].reg;
10198 if (shift == SHIFT_RRX)
10199 inst.instruction |= SHIFT_ROR << 4;
10202 constraint (inst.reloc.exp.X_op != O_constant,
10203 _("expression too complex"));
10205 constraint (value > 32
10206 || (value == 32 && (shift == SHIFT_LSL
10207 || shift == SHIFT_ROR)),
10208 _("shift expression is too large"));
10212 else if (value == 32)
10215 inst.instruction |= shift << 4;
10216 inst.instruction |= (value & 0x1c) << 10;
10217 inst.instruction |= (value & 0x03) << 6;
10222 /* inst.operands[i] was set up by parse_address. Encode it into a
10223 Thumb32 format load or store instruction. Reject forms that cannot
10224 be used with such instructions. If is_t is true, reject forms that
10225 cannot be used with a T instruction; if is_d is true, reject forms
10226 that cannot be used with a D instruction. If it is a store insn,
10227 reject PC in Rn. */
10230 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
10232 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
10234 constraint (!inst.operands[i].isreg,
10235 _("Instruction does not support =N addresses"));
10237 inst.instruction |= inst.operands[i].reg << 16;
10238 if (inst.operands[i].immisreg)
10240 constraint (is_pc, BAD_PC_ADDRESSING);
10241 constraint (is_t || is_d, _("cannot use register index with this instruction"));
10242 constraint (inst.operands[i].negative,
10243 _("Thumb does not support negative register indexing"));
10244 constraint (inst.operands[i].postind,
10245 _("Thumb does not support register post-indexing"));
10246 constraint (inst.operands[i].writeback,
10247 _("Thumb does not support register indexing with writeback"));
10248 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
10249 _("Thumb supports only LSL in shifted register indexing"));
10251 inst.instruction |= inst.operands[i].imm;
10252 if (inst.operands[i].shifted)
10254 constraint (inst.reloc.exp.X_op != O_constant,
10255 _("expression too complex"));
10256 constraint (inst.reloc.exp.X_add_number < 0
10257 || inst.reloc.exp.X_add_number > 3,
10258 _("shift out of range"));
10259 inst.instruction |= inst.reloc.exp.X_add_number << 4;
10261 inst.reloc.type = BFD_RELOC_UNUSED;
10263 else if (inst.operands[i].preind)
10265 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
10266 constraint (is_t && inst.operands[i].writeback,
10267 _("cannot use writeback with this instruction"));
10268 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
10269 BAD_PC_ADDRESSING);
10273 inst.instruction |= 0x01000000;
10274 if (inst.operands[i].writeback)
10275 inst.instruction |= 0x00200000;
10279 inst.instruction |= 0x00000c00;
10280 if (inst.operands[i].writeback)
10281 inst.instruction |= 0x00000100;
10283 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10285 else if (inst.operands[i].postind)
10287 gas_assert (inst.operands[i].writeback);
10288 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
10289 constraint (is_t, _("cannot use post-indexing with this instruction"));
10292 inst.instruction |= 0x00200000;
10294 inst.instruction |= 0x00000900;
10295 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10297 else /* unindexed - only for coprocessor */
10298 inst.error = _("instruction does not accept unindexed addressing");
10301 /* Table of Thumb instructions which exist in both 16- and 32-bit
10302 encodings (the latter only in post-V6T2 cores). The index is the
10303 value used in the insns table below. When there is more than one
10304 possible 16-bit encoding for the instruction, this table always
10306 Also contains several pseudo-instructions used during relaxation. */
10307 #define T16_32_TAB \
10308 X(_adc, 4140, eb400000), \
10309 X(_adcs, 4140, eb500000), \
10310 X(_add, 1c00, eb000000), \
10311 X(_adds, 1c00, eb100000), \
10312 X(_addi, 0000, f1000000), \
10313 X(_addis, 0000, f1100000), \
10314 X(_add_pc,000f, f20f0000), \
10315 X(_add_sp,000d, f10d0000), \
10316 X(_adr, 000f, f20f0000), \
10317 X(_and, 4000, ea000000), \
10318 X(_ands, 4000, ea100000), \
10319 X(_asr, 1000, fa40f000), \
10320 X(_asrs, 1000, fa50f000), \
10321 X(_b, e000, f000b000), \
10322 X(_bcond, d000, f0008000), \
10323 X(_bic, 4380, ea200000), \
10324 X(_bics, 4380, ea300000), \
10325 X(_cmn, 42c0, eb100f00), \
10326 X(_cmp, 2800, ebb00f00), \
10327 X(_cpsie, b660, f3af8400), \
10328 X(_cpsid, b670, f3af8600), \
10329 X(_cpy, 4600, ea4f0000), \
10330 X(_dec_sp,80dd, f1ad0d00), \
10331 X(_eor, 4040, ea800000), \
10332 X(_eors, 4040, ea900000), \
10333 X(_inc_sp,00dd, f10d0d00), \
10334 X(_ldmia, c800, e8900000), \
10335 X(_ldr, 6800, f8500000), \
10336 X(_ldrb, 7800, f8100000), \
10337 X(_ldrh, 8800, f8300000), \
10338 X(_ldrsb, 5600, f9100000), \
10339 X(_ldrsh, 5e00, f9300000), \
10340 X(_ldr_pc,4800, f85f0000), \
10341 X(_ldr_pc2,4800, f85f0000), \
10342 X(_ldr_sp,9800, f85d0000), \
10343 X(_lsl, 0000, fa00f000), \
10344 X(_lsls, 0000, fa10f000), \
10345 X(_lsr, 0800, fa20f000), \
10346 X(_lsrs, 0800, fa30f000), \
10347 X(_mov, 2000, ea4f0000), \
10348 X(_movs, 2000, ea5f0000), \
10349 X(_mul, 4340, fb00f000), \
10350 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10351 X(_mvn, 43c0, ea6f0000), \
10352 X(_mvns, 43c0, ea7f0000), \
10353 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10354 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10355 X(_orr, 4300, ea400000), \
10356 X(_orrs, 4300, ea500000), \
10357 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10358 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10359 X(_rev, ba00, fa90f080), \
10360 X(_rev16, ba40, fa90f090), \
10361 X(_revsh, bac0, fa90f0b0), \
10362 X(_ror, 41c0, fa60f000), \
10363 X(_rors, 41c0, fa70f000), \
10364 X(_sbc, 4180, eb600000), \
10365 X(_sbcs, 4180, eb700000), \
10366 X(_stmia, c000, e8800000), \
10367 X(_str, 6000, f8400000), \
10368 X(_strb, 7000, f8000000), \
10369 X(_strh, 8000, f8200000), \
10370 X(_str_sp,9000, f84d0000), \
10371 X(_sub, 1e00, eba00000), \
10372 X(_subs, 1e00, ebb00000), \
10373 X(_subi, 8000, f1a00000), \
10374 X(_subis, 8000, f1b00000), \
10375 X(_sxtb, b240, fa4ff080), \
10376 X(_sxth, b200, fa0ff080), \
10377 X(_tst, 4200, ea100f00), \
10378 X(_uxtb, b2c0, fa5ff080), \
10379 X(_uxth, b280, fa1ff080), \
10380 X(_nop, bf00, f3af8000), \
10381 X(_yield, bf10, f3af8001), \
10382 X(_wfe, bf20, f3af8002), \
10383 X(_wfi, bf30, f3af8003), \
10384 X(_sev, bf40, f3af8004), \
10385 X(_sevl, bf50, f3af8005), \
10386 X(_udf, de00, f7f0a000)
10388 /* To catch errors in encoding functions, the codes are all offset by
10389 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10390 as 16-bit instructions. */
10391 #define X(a,b,c) T_MNEM##a
10392 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
10395 #define X(a,b,c) 0x##b
10396 static const unsigned short thumb_op16[] = { T16_32_TAB };
10397 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10400 #define X(a,b,c) 0x##c
10401 static const unsigned int thumb_op32[] = { T16_32_TAB };
10402 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10403 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10407 /* Thumb instruction encoders, in alphabetical order. */
10409 /* ADDW or SUBW. */
10412 do_t_add_sub_w (void)
10416 Rd = inst.operands[0].reg;
10417 Rn = inst.operands[1].reg;
10419 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10420 is the SP-{plus,minus}-immediate form of the instruction. */
10422 constraint (Rd == REG_PC, BAD_PC);
10424 reject_bad_reg (Rd);
10426 inst.instruction |= (Rn << 16) | (Rd << 8);
10427 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10430 /* Parse an add or subtract instruction. We get here with inst.instruction
10431 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10434 do_t_add_sub (void)
10438 Rd = inst.operands[0].reg;
10439 Rs = (inst.operands[1].present
10440 ? inst.operands[1].reg /* Rd, Rs, foo */
10441 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10444 set_it_insn_type_last ();
10446 if (unified_syntax)
10449 bfd_boolean narrow;
10452 flags = (inst.instruction == T_MNEM_adds
10453 || inst.instruction == T_MNEM_subs);
10455 narrow = !in_it_block ();
10457 narrow = in_it_block ();
10458 if (!inst.operands[2].isreg)
10462 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10464 add = (inst.instruction == T_MNEM_add
10465 || inst.instruction == T_MNEM_adds);
10467 if (inst.size_req != 4)
10469 /* Attempt to use a narrow opcode, with relaxation if
10471 if (Rd == REG_SP && Rs == REG_SP && !flags)
10472 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
10473 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
10474 opcode = T_MNEM_add_sp;
10475 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
10476 opcode = T_MNEM_add_pc;
10477 else if (Rd <= 7 && Rs <= 7 && narrow)
10480 opcode = add ? T_MNEM_addis : T_MNEM_subis;
10482 opcode = add ? T_MNEM_addi : T_MNEM_subi;
10486 inst.instruction = THUMB_OP16(opcode);
10487 inst.instruction |= (Rd << 4) | Rs;
10488 if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10489 || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
10491 if (inst.size_req == 2)
10492 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10494 inst.relax = opcode;
10498 constraint (inst.size_req == 2, BAD_HIREG);
10500 if (inst.size_req == 4
10501 || (inst.size_req != 2 && !opcode))
10503 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10504 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
10505 THUMB1_RELOC_ONLY);
10508 constraint (add, BAD_PC);
10509 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
10510 _("only SUBS PC, LR, #const allowed"));
10511 constraint (inst.reloc.exp.X_op != O_constant,
10512 _("expression too complex"));
10513 constraint (inst.reloc.exp.X_add_number < 0
10514 || inst.reloc.exp.X_add_number > 0xff,
10515 _("immediate value out of range"));
10516 inst.instruction = T2_SUBS_PC_LR
10517 | inst.reloc.exp.X_add_number;
10518 inst.reloc.type = BFD_RELOC_UNUSED;
10521 else if (Rs == REG_PC)
10523 /* Always use addw/subw. */
10524 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
10525 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10529 inst.instruction = THUMB_OP32 (inst.instruction);
10530 inst.instruction = (inst.instruction & 0xe1ffffff)
10533 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10535 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
10537 inst.instruction |= Rd << 8;
10538 inst.instruction |= Rs << 16;
10543 unsigned int value = inst.reloc.exp.X_add_number;
10544 unsigned int shift = inst.operands[2].shift_kind;
10546 Rn = inst.operands[2].reg;
10547 /* See if we can do this with a 16-bit instruction. */
10548 if (!inst.operands[2].shifted && inst.size_req != 4)
10550 if (Rd > 7 || Rs > 7 || Rn > 7)
10555 inst.instruction = ((inst.instruction == T_MNEM_adds
10556 || inst.instruction == T_MNEM_add)
10558 : T_OPCODE_SUB_R3);
10559 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
10563 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
10565 /* Thumb-1 cores (except v6-M) require at least one high
10566 register in a narrow non flag setting add. */
10567 if (Rd > 7 || Rn > 7
10568 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
10569 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
10576 inst.instruction = T_OPCODE_ADD_HI;
10577 inst.instruction |= (Rd & 8) << 4;
10578 inst.instruction |= (Rd & 7);
10579 inst.instruction |= Rn << 3;
10585 constraint (Rd == REG_PC, BAD_PC);
10586 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10587 constraint (Rs == REG_PC, BAD_PC);
10588 reject_bad_reg (Rn);
10590 /* If we get here, it can't be done in 16 bits. */
10591 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
10592 _("shift must be constant"));
10593 inst.instruction = THUMB_OP32 (inst.instruction);
10594 inst.instruction |= Rd << 8;
10595 inst.instruction |= Rs << 16;
10596 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
10597 _("shift value over 3 not allowed in thumb mode"));
10598 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
10599 _("only LSL shift allowed in thumb mode"));
10600 encode_thumb32_shifted_operand (2);
10605 constraint (inst.instruction == T_MNEM_adds
10606 || inst.instruction == T_MNEM_subs,
10609 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
10611 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
10612 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
10615 inst.instruction = (inst.instruction == T_MNEM_add
10616 ? 0x0000 : 0x8000);
10617 inst.instruction |= (Rd << 4) | Rs;
10618 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10622 Rn = inst.operands[2].reg;
10623 constraint (inst.operands[2].shifted, _("unshifted register required"));
10625 /* We now have Rd, Rs, and Rn set to registers. */
10626 if (Rd > 7 || Rs > 7 || Rn > 7)
10628 /* Can't do this for SUB. */
10629 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
10630 inst.instruction = T_OPCODE_ADD_HI;
10631 inst.instruction |= (Rd & 8) << 4;
10632 inst.instruction |= (Rd & 7);
10634 inst.instruction |= Rn << 3;
10636 inst.instruction |= Rs << 3;
10638 constraint (1, _("dest must overlap one source register"));
10642 inst.instruction = (inst.instruction == T_MNEM_add
10643 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
10644 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
10654 Rd = inst.operands[0].reg;
10655 reject_bad_reg (Rd);
10657 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
10659 /* Defer to section relaxation. */
10660 inst.relax = inst.instruction;
10661 inst.instruction = THUMB_OP16 (inst.instruction);
10662 inst.instruction |= Rd << 4;
10664 else if (unified_syntax && inst.size_req != 2)
10666 /* Generate a 32-bit opcode. */
10667 inst.instruction = THUMB_OP32 (inst.instruction);
10668 inst.instruction |= Rd << 8;
10669 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
10670 inst.reloc.pc_rel = 1;
10674 /* Generate a 16-bit opcode. */
10675 inst.instruction = THUMB_OP16 (inst.instruction);
10676 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10677 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
10678 inst.reloc.pc_rel = 1;
10680 inst.instruction |= Rd << 4;
10684 /* Arithmetic instructions for which there is just one 16-bit
10685 instruction encoding, and it allows only two low registers.
10686 For maximal compatibility with ARM syntax, we allow three register
10687 operands even when Thumb-32 instructions are not available, as long
10688 as the first two are identical. For instance, both "sbc r0,r1" and
10689 "sbc r0,r0,r1" are allowed. */
10695 Rd = inst.operands[0].reg;
10696 Rs = (inst.operands[1].present
10697 ? inst.operands[1].reg /* Rd, Rs, foo */
10698 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10699 Rn = inst.operands[2].reg;
10701 reject_bad_reg (Rd);
10702 reject_bad_reg (Rs);
10703 if (inst.operands[2].isreg)
10704 reject_bad_reg (Rn);
10706 if (unified_syntax)
10708 if (!inst.operands[2].isreg)
10710 /* For an immediate, we always generate a 32-bit opcode;
10711 section relaxation will shrink it later if possible. */
10712 inst.instruction = THUMB_OP32 (inst.instruction);
10713 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10714 inst.instruction |= Rd << 8;
10715 inst.instruction |= Rs << 16;
10716 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10720 bfd_boolean narrow;
10722 /* See if we can do this with a 16-bit instruction. */
10723 if (THUMB_SETS_FLAGS (inst.instruction))
10724 narrow = !in_it_block ();
10726 narrow = in_it_block ();
10728 if (Rd > 7 || Rn > 7 || Rs > 7)
10730 if (inst.operands[2].shifted)
10732 if (inst.size_req == 4)
10738 inst.instruction = THUMB_OP16 (inst.instruction);
10739 inst.instruction |= Rd;
10740 inst.instruction |= Rn << 3;
10744 /* If we get here, it can't be done in 16 bits. */
10745 constraint (inst.operands[2].shifted
10746 && inst.operands[2].immisreg,
10747 _("shift must be constant"));
10748 inst.instruction = THUMB_OP32 (inst.instruction);
10749 inst.instruction |= Rd << 8;
10750 inst.instruction |= Rs << 16;
10751 encode_thumb32_shifted_operand (2);
10756 /* On its face this is a lie - the instruction does set the
10757 flags. However, the only supported mnemonic in this mode
10758 says it doesn't. */
10759 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10761 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10762 _("unshifted register required"));
10763 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10764 constraint (Rd != Rs,
10765 _("dest and source1 must be the same register"));
10767 inst.instruction = THUMB_OP16 (inst.instruction);
10768 inst.instruction |= Rd;
10769 inst.instruction |= Rn << 3;
10773 /* Similarly, but for instructions where the arithmetic operation is
10774 commutative, so we can allow either of them to be different from
10775 the destination operand in a 16-bit instruction. For instance, all
10776 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10783 Rd = inst.operands[0].reg;
10784 Rs = (inst.operands[1].present
10785 ? inst.operands[1].reg /* Rd, Rs, foo */
10786 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10787 Rn = inst.operands[2].reg;
10789 reject_bad_reg (Rd);
10790 reject_bad_reg (Rs);
10791 if (inst.operands[2].isreg)
10792 reject_bad_reg (Rn);
10794 if (unified_syntax)
10796 if (!inst.operands[2].isreg)
10798 /* For an immediate, we always generate a 32-bit opcode;
10799 section relaxation will shrink it later if possible. */
10800 inst.instruction = THUMB_OP32 (inst.instruction);
10801 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10802 inst.instruction |= Rd << 8;
10803 inst.instruction |= Rs << 16;
10804 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10808 bfd_boolean narrow;
10810 /* See if we can do this with a 16-bit instruction. */
10811 if (THUMB_SETS_FLAGS (inst.instruction))
10812 narrow = !in_it_block ();
10814 narrow = in_it_block ();
10816 if (Rd > 7 || Rn > 7 || Rs > 7)
10818 if (inst.operands[2].shifted)
10820 if (inst.size_req == 4)
10827 inst.instruction = THUMB_OP16 (inst.instruction);
10828 inst.instruction |= Rd;
10829 inst.instruction |= Rn << 3;
10834 inst.instruction = THUMB_OP16 (inst.instruction);
10835 inst.instruction |= Rd;
10836 inst.instruction |= Rs << 3;
10841 /* If we get here, it can't be done in 16 bits. */
10842 constraint (inst.operands[2].shifted
10843 && inst.operands[2].immisreg,
10844 _("shift must be constant"));
10845 inst.instruction = THUMB_OP32 (inst.instruction);
10846 inst.instruction |= Rd << 8;
10847 inst.instruction |= Rs << 16;
10848 encode_thumb32_shifted_operand (2);
10853 /* On its face this is a lie - the instruction does set the
10854 flags. However, the only supported mnemonic in this mode
10855 says it doesn't. */
10856 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10858 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10859 _("unshifted register required"));
10860 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10862 inst.instruction = THUMB_OP16 (inst.instruction);
10863 inst.instruction |= Rd;
10866 inst.instruction |= Rn << 3;
10868 inst.instruction |= Rs << 3;
10870 constraint (1, _("dest must overlap one source register"));
10878 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10879 constraint (msb > 32, _("bit-field extends past end of register"));
10880 /* The instruction encoding stores the LSB and MSB,
10881 not the LSB and width. */
10882 Rd = inst.operands[0].reg;
10883 reject_bad_reg (Rd);
10884 inst.instruction |= Rd << 8;
10885 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10886 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10887 inst.instruction |= msb - 1;
10896 Rd = inst.operands[0].reg;
10897 reject_bad_reg (Rd);
10899 /* #0 in second position is alternative syntax for bfc, which is
10900 the same instruction but with REG_PC in the Rm field. */
10901 if (!inst.operands[1].isreg)
10905 Rn = inst.operands[1].reg;
10906 reject_bad_reg (Rn);
10909 msb = inst.operands[2].imm + inst.operands[3].imm;
10910 constraint (msb > 32, _("bit-field extends past end of register"));
10911 /* The instruction encoding stores the LSB and MSB,
10912 not the LSB and width. */
10913 inst.instruction |= Rd << 8;
10914 inst.instruction |= Rn << 16;
10915 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10916 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10917 inst.instruction |= msb - 1;
10925 Rd = inst.operands[0].reg;
10926 Rn = inst.operands[1].reg;
10928 reject_bad_reg (Rd);
10929 reject_bad_reg (Rn);
10931 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10932 _("bit-field extends past end of register"));
10933 inst.instruction |= Rd << 8;
10934 inst.instruction |= Rn << 16;
10935 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10936 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10937 inst.instruction |= inst.operands[3].imm - 1;
10940 /* ARM V5 Thumb BLX (argument parse)
10941 BLX <target_addr> which is BLX(1)
10942 BLX <Rm> which is BLX(2)
10943 Unfortunately, there are two different opcodes for this mnemonic.
10944 So, the insns[].value is not used, and the code here zaps values
10945 into inst.instruction.
10947 ??? How to take advantage of the additional two bits of displacement
10948 available in Thumb32 mode? Need new relocation? */
10953 set_it_insn_type_last ();
10955 if (inst.operands[0].isreg)
10957 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10958 /* We have a register, so this is BLX(2). */
10959 inst.instruction |= inst.operands[0].reg << 3;
10963 /* No register. This must be BLX(1). */
10964 inst.instruction = 0xf000e800;
10965 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10974 bfd_reloc_code_real_type reloc;
10977 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10979 if (in_it_block ())
10981 /* Conditional branches inside IT blocks are encoded as unconditional
10983 cond = COND_ALWAYS;
10988 if (cond != COND_ALWAYS)
10989 opcode = T_MNEM_bcond;
10991 opcode = inst.instruction;
10994 && (inst.size_req == 4
10995 || (inst.size_req != 2
10996 && (inst.operands[0].hasreloc
10997 || inst.reloc.exp.X_op == O_constant))))
10999 inst.instruction = THUMB_OP32(opcode);
11000 if (cond == COND_ALWAYS)
11001 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
11004 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
11005 _("selected architecture does not support "
11006 "wide conditional branch instruction"));
11008 gas_assert (cond != 0xF);
11009 inst.instruction |= cond << 22;
11010 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
11015 inst.instruction = THUMB_OP16(opcode);
11016 if (cond == COND_ALWAYS)
11017 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
11020 inst.instruction |= cond << 8;
11021 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
11023 /* Allow section relaxation. */
11024 if (unified_syntax && inst.size_req != 2)
11025 inst.relax = opcode;
11027 inst.reloc.type = reloc;
11028 inst.reloc.pc_rel = 1;
11031 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11032 between the two is the maximum immediate allowed - which is passed in
11035 do_t_bkpt_hlt1 (int range)
11037 constraint (inst.cond != COND_ALWAYS,
11038 _("instruction is always unconditional"));
11039 if (inst.operands[0].present)
11041 constraint (inst.operands[0].imm > range,
11042 _("immediate value out of range"));
11043 inst.instruction |= inst.operands[0].imm;
11046 set_it_insn_type (NEUTRAL_IT_INSN);
11052 do_t_bkpt_hlt1 (63);
11058 do_t_bkpt_hlt1 (255);
11062 do_t_branch23 (void)
11064 set_it_insn_type_last ();
11065 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
11067 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11068 this file. We used to simply ignore the PLT reloc type here --
11069 the branch encoding is now needed to deal with TLSCALL relocs.
11070 So if we see a PLT reloc now, put it back to how it used to be to
11071 keep the preexisting behaviour. */
11072 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
11073 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
11075 #if defined(OBJ_COFF)
11076 /* If the destination of the branch is a defined symbol which does not have
11077 the THUMB_FUNC attribute, then we must be calling a function which has
11078 the (interfacearm) attribute. We look for the Thumb entry point to that
11079 function and change the branch to refer to that function instead. */
11080 if ( inst.reloc.exp.X_op == O_symbol
11081 && inst.reloc.exp.X_add_symbol != NULL
11082 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
11083 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
11084 inst.reloc.exp.X_add_symbol =
11085 find_real_start (inst.reloc.exp.X_add_symbol);
11092 set_it_insn_type_last ();
11093 inst.instruction |= inst.operands[0].reg << 3;
11094 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11095 should cause the alignment to be checked once it is known. This is
11096 because BX PC only works if the instruction is word aligned. */
11104 set_it_insn_type_last ();
11105 Rm = inst.operands[0].reg;
11106 reject_bad_reg (Rm);
11107 inst.instruction |= Rm << 16;
11116 Rd = inst.operands[0].reg;
11117 Rm = inst.operands[1].reg;
11119 reject_bad_reg (Rd);
11120 reject_bad_reg (Rm);
11122 inst.instruction |= Rd << 8;
11123 inst.instruction |= Rm << 16;
11124 inst.instruction |= Rm;
11130 set_it_insn_type (OUTSIDE_IT_INSN);
11131 inst.instruction |= inst.operands[0].imm;
11137 set_it_insn_type (OUTSIDE_IT_INSN);
11139 && (inst.operands[1].present || inst.size_req == 4)
11140 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
11142 unsigned int imod = (inst.instruction & 0x0030) >> 4;
11143 inst.instruction = 0xf3af8000;
11144 inst.instruction |= imod << 9;
11145 inst.instruction |= inst.operands[0].imm << 5;
11146 if (inst.operands[1].present)
11147 inst.instruction |= 0x100 | inst.operands[1].imm;
11151 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
11152 && (inst.operands[0].imm & 4),
11153 _("selected processor does not support 'A' form "
11154 "of this instruction"));
11155 constraint (inst.operands[1].present || inst.size_req == 4,
11156 _("Thumb does not support the 2-argument "
11157 "form of this instruction"));
11158 inst.instruction |= inst.operands[0].imm;
11162 /* THUMB CPY instruction (argument parse). */
11167 if (inst.size_req == 4)
11169 inst.instruction = THUMB_OP32 (T_MNEM_mov);
11170 inst.instruction |= inst.operands[0].reg << 8;
11171 inst.instruction |= inst.operands[1].reg;
11175 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
11176 inst.instruction |= (inst.operands[0].reg & 0x7);
11177 inst.instruction |= inst.operands[1].reg << 3;
11184 set_it_insn_type (OUTSIDE_IT_INSN);
11185 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11186 inst.instruction |= inst.operands[0].reg;
11187 inst.reloc.pc_rel = 1;
11188 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
11194 inst.instruction |= inst.operands[0].imm;
11200 unsigned Rd, Rn, Rm;
11202 Rd = inst.operands[0].reg;
11203 Rn = (inst.operands[1].present
11204 ? inst.operands[1].reg : Rd);
11205 Rm = inst.operands[2].reg;
11207 reject_bad_reg (Rd);
11208 reject_bad_reg (Rn);
11209 reject_bad_reg (Rm);
11211 inst.instruction |= Rd << 8;
11212 inst.instruction |= Rn << 16;
11213 inst.instruction |= Rm;
11219 if (unified_syntax && inst.size_req == 4)
11220 inst.instruction = THUMB_OP32 (inst.instruction);
11222 inst.instruction = THUMB_OP16 (inst.instruction);
11228 unsigned int cond = inst.operands[0].imm;
11230 set_it_insn_type (IT_INSN);
11231 now_it.mask = (inst.instruction & 0xf) | 0x10;
11233 now_it.warn_deprecated = FALSE;
11235 /* If the condition is a negative condition, invert the mask. */
11236 if ((cond & 0x1) == 0x0)
11238 unsigned int mask = inst.instruction & 0x000f;
11240 if ((mask & 0x7) == 0)
11242 /* No conversion needed. */
11243 now_it.block_length = 1;
11245 else if ((mask & 0x3) == 0)
11248 now_it.block_length = 2;
11250 else if ((mask & 0x1) == 0)
11253 now_it.block_length = 3;
11258 now_it.block_length = 4;
11261 inst.instruction &= 0xfff0;
11262 inst.instruction |= mask;
11265 inst.instruction |= cond << 4;
11268 /* Helper function used for both push/pop and ldm/stm. */
11270 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
11274 load = (inst.instruction & (1 << 20)) != 0;
11276 if (mask & (1 << 13))
11277 inst.error = _("SP not allowed in register list");
11279 if ((mask & (1 << base)) != 0
11281 inst.error = _("having the base register in the register list when "
11282 "using write back is UNPREDICTABLE");
11286 if (mask & (1 << 15))
11288 if (mask & (1 << 14))
11289 inst.error = _("LR and PC should not both be in register list");
11291 set_it_insn_type_last ();
11296 if (mask & (1 << 15))
11297 inst.error = _("PC not allowed in register list");
11300 if ((mask & (mask - 1)) == 0)
11302 /* Single register transfers implemented as str/ldr. */
11305 if (inst.instruction & (1 << 23))
11306 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
11308 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
11312 if (inst.instruction & (1 << 23))
11313 inst.instruction = 0x00800000; /* ia -> [base] */
11315 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
11318 inst.instruction |= 0xf8400000;
11320 inst.instruction |= 0x00100000;
11322 mask = ffs (mask) - 1;
11325 else if (writeback)
11326 inst.instruction |= WRITE_BACK;
11328 inst.instruction |= mask;
11329 inst.instruction |= base << 16;
11335 /* This really doesn't seem worth it. */
11336 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11337 _("expression too complex"));
11338 constraint (inst.operands[1].writeback,
11339 _("Thumb load/store multiple does not support {reglist}^"));
11341 if (unified_syntax)
11343 bfd_boolean narrow;
11347 /* See if we can use a 16-bit instruction. */
11348 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
11349 && inst.size_req != 4
11350 && !(inst.operands[1].imm & ~0xff))
11352 mask = 1 << inst.operands[0].reg;
11354 if (inst.operands[0].reg <= 7)
11356 if (inst.instruction == T_MNEM_stmia
11357 ? inst.operands[0].writeback
11358 : (inst.operands[0].writeback
11359 == !(inst.operands[1].imm & mask)))
11361 if (inst.instruction == T_MNEM_stmia
11362 && (inst.operands[1].imm & mask)
11363 && (inst.operands[1].imm & (mask - 1)))
11364 as_warn (_("value stored for r%d is UNKNOWN"),
11365 inst.operands[0].reg);
11367 inst.instruction = THUMB_OP16 (inst.instruction);
11368 inst.instruction |= inst.operands[0].reg << 8;
11369 inst.instruction |= inst.operands[1].imm;
11372 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11374 /* This means 1 register in reg list one of 3 situations:
11375 1. Instruction is stmia, but without writeback.
11376 2. lmdia without writeback, but with Rn not in
11378 3. ldmia with writeback, but with Rn in reglist.
11379 Case 3 is UNPREDICTABLE behaviour, so we handle
11380 case 1 and 2 which can be converted into a 16-bit
11381 str or ldr. The SP cases are handled below. */
11382 unsigned long opcode;
11383 /* First, record an error for Case 3. */
11384 if (inst.operands[1].imm & mask
11385 && inst.operands[0].writeback)
11387 _("having the base register in the register list when "
11388 "using write back is UNPREDICTABLE");
11390 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
11392 inst.instruction = THUMB_OP16 (opcode);
11393 inst.instruction |= inst.operands[0].reg << 3;
11394 inst.instruction |= (ffs (inst.operands[1].imm)-1);
11398 else if (inst.operands[0] .reg == REG_SP)
11400 if (inst.operands[0].writeback)
11403 THUMB_OP16 (inst.instruction == T_MNEM_stmia
11404 ? T_MNEM_push : T_MNEM_pop);
11405 inst.instruction |= inst.operands[1].imm;
11408 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11411 THUMB_OP16 (inst.instruction == T_MNEM_stmia
11412 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
11413 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
11421 if (inst.instruction < 0xffff)
11422 inst.instruction = THUMB_OP32 (inst.instruction);
11424 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
11425 inst.operands[0].writeback);
11430 constraint (inst.operands[0].reg > 7
11431 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
11432 constraint (inst.instruction != T_MNEM_ldmia
11433 && inst.instruction != T_MNEM_stmia,
11434 _("Thumb-2 instruction only valid in unified syntax"));
11435 if (inst.instruction == T_MNEM_stmia)
11437 if (!inst.operands[0].writeback)
11438 as_warn (_("this instruction will write back the base register"));
11439 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
11440 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
11441 as_warn (_("value stored for r%d is UNKNOWN"),
11442 inst.operands[0].reg);
11446 if (!inst.operands[0].writeback
11447 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
11448 as_warn (_("this instruction will write back the base register"));
11449 else if (inst.operands[0].writeback
11450 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
11451 as_warn (_("this instruction will not write back the base register"));
11454 inst.instruction = THUMB_OP16 (inst.instruction);
11455 inst.instruction |= inst.operands[0].reg << 8;
11456 inst.instruction |= inst.operands[1].imm;
11463 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
11464 || inst.operands[1].postind || inst.operands[1].writeback
11465 || inst.operands[1].immisreg || inst.operands[1].shifted
11466 || inst.operands[1].negative,
11469 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
11471 inst.instruction |= inst.operands[0].reg << 12;
11472 inst.instruction |= inst.operands[1].reg << 16;
11473 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11479 if (!inst.operands[1].present)
11481 constraint (inst.operands[0].reg == REG_LR,
11482 _("r14 not allowed as first register "
11483 "when second register is omitted"));
11484 inst.operands[1].reg = inst.operands[0].reg + 1;
11486 constraint (inst.operands[0].reg == inst.operands[1].reg,
11489 inst.instruction |= inst.operands[0].reg << 12;
11490 inst.instruction |= inst.operands[1].reg << 8;
11491 inst.instruction |= inst.operands[2].reg << 16;
11497 unsigned long opcode;
11500 if (inst.operands[0].isreg
11501 && !inst.operands[0].preind
11502 && inst.operands[0].reg == REG_PC)
11503 set_it_insn_type_last ();
11505 opcode = inst.instruction;
11506 if (unified_syntax)
11508 if (!inst.operands[1].isreg)
11510 if (opcode <= 0xffff)
11511 inst.instruction = THUMB_OP32 (opcode);
11512 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
11515 if (inst.operands[1].isreg
11516 && !inst.operands[1].writeback
11517 && !inst.operands[1].shifted && !inst.operands[1].postind
11518 && !inst.operands[1].negative && inst.operands[0].reg <= 7
11519 && opcode <= 0xffff
11520 && inst.size_req != 4)
11522 /* Insn may have a 16-bit form. */
11523 Rn = inst.operands[1].reg;
11524 if (inst.operands[1].immisreg)
11526 inst.instruction = THUMB_OP16 (opcode);
11528 if (Rn <= 7 && inst.operands[1].imm <= 7)
11530 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
11531 reject_bad_reg (inst.operands[1].imm);
11533 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
11534 && opcode != T_MNEM_ldrsb)
11535 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
11536 || (Rn == REG_SP && opcode == T_MNEM_str))
11543 if (inst.reloc.pc_rel)
11544 opcode = T_MNEM_ldr_pc2;
11546 opcode = T_MNEM_ldr_pc;
11550 if (opcode == T_MNEM_ldr)
11551 opcode = T_MNEM_ldr_sp;
11553 opcode = T_MNEM_str_sp;
11555 inst.instruction = inst.operands[0].reg << 8;
11559 inst.instruction = inst.operands[0].reg;
11560 inst.instruction |= inst.operands[1].reg << 3;
11562 inst.instruction |= THUMB_OP16 (opcode);
11563 if (inst.size_req == 2)
11564 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11566 inst.relax = opcode;
11570 /* Definitely a 32-bit variant. */
11572 /* Warning for Erratum 752419. */
11573 if (opcode == T_MNEM_ldr
11574 && inst.operands[0].reg == REG_SP
11575 && inst.operands[1].writeback == 1
11576 && !inst.operands[1].immisreg)
11578 if (no_cpu_selected ()
11579 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
11580 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
11581 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
11582 as_warn (_("This instruction may be unpredictable "
11583 "if executed on M-profile cores "
11584 "with interrupts enabled."));
11587 /* Do some validations regarding addressing modes. */
11588 if (inst.operands[1].immisreg)
11589 reject_bad_reg (inst.operands[1].imm);
11591 constraint (inst.operands[1].writeback == 1
11592 && inst.operands[0].reg == inst.operands[1].reg,
11595 inst.instruction = THUMB_OP32 (opcode);
11596 inst.instruction |= inst.operands[0].reg << 12;
11597 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
11598 check_ldr_r15_aligned ();
11602 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11604 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
11606 /* Only [Rn,Rm] is acceptable. */
11607 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
11608 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
11609 || inst.operands[1].postind || inst.operands[1].shifted
11610 || inst.operands[1].negative,
11611 _("Thumb does not support this addressing mode"));
11612 inst.instruction = THUMB_OP16 (inst.instruction);
11616 inst.instruction = THUMB_OP16 (inst.instruction);
11617 if (!inst.operands[1].isreg)
11618 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
11621 constraint (!inst.operands[1].preind
11622 || inst.operands[1].shifted
11623 || inst.operands[1].writeback,
11624 _("Thumb does not support this addressing mode"));
11625 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
11627 constraint (inst.instruction & 0x0600,
11628 _("byte or halfword not valid for base register"));
11629 constraint (inst.operands[1].reg == REG_PC
11630 && !(inst.instruction & THUMB_LOAD_BIT),
11631 _("r15 based store not allowed"));
11632 constraint (inst.operands[1].immisreg,
11633 _("invalid base register for register offset"));
11635 if (inst.operands[1].reg == REG_PC)
11636 inst.instruction = T_OPCODE_LDR_PC;
11637 else if (inst.instruction & THUMB_LOAD_BIT)
11638 inst.instruction = T_OPCODE_LDR_SP;
11640 inst.instruction = T_OPCODE_STR_SP;
11642 inst.instruction |= inst.operands[0].reg << 8;
11643 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11647 constraint (inst.operands[1].reg > 7, BAD_HIREG);
11648 if (!inst.operands[1].immisreg)
11650 /* Immediate offset. */
11651 inst.instruction |= inst.operands[0].reg;
11652 inst.instruction |= inst.operands[1].reg << 3;
11653 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11657 /* Register offset. */
11658 constraint (inst.operands[1].imm > 7, BAD_HIREG);
11659 constraint (inst.operands[1].negative,
11660 _("Thumb does not support this addressing mode"));
11663 switch (inst.instruction)
11665 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
11666 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
11667 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
11668 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
11669 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
11670 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
11671 case 0x5600 /* ldrsb */:
11672 case 0x5e00 /* ldrsh */: break;
11676 inst.instruction |= inst.operands[0].reg;
11677 inst.instruction |= inst.operands[1].reg << 3;
11678 inst.instruction |= inst.operands[1].imm << 6;
11684 if (!inst.operands[1].present)
11686 inst.operands[1].reg = inst.operands[0].reg + 1;
11687 constraint (inst.operands[0].reg == REG_LR,
11688 _("r14 not allowed here"));
11689 constraint (inst.operands[0].reg == REG_R12,
11690 _("r12 not allowed here"));
11693 if (inst.operands[2].writeback
11694 && (inst.operands[0].reg == inst.operands[2].reg
11695 || inst.operands[1].reg == inst.operands[2].reg))
11696 as_warn (_("base register written back, and overlaps "
11697 "one of transfer registers"));
11699 inst.instruction |= inst.operands[0].reg << 12;
11700 inst.instruction |= inst.operands[1].reg << 8;
11701 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
11707 inst.instruction |= inst.operands[0].reg << 12;
11708 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
11714 unsigned Rd, Rn, Rm, Ra;
11716 Rd = inst.operands[0].reg;
11717 Rn = inst.operands[1].reg;
11718 Rm = inst.operands[2].reg;
11719 Ra = inst.operands[3].reg;
11721 reject_bad_reg (Rd);
11722 reject_bad_reg (Rn);
11723 reject_bad_reg (Rm);
11724 reject_bad_reg (Ra);
11726 inst.instruction |= Rd << 8;
11727 inst.instruction |= Rn << 16;
11728 inst.instruction |= Rm;
11729 inst.instruction |= Ra << 12;
11735 unsigned RdLo, RdHi, Rn, Rm;
11737 RdLo = inst.operands[0].reg;
11738 RdHi = inst.operands[1].reg;
11739 Rn = inst.operands[2].reg;
11740 Rm = inst.operands[3].reg;
11742 reject_bad_reg (RdLo);
11743 reject_bad_reg (RdHi);
11744 reject_bad_reg (Rn);
11745 reject_bad_reg (Rm);
11747 inst.instruction |= RdLo << 12;
11748 inst.instruction |= RdHi << 8;
11749 inst.instruction |= Rn << 16;
11750 inst.instruction |= Rm;
11754 do_t_mov_cmp (void)
11758 Rn = inst.operands[0].reg;
11759 Rm = inst.operands[1].reg;
11762 set_it_insn_type_last ();
11764 if (unified_syntax)
11766 int r0off = (inst.instruction == T_MNEM_mov
11767 || inst.instruction == T_MNEM_movs) ? 8 : 16;
11768 unsigned long opcode;
11769 bfd_boolean narrow;
11770 bfd_boolean low_regs;
11772 low_regs = (Rn <= 7 && Rm <= 7);
11773 opcode = inst.instruction;
11774 if (in_it_block ())
11775 narrow = opcode != T_MNEM_movs;
11777 narrow = opcode != T_MNEM_movs || low_regs;
11778 if (inst.size_req == 4
11779 || inst.operands[1].shifted)
11782 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11783 if (opcode == T_MNEM_movs && inst.operands[1].isreg
11784 && !inst.operands[1].shifted
11788 inst.instruction = T2_SUBS_PC_LR;
11792 if (opcode == T_MNEM_cmp)
11794 constraint (Rn == REG_PC, BAD_PC);
11797 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11799 warn_deprecated_sp (Rm);
11800 /* R15 was documented as a valid choice for Rm in ARMv6,
11801 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11802 tools reject R15, so we do too. */
11803 constraint (Rm == REG_PC, BAD_PC);
11806 reject_bad_reg (Rm);
11808 else if (opcode == T_MNEM_mov
11809 || opcode == T_MNEM_movs)
11811 if (inst.operands[1].isreg)
11813 if (opcode == T_MNEM_movs)
11815 reject_bad_reg (Rn);
11816 reject_bad_reg (Rm);
11820 /* This is mov.n. */
11821 if ((Rn == REG_SP || Rn == REG_PC)
11822 && (Rm == REG_SP || Rm == REG_PC))
11824 as_tsktsk (_("Use of r%u as a source register is "
11825 "deprecated when r%u is the destination "
11826 "register."), Rm, Rn);
11831 /* This is mov.w. */
11832 constraint (Rn == REG_PC, BAD_PC);
11833 constraint (Rm == REG_PC, BAD_PC);
11834 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11838 reject_bad_reg (Rn);
11841 if (!inst.operands[1].isreg)
11843 /* Immediate operand. */
11844 if (!in_it_block () && opcode == T_MNEM_mov)
11846 if (low_regs && narrow)
11848 inst.instruction = THUMB_OP16 (opcode);
11849 inst.instruction |= Rn << 8;
11850 if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11851 || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
11853 if (inst.size_req == 2)
11854 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11856 inst.relax = opcode;
11861 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11862 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
11863 THUMB1_RELOC_ONLY);
11865 inst.instruction = THUMB_OP32 (inst.instruction);
11866 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11867 inst.instruction |= Rn << r0off;
11868 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11871 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11872 && (inst.instruction == T_MNEM_mov
11873 || inst.instruction == T_MNEM_movs))
11875 /* Register shifts are encoded as separate shift instructions. */
11876 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11878 if (in_it_block ())
11883 if (inst.size_req == 4)
11886 if (!low_regs || inst.operands[1].imm > 7)
11892 switch (inst.operands[1].shift_kind)
11895 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11898 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11901 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11904 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11910 inst.instruction = opcode;
11913 inst.instruction |= Rn;
11914 inst.instruction |= inst.operands[1].imm << 3;
11919 inst.instruction |= CONDS_BIT;
11921 inst.instruction |= Rn << 8;
11922 inst.instruction |= Rm << 16;
11923 inst.instruction |= inst.operands[1].imm;
11928 /* Some mov with immediate shift have narrow variants.
11929 Register shifts are handled above. */
11930 if (low_regs && inst.operands[1].shifted
11931 && (inst.instruction == T_MNEM_mov
11932 || inst.instruction == T_MNEM_movs))
11934 if (in_it_block ())
11935 narrow = (inst.instruction == T_MNEM_mov);
11937 narrow = (inst.instruction == T_MNEM_movs);
11942 switch (inst.operands[1].shift_kind)
11944 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11945 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11946 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11947 default: narrow = FALSE; break;
11953 inst.instruction |= Rn;
11954 inst.instruction |= Rm << 3;
11955 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11959 inst.instruction = THUMB_OP32 (inst.instruction);
11960 inst.instruction |= Rn << r0off;
11961 encode_thumb32_shifted_operand (1);
11965 switch (inst.instruction)
11968 /* In v4t or v5t a move of two lowregs produces unpredictable
11969 results. Don't allow this. */
11972 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11973 "MOV Rd, Rs with two low registers is not "
11974 "permitted on this architecture");
11975 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11979 inst.instruction = T_OPCODE_MOV_HR;
11980 inst.instruction |= (Rn & 0x8) << 4;
11981 inst.instruction |= (Rn & 0x7);
11982 inst.instruction |= Rm << 3;
11986 /* We know we have low registers at this point.
11987 Generate LSLS Rd, Rs, #0. */
11988 inst.instruction = T_OPCODE_LSL_I;
11989 inst.instruction |= Rn;
11990 inst.instruction |= Rm << 3;
11996 inst.instruction = T_OPCODE_CMP_LR;
11997 inst.instruction |= Rn;
11998 inst.instruction |= Rm << 3;
12002 inst.instruction = T_OPCODE_CMP_HR;
12003 inst.instruction |= (Rn & 0x8) << 4;
12004 inst.instruction |= (Rn & 0x7);
12005 inst.instruction |= Rm << 3;
12012 inst.instruction = THUMB_OP16 (inst.instruction);
12014 /* PR 10443: Do not silently ignore shifted operands. */
12015 constraint (inst.operands[1].shifted,
12016 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12018 if (inst.operands[1].isreg)
12020 if (Rn < 8 && Rm < 8)
12022 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12023 since a MOV instruction produces unpredictable results. */
12024 if (inst.instruction == T_OPCODE_MOV_I8)
12025 inst.instruction = T_OPCODE_ADD_I3;
12027 inst.instruction = T_OPCODE_CMP_LR;
12029 inst.instruction |= Rn;
12030 inst.instruction |= Rm << 3;
12034 if (inst.instruction == T_OPCODE_MOV_I8)
12035 inst.instruction = T_OPCODE_MOV_HR;
12037 inst.instruction = T_OPCODE_CMP_HR;
12043 constraint (Rn > 7,
12044 _("only lo regs allowed with immediate"));
12045 inst.instruction |= Rn << 8;
12046 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
12057 top = (inst.instruction & 0x00800000) != 0;
12058 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
12060 constraint (top, _(":lower16: not allowed this instruction"));
12061 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
12063 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
12065 constraint (!top, _(":upper16: not allowed this instruction"));
12066 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
12069 Rd = inst.operands[0].reg;
12070 reject_bad_reg (Rd);
12072 inst.instruction |= Rd << 8;
12073 if (inst.reloc.type == BFD_RELOC_UNUSED)
12075 imm = inst.reloc.exp.X_add_number;
12076 inst.instruction |= (imm & 0xf000) << 4;
12077 inst.instruction |= (imm & 0x0800) << 15;
12078 inst.instruction |= (imm & 0x0700) << 4;
12079 inst.instruction |= (imm & 0x00ff);
12084 do_t_mvn_tst (void)
12088 Rn = inst.operands[0].reg;
12089 Rm = inst.operands[1].reg;
12091 if (inst.instruction == T_MNEM_cmp
12092 || inst.instruction == T_MNEM_cmn)
12093 constraint (Rn == REG_PC, BAD_PC);
12095 reject_bad_reg (Rn);
12096 reject_bad_reg (Rm);
12098 if (unified_syntax)
12100 int r0off = (inst.instruction == T_MNEM_mvn
12101 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
12102 bfd_boolean narrow;
12104 if (inst.size_req == 4
12105 || inst.instruction > 0xffff
12106 || inst.operands[1].shifted
12107 || Rn > 7 || Rm > 7)
12109 else if (inst.instruction == T_MNEM_cmn
12110 || inst.instruction == T_MNEM_tst)
12112 else if (THUMB_SETS_FLAGS (inst.instruction))
12113 narrow = !in_it_block ();
12115 narrow = in_it_block ();
12117 if (!inst.operands[1].isreg)
12119 /* For an immediate, we always generate a 32-bit opcode;
12120 section relaxation will shrink it later if possible. */
12121 if (inst.instruction < 0xffff)
12122 inst.instruction = THUMB_OP32 (inst.instruction);
12123 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12124 inst.instruction |= Rn << r0off;
12125 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12129 /* See if we can do this with a 16-bit instruction. */
12132 inst.instruction = THUMB_OP16 (inst.instruction);
12133 inst.instruction |= Rn;
12134 inst.instruction |= Rm << 3;
12138 constraint (inst.operands[1].shifted
12139 && inst.operands[1].immisreg,
12140 _("shift must be constant"));
12141 if (inst.instruction < 0xffff)
12142 inst.instruction = THUMB_OP32 (inst.instruction);
12143 inst.instruction |= Rn << r0off;
12144 encode_thumb32_shifted_operand (1);
12150 constraint (inst.instruction > 0xffff
12151 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
12152 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
12153 _("unshifted register required"));
12154 constraint (Rn > 7 || Rm > 7,
12157 inst.instruction = THUMB_OP16 (inst.instruction);
12158 inst.instruction |= Rn;
12159 inst.instruction |= Rm << 3;
12168 if (do_vfp_nsyn_mrs () == SUCCESS)
12171 Rd = inst.operands[0].reg;
12172 reject_bad_reg (Rd);
12173 inst.instruction |= Rd << 8;
12175 if (inst.operands[1].isreg)
12177 unsigned br = inst.operands[1].reg;
12178 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
12179 as_bad (_("bad register for mrs"));
12181 inst.instruction |= br & (0xf << 16);
12182 inst.instruction |= (br & 0x300) >> 4;
12183 inst.instruction |= (br & SPSR_BIT) >> 2;
12187 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
12189 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
12191 /* PR gas/12698: The constraint is only applied for m_profile.
12192 If the user has specified -march=all, we want to ignore it as
12193 we are building for any CPU type, including non-m variants. */
12194 bfd_boolean m_profile =
12195 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
12196 constraint ((flags != 0) && m_profile, _("selected processor does "
12197 "not support requested special purpose register"));
12200 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12202 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
12203 _("'APSR', 'CPSR' or 'SPSR' expected"));
12205 inst.instruction |= (flags & SPSR_BIT) >> 2;
12206 inst.instruction |= inst.operands[1].imm & 0xff;
12207 inst.instruction |= 0xf0000;
12217 if (do_vfp_nsyn_msr () == SUCCESS)
12220 constraint (!inst.operands[1].isreg,
12221 _("Thumb encoding does not support an immediate here"));
12223 if (inst.operands[0].isreg)
12224 flags = (int)(inst.operands[0].reg);
12226 flags = inst.operands[0].imm;
12228 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
12230 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
12232 /* PR gas/12698: The constraint is only applied for m_profile.
12233 If the user has specified -march=all, we want to ignore it as
12234 we are building for any CPU type, including non-m variants. */
12235 bfd_boolean m_profile =
12236 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
12237 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
12238 && (bits & ~(PSR_s | PSR_f)) != 0)
12239 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
12240 && bits != PSR_f)) && m_profile,
12241 _("selected processor does not support requested special "
12242 "purpose register"));
12245 constraint ((flags & 0xff) != 0, _("selected processor does not support "
12246 "requested special purpose register"));
12248 Rn = inst.operands[1].reg;
12249 reject_bad_reg (Rn);
12251 inst.instruction |= (flags & SPSR_BIT) >> 2;
12252 inst.instruction |= (flags & 0xf0000) >> 8;
12253 inst.instruction |= (flags & 0x300) >> 4;
12254 inst.instruction |= (flags & 0xff);
12255 inst.instruction |= Rn << 16;
12261 bfd_boolean narrow;
12262 unsigned Rd, Rn, Rm;
12264 if (!inst.operands[2].present)
12265 inst.operands[2].reg = inst.operands[0].reg;
12267 Rd = inst.operands[0].reg;
12268 Rn = inst.operands[1].reg;
12269 Rm = inst.operands[2].reg;
12271 if (unified_syntax)
12273 if (inst.size_req == 4
12279 else if (inst.instruction == T_MNEM_muls)
12280 narrow = !in_it_block ();
12282 narrow = in_it_block ();
12286 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
12287 constraint (Rn > 7 || Rm > 7,
12294 /* 16-bit MULS/Conditional MUL. */
12295 inst.instruction = THUMB_OP16 (inst.instruction);
12296 inst.instruction |= Rd;
12299 inst.instruction |= Rm << 3;
12301 inst.instruction |= Rn << 3;
12303 constraint (1, _("dest must overlap one source register"));
12307 constraint (inst.instruction != T_MNEM_mul,
12308 _("Thumb-2 MUL must not set flags"));
12310 inst.instruction = THUMB_OP32 (inst.instruction);
12311 inst.instruction |= Rd << 8;
12312 inst.instruction |= Rn << 16;
12313 inst.instruction |= Rm << 0;
12315 reject_bad_reg (Rd);
12316 reject_bad_reg (Rn);
12317 reject_bad_reg (Rm);
12324 unsigned RdLo, RdHi, Rn, Rm;
12326 RdLo = inst.operands[0].reg;
12327 RdHi = inst.operands[1].reg;
12328 Rn = inst.operands[2].reg;
12329 Rm = inst.operands[3].reg;
12331 reject_bad_reg (RdLo);
12332 reject_bad_reg (RdHi);
12333 reject_bad_reg (Rn);
12334 reject_bad_reg (Rm);
12336 inst.instruction |= RdLo << 12;
12337 inst.instruction |= RdHi << 8;
12338 inst.instruction |= Rn << 16;
12339 inst.instruction |= Rm;
12342 as_tsktsk (_("rdhi and rdlo must be different"));
12348 set_it_insn_type (NEUTRAL_IT_INSN);
12350 if (unified_syntax)
12352 if (inst.size_req == 4 || inst.operands[0].imm > 15)
12354 inst.instruction = THUMB_OP32 (inst.instruction);
12355 inst.instruction |= inst.operands[0].imm;
12359 /* PR9722: Check for Thumb2 availability before
12360 generating a thumb2 nop instruction. */
12361 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
12363 inst.instruction = THUMB_OP16 (inst.instruction);
12364 inst.instruction |= inst.operands[0].imm << 4;
12367 inst.instruction = 0x46c0;
12372 constraint (inst.operands[0].present,
12373 _("Thumb does not support NOP with hints"));
12374 inst.instruction = 0x46c0;
12381 if (unified_syntax)
12383 bfd_boolean narrow;
12385 if (THUMB_SETS_FLAGS (inst.instruction))
12386 narrow = !in_it_block ();
12388 narrow = in_it_block ();
12389 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12391 if (inst.size_req == 4)
12396 inst.instruction = THUMB_OP32 (inst.instruction);
12397 inst.instruction |= inst.operands[0].reg << 8;
12398 inst.instruction |= inst.operands[1].reg << 16;
12402 inst.instruction = THUMB_OP16 (inst.instruction);
12403 inst.instruction |= inst.operands[0].reg;
12404 inst.instruction |= inst.operands[1].reg << 3;
12409 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
12411 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12413 inst.instruction = THUMB_OP16 (inst.instruction);
12414 inst.instruction |= inst.operands[0].reg;
12415 inst.instruction |= inst.operands[1].reg << 3;
12424 Rd = inst.operands[0].reg;
12425 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
12427 reject_bad_reg (Rd);
12428 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12429 reject_bad_reg (Rn);
12431 inst.instruction |= Rd << 8;
12432 inst.instruction |= Rn << 16;
12434 if (!inst.operands[2].isreg)
12436 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12437 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12443 Rm = inst.operands[2].reg;
12444 reject_bad_reg (Rm);
12446 constraint (inst.operands[2].shifted
12447 && inst.operands[2].immisreg,
12448 _("shift must be constant"));
12449 encode_thumb32_shifted_operand (2);
12456 unsigned Rd, Rn, Rm;
12458 Rd = inst.operands[0].reg;
12459 Rn = inst.operands[1].reg;
12460 Rm = inst.operands[2].reg;
12462 reject_bad_reg (Rd);
12463 reject_bad_reg (Rn);
12464 reject_bad_reg (Rm);
12466 inst.instruction |= Rd << 8;
12467 inst.instruction |= Rn << 16;
12468 inst.instruction |= Rm;
12469 if (inst.operands[3].present)
12471 unsigned int val = inst.reloc.exp.X_add_number;
12472 constraint (inst.reloc.exp.X_op != O_constant,
12473 _("expression too complex"));
12474 inst.instruction |= (val & 0x1c) << 10;
12475 inst.instruction |= (val & 0x03) << 6;
12482 if (!inst.operands[3].present)
12486 inst.instruction &= ~0x00000020;
12488 /* PR 10168. Swap the Rm and Rn registers. */
12489 Rtmp = inst.operands[1].reg;
12490 inst.operands[1].reg = inst.operands[2].reg;
12491 inst.operands[2].reg = Rtmp;
12499 if (inst.operands[0].immisreg)
12500 reject_bad_reg (inst.operands[0].imm);
12502 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
12506 do_t_push_pop (void)
12510 constraint (inst.operands[0].writeback,
12511 _("push/pop do not support {reglist}^"));
12512 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
12513 _("expression too complex"));
12515 mask = inst.operands[0].imm;
12516 if (inst.size_req != 4 && (mask & ~0xff) == 0)
12517 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
12518 else if (inst.size_req != 4
12519 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
12520 ? REG_LR : REG_PC)))
12522 inst.instruction = THUMB_OP16 (inst.instruction);
12523 inst.instruction |= THUMB_PP_PC_LR;
12524 inst.instruction |= mask & 0xff;
12526 else if (unified_syntax)
12528 inst.instruction = THUMB_OP32 (inst.instruction);
12529 encode_thumb2_ldmstm (13, mask, TRUE);
12533 inst.error = _("invalid register list to push/pop instruction");
12543 Rd = inst.operands[0].reg;
12544 Rm = inst.operands[1].reg;
12546 reject_bad_reg (Rd);
12547 reject_bad_reg (Rm);
12549 inst.instruction |= Rd << 8;
12550 inst.instruction |= Rm << 16;
12551 inst.instruction |= Rm;
12559 Rd = inst.operands[0].reg;
12560 Rm = inst.operands[1].reg;
12562 reject_bad_reg (Rd);
12563 reject_bad_reg (Rm);
12565 if (Rd <= 7 && Rm <= 7
12566 && inst.size_req != 4)
12568 inst.instruction = THUMB_OP16 (inst.instruction);
12569 inst.instruction |= Rd;
12570 inst.instruction |= Rm << 3;
12572 else if (unified_syntax)
12574 inst.instruction = THUMB_OP32 (inst.instruction);
12575 inst.instruction |= Rd << 8;
12576 inst.instruction |= Rm << 16;
12577 inst.instruction |= Rm;
12580 inst.error = BAD_HIREG;
12588 Rd = inst.operands[0].reg;
12589 Rm = inst.operands[1].reg;
12591 reject_bad_reg (Rd);
12592 reject_bad_reg (Rm);
12594 inst.instruction |= Rd << 8;
12595 inst.instruction |= Rm;
12603 Rd = inst.operands[0].reg;
12604 Rs = (inst.operands[1].present
12605 ? inst.operands[1].reg /* Rd, Rs, foo */
12606 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
12608 reject_bad_reg (Rd);
12609 reject_bad_reg (Rs);
12610 if (inst.operands[2].isreg)
12611 reject_bad_reg (inst.operands[2].reg);
12613 inst.instruction |= Rd << 8;
12614 inst.instruction |= Rs << 16;
12615 if (!inst.operands[2].isreg)
12617 bfd_boolean narrow;
12619 if ((inst.instruction & 0x00100000) != 0)
12620 narrow = !in_it_block ();
12622 narrow = in_it_block ();
12624 if (Rd > 7 || Rs > 7)
12627 if (inst.size_req == 4 || !unified_syntax)
12630 if (inst.reloc.exp.X_op != O_constant
12631 || inst.reloc.exp.X_add_number != 0)
12634 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12635 relaxation, but it doesn't seem worth the hassle. */
12638 inst.reloc.type = BFD_RELOC_UNUSED;
12639 inst.instruction = THUMB_OP16 (T_MNEM_negs);
12640 inst.instruction |= Rs << 3;
12641 inst.instruction |= Rd;
12645 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12646 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12650 encode_thumb32_shifted_operand (2);
12656 if (warn_on_deprecated
12657 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12658 as_tsktsk (_("setend use is deprecated for ARMv8"));
12660 set_it_insn_type (OUTSIDE_IT_INSN);
12661 if (inst.operands[0].imm)
12662 inst.instruction |= 0x8;
12668 if (!inst.operands[1].present)
12669 inst.operands[1].reg = inst.operands[0].reg;
12671 if (unified_syntax)
12673 bfd_boolean narrow;
12676 switch (inst.instruction)
12679 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
12681 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
12683 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
12685 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
12689 if (THUMB_SETS_FLAGS (inst.instruction))
12690 narrow = !in_it_block ();
12692 narrow = in_it_block ();
12693 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12695 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
12697 if (inst.operands[2].isreg
12698 && (inst.operands[1].reg != inst.operands[0].reg
12699 || inst.operands[2].reg > 7))
12701 if (inst.size_req == 4)
12704 reject_bad_reg (inst.operands[0].reg);
12705 reject_bad_reg (inst.operands[1].reg);
12709 if (inst.operands[2].isreg)
12711 reject_bad_reg (inst.operands[2].reg);
12712 inst.instruction = THUMB_OP32 (inst.instruction);
12713 inst.instruction |= inst.operands[0].reg << 8;
12714 inst.instruction |= inst.operands[1].reg << 16;
12715 inst.instruction |= inst.operands[2].reg;
12717 /* PR 12854: Error on extraneous shifts. */
12718 constraint (inst.operands[2].shifted,
12719 _("extraneous shift as part of operand to shift insn"));
12723 inst.operands[1].shifted = 1;
12724 inst.operands[1].shift_kind = shift_kind;
12725 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
12726 ? T_MNEM_movs : T_MNEM_mov);
12727 inst.instruction |= inst.operands[0].reg << 8;
12728 encode_thumb32_shifted_operand (1);
12729 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12730 inst.reloc.type = BFD_RELOC_UNUSED;
12735 if (inst.operands[2].isreg)
12737 switch (shift_kind)
12739 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
12740 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
12741 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
12742 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
12746 inst.instruction |= inst.operands[0].reg;
12747 inst.instruction |= inst.operands[2].reg << 3;
12749 /* PR 12854: Error on extraneous shifts. */
12750 constraint (inst.operands[2].shifted,
12751 _("extraneous shift as part of operand to shift insn"));
12755 switch (shift_kind)
12757 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12758 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12759 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12762 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12763 inst.instruction |= inst.operands[0].reg;
12764 inst.instruction |= inst.operands[1].reg << 3;
12770 constraint (inst.operands[0].reg > 7
12771 || inst.operands[1].reg > 7, BAD_HIREG);
12772 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12774 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
12776 constraint (inst.operands[2].reg > 7, BAD_HIREG);
12777 constraint (inst.operands[0].reg != inst.operands[1].reg,
12778 _("source1 and dest must be same register"));
12780 switch (inst.instruction)
12782 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
12783 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
12784 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
12785 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
12789 inst.instruction |= inst.operands[0].reg;
12790 inst.instruction |= inst.operands[2].reg << 3;
12792 /* PR 12854: Error on extraneous shifts. */
12793 constraint (inst.operands[2].shifted,
12794 _("extraneous shift as part of operand to shift insn"));
12798 switch (inst.instruction)
12800 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
12801 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
12802 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
12803 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
12806 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12807 inst.instruction |= inst.operands[0].reg;
12808 inst.instruction |= inst.operands[1].reg << 3;
12816 unsigned Rd, Rn, Rm;
12818 Rd = inst.operands[0].reg;
12819 Rn = inst.operands[1].reg;
12820 Rm = inst.operands[2].reg;
12822 reject_bad_reg (Rd);
12823 reject_bad_reg (Rn);
12824 reject_bad_reg (Rm);
12826 inst.instruction |= Rd << 8;
12827 inst.instruction |= Rn << 16;
12828 inst.instruction |= Rm;
12834 unsigned Rd, Rn, Rm;
12836 Rd = inst.operands[0].reg;
12837 Rm = inst.operands[1].reg;
12838 Rn = inst.operands[2].reg;
12840 reject_bad_reg (Rd);
12841 reject_bad_reg (Rn);
12842 reject_bad_reg (Rm);
12844 inst.instruction |= Rd << 8;
12845 inst.instruction |= Rn << 16;
12846 inst.instruction |= Rm;
12852 unsigned int value = inst.reloc.exp.X_add_number;
12853 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12854 _("SMC is not permitted on this architecture"));
12855 constraint (inst.reloc.exp.X_op != O_constant,
12856 _("expression too complex"));
12857 inst.reloc.type = BFD_RELOC_UNUSED;
12858 inst.instruction |= (value & 0xf000) >> 12;
12859 inst.instruction |= (value & 0x0ff0);
12860 inst.instruction |= (value & 0x000f) << 16;
12861 /* PR gas/15623: SMC instructions must be last in an IT block. */
12862 set_it_insn_type_last ();
12868 unsigned int value = inst.reloc.exp.X_add_number;
12870 inst.reloc.type = BFD_RELOC_UNUSED;
12871 inst.instruction |= (value & 0x0fff);
12872 inst.instruction |= (value & 0xf000) << 4;
12876 do_t_ssat_usat (int bias)
12880 Rd = inst.operands[0].reg;
12881 Rn = inst.operands[2].reg;
12883 reject_bad_reg (Rd);
12884 reject_bad_reg (Rn);
12886 inst.instruction |= Rd << 8;
12887 inst.instruction |= inst.operands[1].imm - bias;
12888 inst.instruction |= Rn << 16;
12890 if (inst.operands[3].present)
12892 offsetT shift_amount = inst.reloc.exp.X_add_number;
12894 inst.reloc.type = BFD_RELOC_UNUSED;
12896 constraint (inst.reloc.exp.X_op != O_constant,
12897 _("expression too complex"));
12899 if (shift_amount != 0)
12901 constraint (shift_amount > 31,
12902 _("shift expression is too large"));
12904 if (inst.operands[3].shift_kind == SHIFT_ASR)
12905 inst.instruction |= 0x00200000; /* sh bit. */
12907 inst.instruction |= (shift_amount & 0x1c) << 10;
12908 inst.instruction |= (shift_amount & 0x03) << 6;
12916 do_t_ssat_usat (1);
12924 Rd = inst.operands[0].reg;
12925 Rn = inst.operands[2].reg;
12927 reject_bad_reg (Rd);
12928 reject_bad_reg (Rn);
12930 inst.instruction |= Rd << 8;
12931 inst.instruction |= inst.operands[1].imm - 1;
12932 inst.instruction |= Rn << 16;
12938 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12939 || inst.operands[2].postind || inst.operands[2].writeback
12940 || inst.operands[2].immisreg || inst.operands[2].shifted
12941 || inst.operands[2].negative,
12944 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12946 inst.instruction |= inst.operands[0].reg << 8;
12947 inst.instruction |= inst.operands[1].reg << 12;
12948 inst.instruction |= inst.operands[2].reg << 16;
12949 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12955 if (!inst.operands[2].present)
12956 inst.operands[2].reg = inst.operands[1].reg + 1;
12958 constraint (inst.operands[0].reg == inst.operands[1].reg
12959 || inst.operands[0].reg == inst.operands[2].reg
12960 || inst.operands[0].reg == inst.operands[3].reg,
12963 inst.instruction |= inst.operands[0].reg;
12964 inst.instruction |= inst.operands[1].reg << 12;
12965 inst.instruction |= inst.operands[2].reg << 8;
12966 inst.instruction |= inst.operands[3].reg << 16;
12972 unsigned Rd, Rn, Rm;
12974 Rd = inst.operands[0].reg;
12975 Rn = inst.operands[1].reg;
12976 Rm = inst.operands[2].reg;
12978 reject_bad_reg (Rd);
12979 reject_bad_reg (Rn);
12980 reject_bad_reg (Rm);
12982 inst.instruction |= Rd << 8;
12983 inst.instruction |= Rn << 16;
12984 inst.instruction |= Rm;
12985 inst.instruction |= inst.operands[3].imm << 4;
12993 Rd = inst.operands[0].reg;
12994 Rm = inst.operands[1].reg;
12996 reject_bad_reg (Rd);
12997 reject_bad_reg (Rm);
12999 if (inst.instruction <= 0xffff
13000 && inst.size_req != 4
13001 && Rd <= 7 && Rm <= 7
13002 && (!inst.operands[2].present || inst.operands[2].imm == 0))
13004 inst.instruction = THUMB_OP16 (inst.instruction);
13005 inst.instruction |= Rd;
13006 inst.instruction |= Rm << 3;
13008 else if (unified_syntax)
13010 if (inst.instruction <= 0xffff)
13011 inst.instruction = THUMB_OP32 (inst.instruction);
13012 inst.instruction |= Rd << 8;
13013 inst.instruction |= Rm;
13014 inst.instruction |= inst.operands[2].imm << 4;
13018 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
13019 _("Thumb encoding does not support rotation"));
13020 constraint (1, BAD_HIREG);
13027 /* We have to do the following check manually as ARM_EXT_OS only applies
13029 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
13031 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
13032 /* This only applies to the v6m howver, not later architectures. */
13033 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
13034 as_bad (_("SVC is not permitted on this architecture"));
13035 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
13038 inst.reloc.type = BFD_RELOC_ARM_SWI;
13047 half = (inst.instruction & 0x10) != 0;
13048 set_it_insn_type_last ();
13049 constraint (inst.operands[0].immisreg,
13050 _("instruction requires register index"));
13052 Rn = inst.operands[0].reg;
13053 Rm = inst.operands[0].imm;
13055 constraint (Rn == REG_SP, BAD_SP);
13056 reject_bad_reg (Rm);
13058 constraint (!half && inst.operands[0].shifted,
13059 _("instruction does not allow shifted index"));
13060 inst.instruction |= (Rn << 16) | Rm;
13066 if (!inst.operands[0].present)
13067 inst.operands[0].imm = 0;
13069 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
13071 constraint (inst.size_req == 2,
13072 _("immediate value out of range"));
13073 inst.instruction = THUMB_OP32 (inst.instruction);
13074 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
13075 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
13079 inst.instruction = THUMB_OP16 (inst.instruction);
13080 inst.instruction |= inst.operands[0].imm;
13083 set_it_insn_type (NEUTRAL_IT_INSN);
13090 do_t_ssat_usat (0);
13098 Rd = inst.operands[0].reg;
13099 Rn = inst.operands[2].reg;
13101 reject_bad_reg (Rd);
13102 reject_bad_reg (Rn);
13104 inst.instruction |= Rd << 8;
13105 inst.instruction |= inst.operands[1].imm;
13106 inst.instruction |= Rn << 16;
13109 /* Neon instruction encoder helpers. */
13111 /* Encodings for the different types for various Neon opcodes. */
13113 /* An "invalid" code for the following tables. */
13116 struct neon_tab_entry
13119 unsigned float_or_poly;
13120 unsigned scalar_or_imm;
13123 /* Map overloaded Neon opcodes to their respective encodings. */
13124 #define NEON_ENC_TAB \
13125 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13126 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13127 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13128 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13129 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13130 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13131 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13132 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13133 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13134 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13135 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13136 /* Register variants of the following two instructions are encoded as
13137 vcge / vcgt with the operands reversed. */ \
13138 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13139 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13140 X(vfma, N_INV, 0x0000c10, N_INV), \
13141 X(vfms, N_INV, 0x0200c10, N_INV), \
13142 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13143 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13144 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13145 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13146 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13147 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13148 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13149 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13150 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13151 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13152 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13153 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13154 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13155 X(vshl, 0x0000400, N_INV, 0x0800510), \
13156 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13157 X(vand, 0x0000110, N_INV, 0x0800030), \
13158 X(vbic, 0x0100110, N_INV, 0x0800030), \
13159 X(veor, 0x1000110, N_INV, N_INV), \
13160 X(vorn, 0x0300110, N_INV, 0x0800010), \
13161 X(vorr, 0x0200110, N_INV, 0x0800010), \
13162 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13163 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13164 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13165 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13166 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13167 X(vst1, 0x0000000, 0x0800000, N_INV), \
13168 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13169 X(vst2, 0x0000100, 0x0800100, N_INV), \
13170 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13171 X(vst3, 0x0000200, 0x0800200, N_INV), \
13172 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13173 X(vst4, 0x0000300, 0x0800300, N_INV), \
13174 X(vmovn, 0x1b20200, N_INV, N_INV), \
13175 X(vtrn, 0x1b20080, N_INV, N_INV), \
13176 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13177 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13178 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13179 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13180 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13181 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13182 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13183 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13184 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13185 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13186 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13187 X(vseleq, 0xe000a00, N_INV, N_INV), \
13188 X(vselvs, 0xe100a00, N_INV, N_INV), \
13189 X(vselge, 0xe200a00, N_INV, N_INV), \
13190 X(vselgt, 0xe300a00, N_INV, N_INV), \
13191 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13192 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13193 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13194 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13195 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13196 X(aes, 0x3b00300, N_INV, N_INV), \
13197 X(sha3op, 0x2000c00, N_INV, N_INV), \
13198 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13199 X(sha2op, 0x3ba0380, N_INV, N_INV)
13203 #define X(OPC,I,F,S) N_MNEM_##OPC
13208 static const struct neon_tab_entry neon_enc_tab[] =
13210 #define X(OPC,I,F,S) { (I), (F), (S) }
13215 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13216 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13217 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13218 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13219 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13220 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13221 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13222 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13223 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13224 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13225 #define NEON_ENC_SINGLE_(X) \
13226 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13227 #define NEON_ENC_DOUBLE_(X) \
13228 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13229 #define NEON_ENC_FPV8_(X) \
13230 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13232 #define NEON_ENCODE(type, inst) \
13235 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13236 inst.is_neon = 1; \
13240 #define check_neon_suffixes \
13243 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13245 as_bad (_("invalid neon suffix for non neon instruction")); \
13251 /* Define shapes for instruction operands. The following mnemonic characters
13252 are used in this table:
13254 F - VFP S<n> register
13255 D - Neon D<n> register
13256 Q - Neon Q<n> register
13260 L - D<n> register list
13262 This table is used to generate various data:
13263 - enumerations of the form NS_DDR to be used as arguments to
13265 - a table classifying shapes into single, double, quad, mixed.
13266 - a table used to drive neon_select_shape. */
13268 #define NEON_SHAPE_DEF \
13269 X(3, (D, D, D), DOUBLE), \
13270 X(3, (Q, Q, Q), QUAD), \
13271 X(3, (D, D, I), DOUBLE), \
13272 X(3, (Q, Q, I), QUAD), \
13273 X(3, (D, D, S), DOUBLE), \
13274 X(3, (Q, Q, S), QUAD), \
13275 X(2, (D, D), DOUBLE), \
13276 X(2, (Q, Q), QUAD), \
13277 X(2, (D, S), DOUBLE), \
13278 X(2, (Q, S), QUAD), \
13279 X(2, (D, R), DOUBLE), \
13280 X(2, (Q, R), QUAD), \
13281 X(2, (D, I), DOUBLE), \
13282 X(2, (Q, I), QUAD), \
13283 X(3, (D, L, D), DOUBLE), \
13284 X(2, (D, Q), MIXED), \
13285 X(2, (Q, D), MIXED), \
13286 X(3, (D, Q, I), MIXED), \
13287 X(3, (Q, D, I), MIXED), \
13288 X(3, (Q, D, D), MIXED), \
13289 X(3, (D, Q, Q), MIXED), \
13290 X(3, (Q, Q, D), MIXED), \
13291 X(3, (Q, D, S), MIXED), \
13292 X(3, (D, Q, S), MIXED), \
13293 X(4, (D, D, D, I), DOUBLE), \
13294 X(4, (Q, Q, Q, I), QUAD), \
13295 X(2, (F, F), SINGLE), \
13296 X(3, (F, F, F), SINGLE), \
13297 X(2, (F, I), SINGLE), \
13298 X(2, (F, D), MIXED), \
13299 X(2, (D, F), MIXED), \
13300 X(3, (F, F, I), MIXED), \
13301 X(4, (R, R, F, F), SINGLE), \
13302 X(4, (F, F, R, R), SINGLE), \
13303 X(3, (D, R, R), DOUBLE), \
13304 X(3, (R, R, D), DOUBLE), \
13305 X(2, (S, R), SINGLE), \
13306 X(2, (R, S), SINGLE), \
13307 X(2, (F, R), SINGLE), \
13308 X(2, (R, F), SINGLE), \
13309 /* Half float shape supported so far. */\
13310 X (2, (H, D), MIXED), \
13311 X (2, (D, H), MIXED), \
13312 X (2, (H, F), MIXED), \
13313 X (2, (F, H), MIXED), \
13314 X (2, (H, H), HALF), \
13315 X (2, (H, R), HALF), \
13316 X (2, (R, H), HALF), \
13317 X (2, (H, I), HALF), \
13318 X (3, (H, H, H), HALF), \
13319 X (3, (H, F, I), MIXED), \
13320 X (3, (F, H, I), MIXED)
13322 #define S2(A,B) NS_##A##B
13323 #define S3(A,B,C) NS_##A##B##C
13324 #define S4(A,B,C,D) NS_##A##B##C##D
13326 #define X(N, L, C) S##N L
13339 enum neon_shape_class
13348 #define X(N, L, C) SC_##C
13350 static enum neon_shape_class neon_shape_class[] =
13369 /* Register widths of above. */
13370 static unsigned neon_shape_el_size[] =
13382 struct neon_shape_info
13385 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
13388 #define S2(A,B) { SE_##A, SE_##B }
13389 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13390 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13392 #define X(N, L, C) { N, S##N L }
13394 static struct neon_shape_info neon_shape_tab[] =
13404 /* Bit masks used in type checking given instructions.
13405 'N_EQK' means the type must be the same as (or based on in some way) the key
13406 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13407 set, various other bits can be set as well in order to modify the meaning of
13408 the type constraint. */
13410 enum neon_type_mask
13434 N_KEY = 0x1000000, /* Key element (main type specifier). */
13435 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
13436 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
13437 N_UNT = 0x8000000, /* Must be explicitly untyped. */
13438 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
13439 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
13440 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13441 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13442 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13443 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
13444 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13446 N_MAX_NONSPECIAL = N_P64
13449 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13451 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13452 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13453 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13454 #define N_S_32 (N_S8 | N_S16 | N_S32)
13455 #define N_F_16_32 (N_F16 | N_F32)
13456 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13457 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13458 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13459 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13461 /* Pass this as the first type argument to neon_check_type to ignore types
13463 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13465 /* Select a "shape" for the current instruction (describing register types or
13466 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13467 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13468 function of operand parsing, so this function doesn't need to be called.
13469 Shapes should be listed in order of decreasing length. */
13471 static enum neon_shape
13472 neon_select_shape (enum neon_shape shape, ...)
13475 enum neon_shape first_shape = shape;
13477 /* Fix missing optional operands. FIXME: we don't know at this point how
13478 many arguments we should have, so this makes the assumption that we have
13479 > 1. This is true of all current Neon opcodes, I think, but may not be
13480 true in the future. */
13481 if (!inst.operands[1].present)
13482 inst.operands[1] = inst.operands[0];
13484 va_start (ap, shape);
13486 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
13491 for (j = 0; j < neon_shape_tab[shape].els; j++)
13493 if (!inst.operands[j].present)
13499 switch (neon_shape_tab[shape].el[j])
13501 /* If a .f16, .16, .u16, .s16 type specifier is given over
13502 a VFP single precision register operand, it's essentially
13503 means only half of the register is used.
13505 If the type specifier is given after the mnemonics, the
13506 information is stored in inst.vectype. If the type specifier
13507 is given after register operand, the information is stored
13508 in inst.operands[].vectype.
13510 When there is only one type specifier, and all the register
13511 operands are the same type of hardware register, the type
13512 specifier applies to all register operands.
13514 If no type specifier is given, the shape is inferred from
13515 operand information.
13518 vadd.f16 s0, s1, s2: NS_HHH
13519 vabs.f16 s0, s1: NS_HH
13520 vmov.f16 s0, r1: NS_HR
13521 vmov.f16 r0, s1: NS_RH
13522 vcvt.f16 r0, s1: NS_RH
13523 vcvt.f16.s32 s2, s2, #29: NS_HFI
13524 vcvt.f16.s32 s2, s2: NS_HF
13527 if (!(inst.operands[j].isreg
13528 && inst.operands[j].isvec
13529 && inst.operands[j].issingle
13530 && !inst.operands[j].isquad
13531 && ((inst.vectype.elems == 1
13532 && inst.vectype.el[0].size == 16)
13533 || (inst.vectype.elems > 1
13534 && inst.vectype.el[j].size == 16)
13535 || (inst.vectype.elems == 0
13536 && inst.operands[j].vectype.type != NT_invtype
13537 && inst.operands[j].vectype.size == 16))))
13542 if (!(inst.operands[j].isreg
13543 && inst.operands[j].isvec
13544 && inst.operands[j].issingle
13545 && !inst.operands[j].isquad
13546 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
13547 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
13548 || (inst.vectype.elems == 0
13549 && (inst.operands[j].vectype.size == 32
13550 || inst.operands[j].vectype.type == NT_invtype)))))
13555 if (!(inst.operands[j].isreg
13556 && inst.operands[j].isvec
13557 && !inst.operands[j].isquad
13558 && !inst.operands[j].issingle))
13563 if (!(inst.operands[j].isreg
13564 && !inst.operands[j].isvec))
13569 if (!(inst.operands[j].isreg
13570 && inst.operands[j].isvec
13571 && inst.operands[j].isquad
13572 && !inst.operands[j].issingle))
13577 if (!(!inst.operands[j].isreg
13578 && !inst.operands[j].isscalar))
13583 if (!(!inst.operands[j].isreg
13584 && inst.operands[j].isscalar))
13594 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
13595 /* We've matched all the entries in the shape table, and we don't
13596 have any left over operands which have not been matched. */
13602 if (shape == NS_NULL && first_shape != NS_NULL)
13603 first_error (_("invalid instruction shape"));
13608 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13609 means the Q bit should be set). */
13612 neon_quad (enum neon_shape shape)
13614 return neon_shape_class[shape] == SC_QUAD;
13618 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
13621 /* Allow modification to be made to types which are constrained to be
13622 based on the key element, based on bits set alongside N_EQK. */
13623 if ((typebits & N_EQK) != 0)
13625 if ((typebits & N_HLF) != 0)
13627 else if ((typebits & N_DBL) != 0)
13629 if ((typebits & N_SGN) != 0)
13630 *g_type = NT_signed;
13631 else if ((typebits & N_UNS) != 0)
13632 *g_type = NT_unsigned;
13633 else if ((typebits & N_INT) != 0)
13634 *g_type = NT_integer;
13635 else if ((typebits & N_FLT) != 0)
13636 *g_type = NT_float;
13637 else if ((typebits & N_SIZ) != 0)
13638 *g_type = NT_untyped;
13642 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13643 operand type, i.e. the single type specified in a Neon instruction when it
13644 is the only one given. */
13646 static struct neon_type_el
13647 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
13649 struct neon_type_el dest = *key;
13651 gas_assert ((thisarg & N_EQK) != 0);
13653 neon_modify_type_size (thisarg, &dest.type, &dest.size);
13658 /* Convert Neon type and size into compact bitmask representation. */
13660 static enum neon_type_mask
13661 type_chk_of_el_type (enum neon_el_type type, unsigned size)
13668 case 8: return N_8;
13669 case 16: return N_16;
13670 case 32: return N_32;
13671 case 64: return N_64;
13679 case 8: return N_I8;
13680 case 16: return N_I16;
13681 case 32: return N_I32;
13682 case 64: return N_I64;
13690 case 16: return N_F16;
13691 case 32: return N_F32;
13692 case 64: return N_F64;
13700 case 8: return N_P8;
13701 case 16: return N_P16;
13702 case 64: return N_P64;
13710 case 8: return N_S8;
13711 case 16: return N_S16;
13712 case 32: return N_S32;
13713 case 64: return N_S64;
13721 case 8: return N_U8;
13722 case 16: return N_U16;
13723 case 32: return N_U32;
13724 case 64: return N_U64;
13735 /* Convert compact Neon bitmask type representation to a type and size. Only
13736 handles the case where a single bit is set in the mask. */
13739 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
13740 enum neon_type_mask mask)
13742 if ((mask & N_EQK) != 0)
13745 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
13747 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
13749 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
13751 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
13756 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
13758 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
13759 *type = NT_unsigned;
13760 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
13761 *type = NT_integer;
13762 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
13763 *type = NT_untyped;
13764 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
13766 else if ((mask & (N_F_ALL)) != 0)
13774 /* Modify a bitmask of allowed types. This is only needed for type
13778 modify_types_allowed (unsigned allowed, unsigned mods)
13781 enum neon_el_type type;
13787 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
13789 if (el_type_of_type_chk (&type, &size,
13790 (enum neon_type_mask) (allowed & i)) == SUCCESS)
13792 neon_modify_type_size (mods, &type, &size);
13793 destmask |= type_chk_of_el_type (type, size);
13800 /* Check type and return type classification.
13801 The manual states (paraphrase): If one datatype is given, it indicates the
13803 - the second operand, if there is one
13804 - the operand, if there is no second operand
13805 - the result, if there are no operands.
13806 This isn't quite good enough though, so we use a concept of a "key" datatype
13807 which is set on a per-instruction basis, which is the one which matters when
13808 only one data type is written.
13809 Note: this function has side-effects (e.g. filling in missing operands). All
13810 Neon instructions should call it before performing bit encoding. */
13812 static struct neon_type_el
13813 neon_check_type (unsigned els, enum neon_shape ns, ...)
13816 unsigned i, pass, key_el = 0;
13817 unsigned types[NEON_MAX_TYPE_ELS];
13818 enum neon_el_type k_type = NT_invtype;
13819 unsigned k_size = -1u;
13820 struct neon_type_el badtype = {NT_invtype, -1};
13821 unsigned key_allowed = 0;
13823 /* Optional registers in Neon instructions are always (not) in operand 1.
13824 Fill in the missing operand here, if it was omitted. */
13825 if (els > 1 && !inst.operands[1].present)
13826 inst.operands[1] = inst.operands[0];
13828 /* Suck up all the varargs. */
13830 for (i = 0; i < els; i++)
13832 unsigned thisarg = va_arg (ap, unsigned);
13833 if (thisarg == N_IGNORE_TYPE)
13838 types[i] = thisarg;
13839 if ((thisarg & N_KEY) != 0)
13844 if (inst.vectype.elems > 0)
13845 for (i = 0; i < els; i++)
13846 if (inst.operands[i].vectype.type != NT_invtype)
13848 first_error (_("types specified in both the mnemonic and operands"));
13852 /* Duplicate inst.vectype elements here as necessary.
13853 FIXME: No idea if this is exactly the same as the ARM assembler,
13854 particularly when an insn takes one register and one non-register
13856 if (inst.vectype.elems == 1 && els > 1)
13859 inst.vectype.elems = els;
13860 inst.vectype.el[key_el] = inst.vectype.el[0];
13861 for (j = 0; j < els; j++)
13863 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
13866 else if (inst.vectype.elems == 0 && els > 0)
13869 /* No types were given after the mnemonic, so look for types specified
13870 after each operand. We allow some flexibility here; as long as the
13871 "key" operand has a type, we can infer the others. */
13872 for (j = 0; j < els; j++)
13873 if (inst.operands[j].vectype.type != NT_invtype)
13874 inst.vectype.el[j] = inst.operands[j].vectype;
13876 if (inst.operands[key_el].vectype.type != NT_invtype)
13878 for (j = 0; j < els; j++)
13879 if (inst.operands[j].vectype.type == NT_invtype)
13880 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
13885 first_error (_("operand types can't be inferred"));
13889 else if (inst.vectype.elems != els)
13891 first_error (_("type specifier has the wrong number of parts"));
13895 for (pass = 0; pass < 2; pass++)
13897 for (i = 0; i < els; i++)
13899 unsigned thisarg = types[i];
13900 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
13901 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
13902 enum neon_el_type g_type = inst.vectype.el[i].type;
13903 unsigned g_size = inst.vectype.el[i].size;
13905 /* Decay more-specific signed & unsigned types to sign-insensitive
13906 integer types if sign-specific variants are unavailable. */
13907 if ((g_type == NT_signed || g_type == NT_unsigned)
13908 && (types_allowed & N_SU_ALL) == 0)
13909 g_type = NT_integer;
13911 /* If only untyped args are allowed, decay any more specific types to
13912 them. Some instructions only care about signs for some element
13913 sizes, so handle that properly. */
13914 if (((types_allowed & N_UNT) == 0)
13915 && ((g_size == 8 && (types_allowed & N_8) != 0)
13916 || (g_size == 16 && (types_allowed & N_16) != 0)
13917 || (g_size == 32 && (types_allowed & N_32) != 0)
13918 || (g_size == 64 && (types_allowed & N_64) != 0)))
13919 g_type = NT_untyped;
13923 if ((thisarg & N_KEY) != 0)
13927 key_allowed = thisarg & ~N_KEY;
13929 /* Check architecture constraint on FP16 extension. */
13931 && k_type == NT_float
13932 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
13934 inst.error = _(BAD_FP16);
13941 if ((thisarg & N_VFP) != 0)
13943 enum neon_shape_el regshape;
13944 unsigned regwidth, match;
13946 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13949 first_error (_("invalid instruction shape"));
13952 regshape = neon_shape_tab[ns].el[i];
13953 regwidth = neon_shape_el_size[regshape];
13955 /* In VFP mode, operands must match register widths. If we
13956 have a key operand, use its width, else use the width of
13957 the current operand. */
13963 /* FP16 will use a single precision register. */
13964 if (regwidth == 32 && match == 16)
13966 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
13970 inst.error = _(BAD_FP16);
13975 if (regwidth != match)
13977 first_error (_("operand size must match register width"));
13982 if ((thisarg & N_EQK) == 0)
13984 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13986 if ((given_type & types_allowed) == 0)
13988 first_error (_("bad type in Neon instruction"));
13994 enum neon_el_type mod_k_type = k_type;
13995 unsigned mod_k_size = k_size;
13996 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13997 if (g_type != mod_k_type || g_size != mod_k_size)
13999 first_error (_("inconsistent types in Neon instruction"));
14007 return inst.vectype.el[key_el];
14010 /* Neon-style VFP instruction forwarding. */
14012 /* Thumb VFP instructions have 0xE in the condition field. */
14015 do_vfp_cond_or_thumb (void)
14020 inst.instruction |= 0xe0000000;
14022 inst.instruction |= inst.cond << 28;
14025 /* Look up and encode a simple mnemonic, for use as a helper function for the
14026 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14027 etc. It is assumed that operand parsing has already been done, and that the
14028 operands are in the form expected by the given opcode (this isn't necessarily
14029 the same as the form in which they were parsed, hence some massaging must
14030 take place before this function is called).
14031 Checks current arch version against that in the looked-up opcode. */
14034 do_vfp_nsyn_opcode (const char *opname)
14036 const struct asm_opcode *opcode;
14038 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
14043 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
14044 thumb_mode ? *opcode->tvariant : *opcode->avariant),
14051 inst.instruction = opcode->tvalue;
14052 opcode->tencode ();
14056 inst.instruction = (inst.cond << 28) | opcode->avalue;
14057 opcode->aencode ();
14062 do_vfp_nsyn_add_sub (enum neon_shape rs)
14064 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
14066 if (rs == NS_FFF || rs == NS_HHH)
14069 do_vfp_nsyn_opcode ("fadds");
14071 do_vfp_nsyn_opcode ("fsubs");
14073 /* ARMv8.2 fp16 instruction. */
14075 do_scalar_fp16_v82_encode ();
14080 do_vfp_nsyn_opcode ("faddd");
14082 do_vfp_nsyn_opcode ("fsubd");
14086 /* Check operand types to see if this is a VFP instruction, and if so call
14090 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
14092 enum neon_shape rs;
14093 struct neon_type_el et;
14098 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
14099 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
14103 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
14104 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14105 N_F_ALL | N_KEY | N_VFP);
14112 if (et.type != NT_invtype)
14123 do_vfp_nsyn_mla_mls (enum neon_shape rs)
14125 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
14127 if (rs == NS_FFF || rs == NS_HHH)
14130 do_vfp_nsyn_opcode ("fmacs");
14132 do_vfp_nsyn_opcode ("fnmacs");
14134 /* ARMv8.2 fp16 instruction. */
14136 do_scalar_fp16_v82_encode ();
14141 do_vfp_nsyn_opcode ("fmacd");
14143 do_vfp_nsyn_opcode ("fnmacd");
14148 do_vfp_nsyn_fma_fms (enum neon_shape rs)
14150 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
14152 if (rs == NS_FFF || rs == NS_HHH)
14155 do_vfp_nsyn_opcode ("ffmas");
14157 do_vfp_nsyn_opcode ("ffnmas");
14159 /* ARMv8.2 fp16 instruction. */
14161 do_scalar_fp16_v82_encode ();
14166 do_vfp_nsyn_opcode ("ffmad");
14168 do_vfp_nsyn_opcode ("ffnmad");
14173 do_vfp_nsyn_mul (enum neon_shape rs)
14175 if (rs == NS_FFF || rs == NS_HHH)
14177 do_vfp_nsyn_opcode ("fmuls");
14179 /* ARMv8.2 fp16 instruction. */
14181 do_scalar_fp16_v82_encode ();
14184 do_vfp_nsyn_opcode ("fmuld");
14188 do_vfp_nsyn_abs_neg (enum neon_shape rs)
14190 int is_neg = (inst.instruction & 0x80) != 0;
14191 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
14193 if (rs == NS_FF || rs == NS_HH)
14196 do_vfp_nsyn_opcode ("fnegs");
14198 do_vfp_nsyn_opcode ("fabss");
14200 /* ARMv8.2 fp16 instruction. */
14202 do_scalar_fp16_v82_encode ();
14207 do_vfp_nsyn_opcode ("fnegd");
14209 do_vfp_nsyn_opcode ("fabsd");
14213 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14214 insns belong to Neon, and are handled elsewhere. */
14217 do_vfp_nsyn_ldm_stm (int is_dbmode)
14219 int is_ldm = (inst.instruction & (1 << 20)) != 0;
14223 do_vfp_nsyn_opcode ("fldmdbs");
14225 do_vfp_nsyn_opcode ("fldmias");
14230 do_vfp_nsyn_opcode ("fstmdbs");
14232 do_vfp_nsyn_opcode ("fstmias");
14237 do_vfp_nsyn_sqrt (void)
14239 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
14240 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
14242 if (rs == NS_FF || rs == NS_HH)
14244 do_vfp_nsyn_opcode ("fsqrts");
14246 /* ARMv8.2 fp16 instruction. */
14248 do_scalar_fp16_v82_encode ();
14251 do_vfp_nsyn_opcode ("fsqrtd");
14255 do_vfp_nsyn_div (void)
14257 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
14258 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14259 N_F_ALL | N_KEY | N_VFP);
14261 if (rs == NS_FFF || rs == NS_HHH)
14263 do_vfp_nsyn_opcode ("fdivs");
14265 /* ARMv8.2 fp16 instruction. */
14267 do_scalar_fp16_v82_encode ();
14270 do_vfp_nsyn_opcode ("fdivd");
14274 do_vfp_nsyn_nmul (void)
14276 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
14277 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14278 N_F_ALL | N_KEY | N_VFP);
14280 if (rs == NS_FFF || rs == NS_HHH)
14282 NEON_ENCODE (SINGLE, inst);
14283 do_vfp_sp_dyadic ();
14285 /* ARMv8.2 fp16 instruction. */
14287 do_scalar_fp16_v82_encode ();
14291 NEON_ENCODE (DOUBLE, inst);
14292 do_vfp_dp_rd_rn_rm ();
14294 do_vfp_cond_or_thumb ();
14299 do_vfp_nsyn_cmp (void)
14301 enum neon_shape rs;
14302 if (inst.operands[1].isreg)
14304 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
14305 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
14307 if (rs == NS_FF || rs == NS_HH)
14309 NEON_ENCODE (SINGLE, inst);
14310 do_vfp_sp_monadic ();
14314 NEON_ENCODE (DOUBLE, inst);
14315 do_vfp_dp_rd_rm ();
14320 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
14321 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
14323 switch (inst.instruction & 0x0fffffff)
14326 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
14329 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
14335 if (rs == NS_FI || rs == NS_HI)
14337 NEON_ENCODE (SINGLE, inst);
14338 do_vfp_sp_compare_z ();
14342 NEON_ENCODE (DOUBLE, inst);
14346 do_vfp_cond_or_thumb ();
14348 /* ARMv8.2 fp16 instruction. */
14349 if (rs == NS_HI || rs == NS_HH)
14350 do_scalar_fp16_v82_encode ();
14354 nsyn_insert_sp (void)
14356 inst.operands[1] = inst.operands[0];
14357 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
14358 inst.operands[0].reg = REG_SP;
14359 inst.operands[0].isreg = 1;
14360 inst.operands[0].writeback = 1;
14361 inst.operands[0].present = 1;
14365 do_vfp_nsyn_push (void)
14368 if (inst.operands[1].issingle)
14369 do_vfp_nsyn_opcode ("fstmdbs");
14371 do_vfp_nsyn_opcode ("fstmdbd");
14375 do_vfp_nsyn_pop (void)
14378 if (inst.operands[1].issingle)
14379 do_vfp_nsyn_opcode ("fldmias");
14381 do_vfp_nsyn_opcode ("fldmiad");
14384 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14385 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14388 neon_dp_fixup (struct arm_it* insn)
14390 unsigned int i = insn->instruction;
14395 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14406 insn->instruction = i;
14409 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14413 neon_logbits (unsigned x)
14415 return ffs (x) - 4;
14418 #define LOW4(R) ((R) & 0xf)
14419 #define HI1(R) (((R) >> 4) & 1)
14421 /* Encode insns with bit pattern:
14423 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14424 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14426 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14427 different meaning for some instruction. */
14430 neon_three_same (int isquad, int ubit, int size)
14432 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14433 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14434 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14435 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14436 inst.instruction |= LOW4 (inst.operands[2].reg);
14437 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14438 inst.instruction |= (isquad != 0) << 6;
14439 inst.instruction |= (ubit != 0) << 24;
14441 inst.instruction |= neon_logbits (size) << 20;
14443 neon_dp_fixup (&inst);
14446 /* Encode instructions of the form:
14448 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14449 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14451 Don't write size if SIZE == -1. */
14454 neon_two_same (int qbit, int ubit, int size)
14456 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14457 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14458 inst.instruction |= LOW4 (inst.operands[1].reg);
14459 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14460 inst.instruction |= (qbit != 0) << 6;
14461 inst.instruction |= (ubit != 0) << 24;
14464 inst.instruction |= neon_logbits (size) << 18;
14466 neon_dp_fixup (&inst);
14469 /* Neon instruction encoders, in approximate order of appearance. */
14472 do_neon_dyadic_i_su (void)
14474 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14475 struct neon_type_el et = neon_check_type (3, rs,
14476 N_EQK, N_EQK, N_SU_32 | N_KEY);
14477 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14481 do_neon_dyadic_i64_su (void)
14483 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14484 struct neon_type_el et = neon_check_type (3, rs,
14485 N_EQK, N_EQK, N_SU_ALL | N_KEY);
14486 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14490 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
14493 unsigned size = et.size >> 3;
14494 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14495 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14496 inst.instruction |= LOW4 (inst.operands[1].reg);
14497 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14498 inst.instruction |= (isquad != 0) << 6;
14499 inst.instruction |= immbits << 16;
14500 inst.instruction |= (size >> 3) << 7;
14501 inst.instruction |= (size & 0x7) << 19;
14503 inst.instruction |= (uval != 0) << 24;
14505 neon_dp_fixup (&inst);
14509 do_neon_shl_imm (void)
14511 if (!inst.operands[2].isreg)
14513 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14514 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
14515 int imm = inst.operands[2].imm;
14517 constraint (imm < 0 || (unsigned)imm >= et.size,
14518 _("immediate out of range for shift"));
14519 NEON_ENCODE (IMMED, inst);
14520 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14524 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14525 struct neon_type_el et = neon_check_type (3, rs,
14526 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
14529 /* VSHL/VQSHL 3-register variants have syntax such as:
14531 whereas other 3-register operations encoded by neon_three_same have
14534 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14536 tmp = inst.operands[2].reg;
14537 inst.operands[2].reg = inst.operands[1].reg;
14538 inst.operands[1].reg = tmp;
14539 NEON_ENCODE (INTEGER, inst);
14540 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14545 do_neon_qshl_imm (void)
14547 if (!inst.operands[2].isreg)
14549 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14550 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
14551 int imm = inst.operands[2].imm;
14553 constraint (imm < 0 || (unsigned)imm >= et.size,
14554 _("immediate out of range for shift"));
14555 NEON_ENCODE (IMMED, inst);
14556 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
14560 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14561 struct neon_type_el et = neon_check_type (3, rs,
14562 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
14565 /* See note in do_neon_shl_imm. */
14566 tmp = inst.operands[2].reg;
14567 inst.operands[2].reg = inst.operands[1].reg;
14568 inst.operands[1].reg = tmp;
14569 NEON_ENCODE (INTEGER, inst);
14570 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14575 do_neon_rshl (void)
14577 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14578 struct neon_type_el et = neon_check_type (3, rs,
14579 N_EQK, N_EQK, N_SU_ALL | N_KEY);
14582 tmp = inst.operands[2].reg;
14583 inst.operands[2].reg = inst.operands[1].reg;
14584 inst.operands[1].reg = tmp;
14585 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14589 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
14591 /* Handle .I8 pseudo-instructions. */
14594 /* Unfortunately, this will make everything apart from zero out-of-range.
14595 FIXME is this the intended semantics? There doesn't seem much point in
14596 accepting .I8 if so. */
14597 immediate |= immediate << 8;
14603 if (immediate == (immediate & 0x000000ff))
14605 *immbits = immediate;
14608 else if (immediate == (immediate & 0x0000ff00))
14610 *immbits = immediate >> 8;
14613 else if (immediate == (immediate & 0x00ff0000))
14615 *immbits = immediate >> 16;
14618 else if (immediate == (immediate & 0xff000000))
14620 *immbits = immediate >> 24;
14623 if ((immediate & 0xffff) != (immediate >> 16))
14624 goto bad_immediate;
14625 immediate &= 0xffff;
14628 if (immediate == (immediate & 0x000000ff))
14630 *immbits = immediate;
14633 else if (immediate == (immediate & 0x0000ff00))
14635 *immbits = immediate >> 8;
14640 first_error (_("immediate value out of range"));
14645 do_neon_logic (void)
14647 if (inst.operands[2].present && inst.operands[2].isreg)
14649 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14650 neon_check_type (3, rs, N_IGNORE_TYPE);
14651 /* U bit and size field were set as part of the bitmask. */
14652 NEON_ENCODE (INTEGER, inst);
14653 neon_three_same (neon_quad (rs), 0, -1);
14657 const int three_ops_form = (inst.operands[2].present
14658 && !inst.operands[2].isreg);
14659 const int immoperand = (three_ops_form ? 2 : 1);
14660 enum neon_shape rs = (three_ops_form
14661 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
14662 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
14663 struct neon_type_el et = neon_check_type (2, rs,
14664 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14665 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
14669 if (et.type == NT_invtype)
14672 if (three_ops_form)
14673 constraint (inst.operands[0].reg != inst.operands[1].reg,
14674 _("first and second operands shall be the same register"));
14676 NEON_ENCODE (IMMED, inst);
14678 immbits = inst.operands[immoperand].imm;
14681 /* .i64 is a pseudo-op, so the immediate must be a repeating
14683 if (immbits != (inst.operands[immoperand].regisimm ?
14684 inst.operands[immoperand].reg : 0))
14686 /* Set immbits to an invalid constant. */
14687 immbits = 0xdeadbeef;
14694 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14698 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14702 /* Pseudo-instruction for VBIC. */
14703 neon_invert_size (&immbits, 0, et.size);
14704 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14708 /* Pseudo-instruction for VORR. */
14709 neon_invert_size (&immbits, 0, et.size);
14710 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14720 inst.instruction |= neon_quad (rs) << 6;
14721 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14722 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14723 inst.instruction |= cmode << 8;
14724 neon_write_immbits (immbits);
14726 neon_dp_fixup (&inst);
14731 do_neon_bitfield (void)
14733 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14734 neon_check_type (3, rs, N_IGNORE_TYPE);
14735 neon_three_same (neon_quad (rs), 0, -1);
14739 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
14742 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14743 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
14745 if (et.type == NT_float)
14747 NEON_ENCODE (FLOAT, inst);
14748 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
14752 NEON_ENCODE (INTEGER, inst);
14753 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
14758 do_neon_dyadic_if_su (void)
14760 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
14764 do_neon_dyadic_if_su_d (void)
14766 /* This version only allow D registers, but that constraint is enforced during
14767 operand parsing so we don't need to do anything extra here. */
14768 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
14772 do_neon_dyadic_if_i_d (void)
14774 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14775 affected if we specify unsigned args. */
14776 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14779 enum vfp_or_neon_is_neon_bits
14782 NEON_CHECK_ARCH = 2,
14783 NEON_CHECK_ARCH8 = 4
14786 /* Call this function if an instruction which may have belonged to the VFP or
14787 Neon instruction sets, but turned out to be a Neon instruction (due to the
14788 operand types involved, etc.). We have to check and/or fix-up a couple of
14791 - Make sure the user hasn't attempted to make a Neon instruction
14793 - Alter the value in the condition code field if necessary.
14794 - Make sure that the arch supports Neon instructions.
14796 Which of these operations take place depends on bits from enum
14797 vfp_or_neon_is_neon_bits.
14799 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14800 current instruction's condition is COND_ALWAYS, the condition field is
14801 changed to inst.uncond_value. This is necessary because instructions shared
14802 between VFP and Neon may be conditional for the VFP variants only, and the
14803 unconditional Neon version must have, e.g., 0xF in the condition field. */
14806 vfp_or_neon_is_neon (unsigned check)
14808 /* Conditions are always legal in Thumb mode (IT blocks). */
14809 if (!thumb_mode && (check & NEON_CHECK_CC))
14811 if (inst.cond != COND_ALWAYS)
14813 first_error (_(BAD_COND));
14816 if (inst.uncond_value != -1)
14817 inst.instruction |= inst.uncond_value << 28;
14820 if ((check & NEON_CHECK_ARCH)
14821 && !mark_feature_used (&fpu_neon_ext_v1))
14823 first_error (_(BAD_FPU));
14827 if ((check & NEON_CHECK_ARCH8)
14828 && !mark_feature_used (&fpu_neon_ext_armv8))
14830 first_error (_(BAD_FPU));
14838 do_neon_addsub_if_i (void)
14840 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14843 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14846 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14847 affected if we specify unsigned args. */
14848 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14851 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14853 V<op> A,B (A is operand 0, B is operand 2)
14858 so handle that case specially. */
14861 neon_exchange_operands (void)
14863 if (inst.operands[1].present)
14865 void *scratch = xmalloc (sizeof (inst.operands[0]));
14867 /* Swap operands[1] and operands[2]. */
14868 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14869 inst.operands[1] = inst.operands[2];
14870 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14875 inst.operands[1] = inst.operands[2];
14876 inst.operands[2] = inst.operands[0];
14881 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14883 if (inst.operands[2].isreg)
14886 neon_exchange_operands ();
14887 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14891 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14892 struct neon_type_el et = neon_check_type (2, rs,
14893 N_EQK | N_SIZ, immtypes | N_KEY);
14895 NEON_ENCODE (IMMED, inst);
14896 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14897 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14898 inst.instruction |= LOW4 (inst.operands[1].reg);
14899 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14900 inst.instruction |= neon_quad (rs) << 6;
14901 inst.instruction |= (et.type == NT_float) << 10;
14902 inst.instruction |= neon_logbits (et.size) << 18;
14904 neon_dp_fixup (&inst);
14911 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
14915 do_neon_cmp_inv (void)
14917 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
14923 neon_compare (N_IF_32, N_IF_32, FALSE);
14926 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14927 scalars, which are encoded in 5 bits, M : Rm.
14928 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14929 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14933 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14935 unsigned regno = NEON_SCALAR_REG (scalar);
14936 unsigned elno = NEON_SCALAR_INDEX (scalar);
14941 if (regno > 7 || elno > 3)
14943 return regno | (elno << 3);
14946 if (regno > 15 || elno > 1)
14948 return regno | (elno << 4);
14952 first_error (_("scalar out of range for multiply instruction"));
14958 /* Encode multiply / multiply-accumulate scalar instructions. */
14961 neon_mul_mac (struct neon_type_el et, int ubit)
14965 /* Give a more helpful error message if we have an invalid type. */
14966 if (et.type == NT_invtype)
14969 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14970 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14971 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14972 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14973 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14974 inst.instruction |= LOW4 (scalar);
14975 inst.instruction |= HI1 (scalar) << 5;
14976 inst.instruction |= (et.type == NT_float) << 8;
14977 inst.instruction |= neon_logbits (et.size) << 20;
14978 inst.instruction |= (ubit != 0) << 24;
14980 neon_dp_fixup (&inst);
14984 do_neon_mac_maybe_scalar (void)
14986 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14989 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14992 if (inst.operands[2].isscalar)
14994 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14995 struct neon_type_el et = neon_check_type (3, rs,
14996 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14997 NEON_ENCODE (SCALAR, inst);
14998 neon_mul_mac (et, neon_quad (rs));
15002 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15003 affected if we specify unsigned args. */
15004 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
15009 do_neon_fmac (void)
15011 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
15014 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15017 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
15023 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15024 struct neon_type_el et = neon_check_type (3, rs,
15025 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
15026 neon_three_same (neon_quad (rs), 0, et.size);
15029 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15030 same types as the MAC equivalents. The polynomial type for this instruction
15031 is encoded the same as the integer type. */
15036 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
15039 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15042 if (inst.operands[2].isscalar)
15043 do_neon_mac_maybe_scalar ();
15045 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
15049 do_neon_qdmulh (void)
15051 if (inst.operands[2].isscalar)
15053 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
15054 struct neon_type_el et = neon_check_type (3, rs,
15055 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15056 NEON_ENCODE (SCALAR, inst);
15057 neon_mul_mac (et, neon_quad (rs));
15061 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15062 struct neon_type_el et = neon_check_type (3, rs,
15063 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15064 NEON_ENCODE (INTEGER, inst);
15065 /* The U bit (rounding) comes from bit mask. */
15066 neon_three_same (neon_quad (rs), 0, et.size);
15071 do_neon_qrdmlah (void)
15073 /* Check we're on the correct architecture. */
15074 if (!mark_feature_used (&fpu_neon_ext_armv8))
15076 _("instruction form not available on this architecture.");
15077 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
15079 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15080 record_feature_use (&fpu_neon_ext_v8_1);
15083 if (inst.operands[2].isscalar)
15085 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
15086 struct neon_type_el et = neon_check_type (3, rs,
15087 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15088 NEON_ENCODE (SCALAR, inst);
15089 neon_mul_mac (et, neon_quad (rs));
15093 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15094 struct neon_type_el et = neon_check_type (3, rs,
15095 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15096 NEON_ENCODE (INTEGER, inst);
15097 /* The U bit (rounding) comes from bit mask. */
15098 neon_three_same (neon_quad (rs), 0, et.size);
15103 do_neon_fcmp_absolute (void)
15105 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15106 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
15107 N_F_16_32 | N_KEY);
15108 /* Size field comes from bit mask. */
15109 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
15113 do_neon_fcmp_absolute_inv (void)
15115 neon_exchange_operands ();
15116 do_neon_fcmp_absolute ();
15120 do_neon_step (void)
15122 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15123 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
15124 N_F_16_32 | N_KEY);
15125 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
15129 do_neon_abs_neg (void)
15131 enum neon_shape rs;
15132 struct neon_type_el et;
15134 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
15137 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15140 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15141 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
15143 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15144 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15145 inst.instruction |= LOW4 (inst.operands[1].reg);
15146 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15147 inst.instruction |= neon_quad (rs) << 6;
15148 inst.instruction |= (et.type == NT_float) << 10;
15149 inst.instruction |= neon_logbits (et.size) << 18;
15151 neon_dp_fixup (&inst);
15157 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15158 struct neon_type_el et = neon_check_type (2, rs,
15159 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15160 int imm = inst.operands[2].imm;
15161 constraint (imm < 0 || (unsigned)imm >= et.size,
15162 _("immediate out of range for insert"));
15163 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
15169 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15170 struct neon_type_el et = neon_check_type (2, rs,
15171 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15172 int imm = inst.operands[2].imm;
15173 constraint (imm < 1 || (unsigned)imm > et.size,
15174 _("immediate out of range for insert"));
15175 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
15179 do_neon_qshlu_imm (void)
15181 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15182 struct neon_type_el et = neon_check_type (2, rs,
15183 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
15184 int imm = inst.operands[2].imm;
15185 constraint (imm < 0 || (unsigned)imm >= et.size,
15186 _("immediate out of range for shift"));
15187 /* Only encodes the 'U present' variant of the instruction.
15188 In this case, signed types have OP (bit 8) set to 0.
15189 Unsigned types have OP set to 1. */
15190 inst.instruction |= (et.type == NT_unsigned) << 8;
15191 /* The rest of the bits are the same as other immediate shifts. */
15192 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
15196 do_neon_qmovn (void)
15198 struct neon_type_el et = neon_check_type (2, NS_DQ,
15199 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
15200 /* Saturating move where operands can be signed or unsigned, and the
15201 destination has the same signedness. */
15202 NEON_ENCODE (INTEGER, inst);
15203 if (et.type == NT_unsigned)
15204 inst.instruction |= 0xc0;
15206 inst.instruction |= 0x80;
15207 neon_two_same (0, 1, et.size / 2);
15211 do_neon_qmovun (void)
15213 struct neon_type_el et = neon_check_type (2, NS_DQ,
15214 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
15215 /* Saturating move with unsigned results. Operands must be signed. */
15216 NEON_ENCODE (INTEGER, inst);
15217 neon_two_same (0, 1, et.size / 2);
15221 do_neon_rshift_sat_narrow (void)
15223 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15224 or unsigned. If operands are unsigned, results must also be unsigned. */
15225 struct neon_type_el et = neon_check_type (2, NS_DQI,
15226 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
15227 int imm = inst.operands[2].imm;
15228 /* This gets the bounds check, size encoding and immediate bits calculation
15232 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15233 VQMOVN.I<size> <Dd>, <Qm>. */
15236 inst.operands[2].present = 0;
15237 inst.instruction = N_MNEM_vqmovn;
15242 constraint (imm < 1 || (unsigned)imm > et.size,
15243 _("immediate out of range"));
15244 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
15248 do_neon_rshift_sat_narrow_u (void)
15250 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15251 or unsigned. If operands are unsigned, results must also be unsigned. */
15252 struct neon_type_el et = neon_check_type (2, NS_DQI,
15253 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
15254 int imm = inst.operands[2].imm;
15255 /* This gets the bounds check, size encoding and immediate bits calculation
15259 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15260 VQMOVUN.I<size> <Dd>, <Qm>. */
15263 inst.operands[2].present = 0;
15264 inst.instruction = N_MNEM_vqmovun;
15269 constraint (imm < 1 || (unsigned)imm > et.size,
15270 _("immediate out of range"));
15271 /* FIXME: The manual is kind of unclear about what value U should have in
15272 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15274 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
15278 do_neon_movn (void)
15280 struct neon_type_el et = neon_check_type (2, NS_DQ,
15281 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
15282 NEON_ENCODE (INTEGER, inst);
15283 neon_two_same (0, 1, et.size / 2);
15287 do_neon_rshift_narrow (void)
15289 struct neon_type_el et = neon_check_type (2, NS_DQI,
15290 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
15291 int imm = inst.operands[2].imm;
15292 /* This gets the bounds check, size encoding and immediate bits calculation
15296 /* If immediate is zero then we are a pseudo-instruction for
15297 VMOVN.I<size> <Dd>, <Qm> */
15300 inst.operands[2].present = 0;
15301 inst.instruction = N_MNEM_vmovn;
15306 constraint (imm < 1 || (unsigned)imm > et.size,
15307 _("immediate out of range for narrowing operation"));
15308 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
15312 do_neon_shll (void)
15314 /* FIXME: Type checking when lengthening. */
15315 struct neon_type_el et = neon_check_type (2, NS_QDI,
15316 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
15317 unsigned imm = inst.operands[2].imm;
15319 if (imm == et.size)
15321 /* Maximum shift variant. */
15322 NEON_ENCODE (INTEGER, inst);
15323 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15324 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15325 inst.instruction |= LOW4 (inst.operands[1].reg);
15326 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15327 inst.instruction |= neon_logbits (et.size) << 18;
15329 neon_dp_fixup (&inst);
15333 /* A more-specific type check for non-max versions. */
15334 et = neon_check_type (2, NS_QDI,
15335 N_EQK | N_DBL, N_SU_32 | N_KEY);
15336 NEON_ENCODE (IMMED, inst);
15337 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
15341 /* Check the various types for the VCVT instruction, and return which version
15342 the current instruction is. */
15344 #define CVT_FLAVOUR_VAR \
15345 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15346 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15347 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15348 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15349 /* Half-precision conversions. */ \
15350 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15351 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15352 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15353 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15354 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15355 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15356 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15357 Compared with single/double precision variants, only the co-processor \
15358 field is different, so the encoding flow is reused here. */ \
15359 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15360 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15361 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15362 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15363 /* VFP instructions. */ \
15364 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15365 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15366 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15367 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15368 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15369 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15370 /* VFP instructions with bitshift. */ \
15371 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15372 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15373 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15374 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15375 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15376 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15377 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15378 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15380 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15381 neon_cvt_flavour_##C,
15383 /* The different types of conversions we can do. */
15384 enum neon_cvt_flavour
15387 neon_cvt_flavour_invalid,
15388 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
15393 static enum neon_cvt_flavour
15394 get_neon_cvt_flavour (enum neon_shape rs)
15396 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15397 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15398 if (et.type != NT_invtype) \
15400 inst.error = NULL; \
15401 return (neon_cvt_flavour_##C); \
15404 struct neon_type_el et;
15405 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
15406 || rs == NS_FF) ? N_VFP : 0;
15407 /* The instruction versions which take an immediate take one register
15408 argument, which is extended to the width of the full register. Thus the
15409 "source" and "destination" registers must have the same width. Hack that
15410 here by making the size equal to the key (wider, in this case) operand. */
15411 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
15415 return neon_cvt_flavour_invalid;
15430 /* Neon-syntax VFP conversions. */
15433 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
15435 const char *opname = 0;
15437 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
15438 || rs == NS_FHI || rs == NS_HFI)
15440 /* Conversions with immediate bitshift. */
15441 const char *enc[] =
15443 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15449 if (flavour < (int) ARRAY_SIZE (enc))
15451 opname = enc[flavour];
15452 constraint (inst.operands[0].reg != inst.operands[1].reg,
15453 _("operands 0 and 1 must be the same register"));
15454 inst.operands[1] = inst.operands[2];
15455 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
15460 /* Conversions without bitshift. */
15461 const char *enc[] =
15463 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15469 if (flavour < (int) ARRAY_SIZE (enc))
15470 opname = enc[flavour];
15474 do_vfp_nsyn_opcode (opname);
15476 /* ARMv8.2 fp16 VCVT instruction. */
15477 if (flavour == neon_cvt_flavour_s32_f16
15478 || flavour == neon_cvt_flavour_u32_f16
15479 || flavour == neon_cvt_flavour_f16_u32
15480 || flavour == neon_cvt_flavour_f16_s32)
15481 do_scalar_fp16_v82_encode ();
15485 do_vfp_nsyn_cvtz (void)
15487 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
15488 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
15489 const char *enc[] =
15491 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15497 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
15498 do_vfp_nsyn_opcode (enc[flavour]);
15502 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
15503 enum neon_cvt_mode mode)
15508 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15509 D register operands. */
15510 if (flavour == neon_cvt_flavour_s32_f64
15511 || flavour == neon_cvt_flavour_u32_f64)
15512 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15515 if (flavour == neon_cvt_flavour_s32_f16
15516 || flavour == neon_cvt_flavour_u32_f16)
15517 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
15520 set_it_insn_type (OUTSIDE_IT_INSN);
15524 case neon_cvt_flavour_s32_f64:
15528 case neon_cvt_flavour_s32_f32:
15532 case neon_cvt_flavour_s32_f16:
15536 case neon_cvt_flavour_u32_f64:
15540 case neon_cvt_flavour_u32_f32:
15544 case neon_cvt_flavour_u32_f16:
15549 first_error (_("invalid instruction shape"));
15555 case neon_cvt_mode_a: rm = 0; break;
15556 case neon_cvt_mode_n: rm = 1; break;
15557 case neon_cvt_mode_p: rm = 2; break;
15558 case neon_cvt_mode_m: rm = 3; break;
15559 default: first_error (_("invalid rounding mode")); return;
15562 NEON_ENCODE (FPV8, inst);
15563 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
15564 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
15565 inst.instruction |= sz << 8;
15567 /* ARMv8.2 fp16 VCVT instruction. */
15568 if (flavour == neon_cvt_flavour_s32_f16
15569 ||flavour == neon_cvt_flavour_u32_f16)
15570 do_scalar_fp16_v82_encode ();
15571 inst.instruction |= op << 7;
15572 inst.instruction |= rm << 16;
15573 inst.instruction |= 0xf0000000;
15574 inst.is_neon = TRUE;
15578 do_neon_cvt_1 (enum neon_cvt_mode mode)
15580 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
15581 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
15582 NS_FH, NS_HF, NS_FHI, NS_HFI,
15584 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
15586 if (flavour == neon_cvt_flavour_invalid)
15589 /* PR11109: Handle round-to-zero for VCVT conversions. */
15590 if (mode == neon_cvt_mode_z
15591 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
15592 && (flavour == neon_cvt_flavour_s16_f16
15593 || flavour == neon_cvt_flavour_u16_f16
15594 || flavour == neon_cvt_flavour_s32_f32
15595 || flavour == neon_cvt_flavour_u32_f32
15596 || flavour == neon_cvt_flavour_s32_f64
15597 || flavour == neon_cvt_flavour_u32_f64)
15598 && (rs == NS_FD || rs == NS_FF))
15600 do_vfp_nsyn_cvtz ();
15604 /* ARMv8.2 fp16 VCVT conversions. */
15605 if (mode == neon_cvt_mode_z
15606 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
15607 && (flavour == neon_cvt_flavour_s32_f16
15608 || flavour == neon_cvt_flavour_u32_f16)
15611 do_vfp_nsyn_cvtz ();
15612 do_scalar_fp16_v82_encode ();
15616 /* VFP rather than Neon conversions. */
15617 if (flavour >= neon_cvt_flavour_first_fp)
15619 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15620 do_vfp_nsyn_cvt (rs, flavour);
15622 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
15633 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15634 0x0000100, 0x1000100, 0x0, 0x1000000};
15636 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15639 /* Fixed-point conversion with #0 immediate is encoded as an
15640 integer conversion. */
15641 if (inst.operands[2].present && inst.operands[2].imm == 0)
15643 NEON_ENCODE (IMMED, inst);
15644 if (flavour != neon_cvt_flavour_invalid)
15645 inst.instruction |= enctab[flavour];
15646 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15647 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15648 inst.instruction |= LOW4 (inst.operands[1].reg);
15649 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15650 inst.instruction |= neon_quad (rs) << 6;
15651 inst.instruction |= 1 << 21;
15652 if (flavour < neon_cvt_flavour_s16_f16)
15654 inst.instruction |= 1 << 21;
15655 immbits = 32 - inst.operands[2].imm;
15656 inst.instruction |= immbits << 16;
15660 inst.instruction |= 3 << 20;
15661 immbits = 16 - inst.operands[2].imm;
15662 inst.instruction |= immbits << 16;
15663 inst.instruction &= ~(1 << 9);
15666 neon_dp_fixup (&inst);
15672 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
15674 NEON_ENCODE (FLOAT, inst);
15675 set_it_insn_type (OUTSIDE_IT_INSN);
15677 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
15680 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15681 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15682 inst.instruction |= LOW4 (inst.operands[1].reg);
15683 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15684 inst.instruction |= neon_quad (rs) << 6;
15685 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
15686 || flavour == neon_cvt_flavour_u32_f32) << 7;
15687 inst.instruction |= mode << 8;
15688 if (flavour == neon_cvt_flavour_u16_f16
15689 || flavour == neon_cvt_flavour_s16_f16)
15690 /* Mask off the original size bits and reencode them. */
15691 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
15694 inst.instruction |= 0xfc000000;
15696 inst.instruction |= 0xf0000000;
15702 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
15703 0x100, 0x180, 0x0, 0x080};
15705 NEON_ENCODE (INTEGER, inst);
15707 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15710 if (flavour != neon_cvt_flavour_invalid)
15711 inst.instruction |= enctab[flavour];
15713 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15714 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15715 inst.instruction |= LOW4 (inst.operands[1].reg);
15716 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15717 inst.instruction |= neon_quad (rs) << 6;
15718 if (flavour >= neon_cvt_flavour_s16_f16
15719 && flavour <= neon_cvt_flavour_f16_u16)
15720 /* Half precision. */
15721 inst.instruction |= 1 << 18;
15723 inst.instruction |= 2 << 18;
15725 neon_dp_fixup (&inst);
15730 /* Half-precision conversions for Advanced SIMD -- neon. */
15735 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
15737 as_bad (_("operand size must match register width"));
15742 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
15744 as_bad (_("operand size must match register width"));
15749 inst.instruction = 0x3b60600;
15751 inst.instruction = 0x3b60700;
15753 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15754 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15755 inst.instruction |= LOW4 (inst.operands[1].reg);
15756 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15757 neon_dp_fixup (&inst);
15761 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15762 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15763 do_vfp_nsyn_cvt (rs, flavour);
15765 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
15770 do_neon_cvtr (void)
15772 do_neon_cvt_1 (neon_cvt_mode_x);
15778 do_neon_cvt_1 (neon_cvt_mode_z);
15782 do_neon_cvta (void)
15784 do_neon_cvt_1 (neon_cvt_mode_a);
15788 do_neon_cvtn (void)
15790 do_neon_cvt_1 (neon_cvt_mode_n);
15794 do_neon_cvtp (void)
15796 do_neon_cvt_1 (neon_cvt_mode_p);
15800 do_neon_cvtm (void)
15802 do_neon_cvt_1 (neon_cvt_mode_m);
15806 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
15809 mark_feature_used (&fpu_vfp_ext_armv8);
15811 encode_arm_vfp_reg (inst.operands[0].reg,
15812 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
15813 encode_arm_vfp_reg (inst.operands[1].reg,
15814 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
15815 inst.instruction |= to ? 0x10000 : 0;
15816 inst.instruction |= t ? 0x80 : 0;
15817 inst.instruction |= is_double ? 0x100 : 0;
15818 do_vfp_cond_or_thumb ();
15822 do_neon_cvttb_1 (bfd_boolean t)
15824 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
15825 NS_DF, NS_DH, NS_NULL);
15829 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
15832 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
15834 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
15837 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
15839 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
15841 /* The VCVTB and VCVTT instructions with D-register operands
15842 don't work for SP only targets. */
15843 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15847 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
15849 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
15851 /* The VCVTB and VCVTT instructions with D-register operands
15852 don't work for SP only targets. */
15853 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15857 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
15864 do_neon_cvtb (void)
15866 do_neon_cvttb_1 (FALSE);
15871 do_neon_cvtt (void)
15873 do_neon_cvttb_1 (TRUE);
15877 neon_move_immediate (void)
15879 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
15880 struct neon_type_el et = neon_check_type (2, rs,
15881 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
15882 unsigned immlo, immhi = 0, immbits;
15883 int op, cmode, float_p;
15885 constraint (et.type == NT_invtype,
15886 _("operand size must be specified for immediate VMOV"));
15888 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15889 op = (inst.instruction & (1 << 5)) != 0;
15891 immlo = inst.operands[1].imm;
15892 if (inst.operands[1].regisimm)
15893 immhi = inst.operands[1].reg;
15895 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
15896 _("immediate has bits set outside the operand size"));
15898 float_p = inst.operands[1].immisfloat;
15900 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
15901 et.size, et.type)) == FAIL)
15903 /* Invert relevant bits only. */
15904 neon_invert_size (&immlo, &immhi, et.size);
15905 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15906 with one or the other; those cases are caught by
15907 neon_cmode_for_move_imm. */
15909 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
15910 &op, et.size, et.type)) == FAIL)
15912 first_error (_("immediate out of range"));
15917 inst.instruction &= ~(1 << 5);
15918 inst.instruction |= op << 5;
15920 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15921 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15922 inst.instruction |= neon_quad (rs) << 6;
15923 inst.instruction |= cmode << 8;
15925 neon_write_immbits (immbits);
15931 if (inst.operands[1].isreg)
15933 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15935 NEON_ENCODE (INTEGER, inst);
15936 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15937 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15938 inst.instruction |= LOW4 (inst.operands[1].reg);
15939 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15940 inst.instruction |= neon_quad (rs) << 6;
15944 NEON_ENCODE (IMMED, inst);
15945 neon_move_immediate ();
15948 neon_dp_fixup (&inst);
15951 /* Encode instructions of form:
15953 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15954 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15957 neon_mixed_length (struct neon_type_el et, unsigned size)
15959 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15960 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15961 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15962 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15963 inst.instruction |= LOW4 (inst.operands[2].reg);
15964 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15965 inst.instruction |= (et.type == NT_unsigned) << 24;
15966 inst.instruction |= neon_logbits (size) << 20;
15968 neon_dp_fixup (&inst);
15972 do_neon_dyadic_long (void)
15974 /* FIXME: Type checking for lengthening op. */
15975 struct neon_type_el et = neon_check_type (3, NS_QDD,
15976 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15977 neon_mixed_length (et, et.size);
15981 do_neon_abal (void)
15983 struct neon_type_el et = neon_check_type (3, NS_QDD,
15984 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15985 neon_mixed_length (et, et.size);
15989 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15991 if (inst.operands[2].isscalar)
15993 struct neon_type_el et = neon_check_type (3, NS_QDS,
15994 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
15995 NEON_ENCODE (SCALAR, inst);
15996 neon_mul_mac (et, et.type == NT_unsigned);
16000 struct neon_type_el et = neon_check_type (3, NS_QDD,
16001 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
16002 NEON_ENCODE (INTEGER, inst);
16003 neon_mixed_length (et, et.size);
16008 do_neon_mac_maybe_scalar_long (void)
16010 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
16014 do_neon_dyadic_wide (void)
16016 struct neon_type_el et = neon_check_type (3, NS_QQD,
16017 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
16018 neon_mixed_length (et, et.size);
16022 do_neon_dyadic_narrow (void)
16024 struct neon_type_el et = neon_check_type (3, NS_QDD,
16025 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
16026 /* Operand sign is unimportant, and the U bit is part of the opcode,
16027 so force the operand type to integer. */
16028 et.type = NT_integer;
16029 neon_mixed_length (et, et.size / 2);
16033 do_neon_mul_sat_scalar_long (void)
16035 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
16039 do_neon_vmull (void)
16041 if (inst.operands[2].isscalar)
16042 do_neon_mac_maybe_scalar_long ();
16045 struct neon_type_el et = neon_check_type (3, NS_QDD,
16046 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
16048 if (et.type == NT_poly)
16049 NEON_ENCODE (POLY, inst);
16051 NEON_ENCODE (INTEGER, inst);
16053 /* For polynomial encoding the U bit must be zero, and the size must
16054 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16055 obviously, as 0b10). */
16058 /* Check we're on the correct architecture. */
16059 if (!mark_feature_used (&fpu_crypto_ext_armv8))
16061 _("Instruction form not available on this architecture.");
16066 neon_mixed_length (et, et.size);
16073 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
16074 struct neon_type_el et = neon_check_type (3, rs,
16075 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
16076 unsigned imm = (inst.operands[3].imm * et.size) / 8;
16078 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
16079 _("shift out of range"));
16080 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16081 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16082 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16083 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16084 inst.instruction |= LOW4 (inst.operands[2].reg);
16085 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16086 inst.instruction |= neon_quad (rs) << 6;
16087 inst.instruction |= imm << 8;
16089 neon_dp_fixup (&inst);
16095 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16096 struct neon_type_el et = neon_check_type (2, rs,
16097 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16098 unsigned op = (inst.instruction >> 7) & 3;
16099 /* N (width of reversed regions) is encoded as part of the bitmask. We
16100 extract it here to check the elements to be reversed are smaller.
16101 Otherwise we'd get a reserved instruction. */
16102 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
16103 gas_assert (elsize != 0);
16104 constraint (et.size >= elsize,
16105 _("elements must be smaller than reversal region"));
16106 neon_two_same (neon_quad (rs), 1, et.size);
16112 if (inst.operands[1].isscalar)
16114 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
16115 struct neon_type_el et = neon_check_type (2, rs,
16116 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16117 unsigned sizebits = et.size >> 3;
16118 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
16119 int logsize = neon_logbits (et.size);
16120 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
16122 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
16125 NEON_ENCODE (SCALAR, inst);
16126 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16127 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16128 inst.instruction |= LOW4 (dm);
16129 inst.instruction |= HI1 (dm) << 5;
16130 inst.instruction |= neon_quad (rs) << 6;
16131 inst.instruction |= x << 17;
16132 inst.instruction |= sizebits << 16;
16134 neon_dp_fixup (&inst);
16138 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
16139 struct neon_type_el et = neon_check_type (2, rs,
16140 N_8 | N_16 | N_32 | N_KEY, N_EQK);
16141 /* Duplicate ARM register to lanes of vector. */
16142 NEON_ENCODE (ARMREG, inst);
16145 case 8: inst.instruction |= 0x400000; break;
16146 case 16: inst.instruction |= 0x000020; break;
16147 case 32: inst.instruction |= 0x000000; break;
16150 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
16151 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
16152 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
16153 inst.instruction |= neon_quad (rs) << 21;
16154 /* The encoding for this instruction is identical for the ARM and Thumb
16155 variants, except for the condition field. */
16156 do_vfp_cond_or_thumb ();
16160 /* VMOV has particularly many variations. It can be one of:
16161 0. VMOV<c><q> <Qd>, <Qm>
16162 1. VMOV<c><q> <Dd>, <Dm>
16163 (Register operations, which are VORR with Rm = Rn.)
16164 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16165 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16167 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16168 (ARM register to scalar.)
16169 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16170 (Two ARM registers to vector.)
16171 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16172 (Scalar to ARM register.)
16173 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16174 (Vector to two ARM registers.)
16175 8. VMOV.F32 <Sd>, <Sm>
16176 9. VMOV.F64 <Dd>, <Dm>
16177 (VFP register moves.)
16178 10. VMOV.F32 <Sd>, #imm
16179 11. VMOV.F64 <Dd>, #imm
16180 (VFP float immediate load.)
16181 12. VMOV <Rd>, <Sm>
16182 (VFP single to ARM reg.)
16183 13. VMOV <Sd>, <Rm>
16184 (ARM reg to VFP single.)
16185 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16186 (Two ARM regs to two VFP singles.)
16187 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16188 (Two VFP singles to two ARM regs.)
16190 These cases can be disambiguated using neon_select_shape, except cases 1/9
16191 and 3/11 which depend on the operand type too.
16193 All the encoded bits are hardcoded by this function.
16195 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16196 Cases 5, 7 may be used with VFPv2 and above.
16198 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16199 can specify a type where it doesn't make sense to, and is ignored). */
16204 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
16205 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR,
16206 NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
16207 NS_HR, NS_RH, NS_HI, NS_NULL);
16208 struct neon_type_el et;
16209 const char *ldconst = 0;
16213 case NS_DD: /* case 1/9. */
16214 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
16215 /* It is not an error here if no type is given. */
16217 if (et.type == NT_float && et.size == 64)
16219 do_vfp_nsyn_opcode ("fcpyd");
16222 /* fall through. */
16224 case NS_QQ: /* case 0/1. */
16226 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
16228 /* The architecture manual I have doesn't explicitly state which
16229 value the U bit should have for register->register moves, but
16230 the equivalent VORR instruction has U = 0, so do that. */
16231 inst.instruction = 0x0200110;
16232 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16233 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16234 inst.instruction |= LOW4 (inst.operands[1].reg);
16235 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16236 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16237 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16238 inst.instruction |= neon_quad (rs) << 6;
16240 neon_dp_fixup (&inst);
16244 case NS_DI: /* case 3/11. */
16245 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
16247 if (et.type == NT_float && et.size == 64)
16249 /* case 11 (fconstd). */
16250 ldconst = "fconstd";
16251 goto encode_fconstd;
16253 /* fall through. */
16255 case NS_QI: /* case 2/3. */
16256 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
16258 inst.instruction = 0x0800010;
16259 neon_move_immediate ();
16260 neon_dp_fixup (&inst);
16263 case NS_SR: /* case 4. */
16265 unsigned bcdebits = 0;
16267 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
16268 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
16270 /* .<size> is optional here, defaulting to .32. */
16271 if (inst.vectype.elems == 0
16272 && inst.operands[0].vectype.type == NT_invtype
16273 && inst.operands[1].vectype.type == NT_invtype)
16275 inst.vectype.el[0].type = NT_untyped;
16276 inst.vectype.el[0].size = 32;
16277 inst.vectype.elems = 1;
16280 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
16281 logsize = neon_logbits (et.size);
16283 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
16285 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
16286 && et.size != 32, _(BAD_FPU));
16287 constraint (et.type == NT_invtype, _("bad type for scalar"));
16288 constraint (x >= 64 / et.size, _("scalar index out of range"));
16292 case 8: bcdebits = 0x8; break;
16293 case 16: bcdebits = 0x1; break;
16294 case 32: bcdebits = 0x0; break;
16298 bcdebits |= x << logsize;
16300 inst.instruction = 0xe000b10;
16301 do_vfp_cond_or_thumb ();
16302 inst.instruction |= LOW4 (dn) << 16;
16303 inst.instruction |= HI1 (dn) << 7;
16304 inst.instruction |= inst.operands[1].reg << 12;
16305 inst.instruction |= (bcdebits & 3) << 5;
16306 inst.instruction |= (bcdebits >> 2) << 21;
16310 case NS_DRR: /* case 5 (fmdrr). */
16311 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
16314 inst.instruction = 0xc400b10;
16315 do_vfp_cond_or_thumb ();
16316 inst.instruction |= LOW4 (inst.operands[0].reg);
16317 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
16318 inst.instruction |= inst.operands[1].reg << 12;
16319 inst.instruction |= inst.operands[2].reg << 16;
16322 case NS_RS: /* case 6. */
16325 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
16326 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
16327 unsigned abcdebits = 0;
16329 /* .<dt> is optional here, defaulting to .32. */
16330 if (inst.vectype.elems == 0
16331 && inst.operands[0].vectype.type == NT_invtype
16332 && inst.operands[1].vectype.type == NT_invtype)
16334 inst.vectype.el[0].type = NT_untyped;
16335 inst.vectype.el[0].size = 32;
16336 inst.vectype.elems = 1;
16339 et = neon_check_type (2, NS_NULL,
16340 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
16341 logsize = neon_logbits (et.size);
16343 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
16345 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
16346 && et.size != 32, _(BAD_FPU));
16347 constraint (et.type == NT_invtype, _("bad type for scalar"));
16348 constraint (x >= 64 / et.size, _("scalar index out of range"));
16352 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
16353 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
16354 case 32: abcdebits = 0x00; break;
16358 abcdebits |= x << logsize;
16359 inst.instruction = 0xe100b10;
16360 do_vfp_cond_or_thumb ();
16361 inst.instruction |= LOW4 (dn) << 16;
16362 inst.instruction |= HI1 (dn) << 7;
16363 inst.instruction |= inst.operands[0].reg << 12;
16364 inst.instruction |= (abcdebits & 3) << 5;
16365 inst.instruction |= (abcdebits >> 2) << 21;
16369 case NS_RRD: /* case 7 (fmrrd). */
16370 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
16373 inst.instruction = 0xc500b10;
16374 do_vfp_cond_or_thumb ();
16375 inst.instruction |= inst.operands[0].reg << 12;
16376 inst.instruction |= inst.operands[1].reg << 16;
16377 inst.instruction |= LOW4 (inst.operands[2].reg);
16378 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16381 case NS_FF: /* case 8 (fcpys). */
16382 do_vfp_nsyn_opcode ("fcpys");
16386 case NS_FI: /* case 10 (fconsts). */
16387 ldconst = "fconsts";
16389 if (is_quarter_float (inst.operands[1].imm))
16391 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
16392 do_vfp_nsyn_opcode (ldconst);
16394 /* ARMv8.2 fp16 vmov.f16 instruction. */
16396 do_scalar_fp16_v82_encode ();
16399 first_error (_("immediate out of range"));
16403 case NS_RF: /* case 12 (fmrs). */
16404 do_vfp_nsyn_opcode ("fmrs");
16405 /* ARMv8.2 fp16 vmov.f16 instruction. */
16407 do_scalar_fp16_v82_encode ();
16411 case NS_FR: /* case 13 (fmsr). */
16412 do_vfp_nsyn_opcode ("fmsr");
16413 /* ARMv8.2 fp16 vmov.f16 instruction. */
16415 do_scalar_fp16_v82_encode ();
16418 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16419 (one of which is a list), but we have parsed four. Do some fiddling to
16420 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16422 case NS_RRFF: /* case 14 (fmrrs). */
16423 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
16424 _("VFP registers must be adjacent"));
16425 inst.operands[2].imm = 2;
16426 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
16427 do_vfp_nsyn_opcode ("fmrrs");
16430 case NS_FFRR: /* case 15 (fmsrr). */
16431 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
16432 _("VFP registers must be adjacent"));
16433 inst.operands[1] = inst.operands[2];
16434 inst.operands[2] = inst.operands[3];
16435 inst.operands[0].imm = 2;
16436 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
16437 do_vfp_nsyn_opcode ("fmsrr");
16441 /* neon_select_shape has determined that the instruction
16442 shape is wrong and has already set the error message. */
16451 do_neon_rshift_round_imm (void)
16453 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16454 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
16455 int imm = inst.operands[2].imm;
16457 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16460 inst.operands[2].present = 0;
16465 constraint (imm < 1 || (unsigned)imm > et.size,
16466 _("immediate out of range for shift"));
16467 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
16472 do_neon_movhf (void)
16474 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
16475 constraint (rs != NS_HH, _("invalid suffix"));
16477 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16480 do_vfp_sp_monadic ();
16483 inst.instruction |= 0xf0000000;
16487 do_neon_movl (void)
16489 struct neon_type_el et = neon_check_type (2, NS_QD,
16490 N_EQK | N_DBL, N_SU_32 | N_KEY);
16491 unsigned sizebits = et.size >> 3;
16492 inst.instruction |= sizebits << 19;
16493 neon_two_same (0, et.type == NT_unsigned, -1);
16499 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16500 struct neon_type_el et = neon_check_type (2, rs,
16501 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16502 NEON_ENCODE (INTEGER, inst);
16503 neon_two_same (neon_quad (rs), 1, et.size);
16507 do_neon_zip_uzp (void)
16509 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16510 struct neon_type_el et = neon_check_type (2, rs,
16511 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16512 if (rs == NS_DD && et.size == 32)
16514 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16515 inst.instruction = N_MNEM_vtrn;
16519 neon_two_same (neon_quad (rs), 1, et.size);
16523 do_neon_sat_abs_neg (void)
16525 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16526 struct neon_type_el et = neon_check_type (2, rs,
16527 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
16528 neon_two_same (neon_quad (rs), 1, et.size);
16532 do_neon_pair_long (void)
16534 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16535 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
16536 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16537 inst.instruction |= (et.type == NT_unsigned) << 7;
16538 neon_two_same (neon_quad (rs), 1, et.size);
16542 do_neon_recip_est (void)
16544 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16545 struct neon_type_el et = neon_check_type (2, rs,
16546 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
16547 inst.instruction |= (et.type == NT_float) << 8;
16548 neon_two_same (neon_quad (rs), 1, et.size);
16554 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16555 struct neon_type_el et = neon_check_type (2, rs,
16556 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
16557 neon_two_same (neon_quad (rs), 1, et.size);
16563 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16564 struct neon_type_el et = neon_check_type (2, rs,
16565 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
16566 neon_two_same (neon_quad (rs), 1, et.size);
16572 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16573 struct neon_type_el et = neon_check_type (2, rs,
16574 N_EQK | N_INT, N_8 | N_KEY);
16575 neon_two_same (neon_quad (rs), 1, et.size);
16581 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16582 neon_two_same (neon_quad (rs), 1, -1);
16586 do_neon_tbl_tbx (void)
16588 unsigned listlenbits;
16589 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
16591 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
16593 first_error (_("bad list length for table lookup"));
16597 listlenbits = inst.operands[1].imm - 1;
16598 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16599 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16600 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16601 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16602 inst.instruction |= LOW4 (inst.operands[2].reg);
16603 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16604 inst.instruction |= listlenbits << 8;
16606 neon_dp_fixup (&inst);
16610 do_neon_ldm_stm (void)
16612 /* P, U and L bits are part of bitmask. */
16613 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
16614 unsigned offsetbits = inst.operands[1].imm * 2;
16616 if (inst.operands[1].issingle)
16618 do_vfp_nsyn_ldm_stm (is_dbmode);
16622 constraint (is_dbmode && !inst.operands[0].writeback,
16623 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16625 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16626 _("register list must contain at least 1 and at most 16 "
16629 inst.instruction |= inst.operands[0].reg << 16;
16630 inst.instruction |= inst.operands[0].writeback << 21;
16631 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
16632 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
16634 inst.instruction |= offsetbits;
16636 do_vfp_cond_or_thumb ();
16640 do_neon_ldr_str (void)
16642 int is_ldr = (inst.instruction & (1 << 20)) != 0;
16644 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16645 And is UNPREDICTABLE in thumb mode. */
16647 && inst.operands[1].reg == REG_PC
16648 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
16651 inst.error = _("Use of PC here is UNPREDICTABLE");
16652 else if (warn_on_deprecated)
16653 as_tsktsk (_("Use of PC here is deprecated"));
16656 if (inst.operands[0].issingle)
16659 do_vfp_nsyn_opcode ("flds");
16661 do_vfp_nsyn_opcode ("fsts");
16663 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16664 if (inst.vectype.el[0].size == 16)
16665 do_scalar_fp16_v82_encode ();
16670 do_vfp_nsyn_opcode ("fldd");
16672 do_vfp_nsyn_opcode ("fstd");
16676 /* "interleave" version also handles non-interleaving register VLD1/VST1
16680 do_neon_ld_st_interleave (void)
16682 struct neon_type_el et = neon_check_type (1, NS_NULL,
16683 N_8 | N_16 | N_32 | N_64);
16684 unsigned alignbits = 0;
16686 /* The bits in this table go:
16687 0: register stride of one (0) or two (1)
16688 1,2: register list length, minus one (1, 2, 3, 4).
16689 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16690 We use -1 for invalid entries. */
16691 const int typetable[] =
16693 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16694 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16695 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16696 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16700 if (et.type == NT_invtype)
16703 if (inst.operands[1].immisalign)
16704 switch (inst.operands[1].imm >> 8)
16706 case 64: alignbits = 1; break;
16708 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
16709 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
16710 goto bad_alignment;
16714 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
16715 goto bad_alignment;
16720 first_error (_("bad alignment"));
16724 inst.instruction |= alignbits << 4;
16725 inst.instruction |= neon_logbits (et.size) << 6;
16727 /* Bits [4:6] of the immediate in a list specifier encode register stride
16728 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16729 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16730 up the right value for "type" in a table based on this value and the given
16731 list style, then stick it back. */
16732 idx = ((inst.operands[0].imm >> 4) & 7)
16733 | (((inst.instruction >> 8) & 3) << 3);
16735 typebits = typetable[idx];
16737 constraint (typebits == -1, _("bad list type for instruction"));
16738 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
16739 _("bad element type for instruction"));
16741 inst.instruction &= ~0xf00;
16742 inst.instruction |= typebits << 8;
16745 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16746 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16747 otherwise. The variable arguments are a list of pairs of legal (size, align)
16748 values, terminated with -1. */
16751 neon_alignment_bit (int size, int align, int *do_alignment, ...)
16754 int result = FAIL, thissize, thisalign;
16756 if (!inst.operands[1].immisalign)
16762 va_start (ap, do_alignment);
16766 thissize = va_arg (ap, int);
16767 if (thissize == -1)
16769 thisalign = va_arg (ap, int);
16771 if (size == thissize && align == thisalign)
16774 while (result != SUCCESS);
16778 if (result == SUCCESS)
16781 first_error (_("unsupported alignment for instruction"));
16787 do_neon_ld_st_lane (void)
16789 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
16790 int align_good, do_alignment = 0;
16791 int logsize = neon_logbits (et.size);
16792 int align = inst.operands[1].imm >> 8;
16793 int n = (inst.instruction >> 8) & 3;
16794 int max_el = 64 / et.size;
16796 if (et.type == NT_invtype)
16799 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
16800 _("bad list length"));
16801 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
16802 _("scalar index out of range"));
16803 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
16805 _("stride of 2 unavailable when element size is 8"));
16809 case 0: /* VLD1 / VST1. */
16810 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
16812 if (align_good == FAIL)
16816 unsigned alignbits = 0;
16819 case 16: alignbits = 0x1; break;
16820 case 32: alignbits = 0x3; break;
16823 inst.instruction |= alignbits << 4;
16827 case 1: /* VLD2 / VST2. */
16828 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
16829 16, 32, 32, 64, -1);
16830 if (align_good == FAIL)
16833 inst.instruction |= 1 << 4;
16836 case 2: /* VLD3 / VST3. */
16837 constraint (inst.operands[1].immisalign,
16838 _("can't use alignment with this instruction"));
16841 case 3: /* VLD4 / VST4. */
16842 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
16843 16, 64, 32, 64, 32, 128, -1);
16844 if (align_good == FAIL)
16848 unsigned alignbits = 0;
16851 case 8: alignbits = 0x1; break;
16852 case 16: alignbits = 0x1; break;
16853 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
16856 inst.instruction |= alignbits << 4;
16863 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16864 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16865 inst.instruction |= 1 << (4 + logsize);
16867 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
16868 inst.instruction |= logsize << 10;
16871 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16874 do_neon_ld_dup (void)
16876 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
16877 int align_good, do_alignment = 0;
16879 if (et.type == NT_invtype)
16882 switch ((inst.instruction >> 8) & 3)
16884 case 0: /* VLD1. */
16885 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
16886 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
16887 &do_alignment, 16, 16, 32, 32, -1);
16888 if (align_good == FAIL)
16890 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
16893 case 2: inst.instruction |= 1 << 5; break;
16894 default: first_error (_("bad list length")); return;
16896 inst.instruction |= neon_logbits (et.size) << 6;
16899 case 1: /* VLD2. */
16900 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
16901 &do_alignment, 8, 16, 16, 32, 32, 64,
16903 if (align_good == FAIL)
16905 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
16906 _("bad list length"));
16907 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16908 inst.instruction |= 1 << 5;
16909 inst.instruction |= neon_logbits (et.size) << 6;
16912 case 2: /* VLD3. */
16913 constraint (inst.operands[1].immisalign,
16914 _("can't use alignment with this instruction"));
16915 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
16916 _("bad list length"));
16917 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16918 inst.instruction |= 1 << 5;
16919 inst.instruction |= neon_logbits (et.size) << 6;
16922 case 3: /* VLD4. */
16924 int align = inst.operands[1].imm >> 8;
16925 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
16926 16, 64, 32, 64, 32, 128, -1);
16927 if (align_good == FAIL)
16929 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
16930 _("bad list length"));
16931 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16932 inst.instruction |= 1 << 5;
16933 if (et.size == 32 && align == 128)
16934 inst.instruction |= 0x3 << 6;
16936 inst.instruction |= neon_logbits (et.size) << 6;
16943 inst.instruction |= do_alignment << 4;
16946 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16947 apart from bits [11:4]. */
16950 do_neon_ldx_stx (void)
16952 if (inst.operands[1].isreg)
16953 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16955 switch (NEON_LANE (inst.operands[0].imm))
16957 case NEON_INTERLEAVE_LANES:
16958 NEON_ENCODE (INTERLV, inst);
16959 do_neon_ld_st_interleave ();
16962 case NEON_ALL_LANES:
16963 NEON_ENCODE (DUP, inst);
16964 if (inst.instruction == N_INV)
16966 first_error ("only loads support such operands");
16973 NEON_ENCODE (LANE, inst);
16974 do_neon_ld_st_lane ();
16977 /* L bit comes from bit mask. */
16978 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16979 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16980 inst.instruction |= inst.operands[1].reg << 16;
16982 if (inst.operands[1].postind)
16984 int postreg = inst.operands[1].imm & 0xf;
16985 constraint (!inst.operands[1].immisreg,
16986 _("post-index must be a register"));
16987 constraint (postreg == 0xd || postreg == 0xf,
16988 _("bad register for post-index"));
16989 inst.instruction |= postreg;
16993 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16994 constraint (inst.reloc.exp.X_op != O_constant
16995 || inst.reloc.exp.X_add_number != 0,
16998 if (inst.operands[1].writeback)
17000 inst.instruction |= 0xd;
17003 inst.instruction |= 0xf;
17007 inst.instruction |= 0xf9000000;
17009 inst.instruction |= 0xf4000000;
17014 do_vfp_nsyn_fpv8 (enum neon_shape rs)
17016 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17017 D register operands. */
17018 if (neon_shape_class[rs] == SC_DOUBLE)
17019 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
17022 NEON_ENCODE (FPV8, inst);
17024 if (rs == NS_FFF || rs == NS_HHH)
17026 do_vfp_sp_dyadic ();
17028 /* ARMv8.2 fp16 instruction. */
17030 do_scalar_fp16_v82_encode ();
17033 do_vfp_dp_rd_rn_rm ();
17036 inst.instruction |= 0x100;
17038 inst.instruction |= 0xf0000000;
17044 set_it_insn_type (OUTSIDE_IT_INSN);
17046 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
17047 first_error (_("invalid instruction shape"));
17053 set_it_insn_type (OUTSIDE_IT_INSN);
17055 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
17058 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
17061 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
17065 do_vrint_1 (enum neon_cvt_mode mode)
17067 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
17068 struct neon_type_el et;
17073 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17074 D register operands. */
17075 if (neon_shape_class[rs] == SC_DOUBLE)
17076 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
17079 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
17081 if (et.type != NT_invtype)
17083 /* VFP encodings. */
17084 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
17085 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
17086 set_it_insn_type (OUTSIDE_IT_INSN);
17088 NEON_ENCODE (FPV8, inst);
17089 if (rs == NS_FF || rs == NS_HH)
17090 do_vfp_sp_monadic ();
17092 do_vfp_dp_rd_rm ();
17096 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
17097 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
17098 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
17099 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
17100 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
17101 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
17102 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
17106 inst.instruction |= (rs == NS_DD) << 8;
17107 do_vfp_cond_or_thumb ();
17109 /* ARMv8.2 fp16 vrint instruction. */
17111 do_scalar_fp16_v82_encode ();
17115 /* Neon encodings (or something broken...). */
17117 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
17119 if (et.type == NT_invtype)
17122 set_it_insn_type (OUTSIDE_IT_INSN);
17123 NEON_ENCODE (FLOAT, inst);
17125 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
17128 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17129 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17130 inst.instruction |= LOW4 (inst.operands[1].reg);
17131 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17132 inst.instruction |= neon_quad (rs) << 6;
17133 /* Mask off the original size bits and reencode them. */
17134 inst.instruction = ((inst.instruction & 0xfff3ffff)
17135 | neon_logbits (et.size) << 18);
17139 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
17140 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
17141 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
17142 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
17143 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
17144 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
17145 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
17150 inst.instruction |= 0xfc000000;
17152 inst.instruction |= 0xf0000000;
17159 do_vrint_1 (neon_cvt_mode_x);
17165 do_vrint_1 (neon_cvt_mode_z);
17171 do_vrint_1 (neon_cvt_mode_r);
17177 do_vrint_1 (neon_cvt_mode_a);
17183 do_vrint_1 (neon_cvt_mode_n);
17189 do_vrint_1 (neon_cvt_mode_p);
17195 do_vrint_1 (neon_cvt_mode_m);
17198 /* Crypto v1 instructions. */
17200 do_crypto_2op_1 (unsigned elttype, int op)
17202 set_it_insn_type (OUTSIDE_IT_INSN);
17204 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
17210 NEON_ENCODE (INTEGER, inst);
17211 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17212 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17213 inst.instruction |= LOW4 (inst.operands[1].reg);
17214 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17216 inst.instruction |= op << 6;
17219 inst.instruction |= 0xfc000000;
17221 inst.instruction |= 0xf0000000;
17225 do_crypto_3op_1 (int u, int op)
17227 set_it_insn_type (OUTSIDE_IT_INSN);
17229 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
17230 N_32 | N_UNT | N_KEY).type == NT_invtype)
17235 NEON_ENCODE (INTEGER, inst);
17236 neon_three_same (1, u, 8 << op);
17242 do_crypto_2op_1 (N_8, 0);
17248 do_crypto_2op_1 (N_8, 1);
17254 do_crypto_2op_1 (N_8, 2);
17260 do_crypto_2op_1 (N_8, 3);
17266 do_crypto_3op_1 (0, 0);
17272 do_crypto_3op_1 (0, 1);
17278 do_crypto_3op_1 (0, 2);
17284 do_crypto_3op_1 (0, 3);
17290 do_crypto_3op_1 (1, 0);
17296 do_crypto_3op_1 (1, 1);
17300 do_sha256su1 (void)
17302 do_crypto_3op_1 (1, 2);
17308 do_crypto_2op_1 (N_32, -1);
17314 do_crypto_2op_1 (N_32, 0);
17318 do_sha256su0 (void)
17320 do_crypto_2op_1 (N_32, 1);
17324 do_crc32_1 (unsigned int poly, unsigned int sz)
17326 unsigned int Rd = inst.operands[0].reg;
17327 unsigned int Rn = inst.operands[1].reg;
17328 unsigned int Rm = inst.operands[2].reg;
17330 set_it_insn_type (OUTSIDE_IT_INSN);
17331 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
17332 inst.instruction |= LOW4 (Rn) << 16;
17333 inst.instruction |= LOW4 (Rm);
17334 inst.instruction |= sz << (thumb_mode ? 4 : 21);
17335 inst.instruction |= poly << (thumb_mode ? 20 : 9);
17337 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
17338 as_warn (UNPRED_REG ("r15"));
17339 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
17340 as_warn (UNPRED_REG ("r13"));
17380 /* Overall per-instruction processing. */
17382 /* We need to be able to fix up arbitrary expressions in some statements.
17383 This is so that we can handle symbols that are an arbitrary distance from
17384 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17385 which returns part of an address in a form which will be valid for
17386 a data instruction. We do this by pushing the expression into a symbol
17387 in the expr_section, and creating a fix for that. */
17390 fix_new_arm (fragS * frag,
17404 /* Create an absolute valued symbol, so we have something to
17405 refer to in the object file. Unfortunately for us, gas's
17406 generic expression parsing will already have folded out
17407 any use of .set foo/.type foo %function that may have
17408 been used to set type information of the target location,
17409 that's being specified symbolically. We have to presume
17410 the user knows what they are doing. */
17414 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
17416 symbol = symbol_find_or_make (name);
17417 S_SET_SEGMENT (symbol, absolute_section);
17418 symbol_set_frag (symbol, &zero_address_frag);
17419 S_SET_VALUE (symbol, exp->X_add_number);
17420 exp->X_op = O_symbol;
17421 exp->X_add_symbol = symbol;
17422 exp->X_add_number = 0;
17428 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
17429 (enum bfd_reloc_code_real) reloc);
17433 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
17434 pc_rel, (enum bfd_reloc_code_real) reloc);
17438 /* Mark whether the fix is to a THUMB instruction, or an ARM
17440 new_fix->tc_fix_data = thumb_mode;
17443 /* Create a frg for an instruction requiring relaxation. */
17445 output_relax_insn (void)
17451 /* The size of the instruction is unknown, so tie the debug info to the
17452 start of the instruction. */
17453 dwarf2_emit_insn (0);
17455 switch (inst.reloc.exp.X_op)
17458 sym = inst.reloc.exp.X_add_symbol;
17459 offset = inst.reloc.exp.X_add_number;
17463 offset = inst.reloc.exp.X_add_number;
17466 sym = make_expr_symbol (&inst.reloc.exp);
17470 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
17471 inst.relax, sym, offset, NULL/*offset, opcode*/);
17472 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
17475 /* Write a 32-bit thumb instruction to buf. */
17477 put_thumb32_insn (char * buf, unsigned long insn)
17479 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
17480 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
17484 output_inst (const char * str)
17490 as_bad ("%s -- `%s'", inst.error, str);
17495 output_relax_insn ();
17498 if (inst.size == 0)
17501 to = frag_more (inst.size);
17502 /* PR 9814: Record the thumb mode into the current frag so that we know
17503 what type of NOP padding to use, if necessary. We override any previous
17504 setting so that if the mode has changed then the NOPS that we use will
17505 match the encoding of the last instruction in the frag. */
17506 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
17508 if (thumb_mode && (inst.size > THUMB_SIZE))
17510 gas_assert (inst.size == (2 * THUMB_SIZE));
17511 put_thumb32_insn (to, inst.instruction);
17513 else if (inst.size > INSN_SIZE)
17515 gas_assert (inst.size == (2 * INSN_SIZE));
17516 md_number_to_chars (to, inst.instruction, INSN_SIZE);
17517 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
17520 md_number_to_chars (to, inst.instruction, inst.size);
17522 if (inst.reloc.type != BFD_RELOC_UNUSED)
17523 fix_new_arm (frag_now, to - frag_now->fr_literal,
17524 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
17527 dwarf2_emit_insn (inst.size);
17531 output_it_inst (int cond, int mask, char * to)
17533 unsigned long instruction = 0xbf00;
17536 instruction |= mask;
17537 instruction |= cond << 4;
17541 to = frag_more (2);
17543 dwarf2_emit_insn (2);
17547 md_number_to_chars (to, instruction, 2);
17552 /* Tag values used in struct asm_opcode's tag field. */
17555 OT_unconditional, /* Instruction cannot be conditionalized.
17556 The ARM condition field is still 0xE. */
17557 OT_unconditionalF, /* Instruction cannot be conditionalized
17558 and carries 0xF in its ARM condition field. */
17559 OT_csuffix, /* Instruction takes a conditional suffix. */
17560 OT_csuffixF, /* Some forms of the instruction take a conditional
17561 suffix, others place 0xF where the condition field
17563 OT_cinfix3, /* Instruction takes a conditional infix,
17564 beginning at character index 3. (In
17565 unified mode, it becomes a suffix.) */
17566 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
17567 tsts, cmps, cmns, and teqs. */
17568 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
17569 character index 3, even in unified mode. Used for
17570 legacy instructions where suffix and infix forms
17571 may be ambiguous. */
17572 OT_csuf_or_in3, /* Instruction takes either a conditional
17573 suffix or an infix at character index 3. */
17574 OT_odd_infix_unc, /* This is the unconditional variant of an
17575 instruction that takes a conditional infix
17576 at an unusual position. In unified mode,
17577 this variant will accept a suffix. */
17578 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
17579 are the conditional variants of instructions that
17580 take conditional infixes in unusual positions.
17581 The infix appears at character index
17582 (tag - OT_odd_infix_0). These are not accepted
17583 in unified mode. */
17586 /* Subroutine of md_assemble, responsible for looking up the primary
17587 opcode from the mnemonic the user wrote. STR points to the
17588 beginning of the mnemonic.
17590 This is not simply a hash table lookup, because of conditional
17591 variants. Most instructions have conditional variants, which are
17592 expressed with a _conditional affix_ to the mnemonic. If we were
17593 to encode each conditional variant as a literal string in the opcode
17594 table, it would have approximately 20,000 entries.
17596 Most mnemonics take this affix as a suffix, and in unified syntax,
17597 'most' is upgraded to 'all'. However, in the divided syntax, some
17598 instructions take the affix as an infix, notably the s-variants of
17599 the arithmetic instructions. Of those instructions, all but six
17600 have the infix appear after the third character of the mnemonic.
17602 Accordingly, the algorithm for looking up primary opcodes given
17605 1. Look up the identifier in the opcode table.
17606 If we find a match, go to step U.
17608 2. Look up the last two characters of the identifier in the
17609 conditions table. If we find a match, look up the first N-2
17610 characters of the identifier in the opcode table. If we
17611 find a match, go to step CE.
17613 3. Look up the fourth and fifth characters of the identifier in
17614 the conditions table. If we find a match, extract those
17615 characters from the identifier, and look up the remaining
17616 characters in the opcode table. If we find a match, go
17621 U. Examine the tag field of the opcode structure, in case this is
17622 one of the six instructions with its conditional infix in an
17623 unusual place. If it is, the tag tells us where to find the
17624 infix; look it up in the conditions table and set inst.cond
17625 accordingly. Otherwise, this is an unconditional instruction.
17626 Again set inst.cond accordingly. Return the opcode structure.
17628 CE. Examine the tag field to make sure this is an instruction that
17629 should receive a conditional suffix. If it is not, fail.
17630 Otherwise, set inst.cond from the suffix we already looked up,
17631 and return the opcode structure.
17633 CM. Examine the tag field to make sure this is an instruction that
17634 should receive a conditional infix after the third character.
17635 If it is not, fail. Otherwise, undo the edits to the current
17636 line of input and proceed as for case CE. */
17638 static const struct asm_opcode *
17639 opcode_lookup (char **str)
17643 const struct asm_opcode *opcode;
17644 const struct asm_cond *cond;
17647 /* Scan up to the end of the mnemonic, which must end in white space,
17648 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17649 for (base = end = *str; *end != '\0'; end++)
17650 if (*end == ' ' || *end == '.')
17656 /* Handle a possible width suffix and/or Neon type suffix. */
17661 /* The .w and .n suffixes are only valid if the unified syntax is in
17663 if (unified_syntax && end[1] == 'w')
17665 else if (unified_syntax && end[1] == 'n')
17670 inst.vectype.elems = 0;
17672 *str = end + offset;
17674 if (end[offset] == '.')
17676 /* See if we have a Neon type suffix (possible in either unified or
17677 non-unified ARM syntax mode). */
17678 if (parse_neon_type (&inst.vectype, str) == FAIL)
17681 else if (end[offset] != '\0' && end[offset] != ' ')
17687 /* Look for unaffixed or special-case affixed mnemonic. */
17688 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
17693 if (opcode->tag < OT_odd_infix_0)
17695 inst.cond = COND_ALWAYS;
17699 if (warn_on_deprecated && unified_syntax)
17700 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17701 affix = base + (opcode->tag - OT_odd_infix_0);
17702 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17705 inst.cond = cond->value;
17709 /* Cannot have a conditional suffix on a mnemonic of less than two
17711 if (end - base < 3)
17714 /* Look for suffixed mnemonic. */
17716 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17717 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
17719 if (opcode && cond)
17722 switch (opcode->tag)
17724 case OT_cinfix3_legacy:
17725 /* Ignore conditional suffixes matched on infix only mnemonics. */
17729 case OT_cinfix3_deprecated:
17730 case OT_odd_infix_unc:
17731 if (!unified_syntax)
17733 /* else fall through */
17737 case OT_csuf_or_in3:
17738 inst.cond = cond->value;
17741 case OT_unconditional:
17742 case OT_unconditionalF:
17744 inst.cond = cond->value;
17747 /* Delayed diagnostic. */
17748 inst.error = BAD_COND;
17749 inst.cond = COND_ALWAYS;
17758 /* Cannot have a usual-position infix on a mnemonic of less than
17759 six characters (five would be a suffix). */
17760 if (end - base < 6)
17763 /* Look for infixed mnemonic in the usual position. */
17765 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17769 memcpy (save, affix, 2);
17770 memmove (affix, affix + 2, (end - affix) - 2);
17771 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
17773 memmove (affix + 2, affix, (end - affix) - 2);
17774 memcpy (affix, save, 2);
17777 && (opcode->tag == OT_cinfix3
17778 || opcode->tag == OT_cinfix3_deprecated
17779 || opcode->tag == OT_csuf_or_in3
17780 || opcode->tag == OT_cinfix3_legacy))
17783 if (warn_on_deprecated && unified_syntax
17784 && (opcode->tag == OT_cinfix3
17785 || opcode->tag == OT_cinfix3_deprecated))
17786 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17788 inst.cond = cond->value;
17795 /* This function generates an initial IT instruction, leaving its block
17796 virtually open for the new instructions. Eventually,
17797 the mask will be updated by now_it_add_mask () each time
17798 a new instruction needs to be included in the IT block.
17799 Finally, the block is closed with close_automatic_it_block ().
17800 The block closure can be requested either from md_assemble (),
17801 a tencode (), or due to a label hook. */
17804 new_automatic_it_block (int cond)
17806 now_it.state = AUTOMATIC_IT_BLOCK;
17807 now_it.mask = 0x18;
17809 now_it.block_length = 1;
17810 mapping_state (MAP_THUMB);
17811 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
17812 now_it.warn_deprecated = FALSE;
17813 now_it.insn_cond = TRUE;
17816 /* Close an automatic IT block.
17817 See comments in new_automatic_it_block (). */
17820 close_automatic_it_block (void)
17822 now_it.mask = 0x10;
17823 now_it.block_length = 0;
17826 /* Update the mask of the current automatically-generated IT
17827 instruction. See comments in new_automatic_it_block (). */
17830 now_it_add_mask (int cond)
17832 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17833 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17834 | ((bitvalue) << (nbit)))
17835 const int resulting_bit = (cond & 1);
17837 now_it.mask &= 0xf;
17838 now_it.mask = SET_BIT_VALUE (now_it.mask,
17840 (5 - now_it.block_length));
17841 now_it.mask = SET_BIT_VALUE (now_it.mask,
17843 ((5 - now_it.block_length) - 1) );
17844 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
17847 #undef SET_BIT_VALUE
17850 /* The IT blocks handling machinery is accessed through the these functions:
17851 it_fsm_pre_encode () from md_assemble ()
17852 set_it_insn_type () optional, from the tencode functions
17853 set_it_insn_type_last () ditto
17854 in_it_block () ditto
17855 it_fsm_post_encode () from md_assemble ()
17856 force_automatic_it_block_close () from label habdling functions
17859 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17860 initializing the IT insn type with a generic initial value depending
17861 on the inst.condition.
17862 2) During the tencode function, two things may happen:
17863 a) The tencode function overrides the IT insn type by
17864 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17865 b) The tencode function queries the IT block state by
17866 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17868 Both set_it_insn_type and in_it_block run the internal FSM state
17869 handling function (handle_it_state), because: a) setting the IT insn
17870 type may incur in an invalid state (exiting the function),
17871 and b) querying the state requires the FSM to be updated.
17872 Specifically we want to avoid creating an IT block for conditional
17873 branches, so it_fsm_pre_encode is actually a guess and we can't
17874 determine whether an IT block is required until the tencode () routine
17875 has decided what type of instruction this actually it.
17876 Because of this, if set_it_insn_type and in_it_block have to be used,
17877 set_it_insn_type has to be called first.
17879 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17880 determines the insn IT type depending on the inst.cond code.
17881 When a tencode () routine encodes an instruction that can be
17882 either outside an IT block, or, in the case of being inside, has to be
17883 the last one, set_it_insn_type_last () will determine the proper
17884 IT instruction type based on the inst.cond code. Otherwise,
17885 set_it_insn_type can be called for overriding that logic or
17886 for covering other cases.
17888 Calling handle_it_state () may not transition the IT block state to
17889 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17890 still queried. Instead, if the FSM determines that the state should
17891 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17892 after the tencode () function: that's what it_fsm_post_encode () does.
17894 Since in_it_block () calls the state handling function to get an
17895 updated state, an error may occur (due to invalid insns combination).
17896 In that case, inst.error is set.
17897 Therefore, inst.error has to be checked after the execution of
17898 the tencode () routine.
17900 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17901 any pending state change (if any) that didn't take place in
17902 handle_it_state () as explained above. */
17905 it_fsm_pre_encode (void)
17907 if (inst.cond != COND_ALWAYS)
17908 inst.it_insn_type = INSIDE_IT_INSN;
17910 inst.it_insn_type = OUTSIDE_IT_INSN;
17912 now_it.state_handled = 0;
17915 /* IT state FSM handling function. */
17918 handle_it_state (void)
17920 now_it.state_handled = 1;
17921 now_it.insn_cond = FALSE;
17923 switch (now_it.state)
17925 case OUTSIDE_IT_BLOCK:
17926 switch (inst.it_insn_type)
17928 case OUTSIDE_IT_INSN:
17931 case INSIDE_IT_INSN:
17932 case INSIDE_IT_LAST_INSN:
17933 if (thumb_mode == 0)
17936 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
17937 as_tsktsk (_("Warning: conditional outside an IT block"\
17942 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
17943 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
17945 /* Automatically generate the IT instruction. */
17946 new_automatic_it_block (inst.cond);
17947 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
17948 close_automatic_it_block ();
17952 inst.error = BAD_OUT_IT;
17958 case IF_INSIDE_IT_LAST_INSN:
17959 case NEUTRAL_IT_INSN:
17963 now_it.state = MANUAL_IT_BLOCK;
17964 now_it.block_length = 0;
17969 case AUTOMATIC_IT_BLOCK:
17970 /* Three things may happen now:
17971 a) We should increment current it block size;
17972 b) We should close current it block (closing insn or 4 insns);
17973 c) We should close current it block and start a new one (due
17974 to incompatible conditions or
17975 4 insns-length block reached). */
17977 switch (inst.it_insn_type)
17979 case OUTSIDE_IT_INSN:
17980 /* The closure of the block shall happen immediatelly,
17981 so any in_it_block () call reports the block as closed. */
17982 force_automatic_it_block_close ();
17985 case INSIDE_IT_INSN:
17986 case INSIDE_IT_LAST_INSN:
17987 case IF_INSIDE_IT_LAST_INSN:
17988 now_it.block_length++;
17990 if (now_it.block_length > 4
17991 || !now_it_compatible (inst.cond))
17993 force_automatic_it_block_close ();
17994 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
17995 new_automatic_it_block (inst.cond);
17999 now_it.insn_cond = TRUE;
18000 now_it_add_mask (inst.cond);
18003 if (now_it.state == AUTOMATIC_IT_BLOCK
18004 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
18005 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
18006 close_automatic_it_block ();
18009 case NEUTRAL_IT_INSN:
18010 now_it.block_length++;
18011 now_it.insn_cond = TRUE;
18013 if (now_it.block_length > 4)
18014 force_automatic_it_block_close ();
18016 now_it_add_mask (now_it.cc & 1);
18020 close_automatic_it_block ();
18021 now_it.state = MANUAL_IT_BLOCK;
18026 case MANUAL_IT_BLOCK:
18028 /* Check conditional suffixes. */
18029 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
18032 now_it.mask &= 0x1f;
18033 is_last = (now_it.mask == 0x10);
18034 now_it.insn_cond = TRUE;
18036 switch (inst.it_insn_type)
18038 case OUTSIDE_IT_INSN:
18039 inst.error = BAD_NOT_IT;
18042 case INSIDE_IT_INSN:
18043 if (cond != inst.cond)
18045 inst.error = BAD_IT_COND;
18050 case INSIDE_IT_LAST_INSN:
18051 case IF_INSIDE_IT_LAST_INSN:
18052 if (cond != inst.cond)
18054 inst.error = BAD_IT_COND;
18059 inst.error = BAD_BRANCH;
18064 case NEUTRAL_IT_INSN:
18065 /* The BKPT instruction is unconditional even in an IT block. */
18069 inst.error = BAD_IT_IT;
18079 struct depr_insn_mask
18081 unsigned long pattern;
18082 unsigned long mask;
18083 const char* description;
18086 /* List of 16-bit instruction patterns deprecated in an IT block in
18088 static const struct depr_insn_mask depr_it_insns[] = {
18089 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18090 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18091 { 0xa000, 0xb800, N_("ADR") },
18092 { 0x4800, 0xf800, N_("Literal loads") },
18093 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18094 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18095 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18096 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18097 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18102 it_fsm_post_encode (void)
18106 if (!now_it.state_handled)
18107 handle_it_state ();
18109 if (now_it.insn_cond
18110 && !now_it.warn_deprecated
18111 && warn_on_deprecated
18112 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
18114 if (inst.instruction >= 0x10000)
18116 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18117 "deprecated in ARMv8"));
18118 now_it.warn_deprecated = TRUE;
18122 const struct depr_insn_mask *p = depr_it_insns;
18124 while (p->mask != 0)
18126 if ((inst.instruction & p->mask) == p->pattern)
18128 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18129 "of the following class are deprecated in ARMv8: "
18130 "%s"), p->description);
18131 now_it.warn_deprecated = TRUE;
18139 if (now_it.block_length > 1)
18141 as_tsktsk (_("IT blocks containing more than one conditional "
18142 "instruction are deprecated in ARMv8"));
18143 now_it.warn_deprecated = TRUE;
18147 is_last = (now_it.mask == 0x10);
18150 now_it.state = OUTSIDE_IT_BLOCK;
18156 force_automatic_it_block_close (void)
18158 if (now_it.state == AUTOMATIC_IT_BLOCK)
18160 close_automatic_it_block ();
18161 now_it.state = OUTSIDE_IT_BLOCK;
18169 if (!now_it.state_handled)
18170 handle_it_state ();
18172 return now_it.state != OUTSIDE_IT_BLOCK;
18175 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18176 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18177 here, hence the "known" in the function name. */
18180 known_t32_only_insn (const struct asm_opcode *opcode)
18182 /* Original Thumb-1 wide instruction. */
18183 if (opcode->tencode == do_t_blx
18184 || opcode->tencode == do_t_branch23
18185 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
18186 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
18189 /* Wide-only instruction added to ARMv8-M. */
18190 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m)
18191 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
18192 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
18193 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
18199 /* Whether wide instruction variant can be used if available for a valid OPCODE
18203 t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
18205 if (known_t32_only_insn (opcode))
18208 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18209 of variant T3 of B.W is checked in do_t_branch. */
18210 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
18211 && opcode->tencode == do_t_branch)
18214 /* Wide instruction variants of all instructions with narrow *and* wide
18215 variants become available with ARMv6t2. Other opcodes are either
18216 narrow-only or wide-only and are thus available if OPCODE is valid. */
18217 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
18220 /* OPCODE with narrow only instruction variant or wide variant not
18226 md_assemble (char *str)
18229 const struct asm_opcode * opcode;
18231 /* Align the previous label if needed. */
18232 if (last_label_seen != NULL)
18234 symbol_set_frag (last_label_seen, frag_now);
18235 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
18236 S_SET_SEGMENT (last_label_seen, now_seg);
18239 memset (&inst, '\0', sizeof (inst));
18240 inst.reloc.type = BFD_RELOC_UNUSED;
18242 opcode = opcode_lookup (&p);
18245 /* It wasn't an instruction, but it might be a register alias of
18246 the form alias .req reg, or a Neon .dn/.qn directive. */
18247 if (! create_register_alias (str, p)
18248 && ! create_neon_reg_alias (str, p))
18249 as_bad (_("bad instruction `%s'"), str);
18254 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
18255 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18257 /* The value which unconditional instructions should have in place of the
18258 condition field. */
18259 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
18263 arm_feature_set variant;
18265 variant = cpu_variant;
18266 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18267 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
18268 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
18269 /* Check that this instruction is supported for this CPU. */
18270 if (!opcode->tvariant
18271 || (thumb_mode == 1
18272 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
18274 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
18277 if (inst.cond != COND_ALWAYS && !unified_syntax
18278 && opcode->tencode != do_t_branch)
18280 as_bad (_("Thumb does not support conditional execution"));
18284 /* Two things are addressed here:
18285 1) Implicit require narrow instructions on Thumb-1.
18286 This avoids relaxation accidentally introducing Thumb-2
18288 2) Reject wide instructions in non Thumb-2 cores.
18290 Only instructions with narrow and wide variants need to be handled
18291 but selecting all non wide-only instructions is easier. */
18292 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
18293 && !t32_insn_ok (variant, opcode))
18295 if (inst.size_req == 0)
18297 else if (inst.size_req == 4)
18299 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
18300 as_bad (_("selected processor does not support 32bit wide "
18301 "variant of instruction `%s'"), str);
18303 as_bad (_("selected processor does not support `%s' in "
18304 "Thumb-2 mode"), str);
18309 inst.instruction = opcode->tvalue;
18311 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
18313 /* Prepare the it_insn_type for those encodings that don't set
18315 it_fsm_pre_encode ();
18317 opcode->tencode ();
18319 it_fsm_post_encode ();
18322 if (!(inst.error || inst.relax))
18324 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
18325 inst.size = (inst.instruction > 0xffff ? 4 : 2);
18326 if (inst.size_req && inst.size_req != inst.size)
18328 as_bad (_("cannot honor width suffix -- `%s'"), str);
18333 /* Something has gone badly wrong if we try to relax a fixed size
18335 gas_assert (inst.size_req == 0 || !inst.relax);
18337 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
18338 *opcode->tvariant);
18339 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18340 set those bits when Thumb-2 32-bit instructions are seen. The impact
18341 of relaxable instructions will be considered later after we finish all
18343 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
18344 variant = arm_arch_none;
18346 variant = cpu_variant;
18347 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
18348 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
18351 check_neon_suffixes;
18355 mapping_state (MAP_THUMB);
18358 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
18362 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18363 is_bx = (opcode->aencode == do_bx);
18365 /* Check that this instruction is supported for this CPU. */
18366 if (!(is_bx && fix_v4bx)
18367 && !(opcode->avariant &&
18368 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
18370 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
18375 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
18379 inst.instruction = opcode->avalue;
18380 if (opcode->tag == OT_unconditionalF)
18381 inst.instruction |= 0xFU << 28;
18383 inst.instruction |= inst.cond << 28;
18384 inst.size = INSN_SIZE;
18385 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
18387 it_fsm_pre_encode ();
18388 opcode->aencode ();
18389 it_fsm_post_encode ();
18391 /* Arm mode bx is marked as both v4T and v5 because it's still required
18392 on a hypothetical non-thumb v5 core. */
18394 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
18396 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
18397 *opcode->avariant);
18399 check_neon_suffixes;
18403 mapping_state (MAP_ARM);
18408 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18416 check_it_blocks_finished (void)
18421 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
18422 if (seg_info (sect)->tc_segment_info_data.current_it.state
18423 == MANUAL_IT_BLOCK)
18425 as_warn (_("section '%s' finished with an open IT block."),
18429 if (now_it.state == MANUAL_IT_BLOCK)
18430 as_warn (_("file finished with an open IT block."));
18434 /* Various frobbings of labels and their addresses. */
18437 arm_start_line_hook (void)
18439 last_label_seen = NULL;
18443 arm_frob_label (symbolS * sym)
18445 last_label_seen = sym;
18447 ARM_SET_THUMB (sym, thumb_mode);
18449 #if defined OBJ_COFF || defined OBJ_ELF
18450 ARM_SET_INTERWORK (sym, support_interwork);
18453 force_automatic_it_block_close ();
18455 /* Note - do not allow local symbols (.Lxxx) to be labelled
18456 as Thumb functions. This is because these labels, whilst
18457 they exist inside Thumb code, are not the entry points for
18458 possible ARM->Thumb calls. Also, these labels can be used
18459 as part of a computed goto or switch statement. eg gcc
18460 can generate code that looks like this:
18462 ldr r2, [pc, .Laaa]
18472 The first instruction loads the address of the jump table.
18473 The second instruction converts a table index into a byte offset.
18474 The third instruction gets the jump address out of the table.
18475 The fourth instruction performs the jump.
18477 If the address stored at .Laaa is that of a symbol which has the
18478 Thumb_Func bit set, then the linker will arrange for this address
18479 to have the bottom bit set, which in turn would mean that the
18480 address computation performed by the third instruction would end
18481 up with the bottom bit set. Since the ARM is capable of unaligned
18482 word loads, the instruction would then load the incorrect address
18483 out of the jump table, and chaos would ensue. */
18484 if (label_is_thumb_function_name
18485 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
18486 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
18488 /* When the address of a Thumb function is taken the bottom
18489 bit of that address should be set. This will allow
18490 interworking between Arm and Thumb functions to work
18493 THUMB_SET_FUNC (sym, 1);
18495 label_is_thumb_function_name = FALSE;
18498 dwarf2_emit_label (sym);
18502 arm_data_in_code (void)
18504 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
18506 *input_line_pointer = '/';
18507 input_line_pointer += 5;
18508 *input_line_pointer = 0;
18516 arm_canonicalize_symbol_name (char * name)
18520 if (thumb_mode && (len = strlen (name)) > 5
18521 && streq (name + len - 5, "/data"))
18522 *(name + len - 5) = 0;
18527 /* Table of all register names defined by default. The user can
18528 define additional names with .req. Note that all register names
18529 should appear in both upper and lowercase variants. Some registers
18530 also have mixed-case names. */
18532 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18533 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18534 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18535 #define REGSET(p,t) \
18536 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18537 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18538 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18539 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18540 #define REGSETH(p,t) \
18541 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18542 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18543 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18544 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18545 #define REGSET2(p,t) \
18546 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18547 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18548 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18549 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18550 #define SPLRBANK(base,bank,t) \
18551 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18552 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18553 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18554 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18555 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18556 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18558 static const struct reg_entry reg_names[] =
18560 /* ARM integer registers. */
18561 REGSET(r, RN), REGSET(R, RN),
18563 /* ATPCS synonyms. */
18564 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
18565 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
18566 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
18568 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
18569 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
18570 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
18572 /* Well-known aliases. */
18573 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
18574 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
18576 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
18577 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
18579 /* Coprocessor numbers. */
18580 REGSET(p, CP), REGSET(P, CP),
18582 /* Coprocessor register numbers. The "cr" variants are for backward
18584 REGSET(c, CN), REGSET(C, CN),
18585 REGSET(cr, CN), REGSET(CR, CN),
18587 /* ARM banked registers. */
18588 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
18589 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
18590 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
18591 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
18592 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
18593 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
18594 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
18596 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
18597 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
18598 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
18599 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
18600 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
18601 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
18602 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
18603 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
18605 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
18606 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
18607 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
18608 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
18609 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
18610 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
18611 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
18612 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
18613 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
18615 /* FPA registers. */
18616 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
18617 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
18619 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
18620 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
18622 /* VFP SP registers. */
18623 REGSET(s,VFS), REGSET(S,VFS),
18624 REGSETH(s,VFS), REGSETH(S,VFS),
18626 /* VFP DP Registers. */
18627 REGSET(d,VFD), REGSET(D,VFD),
18628 /* Extra Neon DP registers. */
18629 REGSETH(d,VFD), REGSETH(D,VFD),
18631 /* Neon QP registers. */
18632 REGSET2(q,NQ), REGSET2(Q,NQ),
18634 /* VFP control registers. */
18635 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
18636 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
18637 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
18638 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
18639 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
18640 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
18642 /* Maverick DSP coprocessor registers. */
18643 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
18644 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
18646 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
18647 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
18648 REGDEF(dspsc,0,DSPSC),
18650 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
18651 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
18652 REGDEF(DSPSC,0,DSPSC),
18654 /* iWMMXt data registers - p0, c0-15. */
18655 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
18657 /* iWMMXt control registers - p1, c0-3. */
18658 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
18659 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
18660 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
18661 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
18663 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18664 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
18665 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
18666 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
18667 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
18669 /* XScale accumulator registers. */
18670 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
18676 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18677 within psr_required_here. */
18678 static const struct asm_psr psrs[] =
18680 /* Backward compatibility notation. Note that "all" is no longer
18681 truly all possible PSR bits. */
18682 {"all", PSR_c | PSR_f},
18686 /* Individual flags. */
18692 /* Combinations of flags. */
18693 {"fs", PSR_f | PSR_s},
18694 {"fx", PSR_f | PSR_x},
18695 {"fc", PSR_f | PSR_c},
18696 {"sf", PSR_s | PSR_f},
18697 {"sx", PSR_s | PSR_x},
18698 {"sc", PSR_s | PSR_c},
18699 {"xf", PSR_x | PSR_f},
18700 {"xs", PSR_x | PSR_s},
18701 {"xc", PSR_x | PSR_c},
18702 {"cf", PSR_c | PSR_f},
18703 {"cs", PSR_c | PSR_s},
18704 {"cx", PSR_c | PSR_x},
18705 {"fsx", PSR_f | PSR_s | PSR_x},
18706 {"fsc", PSR_f | PSR_s | PSR_c},
18707 {"fxs", PSR_f | PSR_x | PSR_s},
18708 {"fxc", PSR_f | PSR_x | PSR_c},
18709 {"fcs", PSR_f | PSR_c | PSR_s},
18710 {"fcx", PSR_f | PSR_c | PSR_x},
18711 {"sfx", PSR_s | PSR_f | PSR_x},
18712 {"sfc", PSR_s | PSR_f | PSR_c},
18713 {"sxf", PSR_s | PSR_x | PSR_f},
18714 {"sxc", PSR_s | PSR_x | PSR_c},
18715 {"scf", PSR_s | PSR_c | PSR_f},
18716 {"scx", PSR_s | PSR_c | PSR_x},
18717 {"xfs", PSR_x | PSR_f | PSR_s},
18718 {"xfc", PSR_x | PSR_f | PSR_c},
18719 {"xsf", PSR_x | PSR_s | PSR_f},
18720 {"xsc", PSR_x | PSR_s | PSR_c},
18721 {"xcf", PSR_x | PSR_c | PSR_f},
18722 {"xcs", PSR_x | PSR_c | PSR_s},
18723 {"cfs", PSR_c | PSR_f | PSR_s},
18724 {"cfx", PSR_c | PSR_f | PSR_x},
18725 {"csf", PSR_c | PSR_s | PSR_f},
18726 {"csx", PSR_c | PSR_s | PSR_x},
18727 {"cxf", PSR_c | PSR_x | PSR_f},
18728 {"cxs", PSR_c | PSR_x | PSR_s},
18729 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
18730 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
18731 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
18732 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
18733 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
18734 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
18735 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
18736 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
18737 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
18738 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
18739 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
18740 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
18741 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
18742 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
18743 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
18744 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
18745 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
18746 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
18747 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
18748 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
18749 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
18750 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
18751 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
18752 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
18755 /* Table of V7M psr names. */
18756 static const struct asm_psr v7m_psrs[] =
18758 {"apsr", 0 }, {"APSR", 0 },
18759 {"iapsr", 1 }, {"IAPSR", 1 },
18760 {"eapsr", 2 }, {"EAPSR", 2 },
18761 {"psr", 3 }, {"PSR", 3 },
18762 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18763 {"ipsr", 5 }, {"IPSR", 5 },
18764 {"epsr", 6 }, {"EPSR", 6 },
18765 {"iepsr", 7 }, {"IEPSR", 7 },
18766 {"msp", 8 }, {"MSP", 8 },
18767 {"psp", 9 }, {"PSP", 9 },
18768 {"primask", 16}, {"PRIMASK", 16},
18769 {"basepri", 17}, {"BASEPRI", 17},
18770 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18771 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18772 {"faultmask", 19}, {"FAULTMASK", 19},
18773 {"control", 20}, {"CONTROL", 20}
18776 /* Table of all shift-in-operand names. */
18777 static const struct asm_shift_name shift_names [] =
18779 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
18780 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
18781 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
18782 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
18783 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
18784 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
18787 /* Table of all explicit relocation names. */
18789 static struct reloc_entry reloc_names[] =
18791 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
18792 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
18793 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
18794 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
18795 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
18796 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
18797 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
18798 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
18799 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
18800 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
18801 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
18802 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
18803 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
18804 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
18805 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
18806 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
18807 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
18808 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
18812 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18813 static const struct asm_cond conds[] =
18817 {"cs", 0x2}, {"hs", 0x2},
18818 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18832 #define UL_BARRIER(L,U,CODE,FEAT) \
18833 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18834 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18836 static struct asm_barrier_opt barrier_opt_names[] =
18838 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
18839 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
18840 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
18841 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
18842 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
18843 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
18844 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
18845 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
18846 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
18847 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
18848 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
18849 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
18850 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
18851 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
18852 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
18853 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
18858 /* Table of ARM-format instructions. */
18860 /* Macros for gluing together operand strings. N.B. In all cases
18861 other than OPS0, the trailing OP_stop comes from default
18862 zero-initialization of the unspecified elements of the array. */
18863 #define OPS0() { OP_stop, }
18864 #define OPS1(a) { OP_##a, }
18865 #define OPS2(a,b) { OP_##a,OP_##b, }
18866 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18867 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18868 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18869 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18871 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18872 This is useful when mixing operands for ARM and THUMB, i.e. using the
18873 MIX_ARM_THUMB_OPERANDS macro.
18874 In order to use these macros, prefix the number of operands with _
18876 #define OPS_1(a) { a, }
18877 #define OPS_2(a,b) { a,b, }
18878 #define OPS_3(a,b,c) { a,b,c, }
18879 #define OPS_4(a,b,c,d) { a,b,c,d, }
18880 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18881 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18883 /* These macros abstract out the exact format of the mnemonic table and
18884 save some repeated characters. */
18886 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18887 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18888 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18889 THUMB_VARIANT, do_##ae, do_##te }
18891 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18892 a T_MNEM_xyz enumerator. */
18893 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18894 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18895 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18896 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18898 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18899 infix after the third character. */
18900 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18901 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18902 THUMB_VARIANT, do_##ae, do_##te }
18903 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18904 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18905 THUMB_VARIANT, do_##ae, do_##te }
18906 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18907 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18908 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18909 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18910 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18911 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18912 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18913 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18915 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18916 field is still 0xE. Many of the Thumb variants can be executed
18917 conditionally, so this is checked separately. */
18918 #define TUE(mnem, op, top, nops, ops, ae, te) \
18919 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18920 THUMB_VARIANT, do_##ae, do_##te }
18922 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18923 Used by mnemonics that have very minimal differences in the encoding for
18924 ARM and Thumb variants and can be handled in a common function. */
18925 #define TUEc(mnem, op, top, nops, ops, en) \
18926 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18927 THUMB_VARIANT, do_##en, do_##en }
18929 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18930 condition code field. */
18931 #define TUF(mnem, op, top, nops, ops, ae, te) \
18932 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18933 THUMB_VARIANT, do_##ae, do_##te }
18935 /* ARM-only variants of all the above. */
18936 #define CE(mnem, op, nops, ops, ae) \
18937 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18939 #define C3(mnem, op, nops, ops, ae) \
18940 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18942 /* Legacy mnemonics that always have conditional infix after the third
18944 #define CL(mnem, op, nops, ops, ae) \
18945 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18946 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18948 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18949 #define cCE(mnem, op, nops, ops, ae) \
18950 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18952 /* Legacy coprocessor instructions where conditional infix and conditional
18953 suffix are ambiguous. For consistency this includes all FPA instructions,
18954 not just the potentially ambiguous ones. */
18955 #define cCL(mnem, op, nops, ops, ae) \
18956 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18957 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18959 /* Coprocessor, takes either a suffix or a position-3 infix
18960 (for an FPA corner case). */
18961 #define C3E(mnem, op, nops, ops, ae) \
18962 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18963 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18965 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18966 { m1 #m2 m3, OPS##nops ops, \
18967 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18968 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18970 #define CM(m1, m2, op, nops, ops, ae) \
18971 xCM_ (m1, , m2, op, nops, ops, ae), \
18972 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18973 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18974 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18975 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18976 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18977 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18978 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18979 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18980 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18981 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18982 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18983 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18984 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18985 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18986 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18987 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18988 xCM_ (m1, le, m2, op, nops, ops, ae), \
18989 xCM_ (m1, al, m2, op, nops, ops, ae)
18991 #define UE(mnem, op, nops, ops, ae) \
18992 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18994 #define UF(mnem, op, nops, ops, ae) \
18995 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18997 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18998 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18999 use the same encoding function for each. */
19000 #define NUF(mnem, op, nops, ops, enc) \
19001 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19002 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19004 /* Neon data processing, version which indirects through neon_enc_tab for
19005 the various overloaded versions of opcodes. */
19006 #define nUF(mnem, op, nops, ops, enc) \
19007 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19008 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19010 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19012 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19013 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19014 THUMB_VARIANT, do_##enc, do_##enc }
19016 #define NCE(mnem, op, nops, ops, enc) \
19017 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19019 #define NCEF(mnem, op, nops, ops, enc) \
19020 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19022 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19023 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19024 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19025 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19027 #define nCE(mnem, op, nops, ops, enc) \
19028 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19030 #define nCEF(mnem, op, nops, ops, enc) \
19031 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19035 static const struct asm_opcode insns[] =
19037 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19038 #define THUMB_VARIANT & arm_ext_v4t
19039 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
19040 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
19041 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
19042 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
19043 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
19044 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
19045 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
19046 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
19047 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
19048 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
19049 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
19050 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
19051 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
19052 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
19053 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
19054 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
19056 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19057 for setting PSR flag bits. They are obsolete in V6 and do not
19058 have Thumb equivalents. */
19059 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
19060 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
19061 CL("tstp", 110f000, 2, (RR, SH), cmp),
19062 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
19063 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
19064 CL("cmpp", 150f000, 2, (RR, SH), cmp),
19065 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
19066 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
19067 CL("cmnp", 170f000, 2, (RR, SH), cmp),
19069 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
19070 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
19071 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
19072 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
19074 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
19075 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
19076 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
19078 OP_ADDRGLDR),ldst, t_ldst),
19079 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
19081 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19082 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19083 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19084 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19085 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19086 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19088 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
19089 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
19090 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
19091 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
19094 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
19095 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
19096 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
19097 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
19099 /* Thumb-compatibility pseudo ops. */
19100 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
19101 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
19102 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
19103 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
19104 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
19105 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
19106 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
19107 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
19108 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
19109 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
19110 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
19111 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
19113 /* These may simplify to neg. */
19114 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
19115 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
19117 #undef THUMB_VARIANT
19118 #define THUMB_VARIANT & arm_ext_v6
19120 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
19122 /* V1 instructions with no Thumb analogue prior to V6T2. */
19123 #undef THUMB_VARIANT
19124 #define THUMB_VARIANT & arm_ext_v6t2
19126 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
19127 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
19128 CL("teqp", 130f000, 2, (RR, SH), cmp),
19130 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
19131 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
19132 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
19133 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
19135 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19136 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19138 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19139 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19141 /* V1 instructions with no Thumb analogue at all. */
19142 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
19143 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
19145 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
19146 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
19147 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
19148 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
19149 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
19150 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
19151 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
19152 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
19155 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19156 #undef THUMB_VARIANT
19157 #define THUMB_VARIANT & arm_ext_v4t
19159 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
19160 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
19162 #undef THUMB_VARIANT
19163 #define THUMB_VARIANT & arm_ext_v6t2
19165 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
19166 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
19168 /* Generic coprocessor instructions. */
19169 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
19170 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19171 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19172 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19173 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19174 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
19175 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
19178 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19180 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
19181 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
19184 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19185 #undef THUMB_VARIANT
19186 #define THUMB_VARIANT & arm_ext_msr
19188 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
19189 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
19192 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19193 #undef THUMB_VARIANT
19194 #define THUMB_VARIANT & arm_ext_v6t2
19196 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19197 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19198 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19199 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19200 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19201 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19202 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19203 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19206 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19207 #undef THUMB_VARIANT
19208 #define THUMB_VARIANT & arm_ext_v4t
19210 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19211 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19212 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19213 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19214 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19215 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19218 #define ARM_VARIANT & arm_ext_v4t_5
19220 /* ARM Architecture 4T. */
19221 /* Note: bx (and blx) are required on V5, even if the processor does
19222 not support Thumb. */
19223 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
19226 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19227 #undef THUMB_VARIANT
19228 #define THUMB_VARIANT & arm_ext_v5t
19230 /* Note: blx has 2 variants; the .value coded here is for
19231 BLX(2). Only this variant has conditional execution. */
19232 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
19233 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
19235 #undef THUMB_VARIANT
19236 #define THUMB_VARIANT & arm_ext_v6t2
19238 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
19239 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19240 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19241 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19242 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19243 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
19244 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
19245 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
19248 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19249 #undef THUMB_VARIANT
19250 #define THUMB_VARIANT & arm_ext_v5exp
19252 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19253 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19254 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19255 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19257 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19258 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19260 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19261 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19262 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19263 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19265 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19266 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19267 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19268 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19270 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19271 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19273 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19274 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19275 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19276 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19279 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19280 #undef THUMB_VARIANT
19281 #define THUMB_VARIANT & arm_ext_v6t2
19283 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
19284 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
19286 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
19287 ADDRGLDRS), ldrd, t_ldstd),
19289 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19290 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19293 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19295 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
19298 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19299 #undef THUMB_VARIANT
19300 #define THUMB_VARIANT & arm_ext_v6
19302 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
19303 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
19304 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
19305 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
19306 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
19307 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19308 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19309 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19310 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19311 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
19313 #undef THUMB_VARIANT
19314 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19316 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
19317 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
19319 #undef THUMB_VARIANT
19320 #define THUMB_VARIANT & arm_ext_v6t2
19322 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19323 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19325 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
19326 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
19328 /* ARM V6 not included in V7M. */
19329 #undef THUMB_VARIANT
19330 #define THUMB_VARIANT & arm_ext_v6_notm
19331 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
19332 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
19333 UF(rfeib, 9900a00, 1, (RRw), rfe),
19334 UF(rfeda, 8100a00, 1, (RRw), rfe),
19335 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
19336 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
19337 UF(rfefa, 8100a00, 1, (RRw), rfe),
19338 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
19339 UF(rfeed, 9900a00, 1, (RRw), rfe),
19340 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
19341 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
19342 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
19343 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
19344 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
19345 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
19346 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
19347 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
19348 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
19349 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
19351 /* ARM V6 not included in V7M (eg. integer SIMD). */
19352 #undef THUMB_VARIANT
19353 #define THUMB_VARIANT & arm_ext_v6_dsp
19354 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
19355 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
19356 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19357 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19358 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19359 /* Old name for QASX. */
19360 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19361 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19362 /* Old name for QSAX. */
19363 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19364 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19365 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19366 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19367 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19368 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19369 /* Old name for SASX. */
19370 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19371 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19372 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19373 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19374 /* Old name for SHASX. */
19375 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19376 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19377 /* Old name for SHSAX. */
19378 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19379 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19380 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19381 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19382 /* Old name for SSAX. */
19383 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19384 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19385 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19386 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19387 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19388 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19389 /* Old name for UASX. */
19390 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19391 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19392 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19393 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19394 /* Old name for UHASX. */
19395 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19396 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19397 /* Old name for UHSAX. */
19398 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19399 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19400 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19401 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19402 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19403 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19404 /* Old name for UQASX. */
19405 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19406 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19407 /* Old name for UQSAX. */
19408 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19409 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19410 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19411 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19412 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19413 /* Old name for USAX. */
19414 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19415 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19416 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19417 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19418 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19419 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19420 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19421 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19422 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19423 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19424 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19425 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19426 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19427 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19428 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19429 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19430 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19431 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19432 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19433 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19434 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19435 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19436 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19437 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19438 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19439 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19440 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19441 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19442 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19443 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
19444 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
19445 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19446 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19447 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
19450 #define ARM_VARIANT & arm_ext_v6k
19451 #undef THUMB_VARIANT
19452 #define THUMB_VARIANT & arm_ext_v6k
19454 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
19455 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
19456 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
19457 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
19459 #undef THUMB_VARIANT
19460 #define THUMB_VARIANT & arm_ext_v6_notm
19461 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
19463 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
19464 RRnpcb), strexd, t_strexd),
19466 #undef THUMB_VARIANT
19467 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19468 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
19470 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
19472 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
19474 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
19476 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
19479 #define ARM_VARIANT & arm_ext_sec
19480 #undef THUMB_VARIANT
19481 #define THUMB_VARIANT & arm_ext_sec
19483 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
19486 #define ARM_VARIANT & arm_ext_virt
19487 #undef THUMB_VARIANT
19488 #define THUMB_VARIANT & arm_ext_virt
19490 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
19491 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
19494 #define ARM_VARIANT & arm_ext_pan
19495 #undef THUMB_VARIANT
19496 #define THUMB_VARIANT & arm_ext_pan
19498 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
19501 #define ARM_VARIANT & arm_ext_v6t2
19502 #undef THUMB_VARIANT
19503 #define THUMB_VARIANT & arm_ext_v6t2
19505 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
19506 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
19507 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
19508 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
19510 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
19511 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
19513 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19514 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19515 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19516 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19518 #undef THUMB_VARIANT
19519 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19520 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
19521 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
19523 /* Thumb-only instructions. */
19525 #define ARM_VARIANT NULL
19526 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
19527 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
19529 /* ARM does not really have an IT instruction, so always allow it.
19530 The opcode is copied from Thumb in order to allow warnings in
19531 -mimplicit-it=[never | arm] modes. */
19533 #define ARM_VARIANT & arm_ext_v1
19534 #undef THUMB_VARIANT
19535 #define THUMB_VARIANT & arm_ext_v6t2
19537 TUE("it", bf08, bf08, 1, (COND), it, t_it),
19538 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
19539 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
19540 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
19541 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
19542 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
19543 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
19544 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
19545 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
19546 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
19547 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
19548 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
19549 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
19550 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
19551 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
19552 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19553 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
19554 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
19556 /* Thumb2 only instructions. */
19558 #define ARM_VARIANT NULL
19560 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
19561 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
19562 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
19563 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
19564 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
19565 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
19567 /* Hardware division instructions. */
19569 #define ARM_VARIANT & arm_ext_adiv
19570 #undef THUMB_VARIANT
19571 #define THUMB_VARIANT & arm_ext_div
19573 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
19574 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
19576 /* ARM V6M/V7 instructions. */
19578 #define ARM_VARIANT & arm_ext_barrier
19579 #undef THUMB_VARIANT
19580 #define THUMB_VARIANT & arm_ext_barrier
19582 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
19583 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
19584 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
19586 /* ARM V7 instructions. */
19588 #define ARM_VARIANT & arm_ext_v7
19589 #undef THUMB_VARIANT
19590 #define THUMB_VARIANT & arm_ext_v7
19592 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
19593 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
19596 #define ARM_VARIANT & arm_ext_mp
19597 #undef THUMB_VARIANT
19598 #define THUMB_VARIANT & arm_ext_mp
19600 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
19602 /* AArchv8 instructions. */
19604 #define ARM_VARIANT & arm_ext_v8
19606 /* Instructions shared between armv8-a and armv8-m. */
19607 #undef THUMB_VARIANT
19608 #define THUMB_VARIANT & arm_ext_atomics
19610 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19611 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19612 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19613 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
19614 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
19615 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
19616 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19617 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
19618 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19619 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
19621 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
19623 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
19625 #undef THUMB_VARIANT
19626 #define THUMB_VARIANT & arm_ext_v8
19628 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
19629 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
19630 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
19632 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
19634 /* ARMv8 T32 only. */
19636 #define ARM_VARIANT NULL
19637 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
19638 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
19639 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
19641 /* FP for ARMv8. */
19643 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19644 #undef THUMB_VARIANT
19645 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19647 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
19648 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
19649 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
19650 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
19651 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
19652 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
19653 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
19654 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
19655 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
19656 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
19657 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
19658 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
19659 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
19660 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
19661 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
19662 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
19663 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
19665 /* Crypto v1 extensions. */
19667 #define ARM_VARIANT & fpu_crypto_ext_armv8
19668 #undef THUMB_VARIANT
19669 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19671 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
19672 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
19673 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
19674 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
19675 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
19676 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
19677 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
19678 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
19679 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
19680 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
19681 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
19682 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
19683 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
19684 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
19687 #define ARM_VARIANT & crc_ext_armv8
19688 #undef THUMB_VARIANT
19689 #define THUMB_VARIANT & crc_ext_armv8
19690 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
19691 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
19692 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
19693 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
19694 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
19695 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
19697 /* ARMv8.2 RAS extension. */
19699 #define ARM_VARIANT & arm_ext_v8_2
19700 #undef THUMB_VARIANT
19701 #define THUMB_VARIANT & arm_ext_v8_2
19702 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
19705 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19706 #undef THUMB_VARIANT
19707 #define THUMB_VARIANT NULL
19709 cCE("wfs", e200110, 1, (RR), rd),
19710 cCE("rfs", e300110, 1, (RR), rd),
19711 cCE("wfc", e400110, 1, (RR), rd),
19712 cCE("rfc", e500110, 1, (RR), rd),
19714 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
19715 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
19716 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
19717 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
19719 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
19720 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
19721 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
19722 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
19724 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
19725 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
19726 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
19727 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
19728 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
19729 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
19730 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
19731 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
19732 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
19733 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
19734 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
19735 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
19737 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
19738 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
19739 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
19740 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
19741 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
19742 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
19743 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
19744 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
19745 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
19746 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
19747 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
19748 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
19750 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
19751 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
19752 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
19753 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
19754 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
19755 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
19756 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
19757 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
19758 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
19759 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
19760 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
19761 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
19763 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
19764 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
19765 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
19766 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
19767 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
19768 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
19769 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
19770 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
19771 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
19772 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
19773 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
19774 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
19776 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
19777 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
19778 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
19779 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
19780 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
19781 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
19782 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
19783 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
19784 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
19785 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
19786 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
19787 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
19789 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
19790 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
19791 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
19792 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
19793 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
19794 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
19795 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
19796 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
19797 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
19798 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
19799 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
19800 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
19802 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
19803 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
19804 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
19805 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
19806 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
19807 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
19808 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
19809 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
19810 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
19811 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
19812 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
19813 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
19815 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
19816 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
19817 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
19818 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
19819 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
19820 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
19821 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
19822 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
19823 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
19824 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
19825 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
19826 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
19828 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
19829 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
19830 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
19831 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
19832 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
19833 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
19834 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
19835 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
19836 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
19837 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
19838 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
19839 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
19841 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
19842 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
19843 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
19844 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
19845 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
19846 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
19847 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
19848 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
19849 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
19850 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
19851 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
19852 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
19854 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
19855 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
19856 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
19857 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
19858 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
19859 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
19860 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
19861 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
19862 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
19863 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
19864 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
19865 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
19867 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
19868 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
19869 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
19870 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
19871 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
19872 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
19873 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
19874 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
19875 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
19876 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
19877 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
19878 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
19880 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
19881 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
19882 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
19883 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
19884 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
19885 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
19886 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
19887 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
19888 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
19889 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
19890 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
19891 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
19893 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
19894 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
19895 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
19896 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
19897 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
19898 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
19899 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
19900 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
19901 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
19902 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
19903 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
19904 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
19906 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
19907 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
19908 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
19909 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
19910 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
19911 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
19912 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
19913 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
19914 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
19915 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
19916 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
19917 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
19919 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
19920 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
19921 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
19922 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
19923 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
19924 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
19925 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
19926 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
19927 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
19928 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
19929 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
19930 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
19932 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
19933 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
19934 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
19935 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
19936 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
19937 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19938 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19939 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19940 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
19941 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
19942 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
19943 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
19945 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
19946 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
19947 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
19948 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
19949 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
19950 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19951 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19952 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19953 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
19954 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
19955 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
19956 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
19958 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
19959 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
19960 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
19961 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
19962 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
19963 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19964 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19965 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19966 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
19967 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
19968 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
19969 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
19971 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
19972 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
19973 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
19974 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
19975 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
19976 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19977 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19978 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19979 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
19980 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
19981 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
19982 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
19984 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
19985 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
19986 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
19987 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
19988 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
19989 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19990 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19991 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19992 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
19993 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
19994 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
19995 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
19997 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
19998 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
19999 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
20000 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
20001 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
20002 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20003 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20004 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20005 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
20006 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
20007 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
20008 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
20010 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
20011 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
20012 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
20013 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
20014 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
20015 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20016 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20017 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20018 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
20019 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
20020 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
20021 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
20023 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
20024 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
20025 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
20026 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
20027 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
20028 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20029 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20030 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20031 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
20032 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
20033 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
20034 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
20036 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
20037 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
20038 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
20039 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
20040 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
20041 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20042 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20043 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20044 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
20045 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
20046 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
20047 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
20049 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
20050 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
20051 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
20052 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
20053 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
20054 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20055 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20056 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20057 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
20058 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
20059 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
20060 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
20062 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
20063 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
20064 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
20065 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
20066 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
20067 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20068 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20069 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20070 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
20071 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
20072 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
20073 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
20075 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
20076 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
20077 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
20078 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
20079 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
20080 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20081 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20082 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20083 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
20084 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
20085 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
20086 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
20088 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
20089 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
20090 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
20091 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
20092 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
20093 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20094 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20095 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20096 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
20097 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
20098 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
20099 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
20101 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
20102 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
20103 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
20104 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
20106 cCL("flts", e000110, 2, (RF, RR), rn_rd),
20107 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
20108 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
20109 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
20110 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
20111 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
20112 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
20113 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
20114 cCL("flte", e080110, 2, (RF, RR), rn_rd),
20115 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
20116 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
20117 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
20119 /* The implementation of the FIX instruction is broken on some
20120 assemblers, in that it accepts a precision specifier as well as a
20121 rounding specifier, despite the fact that this is meaningless.
20122 To be more compatible, we accept it as well, though of course it
20123 does not set any bits. */
20124 cCE("fix", e100110, 2, (RR, RF), rd_rm),
20125 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
20126 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
20127 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
20128 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
20129 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
20130 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
20131 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
20132 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
20133 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
20134 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
20135 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
20136 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
20138 /* Instructions that were new with the real FPA, call them V2. */
20140 #define ARM_VARIANT & fpu_fpa_ext_v2
20142 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20143 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20144 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20145 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20146 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20147 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20150 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20152 /* Moves and type conversions. */
20153 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
20154 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
20155 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
20156 cCE("fmstat", ef1fa10, 0, (), noargs),
20157 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
20158 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
20159 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
20160 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
20161 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
20162 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
20163 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
20164 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
20165 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
20166 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
20168 /* Memory operations. */
20169 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
20170 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
20171 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20172 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20173 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20174 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20175 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20176 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20177 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20178 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20179 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20180 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20181 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20182 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20183 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20184 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20185 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20186 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20188 /* Monadic operations. */
20189 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
20190 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
20191 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
20193 /* Dyadic operations. */
20194 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20195 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20196 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20197 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20198 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20199 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20200 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20201 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20202 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20205 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
20206 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
20207 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
20208 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
20210 /* Double precision load/store are still present on single precision
20211 implementations. */
20212 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
20213 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
20214 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20215 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20216 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20217 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20218 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20219 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20220 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20221 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20224 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20226 /* Moves and type conversions. */
20227 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
20228 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
20229 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
20230 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
20231 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
20232 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
20233 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
20234 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
20235 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
20236 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
20237 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
20238 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
20239 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
20241 /* Monadic operations. */
20242 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
20243 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
20244 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
20246 /* Dyadic operations. */
20247 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20248 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20249 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20250 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20251 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20252 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20253 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20254 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20255 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20258 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
20259 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
20260 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
20261 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
20264 #define ARM_VARIANT & fpu_vfp_ext_v2
20266 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
20267 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
20268 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
20269 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
20271 /* Instructions which may belong to either the Neon or VFP instruction sets.
20272 Individual encoder functions perform additional architecture checks. */
20274 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20275 #undef THUMB_VARIANT
20276 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20278 /* These mnemonics are unique to VFP. */
20279 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
20280 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
20281 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20282 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20283 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20284 nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
20285 nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
20286 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
20287 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
20288 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
20290 /* Mnemonics shared by Neon and VFP. */
20291 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
20292 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
20293 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
20295 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
20296 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
20298 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
20299 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
20301 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20302 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20303 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20304 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20305 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20306 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20307 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
20308 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
20310 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
20311 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
20312 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
20313 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
20316 /* NOTE: All VMOV encoding is special-cased! */
20317 NCE(vmov, 0, 1, (VMOV), neon_mov),
20318 NCE(vmovq, 0, 1, (VMOV), neon_mov),
20321 #define ARM_VARIANT & arm_ext_fp16
20322 #undef THUMB_VARIANT
20323 #define THUMB_VARIANT & arm_ext_fp16
20324 /* New instructions added from v8.2, allowing the extraction and insertion of
20325 the upper 16 bits of a 32-bit vector register. */
20326 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
20327 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
20329 #undef THUMB_VARIANT
20330 #define THUMB_VARIANT & fpu_neon_ext_v1
20332 #define ARM_VARIANT & fpu_neon_ext_v1
20334 /* Data processing with three registers of the same length. */
20335 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20336 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
20337 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
20338 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
20339 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
20340 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
20341 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
20342 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
20343 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
20344 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20345 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
20346 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
20347 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
20348 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
20349 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
20350 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
20351 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
20352 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
20353 /* If not immediate, fall back to neon_dyadic_i64_su.
20354 shl_imm should accept I8 I16 I32 I64,
20355 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20356 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
20357 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
20358 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
20359 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
20360 /* Logic ops, types optional & ignored. */
20361 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20362 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20363 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20364 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20365 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20366 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20367 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20368 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20369 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
20370 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
20371 /* Bitfield ops, untyped. */
20372 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
20373 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
20374 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
20375 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
20376 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
20377 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
20378 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20379 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
20380 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
20381 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
20382 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
20383 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
20384 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
20385 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20386 back to neon_dyadic_if_su. */
20387 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
20388 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
20389 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
20390 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
20391 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
20392 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
20393 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
20394 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
20395 /* Comparison. Type I8 I16 I32 F32. */
20396 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
20397 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
20398 /* As above, D registers only. */
20399 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
20400 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
20401 /* Int and float variants, signedness unimportant. */
20402 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
20403 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
20404 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
20405 /* Add/sub take types I8 I16 I32 I64 F32. */
20406 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
20407 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
20408 /* vtst takes sizes 8, 16, 32. */
20409 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
20410 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
20411 /* VMUL takes I8 I16 I32 F32 P8. */
20412 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
20413 /* VQD{R}MULH takes S16 S32. */
20414 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
20415 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
20416 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
20417 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
20418 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
20419 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
20420 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
20421 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
20422 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
20423 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
20424 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
20425 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
20426 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
20427 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
20428 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
20429 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
20430 /* ARM v8.1 extension. */
20431 nUF (vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
20432 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
20433 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
20434 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
20436 /* Two address, int/float. Types S8 S16 S32 F32. */
20437 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
20438 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
20440 /* Data processing with two registers and a shift amount. */
20441 /* Right shifts, and variants with rounding.
20442 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20443 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
20444 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
20445 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
20446 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
20447 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
20448 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
20449 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
20450 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
20451 /* Shift and insert. Sizes accepted 8 16 32 64. */
20452 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
20453 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
20454 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
20455 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
20456 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20457 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
20458 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
20459 /* Right shift immediate, saturating & narrowing, with rounding variants.
20460 Types accepted S16 S32 S64 U16 U32 U64. */
20461 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
20462 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
20463 /* As above, unsigned. Types accepted S16 S32 S64. */
20464 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
20465 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
20466 /* Right shift narrowing. Types accepted I16 I32 I64. */
20467 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
20468 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
20469 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20470 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
20471 /* CVT with optional immediate for fixed-point variant. */
20472 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
20474 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
20475 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
20477 /* Data processing, three registers of different lengths. */
20478 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20479 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
20480 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
20481 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
20482 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
20483 /* If not scalar, fall back to neon_dyadic_long.
20484 Vector types as above, scalar types S16 S32 U16 U32. */
20485 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
20486 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
20487 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20488 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
20489 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
20490 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20491 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
20492 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
20493 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
20494 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
20495 /* Saturating doubling multiplies. Types S16 S32. */
20496 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
20497 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
20498 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
20499 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20500 S16 S32 U16 U32. */
20501 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
20503 /* Extract. Size 8. */
20504 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
20505 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
20507 /* Two registers, miscellaneous. */
20508 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20509 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
20510 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
20511 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
20512 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
20513 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
20514 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
20515 /* Vector replicate. Sizes 8 16 32. */
20516 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
20517 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
20518 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20519 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
20520 /* VMOVN. Types I16 I32 I64. */
20521 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
20522 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20523 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
20524 /* VQMOVUN. Types S16 S32 S64. */
20525 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
20526 /* VZIP / VUZP. Sizes 8 16 32. */
20527 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
20528 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
20529 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
20530 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
20531 /* VQABS / VQNEG. Types S8 S16 S32. */
20532 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
20533 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
20534 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
20535 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
20536 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20537 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
20538 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
20539 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
20540 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
20541 /* Reciprocal estimates. Types U32 F16 F32. */
20542 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
20543 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
20544 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
20545 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
20546 /* VCLS. Types S8 S16 S32. */
20547 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
20548 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
20549 /* VCLZ. Types I8 I16 I32. */
20550 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
20551 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
20552 /* VCNT. Size 8. */
20553 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
20554 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
20555 /* Two address, untyped. */
20556 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
20557 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
20558 /* VTRN. Sizes 8 16 32. */
20559 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
20560 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
20562 /* Table lookup. Size 8. */
20563 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
20564 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
20566 #undef THUMB_VARIANT
20567 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20569 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20571 /* Neon element/structure load/store. */
20572 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
20573 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
20574 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
20575 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
20576 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
20577 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
20578 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
20579 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
20581 #undef THUMB_VARIANT
20582 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20584 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20585 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
20586 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20587 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20588 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20589 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20590 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20591 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20592 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20593 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20595 #undef THUMB_VARIANT
20596 #define THUMB_VARIANT & fpu_vfp_ext_v3
20598 #define ARM_VARIANT & fpu_vfp_ext_v3
20600 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
20601 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20602 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20603 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20604 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20605 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20606 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20607 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20608 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20611 #define ARM_VARIANT & fpu_vfp_ext_fma
20612 #undef THUMB_VARIANT
20613 #define THUMB_VARIANT & fpu_vfp_ext_fma
20614 /* Mnemonics shared by Neon and VFP. These are included in the
20615 VFP FMA variant; NEON and VFP FMA always includes the NEON
20616 FMA instructions. */
20617 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
20618 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
20619 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20620 the v form should always be used. */
20621 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20622 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20623 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20624 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20625 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20626 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20628 #undef THUMB_VARIANT
20630 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20632 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20633 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20634 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20635 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20636 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20637 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20638 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
20639 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
20642 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20644 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
20645 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
20646 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
20647 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
20648 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
20649 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
20650 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
20651 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
20652 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
20653 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
20654 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
20655 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
20656 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
20657 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
20658 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
20659 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
20660 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
20661 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
20662 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
20663 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
20664 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20665 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20666 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20667 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20668 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20669 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20670 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
20671 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
20672 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
20673 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
20674 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
20675 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
20676 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
20677 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
20678 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
20679 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
20680 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
20681 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20682 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20683 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20684 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20685 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20686 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20687 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20688 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20689 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20690 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
20691 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20692 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20693 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20694 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20695 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20696 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20697 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20698 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20699 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20700 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20701 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20702 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20703 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20704 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20705 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20706 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20707 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20708 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20709 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20710 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20711 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20712 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
20713 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
20714 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20715 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20716 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20717 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20718 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20719 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20720 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20721 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20722 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20723 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20724 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20725 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20726 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20727 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20728 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20729 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20730 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20731 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20732 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
20733 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20734 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20735 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20736 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20737 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20738 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20739 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20740 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20741 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20742 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20743 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20744 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20745 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20746 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20747 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20748 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20749 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20750 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20751 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20752 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20753 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20754 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
20755 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20756 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20757 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20758 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20759 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20760 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20761 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20762 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20763 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20764 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20765 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20766 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20767 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20768 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20769 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20770 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20771 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20772 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20773 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20774 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20775 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
20776 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
20777 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20778 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20779 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20780 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20781 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20782 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20783 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20784 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20785 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20786 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
20787 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
20788 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
20789 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
20790 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
20791 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
20792 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20793 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20794 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20795 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
20796 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
20797 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
20798 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
20799 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
20800 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
20801 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20802 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20803 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20804 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20805 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
20808 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20810 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
20811 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
20812 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
20813 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
20814 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
20815 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
20816 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20817 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20818 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20819 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20820 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20821 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20822 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20823 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20824 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20825 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20826 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20827 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20828 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20829 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20830 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
20831 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20832 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20833 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20834 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20835 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20836 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20837 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20838 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20839 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20840 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20841 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20842 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20843 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20844 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20845 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20846 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20847 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20848 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20849 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20850 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20851 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20852 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20853 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20854 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20855 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20856 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20857 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20858 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20859 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20860 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20861 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20862 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20863 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20864 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20865 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20866 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20869 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20871 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
20872 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
20873 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
20874 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
20875 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
20876 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
20877 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
20878 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
20879 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
20880 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
20881 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
20882 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
20883 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
20884 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
20885 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
20886 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
20887 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
20888 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
20889 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
20890 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
20891 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
20892 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
20893 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
20894 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
20895 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
20896 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
20897 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
20898 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
20899 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
20900 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
20901 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
20902 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
20903 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
20904 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
20905 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
20906 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
20907 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
20908 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
20909 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
20910 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
20911 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
20912 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
20913 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
20914 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
20915 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
20916 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
20917 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
20918 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
20919 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
20920 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
20921 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
20922 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
20923 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
20924 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
20925 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
20926 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
20927 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
20928 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
20929 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
20930 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
20931 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
20932 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
20933 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
20934 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
20935 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20936 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20937 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20938 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20939 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20940 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20941 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20942 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20943 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
20944 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
20945 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
20946 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
20949 #define ARM_VARIANT NULL
20950 #undef THUMB_VARIANT
20951 #define THUMB_VARIANT & arm_ext_v8m
20952 TUE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
20953 TUE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
20956 #undef THUMB_VARIANT
20982 /* MD interface: bits in the object file. */
20984 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20985 for use in the a.out file, and stores them in the array pointed to by buf.
20986 This knows about the endian-ness of the target machine and does
20987 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20988 2 (short) and 4 (long) Floating numbers are put out as a series of
20989 LITTLENUMS (shorts, here at least). */
20992 md_number_to_chars (char * buf, valueT val, int n)
20994 if (target_big_endian)
20995 number_to_chars_bigendian (buf, val, n);
20997 number_to_chars_littleendian (buf, val, n);
21001 md_chars_to_number (char * buf, int n)
21004 unsigned char * where = (unsigned char *) buf;
21006 if (target_big_endian)
21011 result |= (*where++ & 255);
21019 result |= (where[n] & 255);
21026 /* MD interface: Sections. */
21028 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21029 that an rs_machine_dependent frag may reach. */
21032 arm_frag_max_var (fragS *fragp)
21034 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21035 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21037 Note that we generate relaxable instructions even for cases that don't
21038 really need it, like an immediate that's a trivial constant. So we're
21039 overestimating the instruction size for some of those cases. Rather
21040 than putting more intelligence here, it would probably be better to
21041 avoid generating a relaxation frag in the first place when it can be
21042 determined up front that a short instruction will suffice. */
21044 gas_assert (fragp->fr_type == rs_machine_dependent);
21048 /* Estimate the size of a frag before relaxing. Assume everything fits in
21052 md_estimate_size_before_relax (fragS * fragp,
21053 segT segtype ATTRIBUTE_UNUSED)
21059 /* Convert a machine dependent frag. */
21062 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
21064 unsigned long insn;
21065 unsigned long old_op;
21073 buf = fragp->fr_literal + fragp->fr_fix;
21075 old_op = bfd_get_16(abfd, buf);
21076 if (fragp->fr_symbol)
21078 exp.X_op = O_symbol;
21079 exp.X_add_symbol = fragp->fr_symbol;
21083 exp.X_op = O_constant;
21085 exp.X_add_number = fragp->fr_offset;
21086 opcode = fragp->fr_subtype;
21089 case T_MNEM_ldr_pc:
21090 case T_MNEM_ldr_pc2:
21091 case T_MNEM_ldr_sp:
21092 case T_MNEM_str_sp:
21099 if (fragp->fr_var == 4)
21101 insn = THUMB_OP32 (opcode);
21102 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
21104 insn |= (old_op & 0x700) << 4;
21108 insn |= (old_op & 7) << 12;
21109 insn |= (old_op & 0x38) << 13;
21111 insn |= 0x00000c00;
21112 put_thumb32_insn (buf, insn);
21113 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
21117 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
21119 pc_rel = (opcode == T_MNEM_ldr_pc2);
21122 if (fragp->fr_var == 4)
21124 insn = THUMB_OP32 (opcode);
21125 insn |= (old_op & 0xf0) << 4;
21126 put_thumb32_insn (buf, insn);
21127 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
21131 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
21132 exp.X_add_number -= 4;
21140 if (fragp->fr_var == 4)
21142 int r0off = (opcode == T_MNEM_mov
21143 || opcode == T_MNEM_movs) ? 0 : 8;
21144 insn = THUMB_OP32 (opcode);
21145 insn = (insn & 0xe1ffffff) | 0x10000000;
21146 insn |= (old_op & 0x700) << r0off;
21147 put_thumb32_insn (buf, insn);
21148 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
21152 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
21157 if (fragp->fr_var == 4)
21159 insn = THUMB_OP32(opcode);
21160 put_thumb32_insn (buf, insn);
21161 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
21164 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
21168 if (fragp->fr_var == 4)
21170 insn = THUMB_OP32(opcode);
21171 insn |= (old_op & 0xf00) << 14;
21172 put_thumb32_insn (buf, insn);
21173 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
21176 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
21179 case T_MNEM_add_sp:
21180 case T_MNEM_add_pc:
21181 case T_MNEM_inc_sp:
21182 case T_MNEM_dec_sp:
21183 if (fragp->fr_var == 4)
21185 /* ??? Choose between add and addw. */
21186 insn = THUMB_OP32 (opcode);
21187 insn |= (old_op & 0xf0) << 4;
21188 put_thumb32_insn (buf, insn);
21189 if (opcode == T_MNEM_add_pc)
21190 reloc_type = BFD_RELOC_ARM_T32_IMM12;
21192 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
21195 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
21203 if (fragp->fr_var == 4)
21205 insn = THUMB_OP32 (opcode);
21206 insn |= (old_op & 0xf0) << 4;
21207 insn |= (old_op & 0xf) << 16;
21208 put_thumb32_insn (buf, insn);
21209 if (insn & (1 << 20))
21210 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
21212 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
21215 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
21221 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21222 (enum bfd_reloc_code_real) reloc_type);
21223 fixp->fx_file = fragp->fr_file;
21224 fixp->fx_line = fragp->fr_line;
21225 fragp->fr_fix += fragp->fr_var;
21227 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21228 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
21229 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
21230 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
21233 /* Return the size of a relaxable immediate operand instruction.
21234 SHIFT and SIZE specify the form of the allowable immediate. */
21236 relax_immediate (fragS *fragp, int size, int shift)
21242 /* ??? Should be able to do better than this. */
21243 if (fragp->fr_symbol)
21246 low = (1 << shift) - 1;
21247 mask = (1 << (shift + size)) - (1 << shift);
21248 offset = fragp->fr_offset;
21249 /* Force misaligned offsets to 32-bit variant. */
21252 if (offset & ~mask)
21257 /* Get the address of a symbol during relaxation. */
21259 relaxed_symbol_addr (fragS *fragp, long stretch)
21265 sym = fragp->fr_symbol;
21266 sym_frag = symbol_get_frag (sym);
21267 know (S_GET_SEGMENT (sym) != absolute_section
21268 || sym_frag == &zero_address_frag);
21269 addr = S_GET_VALUE (sym) + fragp->fr_offset;
21271 /* If frag has yet to be reached on this pass, assume it will
21272 move by STRETCH just as we did. If this is not so, it will
21273 be because some frag between grows, and that will force
21277 && sym_frag->relax_marker != fragp->relax_marker)
21281 /* Adjust stretch for any alignment frag. Note that if have
21282 been expanding the earlier code, the symbol may be
21283 defined in what appears to be an earlier frag. FIXME:
21284 This doesn't handle the fr_subtype field, which specifies
21285 a maximum number of bytes to skip when doing an
21287 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
21289 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
21292 stretch = - ((- stretch)
21293 & ~ ((1 << (int) f->fr_offset) - 1));
21295 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
21307 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21310 relax_adr (fragS *fragp, asection *sec, long stretch)
21315 /* Assume worst case for symbols not known to be in the same section. */
21316 if (fragp->fr_symbol == NULL
21317 || !S_IS_DEFINED (fragp->fr_symbol)
21318 || sec != S_GET_SEGMENT (fragp->fr_symbol)
21319 || S_IS_WEAK (fragp->fr_symbol))
21322 val = relaxed_symbol_addr (fragp, stretch);
21323 addr = fragp->fr_address + fragp->fr_fix;
21324 addr = (addr + 4) & ~3;
21325 /* Force misaligned targets to 32-bit variant. */
21329 if (val < 0 || val > 1020)
21334 /* Return the size of a relaxable add/sub immediate instruction. */
21336 relax_addsub (fragS *fragp, asection *sec)
21341 buf = fragp->fr_literal + fragp->fr_fix;
21342 op = bfd_get_16(sec->owner, buf);
21343 if ((op & 0xf) == ((op >> 4) & 0xf))
21344 return relax_immediate (fragp, 8, 0);
21346 return relax_immediate (fragp, 3, 0);
21349 /* Return TRUE iff the definition of symbol S could be pre-empted
21350 (overridden) at link or load time. */
21352 symbol_preemptible (symbolS *s)
21354 /* Weak symbols can always be pre-empted. */
21358 /* Non-global symbols cannot be pre-empted. */
21359 if (! S_IS_EXTERNAL (s))
21363 /* In ELF, a global symbol can be marked protected, or private. In that
21364 case it can't be pre-empted (other definitions in the same link unit
21365 would violate the ODR). */
21366 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
21370 /* Other global symbols might be pre-empted. */
21374 /* Return the size of a relaxable branch instruction. BITS is the
21375 size of the offset field in the narrow instruction. */
21378 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
21384 /* Assume worst case for symbols not known to be in the same section. */
21385 if (!S_IS_DEFINED (fragp->fr_symbol)
21386 || sec != S_GET_SEGMENT (fragp->fr_symbol)
21387 || S_IS_WEAK (fragp->fr_symbol))
21391 /* A branch to a function in ARM state will require interworking. */
21392 if (S_IS_DEFINED (fragp->fr_symbol)
21393 && ARM_IS_FUNC (fragp->fr_symbol))
21397 if (symbol_preemptible (fragp->fr_symbol))
21400 val = relaxed_symbol_addr (fragp, stretch);
21401 addr = fragp->fr_address + fragp->fr_fix + 4;
21404 /* Offset is a signed value *2 */
21406 if (val >= limit || val < -limit)
21412 /* Relax a machine dependent frag. This returns the amount by which
21413 the current size of the frag should change. */
21416 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
21421 oldsize = fragp->fr_var;
21422 switch (fragp->fr_subtype)
21424 case T_MNEM_ldr_pc2:
21425 newsize = relax_adr (fragp, sec, stretch);
21427 case T_MNEM_ldr_pc:
21428 case T_MNEM_ldr_sp:
21429 case T_MNEM_str_sp:
21430 newsize = relax_immediate (fragp, 8, 2);
21434 newsize = relax_immediate (fragp, 5, 2);
21438 newsize = relax_immediate (fragp, 5, 1);
21442 newsize = relax_immediate (fragp, 5, 0);
21445 newsize = relax_adr (fragp, sec, stretch);
21451 newsize = relax_immediate (fragp, 8, 0);
21454 newsize = relax_branch (fragp, sec, 11, stretch);
21457 newsize = relax_branch (fragp, sec, 8, stretch);
21459 case T_MNEM_add_sp:
21460 case T_MNEM_add_pc:
21461 newsize = relax_immediate (fragp, 8, 2);
21463 case T_MNEM_inc_sp:
21464 case T_MNEM_dec_sp:
21465 newsize = relax_immediate (fragp, 7, 2);
21471 newsize = relax_addsub (fragp, sec);
21477 fragp->fr_var = newsize;
21478 /* Freeze wide instructions that are at or before the same location as
21479 in the previous pass. This avoids infinite loops.
21480 Don't freeze them unconditionally because targets may be artificially
21481 misaligned by the expansion of preceding frags. */
21482 if (stretch <= 0 && newsize > 2)
21484 md_convert_frag (sec->owner, sec, fragp);
21488 return newsize - oldsize;
21491 /* Round up a section size to the appropriate boundary. */
21494 md_section_align (segT segment ATTRIBUTE_UNUSED,
21497 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21498 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
21500 /* For a.out, force the section size to be aligned. If we don't do
21501 this, BFD will align it for us, but it will not write out the
21502 final bytes of the section. This may be a bug in BFD, but it is
21503 easier to fix it here since that is how the other a.out targets
21507 align = bfd_get_section_alignment (stdoutput, segment);
21508 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
21515 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21516 of an rs_align_code fragment. */
21519 arm_handle_align (fragS * fragP)
21521 static unsigned char const arm_noop[2][2][4] =
21524 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21525 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21528 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21529 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21532 static unsigned char const thumb_noop[2][2][2] =
21535 {0xc0, 0x46}, /* LE */
21536 {0x46, 0xc0}, /* BE */
21539 {0x00, 0xbf}, /* LE */
21540 {0xbf, 0x00} /* BE */
21543 static unsigned char const wide_thumb_noop[2][4] =
21544 { /* Wide Thumb-2 */
21545 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21546 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21549 unsigned bytes, fix, noop_size;
21551 const unsigned char * noop;
21552 const unsigned char *narrow_noop = NULL;
21557 if (fragP->fr_type != rs_align_code)
21560 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
21561 p = fragP->fr_literal + fragP->fr_fix;
21564 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
21565 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
21567 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
21569 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
21571 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
21572 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
21574 narrow_noop = thumb_noop[1][target_big_endian];
21575 noop = wide_thumb_noop[target_big_endian];
21578 noop = thumb_noop[0][target_big_endian];
21586 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
21587 ? selected_cpu : arm_arch_none,
21589 [target_big_endian];
21596 fragP->fr_var = noop_size;
21598 if (bytes & (noop_size - 1))
21600 fix = bytes & (noop_size - 1);
21602 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
21604 memset (p, 0, fix);
21611 if (bytes & noop_size)
21613 /* Insert a narrow noop. */
21614 memcpy (p, narrow_noop, noop_size);
21616 bytes -= noop_size;
21620 /* Use wide noops for the remainder */
21624 while (bytes >= noop_size)
21626 memcpy (p, noop, noop_size);
21628 bytes -= noop_size;
21632 fragP->fr_fix += fix;
21635 /* Called from md_do_align. Used to create an alignment
21636 frag in a code section. */
21639 arm_frag_align_code (int n, int max)
21643 /* We assume that there will never be a requirement
21644 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21645 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
21650 _("alignments greater than %d bytes not supported in .text sections."),
21651 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
21652 as_fatal ("%s", err_msg);
21655 p = frag_var (rs_align_code,
21656 MAX_MEM_FOR_RS_ALIGN_CODE,
21658 (relax_substateT) max,
21665 /* Perform target specific initialisation of a frag.
21666 Note - despite the name this initialisation is not done when the frag
21667 is created, but only when its type is assigned. A frag can be created
21668 and used a long time before its type is set, so beware of assuming that
21669 this initialisationis performed first. */
21673 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
21675 /* Record whether this frag is in an ARM or a THUMB area. */
21676 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
21679 #else /* OBJ_ELF is defined. */
21681 arm_init_frag (fragS * fragP, int max_chars)
21683 int frag_thumb_mode;
21685 /* If the current ARM vs THUMB mode has not already
21686 been recorded into this frag then do so now. */
21687 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
21688 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
21690 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
21692 /* Record a mapping symbol for alignment frags. We will delete this
21693 later if the alignment ends up empty. */
21694 switch (fragP->fr_type)
21697 case rs_align_test:
21699 mapping_state_2 (MAP_DATA, max_chars);
21701 case rs_align_code:
21702 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
21709 /* When we change sections we need to issue a new mapping symbol. */
21712 arm_elf_change_section (void)
21714 /* Link an unlinked unwind index table section to the .text section. */
21715 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
21716 && elf_linked_to_section (now_seg) == NULL)
21717 elf_linked_to_section (now_seg) = text_section;
21721 arm_elf_section_type (const char * str, size_t len)
21723 if (len == 5 && strncmp (str, "exidx", 5) == 0)
21724 return SHT_ARM_EXIDX;
21729 /* Code to deal with unwinding tables. */
21731 static void add_unwind_adjustsp (offsetT);
21733 /* Generate any deferred unwind frame offset. */
21736 flush_pending_unwind (void)
21740 offset = unwind.pending_offset;
21741 unwind.pending_offset = 0;
21743 add_unwind_adjustsp (offset);
21746 /* Add an opcode to this list for this function. Two-byte opcodes should
21747 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21751 add_unwind_opcode (valueT op, int length)
21753 /* Add any deferred stack adjustment. */
21754 if (unwind.pending_offset)
21755 flush_pending_unwind ();
21757 unwind.sp_restored = 0;
21759 if (unwind.opcode_count + length > unwind.opcode_alloc)
21761 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
21762 if (unwind.opcodes)
21763 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
21764 unwind.opcode_alloc);
21766 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
21771 unwind.opcodes[unwind.opcode_count] = op & 0xff;
21773 unwind.opcode_count++;
21777 /* Add unwind opcodes to adjust the stack pointer. */
21780 add_unwind_adjustsp (offsetT offset)
21784 if (offset > 0x200)
21786 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21791 /* Long form: 0xb2, uleb128. */
21792 /* This might not fit in a word so add the individual bytes,
21793 remembering the list is built in reverse order. */
21794 o = (valueT) ((offset - 0x204) >> 2);
21796 add_unwind_opcode (0, 1);
21798 /* Calculate the uleb128 encoding of the offset. */
21802 bytes[n] = o & 0x7f;
21808 /* Add the insn. */
21810 add_unwind_opcode (bytes[n - 1], 1);
21811 add_unwind_opcode (0xb2, 1);
21813 else if (offset > 0x100)
21815 /* Two short opcodes. */
21816 add_unwind_opcode (0x3f, 1);
21817 op = (offset - 0x104) >> 2;
21818 add_unwind_opcode (op, 1);
21820 else if (offset > 0)
21822 /* Short opcode. */
21823 op = (offset - 4) >> 2;
21824 add_unwind_opcode (op, 1);
21826 else if (offset < 0)
21829 while (offset > 0x100)
21831 add_unwind_opcode (0x7f, 1);
21834 op = ((offset - 4) >> 2) | 0x40;
21835 add_unwind_opcode (op, 1);
21839 /* Finish the list of unwind opcodes for this function. */
21841 finish_unwind_opcodes (void)
21845 if (unwind.fp_used)
21847 /* Adjust sp as necessary. */
21848 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
21849 flush_pending_unwind ();
21851 /* After restoring sp from the frame pointer. */
21852 op = 0x90 | unwind.fp_reg;
21853 add_unwind_opcode (op, 1);
21856 flush_pending_unwind ();
21860 /* Start an exception table entry. If idx is nonzero this is an index table
21864 start_unwind_section (const segT text_seg, int idx)
21866 const char * text_name;
21867 const char * prefix;
21868 const char * prefix_once;
21869 const char * group_name;
21873 size_t sec_name_len;
21880 prefix = ELF_STRING_ARM_unwind;
21881 prefix_once = ELF_STRING_ARM_unwind_once;
21882 type = SHT_ARM_EXIDX;
21886 prefix = ELF_STRING_ARM_unwind_info;
21887 prefix_once = ELF_STRING_ARM_unwind_info_once;
21888 type = SHT_PROGBITS;
21891 text_name = segment_name (text_seg);
21892 if (streq (text_name, ".text"))
21895 if (strncmp (text_name, ".gnu.linkonce.t.",
21896 strlen (".gnu.linkonce.t.")) == 0)
21898 prefix = prefix_once;
21899 text_name += strlen (".gnu.linkonce.t.");
21902 prefix_len = strlen (prefix);
21903 text_len = strlen (text_name);
21904 sec_name_len = prefix_len + text_len;
21905 sec_name = (char *) xmalloc (sec_name_len + 1);
21906 memcpy (sec_name, prefix, prefix_len);
21907 memcpy (sec_name + prefix_len, text_name, text_len);
21908 sec_name[prefix_len + text_len] = '\0';
21914 /* Handle COMDAT group. */
21915 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
21917 group_name = elf_group_name (text_seg);
21918 if (group_name == NULL)
21920 as_bad (_("Group section `%s' has no group signature"),
21921 segment_name (text_seg));
21922 ignore_rest_of_line ();
21925 flags |= SHF_GROUP;
21929 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
21931 /* Set the section link for index tables. */
21933 elf_linked_to_section (now_seg) = text_seg;
21937 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21938 personality routine data. Returns zero, or the index table value for
21939 an inline entry. */
21942 create_unwind_entry (int have_data)
21947 /* The current word of data. */
21949 /* The number of bytes left in this word. */
21952 finish_unwind_opcodes ();
21954 /* Remember the current text section. */
21955 unwind.saved_seg = now_seg;
21956 unwind.saved_subseg = now_subseg;
21958 start_unwind_section (now_seg, 0);
21960 if (unwind.personality_routine == NULL)
21962 if (unwind.personality_index == -2)
21965 as_bad (_("handlerdata in cantunwind frame"));
21966 return 1; /* EXIDX_CANTUNWIND. */
21969 /* Use a default personality routine if none is specified. */
21970 if (unwind.personality_index == -1)
21972 if (unwind.opcode_count > 3)
21973 unwind.personality_index = 1;
21975 unwind.personality_index = 0;
21978 /* Space for the personality routine entry. */
21979 if (unwind.personality_index == 0)
21981 if (unwind.opcode_count > 3)
21982 as_bad (_("too many unwind opcodes for personality routine 0"));
21986 /* All the data is inline in the index table. */
21989 while (unwind.opcode_count > 0)
21991 unwind.opcode_count--;
21992 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
21996 /* Pad with "finish" opcodes. */
21998 data = (data << 8) | 0xb0;
22005 /* We get two opcodes "free" in the first word. */
22006 size = unwind.opcode_count - 2;
22010 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22011 if (unwind.personality_index != -1)
22013 as_bad (_("attempt to recreate an unwind entry"));
22017 /* An extra byte is required for the opcode count. */
22018 size = unwind.opcode_count + 1;
22021 size = (size + 3) >> 2;
22023 as_bad (_("too many unwind opcodes"));
22025 frag_align (2, 0, 0);
22026 record_alignment (now_seg, 2);
22027 unwind.table_entry = expr_build_dot ();
22029 /* Allocate the table entry. */
22030 ptr = frag_more ((size << 2) + 4);
22031 /* PR 13449: Zero the table entries in case some of them are not used. */
22032 memset (ptr, 0, (size << 2) + 4);
22033 where = frag_now_fix () - ((size << 2) + 4);
22035 switch (unwind.personality_index)
22038 /* ??? Should this be a PLT generating relocation? */
22039 /* Custom personality routine. */
22040 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
22041 BFD_RELOC_ARM_PREL31);
22046 /* Set the first byte to the number of additional words. */
22047 data = size > 0 ? size - 1 : 0;
22051 /* ABI defined personality routines. */
22053 /* Three opcodes bytes are packed into the first word. */
22060 /* The size and first two opcode bytes go in the first word. */
22061 data = ((0x80 + unwind.personality_index) << 8) | size;
22066 /* Should never happen. */
22070 /* Pack the opcodes into words (MSB first), reversing the list at the same
22072 while (unwind.opcode_count > 0)
22076 md_number_to_chars (ptr, data, 4);
22081 unwind.opcode_count--;
22083 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
22086 /* Finish off the last word. */
22089 /* Pad with "finish" opcodes. */
22091 data = (data << 8) | 0xb0;
22093 md_number_to_chars (ptr, data, 4);
22098 /* Add an empty descriptor if there is no user-specified data. */
22099 ptr = frag_more (4);
22100 md_number_to_chars (ptr, 0, 4);
22107 /* Initialize the DWARF-2 unwind information for this procedure. */
22110 tc_arm_frame_initial_instructions (void)
22112 cfi_add_CFA_def_cfa (REG_SP, 0);
22114 #endif /* OBJ_ELF */
22116 /* Convert REGNAME to a DWARF-2 register number. */
22119 tc_arm_regname_to_dw2regnum (char *regname)
22121 int reg = arm_reg_parse (®name, REG_TYPE_RN);
22125 /* PR 16694: Allow VFP registers as well. */
22126 reg = arm_reg_parse (®name, REG_TYPE_VFS);
22130 reg = arm_reg_parse (®name, REG_TYPE_VFD);
22139 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
22143 exp.X_op = O_secrel;
22144 exp.X_add_symbol = symbol;
22145 exp.X_add_number = 0;
22146 emit_expr (&exp, size);
22150 /* MD interface: Symbol and relocation handling. */
22152 /* Return the address within the segment that a PC-relative fixup is
22153 relative to. For ARM, PC-relative fixups applied to instructions
22154 are generally relative to the location of the fixup plus 8 bytes.
22155 Thumb branches are offset by 4, and Thumb loads relative to PC
22156 require special handling. */
22159 md_pcrel_from_section (fixS * fixP, segT seg)
22161 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
22163 /* If this is pc-relative and we are going to emit a relocation
22164 then we just want to put out any pipeline compensation that the linker
22165 will need. Otherwise we want to use the calculated base.
22166 For WinCE we skip the bias for externals as well, since this
22167 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22169 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
22170 || (arm_force_relocation (fixP)
22172 && !S_IS_EXTERNAL (fixP->fx_addsy)
22178 switch (fixP->fx_r_type)
22180 /* PC relative addressing on the Thumb is slightly odd as the
22181 bottom two bits of the PC are forced to zero for the
22182 calculation. This happens *after* application of the
22183 pipeline offset. However, Thumb adrl already adjusts for
22184 this, so we need not do it again. */
22185 case BFD_RELOC_ARM_THUMB_ADD:
22188 case BFD_RELOC_ARM_THUMB_OFFSET:
22189 case BFD_RELOC_ARM_T32_OFFSET_IMM:
22190 case BFD_RELOC_ARM_T32_ADD_PC12:
22191 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22192 return (base + 4) & ~3;
22194 /* Thumb branches are simply offset by +4. */
22195 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22196 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22197 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22198 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22199 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22202 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22204 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22205 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22206 && ARM_IS_FUNC (fixP->fx_addsy)
22207 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22208 base = fixP->fx_where + fixP->fx_frag->fr_address;
22211 /* BLX is like branches above, but forces the low two bits of PC to
22213 case BFD_RELOC_THUMB_PCREL_BLX:
22215 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22216 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22217 && THUMB_IS_FUNC (fixP->fx_addsy)
22218 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22219 base = fixP->fx_where + fixP->fx_frag->fr_address;
22220 return (base + 4) & ~3;
22222 /* ARM mode branches are offset by +8. However, the Windows CE
22223 loader expects the relocation not to take this into account. */
22224 case BFD_RELOC_ARM_PCREL_BLX:
22226 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22227 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22228 && ARM_IS_FUNC (fixP->fx_addsy)
22229 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22230 base = fixP->fx_where + fixP->fx_frag->fr_address;
22233 case BFD_RELOC_ARM_PCREL_CALL:
22235 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22236 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22237 && THUMB_IS_FUNC (fixP->fx_addsy)
22238 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22239 base = fixP->fx_where + fixP->fx_frag->fr_address;
22242 case BFD_RELOC_ARM_PCREL_BRANCH:
22243 case BFD_RELOC_ARM_PCREL_JUMP:
22244 case BFD_RELOC_ARM_PLT32:
22246 /* When handling fixups immediately, because we have already
22247 discovered the value of a symbol, or the address of the frag involved
22248 we must account for the offset by +8, as the OS loader will never see the reloc.
22249 see fixup_segment() in write.c
22250 The S_IS_EXTERNAL test handles the case of global symbols.
22251 Those need the calculated base, not just the pipe compensation the linker will need. */
22253 && fixP->fx_addsy != NULL
22254 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22255 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
22263 /* ARM mode loads relative to PC are also offset by +8. Unlike
22264 branches, the Windows CE loader *does* expect the relocation
22265 to take this into account. */
22266 case BFD_RELOC_ARM_OFFSET_IMM:
22267 case BFD_RELOC_ARM_OFFSET_IMM8:
22268 case BFD_RELOC_ARM_HWLITERAL:
22269 case BFD_RELOC_ARM_LITERAL:
22270 case BFD_RELOC_ARM_CP_OFF_IMM:
22274 /* Other PC-relative relocations are un-offset. */
22280 static bfd_boolean flag_warn_syms = TRUE;
22283 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
22285 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22286 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22287 does mean that the resulting code might be very confusing to the reader.
22288 Also this warning can be triggered if the user omits an operand before
22289 an immediate address, eg:
22293 GAS treats this as an assignment of the value of the symbol foo to a
22294 symbol LDR, and so (without this code) it will not issue any kind of
22295 warning or error message.
22297 Note - ARM instructions are case-insensitive but the strings in the hash
22298 table are all stored in lower case, so we must first ensure that name is
22300 if (flag_warn_syms && arm_ops_hsh)
22302 char * nbuf = strdup (name);
22305 for (p = nbuf; *p; p++)
22307 if (hash_find (arm_ops_hsh, nbuf) != NULL)
22309 static struct hash_control * already_warned = NULL;
22311 if (already_warned == NULL)
22312 already_warned = hash_new ();
22313 /* Only warn about the symbol once. To keep the code
22314 simple we let hash_insert do the lookup for us. */
22315 if (hash_insert (already_warned, name, NULL) == NULL)
22316 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
22325 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22326 Otherwise we have no need to default values of symbols. */
22329 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
22332 if (name[0] == '_' && name[1] == 'G'
22333 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
22337 if (symbol_find (name))
22338 as_bad (_("GOT already in the symbol table"));
22340 GOT_symbol = symbol_new (name, undefined_section,
22341 (valueT) 0, & zero_address_frag);
22351 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22352 computed as two separate immediate values, added together. We
22353 already know that this value cannot be computed by just one ARM
22356 static unsigned int
22357 validate_immediate_twopart (unsigned int val,
22358 unsigned int * highpart)
22363 for (i = 0; i < 32; i += 2)
22364 if (((a = rotate_left (val, i)) & 0xff) != 0)
22370 * highpart = (a >> 8) | ((i + 24) << 7);
22372 else if (a & 0xff0000)
22374 if (a & 0xff000000)
22376 * highpart = (a >> 16) | ((i + 16) << 7);
22380 gas_assert (a & 0xff000000);
22381 * highpart = (a >> 24) | ((i + 8) << 7);
22384 return (a & 0xff) | (i << 7);
22391 validate_offset_imm (unsigned int val, int hwse)
22393 if ((hwse && val > 255) || val > 4095)
22398 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22399 negative immediate constant by altering the instruction. A bit of
22404 by inverting the second operand, and
22407 by negating the second operand. */
22410 negate_data_op (unsigned long * instruction,
22411 unsigned long value)
22414 unsigned long negated, inverted;
22416 negated = encode_arm_immediate (-value);
22417 inverted = encode_arm_immediate (~value);
22419 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
22422 /* First negates. */
22423 case OPCODE_SUB: /* ADD <-> SUB */
22424 new_inst = OPCODE_ADD;
22429 new_inst = OPCODE_SUB;
22433 case OPCODE_CMP: /* CMP <-> CMN */
22434 new_inst = OPCODE_CMN;
22439 new_inst = OPCODE_CMP;
22443 /* Now Inverted ops. */
22444 case OPCODE_MOV: /* MOV <-> MVN */
22445 new_inst = OPCODE_MVN;
22450 new_inst = OPCODE_MOV;
22454 case OPCODE_AND: /* AND <-> BIC */
22455 new_inst = OPCODE_BIC;
22460 new_inst = OPCODE_AND;
22464 case OPCODE_ADC: /* ADC <-> SBC */
22465 new_inst = OPCODE_SBC;
22470 new_inst = OPCODE_ADC;
22474 /* We cannot do anything. */
22479 if (value == (unsigned) FAIL)
22482 *instruction &= OPCODE_MASK;
22483 *instruction |= new_inst << DATA_OP_SHIFT;
22487 /* Like negate_data_op, but for Thumb-2. */
22489 static unsigned int
22490 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
22494 unsigned int negated, inverted;
22496 negated = encode_thumb32_immediate (-value);
22497 inverted = encode_thumb32_immediate (~value);
22499 rd = (*instruction >> 8) & 0xf;
22500 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
22503 /* ADD <-> SUB. Includes CMP <-> CMN. */
22504 case T2_OPCODE_SUB:
22505 new_inst = T2_OPCODE_ADD;
22509 case T2_OPCODE_ADD:
22510 new_inst = T2_OPCODE_SUB;
22514 /* ORR <-> ORN. Includes MOV <-> MVN. */
22515 case T2_OPCODE_ORR:
22516 new_inst = T2_OPCODE_ORN;
22520 case T2_OPCODE_ORN:
22521 new_inst = T2_OPCODE_ORR;
22525 /* AND <-> BIC. TST has no inverted equivalent. */
22526 case T2_OPCODE_AND:
22527 new_inst = T2_OPCODE_BIC;
22534 case T2_OPCODE_BIC:
22535 new_inst = T2_OPCODE_AND;
22540 case T2_OPCODE_ADC:
22541 new_inst = T2_OPCODE_SBC;
22545 case T2_OPCODE_SBC:
22546 new_inst = T2_OPCODE_ADC;
22550 /* We cannot do anything. */
22555 if (value == (unsigned int)FAIL)
22558 *instruction &= T2_OPCODE_MASK;
22559 *instruction |= new_inst << T2_DATA_OP_SHIFT;
22563 /* Read a 32-bit thumb instruction from buf. */
22564 static unsigned long
22565 get_thumb32_insn (char * buf)
22567 unsigned long insn;
22568 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
22569 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22575 /* We usually want to set the low bit on the address of thumb function
22576 symbols. In particular .word foo - . should have the low bit set.
22577 Generic code tries to fold the difference of two symbols to
22578 a constant. Prevent this and force a relocation when the first symbols
22579 is a thumb function. */
22582 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
22584 if (op == O_subtract
22585 && l->X_op == O_symbol
22586 && r->X_op == O_symbol
22587 && THUMB_IS_FUNC (l->X_add_symbol))
22589 l->X_op = O_subtract;
22590 l->X_op_symbol = r->X_add_symbol;
22591 l->X_add_number -= r->X_add_number;
22595 /* Process as normal. */
22599 /* Encode Thumb2 unconditional branches and calls. The encoding
22600 for the 2 are identical for the immediate values. */
22603 encode_thumb2_b_bl_offset (char * buf, offsetT value)
22605 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22608 addressT S, I1, I2, lo, hi;
22610 S = (value >> 24) & 0x01;
22611 I1 = (value >> 23) & 0x01;
22612 I2 = (value >> 22) & 0x01;
22613 hi = (value >> 12) & 0x3ff;
22614 lo = (value >> 1) & 0x7ff;
22615 newval = md_chars_to_number (buf, THUMB_SIZE);
22616 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22617 newval |= (S << 10) | hi;
22618 newval2 &= ~T2I1I2MASK;
22619 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
22620 md_number_to_chars (buf, newval, THUMB_SIZE);
22621 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22625 md_apply_fix (fixS * fixP,
22629 offsetT value = * valP;
22631 unsigned int newimm;
22632 unsigned long temp;
22634 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
22636 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
22638 /* Note whether this will delete the relocation. */
22640 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
22643 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22644 consistency with the behaviour on 32-bit hosts. Remember value
22646 value &= 0xffffffff;
22647 value ^= 0x80000000;
22648 value -= 0x80000000;
22651 fixP->fx_addnumber = value;
22653 /* Same treatment for fixP->fx_offset. */
22654 fixP->fx_offset &= 0xffffffff;
22655 fixP->fx_offset ^= 0x80000000;
22656 fixP->fx_offset -= 0x80000000;
22658 switch (fixP->fx_r_type)
22660 case BFD_RELOC_NONE:
22661 /* This will need to go in the object file. */
22665 case BFD_RELOC_ARM_IMMEDIATE:
22666 /* We claim that this fixup has been processed here,
22667 even if in fact we generate an error because we do
22668 not have a reloc for it, so tc_gen_reloc will reject it. */
22671 if (fixP->fx_addsy)
22673 const char *msg = 0;
22675 if (! S_IS_DEFINED (fixP->fx_addsy))
22676 msg = _("undefined symbol %s used as an immediate value");
22677 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
22678 msg = _("symbol %s is in a different section");
22679 else if (S_IS_WEAK (fixP->fx_addsy))
22680 msg = _("symbol %s is weak and may be overridden later");
22684 as_bad_where (fixP->fx_file, fixP->fx_line,
22685 msg, S_GET_NAME (fixP->fx_addsy));
22690 temp = md_chars_to_number (buf, INSN_SIZE);
22692 /* If the offset is negative, we should use encoding A2 for ADR. */
22693 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
22694 newimm = negate_data_op (&temp, value);
22697 newimm = encode_arm_immediate (value);
22699 /* If the instruction will fail, see if we can fix things up by
22700 changing the opcode. */
22701 if (newimm == (unsigned int) FAIL)
22702 newimm = negate_data_op (&temp, value);
22705 if (newimm == (unsigned int) FAIL)
22707 as_bad_where (fixP->fx_file, fixP->fx_line,
22708 _("invalid constant (%lx) after fixup"),
22709 (unsigned long) value);
22713 newimm |= (temp & 0xfffff000);
22714 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
22717 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22719 unsigned int highpart = 0;
22720 unsigned int newinsn = 0xe1a00000; /* nop. */
22722 if (fixP->fx_addsy)
22724 const char *msg = 0;
22726 if (! S_IS_DEFINED (fixP->fx_addsy))
22727 msg = _("undefined symbol %s used as an immediate value");
22728 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
22729 msg = _("symbol %s is in a different section");
22730 else if (S_IS_WEAK (fixP->fx_addsy))
22731 msg = _("symbol %s is weak and may be overridden later");
22735 as_bad_where (fixP->fx_file, fixP->fx_line,
22736 msg, S_GET_NAME (fixP->fx_addsy));
22741 newimm = encode_arm_immediate (value);
22742 temp = md_chars_to_number (buf, INSN_SIZE);
22744 /* If the instruction will fail, see if we can fix things up by
22745 changing the opcode. */
22746 if (newimm == (unsigned int) FAIL
22747 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
22749 /* No ? OK - try using two ADD instructions to generate
22751 newimm = validate_immediate_twopart (value, & highpart);
22753 /* Yes - then make sure that the second instruction is
22755 if (newimm != (unsigned int) FAIL)
22757 /* Still No ? Try using a negated value. */
22758 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
22759 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
22760 /* Otherwise - give up. */
22763 as_bad_where (fixP->fx_file, fixP->fx_line,
22764 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22769 /* Replace the first operand in the 2nd instruction (which
22770 is the PC) with the destination register. We have
22771 already added in the PC in the first instruction and we
22772 do not want to do it again. */
22773 newinsn &= ~ 0xf0000;
22774 newinsn |= ((newinsn & 0x0f000) << 4);
22777 newimm |= (temp & 0xfffff000);
22778 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
22780 highpart |= (newinsn & 0xfffff000);
22781 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
22785 case BFD_RELOC_ARM_OFFSET_IMM:
22786 if (!fixP->fx_done && seg->use_rela_p)
22789 case BFD_RELOC_ARM_LITERAL:
22795 if (validate_offset_imm (value, 0) == FAIL)
22797 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
22798 as_bad_where (fixP->fx_file, fixP->fx_line,
22799 _("invalid literal constant: pool needs to be closer"));
22801 as_bad_where (fixP->fx_file, fixP->fx_line,
22802 _("bad immediate value for offset (%ld)"),
22807 newval = md_chars_to_number (buf, INSN_SIZE);
22809 newval &= 0xfffff000;
22812 newval &= 0xff7ff000;
22813 newval |= value | (sign ? INDEX_UP : 0);
22815 md_number_to_chars (buf, newval, INSN_SIZE);
22818 case BFD_RELOC_ARM_OFFSET_IMM8:
22819 case BFD_RELOC_ARM_HWLITERAL:
22825 if (validate_offset_imm (value, 1) == FAIL)
22827 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
22828 as_bad_where (fixP->fx_file, fixP->fx_line,
22829 _("invalid literal constant: pool needs to be closer"));
22831 as_bad_where (fixP->fx_file, fixP->fx_line,
22832 _("bad immediate value for 8-bit offset (%ld)"),
22837 newval = md_chars_to_number (buf, INSN_SIZE);
22839 newval &= 0xfffff0f0;
22842 newval &= 0xff7ff0f0;
22843 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
22845 md_number_to_chars (buf, newval, INSN_SIZE);
22848 case BFD_RELOC_ARM_T32_OFFSET_U8:
22849 if (value < 0 || value > 1020 || value % 4 != 0)
22850 as_bad_where (fixP->fx_file, fixP->fx_line,
22851 _("bad immediate value for offset (%ld)"), (long) value);
22854 newval = md_chars_to_number (buf+2, THUMB_SIZE);
22856 md_number_to_chars (buf+2, newval, THUMB_SIZE);
22859 case BFD_RELOC_ARM_T32_OFFSET_IMM:
22860 /* This is a complicated relocation used for all varieties of Thumb32
22861 load/store instruction with immediate offset:
22863 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22864 *4, optional writeback(W)
22865 (doubleword load/store)
22867 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22868 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22869 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22870 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22871 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22873 Uppercase letters indicate bits that are already encoded at
22874 this point. Lowercase letters are our problem. For the
22875 second block of instructions, the secondary opcode nybble
22876 (bits 8..11) is present, and bit 23 is zero, even if this is
22877 a PC-relative operation. */
22878 newval = md_chars_to_number (buf, THUMB_SIZE);
22880 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
22882 if ((newval & 0xf0000000) == 0xe0000000)
22884 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22886 newval |= (1 << 23);
22889 if (value % 4 != 0)
22891 as_bad_where (fixP->fx_file, fixP->fx_line,
22892 _("offset not a multiple of 4"));
22898 as_bad_where (fixP->fx_file, fixP->fx_line,
22899 _("offset out of range"));
22904 else if ((newval & 0x000f0000) == 0x000f0000)
22906 /* PC-relative, 12-bit offset. */
22908 newval |= (1 << 23);
22913 as_bad_where (fixP->fx_file, fixP->fx_line,
22914 _("offset out of range"));
22919 else if ((newval & 0x00000100) == 0x00000100)
22921 /* Writeback: 8-bit, +/- offset. */
22923 newval |= (1 << 9);
22928 as_bad_where (fixP->fx_file, fixP->fx_line,
22929 _("offset out of range"));
22934 else if ((newval & 0x00000f00) == 0x00000e00)
22936 /* T-instruction: positive 8-bit offset. */
22937 if (value < 0 || value > 0xff)
22939 as_bad_where (fixP->fx_file, fixP->fx_line,
22940 _("offset out of range"));
22948 /* Positive 12-bit or negative 8-bit offset. */
22952 newval |= (1 << 23);
22962 as_bad_where (fixP->fx_file, fixP->fx_line,
22963 _("offset out of range"));
22970 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
22971 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
22974 case BFD_RELOC_ARM_SHIFT_IMM:
22975 newval = md_chars_to_number (buf, INSN_SIZE);
22976 if (((unsigned long) value) > 32
22978 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
22980 as_bad_where (fixP->fx_file, fixP->fx_line,
22981 _("shift expression is too large"));
22986 /* Shifts of zero must be done as lsl. */
22988 else if (value == 32)
22990 newval &= 0xfffff07f;
22991 newval |= (value & 0x1f) << 7;
22992 md_number_to_chars (buf, newval, INSN_SIZE);
22995 case BFD_RELOC_ARM_T32_IMMEDIATE:
22996 case BFD_RELOC_ARM_T32_ADD_IMM:
22997 case BFD_RELOC_ARM_T32_IMM12:
22998 case BFD_RELOC_ARM_T32_ADD_PC12:
22999 /* We claim that this fixup has been processed here,
23000 even if in fact we generate an error because we do
23001 not have a reloc for it, so tc_gen_reloc will reject it. */
23005 && ! S_IS_DEFINED (fixP->fx_addsy))
23007 as_bad_where (fixP->fx_file, fixP->fx_line,
23008 _("undefined symbol %s used as an immediate value"),
23009 S_GET_NAME (fixP->fx_addsy));
23013 newval = md_chars_to_number (buf, THUMB_SIZE);
23015 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
23018 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23019 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
23021 newimm = encode_thumb32_immediate (value);
23022 if (newimm == (unsigned int) FAIL)
23023 newimm = thumb32_negate_data_op (&newval, value);
23025 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
23026 && newimm == (unsigned int) FAIL)
23028 /* Turn add/sum into addw/subw. */
23029 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
23030 newval = (newval & 0xfeffffff) | 0x02000000;
23031 /* No flat 12-bit imm encoding for addsw/subsw. */
23032 if ((newval & 0x00100000) == 0)
23034 /* 12 bit immediate for addw/subw. */
23038 newval ^= 0x00a00000;
23041 newimm = (unsigned int) FAIL;
23047 if (newimm == (unsigned int)FAIL)
23049 as_bad_where (fixP->fx_file, fixP->fx_line,
23050 _("invalid constant (%lx) after fixup"),
23051 (unsigned long) value);
23055 newval |= (newimm & 0x800) << 15;
23056 newval |= (newimm & 0x700) << 4;
23057 newval |= (newimm & 0x0ff);
23059 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
23060 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
23063 case BFD_RELOC_ARM_SMC:
23064 if (((unsigned long) value) > 0xffff)
23065 as_bad_where (fixP->fx_file, fixP->fx_line,
23066 _("invalid smc expression"));
23067 newval = md_chars_to_number (buf, INSN_SIZE);
23068 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
23069 md_number_to_chars (buf, newval, INSN_SIZE);
23072 case BFD_RELOC_ARM_HVC:
23073 if (((unsigned long) value) > 0xffff)
23074 as_bad_where (fixP->fx_file, fixP->fx_line,
23075 _("invalid hvc expression"));
23076 newval = md_chars_to_number (buf, INSN_SIZE);
23077 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
23078 md_number_to_chars (buf, newval, INSN_SIZE);
23081 case BFD_RELOC_ARM_SWI:
23082 if (fixP->tc_fix_data != 0)
23084 if (((unsigned long) value) > 0xff)
23085 as_bad_where (fixP->fx_file, fixP->fx_line,
23086 _("invalid swi expression"));
23087 newval = md_chars_to_number (buf, THUMB_SIZE);
23089 md_number_to_chars (buf, newval, THUMB_SIZE);
23093 if (((unsigned long) value) > 0x00ffffff)
23094 as_bad_where (fixP->fx_file, fixP->fx_line,
23095 _("invalid swi expression"));
23096 newval = md_chars_to_number (buf, INSN_SIZE);
23098 md_number_to_chars (buf, newval, INSN_SIZE);
23102 case BFD_RELOC_ARM_MULTI:
23103 if (((unsigned long) value) > 0xffff)
23104 as_bad_where (fixP->fx_file, fixP->fx_line,
23105 _("invalid expression in load/store multiple"));
23106 newval = value | md_chars_to_number (buf, INSN_SIZE);
23107 md_number_to_chars (buf, newval, INSN_SIZE);
23111 case BFD_RELOC_ARM_PCREL_CALL:
23113 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23115 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23116 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23117 && THUMB_IS_FUNC (fixP->fx_addsy))
23118 /* Flip the bl to blx. This is a simple flip
23119 bit here because we generate PCREL_CALL for
23120 unconditional bls. */
23122 newval = md_chars_to_number (buf, INSN_SIZE);
23123 newval = newval | 0x10000000;
23124 md_number_to_chars (buf, newval, INSN_SIZE);
23130 goto arm_branch_common;
23132 case BFD_RELOC_ARM_PCREL_JUMP:
23133 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23135 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23136 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23137 && THUMB_IS_FUNC (fixP->fx_addsy))
23139 /* This would map to a bl<cond>, b<cond>,
23140 b<always> to a Thumb function. We
23141 need to force a relocation for this particular
23143 newval = md_chars_to_number (buf, INSN_SIZE);
23147 case BFD_RELOC_ARM_PLT32:
23149 case BFD_RELOC_ARM_PCREL_BRANCH:
23151 goto arm_branch_common;
23153 case BFD_RELOC_ARM_PCREL_BLX:
23156 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23158 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23159 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23160 && ARM_IS_FUNC (fixP->fx_addsy))
23162 /* Flip the blx to a bl and warn. */
23163 const char *name = S_GET_NAME (fixP->fx_addsy);
23164 newval = 0xeb000000;
23165 as_warn_where (fixP->fx_file, fixP->fx_line,
23166 _("blx to '%s' an ARM ISA state function changed to bl"),
23168 md_number_to_chars (buf, newval, INSN_SIZE);
23174 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
23175 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
23179 /* We are going to store value (shifted right by two) in the
23180 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23181 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23182 also be be clear. */
23184 as_bad_where (fixP->fx_file, fixP->fx_line,
23185 _("misaligned branch destination"));
23186 if ((value & (offsetT)0xfe000000) != (offsetT)0
23187 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
23188 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23190 if (fixP->fx_done || !seg->use_rela_p)
23192 newval = md_chars_to_number (buf, INSN_SIZE);
23193 newval |= (value >> 2) & 0x00ffffff;
23194 /* Set the H bit on BLX instructions. */
23198 newval |= 0x01000000;
23200 newval &= ~0x01000000;
23202 md_number_to_chars (buf, newval, INSN_SIZE);
23206 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
23207 /* CBZ can only branch forward. */
23209 /* Attempts to use CBZ to branch to the next instruction
23210 (which, strictly speaking, are prohibited) will be turned into
23213 FIXME: It may be better to remove the instruction completely and
23214 perform relaxation. */
23217 newval = md_chars_to_number (buf, THUMB_SIZE);
23218 newval = 0xbf00; /* NOP encoding T1 */
23219 md_number_to_chars (buf, newval, THUMB_SIZE);
23224 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23226 if (fixP->fx_done || !seg->use_rela_p)
23228 newval = md_chars_to_number (buf, THUMB_SIZE);
23229 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
23230 md_number_to_chars (buf, newval, THUMB_SIZE);
23235 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
23236 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
23237 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23239 if (fixP->fx_done || !seg->use_rela_p)
23241 newval = md_chars_to_number (buf, THUMB_SIZE);
23242 newval |= (value & 0x1ff) >> 1;
23243 md_number_to_chars (buf, newval, THUMB_SIZE);
23247 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
23248 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
23249 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23251 if (fixP->fx_done || !seg->use_rela_p)
23253 newval = md_chars_to_number (buf, THUMB_SIZE);
23254 newval |= (value & 0xfff) >> 1;
23255 md_number_to_chars (buf, newval, THUMB_SIZE);
23259 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23261 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23262 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23263 && ARM_IS_FUNC (fixP->fx_addsy)
23264 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
23266 /* Force a relocation for a branch 20 bits wide. */
23269 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
23270 as_bad_where (fixP->fx_file, fixP->fx_line,
23271 _("conditional branch out of range"));
23273 if (fixP->fx_done || !seg->use_rela_p)
23276 addressT S, J1, J2, lo, hi;
23278 S = (value & 0x00100000) >> 20;
23279 J2 = (value & 0x00080000) >> 19;
23280 J1 = (value & 0x00040000) >> 18;
23281 hi = (value & 0x0003f000) >> 12;
23282 lo = (value & 0x00000ffe) >> 1;
23284 newval = md_chars_to_number (buf, THUMB_SIZE);
23285 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23286 newval |= (S << 10) | hi;
23287 newval2 |= (J1 << 13) | (J2 << 11) | lo;
23288 md_number_to_chars (buf, newval, THUMB_SIZE);
23289 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
23293 case BFD_RELOC_THUMB_PCREL_BLX:
23294 /* If there is a blx from a thumb state function to
23295 another thumb function flip this to a bl and warn
23299 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23300 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23301 && THUMB_IS_FUNC (fixP->fx_addsy))
23303 const char *name = S_GET_NAME (fixP->fx_addsy);
23304 as_warn_where (fixP->fx_file, fixP->fx_line,
23305 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23307 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23308 newval = newval | 0x1000;
23309 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
23310 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
23315 goto thumb_bl_common;
23317 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23318 /* A bl from Thumb state ISA to an internal ARM state function
23319 is converted to a blx. */
23321 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23322 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23323 && ARM_IS_FUNC (fixP->fx_addsy)
23324 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
23326 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23327 newval = newval & ~0x1000;
23328 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
23329 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
23335 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
23336 /* For a BLX instruction, make sure that the relocation is rounded up
23337 to a word boundary. This follows the semantics of the instruction
23338 which specifies that bit 1 of the target address will come from bit
23339 1 of the base address. */
23340 value = (value + 3) & ~ 3;
23343 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
23344 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
23345 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
23348 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
23350 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
23351 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23352 else if ((value & ~0x1ffffff)
23353 && ((value & ~0x1ffffff) != ~0x1ffffff))
23354 as_bad_where (fixP->fx_file, fixP->fx_line,
23355 _("Thumb2 branch out of range"));
23358 if (fixP->fx_done || !seg->use_rela_p)
23359 encode_thumb2_b_bl_offset (buf, value);
23363 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23364 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
23365 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23367 if (fixP->fx_done || !seg->use_rela_p)
23368 encode_thumb2_b_bl_offset (buf, value);
23373 if (fixP->fx_done || !seg->use_rela_p)
23378 if (fixP->fx_done || !seg->use_rela_p)
23379 md_number_to_chars (buf, value, 2);
23383 case BFD_RELOC_ARM_TLS_CALL:
23384 case BFD_RELOC_ARM_THM_TLS_CALL:
23385 case BFD_RELOC_ARM_TLS_DESCSEQ:
23386 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
23387 case BFD_RELOC_ARM_TLS_GOTDESC:
23388 case BFD_RELOC_ARM_TLS_GD32:
23389 case BFD_RELOC_ARM_TLS_LE32:
23390 case BFD_RELOC_ARM_TLS_IE32:
23391 case BFD_RELOC_ARM_TLS_LDM32:
23392 case BFD_RELOC_ARM_TLS_LDO32:
23393 S_SET_THREAD_LOCAL (fixP->fx_addsy);
23396 case BFD_RELOC_ARM_GOT32:
23397 case BFD_RELOC_ARM_GOTOFF:
23400 case BFD_RELOC_ARM_GOT_PREL:
23401 if (fixP->fx_done || !seg->use_rela_p)
23402 md_number_to_chars (buf, value, 4);
23405 case BFD_RELOC_ARM_TARGET2:
23406 /* TARGET2 is not partial-inplace, so we need to write the
23407 addend here for REL targets, because it won't be written out
23408 during reloc processing later. */
23409 if (fixP->fx_done || !seg->use_rela_p)
23410 md_number_to_chars (buf, fixP->fx_offset, 4);
23414 case BFD_RELOC_RVA:
23416 case BFD_RELOC_ARM_TARGET1:
23417 case BFD_RELOC_ARM_ROSEGREL32:
23418 case BFD_RELOC_ARM_SBREL32:
23419 case BFD_RELOC_32_PCREL:
23421 case BFD_RELOC_32_SECREL:
23423 if (fixP->fx_done || !seg->use_rela_p)
23425 /* For WinCE we only do this for pcrel fixups. */
23426 if (fixP->fx_done || fixP->fx_pcrel)
23428 md_number_to_chars (buf, value, 4);
23432 case BFD_RELOC_ARM_PREL31:
23433 if (fixP->fx_done || !seg->use_rela_p)
23435 newval = md_chars_to_number (buf, 4) & 0x80000000;
23436 if ((value ^ (value >> 1)) & 0x40000000)
23438 as_bad_where (fixP->fx_file, fixP->fx_line,
23439 _("rel31 relocation overflow"));
23441 newval |= value & 0x7fffffff;
23442 md_number_to_chars (buf, newval, 4);
23447 case BFD_RELOC_ARM_CP_OFF_IMM:
23448 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
23449 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
23450 newval = md_chars_to_number (buf, INSN_SIZE);
23452 newval = get_thumb32_insn (buf);
23453 if ((newval & 0x0f200f00) == 0x0d000900)
23455 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23456 has permitted values that are multiples of 2, in the range 0
23458 if (value < -510 || value > 510 || (value & 1))
23459 as_bad_where (fixP->fx_file, fixP->fx_line,
23460 _("co-processor offset out of range"));
23462 else if (value < -1023 || value > 1023 || (value & 3))
23463 as_bad_where (fixP->fx_file, fixP->fx_line,
23464 _("co-processor offset out of range"));
23469 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23470 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
23471 newval = md_chars_to_number (buf, INSN_SIZE);
23473 newval = get_thumb32_insn (buf);
23475 newval &= 0xffffff00;
23478 newval &= 0xff7fff00;
23479 if ((newval & 0x0f200f00) == 0x0d000900)
23481 /* This is a fp16 vstr/vldr.
23483 It requires the immediate offset in the instruction is shifted
23484 left by 1 to be a half-word offset.
23486 Here, left shift by 1 first, and later right shift by 2
23487 should get the right offset. */
23490 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
23492 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23493 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
23494 md_number_to_chars (buf, newval, INSN_SIZE);
23496 put_thumb32_insn (buf, newval);
23499 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
23500 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
23501 if (value < -255 || value > 255)
23502 as_bad_where (fixP->fx_file, fixP->fx_line,
23503 _("co-processor offset out of range"));
23505 goto cp_off_common;
23507 case BFD_RELOC_ARM_THUMB_OFFSET:
23508 newval = md_chars_to_number (buf, THUMB_SIZE);
23509 /* Exactly what ranges, and where the offset is inserted depends
23510 on the type of instruction, we can establish this from the
23512 switch (newval >> 12)
23514 case 4: /* PC load. */
23515 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23516 forced to zero for these loads; md_pcrel_from has already
23517 compensated for this. */
23519 as_bad_where (fixP->fx_file, fixP->fx_line,
23520 _("invalid offset, target not word aligned (0x%08lX)"),
23521 (((unsigned long) fixP->fx_frag->fr_address
23522 + (unsigned long) fixP->fx_where) & ~3)
23523 + (unsigned long) value);
23525 if (value & ~0x3fc)
23526 as_bad_where (fixP->fx_file, fixP->fx_line,
23527 _("invalid offset, value too big (0x%08lX)"),
23530 newval |= value >> 2;
23533 case 9: /* SP load/store. */
23534 if (value & ~0x3fc)
23535 as_bad_where (fixP->fx_file, fixP->fx_line,
23536 _("invalid offset, value too big (0x%08lX)"),
23538 newval |= value >> 2;
23541 case 6: /* Word load/store. */
23543 as_bad_where (fixP->fx_file, fixP->fx_line,
23544 _("invalid offset, value too big (0x%08lX)"),
23546 newval |= value << 4; /* 6 - 2. */
23549 case 7: /* Byte load/store. */
23551 as_bad_where (fixP->fx_file, fixP->fx_line,
23552 _("invalid offset, value too big (0x%08lX)"),
23554 newval |= value << 6;
23557 case 8: /* Halfword load/store. */
23559 as_bad_where (fixP->fx_file, fixP->fx_line,
23560 _("invalid offset, value too big (0x%08lX)"),
23562 newval |= value << 5; /* 6 - 1. */
23566 as_bad_where (fixP->fx_file, fixP->fx_line,
23567 "Unable to process relocation for thumb opcode: %lx",
23568 (unsigned long) newval);
23571 md_number_to_chars (buf, newval, THUMB_SIZE);
23574 case BFD_RELOC_ARM_THUMB_ADD:
23575 /* This is a complicated relocation, since we use it for all of
23576 the following immediate relocations:
23580 9bit ADD/SUB SP word-aligned
23581 10bit ADD PC/SP word-aligned
23583 The type of instruction being processed is encoded in the
23590 newval = md_chars_to_number (buf, THUMB_SIZE);
23592 int rd = (newval >> 4) & 0xf;
23593 int rs = newval & 0xf;
23594 int subtract = !!(newval & 0x8000);
23596 /* Check for HI regs, only very restricted cases allowed:
23597 Adjusting SP, and using PC or SP to get an address. */
23598 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
23599 || (rs > 7 && rs != REG_SP && rs != REG_PC))
23600 as_bad_where (fixP->fx_file, fixP->fx_line,
23601 _("invalid Hi register with immediate"));
23603 /* If value is negative, choose the opposite instruction. */
23607 subtract = !subtract;
23609 as_bad_where (fixP->fx_file, fixP->fx_line,
23610 _("immediate value out of range"));
23615 if (value & ~0x1fc)
23616 as_bad_where (fixP->fx_file, fixP->fx_line,
23617 _("invalid immediate for stack address calculation"));
23618 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
23619 newval |= value >> 2;
23621 else if (rs == REG_PC || rs == REG_SP)
23623 /* PR gas/18541. If the addition is for a defined symbol
23624 within range of an ADR instruction then accept it. */
23627 && fixP->fx_addsy != NULL)
23631 if (! S_IS_DEFINED (fixP->fx_addsy)
23632 || S_GET_SEGMENT (fixP->fx_addsy) != seg
23633 || S_IS_WEAK (fixP->fx_addsy))
23635 as_bad_where (fixP->fx_file, fixP->fx_line,
23636 _("address calculation needs a strongly defined nearby symbol"));
23640 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
23642 /* Round up to the next 4-byte boundary. */
23647 v = S_GET_VALUE (fixP->fx_addsy) - v;
23651 as_bad_where (fixP->fx_file, fixP->fx_line,
23652 _("symbol too far away"));
23662 if (subtract || value & ~0x3fc)
23663 as_bad_where (fixP->fx_file, fixP->fx_line,
23664 _("invalid immediate for address calculation (value = 0x%08lX)"),
23665 (unsigned long) (subtract ? - value : value));
23666 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
23668 newval |= value >> 2;
23673 as_bad_where (fixP->fx_file, fixP->fx_line,
23674 _("immediate value out of range"));
23675 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
23676 newval |= (rd << 8) | value;
23681 as_bad_where (fixP->fx_file, fixP->fx_line,
23682 _("immediate value out of range"));
23683 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
23684 newval |= rd | (rs << 3) | (value << 6);
23687 md_number_to_chars (buf, newval, THUMB_SIZE);
23690 case BFD_RELOC_ARM_THUMB_IMM:
23691 newval = md_chars_to_number (buf, THUMB_SIZE);
23692 if (value < 0 || value > 255)
23693 as_bad_where (fixP->fx_file, fixP->fx_line,
23694 _("invalid immediate: %ld is out of range"),
23697 md_number_to_chars (buf, newval, THUMB_SIZE);
23700 case BFD_RELOC_ARM_THUMB_SHIFT:
23701 /* 5bit shift value (0..32). LSL cannot take 32. */
23702 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
23703 temp = newval & 0xf800;
23704 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
23705 as_bad_where (fixP->fx_file, fixP->fx_line,
23706 _("invalid shift value: %ld"), (long) value);
23707 /* Shifts of zero must be encoded as LSL. */
23709 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
23710 /* Shifts of 32 are encoded as zero. */
23711 else if (value == 32)
23713 newval |= value << 6;
23714 md_number_to_chars (buf, newval, THUMB_SIZE);
23717 case BFD_RELOC_VTABLE_INHERIT:
23718 case BFD_RELOC_VTABLE_ENTRY:
23722 case BFD_RELOC_ARM_MOVW:
23723 case BFD_RELOC_ARM_MOVT:
23724 case BFD_RELOC_ARM_THUMB_MOVW:
23725 case BFD_RELOC_ARM_THUMB_MOVT:
23726 if (fixP->fx_done || !seg->use_rela_p)
23728 /* REL format relocations are limited to a 16-bit addend. */
23729 if (!fixP->fx_done)
23731 if (value < -0x8000 || value > 0x7fff)
23732 as_bad_where (fixP->fx_file, fixP->fx_line,
23733 _("offset out of range"));
23735 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23736 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
23741 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23742 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
23744 newval = get_thumb32_insn (buf);
23745 newval &= 0xfbf08f00;
23746 newval |= (value & 0xf000) << 4;
23747 newval |= (value & 0x0800) << 15;
23748 newval |= (value & 0x0700) << 4;
23749 newval |= (value & 0x00ff);
23750 put_thumb32_insn (buf, newval);
23754 newval = md_chars_to_number (buf, 4);
23755 newval &= 0xfff0f000;
23756 newval |= value & 0x0fff;
23757 newval |= (value & 0xf000) << 4;
23758 md_number_to_chars (buf, newval, 4);
23763 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
23764 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
23765 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
23766 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
23767 gas_assert (!fixP->fx_done);
23770 bfd_boolean is_mov;
23771 bfd_vma encoded_addend = value;
23773 /* Check that addend can be encoded in instruction. */
23774 if (!seg->use_rela_p && (value < 0 || value > 255))
23775 as_bad_where (fixP->fx_file, fixP->fx_line,
23776 _("the offset 0x%08lX is not representable"),
23777 (unsigned long) encoded_addend);
23779 /* Extract the instruction. */
23780 insn = md_chars_to_number (buf, THUMB_SIZE);
23781 is_mov = (insn & 0xf800) == 0x2000;
23786 if (!seg->use_rela_p)
23787 insn |= encoded_addend;
23793 /* Extract the instruction. */
23794 /* Encoding is the following
23799 /* The following conditions must be true :
23804 rd = (insn >> 4) & 0xf;
23806 if ((insn & 0x8000) || (rd != rs) || rd > 7)
23807 as_bad_where (fixP->fx_file, fixP->fx_line,
23808 _("Unable to process relocation for thumb opcode: %lx"),
23809 (unsigned long) insn);
23811 /* Encode as ADD immediate8 thumb 1 code. */
23812 insn = 0x3000 | (rd << 8);
23814 /* Place the encoded addend into the first 8 bits of the
23816 if (!seg->use_rela_p)
23817 insn |= encoded_addend;
23820 /* Update the instruction. */
23821 md_number_to_chars (buf, insn, THUMB_SIZE);
23825 case BFD_RELOC_ARM_ALU_PC_G0_NC:
23826 case BFD_RELOC_ARM_ALU_PC_G0:
23827 case BFD_RELOC_ARM_ALU_PC_G1_NC:
23828 case BFD_RELOC_ARM_ALU_PC_G1:
23829 case BFD_RELOC_ARM_ALU_PC_G2:
23830 case BFD_RELOC_ARM_ALU_SB_G0_NC:
23831 case BFD_RELOC_ARM_ALU_SB_G0:
23832 case BFD_RELOC_ARM_ALU_SB_G1_NC:
23833 case BFD_RELOC_ARM_ALU_SB_G1:
23834 case BFD_RELOC_ARM_ALU_SB_G2:
23835 gas_assert (!fixP->fx_done);
23836 if (!seg->use_rela_p)
23839 bfd_vma encoded_addend;
23840 bfd_vma addend_abs = abs (value);
23842 /* Check that the absolute value of the addend can be
23843 expressed as an 8-bit constant plus a rotation. */
23844 encoded_addend = encode_arm_immediate (addend_abs);
23845 if (encoded_addend == (unsigned int) FAIL)
23846 as_bad_where (fixP->fx_file, fixP->fx_line,
23847 _("the offset 0x%08lX is not representable"),
23848 (unsigned long) addend_abs);
23850 /* Extract the instruction. */
23851 insn = md_chars_to_number (buf, INSN_SIZE);
23853 /* If the addend is positive, use an ADD instruction.
23854 Otherwise use a SUB. Take care not to destroy the S bit. */
23855 insn &= 0xff1fffff;
23861 /* Place the encoded addend into the first 12 bits of the
23863 insn &= 0xfffff000;
23864 insn |= encoded_addend;
23866 /* Update the instruction. */
23867 md_number_to_chars (buf, insn, INSN_SIZE);
23871 case BFD_RELOC_ARM_LDR_PC_G0:
23872 case BFD_RELOC_ARM_LDR_PC_G1:
23873 case BFD_RELOC_ARM_LDR_PC_G2:
23874 case BFD_RELOC_ARM_LDR_SB_G0:
23875 case BFD_RELOC_ARM_LDR_SB_G1:
23876 case BFD_RELOC_ARM_LDR_SB_G2:
23877 gas_assert (!fixP->fx_done);
23878 if (!seg->use_rela_p)
23881 bfd_vma addend_abs = abs (value);
23883 /* Check that the absolute value of the addend can be
23884 encoded in 12 bits. */
23885 if (addend_abs >= 0x1000)
23886 as_bad_where (fixP->fx_file, fixP->fx_line,
23887 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23888 (unsigned long) addend_abs);
23890 /* Extract the instruction. */
23891 insn = md_chars_to_number (buf, INSN_SIZE);
23893 /* If the addend is negative, clear bit 23 of the instruction.
23894 Otherwise set it. */
23896 insn &= ~(1 << 23);
23900 /* Place the absolute value of the addend into the first 12 bits
23901 of the instruction. */
23902 insn &= 0xfffff000;
23903 insn |= addend_abs;
23905 /* Update the instruction. */
23906 md_number_to_chars (buf, insn, INSN_SIZE);
23910 case BFD_RELOC_ARM_LDRS_PC_G0:
23911 case BFD_RELOC_ARM_LDRS_PC_G1:
23912 case BFD_RELOC_ARM_LDRS_PC_G2:
23913 case BFD_RELOC_ARM_LDRS_SB_G0:
23914 case BFD_RELOC_ARM_LDRS_SB_G1:
23915 case BFD_RELOC_ARM_LDRS_SB_G2:
23916 gas_assert (!fixP->fx_done);
23917 if (!seg->use_rela_p)
23920 bfd_vma addend_abs = abs (value);
23922 /* Check that the absolute value of the addend can be
23923 encoded in 8 bits. */
23924 if (addend_abs >= 0x100)
23925 as_bad_where (fixP->fx_file, fixP->fx_line,
23926 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23927 (unsigned long) addend_abs);
23929 /* Extract the instruction. */
23930 insn = md_chars_to_number (buf, INSN_SIZE);
23932 /* If the addend is negative, clear bit 23 of the instruction.
23933 Otherwise set it. */
23935 insn &= ~(1 << 23);
23939 /* Place the first four bits of the absolute value of the addend
23940 into the first 4 bits of the instruction, and the remaining
23941 four into bits 8 .. 11. */
23942 insn &= 0xfffff0f0;
23943 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
23945 /* Update the instruction. */
23946 md_number_to_chars (buf, insn, INSN_SIZE);
23950 case BFD_RELOC_ARM_LDC_PC_G0:
23951 case BFD_RELOC_ARM_LDC_PC_G1:
23952 case BFD_RELOC_ARM_LDC_PC_G2:
23953 case BFD_RELOC_ARM_LDC_SB_G0:
23954 case BFD_RELOC_ARM_LDC_SB_G1:
23955 case BFD_RELOC_ARM_LDC_SB_G2:
23956 gas_assert (!fixP->fx_done);
23957 if (!seg->use_rela_p)
23960 bfd_vma addend_abs = abs (value);
23962 /* Check that the absolute value of the addend is a multiple of
23963 four and, when divided by four, fits in 8 bits. */
23964 if (addend_abs & 0x3)
23965 as_bad_where (fixP->fx_file, fixP->fx_line,
23966 _("bad offset 0x%08lX (must be word-aligned)"),
23967 (unsigned long) addend_abs);
23969 if ((addend_abs >> 2) > 0xff)
23970 as_bad_where (fixP->fx_file, fixP->fx_line,
23971 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23972 (unsigned long) addend_abs);
23974 /* Extract the instruction. */
23975 insn = md_chars_to_number (buf, INSN_SIZE);
23977 /* If the addend is negative, clear bit 23 of the instruction.
23978 Otherwise set it. */
23980 insn &= ~(1 << 23);
23984 /* Place the addend (divided by four) into the first eight
23985 bits of the instruction. */
23986 insn &= 0xfffffff0;
23987 insn |= addend_abs >> 2;
23989 /* Update the instruction. */
23990 md_number_to_chars (buf, insn, INSN_SIZE);
23994 case BFD_RELOC_ARM_V4BX:
23995 /* This will need to go in the object file. */
23999 case BFD_RELOC_UNUSED:
24001 as_bad_where (fixP->fx_file, fixP->fx_line,
24002 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
24006 /* Translate internal representation of relocation info to BFD target
24010 tc_gen_reloc (asection *section, fixS *fixp)
24013 bfd_reloc_code_real_type code;
24015 reloc = (arelent *) xmalloc (sizeof (arelent));
24017 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
24018 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
24019 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
24021 if (fixp->fx_pcrel)
24023 if (section->use_rela_p)
24024 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
24026 fixp->fx_offset = reloc->address;
24028 reloc->addend = fixp->fx_offset;
24030 switch (fixp->fx_r_type)
24033 if (fixp->fx_pcrel)
24035 code = BFD_RELOC_8_PCREL;
24040 if (fixp->fx_pcrel)
24042 code = BFD_RELOC_16_PCREL;
24047 if (fixp->fx_pcrel)
24049 code = BFD_RELOC_32_PCREL;
24053 case BFD_RELOC_ARM_MOVW:
24054 if (fixp->fx_pcrel)
24056 code = BFD_RELOC_ARM_MOVW_PCREL;
24060 case BFD_RELOC_ARM_MOVT:
24061 if (fixp->fx_pcrel)
24063 code = BFD_RELOC_ARM_MOVT_PCREL;
24067 case BFD_RELOC_ARM_THUMB_MOVW:
24068 if (fixp->fx_pcrel)
24070 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
24074 case BFD_RELOC_ARM_THUMB_MOVT:
24075 if (fixp->fx_pcrel)
24077 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
24081 case BFD_RELOC_NONE:
24082 case BFD_RELOC_ARM_PCREL_BRANCH:
24083 case BFD_RELOC_ARM_PCREL_BLX:
24084 case BFD_RELOC_RVA:
24085 case BFD_RELOC_THUMB_PCREL_BRANCH7:
24086 case BFD_RELOC_THUMB_PCREL_BRANCH9:
24087 case BFD_RELOC_THUMB_PCREL_BRANCH12:
24088 case BFD_RELOC_THUMB_PCREL_BRANCH20:
24089 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24090 case BFD_RELOC_THUMB_PCREL_BRANCH25:
24091 case BFD_RELOC_VTABLE_ENTRY:
24092 case BFD_RELOC_VTABLE_INHERIT:
24094 case BFD_RELOC_32_SECREL:
24096 code = fixp->fx_r_type;
24099 case BFD_RELOC_THUMB_PCREL_BLX:
24101 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
24102 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
24105 code = BFD_RELOC_THUMB_PCREL_BLX;
24108 case BFD_RELOC_ARM_LITERAL:
24109 case BFD_RELOC_ARM_HWLITERAL:
24110 /* If this is called then the a literal has
24111 been referenced across a section boundary. */
24112 as_bad_where (fixp->fx_file, fixp->fx_line,
24113 _("literal referenced across section boundary"));
24117 case BFD_RELOC_ARM_TLS_CALL:
24118 case BFD_RELOC_ARM_THM_TLS_CALL:
24119 case BFD_RELOC_ARM_TLS_DESCSEQ:
24120 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
24121 case BFD_RELOC_ARM_GOT32:
24122 case BFD_RELOC_ARM_GOTOFF:
24123 case BFD_RELOC_ARM_GOT_PREL:
24124 case BFD_RELOC_ARM_PLT32:
24125 case BFD_RELOC_ARM_TARGET1:
24126 case BFD_RELOC_ARM_ROSEGREL32:
24127 case BFD_RELOC_ARM_SBREL32:
24128 case BFD_RELOC_ARM_PREL31:
24129 case BFD_RELOC_ARM_TARGET2:
24130 case BFD_RELOC_ARM_TLS_LDO32:
24131 case BFD_RELOC_ARM_PCREL_CALL:
24132 case BFD_RELOC_ARM_PCREL_JUMP:
24133 case BFD_RELOC_ARM_ALU_PC_G0_NC:
24134 case BFD_RELOC_ARM_ALU_PC_G0:
24135 case BFD_RELOC_ARM_ALU_PC_G1_NC:
24136 case BFD_RELOC_ARM_ALU_PC_G1:
24137 case BFD_RELOC_ARM_ALU_PC_G2:
24138 case BFD_RELOC_ARM_LDR_PC_G0:
24139 case BFD_RELOC_ARM_LDR_PC_G1:
24140 case BFD_RELOC_ARM_LDR_PC_G2:
24141 case BFD_RELOC_ARM_LDRS_PC_G0:
24142 case BFD_RELOC_ARM_LDRS_PC_G1:
24143 case BFD_RELOC_ARM_LDRS_PC_G2:
24144 case BFD_RELOC_ARM_LDC_PC_G0:
24145 case BFD_RELOC_ARM_LDC_PC_G1:
24146 case BFD_RELOC_ARM_LDC_PC_G2:
24147 case BFD_RELOC_ARM_ALU_SB_G0_NC:
24148 case BFD_RELOC_ARM_ALU_SB_G0:
24149 case BFD_RELOC_ARM_ALU_SB_G1_NC:
24150 case BFD_RELOC_ARM_ALU_SB_G1:
24151 case BFD_RELOC_ARM_ALU_SB_G2:
24152 case BFD_RELOC_ARM_LDR_SB_G0:
24153 case BFD_RELOC_ARM_LDR_SB_G1:
24154 case BFD_RELOC_ARM_LDR_SB_G2:
24155 case BFD_RELOC_ARM_LDRS_SB_G0:
24156 case BFD_RELOC_ARM_LDRS_SB_G1:
24157 case BFD_RELOC_ARM_LDRS_SB_G2:
24158 case BFD_RELOC_ARM_LDC_SB_G0:
24159 case BFD_RELOC_ARM_LDC_SB_G1:
24160 case BFD_RELOC_ARM_LDC_SB_G2:
24161 case BFD_RELOC_ARM_V4BX:
24162 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
24163 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
24164 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
24165 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
24166 code = fixp->fx_r_type;
24169 case BFD_RELOC_ARM_TLS_GOTDESC:
24170 case BFD_RELOC_ARM_TLS_GD32:
24171 case BFD_RELOC_ARM_TLS_LE32:
24172 case BFD_RELOC_ARM_TLS_IE32:
24173 case BFD_RELOC_ARM_TLS_LDM32:
24174 /* BFD will include the symbol's address in the addend.
24175 But we don't want that, so subtract it out again here. */
24176 if (!S_IS_COMMON (fixp->fx_addsy))
24177 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
24178 code = fixp->fx_r_type;
24182 case BFD_RELOC_ARM_IMMEDIATE:
24183 as_bad_where (fixp->fx_file, fixp->fx_line,
24184 _("internal relocation (type: IMMEDIATE) not fixed up"));
24187 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
24188 as_bad_where (fixp->fx_file, fixp->fx_line,
24189 _("ADRL used for a symbol not defined in the same file"));
24192 case BFD_RELOC_ARM_OFFSET_IMM:
24193 if (section->use_rela_p)
24195 code = fixp->fx_r_type;
24199 if (fixp->fx_addsy != NULL
24200 && !S_IS_DEFINED (fixp->fx_addsy)
24201 && S_IS_LOCAL (fixp->fx_addsy))
24203 as_bad_where (fixp->fx_file, fixp->fx_line,
24204 _("undefined local label `%s'"),
24205 S_GET_NAME (fixp->fx_addsy));
24209 as_bad_where (fixp->fx_file, fixp->fx_line,
24210 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24217 switch (fixp->fx_r_type)
24219 case BFD_RELOC_NONE: type = "NONE"; break;
24220 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
24221 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
24222 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
24223 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
24224 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
24225 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
24226 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
24227 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
24228 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
24229 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
24230 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
24231 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
24232 default: type = _("<unknown>"); break;
24234 as_bad_where (fixp->fx_file, fixp->fx_line,
24235 _("cannot represent %s relocation in this object file format"),
24242 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
24244 && fixp->fx_addsy == GOT_symbol)
24246 code = BFD_RELOC_ARM_GOTPC;
24247 reloc->addend = fixp->fx_offset = reloc->address;
24251 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
24253 if (reloc->howto == NULL)
24255 as_bad_where (fixp->fx_file, fixp->fx_line,
24256 _("cannot represent %s relocation in this object file format"),
24257 bfd_get_reloc_code_name (code));
24261 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24262 vtable entry to be used in the relocation's section offset. */
24263 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
24264 reloc->address = fixp->fx_offset;
24269 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24272 cons_fix_new_arm (fragS * frag,
24276 bfd_reloc_code_real_type reloc)
24281 FIXME: @@ Should look at CPU word size. */
24285 reloc = BFD_RELOC_8;
24288 reloc = BFD_RELOC_16;
24292 reloc = BFD_RELOC_32;
24295 reloc = BFD_RELOC_64;
24300 if (exp->X_op == O_secrel)
24302 exp->X_op = O_symbol;
24303 reloc = BFD_RELOC_32_SECREL;
24307 fix_new_exp (frag, where, size, exp, pcrel, reloc);
24310 #if defined (OBJ_COFF)
24312 arm_validate_fix (fixS * fixP)
24314 /* If the destination of the branch is a defined symbol which does not have
24315 the THUMB_FUNC attribute, then we must be calling a function which has
24316 the (interfacearm) attribute. We look for the Thumb entry point to that
24317 function and change the branch to refer to that function instead. */
24318 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
24319 && fixP->fx_addsy != NULL
24320 && S_IS_DEFINED (fixP->fx_addsy)
24321 && ! THUMB_IS_FUNC (fixP->fx_addsy))
24323 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
24330 arm_force_relocation (struct fix * fixp)
24332 #if defined (OBJ_COFF) && defined (TE_PE)
24333 if (fixp->fx_r_type == BFD_RELOC_RVA)
24337 /* In case we have a call or a branch to a function in ARM ISA mode from
24338 a thumb function or vice-versa force the relocation. These relocations
24339 are cleared off for some cores that might have blx and simple transformations
24343 switch (fixp->fx_r_type)
24345 case BFD_RELOC_ARM_PCREL_JUMP:
24346 case BFD_RELOC_ARM_PCREL_CALL:
24347 case BFD_RELOC_THUMB_PCREL_BLX:
24348 if (THUMB_IS_FUNC (fixp->fx_addsy))
24352 case BFD_RELOC_ARM_PCREL_BLX:
24353 case BFD_RELOC_THUMB_PCREL_BRANCH25:
24354 case BFD_RELOC_THUMB_PCREL_BRANCH20:
24355 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24356 if (ARM_IS_FUNC (fixp->fx_addsy))
24365 /* Resolve these relocations even if the symbol is extern or weak.
24366 Technically this is probably wrong due to symbol preemption.
24367 In practice these relocations do not have enough range to be useful
24368 at dynamic link time, and some code (e.g. in the Linux kernel)
24369 expects these references to be resolved. */
24370 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
24371 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
24372 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
24373 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
24374 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
24375 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
24376 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
24377 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
24378 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
24379 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
24380 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
24381 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
24382 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
24383 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
24386 /* Always leave these relocations for the linker. */
24387 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
24388 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
24389 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
24392 /* Always generate relocations against function symbols. */
24393 if (fixp->fx_r_type == BFD_RELOC_32
24395 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
24398 return generic_force_reloc (fixp);
24401 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24402 /* Relocations against function names must be left unadjusted,
24403 so that the linker can use this information to generate interworking
24404 stubs. The MIPS version of this function
24405 also prevents relocations that are mips-16 specific, but I do not
24406 know why it does this.
24409 There is one other problem that ought to be addressed here, but
24410 which currently is not: Taking the address of a label (rather
24411 than a function) and then later jumping to that address. Such
24412 addresses also ought to have their bottom bit set (assuming that
24413 they reside in Thumb code), but at the moment they will not. */
24416 arm_fix_adjustable (fixS * fixP)
24418 if (fixP->fx_addsy == NULL)
24421 /* Preserve relocations against symbols with function type. */
24422 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
24425 if (THUMB_IS_FUNC (fixP->fx_addsy)
24426 && fixP->fx_subsy == NULL)
24429 /* We need the symbol name for the VTABLE entries. */
24430 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
24431 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
24434 /* Don't allow symbols to be discarded on GOT related relocs. */
24435 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
24436 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
24437 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
24438 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
24439 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
24440 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
24441 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
24442 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
24443 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
24444 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
24445 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
24446 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
24447 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
24448 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
24451 /* Similarly for group relocations. */
24452 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
24453 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
24454 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
24457 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24458 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
24459 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
24460 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
24461 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
24462 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
24463 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
24464 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
24465 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
24468 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24469 offsets, so keep these symbols. */
24470 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24471 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
24476 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24480 elf32_arm_target_format (void)
24483 return (target_big_endian
24484 ? "elf32-bigarm-symbian"
24485 : "elf32-littlearm-symbian");
24486 #elif defined (TE_VXWORKS)
24487 return (target_big_endian
24488 ? "elf32-bigarm-vxworks"
24489 : "elf32-littlearm-vxworks");
24490 #elif defined (TE_NACL)
24491 return (target_big_endian
24492 ? "elf32-bigarm-nacl"
24493 : "elf32-littlearm-nacl");
24495 if (target_big_endian)
24496 return "elf32-bigarm";
24498 return "elf32-littlearm";
24503 armelf_frob_symbol (symbolS * symp,
24506 elf_frob_symbol (symp, puntp);
24510 /* MD interface: Finalization. */
24515 literal_pool * pool;
24517 /* Ensure that all the IT blocks are properly closed. */
24518 check_it_blocks_finished ();
24520 for (pool = list_of_pools; pool; pool = pool->next)
24522 /* Put it at the end of the relevant section. */
24523 subseg_set (pool->section, pool->sub_section);
24525 arm_elf_change_section ();
24532 /* Remove any excess mapping symbols generated for alignment frags in
24533 SEC. We may have created a mapping symbol before a zero byte
24534 alignment; remove it if there's a mapping symbol after the
24537 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
24538 void *dummy ATTRIBUTE_UNUSED)
24540 segment_info_type *seginfo = seg_info (sec);
24543 if (seginfo == NULL || seginfo->frchainP == NULL)
24546 for (fragp = seginfo->frchainP->frch_root;
24548 fragp = fragp->fr_next)
24550 symbolS *sym = fragp->tc_frag_data.last_map;
24551 fragS *next = fragp->fr_next;
24553 /* Variable-sized frags have been converted to fixed size by
24554 this point. But if this was variable-sized to start with,
24555 there will be a fixed-size frag after it. So don't handle
24557 if (sym == NULL || next == NULL)
24560 if (S_GET_VALUE (sym) < next->fr_address)
24561 /* Not at the end of this frag. */
24563 know (S_GET_VALUE (sym) == next->fr_address);
24567 if (next->tc_frag_data.first_map != NULL)
24569 /* Next frag starts with a mapping symbol. Discard this
24571 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
24575 if (next->fr_next == NULL)
24577 /* This mapping symbol is at the end of the section. Discard
24579 know (next->fr_fix == 0 && next->fr_var == 0);
24580 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
24584 /* As long as we have empty frags without any mapping symbols,
24586 /* If the next frag is non-empty and does not start with a
24587 mapping symbol, then this mapping symbol is required. */
24588 if (next->fr_address != next->fr_next->fr_address)
24591 next = next->fr_next;
24593 while (next != NULL);
24598 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24602 arm_adjust_symtab (void)
24607 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
24609 if (ARM_IS_THUMB (sym))
24611 if (THUMB_IS_FUNC (sym))
24613 /* Mark the symbol as a Thumb function. */
24614 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
24615 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
24616 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
24618 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
24619 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
24621 as_bad (_("%s: unexpected function type: %d"),
24622 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
24624 else switch (S_GET_STORAGE_CLASS (sym))
24627 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
24630 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
24633 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
24641 if (ARM_IS_INTERWORK (sym))
24642 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
24649 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
24651 if (ARM_IS_THUMB (sym))
24653 elf_symbol_type * elf_sym;
24655 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
24656 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
24658 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
24659 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
24661 /* If it's a .thumb_func, declare it as so,
24662 otherwise tag label as .code 16. */
24663 if (THUMB_IS_FUNC (sym))
24664 elf_sym->internal_elf_sym.st_target_internal
24665 = ST_BRANCH_TO_THUMB;
24666 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24667 elf_sym->internal_elf_sym.st_info =
24668 ELF_ST_INFO (bind, STT_ARM_16BIT);
24673 /* Remove any overlapping mapping symbols generated by alignment frags. */
24674 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
24675 /* Now do generic ELF adjustments. */
24676 elf_adjust_symtab ();
24680 /* MD interface: Initialization. */
24683 set_constant_flonums (void)
24687 for (i = 0; i < NUM_FLOAT_VALS; i++)
24688 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
24692 /* Auto-select Thumb mode if it's the only available instruction set for the
24693 given architecture. */
24696 autoselect_thumb_from_cpu_variant (void)
24698 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
24699 opcode_select (16);
24708 if ( (arm_ops_hsh = hash_new ()) == NULL
24709 || (arm_cond_hsh = hash_new ()) == NULL
24710 || (arm_shift_hsh = hash_new ()) == NULL
24711 || (arm_psr_hsh = hash_new ()) == NULL
24712 || (arm_v7m_psr_hsh = hash_new ()) == NULL
24713 || (arm_reg_hsh = hash_new ()) == NULL
24714 || (arm_reloc_hsh = hash_new ()) == NULL
24715 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
24716 as_fatal (_("virtual memory exhausted"));
24718 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
24719 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
24720 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
24721 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
24722 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
24723 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
24724 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
24725 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
24726 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
24727 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
24728 (void *) (v7m_psrs + i));
24729 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
24730 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
24732 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
24734 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
24735 (void *) (barrier_opt_names + i));
24737 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
24739 struct reloc_entry * entry = reloc_names + i;
24741 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
24742 /* This makes encode_branch() use the EABI versions of this relocation. */
24743 entry->reloc = BFD_RELOC_UNUSED;
24745 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
24749 set_constant_flonums ();
24751 /* Set the cpu variant based on the command-line options. We prefer
24752 -mcpu= over -march= if both are set (as for GCC); and we prefer
24753 -mfpu= over any other way of setting the floating point unit.
24754 Use of legacy options with new options are faulted. */
24757 if (mcpu_cpu_opt || march_cpu_opt)
24758 as_bad (_("use of old and new-style options to set CPU type"));
24760 mcpu_cpu_opt = legacy_cpu;
24762 else if (!mcpu_cpu_opt)
24763 mcpu_cpu_opt = march_cpu_opt;
24768 as_bad (_("use of old and new-style options to set FPU type"));
24770 mfpu_opt = legacy_fpu;
24772 else if (!mfpu_opt)
24774 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24775 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24776 /* Some environments specify a default FPU. If they don't, infer it
24777 from the processor. */
24779 mfpu_opt = mcpu_fpu_opt;
24781 mfpu_opt = march_fpu_opt;
24783 mfpu_opt = &fpu_default;
24789 if (mcpu_cpu_opt != NULL)
24790 mfpu_opt = &fpu_default;
24791 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
24792 mfpu_opt = &fpu_arch_vfp_v2;
24794 mfpu_opt = &fpu_arch_fpa;
24800 mcpu_cpu_opt = &cpu_default;
24801 selected_cpu = cpu_default;
24803 else if (no_cpu_selected ())
24804 selected_cpu = cpu_default;
24807 selected_cpu = *mcpu_cpu_opt;
24809 mcpu_cpu_opt = &arm_arch_any;
24812 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24814 autoselect_thumb_from_cpu_variant ();
24816 arm_arch_used = thumb_arch_used = arm_arch_none;
24818 #if defined OBJ_COFF || defined OBJ_ELF
24820 unsigned int flags = 0;
24822 #if defined OBJ_ELF
24823 flags = meabi_flags;
24825 switch (meabi_flags)
24827 case EF_ARM_EABI_UNKNOWN:
24829 /* Set the flags in the private structure. */
24830 if (uses_apcs_26) flags |= F_APCS26;
24831 if (support_interwork) flags |= F_INTERWORK;
24832 if (uses_apcs_float) flags |= F_APCS_FLOAT;
24833 if (pic_code) flags |= F_PIC;
24834 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
24835 flags |= F_SOFT_FLOAT;
24837 switch (mfloat_abi_opt)
24839 case ARM_FLOAT_ABI_SOFT:
24840 case ARM_FLOAT_ABI_SOFTFP:
24841 flags |= F_SOFT_FLOAT;
24844 case ARM_FLOAT_ABI_HARD:
24845 if (flags & F_SOFT_FLOAT)
24846 as_bad (_("hard-float conflicts with specified fpu"));
24850 /* Using pure-endian doubles (even if soft-float). */
24851 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
24852 flags |= F_VFP_FLOAT;
24854 #if defined OBJ_ELF
24855 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
24856 flags |= EF_ARM_MAVERICK_FLOAT;
24859 case EF_ARM_EABI_VER4:
24860 case EF_ARM_EABI_VER5:
24861 /* No additional flags to set. */
24868 bfd_set_private_flags (stdoutput, flags);
24870 /* We have run out flags in the COFF header to encode the
24871 status of ATPCS support, so instead we create a dummy,
24872 empty, debug section called .arm.atpcs. */
24877 sec = bfd_make_section (stdoutput, ".arm.atpcs");
24881 bfd_set_section_flags
24882 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
24883 bfd_set_section_size (stdoutput, sec, 0);
24884 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
24890 /* Record the CPU type as well. */
24891 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
24892 mach = bfd_mach_arm_iWMMXt2;
24893 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
24894 mach = bfd_mach_arm_iWMMXt;
24895 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
24896 mach = bfd_mach_arm_XScale;
24897 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
24898 mach = bfd_mach_arm_ep9312;
24899 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
24900 mach = bfd_mach_arm_5TE;
24901 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
24903 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
24904 mach = bfd_mach_arm_5T;
24906 mach = bfd_mach_arm_5;
24908 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
24910 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
24911 mach = bfd_mach_arm_4T;
24913 mach = bfd_mach_arm_4;
24915 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
24916 mach = bfd_mach_arm_3M;
24917 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
24918 mach = bfd_mach_arm_3;
24919 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
24920 mach = bfd_mach_arm_2a;
24921 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
24922 mach = bfd_mach_arm_2;
24924 mach = bfd_mach_arm_unknown;
24926 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
24929 /* Command line processing. */
24932 Invocation line includes a switch not recognized by the base assembler.
24933 See if it's a processor-specific option.
24935 This routine is somewhat complicated by the need for backwards
24936 compatibility (since older releases of gcc can't be changed).
24937 The new options try to make the interface as compatible as
24940 New options (supported) are:
24942 -mcpu=<cpu name> Assemble for selected processor
24943 -march=<architecture name> Assemble for selected architecture
24944 -mfpu=<fpu architecture> Assemble for selected FPU.
24945 -EB/-mbig-endian Big-endian
24946 -EL/-mlittle-endian Little-endian
24947 -k Generate PIC code
24948 -mthumb Start in Thumb mode
24949 -mthumb-interwork Code supports ARM/Thumb interworking
24951 -m[no-]warn-deprecated Warn about deprecated features
24952 -m[no-]warn-syms Warn when symbols match instructions
24954 For now we will also provide support for:
24956 -mapcs-32 32-bit Program counter
24957 -mapcs-26 26-bit Program counter
24958 -macps-float Floats passed in FP registers
24959 -mapcs-reentrant Reentrant code
24961 (sometime these will probably be replaced with -mapcs=<list of options>
24962 and -matpcs=<list of options>)
24964 The remaining options are only supported for back-wards compatibility.
24965 Cpu variants, the arm part is optional:
24966 -m[arm]1 Currently not supported.
24967 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24968 -m[arm]3 Arm 3 processor
24969 -m[arm]6[xx], Arm 6 processors
24970 -m[arm]7[xx][t][[d]m] Arm 7 processors
24971 -m[arm]8[10] Arm 8 processors
24972 -m[arm]9[20][tdmi] Arm 9 processors
24973 -mstrongarm[110[0]] StrongARM processors
24974 -mxscale XScale processors
24975 -m[arm]v[2345[t[e]]] Arm architectures
24976 -mall All (except the ARM1)
24978 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24979 -mfpe-old (No float load/store multiples)
24980 -mvfpxd VFP Single precision
24982 -mno-fpu Disable all floating point instructions
24984 The following CPU names are recognized:
24985 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24986 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24987 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24988 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24989 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24990 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24991 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24995 const char * md_shortopts = "m:k";
24997 #ifdef ARM_BI_ENDIAN
24998 #define OPTION_EB (OPTION_MD_BASE + 0)
24999 #define OPTION_EL (OPTION_MD_BASE + 1)
25001 #if TARGET_BYTES_BIG_ENDIAN
25002 #define OPTION_EB (OPTION_MD_BASE + 0)
25004 #define OPTION_EL (OPTION_MD_BASE + 1)
25007 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25009 struct option md_longopts[] =
25012 {"EB", no_argument, NULL, OPTION_EB},
25015 {"EL", no_argument, NULL, OPTION_EL},
25017 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
25018 {NULL, no_argument, NULL, 0}
25022 size_t md_longopts_size = sizeof (md_longopts);
25024 struct arm_option_table
25026 const char *option; /* Option name to match. */
25027 const char *help; /* Help information. */
25028 int *var; /* Variable to change. */
25029 int value; /* What to change it to. */
25030 const char *deprecated; /* If non-null, print this message. */
25033 struct arm_option_table arm_opts[] =
25035 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
25036 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
25037 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25038 &support_interwork, 1, NULL},
25039 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
25040 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
25041 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
25043 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
25044 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
25045 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
25046 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
25049 /* These are recognized by the assembler, but have no affect on code. */
25050 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
25051 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
25053 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
25054 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25055 &warn_on_deprecated, 0, NULL},
25056 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
25057 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
25058 {NULL, NULL, NULL, 0, NULL}
25061 struct arm_legacy_option_table
25063 const char *option; /* Option name to match. */
25064 const arm_feature_set **var; /* Variable to change. */
25065 const arm_feature_set value; /* What to change it to. */
25066 const char *deprecated; /* If non-null, print this message. */
25069 const struct arm_legacy_option_table arm_legacy_opts[] =
25071 /* DON'T add any new processors to this list -- we want the whole list
25072 to go away... Add them to the processors table instead. */
25073 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
25074 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
25075 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
25076 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
25077 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
25078 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
25079 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
25080 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
25081 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
25082 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
25083 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
25084 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
25085 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
25086 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
25087 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
25088 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
25089 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
25090 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
25091 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
25092 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
25093 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
25094 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
25095 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
25096 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
25097 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
25098 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
25099 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
25100 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
25101 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
25102 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
25103 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
25104 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
25105 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
25106 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
25107 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
25108 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
25109 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
25110 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
25111 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
25112 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
25113 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
25114 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
25115 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
25116 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
25117 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
25118 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
25119 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25120 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25121 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25122 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25123 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
25124 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
25125 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
25126 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
25127 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
25128 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
25129 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
25130 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
25131 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
25132 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
25133 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
25134 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
25135 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
25136 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
25137 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
25138 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
25139 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
25140 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
25141 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
25142 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
25143 N_("use -mcpu=strongarm110")},
25144 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
25145 N_("use -mcpu=strongarm1100")},
25146 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
25147 N_("use -mcpu=strongarm1110")},
25148 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
25149 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
25150 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
25152 /* Architecture variants -- don't add any more to this list either. */
25153 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
25154 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
25155 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
25156 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
25157 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
25158 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
25159 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
25160 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
25161 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
25162 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
25163 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
25164 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
25165 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
25166 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
25167 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
25168 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
25169 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
25170 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
25172 /* Floating point variants -- don't add any more to this list either. */
25173 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
25174 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
25175 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
25176 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
25177 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25179 {NULL, NULL, ARM_ARCH_NONE, NULL}
25182 struct arm_cpu_option_table
25186 const arm_feature_set value;
25187 /* For some CPUs we assume an FPU unless the user explicitly sets
25189 const arm_feature_set default_fpu;
25190 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25192 const char *canonical_name;
25195 /* This list should, at a minimum, contain all the cpu names
25196 recognized by GCC. */
25197 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25198 static const struct arm_cpu_option_table arm_cpus[] =
25200 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
25201 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
25202 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
25203 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
25204 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
25205 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25206 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25207 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25208 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25209 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25210 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25211 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
25212 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25213 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
25214 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25215 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
25216 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25217 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25218 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25219 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25220 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25221 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25222 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25223 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25224 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25225 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25226 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25227 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
25228 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25229 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25230 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25231 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25232 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25233 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25234 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25235 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25236 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25237 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25238 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25239 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
25240 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25241 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25242 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25243 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
25244 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25245 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
25246 /* For V5 or later processors we default to using VFP; but the user
25247 should really set the FPU type explicitly. */
25248 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
25249 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25250 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
25251 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
25252 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
25253 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
25254 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
25255 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25256 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
25257 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
25258 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25259 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25260 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
25261 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
25262 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25263 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
25264 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
25265 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25266 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25267 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
25269 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
25270 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25271 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25272 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25273 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25274 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
25275 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
25276 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
25277 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
25279 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
25280 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
25281 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
25282 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
25283 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
25284 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ, FPU_NONE, NULL),
25285 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ, FPU_ARCH_VFP_V2, NULL),
25286 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
25287 FPU_NONE, "Cortex-A5"),
25288 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
25290 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
25291 ARM_FEATURE_COPROC (FPU_VFP_V3
25292 | FPU_NEON_EXT_V1),
25294 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
25295 ARM_FEATURE_COPROC (FPU_VFP_V3
25296 | FPU_NEON_EXT_V1),
25298 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
25300 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
25302 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
25304 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25306 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25308 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25310 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25312 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25314 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
25315 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
25317 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
25318 FPU_NONE, "Cortex-R5"),
25319 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
25320 FPU_ARCH_VFP_V3D16,
25322 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV,
25323 FPU_ARCH_VFP_V3D16,
25325 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M7"),
25326 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
25327 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
25328 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
25329 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
25330 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
25331 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25334 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25338 /* ??? XSCALE is really an architecture. */
25339 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
25340 /* ??? iwmmxt is not a processor. */
25341 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
25342 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
25343 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
25345 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
25346 FPU_ARCH_MAVERICK, "ARM920T"),
25347 /* Marvell processors. */
25348 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP
25350 ARM_EXT2_V6T2_V8M),
25351 FPU_ARCH_VFP_V3D16, NULL),
25352 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP
25354 ARM_EXT2_V6T2_V8M),
25355 FPU_ARCH_NEON_VFP_V4, NULL),
25356 /* APM X-Gene family. */
25357 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25359 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25362 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
25366 struct arm_arch_option_table
25370 const arm_feature_set value;
25371 const arm_feature_set default_fpu;
25374 /* This list should, at a minimum, contain all the architecture names
25375 recognized by GCC. */
25376 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25377 static const struct arm_arch_option_table arm_archs[] =
25379 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
25380 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
25381 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
25382 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
25383 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
25384 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
25385 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
25386 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
25387 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
25388 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
25389 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
25390 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
25391 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
25392 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
25393 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
25394 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
25395 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
25396 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
25397 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
25398 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
25399 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
25400 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25401 kept to preserve existing behaviour. */
25402 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP),
25403 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP),
25404 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
25405 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
25406 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
25407 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25408 kept to preserve existing behaviour. */
25409 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP),
25410 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP),
25411 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
25412 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
25413 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
25414 /* The official spelling of the ARMv7 profile variants is the dashed form.
25415 Accept the non-dashed form for compatibility with old toolchains. */
25416 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
25417 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP),
25418 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
25419 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
25420 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
25421 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
25422 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
25423 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
25424 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
25425 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP),
25426 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
25427 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP),
25428 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP),
25429 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
25430 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
25431 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
25432 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
25434 #undef ARM_ARCH_OPT
25436 /* ISA extensions in the co-processor and main instruction set space. */
25437 struct arm_option_extension_value_table
25441 const arm_feature_set merge_value;
25442 const arm_feature_set clear_value;
25443 const arm_feature_set allowed_archs;
25446 /* The following table must be in alphabetical order with a NULL last entry.
25448 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
25449 static const struct arm_option_extension_value_table arm_extensions[] =
25451 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
25452 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25453 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
25454 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
25455 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25456 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
25457 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25458 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
25459 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
25461 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
25462 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
25463 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)),
25464 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
25465 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ANY),
25466 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
25467 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ANY),
25468 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
25469 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ANY),
25470 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
25471 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
25472 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)),
25473 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
25474 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
25475 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
25476 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
25477 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
25478 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25479 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
25480 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
25481 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25482 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
25483 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
25484 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V7A)),
25485 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
25486 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
25487 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
25488 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
25490 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
25491 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
25492 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
25493 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ANY),
25494 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE }
25498 /* ISA floating-point and Advanced SIMD extensions. */
25499 struct arm_option_fpu_value_table
25502 const arm_feature_set value;
25505 /* This list should, at a minimum, contain all the fpu names
25506 recognized by GCC. */
25507 static const struct arm_option_fpu_value_table arm_fpus[] =
25509 {"softfpa", FPU_NONE},
25510 {"fpe", FPU_ARCH_FPE},
25511 {"fpe2", FPU_ARCH_FPE},
25512 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
25513 {"fpa", FPU_ARCH_FPA},
25514 {"fpa10", FPU_ARCH_FPA},
25515 {"fpa11", FPU_ARCH_FPA},
25516 {"arm7500fe", FPU_ARCH_FPA},
25517 {"softvfp", FPU_ARCH_VFP},
25518 {"softvfp+vfp", FPU_ARCH_VFP_V2},
25519 {"vfp", FPU_ARCH_VFP_V2},
25520 {"vfp9", FPU_ARCH_VFP_V2},
25521 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
25522 {"vfp10", FPU_ARCH_VFP_V2},
25523 {"vfp10-r0", FPU_ARCH_VFP_V1},
25524 {"vfpxd", FPU_ARCH_VFP_V1xD},
25525 {"vfpv2", FPU_ARCH_VFP_V2},
25526 {"vfpv3", FPU_ARCH_VFP_V3},
25527 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
25528 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
25529 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
25530 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
25531 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
25532 {"arm1020t", FPU_ARCH_VFP_V1},
25533 {"arm1020e", FPU_ARCH_VFP_V2},
25534 {"arm1136jfs", FPU_ARCH_VFP_V2},
25535 {"arm1136jf-s", FPU_ARCH_VFP_V2},
25536 {"maverick", FPU_ARCH_MAVERICK},
25537 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
25538 {"neon-fp16", FPU_ARCH_NEON_FP16},
25539 {"vfpv4", FPU_ARCH_VFP_V4},
25540 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
25541 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
25542 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
25543 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
25544 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
25545 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
25546 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
25547 {"crypto-neon-fp-armv8",
25548 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
25549 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
25550 {"crypto-neon-fp-armv8.1",
25551 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
25552 {NULL, ARM_ARCH_NONE}
25555 struct arm_option_value_table
25561 static const struct arm_option_value_table arm_float_abis[] =
25563 {"hard", ARM_FLOAT_ABI_HARD},
25564 {"softfp", ARM_FLOAT_ABI_SOFTFP},
25565 {"soft", ARM_FLOAT_ABI_SOFT},
25570 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25571 static const struct arm_option_value_table arm_eabis[] =
25573 {"gnu", EF_ARM_EABI_UNKNOWN},
25574 {"4", EF_ARM_EABI_VER4},
25575 {"5", EF_ARM_EABI_VER5},
25580 struct arm_long_option_table
25582 const char * option; /* Substring to match. */
25583 const char * help; /* Help information. */
25584 int (* func) (const char * subopt); /* Function to decode sub-option. */
25585 const char * deprecated; /* If non-null, print this message. */
25589 arm_parse_extension (const char *str, const arm_feature_set **opt_p)
25591 arm_feature_set *ext_set = (arm_feature_set *)
25592 xmalloc (sizeof (arm_feature_set));
25594 /* We insist on extensions being specified in alphabetical order, and with
25595 extensions being added before being removed. We achieve this by having
25596 the global ARM_EXTENSIONS table in alphabetical order, and using the
25597 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25598 or removing it (0) and only allowing it to change in the order
25600 const struct arm_option_extension_value_table * opt = NULL;
25601 int adding_value = -1;
25603 /* Copy the feature set, so that we can modify it. */
25604 *ext_set = **opt_p;
25607 while (str != NULL && *str != 0)
25614 as_bad (_("invalid architectural extension"));
25619 ext = strchr (str, '+');
25624 len = strlen (str);
25626 if (len >= 2 && strncmp (str, "no", 2) == 0)
25628 if (adding_value != 0)
25631 opt = arm_extensions;
25639 if (adding_value == -1)
25642 opt = arm_extensions;
25644 else if (adding_value != 1)
25646 as_bad (_("must specify extensions to add before specifying "
25647 "those to remove"));
25654 as_bad (_("missing architectural extension"));
25658 gas_assert (adding_value != -1);
25659 gas_assert (opt != NULL);
25661 /* Scan over the options table trying to find an exact match. */
25662 for (; opt->name != NULL; opt++)
25663 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25665 /* Check we can apply the extension to this architecture. */
25666 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
25668 as_bad (_("extension does not apply to the base architecture"));
25672 /* Add or remove the extension. */
25674 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
25676 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
25681 if (opt->name == NULL)
25683 /* Did we fail to find an extension because it wasn't specified in
25684 alphabetical order, or because it does not exist? */
25686 for (opt = arm_extensions; opt->name != NULL; opt++)
25687 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25690 if (opt->name == NULL)
25691 as_bad (_("unknown architectural extension `%s'"), str);
25693 as_bad (_("architectural extensions must be specified in "
25694 "alphabetical order"));
25700 /* We should skip the extension we've just matched the next time
25712 arm_parse_cpu (const char *str)
25714 const struct arm_cpu_option_table *opt;
25715 const char *ext = strchr (str, '+');
25721 len = strlen (str);
25725 as_bad (_("missing cpu name `%s'"), str);
25729 for (opt = arm_cpus; opt->name != NULL; opt++)
25730 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25732 mcpu_cpu_opt = &opt->value;
25733 mcpu_fpu_opt = &opt->default_fpu;
25734 if (opt->canonical_name)
25736 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
25737 strcpy (selected_cpu_name, opt->canonical_name);
25743 if (len >= sizeof selected_cpu_name)
25744 len = (sizeof selected_cpu_name) - 1;
25746 for (i = 0; i < len; i++)
25747 selected_cpu_name[i] = TOUPPER (opt->name[i]);
25748 selected_cpu_name[i] = 0;
25752 return arm_parse_extension (ext, &mcpu_cpu_opt);
25757 as_bad (_("unknown cpu `%s'"), str);
25762 arm_parse_arch (const char *str)
25764 const struct arm_arch_option_table *opt;
25765 const char *ext = strchr (str, '+');
25771 len = strlen (str);
25775 as_bad (_("missing architecture name `%s'"), str);
25779 for (opt = arm_archs; opt->name != NULL; opt++)
25780 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25782 march_cpu_opt = &opt->value;
25783 march_fpu_opt = &opt->default_fpu;
25784 strcpy (selected_cpu_name, opt->name);
25787 return arm_parse_extension (ext, &march_cpu_opt);
25792 as_bad (_("unknown architecture `%s'\n"), str);
25797 arm_parse_fpu (const char * str)
25799 const struct arm_option_fpu_value_table * opt;
25801 for (opt = arm_fpus; opt->name != NULL; opt++)
25802 if (streq (opt->name, str))
25804 mfpu_opt = &opt->value;
25808 as_bad (_("unknown floating point format `%s'\n"), str);
25813 arm_parse_float_abi (const char * str)
25815 const struct arm_option_value_table * opt;
25817 for (opt = arm_float_abis; opt->name != NULL; opt++)
25818 if (streq (opt->name, str))
25820 mfloat_abi_opt = opt->value;
25824 as_bad (_("unknown floating point abi `%s'\n"), str);
25830 arm_parse_eabi (const char * str)
25832 const struct arm_option_value_table *opt;
25834 for (opt = arm_eabis; opt->name != NULL; opt++)
25835 if (streq (opt->name, str))
25837 meabi_flags = opt->value;
25840 as_bad (_("unknown EABI `%s'\n"), str);
25846 arm_parse_it_mode (const char * str)
25848 bfd_boolean ret = TRUE;
25850 if (streq ("arm", str))
25851 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
25852 else if (streq ("thumb", str))
25853 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
25854 else if (streq ("always", str))
25855 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
25856 else if (streq ("never", str))
25857 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
25860 as_bad (_("unknown implicit IT mode `%s', should be "\
25861 "arm, thumb, always, or never."), str);
25869 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
25871 codecomposer_syntax = TRUE;
25872 arm_comment_chars[0] = ';';
25873 arm_line_separator_chars[0] = 0;
25877 struct arm_long_option_table arm_long_opts[] =
25879 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25880 arm_parse_cpu, NULL},
25881 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25882 arm_parse_arch, NULL},
25883 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25884 arm_parse_fpu, NULL},
25885 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25886 arm_parse_float_abi, NULL},
25888 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25889 arm_parse_eabi, NULL},
25891 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25892 arm_parse_it_mode, NULL},
25893 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25894 arm_ccs_mode, NULL},
25895 {NULL, NULL, 0, NULL}
25899 md_parse_option (int c, const char * arg)
25901 struct arm_option_table *opt;
25902 const struct arm_legacy_option_table *fopt;
25903 struct arm_long_option_table *lopt;
25909 target_big_endian = 1;
25915 target_big_endian = 0;
25919 case OPTION_FIX_V4BX:
25924 /* Listing option. Just ignore these, we don't support additional
25929 for (opt = arm_opts; opt->option != NULL; opt++)
25931 if (c == opt->option[0]
25932 && ((arg == NULL && opt->option[1] == 0)
25933 || streq (arg, opt->option + 1)))
25935 /* If the option is deprecated, tell the user. */
25936 if (warn_on_deprecated && opt->deprecated != NULL)
25937 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
25938 arg ? arg : "", _(opt->deprecated));
25940 if (opt->var != NULL)
25941 *opt->var = opt->value;
25947 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
25949 if (c == fopt->option[0]
25950 && ((arg == NULL && fopt->option[1] == 0)
25951 || streq (arg, fopt->option + 1)))
25953 /* If the option is deprecated, tell the user. */
25954 if (warn_on_deprecated && fopt->deprecated != NULL)
25955 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
25956 arg ? arg : "", _(fopt->deprecated));
25958 if (fopt->var != NULL)
25959 *fopt->var = &fopt->value;
25965 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
25967 /* These options are expected to have an argument. */
25968 if (c == lopt->option[0]
25970 && strncmp (arg, lopt->option + 1,
25971 strlen (lopt->option + 1)) == 0)
25973 /* If the option is deprecated, tell the user. */
25974 if (warn_on_deprecated && lopt->deprecated != NULL)
25975 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
25976 _(lopt->deprecated));
25978 /* Call the sup-option parser. */
25979 return lopt->func (arg + strlen (lopt->option) - 1);
25990 md_show_usage (FILE * fp)
25992 struct arm_option_table *opt;
25993 struct arm_long_option_table *lopt;
25995 fprintf (fp, _(" ARM-specific assembler options:\n"));
25997 for (opt = arm_opts; opt->option != NULL; opt++)
25998 if (opt->help != NULL)
25999 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
26001 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
26002 if (lopt->help != NULL)
26003 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
26007 -EB assemble code for a big-endian cpu\n"));
26012 -EL assemble code for a little-endian cpu\n"));
26016 --fix-v4bx Allow BX in ARMv4 code\n"));
26024 arm_feature_set flags;
26025 } cpu_arch_ver_table;
26027 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26028 must be sorted least features first but some reordering is needed, eg. for
26029 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26030 static const cpu_arch_ver_table cpu_arch_ver[] =
26036 {4, ARM_ARCH_V5TE},
26037 {5, ARM_ARCH_V5TEJ},
26041 {11, ARM_ARCH_V6M},
26042 {12, ARM_ARCH_V6SM},
26043 {8, ARM_ARCH_V6T2},
26044 {10, ARM_ARCH_V7VE},
26045 {10, ARM_ARCH_V7R},
26046 {10, ARM_ARCH_V7M},
26047 {14, ARM_ARCH_V8A},
26048 {16, ARM_ARCH_V8M_BASE},
26049 {17, ARM_ARCH_V8M_MAIN},
26053 /* Set an attribute if it has not already been set by the user. */
26055 aeabi_set_attribute_int (int tag, int value)
26058 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
26059 || !attributes_set_explicitly[tag])
26060 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
26064 aeabi_set_attribute_string (int tag, const char *value)
26067 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
26068 || !attributes_set_explicitly[tag])
26069 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
26072 /* Set the public EABI object attributes. */
26074 aeabi_set_public_attributes (void)
26079 int fp16_optional = 0;
26080 arm_feature_set flags;
26081 arm_feature_set tmp;
26082 arm_feature_set arm_arch_v8m_base = ARM_ARCH_V8M_BASE;
26083 const cpu_arch_ver_table *p;
26085 /* Choose the architecture based on the capabilities of the requested cpu
26086 (if any) and/or the instructions actually used. */
26087 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
26088 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
26089 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
26091 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
26092 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
26094 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
26095 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
26097 selected_cpu = flags;
26099 /* Allow the user to override the reported architecture. */
26102 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
26103 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
26106 /* We need to make sure that the attributes do not identify us as v6S-M
26107 when the only v6S-M feature in use is the Operating System Extensions. */
26108 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
26109 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
26110 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
26114 for (p = cpu_arch_ver; p->val; p++)
26116 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
26119 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
26123 /* The table lookup above finds the last architecture to contribute
26124 a new feature. Unfortunately, Tag13 is a subset of the union of
26125 v6T2 and v7-M, so it is never seen as contributing a new feature.
26126 We can not search for the last entry which is entirely used,
26127 because if no CPU is specified we build up only those flags
26128 actually used. Perhaps we should separate out the specified
26129 and implicit cases. Avoid taking this path for -march=all by
26130 checking for contradictory v7-A / v7-M features. */
26131 if (arch == TAG_CPU_ARCH_V7
26132 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
26133 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
26134 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
26135 arch = TAG_CPU_ARCH_V7E_M;
26137 ARM_CLEAR_FEATURE (tmp, flags, arm_arch_v8m_base);
26138 if (arch == TAG_CPU_ARCH_V8M_BASE && ARM_CPU_HAS_FEATURE (tmp, arm_arch_any))
26139 arch = TAG_CPU_ARCH_V8M_MAIN;
26141 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26142 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26143 ARMv8-M, -march=all must be detected as ARMv8-A. */
26144 if (arch == TAG_CPU_ARCH_V8M_MAIN
26145 && ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
26146 arch = TAG_CPU_ARCH_V8;
26148 /* Tag_CPU_name. */
26149 if (selected_cpu_name[0])
26153 q = selected_cpu_name;
26154 if (strncmp (q, "armv", 4) == 0)
26159 for (i = 0; q[i]; i++)
26160 q[i] = TOUPPER (q[i]);
26162 aeabi_set_attribute_string (Tag_CPU_name, q);
26165 /* Tag_CPU_arch. */
26166 aeabi_set_attribute_int (Tag_CPU_arch, arch);
26168 /* Tag_CPU_arch_profile. */
26169 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
26170 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
26171 || (ARM_CPU_HAS_FEATURE (flags, arm_ext_atomics)
26172 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m)))
26174 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
26176 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
26181 if (profile != '\0')
26182 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
26184 /* Tag_ARM_ISA_use. */
26185 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
26187 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
26189 /* Tag_THUMB_ISA_use. */
26190 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
26195 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
26196 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
26198 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
26202 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
26205 /* Tag_VFP_arch. */
26206 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
26207 aeabi_set_attribute_int (Tag_VFP_arch,
26208 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
26210 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
26211 aeabi_set_attribute_int (Tag_VFP_arch,
26212 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
26214 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
26217 aeabi_set_attribute_int (Tag_VFP_arch, 3);
26219 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
26221 aeabi_set_attribute_int (Tag_VFP_arch, 4);
26224 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
26225 aeabi_set_attribute_int (Tag_VFP_arch, 2);
26226 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
26227 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
26228 aeabi_set_attribute_int (Tag_VFP_arch, 1);
26230 /* Tag_ABI_HardFP_use. */
26231 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
26232 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
26233 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
26235 /* Tag_WMMX_arch. */
26236 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
26237 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
26238 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
26239 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
26241 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26242 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
26243 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
26244 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
26245 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
26246 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
26248 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
26250 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
26254 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
26259 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26260 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
26261 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
26265 We set Tag_DIV_use to two when integer divide instructions have been used
26266 in ARM state, or when Thumb integer divide instructions have been used,
26267 but we have no architecture profile set, nor have we any ARM instructions.
26269 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26270 by the base architecture.
26272 For new architectures we will have to check these tests. */
26273 gas_assert (arch <= TAG_CPU_ARCH_V8
26274 || (arch >= TAG_CPU_ARCH_V8M_BASE
26275 && arch <= TAG_CPU_ARCH_V8M_MAIN));
26276 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
26277 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
26278 aeabi_set_attribute_int (Tag_DIV_use, 0);
26279 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
26280 || (profile == '\0'
26281 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
26282 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
26283 aeabi_set_attribute_int (Tag_DIV_use, 2);
26285 /* Tag_MP_extension_use. */
26286 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
26287 aeabi_set_attribute_int (Tag_MPextension_use, 1);
26289 /* Tag Virtualization_use. */
26290 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
26292 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
26295 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
26298 /* Add the default contents for the .ARM.attributes section. */
26302 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
26305 aeabi_set_public_attributes ();
26307 #endif /* OBJ_ELF */
26310 /* Parse a .cpu directive. */
26313 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
26315 const struct arm_cpu_option_table *opt;
26319 name = input_line_pointer;
26320 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
26321 input_line_pointer++;
26322 saved_char = *input_line_pointer;
26323 *input_line_pointer = 0;
26325 /* Skip the first "all" entry. */
26326 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
26327 if (streq (opt->name, name))
26329 mcpu_cpu_opt = &opt->value;
26330 selected_cpu = opt->value;
26331 if (opt->canonical_name)
26332 strcpy (selected_cpu_name, opt->canonical_name);
26336 for (i = 0; opt->name[i]; i++)
26337 selected_cpu_name[i] = TOUPPER (opt->name[i]);
26339 selected_cpu_name[i] = 0;
26341 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
26342 *input_line_pointer = saved_char;
26343 demand_empty_rest_of_line ();
26346 as_bad (_("unknown cpu `%s'"), name);
26347 *input_line_pointer = saved_char;
26348 ignore_rest_of_line ();
26352 /* Parse a .arch directive. */
26355 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
26357 const struct arm_arch_option_table *opt;
26361 name = input_line_pointer;
26362 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
26363 input_line_pointer++;
26364 saved_char = *input_line_pointer;
26365 *input_line_pointer = 0;
26367 /* Skip the first "all" entry. */
26368 for (opt = arm_archs + 1; opt->name != NULL; opt++)
26369 if (streq (opt->name, name))
26371 mcpu_cpu_opt = &opt->value;
26372 selected_cpu = opt->value;
26373 strcpy (selected_cpu_name, opt->name);
26374 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
26375 *input_line_pointer = saved_char;
26376 demand_empty_rest_of_line ();
26380 as_bad (_("unknown architecture `%s'\n"), name);
26381 *input_line_pointer = saved_char;
26382 ignore_rest_of_line ();
26386 /* Parse a .object_arch directive. */
26389 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
26391 const struct arm_arch_option_table *opt;
26395 name = input_line_pointer;
26396 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
26397 input_line_pointer++;
26398 saved_char = *input_line_pointer;
26399 *input_line_pointer = 0;
26401 /* Skip the first "all" entry. */
26402 for (opt = arm_archs + 1; opt->name != NULL; opt++)
26403 if (streq (opt->name, name))
26405 object_arch = &opt->value;
26406 *input_line_pointer = saved_char;
26407 demand_empty_rest_of_line ();
26411 as_bad (_("unknown architecture `%s'\n"), name);
26412 *input_line_pointer = saved_char;
26413 ignore_rest_of_line ();
26416 /* Parse a .arch_extension directive. */
26419 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
26421 const struct arm_option_extension_value_table *opt;
26424 int adding_value = 1;
26426 name = input_line_pointer;
26427 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
26428 input_line_pointer++;
26429 saved_char = *input_line_pointer;
26430 *input_line_pointer = 0;
26432 if (strlen (name) >= 2
26433 && strncmp (name, "no", 2) == 0)
26439 for (opt = arm_extensions; opt->name != NULL; opt++)
26440 if (streq (opt->name, name))
26442 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
26444 as_bad (_("architectural extension `%s' is not allowed for the "
26445 "current base architecture"), name);
26450 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu,
26453 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value);
26455 mcpu_cpu_opt = &selected_cpu;
26456 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
26457 *input_line_pointer = saved_char;
26458 demand_empty_rest_of_line ();
26462 if (opt->name == NULL)
26463 as_bad (_("unknown architecture extension `%s'\n"), name);
26465 *input_line_pointer = saved_char;
26466 ignore_rest_of_line ();
26469 /* Parse a .fpu directive. */
26472 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
26474 const struct arm_option_fpu_value_table *opt;
26478 name = input_line_pointer;
26479 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
26480 input_line_pointer++;
26481 saved_char = *input_line_pointer;
26482 *input_line_pointer = 0;
26484 for (opt = arm_fpus; opt->name != NULL; opt++)
26485 if (streq (opt->name, name))
26487 mfpu_opt = &opt->value;
26488 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
26489 *input_line_pointer = saved_char;
26490 demand_empty_rest_of_line ();
26494 as_bad (_("unknown floating point format `%s'\n"), name);
26495 *input_line_pointer = saved_char;
26496 ignore_rest_of_line ();
26499 /* Copy symbol information. */
26502 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
26504 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
26508 /* Given a symbolic attribute NAME, return the proper integer value.
26509 Returns -1 if the attribute is not known. */
26512 arm_convert_symbolic_attribute (const char *name)
26514 static const struct
26519 attribute_table[] =
26521 /* When you modify this table you should
26522 also modify the list in doc/c-arm.texi. */
26523 #define T(tag) {#tag, tag}
26524 T (Tag_CPU_raw_name),
26527 T (Tag_CPU_arch_profile),
26528 T (Tag_ARM_ISA_use),
26529 T (Tag_THUMB_ISA_use),
26533 T (Tag_Advanced_SIMD_arch),
26534 T (Tag_PCS_config),
26535 T (Tag_ABI_PCS_R9_use),
26536 T (Tag_ABI_PCS_RW_data),
26537 T (Tag_ABI_PCS_RO_data),
26538 T (Tag_ABI_PCS_GOT_use),
26539 T (Tag_ABI_PCS_wchar_t),
26540 T (Tag_ABI_FP_rounding),
26541 T (Tag_ABI_FP_denormal),
26542 T (Tag_ABI_FP_exceptions),
26543 T (Tag_ABI_FP_user_exceptions),
26544 T (Tag_ABI_FP_number_model),
26545 T (Tag_ABI_align_needed),
26546 T (Tag_ABI_align8_needed),
26547 T (Tag_ABI_align_preserved),
26548 T (Tag_ABI_align8_preserved),
26549 T (Tag_ABI_enum_size),
26550 T (Tag_ABI_HardFP_use),
26551 T (Tag_ABI_VFP_args),
26552 T (Tag_ABI_WMMX_args),
26553 T (Tag_ABI_optimization_goals),
26554 T (Tag_ABI_FP_optimization_goals),
26555 T (Tag_compatibility),
26556 T (Tag_CPU_unaligned_access),
26557 T (Tag_FP_HP_extension),
26558 T (Tag_VFP_HP_extension),
26559 T (Tag_ABI_FP_16bit_format),
26560 T (Tag_MPextension_use),
26562 T (Tag_nodefaults),
26563 T (Tag_also_compatible_with),
26564 T (Tag_conformance),
26566 T (Tag_Virtualization_use),
26567 /* We deliberately do not include Tag_MPextension_use_legacy. */
26575 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
26576 if (streq (name, attribute_table[i].name))
26577 return attribute_table[i].tag;
26583 /* Apply sym value for relocations only in the case that they are for
26584 local symbols in the same segment as the fixup and you have the
26585 respective architectural feature for blx and simple switches. */
26587 arm_apply_sym_value (struct fix * fixP, segT this_seg)
26590 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
26591 /* PR 17444: If the local symbol is in a different section then a reloc
26592 will always be generated for it, so applying the symbol value now
26593 will result in a double offset being stored in the relocation. */
26594 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
26595 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
26597 switch (fixP->fx_r_type)
26599 case BFD_RELOC_ARM_PCREL_BLX:
26600 case BFD_RELOC_THUMB_PCREL_BRANCH23:
26601 if (ARM_IS_FUNC (fixP->fx_addsy))
26605 case BFD_RELOC_ARM_PCREL_CALL:
26606 case BFD_RELOC_THUMB_PCREL_BLX:
26607 if (THUMB_IS_FUNC (fixP->fx_addsy))
26618 #endif /* OBJ_ELF */