1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994-2013 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant;
127 static arm_feature_set arm_arch_used;
128 static arm_feature_set thumb_arch_used;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26 = FALSE;
132 static int atpcs = FALSE;
133 static int support_interwork = FALSE;
134 static int uses_apcs_float = FALSE;
135 static int pic_code = FALSE;
136 static int fix_v4bx = FALSE;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated = TRUE;
141 /* Variables that we set while parsing command-line options. Once all
142 options have been read we re-process these values to set the real
144 static const arm_feature_set *legacy_cpu = NULL;
145 static const arm_feature_set *legacy_fpu = NULL;
147 static const arm_feature_set *mcpu_cpu_opt = NULL;
148 static const arm_feature_set *mcpu_fpu_opt = NULL;
149 static const arm_feature_set *march_cpu_opt = NULL;
150 static const arm_feature_set *march_fpu_opt = NULL;
151 static const arm_feature_set *mfpu_opt = NULL;
152 static const arm_feature_set *object_arch = NULL;
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default = FPU_DEFAULT;
156 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
158 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
159 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
160 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
161 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
162 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
163 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
166 static const arm_feature_set cpu_default = CPU_DEFAULT;
169 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
170 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
171 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
172 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
173 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
174 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
175 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
176 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
177 static const arm_feature_set arm_ext_v4t_5 =
178 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
180 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
181 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
182 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
183 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
184 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
185 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
186 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
187 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
188 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
189 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
190 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
191 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
192 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
193 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
194 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
195 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
196 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
197 static const arm_feature_set arm_ext_m =
198 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
199 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
200 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
201 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
202 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
203 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
205 static const arm_feature_set arm_arch_any = ARM_ANY;
206 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
208 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
209 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
211 static const arm_feature_set arm_cext_iwmmxt2 =
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
213 static const arm_feature_set arm_cext_iwmmxt =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
215 static const arm_feature_set arm_cext_xscale =
216 ARM_FEATURE (0, ARM_CEXT_XSCALE);
217 static const arm_feature_set arm_cext_maverick =
218 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
219 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
220 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
221 static const arm_feature_set fpu_vfp_ext_v1xd =
222 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
223 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
224 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
225 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
226 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
227 static const arm_feature_set fpu_vfp_ext_d32 =
228 ARM_FEATURE (0, FPU_VFP_EXT_D32);
229 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
230 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
231 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
232 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
233 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
234 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_armv8 =
236 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
237 static const arm_feature_set fpu_neon_ext_armv8 =
238 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
239 static const arm_feature_set fpu_crypto_ext_armv8 =
240 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
241 static const arm_feature_set crc_ext_armv8 =
242 ARM_FEATURE (0, CRC_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
324 /* An immediate operand can start with #, and ld*, st*, pld operands
325 can contain [ and ]. We need to tell APP not to elide whitespace
326 before a [, which can appear as the first operand for pld. */
327 const char arm_symbol_chars[] = "#[]";
342 enum neon_el_type type;
346 #define NEON_MAX_TYPE_ELS 4
350 struct neon_type_el el[NEON_MAX_TYPE_ELS];
354 enum it_instruction_type
359 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
360 if inside, should be the last one. */
361 NEUTRAL_IT_INSN, /* This could be either inside or outside,
362 i.e. BKPT and NOP. */
363 IT_INSN /* The IT insn has been parsed. */
366 /* The maximum number of operands we need. */
367 #define ARM_IT_MAX_OPERANDS 6
372 unsigned long instruction;
376 /* "uncond_value" is set to the value in place of the conditional field in
377 unconditional versions of the instruction, or -1 if nothing is
380 struct neon_type vectype;
381 /* This does not indicate an actual NEON instruction, only that
382 the mnemonic accepts neon-style type suffixes. */
384 /* Set to the opcode if the instruction needs relaxation.
385 Zero if the instruction is not relaxed. */
389 bfd_reloc_code_real_type type;
394 enum it_instruction_type it_insn_type;
400 struct neon_type_el vectype;
401 unsigned present : 1; /* Operand present. */
402 unsigned isreg : 1; /* Operand was a register. */
403 unsigned immisreg : 1; /* .imm field is a second register. */
404 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
405 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
406 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
407 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
408 instructions. This allows us to disambiguate ARM <-> vector insns. */
409 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
410 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
411 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
412 unsigned issingle : 1; /* Operand is VFP single-precision register. */
413 unsigned hasreloc : 1; /* Operand has relocation suffix. */
414 unsigned writeback : 1; /* Operand has trailing ! */
415 unsigned preind : 1; /* Preindexed address. */
416 unsigned postind : 1; /* Postindexed address. */
417 unsigned negative : 1; /* Index register was negated. */
418 unsigned shifted : 1; /* Shift applied to operation. */
419 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
420 } operands[ARM_IT_MAX_OPERANDS];
423 static struct arm_it inst;
425 #define NUM_FLOAT_VALS 8
427 const char * fp_const[] =
429 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
432 /* Number of littlenums required to hold an extended precision number. */
433 #define MAX_LITTLENUMS 6
435 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
445 #define CP_T_X 0x00008000
446 #define CP_T_Y 0x00400000
448 #define CONDS_BIT 0x00100000
449 #define LOAD_BIT 0x00100000
451 #define DOUBLE_LOAD_FLAG 0x00000001
455 const char * template_name;
459 #define COND_ALWAYS 0xE
463 const char * template_name;
467 struct asm_barrier_opt
469 const char * template_name;
471 const arm_feature_set arch;
474 /* The bit that distinguishes CPSR and SPSR. */
475 #define SPSR_BIT (1 << 22)
477 /* The individual PSR flag bits. */
478 #define PSR_c (1 << 16)
479 #define PSR_x (1 << 17)
480 #define PSR_s (1 << 18)
481 #define PSR_f (1 << 19)
486 bfd_reloc_code_real_type reloc;
491 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
492 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
497 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
500 /* Bits for DEFINED field in neon_typed_alias. */
501 #define NTA_HASTYPE 1
502 #define NTA_HASINDEX 2
504 struct neon_typed_alias
506 unsigned char defined;
508 struct neon_type_el eltype;
511 /* ARM register categories. This includes coprocessor numbers and various
512 architecture extensions' registers. */
539 /* Structure for a hash table entry for a register.
540 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
541 information which states whether a vector type or index is specified (for a
542 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
548 unsigned char builtin;
549 struct neon_typed_alias * neon;
552 /* Diagnostics used when we don't get a register of the expected type. */
553 const char * const reg_expected_msgs[] =
555 N_("ARM register expected"),
556 N_("bad or missing co-processor number"),
557 N_("co-processor register expected"),
558 N_("FPA register expected"),
559 N_("VFP single precision register expected"),
560 N_("VFP/Neon double precision register expected"),
561 N_("Neon quad precision register expected"),
562 N_("VFP single or double precision register expected"),
563 N_("Neon double or quad precision register expected"),
564 N_("VFP single, double or Neon quad precision register expected"),
565 N_("VFP system register expected"),
566 N_("Maverick MVF register expected"),
567 N_("Maverick MVD register expected"),
568 N_("Maverick MVFX register expected"),
569 N_("Maverick MVDX register expected"),
570 N_("Maverick MVAX register expected"),
571 N_("Maverick DSPSC register expected"),
572 N_("iWMMXt data register expected"),
573 N_("iWMMXt control register expected"),
574 N_("iWMMXt scalar register expected"),
575 N_("XScale accumulator register expected"),
578 /* Some well known registers that we refer to directly elsewhere. */
584 /* ARM instructions take 4bytes in the object file, Thumb instructions
590 /* Basic string to match. */
591 const char * template_name;
593 /* Parameters to instruction. */
594 unsigned int operands[8];
596 /* Conditional tag - see opcode_lookup. */
597 unsigned int tag : 4;
599 /* Basic instruction code. */
600 unsigned int avalue : 28;
602 /* Thumb-format instruction code. */
605 /* Which architecture variant provides this instruction. */
606 const arm_feature_set * avariant;
607 const arm_feature_set * tvariant;
609 /* Function to call to encode instruction in ARM format. */
610 void (* aencode) (void);
612 /* Function to call to encode instruction in Thumb format. */
613 void (* tencode) (void);
616 /* Defines for various bits that we will want to toggle. */
617 #define INST_IMMEDIATE 0x02000000
618 #define OFFSET_REG 0x02000000
619 #define HWOFFSET_IMM 0x00400000
620 #define SHIFT_BY_REG 0x00000010
621 #define PRE_INDEX 0x01000000
622 #define INDEX_UP 0x00800000
623 #define WRITE_BACK 0x00200000
624 #define LDM_TYPE_2_OR_3 0x00400000
625 #define CPSI_MMOD 0x00020000
627 #define LITERAL_MASK 0xf000f000
628 #define OPCODE_MASK 0xfe1fffff
629 #define V4_STR_BIT 0x00000020
631 #define T2_SUBS_PC_LR 0xf3de8f00
633 #define DATA_OP_SHIFT 21
635 #define T2_OPCODE_MASK 0xfe1fffff
636 #define T2_DATA_OP_SHIFT 21
638 #define A_COND_MASK 0xf0000000
639 #define A_PUSH_POP_OP_MASK 0x0fff0000
641 /* Opcodes for pushing/poping registers to/from the stack. */
642 #define A1_OPCODE_PUSH 0x092d0000
643 #define A2_OPCODE_PUSH 0x052d0004
644 #define A2_OPCODE_POP 0x049d0004
646 /* Codes to distinguish the arithmetic instructions. */
657 #define OPCODE_CMP 10
658 #define OPCODE_CMN 11
659 #define OPCODE_ORR 12
660 #define OPCODE_MOV 13
661 #define OPCODE_BIC 14
662 #define OPCODE_MVN 15
664 #define T2_OPCODE_AND 0
665 #define T2_OPCODE_BIC 1
666 #define T2_OPCODE_ORR 2
667 #define T2_OPCODE_ORN 3
668 #define T2_OPCODE_EOR 4
669 #define T2_OPCODE_ADD 8
670 #define T2_OPCODE_ADC 10
671 #define T2_OPCODE_SBC 11
672 #define T2_OPCODE_SUB 13
673 #define T2_OPCODE_RSB 14
675 #define T_OPCODE_MUL 0x4340
676 #define T_OPCODE_TST 0x4200
677 #define T_OPCODE_CMN 0x42c0
678 #define T_OPCODE_NEG 0x4240
679 #define T_OPCODE_MVN 0x43c0
681 #define T_OPCODE_ADD_R3 0x1800
682 #define T_OPCODE_SUB_R3 0x1a00
683 #define T_OPCODE_ADD_HI 0x4400
684 #define T_OPCODE_ADD_ST 0xb000
685 #define T_OPCODE_SUB_ST 0xb080
686 #define T_OPCODE_ADD_SP 0xa800
687 #define T_OPCODE_ADD_PC 0xa000
688 #define T_OPCODE_ADD_I8 0x3000
689 #define T_OPCODE_SUB_I8 0x3800
690 #define T_OPCODE_ADD_I3 0x1c00
691 #define T_OPCODE_SUB_I3 0x1e00
693 #define T_OPCODE_ASR_R 0x4100
694 #define T_OPCODE_LSL_R 0x4080
695 #define T_OPCODE_LSR_R 0x40c0
696 #define T_OPCODE_ROR_R 0x41c0
697 #define T_OPCODE_ASR_I 0x1000
698 #define T_OPCODE_LSL_I 0x0000
699 #define T_OPCODE_LSR_I 0x0800
701 #define T_OPCODE_MOV_I8 0x2000
702 #define T_OPCODE_CMP_I8 0x2800
703 #define T_OPCODE_CMP_LR 0x4280
704 #define T_OPCODE_MOV_HR 0x4600
705 #define T_OPCODE_CMP_HR 0x4500
707 #define T_OPCODE_LDR_PC 0x4800
708 #define T_OPCODE_LDR_SP 0x9800
709 #define T_OPCODE_STR_SP 0x9000
710 #define T_OPCODE_LDR_IW 0x6800
711 #define T_OPCODE_STR_IW 0x6000
712 #define T_OPCODE_LDR_IH 0x8800
713 #define T_OPCODE_STR_IH 0x8000
714 #define T_OPCODE_LDR_IB 0x7800
715 #define T_OPCODE_STR_IB 0x7000
716 #define T_OPCODE_LDR_RW 0x5800
717 #define T_OPCODE_STR_RW 0x5000
718 #define T_OPCODE_LDR_RH 0x5a00
719 #define T_OPCODE_STR_RH 0x5200
720 #define T_OPCODE_LDR_RB 0x5c00
721 #define T_OPCODE_STR_RB 0x5400
723 #define T_OPCODE_PUSH 0xb400
724 #define T_OPCODE_POP 0xbc00
726 #define T_OPCODE_BRANCH 0xe000
728 #define THUMB_SIZE 2 /* Size of thumb instruction. */
729 #define THUMB_PP_PC_LR 0x0100
730 #define THUMB_LOAD_BIT 0x0800
731 #define THUMB2_LOAD_BIT 0x00100000
733 #define BAD_ARGS _("bad arguments to instruction")
734 #define BAD_SP _("r13 not allowed here")
735 #define BAD_PC _("r15 not allowed here")
736 #define BAD_COND _("instruction cannot be conditional")
737 #define BAD_OVERLAP _("registers may not be the same")
738 #define BAD_HIREG _("lo register required")
739 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
740 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
741 #define BAD_BRANCH _("branch must be last instruction in IT block")
742 #define BAD_NOT_IT _("instruction not allowed in IT block")
743 #define BAD_FPU _("selected FPU does not support instruction")
744 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
745 #define BAD_IT_COND _("incorrect condition in IT block")
746 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
747 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
748 #define BAD_PC_ADDRESSING \
749 _("cannot use register index with PC-relative addressing")
750 #define BAD_PC_WRITEBACK \
751 _("cannot use writeback with PC-relative addressing")
752 #define BAD_RANGE _("branch out of range")
753 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
755 static struct hash_control * arm_ops_hsh;
756 static struct hash_control * arm_cond_hsh;
757 static struct hash_control * arm_shift_hsh;
758 static struct hash_control * arm_psr_hsh;
759 static struct hash_control * arm_v7m_psr_hsh;
760 static struct hash_control * arm_reg_hsh;
761 static struct hash_control * arm_reloc_hsh;
762 static struct hash_control * arm_barrier_opt_hsh;
764 /* Stuff needed to resolve the label ambiguity
773 symbolS * last_label_seen;
774 static int label_is_thumb_function_name = FALSE;
776 /* Literal pool structure. Held on a per-section
777 and per-sub-section basis. */
779 #define MAX_LITERAL_POOL_SIZE 1024
780 typedef struct literal_pool
782 expressionS literals [MAX_LITERAL_POOL_SIZE];
783 unsigned int next_free_entry;
789 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
791 struct literal_pool * next;
794 /* Pointer to a linked list of literal pools. */
795 literal_pool * list_of_pools = NULL;
798 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
800 static struct current_it now_it;
804 now_it_compatible (int cond)
806 return (cond & ~1) == (now_it.cc & ~1);
810 conditional_insn (void)
812 return inst.cond != COND_ALWAYS;
815 static int in_it_block (void);
817 static int handle_it_state (void);
819 static void force_automatic_it_block_close (void);
821 static void it_fsm_post_encode (void);
823 #define set_it_insn_type(type) \
826 inst.it_insn_type = type; \
827 if (handle_it_state () == FAIL) \
832 #define set_it_insn_type_nonvoid(type, failret) \
835 inst.it_insn_type = type; \
836 if (handle_it_state () == FAIL) \
841 #define set_it_insn_type_last() \
844 if (inst.cond == COND_ALWAYS) \
845 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
847 set_it_insn_type (INSIDE_IT_LAST_INSN); \
853 /* This array holds the chars that always start a comment. If the
854 pre-processor is disabled, these aren't very useful. */
855 const char comment_chars[] = "@";
857 /* This array holds the chars that only start a comment at the beginning of
858 a line. If the line seems to have the form '# 123 filename'
859 .line and .file directives will appear in the pre-processed output. */
860 /* Note that input_file.c hand checks for '#' at the beginning of the
861 first line of the input file. This is because the compiler outputs
862 #NO_APP at the beginning of its output. */
863 /* Also note that comments like this one will always work. */
864 const char line_comment_chars[] = "#";
866 const char line_separator_chars[] = ";";
868 /* Chars that can be used to separate mant
869 from exp in floating point numbers. */
870 const char EXP_CHARS[] = "eE";
872 /* Chars that mean this number is a floating point constant. */
876 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
878 /* Prefix characters that indicate the start of an immediate
880 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
882 /* Separator character handling. */
884 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
887 skip_past_char (char ** str, char c)
889 /* PR gas/14987: Allow for whitespace before the expected character. */
890 skip_whitespace (*str);
901 #define skip_past_comma(str) skip_past_char (str, ',')
903 /* Arithmetic expressions (possibly involving symbols). */
905 /* Return TRUE if anything in the expression is a bignum. */
908 walk_no_bignums (symbolS * sp)
910 if (symbol_get_value_expression (sp)->X_op == O_big)
913 if (symbol_get_value_expression (sp)->X_add_symbol)
915 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
916 || (symbol_get_value_expression (sp)->X_op_symbol
917 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
923 static int in_my_get_expression = 0;
925 /* Third argument to my_get_expression. */
926 #define GE_NO_PREFIX 0
927 #define GE_IMM_PREFIX 1
928 #define GE_OPT_PREFIX 2
929 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
930 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
931 #define GE_OPT_PREFIX_BIG 3
934 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
939 /* In unified syntax, all prefixes are optional. */
941 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
946 case GE_NO_PREFIX: break;
948 if (!is_immediate_prefix (**str))
950 inst.error = _("immediate expression requires a # prefix");
956 case GE_OPT_PREFIX_BIG:
957 if (is_immediate_prefix (**str))
963 memset (ep, 0, sizeof (expressionS));
965 save_in = input_line_pointer;
966 input_line_pointer = *str;
967 in_my_get_expression = 1;
968 seg = expression (ep);
969 in_my_get_expression = 0;
971 if (ep->X_op == O_illegal || ep->X_op == O_absent)
973 /* We found a bad or missing expression in md_operand(). */
974 *str = input_line_pointer;
975 input_line_pointer = save_in;
976 if (inst.error == NULL)
977 inst.error = (ep->X_op == O_absent
978 ? _("missing expression") :_("bad expression"));
983 if (seg != absolute_section
984 && seg != text_section
985 && seg != data_section
986 && seg != bss_section
987 && seg != undefined_section)
989 inst.error = _("bad segment");
990 *str = input_line_pointer;
991 input_line_pointer = save_in;
998 /* Get rid of any bignums now, so that we don't generate an error for which
999 we can't establish a line number later on. Big numbers are never valid
1000 in instructions, which is where this routine is always called. */
1001 if (prefix_mode != GE_OPT_PREFIX_BIG
1002 && (ep->X_op == O_big
1003 || (ep->X_add_symbol
1004 && (walk_no_bignums (ep->X_add_symbol)
1006 && walk_no_bignums (ep->X_op_symbol))))))
1008 inst.error = _("invalid constant");
1009 *str = input_line_pointer;
1010 input_line_pointer = save_in;
1014 *str = input_line_pointer;
1015 input_line_pointer = save_in;
1019 /* Turn a string in input_line_pointer into a floating point constant
1020 of type TYPE, and store the appropriate bytes in *LITP. The number
1021 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1022 returned, or NULL on OK.
1024 Note that fp constants aren't represent in the normal way on the ARM.
1025 In big endian mode, things are as expected. However, in little endian
1026 mode fp constants are big-endian word-wise, and little-endian byte-wise
1027 within the words. For example, (double) 1.1 in big endian mode is
1028 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1029 the byte sequence 99 99 f1 3f 9a 99 99 99.
1031 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1034 md_atof (int type, char * litP, int * sizeP)
1037 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1069 return _("Unrecognized or unsupported floating point constant");
1072 t = atof_ieee (input_line_pointer, type, words);
1074 input_line_pointer = t;
1075 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1077 if (target_big_endian)
1079 for (i = 0; i < prec; i++)
1081 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1082 litP += sizeof (LITTLENUM_TYPE);
1087 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1088 for (i = prec - 1; i >= 0; i--)
1090 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1091 litP += sizeof (LITTLENUM_TYPE);
1094 /* For a 4 byte float the order of elements in `words' is 1 0.
1095 For an 8 byte float the order is 1 0 3 2. */
1096 for (i = 0; i < prec; i += 2)
1098 md_number_to_chars (litP, (valueT) words[i + 1],
1099 sizeof (LITTLENUM_TYPE));
1100 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1101 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1102 litP += 2 * sizeof (LITTLENUM_TYPE);
1109 /* We handle all bad expressions here, so that we can report the faulty
1110 instruction in the error message. */
1112 md_operand (expressionS * exp)
1114 if (in_my_get_expression)
1115 exp->X_op = O_illegal;
1118 /* Immediate values. */
1120 /* Generic immediate-value read function for use in directives.
1121 Accepts anything that 'expression' can fold to a constant.
1122 *val receives the number. */
1125 immediate_for_directive (int *val)
1128 exp.X_op = O_illegal;
1130 if (is_immediate_prefix (*input_line_pointer))
1132 input_line_pointer++;
1136 if (exp.X_op != O_constant)
1138 as_bad (_("expected #constant"));
1139 ignore_rest_of_line ();
1142 *val = exp.X_add_number;
1147 /* Register parsing. */
1149 /* Generic register parser. CCP points to what should be the
1150 beginning of a register name. If it is indeed a valid register
1151 name, advance CCP over it and return the reg_entry structure;
1152 otherwise return NULL. Does not issue diagnostics. */
1154 static struct reg_entry *
1155 arm_reg_parse_multi (char **ccp)
1159 struct reg_entry *reg;
1161 #ifdef REGISTER_PREFIX
1162 if (*start != REGISTER_PREFIX)
1166 #ifdef OPTIONAL_REGISTER_PREFIX
1167 if (*start == OPTIONAL_REGISTER_PREFIX)
1172 if (!ISALPHA (*p) || !is_name_beginner (*p))
1177 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1179 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1189 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1190 enum arm_reg_type type)
1192 /* Alternative syntaxes are accepted for a few register classes. */
1199 /* Generic coprocessor register names are allowed for these. */
1200 if (reg && reg->type == REG_TYPE_CN)
1205 /* For backward compatibility, a bare number is valid here. */
1207 unsigned long processor = strtoul (start, ccp, 10);
1208 if (*ccp != start && processor <= 15)
1212 case REG_TYPE_MMXWC:
1213 /* WC includes WCG. ??? I'm not sure this is true for all
1214 instructions that take WC registers. */
1215 if (reg && reg->type == REG_TYPE_MMXWCG)
1226 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1227 return value is the register number or FAIL. */
1230 arm_reg_parse (char **ccp, enum arm_reg_type type)
1233 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1236 /* Do not allow a scalar (reg+index) to parse as a register. */
1237 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1240 if (reg && reg->type == type)
1243 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1250 /* Parse a Neon type specifier. *STR should point at the leading '.'
1251 character. Does no verification at this stage that the type fits the opcode
1258 Can all be legally parsed by this function.
1260 Fills in neon_type struct pointer with parsed information, and updates STR
1261 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1262 type, FAIL if not. */
1265 parse_neon_type (struct neon_type *type, char **str)
1272 while (type->elems < NEON_MAX_TYPE_ELS)
1274 enum neon_el_type thistype = NT_untyped;
1275 unsigned thissize = -1u;
1282 /* Just a size without an explicit type. */
1286 switch (TOLOWER (*ptr))
1288 case 'i': thistype = NT_integer; break;
1289 case 'f': thistype = NT_float; break;
1290 case 'p': thistype = NT_poly; break;
1291 case 's': thistype = NT_signed; break;
1292 case 'u': thistype = NT_unsigned; break;
1294 thistype = NT_float;
1299 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1305 /* .f is an abbreviation for .f32. */
1306 if (thistype == NT_float && !ISDIGIT (*ptr))
1311 thissize = strtoul (ptr, &ptr, 10);
1313 if (thissize != 8 && thissize != 16 && thissize != 32
1316 as_bad (_("bad size %d in type specifier"), thissize);
1324 type->el[type->elems].type = thistype;
1325 type->el[type->elems].size = thissize;
1330 /* Empty/missing type is not a successful parse. */
1331 if (type->elems == 0)
1339 /* Errors may be set multiple times during parsing or bit encoding
1340 (particularly in the Neon bits), but usually the earliest error which is set
1341 will be the most meaningful. Avoid overwriting it with later (cascading)
1342 errors by calling this function. */
1345 first_error (const char *err)
1351 /* Parse a single type, e.g. ".s32", leading period included. */
1353 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1356 struct neon_type optype;
1360 if (parse_neon_type (&optype, &str) == SUCCESS)
1362 if (optype.elems == 1)
1363 *vectype = optype.el[0];
1366 first_error (_("only one type should be specified for operand"));
1372 first_error (_("vector type expected"));
1384 /* Special meanings for indices (which have a range of 0-7), which will fit into
1387 #define NEON_ALL_LANES 15
1388 #define NEON_INTERLEAVE_LANES 14
1390 /* Parse either a register or a scalar, with an optional type. Return the
1391 register number, and optionally fill in the actual type of the register
1392 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1393 type/index information in *TYPEINFO. */
1396 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1397 enum arm_reg_type *rtype,
1398 struct neon_typed_alias *typeinfo)
1401 struct reg_entry *reg = arm_reg_parse_multi (&str);
1402 struct neon_typed_alias atype;
1403 struct neon_type_el parsetype;
1407 atype.eltype.type = NT_invtype;
1408 atype.eltype.size = -1;
1410 /* Try alternate syntax for some types of register. Note these are mutually
1411 exclusive with the Neon syntax extensions. */
1414 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1422 /* Undo polymorphism when a set of register types may be accepted. */
1423 if ((type == REG_TYPE_NDQ
1424 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1425 || (type == REG_TYPE_VFSD
1426 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1427 || (type == REG_TYPE_NSDQ
1428 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1429 || reg->type == REG_TYPE_NQ))
1430 || (type == REG_TYPE_MMXWC
1431 && (reg->type == REG_TYPE_MMXWCG)))
1432 type = (enum arm_reg_type) reg->type;
1434 if (type != reg->type)
1440 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1442 if ((atype.defined & NTA_HASTYPE) != 0)
1444 first_error (_("can't redefine type for operand"));
1447 atype.defined |= NTA_HASTYPE;
1448 atype.eltype = parsetype;
1451 if (skip_past_char (&str, '[') == SUCCESS)
1453 if (type != REG_TYPE_VFD)
1455 first_error (_("only D registers may be indexed"));
1459 if ((atype.defined & NTA_HASINDEX) != 0)
1461 first_error (_("can't change index for operand"));
1465 atype.defined |= NTA_HASINDEX;
1467 if (skip_past_char (&str, ']') == SUCCESS)
1468 atype.index = NEON_ALL_LANES;
1473 my_get_expression (&exp, &str, GE_NO_PREFIX);
1475 if (exp.X_op != O_constant)
1477 first_error (_("constant expression required"));
1481 if (skip_past_char (&str, ']') == FAIL)
1484 atype.index = exp.X_add_number;
1499 /* Like arm_reg_parse, but allow allow the following extra features:
1500 - If RTYPE is non-zero, return the (possibly restricted) type of the
1501 register (e.g. Neon double or quad reg when either has been requested).
1502 - If this is a Neon vector type with additional type information, fill
1503 in the struct pointed to by VECTYPE (if non-NULL).
1504 This function will fault on encountering a scalar. */
1507 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1508 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1510 struct neon_typed_alias atype;
1512 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1517 /* Do not allow regname(... to parse as a register. */
1521 /* Do not allow a scalar (reg+index) to parse as a register. */
1522 if ((atype.defined & NTA_HASINDEX) != 0)
1524 first_error (_("register operand expected, but got scalar"));
1529 *vectype = atype.eltype;
1536 #define NEON_SCALAR_REG(X) ((X) >> 4)
1537 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1539 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1540 have enough information to be able to do a good job bounds-checking. So, we
1541 just do easy checks here, and do further checks later. */
1544 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1548 struct neon_typed_alias atype;
1550 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1552 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1555 if (atype.index == NEON_ALL_LANES)
1557 first_error (_("scalar must have an index"));
1560 else if (atype.index >= 64 / elsize)
1562 first_error (_("scalar index out of range"));
1567 *type = atype.eltype;
1571 return reg * 16 + atype.index;
1574 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1577 parse_reg_list (char ** strp)
1579 char * str = * strp;
1583 /* We come back here if we get ranges concatenated by '+' or '|'. */
1598 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1600 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1610 first_error (_("bad range in register list"));
1614 for (i = cur_reg + 1; i < reg; i++)
1616 if (range & (1 << i))
1618 (_("Warning: duplicated register (r%d) in register list"),
1626 if (range & (1 << reg))
1627 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1629 else if (reg <= cur_reg)
1630 as_tsktsk (_("Warning: register range not in ascending order"));
1635 while (skip_past_comma (&str) != FAIL
1636 || (in_range = 1, *str++ == '-'));
1641 first_error (_("missing `}'"));
1649 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1652 if (exp.X_op == O_constant)
1654 if (exp.X_add_number
1655 != (exp.X_add_number & 0x0000ffff))
1657 inst.error = _("invalid register mask");
1661 if ((range & exp.X_add_number) != 0)
1663 int regno = range & exp.X_add_number;
1666 regno = (1 << regno) - 1;
1668 (_("Warning: duplicated register (r%d) in register list"),
1672 range |= exp.X_add_number;
1676 if (inst.reloc.type != 0)
1678 inst.error = _("expression too complex");
1682 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1683 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1684 inst.reloc.pc_rel = 0;
1688 if (*str == '|' || *str == '+')
1694 while (another_range);
1700 /* Types of registers in a list. */
1709 /* Parse a VFP register list. If the string is invalid return FAIL.
1710 Otherwise return the number of registers, and set PBASE to the first
1711 register. Parses registers of type ETYPE.
1712 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1713 - Q registers can be used to specify pairs of D registers
1714 - { } can be omitted from around a singleton register list
1715 FIXME: This is not implemented, as it would require backtracking in
1718 This could be done (the meaning isn't really ambiguous), but doesn't
1719 fit in well with the current parsing framework.
1720 - 32 D registers may be used (also true for VFPv3).
1721 FIXME: Types are ignored in these register lists, which is probably a
1725 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1730 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1734 unsigned long mask = 0;
1739 inst.error = _("expecting {");
1748 regtype = REG_TYPE_VFS;
1753 regtype = REG_TYPE_VFD;
1756 case REGLIST_NEON_D:
1757 regtype = REG_TYPE_NDQ;
1761 if (etype != REGLIST_VFP_S)
1763 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1764 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1768 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1771 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1778 base_reg = max_regs;
1782 int setmask = 1, addregs = 1;
1784 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1786 if (new_base == FAIL)
1788 first_error (_(reg_expected_msgs[regtype]));
1792 if (new_base >= max_regs)
1794 first_error (_("register out of range in list"));
1798 /* Note: a value of 2 * n is returned for the register Q<n>. */
1799 if (regtype == REG_TYPE_NQ)
1805 if (new_base < base_reg)
1806 base_reg = new_base;
1808 if (mask & (setmask << new_base))
1810 first_error (_("invalid register list"));
1814 if ((mask >> new_base) != 0 && ! warned)
1816 as_tsktsk (_("register list not in ascending order"));
1820 mask |= setmask << new_base;
1823 if (*str == '-') /* We have the start of a range expression */
1829 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1832 inst.error = gettext (reg_expected_msgs[regtype]);
1836 if (high_range >= max_regs)
1838 first_error (_("register out of range in list"));
1842 if (regtype == REG_TYPE_NQ)
1843 high_range = high_range + 1;
1845 if (high_range <= new_base)
1847 inst.error = _("register range not in ascending order");
1851 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1853 if (mask & (setmask << new_base))
1855 inst.error = _("invalid register list");
1859 mask |= setmask << new_base;
1864 while (skip_past_comma (&str) != FAIL);
1868 /* Sanity check -- should have raised a parse error above. */
1869 if (count == 0 || count > max_regs)
1874 /* Final test -- the registers must be consecutive. */
1876 for (i = 0; i < count; i++)
1878 if ((mask & (1u << i)) == 0)
1880 inst.error = _("non-contiguous register range");
1890 /* True if two alias types are the same. */
1893 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1901 if (a->defined != b->defined)
1904 if ((a->defined & NTA_HASTYPE) != 0
1905 && (a->eltype.type != b->eltype.type
1906 || a->eltype.size != b->eltype.size))
1909 if ((a->defined & NTA_HASINDEX) != 0
1910 && (a->index != b->index))
1916 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1917 The base register is put in *PBASE.
1918 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1920 The register stride (minus one) is put in bit 4 of the return value.
1921 Bits [6:5] encode the list length (minus one).
1922 The type of the list elements is put in *ELTYPE, if non-NULL. */
1924 #define NEON_LANE(X) ((X) & 0xf)
1925 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1926 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1929 parse_neon_el_struct_list (char **str, unsigned *pbase,
1930 struct neon_type_el *eltype)
1937 int leading_brace = 0;
1938 enum arm_reg_type rtype = REG_TYPE_NDQ;
1939 const char *const incr_error = _("register stride must be 1 or 2");
1940 const char *const type_error = _("mismatched element/structure types in list");
1941 struct neon_typed_alias firsttype;
1943 if (skip_past_char (&ptr, '{') == SUCCESS)
1948 struct neon_typed_alias atype;
1949 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1953 first_error (_(reg_expected_msgs[rtype]));
1960 if (rtype == REG_TYPE_NQ)
1966 else if (reg_incr == -1)
1968 reg_incr = getreg - base_reg;
1969 if (reg_incr < 1 || reg_incr > 2)
1971 first_error (_(incr_error));
1975 else if (getreg != base_reg + reg_incr * count)
1977 first_error (_(incr_error));
1981 if (! neon_alias_types_same (&atype, &firsttype))
1983 first_error (_(type_error));
1987 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1991 struct neon_typed_alias htype;
1992 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1994 lane = NEON_INTERLEAVE_LANES;
1995 else if (lane != NEON_INTERLEAVE_LANES)
1997 first_error (_(type_error));
2002 else if (reg_incr != 1)
2004 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2008 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2011 first_error (_(reg_expected_msgs[rtype]));
2014 if (! neon_alias_types_same (&htype, &firsttype))
2016 first_error (_(type_error));
2019 count += hireg + dregs - getreg;
2023 /* If we're using Q registers, we can't use [] or [n] syntax. */
2024 if (rtype == REG_TYPE_NQ)
2030 if ((atype.defined & NTA_HASINDEX) != 0)
2034 else if (lane != atype.index)
2036 first_error (_(type_error));
2040 else if (lane == -1)
2041 lane = NEON_INTERLEAVE_LANES;
2042 else if (lane != NEON_INTERLEAVE_LANES)
2044 first_error (_(type_error));
2049 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2051 /* No lane set by [x]. We must be interleaving structures. */
2053 lane = NEON_INTERLEAVE_LANES;
2056 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2057 || (count > 1 && reg_incr == -1))
2059 first_error (_("error parsing element/structure list"));
2063 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2065 first_error (_("expected }"));
2073 *eltype = firsttype.eltype;
2078 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2081 /* Parse an explicit relocation suffix on an expression. This is
2082 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2083 arm_reloc_hsh contains no entries, so this function can only
2084 succeed if there is no () after the word. Returns -1 on error,
2085 BFD_RELOC_UNUSED if there wasn't any suffix. */
2088 parse_reloc (char **str)
2090 struct reloc_entry *r;
2094 return BFD_RELOC_UNUSED;
2099 while (*q && *q != ')' && *q != ',')
2104 if ((r = (struct reloc_entry *)
2105 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2112 /* Directives: register aliases. */
2114 static struct reg_entry *
2115 insert_reg_alias (char *str, unsigned number, int type)
2117 struct reg_entry *new_reg;
2120 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2122 if (new_reg->builtin)
2123 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2125 /* Only warn about a redefinition if it's not defined as the
2127 else if (new_reg->number != number || new_reg->type != type)
2128 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2133 name = xstrdup (str);
2134 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2136 new_reg->name = name;
2137 new_reg->number = number;
2138 new_reg->type = type;
2139 new_reg->builtin = FALSE;
2140 new_reg->neon = NULL;
2142 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2149 insert_neon_reg_alias (char *str, int number, int type,
2150 struct neon_typed_alias *atype)
2152 struct reg_entry *reg = insert_reg_alias (str, number, type);
2156 first_error (_("attempt to redefine typed alias"));
2162 reg->neon = (struct neon_typed_alias *)
2163 xmalloc (sizeof (struct neon_typed_alias));
2164 *reg->neon = *atype;
2168 /* Look for the .req directive. This is of the form:
2170 new_register_name .req existing_register_name
2172 If we find one, or if it looks sufficiently like one that we want to
2173 handle any error here, return TRUE. Otherwise return FALSE. */
2176 create_register_alias (char * newname, char *p)
2178 struct reg_entry *old;
2179 char *oldname, *nbuf;
2182 /* The input scrubber ensures that whitespace after the mnemonic is
2183 collapsed to single spaces. */
2185 if (strncmp (oldname, " .req ", 6) != 0)
2189 if (*oldname == '\0')
2192 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2195 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2199 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2200 the desired alias name, and p points to its end. If not, then
2201 the desired alias name is in the global original_case_string. */
2202 #ifdef TC_CASE_SENSITIVE
2205 newname = original_case_string;
2206 nlen = strlen (newname);
2209 nbuf = (char *) alloca (nlen + 1);
2210 memcpy (nbuf, newname, nlen);
2213 /* Create aliases under the new name as stated; an all-lowercase
2214 version of the new name; and an all-uppercase version of the new
2216 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2218 for (p = nbuf; *p; p++)
2221 if (strncmp (nbuf, newname, nlen))
2223 /* If this attempt to create an additional alias fails, do not bother
2224 trying to create the all-lower case alias. We will fail and issue
2225 a second, duplicate error message. This situation arises when the
2226 programmer does something like:
2229 The second .req creates the "Foo" alias but then fails to create
2230 the artificial FOO alias because it has already been created by the
2232 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2236 for (p = nbuf; *p; p++)
2239 if (strncmp (nbuf, newname, nlen))
2240 insert_reg_alias (nbuf, old->number, old->type);
2246 /* Create a Neon typed/indexed register alias using directives, e.g.:
2251 These typed registers can be used instead of the types specified after the
2252 Neon mnemonic, so long as all operands given have types. Types can also be
2253 specified directly, e.g.:
2254 vadd d0.s32, d1.s32, d2.s32 */
2257 create_neon_reg_alias (char *newname, char *p)
2259 enum arm_reg_type basetype;
2260 struct reg_entry *basereg;
2261 struct reg_entry mybasereg;
2262 struct neon_type ntype;
2263 struct neon_typed_alias typeinfo;
2264 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2267 typeinfo.defined = 0;
2268 typeinfo.eltype.type = NT_invtype;
2269 typeinfo.eltype.size = -1;
2270 typeinfo.index = -1;
2274 if (strncmp (p, " .dn ", 5) == 0)
2275 basetype = REG_TYPE_VFD;
2276 else if (strncmp (p, " .qn ", 5) == 0)
2277 basetype = REG_TYPE_NQ;
2286 basereg = arm_reg_parse_multi (&p);
2288 if (basereg && basereg->type != basetype)
2290 as_bad (_("bad type for register"));
2294 if (basereg == NULL)
2297 /* Try parsing as an integer. */
2298 my_get_expression (&exp, &p, GE_NO_PREFIX);
2299 if (exp.X_op != O_constant)
2301 as_bad (_("expression must be constant"));
2304 basereg = &mybasereg;
2305 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2311 typeinfo = *basereg->neon;
2313 if (parse_neon_type (&ntype, &p) == SUCCESS)
2315 /* We got a type. */
2316 if (typeinfo.defined & NTA_HASTYPE)
2318 as_bad (_("can't redefine the type of a register alias"));
2322 typeinfo.defined |= NTA_HASTYPE;
2323 if (ntype.elems != 1)
2325 as_bad (_("you must specify a single type only"));
2328 typeinfo.eltype = ntype.el[0];
2331 if (skip_past_char (&p, '[') == SUCCESS)
2334 /* We got a scalar index. */
2336 if (typeinfo.defined & NTA_HASINDEX)
2338 as_bad (_("can't redefine the index of a scalar alias"));
2342 my_get_expression (&exp, &p, GE_NO_PREFIX);
2344 if (exp.X_op != O_constant)
2346 as_bad (_("scalar index must be constant"));
2350 typeinfo.defined |= NTA_HASINDEX;
2351 typeinfo.index = exp.X_add_number;
2353 if (skip_past_char (&p, ']') == FAIL)
2355 as_bad (_("expecting ]"));
2360 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2361 the desired alias name, and p points to its end. If not, then
2362 the desired alias name is in the global original_case_string. */
2363 #ifdef TC_CASE_SENSITIVE
2364 namelen = nameend - newname;
2366 newname = original_case_string;
2367 namelen = strlen (newname);
2370 namebuf = (char *) alloca (namelen + 1);
2371 strncpy (namebuf, newname, namelen);
2372 namebuf[namelen] = '\0';
2374 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2375 typeinfo.defined != 0 ? &typeinfo : NULL);
2377 /* Insert name in all uppercase. */
2378 for (p = namebuf; *p; p++)
2381 if (strncmp (namebuf, newname, namelen))
2382 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2383 typeinfo.defined != 0 ? &typeinfo : NULL);
2385 /* Insert name in all lowercase. */
2386 for (p = namebuf; *p; p++)
2389 if (strncmp (namebuf, newname, namelen))
2390 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2391 typeinfo.defined != 0 ? &typeinfo : NULL);
2396 /* Should never be called, as .req goes between the alias and the
2397 register name, not at the beginning of the line. */
2400 s_req (int a ATTRIBUTE_UNUSED)
2402 as_bad (_("invalid syntax for .req directive"));
2406 s_dn (int a ATTRIBUTE_UNUSED)
2408 as_bad (_("invalid syntax for .dn directive"));
2412 s_qn (int a ATTRIBUTE_UNUSED)
2414 as_bad (_("invalid syntax for .qn directive"));
2417 /* The .unreq directive deletes an alias which was previously defined
2418 by .req. For example:
2424 s_unreq (int a ATTRIBUTE_UNUSED)
2429 name = input_line_pointer;
2431 while (*input_line_pointer != 0
2432 && *input_line_pointer != ' '
2433 && *input_line_pointer != '\n')
2434 ++input_line_pointer;
2436 saved_char = *input_line_pointer;
2437 *input_line_pointer = 0;
2440 as_bad (_("invalid syntax for .unreq directive"));
2443 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2447 as_bad (_("unknown register alias '%s'"), name);
2448 else if (reg->builtin)
2449 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2456 hash_delete (arm_reg_hsh, name, FALSE);
2457 free ((char *) reg->name);
2462 /* Also locate the all upper case and all lower case versions.
2463 Do not complain if we cannot find one or the other as it
2464 was probably deleted above. */
2466 nbuf = strdup (name);
2467 for (p = nbuf; *p; p++)
2469 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2472 hash_delete (arm_reg_hsh, nbuf, FALSE);
2473 free ((char *) reg->name);
2479 for (p = nbuf; *p; p++)
2481 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2484 hash_delete (arm_reg_hsh, nbuf, FALSE);
2485 free ((char *) reg->name);
2495 *input_line_pointer = saved_char;
2496 demand_empty_rest_of_line ();
2499 /* Directives: Instruction set selection. */
2502 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2503 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2504 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2505 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2507 /* Create a new mapping symbol for the transition to STATE. */
2510 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2513 const char * symname;
2520 type = BSF_NO_FLAGS;
2524 type = BSF_NO_FLAGS;
2528 type = BSF_NO_FLAGS;
2534 symbolP = symbol_new (symname, now_seg, value, frag);
2535 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2540 THUMB_SET_FUNC (symbolP, 0);
2541 ARM_SET_THUMB (symbolP, 0);
2542 ARM_SET_INTERWORK (symbolP, support_interwork);
2546 THUMB_SET_FUNC (symbolP, 1);
2547 ARM_SET_THUMB (symbolP, 1);
2548 ARM_SET_INTERWORK (symbolP, support_interwork);
2556 /* Save the mapping symbols for future reference. Also check that
2557 we do not place two mapping symbols at the same offset within a
2558 frag. We'll handle overlap between frags in
2559 check_mapping_symbols.
2561 If .fill or other data filling directive generates zero sized data,
2562 the mapping symbol for the following code will have the same value
2563 as the one generated for the data filling directive. In this case,
2564 we replace the old symbol with the new one at the same address. */
2567 if (frag->tc_frag_data.first_map != NULL)
2569 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2570 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2572 frag->tc_frag_data.first_map = symbolP;
2574 if (frag->tc_frag_data.last_map != NULL)
2576 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2577 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2578 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2580 frag->tc_frag_data.last_map = symbolP;
2583 /* We must sometimes convert a region marked as code to data during
2584 code alignment, if an odd number of bytes have to be padded. The
2585 code mapping symbol is pushed to an aligned address. */
2588 insert_data_mapping_symbol (enum mstate state,
2589 valueT value, fragS *frag, offsetT bytes)
2591 /* If there was already a mapping symbol, remove it. */
2592 if (frag->tc_frag_data.last_map != NULL
2593 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2595 symbolS *symp = frag->tc_frag_data.last_map;
2599 know (frag->tc_frag_data.first_map == symp);
2600 frag->tc_frag_data.first_map = NULL;
2602 frag->tc_frag_data.last_map = NULL;
2603 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2606 make_mapping_symbol (MAP_DATA, value, frag);
2607 make_mapping_symbol (state, value + bytes, frag);
2610 static void mapping_state_2 (enum mstate state, int max_chars);
2612 /* Set the mapping state to STATE. Only call this when about to
2613 emit some STATE bytes to the file. */
2616 mapping_state (enum mstate state)
2618 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2620 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2622 if (mapstate == state)
2623 /* The mapping symbol has already been emitted.
2624 There is nothing else to do. */
2627 if (state == MAP_ARM || state == MAP_THUMB)
2629 All ARM instructions require 4-byte alignment.
2630 (Almost) all Thumb instructions require 2-byte alignment.
2632 When emitting instructions into any section, mark the section
2635 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2636 but themselves require 2-byte alignment; this applies to some
2637 PC- relative forms. However, these cases will invovle implicit
2638 literal pool generation or an explicit .align >=2, both of
2639 which will cause the section to me marked with sufficient
2640 alignment. Thus, we don't handle those cases here. */
2641 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2643 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2644 /* This case will be evaluated later in the next else. */
2646 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2647 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2649 /* Only add the symbol if the offset is > 0:
2650 if we're at the first frag, check it's size > 0;
2651 if we're not at the first frag, then for sure
2652 the offset is > 0. */
2653 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2654 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2657 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2660 mapping_state_2 (state, 0);
2664 /* Same as mapping_state, but MAX_CHARS bytes have already been
2665 allocated. Put the mapping symbol that far back. */
2668 mapping_state_2 (enum mstate state, int max_chars)
2670 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2672 if (!SEG_NORMAL (now_seg))
2675 if (mapstate == state)
2676 /* The mapping symbol has already been emitted.
2677 There is nothing else to do. */
2680 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2681 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2684 #define mapping_state(x) ((void)0)
2685 #define mapping_state_2(x, y) ((void)0)
2688 /* Find the real, Thumb encoded start of a Thumb function. */
2692 find_real_start (symbolS * symbolP)
2695 const char * name = S_GET_NAME (symbolP);
2696 symbolS * new_target;
2698 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2699 #define STUB_NAME ".real_start_of"
2704 /* The compiler may generate BL instructions to local labels because
2705 it needs to perform a branch to a far away location. These labels
2706 do not have a corresponding ".real_start_of" label. We check
2707 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2708 the ".real_start_of" convention for nonlocal branches. */
2709 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2712 real_start = ACONCAT ((STUB_NAME, name, NULL));
2713 new_target = symbol_find (real_start);
2715 if (new_target == NULL)
2717 as_warn (_("Failed to find real start of function: %s\n"), name);
2718 new_target = symbolP;
2726 opcode_select (int width)
2733 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2734 as_bad (_("selected processor does not support THUMB opcodes"));
2737 /* No need to force the alignment, since we will have been
2738 coming from ARM mode, which is word-aligned. */
2739 record_alignment (now_seg, 1);
2746 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2747 as_bad (_("selected processor does not support ARM opcodes"));
2752 frag_align (2, 0, 0);
2754 record_alignment (now_seg, 1);
2759 as_bad (_("invalid instruction size selected (%d)"), width);
2764 s_arm (int ignore ATTRIBUTE_UNUSED)
2767 demand_empty_rest_of_line ();
2771 s_thumb (int ignore ATTRIBUTE_UNUSED)
2774 demand_empty_rest_of_line ();
2778 s_code (int unused ATTRIBUTE_UNUSED)
2782 temp = get_absolute_expression ();
2787 opcode_select (temp);
2791 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2796 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2798 /* If we are not already in thumb mode go into it, EVEN if
2799 the target processor does not support thumb instructions.
2800 This is used by gcc/config/arm/lib1funcs.asm for example
2801 to compile interworking support functions even if the
2802 target processor should not support interworking. */
2806 record_alignment (now_seg, 1);
2809 demand_empty_rest_of_line ();
2813 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2817 /* The following label is the name/address of the start of a Thumb function.
2818 We need to know this for the interworking support. */
2819 label_is_thumb_function_name = TRUE;
2822 /* Perform a .set directive, but also mark the alias as
2823 being a thumb function. */
2826 s_thumb_set (int equiv)
2828 /* XXX the following is a duplicate of the code for s_set() in read.c
2829 We cannot just call that code as we need to get at the symbol that
2836 /* Especial apologies for the random logic:
2837 This just grew, and could be parsed much more simply!
2839 name = input_line_pointer;
2840 delim = get_symbol_end ();
2841 end_name = input_line_pointer;
2844 if (*input_line_pointer != ',')
2847 as_bad (_("expected comma after name \"%s\""), name);
2849 ignore_rest_of_line ();
2853 input_line_pointer++;
2856 if (name[0] == '.' && name[1] == '\0')
2858 /* XXX - this should not happen to .thumb_set. */
2862 if ((symbolP = symbol_find (name)) == NULL
2863 && (symbolP = md_undefined_symbol (name)) == NULL)
2866 /* When doing symbol listings, play games with dummy fragments living
2867 outside the normal fragment chain to record the file and line info
2869 if (listing & LISTING_SYMBOLS)
2871 extern struct list_info_struct * listing_tail;
2872 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2874 memset (dummy_frag, 0, sizeof (fragS));
2875 dummy_frag->fr_type = rs_fill;
2876 dummy_frag->line = listing_tail;
2877 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2878 dummy_frag->fr_symbol = symbolP;
2882 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2885 /* "set" symbols are local unless otherwise specified. */
2886 SF_SET_LOCAL (symbolP);
2887 #endif /* OBJ_COFF */
2888 } /* Make a new symbol. */
2890 symbol_table_insert (symbolP);
2895 && S_IS_DEFINED (symbolP)
2896 && S_GET_SEGMENT (symbolP) != reg_section)
2897 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2899 pseudo_set (symbolP);
2901 demand_empty_rest_of_line ();
2903 /* XXX Now we come to the Thumb specific bit of code. */
2905 THUMB_SET_FUNC (symbolP, 1);
2906 ARM_SET_THUMB (symbolP, 1);
2907 #if defined OBJ_ELF || defined OBJ_COFF
2908 ARM_SET_INTERWORK (symbolP, support_interwork);
2912 /* Directives: Mode selection. */
2914 /* .syntax [unified|divided] - choose the new unified syntax
2915 (same for Arm and Thumb encoding, modulo slight differences in what
2916 can be represented) or the old divergent syntax for each mode. */
2918 s_syntax (int unused ATTRIBUTE_UNUSED)
2922 name = input_line_pointer;
2923 delim = get_symbol_end ();
2925 if (!strcasecmp (name, "unified"))
2926 unified_syntax = TRUE;
2927 else if (!strcasecmp (name, "divided"))
2928 unified_syntax = FALSE;
2931 as_bad (_("unrecognized syntax mode \"%s\""), name);
2934 *input_line_pointer = delim;
2935 demand_empty_rest_of_line ();
2938 /* Directives: sectioning and alignment. */
2940 /* Same as s_align_ptwo but align 0 => align 2. */
2943 s_align (int unused ATTRIBUTE_UNUSED)
2948 long max_alignment = 15;
2950 temp = get_absolute_expression ();
2951 if (temp > max_alignment)
2952 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2955 as_bad (_("alignment negative. 0 assumed."));
2959 if (*input_line_pointer == ',')
2961 input_line_pointer++;
2962 temp_fill = get_absolute_expression ();
2974 /* Only make a frag if we HAVE to. */
2975 if (temp && !need_pass_2)
2977 if (!fill_p && subseg_text_p (now_seg))
2978 frag_align_code (temp, 0);
2980 frag_align (temp, (int) temp_fill, 0);
2982 demand_empty_rest_of_line ();
2984 record_alignment (now_seg, temp);
2988 s_bss (int ignore ATTRIBUTE_UNUSED)
2990 /* We don't support putting frags in the BSS segment, we fake it by
2991 marking in_bss, then looking at s_skip for clues. */
2992 subseg_set (bss_section, 0);
2993 demand_empty_rest_of_line ();
2995 #ifdef md_elf_section_change_hook
2996 md_elf_section_change_hook ();
3001 s_even (int ignore ATTRIBUTE_UNUSED)
3003 /* Never make frag if expect extra pass. */
3005 frag_align (1, 0, 0);
3007 record_alignment (now_seg, 1);
3009 demand_empty_rest_of_line ();
3012 /* Directives: Literal pools. */
3014 static literal_pool *
3015 find_literal_pool (void)
3017 literal_pool * pool;
3019 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3021 if (pool->section == now_seg
3022 && pool->sub_section == now_subseg)
3029 static literal_pool *
3030 find_or_make_literal_pool (void)
3032 /* Next literal pool ID number. */
3033 static unsigned int latest_pool_num = 1;
3034 literal_pool * pool;
3036 pool = find_literal_pool ();
3040 /* Create a new pool. */
3041 pool = (literal_pool *) xmalloc (sizeof (* pool));
3045 pool->next_free_entry = 0;
3046 pool->section = now_seg;
3047 pool->sub_section = now_subseg;
3048 pool->next = list_of_pools;
3049 pool->symbol = NULL;
3051 /* Add it to the list. */
3052 list_of_pools = pool;
3055 /* New pools, and emptied pools, will have a NULL symbol. */
3056 if (pool->symbol == NULL)
3058 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3059 (valueT) 0, &zero_address_frag);
3060 pool->id = latest_pool_num ++;
3067 /* Add the literal in the global 'inst'
3068 structure to the relevant literal pool. */
3071 add_to_lit_pool (void)
3073 literal_pool * pool;
3076 pool = find_or_make_literal_pool ();
3078 /* Check if this literal value is already in the pool. */
3079 for (entry = 0; entry < pool->next_free_entry; entry ++)
3081 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3082 && (inst.reloc.exp.X_op == O_constant)
3083 && (pool->literals[entry].X_add_number
3084 == inst.reloc.exp.X_add_number)
3085 && (pool->literals[entry].X_unsigned
3086 == inst.reloc.exp.X_unsigned))
3089 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3090 && (inst.reloc.exp.X_op == O_symbol)
3091 && (pool->literals[entry].X_add_number
3092 == inst.reloc.exp.X_add_number)
3093 && (pool->literals[entry].X_add_symbol
3094 == inst.reloc.exp.X_add_symbol)
3095 && (pool->literals[entry].X_op_symbol
3096 == inst.reloc.exp.X_op_symbol))
3100 /* Do we need to create a new entry? */
3101 if (entry == pool->next_free_entry)
3103 if (entry >= MAX_LITERAL_POOL_SIZE)
3105 inst.error = _("literal pool overflow");
3109 pool->literals[entry] = inst.reloc.exp;
3111 /* PR ld/12974: Record the location of the first source line to reference
3112 this entry in the literal pool. If it turns out during linking that the
3113 symbol does not exist we will be able to give an accurate line number for
3114 the (first use of the) missing reference. */
3115 if (debug_type == DEBUG_DWARF2)
3116 dwarf2_where (pool->locs + entry);
3118 pool->next_free_entry += 1;
3121 inst.reloc.exp.X_op = O_symbol;
3122 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3123 inst.reloc.exp.X_add_symbol = pool->symbol;
3128 /* Can't use symbol_new here, so have to create a symbol and then at
3129 a later date assign it a value. Thats what these functions do. */
3132 symbol_locate (symbolS * symbolP,
3133 const char * name, /* It is copied, the caller can modify. */
3134 segT segment, /* Segment identifier (SEG_<something>). */
3135 valueT valu, /* Symbol value. */
3136 fragS * frag) /* Associated fragment. */
3138 unsigned int name_length;
3139 char * preserved_copy_of_name;
3141 name_length = strlen (name) + 1; /* +1 for \0. */
3142 obstack_grow (¬es, name, name_length);
3143 preserved_copy_of_name = (char *) obstack_finish (¬es);
3145 #ifdef tc_canonicalize_symbol_name
3146 preserved_copy_of_name =
3147 tc_canonicalize_symbol_name (preserved_copy_of_name);
3150 S_SET_NAME (symbolP, preserved_copy_of_name);
3152 S_SET_SEGMENT (symbolP, segment);
3153 S_SET_VALUE (symbolP, valu);
3154 symbol_clear_list_pointers (symbolP);
3156 symbol_set_frag (symbolP, frag);
3158 /* Link to end of symbol chain. */
3160 extern int symbol_table_frozen;
3162 if (symbol_table_frozen)
3166 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3168 obj_symbol_new_hook (symbolP);
3170 #ifdef tc_symbol_new_hook
3171 tc_symbol_new_hook (symbolP);
3175 verify_symbol_chain (symbol_rootP, symbol_lastP);
3176 #endif /* DEBUG_SYMS */
3181 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3184 literal_pool * pool;
3187 pool = find_literal_pool ();
3189 || pool->symbol == NULL
3190 || pool->next_free_entry == 0)
3193 mapping_state (MAP_DATA);
3195 /* Align pool as you have word accesses.
3196 Only make a frag if we have to. */
3198 frag_align (2, 0, 0);
3200 record_alignment (now_seg, 2);
3202 sprintf (sym_name, "$$lit_\002%x", pool->id);
3204 symbol_locate (pool->symbol, sym_name, now_seg,
3205 (valueT) frag_now_fix (), frag_now);
3206 symbol_table_insert (pool->symbol);
3208 ARM_SET_THUMB (pool->symbol, thumb_mode);
3210 #if defined OBJ_COFF || defined OBJ_ELF
3211 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3214 for (entry = 0; entry < pool->next_free_entry; entry ++)
3217 if (debug_type == DEBUG_DWARF2)
3218 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3220 /* First output the expression in the instruction to the pool. */
3221 emit_expr (&(pool->literals[entry]), 4); /* .word */
3224 /* Mark the pool as empty. */
3225 pool->next_free_entry = 0;
3226 pool->symbol = NULL;
3230 /* Forward declarations for functions below, in the MD interface
3232 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3233 static valueT create_unwind_entry (int);
3234 static void start_unwind_section (const segT, int);
3235 static void add_unwind_opcode (valueT, int);
3236 static void flush_pending_unwind (void);
3238 /* Directives: Data. */
3241 s_arm_elf_cons (int nbytes)
3245 #ifdef md_flush_pending_output
3246 md_flush_pending_output ();
3249 if (is_it_end_of_statement ())
3251 demand_empty_rest_of_line ();
3255 #ifdef md_cons_align
3256 md_cons_align (nbytes);
3259 mapping_state (MAP_DATA);
3263 char *base = input_line_pointer;
3267 if (exp.X_op != O_symbol)
3268 emit_expr (&exp, (unsigned int) nbytes);
3271 char *before_reloc = input_line_pointer;
3272 reloc = parse_reloc (&input_line_pointer);
3275 as_bad (_("unrecognized relocation suffix"));
3276 ignore_rest_of_line ();
3279 else if (reloc == BFD_RELOC_UNUSED)
3280 emit_expr (&exp, (unsigned int) nbytes);
3283 reloc_howto_type *howto = (reloc_howto_type *)
3284 bfd_reloc_type_lookup (stdoutput,
3285 (bfd_reloc_code_real_type) reloc);
3286 int size = bfd_get_reloc_size (howto);
3288 if (reloc == BFD_RELOC_ARM_PLT32)
3290 as_bad (_("(plt) is only valid on branch targets"));
3291 reloc = BFD_RELOC_UNUSED;
3296 as_bad (_("%s relocations do not fit in %d bytes"),
3297 howto->name, nbytes);
3300 /* We've parsed an expression stopping at O_symbol.
3301 But there may be more expression left now that we
3302 have parsed the relocation marker. Parse it again.
3303 XXX Surely there is a cleaner way to do this. */
3304 char *p = input_line_pointer;
3306 char *save_buf = (char *) alloca (input_line_pointer - base);
3307 memcpy (save_buf, base, input_line_pointer - base);
3308 memmove (base + (input_line_pointer - before_reloc),
3309 base, before_reloc - base);
3311 input_line_pointer = base + (input_line_pointer-before_reloc);
3313 memcpy (base, save_buf, p - base);
3315 offset = nbytes - size;
3316 p = frag_more ((int) nbytes);
3317 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3318 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3323 while (*input_line_pointer++ == ',');
3325 /* Put terminator back into stream. */
3326 input_line_pointer --;
3327 demand_empty_rest_of_line ();
3330 /* Emit an expression containing a 32-bit thumb instruction.
3331 Implementation based on put_thumb32_insn. */
3334 emit_thumb32_expr (expressionS * exp)
3336 expressionS exp_high = *exp;
3338 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3339 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3340 exp->X_add_number &= 0xffff;
3341 emit_expr (exp, (unsigned int) THUMB_SIZE);
3344 /* Guess the instruction size based on the opcode. */
3347 thumb_insn_size (int opcode)
3349 if ((unsigned int) opcode < 0xe800u)
3351 else if ((unsigned int) opcode >= 0xe8000000u)
3358 emit_insn (expressionS *exp, int nbytes)
3362 if (exp->X_op == O_constant)
3367 size = thumb_insn_size (exp->X_add_number);
3371 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3373 as_bad (_(".inst.n operand too big. "\
3374 "Use .inst.w instead"));
3379 if (now_it.state == AUTOMATIC_IT_BLOCK)
3380 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3382 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3384 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3385 emit_thumb32_expr (exp);
3387 emit_expr (exp, (unsigned int) size);
3389 it_fsm_post_encode ();
3393 as_bad (_("cannot determine Thumb instruction size. " \
3394 "Use .inst.n/.inst.w instead"));
3397 as_bad (_("constant expression required"));
3402 /* Like s_arm_elf_cons but do not use md_cons_align and
3403 set the mapping state to MAP_ARM/MAP_THUMB. */
3406 s_arm_elf_inst (int nbytes)
3408 if (is_it_end_of_statement ())
3410 demand_empty_rest_of_line ();
3414 /* Calling mapping_state () here will not change ARM/THUMB,
3415 but will ensure not to be in DATA state. */
3418 mapping_state (MAP_THUMB);
3423 as_bad (_("width suffixes are invalid in ARM mode"));
3424 ignore_rest_of_line ();
3430 mapping_state (MAP_ARM);
3439 if (! emit_insn (& exp, nbytes))
3441 ignore_rest_of_line ();
3445 while (*input_line_pointer++ == ',');
3447 /* Put terminator back into stream. */
3448 input_line_pointer --;
3449 demand_empty_rest_of_line ();
3452 /* Parse a .rel31 directive. */
3455 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3462 if (*input_line_pointer == '1')
3463 highbit = 0x80000000;
3464 else if (*input_line_pointer != '0')
3465 as_bad (_("expected 0 or 1"));
3467 input_line_pointer++;
3468 if (*input_line_pointer != ',')
3469 as_bad (_("missing comma"));
3470 input_line_pointer++;
3472 #ifdef md_flush_pending_output
3473 md_flush_pending_output ();
3476 #ifdef md_cons_align
3480 mapping_state (MAP_DATA);
3485 md_number_to_chars (p, highbit, 4);
3486 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3487 BFD_RELOC_ARM_PREL31);
3489 demand_empty_rest_of_line ();
3492 /* Directives: AEABI stack-unwind tables. */
3494 /* Parse an unwind_fnstart directive. Simply records the current location. */
3497 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3499 demand_empty_rest_of_line ();
3500 if (unwind.proc_start)
3502 as_bad (_("duplicate .fnstart directive"));
3506 /* Mark the start of the function. */
3507 unwind.proc_start = expr_build_dot ();
3509 /* Reset the rest of the unwind info. */
3510 unwind.opcode_count = 0;
3511 unwind.table_entry = NULL;
3512 unwind.personality_routine = NULL;
3513 unwind.personality_index = -1;
3514 unwind.frame_size = 0;
3515 unwind.fp_offset = 0;
3516 unwind.fp_reg = REG_SP;
3518 unwind.sp_restored = 0;
3522 /* Parse a handlerdata directive. Creates the exception handling table entry
3523 for the function. */
3526 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3528 demand_empty_rest_of_line ();
3529 if (!unwind.proc_start)
3530 as_bad (MISSING_FNSTART);
3532 if (unwind.table_entry)
3533 as_bad (_("duplicate .handlerdata directive"));
3535 create_unwind_entry (1);
3538 /* Parse an unwind_fnend directive. Generates the index table entry. */
3541 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3546 unsigned int marked_pr_dependency;
3548 demand_empty_rest_of_line ();
3550 if (!unwind.proc_start)
3552 as_bad (_(".fnend directive without .fnstart"));
3556 /* Add eh table entry. */
3557 if (unwind.table_entry == NULL)
3558 val = create_unwind_entry (0);
3562 /* Add index table entry. This is two words. */
3563 start_unwind_section (unwind.saved_seg, 1);
3564 frag_align (2, 0, 0);
3565 record_alignment (now_seg, 2);
3567 ptr = frag_more (8);
3569 where = frag_now_fix () - 8;
3571 /* Self relative offset of the function start. */
3572 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3573 BFD_RELOC_ARM_PREL31);
3575 /* Indicate dependency on EHABI-defined personality routines to the
3576 linker, if it hasn't been done already. */
3577 marked_pr_dependency
3578 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3579 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3580 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3582 static const char *const name[] =
3584 "__aeabi_unwind_cpp_pr0",
3585 "__aeabi_unwind_cpp_pr1",
3586 "__aeabi_unwind_cpp_pr2"
3588 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3589 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3590 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3591 |= 1 << unwind.personality_index;
3595 /* Inline exception table entry. */
3596 md_number_to_chars (ptr + 4, val, 4);
3598 /* Self relative offset of the table entry. */
3599 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3600 BFD_RELOC_ARM_PREL31);
3602 /* Restore the original section. */
3603 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3605 unwind.proc_start = NULL;
3609 /* Parse an unwind_cantunwind directive. */
3612 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3614 demand_empty_rest_of_line ();
3615 if (!unwind.proc_start)
3616 as_bad (MISSING_FNSTART);
3618 if (unwind.personality_routine || unwind.personality_index != -1)
3619 as_bad (_("personality routine specified for cantunwind frame"));
3621 unwind.personality_index = -2;
3625 /* Parse a personalityindex directive. */
3628 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3632 if (!unwind.proc_start)
3633 as_bad (MISSING_FNSTART);
3635 if (unwind.personality_routine || unwind.personality_index != -1)
3636 as_bad (_("duplicate .personalityindex directive"));
3640 if (exp.X_op != O_constant
3641 || exp.X_add_number < 0 || exp.X_add_number > 15)
3643 as_bad (_("bad personality routine number"));
3644 ignore_rest_of_line ();
3648 unwind.personality_index = exp.X_add_number;
3650 demand_empty_rest_of_line ();
3654 /* Parse a personality directive. */
3657 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3661 if (!unwind.proc_start)
3662 as_bad (MISSING_FNSTART);
3664 if (unwind.personality_routine || unwind.personality_index != -1)
3665 as_bad (_("duplicate .personality directive"));
3667 name = input_line_pointer;
3668 c = get_symbol_end ();
3669 p = input_line_pointer;
3670 unwind.personality_routine = symbol_find_or_make (name);
3672 demand_empty_rest_of_line ();
3676 /* Parse a directive saving core registers. */
3679 s_arm_unwind_save_core (void)
3685 range = parse_reg_list (&input_line_pointer);
3688 as_bad (_("expected register list"));
3689 ignore_rest_of_line ();
3693 demand_empty_rest_of_line ();
3695 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3696 into .unwind_save {..., sp...}. We aren't bothered about the value of
3697 ip because it is clobbered by calls. */
3698 if (unwind.sp_restored && unwind.fp_reg == 12
3699 && (range & 0x3000) == 0x1000)
3701 unwind.opcode_count--;
3702 unwind.sp_restored = 0;
3703 range = (range | 0x2000) & ~0x1000;
3704 unwind.pending_offset = 0;
3710 /* See if we can use the short opcodes. These pop a block of up to 8
3711 registers starting with r4, plus maybe r14. */
3712 for (n = 0; n < 8; n++)
3714 /* Break at the first non-saved register. */
3715 if ((range & (1 << (n + 4))) == 0)
3718 /* See if there are any other bits set. */
3719 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3721 /* Use the long form. */
3722 op = 0x8000 | ((range >> 4) & 0xfff);
3723 add_unwind_opcode (op, 2);
3727 /* Use the short form. */
3729 op = 0xa8; /* Pop r14. */
3731 op = 0xa0; /* Do not pop r14. */
3733 add_unwind_opcode (op, 1);
3740 op = 0xb100 | (range & 0xf);
3741 add_unwind_opcode (op, 2);
3744 /* Record the number of bytes pushed. */
3745 for (n = 0; n < 16; n++)
3747 if (range & (1 << n))
3748 unwind.frame_size += 4;
3753 /* Parse a directive saving FPA registers. */
3756 s_arm_unwind_save_fpa (int reg)
3762 /* Get Number of registers to transfer. */
3763 if (skip_past_comma (&input_line_pointer) != FAIL)
3766 exp.X_op = O_illegal;
3768 if (exp.X_op != O_constant)
3770 as_bad (_("expected , <constant>"));
3771 ignore_rest_of_line ();
3775 num_regs = exp.X_add_number;
3777 if (num_regs < 1 || num_regs > 4)
3779 as_bad (_("number of registers must be in the range [1:4]"));
3780 ignore_rest_of_line ();
3784 demand_empty_rest_of_line ();
3789 op = 0xb4 | (num_regs - 1);
3790 add_unwind_opcode (op, 1);
3795 op = 0xc800 | (reg << 4) | (num_regs - 1);
3796 add_unwind_opcode (op, 2);
3798 unwind.frame_size += num_regs * 12;
3802 /* Parse a directive saving VFP registers for ARMv6 and above. */
3805 s_arm_unwind_save_vfp_armv6 (void)
3810 int num_vfpv3_regs = 0;
3811 int num_regs_below_16;
3813 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3816 as_bad (_("expected register list"));
3817 ignore_rest_of_line ();
3821 demand_empty_rest_of_line ();
3823 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3824 than FSTMX/FLDMX-style ones). */
3826 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3828 num_vfpv3_regs = count;
3829 else if (start + count > 16)
3830 num_vfpv3_regs = start + count - 16;
3832 if (num_vfpv3_regs > 0)
3834 int start_offset = start > 16 ? start - 16 : 0;
3835 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3836 add_unwind_opcode (op, 2);
3839 /* Generate opcode for registers numbered in the range 0 .. 15. */
3840 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3841 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3842 if (num_regs_below_16 > 0)
3844 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3845 add_unwind_opcode (op, 2);
3848 unwind.frame_size += count * 8;
3852 /* Parse a directive saving VFP registers for pre-ARMv6. */
3855 s_arm_unwind_save_vfp (void)
3861 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3864 as_bad (_("expected register list"));
3865 ignore_rest_of_line ();
3869 demand_empty_rest_of_line ();
3874 op = 0xb8 | (count - 1);
3875 add_unwind_opcode (op, 1);
3880 op = 0xb300 | (reg << 4) | (count - 1);
3881 add_unwind_opcode (op, 2);
3883 unwind.frame_size += count * 8 + 4;
3887 /* Parse a directive saving iWMMXt data registers. */
3890 s_arm_unwind_save_mmxwr (void)
3898 if (*input_line_pointer == '{')
3899 input_line_pointer++;
3903 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3907 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3912 as_tsktsk (_("register list not in ascending order"));
3915 if (*input_line_pointer == '-')
3917 input_line_pointer++;
3918 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3921 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3924 else if (reg >= hi_reg)
3926 as_bad (_("bad register range"));
3929 for (; reg < hi_reg; reg++)
3933 while (skip_past_comma (&input_line_pointer) != FAIL);
3935 if (*input_line_pointer == '}')
3936 input_line_pointer++;
3938 demand_empty_rest_of_line ();
3940 /* Generate any deferred opcodes because we're going to be looking at
3942 flush_pending_unwind ();
3944 for (i = 0; i < 16; i++)
3946 if (mask & (1 << i))
3947 unwind.frame_size += 8;
3950 /* Attempt to combine with a previous opcode. We do this because gcc
3951 likes to output separate unwind directives for a single block of
3953 if (unwind.opcode_count > 0)
3955 i = unwind.opcodes[unwind.opcode_count - 1];
3956 if ((i & 0xf8) == 0xc0)
3959 /* Only merge if the blocks are contiguous. */
3962 if ((mask & 0xfe00) == (1 << 9))
3964 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3965 unwind.opcode_count--;
3968 else if (i == 6 && unwind.opcode_count >= 2)
3970 i = unwind.opcodes[unwind.opcode_count - 2];
3974 op = 0xffff << (reg - 1);
3976 && ((mask & op) == (1u << (reg - 1))))
3978 op = (1 << (reg + i + 1)) - 1;
3979 op &= ~((1 << reg) - 1);
3981 unwind.opcode_count -= 2;
3988 /* We want to generate opcodes in the order the registers have been
3989 saved, ie. descending order. */
3990 for (reg = 15; reg >= -1; reg--)
3992 /* Save registers in blocks. */
3994 || !(mask & (1 << reg)))
3996 /* We found an unsaved reg. Generate opcodes to save the
4003 op = 0xc0 | (hi_reg - 10);
4004 add_unwind_opcode (op, 1);
4009 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4010 add_unwind_opcode (op, 2);
4019 ignore_rest_of_line ();
4023 s_arm_unwind_save_mmxwcg (void)
4030 if (*input_line_pointer == '{')
4031 input_line_pointer++;
4035 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4039 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4045 as_tsktsk (_("register list not in ascending order"));
4048 if (*input_line_pointer == '-')
4050 input_line_pointer++;
4051 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4054 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4057 else if (reg >= hi_reg)
4059 as_bad (_("bad register range"));
4062 for (; reg < hi_reg; reg++)
4066 while (skip_past_comma (&input_line_pointer) != FAIL);
4068 if (*input_line_pointer == '}')
4069 input_line_pointer++;
4071 demand_empty_rest_of_line ();
4073 /* Generate any deferred opcodes because we're going to be looking at
4075 flush_pending_unwind ();
4077 for (reg = 0; reg < 16; reg++)
4079 if (mask & (1 << reg))
4080 unwind.frame_size += 4;
4083 add_unwind_opcode (op, 2);
4086 ignore_rest_of_line ();
4090 /* Parse an unwind_save directive.
4091 If the argument is non-zero, this is a .vsave directive. */
4094 s_arm_unwind_save (int arch_v6)
4097 struct reg_entry *reg;
4098 bfd_boolean had_brace = FALSE;
4100 if (!unwind.proc_start)
4101 as_bad (MISSING_FNSTART);
4103 /* Figure out what sort of save we have. */
4104 peek = input_line_pointer;
4112 reg = arm_reg_parse_multi (&peek);
4116 as_bad (_("register expected"));
4117 ignore_rest_of_line ();
4126 as_bad (_("FPA .unwind_save does not take a register list"));
4127 ignore_rest_of_line ();
4130 input_line_pointer = peek;
4131 s_arm_unwind_save_fpa (reg->number);
4134 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4137 s_arm_unwind_save_vfp_armv6 ();
4139 s_arm_unwind_save_vfp ();
4141 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4142 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4145 as_bad (_(".unwind_save does not support this kind of register"));
4146 ignore_rest_of_line ();
4151 /* Parse an unwind_movsp directive. */
4154 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4160 if (!unwind.proc_start)
4161 as_bad (MISSING_FNSTART);
4163 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4166 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4167 ignore_rest_of_line ();
4171 /* Optional constant. */
4172 if (skip_past_comma (&input_line_pointer) != FAIL)
4174 if (immediate_for_directive (&offset) == FAIL)
4180 demand_empty_rest_of_line ();
4182 if (reg == REG_SP || reg == REG_PC)
4184 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4188 if (unwind.fp_reg != REG_SP)
4189 as_bad (_("unexpected .unwind_movsp directive"));
4191 /* Generate opcode to restore the value. */
4193 add_unwind_opcode (op, 1);
4195 /* Record the information for later. */
4196 unwind.fp_reg = reg;
4197 unwind.fp_offset = unwind.frame_size - offset;
4198 unwind.sp_restored = 1;
4201 /* Parse an unwind_pad directive. */
4204 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4208 if (!unwind.proc_start)
4209 as_bad (MISSING_FNSTART);
4211 if (immediate_for_directive (&offset) == FAIL)
4216 as_bad (_("stack increment must be multiple of 4"));
4217 ignore_rest_of_line ();
4221 /* Don't generate any opcodes, just record the details for later. */
4222 unwind.frame_size += offset;
4223 unwind.pending_offset += offset;
4225 demand_empty_rest_of_line ();
4228 /* Parse an unwind_setfp directive. */
4231 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4237 if (!unwind.proc_start)
4238 as_bad (MISSING_FNSTART);
4240 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4241 if (skip_past_comma (&input_line_pointer) == FAIL)
4244 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4246 if (fp_reg == FAIL || sp_reg == FAIL)
4248 as_bad (_("expected <reg>, <reg>"));
4249 ignore_rest_of_line ();
4253 /* Optional constant. */
4254 if (skip_past_comma (&input_line_pointer) != FAIL)
4256 if (immediate_for_directive (&offset) == FAIL)
4262 demand_empty_rest_of_line ();
4264 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4266 as_bad (_("register must be either sp or set by a previous"
4267 "unwind_movsp directive"));
4271 /* Don't generate any opcodes, just record the information for later. */
4272 unwind.fp_reg = fp_reg;
4274 if (sp_reg == REG_SP)
4275 unwind.fp_offset = unwind.frame_size - offset;
4277 unwind.fp_offset -= offset;
4280 /* Parse an unwind_raw directive. */
4283 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4286 /* This is an arbitrary limit. */
4287 unsigned char op[16];
4290 if (!unwind.proc_start)
4291 as_bad (MISSING_FNSTART);
4294 if (exp.X_op == O_constant
4295 && skip_past_comma (&input_line_pointer) != FAIL)
4297 unwind.frame_size += exp.X_add_number;
4301 exp.X_op = O_illegal;
4303 if (exp.X_op != O_constant)
4305 as_bad (_("expected <offset>, <opcode>"));
4306 ignore_rest_of_line ();
4312 /* Parse the opcode. */
4317 as_bad (_("unwind opcode too long"));
4318 ignore_rest_of_line ();
4320 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4322 as_bad (_("invalid unwind opcode"));
4323 ignore_rest_of_line ();
4326 op[count++] = exp.X_add_number;
4328 /* Parse the next byte. */
4329 if (skip_past_comma (&input_line_pointer) == FAIL)
4335 /* Add the opcode bytes in reverse order. */
4337 add_unwind_opcode (op[count], 1);
4339 demand_empty_rest_of_line ();
4343 /* Parse a .eabi_attribute directive. */
4346 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4348 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4350 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4351 attributes_set_explicitly[tag] = 1;
4354 /* Emit a tls fix for the symbol. */
4357 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4361 #ifdef md_flush_pending_output
4362 md_flush_pending_output ();
4365 #ifdef md_cons_align
4369 /* Since we're just labelling the code, there's no need to define a
4372 p = obstack_next_free (&frchain_now->frch_obstack);
4373 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4374 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4375 : BFD_RELOC_ARM_TLS_DESCSEQ);
4377 #endif /* OBJ_ELF */
4379 static void s_arm_arch (int);
4380 static void s_arm_object_arch (int);
4381 static void s_arm_cpu (int);
4382 static void s_arm_fpu (int);
4383 static void s_arm_arch_extension (int);
4388 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4395 if (exp.X_op == O_symbol)
4396 exp.X_op = O_secrel;
4398 emit_expr (&exp, 4);
4400 while (*input_line_pointer++ == ',');
4402 input_line_pointer--;
4403 demand_empty_rest_of_line ();
4407 /* This table describes all the machine specific pseudo-ops the assembler
4408 has to support. The fields are:
4409 pseudo-op name without dot
4410 function to call to execute this pseudo-op
4411 Integer arg to pass to the function. */
4413 const pseudo_typeS md_pseudo_table[] =
4415 /* Never called because '.req' does not start a line. */
4416 { "req", s_req, 0 },
4417 /* Following two are likewise never called. */
4420 { "unreq", s_unreq, 0 },
4421 { "bss", s_bss, 0 },
4422 { "align", s_align, 0 },
4423 { "arm", s_arm, 0 },
4424 { "thumb", s_thumb, 0 },
4425 { "code", s_code, 0 },
4426 { "force_thumb", s_force_thumb, 0 },
4427 { "thumb_func", s_thumb_func, 0 },
4428 { "thumb_set", s_thumb_set, 0 },
4429 { "even", s_even, 0 },
4430 { "ltorg", s_ltorg, 0 },
4431 { "pool", s_ltorg, 0 },
4432 { "syntax", s_syntax, 0 },
4433 { "cpu", s_arm_cpu, 0 },
4434 { "arch", s_arm_arch, 0 },
4435 { "object_arch", s_arm_object_arch, 0 },
4436 { "fpu", s_arm_fpu, 0 },
4437 { "arch_extension", s_arm_arch_extension, 0 },
4439 { "word", s_arm_elf_cons, 4 },
4440 { "long", s_arm_elf_cons, 4 },
4441 { "inst.n", s_arm_elf_inst, 2 },
4442 { "inst.w", s_arm_elf_inst, 4 },
4443 { "inst", s_arm_elf_inst, 0 },
4444 { "rel31", s_arm_rel31, 0 },
4445 { "fnstart", s_arm_unwind_fnstart, 0 },
4446 { "fnend", s_arm_unwind_fnend, 0 },
4447 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4448 { "personality", s_arm_unwind_personality, 0 },
4449 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4450 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4451 { "save", s_arm_unwind_save, 0 },
4452 { "vsave", s_arm_unwind_save, 1 },
4453 { "movsp", s_arm_unwind_movsp, 0 },
4454 { "pad", s_arm_unwind_pad, 0 },
4455 { "setfp", s_arm_unwind_setfp, 0 },
4456 { "unwind_raw", s_arm_unwind_raw, 0 },
4457 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4458 { "tlsdescseq", s_arm_tls_descseq, 0 },
4462 /* These are used for dwarf. */
4466 /* These are used for dwarf2. */
4467 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4468 { "loc", dwarf2_directive_loc, 0 },
4469 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4471 { "extend", float_cons, 'x' },
4472 { "ldouble", float_cons, 'x' },
4473 { "packed", float_cons, 'p' },
4475 {"secrel32", pe_directive_secrel, 0},
4480 /* Parser functions used exclusively in instruction operands. */
4482 /* Generic immediate-value read function for use in insn parsing.
4483 STR points to the beginning of the immediate (the leading #);
4484 VAL receives the value; if the value is outside [MIN, MAX]
4485 issue an error. PREFIX_OPT is true if the immediate prefix is
4489 parse_immediate (char **str, int *val, int min, int max,
4490 bfd_boolean prefix_opt)
4493 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4494 if (exp.X_op != O_constant)
4496 inst.error = _("constant expression required");
4500 if (exp.X_add_number < min || exp.X_add_number > max)
4502 inst.error = _("immediate value out of range");
4506 *val = exp.X_add_number;
4510 /* Less-generic immediate-value read function with the possibility of loading a
4511 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4512 instructions. Puts the result directly in inst.operands[i]. */
4515 parse_big_immediate (char **str, int i)
4520 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4522 if (exp.X_op == O_constant)
4524 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4525 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4526 O_constant. We have to be careful not to break compilation for
4527 32-bit X_add_number, though. */
4528 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4530 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4531 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4532 inst.operands[i].regisimm = 1;
4535 else if (exp.X_op == O_big
4536 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4538 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4540 /* Bignums have their least significant bits in
4541 generic_bignum[0]. Make sure we put 32 bits in imm and
4542 32 bits in reg, in a (hopefully) portable way. */
4543 gas_assert (parts != 0);
4545 /* Make sure that the number is not too big.
4546 PR 11972: Bignums can now be sign-extended to the
4547 size of a .octa so check that the out of range bits
4548 are all zero or all one. */
4549 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4551 LITTLENUM_TYPE m = -1;
4553 if (generic_bignum[parts * 2] != 0
4554 && generic_bignum[parts * 2] != m)
4557 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4558 if (generic_bignum[j] != generic_bignum[j-1])
4562 inst.operands[i].imm = 0;
4563 for (j = 0; j < parts; j++, idx++)
4564 inst.operands[i].imm |= generic_bignum[idx]
4565 << (LITTLENUM_NUMBER_OF_BITS * j);
4566 inst.operands[i].reg = 0;
4567 for (j = 0; j < parts; j++, idx++)
4568 inst.operands[i].reg |= generic_bignum[idx]
4569 << (LITTLENUM_NUMBER_OF_BITS * j);
4570 inst.operands[i].regisimm = 1;
4580 /* Returns the pseudo-register number of an FPA immediate constant,
4581 or FAIL if there isn't a valid constant here. */
4584 parse_fpa_immediate (char ** str)
4586 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4592 /* First try and match exact strings, this is to guarantee
4593 that some formats will work even for cross assembly. */
4595 for (i = 0; fp_const[i]; i++)
4597 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4601 *str += strlen (fp_const[i]);
4602 if (is_end_of_line[(unsigned char) **str])
4608 /* Just because we didn't get a match doesn't mean that the constant
4609 isn't valid, just that it is in a format that we don't
4610 automatically recognize. Try parsing it with the standard
4611 expression routines. */
4613 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4615 /* Look for a raw floating point number. */
4616 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4617 && is_end_of_line[(unsigned char) *save_in])
4619 for (i = 0; i < NUM_FLOAT_VALS; i++)
4621 for (j = 0; j < MAX_LITTLENUMS; j++)
4623 if (words[j] != fp_values[i][j])
4627 if (j == MAX_LITTLENUMS)
4635 /* Try and parse a more complex expression, this will probably fail
4636 unless the code uses a floating point prefix (eg "0f"). */
4637 save_in = input_line_pointer;
4638 input_line_pointer = *str;
4639 if (expression (&exp) == absolute_section
4640 && exp.X_op == O_big
4641 && exp.X_add_number < 0)
4643 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4645 if (gen_to_words (words, 5, (long) 15) == 0)
4647 for (i = 0; i < NUM_FLOAT_VALS; i++)
4649 for (j = 0; j < MAX_LITTLENUMS; j++)
4651 if (words[j] != fp_values[i][j])
4655 if (j == MAX_LITTLENUMS)
4657 *str = input_line_pointer;
4658 input_line_pointer = save_in;
4665 *str = input_line_pointer;
4666 input_line_pointer = save_in;
4667 inst.error = _("invalid FPA immediate expression");
4671 /* Returns 1 if a number has "quarter-precision" float format
4672 0baBbbbbbc defgh000 00000000 00000000. */
4675 is_quarter_float (unsigned imm)
4677 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4678 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4681 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4682 0baBbbbbbc defgh000 00000000 00000000.
4683 The zero and minus-zero cases need special handling, since they can't be
4684 encoded in the "quarter-precision" float format, but can nonetheless be
4685 loaded as integer constants. */
4688 parse_qfloat_immediate (char **ccp, int *immed)
4692 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4693 int found_fpchar = 0;
4695 skip_past_char (&str, '#');
4697 /* We must not accidentally parse an integer as a floating-point number. Make
4698 sure that the value we parse is not an integer by checking for special
4699 characters '.' or 'e'.
4700 FIXME: This is a horrible hack, but doing better is tricky because type
4701 information isn't in a very usable state at parse time. */
4703 skip_whitespace (fpnum);
4705 if (strncmp (fpnum, "0x", 2) == 0)
4709 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4710 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4720 if ((str = atof_ieee (str, 's', words)) != NULL)
4722 unsigned fpword = 0;
4725 /* Our FP word must be 32 bits (single-precision FP). */
4726 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4728 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4732 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4745 /* Shift operands. */
4748 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4751 struct asm_shift_name
4754 enum shift_kind kind;
4757 /* Third argument to parse_shift. */
4758 enum parse_shift_mode
4760 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4761 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4762 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4763 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4764 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4767 /* Parse a <shift> specifier on an ARM data processing instruction.
4768 This has three forms:
4770 (LSL|LSR|ASL|ASR|ROR) Rs
4771 (LSL|LSR|ASL|ASR|ROR) #imm
4774 Note that ASL is assimilated to LSL in the instruction encoding, and
4775 RRX to ROR #0 (which cannot be written as such). */
4778 parse_shift (char **str, int i, enum parse_shift_mode mode)
4780 const struct asm_shift_name *shift_name;
4781 enum shift_kind shift;
4786 for (p = *str; ISALPHA (*p); p++)
4791 inst.error = _("shift expression expected");
4795 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4798 if (shift_name == NULL)
4800 inst.error = _("shift expression expected");
4804 shift = shift_name->kind;
4808 case NO_SHIFT_RESTRICT:
4809 case SHIFT_IMMEDIATE: break;
4811 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4812 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4814 inst.error = _("'LSL' or 'ASR' required");
4819 case SHIFT_LSL_IMMEDIATE:
4820 if (shift != SHIFT_LSL)
4822 inst.error = _("'LSL' required");
4827 case SHIFT_ASR_IMMEDIATE:
4828 if (shift != SHIFT_ASR)
4830 inst.error = _("'ASR' required");
4838 if (shift != SHIFT_RRX)
4840 /* Whitespace can appear here if the next thing is a bare digit. */
4841 skip_whitespace (p);
4843 if (mode == NO_SHIFT_RESTRICT
4844 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4846 inst.operands[i].imm = reg;
4847 inst.operands[i].immisreg = 1;
4849 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4852 inst.operands[i].shift_kind = shift;
4853 inst.operands[i].shifted = 1;
4858 /* Parse a <shifter_operand> for an ARM data processing instruction:
4861 #<immediate>, <rotate>
4865 where <shift> is defined by parse_shift above, and <rotate> is a
4866 multiple of 2 between 0 and 30. Validation of immediate operands
4867 is deferred to md_apply_fix. */
4870 parse_shifter_operand (char **str, int i)
4875 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4877 inst.operands[i].reg = value;
4878 inst.operands[i].isreg = 1;
4880 /* parse_shift will override this if appropriate */
4881 inst.reloc.exp.X_op = O_constant;
4882 inst.reloc.exp.X_add_number = 0;
4884 if (skip_past_comma (str) == FAIL)
4887 /* Shift operation on register. */
4888 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4891 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4894 if (skip_past_comma (str) == SUCCESS)
4896 /* #x, y -- ie explicit rotation by Y. */
4897 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4900 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4902 inst.error = _("constant expression expected");
4906 value = exp.X_add_number;
4907 if (value < 0 || value > 30 || value % 2 != 0)
4909 inst.error = _("invalid rotation");
4912 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4914 inst.error = _("invalid constant");
4918 /* Encode as specified. */
4919 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4923 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4924 inst.reloc.pc_rel = 0;
4928 /* Group relocation information. Each entry in the table contains the
4929 textual name of the relocation as may appear in assembler source
4930 and must end with a colon.
4931 Along with this textual name are the relocation codes to be used if
4932 the corresponding instruction is an ALU instruction (ADD or SUB only),
4933 an LDR, an LDRS, or an LDC. */
4935 struct group_reloc_table_entry
4946 /* Varieties of non-ALU group relocation. */
4953 static struct group_reloc_table_entry group_reloc_table[] =
4954 { /* Program counter relative: */
4956 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4961 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4962 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4963 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4964 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4966 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4971 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4972 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4973 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4974 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4976 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4977 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4978 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4979 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4980 /* Section base relative */
4982 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4987 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4988 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4989 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4990 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4992 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4997 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4998 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4999 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5000 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5002 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5003 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5004 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5005 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5007 /* Given the address of a pointer pointing to the textual name of a group
5008 relocation as may appear in assembler source, attempt to find its details
5009 in group_reloc_table. The pointer will be updated to the character after
5010 the trailing colon. On failure, FAIL will be returned; SUCCESS
5011 otherwise. On success, *entry will be updated to point at the relevant
5012 group_reloc_table entry. */
5015 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5018 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5020 int length = strlen (group_reloc_table[i].name);
5022 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5023 && (*str)[length] == ':')
5025 *out = &group_reloc_table[i];
5026 *str += (length + 1);
5034 /* Parse a <shifter_operand> for an ARM data processing instruction
5035 (as for parse_shifter_operand) where group relocations are allowed:
5038 #<immediate>, <rotate>
5039 #:<group_reloc>:<expression>
5043 where <group_reloc> is one of the strings defined in group_reloc_table.
5044 The hashes are optional.
5046 Everything else is as for parse_shifter_operand. */
5048 static parse_operand_result
5049 parse_shifter_operand_group_reloc (char **str, int i)
5051 /* Determine if we have the sequence of characters #: or just :
5052 coming next. If we do, then we check for a group relocation.
5053 If we don't, punt the whole lot to parse_shifter_operand. */
5055 if (((*str)[0] == '#' && (*str)[1] == ':')
5056 || (*str)[0] == ':')
5058 struct group_reloc_table_entry *entry;
5060 if ((*str)[0] == '#')
5065 /* Try to parse a group relocation. Anything else is an error. */
5066 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5068 inst.error = _("unknown group relocation");
5069 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5072 /* We now have the group relocation table entry corresponding to
5073 the name in the assembler source. Next, we parse the expression. */
5074 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5075 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5077 /* Record the relocation type (always the ALU variant here). */
5078 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5079 gas_assert (inst.reloc.type != 0);
5081 return PARSE_OPERAND_SUCCESS;
5084 return parse_shifter_operand (str, i) == SUCCESS
5085 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5087 /* Never reached. */
5090 /* Parse a Neon alignment expression. Information is written to
5091 inst.operands[i]. We assume the initial ':' has been skipped.
5093 align .imm = align << 8, .immisalign=1, .preind=0 */
5094 static parse_operand_result
5095 parse_neon_alignment (char **str, int i)
5100 my_get_expression (&exp, &p, GE_NO_PREFIX);
5102 if (exp.X_op != O_constant)
5104 inst.error = _("alignment must be constant");
5105 return PARSE_OPERAND_FAIL;
5108 inst.operands[i].imm = exp.X_add_number << 8;
5109 inst.operands[i].immisalign = 1;
5110 /* Alignments are not pre-indexes. */
5111 inst.operands[i].preind = 0;
5114 return PARSE_OPERAND_SUCCESS;
5117 /* Parse all forms of an ARM address expression. Information is written
5118 to inst.operands[i] and/or inst.reloc.
5120 Preindexed addressing (.preind=1):
5122 [Rn, #offset] .reg=Rn .reloc.exp=offset
5123 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5124 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5125 .shift_kind=shift .reloc.exp=shift_imm
5127 These three may have a trailing ! which causes .writeback to be set also.
5129 Postindexed addressing (.postind=1, .writeback=1):
5131 [Rn], #offset .reg=Rn .reloc.exp=offset
5132 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5133 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5134 .shift_kind=shift .reloc.exp=shift_imm
5136 Unindexed addressing (.preind=0, .postind=0):
5138 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5142 [Rn]{!} shorthand for [Rn,#0]{!}
5143 =immediate .isreg=0 .reloc.exp=immediate
5144 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5146 It is the caller's responsibility to check for addressing modes not
5147 supported by the instruction, and to set inst.reloc.type. */
5149 static parse_operand_result
5150 parse_address_main (char **str, int i, int group_relocations,
5151 group_reloc_type group_type)
5156 if (skip_past_char (&p, '[') == FAIL)
5158 if (skip_past_char (&p, '=') == FAIL)
5160 /* Bare address - translate to PC-relative offset. */
5161 inst.reloc.pc_rel = 1;
5162 inst.operands[i].reg = REG_PC;
5163 inst.operands[i].isreg = 1;
5164 inst.operands[i].preind = 1;
5166 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5168 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5169 return PARSE_OPERAND_FAIL;
5172 return PARSE_OPERAND_SUCCESS;
5175 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5176 skip_whitespace (p);
5178 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5180 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5181 return PARSE_OPERAND_FAIL;
5183 inst.operands[i].reg = reg;
5184 inst.operands[i].isreg = 1;
5186 if (skip_past_comma (&p) == SUCCESS)
5188 inst.operands[i].preind = 1;
5191 else if (*p == '-') p++, inst.operands[i].negative = 1;
5193 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5195 inst.operands[i].imm = reg;
5196 inst.operands[i].immisreg = 1;
5198 if (skip_past_comma (&p) == SUCCESS)
5199 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5200 return PARSE_OPERAND_FAIL;
5202 else if (skip_past_char (&p, ':') == SUCCESS)
5204 /* FIXME: '@' should be used here, but it's filtered out by generic
5205 code before we get to see it here. This may be subject to
5207 parse_operand_result result = parse_neon_alignment (&p, i);
5209 if (result != PARSE_OPERAND_SUCCESS)
5214 if (inst.operands[i].negative)
5216 inst.operands[i].negative = 0;
5220 if (group_relocations
5221 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5223 struct group_reloc_table_entry *entry;
5225 /* Skip over the #: or : sequence. */
5231 /* Try to parse a group relocation. Anything else is an
5233 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5235 inst.error = _("unknown group relocation");
5236 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5239 /* We now have the group relocation table entry corresponding to
5240 the name in the assembler source. Next, we parse the
5242 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5243 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5245 /* Record the relocation type. */
5249 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5253 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5257 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5264 if (inst.reloc.type == 0)
5266 inst.error = _("this group relocation is not allowed on this instruction");
5267 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5273 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5274 return PARSE_OPERAND_FAIL;
5275 /* If the offset is 0, find out if it's a +0 or -0. */
5276 if (inst.reloc.exp.X_op == O_constant
5277 && inst.reloc.exp.X_add_number == 0)
5279 skip_whitespace (q);
5283 skip_whitespace (q);
5286 inst.operands[i].negative = 1;
5291 else if (skip_past_char (&p, ':') == SUCCESS)
5293 /* FIXME: '@' should be used here, but it's filtered out by generic code
5294 before we get to see it here. This may be subject to change. */
5295 parse_operand_result result = parse_neon_alignment (&p, i);
5297 if (result != PARSE_OPERAND_SUCCESS)
5301 if (skip_past_char (&p, ']') == FAIL)
5303 inst.error = _("']' expected");
5304 return PARSE_OPERAND_FAIL;
5307 if (skip_past_char (&p, '!') == SUCCESS)
5308 inst.operands[i].writeback = 1;
5310 else if (skip_past_comma (&p) == SUCCESS)
5312 if (skip_past_char (&p, '{') == SUCCESS)
5314 /* [Rn], {expr} - unindexed, with option */
5315 if (parse_immediate (&p, &inst.operands[i].imm,
5316 0, 255, TRUE) == FAIL)
5317 return PARSE_OPERAND_FAIL;
5319 if (skip_past_char (&p, '}') == FAIL)
5321 inst.error = _("'}' expected at end of 'option' field");
5322 return PARSE_OPERAND_FAIL;
5324 if (inst.operands[i].preind)
5326 inst.error = _("cannot combine index with option");
5327 return PARSE_OPERAND_FAIL;
5330 return PARSE_OPERAND_SUCCESS;
5334 inst.operands[i].postind = 1;
5335 inst.operands[i].writeback = 1;
5337 if (inst.operands[i].preind)
5339 inst.error = _("cannot combine pre- and post-indexing");
5340 return PARSE_OPERAND_FAIL;
5344 else if (*p == '-') p++, inst.operands[i].negative = 1;
5346 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5348 /* We might be using the immediate for alignment already. If we
5349 are, OR the register number into the low-order bits. */
5350 if (inst.operands[i].immisalign)
5351 inst.operands[i].imm |= reg;
5353 inst.operands[i].imm = reg;
5354 inst.operands[i].immisreg = 1;
5356 if (skip_past_comma (&p) == SUCCESS)
5357 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5358 return PARSE_OPERAND_FAIL;
5363 if (inst.operands[i].negative)
5365 inst.operands[i].negative = 0;
5368 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5369 return PARSE_OPERAND_FAIL;
5370 /* If the offset is 0, find out if it's a +0 or -0. */
5371 if (inst.reloc.exp.X_op == O_constant
5372 && inst.reloc.exp.X_add_number == 0)
5374 skip_whitespace (q);
5378 skip_whitespace (q);
5381 inst.operands[i].negative = 1;
5387 /* If at this point neither .preind nor .postind is set, we have a
5388 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5389 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5391 inst.operands[i].preind = 1;
5392 inst.reloc.exp.X_op = O_constant;
5393 inst.reloc.exp.X_add_number = 0;
5396 return PARSE_OPERAND_SUCCESS;
5400 parse_address (char **str, int i)
5402 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5406 static parse_operand_result
5407 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5409 return parse_address_main (str, i, 1, type);
5412 /* Parse an operand for a MOVW or MOVT instruction. */
5414 parse_half (char **str)
5419 skip_past_char (&p, '#');
5420 if (strncasecmp (p, ":lower16:", 9) == 0)
5421 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5422 else if (strncasecmp (p, ":upper16:", 9) == 0)
5423 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5425 if (inst.reloc.type != BFD_RELOC_UNUSED)
5428 skip_whitespace (p);
5431 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5434 if (inst.reloc.type == BFD_RELOC_UNUSED)
5436 if (inst.reloc.exp.X_op != O_constant)
5438 inst.error = _("constant expression expected");
5441 if (inst.reloc.exp.X_add_number < 0
5442 || inst.reloc.exp.X_add_number > 0xffff)
5444 inst.error = _("immediate value out of range");
5452 /* Miscellaneous. */
5454 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5455 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5457 parse_psr (char **str, bfd_boolean lhs)
5460 unsigned long psr_field;
5461 const struct asm_psr *psr;
5463 bfd_boolean is_apsr = FALSE;
5464 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5466 /* PR gas/12698: If the user has specified -march=all then m_profile will
5467 be TRUE, but we want to ignore it in this case as we are building for any
5468 CPU type, including non-m variants. */
5469 if (selected_cpu.core == arm_arch_any.core)
5472 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5473 feature for ease of use and backwards compatibility. */
5475 if (strncasecmp (p, "SPSR", 4) == 0)
5478 goto unsupported_psr;
5480 psr_field = SPSR_BIT;
5482 else if (strncasecmp (p, "CPSR", 4) == 0)
5485 goto unsupported_psr;
5489 else if (strncasecmp (p, "APSR", 4) == 0)
5491 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5492 and ARMv7-R architecture CPUs. */
5501 while (ISALNUM (*p) || *p == '_');
5503 if (strncasecmp (start, "iapsr", 5) == 0
5504 || strncasecmp (start, "eapsr", 5) == 0
5505 || strncasecmp (start, "xpsr", 4) == 0
5506 || strncasecmp (start, "psr", 3) == 0)
5507 p = start + strcspn (start, "rR") + 1;
5509 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5515 /* If APSR is being written, a bitfield may be specified. Note that
5516 APSR itself is handled above. */
5517 if (psr->field <= 3)
5519 psr_field = psr->field;
5525 /* M-profile MSR instructions have the mask field set to "10", except
5526 *PSR variants which modify APSR, which may use a different mask (and
5527 have been handled already). Do that by setting the PSR_f field
5529 return psr->field | (lhs ? PSR_f : 0);
5532 goto unsupported_psr;
5538 /* A suffix follows. */
5544 while (ISALNUM (*p) || *p == '_');
5548 /* APSR uses a notation for bits, rather than fields. */
5549 unsigned int nzcvq_bits = 0;
5550 unsigned int g_bit = 0;
5553 for (bit = start; bit != p; bit++)
5555 switch (TOLOWER (*bit))
5558 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5562 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5566 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5570 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5574 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5578 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5582 inst.error = _("unexpected bit specified after APSR");
5587 if (nzcvq_bits == 0x1f)
5592 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5594 inst.error = _("selected processor does not "
5595 "support DSP extension");
5602 if ((nzcvq_bits & 0x20) != 0
5603 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5604 || (g_bit & 0x2) != 0)
5606 inst.error = _("bad bitmask specified after APSR");
5612 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5617 psr_field |= psr->field;
5623 goto error; /* Garbage after "[CS]PSR". */
5625 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5626 is deprecated, but allow it anyway. */
5630 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5633 else if (!m_profile)
5634 /* These bits are never right for M-profile devices: don't set them
5635 (only code paths which read/write APSR reach here). */
5636 psr_field |= (PSR_c | PSR_f);
5642 inst.error = _("selected processor does not support requested special "
5643 "purpose register");
5647 inst.error = _("flag for {c}psr instruction expected");
5651 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5652 value suitable for splatting into the AIF field of the instruction. */
5655 parse_cps_flags (char **str)
5664 case '\0': case ',':
5667 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5668 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5669 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5672 inst.error = _("unrecognized CPS flag");
5677 if (saw_a_flag == 0)
5679 inst.error = _("missing CPS flags");
5687 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5688 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5691 parse_endian_specifier (char **str)
5696 if (strncasecmp (s, "BE", 2))
5698 else if (strncasecmp (s, "LE", 2))
5702 inst.error = _("valid endian specifiers are be or le");
5706 if (ISALNUM (s[2]) || s[2] == '_')
5708 inst.error = _("valid endian specifiers are be or le");
5713 return little_endian;
5716 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5717 value suitable for poking into the rotate field of an sxt or sxta
5718 instruction, or FAIL on error. */
5721 parse_ror (char **str)
5726 if (strncasecmp (s, "ROR", 3) == 0)
5730 inst.error = _("missing rotation field after comma");
5734 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5739 case 0: *str = s; return 0x0;
5740 case 8: *str = s; return 0x1;
5741 case 16: *str = s; return 0x2;
5742 case 24: *str = s; return 0x3;
5745 inst.error = _("rotation can only be 0, 8, 16, or 24");
5750 /* Parse a conditional code (from conds[] below). The value returned is in the
5751 range 0 .. 14, or FAIL. */
5753 parse_cond (char **str)
5756 const struct asm_cond *c;
5758 /* Condition codes are always 2 characters, so matching up to
5759 3 characters is sufficient. */
5764 while (ISALPHA (*q) && n < 3)
5766 cond[n] = TOLOWER (*q);
5771 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5774 inst.error = _("condition required");
5782 /* If the given feature available in the selected CPU, mark it as used.
5783 Returns TRUE iff feature is available. */
5785 mark_feature_used (const arm_feature_set *feature)
5787 /* Ensure the option is valid on the current architecture. */
5788 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5791 /* Add the appropriate architecture feature for the barrier option used.
5794 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5796 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5801 /* Parse an option for a barrier instruction. Returns the encoding for the
5804 parse_barrier (char **str)
5807 const struct asm_barrier_opt *o;
5810 while (ISALPHA (*q))
5813 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5818 if (!mark_feature_used (&o->arch))
5825 /* Parse the operands of a table branch instruction. Similar to a memory
5828 parse_tb (char **str)
5833 if (skip_past_char (&p, '[') == FAIL)
5835 inst.error = _("'[' expected");
5839 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5841 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5844 inst.operands[0].reg = reg;
5846 if (skip_past_comma (&p) == FAIL)
5848 inst.error = _("',' expected");
5852 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5854 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5857 inst.operands[0].imm = reg;
5859 if (skip_past_comma (&p) == SUCCESS)
5861 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5863 if (inst.reloc.exp.X_add_number != 1)
5865 inst.error = _("invalid shift");
5868 inst.operands[0].shifted = 1;
5871 if (skip_past_char (&p, ']') == FAIL)
5873 inst.error = _("']' expected");
5880 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5881 information on the types the operands can take and how they are encoded.
5882 Up to four operands may be read; this function handles setting the
5883 ".present" field for each read operand itself.
5884 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5885 else returns FAIL. */
5888 parse_neon_mov (char **str, int *which_operand)
5890 int i = *which_operand, val;
5891 enum arm_reg_type rtype;
5893 struct neon_type_el optype;
5895 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5897 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5898 inst.operands[i].reg = val;
5899 inst.operands[i].isscalar = 1;
5900 inst.operands[i].vectype = optype;
5901 inst.operands[i++].present = 1;
5903 if (skip_past_comma (&ptr) == FAIL)
5906 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5909 inst.operands[i].reg = val;
5910 inst.operands[i].isreg = 1;
5911 inst.operands[i].present = 1;
5913 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5916 /* Cases 0, 1, 2, 3, 5 (D only). */
5917 if (skip_past_comma (&ptr) == FAIL)
5920 inst.operands[i].reg = val;
5921 inst.operands[i].isreg = 1;
5922 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5923 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5924 inst.operands[i].isvec = 1;
5925 inst.operands[i].vectype = optype;
5926 inst.operands[i++].present = 1;
5928 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5930 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5931 Case 13: VMOV <Sd>, <Rm> */
5932 inst.operands[i].reg = val;
5933 inst.operands[i].isreg = 1;
5934 inst.operands[i].present = 1;
5936 if (rtype == REG_TYPE_NQ)
5938 first_error (_("can't use Neon quad register here"));
5941 else if (rtype != REG_TYPE_VFS)
5944 if (skip_past_comma (&ptr) == FAIL)
5946 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5948 inst.operands[i].reg = val;
5949 inst.operands[i].isreg = 1;
5950 inst.operands[i].present = 1;
5953 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5956 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5957 Case 1: VMOV<c><q> <Dd>, <Dm>
5958 Case 8: VMOV.F32 <Sd>, <Sm>
5959 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5961 inst.operands[i].reg = val;
5962 inst.operands[i].isreg = 1;
5963 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5964 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5965 inst.operands[i].isvec = 1;
5966 inst.operands[i].vectype = optype;
5967 inst.operands[i].present = 1;
5969 if (skip_past_comma (&ptr) == SUCCESS)
5974 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5977 inst.operands[i].reg = val;
5978 inst.operands[i].isreg = 1;
5979 inst.operands[i++].present = 1;
5981 if (skip_past_comma (&ptr) == FAIL)
5984 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5987 inst.operands[i].reg = val;
5988 inst.operands[i].isreg = 1;
5989 inst.operands[i].present = 1;
5992 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5993 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5994 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5995 Case 10: VMOV.F32 <Sd>, #<imm>
5996 Case 11: VMOV.F64 <Dd>, #<imm> */
5997 inst.operands[i].immisfloat = 1;
5998 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5999 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6000 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6004 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6008 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6011 inst.operands[i].reg = val;
6012 inst.operands[i].isreg = 1;
6013 inst.operands[i++].present = 1;
6015 if (skip_past_comma (&ptr) == FAIL)
6018 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6020 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6021 inst.operands[i].reg = val;
6022 inst.operands[i].isscalar = 1;
6023 inst.operands[i].present = 1;
6024 inst.operands[i].vectype = optype;
6026 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6028 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6029 inst.operands[i].reg = val;
6030 inst.operands[i].isreg = 1;
6031 inst.operands[i++].present = 1;
6033 if (skip_past_comma (&ptr) == FAIL)
6036 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6039 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6043 inst.operands[i].reg = val;
6044 inst.operands[i].isreg = 1;
6045 inst.operands[i].isvec = 1;
6046 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6047 inst.operands[i].vectype = optype;
6048 inst.operands[i].present = 1;
6050 if (rtype == REG_TYPE_VFS)
6054 if (skip_past_comma (&ptr) == FAIL)
6056 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6059 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6062 inst.operands[i].reg = val;
6063 inst.operands[i].isreg = 1;
6064 inst.operands[i].isvec = 1;
6065 inst.operands[i].issingle = 1;
6066 inst.operands[i].vectype = optype;
6067 inst.operands[i].present = 1;
6070 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6074 inst.operands[i].reg = val;
6075 inst.operands[i].isreg = 1;
6076 inst.operands[i].isvec = 1;
6077 inst.operands[i].issingle = 1;
6078 inst.operands[i].vectype = optype;
6079 inst.operands[i].present = 1;
6084 first_error (_("parse error"));
6088 /* Successfully parsed the operands. Update args. */
6094 first_error (_("expected comma"));
6098 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6102 /* Use this macro when the operand constraints are different
6103 for ARM and THUMB (e.g. ldrd). */
6104 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6105 ((arm_operand) | ((thumb_operand) << 16))
6107 /* Matcher codes for parse_operands. */
6108 enum operand_parse_code
6110 OP_stop, /* end of line */
6112 OP_RR, /* ARM register */
6113 OP_RRnpc, /* ARM register, not r15 */
6114 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6115 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6116 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6117 optional trailing ! */
6118 OP_RRw, /* ARM register, not r15, optional trailing ! */
6119 OP_RCP, /* Coprocessor number */
6120 OP_RCN, /* Coprocessor register */
6121 OP_RF, /* FPA register */
6122 OP_RVS, /* VFP single precision register */
6123 OP_RVD, /* VFP double precision register (0..15) */
6124 OP_RND, /* Neon double precision register (0..31) */
6125 OP_RNQ, /* Neon quad precision register */
6126 OP_RVSD, /* VFP single or double precision register */
6127 OP_RNDQ, /* Neon double or quad precision register */
6128 OP_RNSDQ, /* Neon single, double or quad precision register */
6129 OP_RNSC, /* Neon scalar D[X] */
6130 OP_RVC, /* VFP control register */
6131 OP_RMF, /* Maverick F register */
6132 OP_RMD, /* Maverick D register */
6133 OP_RMFX, /* Maverick FX register */
6134 OP_RMDX, /* Maverick DX register */
6135 OP_RMAX, /* Maverick AX register */
6136 OP_RMDS, /* Maverick DSPSC register */
6137 OP_RIWR, /* iWMMXt wR register */
6138 OP_RIWC, /* iWMMXt wC register */
6139 OP_RIWG, /* iWMMXt wCG register */
6140 OP_RXA, /* XScale accumulator register */
6142 OP_REGLST, /* ARM register list */
6143 OP_VRSLST, /* VFP single-precision register list */
6144 OP_VRDLST, /* VFP double-precision register list */
6145 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6146 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6147 OP_NSTRLST, /* Neon element/structure list */
6149 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6150 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6151 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6152 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6153 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6154 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6155 OP_VMOV, /* Neon VMOV operands. */
6156 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6157 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6158 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6160 OP_I0, /* immediate zero */
6161 OP_I7, /* immediate value 0 .. 7 */
6162 OP_I15, /* 0 .. 15 */
6163 OP_I16, /* 1 .. 16 */
6164 OP_I16z, /* 0 .. 16 */
6165 OP_I31, /* 0 .. 31 */
6166 OP_I31w, /* 0 .. 31, optional trailing ! */
6167 OP_I32, /* 1 .. 32 */
6168 OP_I32z, /* 0 .. 32 */
6169 OP_I63, /* 0 .. 63 */
6170 OP_I63s, /* -64 .. 63 */
6171 OP_I64, /* 1 .. 64 */
6172 OP_I64z, /* 0 .. 64 */
6173 OP_I255, /* 0 .. 255 */
6175 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6176 OP_I7b, /* 0 .. 7 */
6177 OP_I15b, /* 0 .. 15 */
6178 OP_I31b, /* 0 .. 31 */
6180 OP_SH, /* shifter operand */
6181 OP_SHG, /* shifter operand with possible group relocation */
6182 OP_ADDR, /* Memory address expression (any mode) */
6183 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6184 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6185 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6186 OP_EXP, /* arbitrary expression */
6187 OP_EXPi, /* same, with optional immediate prefix */
6188 OP_EXPr, /* same, with optional relocation suffix */
6189 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6191 OP_CPSF, /* CPS flags */
6192 OP_ENDI, /* Endianness specifier */
6193 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6194 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6195 OP_COND, /* conditional code */
6196 OP_TB, /* Table branch. */
6198 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6200 OP_RRnpc_I0, /* ARM register or literal 0 */
6201 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6202 OP_RR_EXi, /* ARM register or expression with imm prefix */
6203 OP_RF_IF, /* FPA register or immediate */
6204 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6205 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6207 /* Optional operands. */
6208 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6209 OP_oI31b, /* 0 .. 31 */
6210 OP_oI32b, /* 1 .. 32 */
6211 OP_oI32z, /* 0 .. 32 */
6212 OP_oIffffb, /* 0 .. 65535 */
6213 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6215 OP_oRR, /* ARM register */
6216 OP_oRRnpc, /* ARM register, not the PC */
6217 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6218 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6219 OP_oRND, /* Optional Neon double precision register */
6220 OP_oRNQ, /* Optional Neon quad precision register */
6221 OP_oRNDQ, /* Optional Neon double or quad precision register */
6222 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6223 OP_oSHll, /* LSL immediate */
6224 OP_oSHar, /* ASR immediate */
6225 OP_oSHllar, /* LSL or ASR immediate */
6226 OP_oROR, /* ROR 0/8/16/24 */
6227 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6229 /* Some pre-defined mixed (ARM/THUMB) operands. */
6230 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6231 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6232 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6234 OP_FIRST_OPTIONAL = OP_oI7b
6237 /* Generic instruction operand parser. This does no encoding and no
6238 semantic validation; it merely squirrels values away in the inst
6239 structure. Returns SUCCESS or FAIL depending on whether the
6240 specified grammar matched. */
6242 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6244 unsigned const int *upat = pattern;
6245 char *backtrack_pos = 0;
6246 const char *backtrack_error = 0;
6247 int i, val = 0, backtrack_index = 0;
6248 enum arm_reg_type rtype;
6249 parse_operand_result result;
6250 unsigned int op_parse_code;
6252 #define po_char_or_fail(chr) \
6255 if (skip_past_char (&str, chr) == FAIL) \
6260 #define po_reg_or_fail(regtype) \
6263 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6264 & inst.operands[i].vectype); \
6267 first_error (_(reg_expected_msgs[regtype])); \
6270 inst.operands[i].reg = val; \
6271 inst.operands[i].isreg = 1; \
6272 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6273 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6274 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6275 || rtype == REG_TYPE_VFD \
6276 || rtype == REG_TYPE_NQ); \
6280 #define po_reg_or_goto(regtype, label) \
6283 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6284 & inst.operands[i].vectype); \
6288 inst.operands[i].reg = val; \
6289 inst.operands[i].isreg = 1; \
6290 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6291 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6292 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6293 || rtype == REG_TYPE_VFD \
6294 || rtype == REG_TYPE_NQ); \
6298 #define po_imm_or_fail(min, max, popt) \
6301 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6303 inst.operands[i].imm = val; \
6307 #define po_scalar_or_goto(elsz, label) \
6310 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6313 inst.operands[i].reg = val; \
6314 inst.operands[i].isscalar = 1; \
6318 #define po_misc_or_fail(expr) \
6326 #define po_misc_or_fail_no_backtrack(expr) \
6330 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6331 backtrack_pos = 0; \
6332 if (result != PARSE_OPERAND_SUCCESS) \
6337 #define po_barrier_or_imm(str) \
6340 val = parse_barrier (&str); \
6343 if (ISALPHA (*str)) \
6350 if ((inst.instruction & 0xf0) == 0x60 \
6353 /* ISB can only take SY as an option. */ \
6354 inst.error = _("invalid barrier type"); \
6361 skip_whitespace (str);
6363 for (i = 0; upat[i] != OP_stop; i++)
6365 op_parse_code = upat[i];
6366 if (op_parse_code >= 1<<16)
6367 op_parse_code = thumb ? (op_parse_code >> 16)
6368 : (op_parse_code & ((1<<16)-1));
6370 if (op_parse_code >= OP_FIRST_OPTIONAL)
6372 /* Remember where we are in case we need to backtrack. */
6373 gas_assert (!backtrack_pos);
6374 backtrack_pos = str;
6375 backtrack_error = inst.error;
6376 backtrack_index = i;
6379 if (i > 0 && (i > 1 || inst.operands[0].present))
6380 po_char_or_fail (',');
6382 switch (op_parse_code)
6390 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6391 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6392 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6393 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6394 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6395 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6397 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6399 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6401 /* Also accept generic coprocessor regs for unknown registers. */
6403 po_reg_or_fail (REG_TYPE_CN);
6405 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6406 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6407 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6408 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6409 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6410 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6411 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6412 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6413 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6414 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6416 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6418 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6419 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6421 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6423 /* Neon scalar. Using an element size of 8 means that some invalid
6424 scalars are accepted here, so deal with those in later code. */
6425 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6429 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6432 po_imm_or_fail (0, 0, TRUE);
6437 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6442 po_scalar_or_goto (8, try_rr);
6445 po_reg_or_fail (REG_TYPE_RN);
6451 po_scalar_or_goto (8, try_nsdq);
6454 po_reg_or_fail (REG_TYPE_NSDQ);
6460 po_scalar_or_goto (8, try_ndq);
6463 po_reg_or_fail (REG_TYPE_NDQ);
6469 po_scalar_or_goto (8, try_vfd);
6472 po_reg_or_fail (REG_TYPE_VFD);
6477 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6478 not careful then bad things might happen. */
6479 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6484 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6487 /* There's a possibility of getting a 64-bit immediate here, so
6488 we need special handling. */
6489 if (parse_big_immediate (&str, i) == FAIL)
6491 inst.error = _("immediate value is out of range");
6499 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6502 po_imm_or_fail (0, 63, TRUE);
6507 po_char_or_fail ('[');
6508 po_reg_or_fail (REG_TYPE_RN);
6509 po_char_or_fail (']');
6515 po_reg_or_fail (REG_TYPE_RN);
6516 if (skip_past_char (&str, '!') == SUCCESS)
6517 inst.operands[i].writeback = 1;
6521 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6522 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6523 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6524 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6525 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6526 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6527 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6528 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6529 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6530 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6531 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6532 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6534 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6536 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6537 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6539 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6540 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6541 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6542 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6544 /* Immediate variants */
6546 po_char_or_fail ('{');
6547 po_imm_or_fail (0, 255, TRUE);
6548 po_char_or_fail ('}');
6552 /* The expression parser chokes on a trailing !, so we have
6553 to find it first and zap it. */
6556 while (*s && *s != ',')
6561 inst.operands[i].writeback = 1;
6563 po_imm_or_fail (0, 31, TRUE);
6571 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6576 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6581 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6583 if (inst.reloc.exp.X_op == O_symbol)
6585 val = parse_reloc (&str);
6588 inst.error = _("unrecognized relocation suffix");
6591 else if (val != BFD_RELOC_UNUSED)
6593 inst.operands[i].imm = val;
6594 inst.operands[i].hasreloc = 1;
6599 /* Operand for MOVW or MOVT. */
6601 po_misc_or_fail (parse_half (&str));
6604 /* Register or expression. */
6605 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6606 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6608 /* Register or immediate. */
6609 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6610 I0: po_imm_or_fail (0, 0, FALSE); break;
6612 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6614 if (!is_immediate_prefix (*str))
6617 val = parse_fpa_immediate (&str);
6620 /* FPA immediates are encoded as registers 8-15.
6621 parse_fpa_immediate has already applied the offset. */
6622 inst.operands[i].reg = val;
6623 inst.operands[i].isreg = 1;
6626 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6627 I32z: po_imm_or_fail (0, 32, FALSE); break;
6629 /* Two kinds of register. */
6632 struct reg_entry *rege = arm_reg_parse_multi (&str);
6634 || (rege->type != REG_TYPE_MMXWR
6635 && rege->type != REG_TYPE_MMXWC
6636 && rege->type != REG_TYPE_MMXWCG))
6638 inst.error = _("iWMMXt data or control register expected");
6641 inst.operands[i].reg = rege->number;
6642 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6648 struct reg_entry *rege = arm_reg_parse_multi (&str);
6650 || (rege->type != REG_TYPE_MMXWC
6651 && rege->type != REG_TYPE_MMXWCG))
6653 inst.error = _("iWMMXt control register expected");
6656 inst.operands[i].reg = rege->number;
6657 inst.operands[i].isreg = 1;
6662 case OP_CPSF: val = parse_cps_flags (&str); break;
6663 case OP_ENDI: val = parse_endian_specifier (&str); break;
6664 case OP_oROR: val = parse_ror (&str); break;
6665 case OP_COND: val = parse_cond (&str); break;
6666 case OP_oBARRIER_I15:
6667 po_barrier_or_imm (str); break;
6669 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6675 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6676 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6678 inst.error = _("Banked registers are not available with this "
6684 val = parse_psr (&str, op_parse_code == OP_wPSR);
6688 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6691 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6693 if (strncasecmp (str, "APSR_", 5) == 0)
6700 case 'c': found = (found & 1) ? 16 : found | 1; break;
6701 case 'n': found = (found & 2) ? 16 : found | 2; break;
6702 case 'z': found = (found & 4) ? 16 : found | 4; break;
6703 case 'v': found = (found & 8) ? 16 : found | 8; break;
6704 default: found = 16;
6708 inst.operands[i].isvec = 1;
6709 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6710 inst.operands[i].reg = REG_PC;
6717 po_misc_or_fail (parse_tb (&str));
6720 /* Register lists. */
6722 val = parse_reg_list (&str);
6725 inst.operands[1].writeback = 1;
6731 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6735 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6739 /* Allow Q registers too. */
6740 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6745 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6747 inst.operands[i].issingle = 1;
6752 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6757 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6758 &inst.operands[i].vectype);
6761 /* Addressing modes */
6763 po_misc_or_fail (parse_address (&str, i));
6767 po_misc_or_fail_no_backtrack (
6768 parse_address_group_reloc (&str, i, GROUP_LDR));
6772 po_misc_or_fail_no_backtrack (
6773 parse_address_group_reloc (&str, i, GROUP_LDRS));
6777 po_misc_or_fail_no_backtrack (
6778 parse_address_group_reloc (&str, i, GROUP_LDC));
6782 po_misc_or_fail (parse_shifter_operand (&str, i));
6786 po_misc_or_fail_no_backtrack (
6787 parse_shifter_operand_group_reloc (&str, i));
6791 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6795 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6799 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6803 as_fatal (_("unhandled operand code %d"), op_parse_code);
6806 /* Various value-based sanity checks and shared operations. We
6807 do not signal immediate failures for the register constraints;
6808 this allows a syntax error to take precedence. */
6809 switch (op_parse_code)
6817 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6818 inst.error = BAD_PC;
6823 if (inst.operands[i].isreg)
6825 if (inst.operands[i].reg == REG_PC)
6826 inst.error = BAD_PC;
6827 else if (inst.operands[i].reg == REG_SP)
6828 inst.error = BAD_SP;
6833 if (inst.operands[i].isreg
6834 && inst.operands[i].reg == REG_PC
6835 && (inst.operands[i].writeback || thumb))
6836 inst.error = BAD_PC;
6845 case OP_oBARRIER_I15:
6854 inst.operands[i].imm = val;
6861 /* If we get here, this operand was successfully parsed. */
6862 inst.operands[i].present = 1;
6866 inst.error = BAD_ARGS;
6871 /* The parse routine should already have set inst.error, but set a
6872 default here just in case. */
6874 inst.error = _("syntax error");
6878 /* Do not backtrack over a trailing optional argument that
6879 absorbed some text. We will only fail again, with the
6880 'garbage following instruction' error message, which is
6881 probably less helpful than the current one. */
6882 if (backtrack_index == i && backtrack_pos != str
6883 && upat[i+1] == OP_stop)
6886 inst.error = _("syntax error");
6890 /* Try again, skipping the optional argument at backtrack_pos. */
6891 str = backtrack_pos;
6892 inst.error = backtrack_error;
6893 inst.operands[backtrack_index].present = 0;
6894 i = backtrack_index;
6898 /* Check that we have parsed all the arguments. */
6899 if (*str != '\0' && !inst.error)
6900 inst.error = _("garbage following instruction");
6902 return inst.error ? FAIL : SUCCESS;
6905 #undef po_char_or_fail
6906 #undef po_reg_or_fail
6907 #undef po_reg_or_goto
6908 #undef po_imm_or_fail
6909 #undef po_scalar_or_fail
6910 #undef po_barrier_or_imm
6912 /* Shorthand macro for instruction encoding functions issuing errors. */
6913 #define constraint(expr, err) \
6924 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6925 instructions are unpredictable if these registers are used. This
6926 is the BadReg predicate in ARM's Thumb-2 documentation. */
6927 #define reject_bad_reg(reg) \
6929 if (reg == REG_SP || reg == REG_PC) \
6931 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6936 /* If REG is R13 (the stack pointer), warn that its use is
6938 #define warn_deprecated_sp(reg) \
6940 if (warn_on_deprecated && reg == REG_SP) \
6941 as_warn (_("use of r13 is deprecated")); \
6944 /* Functions for operand encoding. ARM, then Thumb. */
6946 #define rotate_left(v, n) (v << n | v >> (32 - n))
6948 /* If VAL can be encoded in the immediate field of an ARM instruction,
6949 return the encoded form. Otherwise, return FAIL. */
6952 encode_arm_immediate (unsigned int val)
6956 for (i = 0; i < 32; i += 2)
6957 if ((a = rotate_left (val, i)) <= 0xff)
6958 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6963 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6964 return the encoded form. Otherwise, return FAIL. */
6966 encode_thumb32_immediate (unsigned int val)
6973 for (i = 1; i <= 24; i++)
6976 if ((val & ~(0xff << i)) == 0)
6977 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6981 if (val == ((a << 16) | a))
6983 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6987 if (val == ((a << 16) | a))
6988 return 0x200 | (a >> 8);
6992 /* Encode a VFP SP or DP register number into inst.instruction. */
6995 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6997 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
7000 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
7003 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7006 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7011 first_error (_("D register out of range for selected VFP version"));
7019 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7023 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7027 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7031 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7035 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7039 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7047 /* Encode a <shift> in an ARM-format instruction. The immediate,
7048 if any, is handled by md_apply_fix. */
7050 encode_arm_shift (int i)
7052 if (inst.operands[i].shift_kind == SHIFT_RRX)
7053 inst.instruction |= SHIFT_ROR << 5;
7056 inst.instruction |= inst.operands[i].shift_kind << 5;
7057 if (inst.operands[i].immisreg)
7059 inst.instruction |= SHIFT_BY_REG;
7060 inst.instruction |= inst.operands[i].imm << 8;
7063 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7068 encode_arm_shifter_operand (int i)
7070 if (inst.operands[i].isreg)
7072 inst.instruction |= inst.operands[i].reg;
7073 encode_arm_shift (i);
7077 inst.instruction |= INST_IMMEDIATE;
7078 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7079 inst.instruction |= inst.operands[i].imm;
7083 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7085 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7088 Generate an error if the operand is not a register. */
7089 constraint (!inst.operands[i].isreg,
7090 _("Instruction does not support =N addresses"));
7092 inst.instruction |= inst.operands[i].reg << 16;
7094 if (inst.operands[i].preind)
7098 inst.error = _("instruction does not accept preindexed addressing");
7101 inst.instruction |= PRE_INDEX;
7102 if (inst.operands[i].writeback)
7103 inst.instruction |= WRITE_BACK;
7106 else if (inst.operands[i].postind)
7108 gas_assert (inst.operands[i].writeback);
7110 inst.instruction |= WRITE_BACK;
7112 else /* unindexed - only for coprocessor */
7114 inst.error = _("instruction does not accept unindexed addressing");
7118 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7119 && (((inst.instruction & 0x000f0000) >> 16)
7120 == ((inst.instruction & 0x0000f000) >> 12)))
7121 as_warn ((inst.instruction & LOAD_BIT)
7122 ? _("destination register same as write-back base")
7123 : _("source register same as write-back base"));
7126 /* inst.operands[i] was set up by parse_address. Encode it into an
7127 ARM-format mode 2 load or store instruction. If is_t is true,
7128 reject forms that cannot be used with a T instruction (i.e. not
7131 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7133 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7135 encode_arm_addr_mode_common (i, is_t);
7137 if (inst.operands[i].immisreg)
7139 constraint ((inst.operands[i].imm == REG_PC
7140 || (is_pc && inst.operands[i].writeback)),
7142 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7143 inst.instruction |= inst.operands[i].imm;
7144 if (!inst.operands[i].negative)
7145 inst.instruction |= INDEX_UP;
7146 if (inst.operands[i].shifted)
7148 if (inst.operands[i].shift_kind == SHIFT_RRX)
7149 inst.instruction |= SHIFT_ROR << 5;
7152 inst.instruction |= inst.operands[i].shift_kind << 5;
7153 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7157 else /* immediate offset in inst.reloc */
7159 if (is_pc && !inst.reloc.pc_rel)
7161 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7163 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7164 cannot use PC in addressing.
7165 PC cannot be used in writeback addressing, either. */
7166 constraint ((is_t || inst.operands[i].writeback),
7169 /* Use of PC in str is deprecated for ARMv7. */
7170 if (warn_on_deprecated
7172 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7173 as_warn (_("use of PC in this instruction is deprecated"));
7176 if (inst.reloc.type == BFD_RELOC_UNUSED)
7178 /* Prefer + for zero encoded value. */
7179 if (!inst.operands[i].negative)
7180 inst.instruction |= INDEX_UP;
7181 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7186 /* inst.operands[i] was set up by parse_address. Encode it into an
7187 ARM-format mode 3 load or store instruction. Reject forms that
7188 cannot be used with such instructions. If is_t is true, reject
7189 forms that cannot be used with a T instruction (i.e. not
7192 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7194 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7196 inst.error = _("instruction does not accept scaled register index");
7200 encode_arm_addr_mode_common (i, is_t);
7202 if (inst.operands[i].immisreg)
7204 constraint ((inst.operands[i].imm == REG_PC
7205 || inst.operands[i].reg == REG_PC),
7207 inst.instruction |= inst.operands[i].imm;
7208 if (!inst.operands[i].negative)
7209 inst.instruction |= INDEX_UP;
7211 else /* immediate offset in inst.reloc */
7213 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7214 && inst.operands[i].writeback),
7216 inst.instruction |= HWOFFSET_IMM;
7217 if (inst.reloc.type == BFD_RELOC_UNUSED)
7219 /* Prefer + for zero encoded value. */
7220 if (!inst.operands[i].negative)
7221 inst.instruction |= INDEX_UP;
7223 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7228 /* inst.operands[i] was set up by parse_address. Encode it into an
7229 ARM-format instruction. Reject all forms which cannot be encoded
7230 into a coprocessor load/store instruction. If wb_ok is false,
7231 reject use of writeback; if unind_ok is false, reject use of
7232 unindexed addressing. If reloc_override is not 0, use it instead
7233 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7234 (in which case it is preserved). */
7237 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7239 inst.instruction |= inst.operands[i].reg << 16;
7241 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7243 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7245 gas_assert (!inst.operands[i].writeback);
7248 inst.error = _("instruction does not support unindexed addressing");
7251 inst.instruction |= inst.operands[i].imm;
7252 inst.instruction |= INDEX_UP;
7256 if (inst.operands[i].preind)
7257 inst.instruction |= PRE_INDEX;
7259 if (inst.operands[i].writeback)
7261 if (inst.operands[i].reg == REG_PC)
7263 inst.error = _("pc may not be used with write-back");
7268 inst.error = _("instruction does not support writeback");
7271 inst.instruction |= WRITE_BACK;
7275 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7276 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7277 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7278 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7281 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7283 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7286 /* Prefer + for zero encoded value. */
7287 if (!inst.operands[i].negative)
7288 inst.instruction |= INDEX_UP;
7293 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7294 Determine whether it can be performed with a move instruction; if
7295 it can, convert inst.instruction to that move instruction and
7296 return TRUE; if it can't, convert inst.instruction to a literal-pool
7297 load and return FALSE. If this is not a valid thing to do in the
7298 current context, set inst.error and return TRUE.
7300 inst.operands[i] describes the destination register. */
7303 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7308 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7312 if ((inst.instruction & tbit) == 0)
7314 inst.error = _("invalid pseudo operation");
7317 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7319 inst.error = _("constant expression expected");
7322 if (inst.reloc.exp.X_op == O_constant)
7326 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7328 /* This can be done with a mov(1) instruction. */
7329 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7330 inst.instruction |= inst.reloc.exp.X_add_number;
7336 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7339 /* This can be done with a mov instruction. */
7340 inst.instruction &= LITERAL_MASK;
7341 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7342 inst.instruction |= value & 0xfff;
7346 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7349 /* This can be done with a mvn instruction. */
7350 inst.instruction &= LITERAL_MASK;
7351 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7352 inst.instruction |= value & 0xfff;
7358 if (add_to_lit_pool () == FAIL)
7360 inst.error = _("literal pool insertion failed");
7363 inst.operands[1].reg = REG_PC;
7364 inst.operands[1].isreg = 1;
7365 inst.operands[1].preind = 1;
7366 inst.reloc.pc_rel = 1;
7367 inst.reloc.type = (thumb_p
7368 ? BFD_RELOC_ARM_THUMB_OFFSET
7370 ? BFD_RELOC_ARM_HWLITERAL
7371 : BFD_RELOC_ARM_LITERAL));
7375 /* Functions for instruction encoding, sorted by sub-architecture.
7376 First some generics; their names are taken from the conventional
7377 bit positions for register arguments in ARM format instructions. */
7387 inst.instruction |= inst.operands[0].reg << 12;
7393 inst.instruction |= inst.operands[0].reg << 12;
7394 inst.instruction |= inst.operands[1].reg;
7400 inst.instruction |= inst.operands[0].reg;
7401 inst.instruction |= inst.operands[1].reg << 16;
7407 inst.instruction |= inst.operands[0].reg << 12;
7408 inst.instruction |= inst.operands[1].reg << 16;
7414 inst.instruction |= inst.operands[0].reg << 16;
7415 inst.instruction |= inst.operands[1].reg << 12;
7419 check_obsolete (const arm_feature_set *feature, const char *msg)
7421 if (ARM_CPU_IS_ANY (cpu_variant))
7423 as_warn ("%s", msg);
7426 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7438 unsigned Rn = inst.operands[2].reg;
7439 /* Enforce restrictions on SWP instruction. */
7440 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7442 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7443 _("Rn must not overlap other operands"));
7445 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7447 if (!check_obsolete (&arm_ext_v8,
7448 _("swp{b} use is obsoleted for ARMv8 and later"))
7449 && warn_on_deprecated
7450 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7451 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7454 inst.instruction |= inst.operands[0].reg << 12;
7455 inst.instruction |= inst.operands[1].reg;
7456 inst.instruction |= Rn << 16;
7462 inst.instruction |= inst.operands[0].reg << 12;
7463 inst.instruction |= inst.operands[1].reg << 16;
7464 inst.instruction |= inst.operands[2].reg;
7470 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7471 constraint (((inst.reloc.exp.X_op != O_constant
7472 && inst.reloc.exp.X_op != O_illegal)
7473 || inst.reloc.exp.X_add_number != 0),
7475 inst.instruction |= inst.operands[0].reg;
7476 inst.instruction |= inst.operands[1].reg << 12;
7477 inst.instruction |= inst.operands[2].reg << 16;
7483 inst.instruction |= inst.operands[0].imm;
7489 inst.instruction |= inst.operands[0].reg << 12;
7490 encode_arm_cp_address (1, TRUE, TRUE, 0);
7493 /* ARM instructions, in alphabetical order by function name (except
7494 that wrapper functions appear immediately after the function they
7497 /* This is a pseudo-op of the form "adr rd, label" to be converted
7498 into a relative address of the form "add rd, pc, #label-.-8". */
7503 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7505 /* Frag hacking will turn this into a sub instruction if the offset turns
7506 out to be negative. */
7507 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7508 inst.reloc.pc_rel = 1;
7509 inst.reloc.exp.X_add_number -= 8;
7512 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7513 into a relative address of the form:
7514 add rd, pc, #low(label-.-8)"
7515 add rd, rd, #high(label-.-8)" */
7520 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7522 /* Frag hacking will turn this into a sub instruction if the offset turns
7523 out to be negative. */
7524 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7525 inst.reloc.pc_rel = 1;
7526 inst.size = INSN_SIZE * 2;
7527 inst.reloc.exp.X_add_number -= 8;
7533 if (!inst.operands[1].present)
7534 inst.operands[1].reg = inst.operands[0].reg;
7535 inst.instruction |= inst.operands[0].reg << 12;
7536 inst.instruction |= inst.operands[1].reg << 16;
7537 encode_arm_shifter_operand (2);
7543 if (inst.operands[0].present)
7545 constraint ((inst.instruction & 0xf0) != 0x40
7546 && inst.operands[0].imm > 0xf
7547 && inst.operands[0].imm < 0x0,
7548 _("bad barrier type"));
7549 inst.instruction |= inst.operands[0].imm;
7552 inst.instruction |= 0xf;
7558 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7559 constraint (msb > 32, _("bit-field extends past end of register"));
7560 /* The instruction encoding stores the LSB and MSB,
7561 not the LSB and width. */
7562 inst.instruction |= inst.operands[0].reg << 12;
7563 inst.instruction |= inst.operands[1].imm << 7;
7564 inst.instruction |= (msb - 1) << 16;
7572 /* #0 in second position is alternative syntax for bfc, which is
7573 the same instruction but with REG_PC in the Rm field. */
7574 if (!inst.operands[1].isreg)
7575 inst.operands[1].reg = REG_PC;
7577 msb = inst.operands[2].imm + inst.operands[3].imm;
7578 constraint (msb > 32, _("bit-field extends past end of register"));
7579 /* The instruction encoding stores the LSB and MSB,
7580 not the LSB and width. */
7581 inst.instruction |= inst.operands[0].reg << 12;
7582 inst.instruction |= inst.operands[1].reg;
7583 inst.instruction |= inst.operands[2].imm << 7;
7584 inst.instruction |= (msb - 1) << 16;
7590 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7591 _("bit-field extends past end of register"));
7592 inst.instruction |= inst.operands[0].reg << 12;
7593 inst.instruction |= inst.operands[1].reg;
7594 inst.instruction |= inst.operands[2].imm << 7;
7595 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7598 /* ARM V5 breakpoint instruction (argument parse)
7599 BKPT <16 bit unsigned immediate>
7600 Instruction is not conditional.
7601 The bit pattern given in insns[] has the COND_ALWAYS condition,
7602 and it is an error if the caller tried to override that. */
7607 /* Top 12 of 16 bits to bits 19:8. */
7608 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7610 /* Bottom 4 of 16 bits to bits 3:0. */
7611 inst.instruction |= inst.operands[0].imm & 0xf;
7615 encode_branch (int default_reloc)
7617 if (inst.operands[0].hasreloc)
7619 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7620 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7621 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7622 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7623 ? BFD_RELOC_ARM_PLT32
7624 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7627 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7628 inst.reloc.pc_rel = 1;
7635 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7636 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7639 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7646 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7648 if (inst.cond == COND_ALWAYS)
7649 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7651 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7655 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7658 /* ARM V5 branch-link-exchange instruction (argument parse)
7659 BLX <target_addr> ie BLX(1)
7660 BLX{<condition>} <Rm> ie BLX(2)
7661 Unfortunately, there are two different opcodes for this mnemonic.
7662 So, the insns[].value is not used, and the code here zaps values
7663 into inst.instruction.
7664 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7669 if (inst.operands[0].isreg)
7671 /* Arg is a register; the opcode provided by insns[] is correct.
7672 It is not illegal to do "blx pc", just useless. */
7673 if (inst.operands[0].reg == REG_PC)
7674 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7676 inst.instruction |= inst.operands[0].reg;
7680 /* Arg is an address; this instruction cannot be executed
7681 conditionally, and the opcode must be adjusted.
7682 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7683 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7684 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7685 inst.instruction = 0xfa000000;
7686 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7693 bfd_boolean want_reloc;
7695 if (inst.operands[0].reg == REG_PC)
7696 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7698 inst.instruction |= inst.operands[0].reg;
7699 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7700 it is for ARMv4t or earlier. */
7701 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7702 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7706 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7711 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7715 /* ARM v5TEJ. Jump to Jazelle code. */
7720 if (inst.operands[0].reg == REG_PC)
7721 as_tsktsk (_("use of r15 in bxj is not really useful"));
7723 inst.instruction |= inst.operands[0].reg;
7726 /* Co-processor data operation:
7727 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7728 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7732 inst.instruction |= inst.operands[0].reg << 8;
7733 inst.instruction |= inst.operands[1].imm << 20;
7734 inst.instruction |= inst.operands[2].reg << 12;
7735 inst.instruction |= inst.operands[3].reg << 16;
7736 inst.instruction |= inst.operands[4].reg;
7737 inst.instruction |= inst.operands[5].imm << 5;
7743 inst.instruction |= inst.operands[0].reg << 16;
7744 encode_arm_shifter_operand (1);
7747 /* Transfer between coprocessor and ARM registers.
7748 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7753 No special properties. */
7755 struct deprecated_coproc_regs_s
7762 arm_feature_set deprecated;
7763 arm_feature_set obsoleted;
7764 const char *dep_msg;
7765 const char *obs_msg;
7768 #define DEPR_ACCESS_V8 \
7769 N_("This coprocessor register access is deprecated in ARMv8")
7771 /* Table of all deprecated coprocessor registers. */
7772 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7774 {15, 0, 7, 10, 5, /* CP15DMB. */
7775 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7776 DEPR_ACCESS_V8, NULL},
7777 {15, 0, 7, 10, 4, /* CP15DSB. */
7778 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7779 DEPR_ACCESS_V8, NULL},
7780 {15, 0, 7, 5, 4, /* CP15ISB. */
7781 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7782 DEPR_ACCESS_V8, NULL},
7783 {14, 6, 1, 0, 0, /* TEEHBR. */
7784 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7785 DEPR_ACCESS_V8, NULL},
7786 {14, 6, 0, 0, 0, /* TEECR. */
7787 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7788 DEPR_ACCESS_V8, NULL},
7791 #undef DEPR_ACCESS_V8
7793 static const size_t deprecated_coproc_reg_count =
7794 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7802 Rd = inst.operands[2].reg;
7805 if (inst.instruction == 0xee000010
7806 || inst.instruction == 0xfe000010)
7808 reject_bad_reg (Rd);
7811 constraint (Rd == REG_SP, BAD_SP);
7816 if (inst.instruction == 0xe000010)
7817 constraint (Rd == REG_PC, BAD_PC);
7820 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7822 const struct deprecated_coproc_regs_s *r =
7823 deprecated_coproc_regs + i;
7825 if (inst.operands[0].reg == r->cp
7826 && inst.operands[1].imm == r->opc1
7827 && inst.operands[3].reg == r->crn
7828 && inst.operands[4].reg == r->crm
7829 && inst.operands[5].imm == r->opc2)
7831 if (! ARM_CPU_IS_ANY (cpu_variant)
7832 && warn_on_deprecated
7833 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7834 as_warn ("%s", r->dep_msg);
7838 inst.instruction |= inst.operands[0].reg << 8;
7839 inst.instruction |= inst.operands[1].imm << 21;
7840 inst.instruction |= Rd << 12;
7841 inst.instruction |= inst.operands[3].reg << 16;
7842 inst.instruction |= inst.operands[4].reg;
7843 inst.instruction |= inst.operands[5].imm << 5;
7846 /* Transfer between coprocessor register and pair of ARM registers.
7847 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7852 Two XScale instructions are special cases of these:
7854 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7855 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7857 Result unpredictable if Rd or Rn is R15. */
7864 Rd = inst.operands[2].reg;
7865 Rn = inst.operands[3].reg;
7869 reject_bad_reg (Rd);
7870 reject_bad_reg (Rn);
7874 constraint (Rd == REG_PC, BAD_PC);
7875 constraint (Rn == REG_PC, BAD_PC);
7878 inst.instruction |= inst.operands[0].reg << 8;
7879 inst.instruction |= inst.operands[1].imm << 4;
7880 inst.instruction |= Rd << 12;
7881 inst.instruction |= Rn << 16;
7882 inst.instruction |= inst.operands[4].reg;
7888 inst.instruction |= inst.operands[0].imm << 6;
7889 if (inst.operands[1].present)
7891 inst.instruction |= CPSI_MMOD;
7892 inst.instruction |= inst.operands[1].imm;
7899 inst.instruction |= inst.operands[0].imm;
7905 unsigned Rd, Rn, Rm;
7907 Rd = inst.operands[0].reg;
7908 Rn = (inst.operands[1].present
7909 ? inst.operands[1].reg : Rd);
7910 Rm = inst.operands[2].reg;
7912 constraint ((Rd == REG_PC), BAD_PC);
7913 constraint ((Rn == REG_PC), BAD_PC);
7914 constraint ((Rm == REG_PC), BAD_PC);
7916 inst.instruction |= Rd << 16;
7917 inst.instruction |= Rn << 0;
7918 inst.instruction |= Rm << 8;
7924 /* There is no IT instruction in ARM mode. We
7925 process it to do the validation as if in
7926 thumb mode, just in case the code gets
7927 assembled for thumb using the unified syntax. */
7932 set_it_insn_type (IT_INSN);
7933 now_it.mask = (inst.instruction & 0xf) | 0x10;
7934 now_it.cc = inst.operands[0].imm;
7938 /* If there is only one register in the register list,
7939 then return its register number. Otherwise return -1. */
7941 only_one_reg_in_list (int range)
7943 int i = ffs (range) - 1;
7944 return (i > 15 || range != (1 << i)) ? -1 : i;
7948 encode_ldmstm(int from_push_pop_mnem)
7950 int base_reg = inst.operands[0].reg;
7951 int range = inst.operands[1].imm;
7954 inst.instruction |= base_reg << 16;
7955 inst.instruction |= range;
7957 if (inst.operands[1].writeback)
7958 inst.instruction |= LDM_TYPE_2_OR_3;
7960 if (inst.operands[0].writeback)
7962 inst.instruction |= WRITE_BACK;
7963 /* Check for unpredictable uses of writeback. */
7964 if (inst.instruction & LOAD_BIT)
7966 /* Not allowed in LDM type 2. */
7967 if ((inst.instruction & LDM_TYPE_2_OR_3)
7968 && ((range & (1 << REG_PC)) == 0))
7969 as_warn (_("writeback of base register is UNPREDICTABLE"));
7970 /* Only allowed if base reg not in list for other types. */
7971 else if (range & (1 << base_reg))
7972 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7976 /* Not allowed for type 2. */
7977 if (inst.instruction & LDM_TYPE_2_OR_3)
7978 as_warn (_("writeback of base register is UNPREDICTABLE"));
7979 /* Only allowed if base reg not in list, or first in list. */
7980 else if ((range & (1 << base_reg))
7981 && (range & ((1 << base_reg) - 1)))
7982 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7986 /* If PUSH/POP has only one register, then use the A2 encoding. */
7987 one_reg = only_one_reg_in_list (range);
7988 if (from_push_pop_mnem && one_reg >= 0)
7990 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7992 inst.instruction &= A_COND_MASK;
7993 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7994 inst.instruction |= one_reg << 12;
8001 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
8004 /* ARMv5TE load-consecutive (argument parse)
8013 constraint (inst.operands[0].reg % 2 != 0,
8014 _("first transfer register must be even"));
8015 constraint (inst.operands[1].present
8016 && inst.operands[1].reg != inst.operands[0].reg + 1,
8017 _("can only transfer two consecutive registers"));
8018 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8019 constraint (!inst.operands[2].isreg, _("'[' expected"));
8021 if (!inst.operands[1].present)
8022 inst.operands[1].reg = inst.operands[0].reg + 1;
8024 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8025 register and the first register written; we have to diagnose
8026 overlap between the base and the second register written here. */
8028 if (inst.operands[2].reg == inst.operands[1].reg
8029 && (inst.operands[2].writeback || inst.operands[2].postind))
8030 as_warn (_("base register written back, and overlaps "
8031 "second transfer register"));
8033 if (!(inst.instruction & V4_STR_BIT))
8035 /* For an index-register load, the index register must not overlap the
8036 destination (even if not write-back). */
8037 if (inst.operands[2].immisreg
8038 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8039 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8040 as_warn (_("index register overlaps transfer register"));
8042 inst.instruction |= inst.operands[0].reg << 12;
8043 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8049 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8050 || inst.operands[1].postind || inst.operands[1].writeback
8051 || inst.operands[1].immisreg || inst.operands[1].shifted
8052 || inst.operands[1].negative
8053 /* This can arise if the programmer has written
8055 or if they have mistakenly used a register name as the last
8058 It is very difficult to distinguish between these two cases
8059 because "rX" might actually be a label. ie the register
8060 name has been occluded by a symbol of the same name. So we
8061 just generate a general 'bad addressing mode' type error
8062 message and leave it up to the programmer to discover the
8063 true cause and fix their mistake. */
8064 || (inst.operands[1].reg == REG_PC),
8067 constraint (inst.reloc.exp.X_op != O_constant
8068 || inst.reloc.exp.X_add_number != 0,
8069 _("offset must be zero in ARM encoding"));
8071 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8073 inst.instruction |= inst.operands[0].reg << 12;
8074 inst.instruction |= inst.operands[1].reg << 16;
8075 inst.reloc.type = BFD_RELOC_UNUSED;
8081 constraint (inst.operands[0].reg % 2 != 0,
8082 _("even register required"));
8083 constraint (inst.operands[1].present
8084 && inst.operands[1].reg != inst.operands[0].reg + 1,
8085 _("can only load two consecutive registers"));
8086 /* If op 1 were present and equal to PC, this function wouldn't
8087 have been called in the first place. */
8088 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8090 inst.instruction |= inst.operands[0].reg << 12;
8091 inst.instruction |= inst.operands[2].reg << 16;
8094 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8095 which is not a multiple of four is UNPREDICTABLE. */
8097 check_ldr_r15_aligned (void)
8099 constraint (!(inst.operands[1].immisreg)
8100 && (inst.operands[0].reg == REG_PC
8101 && inst.operands[1].reg == REG_PC
8102 && (inst.reloc.exp.X_add_number & 0x3)),
8103 _("ldr to register 15 must be 4-byte alligned"));
8109 inst.instruction |= inst.operands[0].reg << 12;
8110 if (!inst.operands[1].isreg)
8111 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8113 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8114 check_ldr_r15_aligned ();
8120 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8122 if (inst.operands[1].preind)
8124 constraint (inst.reloc.exp.X_op != O_constant
8125 || inst.reloc.exp.X_add_number != 0,
8126 _("this instruction requires a post-indexed address"));
8128 inst.operands[1].preind = 0;
8129 inst.operands[1].postind = 1;
8130 inst.operands[1].writeback = 1;
8132 inst.instruction |= inst.operands[0].reg << 12;
8133 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8136 /* Halfword and signed-byte load/store operations. */
8141 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8142 inst.instruction |= inst.operands[0].reg << 12;
8143 if (!inst.operands[1].isreg)
8144 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8146 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8152 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8154 if (inst.operands[1].preind)
8156 constraint (inst.reloc.exp.X_op != O_constant
8157 || inst.reloc.exp.X_add_number != 0,
8158 _("this instruction requires a post-indexed address"));
8160 inst.operands[1].preind = 0;
8161 inst.operands[1].postind = 1;
8162 inst.operands[1].writeback = 1;
8164 inst.instruction |= inst.operands[0].reg << 12;
8165 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8168 /* Co-processor register load/store.
8169 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8173 inst.instruction |= inst.operands[0].reg << 8;
8174 inst.instruction |= inst.operands[1].reg << 12;
8175 encode_arm_cp_address (2, TRUE, TRUE, 0);
8181 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8182 if (inst.operands[0].reg == inst.operands[1].reg
8183 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8184 && !(inst.instruction & 0x00400000))
8185 as_tsktsk (_("Rd and Rm should be different in mla"));
8187 inst.instruction |= inst.operands[0].reg << 16;
8188 inst.instruction |= inst.operands[1].reg;
8189 inst.instruction |= inst.operands[2].reg << 8;
8190 inst.instruction |= inst.operands[3].reg << 12;
8196 inst.instruction |= inst.operands[0].reg << 12;
8197 encode_arm_shifter_operand (1);
8200 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8207 top = (inst.instruction & 0x00400000) != 0;
8208 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8209 _(":lower16: not allowed this instruction"));
8210 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8211 _(":upper16: not allowed instruction"));
8212 inst.instruction |= inst.operands[0].reg << 12;
8213 if (inst.reloc.type == BFD_RELOC_UNUSED)
8215 imm = inst.reloc.exp.X_add_number;
8216 /* The value is in two pieces: 0:11, 16:19. */
8217 inst.instruction |= (imm & 0x00000fff);
8218 inst.instruction |= (imm & 0x0000f000) << 4;
8222 static void do_vfp_nsyn_opcode (const char *);
8225 do_vfp_nsyn_mrs (void)
8227 if (inst.operands[0].isvec)
8229 if (inst.operands[1].reg != 1)
8230 first_error (_("operand 1 must be FPSCR"));
8231 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8232 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8233 do_vfp_nsyn_opcode ("fmstat");
8235 else if (inst.operands[1].isvec)
8236 do_vfp_nsyn_opcode ("fmrx");
8244 do_vfp_nsyn_msr (void)
8246 if (inst.operands[0].isvec)
8247 do_vfp_nsyn_opcode ("fmxr");
8257 unsigned Rt = inst.operands[0].reg;
8259 if (thumb_mode && inst.operands[0].reg == REG_SP)
8261 inst.error = BAD_SP;
8265 /* APSR_ sets isvec. All other refs to PC are illegal. */
8266 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8268 inst.error = BAD_PC;
8272 switch (inst.operands[1].reg)
8279 inst.instruction |= (inst.operands[1].reg << 16);
8282 first_error (_("operand 1 must be a VFP extension System Register"));
8285 inst.instruction |= (Rt << 12);
8291 unsigned Rt = inst.operands[1].reg;
8294 reject_bad_reg (Rt);
8295 else if (Rt == REG_PC)
8297 inst.error = BAD_PC;
8301 switch (inst.operands[0].reg)
8306 inst.instruction |= (inst.operands[0].reg << 16);
8309 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8312 inst.instruction |= (Rt << 12);
8320 if (do_vfp_nsyn_mrs () == SUCCESS)
8323 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8324 inst.instruction |= inst.operands[0].reg << 12;
8326 if (inst.operands[1].isreg)
8328 br = inst.operands[1].reg;
8329 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8330 as_bad (_("bad register for mrs"));
8334 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8335 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8337 _("'APSR', 'CPSR' or 'SPSR' expected"));
8338 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8341 inst.instruction |= br;
8344 /* Two possible forms:
8345 "{C|S}PSR_<field>, Rm",
8346 "{C|S}PSR_f, #expression". */
8351 if (do_vfp_nsyn_msr () == SUCCESS)
8354 inst.instruction |= inst.operands[0].imm;
8355 if (inst.operands[1].isreg)
8356 inst.instruction |= inst.operands[1].reg;
8359 inst.instruction |= INST_IMMEDIATE;
8360 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8361 inst.reloc.pc_rel = 0;
8368 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8370 if (!inst.operands[2].present)
8371 inst.operands[2].reg = inst.operands[0].reg;
8372 inst.instruction |= inst.operands[0].reg << 16;
8373 inst.instruction |= inst.operands[1].reg;
8374 inst.instruction |= inst.operands[2].reg << 8;
8376 if (inst.operands[0].reg == inst.operands[1].reg
8377 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8378 as_tsktsk (_("Rd and Rm should be different in mul"));
8381 /* Long Multiply Parser
8382 UMULL RdLo, RdHi, Rm, Rs
8383 SMULL RdLo, RdHi, Rm, Rs
8384 UMLAL RdLo, RdHi, Rm, Rs
8385 SMLAL RdLo, RdHi, Rm, Rs. */
8390 inst.instruction |= inst.operands[0].reg << 12;
8391 inst.instruction |= inst.operands[1].reg << 16;
8392 inst.instruction |= inst.operands[2].reg;
8393 inst.instruction |= inst.operands[3].reg << 8;
8395 /* rdhi and rdlo must be different. */
8396 if (inst.operands[0].reg == inst.operands[1].reg)
8397 as_tsktsk (_("rdhi and rdlo must be different"));
8399 /* rdhi, rdlo and rm must all be different before armv6. */
8400 if ((inst.operands[0].reg == inst.operands[2].reg
8401 || inst.operands[1].reg == inst.operands[2].reg)
8402 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8403 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8409 if (inst.operands[0].present
8410 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8412 /* Architectural NOP hints are CPSR sets with no bits selected. */
8413 inst.instruction &= 0xf0000000;
8414 inst.instruction |= 0x0320f000;
8415 if (inst.operands[0].present)
8416 inst.instruction |= inst.operands[0].imm;
8420 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8421 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8422 Condition defaults to COND_ALWAYS.
8423 Error if Rd, Rn or Rm are R15. */
8428 inst.instruction |= inst.operands[0].reg << 12;
8429 inst.instruction |= inst.operands[1].reg << 16;
8430 inst.instruction |= inst.operands[2].reg;
8431 if (inst.operands[3].present)
8432 encode_arm_shift (3);
8435 /* ARM V6 PKHTB (Argument Parse). */
8440 if (!inst.operands[3].present)
8442 /* If the shift specifier is omitted, turn the instruction
8443 into pkhbt rd, rm, rn. */
8444 inst.instruction &= 0xfff00010;
8445 inst.instruction |= inst.operands[0].reg << 12;
8446 inst.instruction |= inst.operands[1].reg;
8447 inst.instruction |= inst.operands[2].reg << 16;
8451 inst.instruction |= inst.operands[0].reg << 12;
8452 inst.instruction |= inst.operands[1].reg << 16;
8453 inst.instruction |= inst.operands[2].reg;
8454 encode_arm_shift (3);
8458 /* ARMv5TE: Preload-Cache
8459 MP Extensions: Preload for write
8463 Syntactically, like LDR with B=1, W=0, L=1. */
8468 constraint (!inst.operands[0].isreg,
8469 _("'[' expected after PLD mnemonic"));
8470 constraint (inst.operands[0].postind,
8471 _("post-indexed expression used in preload instruction"));
8472 constraint (inst.operands[0].writeback,
8473 _("writeback used in preload instruction"));
8474 constraint (!inst.operands[0].preind,
8475 _("unindexed addressing used in preload instruction"));
8476 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8479 /* ARMv7: PLI <addr_mode> */
8483 constraint (!inst.operands[0].isreg,
8484 _("'[' expected after PLI mnemonic"));
8485 constraint (inst.operands[0].postind,
8486 _("post-indexed expression used in preload instruction"));
8487 constraint (inst.operands[0].writeback,
8488 _("writeback used in preload instruction"));
8489 constraint (!inst.operands[0].preind,
8490 _("unindexed addressing used in preload instruction"));
8491 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8492 inst.instruction &= ~PRE_INDEX;
8498 inst.operands[1] = inst.operands[0];
8499 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8500 inst.operands[0].isreg = 1;
8501 inst.operands[0].writeback = 1;
8502 inst.operands[0].reg = REG_SP;
8503 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8506 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8507 word at the specified address and the following word
8509 Unconditionally executed.
8510 Error if Rn is R15. */
8515 inst.instruction |= inst.operands[0].reg << 16;
8516 if (inst.operands[0].writeback)
8517 inst.instruction |= WRITE_BACK;
8520 /* ARM V6 ssat (argument parse). */
8525 inst.instruction |= inst.operands[0].reg << 12;
8526 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8527 inst.instruction |= inst.operands[2].reg;
8529 if (inst.operands[3].present)
8530 encode_arm_shift (3);
8533 /* ARM V6 usat (argument parse). */
8538 inst.instruction |= inst.operands[0].reg << 12;
8539 inst.instruction |= inst.operands[1].imm << 16;
8540 inst.instruction |= inst.operands[2].reg;
8542 if (inst.operands[3].present)
8543 encode_arm_shift (3);
8546 /* ARM V6 ssat16 (argument parse). */
8551 inst.instruction |= inst.operands[0].reg << 12;
8552 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8553 inst.instruction |= inst.operands[2].reg;
8559 inst.instruction |= inst.operands[0].reg << 12;
8560 inst.instruction |= inst.operands[1].imm << 16;
8561 inst.instruction |= inst.operands[2].reg;
8564 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8565 preserving the other bits.
8567 setend <endian_specifier>, where <endian_specifier> is either
8573 if (warn_on_deprecated
8574 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8575 as_warn (_("setend use is deprecated for ARMv8"));
8577 if (inst.operands[0].imm)
8578 inst.instruction |= 0x200;
8584 unsigned int Rm = (inst.operands[1].present
8585 ? inst.operands[1].reg
8586 : inst.operands[0].reg);
8588 inst.instruction |= inst.operands[0].reg << 12;
8589 inst.instruction |= Rm;
8590 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8592 inst.instruction |= inst.operands[2].reg << 8;
8593 inst.instruction |= SHIFT_BY_REG;
8594 /* PR 12854: Error on extraneous shifts. */
8595 constraint (inst.operands[2].shifted,
8596 _("extraneous shift as part of operand to shift insn"));
8599 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8605 inst.reloc.type = BFD_RELOC_ARM_SMC;
8606 inst.reloc.pc_rel = 0;
8612 inst.reloc.type = BFD_RELOC_ARM_HVC;
8613 inst.reloc.pc_rel = 0;
8619 inst.reloc.type = BFD_RELOC_ARM_SWI;
8620 inst.reloc.pc_rel = 0;
8623 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8624 SMLAxy{cond} Rd,Rm,Rs,Rn
8625 SMLAWy{cond} Rd,Rm,Rs,Rn
8626 Error if any register is R15. */
8631 inst.instruction |= inst.operands[0].reg << 16;
8632 inst.instruction |= inst.operands[1].reg;
8633 inst.instruction |= inst.operands[2].reg << 8;
8634 inst.instruction |= inst.operands[3].reg << 12;
8637 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8638 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8639 Error if any register is R15.
8640 Warning if Rdlo == Rdhi. */
8645 inst.instruction |= inst.operands[0].reg << 12;
8646 inst.instruction |= inst.operands[1].reg << 16;
8647 inst.instruction |= inst.operands[2].reg;
8648 inst.instruction |= inst.operands[3].reg << 8;
8650 if (inst.operands[0].reg == inst.operands[1].reg)
8651 as_tsktsk (_("rdhi and rdlo must be different"));
8654 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8655 SMULxy{cond} Rd,Rm,Rs
8656 Error if any register is R15. */
8661 inst.instruction |= inst.operands[0].reg << 16;
8662 inst.instruction |= inst.operands[1].reg;
8663 inst.instruction |= inst.operands[2].reg << 8;
8666 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8667 the same for both ARM and Thumb-2. */
8674 if (inst.operands[0].present)
8676 reg = inst.operands[0].reg;
8677 constraint (reg != REG_SP, _("SRS base register must be r13"));
8682 inst.instruction |= reg << 16;
8683 inst.instruction |= inst.operands[1].imm;
8684 if (inst.operands[0].writeback || inst.operands[1].writeback)
8685 inst.instruction |= WRITE_BACK;
8688 /* ARM V6 strex (argument parse). */
8693 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8694 || inst.operands[2].postind || inst.operands[2].writeback
8695 || inst.operands[2].immisreg || inst.operands[2].shifted
8696 || inst.operands[2].negative
8697 /* See comment in do_ldrex(). */
8698 || (inst.operands[2].reg == REG_PC),
8701 constraint (inst.operands[0].reg == inst.operands[1].reg
8702 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8704 constraint (inst.reloc.exp.X_op != O_constant
8705 || inst.reloc.exp.X_add_number != 0,
8706 _("offset must be zero in ARM encoding"));
8708 inst.instruction |= inst.operands[0].reg << 12;
8709 inst.instruction |= inst.operands[1].reg;
8710 inst.instruction |= inst.operands[2].reg << 16;
8711 inst.reloc.type = BFD_RELOC_UNUSED;
8717 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8718 || inst.operands[2].postind || inst.operands[2].writeback
8719 || inst.operands[2].immisreg || inst.operands[2].shifted
8720 || inst.operands[2].negative,
8723 constraint (inst.operands[0].reg == inst.operands[1].reg
8724 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8732 constraint (inst.operands[1].reg % 2 != 0,
8733 _("even register required"));
8734 constraint (inst.operands[2].present
8735 && inst.operands[2].reg != inst.operands[1].reg + 1,
8736 _("can only store two consecutive registers"));
8737 /* If op 2 were present and equal to PC, this function wouldn't
8738 have been called in the first place. */
8739 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8741 constraint (inst.operands[0].reg == inst.operands[1].reg
8742 || inst.operands[0].reg == inst.operands[1].reg + 1
8743 || inst.operands[0].reg == inst.operands[3].reg,
8746 inst.instruction |= inst.operands[0].reg << 12;
8747 inst.instruction |= inst.operands[1].reg;
8748 inst.instruction |= inst.operands[3].reg << 16;
8755 constraint (inst.operands[0].reg == inst.operands[1].reg
8756 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8764 constraint (inst.operands[0].reg == inst.operands[1].reg
8765 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8770 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8771 extends it to 32-bits, and adds the result to a value in another
8772 register. You can specify a rotation by 0, 8, 16, or 24 bits
8773 before extracting the 16-bit value.
8774 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8775 Condition defaults to COND_ALWAYS.
8776 Error if any register uses R15. */
8781 inst.instruction |= inst.operands[0].reg << 12;
8782 inst.instruction |= inst.operands[1].reg << 16;
8783 inst.instruction |= inst.operands[2].reg;
8784 inst.instruction |= inst.operands[3].imm << 10;
8789 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8790 Condition defaults to COND_ALWAYS.
8791 Error if any register uses R15. */
8796 inst.instruction |= inst.operands[0].reg << 12;
8797 inst.instruction |= inst.operands[1].reg;
8798 inst.instruction |= inst.operands[2].imm << 10;
8801 /* VFP instructions. In a logical order: SP variant first, monad
8802 before dyad, arithmetic then move then load/store. */
8805 do_vfp_sp_monadic (void)
8807 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8808 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8812 do_vfp_sp_dyadic (void)
8814 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8815 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8816 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8820 do_vfp_sp_compare_z (void)
8822 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8826 do_vfp_dp_sp_cvt (void)
8828 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8829 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8833 do_vfp_sp_dp_cvt (void)
8835 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8836 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8840 do_vfp_reg_from_sp (void)
8842 inst.instruction |= inst.operands[0].reg << 12;
8843 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8847 do_vfp_reg2_from_sp2 (void)
8849 constraint (inst.operands[2].imm != 2,
8850 _("only two consecutive VFP SP registers allowed here"));
8851 inst.instruction |= inst.operands[0].reg << 12;
8852 inst.instruction |= inst.operands[1].reg << 16;
8853 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8857 do_vfp_sp_from_reg (void)
8859 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8860 inst.instruction |= inst.operands[1].reg << 12;
8864 do_vfp_sp2_from_reg2 (void)
8866 constraint (inst.operands[0].imm != 2,
8867 _("only two consecutive VFP SP registers allowed here"));
8868 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8869 inst.instruction |= inst.operands[1].reg << 12;
8870 inst.instruction |= inst.operands[2].reg << 16;
8874 do_vfp_sp_ldst (void)
8876 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8877 encode_arm_cp_address (1, FALSE, TRUE, 0);
8881 do_vfp_dp_ldst (void)
8883 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8884 encode_arm_cp_address (1, FALSE, TRUE, 0);
8889 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8891 if (inst.operands[0].writeback)
8892 inst.instruction |= WRITE_BACK;
8894 constraint (ldstm_type != VFP_LDSTMIA,
8895 _("this addressing mode requires base-register writeback"));
8896 inst.instruction |= inst.operands[0].reg << 16;
8897 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8898 inst.instruction |= inst.operands[1].imm;
8902 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8906 if (inst.operands[0].writeback)
8907 inst.instruction |= WRITE_BACK;
8909 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8910 _("this addressing mode requires base-register writeback"));
8912 inst.instruction |= inst.operands[0].reg << 16;
8913 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8915 count = inst.operands[1].imm << 1;
8916 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8919 inst.instruction |= count;
8923 do_vfp_sp_ldstmia (void)
8925 vfp_sp_ldstm (VFP_LDSTMIA);
8929 do_vfp_sp_ldstmdb (void)
8931 vfp_sp_ldstm (VFP_LDSTMDB);
8935 do_vfp_dp_ldstmia (void)
8937 vfp_dp_ldstm (VFP_LDSTMIA);
8941 do_vfp_dp_ldstmdb (void)
8943 vfp_dp_ldstm (VFP_LDSTMDB);
8947 do_vfp_xp_ldstmia (void)
8949 vfp_dp_ldstm (VFP_LDSTMIAX);
8953 do_vfp_xp_ldstmdb (void)
8955 vfp_dp_ldstm (VFP_LDSTMDBX);
8959 do_vfp_dp_rd_rm (void)
8961 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8962 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8966 do_vfp_dp_rn_rd (void)
8968 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8969 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8973 do_vfp_dp_rd_rn (void)
8975 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8976 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8980 do_vfp_dp_rd_rn_rm (void)
8982 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8983 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8984 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8990 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8994 do_vfp_dp_rm_rd_rn (void)
8996 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8997 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8998 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
9001 /* VFPv3 instructions. */
9003 do_vfp_sp_const (void)
9005 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9006 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9007 inst.instruction |= (inst.operands[1].imm & 0x0f);
9011 do_vfp_dp_const (void)
9013 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9014 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9015 inst.instruction |= (inst.operands[1].imm & 0x0f);
9019 vfp_conv (int srcsize)
9021 int immbits = srcsize - inst.operands[1].imm;
9023 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9025 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9026 i.e. immbits must be in range 0 - 16. */
9027 inst.error = _("immediate value out of range, expected range [0, 16]");
9030 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9032 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9033 i.e. immbits must be in range 0 - 31. */
9034 inst.error = _("immediate value out of range, expected range [1, 32]");
9038 inst.instruction |= (immbits & 1) << 5;
9039 inst.instruction |= (immbits >> 1);
9043 do_vfp_sp_conv_16 (void)
9045 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9050 do_vfp_dp_conv_16 (void)
9052 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9057 do_vfp_sp_conv_32 (void)
9059 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9064 do_vfp_dp_conv_32 (void)
9066 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9070 /* FPA instructions. Also in a logical order. */
9075 inst.instruction |= inst.operands[0].reg << 16;
9076 inst.instruction |= inst.operands[1].reg;
9080 do_fpa_ldmstm (void)
9082 inst.instruction |= inst.operands[0].reg << 12;
9083 switch (inst.operands[1].imm)
9085 case 1: inst.instruction |= CP_T_X; break;
9086 case 2: inst.instruction |= CP_T_Y; break;
9087 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9092 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9094 /* The instruction specified "ea" or "fd", so we can only accept
9095 [Rn]{!}. The instruction does not really support stacking or
9096 unstacking, so we have to emulate these by setting appropriate
9097 bits and offsets. */
9098 constraint (inst.reloc.exp.X_op != O_constant
9099 || inst.reloc.exp.X_add_number != 0,
9100 _("this instruction does not support indexing"));
9102 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9103 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9105 if (!(inst.instruction & INDEX_UP))
9106 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9108 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9110 inst.operands[2].preind = 0;
9111 inst.operands[2].postind = 1;
9115 encode_arm_cp_address (2, TRUE, TRUE, 0);
9118 /* iWMMXt instructions: strictly in alphabetical order. */
9121 do_iwmmxt_tandorc (void)
9123 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9127 do_iwmmxt_textrc (void)
9129 inst.instruction |= inst.operands[0].reg << 12;
9130 inst.instruction |= inst.operands[1].imm;
9134 do_iwmmxt_textrm (void)
9136 inst.instruction |= inst.operands[0].reg << 12;
9137 inst.instruction |= inst.operands[1].reg << 16;
9138 inst.instruction |= inst.operands[2].imm;
9142 do_iwmmxt_tinsr (void)
9144 inst.instruction |= inst.operands[0].reg << 16;
9145 inst.instruction |= inst.operands[1].reg << 12;
9146 inst.instruction |= inst.operands[2].imm;
9150 do_iwmmxt_tmia (void)
9152 inst.instruction |= inst.operands[0].reg << 5;
9153 inst.instruction |= inst.operands[1].reg;
9154 inst.instruction |= inst.operands[2].reg << 12;
9158 do_iwmmxt_waligni (void)
9160 inst.instruction |= inst.operands[0].reg << 12;
9161 inst.instruction |= inst.operands[1].reg << 16;
9162 inst.instruction |= inst.operands[2].reg;
9163 inst.instruction |= inst.operands[3].imm << 20;
9167 do_iwmmxt_wmerge (void)
9169 inst.instruction |= inst.operands[0].reg << 12;
9170 inst.instruction |= inst.operands[1].reg << 16;
9171 inst.instruction |= inst.operands[2].reg;
9172 inst.instruction |= inst.operands[3].imm << 21;
9176 do_iwmmxt_wmov (void)
9178 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9179 inst.instruction |= inst.operands[0].reg << 12;
9180 inst.instruction |= inst.operands[1].reg << 16;
9181 inst.instruction |= inst.operands[1].reg;
9185 do_iwmmxt_wldstbh (void)
9188 inst.instruction |= inst.operands[0].reg << 12;
9190 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9192 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9193 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9197 do_iwmmxt_wldstw (void)
9199 /* RIWR_RIWC clears .isreg for a control register. */
9200 if (!inst.operands[0].isreg)
9202 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9203 inst.instruction |= 0xf0000000;
9206 inst.instruction |= inst.operands[0].reg << 12;
9207 encode_arm_cp_address (1, TRUE, TRUE, 0);
9211 do_iwmmxt_wldstd (void)
9213 inst.instruction |= inst.operands[0].reg << 12;
9214 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9215 && inst.operands[1].immisreg)
9217 inst.instruction &= ~0x1a000ff;
9218 inst.instruction |= (0xf << 28);
9219 if (inst.operands[1].preind)
9220 inst.instruction |= PRE_INDEX;
9221 if (!inst.operands[1].negative)
9222 inst.instruction |= INDEX_UP;
9223 if (inst.operands[1].writeback)
9224 inst.instruction |= WRITE_BACK;
9225 inst.instruction |= inst.operands[1].reg << 16;
9226 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9227 inst.instruction |= inst.operands[1].imm;
9230 encode_arm_cp_address (1, TRUE, FALSE, 0);
9234 do_iwmmxt_wshufh (void)
9236 inst.instruction |= inst.operands[0].reg << 12;
9237 inst.instruction |= inst.operands[1].reg << 16;
9238 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9239 inst.instruction |= (inst.operands[2].imm & 0x0f);
9243 do_iwmmxt_wzero (void)
9245 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9246 inst.instruction |= inst.operands[0].reg;
9247 inst.instruction |= inst.operands[0].reg << 12;
9248 inst.instruction |= inst.operands[0].reg << 16;
9252 do_iwmmxt_wrwrwr_or_imm5 (void)
9254 if (inst.operands[2].isreg)
9257 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9258 _("immediate operand requires iWMMXt2"));
9260 if (inst.operands[2].imm == 0)
9262 switch ((inst.instruction >> 20) & 0xf)
9268 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9269 inst.operands[2].imm = 16;
9270 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9276 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9277 inst.operands[2].imm = 32;
9278 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9285 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9287 wrn = (inst.instruction >> 16) & 0xf;
9288 inst.instruction &= 0xff0fff0f;
9289 inst.instruction |= wrn;
9290 /* Bail out here; the instruction is now assembled. */
9295 /* Map 32 -> 0, etc. */
9296 inst.operands[2].imm &= 0x1f;
9297 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9301 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9302 operations first, then control, shift, and load/store. */
9304 /* Insns like "foo X,Y,Z". */
9307 do_mav_triple (void)
9309 inst.instruction |= inst.operands[0].reg << 16;
9310 inst.instruction |= inst.operands[1].reg;
9311 inst.instruction |= inst.operands[2].reg << 12;
9314 /* Insns like "foo W,X,Y,Z".
9315 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9320 inst.instruction |= inst.operands[0].reg << 5;
9321 inst.instruction |= inst.operands[1].reg << 12;
9322 inst.instruction |= inst.operands[2].reg << 16;
9323 inst.instruction |= inst.operands[3].reg;
9326 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9330 inst.instruction |= inst.operands[1].reg << 12;
9333 /* Maverick shift immediate instructions.
9334 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9335 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9340 int imm = inst.operands[2].imm;
9342 inst.instruction |= inst.operands[0].reg << 12;
9343 inst.instruction |= inst.operands[1].reg << 16;
9345 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9346 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9347 Bit 4 should be 0. */
9348 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9350 inst.instruction |= imm;
9353 /* XScale instructions. Also sorted arithmetic before move. */
9355 /* Xscale multiply-accumulate (argument parse)
9358 MIAxycc acc0,Rm,Rs. */
9363 inst.instruction |= inst.operands[1].reg;
9364 inst.instruction |= inst.operands[2].reg << 12;
9367 /* Xscale move-accumulator-register (argument parse)
9369 MARcc acc0,RdLo,RdHi. */
9374 inst.instruction |= inst.operands[1].reg << 12;
9375 inst.instruction |= inst.operands[2].reg << 16;
9378 /* Xscale move-register-accumulator (argument parse)
9380 MRAcc RdLo,RdHi,acc0. */
9385 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9386 inst.instruction |= inst.operands[0].reg << 12;
9387 inst.instruction |= inst.operands[1].reg << 16;
9390 /* Encoding functions relevant only to Thumb. */
9392 /* inst.operands[i] is a shifted-register operand; encode
9393 it into inst.instruction in the format used by Thumb32. */
9396 encode_thumb32_shifted_operand (int i)
9398 unsigned int value = inst.reloc.exp.X_add_number;
9399 unsigned int shift = inst.operands[i].shift_kind;
9401 constraint (inst.operands[i].immisreg,
9402 _("shift by register not allowed in thumb mode"));
9403 inst.instruction |= inst.operands[i].reg;
9404 if (shift == SHIFT_RRX)
9405 inst.instruction |= SHIFT_ROR << 4;
9408 constraint (inst.reloc.exp.X_op != O_constant,
9409 _("expression too complex"));
9411 constraint (value > 32
9412 || (value == 32 && (shift == SHIFT_LSL
9413 || shift == SHIFT_ROR)),
9414 _("shift expression is too large"));
9418 else if (value == 32)
9421 inst.instruction |= shift << 4;
9422 inst.instruction |= (value & 0x1c) << 10;
9423 inst.instruction |= (value & 0x03) << 6;
9428 /* inst.operands[i] was set up by parse_address. Encode it into a
9429 Thumb32 format load or store instruction. Reject forms that cannot
9430 be used with such instructions. If is_t is true, reject forms that
9431 cannot be used with a T instruction; if is_d is true, reject forms
9432 that cannot be used with a D instruction. If it is a store insn,
9436 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9438 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9440 constraint (!inst.operands[i].isreg,
9441 _("Instruction does not support =N addresses"));
9443 inst.instruction |= inst.operands[i].reg << 16;
9444 if (inst.operands[i].immisreg)
9446 constraint (is_pc, BAD_PC_ADDRESSING);
9447 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9448 constraint (inst.operands[i].negative,
9449 _("Thumb does not support negative register indexing"));
9450 constraint (inst.operands[i].postind,
9451 _("Thumb does not support register post-indexing"));
9452 constraint (inst.operands[i].writeback,
9453 _("Thumb does not support register indexing with writeback"));
9454 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9455 _("Thumb supports only LSL in shifted register indexing"));
9457 inst.instruction |= inst.operands[i].imm;
9458 if (inst.operands[i].shifted)
9460 constraint (inst.reloc.exp.X_op != O_constant,
9461 _("expression too complex"));
9462 constraint (inst.reloc.exp.X_add_number < 0
9463 || inst.reloc.exp.X_add_number > 3,
9464 _("shift out of range"));
9465 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9467 inst.reloc.type = BFD_RELOC_UNUSED;
9469 else if (inst.operands[i].preind)
9471 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9472 constraint (is_t && inst.operands[i].writeback,
9473 _("cannot use writeback with this instruction"));
9474 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
9479 inst.instruction |= 0x01000000;
9480 if (inst.operands[i].writeback)
9481 inst.instruction |= 0x00200000;
9485 inst.instruction |= 0x00000c00;
9486 if (inst.operands[i].writeback)
9487 inst.instruction |= 0x00000100;
9489 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9491 else if (inst.operands[i].postind)
9493 gas_assert (inst.operands[i].writeback);
9494 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9495 constraint (is_t, _("cannot use post-indexing with this instruction"));
9498 inst.instruction |= 0x00200000;
9500 inst.instruction |= 0x00000900;
9501 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9503 else /* unindexed - only for coprocessor */
9504 inst.error = _("instruction does not accept unindexed addressing");
9507 /* Table of Thumb instructions which exist in both 16- and 32-bit
9508 encodings (the latter only in post-V6T2 cores). The index is the
9509 value used in the insns table below. When there is more than one
9510 possible 16-bit encoding for the instruction, this table always
9512 Also contains several pseudo-instructions used during relaxation. */
9513 #define T16_32_TAB \
9514 X(_adc, 4140, eb400000), \
9515 X(_adcs, 4140, eb500000), \
9516 X(_add, 1c00, eb000000), \
9517 X(_adds, 1c00, eb100000), \
9518 X(_addi, 0000, f1000000), \
9519 X(_addis, 0000, f1100000), \
9520 X(_add_pc,000f, f20f0000), \
9521 X(_add_sp,000d, f10d0000), \
9522 X(_adr, 000f, f20f0000), \
9523 X(_and, 4000, ea000000), \
9524 X(_ands, 4000, ea100000), \
9525 X(_asr, 1000, fa40f000), \
9526 X(_asrs, 1000, fa50f000), \
9527 X(_b, e000, f000b000), \
9528 X(_bcond, d000, f0008000), \
9529 X(_bic, 4380, ea200000), \
9530 X(_bics, 4380, ea300000), \
9531 X(_cmn, 42c0, eb100f00), \
9532 X(_cmp, 2800, ebb00f00), \
9533 X(_cpsie, b660, f3af8400), \
9534 X(_cpsid, b670, f3af8600), \
9535 X(_cpy, 4600, ea4f0000), \
9536 X(_dec_sp,80dd, f1ad0d00), \
9537 X(_eor, 4040, ea800000), \
9538 X(_eors, 4040, ea900000), \
9539 X(_inc_sp,00dd, f10d0d00), \
9540 X(_ldmia, c800, e8900000), \
9541 X(_ldr, 6800, f8500000), \
9542 X(_ldrb, 7800, f8100000), \
9543 X(_ldrh, 8800, f8300000), \
9544 X(_ldrsb, 5600, f9100000), \
9545 X(_ldrsh, 5e00, f9300000), \
9546 X(_ldr_pc,4800, f85f0000), \
9547 X(_ldr_pc2,4800, f85f0000), \
9548 X(_ldr_sp,9800, f85d0000), \
9549 X(_lsl, 0000, fa00f000), \
9550 X(_lsls, 0000, fa10f000), \
9551 X(_lsr, 0800, fa20f000), \
9552 X(_lsrs, 0800, fa30f000), \
9553 X(_mov, 2000, ea4f0000), \
9554 X(_movs, 2000, ea5f0000), \
9555 X(_mul, 4340, fb00f000), \
9556 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9557 X(_mvn, 43c0, ea6f0000), \
9558 X(_mvns, 43c0, ea7f0000), \
9559 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9560 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9561 X(_orr, 4300, ea400000), \
9562 X(_orrs, 4300, ea500000), \
9563 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9564 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9565 X(_rev, ba00, fa90f080), \
9566 X(_rev16, ba40, fa90f090), \
9567 X(_revsh, bac0, fa90f0b0), \
9568 X(_ror, 41c0, fa60f000), \
9569 X(_rors, 41c0, fa70f000), \
9570 X(_sbc, 4180, eb600000), \
9571 X(_sbcs, 4180, eb700000), \
9572 X(_stmia, c000, e8800000), \
9573 X(_str, 6000, f8400000), \
9574 X(_strb, 7000, f8000000), \
9575 X(_strh, 8000, f8200000), \
9576 X(_str_sp,9000, f84d0000), \
9577 X(_sub, 1e00, eba00000), \
9578 X(_subs, 1e00, ebb00000), \
9579 X(_subi, 8000, f1a00000), \
9580 X(_subis, 8000, f1b00000), \
9581 X(_sxtb, b240, fa4ff080), \
9582 X(_sxth, b200, fa0ff080), \
9583 X(_tst, 4200, ea100f00), \
9584 X(_uxtb, b2c0, fa5ff080), \
9585 X(_uxth, b280, fa1ff080), \
9586 X(_nop, bf00, f3af8000), \
9587 X(_yield, bf10, f3af8001), \
9588 X(_wfe, bf20, f3af8002), \
9589 X(_wfi, bf30, f3af8003), \
9590 X(_sev, bf40, f3af8004), \
9591 X(_sevl, bf50, f3af8005)
9593 /* To catch errors in encoding functions, the codes are all offset by
9594 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9595 as 16-bit instructions. */
9596 #define X(a,b,c) T_MNEM##a
9597 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9600 #define X(a,b,c) 0x##b
9601 static const unsigned short thumb_op16[] = { T16_32_TAB };
9602 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9605 #define X(a,b,c) 0x##c
9606 static const unsigned int thumb_op32[] = { T16_32_TAB };
9607 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9608 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9612 /* Thumb instruction encoders, in alphabetical order. */
9617 do_t_add_sub_w (void)
9621 Rd = inst.operands[0].reg;
9622 Rn = inst.operands[1].reg;
9624 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9625 is the SP-{plus,minus}-immediate form of the instruction. */
9627 constraint (Rd == REG_PC, BAD_PC);
9629 reject_bad_reg (Rd);
9631 inst.instruction |= (Rn << 16) | (Rd << 8);
9632 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9635 /* Parse an add or subtract instruction. We get here with inst.instruction
9636 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9643 Rd = inst.operands[0].reg;
9644 Rs = (inst.operands[1].present
9645 ? inst.operands[1].reg /* Rd, Rs, foo */
9646 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9649 set_it_insn_type_last ();
9657 flags = (inst.instruction == T_MNEM_adds
9658 || inst.instruction == T_MNEM_subs);
9660 narrow = !in_it_block ();
9662 narrow = in_it_block ();
9663 if (!inst.operands[2].isreg)
9667 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9669 add = (inst.instruction == T_MNEM_add
9670 || inst.instruction == T_MNEM_adds);
9672 if (inst.size_req != 4)
9674 /* Attempt to use a narrow opcode, with relaxation if
9676 if (Rd == REG_SP && Rs == REG_SP && !flags)
9677 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9678 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9679 opcode = T_MNEM_add_sp;
9680 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9681 opcode = T_MNEM_add_pc;
9682 else if (Rd <= 7 && Rs <= 7 && narrow)
9685 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9687 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9691 inst.instruction = THUMB_OP16(opcode);
9692 inst.instruction |= (Rd << 4) | Rs;
9693 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9694 if (inst.size_req != 2)
9695 inst.relax = opcode;
9698 constraint (inst.size_req == 2, BAD_HIREG);
9700 if (inst.size_req == 4
9701 || (inst.size_req != 2 && !opcode))
9705 constraint (add, BAD_PC);
9706 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9707 _("only SUBS PC, LR, #const allowed"));
9708 constraint (inst.reloc.exp.X_op != O_constant,
9709 _("expression too complex"));
9710 constraint (inst.reloc.exp.X_add_number < 0
9711 || inst.reloc.exp.X_add_number > 0xff,
9712 _("immediate value out of range"));
9713 inst.instruction = T2_SUBS_PC_LR
9714 | inst.reloc.exp.X_add_number;
9715 inst.reloc.type = BFD_RELOC_UNUSED;
9718 else if (Rs == REG_PC)
9720 /* Always use addw/subw. */
9721 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9722 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9726 inst.instruction = THUMB_OP32 (inst.instruction);
9727 inst.instruction = (inst.instruction & 0xe1ffffff)
9730 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9732 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9734 inst.instruction |= Rd << 8;
9735 inst.instruction |= Rs << 16;
9740 unsigned int value = inst.reloc.exp.X_add_number;
9741 unsigned int shift = inst.operands[2].shift_kind;
9743 Rn = inst.operands[2].reg;
9744 /* See if we can do this with a 16-bit instruction. */
9745 if (!inst.operands[2].shifted && inst.size_req != 4)
9747 if (Rd > 7 || Rs > 7 || Rn > 7)
9752 inst.instruction = ((inst.instruction == T_MNEM_adds
9753 || inst.instruction == T_MNEM_add)
9756 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9760 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9762 /* Thumb-1 cores (except v6-M) require at least one high
9763 register in a narrow non flag setting add. */
9764 if (Rd > 7 || Rn > 7
9765 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9766 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9773 inst.instruction = T_OPCODE_ADD_HI;
9774 inst.instruction |= (Rd & 8) << 4;
9775 inst.instruction |= (Rd & 7);
9776 inst.instruction |= Rn << 3;
9782 constraint (Rd == REG_PC, BAD_PC);
9783 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9784 constraint (Rs == REG_PC, BAD_PC);
9785 reject_bad_reg (Rn);
9787 /* If we get here, it can't be done in 16 bits. */
9788 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9789 _("shift must be constant"));
9790 inst.instruction = THUMB_OP32 (inst.instruction);
9791 inst.instruction |= Rd << 8;
9792 inst.instruction |= Rs << 16;
9793 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9794 _("shift value over 3 not allowed in thumb mode"));
9795 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9796 _("only LSL shift allowed in thumb mode"));
9797 encode_thumb32_shifted_operand (2);
9802 constraint (inst.instruction == T_MNEM_adds
9803 || inst.instruction == T_MNEM_subs,
9806 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9808 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9809 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9812 inst.instruction = (inst.instruction == T_MNEM_add
9814 inst.instruction |= (Rd << 4) | Rs;
9815 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9819 Rn = inst.operands[2].reg;
9820 constraint (inst.operands[2].shifted, _("unshifted register required"));
9822 /* We now have Rd, Rs, and Rn set to registers. */
9823 if (Rd > 7 || Rs > 7 || Rn > 7)
9825 /* Can't do this for SUB. */
9826 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9827 inst.instruction = T_OPCODE_ADD_HI;
9828 inst.instruction |= (Rd & 8) << 4;
9829 inst.instruction |= (Rd & 7);
9831 inst.instruction |= Rn << 3;
9833 inst.instruction |= Rs << 3;
9835 constraint (1, _("dest must overlap one source register"));
9839 inst.instruction = (inst.instruction == T_MNEM_add
9840 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9841 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9851 Rd = inst.operands[0].reg;
9852 reject_bad_reg (Rd);
9854 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9856 /* Defer to section relaxation. */
9857 inst.relax = inst.instruction;
9858 inst.instruction = THUMB_OP16 (inst.instruction);
9859 inst.instruction |= Rd << 4;
9861 else if (unified_syntax && inst.size_req != 2)
9863 /* Generate a 32-bit opcode. */
9864 inst.instruction = THUMB_OP32 (inst.instruction);
9865 inst.instruction |= Rd << 8;
9866 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9867 inst.reloc.pc_rel = 1;
9871 /* Generate a 16-bit opcode. */
9872 inst.instruction = THUMB_OP16 (inst.instruction);
9873 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9874 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9875 inst.reloc.pc_rel = 1;
9877 inst.instruction |= Rd << 4;
9881 /* Arithmetic instructions for which there is just one 16-bit
9882 instruction encoding, and it allows only two low registers.
9883 For maximal compatibility with ARM syntax, we allow three register
9884 operands even when Thumb-32 instructions are not available, as long
9885 as the first two are identical. For instance, both "sbc r0,r1" and
9886 "sbc r0,r0,r1" are allowed. */
9892 Rd = inst.operands[0].reg;
9893 Rs = (inst.operands[1].present
9894 ? inst.operands[1].reg /* Rd, Rs, foo */
9895 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9896 Rn = inst.operands[2].reg;
9898 reject_bad_reg (Rd);
9899 reject_bad_reg (Rs);
9900 if (inst.operands[2].isreg)
9901 reject_bad_reg (Rn);
9905 if (!inst.operands[2].isreg)
9907 /* For an immediate, we always generate a 32-bit opcode;
9908 section relaxation will shrink it later if possible. */
9909 inst.instruction = THUMB_OP32 (inst.instruction);
9910 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9911 inst.instruction |= Rd << 8;
9912 inst.instruction |= Rs << 16;
9913 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9919 /* See if we can do this with a 16-bit instruction. */
9920 if (THUMB_SETS_FLAGS (inst.instruction))
9921 narrow = !in_it_block ();
9923 narrow = in_it_block ();
9925 if (Rd > 7 || Rn > 7 || Rs > 7)
9927 if (inst.operands[2].shifted)
9929 if (inst.size_req == 4)
9935 inst.instruction = THUMB_OP16 (inst.instruction);
9936 inst.instruction |= Rd;
9937 inst.instruction |= Rn << 3;
9941 /* If we get here, it can't be done in 16 bits. */
9942 constraint (inst.operands[2].shifted
9943 && inst.operands[2].immisreg,
9944 _("shift must be constant"));
9945 inst.instruction = THUMB_OP32 (inst.instruction);
9946 inst.instruction |= Rd << 8;
9947 inst.instruction |= Rs << 16;
9948 encode_thumb32_shifted_operand (2);
9953 /* On its face this is a lie - the instruction does set the
9954 flags. However, the only supported mnemonic in this mode
9956 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9958 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9959 _("unshifted register required"));
9960 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9961 constraint (Rd != Rs,
9962 _("dest and source1 must be the same register"));
9964 inst.instruction = THUMB_OP16 (inst.instruction);
9965 inst.instruction |= Rd;
9966 inst.instruction |= Rn << 3;
9970 /* Similarly, but for instructions where the arithmetic operation is
9971 commutative, so we can allow either of them to be different from
9972 the destination operand in a 16-bit instruction. For instance, all
9973 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9980 Rd = inst.operands[0].reg;
9981 Rs = (inst.operands[1].present
9982 ? inst.operands[1].reg /* Rd, Rs, foo */
9983 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9984 Rn = inst.operands[2].reg;
9986 reject_bad_reg (Rd);
9987 reject_bad_reg (Rs);
9988 if (inst.operands[2].isreg)
9989 reject_bad_reg (Rn);
9993 if (!inst.operands[2].isreg)
9995 /* For an immediate, we always generate a 32-bit opcode;
9996 section relaxation will shrink it later if possible. */
9997 inst.instruction = THUMB_OP32 (inst.instruction);
9998 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9999 inst.instruction |= Rd << 8;
10000 inst.instruction |= Rs << 16;
10001 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10005 bfd_boolean narrow;
10007 /* See if we can do this with a 16-bit instruction. */
10008 if (THUMB_SETS_FLAGS (inst.instruction))
10009 narrow = !in_it_block ();
10011 narrow = in_it_block ();
10013 if (Rd > 7 || Rn > 7 || Rs > 7)
10015 if (inst.operands[2].shifted)
10017 if (inst.size_req == 4)
10024 inst.instruction = THUMB_OP16 (inst.instruction);
10025 inst.instruction |= Rd;
10026 inst.instruction |= Rn << 3;
10031 inst.instruction = THUMB_OP16 (inst.instruction);
10032 inst.instruction |= Rd;
10033 inst.instruction |= Rs << 3;
10038 /* If we get here, it can't be done in 16 bits. */
10039 constraint (inst.operands[2].shifted
10040 && inst.operands[2].immisreg,
10041 _("shift must be constant"));
10042 inst.instruction = THUMB_OP32 (inst.instruction);
10043 inst.instruction |= Rd << 8;
10044 inst.instruction |= Rs << 16;
10045 encode_thumb32_shifted_operand (2);
10050 /* On its face this is a lie - the instruction does set the
10051 flags. However, the only supported mnemonic in this mode
10052 says it doesn't. */
10053 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10055 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10056 _("unshifted register required"));
10057 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10059 inst.instruction = THUMB_OP16 (inst.instruction);
10060 inst.instruction |= Rd;
10063 inst.instruction |= Rn << 3;
10065 inst.instruction |= Rs << 3;
10067 constraint (1, _("dest must overlap one source register"));
10072 do_t_barrier (void)
10074 if (inst.operands[0].present)
10076 constraint ((inst.instruction & 0xf0) != 0x40
10077 && inst.operands[0].imm > 0xf
10078 && inst.operands[0].imm < 0x0,
10079 _("bad barrier type"));
10080 inst.instruction |= inst.operands[0].imm;
10083 inst.instruction |= 0xf;
10090 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10091 constraint (msb > 32, _("bit-field extends past end of register"));
10092 /* The instruction encoding stores the LSB and MSB,
10093 not the LSB and width. */
10094 Rd = inst.operands[0].reg;
10095 reject_bad_reg (Rd);
10096 inst.instruction |= Rd << 8;
10097 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10098 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10099 inst.instruction |= msb - 1;
10108 Rd = inst.operands[0].reg;
10109 reject_bad_reg (Rd);
10111 /* #0 in second position is alternative syntax for bfc, which is
10112 the same instruction but with REG_PC in the Rm field. */
10113 if (!inst.operands[1].isreg)
10117 Rn = inst.operands[1].reg;
10118 reject_bad_reg (Rn);
10121 msb = inst.operands[2].imm + inst.operands[3].imm;
10122 constraint (msb > 32, _("bit-field extends past end of register"));
10123 /* The instruction encoding stores the LSB and MSB,
10124 not the LSB and width. */
10125 inst.instruction |= Rd << 8;
10126 inst.instruction |= Rn << 16;
10127 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10128 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10129 inst.instruction |= msb - 1;
10137 Rd = inst.operands[0].reg;
10138 Rn = inst.operands[1].reg;
10140 reject_bad_reg (Rd);
10141 reject_bad_reg (Rn);
10143 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10144 _("bit-field extends past end of register"));
10145 inst.instruction |= Rd << 8;
10146 inst.instruction |= Rn << 16;
10147 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10148 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10149 inst.instruction |= inst.operands[3].imm - 1;
10152 /* ARM V5 Thumb BLX (argument parse)
10153 BLX <target_addr> which is BLX(1)
10154 BLX <Rm> which is BLX(2)
10155 Unfortunately, there are two different opcodes for this mnemonic.
10156 So, the insns[].value is not used, and the code here zaps values
10157 into inst.instruction.
10159 ??? How to take advantage of the additional two bits of displacement
10160 available in Thumb32 mode? Need new relocation? */
10165 set_it_insn_type_last ();
10167 if (inst.operands[0].isreg)
10169 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10170 /* We have a register, so this is BLX(2). */
10171 inst.instruction |= inst.operands[0].reg << 3;
10175 /* No register. This must be BLX(1). */
10176 inst.instruction = 0xf000e800;
10177 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10189 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10191 if (in_it_block ())
10193 /* Conditional branches inside IT blocks are encoded as unconditional
10195 cond = COND_ALWAYS;
10200 if (cond != COND_ALWAYS)
10201 opcode = T_MNEM_bcond;
10203 opcode = inst.instruction;
10206 && (inst.size_req == 4
10207 || (inst.size_req != 2
10208 && (inst.operands[0].hasreloc
10209 || inst.reloc.exp.X_op == O_constant))))
10211 inst.instruction = THUMB_OP32(opcode);
10212 if (cond == COND_ALWAYS)
10213 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10216 gas_assert (cond != 0xF);
10217 inst.instruction |= cond << 22;
10218 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10223 inst.instruction = THUMB_OP16(opcode);
10224 if (cond == COND_ALWAYS)
10225 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10228 inst.instruction |= cond << 8;
10229 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10231 /* Allow section relaxation. */
10232 if (unified_syntax && inst.size_req != 2)
10233 inst.relax = opcode;
10235 inst.reloc.type = reloc;
10236 inst.reloc.pc_rel = 1;
10239 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10240 between the two is the maximum immediate allowed - which is passed in
10243 do_t_bkpt_hlt1 (int range)
10245 constraint (inst.cond != COND_ALWAYS,
10246 _("instruction is always unconditional"));
10247 if (inst.operands[0].present)
10249 constraint (inst.operands[0].imm > range,
10250 _("immediate value out of range"));
10251 inst.instruction |= inst.operands[0].imm;
10254 set_it_insn_type (NEUTRAL_IT_INSN);
10260 do_t_bkpt_hlt1 (63);
10266 do_t_bkpt_hlt1 (255);
10270 do_t_branch23 (void)
10272 set_it_insn_type_last ();
10273 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10275 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10276 this file. We used to simply ignore the PLT reloc type here --
10277 the branch encoding is now needed to deal with TLSCALL relocs.
10278 So if we see a PLT reloc now, put it back to how it used to be to
10279 keep the preexisting behaviour. */
10280 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10281 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10283 #if defined(OBJ_COFF)
10284 /* If the destination of the branch is a defined symbol which does not have
10285 the THUMB_FUNC attribute, then we must be calling a function which has
10286 the (interfacearm) attribute. We look for the Thumb entry point to that
10287 function and change the branch to refer to that function instead. */
10288 if ( inst.reloc.exp.X_op == O_symbol
10289 && inst.reloc.exp.X_add_symbol != NULL
10290 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10291 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10292 inst.reloc.exp.X_add_symbol =
10293 find_real_start (inst.reloc.exp.X_add_symbol);
10300 set_it_insn_type_last ();
10301 inst.instruction |= inst.operands[0].reg << 3;
10302 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10303 should cause the alignment to be checked once it is known. This is
10304 because BX PC only works if the instruction is word aligned. */
10312 set_it_insn_type_last ();
10313 Rm = inst.operands[0].reg;
10314 reject_bad_reg (Rm);
10315 inst.instruction |= Rm << 16;
10324 Rd = inst.operands[0].reg;
10325 Rm = inst.operands[1].reg;
10327 reject_bad_reg (Rd);
10328 reject_bad_reg (Rm);
10330 inst.instruction |= Rd << 8;
10331 inst.instruction |= Rm << 16;
10332 inst.instruction |= Rm;
10338 set_it_insn_type (OUTSIDE_IT_INSN);
10339 inst.instruction |= inst.operands[0].imm;
10345 set_it_insn_type (OUTSIDE_IT_INSN);
10347 && (inst.operands[1].present || inst.size_req == 4)
10348 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10350 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10351 inst.instruction = 0xf3af8000;
10352 inst.instruction |= imod << 9;
10353 inst.instruction |= inst.operands[0].imm << 5;
10354 if (inst.operands[1].present)
10355 inst.instruction |= 0x100 | inst.operands[1].imm;
10359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10360 && (inst.operands[0].imm & 4),
10361 _("selected processor does not support 'A' form "
10362 "of this instruction"));
10363 constraint (inst.operands[1].present || inst.size_req == 4,
10364 _("Thumb does not support the 2-argument "
10365 "form of this instruction"));
10366 inst.instruction |= inst.operands[0].imm;
10370 /* THUMB CPY instruction (argument parse). */
10375 if (inst.size_req == 4)
10377 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10378 inst.instruction |= inst.operands[0].reg << 8;
10379 inst.instruction |= inst.operands[1].reg;
10383 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10384 inst.instruction |= (inst.operands[0].reg & 0x7);
10385 inst.instruction |= inst.operands[1].reg << 3;
10392 set_it_insn_type (OUTSIDE_IT_INSN);
10393 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10394 inst.instruction |= inst.operands[0].reg;
10395 inst.reloc.pc_rel = 1;
10396 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10402 inst.instruction |= inst.operands[0].imm;
10408 unsigned Rd, Rn, Rm;
10410 Rd = inst.operands[0].reg;
10411 Rn = (inst.operands[1].present
10412 ? inst.operands[1].reg : Rd);
10413 Rm = inst.operands[2].reg;
10415 reject_bad_reg (Rd);
10416 reject_bad_reg (Rn);
10417 reject_bad_reg (Rm);
10419 inst.instruction |= Rd << 8;
10420 inst.instruction |= Rn << 16;
10421 inst.instruction |= Rm;
10427 if (unified_syntax && inst.size_req == 4)
10428 inst.instruction = THUMB_OP32 (inst.instruction);
10430 inst.instruction = THUMB_OP16 (inst.instruction);
10436 unsigned int cond = inst.operands[0].imm;
10438 set_it_insn_type (IT_INSN);
10439 now_it.mask = (inst.instruction & 0xf) | 0x10;
10441 now_it.warn_deprecated = FALSE;
10443 /* If the condition is a negative condition, invert the mask. */
10444 if ((cond & 0x1) == 0x0)
10446 unsigned int mask = inst.instruction & 0x000f;
10448 if ((mask & 0x7) == 0)
10450 /* No conversion needed. */
10451 now_it.block_length = 1;
10453 else if ((mask & 0x3) == 0)
10456 now_it.block_length = 2;
10458 else if ((mask & 0x1) == 0)
10461 now_it.block_length = 3;
10466 now_it.block_length = 4;
10469 inst.instruction &= 0xfff0;
10470 inst.instruction |= mask;
10473 inst.instruction |= cond << 4;
10476 /* Helper function used for both push/pop and ldm/stm. */
10478 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10482 load = (inst.instruction & (1 << 20)) != 0;
10484 if (mask & (1 << 13))
10485 inst.error = _("SP not allowed in register list");
10487 if ((mask & (1 << base)) != 0
10489 inst.error = _("having the base register in the register list when "
10490 "using write back is UNPREDICTABLE");
10494 if (mask & (1 << 15))
10496 if (mask & (1 << 14))
10497 inst.error = _("LR and PC should not both be in register list");
10499 set_it_insn_type_last ();
10504 if (mask & (1 << 15))
10505 inst.error = _("PC not allowed in register list");
10508 if ((mask & (mask - 1)) == 0)
10510 /* Single register transfers implemented as str/ldr. */
10513 if (inst.instruction & (1 << 23))
10514 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10516 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10520 if (inst.instruction & (1 << 23))
10521 inst.instruction = 0x00800000; /* ia -> [base] */
10523 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10526 inst.instruction |= 0xf8400000;
10528 inst.instruction |= 0x00100000;
10530 mask = ffs (mask) - 1;
10533 else if (writeback)
10534 inst.instruction |= WRITE_BACK;
10536 inst.instruction |= mask;
10537 inst.instruction |= base << 16;
10543 /* This really doesn't seem worth it. */
10544 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10545 _("expression too complex"));
10546 constraint (inst.operands[1].writeback,
10547 _("Thumb load/store multiple does not support {reglist}^"));
10549 if (unified_syntax)
10551 bfd_boolean narrow;
10555 /* See if we can use a 16-bit instruction. */
10556 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10557 && inst.size_req != 4
10558 && !(inst.operands[1].imm & ~0xff))
10560 mask = 1 << inst.operands[0].reg;
10562 if (inst.operands[0].reg <= 7)
10564 if (inst.instruction == T_MNEM_stmia
10565 ? inst.operands[0].writeback
10566 : (inst.operands[0].writeback
10567 == !(inst.operands[1].imm & mask)))
10569 if (inst.instruction == T_MNEM_stmia
10570 && (inst.operands[1].imm & mask)
10571 && (inst.operands[1].imm & (mask - 1)))
10572 as_warn (_("value stored for r%d is UNKNOWN"),
10573 inst.operands[0].reg);
10575 inst.instruction = THUMB_OP16 (inst.instruction);
10576 inst.instruction |= inst.operands[0].reg << 8;
10577 inst.instruction |= inst.operands[1].imm;
10580 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10582 /* This means 1 register in reg list one of 3 situations:
10583 1. Instruction is stmia, but without writeback.
10584 2. lmdia without writeback, but with Rn not in
10586 3. ldmia with writeback, but with Rn in reglist.
10587 Case 3 is UNPREDICTABLE behaviour, so we handle
10588 case 1 and 2 which can be converted into a 16-bit
10589 str or ldr. The SP cases are handled below. */
10590 unsigned long opcode;
10591 /* First, record an error for Case 3. */
10592 if (inst.operands[1].imm & mask
10593 && inst.operands[0].writeback)
10595 _("having the base register in the register list when "
10596 "using write back is UNPREDICTABLE");
10598 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10600 inst.instruction = THUMB_OP16 (opcode);
10601 inst.instruction |= inst.operands[0].reg << 3;
10602 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10606 else if (inst.operands[0] .reg == REG_SP)
10608 if (inst.operands[0].writeback)
10611 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10612 ? T_MNEM_push : T_MNEM_pop);
10613 inst.instruction |= inst.operands[1].imm;
10616 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10619 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10620 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10621 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10629 if (inst.instruction < 0xffff)
10630 inst.instruction = THUMB_OP32 (inst.instruction);
10632 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10633 inst.operands[0].writeback);
10638 constraint (inst.operands[0].reg > 7
10639 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10640 constraint (inst.instruction != T_MNEM_ldmia
10641 && inst.instruction != T_MNEM_stmia,
10642 _("Thumb-2 instruction only valid in unified syntax"));
10643 if (inst.instruction == T_MNEM_stmia)
10645 if (!inst.operands[0].writeback)
10646 as_warn (_("this instruction will write back the base register"));
10647 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10648 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10649 as_warn (_("value stored for r%d is UNKNOWN"),
10650 inst.operands[0].reg);
10654 if (!inst.operands[0].writeback
10655 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10656 as_warn (_("this instruction will write back the base register"));
10657 else if (inst.operands[0].writeback
10658 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10659 as_warn (_("this instruction will not write back the base register"));
10662 inst.instruction = THUMB_OP16 (inst.instruction);
10663 inst.instruction |= inst.operands[0].reg << 8;
10664 inst.instruction |= inst.operands[1].imm;
10671 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10672 || inst.operands[1].postind || inst.operands[1].writeback
10673 || inst.operands[1].immisreg || inst.operands[1].shifted
10674 || inst.operands[1].negative,
10677 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10679 inst.instruction |= inst.operands[0].reg << 12;
10680 inst.instruction |= inst.operands[1].reg << 16;
10681 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10687 if (!inst.operands[1].present)
10689 constraint (inst.operands[0].reg == REG_LR,
10690 _("r14 not allowed as first register "
10691 "when second register is omitted"));
10692 inst.operands[1].reg = inst.operands[0].reg + 1;
10694 constraint (inst.operands[0].reg == inst.operands[1].reg,
10697 inst.instruction |= inst.operands[0].reg << 12;
10698 inst.instruction |= inst.operands[1].reg << 8;
10699 inst.instruction |= inst.operands[2].reg << 16;
10705 unsigned long opcode;
10708 if (inst.operands[0].isreg
10709 && !inst.operands[0].preind
10710 && inst.operands[0].reg == REG_PC)
10711 set_it_insn_type_last ();
10713 opcode = inst.instruction;
10714 if (unified_syntax)
10716 if (!inst.operands[1].isreg)
10718 if (opcode <= 0xffff)
10719 inst.instruction = THUMB_OP32 (opcode);
10720 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10723 if (inst.operands[1].isreg
10724 && !inst.operands[1].writeback
10725 && !inst.operands[1].shifted && !inst.operands[1].postind
10726 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10727 && opcode <= 0xffff
10728 && inst.size_req != 4)
10730 /* Insn may have a 16-bit form. */
10731 Rn = inst.operands[1].reg;
10732 if (inst.operands[1].immisreg)
10734 inst.instruction = THUMB_OP16 (opcode);
10736 if (Rn <= 7 && inst.operands[1].imm <= 7)
10738 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10739 reject_bad_reg (inst.operands[1].imm);
10741 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10742 && opcode != T_MNEM_ldrsb)
10743 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10744 || (Rn == REG_SP && opcode == T_MNEM_str))
10751 if (inst.reloc.pc_rel)
10752 opcode = T_MNEM_ldr_pc2;
10754 opcode = T_MNEM_ldr_pc;
10758 if (opcode == T_MNEM_ldr)
10759 opcode = T_MNEM_ldr_sp;
10761 opcode = T_MNEM_str_sp;
10763 inst.instruction = inst.operands[0].reg << 8;
10767 inst.instruction = inst.operands[0].reg;
10768 inst.instruction |= inst.operands[1].reg << 3;
10770 inst.instruction |= THUMB_OP16 (opcode);
10771 if (inst.size_req == 2)
10772 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10774 inst.relax = opcode;
10778 /* Definitely a 32-bit variant. */
10780 /* Warning for Erratum 752419. */
10781 if (opcode == T_MNEM_ldr
10782 && inst.operands[0].reg == REG_SP
10783 && inst.operands[1].writeback == 1
10784 && !inst.operands[1].immisreg)
10786 if (no_cpu_selected ()
10787 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10788 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10789 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10790 as_warn (_("This instruction may be unpredictable "
10791 "if executed on M-profile cores "
10792 "with interrupts enabled."));
10795 /* Do some validations regarding addressing modes. */
10796 if (inst.operands[1].immisreg)
10797 reject_bad_reg (inst.operands[1].imm);
10799 constraint (inst.operands[1].writeback == 1
10800 && inst.operands[0].reg == inst.operands[1].reg,
10803 inst.instruction = THUMB_OP32 (opcode);
10804 inst.instruction |= inst.operands[0].reg << 12;
10805 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10806 check_ldr_r15_aligned ();
10810 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10812 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10814 /* Only [Rn,Rm] is acceptable. */
10815 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10816 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10817 || inst.operands[1].postind || inst.operands[1].shifted
10818 || inst.operands[1].negative,
10819 _("Thumb does not support this addressing mode"));
10820 inst.instruction = THUMB_OP16 (inst.instruction);
10824 inst.instruction = THUMB_OP16 (inst.instruction);
10825 if (!inst.operands[1].isreg)
10826 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10829 constraint (!inst.operands[1].preind
10830 || inst.operands[1].shifted
10831 || inst.operands[1].writeback,
10832 _("Thumb does not support this addressing mode"));
10833 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10835 constraint (inst.instruction & 0x0600,
10836 _("byte or halfword not valid for base register"));
10837 constraint (inst.operands[1].reg == REG_PC
10838 && !(inst.instruction & THUMB_LOAD_BIT),
10839 _("r15 based store not allowed"));
10840 constraint (inst.operands[1].immisreg,
10841 _("invalid base register for register offset"));
10843 if (inst.operands[1].reg == REG_PC)
10844 inst.instruction = T_OPCODE_LDR_PC;
10845 else if (inst.instruction & THUMB_LOAD_BIT)
10846 inst.instruction = T_OPCODE_LDR_SP;
10848 inst.instruction = T_OPCODE_STR_SP;
10850 inst.instruction |= inst.operands[0].reg << 8;
10851 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10855 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10856 if (!inst.operands[1].immisreg)
10858 /* Immediate offset. */
10859 inst.instruction |= inst.operands[0].reg;
10860 inst.instruction |= inst.operands[1].reg << 3;
10861 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10865 /* Register offset. */
10866 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10867 constraint (inst.operands[1].negative,
10868 _("Thumb does not support this addressing mode"));
10871 switch (inst.instruction)
10873 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10874 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10875 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10876 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10877 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10878 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10879 case 0x5600 /* ldrsb */:
10880 case 0x5e00 /* ldrsh */: break;
10884 inst.instruction |= inst.operands[0].reg;
10885 inst.instruction |= inst.operands[1].reg << 3;
10886 inst.instruction |= inst.operands[1].imm << 6;
10892 if (!inst.operands[1].present)
10894 inst.operands[1].reg = inst.operands[0].reg + 1;
10895 constraint (inst.operands[0].reg == REG_LR,
10896 _("r14 not allowed here"));
10897 constraint (inst.operands[0].reg == REG_R12,
10898 _("r12 not allowed here"));
10901 if (inst.operands[2].writeback
10902 && (inst.operands[0].reg == inst.operands[2].reg
10903 || inst.operands[1].reg == inst.operands[2].reg))
10904 as_warn (_("base register written back, and overlaps "
10905 "one of transfer registers"));
10907 inst.instruction |= inst.operands[0].reg << 12;
10908 inst.instruction |= inst.operands[1].reg << 8;
10909 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10915 inst.instruction |= inst.operands[0].reg << 12;
10916 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10922 unsigned Rd, Rn, Rm, Ra;
10924 Rd = inst.operands[0].reg;
10925 Rn = inst.operands[1].reg;
10926 Rm = inst.operands[2].reg;
10927 Ra = inst.operands[3].reg;
10929 reject_bad_reg (Rd);
10930 reject_bad_reg (Rn);
10931 reject_bad_reg (Rm);
10932 reject_bad_reg (Ra);
10934 inst.instruction |= Rd << 8;
10935 inst.instruction |= Rn << 16;
10936 inst.instruction |= Rm;
10937 inst.instruction |= Ra << 12;
10943 unsigned RdLo, RdHi, Rn, Rm;
10945 RdLo = inst.operands[0].reg;
10946 RdHi = inst.operands[1].reg;
10947 Rn = inst.operands[2].reg;
10948 Rm = inst.operands[3].reg;
10950 reject_bad_reg (RdLo);
10951 reject_bad_reg (RdHi);
10952 reject_bad_reg (Rn);
10953 reject_bad_reg (Rm);
10955 inst.instruction |= RdLo << 12;
10956 inst.instruction |= RdHi << 8;
10957 inst.instruction |= Rn << 16;
10958 inst.instruction |= Rm;
10962 do_t_mov_cmp (void)
10966 Rn = inst.operands[0].reg;
10967 Rm = inst.operands[1].reg;
10970 set_it_insn_type_last ();
10972 if (unified_syntax)
10974 int r0off = (inst.instruction == T_MNEM_mov
10975 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10976 unsigned long opcode;
10977 bfd_boolean narrow;
10978 bfd_boolean low_regs;
10980 low_regs = (Rn <= 7 && Rm <= 7);
10981 opcode = inst.instruction;
10982 if (in_it_block ())
10983 narrow = opcode != T_MNEM_movs;
10985 narrow = opcode != T_MNEM_movs || low_regs;
10986 if (inst.size_req == 4
10987 || inst.operands[1].shifted)
10990 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10991 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10992 && !inst.operands[1].shifted
10996 inst.instruction = T2_SUBS_PC_LR;
11000 if (opcode == T_MNEM_cmp)
11002 constraint (Rn == REG_PC, BAD_PC);
11005 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11007 warn_deprecated_sp (Rm);
11008 /* R15 was documented as a valid choice for Rm in ARMv6,
11009 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11010 tools reject R15, so we do too. */
11011 constraint (Rm == REG_PC, BAD_PC);
11014 reject_bad_reg (Rm);
11016 else if (opcode == T_MNEM_mov
11017 || opcode == T_MNEM_movs)
11019 if (inst.operands[1].isreg)
11021 if (opcode == T_MNEM_movs)
11023 reject_bad_reg (Rn);
11024 reject_bad_reg (Rm);
11028 /* This is mov.n. */
11029 if ((Rn == REG_SP || Rn == REG_PC)
11030 && (Rm == REG_SP || Rm == REG_PC))
11032 as_warn (_("Use of r%u as a source register is "
11033 "deprecated when r%u is the destination "
11034 "register."), Rm, Rn);
11039 /* This is mov.w. */
11040 constraint (Rn == REG_PC, BAD_PC);
11041 constraint (Rm == REG_PC, BAD_PC);
11042 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11046 reject_bad_reg (Rn);
11049 if (!inst.operands[1].isreg)
11051 /* Immediate operand. */
11052 if (!in_it_block () && opcode == T_MNEM_mov)
11054 if (low_regs && narrow)
11056 inst.instruction = THUMB_OP16 (opcode);
11057 inst.instruction |= Rn << 8;
11058 if (inst.size_req == 2)
11059 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11061 inst.relax = opcode;
11065 inst.instruction = THUMB_OP32 (inst.instruction);
11066 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11067 inst.instruction |= Rn << r0off;
11068 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11071 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11072 && (inst.instruction == T_MNEM_mov
11073 || inst.instruction == T_MNEM_movs))
11075 /* Register shifts are encoded as separate shift instructions. */
11076 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11078 if (in_it_block ())
11083 if (inst.size_req == 4)
11086 if (!low_regs || inst.operands[1].imm > 7)
11092 switch (inst.operands[1].shift_kind)
11095 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11098 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11101 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11104 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11110 inst.instruction = opcode;
11113 inst.instruction |= Rn;
11114 inst.instruction |= inst.operands[1].imm << 3;
11119 inst.instruction |= CONDS_BIT;
11121 inst.instruction |= Rn << 8;
11122 inst.instruction |= Rm << 16;
11123 inst.instruction |= inst.operands[1].imm;
11128 /* Some mov with immediate shift have narrow variants.
11129 Register shifts are handled above. */
11130 if (low_regs && inst.operands[1].shifted
11131 && (inst.instruction == T_MNEM_mov
11132 || inst.instruction == T_MNEM_movs))
11134 if (in_it_block ())
11135 narrow = (inst.instruction == T_MNEM_mov);
11137 narrow = (inst.instruction == T_MNEM_movs);
11142 switch (inst.operands[1].shift_kind)
11144 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11145 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11146 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11147 default: narrow = FALSE; break;
11153 inst.instruction |= Rn;
11154 inst.instruction |= Rm << 3;
11155 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11159 inst.instruction = THUMB_OP32 (inst.instruction);
11160 inst.instruction |= Rn << r0off;
11161 encode_thumb32_shifted_operand (1);
11165 switch (inst.instruction)
11168 /* In v4t or v5t a move of two lowregs produces unpredictable
11169 results. Don't allow this. */
11172 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11173 "MOV Rd, Rs with two low registers is not "
11174 "permitted on this architecture");
11175 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11179 inst.instruction = T_OPCODE_MOV_HR;
11180 inst.instruction |= (Rn & 0x8) << 4;
11181 inst.instruction |= (Rn & 0x7);
11182 inst.instruction |= Rm << 3;
11186 /* We know we have low registers at this point.
11187 Generate LSLS Rd, Rs, #0. */
11188 inst.instruction = T_OPCODE_LSL_I;
11189 inst.instruction |= Rn;
11190 inst.instruction |= Rm << 3;
11196 inst.instruction = T_OPCODE_CMP_LR;
11197 inst.instruction |= Rn;
11198 inst.instruction |= Rm << 3;
11202 inst.instruction = T_OPCODE_CMP_HR;
11203 inst.instruction |= (Rn & 0x8) << 4;
11204 inst.instruction |= (Rn & 0x7);
11205 inst.instruction |= Rm << 3;
11212 inst.instruction = THUMB_OP16 (inst.instruction);
11214 /* PR 10443: Do not silently ignore shifted operands. */
11215 constraint (inst.operands[1].shifted,
11216 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11218 if (inst.operands[1].isreg)
11220 if (Rn < 8 && Rm < 8)
11222 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11223 since a MOV instruction produces unpredictable results. */
11224 if (inst.instruction == T_OPCODE_MOV_I8)
11225 inst.instruction = T_OPCODE_ADD_I3;
11227 inst.instruction = T_OPCODE_CMP_LR;
11229 inst.instruction |= Rn;
11230 inst.instruction |= Rm << 3;
11234 if (inst.instruction == T_OPCODE_MOV_I8)
11235 inst.instruction = T_OPCODE_MOV_HR;
11237 inst.instruction = T_OPCODE_CMP_HR;
11243 constraint (Rn > 7,
11244 _("only lo regs allowed with immediate"));
11245 inst.instruction |= Rn << 8;
11246 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11257 top = (inst.instruction & 0x00800000) != 0;
11258 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11260 constraint (top, _(":lower16: not allowed this instruction"));
11261 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11263 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11265 constraint (!top, _(":upper16: not allowed this instruction"));
11266 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11269 Rd = inst.operands[0].reg;
11270 reject_bad_reg (Rd);
11272 inst.instruction |= Rd << 8;
11273 if (inst.reloc.type == BFD_RELOC_UNUSED)
11275 imm = inst.reloc.exp.X_add_number;
11276 inst.instruction |= (imm & 0xf000) << 4;
11277 inst.instruction |= (imm & 0x0800) << 15;
11278 inst.instruction |= (imm & 0x0700) << 4;
11279 inst.instruction |= (imm & 0x00ff);
11284 do_t_mvn_tst (void)
11288 Rn = inst.operands[0].reg;
11289 Rm = inst.operands[1].reg;
11291 if (inst.instruction == T_MNEM_cmp
11292 || inst.instruction == T_MNEM_cmn)
11293 constraint (Rn == REG_PC, BAD_PC);
11295 reject_bad_reg (Rn);
11296 reject_bad_reg (Rm);
11298 if (unified_syntax)
11300 int r0off = (inst.instruction == T_MNEM_mvn
11301 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11302 bfd_boolean narrow;
11304 if (inst.size_req == 4
11305 || inst.instruction > 0xffff
11306 || inst.operands[1].shifted
11307 || Rn > 7 || Rm > 7)
11309 else if (inst.instruction == T_MNEM_cmn)
11311 else if (THUMB_SETS_FLAGS (inst.instruction))
11312 narrow = !in_it_block ();
11314 narrow = in_it_block ();
11316 if (!inst.operands[1].isreg)
11318 /* For an immediate, we always generate a 32-bit opcode;
11319 section relaxation will shrink it later if possible. */
11320 if (inst.instruction < 0xffff)
11321 inst.instruction = THUMB_OP32 (inst.instruction);
11322 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11323 inst.instruction |= Rn << r0off;
11324 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11328 /* See if we can do this with a 16-bit instruction. */
11331 inst.instruction = THUMB_OP16 (inst.instruction);
11332 inst.instruction |= Rn;
11333 inst.instruction |= Rm << 3;
11337 constraint (inst.operands[1].shifted
11338 && inst.operands[1].immisreg,
11339 _("shift must be constant"));
11340 if (inst.instruction < 0xffff)
11341 inst.instruction = THUMB_OP32 (inst.instruction);
11342 inst.instruction |= Rn << r0off;
11343 encode_thumb32_shifted_operand (1);
11349 constraint (inst.instruction > 0xffff
11350 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11351 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11352 _("unshifted register required"));
11353 constraint (Rn > 7 || Rm > 7,
11356 inst.instruction = THUMB_OP16 (inst.instruction);
11357 inst.instruction |= Rn;
11358 inst.instruction |= Rm << 3;
11367 if (do_vfp_nsyn_mrs () == SUCCESS)
11370 Rd = inst.operands[0].reg;
11371 reject_bad_reg (Rd);
11372 inst.instruction |= Rd << 8;
11374 if (inst.operands[1].isreg)
11376 unsigned br = inst.operands[1].reg;
11377 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11378 as_bad (_("bad register for mrs"));
11380 inst.instruction |= br & (0xf << 16);
11381 inst.instruction |= (br & 0x300) >> 4;
11382 inst.instruction |= (br & SPSR_BIT) >> 2;
11386 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11388 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11390 /* PR gas/12698: The constraint is only applied for m_profile.
11391 If the user has specified -march=all, we want to ignore it as
11392 we are building for any CPU type, including non-m variants. */
11393 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11394 constraint ((flags != 0) && m_profile, _("selected processor does "
11395 "not support requested special purpose register"));
11398 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11400 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11401 _("'APSR', 'CPSR' or 'SPSR' expected"));
11403 inst.instruction |= (flags & SPSR_BIT) >> 2;
11404 inst.instruction |= inst.operands[1].imm & 0xff;
11405 inst.instruction |= 0xf0000;
11415 if (do_vfp_nsyn_msr () == SUCCESS)
11418 constraint (!inst.operands[1].isreg,
11419 _("Thumb encoding does not support an immediate here"));
11421 if (inst.operands[0].isreg)
11422 flags = (int)(inst.operands[0].reg);
11424 flags = inst.operands[0].imm;
11426 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11428 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11430 /* PR gas/12698: The constraint is only applied for m_profile.
11431 If the user has specified -march=all, we want to ignore it as
11432 we are building for any CPU type, including non-m variants. */
11433 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11434 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11435 && (bits & ~(PSR_s | PSR_f)) != 0)
11436 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11437 && bits != PSR_f)) && m_profile,
11438 _("selected processor does not support requested special "
11439 "purpose register"));
11442 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11443 "requested special purpose register"));
11445 Rn = inst.operands[1].reg;
11446 reject_bad_reg (Rn);
11448 inst.instruction |= (flags & SPSR_BIT) >> 2;
11449 inst.instruction |= (flags & 0xf0000) >> 8;
11450 inst.instruction |= (flags & 0x300) >> 4;
11451 inst.instruction |= (flags & 0xff);
11452 inst.instruction |= Rn << 16;
11458 bfd_boolean narrow;
11459 unsigned Rd, Rn, Rm;
11461 if (!inst.operands[2].present)
11462 inst.operands[2].reg = inst.operands[0].reg;
11464 Rd = inst.operands[0].reg;
11465 Rn = inst.operands[1].reg;
11466 Rm = inst.operands[2].reg;
11468 if (unified_syntax)
11470 if (inst.size_req == 4
11476 else if (inst.instruction == T_MNEM_muls)
11477 narrow = !in_it_block ();
11479 narrow = in_it_block ();
11483 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11484 constraint (Rn > 7 || Rm > 7,
11491 /* 16-bit MULS/Conditional MUL. */
11492 inst.instruction = THUMB_OP16 (inst.instruction);
11493 inst.instruction |= Rd;
11496 inst.instruction |= Rm << 3;
11498 inst.instruction |= Rn << 3;
11500 constraint (1, _("dest must overlap one source register"));
11504 constraint (inst.instruction != T_MNEM_mul,
11505 _("Thumb-2 MUL must not set flags"));
11507 inst.instruction = THUMB_OP32 (inst.instruction);
11508 inst.instruction |= Rd << 8;
11509 inst.instruction |= Rn << 16;
11510 inst.instruction |= Rm << 0;
11512 reject_bad_reg (Rd);
11513 reject_bad_reg (Rn);
11514 reject_bad_reg (Rm);
11521 unsigned RdLo, RdHi, Rn, Rm;
11523 RdLo = inst.operands[0].reg;
11524 RdHi = inst.operands[1].reg;
11525 Rn = inst.operands[2].reg;
11526 Rm = inst.operands[3].reg;
11528 reject_bad_reg (RdLo);
11529 reject_bad_reg (RdHi);
11530 reject_bad_reg (Rn);
11531 reject_bad_reg (Rm);
11533 inst.instruction |= RdLo << 12;
11534 inst.instruction |= RdHi << 8;
11535 inst.instruction |= Rn << 16;
11536 inst.instruction |= Rm;
11539 as_tsktsk (_("rdhi and rdlo must be different"));
11545 set_it_insn_type (NEUTRAL_IT_INSN);
11547 if (unified_syntax)
11549 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11551 inst.instruction = THUMB_OP32 (inst.instruction);
11552 inst.instruction |= inst.operands[0].imm;
11556 /* PR9722: Check for Thumb2 availability before
11557 generating a thumb2 nop instruction. */
11558 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11560 inst.instruction = THUMB_OP16 (inst.instruction);
11561 inst.instruction |= inst.operands[0].imm << 4;
11564 inst.instruction = 0x46c0;
11569 constraint (inst.operands[0].present,
11570 _("Thumb does not support NOP with hints"));
11571 inst.instruction = 0x46c0;
11578 if (unified_syntax)
11580 bfd_boolean narrow;
11582 if (THUMB_SETS_FLAGS (inst.instruction))
11583 narrow = !in_it_block ();
11585 narrow = in_it_block ();
11586 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11588 if (inst.size_req == 4)
11593 inst.instruction = THUMB_OP32 (inst.instruction);
11594 inst.instruction |= inst.operands[0].reg << 8;
11595 inst.instruction |= inst.operands[1].reg << 16;
11599 inst.instruction = THUMB_OP16 (inst.instruction);
11600 inst.instruction |= inst.operands[0].reg;
11601 inst.instruction |= inst.operands[1].reg << 3;
11606 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11608 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11610 inst.instruction = THUMB_OP16 (inst.instruction);
11611 inst.instruction |= inst.operands[0].reg;
11612 inst.instruction |= inst.operands[1].reg << 3;
11621 Rd = inst.operands[0].reg;
11622 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11624 reject_bad_reg (Rd);
11625 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11626 reject_bad_reg (Rn);
11628 inst.instruction |= Rd << 8;
11629 inst.instruction |= Rn << 16;
11631 if (!inst.operands[2].isreg)
11633 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11634 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11640 Rm = inst.operands[2].reg;
11641 reject_bad_reg (Rm);
11643 constraint (inst.operands[2].shifted
11644 && inst.operands[2].immisreg,
11645 _("shift must be constant"));
11646 encode_thumb32_shifted_operand (2);
11653 unsigned Rd, Rn, Rm;
11655 Rd = inst.operands[0].reg;
11656 Rn = inst.operands[1].reg;
11657 Rm = inst.operands[2].reg;
11659 reject_bad_reg (Rd);
11660 reject_bad_reg (Rn);
11661 reject_bad_reg (Rm);
11663 inst.instruction |= Rd << 8;
11664 inst.instruction |= Rn << 16;
11665 inst.instruction |= Rm;
11666 if (inst.operands[3].present)
11668 unsigned int val = inst.reloc.exp.X_add_number;
11669 constraint (inst.reloc.exp.X_op != O_constant,
11670 _("expression too complex"));
11671 inst.instruction |= (val & 0x1c) << 10;
11672 inst.instruction |= (val & 0x03) << 6;
11679 if (!inst.operands[3].present)
11683 inst.instruction &= ~0x00000020;
11685 /* PR 10168. Swap the Rm and Rn registers. */
11686 Rtmp = inst.operands[1].reg;
11687 inst.operands[1].reg = inst.operands[2].reg;
11688 inst.operands[2].reg = Rtmp;
11696 if (inst.operands[0].immisreg)
11697 reject_bad_reg (inst.operands[0].imm);
11699 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11703 do_t_push_pop (void)
11707 constraint (inst.operands[0].writeback,
11708 _("push/pop do not support {reglist}^"));
11709 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11710 _("expression too complex"));
11712 mask = inst.operands[0].imm;
11713 if ((mask & ~0xff) == 0)
11714 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11715 else if ((inst.instruction == T_MNEM_push
11716 && (mask & ~0xff) == 1 << REG_LR)
11717 || (inst.instruction == T_MNEM_pop
11718 && (mask & ~0xff) == 1 << REG_PC))
11720 inst.instruction = THUMB_OP16 (inst.instruction);
11721 inst.instruction |= THUMB_PP_PC_LR;
11722 inst.instruction |= mask & 0xff;
11724 else if (unified_syntax)
11726 inst.instruction = THUMB_OP32 (inst.instruction);
11727 encode_thumb2_ldmstm (13, mask, TRUE);
11731 inst.error = _("invalid register list to push/pop instruction");
11741 Rd = inst.operands[0].reg;
11742 Rm = inst.operands[1].reg;
11744 reject_bad_reg (Rd);
11745 reject_bad_reg (Rm);
11747 inst.instruction |= Rd << 8;
11748 inst.instruction |= Rm << 16;
11749 inst.instruction |= Rm;
11757 Rd = inst.operands[0].reg;
11758 Rm = inst.operands[1].reg;
11760 reject_bad_reg (Rd);
11761 reject_bad_reg (Rm);
11763 if (Rd <= 7 && Rm <= 7
11764 && inst.size_req != 4)
11766 inst.instruction = THUMB_OP16 (inst.instruction);
11767 inst.instruction |= Rd;
11768 inst.instruction |= Rm << 3;
11770 else if (unified_syntax)
11772 inst.instruction = THUMB_OP32 (inst.instruction);
11773 inst.instruction |= Rd << 8;
11774 inst.instruction |= Rm << 16;
11775 inst.instruction |= Rm;
11778 inst.error = BAD_HIREG;
11786 Rd = inst.operands[0].reg;
11787 Rm = inst.operands[1].reg;
11789 reject_bad_reg (Rd);
11790 reject_bad_reg (Rm);
11792 inst.instruction |= Rd << 8;
11793 inst.instruction |= Rm;
11801 Rd = inst.operands[0].reg;
11802 Rs = (inst.operands[1].present
11803 ? inst.operands[1].reg /* Rd, Rs, foo */
11804 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11806 reject_bad_reg (Rd);
11807 reject_bad_reg (Rs);
11808 if (inst.operands[2].isreg)
11809 reject_bad_reg (inst.operands[2].reg);
11811 inst.instruction |= Rd << 8;
11812 inst.instruction |= Rs << 16;
11813 if (!inst.operands[2].isreg)
11815 bfd_boolean narrow;
11817 if ((inst.instruction & 0x00100000) != 0)
11818 narrow = !in_it_block ();
11820 narrow = in_it_block ();
11822 if (Rd > 7 || Rs > 7)
11825 if (inst.size_req == 4 || !unified_syntax)
11828 if (inst.reloc.exp.X_op != O_constant
11829 || inst.reloc.exp.X_add_number != 0)
11832 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11833 relaxation, but it doesn't seem worth the hassle. */
11836 inst.reloc.type = BFD_RELOC_UNUSED;
11837 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11838 inst.instruction |= Rs << 3;
11839 inst.instruction |= Rd;
11843 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11844 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11848 encode_thumb32_shifted_operand (2);
11854 if (warn_on_deprecated
11855 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11856 as_warn (_("setend use is deprecated for ARMv8"));
11858 set_it_insn_type (OUTSIDE_IT_INSN);
11859 if (inst.operands[0].imm)
11860 inst.instruction |= 0x8;
11866 if (!inst.operands[1].present)
11867 inst.operands[1].reg = inst.operands[0].reg;
11869 if (unified_syntax)
11871 bfd_boolean narrow;
11874 switch (inst.instruction)
11877 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11879 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11881 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11883 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11887 if (THUMB_SETS_FLAGS (inst.instruction))
11888 narrow = !in_it_block ();
11890 narrow = in_it_block ();
11891 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11893 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11895 if (inst.operands[2].isreg
11896 && (inst.operands[1].reg != inst.operands[0].reg
11897 || inst.operands[2].reg > 7))
11899 if (inst.size_req == 4)
11902 reject_bad_reg (inst.operands[0].reg);
11903 reject_bad_reg (inst.operands[1].reg);
11907 if (inst.operands[2].isreg)
11909 reject_bad_reg (inst.operands[2].reg);
11910 inst.instruction = THUMB_OP32 (inst.instruction);
11911 inst.instruction |= inst.operands[0].reg << 8;
11912 inst.instruction |= inst.operands[1].reg << 16;
11913 inst.instruction |= inst.operands[2].reg;
11915 /* PR 12854: Error on extraneous shifts. */
11916 constraint (inst.operands[2].shifted,
11917 _("extraneous shift as part of operand to shift insn"));
11921 inst.operands[1].shifted = 1;
11922 inst.operands[1].shift_kind = shift_kind;
11923 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11924 ? T_MNEM_movs : T_MNEM_mov);
11925 inst.instruction |= inst.operands[0].reg << 8;
11926 encode_thumb32_shifted_operand (1);
11927 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11928 inst.reloc.type = BFD_RELOC_UNUSED;
11933 if (inst.operands[2].isreg)
11935 switch (shift_kind)
11937 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11938 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11939 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11940 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11944 inst.instruction |= inst.operands[0].reg;
11945 inst.instruction |= inst.operands[2].reg << 3;
11947 /* PR 12854: Error on extraneous shifts. */
11948 constraint (inst.operands[2].shifted,
11949 _("extraneous shift as part of operand to shift insn"));
11953 switch (shift_kind)
11955 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11956 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11957 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11960 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11961 inst.instruction |= inst.operands[0].reg;
11962 inst.instruction |= inst.operands[1].reg << 3;
11968 constraint (inst.operands[0].reg > 7
11969 || inst.operands[1].reg > 7, BAD_HIREG);
11970 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11972 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11974 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11975 constraint (inst.operands[0].reg != inst.operands[1].reg,
11976 _("source1 and dest must be same register"));
11978 switch (inst.instruction)
11980 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11981 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11982 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11983 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11987 inst.instruction |= inst.operands[0].reg;
11988 inst.instruction |= inst.operands[2].reg << 3;
11990 /* PR 12854: Error on extraneous shifts. */
11991 constraint (inst.operands[2].shifted,
11992 _("extraneous shift as part of operand to shift insn"));
11996 switch (inst.instruction)
11998 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11999 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
12000 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
12001 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
12004 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12005 inst.instruction |= inst.operands[0].reg;
12006 inst.instruction |= inst.operands[1].reg << 3;
12014 unsigned Rd, Rn, Rm;
12016 Rd = inst.operands[0].reg;
12017 Rn = inst.operands[1].reg;
12018 Rm = inst.operands[2].reg;
12020 reject_bad_reg (Rd);
12021 reject_bad_reg (Rn);
12022 reject_bad_reg (Rm);
12024 inst.instruction |= Rd << 8;
12025 inst.instruction |= Rn << 16;
12026 inst.instruction |= Rm;
12032 unsigned Rd, Rn, Rm;
12034 Rd = inst.operands[0].reg;
12035 Rm = inst.operands[1].reg;
12036 Rn = inst.operands[2].reg;
12038 reject_bad_reg (Rd);
12039 reject_bad_reg (Rn);
12040 reject_bad_reg (Rm);
12042 inst.instruction |= Rd << 8;
12043 inst.instruction |= Rn << 16;
12044 inst.instruction |= Rm;
12050 unsigned int value = inst.reloc.exp.X_add_number;
12051 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12052 _("SMC is not permitted on this architecture"));
12053 constraint (inst.reloc.exp.X_op != O_constant,
12054 _("expression too complex"));
12055 inst.reloc.type = BFD_RELOC_UNUSED;
12056 inst.instruction |= (value & 0xf000) >> 12;
12057 inst.instruction |= (value & 0x0ff0);
12058 inst.instruction |= (value & 0x000f) << 16;
12064 unsigned int value = inst.reloc.exp.X_add_number;
12066 inst.reloc.type = BFD_RELOC_UNUSED;
12067 inst.instruction |= (value & 0x0fff);
12068 inst.instruction |= (value & 0xf000) << 4;
12072 do_t_ssat_usat (int bias)
12076 Rd = inst.operands[0].reg;
12077 Rn = inst.operands[2].reg;
12079 reject_bad_reg (Rd);
12080 reject_bad_reg (Rn);
12082 inst.instruction |= Rd << 8;
12083 inst.instruction |= inst.operands[1].imm - bias;
12084 inst.instruction |= Rn << 16;
12086 if (inst.operands[3].present)
12088 offsetT shift_amount = inst.reloc.exp.X_add_number;
12090 inst.reloc.type = BFD_RELOC_UNUSED;
12092 constraint (inst.reloc.exp.X_op != O_constant,
12093 _("expression too complex"));
12095 if (shift_amount != 0)
12097 constraint (shift_amount > 31,
12098 _("shift expression is too large"));
12100 if (inst.operands[3].shift_kind == SHIFT_ASR)
12101 inst.instruction |= 0x00200000; /* sh bit. */
12103 inst.instruction |= (shift_amount & 0x1c) << 10;
12104 inst.instruction |= (shift_amount & 0x03) << 6;
12112 do_t_ssat_usat (1);
12120 Rd = inst.operands[0].reg;
12121 Rn = inst.operands[2].reg;
12123 reject_bad_reg (Rd);
12124 reject_bad_reg (Rn);
12126 inst.instruction |= Rd << 8;
12127 inst.instruction |= inst.operands[1].imm - 1;
12128 inst.instruction |= Rn << 16;
12134 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12135 || inst.operands[2].postind || inst.operands[2].writeback
12136 || inst.operands[2].immisreg || inst.operands[2].shifted
12137 || inst.operands[2].negative,
12140 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12142 inst.instruction |= inst.operands[0].reg << 8;
12143 inst.instruction |= inst.operands[1].reg << 12;
12144 inst.instruction |= inst.operands[2].reg << 16;
12145 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12151 if (!inst.operands[2].present)
12152 inst.operands[2].reg = inst.operands[1].reg + 1;
12154 constraint (inst.operands[0].reg == inst.operands[1].reg
12155 || inst.operands[0].reg == inst.operands[2].reg
12156 || inst.operands[0].reg == inst.operands[3].reg,
12159 inst.instruction |= inst.operands[0].reg;
12160 inst.instruction |= inst.operands[1].reg << 12;
12161 inst.instruction |= inst.operands[2].reg << 8;
12162 inst.instruction |= inst.operands[3].reg << 16;
12168 unsigned Rd, Rn, Rm;
12170 Rd = inst.operands[0].reg;
12171 Rn = inst.operands[1].reg;
12172 Rm = inst.operands[2].reg;
12174 reject_bad_reg (Rd);
12175 reject_bad_reg (Rn);
12176 reject_bad_reg (Rm);
12178 inst.instruction |= Rd << 8;
12179 inst.instruction |= Rn << 16;
12180 inst.instruction |= Rm;
12181 inst.instruction |= inst.operands[3].imm << 4;
12189 Rd = inst.operands[0].reg;
12190 Rm = inst.operands[1].reg;
12192 reject_bad_reg (Rd);
12193 reject_bad_reg (Rm);
12195 if (inst.instruction <= 0xffff
12196 && inst.size_req != 4
12197 && Rd <= 7 && Rm <= 7
12198 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12200 inst.instruction = THUMB_OP16 (inst.instruction);
12201 inst.instruction |= Rd;
12202 inst.instruction |= Rm << 3;
12204 else if (unified_syntax)
12206 if (inst.instruction <= 0xffff)
12207 inst.instruction = THUMB_OP32 (inst.instruction);
12208 inst.instruction |= Rd << 8;
12209 inst.instruction |= Rm;
12210 inst.instruction |= inst.operands[2].imm << 4;
12214 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12215 _("Thumb encoding does not support rotation"));
12216 constraint (1, BAD_HIREG);
12223 /* We have to do the following check manually as ARM_EXT_OS only applies
12225 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12227 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12228 /* This only applies to the v6m howver, not later architectures. */
12229 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12230 as_bad (_("SVC is not permitted on this architecture"));
12231 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12234 inst.reloc.type = BFD_RELOC_ARM_SWI;
12243 half = (inst.instruction & 0x10) != 0;
12244 set_it_insn_type_last ();
12245 constraint (inst.operands[0].immisreg,
12246 _("instruction requires register index"));
12248 Rn = inst.operands[0].reg;
12249 Rm = inst.operands[0].imm;
12251 constraint (Rn == REG_SP, BAD_SP);
12252 reject_bad_reg (Rm);
12254 constraint (!half && inst.operands[0].shifted,
12255 _("instruction does not allow shifted index"));
12256 inst.instruction |= (Rn << 16) | Rm;
12262 do_t_ssat_usat (0);
12270 Rd = inst.operands[0].reg;
12271 Rn = inst.operands[2].reg;
12273 reject_bad_reg (Rd);
12274 reject_bad_reg (Rn);
12276 inst.instruction |= Rd << 8;
12277 inst.instruction |= inst.operands[1].imm;
12278 inst.instruction |= Rn << 16;
12281 /* Neon instruction encoder helpers. */
12283 /* Encodings for the different types for various Neon opcodes. */
12285 /* An "invalid" code for the following tables. */
12288 struct neon_tab_entry
12291 unsigned float_or_poly;
12292 unsigned scalar_or_imm;
12295 /* Map overloaded Neon opcodes to their respective encodings. */
12296 #define NEON_ENC_TAB \
12297 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12298 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12299 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12300 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12301 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12302 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12303 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12304 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12305 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12306 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12307 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12308 /* Register variants of the following two instructions are encoded as
12309 vcge / vcgt with the operands reversed. */ \
12310 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12311 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12312 X(vfma, N_INV, 0x0000c10, N_INV), \
12313 X(vfms, N_INV, 0x0200c10, N_INV), \
12314 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12315 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12316 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12317 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12318 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12319 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12320 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12321 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12322 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12323 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12324 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12325 X(vshl, 0x0000400, N_INV, 0x0800510), \
12326 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12327 X(vand, 0x0000110, N_INV, 0x0800030), \
12328 X(vbic, 0x0100110, N_INV, 0x0800030), \
12329 X(veor, 0x1000110, N_INV, N_INV), \
12330 X(vorn, 0x0300110, N_INV, 0x0800010), \
12331 X(vorr, 0x0200110, N_INV, 0x0800010), \
12332 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12333 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12334 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12335 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12336 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12337 X(vst1, 0x0000000, 0x0800000, N_INV), \
12338 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12339 X(vst2, 0x0000100, 0x0800100, N_INV), \
12340 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12341 X(vst3, 0x0000200, 0x0800200, N_INV), \
12342 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12343 X(vst4, 0x0000300, 0x0800300, N_INV), \
12344 X(vmovn, 0x1b20200, N_INV, N_INV), \
12345 X(vtrn, 0x1b20080, N_INV, N_INV), \
12346 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12347 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12348 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12349 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12350 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12351 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12352 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12353 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12354 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12355 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12356 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12357 X(vseleq, 0xe000a00, N_INV, N_INV), \
12358 X(vselvs, 0xe100a00, N_INV, N_INV), \
12359 X(vselge, 0xe200a00, N_INV, N_INV), \
12360 X(vselgt, 0xe300a00, N_INV, N_INV), \
12361 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12362 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12363 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12364 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12365 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12366 X(aes, 0x3b00300, N_INV, N_INV), \
12367 X(sha3op, 0x2000c00, N_INV, N_INV), \
12368 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12369 X(sha2op, 0x3ba0380, N_INV, N_INV)
12373 #define X(OPC,I,F,S) N_MNEM_##OPC
12378 static const struct neon_tab_entry neon_enc_tab[] =
12380 #define X(OPC,I,F,S) { (I), (F), (S) }
12385 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12386 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12387 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12388 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12389 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12390 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12391 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12392 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12393 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12394 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12395 #define NEON_ENC_SINGLE_(X) \
12396 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12397 #define NEON_ENC_DOUBLE_(X) \
12398 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12399 #define NEON_ENC_FPV8_(X) \
12400 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12402 #define NEON_ENCODE(type, inst) \
12405 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12406 inst.is_neon = 1; \
12410 #define check_neon_suffixes \
12413 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12415 as_bad (_("invalid neon suffix for non neon instruction")); \
12421 /* Define shapes for instruction operands. The following mnemonic characters
12422 are used in this table:
12424 F - VFP S<n> register
12425 D - Neon D<n> register
12426 Q - Neon Q<n> register
12430 L - D<n> register list
12432 This table is used to generate various data:
12433 - enumerations of the form NS_DDR to be used as arguments to
12435 - a table classifying shapes into single, double, quad, mixed.
12436 - a table used to drive neon_select_shape. */
12438 #define NEON_SHAPE_DEF \
12439 X(3, (D, D, D), DOUBLE), \
12440 X(3, (Q, Q, Q), QUAD), \
12441 X(3, (D, D, I), DOUBLE), \
12442 X(3, (Q, Q, I), QUAD), \
12443 X(3, (D, D, S), DOUBLE), \
12444 X(3, (Q, Q, S), QUAD), \
12445 X(2, (D, D), DOUBLE), \
12446 X(2, (Q, Q), QUAD), \
12447 X(2, (D, S), DOUBLE), \
12448 X(2, (Q, S), QUAD), \
12449 X(2, (D, R), DOUBLE), \
12450 X(2, (Q, R), QUAD), \
12451 X(2, (D, I), DOUBLE), \
12452 X(2, (Q, I), QUAD), \
12453 X(3, (D, L, D), DOUBLE), \
12454 X(2, (D, Q), MIXED), \
12455 X(2, (Q, D), MIXED), \
12456 X(3, (D, Q, I), MIXED), \
12457 X(3, (Q, D, I), MIXED), \
12458 X(3, (Q, D, D), MIXED), \
12459 X(3, (D, Q, Q), MIXED), \
12460 X(3, (Q, Q, D), MIXED), \
12461 X(3, (Q, D, S), MIXED), \
12462 X(3, (D, Q, S), MIXED), \
12463 X(4, (D, D, D, I), DOUBLE), \
12464 X(4, (Q, Q, Q, I), QUAD), \
12465 X(2, (F, F), SINGLE), \
12466 X(3, (F, F, F), SINGLE), \
12467 X(2, (F, I), SINGLE), \
12468 X(2, (F, D), MIXED), \
12469 X(2, (D, F), MIXED), \
12470 X(3, (F, F, I), MIXED), \
12471 X(4, (R, R, F, F), SINGLE), \
12472 X(4, (F, F, R, R), SINGLE), \
12473 X(3, (D, R, R), DOUBLE), \
12474 X(3, (R, R, D), DOUBLE), \
12475 X(2, (S, R), SINGLE), \
12476 X(2, (R, S), SINGLE), \
12477 X(2, (F, R), SINGLE), \
12478 X(2, (R, F), SINGLE)
12480 #define S2(A,B) NS_##A##B
12481 #define S3(A,B,C) NS_##A##B##C
12482 #define S4(A,B,C,D) NS_##A##B##C##D
12484 #define X(N, L, C) S##N L
12497 enum neon_shape_class
12505 #define X(N, L, C) SC_##C
12507 static enum neon_shape_class neon_shape_class[] =
12525 /* Register widths of above. */
12526 static unsigned neon_shape_el_size[] =
12537 struct neon_shape_info
12540 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12543 #define S2(A,B) { SE_##A, SE_##B }
12544 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12545 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12547 #define X(N, L, C) { N, S##N L }
12549 static struct neon_shape_info neon_shape_tab[] =
12559 /* Bit masks used in type checking given instructions.
12560 'N_EQK' means the type must be the same as (or based on in some way) the key
12561 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12562 set, various other bits can be set as well in order to modify the meaning of
12563 the type constraint. */
12565 enum neon_type_mask
12589 N_KEY = 0x1000000, /* Key element (main type specifier). */
12590 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12591 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12592 N_UNT = 0x8000000, /* Must be explicitly untyped. */
12593 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12594 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12595 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12596 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12597 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12598 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12599 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12601 N_MAX_NONSPECIAL = N_P64
12604 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12606 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12607 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12608 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12609 #define N_SUF_32 (N_SU_32 | N_F32)
12610 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12611 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12613 /* Pass this as the first type argument to neon_check_type to ignore types
12615 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12617 /* Select a "shape" for the current instruction (describing register types or
12618 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12619 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12620 function of operand parsing, so this function doesn't need to be called.
12621 Shapes should be listed in order of decreasing length. */
12623 static enum neon_shape
12624 neon_select_shape (enum neon_shape shape, ...)
12627 enum neon_shape first_shape = shape;
12629 /* Fix missing optional operands. FIXME: we don't know at this point how
12630 many arguments we should have, so this makes the assumption that we have
12631 > 1. This is true of all current Neon opcodes, I think, but may not be
12632 true in the future. */
12633 if (!inst.operands[1].present)
12634 inst.operands[1] = inst.operands[0];
12636 va_start (ap, shape);
12638 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12643 for (j = 0; j < neon_shape_tab[shape].els; j++)
12645 if (!inst.operands[j].present)
12651 switch (neon_shape_tab[shape].el[j])
12654 if (!(inst.operands[j].isreg
12655 && inst.operands[j].isvec
12656 && inst.operands[j].issingle
12657 && !inst.operands[j].isquad))
12662 if (!(inst.operands[j].isreg
12663 && inst.operands[j].isvec
12664 && !inst.operands[j].isquad
12665 && !inst.operands[j].issingle))
12670 if (!(inst.operands[j].isreg
12671 && !inst.operands[j].isvec))
12676 if (!(inst.operands[j].isreg
12677 && inst.operands[j].isvec
12678 && inst.operands[j].isquad
12679 && !inst.operands[j].issingle))
12684 if (!(!inst.operands[j].isreg
12685 && !inst.operands[j].isscalar))
12690 if (!(!inst.operands[j].isreg
12691 && inst.operands[j].isscalar))
12701 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12702 /* We've matched all the entries in the shape table, and we don't
12703 have any left over operands which have not been matched. */
12709 if (shape == NS_NULL && first_shape != NS_NULL)
12710 first_error (_("invalid instruction shape"));
12715 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12716 means the Q bit should be set). */
12719 neon_quad (enum neon_shape shape)
12721 return neon_shape_class[shape] == SC_QUAD;
12725 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12728 /* Allow modification to be made to types which are constrained to be
12729 based on the key element, based on bits set alongside N_EQK. */
12730 if ((typebits & N_EQK) != 0)
12732 if ((typebits & N_HLF) != 0)
12734 else if ((typebits & N_DBL) != 0)
12736 if ((typebits & N_SGN) != 0)
12737 *g_type = NT_signed;
12738 else if ((typebits & N_UNS) != 0)
12739 *g_type = NT_unsigned;
12740 else if ((typebits & N_INT) != 0)
12741 *g_type = NT_integer;
12742 else if ((typebits & N_FLT) != 0)
12743 *g_type = NT_float;
12744 else if ((typebits & N_SIZ) != 0)
12745 *g_type = NT_untyped;
12749 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12750 operand type, i.e. the single type specified in a Neon instruction when it
12751 is the only one given. */
12753 static struct neon_type_el
12754 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12756 struct neon_type_el dest = *key;
12758 gas_assert ((thisarg & N_EQK) != 0);
12760 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12765 /* Convert Neon type and size into compact bitmask representation. */
12767 static enum neon_type_mask
12768 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12775 case 8: return N_8;
12776 case 16: return N_16;
12777 case 32: return N_32;
12778 case 64: return N_64;
12786 case 8: return N_I8;
12787 case 16: return N_I16;
12788 case 32: return N_I32;
12789 case 64: return N_I64;
12797 case 16: return N_F16;
12798 case 32: return N_F32;
12799 case 64: return N_F64;
12807 case 8: return N_P8;
12808 case 16: return N_P16;
12809 case 64: return N_P64;
12817 case 8: return N_S8;
12818 case 16: return N_S16;
12819 case 32: return N_S32;
12820 case 64: return N_S64;
12828 case 8: return N_U8;
12829 case 16: return N_U16;
12830 case 32: return N_U32;
12831 case 64: return N_U64;
12842 /* Convert compact Neon bitmask type representation to a type and size. Only
12843 handles the case where a single bit is set in the mask. */
12846 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12847 enum neon_type_mask mask)
12849 if ((mask & N_EQK) != 0)
12852 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12854 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
12856 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12858 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
12863 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12865 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12866 *type = NT_unsigned;
12867 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12868 *type = NT_integer;
12869 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12870 *type = NT_untyped;
12871 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
12873 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
12881 /* Modify a bitmask of allowed types. This is only needed for type
12885 modify_types_allowed (unsigned allowed, unsigned mods)
12888 enum neon_el_type type;
12894 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12896 if (el_type_of_type_chk (&type, &size,
12897 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12899 neon_modify_type_size (mods, &type, &size);
12900 destmask |= type_chk_of_el_type (type, size);
12907 /* Check type and return type classification.
12908 The manual states (paraphrase): If one datatype is given, it indicates the
12910 - the second operand, if there is one
12911 - the operand, if there is no second operand
12912 - the result, if there are no operands.
12913 This isn't quite good enough though, so we use a concept of a "key" datatype
12914 which is set on a per-instruction basis, which is the one which matters when
12915 only one data type is written.
12916 Note: this function has side-effects (e.g. filling in missing operands). All
12917 Neon instructions should call it before performing bit encoding. */
12919 static struct neon_type_el
12920 neon_check_type (unsigned els, enum neon_shape ns, ...)
12923 unsigned i, pass, key_el = 0;
12924 unsigned types[NEON_MAX_TYPE_ELS];
12925 enum neon_el_type k_type = NT_invtype;
12926 unsigned k_size = -1u;
12927 struct neon_type_el badtype = {NT_invtype, -1};
12928 unsigned key_allowed = 0;
12930 /* Optional registers in Neon instructions are always (not) in operand 1.
12931 Fill in the missing operand here, if it was omitted. */
12932 if (els > 1 && !inst.operands[1].present)
12933 inst.operands[1] = inst.operands[0];
12935 /* Suck up all the varargs. */
12937 for (i = 0; i < els; i++)
12939 unsigned thisarg = va_arg (ap, unsigned);
12940 if (thisarg == N_IGNORE_TYPE)
12945 types[i] = thisarg;
12946 if ((thisarg & N_KEY) != 0)
12951 if (inst.vectype.elems > 0)
12952 for (i = 0; i < els; i++)
12953 if (inst.operands[i].vectype.type != NT_invtype)
12955 first_error (_("types specified in both the mnemonic and operands"));
12959 /* Duplicate inst.vectype elements here as necessary.
12960 FIXME: No idea if this is exactly the same as the ARM assembler,
12961 particularly when an insn takes one register and one non-register
12963 if (inst.vectype.elems == 1 && els > 1)
12966 inst.vectype.elems = els;
12967 inst.vectype.el[key_el] = inst.vectype.el[0];
12968 for (j = 0; j < els; j++)
12970 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12973 else if (inst.vectype.elems == 0 && els > 0)
12976 /* No types were given after the mnemonic, so look for types specified
12977 after each operand. We allow some flexibility here; as long as the
12978 "key" operand has a type, we can infer the others. */
12979 for (j = 0; j < els; j++)
12980 if (inst.operands[j].vectype.type != NT_invtype)
12981 inst.vectype.el[j] = inst.operands[j].vectype;
12983 if (inst.operands[key_el].vectype.type != NT_invtype)
12985 for (j = 0; j < els; j++)
12986 if (inst.operands[j].vectype.type == NT_invtype)
12987 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12992 first_error (_("operand types can't be inferred"));
12996 else if (inst.vectype.elems != els)
12998 first_error (_("type specifier has the wrong number of parts"));
13002 for (pass = 0; pass < 2; pass++)
13004 for (i = 0; i < els; i++)
13006 unsigned thisarg = types[i];
13007 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
13008 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
13009 enum neon_el_type g_type = inst.vectype.el[i].type;
13010 unsigned g_size = inst.vectype.el[i].size;
13012 /* Decay more-specific signed & unsigned types to sign-insensitive
13013 integer types if sign-specific variants are unavailable. */
13014 if ((g_type == NT_signed || g_type == NT_unsigned)
13015 && (types_allowed & N_SU_ALL) == 0)
13016 g_type = NT_integer;
13018 /* If only untyped args are allowed, decay any more specific types to
13019 them. Some instructions only care about signs for some element
13020 sizes, so handle that properly. */
13021 if (((types_allowed & N_UNT) == 0)
13022 && ((g_size == 8 && (types_allowed & N_8) != 0)
13023 || (g_size == 16 && (types_allowed & N_16) != 0)
13024 || (g_size == 32 && (types_allowed & N_32) != 0)
13025 || (g_size == 64 && (types_allowed & N_64) != 0)))
13026 g_type = NT_untyped;
13030 if ((thisarg & N_KEY) != 0)
13034 key_allowed = thisarg & ~N_KEY;
13039 if ((thisarg & N_VFP) != 0)
13041 enum neon_shape_el regshape;
13042 unsigned regwidth, match;
13044 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13047 first_error (_("invalid instruction shape"));
13050 regshape = neon_shape_tab[ns].el[i];
13051 regwidth = neon_shape_el_size[regshape];
13053 /* In VFP mode, operands must match register widths. If we
13054 have a key operand, use its width, else use the width of
13055 the current operand. */
13061 if (regwidth != match)
13063 first_error (_("operand size must match register width"));
13068 if ((thisarg & N_EQK) == 0)
13070 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13072 if ((given_type & types_allowed) == 0)
13074 first_error (_("bad type in Neon instruction"));
13080 enum neon_el_type mod_k_type = k_type;
13081 unsigned mod_k_size = k_size;
13082 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13083 if (g_type != mod_k_type || g_size != mod_k_size)
13085 first_error (_("inconsistent types in Neon instruction"));
13093 return inst.vectype.el[key_el];
13096 /* Neon-style VFP instruction forwarding. */
13098 /* Thumb VFP instructions have 0xE in the condition field. */
13101 do_vfp_cond_or_thumb (void)
13106 inst.instruction |= 0xe0000000;
13108 inst.instruction |= inst.cond << 28;
13111 /* Look up and encode a simple mnemonic, for use as a helper function for the
13112 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13113 etc. It is assumed that operand parsing has already been done, and that the
13114 operands are in the form expected by the given opcode (this isn't necessarily
13115 the same as the form in which they were parsed, hence some massaging must
13116 take place before this function is called).
13117 Checks current arch version against that in the looked-up opcode. */
13120 do_vfp_nsyn_opcode (const char *opname)
13122 const struct asm_opcode *opcode;
13124 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13129 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13130 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13137 inst.instruction = opcode->tvalue;
13138 opcode->tencode ();
13142 inst.instruction = (inst.cond << 28) | opcode->avalue;
13143 opcode->aencode ();
13148 do_vfp_nsyn_add_sub (enum neon_shape rs)
13150 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13155 do_vfp_nsyn_opcode ("fadds");
13157 do_vfp_nsyn_opcode ("fsubs");
13162 do_vfp_nsyn_opcode ("faddd");
13164 do_vfp_nsyn_opcode ("fsubd");
13168 /* Check operand types to see if this is a VFP instruction, and if so call
13172 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13174 enum neon_shape rs;
13175 struct neon_type_el et;
13180 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13181 et = neon_check_type (2, rs,
13182 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13186 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13187 et = neon_check_type (3, rs,
13188 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13195 if (et.type != NT_invtype)
13206 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13208 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13213 do_vfp_nsyn_opcode ("fmacs");
13215 do_vfp_nsyn_opcode ("fnmacs");
13220 do_vfp_nsyn_opcode ("fmacd");
13222 do_vfp_nsyn_opcode ("fnmacd");
13227 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13229 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13234 do_vfp_nsyn_opcode ("ffmas");
13236 do_vfp_nsyn_opcode ("ffnmas");
13241 do_vfp_nsyn_opcode ("ffmad");
13243 do_vfp_nsyn_opcode ("ffnmad");
13248 do_vfp_nsyn_mul (enum neon_shape rs)
13251 do_vfp_nsyn_opcode ("fmuls");
13253 do_vfp_nsyn_opcode ("fmuld");
13257 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13259 int is_neg = (inst.instruction & 0x80) != 0;
13260 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13265 do_vfp_nsyn_opcode ("fnegs");
13267 do_vfp_nsyn_opcode ("fabss");
13272 do_vfp_nsyn_opcode ("fnegd");
13274 do_vfp_nsyn_opcode ("fabsd");
13278 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13279 insns belong to Neon, and are handled elsewhere. */
13282 do_vfp_nsyn_ldm_stm (int is_dbmode)
13284 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13288 do_vfp_nsyn_opcode ("fldmdbs");
13290 do_vfp_nsyn_opcode ("fldmias");
13295 do_vfp_nsyn_opcode ("fstmdbs");
13297 do_vfp_nsyn_opcode ("fstmias");
13302 do_vfp_nsyn_sqrt (void)
13304 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13305 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13308 do_vfp_nsyn_opcode ("fsqrts");
13310 do_vfp_nsyn_opcode ("fsqrtd");
13314 do_vfp_nsyn_div (void)
13316 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13317 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13318 N_F32 | N_F64 | N_KEY | N_VFP);
13321 do_vfp_nsyn_opcode ("fdivs");
13323 do_vfp_nsyn_opcode ("fdivd");
13327 do_vfp_nsyn_nmul (void)
13329 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13330 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13331 N_F32 | N_F64 | N_KEY | N_VFP);
13335 NEON_ENCODE (SINGLE, inst);
13336 do_vfp_sp_dyadic ();
13340 NEON_ENCODE (DOUBLE, inst);
13341 do_vfp_dp_rd_rn_rm ();
13343 do_vfp_cond_or_thumb ();
13347 do_vfp_nsyn_cmp (void)
13349 if (inst.operands[1].isreg)
13351 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13352 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13356 NEON_ENCODE (SINGLE, inst);
13357 do_vfp_sp_monadic ();
13361 NEON_ENCODE (DOUBLE, inst);
13362 do_vfp_dp_rd_rm ();
13367 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13368 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13370 switch (inst.instruction & 0x0fffffff)
13373 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13376 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13384 NEON_ENCODE (SINGLE, inst);
13385 do_vfp_sp_compare_z ();
13389 NEON_ENCODE (DOUBLE, inst);
13393 do_vfp_cond_or_thumb ();
13397 nsyn_insert_sp (void)
13399 inst.operands[1] = inst.operands[0];
13400 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13401 inst.operands[0].reg = REG_SP;
13402 inst.operands[0].isreg = 1;
13403 inst.operands[0].writeback = 1;
13404 inst.operands[0].present = 1;
13408 do_vfp_nsyn_push (void)
13411 if (inst.operands[1].issingle)
13412 do_vfp_nsyn_opcode ("fstmdbs");
13414 do_vfp_nsyn_opcode ("fstmdbd");
13418 do_vfp_nsyn_pop (void)
13421 if (inst.operands[1].issingle)
13422 do_vfp_nsyn_opcode ("fldmias");
13424 do_vfp_nsyn_opcode ("fldmiad");
13427 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13428 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13431 neon_dp_fixup (struct arm_it* insn)
13433 unsigned int i = insn->instruction;
13438 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13449 insn->instruction = i;
13452 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13456 neon_logbits (unsigned x)
13458 return ffs (x) - 4;
13461 #define LOW4(R) ((R) & 0xf)
13462 #define HI1(R) (((R) >> 4) & 1)
13464 /* Encode insns with bit pattern:
13466 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13467 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13469 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13470 different meaning for some instruction. */
13473 neon_three_same (int isquad, int ubit, int size)
13475 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13476 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13477 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13478 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13479 inst.instruction |= LOW4 (inst.operands[2].reg);
13480 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13481 inst.instruction |= (isquad != 0) << 6;
13482 inst.instruction |= (ubit != 0) << 24;
13484 inst.instruction |= neon_logbits (size) << 20;
13486 neon_dp_fixup (&inst);
13489 /* Encode instructions of the form:
13491 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13492 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13494 Don't write size if SIZE == -1. */
13497 neon_two_same (int qbit, int ubit, int size)
13499 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13500 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13501 inst.instruction |= LOW4 (inst.operands[1].reg);
13502 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13503 inst.instruction |= (qbit != 0) << 6;
13504 inst.instruction |= (ubit != 0) << 24;
13507 inst.instruction |= neon_logbits (size) << 18;
13509 neon_dp_fixup (&inst);
13512 /* Neon instruction encoders, in approximate order of appearance. */
13515 do_neon_dyadic_i_su (void)
13517 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13518 struct neon_type_el et = neon_check_type (3, rs,
13519 N_EQK, N_EQK, N_SU_32 | N_KEY);
13520 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13524 do_neon_dyadic_i64_su (void)
13526 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13527 struct neon_type_el et = neon_check_type (3, rs,
13528 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13529 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13533 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13536 unsigned size = et.size >> 3;
13537 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13538 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13539 inst.instruction |= LOW4 (inst.operands[1].reg);
13540 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13541 inst.instruction |= (isquad != 0) << 6;
13542 inst.instruction |= immbits << 16;
13543 inst.instruction |= (size >> 3) << 7;
13544 inst.instruction |= (size & 0x7) << 19;
13546 inst.instruction |= (uval != 0) << 24;
13548 neon_dp_fixup (&inst);
13552 do_neon_shl_imm (void)
13554 if (!inst.operands[2].isreg)
13556 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13557 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13558 NEON_ENCODE (IMMED, inst);
13559 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13563 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13564 struct neon_type_el et = neon_check_type (3, rs,
13565 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13568 /* VSHL/VQSHL 3-register variants have syntax such as:
13570 whereas other 3-register operations encoded by neon_three_same have
13573 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13575 tmp = inst.operands[2].reg;
13576 inst.operands[2].reg = inst.operands[1].reg;
13577 inst.operands[1].reg = tmp;
13578 NEON_ENCODE (INTEGER, inst);
13579 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13584 do_neon_qshl_imm (void)
13586 if (!inst.operands[2].isreg)
13588 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13589 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13591 NEON_ENCODE (IMMED, inst);
13592 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13593 inst.operands[2].imm);
13597 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13598 struct neon_type_el et = neon_check_type (3, rs,
13599 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13602 /* See note in do_neon_shl_imm. */
13603 tmp = inst.operands[2].reg;
13604 inst.operands[2].reg = inst.operands[1].reg;
13605 inst.operands[1].reg = tmp;
13606 NEON_ENCODE (INTEGER, inst);
13607 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13612 do_neon_rshl (void)
13614 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13615 struct neon_type_el et = neon_check_type (3, rs,
13616 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13619 tmp = inst.operands[2].reg;
13620 inst.operands[2].reg = inst.operands[1].reg;
13621 inst.operands[1].reg = tmp;
13622 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13626 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13628 /* Handle .I8 pseudo-instructions. */
13631 /* Unfortunately, this will make everything apart from zero out-of-range.
13632 FIXME is this the intended semantics? There doesn't seem much point in
13633 accepting .I8 if so. */
13634 immediate |= immediate << 8;
13640 if (immediate == (immediate & 0x000000ff))
13642 *immbits = immediate;
13645 else if (immediate == (immediate & 0x0000ff00))
13647 *immbits = immediate >> 8;
13650 else if (immediate == (immediate & 0x00ff0000))
13652 *immbits = immediate >> 16;
13655 else if (immediate == (immediate & 0xff000000))
13657 *immbits = immediate >> 24;
13660 if ((immediate & 0xffff) != (immediate >> 16))
13661 goto bad_immediate;
13662 immediate &= 0xffff;
13665 if (immediate == (immediate & 0x000000ff))
13667 *immbits = immediate;
13670 else if (immediate == (immediate & 0x0000ff00))
13672 *immbits = immediate >> 8;
13677 first_error (_("immediate value out of range"));
13681 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13685 neon_bits_same_in_bytes (unsigned imm)
13687 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13688 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13689 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13690 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13693 /* For immediate of above form, return 0bABCD. */
13696 neon_squash_bits (unsigned imm)
13698 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13699 | ((imm & 0x01000000) >> 21);
13702 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13705 neon_qfloat_bits (unsigned imm)
13707 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13710 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13711 the instruction. *OP is passed as the initial value of the op field, and
13712 may be set to a different value depending on the constant (i.e.
13713 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13714 MVN). If the immediate looks like a repeated pattern then also
13715 try smaller element sizes. */
13718 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13719 unsigned *immbits, int *op, int size,
13720 enum neon_el_type type)
13722 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13724 if (type == NT_float && !float_p)
13727 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13729 if (size != 32 || *op == 1)
13731 *immbits = neon_qfloat_bits (immlo);
13737 if (neon_bits_same_in_bytes (immhi)
13738 && neon_bits_same_in_bytes (immlo))
13742 *immbits = (neon_squash_bits (immhi) << 4)
13743 | neon_squash_bits (immlo);
13748 if (immhi != immlo)
13754 if (immlo == (immlo & 0x000000ff))
13759 else if (immlo == (immlo & 0x0000ff00))
13761 *immbits = immlo >> 8;
13764 else if (immlo == (immlo & 0x00ff0000))
13766 *immbits = immlo >> 16;
13769 else if (immlo == (immlo & 0xff000000))
13771 *immbits = immlo >> 24;
13774 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13776 *immbits = (immlo >> 8) & 0xff;
13779 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13781 *immbits = (immlo >> 16) & 0xff;
13785 if ((immlo & 0xffff) != (immlo >> 16))
13792 if (immlo == (immlo & 0x000000ff))
13797 else if (immlo == (immlo & 0x0000ff00))
13799 *immbits = immlo >> 8;
13803 if ((immlo & 0xff) != (immlo >> 8))
13808 if (immlo == (immlo & 0x000000ff))
13810 /* Don't allow MVN with 8-bit immediate. */
13820 /* Write immediate bits [7:0] to the following locations:
13822 |28/24|23 19|18 16|15 4|3 0|
13823 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13825 This function is used by VMOV/VMVN/VORR/VBIC. */
13828 neon_write_immbits (unsigned immbits)
13830 inst.instruction |= immbits & 0xf;
13831 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13832 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13835 /* Invert low-order SIZE bits of XHI:XLO. */
13838 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13840 unsigned immlo = xlo ? *xlo : 0;
13841 unsigned immhi = xhi ? *xhi : 0;
13846 immlo = (~immlo) & 0xff;
13850 immlo = (~immlo) & 0xffff;
13854 immhi = (~immhi) & 0xffffffff;
13855 /* fall through. */
13858 immlo = (~immlo) & 0xffffffff;
13873 do_neon_logic (void)
13875 if (inst.operands[2].present && inst.operands[2].isreg)
13877 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13878 neon_check_type (3, rs, N_IGNORE_TYPE);
13879 /* U bit and size field were set as part of the bitmask. */
13880 NEON_ENCODE (INTEGER, inst);
13881 neon_three_same (neon_quad (rs), 0, -1);
13885 const int three_ops_form = (inst.operands[2].present
13886 && !inst.operands[2].isreg);
13887 const int immoperand = (three_ops_form ? 2 : 1);
13888 enum neon_shape rs = (three_ops_form
13889 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13890 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13891 struct neon_type_el et = neon_check_type (2, rs,
13892 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13893 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13897 if (et.type == NT_invtype)
13900 if (three_ops_form)
13901 constraint (inst.operands[0].reg != inst.operands[1].reg,
13902 _("first and second operands shall be the same register"));
13904 NEON_ENCODE (IMMED, inst);
13906 immbits = inst.operands[immoperand].imm;
13909 /* .i64 is a pseudo-op, so the immediate must be a repeating
13911 if (immbits != (inst.operands[immoperand].regisimm ?
13912 inst.operands[immoperand].reg : 0))
13914 /* Set immbits to an invalid constant. */
13915 immbits = 0xdeadbeef;
13922 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13926 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13930 /* Pseudo-instruction for VBIC. */
13931 neon_invert_size (&immbits, 0, et.size);
13932 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13936 /* Pseudo-instruction for VORR. */
13937 neon_invert_size (&immbits, 0, et.size);
13938 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13948 inst.instruction |= neon_quad (rs) << 6;
13949 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13950 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13951 inst.instruction |= cmode << 8;
13952 neon_write_immbits (immbits);
13954 neon_dp_fixup (&inst);
13959 do_neon_bitfield (void)
13961 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13962 neon_check_type (3, rs, N_IGNORE_TYPE);
13963 neon_three_same (neon_quad (rs), 0, -1);
13967 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13970 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13971 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13973 if (et.type == NT_float)
13975 NEON_ENCODE (FLOAT, inst);
13976 neon_three_same (neon_quad (rs), 0, -1);
13980 NEON_ENCODE (INTEGER, inst);
13981 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13986 do_neon_dyadic_if_su (void)
13988 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13992 do_neon_dyadic_if_su_d (void)
13994 /* This version only allow D registers, but that constraint is enforced during
13995 operand parsing so we don't need to do anything extra here. */
13996 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
14000 do_neon_dyadic_if_i_d (void)
14002 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14003 affected if we specify unsigned args. */
14004 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14007 enum vfp_or_neon_is_neon_bits
14010 NEON_CHECK_ARCH = 2,
14011 NEON_CHECK_ARCH8 = 4
14014 /* Call this function if an instruction which may have belonged to the VFP or
14015 Neon instruction sets, but turned out to be a Neon instruction (due to the
14016 operand types involved, etc.). We have to check and/or fix-up a couple of
14019 - Make sure the user hasn't attempted to make a Neon instruction
14021 - Alter the value in the condition code field if necessary.
14022 - Make sure that the arch supports Neon instructions.
14024 Which of these operations take place depends on bits from enum
14025 vfp_or_neon_is_neon_bits.
14027 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14028 current instruction's condition is COND_ALWAYS, the condition field is
14029 changed to inst.uncond_value. This is necessary because instructions shared
14030 between VFP and Neon may be conditional for the VFP variants only, and the
14031 unconditional Neon version must have, e.g., 0xF in the condition field. */
14034 vfp_or_neon_is_neon (unsigned check)
14036 /* Conditions are always legal in Thumb mode (IT blocks). */
14037 if (!thumb_mode && (check & NEON_CHECK_CC))
14039 if (inst.cond != COND_ALWAYS)
14041 first_error (_(BAD_COND));
14044 if (inst.uncond_value != -1)
14045 inst.instruction |= inst.uncond_value << 28;
14048 if ((check & NEON_CHECK_ARCH)
14049 && !mark_feature_used (&fpu_neon_ext_v1))
14051 first_error (_(BAD_FPU));
14055 if ((check & NEON_CHECK_ARCH8)
14056 && !mark_feature_used (&fpu_neon_ext_armv8))
14058 first_error (_(BAD_FPU));
14066 do_neon_addsub_if_i (void)
14068 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14071 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14074 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14075 affected if we specify unsigned args. */
14076 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14079 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14081 V<op> A,B (A is operand 0, B is operand 2)
14086 so handle that case specially. */
14089 neon_exchange_operands (void)
14091 void *scratch = alloca (sizeof (inst.operands[0]));
14092 if (inst.operands[1].present)
14094 /* Swap operands[1] and operands[2]. */
14095 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14096 inst.operands[1] = inst.operands[2];
14097 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14101 inst.operands[1] = inst.operands[2];
14102 inst.operands[2] = inst.operands[0];
14107 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14109 if (inst.operands[2].isreg)
14112 neon_exchange_operands ();
14113 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14117 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14118 struct neon_type_el et = neon_check_type (2, rs,
14119 N_EQK | N_SIZ, immtypes | N_KEY);
14121 NEON_ENCODE (IMMED, inst);
14122 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14123 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14124 inst.instruction |= LOW4 (inst.operands[1].reg);
14125 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14126 inst.instruction |= neon_quad (rs) << 6;
14127 inst.instruction |= (et.type == NT_float) << 10;
14128 inst.instruction |= neon_logbits (et.size) << 18;
14130 neon_dp_fixup (&inst);
14137 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14141 do_neon_cmp_inv (void)
14143 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14149 neon_compare (N_IF_32, N_IF_32, FALSE);
14152 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14153 scalars, which are encoded in 5 bits, M : Rm.
14154 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14155 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14159 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14161 unsigned regno = NEON_SCALAR_REG (scalar);
14162 unsigned elno = NEON_SCALAR_INDEX (scalar);
14167 if (regno > 7 || elno > 3)
14169 return regno | (elno << 3);
14172 if (regno > 15 || elno > 1)
14174 return regno | (elno << 4);
14178 first_error (_("scalar out of range for multiply instruction"));
14184 /* Encode multiply / multiply-accumulate scalar instructions. */
14187 neon_mul_mac (struct neon_type_el et, int ubit)
14191 /* Give a more helpful error message if we have an invalid type. */
14192 if (et.type == NT_invtype)
14195 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14196 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14197 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14198 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14199 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14200 inst.instruction |= LOW4 (scalar);
14201 inst.instruction |= HI1 (scalar) << 5;
14202 inst.instruction |= (et.type == NT_float) << 8;
14203 inst.instruction |= neon_logbits (et.size) << 20;
14204 inst.instruction |= (ubit != 0) << 24;
14206 neon_dp_fixup (&inst);
14210 do_neon_mac_maybe_scalar (void)
14212 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14215 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14218 if (inst.operands[2].isscalar)
14220 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14221 struct neon_type_el et = neon_check_type (3, rs,
14222 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14223 NEON_ENCODE (SCALAR, inst);
14224 neon_mul_mac (et, neon_quad (rs));
14228 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14229 affected if we specify unsigned args. */
14230 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14235 do_neon_fmac (void)
14237 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14240 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14243 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14249 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14250 struct neon_type_el et = neon_check_type (3, rs,
14251 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14252 neon_three_same (neon_quad (rs), 0, et.size);
14255 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14256 same types as the MAC equivalents. The polynomial type for this instruction
14257 is encoded the same as the integer type. */
14262 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14265 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14268 if (inst.operands[2].isscalar)
14269 do_neon_mac_maybe_scalar ();
14271 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14275 do_neon_qdmulh (void)
14277 if (inst.operands[2].isscalar)
14279 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14280 struct neon_type_el et = neon_check_type (3, rs,
14281 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14282 NEON_ENCODE (SCALAR, inst);
14283 neon_mul_mac (et, neon_quad (rs));
14287 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14288 struct neon_type_el et = neon_check_type (3, rs,
14289 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14290 NEON_ENCODE (INTEGER, inst);
14291 /* The U bit (rounding) comes from bit mask. */
14292 neon_three_same (neon_quad (rs), 0, et.size);
14297 do_neon_fcmp_absolute (void)
14299 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14300 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14301 /* Size field comes from bit mask. */
14302 neon_three_same (neon_quad (rs), 1, -1);
14306 do_neon_fcmp_absolute_inv (void)
14308 neon_exchange_operands ();
14309 do_neon_fcmp_absolute ();
14313 do_neon_step (void)
14315 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14316 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14317 neon_three_same (neon_quad (rs), 0, -1);
14321 do_neon_abs_neg (void)
14323 enum neon_shape rs;
14324 struct neon_type_el et;
14326 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14329 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14332 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14333 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14335 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14336 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14337 inst.instruction |= LOW4 (inst.operands[1].reg);
14338 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14339 inst.instruction |= neon_quad (rs) << 6;
14340 inst.instruction |= (et.type == NT_float) << 10;
14341 inst.instruction |= neon_logbits (et.size) << 18;
14343 neon_dp_fixup (&inst);
14349 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14350 struct neon_type_el et = neon_check_type (2, rs,
14351 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14352 int imm = inst.operands[2].imm;
14353 constraint (imm < 0 || (unsigned)imm >= et.size,
14354 _("immediate out of range for insert"));
14355 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14361 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14362 struct neon_type_el et = neon_check_type (2, rs,
14363 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14364 int imm = inst.operands[2].imm;
14365 constraint (imm < 1 || (unsigned)imm > et.size,
14366 _("immediate out of range for insert"));
14367 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14371 do_neon_qshlu_imm (void)
14373 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14374 struct neon_type_el et = neon_check_type (2, rs,
14375 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14376 int imm = inst.operands[2].imm;
14377 constraint (imm < 0 || (unsigned)imm >= et.size,
14378 _("immediate out of range for shift"));
14379 /* Only encodes the 'U present' variant of the instruction.
14380 In this case, signed types have OP (bit 8) set to 0.
14381 Unsigned types have OP set to 1. */
14382 inst.instruction |= (et.type == NT_unsigned) << 8;
14383 /* The rest of the bits are the same as other immediate shifts. */
14384 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14388 do_neon_qmovn (void)
14390 struct neon_type_el et = neon_check_type (2, NS_DQ,
14391 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14392 /* Saturating move where operands can be signed or unsigned, and the
14393 destination has the same signedness. */
14394 NEON_ENCODE (INTEGER, inst);
14395 if (et.type == NT_unsigned)
14396 inst.instruction |= 0xc0;
14398 inst.instruction |= 0x80;
14399 neon_two_same (0, 1, et.size / 2);
14403 do_neon_qmovun (void)
14405 struct neon_type_el et = neon_check_type (2, NS_DQ,
14406 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14407 /* Saturating move with unsigned results. Operands must be signed. */
14408 NEON_ENCODE (INTEGER, inst);
14409 neon_two_same (0, 1, et.size / 2);
14413 do_neon_rshift_sat_narrow (void)
14415 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14416 or unsigned. If operands are unsigned, results must also be unsigned. */
14417 struct neon_type_el et = neon_check_type (2, NS_DQI,
14418 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14419 int imm = inst.operands[2].imm;
14420 /* This gets the bounds check, size encoding and immediate bits calculation
14424 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14425 VQMOVN.I<size> <Dd>, <Qm>. */
14428 inst.operands[2].present = 0;
14429 inst.instruction = N_MNEM_vqmovn;
14434 constraint (imm < 1 || (unsigned)imm > et.size,
14435 _("immediate out of range"));
14436 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14440 do_neon_rshift_sat_narrow_u (void)
14442 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14443 or unsigned. If operands are unsigned, results must also be unsigned. */
14444 struct neon_type_el et = neon_check_type (2, NS_DQI,
14445 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14446 int imm = inst.operands[2].imm;
14447 /* This gets the bounds check, size encoding and immediate bits calculation
14451 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14452 VQMOVUN.I<size> <Dd>, <Qm>. */
14455 inst.operands[2].present = 0;
14456 inst.instruction = N_MNEM_vqmovun;
14461 constraint (imm < 1 || (unsigned)imm > et.size,
14462 _("immediate out of range"));
14463 /* FIXME: The manual is kind of unclear about what value U should have in
14464 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14466 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14470 do_neon_movn (void)
14472 struct neon_type_el et = neon_check_type (2, NS_DQ,
14473 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14474 NEON_ENCODE (INTEGER, inst);
14475 neon_two_same (0, 1, et.size / 2);
14479 do_neon_rshift_narrow (void)
14481 struct neon_type_el et = neon_check_type (2, NS_DQI,
14482 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14483 int imm = inst.operands[2].imm;
14484 /* This gets the bounds check, size encoding and immediate bits calculation
14488 /* If immediate is zero then we are a pseudo-instruction for
14489 VMOVN.I<size> <Dd>, <Qm> */
14492 inst.operands[2].present = 0;
14493 inst.instruction = N_MNEM_vmovn;
14498 constraint (imm < 1 || (unsigned)imm > et.size,
14499 _("immediate out of range for narrowing operation"));
14500 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14504 do_neon_shll (void)
14506 /* FIXME: Type checking when lengthening. */
14507 struct neon_type_el et = neon_check_type (2, NS_QDI,
14508 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14509 unsigned imm = inst.operands[2].imm;
14511 if (imm == et.size)
14513 /* Maximum shift variant. */
14514 NEON_ENCODE (INTEGER, inst);
14515 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14516 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14517 inst.instruction |= LOW4 (inst.operands[1].reg);
14518 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14519 inst.instruction |= neon_logbits (et.size) << 18;
14521 neon_dp_fixup (&inst);
14525 /* A more-specific type check for non-max versions. */
14526 et = neon_check_type (2, NS_QDI,
14527 N_EQK | N_DBL, N_SU_32 | N_KEY);
14528 NEON_ENCODE (IMMED, inst);
14529 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14533 /* Check the various types for the VCVT instruction, and return which version
14534 the current instruction is. */
14536 #define CVT_FLAVOUR_VAR \
14537 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14538 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14539 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14540 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14541 /* Half-precision conversions. */ \
14542 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14543 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14544 /* VFP instructions. */ \
14545 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14546 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14547 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14548 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14549 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14550 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14551 /* VFP instructions with bitshift. */ \
14552 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14553 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14554 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14555 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14556 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14557 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14558 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14559 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14561 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14562 neon_cvt_flavour_##C,
14564 /* The different types of conversions we can do. */
14565 enum neon_cvt_flavour
14568 neon_cvt_flavour_invalid,
14569 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14574 static enum neon_cvt_flavour
14575 get_neon_cvt_flavour (enum neon_shape rs)
14577 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14578 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14579 if (et.type != NT_invtype) \
14581 inst.error = NULL; \
14582 return (neon_cvt_flavour_##C); \
14585 struct neon_type_el et;
14586 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14587 || rs == NS_FF) ? N_VFP : 0;
14588 /* The instruction versions which take an immediate take one register
14589 argument, which is extended to the width of the full register. Thus the
14590 "source" and "destination" registers must have the same width. Hack that
14591 here by making the size equal to the key (wider, in this case) operand. */
14592 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14596 return neon_cvt_flavour_invalid;
14611 /* Neon-syntax VFP conversions. */
14614 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
14616 const char *opname = 0;
14618 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14620 /* Conversions with immediate bitshift. */
14621 const char *enc[] =
14623 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14629 if (flavour < (int) ARRAY_SIZE (enc))
14631 opname = enc[flavour];
14632 constraint (inst.operands[0].reg != inst.operands[1].reg,
14633 _("operands 0 and 1 must be the same register"));
14634 inst.operands[1] = inst.operands[2];
14635 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14640 /* Conversions without bitshift. */
14641 const char *enc[] =
14643 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14649 if (flavour < (int) ARRAY_SIZE (enc))
14650 opname = enc[flavour];
14654 do_vfp_nsyn_opcode (opname);
14658 do_vfp_nsyn_cvtz (void)
14660 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14661 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14662 const char *enc[] =
14664 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14670 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14671 do_vfp_nsyn_opcode (enc[flavour]);
14675 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
14676 enum neon_cvt_mode mode)
14681 set_it_insn_type (OUTSIDE_IT_INSN);
14685 case neon_cvt_flavour_s32_f64:
14689 case neon_cvt_flavour_s32_f32:
14693 case neon_cvt_flavour_u32_f64:
14697 case neon_cvt_flavour_u32_f32:
14702 first_error (_("invalid instruction shape"));
14708 case neon_cvt_mode_a: rm = 0; break;
14709 case neon_cvt_mode_n: rm = 1; break;
14710 case neon_cvt_mode_p: rm = 2; break;
14711 case neon_cvt_mode_m: rm = 3; break;
14712 default: first_error (_("invalid rounding mode")); return;
14715 NEON_ENCODE (FPV8, inst);
14716 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14717 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
14718 inst.instruction |= sz << 8;
14719 inst.instruction |= op << 7;
14720 inst.instruction |= rm << 16;
14721 inst.instruction |= 0xf0000000;
14722 inst.is_neon = TRUE;
14726 do_neon_cvt_1 (enum neon_cvt_mode mode)
14728 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14729 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14730 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14732 /* PR11109: Handle round-to-zero for VCVT conversions. */
14733 if (mode == neon_cvt_mode_z
14734 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14735 && (flavour == neon_cvt_flavour_s32_f32
14736 || flavour == neon_cvt_flavour_u32_f32
14737 || flavour == neon_cvt_flavour_s32_f64
14738 || flavour == neon_cvt_flavour_u32_f64)
14739 && (rs == NS_FD || rs == NS_FF))
14741 do_vfp_nsyn_cvtz ();
14745 /* VFP rather than Neon conversions. */
14746 if (flavour >= neon_cvt_flavour_first_fp)
14748 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14749 do_vfp_nsyn_cvt (rs, flavour);
14751 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14762 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14764 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14767 /* Fixed-point conversion with #0 immediate is encoded as an
14768 integer conversion. */
14769 if (inst.operands[2].present && inst.operands[2].imm == 0)
14771 immbits = 32 - inst.operands[2].imm;
14772 NEON_ENCODE (IMMED, inst);
14773 if (flavour != neon_cvt_flavour_invalid)
14774 inst.instruction |= enctab[flavour];
14775 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14776 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14777 inst.instruction |= LOW4 (inst.operands[1].reg);
14778 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14779 inst.instruction |= neon_quad (rs) << 6;
14780 inst.instruction |= 1 << 21;
14781 inst.instruction |= immbits << 16;
14783 neon_dp_fixup (&inst);
14789 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
14791 NEON_ENCODE (FLOAT, inst);
14792 set_it_insn_type (OUTSIDE_IT_INSN);
14794 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
14797 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14798 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14799 inst.instruction |= LOW4 (inst.operands[1].reg);
14800 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14801 inst.instruction |= neon_quad (rs) << 6;
14802 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
14803 inst.instruction |= mode << 8;
14805 inst.instruction |= 0xfc000000;
14807 inst.instruction |= 0xf0000000;
14813 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14815 NEON_ENCODE (INTEGER, inst);
14817 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14820 if (flavour != neon_cvt_flavour_invalid)
14821 inst.instruction |= enctab[flavour];
14823 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14824 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14825 inst.instruction |= LOW4 (inst.operands[1].reg);
14826 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14827 inst.instruction |= neon_quad (rs) << 6;
14828 inst.instruction |= 2 << 18;
14830 neon_dp_fixup (&inst);
14835 /* Half-precision conversions for Advanced SIMD -- neon. */
14840 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14842 as_bad (_("operand size must match register width"));
14847 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14849 as_bad (_("operand size must match register width"));
14854 inst.instruction = 0x3b60600;
14856 inst.instruction = 0x3b60700;
14858 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14859 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14860 inst.instruction |= LOW4 (inst.operands[1].reg);
14861 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14862 neon_dp_fixup (&inst);
14866 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14867 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14868 do_vfp_nsyn_cvt (rs, flavour);
14870 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14875 do_neon_cvtr (void)
14877 do_neon_cvt_1 (neon_cvt_mode_x);
14883 do_neon_cvt_1 (neon_cvt_mode_z);
14887 do_neon_cvta (void)
14889 do_neon_cvt_1 (neon_cvt_mode_a);
14893 do_neon_cvtn (void)
14895 do_neon_cvt_1 (neon_cvt_mode_n);
14899 do_neon_cvtp (void)
14901 do_neon_cvt_1 (neon_cvt_mode_p);
14905 do_neon_cvtm (void)
14907 do_neon_cvt_1 (neon_cvt_mode_m);
14911 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
14914 mark_feature_used (&fpu_vfp_ext_armv8);
14916 encode_arm_vfp_reg (inst.operands[0].reg,
14917 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
14918 encode_arm_vfp_reg (inst.operands[1].reg,
14919 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
14920 inst.instruction |= to ? 0x10000 : 0;
14921 inst.instruction |= t ? 0x80 : 0;
14922 inst.instruction |= is_double ? 0x100 : 0;
14923 do_vfp_cond_or_thumb ();
14927 do_neon_cvttb_1 (bfd_boolean t)
14929 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
14933 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
14936 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
14938 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
14941 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
14943 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
14946 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
14948 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
14951 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
14958 do_neon_cvtb (void)
14960 do_neon_cvttb_1 (FALSE);
14965 do_neon_cvtt (void)
14967 do_neon_cvttb_1 (TRUE);
14971 neon_move_immediate (void)
14973 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14974 struct neon_type_el et = neon_check_type (2, rs,
14975 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14976 unsigned immlo, immhi = 0, immbits;
14977 int op, cmode, float_p;
14979 constraint (et.type == NT_invtype,
14980 _("operand size must be specified for immediate VMOV"));
14982 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14983 op = (inst.instruction & (1 << 5)) != 0;
14985 immlo = inst.operands[1].imm;
14986 if (inst.operands[1].regisimm)
14987 immhi = inst.operands[1].reg;
14989 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14990 _("immediate has bits set outside the operand size"));
14992 float_p = inst.operands[1].immisfloat;
14994 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14995 et.size, et.type)) == FAIL)
14997 /* Invert relevant bits only. */
14998 neon_invert_size (&immlo, &immhi, et.size);
14999 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15000 with one or the other; those cases are caught by
15001 neon_cmode_for_move_imm. */
15003 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
15004 &op, et.size, et.type)) == FAIL)
15006 first_error (_("immediate out of range"));
15011 inst.instruction &= ~(1 << 5);
15012 inst.instruction |= op << 5;
15014 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15015 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15016 inst.instruction |= neon_quad (rs) << 6;
15017 inst.instruction |= cmode << 8;
15019 neon_write_immbits (immbits);
15025 if (inst.operands[1].isreg)
15027 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15029 NEON_ENCODE (INTEGER, inst);
15030 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15031 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15032 inst.instruction |= LOW4 (inst.operands[1].reg);
15033 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15034 inst.instruction |= neon_quad (rs) << 6;
15038 NEON_ENCODE (IMMED, inst);
15039 neon_move_immediate ();
15042 neon_dp_fixup (&inst);
15045 /* Encode instructions of form:
15047 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15048 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15051 neon_mixed_length (struct neon_type_el et, unsigned size)
15053 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15054 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15055 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15056 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15057 inst.instruction |= LOW4 (inst.operands[2].reg);
15058 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15059 inst.instruction |= (et.type == NT_unsigned) << 24;
15060 inst.instruction |= neon_logbits (size) << 20;
15062 neon_dp_fixup (&inst);
15066 do_neon_dyadic_long (void)
15068 /* FIXME: Type checking for lengthening op. */
15069 struct neon_type_el et = neon_check_type (3, NS_QDD,
15070 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15071 neon_mixed_length (et, et.size);
15075 do_neon_abal (void)
15077 struct neon_type_el et = neon_check_type (3, NS_QDD,
15078 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15079 neon_mixed_length (et, et.size);
15083 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15085 if (inst.operands[2].isscalar)
15087 struct neon_type_el et = neon_check_type (3, NS_QDS,
15088 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
15089 NEON_ENCODE (SCALAR, inst);
15090 neon_mul_mac (et, et.type == NT_unsigned);
15094 struct neon_type_el et = neon_check_type (3, NS_QDD,
15095 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
15096 NEON_ENCODE (INTEGER, inst);
15097 neon_mixed_length (et, et.size);
15102 do_neon_mac_maybe_scalar_long (void)
15104 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15108 do_neon_dyadic_wide (void)
15110 struct neon_type_el et = neon_check_type (3, NS_QQD,
15111 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15112 neon_mixed_length (et, et.size);
15116 do_neon_dyadic_narrow (void)
15118 struct neon_type_el et = neon_check_type (3, NS_QDD,
15119 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
15120 /* Operand sign is unimportant, and the U bit is part of the opcode,
15121 so force the operand type to integer. */
15122 et.type = NT_integer;
15123 neon_mixed_length (et, et.size / 2);
15127 do_neon_mul_sat_scalar_long (void)
15129 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15133 do_neon_vmull (void)
15135 if (inst.operands[2].isscalar)
15136 do_neon_mac_maybe_scalar_long ();
15139 struct neon_type_el et = neon_check_type (3, NS_QDD,
15140 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
15142 if (et.type == NT_poly)
15143 NEON_ENCODE (POLY, inst);
15145 NEON_ENCODE (INTEGER, inst);
15147 /* For polynomial encoding the U bit must be zero, and the size must
15148 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15149 obviously, as 0b10). */
15152 /* Check we're on the correct architecture. */
15153 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15155 _("Instruction form not available on this architecture.");
15160 neon_mixed_length (et, et.size);
15167 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
15168 struct neon_type_el et = neon_check_type (3, rs,
15169 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15170 unsigned imm = (inst.operands[3].imm * et.size) / 8;
15172 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15173 _("shift out of range"));
15174 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15175 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15176 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15177 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15178 inst.instruction |= LOW4 (inst.operands[2].reg);
15179 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15180 inst.instruction |= neon_quad (rs) << 6;
15181 inst.instruction |= imm << 8;
15183 neon_dp_fixup (&inst);
15189 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15190 struct neon_type_el et = neon_check_type (2, rs,
15191 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15192 unsigned op = (inst.instruction >> 7) & 3;
15193 /* N (width of reversed regions) is encoded as part of the bitmask. We
15194 extract it here to check the elements to be reversed are smaller.
15195 Otherwise we'd get a reserved instruction. */
15196 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15197 gas_assert (elsize != 0);
15198 constraint (et.size >= elsize,
15199 _("elements must be smaller than reversal region"));
15200 neon_two_same (neon_quad (rs), 1, et.size);
15206 if (inst.operands[1].isscalar)
15208 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15209 struct neon_type_el et = neon_check_type (2, rs,
15210 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15211 unsigned sizebits = et.size >> 3;
15212 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15213 int logsize = neon_logbits (et.size);
15214 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15216 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15219 NEON_ENCODE (SCALAR, inst);
15220 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15221 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15222 inst.instruction |= LOW4 (dm);
15223 inst.instruction |= HI1 (dm) << 5;
15224 inst.instruction |= neon_quad (rs) << 6;
15225 inst.instruction |= x << 17;
15226 inst.instruction |= sizebits << 16;
15228 neon_dp_fixup (&inst);
15232 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15233 struct neon_type_el et = neon_check_type (2, rs,
15234 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15235 /* Duplicate ARM register to lanes of vector. */
15236 NEON_ENCODE (ARMREG, inst);
15239 case 8: inst.instruction |= 0x400000; break;
15240 case 16: inst.instruction |= 0x000020; break;
15241 case 32: inst.instruction |= 0x000000; break;
15244 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15245 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15246 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15247 inst.instruction |= neon_quad (rs) << 21;
15248 /* The encoding for this instruction is identical for the ARM and Thumb
15249 variants, except for the condition field. */
15250 do_vfp_cond_or_thumb ();
15254 /* VMOV has particularly many variations. It can be one of:
15255 0. VMOV<c><q> <Qd>, <Qm>
15256 1. VMOV<c><q> <Dd>, <Dm>
15257 (Register operations, which are VORR with Rm = Rn.)
15258 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15259 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15261 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15262 (ARM register to scalar.)
15263 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15264 (Two ARM registers to vector.)
15265 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15266 (Scalar to ARM register.)
15267 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15268 (Vector to two ARM registers.)
15269 8. VMOV.F32 <Sd>, <Sm>
15270 9. VMOV.F64 <Dd>, <Dm>
15271 (VFP register moves.)
15272 10. VMOV.F32 <Sd>, #imm
15273 11. VMOV.F64 <Dd>, #imm
15274 (VFP float immediate load.)
15275 12. VMOV <Rd>, <Sm>
15276 (VFP single to ARM reg.)
15277 13. VMOV <Sd>, <Rm>
15278 (ARM reg to VFP single.)
15279 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15280 (Two ARM regs to two VFP singles.)
15281 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15282 (Two VFP singles to two ARM regs.)
15284 These cases can be disambiguated using neon_select_shape, except cases 1/9
15285 and 3/11 which depend on the operand type too.
15287 All the encoded bits are hardcoded by this function.
15289 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15290 Cases 5, 7 may be used with VFPv2 and above.
15292 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15293 can specify a type where it doesn't make sense to, and is ignored). */
15298 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15299 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15301 struct neon_type_el et;
15302 const char *ldconst = 0;
15306 case NS_DD: /* case 1/9. */
15307 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15308 /* It is not an error here if no type is given. */
15310 if (et.type == NT_float && et.size == 64)
15312 do_vfp_nsyn_opcode ("fcpyd");
15315 /* fall through. */
15317 case NS_QQ: /* case 0/1. */
15319 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15321 /* The architecture manual I have doesn't explicitly state which
15322 value the U bit should have for register->register moves, but
15323 the equivalent VORR instruction has U = 0, so do that. */
15324 inst.instruction = 0x0200110;
15325 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15326 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15327 inst.instruction |= LOW4 (inst.operands[1].reg);
15328 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15329 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15330 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15331 inst.instruction |= neon_quad (rs) << 6;
15333 neon_dp_fixup (&inst);
15337 case NS_DI: /* case 3/11. */
15338 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15340 if (et.type == NT_float && et.size == 64)
15342 /* case 11 (fconstd). */
15343 ldconst = "fconstd";
15344 goto encode_fconstd;
15346 /* fall through. */
15348 case NS_QI: /* case 2/3. */
15349 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15351 inst.instruction = 0x0800010;
15352 neon_move_immediate ();
15353 neon_dp_fixup (&inst);
15356 case NS_SR: /* case 4. */
15358 unsigned bcdebits = 0;
15360 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15361 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15363 /* .<size> is optional here, defaulting to .32. */
15364 if (inst.vectype.elems == 0
15365 && inst.operands[0].vectype.type == NT_invtype
15366 && inst.operands[1].vectype.type == NT_invtype)
15368 inst.vectype.el[0].type = NT_untyped;
15369 inst.vectype.el[0].size = 32;
15370 inst.vectype.elems = 1;
15373 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15374 logsize = neon_logbits (et.size);
15376 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15378 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15379 && et.size != 32, _(BAD_FPU));
15380 constraint (et.type == NT_invtype, _("bad type for scalar"));
15381 constraint (x >= 64 / et.size, _("scalar index out of range"));
15385 case 8: bcdebits = 0x8; break;
15386 case 16: bcdebits = 0x1; break;
15387 case 32: bcdebits = 0x0; break;
15391 bcdebits |= x << logsize;
15393 inst.instruction = 0xe000b10;
15394 do_vfp_cond_or_thumb ();
15395 inst.instruction |= LOW4 (dn) << 16;
15396 inst.instruction |= HI1 (dn) << 7;
15397 inst.instruction |= inst.operands[1].reg << 12;
15398 inst.instruction |= (bcdebits & 3) << 5;
15399 inst.instruction |= (bcdebits >> 2) << 21;
15403 case NS_DRR: /* case 5 (fmdrr). */
15404 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15407 inst.instruction = 0xc400b10;
15408 do_vfp_cond_or_thumb ();
15409 inst.instruction |= LOW4 (inst.operands[0].reg);
15410 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15411 inst.instruction |= inst.operands[1].reg << 12;
15412 inst.instruction |= inst.operands[2].reg << 16;
15415 case NS_RS: /* case 6. */
15418 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15419 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15420 unsigned abcdebits = 0;
15422 /* .<dt> is optional here, defaulting to .32. */
15423 if (inst.vectype.elems == 0
15424 && inst.operands[0].vectype.type == NT_invtype
15425 && inst.operands[1].vectype.type == NT_invtype)
15427 inst.vectype.el[0].type = NT_untyped;
15428 inst.vectype.el[0].size = 32;
15429 inst.vectype.elems = 1;
15432 et = neon_check_type (2, NS_NULL,
15433 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15434 logsize = neon_logbits (et.size);
15436 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15438 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15439 && et.size != 32, _(BAD_FPU));
15440 constraint (et.type == NT_invtype, _("bad type for scalar"));
15441 constraint (x >= 64 / et.size, _("scalar index out of range"));
15445 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15446 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15447 case 32: abcdebits = 0x00; break;
15451 abcdebits |= x << logsize;
15452 inst.instruction = 0xe100b10;
15453 do_vfp_cond_or_thumb ();
15454 inst.instruction |= LOW4 (dn) << 16;
15455 inst.instruction |= HI1 (dn) << 7;
15456 inst.instruction |= inst.operands[0].reg << 12;
15457 inst.instruction |= (abcdebits & 3) << 5;
15458 inst.instruction |= (abcdebits >> 2) << 21;
15462 case NS_RRD: /* case 7 (fmrrd). */
15463 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15466 inst.instruction = 0xc500b10;
15467 do_vfp_cond_or_thumb ();
15468 inst.instruction |= inst.operands[0].reg << 12;
15469 inst.instruction |= inst.operands[1].reg << 16;
15470 inst.instruction |= LOW4 (inst.operands[2].reg);
15471 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15474 case NS_FF: /* case 8 (fcpys). */
15475 do_vfp_nsyn_opcode ("fcpys");
15478 case NS_FI: /* case 10 (fconsts). */
15479 ldconst = "fconsts";
15481 if (is_quarter_float (inst.operands[1].imm))
15483 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15484 do_vfp_nsyn_opcode (ldconst);
15487 first_error (_("immediate out of range"));
15490 case NS_RF: /* case 12 (fmrs). */
15491 do_vfp_nsyn_opcode ("fmrs");
15494 case NS_FR: /* case 13 (fmsr). */
15495 do_vfp_nsyn_opcode ("fmsr");
15498 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15499 (one of which is a list), but we have parsed four. Do some fiddling to
15500 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15502 case NS_RRFF: /* case 14 (fmrrs). */
15503 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15504 _("VFP registers must be adjacent"));
15505 inst.operands[2].imm = 2;
15506 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15507 do_vfp_nsyn_opcode ("fmrrs");
15510 case NS_FFRR: /* case 15 (fmsrr). */
15511 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15512 _("VFP registers must be adjacent"));
15513 inst.operands[1] = inst.operands[2];
15514 inst.operands[2] = inst.operands[3];
15515 inst.operands[0].imm = 2;
15516 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15517 do_vfp_nsyn_opcode ("fmsrr");
15521 /* neon_select_shape has determined that the instruction
15522 shape is wrong and has already set the error message. */
15531 do_neon_rshift_round_imm (void)
15533 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15534 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15535 int imm = inst.operands[2].imm;
15537 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15540 inst.operands[2].present = 0;
15545 constraint (imm < 1 || (unsigned)imm > et.size,
15546 _("immediate out of range for shift"));
15547 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15552 do_neon_movl (void)
15554 struct neon_type_el et = neon_check_type (2, NS_QD,
15555 N_EQK | N_DBL, N_SU_32 | N_KEY);
15556 unsigned sizebits = et.size >> 3;
15557 inst.instruction |= sizebits << 19;
15558 neon_two_same (0, et.type == NT_unsigned, -1);
15564 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15565 struct neon_type_el et = neon_check_type (2, rs,
15566 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15567 NEON_ENCODE (INTEGER, inst);
15568 neon_two_same (neon_quad (rs), 1, et.size);
15572 do_neon_zip_uzp (void)
15574 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15575 struct neon_type_el et = neon_check_type (2, rs,
15576 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15577 if (rs == NS_DD && et.size == 32)
15579 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15580 inst.instruction = N_MNEM_vtrn;
15584 neon_two_same (neon_quad (rs), 1, et.size);
15588 do_neon_sat_abs_neg (void)
15590 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15591 struct neon_type_el et = neon_check_type (2, rs,
15592 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15593 neon_two_same (neon_quad (rs), 1, et.size);
15597 do_neon_pair_long (void)
15599 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15600 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15601 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15602 inst.instruction |= (et.type == NT_unsigned) << 7;
15603 neon_two_same (neon_quad (rs), 1, et.size);
15607 do_neon_recip_est (void)
15609 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15610 struct neon_type_el et = neon_check_type (2, rs,
15611 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15612 inst.instruction |= (et.type == NT_float) << 8;
15613 neon_two_same (neon_quad (rs), 1, et.size);
15619 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15620 struct neon_type_el et = neon_check_type (2, rs,
15621 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15622 neon_two_same (neon_quad (rs), 1, et.size);
15628 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15629 struct neon_type_el et = neon_check_type (2, rs,
15630 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15631 neon_two_same (neon_quad (rs), 1, et.size);
15637 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15638 struct neon_type_el et = neon_check_type (2, rs,
15639 N_EQK | N_INT, N_8 | N_KEY);
15640 neon_two_same (neon_quad (rs), 1, et.size);
15646 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15647 neon_two_same (neon_quad (rs), 1, -1);
15651 do_neon_tbl_tbx (void)
15653 unsigned listlenbits;
15654 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15656 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15658 first_error (_("bad list length for table lookup"));
15662 listlenbits = inst.operands[1].imm - 1;
15663 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15664 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15665 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15666 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15667 inst.instruction |= LOW4 (inst.operands[2].reg);
15668 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15669 inst.instruction |= listlenbits << 8;
15671 neon_dp_fixup (&inst);
15675 do_neon_ldm_stm (void)
15677 /* P, U and L bits are part of bitmask. */
15678 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15679 unsigned offsetbits = inst.operands[1].imm * 2;
15681 if (inst.operands[1].issingle)
15683 do_vfp_nsyn_ldm_stm (is_dbmode);
15687 constraint (is_dbmode && !inst.operands[0].writeback,
15688 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15690 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15691 _("register list must contain at least 1 and at most 16 "
15694 inst.instruction |= inst.operands[0].reg << 16;
15695 inst.instruction |= inst.operands[0].writeback << 21;
15696 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15697 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15699 inst.instruction |= offsetbits;
15701 do_vfp_cond_or_thumb ();
15705 do_neon_ldr_str (void)
15707 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15709 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15710 And is UNPREDICTABLE in thumb mode. */
15712 && inst.operands[1].reg == REG_PC
15713 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
15716 inst.error = _("Use of PC here is UNPREDICTABLE");
15717 else if (warn_on_deprecated)
15718 as_warn (_("Use of PC here is deprecated"));
15721 if (inst.operands[0].issingle)
15724 do_vfp_nsyn_opcode ("flds");
15726 do_vfp_nsyn_opcode ("fsts");
15731 do_vfp_nsyn_opcode ("fldd");
15733 do_vfp_nsyn_opcode ("fstd");
15737 /* "interleave" version also handles non-interleaving register VLD1/VST1
15741 do_neon_ld_st_interleave (void)
15743 struct neon_type_el et = neon_check_type (1, NS_NULL,
15744 N_8 | N_16 | N_32 | N_64);
15745 unsigned alignbits = 0;
15747 /* The bits in this table go:
15748 0: register stride of one (0) or two (1)
15749 1,2: register list length, minus one (1, 2, 3, 4).
15750 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15751 We use -1 for invalid entries. */
15752 const int typetable[] =
15754 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15755 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15756 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15757 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15761 if (et.type == NT_invtype)
15764 if (inst.operands[1].immisalign)
15765 switch (inst.operands[1].imm >> 8)
15767 case 64: alignbits = 1; break;
15769 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15770 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15771 goto bad_alignment;
15775 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15776 goto bad_alignment;
15781 first_error (_("bad alignment"));
15785 inst.instruction |= alignbits << 4;
15786 inst.instruction |= neon_logbits (et.size) << 6;
15788 /* Bits [4:6] of the immediate in a list specifier encode register stride
15789 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15790 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15791 up the right value for "type" in a table based on this value and the given
15792 list style, then stick it back. */
15793 idx = ((inst.operands[0].imm >> 4) & 7)
15794 | (((inst.instruction >> 8) & 3) << 3);
15796 typebits = typetable[idx];
15798 constraint (typebits == -1, _("bad list type for instruction"));
15800 inst.instruction &= ~0xf00;
15801 inst.instruction |= typebits << 8;
15804 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15805 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15806 otherwise. The variable arguments are a list of pairs of legal (size, align)
15807 values, terminated with -1. */
15810 neon_alignment_bit (int size, int align, int *do_align, ...)
15813 int result = FAIL, thissize, thisalign;
15815 if (!inst.operands[1].immisalign)
15821 va_start (ap, do_align);
15825 thissize = va_arg (ap, int);
15826 if (thissize == -1)
15828 thisalign = va_arg (ap, int);
15830 if (size == thissize && align == thisalign)
15833 while (result != SUCCESS);
15837 if (result == SUCCESS)
15840 first_error (_("unsupported alignment for instruction"));
15846 do_neon_ld_st_lane (void)
15848 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15849 int align_good, do_align = 0;
15850 int logsize = neon_logbits (et.size);
15851 int align = inst.operands[1].imm >> 8;
15852 int n = (inst.instruction >> 8) & 3;
15853 int max_el = 64 / et.size;
15855 if (et.type == NT_invtype)
15858 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15859 _("bad list length"));
15860 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15861 _("scalar index out of range"));
15862 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15864 _("stride of 2 unavailable when element size is 8"));
15868 case 0: /* VLD1 / VST1. */
15869 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15871 if (align_good == FAIL)
15875 unsigned alignbits = 0;
15878 case 16: alignbits = 0x1; break;
15879 case 32: alignbits = 0x3; break;
15882 inst.instruction |= alignbits << 4;
15886 case 1: /* VLD2 / VST2. */
15887 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15889 if (align_good == FAIL)
15892 inst.instruction |= 1 << 4;
15895 case 2: /* VLD3 / VST3. */
15896 constraint (inst.operands[1].immisalign,
15897 _("can't use alignment with this instruction"));
15900 case 3: /* VLD4 / VST4. */
15901 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15902 16, 64, 32, 64, 32, 128, -1);
15903 if (align_good == FAIL)
15907 unsigned alignbits = 0;
15910 case 8: alignbits = 0x1; break;
15911 case 16: alignbits = 0x1; break;
15912 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15915 inst.instruction |= alignbits << 4;
15922 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15923 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15924 inst.instruction |= 1 << (4 + logsize);
15926 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15927 inst.instruction |= logsize << 10;
15930 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15933 do_neon_ld_dup (void)
15935 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15936 int align_good, do_align = 0;
15938 if (et.type == NT_invtype)
15941 switch ((inst.instruction >> 8) & 3)
15943 case 0: /* VLD1. */
15944 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15945 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15946 &do_align, 16, 16, 32, 32, -1);
15947 if (align_good == FAIL)
15949 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15952 case 2: inst.instruction |= 1 << 5; break;
15953 default: first_error (_("bad list length")); return;
15955 inst.instruction |= neon_logbits (et.size) << 6;
15958 case 1: /* VLD2. */
15959 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15960 &do_align, 8, 16, 16, 32, 32, 64, -1);
15961 if (align_good == FAIL)
15963 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15964 _("bad list length"));
15965 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15966 inst.instruction |= 1 << 5;
15967 inst.instruction |= neon_logbits (et.size) << 6;
15970 case 2: /* VLD3. */
15971 constraint (inst.operands[1].immisalign,
15972 _("can't use alignment with this instruction"));
15973 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15974 _("bad list length"));
15975 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15976 inst.instruction |= 1 << 5;
15977 inst.instruction |= neon_logbits (et.size) << 6;
15980 case 3: /* VLD4. */
15982 int align = inst.operands[1].imm >> 8;
15983 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15984 16, 64, 32, 64, 32, 128, -1);
15985 if (align_good == FAIL)
15987 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15988 _("bad list length"));
15989 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15990 inst.instruction |= 1 << 5;
15991 if (et.size == 32 && align == 128)
15992 inst.instruction |= 0x3 << 6;
15994 inst.instruction |= neon_logbits (et.size) << 6;
16001 inst.instruction |= do_align << 4;
16004 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16005 apart from bits [11:4]. */
16008 do_neon_ldx_stx (void)
16010 if (inst.operands[1].isreg)
16011 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16013 switch (NEON_LANE (inst.operands[0].imm))
16015 case NEON_INTERLEAVE_LANES:
16016 NEON_ENCODE (INTERLV, inst);
16017 do_neon_ld_st_interleave ();
16020 case NEON_ALL_LANES:
16021 NEON_ENCODE (DUP, inst);
16022 if (inst.instruction == N_INV)
16024 first_error ("only loads support such operands");
16031 NEON_ENCODE (LANE, inst);
16032 do_neon_ld_st_lane ();
16035 /* L bit comes from bit mask. */
16036 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16037 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16038 inst.instruction |= inst.operands[1].reg << 16;
16040 if (inst.operands[1].postind)
16042 int postreg = inst.operands[1].imm & 0xf;
16043 constraint (!inst.operands[1].immisreg,
16044 _("post-index must be a register"));
16045 constraint (postreg == 0xd || postreg == 0xf,
16046 _("bad register for post-index"));
16047 inst.instruction |= postreg;
16049 else if (inst.operands[1].writeback)
16051 inst.instruction |= 0xd;
16054 inst.instruction |= 0xf;
16057 inst.instruction |= 0xf9000000;
16059 inst.instruction |= 0xf4000000;
16064 do_vfp_nsyn_fpv8 (enum neon_shape rs)
16066 NEON_ENCODE (FPV8, inst);
16069 do_vfp_sp_dyadic ();
16071 do_vfp_dp_rd_rn_rm ();
16074 inst.instruction |= 0x100;
16076 inst.instruction |= 0xf0000000;
16082 set_it_insn_type (OUTSIDE_IT_INSN);
16084 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16085 first_error (_("invalid instruction shape"));
16091 set_it_insn_type (OUTSIDE_IT_INSN);
16093 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16096 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16099 neon_dyadic_misc (NT_untyped, N_F32, 0);
16103 do_vrint_1 (enum neon_cvt_mode mode)
16105 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16106 struct neon_type_el et;
16111 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16112 if (et.type != NT_invtype)
16114 /* VFP encodings. */
16115 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16116 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16117 set_it_insn_type (OUTSIDE_IT_INSN);
16119 NEON_ENCODE (FPV8, inst);
16121 do_vfp_sp_monadic ();
16123 do_vfp_dp_rd_rm ();
16127 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16128 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16129 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16130 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16131 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16132 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16133 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16137 inst.instruction |= (rs == NS_DD) << 8;
16138 do_vfp_cond_or_thumb ();
16142 /* Neon encodings (or something broken...). */
16144 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16146 if (et.type == NT_invtype)
16149 set_it_insn_type (OUTSIDE_IT_INSN);
16150 NEON_ENCODE (FLOAT, inst);
16152 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16155 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16156 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16157 inst.instruction |= LOW4 (inst.operands[1].reg);
16158 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16159 inst.instruction |= neon_quad (rs) << 6;
16162 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16163 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16164 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16165 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16166 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16167 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16168 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16173 inst.instruction |= 0xfc000000;
16175 inst.instruction |= 0xf0000000;
16182 do_vrint_1 (neon_cvt_mode_x);
16188 do_vrint_1 (neon_cvt_mode_z);
16194 do_vrint_1 (neon_cvt_mode_r);
16200 do_vrint_1 (neon_cvt_mode_a);
16206 do_vrint_1 (neon_cvt_mode_n);
16212 do_vrint_1 (neon_cvt_mode_p);
16218 do_vrint_1 (neon_cvt_mode_m);
16221 /* Crypto v1 instructions. */
16223 do_crypto_2op_1 (unsigned elttype, int op)
16225 set_it_insn_type (OUTSIDE_IT_INSN);
16227 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16233 NEON_ENCODE (INTEGER, inst);
16234 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16235 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16236 inst.instruction |= LOW4 (inst.operands[1].reg);
16237 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16239 inst.instruction |= op << 6;
16242 inst.instruction |= 0xfc000000;
16244 inst.instruction |= 0xf0000000;
16248 do_crypto_3op_1 (int u, int op)
16250 set_it_insn_type (OUTSIDE_IT_INSN);
16252 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16253 N_32 | N_UNT | N_KEY).type == NT_invtype)
16258 NEON_ENCODE (INTEGER, inst);
16259 neon_three_same (1, u, 8 << op);
16265 do_crypto_2op_1 (N_8, 0);
16271 do_crypto_2op_1 (N_8, 1);
16277 do_crypto_2op_1 (N_8, 2);
16283 do_crypto_2op_1 (N_8, 3);
16289 do_crypto_3op_1 (0, 0);
16295 do_crypto_3op_1 (0, 1);
16301 do_crypto_3op_1 (0, 2);
16307 do_crypto_3op_1 (0, 3);
16313 do_crypto_3op_1 (1, 0);
16319 do_crypto_3op_1 (1, 1);
16323 do_sha256su1 (void)
16325 do_crypto_3op_1 (1, 2);
16331 do_crypto_2op_1 (N_32, -1);
16337 do_crypto_2op_1 (N_32, 0);
16341 do_sha256su0 (void)
16343 do_crypto_2op_1 (N_32, 1);
16347 do_crc32_1 (unsigned int poly, unsigned int sz)
16349 unsigned int Rd = inst.operands[0].reg;
16350 unsigned int Rn = inst.operands[1].reg;
16351 unsigned int Rm = inst.operands[2].reg;
16353 set_it_insn_type (OUTSIDE_IT_INSN);
16354 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
16355 inst.instruction |= LOW4 (Rn) << 16;
16356 inst.instruction |= LOW4 (Rm);
16357 inst.instruction |= sz << (thumb_mode ? 4 : 21);
16358 inst.instruction |= poly << (thumb_mode ? 20 : 9);
16360 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
16361 as_warn (UNPRED_REG ("r15"));
16362 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
16363 as_warn (UNPRED_REG ("r13"));
16403 /* Overall per-instruction processing. */
16405 /* We need to be able to fix up arbitrary expressions in some statements.
16406 This is so that we can handle symbols that are an arbitrary distance from
16407 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16408 which returns part of an address in a form which will be valid for
16409 a data instruction. We do this by pushing the expression into a symbol
16410 in the expr_section, and creating a fix for that. */
16413 fix_new_arm (fragS * frag,
16427 /* Create an absolute valued symbol, so we have something to
16428 refer to in the object file. Unfortunately for us, gas's
16429 generic expression parsing will already have folded out
16430 any use of .set foo/.type foo %function that may have
16431 been used to set type information of the target location,
16432 that's being specified symbolically. We have to presume
16433 the user knows what they are doing. */
16437 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16439 symbol = symbol_find_or_make (name);
16440 S_SET_SEGMENT (symbol, absolute_section);
16441 symbol_set_frag (symbol, &zero_address_frag);
16442 S_SET_VALUE (symbol, exp->X_add_number);
16443 exp->X_op = O_symbol;
16444 exp->X_add_symbol = symbol;
16445 exp->X_add_number = 0;
16451 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
16452 (enum bfd_reloc_code_real) reloc);
16456 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
16457 pc_rel, (enum bfd_reloc_code_real) reloc);
16461 /* Mark whether the fix is to a THUMB instruction, or an ARM
16463 new_fix->tc_fix_data = thumb_mode;
16466 /* Create a frg for an instruction requiring relaxation. */
16468 output_relax_insn (void)
16474 /* The size of the instruction is unknown, so tie the debug info to the
16475 start of the instruction. */
16476 dwarf2_emit_insn (0);
16478 switch (inst.reloc.exp.X_op)
16481 sym = inst.reloc.exp.X_add_symbol;
16482 offset = inst.reloc.exp.X_add_number;
16486 offset = inst.reloc.exp.X_add_number;
16489 sym = make_expr_symbol (&inst.reloc.exp);
16493 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16494 inst.relax, sym, offset, NULL/*offset, opcode*/);
16495 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
16498 /* Write a 32-bit thumb instruction to buf. */
16500 put_thumb32_insn (char * buf, unsigned long insn)
16502 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16503 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16507 output_inst (const char * str)
16513 as_bad ("%s -- `%s'", inst.error, str);
16518 output_relax_insn ();
16521 if (inst.size == 0)
16524 to = frag_more (inst.size);
16525 /* PR 9814: Record the thumb mode into the current frag so that we know
16526 what type of NOP padding to use, if necessary. We override any previous
16527 setting so that if the mode has changed then the NOPS that we use will
16528 match the encoding of the last instruction in the frag. */
16529 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
16531 if (thumb_mode && (inst.size > THUMB_SIZE))
16533 gas_assert (inst.size == (2 * THUMB_SIZE));
16534 put_thumb32_insn (to, inst.instruction);
16536 else if (inst.size > INSN_SIZE)
16538 gas_assert (inst.size == (2 * INSN_SIZE));
16539 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16540 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
16543 md_number_to_chars (to, inst.instruction, inst.size);
16545 if (inst.reloc.type != BFD_RELOC_UNUSED)
16546 fix_new_arm (frag_now, to - frag_now->fr_literal,
16547 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16550 dwarf2_emit_insn (inst.size);
16554 output_it_inst (int cond, int mask, char * to)
16556 unsigned long instruction = 0xbf00;
16559 instruction |= mask;
16560 instruction |= cond << 4;
16564 to = frag_more (2);
16566 dwarf2_emit_insn (2);
16570 md_number_to_chars (to, instruction, 2);
16575 /* Tag values used in struct asm_opcode's tag field. */
16578 OT_unconditional, /* Instruction cannot be conditionalized.
16579 The ARM condition field is still 0xE. */
16580 OT_unconditionalF, /* Instruction cannot be conditionalized
16581 and carries 0xF in its ARM condition field. */
16582 OT_csuffix, /* Instruction takes a conditional suffix. */
16583 OT_csuffixF, /* Some forms of the instruction take a conditional
16584 suffix, others place 0xF where the condition field
16586 OT_cinfix3, /* Instruction takes a conditional infix,
16587 beginning at character index 3. (In
16588 unified mode, it becomes a suffix.) */
16589 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16590 tsts, cmps, cmns, and teqs. */
16591 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16592 character index 3, even in unified mode. Used for
16593 legacy instructions where suffix and infix forms
16594 may be ambiguous. */
16595 OT_csuf_or_in3, /* Instruction takes either a conditional
16596 suffix or an infix at character index 3. */
16597 OT_odd_infix_unc, /* This is the unconditional variant of an
16598 instruction that takes a conditional infix
16599 at an unusual position. In unified mode,
16600 this variant will accept a suffix. */
16601 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16602 are the conditional variants of instructions that
16603 take conditional infixes in unusual positions.
16604 The infix appears at character index
16605 (tag - OT_odd_infix_0). These are not accepted
16606 in unified mode. */
16609 /* Subroutine of md_assemble, responsible for looking up the primary
16610 opcode from the mnemonic the user wrote. STR points to the
16611 beginning of the mnemonic.
16613 This is not simply a hash table lookup, because of conditional
16614 variants. Most instructions have conditional variants, which are
16615 expressed with a _conditional affix_ to the mnemonic. If we were
16616 to encode each conditional variant as a literal string in the opcode
16617 table, it would have approximately 20,000 entries.
16619 Most mnemonics take this affix as a suffix, and in unified syntax,
16620 'most' is upgraded to 'all'. However, in the divided syntax, some
16621 instructions take the affix as an infix, notably the s-variants of
16622 the arithmetic instructions. Of those instructions, all but six
16623 have the infix appear after the third character of the mnemonic.
16625 Accordingly, the algorithm for looking up primary opcodes given
16628 1. Look up the identifier in the opcode table.
16629 If we find a match, go to step U.
16631 2. Look up the last two characters of the identifier in the
16632 conditions table. If we find a match, look up the first N-2
16633 characters of the identifier in the opcode table. If we
16634 find a match, go to step CE.
16636 3. Look up the fourth and fifth characters of the identifier in
16637 the conditions table. If we find a match, extract those
16638 characters from the identifier, and look up the remaining
16639 characters in the opcode table. If we find a match, go
16644 U. Examine the tag field of the opcode structure, in case this is
16645 one of the six instructions with its conditional infix in an
16646 unusual place. If it is, the tag tells us where to find the
16647 infix; look it up in the conditions table and set inst.cond
16648 accordingly. Otherwise, this is an unconditional instruction.
16649 Again set inst.cond accordingly. Return the opcode structure.
16651 CE. Examine the tag field to make sure this is an instruction that
16652 should receive a conditional suffix. If it is not, fail.
16653 Otherwise, set inst.cond from the suffix we already looked up,
16654 and return the opcode structure.
16656 CM. Examine the tag field to make sure this is an instruction that
16657 should receive a conditional infix after the third character.
16658 If it is not, fail. Otherwise, undo the edits to the current
16659 line of input and proceed as for case CE. */
16661 static const struct asm_opcode *
16662 opcode_lookup (char **str)
16666 const struct asm_opcode *opcode;
16667 const struct asm_cond *cond;
16670 /* Scan up to the end of the mnemonic, which must end in white space,
16671 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16672 for (base = end = *str; *end != '\0'; end++)
16673 if (*end == ' ' || *end == '.')
16679 /* Handle a possible width suffix and/or Neon type suffix. */
16684 /* The .w and .n suffixes are only valid if the unified syntax is in
16686 if (unified_syntax && end[1] == 'w')
16688 else if (unified_syntax && end[1] == 'n')
16693 inst.vectype.elems = 0;
16695 *str = end + offset;
16697 if (end[offset] == '.')
16699 /* See if we have a Neon type suffix (possible in either unified or
16700 non-unified ARM syntax mode). */
16701 if (parse_neon_type (&inst.vectype, str) == FAIL)
16704 else if (end[offset] != '\0' && end[offset] != ' ')
16710 /* Look for unaffixed or special-case affixed mnemonic. */
16711 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16716 if (opcode->tag < OT_odd_infix_0)
16718 inst.cond = COND_ALWAYS;
16722 if (warn_on_deprecated && unified_syntax)
16723 as_warn (_("conditional infixes are deprecated in unified syntax"));
16724 affix = base + (opcode->tag - OT_odd_infix_0);
16725 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16728 inst.cond = cond->value;
16732 /* Cannot have a conditional suffix on a mnemonic of less than two
16734 if (end - base < 3)
16737 /* Look for suffixed mnemonic. */
16739 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16740 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16742 if (opcode && cond)
16745 switch (opcode->tag)
16747 case OT_cinfix3_legacy:
16748 /* Ignore conditional suffixes matched on infix only mnemonics. */
16752 case OT_cinfix3_deprecated:
16753 case OT_odd_infix_unc:
16754 if (!unified_syntax)
16756 /* else fall through */
16760 case OT_csuf_or_in3:
16761 inst.cond = cond->value;
16764 case OT_unconditional:
16765 case OT_unconditionalF:
16767 inst.cond = cond->value;
16770 /* Delayed diagnostic. */
16771 inst.error = BAD_COND;
16772 inst.cond = COND_ALWAYS;
16781 /* Cannot have a usual-position infix on a mnemonic of less than
16782 six characters (five would be a suffix). */
16783 if (end - base < 6)
16786 /* Look for infixed mnemonic in the usual position. */
16788 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16792 memcpy (save, affix, 2);
16793 memmove (affix, affix + 2, (end - affix) - 2);
16794 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16796 memmove (affix + 2, affix, (end - affix) - 2);
16797 memcpy (affix, save, 2);
16800 && (opcode->tag == OT_cinfix3
16801 || opcode->tag == OT_cinfix3_deprecated
16802 || opcode->tag == OT_csuf_or_in3
16803 || opcode->tag == OT_cinfix3_legacy))
16806 if (warn_on_deprecated && unified_syntax
16807 && (opcode->tag == OT_cinfix3
16808 || opcode->tag == OT_cinfix3_deprecated))
16809 as_warn (_("conditional infixes are deprecated in unified syntax"));
16811 inst.cond = cond->value;
16818 /* This function generates an initial IT instruction, leaving its block
16819 virtually open for the new instructions. Eventually,
16820 the mask will be updated by now_it_add_mask () each time
16821 a new instruction needs to be included in the IT block.
16822 Finally, the block is closed with close_automatic_it_block ().
16823 The block closure can be requested either from md_assemble (),
16824 a tencode (), or due to a label hook. */
16827 new_automatic_it_block (int cond)
16829 now_it.state = AUTOMATIC_IT_BLOCK;
16830 now_it.mask = 0x18;
16832 now_it.block_length = 1;
16833 mapping_state (MAP_THUMB);
16834 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16835 now_it.warn_deprecated = FALSE;
16836 now_it.insn_cond = TRUE;
16839 /* Close an automatic IT block.
16840 See comments in new_automatic_it_block (). */
16843 close_automatic_it_block (void)
16845 now_it.mask = 0x10;
16846 now_it.block_length = 0;
16849 /* Update the mask of the current automatically-generated IT
16850 instruction. See comments in new_automatic_it_block (). */
16853 now_it_add_mask (int cond)
16855 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16856 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16857 | ((bitvalue) << (nbit)))
16858 const int resulting_bit = (cond & 1);
16860 now_it.mask &= 0xf;
16861 now_it.mask = SET_BIT_VALUE (now_it.mask,
16863 (5 - now_it.block_length));
16864 now_it.mask = SET_BIT_VALUE (now_it.mask,
16866 ((5 - now_it.block_length) - 1) );
16867 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16870 #undef SET_BIT_VALUE
16873 /* The IT blocks handling machinery is accessed through the these functions:
16874 it_fsm_pre_encode () from md_assemble ()
16875 set_it_insn_type () optional, from the tencode functions
16876 set_it_insn_type_last () ditto
16877 in_it_block () ditto
16878 it_fsm_post_encode () from md_assemble ()
16879 force_automatic_it_block_close () from label habdling functions
16882 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16883 initializing the IT insn type with a generic initial value depending
16884 on the inst.condition.
16885 2) During the tencode function, two things may happen:
16886 a) The tencode function overrides the IT insn type by
16887 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16888 b) The tencode function queries the IT block state by
16889 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16891 Both set_it_insn_type and in_it_block run the internal FSM state
16892 handling function (handle_it_state), because: a) setting the IT insn
16893 type may incur in an invalid state (exiting the function),
16894 and b) querying the state requires the FSM to be updated.
16895 Specifically we want to avoid creating an IT block for conditional
16896 branches, so it_fsm_pre_encode is actually a guess and we can't
16897 determine whether an IT block is required until the tencode () routine
16898 has decided what type of instruction this actually it.
16899 Because of this, if set_it_insn_type and in_it_block have to be used,
16900 set_it_insn_type has to be called first.
16902 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16903 determines the insn IT type depending on the inst.cond code.
16904 When a tencode () routine encodes an instruction that can be
16905 either outside an IT block, or, in the case of being inside, has to be
16906 the last one, set_it_insn_type_last () will determine the proper
16907 IT instruction type based on the inst.cond code. Otherwise,
16908 set_it_insn_type can be called for overriding that logic or
16909 for covering other cases.
16911 Calling handle_it_state () may not transition the IT block state to
16912 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16913 still queried. Instead, if the FSM determines that the state should
16914 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16915 after the tencode () function: that's what it_fsm_post_encode () does.
16917 Since in_it_block () calls the state handling function to get an
16918 updated state, an error may occur (due to invalid insns combination).
16919 In that case, inst.error is set.
16920 Therefore, inst.error has to be checked after the execution of
16921 the tencode () routine.
16923 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16924 any pending state change (if any) that didn't take place in
16925 handle_it_state () as explained above. */
16928 it_fsm_pre_encode (void)
16930 if (inst.cond != COND_ALWAYS)
16931 inst.it_insn_type = INSIDE_IT_INSN;
16933 inst.it_insn_type = OUTSIDE_IT_INSN;
16935 now_it.state_handled = 0;
16938 /* IT state FSM handling function. */
16941 handle_it_state (void)
16943 now_it.state_handled = 1;
16944 now_it.insn_cond = FALSE;
16946 switch (now_it.state)
16948 case OUTSIDE_IT_BLOCK:
16949 switch (inst.it_insn_type)
16951 case OUTSIDE_IT_INSN:
16954 case INSIDE_IT_INSN:
16955 case INSIDE_IT_LAST_INSN:
16956 if (thumb_mode == 0)
16959 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16960 as_tsktsk (_("Warning: conditional outside an IT block"\
16965 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16966 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16968 /* Automatically generate the IT instruction. */
16969 new_automatic_it_block (inst.cond);
16970 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16971 close_automatic_it_block ();
16975 inst.error = BAD_OUT_IT;
16981 case IF_INSIDE_IT_LAST_INSN:
16982 case NEUTRAL_IT_INSN:
16986 now_it.state = MANUAL_IT_BLOCK;
16987 now_it.block_length = 0;
16992 case AUTOMATIC_IT_BLOCK:
16993 /* Three things may happen now:
16994 a) We should increment current it block size;
16995 b) We should close current it block (closing insn or 4 insns);
16996 c) We should close current it block and start a new one (due
16997 to incompatible conditions or
16998 4 insns-length block reached). */
17000 switch (inst.it_insn_type)
17002 case OUTSIDE_IT_INSN:
17003 /* The closure of the block shall happen immediatelly,
17004 so any in_it_block () call reports the block as closed. */
17005 force_automatic_it_block_close ();
17008 case INSIDE_IT_INSN:
17009 case INSIDE_IT_LAST_INSN:
17010 case IF_INSIDE_IT_LAST_INSN:
17011 now_it.block_length++;
17013 if (now_it.block_length > 4
17014 || !now_it_compatible (inst.cond))
17016 force_automatic_it_block_close ();
17017 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
17018 new_automatic_it_block (inst.cond);
17022 now_it.insn_cond = TRUE;
17023 now_it_add_mask (inst.cond);
17026 if (now_it.state == AUTOMATIC_IT_BLOCK
17027 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
17028 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
17029 close_automatic_it_block ();
17032 case NEUTRAL_IT_INSN:
17033 now_it.block_length++;
17034 now_it.insn_cond = TRUE;
17036 if (now_it.block_length > 4)
17037 force_automatic_it_block_close ();
17039 now_it_add_mask (now_it.cc & 1);
17043 close_automatic_it_block ();
17044 now_it.state = MANUAL_IT_BLOCK;
17049 case MANUAL_IT_BLOCK:
17051 /* Check conditional suffixes. */
17052 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
17055 now_it.mask &= 0x1f;
17056 is_last = (now_it.mask == 0x10);
17057 now_it.insn_cond = TRUE;
17059 switch (inst.it_insn_type)
17061 case OUTSIDE_IT_INSN:
17062 inst.error = BAD_NOT_IT;
17065 case INSIDE_IT_INSN:
17066 if (cond != inst.cond)
17068 inst.error = BAD_IT_COND;
17073 case INSIDE_IT_LAST_INSN:
17074 case IF_INSIDE_IT_LAST_INSN:
17075 if (cond != inst.cond)
17077 inst.error = BAD_IT_COND;
17082 inst.error = BAD_BRANCH;
17087 case NEUTRAL_IT_INSN:
17088 /* The BKPT instruction is unconditional even in an IT block. */
17092 inst.error = BAD_IT_IT;
17102 struct depr_insn_mask
17104 unsigned long pattern;
17105 unsigned long mask;
17106 const char* description;
17109 /* List of 16-bit instruction patterns deprecated in an IT block in
17111 static const struct depr_insn_mask depr_it_insns[] = {
17112 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17113 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17114 { 0xa000, 0xb800, N_("ADR") },
17115 { 0x4800, 0xf800, N_("Literal loads") },
17116 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17117 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17122 it_fsm_post_encode (void)
17126 if (!now_it.state_handled)
17127 handle_it_state ();
17129 if (now_it.insn_cond
17130 && !now_it.warn_deprecated
17131 && warn_on_deprecated
17132 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17134 if (inst.instruction >= 0x10000)
17136 as_warn (_("it blocks containing wide Thumb instructions are "
17137 "deprecated in ARMv8"));
17138 now_it.warn_deprecated = TRUE;
17142 const struct depr_insn_mask *p = depr_it_insns;
17144 while (p->mask != 0)
17146 if ((inst.instruction & p->mask) == p->pattern)
17148 as_warn (_("it blocks containing 16-bit Thumb intsructions "
17149 "of the following class are deprecated in ARMv8: "
17150 "%s"), p->description);
17151 now_it.warn_deprecated = TRUE;
17159 if (now_it.block_length > 1)
17161 as_warn (_("it blocks of more than one conditional instruction are "
17162 "deprecated in ARMv8"));
17163 now_it.warn_deprecated = TRUE;
17167 is_last = (now_it.mask == 0x10);
17170 now_it.state = OUTSIDE_IT_BLOCK;
17176 force_automatic_it_block_close (void)
17178 if (now_it.state == AUTOMATIC_IT_BLOCK)
17180 close_automatic_it_block ();
17181 now_it.state = OUTSIDE_IT_BLOCK;
17189 if (!now_it.state_handled)
17190 handle_it_state ();
17192 return now_it.state != OUTSIDE_IT_BLOCK;
17196 md_assemble (char *str)
17199 const struct asm_opcode * opcode;
17201 /* Align the previous label if needed. */
17202 if (last_label_seen != NULL)
17204 symbol_set_frag (last_label_seen, frag_now);
17205 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17206 S_SET_SEGMENT (last_label_seen, now_seg);
17209 memset (&inst, '\0', sizeof (inst));
17210 inst.reloc.type = BFD_RELOC_UNUSED;
17212 opcode = opcode_lookup (&p);
17215 /* It wasn't an instruction, but it might be a register alias of
17216 the form alias .req reg, or a Neon .dn/.qn directive. */
17217 if (! create_register_alias (str, p)
17218 && ! create_neon_reg_alias (str, p))
17219 as_bad (_("bad instruction `%s'"), str);
17224 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
17225 as_warn (_("s suffix on comparison instruction is deprecated"));
17227 /* The value which unconditional instructions should have in place of the
17228 condition field. */
17229 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17233 arm_feature_set variant;
17235 variant = cpu_variant;
17236 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17237 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17238 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
17239 /* Check that this instruction is supported for this CPU. */
17240 if (!opcode->tvariant
17241 || (thumb_mode == 1
17242 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
17244 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
17247 if (inst.cond != COND_ALWAYS && !unified_syntax
17248 && opcode->tencode != do_t_branch)
17250 as_bad (_("Thumb does not support conditional execution"));
17254 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
17256 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
17257 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17258 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17260 /* Two things are addressed here.
17261 1) Implicit require narrow instructions on Thumb-1.
17262 This avoids relaxation accidentally introducing Thumb-2
17264 2) Reject wide instructions in non Thumb-2 cores. */
17265 if (inst.size_req == 0)
17267 else if (inst.size_req == 4)
17269 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
17275 inst.instruction = opcode->tvalue;
17277 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
17279 /* Prepare the it_insn_type for those encodings that don't set
17281 it_fsm_pre_encode ();
17283 opcode->tencode ();
17285 it_fsm_post_encode ();
17288 if (!(inst.error || inst.relax))
17290 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
17291 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17292 if (inst.size_req && inst.size_req != inst.size)
17294 as_bad (_("cannot honor width suffix -- `%s'"), str);
17299 /* Something has gone badly wrong if we try to relax a fixed size
17301 gas_assert (inst.size_req == 0 || !inst.relax);
17303 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17304 *opcode->tvariant);
17305 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17306 set those bits when Thumb-2 32-bit instructions are seen. ie.
17307 anything other than bl/blx and v6-M instructions.
17308 This is overly pessimistic for relaxable instructions. */
17309 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
17311 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17312 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
17313 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17316 check_neon_suffixes;
17320 mapping_state (MAP_THUMB);
17323 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
17327 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17328 is_bx = (opcode->aencode == do_bx);
17330 /* Check that this instruction is supported for this CPU. */
17331 if (!(is_bx && fix_v4bx)
17332 && !(opcode->avariant &&
17333 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
17335 as_bad (_("selected processor does not support ARM mode `%s'"), str);
17340 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17344 inst.instruction = opcode->avalue;
17345 if (opcode->tag == OT_unconditionalF)
17346 inst.instruction |= 0xF << 28;
17348 inst.instruction |= inst.cond << 28;
17349 inst.size = INSN_SIZE;
17350 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
17352 it_fsm_pre_encode ();
17353 opcode->aencode ();
17354 it_fsm_post_encode ();
17356 /* Arm mode bx is marked as both v4T and v5 because it's still required
17357 on a hypothetical non-thumb v5 core. */
17359 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
17361 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17362 *opcode->avariant);
17364 check_neon_suffixes;
17368 mapping_state (MAP_ARM);
17373 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17381 check_it_blocks_finished (void)
17386 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17387 if (seg_info (sect)->tc_segment_info_data.current_it.state
17388 == MANUAL_IT_BLOCK)
17390 as_warn (_("section '%s' finished with an open IT block."),
17394 if (now_it.state == MANUAL_IT_BLOCK)
17395 as_warn (_("file finished with an open IT block."));
17399 /* Various frobbings of labels and their addresses. */
17402 arm_start_line_hook (void)
17404 last_label_seen = NULL;
17408 arm_frob_label (symbolS * sym)
17410 last_label_seen = sym;
17412 ARM_SET_THUMB (sym, thumb_mode);
17414 #if defined OBJ_COFF || defined OBJ_ELF
17415 ARM_SET_INTERWORK (sym, support_interwork);
17418 force_automatic_it_block_close ();
17420 /* Note - do not allow local symbols (.Lxxx) to be labelled
17421 as Thumb functions. This is because these labels, whilst
17422 they exist inside Thumb code, are not the entry points for
17423 possible ARM->Thumb calls. Also, these labels can be used
17424 as part of a computed goto or switch statement. eg gcc
17425 can generate code that looks like this:
17427 ldr r2, [pc, .Laaa]
17437 The first instruction loads the address of the jump table.
17438 The second instruction converts a table index into a byte offset.
17439 The third instruction gets the jump address out of the table.
17440 The fourth instruction performs the jump.
17442 If the address stored at .Laaa is that of a symbol which has the
17443 Thumb_Func bit set, then the linker will arrange for this address
17444 to have the bottom bit set, which in turn would mean that the
17445 address computation performed by the third instruction would end
17446 up with the bottom bit set. Since the ARM is capable of unaligned
17447 word loads, the instruction would then load the incorrect address
17448 out of the jump table, and chaos would ensue. */
17449 if (label_is_thumb_function_name
17450 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17451 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
17453 /* When the address of a Thumb function is taken the bottom
17454 bit of that address should be set. This will allow
17455 interworking between Arm and Thumb functions to work
17458 THUMB_SET_FUNC (sym, 1);
17460 label_is_thumb_function_name = FALSE;
17463 dwarf2_emit_label (sym);
17467 arm_data_in_code (void)
17469 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
17471 *input_line_pointer = '/';
17472 input_line_pointer += 5;
17473 *input_line_pointer = 0;
17481 arm_canonicalize_symbol_name (char * name)
17485 if (thumb_mode && (len = strlen (name)) > 5
17486 && streq (name + len - 5, "/data"))
17487 *(name + len - 5) = 0;
17492 /* Table of all register names defined by default. The user can
17493 define additional names with .req. Note that all register names
17494 should appear in both upper and lowercase variants. Some registers
17495 also have mixed-case names. */
17497 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17498 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17499 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17500 #define REGSET(p,t) \
17501 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17502 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17503 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17504 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17505 #define REGSETH(p,t) \
17506 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17507 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17508 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17509 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17510 #define REGSET2(p,t) \
17511 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17512 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17513 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17514 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17515 #define SPLRBANK(base,bank,t) \
17516 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17517 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17518 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17519 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17520 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17521 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17523 static const struct reg_entry reg_names[] =
17525 /* ARM integer registers. */
17526 REGSET(r, RN), REGSET(R, RN),
17528 /* ATPCS synonyms. */
17529 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17530 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17531 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
17533 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17534 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17535 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
17537 /* Well-known aliases. */
17538 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17539 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17541 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17542 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17544 /* Coprocessor numbers. */
17545 REGSET(p, CP), REGSET(P, CP),
17547 /* Coprocessor register numbers. The "cr" variants are for backward
17549 REGSET(c, CN), REGSET(C, CN),
17550 REGSET(cr, CN), REGSET(CR, CN),
17552 /* ARM banked registers. */
17553 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17554 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17555 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17556 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17557 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17558 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17559 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17561 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17562 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17563 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17564 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17565 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
17566 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
17567 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17568 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17570 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17571 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17572 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17573 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17574 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17575 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17576 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
17577 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
17578 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17580 /* FPA registers. */
17581 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17582 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17584 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17585 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17587 /* VFP SP registers. */
17588 REGSET(s,VFS), REGSET(S,VFS),
17589 REGSETH(s,VFS), REGSETH(S,VFS),
17591 /* VFP DP Registers. */
17592 REGSET(d,VFD), REGSET(D,VFD),
17593 /* Extra Neon DP registers. */
17594 REGSETH(d,VFD), REGSETH(D,VFD),
17596 /* Neon QP registers. */
17597 REGSET2(q,NQ), REGSET2(Q,NQ),
17599 /* VFP control registers. */
17600 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17601 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
17602 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17603 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17604 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17605 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
17607 /* Maverick DSP coprocessor registers. */
17608 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17609 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17611 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17612 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17613 REGDEF(dspsc,0,DSPSC),
17615 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17616 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17617 REGDEF(DSPSC,0,DSPSC),
17619 /* iWMMXt data registers - p0, c0-15. */
17620 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17622 /* iWMMXt control registers - p1, c0-3. */
17623 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17624 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17625 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17626 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17628 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17629 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17630 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17631 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17632 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17634 /* XScale accumulator registers. */
17635 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17641 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17642 within psr_required_here. */
17643 static const struct asm_psr psrs[] =
17645 /* Backward compatibility notation. Note that "all" is no longer
17646 truly all possible PSR bits. */
17647 {"all", PSR_c | PSR_f},
17651 /* Individual flags. */
17657 /* Combinations of flags. */
17658 {"fs", PSR_f | PSR_s},
17659 {"fx", PSR_f | PSR_x},
17660 {"fc", PSR_f | PSR_c},
17661 {"sf", PSR_s | PSR_f},
17662 {"sx", PSR_s | PSR_x},
17663 {"sc", PSR_s | PSR_c},
17664 {"xf", PSR_x | PSR_f},
17665 {"xs", PSR_x | PSR_s},
17666 {"xc", PSR_x | PSR_c},
17667 {"cf", PSR_c | PSR_f},
17668 {"cs", PSR_c | PSR_s},
17669 {"cx", PSR_c | PSR_x},
17670 {"fsx", PSR_f | PSR_s | PSR_x},
17671 {"fsc", PSR_f | PSR_s | PSR_c},
17672 {"fxs", PSR_f | PSR_x | PSR_s},
17673 {"fxc", PSR_f | PSR_x | PSR_c},
17674 {"fcs", PSR_f | PSR_c | PSR_s},
17675 {"fcx", PSR_f | PSR_c | PSR_x},
17676 {"sfx", PSR_s | PSR_f | PSR_x},
17677 {"sfc", PSR_s | PSR_f | PSR_c},
17678 {"sxf", PSR_s | PSR_x | PSR_f},
17679 {"sxc", PSR_s | PSR_x | PSR_c},
17680 {"scf", PSR_s | PSR_c | PSR_f},
17681 {"scx", PSR_s | PSR_c | PSR_x},
17682 {"xfs", PSR_x | PSR_f | PSR_s},
17683 {"xfc", PSR_x | PSR_f | PSR_c},
17684 {"xsf", PSR_x | PSR_s | PSR_f},
17685 {"xsc", PSR_x | PSR_s | PSR_c},
17686 {"xcf", PSR_x | PSR_c | PSR_f},
17687 {"xcs", PSR_x | PSR_c | PSR_s},
17688 {"cfs", PSR_c | PSR_f | PSR_s},
17689 {"cfx", PSR_c | PSR_f | PSR_x},
17690 {"csf", PSR_c | PSR_s | PSR_f},
17691 {"csx", PSR_c | PSR_s | PSR_x},
17692 {"cxf", PSR_c | PSR_x | PSR_f},
17693 {"cxs", PSR_c | PSR_x | PSR_s},
17694 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17695 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17696 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17697 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17698 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17699 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17700 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17701 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17702 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17703 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17704 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17705 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17706 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17707 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17708 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17709 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17710 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17711 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17712 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17713 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17714 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17715 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17716 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17717 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17720 /* Table of V7M psr names. */
17721 static const struct asm_psr v7m_psrs[] =
17723 {"apsr", 0 }, {"APSR", 0 },
17724 {"iapsr", 1 }, {"IAPSR", 1 },
17725 {"eapsr", 2 }, {"EAPSR", 2 },
17726 {"psr", 3 }, {"PSR", 3 },
17727 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17728 {"ipsr", 5 }, {"IPSR", 5 },
17729 {"epsr", 6 }, {"EPSR", 6 },
17730 {"iepsr", 7 }, {"IEPSR", 7 },
17731 {"msp", 8 }, {"MSP", 8 },
17732 {"psp", 9 }, {"PSP", 9 },
17733 {"primask", 16}, {"PRIMASK", 16},
17734 {"basepri", 17}, {"BASEPRI", 17},
17735 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17736 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17737 {"faultmask", 19}, {"FAULTMASK", 19},
17738 {"control", 20}, {"CONTROL", 20}
17741 /* Table of all shift-in-operand names. */
17742 static const struct asm_shift_name shift_names [] =
17744 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17745 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17746 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17747 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17748 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17749 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17752 /* Table of all explicit relocation names. */
17754 static struct reloc_entry reloc_names[] =
17756 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17757 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17758 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17759 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17760 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17761 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17762 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17763 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17764 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17765 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17766 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17767 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17768 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17769 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17770 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17771 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17772 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17773 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17777 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17778 static const struct asm_cond conds[] =
17782 {"cs", 0x2}, {"hs", 0x2},
17783 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17797 #define UL_BARRIER(L,U,CODE,FEAT) \
17798 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17799 { U, CODE, ARM_FEATURE (FEAT, 0) }
17801 static struct asm_barrier_opt barrier_opt_names[] =
17803 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17804 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17805 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17806 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17807 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17808 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17809 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17810 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17811 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17812 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17813 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17814 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17815 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17816 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17817 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17818 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
17823 /* Table of ARM-format instructions. */
17825 /* Macros for gluing together operand strings. N.B. In all cases
17826 other than OPS0, the trailing OP_stop comes from default
17827 zero-initialization of the unspecified elements of the array. */
17828 #define OPS0() { OP_stop, }
17829 #define OPS1(a) { OP_##a, }
17830 #define OPS2(a,b) { OP_##a,OP_##b, }
17831 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17832 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17833 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17834 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17836 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17837 This is useful when mixing operands for ARM and THUMB, i.e. using the
17838 MIX_ARM_THUMB_OPERANDS macro.
17839 In order to use these macros, prefix the number of operands with _
17841 #define OPS_1(a) { a, }
17842 #define OPS_2(a,b) { a,b, }
17843 #define OPS_3(a,b,c) { a,b,c, }
17844 #define OPS_4(a,b,c,d) { a,b,c,d, }
17845 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17846 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17848 /* These macros abstract out the exact format of the mnemonic table and
17849 save some repeated characters. */
17851 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17852 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17853 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17854 THUMB_VARIANT, do_##ae, do_##te }
17856 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17857 a T_MNEM_xyz enumerator. */
17858 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17859 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17860 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17861 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17863 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17864 infix after the third character. */
17865 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17866 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17867 THUMB_VARIANT, do_##ae, do_##te }
17868 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17869 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17870 THUMB_VARIANT, do_##ae, do_##te }
17871 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17872 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17873 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17874 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17875 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17876 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17877 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17878 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17880 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17881 field is still 0xE. Many of the Thumb variants can be executed
17882 conditionally, so this is checked separately. */
17883 #define TUE(mnem, op, top, nops, ops, ae, te) \
17884 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17885 THUMB_VARIANT, do_##ae, do_##te }
17887 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
17888 Used by mnemonics that have very minimal differences in the encoding for
17889 ARM and Thumb variants and can be handled in a common function. */
17890 #define TUEc(mnem, op, top, nops, ops, en) \
17891 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17892 THUMB_VARIANT, do_##en, do_##en }
17894 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17895 condition code field. */
17896 #define TUF(mnem, op, top, nops, ops, ae, te) \
17897 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17898 THUMB_VARIANT, do_##ae, do_##te }
17900 /* ARM-only variants of all the above. */
17901 #define CE(mnem, op, nops, ops, ae) \
17902 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17904 #define C3(mnem, op, nops, ops, ae) \
17905 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17907 /* Legacy mnemonics that always have conditional infix after the third
17909 #define CL(mnem, op, nops, ops, ae) \
17910 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17911 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17913 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17914 #define cCE(mnem, op, nops, ops, ae) \
17915 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17917 /* Legacy coprocessor instructions where conditional infix and conditional
17918 suffix are ambiguous. For consistency this includes all FPA instructions,
17919 not just the potentially ambiguous ones. */
17920 #define cCL(mnem, op, nops, ops, ae) \
17921 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17922 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17924 /* Coprocessor, takes either a suffix or a position-3 infix
17925 (for an FPA corner case). */
17926 #define C3E(mnem, op, nops, ops, ae) \
17927 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17928 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17930 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17931 { m1 #m2 m3, OPS##nops ops, \
17932 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17933 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17935 #define CM(m1, m2, op, nops, ops, ae) \
17936 xCM_ (m1, , m2, op, nops, ops, ae), \
17937 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17938 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17939 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17940 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17941 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17942 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17943 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17944 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17945 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17946 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17947 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17948 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17949 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17950 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17951 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17952 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17953 xCM_ (m1, le, m2, op, nops, ops, ae), \
17954 xCM_ (m1, al, m2, op, nops, ops, ae)
17956 #define UE(mnem, op, nops, ops, ae) \
17957 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17959 #define UF(mnem, op, nops, ops, ae) \
17960 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17962 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17963 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17964 use the same encoding function for each. */
17965 #define NUF(mnem, op, nops, ops, enc) \
17966 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17967 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17969 /* Neon data processing, version which indirects through neon_enc_tab for
17970 the various overloaded versions of opcodes. */
17971 #define nUF(mnem, op, nops, ops, enc) \
17972 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17973 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17975 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17977 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17978 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17979 THUMB_VARIANT, do_##enc, do_##enc }
17981 #define NCE(mnem, op, nops, ops, enc) \
17982 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17984 #define NCEF(mnem, op, nops, ops, enc) \
17985 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17987 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17988 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17989 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17990 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17992 #define nCE(mnem, op, nops, ops, enc) \
17993 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17995 #define nCEF(mnem, op, nops, ops, enc) \
17996 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18000 static const struct asm_opcode insns[] =
18002 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
18003 #define THUMB_VARIANT &arm_ext_v4t
18004 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
18005 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
18006 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
18007 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
18008 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
18009 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
18010 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
18011 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
18012 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
18013 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
18014 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
18015 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
18016 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
18017 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
18018 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
18019 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
18021 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18022 for setting PSR flag bits. They are obsolete in V6 and do not
18023 have Thumb equivalents. */
18024 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18025 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18026 CL("tstp", 110f000, 2, (RR, SH), cmp),
18027 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18028 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18029 CL("cmpp", 150f000, 2, (RR, SH), cmp),
18030 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18031 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18032 CL("cmnp", 170f000, 2, (RR, SH), cmp),
18034 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
18035 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
18036 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
18037 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
18039 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
18040 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18041 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
18043 OP_ADDRGLDR),ldst, t_ldst),
18044 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18046 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18047 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18048 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18049 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18050 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18051 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18053 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
18054 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
18055 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
18056 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
18059 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
18060 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
18061 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
18063 /* Thumb-compatibility pseudo ops. */
18064 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
18065 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
18066 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
18067 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
18068 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
18069 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
18070 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
18071 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
18072 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
18073 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
18074 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
18075 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
18077 /* These may simplify to neg. */
18078 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
18079 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
18081 #undef THUMB_VARIANT
18082 #define THUMB_VARIANT & arm_ext_v6
18084 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
18086 /* V1 instructions with no Thumb analogue prior to V6T2. */
18087 #undef THUMB_VARIANT
18088 #define THUMB_VARIANT & arm_ext_v6t2
18090 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18091 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18092 CL("teqp", 130f000, 2, (RR, SH), cmp),
18094 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18095 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18096 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18097 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18099 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18100 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18102 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18103 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18105 /* V1 instructions with no Thumb analogue at all. */
18106 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
18107 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18109 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18110 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18111 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18112 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18113 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18114 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18115 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18116 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18119 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18120 #undef THUMB_VARIANT
18121 #define THUMB_VARIANT & arm_ext_v4t
18123 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18124 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18126 #undef THUMB_VARIANT
18127 #define THUMB_VARIANT & arm_ext_v6t2
18129 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18130 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18132 /* Generic coprocessor instructions. */
18133 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18134 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18135 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18136 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18137 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18138 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18139 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
18142 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18144 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18145 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18148 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18149 #undef THUMB_VARIANT
18150 #define THUMB_VARIANT & arm_ext_msr
18152 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18153 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
18156 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18157 #undef THUMB_VARIANT
18158 #define THUMB_VARIANT & arm_ext_v6t2
18160 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18161 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18162 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18163 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18164 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18165 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18166 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18167 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18170 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18171 #undef THUMB_VARIANT
18172 #define THUMB_VARIANT & arm_ext_v4t
18174 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18175 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18176 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18177 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18178 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18179 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18182 #define ARM_VARIANT & arm_ext_v4t_5
18184 /* ARM Architecture 4T. */
18185 /* Note: bx (and blx) are required on V5, even if the processor does
18186 not support Thumb. */
18187 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
18190 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18191 #undef THUMB_VARIANT
18192 #define THUMB_VARIANT & arm_ext_v5t
18194 /* Note: blx has 2 variants; the .value coded here is for
18195 BLX(2). Only this variant has conditional execution. */
18196 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18197 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
18199 #undef THUMB_VARIANT
18200 #define THUMB_VARIANT & arm_ext_v6t2
18202 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18203 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18204 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18205 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18206 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18207 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18208 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18209 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18212 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18213 #undef THUMB_VARIANT
18214 #define THUMB_VARIANT &arm_ext_v5exp
18216 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18217 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18218 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18219 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18221 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18222 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18224 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18225 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18226 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18227 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18229 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18230 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18231 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18232 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18234 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18235 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18237 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18238 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18239 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18240 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18243 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18244 #undef THUMB_VARIANT
18245 #define THUMB_VARIANT &arm_ext_v6t2
18247 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
18248 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18250 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18251 ADDRGLDRS), ldrd, t_ldstd),
18253 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18254 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18257 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18259 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
18262 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18263 #undef THUMB_VARIANT
18264 #define THUMB_VARIANT & arm_ext_v6
18266 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18267 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18268 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18269 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18270 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18271 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18272 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18273 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18274 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18275 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
18277 #undef THUMB_VARIANT
18278 #define THUMB_VARIANT & arm_ext_v6t2
18280 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18281 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18283 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18284 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18286 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18287 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
18289 /* ARM V6 not included in V7M. */
18290 #undef THUMB_VARIANT
18291 #define THUMB_VARIANT & arm_ext_v6_notm
18292 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18293 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18294 UF(rfeib, 9900a00, 1, (RRw), rfe),
18295 UF(rfeda, 8100a00, 1, (RRw), rfe),
18296 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18297 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18298 UF(rfefa, 8100a00, 1, (RRw), rfe),
18299 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18300 UF(rfeed, 9900a00, 1, (RRw), rfe),
18301 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18302 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18303 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18304 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
18305 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
18306 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
18307 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
18308 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18309 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18311 /* ARM V6 not included in V7M (eg. integer SIMD). */
18312 #undef THUMB_VARIANT
18313 #define THUMB_VARIANT & arm_ext_v6_dsp
18314 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18315 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18316 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18317 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18318 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18319 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18320 /* Old name for QASX. */
18321 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18322 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18323 /* Old name for QSAX. */
18324 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18325 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18326 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18327 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18328 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18329 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18330 /* Old name for SASX. */
18331 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18332 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18333 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18334 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18335 /* Old name for SHASX. */
18336 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18337 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18338 /* Old name for SHSAX. */
18339 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18340 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18341 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18342 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18343 /* Old name for SSAX. */
18344 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18345 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18346 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18347 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18348 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18349 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18350 /* Old name for UASX. */
18351 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18352 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18353 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18354 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18355 /* Old name for UHASX. */
18356 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18357 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18358 /* Old name for UHSAX. */
18359 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18360 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18361 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18362 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18363 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18364 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18365 /* Old name for UQASX. */
18366 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18367 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18368 /* Old name for UQSAX. */
18369 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18370 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18371 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18372 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18373 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18374 /* Old name for USAX. */
18375 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18376 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18377 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18378 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18379 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18380 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18381 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18382 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18383 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18384 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18385 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18386 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18387 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18388 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18389 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18390 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18391 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18392 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18393 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18394 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18395 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18396 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18397 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18398 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18399 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18400 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18401 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18402 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18403 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18404 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18405 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18406 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18407 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18408 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
18411 #define ARM_VARIANT & arm_ext_v6k
18412 #undef THUMB_VARIANT
18413 #define THUMB_VARIANT & arm_ext_v6k
18415 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18416 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18417 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18418 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
18420 #undef THUMB_VARIANT
18421 #define THUMB_VARIANT & arm_ext_v6_notm
18422 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18424 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18425 RRnpcb), strexd, t_strexd),
18427 #undef THUMB_VARIANT
18428 #define THUMB_VARIANT & arm_ext_v6t2
18429 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18431 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18433 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18435 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18437 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
18440 #define ARM_VARIANT & arm_ext_sec
18441 #undef THUMB_VARIANT
18442 #define THUMB_VARIANT & arm_ext_sec
18444 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
18447 #define ARM_VARIANT & arm_ext_virt
18448 #undef THUMB_VARIANT
18449 #define THUMB_VARIANT & arm_ext_virt
18451 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18452 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18455 #define ARM_VARIANT & arm_ext_v6t2
18456 #undef THUMB_VARIANT
18457 #define THUMB_VARIANT & arm_ext_v6t2
18459 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18460 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18461 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18462 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18464 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18465 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18466 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18467 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
18469 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18470 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18471 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18472 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18474 /* Thumb-only instructions. */
18476 #define ARM_VARIANT NULL
18477 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18478 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
18480 /* ARM does not really have an IT instruction, so always allow it.
18481 The opcode is copied from Thumb in order to allow warnings in
18482 -mimplicit-it=[never | arm] modes. */
18484 #define ARM_VARIANT & arm_ext_v1
18486 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18487 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18488 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18489 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18490 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18491 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18492 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18493 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18494 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18495 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18496 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18497 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18498 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18499 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18500 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
18501 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18502 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18503 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
18505 /* Thumb2 only instructions. */
18507 #define ARM_VARIANT NULL
18509 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18510 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18511 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18512 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18513 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18514 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
18516 /* Hardware division instructions. */
18518 #define ARM_VARIANT & arm_ext_adiv
18519 #undef THUMB_VARIANT
18520 #define THUMB_VARIANT & arm_ext_div
18522 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18523 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
18525 /* ARM V6M/V7 instructions. */
18527 #define ARM_VARIANT & arm_ext_barrier
18528 #undef THUMB_VARIANT
18529 #define THUMB_VARIANT & arm_ext_barrier
18531 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
18532 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
18533 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
18535 /* ARM V7 instructions. */
18537 #define ARM_VARIANT & arm_ext_v7
18538 #undef THUMB_VARIANT
18539 #define THUMB_VARIANT & arm_ext_v7
18541 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18542 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
18545 #define ARM_VARIANT & arm_ext_mp
18546 #undef THUMB_VARIANT
18547 #define THUMB_VARIANT & arm_ext_mp
18549 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18551 /* AArchv8 instructions. */
18553 #define ARM_VARIANT & arm_ext_v8
18554 #undef THUMB_VARIANT
18555 #define THUMB_VARIANT & arm_ext_v8
18557 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
18558 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
18559 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18560 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
18562 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18563 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18564 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18566 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
18568 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18570 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18572 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18573 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18574 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18575 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18576 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18577 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18579 /* ARMv8 T32 only. */
18581 #define ARM_VARIANT NULL
18582 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18583 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18584 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18586 /* FP for ARMv8. */
18588 #define ARM_VARIANT & fpu_vfp_ext_armv8
18589 #undef THUMB_VARIANT
18590 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18592 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18593 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18594 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18595 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
18596 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18597 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18598 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
18599 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
18600 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
18601 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
18602 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
18603 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
18604 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
18605 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
18606 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
18607 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
18608 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
18610 /* Crypto v1 extensions. */
18612 #define ARM_VARIANT & fpu_crypto_ext_armv8
18613 #undef THUMB_VARIANT
18614 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18616 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
18617 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
18618 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
18619 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
18620 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
18621 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
18622 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
18623 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
18624 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
18625 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
18626 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
18627 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
18628 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
18629 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
18632 #define ARM_VARIANT & crc_ext_armv8
18633 #undef THUMB_VARIANT
18634 #define THUMB_VARIANT & crc_ext_armv8
18635 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
18636 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
18637 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
18638 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
18639 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
18640 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
18643 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18644 #undef THUMB_VARIANT
18645 #define THUMB_VARIANT NULL
18647 cCE("wfs", e200110, 1, (RR), rd),
18648 cCE("rfs", e300110, 1, (RR), rd),
18649 cCE("wfc", e400110, 1, (RR), rd),
18650 cCE("rfc", e500110, 1, (RR), rd),
18652 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18653 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18654 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18655 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18657 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18658 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18659 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18660 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18662 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18663 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18664 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18665 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18666 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18667 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18668 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18669 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18670 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18671 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18672 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18673 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18675 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18676 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18677 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18678 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18679 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18680 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18681 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18682 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18683 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18684 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18685 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18686 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18688 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18689 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18690 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18691 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18692 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18693 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18694 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18695 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18696 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18697 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18698 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18699 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18701 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18702 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18703 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18704 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18705 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18706 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18707 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18708 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18709 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18710 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18711 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18712 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18714 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18715 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18716 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18717 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18718 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18719 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18720 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18721 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18722 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18723 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18724 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18725 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18727 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18728 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18729 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18730 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18731 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18732 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18733 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18734 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18735 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18736 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18737 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18738 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18740 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18741 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18742 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18743 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18744 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18745 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18746 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18747 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18748 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18749 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18750 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18751 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18753 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18754 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18755 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18756 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18757 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18758 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18759 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18760 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18761 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18762 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18763 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18764 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18766 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18767 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18768 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18769 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18770 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18771 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18772 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18773 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18774 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18775 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18776 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18777 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18779 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18780 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18781 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18782 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18783 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18784 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18785 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18786 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18787 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18788 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18789 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18790 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18792 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18793 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18794 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18795 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18796 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18797 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18798 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18799 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18800 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18801 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18802 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18803 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18805 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18806 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18807 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18808 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18809 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18810 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18811 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18812 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18813 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18814 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18815 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18816 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18818 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18819 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18820 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18821 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18822 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18823 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18824 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18825 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18826 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18827 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18828 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18829 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18831 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18832 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18833 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18834 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18835 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18836 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18837 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18838 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18839 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18840 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18841 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18842 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18844 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18845 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18846 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18847 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18848 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18849 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18850 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18851 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18852 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18853 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18854 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18855 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18857 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18858 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18859 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18860 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18861 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18862 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18863 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18864 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18865 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18866 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18867 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18868 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18870 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18871 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18872 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18873 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18874 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18875 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18876 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18877 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18878 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18879 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18880 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18881 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18883 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18884 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18885 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18886 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18887 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18888 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18889 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18890 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18891 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18892 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18893 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18894 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18896 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18897 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18898 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18899 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18900 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18901 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18902 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18903 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18904 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18905 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18906 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18907 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18909 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18910 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18911 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18912 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18913 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18914 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18915 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18916 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18917 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18918 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18919 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18920 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18922 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18923 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18924 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18925 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18926 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18927 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18928 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18929 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18930 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18931 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18932 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18933 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18935 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18936 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18937 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18938 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18939 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18940 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18941 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18942 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18943 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18944 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18945 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18946 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18948 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18949 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18950 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18951 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18952 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18953 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18954 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18955 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18956 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18957 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18958 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18959 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18961 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18962 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18963 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18964 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18965 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18966 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18967 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18968 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18969 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18970 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18971 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18972 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18974 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18975 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18976 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18977 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18978 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18979 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18980 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18981 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18982 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18983 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18984 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18985 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18987 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18988 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18989 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18990 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18991 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18992 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18993 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18994 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18995 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18996 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18997 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18998 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
19000 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19001 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19002 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19003 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19004 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19005 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19006 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19007 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19008 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19009 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19010 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19011 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19013 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19014 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19015 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19016 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19017 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19018 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19019 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19020 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19021 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19022 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19023 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19024 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19026 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19027 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19028 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19029 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19030 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19031 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19032 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19033 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19034 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19035 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19036 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19037 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19039 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
19040 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
19041 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
19042 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
19044 cCL("flts", e000110, 2, (RF, RR), rn_rd),
19045 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
19046 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
19047 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
19048 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
19049 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
19050 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
19051 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
19052 cCL("flte", e080110, 2, (RF, RR), rn_rd),
19053 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
19054 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
19055 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
19057 /* The implementation of the FIX instruction is broken on some
19058 assemblers, in that it accepts a precision specifier as well as a
19059 rounding specifier, despite the fact that this is meaningless.
19060 To be more compatible, we accept it as well, though of course it
19061 does not set any bits. */
19062 cCE("fix", e100110, 2, (RR, RF), rd_rm),
19063 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
19064 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
19065 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
19066 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
19067 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
19068 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
19069 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
19070 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
19071 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
19072 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
19073 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
19074 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
19076 /* Instructions that were new with the real FPA, call them V2. */
19078 #define ARM_VARIANT & fpu_fpa_ext_v2
19080 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19081 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19082 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19083 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19084 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19085 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19088 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19090 /* Moves and type conversions. */
19091 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
19092 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
19093 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
19094 cCE("fmstat", ef1fa10, 0, (), noargs),
19095 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
19096 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
19097 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
19098 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
19099 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
19100 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19101 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
19102 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19103 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
19104 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
19106 /* Memory operations. */
19107 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19108 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19109 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19110 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19111 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19112 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19113 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19114 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19115 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19116 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19117 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19118 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19119 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19120 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19121 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19122 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19123 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19124 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19126 /* Monadic operations. */
19127 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19128 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19129 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
19131 /* Dyadic operations. */
19132 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19133 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19134 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19135 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19136 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19137 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19138 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19139 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19140 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19143 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19144 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19145 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19146 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
19148 /* Double precision load/store are still present on single precision
19149 implementations. */
19150 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19151 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19152 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19153 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19154 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19155 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19156 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19157 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19158 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19159 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19162 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19164 /* Moves and type conversions. */
19165 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19166 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19167 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19168 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19169 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19170 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19171 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19172 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19173 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19174 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19175 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19176 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19177 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19179 /* Monadic operations. */
19180 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19181 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19182 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19184 /* Dyadic operations. */
19185 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19186 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19187 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19188 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19189 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19190 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19191 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19192 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19193 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19196 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19197 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19198 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19199 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
19202 #define ARM_VARIANT & fpu_vfp_ext_v2
19204 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19205 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19206 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19207 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
19209 /* Instructions which may belong to either the Neon or VFP instruction sets.
19210 Individual encoder functions perform additional architecture checks. */
19212 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19213 #undef THUMB_VARIANT
19214 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19216 /* These mnemonics are unique to VFP. */
19217 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19218 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
19219 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19220 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19221 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19222 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19223 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19224 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19225 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19226 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19228 /* Mnemonics shared by Neon and VFP. */
19229 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19230 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19231 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19233 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19234 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19236 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19237 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19239 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19240 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19241 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19242 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19243 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19244 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19245 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19246 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19248 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
19249 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
19250 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19251 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
19254 /* NOTE: All VMOV encoding is special-cased! */
19255 NCE(vmov, 0, 1, (VMOV), neon_mov),
19256 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19258 #undef THUMB_VARIANT
19259 #define THUMB_VARIANT & fpu_neon_ext_v1
19261 #define ARM_VARIANT & fpu_neon_ext_v1
19263 /* Data processing with three registers of the same length. */
19264 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19265 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19266 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19267 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19268 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19269 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19270 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19271 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19272 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19273 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19274 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19275 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19276 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19277 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19278 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19279 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19280 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19281 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19282 /* If not immediate, fall back to neon_dyadic_i64_su.
19283 shl_imm should accept I8 I16 I32 I64,
19284 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19285 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19286 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19287 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19288 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
19289 /* Logic ops, types optional & ignored. */
19290 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19291 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19292 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19293 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19294 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19295 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19296 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19297 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19298 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19299 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
19300 /* Bitfield ops, untyped. */
19301 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19302 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19303 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19304 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19305 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19306 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19307 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19308 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19309 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19310 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19311 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19312 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19313 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19314 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19315 back to neon_dyadic_if_su. */
19316 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19317 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19318 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19319 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19320 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19321 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19322 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19323 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19324 /* Comparison. Type I8 I16 I32 F32. */
19325 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19326 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
19327 /* As above, D registers only. */
19328 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19329 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19330 /* Int and float variants, signedness unimportant. */
19331 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19332 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19333 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
19334 /* Add/sub take types I8 I16 I32 I64 F32. */
19335 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19336 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19337 /* vtst takes sizes 8, 16, 32. */
19338 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19339 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19340 /* VMUL takes I8 I16 I32 F32 P8. */
19341 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
19342 /* VQD{R}MULH takes S16 S32. */
19343 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19344 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19345 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19346 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19347 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19348 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19349 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19350 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19351 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19352 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19353 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19354 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19355 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19356 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19357 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19358 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19360 /* Two address, int/float. Types S8 S16 S32 F32. */
19361 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
19362 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19364 /* Data processing with two registers and a shift amount. */
19365 /* Right shifts, and variants with rounding.
19366 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19367 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19368 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19369 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19370 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19371 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19372 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19373 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19374 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19375 /* Shift and insert. Sizes accepted 8 16 32 64. */
19376 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19377 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19378 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19379 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19380 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19381 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19382 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19383 /* Right shift immediate, saturating & narrowing, with rounding variants.
19384 Types accepted S16 S32 S64 U16 U32 U64. */
19385 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19386 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19387 /* As above, unsigned. Types accepted S16 S32 S64. */
19388 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19389 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19390 /* Right shift narrowing. Types accepted I16 I32 I64. */
19391 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19392 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19393 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19394 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
19395 /* CVT with optional immediate for fixed-point variant. */
19396 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
19398 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19399 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
19401 /* Data processing, three registers of different lengths. */
19402 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19403 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19404 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19405 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19406 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19407 /* If not scalar, fall back to neon_dyadic_long.
19408 Vector types as above, scalar types S16 S32 U16 U32. */
19409 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19410 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19411 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19412 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19413 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19414 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19415 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19416 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19417 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19418 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19419 /* Saturating doubling multiplies. Types S16 S32. */
19420 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19421 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19422 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19423 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19424 S16 S32 U16 U32. */
19425 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
19427 /* Extract. Size 8. */
19428 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19429 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
19431 /* Two registers, miscellaneous. */
19432 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19433 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19434 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19435 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19436 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19437 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19438 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19439 /* Vector replicate. Sizes 8 16 32. */
19440 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19441 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
19442 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19443 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19444 /* VMOVN. Types I16 I32 I64. */
19445 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
19446 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19447 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
19448 /* VQMOVUN. Types S16 S32 S64. */
19449 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
19450 /* VZIP / VUZP. Sizes 8 16 32. */
19451 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19452 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19453 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19454 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19455 /* VQABS / VQNEG. Types S8 S16 S32. */
19456 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19457 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19458 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19459 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19460 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19461 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19462 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19463 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19464 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19465 /* Reciprocal estimates. Types U32 F32. */
19466 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19467 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19468 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19469 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19470 /* VCLS. Types S8 S16 S32. */
19471 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19472 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19473 /* VCLZ. Types I8 I16 I32. */
19474 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19475 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19476 /* VCNT. Size 8. */
19477 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19478 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19479 /* Two address, untyped. */
19480 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19481 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19482 /* VTRN. Sizes 8 16 32. */
19483 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19484 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
19486 /* Table lookup. Size 8. */
19487 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19488 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19490 #undef THUMB_VARIANT
19491 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19493 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19495 /* Neon element/structure load/store. */
19496 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19497 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19498 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19499 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19500 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19501 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19502 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19503 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19505 #undef THUMB_VARIANT
19506 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
19508 #define ARM_VARIANT &fpu_vfp_ext_v3xd
19509 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19510 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19511 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19512 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19513 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19514 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19515 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19516 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19517 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19519 #undef THUMB_VARIANT
19520 #define THUMB_VARIANT & fpu_vfp_ext_v3
19522 #define ARM_VARIANT & fpu_vfp_ext_v3
19524 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
19525 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19526 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19527 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19528 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19529 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19530 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19531 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19532 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19535 #define ARM_VARIANT &fpu_vfp_ext_fma
19536 #undef THUMB_VARIANT
19537 #define THUMB_VARIANT &fpu_vfp_ext_fma
19538 /* Mnemonics shared by Neon and VFP. These are included in the
19539 VFP FMA variant; NEON and VFP FMA always includes the NEON
19540 FMA instructions. */
19541 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19542 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19543 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19544 the v form should always be used. */
19545 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19546 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19547 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19548 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19549 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19550 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19552 #undef THUMB_VARIANT
19554 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19556 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19557 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19558 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19559 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19560 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19561 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19562 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19563 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
19566 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19568 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19569 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19570 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19571 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19572 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19573 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19574 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19575 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19576 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19577 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19578 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19579 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19580 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19581 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19582 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19583 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19584 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19585 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19586 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19587 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19588 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19589 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19590 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19591 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19592 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19593 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19594 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
19595 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
19596 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
19597 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19598 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19599 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19600 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19601 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19602 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19603 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19604 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19605 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19606 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19607 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19608 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19609 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19610 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19611 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19612 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19613 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19614 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19615 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19616 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19617 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19618 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19619 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19620 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19621 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19622 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19623 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19624 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19625 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19626 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19627 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19628 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19629 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19630 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19631 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19632 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19633 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19634 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19635 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19636 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19637 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19638 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19639 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19640 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19641 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19642 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19643 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19644 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19645 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19646 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19647 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19648 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19649 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19650 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19651 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19652 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19653 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19654 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19655 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19656 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19657 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19658 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19659 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19660 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19661 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19662 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19663 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19664 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19665 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19666 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19667 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19668 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19669 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19670 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19671 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19672 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19673 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19674 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19675 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19676 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19677 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19678 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19679 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19680 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19681 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19682 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19683 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19684 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19685 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19686 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19687 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19688 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19689 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19690 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19691 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19692 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19693 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19694 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19695 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19696 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19697 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19698 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19699 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19700 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19701 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19702 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19703 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19704 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19705 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19706 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19707 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19708 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19709 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19710 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19711 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19712 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19713 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19714 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19715 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19716 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19717 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19718 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19719 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19720 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19721 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19722 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19723 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19724 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19725 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19726 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19727 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19728 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19729 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
19732 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19734 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19735 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19736 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19737 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19738 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19739 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19740 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19741 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19742 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19743 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19744 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19745 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19746 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19747 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19748 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19749 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19750 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19751 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19752 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19753 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19754 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19755 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19756 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19757 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19758 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19759 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19760 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19761 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19762 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19763 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19764 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19765 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19766 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19767 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19768 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19769 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19770 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19771 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19772 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19773 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19774 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19775 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19776 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19777 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19778 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19779 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19780 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19781 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19782 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19783 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19784 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19785 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19786 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19787 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19788 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19789 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19790 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19793 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19795 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19796 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19797 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19798 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19799 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19800 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19801 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19802 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19803 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19804 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19805 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19806 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19807 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19808 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19809 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
19810 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
19811 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
19812 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
19813 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
19814 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
19815 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
19816 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
19817 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
19818 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
19819 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19820 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19821 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19822 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19823 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19824 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
19825 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19826 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19827 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19828 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19829 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
19830 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
19831 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
19832 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
19833 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
19834 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
19835 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19836 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19837 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
19838 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
19839 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19840 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19841 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19842 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19843 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19844 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19845 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19846 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19847 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19848 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19849 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19850 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19851 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19852 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19853 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19854 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19855 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19856 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19857 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19858 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19859 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19860 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19861 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19862 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19863 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19864 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19865 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19866 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19867 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19868 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19869 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19870 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19873 #undef THUMB_VARIANT
19899 /* MD interface: bits in the object file. */
19901 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19902 for use in the a.out file, and stores them in the array pointed to by buf.
19903 This knows about the endian-ness of the target machine and does
19904 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19905 2 (short) and 4 (long) Floating numbers are put out as a series of
19906 LITTLENUMS (shorts, here at least). */
19909 md_number_to_chars (char * buf, valueT val, int n)
19911 if (target_big_endian)
19912 number_to_chars_bigendian (buf, val, n);
19914 number_to_chars_littleendian (buf, val, n);
19918 md_chars_to_number (char * buf, int n)
19921 unsigned char * where = (unsigned char *) buf;
19923 if (target_big_endian)
19928 result |= (*where++ & 255);
19936 result |= (where[n] & 255);
19943 /* MD interface: Sections. */
19945 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19946 that an rs_machine_dependent frag may reach. */
19949 arm_frag_max_var (fragS *fragp)
19951 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19952 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19954 Note that we generate relaxable instructions even for cases that don't
19955 really need it, like an immediate that's a trivial constant. So we're
19956 overestimating the instruction size for some of those cases. Rather
19957 than putting more intelligence here, it would probably be better to
19958 avoid generating a relaxation frag in the first place when it can be
19959 determined up front that a short instruction will suffice. */
19961 gas_assert (fragp->fr_type == rs_machine_dependent);
19965 /* Estimate the size of a frag before relaxing. Assume everything fits in
19969 md_estimate_size_before_relax (fragS * fragp,
19970 segT segtype ATTRIBUTE_UNUSED)
19976 /* Convert a machine dependent frag. */
19979 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19981 unsigned long insn;
19982 unsigned long old_op;
19990 buf = fragp->fr_literal + fragp->fr_fix;
19992 old_op = bfd_get_16(abfd, buf);
19993 if (fragp->fr_symbol)
19995 exp.X_op = O_symbol;
19996 exp.X_add_symbol = fragp->fr_symbol;
20000 exp.X_op = O_constant;
20002 exp.X_add_number = fragp->fr_offset;
20003 opcode = fragp->fr_subtype;
20006 case T_MNEM_ldr_pc:
20007 case T_MNEM_ldr_pc2:
20008 case T_MNEM_ldr_sp:
20009 case T_MNEM_str_sp:
20016 if (fragp->fr_var == 4)
20018 insn = THUMB_OP32 (opcode);
20019 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
20021 insn |= (old_op & 0x700) << 4;
20025 insn |= (old_op & 7) << 12;
20026 insn |= (old_op & 0x38) << 13;
20028 insn |= 0x00000c00;
20029 put_thumb32_insn (buf, insn);
20030 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
20034 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
20036 pc_rel = (opcode == T_MNEM_ldr_pc2);
20039 if (fragp->fr_var == 4)
20041 insn = THUMB_OP32 (opcode);
20042 insn |= (old_op & 0xf0) << 4;
20043 put_thumb32_insn (buf, insn);
20044 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
20048 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20049 exp.X_add_number -= 4;
20057 if (fragp->fr_var == 4)
20059 int r0off = (opcode == T_MNEM_mov
20060 || opcode == T_MNEM_movs) ? 0 : 8;
20061 insn = THUMB_OP32 (opcode);
20062 insn = (insn & 0xe1ffffff) | 0x10000000;
20063 insn |= (old_op & 0x700) << r0off;
20064 put_thumb32_insn (buf, insn);
20065 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20069 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
20074 if (fragp->fr_var == 4)
20076 insn = THUMB_OP32(opcode);
20077 put_thumb32_insn (buf, insn);
20078 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
20081 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
20085 if (fragp->fr_var == 4)
20087 insn = THUMB_OP32(opcode);
20088 insn |= (old_op & 0xf00) << 14;
20089 put_thumb32_insn (buf, insn);
20090 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
20093 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
20096 case T_MNEM_add_sp:
20097 case T_MNEM_add_pc:
20098 case T_MNEM_inc_sp:
20099 case T_MNEM_dec_sp:
20100 if (fragp->fr_var == 4)
20102 /* ??? Choose between add and addw. */
20103 insn = THUMB_OP32 (opcode);
20104 insn |= (old_op & 0xf0) << 4;
20105 put_thumb32_insn (buf, insn);
20106 if (opcode == T_MNEM_add_pc)
20107 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20109 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20112 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20120 if (fragp->fr_var == 4)
20122 insn = THUMB_OP32 (opcode);
20123 insn |= (old_op & 0xf0) << 4;
20124 insn |= (old_op & 0xf) << 16;
20125 put_thumb32_insn (buf, insn);
20126 if (insn & (1 << 20))
20127 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20129 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20132 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20138 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
20139 (enum bfd_reloc_code_real) reloc_type);
20140 fixp->fx_file = fragp->fr_file;
20141 fixp->fx_line = fragp->fr_line;
20142 fragp->fr_fix += fragp->fr_var;
20145 /* Return the size of a relaxable immediate operand instruction.
20146 SHIFT and SIZE specify the form of the allowable immediate. */
20148 relax_immediate (fragS *fragp, int size, int shift)
20154 /* ??? Should be able to do better than this. */
20155 if (fragp->fr_symbol)
20158 low = (1 << shift) - 1;
20159 mask = (1 << (shift + size)) - (1 << shift);
20160 offset = fragp->fr_offset;
20161 /* Force misaligned offsets to 32-bit variant. */
20164 if (offset & ~mask)
20169 /* Get the address of a symbol during relaxation. */
20171 relaxed_symbol_addr (fragS *fragp, long stretch)
20177 sym = fragp->fr_symbol;
20178 sym_frag = symbol_get_frag (sym);
20179 know (S_GET_SEGMENT (sym) != absolute_section
20180 || sym_frag == &zero_address_frag);
20181 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20183 /* If frag has yet to be reached on this pass, assume it will
20184 move by STRETCH just as we did. If this is not so, it will
20185 be because some frag between grows, and that will force
20189 && sym_frag->relax_marker != fragp->relax_marker)
20193 /* Adjust stretch for any alignment frag. Note that if have
20194 been expanding the earlier code, the symbol may be
20195 defined in what appears to be an earlier frag. FIXME:
20196 This doesn't handle the fr_subtype field, which specifies
20197 a maximum number of bytes to skip when doing an
20199 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20201 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20204 stretch = - ((- stretch)
20205 & ~ ((1 << (int) f->fr_offset) - 1));
20207 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20219 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20222 relax_adr (fragS *fragp, asection *sec, long stretch)
20227 /* Assume worst case for symbols not known to be in the same section. */
20228 if (fragp->fr_symbol == NULL
20229 || !S_IS_DEFINED (fragp->fr_symbol)
20230 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20231 || S_IS_WEAK (fragp->fr_symbol))
20234 val = relaxed_symbol_addr (fragp, stretch);
20235 addr = fragp->fr_address + fragp->fr_fix;
20236 addr = (addr + 4) & ~3;
20237 /* Force misaligned targets to 32-bit variant. */
20241 if (val < 0 || val > 1020)
20246 /* Return the size of a relaxable add/sub immediate instruction. */
20248 relax_addsub (fragS *fragp, asection *sec)
20253 buf = fragp->fr_literal + fragp->fr_fix;
20254 op = bfd_get_16(sec->owner, buf);
20255 if ((op & 0xf) == ((op >> 4) & 0xf))
20256 return relax_immediate (fragp, 8, 0);
20258 return relax_immediate (fragp, 3, 0);
20262 /* Return the size of a relaxable branch instruction. BITS is the
20263 size of the offset field in the narrow instruction. */
20266 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
20272 /* Assume worst case for symbols not known to be in the same section. */
20273 if (!S_IS_DEFINED (fragp->fr_symbol)
20274 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20275 || S_IS_WEAK (fragp->fr_symbol))
20279 if (S_IS_DEFINED (fragp->fr_symbol)
20280 && ARM_IS_FUNC (fragp->fr_symbol))
20283 /* PR 12532. Global symbols with default visibility might
20284 be preempted, so do not relax relocations to them. */
20285 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
20286 && (! S_IS_LOCAL (fragp->fr_symbol)))
20290 val = relaxed_symbol_addr (fragp, stretch);
20291 addr = fragp->fr_address + fragp->fr_fix + 4;
20294 /* Offset is a signed value *2 */
20296 if (val >= limit || val < -limit)
20302 /* Relax a machine dependent frag. This returns the amount by which
20303 the current size of the frag should change. */
20306 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
20311 oldsize = fragp->fr_var;
20312 switch (fragp->fr_subtype)
20314 case T_MNEM_ldr_pc2:
20315 newsize = relax_adr (fragp, sec, stretch);
20317 case T_MNEM_ldr_pc:
20318 case T_MNEM_ldr_sp:
20319 case T_MNEM_str_sp:
20320 newsize = relax_immediate (fragp, 8, 2);
20324 newsize = relax_immediate (fragp, 5, 2);
20328 newsize = relax_immediate (fragp, 5, 1);
20332 newsize = relax_immediate (fragp, 5, 0);
20335 newsize = relax_adr (fragp, sec, stretch);
20341 newsize = relax_immediate (fragp, 8, 0);
20344 newsize = relax_branch (fragp, sec, 11, stretch);
20347 newsize = relax_branch (fragp, sec, 8, stretch);
20349 case T_MNEM_add_sp:
20350 case T_MNEM_add_pc:
20351 newsize = relax_immediate (fragp, 8, 2);
20353 case T_MNEM_inc_sp:
20354 case T_MNEM_dec_sp:
20355 newsize = relax_immediate (fragp, 7, 2);
20361 newsize = relax_addsub (fragp, sec);
20367 fragp->fr_var = newsize;
20368 /* Freeze wide instructions that are at or before the same location as
20369 in the previous pass. This avoids infinite loops.
20370 Don't freeze them unconditionally because targets may be artificially
20371 misaligned by the expansion of preceding frags. */
20372 if (stretch <= 0 && newsize > 2)
20374 md_convert_frag (sec->owner, sec, fragp);
20378 return newsize - oldsize;
20381 /* Round up a section size to the appropriate boundary. */
20384 md_section_align (segT segment ATTRIBUTE_UNUSED,
20387 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20388 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20390 /* For a.out, force the section size to be aligned. If we don't do
20391 this, BFD will align it for us, but it will not write out the
20392 final bytes of the section. This may be a bug in BFD, but it is
20393 easier to fix it here since that is how the other a.out targets
20397 align = bfd_get_section_alignment (stdoutput, segment);
20398 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20405 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20406 of an rs_align_code fragment. */
20409 arm_handle_align (fragS * fragP)
20411 static char const arm_noop[2][2][4] =
20414 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20415 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20418 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20419 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20422 static char const thumb_noop[2][2][2] =
20425 {0xc0, 0x46}, /* LE */
20426 {0x46, 0xc0}, /* BE */
20429 {0x00, 0xbf}, /* LE */
20430 {0xbf, 0x00} /* BE */
20433 static char const wide_thumb_noop[2][4] =
20434 { /* Wide Thumb-2 */
20435 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20436 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20439 unsigned bytes, fix, noop_size;
20442 const char *narrow_noop = NULL;
20447 if (fragP->fr_type != rs_align_code)
20450 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20451 p = fragP->fr_literal + fragP->fr_fix;
20454 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20455 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
20457 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
20459 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
20461 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
20463 narrow_noop = thumb_noop[1][target_big_endian];
20464 noop = wide_thumb_noop[target_big_endian];
20467 noop = thumb_noop[0][target_big_endian];
20475 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
20476 [target_big_endian];
20483 fragP->fr_var = noop_size;
20485 if (bytes & (noop_size - 1))
20487 fix = bytes & (noop_size - 1);
20489 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20491 memset (p, 0, fix);
20498 if (bytes & noop_size)
20500 /* Insert a narrow noop. */
20501 memcpy (p, narrow_noop, noop_size);
20503 bytes -= noop_size;
20507 /* Use wide noops for the remainder */
20511 while (bytes >= noop_size)
20513 memcpy (p, noop, noop_size);
20515 bytes -= noop_size;
20519 fragP->fr_fix += fix;
20522 /* Called from md_do_align. Used to create an alignment
20523 frag in a code section. */
20526 arm_frag_align_code (int n, int max)
20530 /* We assume that there will never be a requirement
20531 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20532 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
20537 _("alignments greater than %d bytes not supported in .text sections."),
20538 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20539 as_fatal ("%s", err_msg);
20542 p = frag_var (rs_align_code,
20543 MAX_MEM_FOR_RS_ALIGN_CODE,
20545 (relax_substateT) max,
20552 /* Perform target specific initialisation of a frag.
20553 Note - despite the name this initialisation is not done when the frag
20554 is created, but only when its type is assigned. A frag can be created
20555 and used a long time before its type is set, so beware of assuming that
20556 this initialisationis performed first. */
20560 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20562 /* Record whether this frag is in an ARM or a THUMB area. */
20563 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20566 #else /* OBJ_ELF is defined. */
20568 arm_init_frag (fragS * fragP, int max_chars)
20570 /* If the current ARM vs THUMB mode has not already
20571 been recorded into this frag then do so now. */
20572 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20574 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20576 /* Record a mapping symbol for alignment frags. We will delete this
20577 later if the alignment ends up empty. */
20578 switch (fragP->fr_type)
20581 case rs_align_test:
20583 mapping_state_2 (MAP_DATA, max_chars);
20585 case rs_align_code:
20586 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20594 /* When we change sections we need to issue a new mapping symbol. */
20597 arm_elf_change_section (void)
20599 /* Link an unlinked unwind index table section to the .text section. */
20600 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20601 && elf_linked_to_section (now_seg) == NULL)
20602 elf_linked_to_section (now_seg) = text_section;
20606 arm_elf_section_type (const char * str, size_t len)
20608 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20609 return SHT_ARM_EXIDX;
20614 /* Code to deal with unwinding tables. */
20616 static void add_unwind_adjustsp (offsetT);
20618 /* Generate any deferred unwind frame offset. */
20621 flush_pending_unwind (void)
20625 offset = unwind.pending_offset;
20626 unwind.pending_offset = 0;
20628 add_unwind_adjustsp (offset);
20631 /* Add an opcode to this list for this function. Two-byte opcodes should
20632 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20636 add_unwind_opcode (valueT op, int length)
20638 /* Add any deferred stack adjustment. */
20639 if (unwind.pending_offset)
20640 flush_pending_unwind ();
20642 unwind.sp_restored = 0;
20644 if (unwind.opcode_count + length > unwind.opcode_alloc)
20646 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20647 if (unwind.opcodes)
20648 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
20649 unwind.opcode_alloc);
20651 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
20656 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20658 unwind.opcode_count++;
20662 /* Add unwind opcodes to adjust the stack pointer. */
20665 add_unwind_adjustsp (offsetT offset)
20669 if (offset > 0x200)
20671 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20676 /* Long form: 0xb2, uleb128. */
20677 /* This might not fit in a word so add the individual bytes,
20678 remembering the list is built in reverse order. */
20679 o = (valueT) ((offset - 0x204) >> 2);
20681 add_unwind_opcode (0, 1);
20683 /* Calculate the uleb128 encoding of the offset. */
20687 bytes[n] = o & 0x7f;
20693 /* Add the insn. */
20695 add_unwind_opcode (bytes[n - 1], 1);
20696 add_unwind_opcode (0xb2, 1);
20698 else if (offset > 0x100)
20700 /* Two short opcodes. */
20701 add_unwind_opcode (0x3f, 1);
20702 op = (offset - 0x104) >> 2;
20703 add_unwind_opcode (op, 1);
20705 else if (offset > 0)
20707 /* Short opcode. */
20708 op = (offset - 4) >> 2;
20709 add_unwind_opcode (op, 1);
20711 else if (offset < 0)
20714 while (offset > 0x100)
20716 add_unwind_opcode (0x7f, 1);
20719 op = ((offset - 4) >> 2) | 0x40;
20720 add_unwind_opcode (op, 1);
20724 /* Finish the list of unwind opcodes for this function. */
20726 finish_unwind_opcodes (void)
20730 if (unwind.fp_used)
20732 /* Adjust sp as necessary. */
20733 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20734 flush_pending_unwind ();
20736 /* After restoring sp from the frame pointer. */
20737 op = 0x90 | unwind.fp_reg;
20738 add_unwind_opcode (op, 1);
20741 flush_pending_unwind ();
20745 /* Start an exception table entry. If idx is nonzero this is an index table
20749 start_unwind_section (const segT text_seg, int idx)
20751 const char * text_name;
20752 const char * prefix;
20753 const char * prefix_once;
20754 const char * group_name;
20758 size_t sec_name_len;
20765 prefix = ELF_STRING_ARM_unwind;
20766 prefix_once = ELF_STRING_ARM_unwind_once;
20767 type = SHT_ARM_EXIDX;
20771 prefix = ELF_STRING_ARM_unwind_info;
20772 prefix_once = ELF_STRING_ARM_unwind_info_once;
20773 type = SHT_PROGBITS;
20776 text_name = segment_name (text_seg);
20777 if (streq (text_name, ".text"))
20780 if (strncmp (text_name, ".gnu.linkonce.t.",
20781 strlen (".gnu.linkonce.t.")) == 0)
20783 prefix = prefix_once;
20784 text_name += strlen (".gnu.linkonce.t.");
20787 prefix_len = strlen (prefix);
20788 text_len = strlen (text_name);
20789 sec_name_len = prefix_len + text_len;
20790 sec_name = (char *) xmalloc (sec_name_len + 1);
20791 memcpy (sec_name, prefix, prefix_len);
20792 memcpy (sec_name + prefix_len, text_name, text_len);
20793 sec_name[prefix_len + text_len] = '\0';
20799 /* Handle COMDAT group. */
20800 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20802 group_name = elf_group_name (text_seg);
20803 if (group_name == NULL)
20805 as_bad (_("Group section `%s' has no group signature"),
20806 segment_name (text_seg));
20807 ignore_rest_of_line ();
20810 flags |= SHF_GROUP;
20814 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20816 /* Set the section link for index tables. */
20818 elf_linked_to_section (now_seg) = text_seg;
20822 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20823 personality routine data. Returns zero, or the index table value for
20824 and inline entry. */
20827 create_unwind_entry (int have_data)
20832 /* The current word of data. */
20834 /* The number of bytes left in this word. */
20837 finish_unwind_opcodes ();
20839 /* Remember the current text section. */
20840 unwind.saved_seg = now_seg;
20841 unwind.saved_subseg = now_subseg;
20843 start_unwind_section (now_seg, 0);
20845 if (unwind.personality_routine == NULL)
20847 if (unwind.personality_index == -2)
20850 as_bad (_("handlerdata in cantunwind frame"));
20851 return 1; /* EXIDX_CANTUNWIND. */
20854 /* Use a default personality routine if none is specified. */
20855 if (unwind.personality_index == -1)
20857 if (unwind.opcode_count > 3)
20858 unwind.personality_index = 1;
20860 unwind.personality_index = 0;
20863 /* Space for the personality routine entry. */
20864 if (unwind.personality_index == 0)
20866 if (unwind.opcode_count > 3)
20867 as_bad (_("too many unwind opcodes for personality routine 0"));
20871 /* All the data is inline in the index table. */
20874 while (unwind.opcode_count > 0)
20876 unwind.opcode_count--;
20877 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20881 /* Pad with "finish" opcodes. */
20883 data = (data << 8) | 0xb0;
20890 /* We get two opcodes "free" in the first word. */
20891 size = unwind.opcode_count - 2;
20895 gas_assert (unwind.personality_index == -1);
20897 /* An extra byte is required for the opcode count. */
20898 size = unwind.opcode_count + 1;
20901 size = (size + 3) >> 2;
20903 as_bad (_("too many unwind opcodes"));
20905 frag_align (2, 0, 0);
20906 record_alignment (now_seg, 2);
20907 unwind.table_entry = expr_build_dot ();
20909 /* Allocate the table entry. */
20910 ptr = frag_more ((size << 2) + 4);
20911 /* PR 13449: Zero the table entries in case some of them are not used. */
20912 memset (ptr, 0, (size << 2) + 4);
20913 where = frag_now_fix () - ((size << 2) + 4);
20915 switch (unwind.personality_index)
20918 /* ??? Should this be a PLT generating relocation? */
20919 /* Custom personality routine. */
20920 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20921 BFD_RELOC_ARM_PREL31);
20926 /* Set the first byte to the number of additional words. */
20927 data = size > 0 ? size - 1 : 0;
20931 /* ABI defined personality routines. */
20933 /* Three opcodes bytes are packed into the first word. */
20940 /* The size and first two opcode bytes go in the first word. */
20941 data = ((0x80 + unwind.personality_index) << 8) | size;
20946 /* Should never happen. */
20950 /* Pack the opcodes into words (MSB first), reversing the list at the same
20952 while (unwind.opcode_count > 0)
20956 md_number_to_chars (ptr, data, 4);
20961 unwind.opcode_count--;
20963 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20966 /* Finish off the last word. */
20969 /* Pad with "finish" opcodes. */
20971 data = (data << 8) | 0xb0;
20973 md_number_to_chars (ptr, data, 4);
20978 /* Add an empty descriptor if there is no user-specified data. */
20979 ptr = frag_more (4);
20980 md_number_to_chars (ptr, 0, 4);
20987 /* Initialize the DWARF-2 unwind information for this procedure. */
20990 tc_arm_frame_initial_instructions (void)
20992 cfi_add_CFA_def_cfa (REG_SP, 0);
20994 #endif /* OBJ_ELF */
20996 /* Convert REGNAME to a DWARF-2 register number. */
20999 tc_arm_regname_to_dw2regnum (char *regname)
21001 int reg = arm_reg_parse (®name, REG_TYPE_RN);
21011 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
21015 exp.X_op = O_secrel;
21016 exp.X_add_symbol = symbol;
21017 exp.X_add_number = 0;
21018 emit_expr (&exp, size);
21022 /* MD interface: Symbol and relocation handling. */
21024 /* Return the address within the segment that a PC-relative fixup is
21025 relative to. For ARM, PC-relative fixups applied to instructions
21026 are generally relative to the location of the fixup plus 8 bytes.
21027 Thumb branches are offset by 4, and Thumb loads relative to PC
21028 require special handling. */
21031 md_pcrel_from_section (fixS * fixP, segT seg)
21033 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
21035 /* If this is pc-relative and we are going to emit a relocation
21036 then we just want to put out any pipeline compensation that the linker
21037 will need. Otherwise we want to use the calculated base.
21038 For WinCE we skip the bias for externals as well, since this
21039 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21041 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
21042 || (arm_force_relocation (fixP)
21044 && !S_IS_EXTERNAL (fixP->fx_addsy)
21050 switch (fixP->fx_r_type)
21052 /* PC relative addressing on the Thumb is slightly odd as the
21053 bottom two bits of the PC are forced to zero for the
21054 calculation. This happens *after* application of the
21055 pipeline offset. However, Thumb adrl already adjusts for
21056 this, so we need not do it again. */
21057 case BFD_RELOC_ARM_THUMB_ADD:
21060 case BFD_RELOC_ARM_THUMB_OFFSET:
21061 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21062 case BFD_RELOC_ARM_T32_ADD_PC12:
21063 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21064 return (base + 4) & ~3;
21066 /* Thumb branches are simply offset by +4. */
21067 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21068 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21069 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21070 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21071 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21074 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21076 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21077 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21078 && ARM_IS_FUNC (fixP->fx_addsy)
21079 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21080 base = fixP->fx_where + fixP->fx_frag->fr_address;
21083 /* BLX is like branches above, but forces the low two bits of PC to
21085 case BFD_RELOC_THUMB_PCREL_BLX:
21087 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21088 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21089 && THUMB_IS_FUNC (fixP->fx_addsy)
21090 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21091 base = fixP->fx_where + fixP->fx_frag->fr_address;
21092 return (base + 4) & ~3;
21094 /* ARM mode branches are offset by +8. However, the Windows CE
21095 loader expects the relocation not to take this into account. */
21096 case BFD_RELOC_ARM_PCREL_BLX:
21098 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21099 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21100 && ARM_IS_FUNC (fixP->fx_addsy)
21101 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21102 base = fixP->fx_where + fixP->fx_frag->fr_address;
21105 case BFD_RELOC_ARM_PCREL_CALL:
21107 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21108 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21109 && THUMB_IS_FUNC (fixP->fx_addsy)
21110 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21111 base = fixP->fx_where + fixP->fx_frag->fr_address;
21114 case BFD_RELOC_ARM_PCREL_BRANCH:
21115 case BFD_RELOC_ARM_PCREL_JUMP:
21116 case BFD_RELOC_ARM_PLT32:
21118 /* When handling fixups immediately, because we have already
21119 discovered the value of a symbol, or the address of the frag involved
21120 we must account for the offset by +8, as the OS loader will never see the reloc.
21121 see fixup_segment() in write.c
21122 The S_IS_EXTERNAL test handles the case of global symbols.
21123 Those need the calculated base, not just the pipe compensation the linker will need. */
21125 && fixP->fx_addsy != NULL
21126 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21127 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21135 /* ARM mode loads relative to PC are also offset by +8. Unlike
21136 branches, the Windows CE loader *does* expect the relocation
21137 to take this into account. */
21138 case BFD_RELOC_ARM_OFFSET_IMM:
21139 case BFD_RELOC_ARM_OFFSET_IMM8:
21140 case BFD_RELOC_ARM_HWLITERAL:
21141 case BFD_RELOC_ARM_LITERAL:
21142 case BFD_RELOC_ARM_CP_OFF_IMM:
21146 /* Other PC-relative relocations are un-offset. */
21152 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21153 Otherwise we have no need to default values of symbols. */
21156 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
21159 if (name[0] == '_' && name[1] == 'G'
21160 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21164 if (symbol_find (name))
21165 as_bad (_("GOT already in the symbol table"));
21167 GOT_symbol = symbol_new (name, undefined_section,
21168 (valueT) 0, & zero_address_frag);
21178 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21179 computed as two separate immediate values, added together. We
21180 already know that this value cannot be computed by just one ARM
21183 static unsigned int
21184 validate_immediate_twopart (unsigned int val,
21185 unsigned int * highpart)
21190 for (i = 0; i < 32; i += 2)
21191 if (((a = rotate_left (val, i)) & 0xff) != 0)
21197 * highpart = (a >> 8) | ((i + 24) << 7);
21199 else if (a & 0xff0000)
21201 if (a & 0xff000000)
21203 * highpart = (a >> 16) | ((i + 16) << 7);
21207 gas_assert (a & 0xff000000);
21208 * highpart = (a >> 24) | ((i + 8) << 7);
21211 return (a & 0xff) | (i << 7);
21218 validate_offset_imm (unsigned int val, int hwse)
21220 if ((hwse && val > 255) || val > 4095)
21225 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21226 negative immediate constant by altering the instruction. A bit of
21231 by inverting the second operand, and
21234 by negating the second operand. */
21237 negate_data_op (unsigned long * instruction,
21238 unsigned long value)
21241 unsigned long negated, inverted;
21243 negated = encode_arm_immediate (-value);
21244 inverted = encode_arm_immediate (~value);
21246 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21249 /* First negates. */
21250 case OPCODE_SUB: /* ADD <-> SUB */
21251 new_inst = OPCODE_ADD;
21256 new_inst = OPCODE_SUB;
21260 case OPCODE_CMP: /* CMP <-> CMN */
21261 new_inst = OPCODE_CMN;
21266 new_inst = OPCODE_CMP;
21270 /* Now Inverted ops. */
21271 case OPCODE_MOV: /* MOV <-> MVN */
21272 new_inst = OPCODE_MVN;
21277 new_inst = OPCODE_MOV;
21281 case OPCODE_AND: /* AND <-> BIC */
21282 new_inst = OPCODE_BIC;
21287 new_inst = OPCODE_AND;
21291 case OPCODE_ADC: /* ADC <-> SBC */
21292 new_inst = OPCODE_SBC;
21297 new_inst = OPCODE_ADC;
21301 /* We cannot do anything. */
21306 if (value == (unsigned) FAIL)
21309 *instruction &= OPCODE_MASK;
21310 *instruction |= new_inst << DATA_OP_SHIFT;
21314 /* Like negate_data_op, but for Thumb-2. */
21316 static unsigned int
21317 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
21321 unsigned int negated, inverted;
21323 negated = encode_thumb32_immediate (-value);
21324 inverted = encode_thumb32_immediate (~value);
21326 rd = (*instruction >> 8) & 0xf;
21327 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21330 /* ADD <-> SUB. Includes CMP <-> CMN. */
21331 case T2_OPCODE_SUB:
21332 new_inst = T2_OPCODE_ADD;
21336 case T2_OPCODE_ADD:
21337 new_inst = T2_OPCODE_SUB;
21341 /* ORR <-> ORN. Includes MOV <-> MVN. */
21342 case T2_OPCODE_ORR:
21343 new_inst = T2_OPCODE_ORN;
21347 case T2_OPCODE_ORN:
21348 new_inst = T2_OPCODE_ORR;
21352 /* AND <-> BIC. TST has no inverted equivalent. */
21353 case T2_OPCODE_AND:
21354 new_inst = T2_OPCODE_BIC;
21361 case T2_OPCODE_BIC:
21362 new_inst = T2_OPCODE_AND;
21367 case T2_OPCODE_ADC:
21368 new_inst = T2_OPCODE_SBC;
21372 case T2_OPCODE_SBC:
21373 new_inst = T2_OPCODE_ADC;
21377 /* We cannot do anything. */
21382 if (value == (unsigned int)FAIL)
21385 *instruction &= T2_OPCODE_MASK;
21386 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21390 /* Read a 32-bit thumb instruction from buf. */
21391 static unsigned long
21392 get_thumb32_insn (char * buf)
21394 unsigned long insn;
21395 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21396 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21402 /* We usually want to set the low bit on the address of thumb function
21403 symbols. In particular .word foo - . should have the low bit set.
21404 Generic code tries to fold the difference of two symbols to
21405 a constant. Prevent this and force a relocation when the first symbols
21406 is a thumb function. */
21409 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21411 if (op == O_subtract
21412 && l->X_op == O_symbol
21413 && r->X_op == O_symbol
21414 && THUMB_IS_FUNC (l->X_add_symbol))
21416 l->X_op = O_subtract;
21417 l->X_op_symbol = r->X_add_symbol;
21418 l->X_add_number -= r->X_add_number;
21422 /* Process as normal. */
21426 /* Encode Thumb2 unconditional branches and calls. The encoding
21427 for the 2 are identical for the immediate values. */
21430 encode_thumb2_b_bl_offset (char * buf, offsetT value)
21432 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21435 addressT S, I1, I2, lo, hi;
21437 S = (value >> 24) & 0x01;
21438 I1 = (value >> 23) & 0x01;
21439 I2 = (value >> 22) & 0x01;
21440 hi = (value >> 12) & 0x3ff;
21441 lo = (value >> 1) & 0x7ff;
21442 newval = md_chars_to_number (buf, THUMB_SIZE);
21443 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21444 newval |= (S << 10) | hi;
21445 newval2 &= ~T2I1I2MASK;
21446 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21447 md_number_to_chars (buf, newval, THUMB_SIZE);
21448 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21452 md_apply_fix (fixS * fixP,
21456 offsetT value = * valP;
21458 unsigned int newimm;
21459 unsigned long temp;
21461 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
21463 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
21465 /* Note whether this will delete the relocation. */
21467 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21470 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21471 consistency with the behaviour on 32-bit hosts. Remember value
21473 value &= 0xffffffff;
21474 value ^= 0x80000000;
21475 value -= 0x80000000;
21478 fixP->fx_addnumber = value;
21480 /* Same treatment for fixP->fx_offset. */
21481 fixP->fx_offset &= 0xffffffff;
21482 fixP->fx_offset ^= 0x80000000;
21483 fixP->fx_offset -= 0x80000000;
21485 switch (fixP->fx_r_type)
21487 case BFD_RELOC_NONE:
21488 /* This will need to go in the object file. */
21492 case BFD_RELOC_ARM_IMMEDIATE:
21493 /* We claim that this fixup has been processed here,
21494 even if in fact we generate an error because we do
21495 not have a reloc for it, so tc_gen_reloc will reject it. */
21498 if (fixP->fx_addsy)
21500 const char *msg = 0;
21502 if (! S_IS_DEFINED (fixP->fx_addsy))
21503 msg = _("undefined symbol %s used as an immediate value");
21504 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21505 msg = _("symbol %s is in a different section");
21506 else if (S_IS_WEAK (fixP->fx_addsy))
21507 msg = _("symbol %s is weak and may be overridden later");
21511 as_bad_where (fixP->fx_file, fixP->fx_line,
21512 msg, S_GET_NAME (fixP->fx_addsy));
21517 temp = md_chars_to_number (buf, INSN_SIZE);
21519 /* If the offset is negative, we should use encoding A2 for ADR. */
21520 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21521 newimm = negate_data_op (&temp, value);
21524 newimm = encode_arm_immediate (value);
21526 /* If the instruction will fail, see if we can fix things up by
21527 changing the opcode. */
21528 if (newimm == (unsigned int) FAIL)
21529 newimm = negate_data_op (&temp, value);
21532 if (newimm == (unsigned int) FAIL)
21534 as_bad_where (fixP->fx_file, fixP->fx_line,
21535 _("invalid constant (%lx) after fixup"),
21536 (unsigned long) value);
21540 newimm |= (temp & 0xfffff000);
21541 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21544 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21546 unsigned int highpart = 0;
21547 unsigned int newinsn = 0xe1a00000; /* nop. */
21549 if (fixP->fx_addsy)
21551 const char *msg = 0;
21553 if (! S_IS_DEFINED (fixP->fx_addsy))
21554 msg = _("undefined symbol %s used as an immediate value");
21555 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21556 msg = _("symbol %s is in a different section");
21557 else if (S_IS_WEAK (fixP->fx_addsy))
21558 msg = _("symbol %s is weak and may be overridden later");
21562 as_bad_where (fixP->fx_file, fixP->fx_line,
21563 msg, S_GET_NAME (fixP->fx_addsy));
21568 newimm = encode_arm_immediate (value);
21569 temp = md_chars_to_number (buf, INSN_SIZE);
21571 /* If the instruction will fail, see if we can fix things up by
21572 changing the opcode. */
21573 if (newimm == (unsigned int) FAIL
21574 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21576 /* No ? OK - try using two ADD instructions to generate
21578 newimm = validate_immediate_twopart (value, & highpart);
21580 /* Yes - then make sure that the second instruction is
21582 if (newimm != (unsigned int) FAIL)
21584 /* Still No ? Try using a negated value. */
21585 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21586 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21587 /* Otherwise - give up. */
21590 as_bad_where (fixP->fx_file, fixP->fx_line,
21591 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21596 /* Replace the first operand in the 2nd instruction (which
21597 is the PC) with the destination register. We have
21598 already added in the PC in the first instruction and we
21599 do not want to do it again. */
21600 newinsn &= ~ 0xf0000;
21601 newinsn |= ((newinsn & 0x0f000) << 4);
21604 newimm |= (temp & 0xfffff000);
21605 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21607 highpart |= (newinsn & 0xfffff000);
21608 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21612 case BFD_RELOC_ARM_OFFSET_IMM:
21613 if (!fixP->fx_done && seg->use_rela_p)
21616 case BFD_RELOC_ARM_LITERAL:
21622 if (validate_offset_imm (value, 0) == FAIL)
21624 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21625 as_bad_where (fixP->fx_file, fixP->fx_line,
21626 _("invalid literal constant: pool needs to be closer"));
21628 as_bad_where (fixP->fx_file, fixP->fx_line,
21629 _("bad immediate value for offset (%ld)"),
21634 newval = md_chars_to_number (buf, INSN_SIZE);
21636 newval &= 0xfffff000;
21639 newval &= 0xff7ff000;
21640 newval |= value | (sign ? INDEX_UP : 0);
21642 md_number_to_chars (buf, newval, INSN_SIZE);
21645 case BFD_RELOC_ARM_OFFSET_IMM8:
21646 case BFD_RELOC_ARM_HWLITERAL:
21652 if (validate_offset_imm (value, 1) == FAIL)
21654 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21655 as_bad_where (fixP->fx_file, fixP->fx_line,
21656 _("invalid literal constant: pool needs to be closer"));
21658 as_bad_where (fixP->fx_file, fixP->fx_line,
21659 _("bad immediate value for 8-bit offset (%ld)"),
21664 newval = md_chars_to_number (buf, INSN_SIZE);
21666 newval &= 0xfffff0f0;
21669 newval &= 0xff7ff0f0;
21670 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21672 md_number_to_chars (buf, newval, INSN_SIZE);
21675 case BFD_RELOC_ARM_T32_OFFSET_U8:
21676 if (value < 0 || value > 1020 || value % 4 != 0)
21677 as_bad_where (fixP->fx_file, fixP->fx_line,
21678 _("bad immediate value for offset (%ld)"), (long) value);
21681 newval = md_chars_to_number (buf+2, THUMB_SIZE);
21683 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21686 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21687 /* This is a complicated relocation used for all varieties of Thumb32
21688 load/store instruction with immediate offset:
21690 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21691 *4, optional writeback(W)
21692 (doubleword load/store)
21694 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21695 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21696 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21697 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21698 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21700 Uppercase letters indicate bits that are already encoded at
21701 this point. Lowercase letters are our problem. For the
21702 second block of instructions, the secondary opcode nybble
21703 (bits 8..11) is present, and bit 23 is zero, even if this is
21704 a PC-relative operation. */
21705 newval = md_chars_to_number (buf, THUMB_SIZE);
21707 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
21709 if ((newval & 0xf0000000) == 0xe0000000)
21711 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21713 newval |= (1 << 23);
21716 if (value % 4 != 0)
21718 as_bad_where (fixP->fx_file, fixP->fx_line,
21719 _("offset not a multiple of 4"));
21725 as_bad_where (fixP->fx_file, fixP->fx_line,
21726 _("offset out of range"));
21731 else if ((newval & 0x000f0000) == 0x000f0000)
21733 /* PC-relative, 12-bit offset. */
21735 newval |= (1 << 23);
21740 as_bad_where (fixP->fx_file, fixP->fx_line,
21741 _("offset out of range"));
21746 else if ((newval & 0x00000100) == 0x00000100)
21748 /* Writeback: 8-bit, +/- offset. */
21750 newval |= (1 << 9);
21755 as_bad_where (fixP->fx_file, fixP->fx_line,
21756 _("offset out of range"));
21761 else if ((newval & 0x00000f00) == 0x00000e00)
21763 /* T-instruction: positive 8-bit offset. */
21764 if (value < 0 || value > 0xff)
21766 as_bad_where (fixP->fx_file, fixP->fx_line,
21767 _("offset out of range"));
21775 /* Positive 12-bit or negative 8-bit offset. */
21779 newval |= (1 << 23);
21789 as_bad_where (fixP->fx_file, fixP->fx_line,
21790 _("offset out of range"));
21797 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21798 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21801 case BFD_RELOC_ARM_SHIFT_IMM:
21802 newval = md_chars_to_number (buf, INSN_SIZE);
21803 if (((unsigned long) value) > 32
21805 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21807 as_bad_where (fixP->fx_file, fixP->fx_line,
21808 _("shift expression is too large"));
21813 /* Shifts of zero must be done as lsl. */
21815 else if (value == 32)
21817 newval &= 0xfffff07f;
21818 newval |= (value & 0x1f) << 7;
21819 md_number_to_chars (buf, newval, INSN_SIZE);
21822 case BFD_RELOC_ARM_T32_IMMEDIATE:
21823 case BFD_RELOC_ARM_T32_ADD_IMM:
21824 case BFD_RELOC_ARM_T32_IMM12:
21825 case BFD_RELOC_ARM_T32_ADD_PC12:
21826 /* We claim that this fixup has been processed here,
21827 even if in fact we generate an error because we do
21828 not have a reloc for it, so tc_gen_reloc will reject it. */
21832 && ! S_IS_DEFINED (fixP->fx_addsy))
21834 as_bad_where (fixP->fx_file, fixP->fx_line,
21835 _("undefined symbol %s used as an immediate value"),
21836 S_GET_NAME (fixP->fx_addsy));
21840 newval = md_chars_to_number (buf, THUMB_SIZE);
21842 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21845 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21846 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21848 newimm = encode_thumb32_immediate (value);
21849 if (newimm == (unsigned int) FAIL)
21850 newimm = thumb32_negate_data_op (&newval, value);
21852 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21853 && newimm == (unsigned int) FAIL)
21855 /* Turn add/sum into addw/subw. */
21856 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21857 newval = (newval & 0xfeffffff) | 0x02000000;
21858 /* No flat 12-bit imm encoding for addsw/subsw. */
21859 if ((newval & 0x00100000) == 0)
21861 /* 12 bit immediate for addw/subw. */
21865 newval ^= 0x00a00000;
21868 newimm = (unsigned int) FAIL;
21874 if (newimm == (unsigned int)FAIL)
21876 as_bad_where (fixP->fx_file, fixP->fx_line,
21877 _("invalid constant (%lx) after fixup"),
21878 (unsigned long) value);
21882 newval |= (newimm & 0x800) << 15;
21883 newval |= (newimm & 0x700) << 4;
21884 newval |= (newimm & 0x0ff);
21886 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21887 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21890 case BFD_RELOC_ARM_SMC:
21891 if (((unsigned long) value) > 0xffff)
21892 as_bad_where (fixP->fx_file, fixP->fx_line,
21893 _("invalid smc expression"));
21894 newval = md_chars_to_number (buf, INSN_SIZE);
21895 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21896 md_number_to_chars (buf, newval, INSN_SIZE);
21899 case BFD_RELOC_ARM_HVC:
21900 if (((unsigned long) value) > 0xffff)
21901 as_bad_where (fixP->fx_file, fixP->fx_line,
21902 _("invalid hvc expression"));
21903 newval = md_chars_to_number (buf, INSN_SIZE);
21904 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21905 md_number_to_chars (buf, newval, INSN_SIZE);
21908 case BFD_RELOC_ARM_SWI:
21909 if (fixP->tc_fix_data != 0)
21911 if (((unsigned long) value) > 0xff)
21912 as_bad_where (fixP->fx_file, fixP->fx_line,
21913 _("invalid swi expression"));
21914 newval = md_chars_to_number (buf, THUMB_SIZE);
21916 md_number_to_chars (buf, newval, THUMB_SIZE);
21920 if (((unsigned long) value) > 0x00ffffff)
21921 as_bad_where (fixP->fx_file, fixP->fx_line,
21922 _("invalid swi expression"));
21923 newval = md_chars_to_number (buf, INSN_SIZE);
21925 md_number_to_chars (buf, newval, INSN_SIZE);
21929 case BFD_RELOC_ARM_MULTI:
21930 if (((unsigned long) value) > 0xffff)
21931 as_bad_where (fixP->fx_file, fixP->fx_line,
21932 _("invalid expression in load/store multiple"));
21933 newval = value | md_chars_to_number (buf, INSN_SIZE);
21934 md_number_to_chars (buf, newval, INSN_SIZE);
21938 case BFD_RELOC_ARM_PCREL_CALL:
21940 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21942 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21943 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21944 && THUMB_IS_FUNC (fixP->fx_addsy))
21945 /* Flip the bl to blx. This is a simple flip
21946 bit here because we generate PCREL_CALL for
21947 unconditional bls. */
21949 newval = md_chars_to_number (buf, INSN_SIZE);
21950 newval = newval | 0x10000000;
21951 md_number_to_chars (buf, newval, INSN_SIZE);
21957 goto arm_branch_common;
21959 case BFD_RELOC_ARM_PCREL_JUMP:
21960 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21962 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21963 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21964 && THUMB_IS_FUNC (fixP->fx_addsy))
21966 /* This would map to a bl<cond>, b<cond>,
21967 b<always> to a Thumb function. We
21968 need to force a relocation for this particular
21970 newval = md_chars_to_number (buf, INSN_SIZE);
21974 case BFD_RELOC_ARM_PLT32:
21976 case BFD_RELOC_ARM_PCREL_BRANCH:
21978 goto arm_branch_common;
21980 case BFD_RELOC_ARM_PCREL_BLX:
21983 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21985 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21986 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21987 && ARM_IS_FUNC (fixP->fx_addsy))
21989 /* Flip the blx to a bl and warn. */
21990 const char *name = S_GET_NAME (fixP->fx_addsy);
21991 newval = 0xeb000000;
21992 as_warn_where (fixP->fx_file, fixP->fx_line,
21993 _("blx to '%s' an ARM ISA state function changed to bl"),
21995 md_number_to_chars (buf, newval, INSN_SIZE);
22001 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22002 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
22006 /* We are going to store value (shifted right by two) in the
22007 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22008 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22009 also be be clear. */
22011 as_bad_where (fixP->fx_file, fixP->fx_line,
22012 _("misaligned branch destination"));
22013 if ((value & (offsetT)0xfe000000) != (offsetT)0
22014 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
22015 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22017 if (fixP->fx_done || !seg->use_rela_p)
22019 newval = md_chars_to_number (buf, INSN_SIZE);
22020 newval |= (value >> 2) & 0x00ffffff;
22021 /* Set the H bit on BLX instructions. */
22025 newval |= 0x01000000;
22027 newval &= ~0x01000000;
22029 md_number_to_chars (buf, newval, INSN_SIZE);
22033 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
22034 /* CBZ can only branch forward. */
22036 /* Attempts to use CBZ to branch to the next instruction
22037 (which, strictly speaking, are prohibited) will be turned into
22040 FIXME: It may be better to remove the instruction completely and
22041 perform relaxation. */
22044 newval = md_chars_to_number (buf, THUMB_SIZE);
22045 newval = 0xbf00; /* NOP encoding T1 */
22046 md_number_to_chars (buf, newval, THUMB_SIZE);
22051 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22053 if (fixP->fx_done || !seg->use_rela_p)
22055 newval = md_chars_to_number (buf, THUMB_SIZE);
22056 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
22057 md_number_to_chars (buf, newval, THUMB_SIZE);
22062 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
22063 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
22064 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22066 if (fixP->fx_done || !seg->use_rela_p)
22068 newval = md_chars_to_number (buf, THUMB_SIZE);
22069 newval |= (value & 0x1ff) >> 1;
22070 md_number_to_chars (buf, newval, THUMB_SIZE);
22074 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
22075 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
22076 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22078 if (fixP->fx_done || !seg->use_rela_p)
22080 newval = md_chars_to_number (buf, THUMB_SIZE);
22081 newval |= (value & 0xfff) >> 1;
22082 md_number_to_chars (buf, newval, THUMB_SIZE);
22086 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22088 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22089 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22090 && ARM_IS_FUNC (fixP->fx_addsy)
22091 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22093 /* Force a relocation for a branch 20 bits wide. */
22096 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
22097 as_bad_where (fixP->fx_file, fixP->fx_line,
22098 _("conditional branch out of range"));
22100 if (fixP->fx_done || !seg->use_rela_p)
22103 addressT S, J1, J2, lo, hi;
22105 S = (value & 0x00100000) >> 20;
22106 J2 = (value & 0x00080000) >> 19;
22107 J1 = (value & 0x00040000) >> 18;
22108 hi = (value & 0x0003f000) >> 12;
22109 lo = (value & 0x00000ffe) >> 1;
22111 newval = md_chars_to_number (buf, THUMB_SIZE);
22112 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22113 newval |= (S << 10) | hi;
22114 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22115 md_number_to_chars (buf, newval, THUMB_SIZE);
22116 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22120 case BFD_RELOC_THUMB_PCREL_BLX:
22121 /* If there is a blx from a thumb state function to
22122 another thumb function flip this to a bl and warn
22126 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22127 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22128 && THUMB_IS_FUNC (fixP->fx_addsy))
22130 const char *name = S_GET_NAME (fixP->fx_addsy);
22131 as_warn_where (fixP->fx_file, fixP->fx_line,
22132 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22134 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22135 newval = newval | 0x1000;
22136 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22137 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22142 goto thumb_bl_common;
22144 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22145 /* A bl from Thumb state ISA to an internal ARM state function
22146 is converted to a blx. */
22148 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22149 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22150 && ARM_IS_FUNC (fixP->fx_addsy)
22151 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22153 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22154 newval = newval & ~0x1000;
22155 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22156 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22162 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22163 /* For a BLX instruction, make sure that the relocation is rounded up
22164 to a word boundary. This follows the semantics of the instruction
22165 which specifies that bit 1 of the target address will come from bit
22166 1 of the base address. */
22167 value = (value + 3) & ~ 3;
22170 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22171 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22172 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22175 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22177 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22178 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22179 else if ((value & ~0x1ffffff)
22180 && ((value & ~0x1ffffff) != ~0x1ffffff))
22181 as_bad_where (fixP->fx_file, fixP->fx_line,
22182 _("Thumb2 branch out of range"));
22185 if (fixP->fx_done || !seg->use_rela_p)
22186 encode_thumb2_b_bl_offset (buf, value);
22190 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22191 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22192 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22194 if (fixP->fx_done || !seg->use_rela_p)
22195 encode_thumb2_b_bl_offset (buf, value);
22200 if (fixP->fx_done || !seg->use_rela_p)
22201 md_number_to_chars (buf, value, 1);
22205 if (fixP->fx_done || !seg->use_rela_p)
22206 md_number_to_chars (buf, value, 2);
22210 case BFD_RELOC_ARM_TLS_CALL:
22211 case BFD_RELOC_ARM_THM_TLS_CALL:
22212 case BFD_RELOC_ARM_TLS_DESCSEQ:
22213 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22214 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22217 case BFD_RELOC_ARM_TLS_GOTDESC:
22218 case BFD_RELOC_ARM_TLS_GD32:
22219 case BFD_RELOC_ARM_TLS_LE32:
22220 case BFD_RELOC_ARM_TLS_IE32:
22221 case BFD_RELOC_ARM_TLS_LDM32:
22222 case BFD_RELOC_ARM_TLS_LDO32:
22223 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22226 case BFD_RELOC_ARM_GOT32:
22227 case BFD_RELOC_ARM_GOTOFF:
22228 if (fixP->fx_done || !seg->use_rela_p)
22229 md_number_to_chars (buf, 0, 4);
22232 case BFD_RELOC_ARM_GOT_PREL:
22233 if (fixP->fx_done || !seg->use_rela_p)
22234 md_number_to_chars (buf, value, 4);
22237 case BFD_RELOC_ARM_TARGET2:
22238 /* TARGET2 is not partial-inplace, so we need to write the
22239 addend here for REL targets, because it won't be written out
22240 during reloc processing later. */
22241 if (fixP->fx_done || !seg->use_rela_p)
22242 md_number_to_chars (buf, fixP->fx_offset, 4);
22246 case BFD_RELOC_RVA:
22248 case BFD_RELOC_ARM_TARGET1:
22249 case BFD_RELOC_ARM_ROSEGREL32:
22250 case BFD_RELOC_ARM_SBREL32:
22251 case BFD_RELOC_32_PCREL:
22253 case BFD_RELOC_32_SECREL:
22255 if (fixP->fx_done || !seg->use_rela_p)
22257 /* For WinCE we only do this for pcrel fixups. */
22258 if (fixP->fx_done || fixP->fx_pcrel)
22260 md_number_to_chars (buf, value, 4);
22264 case BFD_RELOC_ARM_PREL31:
22265 if (fixP->fx_done || !seg->use_rela_p)
22267 newval = md_chars_to_number (buf, 4) & 0x80000000;
22268 if ((value ^ (value >> 1)) & 0x40000000)
22270 as_bad_where (fixP->fx_file, fixP->fx_line,
22271 _("rel31 relocation overflow"));
22273 newval |= value & 0x7fffffff;
22274 md_number_to_chars (buf, newval, 4);
22279 case BFD_RELOC_ARM_CP_OFF_IMM:
22280 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22281 if (value < -1023 || value > 1023 || (value & 3))
22282 as_bad_where (fixP->fx_file, fixP->fx_line,
22283 _("co-processor offset out of range"));
22288 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22289 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22290 newval = md_chars_to_number (buf, INSN_SIZE);
22292 newval = get_thumb32_insn (buf);
22294 newval &= 0xffffff00;
22297 newval &= 0xff7fff00;
22298 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22300 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22301 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22302 md_number_to_chars (buf, newval, INSN_SIZE);
22304 put_thumb32_insn (buf, newval);
22307 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
22308 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
22309 if (value < -255 || value > 255)
22310 as_bad_where (fixP->fx_file, fixP->fx_line,
22311 _("co-processor offset out of range"));
22313 goto cp_off_common;
22315 case BFD_RELOC_ARM_THUMB_OFFSET:
22316 newval = md_chars_to_number (buf, THUMB_SIZE);
22317 /* Exactly what ranges, and where the offset is inserted depends
22318 on the type of instruction, we can establish this from the
22320 switch (newval >> 12)
22322 case 4: /* PC load. */
22323 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22324 forced to zero for these loads; md_pcrel_from has already
22325 compensated for this. */
22327 as_bad_where (fixP->fx_file, fixP->fx_line,
22328 _("invalid offset, target not word aligned (0x%08lX)"),
22329 (((unsigned long) fixP->fx_frag->fr_address
22330 + (unsigned long) fixP->fx_where) & ~3)
22331 + (unsigned long) value);
22333 if (value & ~0x3fc)
22334 as_bad_where (fixP->fx_file, fixP->fx_line,
22335 _("invalid offset, value too big (0x%08lX)"),
22338 newval |= value >> 2;
22341 case 9: /* SP load/store. */
22342 if (value & ~0x3fc)
22343 as_bad_where (fixP->fx_file, fixP->fx_line,
22344 _("invalid offset, value too big (0x%08lX)"),
22346 newval |= value >> 2;
22349 case 6: /* Word load/store. */
22351 as_bad_where (fixP->fx_file, fixP->fx_line,
22352 _("invalid offset, value too big (0x%08lX)"),
22354 newval |= value << 4; /* 6 - 2. */
22357 case 7: /* Byte load/store. */
22359 as_bad_where (fixP->fx_file, fixP->fx_line,
22360 _("invalid offset, value too big (0x%08lX)"),
22362 newval |= value << 6;
22365 case 8: /* Halfword load/store. */
22367 as_bad_where (fixP->fx_file, fixP->fx_line,
22368 _("invalid offset, value too big (0x%08lX)"),
22370 newval |= value << 5; /* 6 - 1. */
22374 as_bad_where (fixP->fx_file, fixP->fx_line,
22375 "Unable to process relocation for thumb opcode: %lx",
22376 (unsigned long) newval);
22379 md_number_to_chars (buf, newval, THUMB_SIZE);
22382 case BFD_RELOC_ARM_THUMB_ADD:
22383 /* This is a complicated relocation, since we use it for all of
22384 the following immediate relocations:
22388 9bit ADD/SUB SP word-aligned
22389 10bit ADD PC/SP word-aligned
22391 The type of instruction being processed is encoded in the
22398 newval = md_chars_to_number (buf, THUMB_SIZE);
22400 int rd = (newval >> 4) & 0xf;
22401 int rs = newval & 0xf;
22402 int subtract = !!(newval & 0x8000);
22404 /* Check for HI regs, only very restricted cases allowed:
22405 Adjusting SP, and using PC or SP to get an address. */
22406 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22407 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22408 as_bad_where (fixP->fx_file, fixP->fx_line,
22409 _("invalid Hi register with immediate"));
22411 /* If value is negative, choose the opposite instruction. */
22415 subtract = !subtract;
22417 as_bad_where (fixP->fx_file, fixP->fx_line,
22418 _("immediate value out of range"));
22423 if (value & ~0x1fc)
22424 as_bad_where (fixP->fx_file, fixP->fx_line,
22425 _("invalid immediate for stack address calculation"));
22426 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22427 newval |= value >> 2;
22429 else if (rs == REG_PC || rs == REG_SP)
22431 if (subtract || value & ~0x3fc)
22432 as_bad_where (fixP->fx_file, fixP->fx_line,
22433 _("invalid immediate for address calculation (value = 0x%08lX)"),
22434 (unsigned long) value);
22435 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22437 newval |= value >> 2;
22442 as_bad_where (fixP->fx_file, fixP->fx_line,
22443 _("immediate value out of range"));
22444 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22445 newval |= (rd << 8) | value;
22450 as_bad_where (fixP->fx_file, fixP->fx_line,
22451 _("immediate value out of range"));
22452 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22453 newval |= rd | (rs << 3) | (value << 6);
22456 md_number_to_chars (buf, newval, THUMB_SIZE);
22459 case BFD_RELOC_ARM_THUMB_IMM:
22460 newval = md_chars_to_number (buf, THUMB_SIZE);
22461 if (value < 0 || value > 255)
22462 as_bad_where (fixP->fx_file, fixP->fx_line,
22463 _("invalid immediate: %ld is out of range"),
22466 md_number_to_chars (buf, newval, THUMB_SIZE);
22469 case BFD_RELOC_ARM_THUMB_SHIFT:
22470 /* 5bit shift value (0..32). LSL cannot take 32. */
22471 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22472 temp = newval & 0xf800;
22473 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22474 as_bad_where (fixP->fx_file, fixP->fx_line,
22475 _("invalid shift value: %ld"), (long) value);
22476 /* Shifts of zero must be encoded as LSL. */
22478 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22479 /* Shifts of 32 are encoded as zero. */
22480 else if (value == 32)
22482 newval |= value << 6;
22483 md_number_to_chars (buf, newval, THUMB_SIZE);
22486 case BFD_RELOC_VTABLE_INHERIT:
22487 case BFD_RELOC_VTABLE_ENTRY:
22491 case BFD_RELOC_ARM_MOVW:
22492 case BFD_RELOC_ARM_MOVT:
22493 case BFD_RELOC_ARM_THUMB_MOVW:
22494 case BFD_RELOC_ARM_THUMB_MOVT:
22495 if (fixP->fx_done || !seg->use_rela_p)
22497 /* REL format relocations are limited to a 16-bit addend. */
22498 if (!fixP->fx_done)
22500 if (value < -0x8000 || value > 0x7fff)
22501 as_bad_where (fixP->fx_file, fixP->fx_line,
22502 _("offset out of range"));
22504 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22505 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22510 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22511 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22513 newval = get_thumb32_insn (buf);
22514 newval &= 0xfbf08f00;
22515 newval |= (value & 0xf000) << 4;
22516 newval |= (value & 0x0800) << 15;
22517 newval |= (value & 0x0700) << 4;
22518 newval |= (value & 0x00ff);
22519 put_thumb32_insn (buf, newval);
22523 newval = md_chars_to_number (buf, 4);
22524 newval &= 0xfff0f000;
22525 newval |= value & 0x0fff;
22526 newval |= (value & 0xf000) << 4;
22527 md_number_to_chars (buf, newval, 4);
22532 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22533 case BFD_RELOC_ARM_ALU_PC_G0:
22534 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22535 case BFD_RELOC_ARM_ALU_PC_G1:
22536 case BFD_RELOC_ARM_ALU_PC_G2:
22537 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22538 case BFD_RELOC_ARM_ALU_SB_G0:
22539 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22540 case BFD_RELOC_ARM_ALU_SB_G1:
22541 case BFD_RELOC_ARM_ALU_SB_G2:
22542 gas_assert (!fixP->fx_done);
22543 if (!seg->use_rela_p)
22546 bfd_vma encoded_addend;
22547 bfd_vma addend_abs = abs (value);
22549 /* Check that the absolute value of the addend can be
22550 expressed as an 8-bit constant plus a rotation. */
22551 encoded_addend = encode_arm_immediate (addend_abs);
22552 if (encoded_addend == (unsigned int) FAIL)
22553 as_bad_where (fixP->fx_file, fixP->fx_line,
22554 _("the offset 0x%08lX is not representable"),
22555 (unsigned long) addend_abs);
22557 /* Extract the instruction. */
22558 insn = md_chars_to_number (buf, INSN_SIZE);
22560 /* If the addend is positive, use an ADD instruction.
22561 Otherwise use a SUB. Take care not to destroy the S bit. */
22562 insn &= 0xff1fffff;
22568 /* Place the encoded addend into the first 12 bits of the
22570 insn &= 0xfffff000;
22571 insn |= encoded_addend;
22573 /* Update the instruction. */
22574 md_number_to_chars (buf, insn, INSN_SIZE);
22578 case BFD_RELOC_ARM_LDR_PC_G0:
22579 case BFD_RELOC_ARM_LDR_PC_G1:
22580 case BFD_RELOC_ARM_LDR_PC_G2:
22581 case BFD_RELOC_ARM_LDR_SB_G0:
22582 case BFD_RELOC_ARM_LDR_SB_G1:
22583 case BFD_RELOC_ARM_LDR_SB_G2:
22584 gas_assert (!fixP->fx_done);
22585 if (!seg->use_rela_p)
22588 bfd_vma addend_abs = abs (value);
22590 /* Check that the absolute value of the addend can be
22591 encoded in 12 bits. */
22592 if (addend_abs >= 0x1000)
22593 as_bad_where (fixP->fx_file, fixP->fx_line,
22594 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22595 (unsigned long) addend_abs);
22597 /* Extract the instruction. */
22598 insn = md_chars_to_number (buf, INSN_SIZE);
22600 /* If the addend is negative, clear bit 23 of the instruction.
22601 Otherwise set it. */
22603 insn &= ~(1 << 23);
22607 /* Place the absolute value of the addend into the first 12 bits
22608 of the instruction. */
22609 insn &= 0xfffff000;
22610 insn |= addend_abs;
22612 /* Update the instruction. */
22613 md_number_to_chars (buf, insn, INSN_SIZE);
22617 case BFD_RELOC_ARM_LDRS_PC_G0:
22618 case BFD_RELOC_ARM_LDRS_PC_G1:
22619 case BFD_RELOC_ARM_LDRS_PC_G2:
22620 case BFD_RELOC_ARM_LDRS_SB_G0:
22621 case BFD_RELOC_ARM_LDRS_SB_G1:
22622 case BFD_RELOC_ARM_LDRS_SB_G2:
22623 gas_assert (!fixP->fx_done);
22624 if (!seg->use_rela_p)
22627 bfd_vma addend_abs = abs (value);
22629 /* Check that the absolute value of the addend can be
22630 encoded in 8 bits. */
22631 if (addend_abs >= 0x100)
22632 as_bad_where (fixP->fx_file, fixP->fx_line,
22633 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22634 (unsigned long) addend_abs);
22636 /* Extract the instruction. */
22637 insn = md_chars_to_number (buf, INSN_SIZE);
22639 /* If the addend is negative, clear bit 23 of the instruction.
22640 Otherwise set it. */
22642 insn &= ~(1 << 23);
22646 /* Place the first four bits of the absolute value of the addend
22647 into the first 4 bits of the instruction, and the remaining
22648 four into bits 8 .. 11. */
22649 insn &= 0xfffff0f0;
22650 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22652 /* Update the instruction. */
22653 md_number_to_chars (buf, insn, INSN_SIZE);
22657 case BFD_RELOC_ARM_LDC_PC_G0:
22658 case BFD_RELOC_ARM_LDC_PC_G1:
22659 case BFD_RELOC_ARM_LDC_PC_G2:
22660 case BFD_RELOC_ARM_LDC_SB_G0:
22661 case BFD_RELOC_ARM_LDC_SB_G1:
22662 case BFD_RELOC_ARM_LDC_SB_G2:
22663 gas_assert (!fixP->fx_done);
22664 if (!seg->use_rela_p)
22667 bfd_vma addend_abs = abs (value);
22669 /* Check that the absolute value of the addend is a multiple of
22670 four and, when divided by four, fits in 8 bits. */
22671 if (addend_abs & 0x3)
22672 as_bad_where (fixP->fx_file, fixP->fx_line,
22673 _("bad offset 0x%08lX (must be word-aligned)"),
22674 (unsigned long) addend_abs);
22676 if ((addend_abs >> 2) > 0xff)
22677 as_bad_where (fixP->fx_file, fixP->fx_line,
22678 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22679 (unsigned long) addend_abs);
22681 /* Extract the instruction. */
22682 insn = md_chars_to_number (buf, INSN_SIZE);
22684 /* If the addend is negative, clear bit 23 of the instruction.
22685 Otherwise set it. */
22687 insn &= ~(1 << 23);
22691 /* Place the addend (divided by four) into the first eight
22692 bits of the instruction. */
22693 insn &= 0xfffffff0;
22694 insn |= addend_abs >> 2;
22696 /* Update the instruction. */
22697 md_number_to_chars (buf, insn, INSN_SIZE);
22701 case BFD_RELOC_ARM_V4BX:
22702 /* This will need to go in the object file. */
22706 case BFD_RELOC_UNUSED:
22708 as_bad_where (fixP->fx_file, fixP->fx_line,
22709 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22713 /* Translate internal representation of relocation info to BFD target
22717 tc_gen_reloc (asection *section, fixS *fixp)
22720 bfd_reloc_code_real_type code;
22722 reloc = (arelent *) xmalloc (sizeof (arelent));
22724 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
22725 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22726 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
22728 if (fixp->fx_pcrel)
22730 if (section->use_rela_p)
22731 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22733 fixp->fx_offset = reloc->address;
22735 reloc->addend = fixp->fx_offset;
22737 switch (fixp->fx_r_type)
22740 if (fixp->fx_pcrel)
22742 code = BFD_RELOC_8_PCREL;
22747 if (fixp->fx_pcrel)
22749 code = BFD_RELOC_16_PCREL;
22754 if (fixp->fx_pcrel)
22756 code = BFD_RELOC_32_PCREL;
22760 case BFD_RELOC_ARM_MOVW:
22761 if (fixp->fx_pcrel)
22763 code = BFD_RELOC_ARM_MOVW_PCREL;
22767 case BFD_RELOC_ARM_MOVT:
22768 if (fixp->fx_pcrel)
22770 code = BFD_RELOC_ARM_MOVT_PCREL;
22774 case BFD_RELOC_ARM_THUMB_MOVW:
22775 if (fixp->fx_pcrel)
22777 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22781 case BFD_RELOC_ARM_THUMB_MOVT:
22782 if (fixp->fx_pcrel)
22784 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22788 case BFD_RELOC_NONE:
22789 case BFD_RELOC_ARM_PCREL_BRANCH:
22790 case BFD_RELOC_ARM_PCREL_BLX:
22791 case BFD_RELOC_RVA:
22792 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22793 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22794 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22795 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22796 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22797 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22798 case BFD_RELOC_VTABLE_ENTRY:
22799 case BFD_RELOC_VTABLE_INHERIT:
22801 case BFD_RELOC_32_SECREL:
22803 code = fixp->fx_r_type;
22806 case BFD_RELOC_THUMB_PCREL_BLX:
22808 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22809 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22812 code = BFD_RELOC_THUMB_PCREL_BLX;
22815 case BFD_RELOC_ARM_LITERAL:
22816 case BFD_RELOC_ARM_HWLITERAL:
22817 /* If this is called then the a literal has
22818 been referenced across a section boundary. */
22819 as_bad_where (fixp->fx_file, fixp->fx_line,
22820 _("literal referenced across section boundary"));
22824 case BFD_RELOC_ARM_TLS_CALL:
22825 case BFD_RELOC_ARM_THM_TLS_CALL:
22826 case BFD_RELOC_ARM_TLS_DESCSEQ:
22827 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22828 case BFD_RELOC_ARM_GOT32:
22829 case BFD_RELOC_ARM_GOTOFF:
22830 case BFD_RELOC_ARM_GOT_PREL:
22831 case BFD_RELOC_ARM_PLT32:
22832 case BFD_RELOC_ARM_TARGET1:
22833 case BFD_RELOC_ARM_ROSEGREL32:
22834 case BFD_RELOC_ARM_SBREL32:
22835 case BFD_RELOC_ARM_PREL31:
22836 case BFD_RELOC_ARM_TARGET2:
22837 case BFD_RELOC_ARM_TLS_LE32:
22838 case BFD_RELOC_ARM_TLS_LDO32:
22839 case BFD_RELOC_ARM_PCREL_CALL:
22840 case BFD_RELOC_ARM_PCREL_JUMP:
22841 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22842 case BFD_RELOC_ARM_ALU_PC_G0:
22843 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22844 case BFD_RELOC_ARM_ALU_PC_G1:
22845 case BFD_RELOC_ARM_ALU_PC_G2:
22846 case BFD_RELOC_ARM_LDR_PC_G0:
22847 case BFD_RELOC_ARM_LDR_PC_G1:
22848 case BFD_RELOC_ARM_LDR_PC_G2:
22849 case BFD_RELOC_ARM_LDRS_PC_G0:
22850 case BFD_RELOC_ARM_LDRS_PC_G1:
22851 case BFD_RELOC_ARM_LDRS_PC_G2:
22852 case BFD_RELOC_ARM_LDC_PC_G0:
22853 case BFD_RELOC_ARM_LDC_PC_G1:
22854 case BFD_RELOC_ARM_LDC_PC_G2:
22855 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22856 case BFD_RELOC_ARM_ALU_SB_G0:
22857 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22858 case BFD_RELOC_ARM_ALU_SB_G1:
22859 case BFD_RELOC_ARM_ALU_SB_G2:
22860 case BFD_RELOC_ARM_LDR_SB_G0:
22861 case BFD_RELOC_ARM_LDR_SB_G1:
22862 case BFD_RELOC_ARM_LDR_SB_G2:
22863 case BFD_RELOC_ARM_LDRS_SB_G0:
22864 case BFD_RELOC_ARM_LDRS_SB_G1:
22865 case BFD_RELOC_ARM_LDRS_SB_G2:
22866 case BFD_RELOC_ARM_LDC_SB_G0:
22867 case BFD_RELOC_ARM_LDC_SB_G1:
22868 case BFD_RELOC_ARM_LDC_SB_G2:
22869 case BFD_RELOC_ARM_V4BX:
22870 code = fixp->fx_r_type;
22873 case BFD_RELOC_ARM_TLS_GOTDESC:
22874 case BFD_RELOC_ARM_TLS_GD32:
22875 case BFD_RELOC_ARM_TLS_IE32:
22876 case BFD_RELOC_ARM_TLS_LDM32:
22877 /* BFD will include the symbol's address in the addend.
22878 But we don't want that, so subtract it out again here. */
22879 if (!S_IS_COMMON (fixp->fx_addsy))
22880 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22881 code = fixp->fx_r_type;
22885 case BFD_RELOC_ARM_IMMEDIATE:
22886 as_bad_where (fixp->fx_file, fixp->fx_line,
22887 _("internal relocation (type: IMMEDIATE) not fixed up"));
22890 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22891 as_bad_where (fixp->fx_file, fixp->fx_line,
22892 _("ADRL used for a symbol not defined in the same file"));
22895 case BFD_RELOC_ARM_OFFSET_IMM:
22896 if (section->use_rela_p)
22898 code = fixp->fx_r_type;
22902 if (fixp->fx_addsy != NULL
22903 && !S_IS_DEFINED (fixp->fx_addsy)
22904 && S_IS_LOCAL (fixp->fx_addsy))
22906 as_bad_where (fixp->fx_file, fixp->fx_line,
22907 _("undefined local label `%s'"),
22908 S_GET_NAME (fixp->fx_addsy));
22912 as_bad_where (fixp->fx_file, fixp->fx_line,
22913 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22920 switch (fixp->fx_r_type)
22922 case BFD_RELOC_NONE: type = "NONE"; break;
22923 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22924 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22925 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22926 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22927 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22928 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22929 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22930 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22931 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22932 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22933 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22934 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22935 default: type = _("<unknown>"); break;
22937 as_bad_where (fixp->fx_file, fixp->fx_line,
22938 _("cannot represent %s relocation in this object file format"),
22945 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22947 && fixp->fx_addsy == GOT_symbol)
22949 code = BFD_RELOC_ARM_GOTPC;
22950 reloc->addend = fixp->fx_offset = reloc->address;
22954 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22956 if (reloc->howto == NULL)
22958 as_bad_where (fixp->fx_file, fixp->fx_line,
22959 _("cannot represent %s relocation in this object file format"),
22960 bfd_get_reloc_code_name (code));
22964 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22965 vtable entry to be used in the relocation's section offset. */
22966 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22967 reloc->address = fixp->fx_offset;
22972 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22975 cons_fix_new_arm (fragS * frag,
22980 bfd_reloc_code_real_type type;
22984 FIXME: @@ Should look at CPU word size. */
22988 type = BFD_RELOC_8;
22991 type = BFD_RELOC_16;
22995 type = BFD_RELOC_32;
22998 type = BFD_RELOC_64;
23003 if (exp->X_op == O_secrel)
23005 exp->X_op = O_symbol;
23006 type = BFD_RELOC_32_SECREL;
23010 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
23013 #if defined (OBJ_COFF)
23015 arm_validate_fix (fixS * fixP)
23017 /* If the destination of the branch is a defined symbol which does not have
23018 the THUMB_FUNC attribute, then we must be calling a function which has
23019 the (interfacearm) attribute. We look for the Thumb entry point to that
23020 function and change the branch to refer to that function instead. */
23021 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
23022 && fixP->fx_addsy != NULL
23023 && S_IS_DEFINED (fixP->fx_addsy)
23024 && ! THUMB_IS_FUNC (fixP->fx_addsy))
23026 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
23033 arm_force_relocation (struct fix * fixp)
23035 #if defined (OBJ_COFF) && defined (TE_PE)
23036 if (fixp->fx_r_type == BFD_RELOC_RVA)
23040 /* In case we have a call or a branch to a function in ARM ISA mode from
23041 a thumb function or vice-versa force the relocation. These relocations
23042 are cleared off for some cores that might have blx and simple transformations
23046 switch (fixp->fx_r_type)
23048 case BFD_RELOC_ARM_PCREL_JUMP:
23049 case BFD_RELOC_ARM_PCREL_CALL:
23050 case BFD_RELOC_THUMB_PCREL_BLX:
23051 if (THUMB_IS_FUNC (fixp->fx_addsy))
23055 case BFD_RELOC_ARM_PCREL_BLX:
23056 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23057 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23058 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23059 if (ARM_IS_FUNC (fixp->fx_addsy))
23068 /* Resolve these relocations even if the symbol is extern or weak.
23069 Technically this is probably wrong due to symbol preemption.
23070 In practice these relocations do not have enough range to be useful
23071 at dynamic link time, and some code (e.g. in the Linux kernel)
23072 expects these references to be resolved. */
23073 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
23074 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
23075 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
23076 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
23077 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23078 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
23079 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
23080 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
23081 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23082 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
23083 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
23084 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
23085 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
23086 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
23089 /* Always leave these relocations for the linker. */
23090 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23091 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23092 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23095 /* Always generate relocations against function symbols. */
23096 if (fixp->fx_r_type == BFD_RELOC_32
23098 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
23101 return generic_force_reloc (fixp);
23104 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23105 /* Relocations against function names must be left unadjusted,
23106 so that the linker can use this information to generate interworking
23107 stubs. The MIPS version of this function
23108 also prevents relocations that are mips-16 specific, but I do not
23109 know why it does this.
23112 There is one other problem that ought to be addressed here, but
23113 which currently is not: Taking the address of a label (rather
23114 than a function) and then later jumping to that address. Such
23115 addresses also ought to have their bottom bit set (assuming that
23116 they reside in Thumb code), but at the moment they will not. */
23119 arm_fix_adjustable (fixS * fixP)
23121 if (fixP->fx_addsy == NULL)
23124 /* Preserve relocations against symbols with function type. */
23125 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
23128 if (THUMB_IS_FUNC (fixP->fx_addsy)
23129 && fixP->fx_subsy == NULL)
23132 /* We need the symbol name for the VTABLE entries. */
23133 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23134 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23137 /* Don't allow symbols to be discarded on GOT related relocs. */
23138 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23139 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23140 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23141 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23142 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23143 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23144 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23145 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
23146 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23147 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23148 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23149 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23150 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
23151 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
23154 /* Similarly for group relocations. */
23155 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23156 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23157 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23160 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23161 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23162 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23163 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23164 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23165 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23166 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23167 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23168 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
23173 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23178 elf32_arm_target_format (void)
23181 return (target_big_endian
23182 ? "elf32-bigarm-symbian"
23183 : "elf32-littlearm-symbian");
23184 #elif defined (TE_VXWORKS)
23185 return (target_big_endian
23186 ? "elf32-bigarm-vxworks"
23187 : "elf32-littlearm-vxworks");
23188 #elif defined (TE_NACL)
23189 return (target_big_endian
23190 ? "elf32-bigarm-nacl"
23191 : "elf32-littlearm-nacl");
23193 if (target_big_endian)
23194 return "elf32-bigarm";
23196 return "elf32-littlearm";
23201 armelf_frob_symbol (symbolS * symp,
23204 elf_frob_symbol (symp, puntp);
23208 /* MD interface: Finalization. */
23213 literal_pool * pool;
23215 /* Ensure that all the IT blocks are properly closed. */
23216 check_it_blocks_finished ();
23218 for (pool = list_of_pools; pool; pool = pool->next)
23220 /* Put it at the end of the relevant section. */
23221 subseg_set (pool->section, pool->sub_section);
23223 arm_elf_change_section ();
23230 /* Remove any excess mapping symbols generated for alignment frags in
23231 SEC. We may have created a mapping symbol before a zero byte
23232 alignment; remove it if there's a mapping symbol after the
23235 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23236 void *dummy ATTRIBUTE_UNUSED)
23238 segment_info_type *seginfo = seg_info (sec);
23241 if (seginfo == NULL || seginfo->frchainP == NULL)
23244 for (fragp = seginfo->frchainP->frch_root;
23246 fragp = fragp->fr_next)
23248 symbolS *sym = fragp->tc_frag_data.last_map;
23249 fragS *next = fragp->fr_next;
23251 /* Variable-sized frags have been converted to fixed size by
23252 this point. But if this was variable-sized to start with,
23253 there will be a fixed-size frag after it. So don't handle
23255 if (sym == NULL || next == NULL)
23258 if (S_GET_VALUE (sym) < next->fr_address)
23259 /* Not at the end of this frag. */
23261 know (S_GET_VALUE (sym) == next->fr_address);
23265 if (next->tc_frag_data.first_map != NULL)
23267 /* Next frag starts with a mapping symbol. Discard this
23269 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23273 if (next->fr_next == NULL)
23275 /* This mapping symbol is at the end of the section. Discard
23277 know (next->fr_fix == 0 && next->fr_var == 0);
23278 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23282 /* As long as we have empty frags without any mapping symbols,
23284 /* If the next frag is non-empty and does not start with a
23285 mapping symbol, then this mapping symbol is required. */
23286 if (next->fr_address != next->fr_next->fr_address)
23289 next = next->fr_next;
23291 while (next != NULL);
23296 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23300 arm_adjust_symtab (void)
23305 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23307 if (ARM_IS_THUMB (sym))
23309 if (THUMB_IS_FUNC (sym))
23311 /* Mark the symbol as a Thumb function. */
23312 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23313 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23314 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
23316 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23317 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23319 as_bad (_("%s: unexpected function type: %d"),
23320 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23322 else switch (S_GET_STORAGE_CLASS (sym))
23325 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23328 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23331 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23339 if (ARM_IS_INTERWORK (sym))
23340 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
23347 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23349 if (ARM_IS_THUMB (sym))
23351 elf_symbol_type * elf_sym;
23353 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23354 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
23356 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23357 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
23359 /* If it's a .thumb_func, declare it as so,
23360 otherwise tag label as .code 16. */
23361 if (THUMB_IS_FUNC (sym))
23362 elf_sym->internal_elf_sym.st_target_internal
23363 = ST_BRANCH_TO_THUMB;
23364 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23365 elf_sym->internal_elf_sym.st_info =
23366 ELF_ST_INFO (bind, STT_ARM_16BIT);
23371 /* Remove any overlapping mapping symbols generated by alignment frags. */
23372 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
23373 /* Now do generic ELF adjustments. */
23374 elf_adjust_symtab ();
23378 /* MD interface: Initialization. */
23381 set_constant_flonums (void)
23385 for (i = 0; i < NUM_FLOAT_VALS; i++)
23386 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23390 /* Auto-select Thumb mode if it's the only available instruction set for the
23391 given architecture. */
23394 autoselect_thumb_from_cpu_variant (void)
23396 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23397 opcode_select (16);
23406 if ( (arm_ops_hsh = hash_new ()) == NULL
23407 || (arm_cond_hsh = hash_new ()) == NULL
23408 || (arm_shift_hsh = hash_new ()) == NULL
23409 || (arm_psr_hsh = hash_new ()) == NULL
23410 || (arm_v7m_psr_hsh = hash_new ()) == NULL
23411 || (arm_reg_hsh = hash_new ()) == NULL
23412 || (arm_reloc_hsh = hash_new ()) == NULL
23413 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
23414 as_fatal (_("virtual memory exhausted"));
23416 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
23417 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
23418 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
23419 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
23420 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
23421 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
23422 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
23423 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
23424 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
23425 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
23426 (void *) (v7m_psrs + i));
23427 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
23428 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
23430 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23432 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
23433 (void *) (barrier_opt_names + i));
23435 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23437 struct reloc_entry * entry = reloc_names + i;
23439 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23440 /* This makes encode_branch() use the EABI versions of this relocation. */
23441 entry->reloc = BFD_RELOC_UNUSED;
23443 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23447 set_constant_flonums ();
23449 /* Set the cpu variant based on the command-line options. We prefer
23450 -mcpu= over -march= if both are set (as for GCC); and we prefer
23451 -mfpu= over any other way of setting the floating point unit.
23452 Use of legacy options with new options are faulted. */
23455 if (mcpu_cpu_opt || march_cpu_opt)
23456 as_bad (_("use of old and new-style options to set CPU type"));
23458 mcpu_cpu_opt = legacy_cpu;
23460 else if (!mcpu_cpu_opt)
23461 mcpu_cpu_opt = march_cpu_opt;
23466 as_bad (_("use of old and new-style options to set FPU type"));
23468 mfpu_opt = legacy_fpu;
23470 else if (!mfpu_opt)
23472 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23473 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23474 /* Some environments specify a default FPU. If they don't, infer it
23475 from the processor. */
23477 mfpu_opt = mcpu_fpu_opt;
23479 mfpu_opt = march_fpu_opt;
23481 mfpu_opt = &fpu_default;
23487 if (mcpu_cpu_opt != NULL)
23488 mfpu_opt = &fpu_default;
23489 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
23490 mfpu_opt = &fpu_arch_vfp_v2;
23492 mfpu_opt = &fpu_arch_fpa;
23498 mcpu_cpu_opt = &cpu_default;
23499 selected_cpu = cpu_default;
23503 selected_cpu = *mcpu_cpu_opt;
23505 mcpu_cpu_opt = &arm_arch_any;
23508 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23510 autoselect_thumb_from_cpu_variant ();
23512 arm_arch_used = thumb_arch_used = arm_arch_none;
23514 #if defined OBJ_COFF || defined OBJ_ELF
23516 unsigned int flags = 0;
23518 #if defined OBJ_ELF
23519 flags = meabi_flags;
23521 switch (meabi_flags)
23523 case EF_ARM_EABI_UNKNOWN:
23525 /* Set the flags in the private structure. */
23526 if (uses_apcs_26) flags |= F_APCS26;
23527 if (support_interwork) flags |= F_INTERWORK;
23528 if (uses_apcs_float) flags |= F_APCS_FLOAT;
23529 if (pic_code) flags |= F_PIC;
23530 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
23531 flags |= F_SOFT_FLOAT;
23533 switch (mfloat_abi_opt)
23535 case ARM_FLOAT_ABI_SOFT:
23536 case ARM_FLOAT_ABI_SOFTFP:
23537 flags |= F_SOFT_FLOAT;
23540 case ARM_FLOAT_ABI_HARD:
23541 if (flags & F_SOFT_FLOAT)
23542 as_bad (_("hard-float conflicts with specified fpu"));
23546 /* Using pure-endian doubles (even if soft-float). */
23547 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
23548 flags |= F_VFP_FLOAT;
23550 #if defined OBJ_ELF
23551 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
23552 flags |= EF_ARM_MAVERICK_FLOAT;
23555 case EF_ARM_EABI_VER4:
23556 case EF_ARM_EABI_VER5:
23557 /* No additional flags to set. */
23564 bfd_set_private_flags (stdoutput, flags);
23566 /* We have run out flags in the COFF header to encode the
23567 status of ATPCS support, so instead we create a dummy,
23568 empty, debug section called .arm.atpcs. */
23573 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23577 bfd_set_section_flags
23578 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23579 bfd_set_section_size (stdoutput, sec, 0);
23580 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23586 /* Record the CPU type as well. */
23587 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23588 mach = bfd_mach_arm_iWMMXt2;
23589 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
23590 mach = bfd_mach_arm_iWMMXt;
23591 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
23592 mach = bfd_mach_arm_XScale;
23593 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
23594 mach = bfd_mach_arm_ep9312;
23595 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
23596 mach = bfd_mach_arm_5TE;
23597 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
23599 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23600 mach = bfd_mach_arm_5T;
23602 mach = bfd_mach_arm_5;
23604 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
23606 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23607 mach = bfd_mach_arm_4T;
23609 mach = bfd_mach_arm_4;
23611 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
23612 mach = bfd_mach_arm_3M;
23613 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23614 mach = bfd_mach_arm_3;
23615 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23616 mach = bfd_mach_arm_2a;
23617 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23618 mach = bfd_mach_arm_2;
23620 mach = bfd_mach_arm_unknown;
23622 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23625 /* Command line processing. */
23628 Invocation line includes a switch not recognized by the base assembler.
23629 See if it's a processor-specific option.
23631 This routine is somewhat complicated by the need for backwards
23632 compatibility (since older releases of gcc can't be changed).
23633 The new options try to make the interface as compatible as
23636 New options (supported) are:
23638 -mcpu=<cpu name> Assemble for selected processor
23639 -march=<architecture name> Assemble for selected architecture
23640 -mfpu=<fpu architecture> Assemble for selected FPU.
23641 -EB/-mbig-endian Big-endian
23642 -EL/-mlittle-endian Little-endian
23643 -k Generate PIC code
23644 -mthumb Start in Thumb mode
23645 -mthumb-interwork Code supports ARM/Thumb interworking
23647 -m[no-]warn-deprecated Warn about deprecated features
23649 For now we will also provide support for:
23651 -mapcs-32 32-bit Program counter
23652 -mapcs-26 26-bit Program counter
23653 -macps-float Floats passed in FP registers
23654 -mapcs-reentrant Reentrant code
23656 (sometime these will probably be replaced with -mapcs=<list of options>
23657 and -matpcs=<list of options>)
23659 The remaining options are only supported for back-wards compatibility.
23660 Cpu variants, the arm part is optional:
23661 -m[arm]1 Currently not supported.
23662 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23663 -m[arm]3 Arm 3 processor
23664 -m[arm]6[xx], Arm 6 processors
23665 -m[arm]7[xx][t][[d]m] Arm 7 processors
23666 -m[arm]8[10] Arm 8 processors
23667 -m[arm]9[20][tdmi] Arm 9 processors
23668 -mstrongarm[110[0]] StrongARM processors
23669 -mxscale XScale processors
23670 -m[arm]v[2345[t[e]]] Arm architectures
23671 -mall All (except the ARM1)
23673 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23674 -mfpe-old (No float load/store multiples)
23675 -mvfpxd VFP Single precision
23677 -mno-fpu Disable all floating point instructions
23679 The following CPU names are recognized:
23680 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23681 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23682 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23683 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23684 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23685 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23686 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23690 const char * md_shortopts = "m:k";
23692 #ifdef ARM_BI_ENDIAN
23693 #define OPTION_EB (OPTION_MD_BASE + 0)
23694 #define OPTION_EL (OPTION_MD_BASE + 1)
23696 #if TARGET_BYTES_BIG_ENDIAN
23697 #define OPTION_EB (OPTION_MD_BASE + 0)
23699 #define OPTION_EL (OPTION_MD_BASE + 1)
23702 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23704 struct option md_longopts[] =
23707 {"EB", no_argument, NULL, OPTION_EB},
23710 {"EL", no_argument, NULL, OPTION_EL},
23712 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
23713 {NULL, no_argument, NULL, 0}
23716 size_t md_longopts_size = sizeof (md_longopts);
23718 struct arm_option_table
23720 char *option; /* Option name to match. */
23721 char *help; /* Help information. */
23722 int *var; /* Variable to change. */
23723 int value; /* What to change it to. */
23724 char *deprecated; /* If non-null, print this message. */
23727 struct arm_option_table arm_opts[] =
23729 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23730 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23731 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23732 &support_interwork, 1, NULL},
23733 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23734 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23735 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23737 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23738 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23739 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23740 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23743 /* These are recognized by the assembler, but have no affect on code. */
23744 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23745 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
23747 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23748 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23749 &warn_on_deprecated, 0, NULL},
23750 {NULL, NULL, NULL, 0, NULL}
23753 struct arm_legacy_option_table
23755 char *option; /* Option name to match. */
23756 const arm_feature_set **var; /* Variable to change. */
23757 const arm_feature_set value; /* What to change it to. */
23758 char *deprecated; /* If non-null, print this message. */
23761 const struct arm_legacy_option_table arm_legacy_opts[] =
23763 /* DON'T add any new processors to this list -- we want the whole list
23764 to go away... Add them to the processors table instead. */
23765 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23766 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23767 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23768 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23769 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23770 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23771 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23772 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23773 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23774 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23775 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23776 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23777 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23778 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23779 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23780 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23781 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23782 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23783 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23784 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23785 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23786 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23787 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23788 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23789 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23790 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23791 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23792 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23793 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23794 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23795 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23796 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23797 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23798 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23799 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23800 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23801 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23802 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23803 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23804 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23805 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23806 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23807 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23808 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23809 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23810 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23811 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23812 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23813 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23814 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23815 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23816 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23817 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23818 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23819 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23820 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23821 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23822 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23823 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23824 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23825 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23826 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23827 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23828 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23829 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23830 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23831 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23832 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23833 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23834 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23835 N_("use -mcpu=strongarm110")},
23836 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23837 N_("use -mcpu=strongarm1100")},
23838 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23839 N_("use -mcpu=strongarm1110")},
23840 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23841 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23842 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23844 /* Architecture variants -- don't add any more to this list either. */
23845 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23846 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23847 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23848 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23849 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23850 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23851 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23852 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23853 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23854 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23855 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23856 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23857 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23858 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23859 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23860 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23861 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23862 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23864 /* Floating point variants -- don't add any more to this list either. */
23865 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23866 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23867 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23868 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23869 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23871 {NULL, NULL, ARM_ARCH_NONE, NULL}
23874 struct arm_cpu_option_table
23878 const arm_feature_set value;
23879 /* For some CPUs we assume an FPU unless the user explicitly sets
23881 const arm_feature_set default_fpu;
23882 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23884 const char *canonical_name;
23887 /* This list should, at a minimum, contain all the cpu names
23888 recognized by GCC. */
23889 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23890 static const struct arm_cpu_option_table arm_cpus[] =
23892 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23893 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23894 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23895 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23896 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23897 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23898 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23899 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23900 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23901 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23902 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23903 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23904 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23905 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23906 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23907 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23908 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23909 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23910 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23911 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23912 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23913 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23914 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23915 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23916 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23917 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23918 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23919 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23920 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23921 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23922 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23923 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23924 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23925 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23926 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23927 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23928 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23929 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23930 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23931 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23932 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23933 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23934 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23935 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23936 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23937 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23938 /* For V5 or later processors we default to using VFP; but the user
23939 should really set the FPU type explicitly. */
23940 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23941 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23942 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23943 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23944 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23945 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23946 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23947 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23948 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23949 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23950 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23951 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23952 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23953 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23954 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23955 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23956 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23957 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23958 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23959 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23961 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23962 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23963 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23964 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23965 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23966 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23967 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23968 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23969 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23971 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23972 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23973 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23974 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23975 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23976 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23977 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23978 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23979 FPU_NONE, "Cortex-A5"),
23980 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23981 FPU_ARCH_NEON_VFP_V4,
23983 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23984 ARM_FEATURE (0, FPU_VFP_V3
23985 | FPU_NEON_EXT_V1),
23987 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23988 ARM_FEATURE (0, FPU_VFP_V3
23989 | FPU_NEON_EXT_V1),
23991 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23992 FPU_ARCH_NEON_VFP_V4,
23994 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23996 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23998 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23999 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
24001 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
24002 FPU_NONE, "Cortex-R5"),
24003 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
24004 FPU_ARCH_VFP_V3D16,
24006 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
24007 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
24008 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
24009 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
24010 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
24011 /* ??? XSCALE is really an architecture. */
24012 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24013 /* ??? iwmmxt is not a processor. */
24014 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
24015 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
24016 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24018 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
24019 FPU_ARCH_MAVERICK, "ARM920T"),
24020 /* Marvell processors. */
24021 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0),
24022 FPU_ARCH_VFP_V3D16, NULL),
24024 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
24028 struct arm_arch_option_table
24032 const arm_feature_set value;
24033 const arm_feature_set default_fpu;
24036 /* This list should, at a minimum, contain all the architecture names
24037 recognized by GCC. */
24038 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24039 static const struct arm_arch_option_table arm_archs[] =
24041 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
24042 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
24043 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
24044 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
24045 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
24046 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
24047 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
24048 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
24049 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
24050 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
24051 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
24052 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
24053 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
24054 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
24055 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
24056 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
24057 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
24058 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
24059 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
24060 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
24061 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
24062 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
24063 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
24064 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
24065 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
24066 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
24067 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
24068 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
24069 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
24070 /* The official spelling of the ARMv7 profile variants is the dashed form.
24071 Accept the non-dashed form for compatibility with old toolchains. */
24072 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24073 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24074 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24075 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24076 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24077 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24078 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
24079 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
24080 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
24081 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
24082 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
24083 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24085 #undef ARM_ARCH_OPT
24087 /* ISA extensions in the co-processor and main instruction set space. */
24088 struct arm_option_extension_value_table
24092 const arm_feature_set value;
24093 const arm_feature_set allowed_archs;
24096 /* The following table must be in alphabetical order with a NULL last entry.
24098 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
24099 static const struct arm_option_extension_value_table arm_extensions[] =
24101 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (ARM_EXT_V8, 0)),
24102 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24103 ARM_FEATURE (ARM_EXT_V8, 0)),
24104 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
24105 ARM_FEATURE (ARM_EXT_V8, 0)),
24106 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
24107 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24108 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
24109 ARM_EXT_OPT ("iwmmxt2",
24110 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
24111 ARM_EXT_OPT ("maverick",
24112 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
24113 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
24114 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24115 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
24116 ARM_FEATURE (ARM_EXT_V8, 0)),
24117 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
24118 ARM_FEATURE (ARM_EXT_V6M, 0)),
24119 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
24120 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
24121 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
24123 ARM_FEATURE (ARM_EXT_V7A, 0)),
24124 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24125 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24129 /* ISA floating-point and Advanced SIMD extensions. */
24130 struct arm_option_fpu_value_table
24133 const arm_feature_set value;
24136 /* This list should, at a minimum, contain all the fpu names
24137 recognized by GCC. */
24138 static const struct arm_option_fpu_value_table arm_fpus[] =
24140 {"softfpa", FPU_NONE},
24141 {"fpe", FPU_ARCH_FPE},
24142 {"fpe2", FPU_ARCH_FPE},
24143 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24144 {"fpa", FPU_ARCH_FPA},
24145 {"fpa10", FPU_ARCH_FPA},
24146 {"fpa11", FPU_ARCH_FPA},
24147 {"arm7500fe", FPU_ARCH_FPA},
24148 {"softvfp", FPU_ARCH_VFP},
24149 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24150 {"vfp", FPU_ARCH_VFP_V2},
24151 {"vfp9", FPU_ARCH_VFP_V2},
24152 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
24153 {"vfp10", FPU_ARCH_VFP_V2},
24154 {"vfp10-r0", FPU_ARCH_VFP_V1},
24155 {"vfpxd", FPU_ARCH_VFP_V1xD},
24156 {"vfpv2", FPU_ARCH_VFP_V2},
24157 {"vfpv3", FPU_ARCH_VFP_V3},
24158 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
24159 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
24160 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24161 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24162 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
24163 {"arm1020t", FPU_ARCH_VFP_V1},
24164 {"arm1020e", FPU_ARCH_VFP_V2},
24165 {"arm1136jfs", FPU_ARCH_VFP_V2},
24166 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24167 {"maverick", FPU_ARCH_MAVERICK},
24168 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
24169 {"neon-fp16", FPU_ARCH_NEON_FP16},
24170 {"vfpv4", FPU_ARCH_VFP_V4},
24171 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
24172 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
24173 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
24174 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24175 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24176 {"crypto-neon-fp-armv8",
24177 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
24178 {NULL, ARM_ARCH_NONE}
24181 struct arm_option_value_table
24187 static const struct arm_option_value_table arm_float_abis[] =
24189 {"hard", ARM_FLOAT_ABI_HARD},
24190 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24191 {"soft", ARM_FLOAT_ABI_SOFT},
24196 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24197 static const struct arm_option_value_table arm_eabis[] =
24199 {"gnu", EF_ARM_EABI_UNKNOWN},
24200 {"4", EF_ARM_EABI_VER4},
24201 {"5", EF_ARM_EABI_VER5},
24206 struct arm_long_option_table
24208 char * option; /* Substring to match. */
24209 char * help; /* Help information. */
24210 int (* func) (char * subopt); /* Function to decode sub-option. */
24211 char * deprecated; /* If non-null, print this message. */
24215 arm_parse_extension (char *str, const arm_feature_set **opt_p)
24217 arm_feature_set *ext_set = (arm_feature_set *)
24218 xmalloc (sizeof (arm_feature_set));
24220 /* We insist on extensions being specified in alphabetical order, and with
24221 extensions being added before being removed. We achieve this by having
24222 the global ARM_EXTENSIONS table in alphabetical order, and using the
24223 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24224 or removing it (0) and only allowing it to change in the order
24226 const struct arm_option_extension_value_table * opt = NULL;
24227 int adding_value = -1;
24229 /* Copy the feature set, so that we can modify it. */
24230 *ext_set = **opt_p;
24233 while (str != NULL && *str != 0)
24240 as_bad (_("invalid architectural extension"));
24245 ext = strchr (str, '+');
24250 len = strlen (str);
24252 if (len >= 2 && strncmp (str, "no", 2) == 0)
24254 if (adding_value != 0)
24257 opt = arm_extensions;
24265 if (adding_value == -1)
24268 opt = arm_extensions;
24270 else if (adding_value != 1)
24272 as_bad (_("must specify extensions to add before specifying "
24273 "those to remove"));
24280 as_bad (_("missing architectural extension"));
24284 gas_assert (adding_value != -1);
24285 gas_assert (opt != NULL);
24287 /* Scan over the options table trying to find an exact match. */
24288 for (; opt->name != NULL; opt++)
24289 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24291 /* Check we can apply the extension to this architecture. */
24292 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24294 as_bad (_("extension does not apply to the base architecture"));
24298 /* Add or remove the extension. */
24300 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
24302 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
24307 if (opt->name == NULL)
24309 /* Did we fail to find an extension because it wasn't specified in
24310 alphabetical order, or because it does not exist? */
24312 for (opt = arm_extensions; opt->name != NULL; opt++)
24313 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24316 if (opt->name == NULL)
24317 as_bad (_("unknown architectural extension `%s'"), str);
24319 as_bad (_("architectural extensions must be specified in "
24320 "alphabetical order"));
24326 /* We should skip the extension we've just matched the next time
24338 arm_parse_cpu (char *str)
24340 const struct arm_cpu_option_table *opt;
24341 char *ext = strchr (str, '+');
24347 len = strlen (str);
24351 as_bad (_("missing cpu name `%s'"), str);
24355 for (opt = arm_cpus; opt->name != NULL; opt++)
24356 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24358 mcpu_cpu_opt = &opt->value;
24359 mcpu_fpu_opt = &opt->default_fpu;
24360 if (opt->canonical_name)
24361 strcpy (selected_cpu_name, opt->canonical_name);
24366 for (i = 0; i < len; i++)
24367 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24368 selected_cpu_name[i] = 0;
24372 return arm_parse_extension (ext, &mcpu_cpu_opt);
24377 as_bad (_("unknown cpu `%s'"), str);
24382 arm_parse_arch (char *str)
24384 const struct arm_arch_option_table *opt;
24385 char *ext = strchr (str, '+');
24391 len = strlen (str);
24395 as_bad (_("missing architecture name `%s'"), str);
24399 for (opt = arm_archs; opt->name != NULL; opt++)
24400 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24402 march_cpu_opt = &opt->value;
24403 march_fpu_opt = &opt->default_fpu;
24404 strcpy (selected_cpu_name, opt->name);
24407 return arm_parse_extension (ext, &march_cpu_opt);
24412 as_bad (_("unknown architecture `%s'\n"), str);
24417 arm_parse_fpu (char * str)
24419 const struct arm_option_fpu_value_table * opt;
24421 for (opt = arm_fpus; opt->name != NULL; opt++)
24422 if (streq (opt->name, str))
24424 mfpu_opt = &opt->value;
24428 as_bad (_("unknown floating point format `%s'\n"), str);
24433 arm_parse_float_abi (char * str)
24435 const struct arm_option_value_table * opt;
24437 for (opt = arm_float_abis; opt->name != NULL; opt++)
24438 if (streq (opt->name, str))
24440 mfloat_abi_opt = opt->value;
24444 as_bad (_("unknown floating point abi `%s'\n"), str);
24450 arm_parse_eabi (char * str)
24452 const struct arm_option_value_table *opt;
24454 for (opt = arm_eabis; opt->name != NULL; opt++)
24455 if (streq (opt->name, str))
24457 meabi_flags = opt->value;
24460 as_bad (_("unknown EABI `%s'\n"), str);
24466 arm_parse_it_mode (char * str)
24468 bfd_boolean ret = TRUE;
24470 if (streq ("arm", str))
24471 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24472 else if (streq ("thumb", str))
24473 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24474 else if (streq ("always", str))
24475 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24476 else if (streq ("never", str))
24477 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24480 as_bad (_("unknown implicit IT mode `%s', should be "\
24481 "arm, thumb, always, or never."), str);
24488 struct arm_long_option_table arm_long_opts[] =
24490 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24491 arm_parse_cpu, NULL},
24492 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24493 arm_parse_arch, NULL},
24494 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24495 arm_parse_fpu, NULL},
24496 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24497 arm_parse_float_abi, NULL},
24499 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24500 arm_parse_eabi, NULL},
24502 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24503 arm_parse_it_mode, NULL},
24504 {NULL, NULL, 0, NULL}
24508 md_parse_option (int c, char * arg)
24510 struct arm_option_table *opt;
24511 const struct arm_legacy_option_table *fopt;
24512 struct arm_long_option_table *lopt;
24518 target_big_endian = 1;
24524 target_big_endian = 0;
24528 case OPTION_FIX_V4BX:
24533 /* Listing option. Just ignore these, we don't support additional
24538 for (opt = arm_opts; opt->option != NULL; opt++)
24540 if (c == opt->option[0]
24541 && ((arg == NULL && opt->option[1] == 0)
24542 || streq (arg, opt->option + 1)))
24544 /* If the option is deprecated, tell the user. */
24545 if (warn_on_deprecated && opt->deprecated != NULL)
24546 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24547 arg ? arg : "", _(opt->deprecated));
24549 if (opt->var != NULL)
24550 *opt->var = opt->value;
24556 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
24558 if (c == fopt->option[0]
24559 && ((arg == NULL && fopt->option[1] == 0)
24560 || streq (arg, fopt->option + 1)))
24562 /* If the option is deprecated, tell the user. */
24563 if (warn_on_deprecated && fopt->deprecated != NULL)
24564 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24565 arg ? arg : "", _(fopt->deprecated));
24567 if (fopt->var != NULL)
24568 *fopt->var = &fopt->value;
24574 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24576 /* These options are expected to have an argument. */
24577 if (c == lopt->option[0]
24579 && strncmp (arg, lopt->option + 1,
24580 strlen (lopt->option + 1)) == 0)
24582 /* If the option is deprecated, tell the user. */
24583 if (warn_on_deprecated && lopt->deprecated != NULL)
24584 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24585 _(lopt->deprecated));
24587 /* Call the sup-option parser. */
24588 return lopt->func (arg + strlen (lopt->option) - 1);
24599 md_show_usage (FILE * fp)
24601 struct arm_option_table *opt;
24602 struct arm_long_option_table *lopt;
24604 fprintf (fp, _(" ARM-specific assembler options:\n"));
24606 for (opt = arm_opts; opt->option != NULL; opt++)
24607 if (opt->help != NULL)
24608 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
24610 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24611 if (lopt->help != NULL)
24612 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
24616 -EB assemble code for a big-endian cpu\n"));
24621 -EL assemble code for a little-endian cpu\n"));
24625 --fix-v4bx Allow BX in ARMv4 code\n"));
24633 arm_feature_set flags;
24634 } cpu_arch_ver_table;
24636 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24637 least features first. */
24638 static const cpu_arch_ver_table cpu_arch_ver[] =
24644 {4, ARM_ARCH_V5TE},
24645 {5, ARM_ARCH_V5TEJ},
24649 {11, ARM_ARCH_V6M},
24650 {12, ARM_ARCH_V6SM},
24651 {8, ARM_ARCH_V6T2},
24652 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
24653 {10, ARM_ARCH_V7R},
24654 {10, ARM_ARCH_V7M},
24655 {14, ARM_ARCH_V8A},
24659 /* Set an attribute if it has not already been set by the user. */
24661 aeabi_set_attribute_int (int tag, int value)
24664 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24665 || !attributes_set_explicitly[tag])
24666 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24670 aeabi_set_attribute_string (int tag, const char *value)
24673 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24674 || !attributes_set_explicitly[tag])
24675 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24678 /* Set the public EABI object attributes. */
24680 aeabi_set_public_attributes (void)
24685 int fp16_optional = 0;
24686 arm_feature_set flags;
24687 arm_feature_set tmp;
24688 const cpu_arch_ver_table *p;
24690 /* Choose the architecture based on the capabilities of the requested cpu
24691 (if any) and/or the instructions actually used. */
24692 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24693 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24694 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
24696 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24697 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24699 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24700 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24702 /* Allow the user to override the reported architecture. */
24705 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24706 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24709 /* We need to make sure that the attributes do not identify us as v6S-M
24710 when the only v6S-M feature in use is the Operating System Extensions. */
24711 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24712 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
24713 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
24717 for (p = cpu_arch_ver; p->val; p++)
24719 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24722 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24726 /* The table lookup above finds the last architecture to contribute
24727 a new feature. Unfortunately, Tag13 is a subset of the union of
24728 v6T2 and v7-M, so it is never seen as contributing a new feature.
24729 We can not search for the last entry which is entirely used,
24730 because if no CPU is specified we build up only those flags
24731 actually used. Perhaps we should separate out the specified
24732 and implicit cases. Avoid taking this path for -march=all by
24733 checking for contradictory v7-A / v7-M features. */
24735 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24736 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24737 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24740 /* Tag_CPU_name. */
24741 if (selected_cpu_name[0])
24745 q = selected_cpu_name;
24746 if (strncmp (q, "armv", 4) == 0)
24751 for (i = 0; q[i]; i++)
24752 q[i] = TOUPPER (q[i]);
24754 aeabi_set_attribute_string (Tag_CPU_name, q);
24757 /* Tag_CPU_arch. */
24758 aeabi_set_attribute_int (Tag_CPU_arch, arch);
24760 /* Tag_CPU_arch_profile. */
24761 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
24763 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
24765 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
24770 if (profile != '\0')
24771 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
24773 /* Tag_ARM_ISA_use. */
24774 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24776 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
24778 /* Tag_THUMB_ISA_use. */
24779 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24781 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24782 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
24784 /* Tag_VFP_arch. */
24785 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24786 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24787 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
24788 aeabi_set_attribute_int (Tag_VFP_arch,
24789 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24791 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
24794 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24796 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
24798 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24801 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24802 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24803 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24804 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24805 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24807 /* Tag_ABI_HardFP_use. */
24808 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24809 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24810 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24812 /* Tag_WMMX_arch. */
24813 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24814 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24815 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24816 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24818 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24819 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24820 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24821 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24823 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24825 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24829 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24834 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24835 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24836 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24840 We set Tag_DIV_use to two when integer divide instructions have been used
24841 in ARM state, or when Thumb integer divide instructions have been used,
24842 but we have no architecture profile set, nor have we any ARM instructions.
24844 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24847 For new architectures we will have to check these tests. */
24848 gas_assert (arch <= TAG_CPU_ARCH_V8);
24849 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24850 aeabi_set_attribute_int (Tag_DIV_use, 0);
24851 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24852 || (profile == '\0'
24853 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24854 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24855 aeabi_set_attribute_int (Tag_DIV_use, 2);
24857 /* Tag_MP_extension_use. */
24858 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24859 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24861 /* Tag Virtualization_use. */
24862 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24864 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24867 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24870 /* Add the default contents for the .ARM.attributes section. */
24874 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24877 aeabi_set_public_attributes ();
24879 #endif /* OBJ_ELF */
24882 /* Parse a .cpu directive. */
24885 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24887 const struct arm_cpu_option_table *opt;
24891 name = input_line_pointer;
24892 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24893 input_line_pointer++;
24894 saved_char = *input_line_pointer;
24895 *input_line_pointer = 0;
24897 /* Skip the first "all" entry. */
24898 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24899 if (streq (opt->name, name))
24901 mcpu_cpu_opt = &opt->value;
24902 selected_cpu = opt->value;
24903 if (opt->canonical_name)
24904 strcpy (selected_cpu_name, opt->canonical_name);
24908 for (i = 0; opt->name[i]; i++)
24909 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24911 selected_cpu_name[i] = 0;
24913 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24914 *input_line_pointer = saved_char;
24915 demand_empty_rest_of_line ();
24918 as_bad (_("unknown cpu `%s'"), name);
24919 *input_line_pointer = saved_char;
24920 ignore_rest_of_line ();
24924 /* Parse a .arch directive. */
24927 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24929 const struct arm_arch_option_table *opt;
24933 name = input_line_pointer;
24934 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24935 input_line_pointer++;
24936 saved_char = *input_line_pointer;
24937 *input_line_pointer = 0;
24939 /* Skip the first "all" entry. */
24940 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24941 if (streq (opt->name, name))
24943 mcpu_cpu_opt = &opt->value;
24944 selected_cpu = opt->value;
24945 strcpy (selected_cpu_name, opt->name);
24946 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24947 *input_line_pointer = saved_char;
24948 demand_empty_rest_of_line ();
24952 as_bad (_("unknown architecture `%s'\n"), name);
24953 *input_line_pointer = saved_char;
24954 ignore_rest_of_line ();
24958 /* Parse a .object_arch directive. */
24961 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24963 const struct arm_arch_option_table *opt;
24967 name = input_line_pointer;
24968 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24969 input_line_pointer++;
24970 saved_char = *input_line_pointer;
24971 *input_line_pointer = 0;
24973 /* Skip the first "all" entry. */
24974 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24975 if (streq (opt->name, name))
24977 object_arch = &opt->value;
24978 *input_line_pointer = saved_char;
24979 demand_empty_rest_of_line ();
24983 as_bad (_("unknown architecture `%s'\n"), name);
24984 *input_line_pointer = saved_char;
24985 ignore_rest_of_line ();
24988 /* Parse a .arch_extension directive. */
24991 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24993 const struct arm_option_extension_value_table *opt;
24996 int adding_value = 1;
24998 name = input_line_pointer;
24999 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25000 input_line_pointer++;
25001 saved_char = *input_line_pointer;
25002 *input_line_pointer = 0;
25004 if (strlen (name) >= 2
25005 && strncmp (name, "no", 2) == 0)
25011 for (opt = arm_extensions; opt->name != NULL; opt++)
25012 if (streq (opt->name, name))
25014 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
25016 as_bad (_("architectural extension `%s' is not allowed for the "
25017 "current base architecture"), name);
25022 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
25024 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
25026 mcpu_cpu_opt = &selected_cpu;
25027 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25028 *input_line_pointer = saved_char;
25029 demand_empty_rest_of_line ();
25033 if (opt->name == NULL)
25034 as_bad (_("unknown architecture `%s'\n"), name);
25036 *input_line_pointer = saved_char;
25037 ignore_rest_of_line ();
25040 /* Parse a .fpu directive. */
25043 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
25045 const struct arm_option_fpu_value_table *opt;
25049 name = input_line_pointer;
25050 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25051 input_line_pointer++;
25052 saved_char = *input_line_pointer;
25053 *input_line_pointer = 0;
25055 for (opt = arm_fpus; opt->name != NULL; opt++)
25056 if (streq (opt->name, name))
25058 mfpu_opt = &opt->value;
25059 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25060 *input_line_pointer = saved_char;
25061 demand_empty_rest_of_line ();
25065 as_bad (_("unknown floating point format `%s'\n"), name);
25066 *input_line_pointer = saved_char;
25067 ignore_rest_of_line ();
25070 /* Copy symbol information. */
25073 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
25075 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
25079 /* Given a symbolic attribute NAME, return the proper integer value.
25080 Returns -1 if the attribute is not known. */
25083 arm_convert_symbolic_attribute (const char *name)
25085 static const struct
25090 attribute_table[] =
25092 /* When you modify this table you should
25093 also modify the list in doc/c-arm.texi. */
25094 #define T(tag) {#tag, tag}
25095 T (Tag_CPU_raw_name),
25098 T (Tag_CPU_arch_profile),
25099 T (Tag_ARM_ISA_use),
25100 T (Tag_THUMB_ISA_use),
25104 T (Tag_Advanced_SIMD_arch),
25105 T (Tag_PCS_config),
25106 T (Tag_ABI_PCS_R9_use),
25107 T (Tag_ABI_PCS_RW_data),
25108 T (Tag_ABI_PCS_RO_data),
25109 T (Tag_ABI_PCS_GOT_use),
25110 T (Tag_ABI_PCS_wchar_t),
25111 T (Tag_ABI_FP_rounding),
25112 T (Tag_ABI_FP_denormal),
25113 T (Tag_ABI_FP_exceptions),
25114 T (Tag_ABI_FP_user_exceptions),
25115 T (Tag_ABI_FP_number_model),
25116 T (Tag_ABI_align_needed),
25117 T (Tag_ABI_align8_needed),
25118 T (Tag_ABI_align_preserved),
25119 T (Tag_ABI_align8_preserved),
25120 T (Tag_ABI_enum_size),
25121 T (Tag_ABI_HardFP_use),
25122 T (Tag_ABI_VFP_args),
25123 T (Tag_ABI_WMMX_args),
25124 T (Tag_ABI_optimization_goals),
25125 T (Tag_ABI_FP_optimization_goals),
25126 T (Tag_compatibility),
25127 T (Tag_CPU_unaligned_access),
25128 T (Tag_FP_HP_extension),
25129 T (Tag_VFP_HP_extension),
25130 T (Tag_ABI_FP_16bit_format),
25131 T (Tag_MPextension_use),
25133 T (Tag_nodefaults),
25134 T (Tag_also_compatible_with),
25135 T (Tag_conformance),
25137 T (Tag_Virtualization_use),
25138 /* We deliberately do not include Tag_MPextension_use_legacy. */
25146 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
25147 if (streq (name, attribute_table[i].name))
25148 return attribute_table[i].tag;
25154 /* Apply sym value for relocations only in the case that
25155 they are for local symbols and you have the respective
25156 architectural feature for blx and simple switches. */
25158 arm_apply_sym_value (struct fix * fixP)
25161 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
25162 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
25164 switch (fixP->fx_r_type)
25166 case BFD_RELOC_ARM_PCREL_BLX:
25167 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25168 if (ARM_IS_FUNC (fixP->fx_addsy))
25172 case BFD_RELOC_ARM_PCREL_CALL:
25173 case BFD_RELOC_THUMB_PCREL_BLX:
25174 if (THUMB_IS_FUNC (fixP->fx_addsy))
25185 #endif /* OBJ_ELF */