1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994-2013 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant;
127 static arm_feature_set arm_arch_used;
128 static arm_feature_set thumb_arch_used;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26 = FALSE;
132 static int atpcs = FALSE;
133 static int support_interwork = FALSE;
134 static int uses_apcs_float = FALSE;
135 static int pic_code = FALSE;
136 static int fix_v4bx = FALSE;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated = TRUE;
141 /* Variables that we set while parsing command-line options. Once all
142 options have been read we re-process these values to set the real
144 static const arm_feature_set *legacy_cpu = NULL;
145 static const arm_feature_set *legacy_fpu = NULL;
147 static const arm_feature_set *mcpu_cpu_opt = NULL;
148 static const arm_feature_set *mcpu_fpu_opt = NULL;
149 static const arm_feature_set *march_cpu_opt = NULL;
150 static const arm_feature_set *march_fpu_opt = NULL;
151 static const arm_feature_set *mfpu_opt = NULL;
152 static const arm_feature_set *object_arch = NULL;
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default = FPU_DEFAULT;
156 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
158 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
159 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
160 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
161 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
162 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
163 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
166 static const arm_feature_set cpu_default = CPU_DEFAULT;
169 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
170 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
171 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
172 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
173 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
174 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
175 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
176 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
177 static const arm_feature_set arm_ext_v4t_5 =
178 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
180 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
181 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
182 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
183 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
184 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
185 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
186 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
187 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
188 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
189 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
190 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
191 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
192 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
193 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
194 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
195 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
196 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
197 static const arm_feature_set arm_ext_m =
198 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
199 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
200 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
201 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
202 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
203 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
205 static const arm_feature_set arm_arch_any = ARM_ANY;
206 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
208 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
209 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
211 static const arm_feature_set arm_cext_iwmmxt2 =
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
213 static const arm_feature_set arm_cext_iwmmxt =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
215 static const arm_feature_set arm_cext_xscale =
216 ARM_FEATURE (0, ARM_CEXT_XSCALE);
217 static const arm_feature_set arm_cext_maverick =
218 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
219 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
220 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
221 static const arm_feature_set fpu_vfp_ext_v1xd =
222 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
223 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
224 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
225 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
226 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
227 static const arm_feature_set fpu_vfp_ext_d32 =
228 ARM_FEATURE (0, FPU_VFP_EXT_D32);
229 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
230 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
231 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
232 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
233 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
234 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_armv8 =
236 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
237 static const arm_feature_set fpu_neon_ext_armv8 =
238 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
239 static const arm_feature_set fpu_crypto_ext_armv8 =
240 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
241 static const arm_feature_set crc_ext_armv8 =
242 ARM_FEATURE (0, CRC_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
324 /* An immediate operand can start with #, and ld*, st*, pld operands
325 can contain [ and ]. We need to tell APP not to elide whitespace
326 before a [, which can appear as the first operand for pld. */
327 const char arm_symbol_chars[] = "#[]";
342 enum neon_el_type type;
346 #define NEON_MAX_TYPE_ELS 4
350 struct neon_type_el el[NEON_MAX_TYPE_ELS];
354 enum it_instruction_type
359 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
360 if inside, should be the last one. */
361 NEUTRAL_IT_INSN, /* This could be either inside or outside,
362 i.e. BKPT and NOP. */
363 IT_INSN /* The IT insn has been parsed. */
366 /* The maximum number of operands we need. */
367 #define ARM_IT_MAX_OPERANDS 6
372 unsigned long instruction;
376 /* "uncond_value" is set to the value in place of the conditional field in
377 unconditional versions of the instruction, or -1 if nothing is
380 struct neon_type vectype;
381 /* This does not indicate an actual NEON instruction, only that
382 the mnemonic accepts neon-style type suffixes. */
384 /* Set to the opcode if the instruction needs relaxation.
385 Zero if the instruction is not relaxed. */
389 bfd_reloc_code_real_type type;
394 enum it_instruction_type it_insn_type;
400 struct neon_type_el vectype;
401 unsigned present : 1; /* Operand present. */
402 unsigned isreg : 1; /* Operand was a register. */
403 unsigned immisreg : 1; /* .imm field is a second register. */
404 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
405 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
406 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
407 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
408 instructions. This allows us to disambiguate ARM <-> vector insns. */
409 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
410 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
411 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
412 unsigned issingle : 1; /* Operand is VFP single-precision register. */
413 unsigned hasreloc : 1; /* Operand has relocation suffix. */
414 unsigned writeback : 1; /* Operand has trailing ! */
415 unsigned preind : 1; /* Preindexed address. */
416 unsigned postind : 1; /* Postindexed address. */
417 unsigned negative : 1; /* Index register was negated. */
418 unsigned shifted : 1; /* Shift applied to operation. */
419 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
420 } operands[ARM_IT_MAX_OPERANDS];
423 static struct arm_it inst;
425 #define NUM_FLOAT_VALS 8
427 const char * fp_const[] =
429 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
432 /* Number of littlenums required to hold an extended precision number. */
433 #define MAX_LITTLENUMS 6
435 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
445 #define CP_T_X 0x00008000
446 #define CP_T_Y 0x00400000
448 #define CONDS_BIT 0x00100000
449 #define LOAD_BIT 0x00100000
451 #define DOUBLE_LOAD_FLAG 0x00000001
455 const char * template_name;
459 #define COND_ALWAYS 0xE
463 const char * template_name;
467 struct asm_barrier_opt
469 const char * template_name;
471 const arm_feature_set arch;
474 /* The bit that distinguishes CPSR and SPSR. */
475 #define SPSR_BIT (1 << 22)
477 /* The individual PSR flag bits. */
478 #define PSR_c (1 << 16)
479 #define PSR_x (1 << 17)
480 #define PSR_s (1 << 18)
481 #define PSR_f (1 << 19)
486 bfd_reloc_code_real_type reloc;
491 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
492 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
497 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
500 /* Bits for DEFINED field in neon_typed_alias. */
501 #define NTA_HASTYPE 1
502 #define NTA_HASINDEX 2
504 struct neon_typed_alias
506 unsigned char defined;
508 struct neon_type_el eltype;
511 /* ARM register categories. This includes coprocessor numbers and various
512 architecture extensions' registers. */
539 /* Structure for a hash table entry for a register.
540 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
541 information which states whether a vector type or index is specified (for a
542 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
548 unsigned char builtin;
549 struct neon_typed_alias * neon;
552 /* Diagnostics used when we don't get a register of the expected type. */
553 const char * const reg_expected_msgs[] =
555 N_("ARM register expected"),
556 N_("bad or missing co-processor number"),
557 N_("co-processor register expected"),
558 N_("FPA register expected"),
559 N_("VFP single precision register expected"),
560 N_("VFP/Neon double precision register expected"),
561 N_("Neon quad precision register expected"),
562 N_("VFP single or double precision register expected"),
563 N_("Neon double or quad precision register expected"),
564 N_("VFP single, double or Neon quad precision register expected"),
565 N_("VFP system register expected"),
566 N_("Maverick MVF register expected"),
567 N_("Maverick MVD register expected"),
568 N_("Maverick MVFX register expected"),
569 N_("Maverick MVDX register expected"),
570 N_("Maverick MVAX register expected"),
571 N_("Maverick DSPSC register expected"),
572 N_("iWMMXt data register expected"),
573 N_("iWMMXt control register expected"),
574 N_("iWMMXt scalar register expected"),
575 N_("XScale accumulator register expected"),
578 /* Some well known registers that we refer to directly elsewhere. */
584 /* ARM instructions take 4bytes in the object file, Thumb instructions
590 /* Basic string to match. */
591 const char * template_name;
593 /* Parameters to instruction. */
594 unsigned int operands[8];
596 /* Conditional tag - see opcode_lookup. */
597 unsigned int tag : 4;
599 /* Basic instruction code. */
600 unsigned int avalue : 28;
602 /* Thumb-format instruction code. */
605 /* Which architecture variant provides this instruction. */
606 const arm_feature_set * avariant;
607 const arm_feature_set * tvariant;
609 /* Function to call to encode instruction in ARM format. */
610 void (* aencode) (void);
612 /* Function to call to encode instruction in Thumb format. */
613 void (* tencode) (void);
616 /* Defines for various bits that we will want to toggle. */
617 #define INST_IMMEDIATE 0x02000000
618 #define OFFSET_REG 0x02000000
619 #define HWOFFSET_IMM 0x00400000
620 #define SHIFT_BY_REG 0x00000010
621 #define PRE_INDEX 0x01000000
622 #define INDEX_UP 0x00800000
623 #define WRITE_BACK 0x00200000
624 #define LDM_TYPE_2_OR_3 0x00400000
625 #define CPSI_MMOD 0x00020000
627 #define LITERAL_MASK 0xf000f000
628 #define OPCODE_MASK 0xfe1fffff
629 #define V4_STR_BIT 0x00000020
631 #define T2_SUBS_PC_LR 0xf3de8f00
633 #define DATA_OP_SHIFT 21
635 #define T2_OPCODE_MASK 0xfe1fffff
636 #define T2_DATA_OP_SHIFT 21
638 #define A_COND_MASK 0xf0000000
639 #define A_PUSH_POP_OP_MASK 0x0fff0000
641 /* Opcodes for pushing/poping registers to/from the stack. */
642 #define A1_OPCODE_PUSH 0x092d0000
643 #define A2_OPCODE_PUSH 0x052d0004
644 #define A2_OPCODE_POP 0x049d0004
646 /* Codes to distinguish the arithmetic instructions. */
657 #define OPCODE_CMP 10
658 #define OPCODE_CMN 11
659 #define OPCODE_ORR 12
660 #define OPCODE_MOV 13
661 #define OPCODE_BIC 14
662 #define OPCODE_MVN 15
664 #define T2_OPCODE_AND 0
665 #define T2_OPCODE_BIC 1
666 #define T2_OPCODE_ORR 2
667 #define T2_OPCODE_ORN 3
668 #define T2_OPCODE_EOR 4
669 #define T2_OPCODE_ADD 8
670 #define T2_OPCODE_ADC 10
671 #define T2_OPCODE_SBC 11
672 #define T2_OPCODE_SUB 13
673 #define T2_OPCODE_RSB 14
675 #define T_OPCODE_MUL 0x4340
676 #define T_OPCODE_TST 0x4200
677 #define T_OPCODE_CMN 0x42c0
678 #define T_OPCODE_NEG 0x4240
679 #define T_OPCODE_MVN 0x43c0
681 #define T_OPCODE_ADD_R3 0x1800
682 #define T_OPCODE_SUB_R3 0x1a00
683 #define T_OPCODE_ADD_HI 0x4400
684 #define T_OPCODE_ADD_ST 0xb000
685 #define T_OPCODE_SUB_ST 0xb080
686 #define T_OPCODE_ADD_SP 0xa800
687 #define T_OPCODE_ADD_PC 0xa000
688 #define T_OPCODE_ADD_I8 0x3000
689 #define T_OPCODE_SUB_I8 0x3800
690 #define T_OPCODE_ADD_I3 0x1c00
691 #define T_OPCODE_SUB_I3 0x1e00
693 #define T_OPCODE_ASR_R 0x4100
694 #define T_OPCODE_LSL_R 0x4080
695 #define T_OPCODE_LSR_R 0x40c0
696 #define T_OPCODE_ROR_R 0x41c0
697 #define T_OPCODE_ASR_I 0x1000
698 #define T_OPCODE_LSL_I 0x0000
699 #define T_OPCODE_LSR_I 0x0800
701 #define T_OPCODE_MOV_I8 0x2000
702 #define T_OPCODE_CMP_I8 0x2800
703 #define T_OPCODE_CMP_LR 0x4280
704 #define T_OPCODE_MOV_HR 0x4600
705 #define T_OPCODE_CMP_HR 0x4500
707 #define T_OPCODE_LDR_PC 0x4800
708 #define T_OPCODE_LDR_SP 0x9800
709 #define T_OPCODE_STR_SP 0x9000
710 #define T_OPCODE_LDR_IW 0x6800
711 #define T_OPCODE_STR_IW 0x6000
712 #define T_OPCODE_LDR_IH 0x8800
713 #define T_OPCODE_STR_IH 0x8000
714 #define T_OPCODE_LDR_IB 0x7800
715 #define T_OPCODE_STR_IB 0x7000
716 #define T_OPCODE_LDR_RW 0x5800
717 #define T_OPCODE_STR_RW 0x5000
718 #define T_OPCODE_LDR_RH 0x5a00
719 #define T_OPCODE_STR_RH 0x5200
720 #define T_OPCODE_LDR_RB 0x5c00
721 #define T_OPCODE_STR_RB 0x5400
723 #define T_OPCODE_PUSH 0xb400
724 #define T_OPCODE_POP 0xbc00
726 #define T_OPCODE_BRANCH 0xe000
728 #define THUMB_SIZE 2 /* Size of thumb instruction. */
729 #define THUMB_PP_PC_LR 0x0100
730 #define THUMB_LOAD_BIT 0x0800
731 #define THUMB2_LOAD_BIT 0x00100000
733 #define BAD_ARGS _("bad arguments to instruction")
734 #define BAD_SP _("r13 not allowed here")
735 #define BAD_PC _("r15 not allowed here")
736 #define BAD_COND _("instruction cannot be conditional")
737 #define BAD_OVERLAP _("registers may not be the same")
738 #define BAD_HIREG _("lo register required")
739 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
740 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
741 #define BAD_BRANCH _("branch must be last instruction in IT block")
742 #define BAD_NOT_IT _("instruction not allowed in IT block")
743 #define BAD_FPU _("selected FPU does not support instruction")
744 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
745 #define BAD_IT_COND _("incorrect condition in IT block")
746 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
747 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
748 #define BAD_PC_ADDRESSING \
749 _("cannot use register index with PC-relative addressing")
750 #define BAD_PC_WRITEBACK \
751 _("cannot use writeback with PC-relative addressing")
752 #define BAD_RANGE _("branch out of range")
753 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
755 static struct hash_control * arm_ops_hsh;
756 static struct hash_control * arm_cond_hsh;
757 static struct hash_control * arm_shift_hsh;
758 static struct hash_control * arm_psr_hsh;
759 static struct hash_control * arm_v7m_psr_hsh;
760 static struct hash_control * arm_reg_hsh;
761 static struct hash_control * arm_reloc_hsh;
762 static struct hash_control * arm_barrier_opt_hsh;
764 /* Stuff needed to resolve the label ambiguity
773 symbolS * last_label_seen;
774 static int label_is_thumb_function_name = FALSE;
776 /* Literal pool structure. Held on a per-section
777 and per-sub-section basis. */
779 #define MAX_LITERAL_POOL_SIZE 1024
780 typedef struct literal_pool
782 expressionS literals [MAX_LITERAL_POOL_SIZE];
783 unsigned int next_free_entry;
789 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
791 struct literal_pool * next;
794 /* Pointer to a linked list of literal pools. */
795 literal_pool * list_of_pools = NULL;
798 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
800 static struct current_it now_it;
804 now_it_compatible (int cond)
806 return (cond & ~1) == (now_it.cc & ~1);
810 conditional_insn (void)
812 return inst.cond != COND_ALWAYS;
815 static int in_it_block (void);
817 static int handle_it_state (void);
819 static void force_automatic_it_block_close (void);
821 static void it_fsm_post_encode (void);
823 #define set_it_insn_type(type) \
826 inst.it_insn_type = type; \
827 if (handle_it_state () == FAIL) \
832 #define set_it_insn_type_nonvoid(type, failret) \
835 inst.it_insn_type = type; \
836 if (handle_it_state () == FAIL) \
841 #define set_it_insn_type_last() \
844 if (inst.cond == COND_ALWAYS) \
845 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
847 set_it_insn_type (INSIDE_IT_LAST_INSN); \
853 /* This array holds the chars that always start a comment. If the
854 pre-processor is disabled, these aren't very useful. */
855 const char comment_chars[] = "@";
857 /* This array holds the chars that only start a comment at the beginning of
858 a line. If the line seems to have the form '# 123 filename'
859 .line and .file directives will appear in the pre-processed output. */
860 /* Note that input_file.c hand checks for '#' at the beginning of the
861 first line of the input file. This is because the compiler outputs
862 #NO_APP at the beginning of its output. */
863 /* Also note that comments like this one will always work. */
864 const char line_comment_chars[] = "#";
866 const char line_separator_chars[] = ";";
868 /* Chars that can be used to separate mant
869 from exp in floating point numbers. */
870 const char EXP_CHARS[] = "eE";
872 /* Chars that mean this number is a floating point constant. */
876 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
878 /* Prefix characters that indicate the start of an immediate
880 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
882 /* Separator character handling. */
884 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
887 skip_past_char (char ** str, char c)
889 /* PR gas/14987: Allow for whitespace before the expected character. */
890 skip_whitespace (*str);
901 #define skip_past_comma(str) skip_past_char (str, ',')
903 /* Arithmetic expressions (possibly involving symbols). */
905 /* Return TRUE if anything in the expression is a bignum. */
908 walk_no_bignums (symbolS * sp)
910 if (symbol_get_value_expression (sp)->X_op == O_big)
913 if (symbol_get_value_expression (sp)->X_add_symbol)
915 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
916 || (symbol_get_value_expression (sp)->X_op_symbol
917 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
923 static int in_my_get_expression = 0;
925 /* Third argument to my_get_expression. */
926 #define GE_NO_PREFIX 0
927 #define GE_IMM_PREFIX 1
928 #define GE_OPT_PREFIX 2
929 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
930 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
931 #define GE_OPT_PREFIX_BIG 3
934 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
939 /* In unified syntax, all prefixes are optional. */
941 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
946 case GE_NO_PREFIX: break;
948 if (!is_immediate_prefix (**str))
950 inst.error = _("immediate expression requires a # prefix");
956 case GE_OPT_PREFIX_BIG:
957 if (is_immediate_prefix (**str))
963 memset (ep, 0, sizeof (expressionS));
965 save_in = input_line_pointer;
966 input_line_pointer = *str;
967 in_my_get_expression = 1;
968 seg = expression (ep);
969 in_my_get_expression = 0;
971 if (ep->X_op == O_illegal || ep->X_op == O_absent)
973 /* We found a bad or missing expression in md_operand(). */
974 *str = input_line_pointer;
975 input_line_pointer = save_in;
976 if (inst.error == NULL)
977 inst.error = (ep->X_op == O_absent
978 ? _("missing expression") :_("bad expression"));
983 if (seg != absolute_section
984 && seg != text_section
985 && seg != data_section
986 && seg != bss_section
987 && seg != undefined_section)
989 inst.error = _("bad segment");
990 *str = input_line_pointer;
991 input_line_pointer = save_in;
998 /* Get rid of any bignums now, so that we don't generate an error for which
999 we can't establish a line number later on. Big numbers are never valid
1000 in instructions, which is where this routine is always called. */
1001 if (prefix_mode != GE_OPT_PREFIX_BIG
1002 && (ep->X_op == O_big
1003 || (ep->X_add_symbol
1004 && (walk_no_bignums (ep->X_add_symbol)
1006 && walk_no_bignums (ep->X_op_symbol))))))
1008 inst.error = _("invalid constant");
1009 *str = input_line_pointer;
1010 input_line_pointer = save_in;
1014 *str = input_line_pointer;
1015 input_line_pointer = save_in;
1019 /* Turn a string in input_line_pointer into a floating point constant
1020 of type TYPE, and store the appropriate bytes in *LITP. The number
1021 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1022 returned, or NULL on OK.
1024 Note that fp constants aren't represent in the normal way on the ARM.
1025 In big endian mode, things are as expected. However, in little endian
1026 mode fp constants are big-endian word-wise, and little-endian byte-wise
1027 within the words. For example, (double) 1.1 in big endian mode is
1028 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1029 the byte sequence 99 99 f1 3f 9a 99 99 99.
1031 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1034 md_atof (int type, char * litP, int * sizeP)
1037 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1069 return _("Unrecognized or unsupported floating point constant");
1072 t = atof_ieee (input_line_pointer, type, words);
1074 input_line_pointer = t;
1075 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1077 if (target_big_endian)
1079 for (i = 0; i < prec; i++)
1081 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1082 litP += sizeof (LITTLENUM_TYPE);
1087 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1088 for (i = prec - 1; i >= 0; i--)
1090 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1091 litP += sizeof (LITTLENUM_TYPE);
1094 /* For a 4 byte float the order of elements in `words' is 1 0.
1095 For an 8 byte float the order is 1 0 3 2. */
1096 for (i = 0; i < prec; i += 2)
1098 md_number_to_chars (litP, (valueT) words[i + 1],
1099 sizeof (LITTLENUM_TYPE));
1100 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1101 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1102 litP += 2 * sizeof (LITTLENUM_TYPE);
1109 /* We handle all bad expressions here, so that we can report the faulty
1110 instruction in the error message. */
1112 md_operand (expressionS * exp)
1114 if (in_my_get_expression)
1115 exp->X_op = O_illegal;
1118 /* Immediate values. */
1120 /* Generic immediate-value read function for use in directives.
1121 Accepts anything that 'expression' can fold to a constant.
1122 *val receives the number. */
1125 immediate_for_directive (int *val)
1128 exp.X_op = O_illegal;
1130 if (is_immediate_prefix (*input_line_pointer))
1132 input_line_pointer++;
1136 if (exp.X_op != O_constant)
1138 as_bad (_("expected #constant"));
1139 ignore_rest_of_line ();
1142 *val = exp.X_add_number;
1147 /* Register parsing. */
1149 /* Generic register parser. CCP points to what should be the
1150 beginning of a register name. If it is indeed a valid register
1151 name, advance CCP over it and return the reg_entry structure;
1152 otherwise return NULL. Does not issue diagnostics. */
1154 static struct reg_entry *
1155 arm_reg_parse_multi (char **ccp)
1159 struct reg_entry *reg;
1161 #ifdef REGISTER_PREFIX
1162 if (*start != REGISTER_PREFIX)
1166 #ifdef OPTIONAL_REGISTER_PREFIX
1167 if (*start == OPTIONAL_REGISTER_PREFIX)
1172 if (!ISALPHA (*p) || !is_name_beginner (*p))
1177 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1179 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1189 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1190 enum arm_reg_type type)
1192 /* Alternative syntaxes are accepted for a few register classes. */
1199 /* Generic coprocessor register names are allowed for these. */
1200 if (reg && reg->type == REG_TYPE_CN)
1205 /* For backward compatibility, a bare number is valid here. */
1207 unsigned long processor = strtoul (start, ccp, 10);
1208 if (*ccp != start && processor <= 15)
1212 case REG_TYPE_MMXWC:
1213 /* WC includes WCG. ??? I'm not sure this is true for all
1214 instructions that take WC registers. */
1215 if (reg && reg->type == REG_TYPE_MMXWCG)
1226 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1227 return value is the register number or FAIL. */
1230 arm_reg_parse (char **ccp, enum arm_reg_type type)
1233 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1236 /* Do not allow a scalar (reg+index) to parse as a register. */
1237 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1240 if (reg && reg->type == type)
1243 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1250 /* Parse a Neon type specifier. *STR should point at the leading '.'
1251 character. Does no verification at this stage that the type fits the opcode
1258 Can all be legally parsed by this function.
1260 Fills in neon_type struct pointer with parsed information, and updates STR
1261 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1262 type, FAIL if not. */
1265 parse_neon_type (struct neon_type *type, char **str)
1272 while (type->elems < NEON_MAX_TYPE_ELS)
1274 enum neon_el_type thistype = NT_untyped;
1275 unsigned thissize = -1u;
1282 /* Just a size without an explicit type. */
1286 switch (TOLOWER (*ptr))
1288 case 'i': thistype = NT_integer; break;
1289 case 'f': thistype = NT_float; break;
1290 case 'p': thistype = NT_poly; break;
1291 case 's': thistype = NT_signed; break;
1292 case 'u': thistype = NT_unsigned; break;
1294 thistype = NT_float;
1299 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1305 /* .f is an abbreviation for .f32. */
1306 if (thistype == NT_float && !ISDIGIT (*ptr))
1311 thissize = strtoul (ptr, &ptr, 10);
1313 if (thissize != 8 && thissize != 16 && thissize != 32
1316 as_bad (_("bad size %d in type specifier"), thissize);
1324 type->el[type->elems].type = thistype;
1325 type->el[type->elems].size = thissize;
1330 /* Empty/missing type is not a successful parse. */
1331 if (type->elems == 0)
1339 /* Errors may be set multiple times during parsing or bit encoding
1340 (particularly in the Neon bits), but usually the earliest error which is set
1341 will be the most meaningful. Avoid overwriting it with later (cascading)
1342 errors by calling this function. */
1345 first_error (const char *err)
1351 /* Parse a single type, e.g. ".s32", leading period included. */
1353 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1356 struct neon_type optype;
1360 if (parse_neon_type (&optype, &str) == SUCCESS)
1362 if (optype.elems == 1)
1363 *vectype = optype.el[0];
1366 first_error (_("only one type should be specified for operand"));
1372 first_error (_("vector type expected"));
1384 /* Special meanings for indices (which have a range of 0-7), which will fit into
1387 #define NEON_ALL_LANES 15
1388 #define NEON_INTERLEAVE_LANES 14
1390 /* Parse either a register or a scalar, with an optional type. Return the
1391 register number, and optionally fill in the actual type of the register
1392 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1393 type/index information in *TYPEINFO. */
1396 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1397 enum arm_reg_type *rtype,
1398 struct neon_typed_alias *typeinfo)
1401 struct reg_entry *reg = arm_reg_parse_multi (&str);
1402 struct neon_typed_alias atype;
1403 struct neon_type_el parsetype;
1407 atype.eltype.type = NT_invtype;
1408 atype.eltype.size = -1;
1410 /* Try alternate syntax for some types of register. Note these are mutually
1411 exclusive with the Neon syntax extensions. */
1414 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1422 /* Undo polymorphism when a set of register types may be accepted. */
1423 if ((type == REG_TYPE_NDQ
1424 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1425 || (type == REG_TYPE_VFSD
1426 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1427 || (type == REG_TYPE_NSDQ
1428 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1429 || reg->type == REG_TYPE_NQ))
1430 || (type == REG_TYPE_MMXWC
1431 && (reg->type == REG_TYPE_MMXWCG)))
1432 type = (enum arm_reg_type) reg->type;
1434 if (type != reg->type)
1440 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1442 if ((atype.defined & NTA_HASTYPE) != 0)
1444 first_error (_("can't redefine type for operand"));
1447 atype.defined |= NTA_HASTYPE;
1448 atype.eltype = parsetype;
1451 if (skip_past_char (&str, '[') == SUCCESS)
1453 if (type != REG_TYPE_VFD)
1455 first_error (_("only D registers may be indexed"));
1459 if ((atype.defined & NTA_HASINDEX) != 0)
1461 first_error (_("can't change index for operand"));
1465 atype.defined |= NTA_HASINDEX;
1467 if (skip_past_char (&str, ']') == SUCCESS)
1468 atype.index = NEON_ALL_LANES;
1473 my_get_expression (&exp, &str, GE_NO_PREFIX);
1475 if (exp.X_op != O_constant)
1477 first_error (_("constant expression required"));
1481 if (skip_past_char (&str, ']') == FAIL)
1484 atype.index = exp.X_add_number;
1499 /* Like arm_reg_parse, but allow allow the following extra features:
1500 - If RTYPE is non-zero, return the (possibly restricted) type of the
1501 register (e.g. Neon double or quad reg when either has been requested).
1502 - If this is a Neon vector type with additional type information, fill
1503 in the struct pointed to by VECTYPE (if non-NULL).
1504 This function will fault on encountering a scalar. */
1507 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1508 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1510 struct neon_typed_alias atype;
1512 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1517 /* Do not allow regname(... to parse as a register. */
1521 /* Do not allow a scalar (reg+index) to parse as a register. */
1522 if ((atype.defined & NTA_HASINDEX) != 0)
1524 first_error (_("register operand expected, but got scalar"));
1529 *vectype = atype.eltype;
1536 #define NEON_SCALAR_REG(X) ((X) >> 4)
1537 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1539 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1540 have enough information to be able to do a good job bounds-checking. So, we
1541 just do easy checks here, and do further checks later. */
1544 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1548 struct neon_typed_alias atype;
1550 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1552 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1555 if (atype.index == NEON_ALL_LANES)
1557 first_error (_("scalar must have an index"));
1560 else if (atype.index >= 64 / elsize)
1562 first_error (_("scalar index out of range"));
1567 *type = atype.eltype;
1571 return reg * 16 + atype.index;
1574 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1577 parse_reg_list (char ** strp)
1579 char * str = * strp;
1583 /* We come back here if we get ranges concatenated by '+' or '|'. */
1598 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1600 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1610 first_error (_("bad range in register list"));
1614 for (i = cur_reg + 1; i < reg; i++)
1616 if (range & (1 << i))
1618 (_("Warning: duplicated register (r%d) in register list"),
1626 if (range & (1 << reg))
1627 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1629 else if (reg <= cur_reg)
1630 as_tsktsk (_("Warning: register range not in ascending order"));
1635 while (skip_past_comma (&str) != FAIL
1636 || (in_range = 1, *str++ == '-'));
1641 first_error (_("missing `}'"));
1649 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1652 if (exp.X_op == O_constant)
1654 if (exp.X_add_number
1655 != (exp.X_add_number & 0x0000ffff))
1657 inst.error = _("invalid register mask");
1661 if ((range & exp.X_add_number) != 0)
1663 int regno = range & exp.X_add_number;
1666 regno = (1 << regno) - 1;
1668 (_("Warning: duplicated register (r%d) in register list"),
1672 range |= exp.X_add_number;
1676 if (inst.reloc.type != 0)
1678 inst.error = _("expression too complex");
1682 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1683 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1684 inst.reloc.pc_rel = 0;
1688 if (*str == '|' || *str == '+')
1694 while (another_range);
1700 /* Types of registers in a list. */
1709 /* Parse a VFP register list. If the string is invalid return FAIL.
1710 Otherwise return the number of registers, and set PBASE to the first
1711 register. Parses registers of type ETYPE.
1712 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1713 - Q registers can be used to specify pairs of D registers
1714 - { } can be omitted from around a singleton register list
1715 FIXME: This is not implemented, as it would require backtracking in
1718 This could be done (the meaning isn't really ambiguous), but doesn't
1719 fit in well with the current parsing framework.
1720 - 32 D registers may be used (also true for VFPv3).
1721 FIXME: Types are ignored in these register lists, which is probably a
1725 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1730 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1734 unsigned long mask = 0;
1739 inst.error = _("expecting {");
1748 regtype = REG_TYPE_VFS;
1753 regtype = REG_TYPE_VFD;
1756 case REGLIST_NEON_D:
1757 regtype = REG_TYPE_NDQ;
1761 if (etype != REGLIST_VFP_S)
1763 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1764 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1768 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1771 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1778 base_reg = max_regs;
1782 int setmask = 1, addregs = 1;
1784 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1786 if (new_base == FAIL)
1788 first_error (_(reg_expected_msgs[regtype]));
1792 if (new_base >= max_regs)
1794 first_error (_("register out of range in list"));
1798 /* Note: a value of 2 * n is returned for the register Q<n>. */
1799 if (regtype == REG_TYPE_NQ)
1805 if (new_base < base_reg)
1806 base_reg = new_base;
1808 if (mask & (setmask << new_base))
1810 first_error (_("invalid register list"));
1814 if ((mask >> new_base) != 0 && ! warned)
1816 as_tsktsk (_("register list not in ascending order"));
1820 mask |= setmask << new_base;
1823 if (*str == '-') /* We have the start of a range expression */
1829 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1832 inst.error = gettext (reg_expected_msgs[regtype]);
1836 if (high_range >= max_regs)
1838 first_error (_("register out of range in list"));
1842 if (regtype == REG_TYPE_NQ)
1843 high_range = high_range + 1;
1845 if (high_range <= new_base)
1847 inst.error = _("register range not in ascending order");
1851 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1853 if (mask & (setmask << new_base))
1855 inst.error = _("invalid register list");
1859 mask |= setmask << new_base;
1864 while (skip_past_comma (&str) != FAIL);
1868 /* Sanity check -- should have raised a parse error above. */
1869 if (count == 0 || count > max_regs)
1874 /* Final test -- the registers must be consecutive. */
1876 for (i = 0; i < count; i++)
1878 if ((mask & (1u << i)) == 0)
1880 inst.error = _("non-contiguous register range");
1890 /* True if two alias types are the same. */
1893 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1901 if (a->defined != b->defined)
1904 if ((a->defined & NTA_HASTYPE) != 0
1905 && (a->eltype.type != b->eltype.type
1906 || a->eltype.size != b->eltype.size))
1909 if ((a->defined & NTA_HASINDEX) != 0
1910 && (a->index != b->index))
1916 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1917 The base register is put in *PBASE.
1918 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1920 The register stride (minus one) is put in bit 4 of the return value.
1921 Bits [6:5] encode the list length (minus one).
1922 The type of the list elements is put in *ELTYPE, if non-NULL. */
1924 #define NEON_LANE(X) ((X) & 0xf)
1925 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1926 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1929 parse_neon_el_struct_list (char **str, unsigned *pbase,
1930 struct neon_type_el *eltype)
1937 int leading_brace = 0;
1938 enum arm_reg_type rtype = REG_TYPE_NDQ;
1939 const char *const incr_error = _("register stride must be 1 or 2");
1940 const char *const type_error = _("mismatched element/structure types in list");
1941 struct neon_typed_alias firsttype;
1943 if (skip_past_char (&ptr, '{') == SUCCESS)
1948 struct neon_typed_alias atype;
1949 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1953 first_error (_(reg_expected_msgs[rtype]));
1960 if (rtype == REG_TYPE_NQ)
1966 else if (reg_incr == -1)
1968 reg_incr = getreg - base_reg;
1969 if (reg_incr < 1 || reg_incr > 2)
1971 first_error (_(incr_error));
1975 else if (getreg != base_reg + reg_incr * count)
1977 first_error (_(incr_error));
1981 if (! neon_alias_types_same (&atype, &firsttype))
1983 first_error (_(type_error));
1987 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1991 struct neon_typed_alias htype;
1992 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1994 lane = NEON_INTERLEAVE_LANES;
1995 else if (lane != NEON_INTERLEAVE_LANES)
1997 first_error (_(type_error));
2002 else if (reg_incr != 1)
2004 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2008 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2011 first_error (_(reg_expected_msgs[rtype]));
2014 if (! neon_alias_types_same (&htype, &firsttype))
2016 first_error (_(type_error));
2019 count += hireg + dregs - getreg;
2023 /* If we're using Q registers, we can't use [] or [n] syntax. */
2024 if (rtype == REG_TYPE_NQ)
2030 if ((atype.defined & NTA_HASINDEX) != 0)
2034 else if (lane != atype.index)
2036 first_error (_(type_error));
2040 else if (lane == -1)
2041 lane = NEON_INTERLEAVE_LANES;
2042 else if (lane != NEON_INTERLEAVE_LANES)
2044 first_error (_(type_error));
2049 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2051 /* No lane set by [x]. We must be interleaving structures. */
2053 lane = NEON_INTERLEAVE_LANES;
2056 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2057 || (count > 1 && reg_incr == -1))
2059 first_error (_("error parsing element/structure list"));
2063 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2065 first_error (_("expected }"));
2073 *eltype = firsttype.eltype;
2078 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2081 /* Parse an explicit relocation suffix on an expression. This is
2082 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2083 arm_reloc_hsh contains no entries, so this function can only
2084 succeed if there is no () after the word. Returns -1 on error,
2085 BFD_RELOC_UNUSED if there wasn't any suffix. */
2088 parse_reloc (char **str)
2090 struct reloc_entry *r;
2094 return BFD_RELOC_UNUSED;
2099 while (*q && *q != ')' && *q != ',')
2104 if ((r = (struct reloc_entry *)
2105 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2112 /* Directives: register aliases. */
2114 static struct reg_entry *
2115 insert_reg_alias (char *str, unsigned number, int type)
2117 struct reg_entry *new_reg;
2120 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2122 if (new_reg->builtin)
2123 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2125 /* Only warn about a redefinition if it's not defined as the
2127 else if (new_reg->number != number || new_reg->type != type)
2128 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2133 name = xstrdup (str);
2134 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2136 new_reg->name = name;
2137 new_reg->number = number;
2138 new_reg->type = type;
2139 new_reg->builtin = FALSE;
2140 new_reg->neon = NULL;
2142 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2149 insert_neon_reg_alias (char *str, int number, int type,
2150 struct neon_typed_alias *atype)
2152 struct reg_entry *reg = insert_reg_alias (str, number, type);
2156 first_error (_("attempt to redefine typed alias"));
2162 reg->neon = (struct neon_typed_alias *)
2163 xmalloc (sizeof (struct neon_typed_alias));
2164 *reg->neon = *atype;
2168 /* Look for the .req directive. This is of the form:
2170 new_register_name .req existing_register_name
2172 If we find one, or if it looks sufficiently like one that we want to
2173 handle any error here, return TRUE. Otherwise return FALSE. */
2176 create_register_alias (char * newname, char *p)
2178 struct reg_entry *old;
2179 char *oldname, *nbuf;
2182 /* The input scrubber ensures that whitespace after the mnemonic is
2183 collapsed to single spaces. */
2185 if (strncmp (oldname, " .req ", 6) != 0)
2189 if (*oldname == '\0')
2192 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2195 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2199 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2200 the desired alias name, and p points to its end. If not, then
2201 the desired alias name is in the global original_case_string. */
2202 #ifdef TC_CASE_SENSITIVE
2205 newname = original_case_string;
2206 nlen = strlen (newname);
2209 nbuf = (char *) alloca (nlen + 1);
2210 memcpy (nbuf, newname, nlen);
2213 /* Create aliases under the new name as stated; an all-lowercase
2214 version of the new name; and an all-uppercase version of the new
2216 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2218 for (p = nbuf; *p; p++)
2221 if (strncmp (nbuf, newname, nlen))
2223 /* If this attempt to create an additional alias fails, do not bother
2224 trying to create the all-lower case alias. We will fail and issue
2225 a second, duplicate error message. This situation arises when the
2226 programmer does something like:
2229 The second .req creates the "Foo" alias but then fails to create
2230 the artificial FOO alias because it has already been created by the
2232 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2236 for (p = nbuf; *p; p++)
2239 if (strncmp (nbuf, newname, nlen))
2240 insert_reg_alias (nbuf, old->number, old->type);
2246 /* Create a Neon typed/indexed register alias using directives, e.g.:
2251 These typed registers can be used instead of the types specified after the
2252 Neon mnemonic, so long as all operands given have types. Types can also be
2253 specified directly, e.g.:
2254 vadd d0.s32, d1.s32, d2.s32 */
2257 create_neon_reg_alias (char *newname, char *p)
2259 enum arm_reg_type basetype;
2260 struct reg_entry *basereg;
2261 struct reg_entry mybasereg;
2262 struct neon_type ntype;
2263 struct neon_typed_alias typeinfo;
2264 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2267 typeinfo.defined = 0;
2268 typeinfo.eltype.type = NT_invtype;
2269 typeinfo.eltype.size = -1;
2270 typeinfo.index = -1;
2274 if (strncmp (p, " .dn ", 5) == 0)
2275 basetype = REG_TYPE_VFD;
2276 else if (strncmp (p, " .qn ", 5) == 0)
2277 basetype = REG_TYPE_NQ;
2286 basereg = arm_reg_parse_multi (&p);
2288 if (basereg && basereg->type != basetype)
2290 as_bad (_("bad type for register"));
2294 if (basereg == NULL)
2297 /* Try parsing as an integer. */
2298 my_get_expression (&exp, &p, GE_NO_PREFIX);
2299 if (exp.X_op != O_constant)
2301 as_bad (_("expression must be constant"));
2304 basereg = &mybasereg;
2305 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2311 typeinfo = *basereg->neon;
2313 if (parse_neon_type (&ntype, &p) == SUCCESS)
2315 /* We got a type. */
2316 if (typeinfo.defined & NTA_HASTYPE)
2318 as_bad (_("can't redefine the type of a register alias"));
2322 typeinfo.defined |= NTA_HASTYPE;
2323 if (ntype.elems != 1)
2325 as_bad (_("you must specify a single type only"));
2328 typeinfo.eltype = ntype.el[0];
2331 if (skip_past_char (&p, '[') == SUCCESS)
2334 /* We got a scalar index. */
2336 if (typeinfo.defined & NTA_HASINDEX)
2338 as_bad (_("can't redefine the index of a scalar alias"));
2342 my_get_expression (&exp, &p, GE_NO_PREFIX);
2344 if (exp.X_op != O_constant)
2346 as_bad (_("scalar index must be constant"));
2350 typeinfo.defined |= NTA_HASINDEX;
2351 typeinfo.index = exp.X_add_number;
2353 if (skip_past_char (&p, ']') == FAIL)
2355 as_bad (_("expecting ]"));
2360 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2361 the desired alias name, and p points to its end. If not, then
2362 the desired alias name is in the global original_case_string. */
2363 #ifdef TC_CASE_SENSITIVE
2364 namelen = nameend - newname;
2366 newname = original_case_string;
2367 namelen = strlen (newname);
2370 namebuf = (char *) alloca (namelen + 1);
2371 strncpy (namebuf, newname, namelen);
2372 namebuf[namelen] = '\0';
2374 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2375 typeinfo.defined != 0 ? &typeinfo : NULL);
2377 /* Insert name in all uppercase. */
2378 for (p = namebuf; *p; p++)
2381 if (strncmp (namebuf, newname, namelen))
2382 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2383 typeinfo.defined != 0 ? &typeinfo : NULL);
2385 /* Insert name in all lowercase. */
2386 for (p = namebuf; *p; p++)
2389 if (strncmp (namebuf, newname, namelen))
2390 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2391 typeinfo.defined != 0 ? &typeinfo : NULL);
2396 /* Should never be called, as .req goes between the alias and the
2397 register name, not at the beginning of the line. */
2400 s_req (int a ATTRIBUTE_UNUSED)
2402 as_bad (_("invalid syntax for .req directive"));
2406 s_dn (int a ATTRIBUTE_UNUSED)
2408 as_bad (_("invalid syntax for .dn directive"));
2412 s_qn (int a ATTRIBUTE_UNUSED)
2414 as_bad (_("invalid syntax for .qn directive"));
2417 /* The .unreq directive deletes an alias which was previously defined
2418 by .req. For example:
2424 s_unreq (int a ATTRIBUTE_UNUSED)
2429 name = input_line_pointer;
2431 while (*input_line_pointer != 0
2432 && *input_line_pointer != ' '
2433 && *input_line_pointer != '\n')
2434 ++input_line_pointer;
2436 saved_char = *input_line_pointer;
2437 *input_line_pointer = 0;
2440 as_bad (_("invalid syntax for .unreq directive"));
2443 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2447 as_bad (_("unknown register alias '%s'"), name);
2448 else if (reg->builtin)
2449 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2456 hash_delete (arm_reg_hsh, name, FALSE);
2457 free ((char *) reg->name);
2462 /* Also locate the all upper case and all lower case versions.
2463 Do not complain if we cannot find one or the other as it
2464 was probably deleted above. */
2466 nbuf = strdup (name);
2467 for (p = nbuf; *p; p++)
2469 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2472 hash_delete (arm_reg_hsh, nbuf, FALSE);
2473 free ((char *) reg->name);
2479 for (p = nbuf; *p; p++)
2481 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2484 hash_delete (arm_reg_hsh, nbuf, FALSE);
2485 free ((char *) reg->name);
2495 *input_line_pointer = saved_char;
2496 demand_empty_rest_of_line ();
2499 /* Directives: Instruction set selection. */
2502 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2503 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2504 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2505 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2507 /* Create a new mapping symbol for the transition to STATE. */
2510 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2513 const char * symname;
2520 type = BSF_NO_FLAGS;
2524 type = BSF_NO_FLAGS;
2528 type = BSF_NO_FLAGS;
2534 symbolP = symbol_new (symname, now_seg, value, frag);
2535 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2540 THUMB_SET_FUNC (symbolP, 0);
2541 ARM_SET_THUMB (symbolP, 0);
2542 ARM_SET_INTERWORK (symbolP, support_interwork);
2546 THUMB_SET_FUNC (symbolP, 1);
2547 ARM_SET_THUMB (symbolP, 1);
2548 ARM_SET_INTERWORK (symbolP, support_interwork);
2556 /* Save the mapping symbols for future reference. Also check that
2557 we do not place two mapping symbols at the same offset within a
2558 frag. We'll handle overlap between frags in
2559 check_mapping_symbols.
2561 If .fill or other data filling directive generates zero sized data,
2562 the mapping symbol for the following code will have the same value
2563 as the one generated for the data filling directive. In this case,
2564 we replace the old symbol with the new one at the same address. */
2567 if (frag->tc_frag_data.first_map != NULL)
2569 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2570 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2572 frag->tc_frag_data.first_map = symbolP;
2574 if (frag->tc_frag_data.last_map != NULL)
2576 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2577 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2578 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2580 frag->tc_frag_data.last_map = symbolP;
2583 /* We must sometimes convert a region marked as code to data during
2584 code alignment, if an odd number of bytes have to be padded. The
2585 code mapping symbol is pushed to an aligned address. */
2588 insert_data_mapping_symbol (enum mstate state,
2589 valueT value, fragS *frag, offsetT bytes)
2591 /* If there was already a mapping symbol, remove it. */
2592 if (frag->tc_frag_data.last_map != NULL
2593 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2595 symbolS *symp = frag->tc_frag_data.last_map;
2599 know (frag->tc_frag_data.first_map == symp);
2600 frag->tc_frag_data.first_map = NULL;
2602 frag->tc_frag_data.last_map = NULL;
2603 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2606 make_mapping_symbol (MAP_DATA, value, frag);
2607 make_mapping_symbol (state, value + bytes, frag);
2610 static void mapping_state_2 (enum mstate state, int max_chars);
2612 /* Set the mapping state to STATE. Only call this when about to
2613 emit some STATE bytes to the file. */
2616 mapping_state (enum mstate state)
2618 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2620 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2622 if (mapstate == state)
2623 /* The mapping symbol has already been emitted.
2624 There is nothing else to do. */
2627 if (state == MAP_ARM || state == MAP_THUMB)
2629 All ARM instructions require 4-byte alignment.
2630 (Almost) all Thumb instructions require 2-byte alignment.
2632 When emitting instructions into any section, mark the section
2635 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2636 but themselves require 2-byte alignment; this applies to some
2637 PC- relative forms. However, these cases will invovle implicit
2638 literal pool generation or an explicit .align >=2, both of
2639 which will cause the section to me marked with sufficient
2640 alignment. Thus, we don't handle those cases here. */
2641 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2643 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2644 /* This case will be evaluated later in the next else. */
2646 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2647 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2649 /* Only add the symbol if the offset is > 0:
2650 if we're at the first frag, check it's size > 0;
2651 if we're not at the first frag, then for sure
2652 the offset is > 0. */
2653 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2654 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2657 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2660 mapping_state_2 (state, 0);
2664 /* Same as mapping_state, but MAX_CHARS bytes have already been
2665 allocated. Put the mapping symbol that far back. */
2668 mapping_state_2 (enum mstate state, int max_chars)
2670 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2672 if (!SEG_NORMAL (now_seg))
2675 if (mapstate == state)
2676 /* The mapping symbol has already been emitted.
2677 There is nothing else to do. */
2680 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2681 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2684 #define mapping_state(x) ((void)0)
2685 #define mapping_state_2(x, y) ((void)0)
2688 /* Find the real, Thumb encoded start of a Thumb function. */
2692 find_real_start (symbolS * symbolP)
2695 const char * name = S_GET_NAME (symbolP);
2696 symbolS * new_target;
2698 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2699 #define STUB_NAME ".real_start_of"
2704 /* The compiler may generate BL instructions to local labels because
2705 it needs to perform a branch to a far away location. These labels
2706 do not have a corresponding ".real_start_of" label. We check
2707 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2708 the ".real_start_of" convention for nonlocal branches. */
2709 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2712 real_start = ACONCAT ((STUB_NAME, name, NULL));
2713 new_target = symbol_find (real_start);
2715 if (new_target == NULL)
2717 as_warn (_("Failed to find real start of function: %s\n"), name);
2718 new_target = symbolP;
2726 opcode_select (int width)
2733 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2734 as_bad (_("selected processor does not support THUMB opcodes"));
2737 /* No need to force the alignment, since we will have been
2738 coming from ARM mode, which is word-aligned. */
2739 record_alignment (now_seg, 1);
2746 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2747 as_bad (_("selected processor does not support ARM opcodes"));
2752 frag_align (2, 0, 0);
2754 record_alignment (now_seg, 1);
2759 as_bad (_("invalid instruction size selected (%d)"), width);
2764 s_arm (int ignore ATTRIBUTE_UNUSED)
2767 demand_empty_rest_of_line ();
2771 s_thumb (int ignore ATTRIBUTE_UNUSED)
2774 demand_empty_rest_of_line ();
2778 s_code (int unused ATTRIBUTE_UNUSED)
2782 temp = get_absolute_expression ();
2787 opcode_select (temp);
2791 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2796 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2798 /* If we are not already in thumb mode go into it, EVEN if
2799 the target processor does not support thumb instructions.
2800 This is used by gcc/config/arm/lib1funcs.asm for example
2801 to compile interworking support functions even if the
2802 target processor should not support interworking. */
2806 record_alignment (now_seg, 1);
2809 demand_empty_rest_of_line ();
2813 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2817 /* The following label is the name/address of the start of a Thumb function.
2818 We need to know this for the interworking support. */
2819 label_is_thumb_function_name = TRUE;
2822 /* Perform a .set directive, but also mark the alias as
2823 being a thumb function. */
2826 s_thumb_set (int equiv)
2828 /* XXX the following is a duplicate of the code for s_set() in read.c
2829 We cannot just call that code as we need to get at the symbol that
2836 /* Especial apologies for the random logic:
2837 This just grew, and could be parsed much more simply!
2839 name = input_line_pointer;
2840 delim = get_symbol_end ();
2841 end_name = input_line_pointer;
2844 if (*input_line_pointer != ',')
2847 as_bad (_("expected comma after name \"%s\""), name);
2849 ignore_rest_of_line ();
2853 input_line_pointer++;
2856 if (name[0] == '.' && name[1] == '\0')
2858 /* XXX - this should not happen to .thumb_set. */
2862 if ((symbolP = symbol_find (name)) == NULL
2863 && (symbolP = md_undefined_symbol (name)) == NULL)
2866 /* When doing symbol listings, play games with dummy fragments living
2867 outside the normal fragment chain to record the file and line info
2869 if (listing & LISTING_SYMBOLS)
2871 extern struct list_info_struct * listing_tail;
2872 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2874 memset (dummy_frag, 0, sizeof (fragS));
2875 dummy_frag->fr_type = rs_fill;
2876 dummy_frag->line = listing_tail;
2877 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2878 dummy_frag->fr_symbol = symbolP;
2882 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2885 /* "set" symbols are local unless otherwise specified. */
2886 SF_SET_LOCAL (symbolP);
2887 #endif /* OBJ_COFF */
2888 } /* Make a new symbol. */
2890 symbol_table_insert (symbolP);
2895 && S_IS_DEFINED (symbolP)
2896 && S_GET_SEGMENT (symbolP) != reg_section)
2897 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2899 pseudo_set (symbolP);
2901 demand_empty_rest_of_line ();
2903 /* XXX Now we come to the Thumb specific bit of code. */
2905 THUMB_SET_FUNC (symbolP, 1);
2906 ARM_SET_THUMB (symbolP, 1);
2907 #if defined OBJ_ELF || defined OBJ_COFF
2908 ARM_SET_INTERWORK (symbolP, support_interwork);
2912 /* Directives: Mode selection. */
2914 /* .syntax [unified|divided] - choose the new unified syntax
2915 (same for Arm and Thumb encoding, modulo slight differences in what
2916 can be represented) or the old divergent syntax for each mode. */
2918 s_syntax (int unused ATTRIBUTE_UNUSED)
2922 name = input_line_pointer;
2923 delim = get_symbol_end ();
2925 if (!strcasecmp (name, "unified"))
2926 unified_syntax = TRUE;
2927 else if (!strcasecmp (name, "divided"))
2928 unified_syntax = FALSE;
2931 as_bad (_("unrecognized syntax mode \"%s\""), name);
2934 *input_line_pointer = delim;
2935 demand_empty_rest_of_line ();
2938 /* Directives: sectioning and alignment. */
2940 /* Same as s_align_ptwo but align 0 => align 2. */
2943 s_align (int unused ATTRIBUTE_UNUSED)
2948 long max_alignment = 15;
2950 temp = get_absolute_expression ();
2951 if (temp > max_alignment)
2952 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2955 as_bad (_("alignment negative. 0 assumed."));
2959 if (*input_line_pointer == ',')
2961 input_line_pointer++;
2962 temp_fill = get_absolute_expression ();
2974 /* Only make a frag if we HAVE to. */
2975 if (temp && !need_pass_2)
2977 if (!fill_p && subseg_text_p (now_seg))
2978 frag_align_code (temp, 0);
2980 frag_align (temp, (int) temp_fill, 0);
2982 demand_empty_rest_of_line ();
2984 record_alignment (now_seg, temp);
2988 s_bss (int ignore ATTRIBUTE_UNUSED)
2990 /* We don't support putting frags in the BSS segment, we fake it by
2991 marking in_bss, then looking at s_skip for clues. */
2992 subseg_set (bss_section, 0);
2993 demand_empty_rest_of_line ();
2995 #ifdef md_elf_section_change_hook
2996 md_elf_section_change_hook ();
3001 s_even (int ignore ATTRIBUTE_UNUSED)
3003 /* Never make frag if expect extra pass. */
3005 frag_align (1, 0, 0);
3007 record_alignment (now_seg, 1);
3009 demand_empty_rest_of_line ();
3012 /* Directives: Literal pools. */
3014 static literal_pool *
3015 find_literal_pool (void)
3017 literal_pool * pool;
3019 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3021 if (pool->section == now_seg
3022 && pool->sub_section == now_subseg)
3029 static literal_pool *
3030 find_or_make_literal_pool (void)
3032 /* Next literal pool ID number. */
3033 static unsigned int latest_pool_num = 1;
3034 literal_pool * pool;
3036 pool = find_literal_pool ();
3040 /* Create a new pool. */
3041 pool = (literal_pool *) xmalloc (sizeof (* pool));
3045 pool->next_free_entry = 0;
3046 pool->section = now_seg;
3047 pool->sub_section = now_subseg;
3048 pool->next = list_of_pools;
3049 pool->symbol = NULL;
3051 /* Add it to the list. */
3052 list_of_pools = pool;
3055 /* New pools, and emptied pools, will have a NULL symbol. */
3056 if (pool->symbol == NULL)
3058 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3059 (valueT) 0, &zero_address_frag);
3060 pool->id = latest_pool_num ++;
3067 /* Add the literal in the global 'inst'
3068 structure to the relevant literal pool. */
3071 add_to_lit_pool (void)
3073 literal_pool * pool;
3076 pool = find_or_make_literal_pool ();
3078 /* Check if this literal value is already in the pool. */
3079 for (entry = 0; entry < pool->next_free_entry; entry ++)
3081 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3082 && (inst.reloc.exp.X_op == O_constant)
3083 && (pool->literals[entry].X_add_number
3084 == inst.reloc.exp.X_add_number)
3085 && (pool->literals[entry].X_unsigned
3086 == inst.reloc.exp.X_unsigned))
3089 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3090 && (inst.reloc.exp.X_op == O_symbol)
3091 && (pool->literals[entry].X_add_number
3092 == inst.reloc.exp.X_add_number)
3093 && (pool->literals[entry].X_add_symbol
3094 == inst.reloc.exp.X_add_symbol)
3095 && (pool->literals[entry].X_op_symbol
3096 == inst.reloc.exp.X_op_symbol))
3100 /* Do we need to create a new entry? */
3101 if (entry == pool->next_free_entry)
3103 if (entry >= MAX_LITERAL_POOL_SIZE)
3105 inst.error = _("literal pool overflow");
3109 pool->literals[entry] = inst.reloc.exp;
3111 /* PR ld/12974: Record the location of the first source line to reference
3112 this entry in the literal pool. If it turns out during linking that the
3113 symbol does not exist we will be able to give an accurate line number for
3114 the (first use of the) missing reference. */
3115 if (debug_type == DEBUG_DWARF2)
3116 dwarf2_where (pool->locs + entry);
3118 pool->next_free_entry += 1;
3121 inst.reloc.exp.X_op = O_symbol;
3122 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3123 inst.reloc.exp.X_add_symbol = pool->symbol;
3128 /* Can't use symbol_new here, so have to create a symbol and then at
3129 a later date assign it a value. Thats what these functions do. */
3132 symbol_locate (symbolS * symbolP,
3133 const char * name, /* It is copied, the caller can modify. */
3134 segT segment, /* Segment identifier (SEG_<something>). */
3135 valueT valu, /* Symbol value. */
3136 fragS * frag) /* Associated fragment. */
3138 unsigned int name_length;
3139 char * preserved_copy_of_name;
3141 name_length = strlen (name) + 1; /* +1 for \0. */
3142 obstack_grow (¬es, name, name_length);
3143 preserved_copy_of_name = (char *) obstack_finish (¬es);
3145 #ifdef tc_canonicalize_symbol_name
3146 preserved_copy_of_name =
3147 tc_canonicalize_symbol_name (preserved_copy_of_name);
3150 S_SET_NAME (symbolP, preserved_copy_of_name);
3152 S_SET_SEGMENT (symbolP, segment);
3153 S_SET_VALUE (symbolP, valu);
3154 symbol_clear_list_pointers (symbolP);
3156 symbol_set_frag (symbolP, frag);
3158 /* Link to end of symbol chain. */
3160 extern int symbol_table_frozen;
3162 if (symbol_table_frozen)
3166 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3168 obj_symbol_new_hook (symbolP);
3170 #ifdef tc_symbol_new_hook
3171 tc_symbol_new_hook (symbolP);
3175 verify_symbol_chain (symbol_rootP, symbol_lastP);
3176 #endif /* DEBUG_SYMS */
3181 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3184 literal_pool * pool;
3187 pool = find_literal_pool ();
3189 || pool->symbol == NULL
3190 || pool->next_free_entry == 0)
3193 mapping_state (MAP_DATA);
3195 /* Align pool as you have word accesses.
3196 Only make a frag if we have to. */
3198 frag_align (2, 0, 0);
3200 record_alignment (now_seg, 2);
3202 sprintf (sym_name, "$$lit_\002%x", pool->id);
3204 symbol_locate (pool->symbol, sym_name, now_seg,
3205 (valueT) frag_now_fix (), frag_now);
3206 symbol_table_insert (pool->symbol);
3208 ARM_SET_THUMB (pool->symbol, thumb_mode);
3210 #if defined OBJ_COFF || defined OBJ_ELF
3211 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3214 for (entry = 0; entry < pool->next_free_entry; entry ++)
3217 if (debug_type == DEBUG_DWARF2)
3218 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3220 /* First output the expression in the instruction to the pool. */
3221 emit_expr (&(pool->literals[entry]), 4); /* .word */
3224 /* Mark the pool as empty. */
3225 pool->next_free_entry = 0;
3226 pool->symbol = NULL;
3230 /* Forward declarations for functions below, in the MD interface
3232 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3233 static valueT create_unwind_entry (int);
3234 static void start_unwind_section (const segT, int);
3235 static void add_unwind_opcode (valueT, int);
3236 static void flush_pending_unwind (void);
3238 /* Directives: Data. */
3241 s_arm_elf_cons (int nbytes)
3245 #ifdef md_flush_pending_output
3246 md_flush_pending_output ();
3249 if (is_it_end_of_statement ())
3251 demand_empty_rest_of_line ();
3255 #ifdef md_cons_align
3256 md_cons_align (nbytes);
3259 mapping_state (MAP_DATA);
3263 char *base = input_line_pointer;
3267 if (exp.X_op != O_symbol)
3268 emit_expr (&exp, (unsigned int) nbytes);
3271 char *before_reloc = input_line_pointer;
3272 reloc = parse_reloc (&input_line_pointer);
3275 as_bad (_("unrecognized relocation suffix"));
3276 ignore_rest_of_line ();
3279 else if (reloc == BFD_RELOC_UNUSED)
3280 emit_expr (&exp, (unsigned int) nbytes);
3283 reloc_howto_type *howto = (reloc_howto_type *)
3284 bfd_reloc_type_lookup (stdoutput,
3285 (bfd_reloc_code_real_type) reloc);
3286 int size = bfd_get_reloc_size (howto);
3288 if (reloc == BFD_RELOC_ARM_PLT32)
3290 as_bad (_("(plt) is only valid on branch targets"));
3291 reloc = BFD_RELOC_UNUSED;
3296 as_bad (_("%s relocations do not fit in %d bytes"),
3297 howto->name, nbytes);
3300 /* We've parsed an expression stopping at O_symbol.
3301 But there may be more expression left now that we
3302 have parsed the relocation marker. Parse it again.
3303 XXX Surely there is a cleaner way to do this. */
3304 char *p = input_line_pointer;
3306 char *save_buf = (char *) alloca (input_line_pointer - base);
3307 memcpy (save_buf, base, input_line_pointer - base);
3308 memmove (base + (input_line_pointer - before_reloc),
3309 base, before_reloc - base);
3311 input_line_pointer = base + (input_line_pointer-before_reloc);
3313 memcpy (base, save_buf, p - base);
3315 offset = nbytes - size;
3316 p = frag_more ((int) nbytes);
3317 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3318 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3323 while (*input_line_pointer++ == ',');
3325 /* Put terminator back into stream. */
3326 input_line_pointer --;
3327 demand_empty_rest_of_line ();
3330 /* Emit an expression containing a 32-bit thumb instruction.
3331 Implementation based on put_thumb32_insn. */
3334 emit_thumb32_expr (expressionS * exp)
3336 expressionS exp_high = *exp;
3338 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3339 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3340 exp->X_add_number &= 0xffff;
3341 emit_expr (exp, (unsigned int) THUMB_SIZE);
3344 /* Guess the instruction size based on the opcode. */
3347 thumb_insn_size (int opcode)
3349 if ((unsigned int) opcode < 0xe800u)
3351 else if ((unsigned int) opcode >= 0xe8000000u)
3358 emit_insn (expressionS *exp, int nbytes)
3362 if (exp->X_op == O_constant)
3367 size = thumb_insn_size (exp->X_add_number);
3371 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3373 as_bad (_(".inst.n operand too big. "\
3374 "Use .inst.w instead"));
3379 if (now_it.state == AUTOMATIC_IT_BLOCK)
3380 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3382 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3384 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3385 emit_thumb32_expr (exp);
3387 emit_expr (exp, (unsigned int) size);
3389 it_fsm_post_encode ();
3393 as_bad (_("cannot determine Thumb instruction size. " \
3394 "Use .inst.n/.inst.w instead"));
3397 as_bad (_("constant expression required"));
3402 /* Like s_arm_elf_cons but do not use md_cons_align and
3403 set the mapping state to MAP_ARM/MAP_THUMB. */
3406 s_arm_elf_inst (int nbytes)
3408 if (is_it_end_of_statement ())
3410 demand_empty_rest_of_line ();
3414 /* Calling mapping_state () here will not change ARM/THUMB,
3415 but will ensure not to be in DATA state. */
3418 mapping_state (MAP_THUMB);
3423 as_bad (_("width suffixes are invalid in ARM mode"));
3424 ignore_rest_of_line ();
3430 mapping_state (MAP_ARM);
3439 if (! emit_insn (& exp, nbytes))
3441 ignore_rest_of_line ();
3445 while (*input_line_pointer++ == ',');
3447 /* Put terminator back into stream. */
3448 input_line_pointer --;
3449 demand_empty_rest_of_line ();
3452 /* Parse a .rel31 directive. */
3455 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3462 if (*input_line_pointer == '1')
3463 highbit = 0x80000000;
3464 else if (*input_line_pointer != '0')
3465 as_bad (_("expected 0 or 1"));
3467 input_line_pointer++;
3468 if (*input_line_pointer != ',')
3469 as_bad (_("missing comma"));
3470 input_line_pointer++;
3472 #ifdef md_flush_pending_output
3473 md_flush_pending_output ();
3476 #ifdef md_cons_align
3480 mapping_state (MAP_DATA);
3485 md_number_to_chars (p, highbit, 4);
3486 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3487 BFD_RELOC_ARM_PREL31);
3489 demand_empty_rest_of_line ();
3492 /* Directives: AEABI stack-unwind tables. */
3494 /* Parse an unwind_fnstart directive. Simply records the current location. */
3497 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3499 demand_empty_rest_of_line ();
3500 if (unwind.proc_start)
3502 as_bad (_("duplicate .fnstart directive"));
3506 /* Mark the start of the function. */
3507 unwind.proc_start = expr_build_dot ();
3509 /* Reset the rest of the unwind info. */
3510 unwind.opcode_count = 0;
3511 unwind.table_entry = NULL;
3512 unwind.personality_routine = NULL;
3513 unwind.personality_index = -1;
3514 unwind.frame_size = 0;
3515 unwind.fp_offset = 0;
3516 unwind.fp_reg = REG_SP;
3518 unwind.sp_restored = 0;
3522 /* Parse a handlerdata directive. Creates the exception handling table entry
3523 for the function. */
3526 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3528 demand_empty_rest_of_line ();
3529 if (!unwind.proc_start)
3530 as_bad (MISSING_FNSTART);
3532 if (unwind.table_entry)
3533 as_bad (_("duplicate .handlerdata directive"));
3535 create_unwind_entry (1);
3538 /* Parse an unwind_fnend directive. Generates the index table entry. */
3541 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3546 unsigned int marked_pr_dependency;
3548 demand_empty_rest_of_line ();
3550 if (!unwind.proc_start)
3552 as_bad (_(".fnend directive without .fnstart"));
3556 /* Add eh table entry. */
3557 if (unwind.table_entry == NULL)
3558 val = create_unwind_entry (0);
3562 /* Add index table entry. This is two words. */
3563 start_unwind_section (unwind.saved_seg, 1);
3564 frag_align (2, 0, 0);
3565 record_alignment (now_seg, 2);
3567 ptr = frag_more (8);
3569 where = frag_now_fix () - 8;
3571 /* Self relative offset of the function start. */
3572 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3573 BFD_RELOC_ARM_PREL31);
3575 /* Indicate dependency on EHABI-defined personality routines to the
3576 linker, if it hasn't been done already. */
3577 marked_pr_dependency
3578 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3579 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3580 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3582 static const char *const name[] =
3584 "__aeabi_unwind_cpp_pr0",
3585 "__aeabi_unwind_cpp_pr1",
3586 "__aeabi_unwind_cpp_pr2"
3588 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3589 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3590 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3591 |= 1 << unwind.personality_index;
3595 /* Inline exception table entry. */
3596 md_number_to_chars (ptr + 4, val, 4);
3598 /* Self relative offset of the table entry. */
3599 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3600 BFD_RELOC_ARM_PREL31);
3602 /* Restore the original section. */
3603 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3605 unwind.proc_start = NULL;
3609 /* Parse an unwind_cantunwind directive. */
3612 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3614 demand_empty_rest_of_line ();
3615 if (!unwind.proc_start)
3616 as_bad (MISSING_FNSTART);
3618 if (unwind.personality_routine || unwind.personality_index != -1)
3619 as_bad (_("personality routine specified for cantunwind frame"));
3621 unwind.personality_index = -2;
3625 /* Parse a personalityindex directive. */
3628 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3632 if (!unwind.proc_start)
3633 as_bad (MISSING_FNSTART);
3635 if (unwind.personality_routine || unwind.personality_index != -1)
3636 as_bad (_("duplicate .personalityindex directive"));
3640 if (exp.X_op != O_constant
3641 || exp.X_add_number < 0 || exp.X_add_number > 15)
3643 as_bad (_("bad personality routine number"));
3644 ignore_rest_of_line ();
3648 unwind.personality_index = exp.X_add_number;
3650 demand_empty_rest_of_line ();
3654 /* Parse a personality directive. */
3657 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3661 if (!unwind.proc_start)
3662 as_bad (MISSING_FNSTART);
3664 if (unwind.personality_routine || unwind.personality_index != -1)
3665 as_bad (_("duplicate .personality directive"));
3667 name = input_line_pointer;
3668 c = get_symbol_end ();
3669 p = input_line_pointer;
3670 unwind.personality_routine = symbol_find_or_make (name);
3672 demand_empty_rest_of_line ();
3676 /* Parse a directive saving core registers. */
3679 s_arm_unwind_save_core (void)
3685 range = parse_reg_list (&input_line_pointer);
3688 as_bad (_("expected register list"));
3689 ignore_rest_of_line ();
3693 demand_empty_rest_of_line ();
3695 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3696 into .unwind_save {..., sp...}. We aren't bothered about the value of
3697 ip because it is clobbered by calls. */
3698 if (unwind.sp_restored && unwind.fp_reg == 12
3699 && (range & 0x3000) == 0x1000)
3701 unwind.opcode_count--;
3702 unwind.sp_restored = 0;
3703 range = (range | 0x2000) & ~0x1000;
3704 unwind.pending_offset = 0;
3710 /* See if we can use the short opcodes. These pop a block of up to 8
3711 registers starting with r4, plus maybe r14. */
3712 for (n = 0; n < 8; n++)
3714 /* Break at the first non-saved register. */
3715 if ((range & (1 << (n + 4))) == 0)
3718 /* See if there are any other bits set. */
3719 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3721 /* Use the long form. */
3722 op = 0x8000 | ((range >> 4) & 0xfff);
3723 add_unwind_opcode (op, 2);
3727 /* Use the short form. */
3729 op = 0xa8; /* Pop r14. */
3731 op = 0xa0; /* Do not pop r14. */
3733 add_unwind_opcode (op, 1);
3740 op = 0xb100 | (range & 0xf);
3741 add_unwind_opcode (op, 2);
3744 /* Record the number of bytes pushed. */
3745 for (n = 0; n < 16; n++)
3747 if (range & (1 << n))
3748 unwind.frame_size += 4;
3753 /* Parse a directive saving FPA registers. */
3756 s_arm_unwind_save_fpa (int reg)
3762 /* Get Number of registers to transfer. */
3763 if (skip_past_comma (&input_line_pointer) != FAIL)
3766 exp.X_op = O_illegal;
3768 if (exp.X_op != O_constant)
3770 as_bad (_("expected , <constant>"));
3771 ignore_rest_of_line ();
3775 num_regs = exp.X_add_number;
3777 if (num_regs < 1 || num_regs > 4)
3779 as_bad (_("number of registers must be in the range [1:4]"));
3780 ignore_rest_of_line ();
3784 demand_empty_rest_of_line ();
3789 op = 0xb4 | (num_regs - 1);
3790 add_unwind_opcode (op, 1);
3795 op = 0xc800 | (reg << 4) | (num_regs - 1);
3796 add_unwind_opcode (op, 2);
3798 unwind.frame_size += num_regs * 12;
3802 /* Parse a directive saving VFP registers for ARMv6 and above. */
3805 s_arm_unwind_save_vfp_armv6 (void)
3810 int num_vfpv3_regs = 0;
3811 int num_regs_below_16;
3813 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3816 as_bad (_("expected register list"));
3817 ignore_rest_of_line ();
3821 demand_empty_rest_of_line ();
3823 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3824 than FSTMX/FLDMX-style ones). */
3826 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3828 num_vfpv3_regs = count;
3829 else if (start + count > 16)
3830 num_vfpv3_regs = start + count - 16;
3832 if (num_vfpv3_regs > 0)
3834 int start_offset = start > 16 ? start - 16 : 0;
3835 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3836 add_unwind_opcode (op, 2);
3839 /* Generate opcode for registers numbered in the range 0 .. 15. */
3840 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3841 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3842 if (num_regs_below_16 > 0)
3844 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3845 add_unwind_opcode (op, 2);
3848 unwind.frame_size += count * 8;
3852 /* Parse a directive saving VFP registers for pre-ARMv6. */
3855 s_arm_unwind_save_vfp (void)
3861 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3864 as_bad (_("expected register list"));
3865 ignore_rest_of_line ();
3869 demand_empty_rest_of_line ();
3874 op = 0xb8 | (count - 1);
3875 add_unwind_opcode (op, 1);
3880 op = 0xb300 | (reg << 4) | (count - 1);
3881 add_unwind_opcode (op, 2);
3883 unwind.frame_size += count * 8 + 4;
3887 /* Parse a directive saving iWMMXt data registers. */
3890 s_arm_unwind_save_mmxwr (void)
3898 if (*input_line_pointer == '{')
3899 input_line_pointer++;
3903 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3907 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3912 as_tsktsk (_("register list not in ascending order"));
3915 if (*input_line_pointer == '-')
3917 input_line_pointer++;
3918 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3921 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3924 else if (reg >= hi_reg)
3926 as_bad (_("bad register range"));
3929 for (; reg < hi_reg; reg++)
3933 while (skip_past_comma (&input_line_pointer) != FAIL);
3935 if (*input_line_pointer == '}')
3936 input_line_pointer++;
3938 demand_empty_rest_of_line ();
3940 /* Generate any deferred opcodes because we're going to be looking at
3942 flush_pending_unwind ();
3944 for (i = 0; i < 16; i++)
3946 if (mask & (1 << i))
3947 unwind.frame_size += 8;
3950 /* Attempt to combine with a previous opcode. We do this because gcc
3951 likes to output separate unwind directives for a single block of
3953 if (unwind.opcode_count > 0)
3955 i = unwind.opcodes[unwind.opcode_count - 1];
3956 if ((i & 0xf8) == 0xc0)
3959 /* Only merge if the blocks are contiguous. */
3962 if ((mask & 0xfe00) == (1 << 9))
3964 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3965 unwind.opcode_count--;
3968 else if (i == 6 && unwind.opcode_count >= 2)
3970 i = unwind.opcodes[unwind.opcode_count - 2];
3974 op = 0xffff << (reg - 1);
3976 && ((mask & op) == (1u << (reg - 1))))
3978 op = (1 << (reg + i + 1)) - 1;
3979 op &= ~((1 << reg) - 1);
3981 unwind.opcode_count -= 2;
3988 /* We want to generate opcodes in the order the registers have been
3989 saved, ie. descending order. */
3990 for (reg = 15; reg >= -1; reg--)
3992 /* Save registers in blocks. */
3994 || !(mask & (1 << reg)))
3996 /* We found an unsaved reg. Generate opcodes to save the
4003 op = 0xc0 | (hi_reg - 10);
4004 add_unwind_opcode (op, 1);
4009 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4010 add_unwind_opcode (op, 2);
4019 ignore_rest_of_line ();
4023 s_arm_unwind_save_mmxwcg (void)
4030 if (*input_line_pointer == '{')
4031 input_line_pointer++;
4035 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4039 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4045 as_tsktsk (_("register list not in ascending order"));
4048 if (*input_line_pointer == '-')
4050 input_line_pointer++;
4051 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4054 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4057 else if (reg >= hi_reg)
4059 as_bad (_("bad register range"));
4062 for (; reg < hi_reg; reg++)
4066 while (skip_past_comma (&input_line_pointer) != FAIL);
4068 if (*input_line_pointer == '}')
4069 input_line_pointer++;
4071 demand_empty_rest_of_line ();
4073 /* Generate any deferred opcodes because we're going to be looking at
4075 flush_pending_unwind ();
4077 for (reg = 0; reg < 16; reg++)
4079 if (mask & (1 << reg))
4080 unwind.frame_size += 4;
4083 add_unwind_opcode (op, 2);
4086 ignore_rest_of_line ();
4090 /* Parse an unwind_save directive.
4091 If the argument is non-zero, this is a .vsave directive. */
4094 s_arm_unwind_save (int arch_v6)
4097 struct reg_entry *reg;
4098 bfd_boolean had_brace = FALSE;
4100 if (!unwind.proc_start)
4101 as_bad (MISSING_FNSTART);
4103 /* Figure out what sort of save we have. */
4104 peek = input_line_pointer;
4112 reg = arm_reg_parse_multi (&peek);
4116 as_bad (_("register expected"));
4117 ignore_rest_of_line ();
4126 as_bad (_("FPA .unwind_save does not take a register list"));
4127 ignore_rest_of_line ();
4130 input_line_pointer = peek;
4131 s_arm_unwind_save_fpa (reg->number);
4134 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4137 s_arm_unwind_save_vfp_armv6 ();
4139 s_arm_unwind_save_vfp ();
4141 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4142 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4145 as_bad (_(".unwind_save does not support this kind of register"));
4146 ignore_rest_of_line ();
4151 /* Parse an unwind_movsp directive. */
4154 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4160 if (!unwind.proc_start)
4161 as_bad (MISSING_FNSTART);
4163 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4166 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4167 ignore_rest_of_line ();
4171 /* Optional constant. */
4172 if (skip_past_comma (&input_line_pointer) != FAIL)
4174 if (immediate_for_directive (&offset) == FAIL)
4180 demand_empty_rest_of_line ();
4182 if (reg == REG_SP || reg == REG_PC)
4184 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4188 if (unwind.fp_reg != REG_SP)
4189 as_bad (_("unexpected .unwind_movsp directive"));
4191 /* Generate opcode to restore the value. */
4193 add_unwind_opcode (op, 1);
4195 /* Record the information for later. */
4196 unwind.fp_reg = reg;
4197 unwind.fp_offset = unwind.frame_size - offset;
4198 unwind.sp_restored = 1;
4201 /* Parse an unwind_pad directive. */
4204 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4208 if (!unwind.proc_start)
4209 as_bad (MISSING_FNSTART);
4211 if (immediate_for_directive (&offset) == FAIL)
4216 as_bad (_("stack increment must be multiple of 4"));
4217 ignore_rest_of_line ();
4221 /* Don't generate any opcodes, just record the details for later. */
4222 unwind.frame_size += offset;
4223 unwind.pending_offset += offset;
4225 demand_empty_rest_of_line ();
4228 /* Parse an unwind_setfp directive. */
4231 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4237 if (!unwind.proc_start)
4238 as_bad (MISSING_FNSTART);
4240 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4241 if (skip_past_comma (&input_line_pointer) == FAIL)
4244 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4246 if (fp_reg == FAIL || sp_reg == FAIL)
4248 as_bad (_("expected <reg>, <reg>"));
4249 ignore_rest_of_line ();
4253 /* Optional constant. */
4254 if (skip_past_comma (&input_line_pointer) != FAIL)
4256 if (immediate_for_directive (&offset) == FAIL)
4262 demand_empty_rest_of_line ();
4264 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4266 as_bad (_("register must be either sp or set by a previous"
4267 "unwind_movsp directive"));
4271 /* Don't generate any opcodes, just record the information for later. */
4272 unwind.fp_reg = fp_reg;
4274 if (sp_reg == REG_SP)
4275 unwind.fp_offset = unwind.frame_size - offset;
4277 unwind.fp_offset -= offset;
4280 /* Parse an unwind_raw directive. */
4283 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4286 /* This is an arbitrary limit. */
4287 unsigned char op[16];
4290 if (!unwind.proc_start)
4291 as_bad (MISSING_FNSTART);
4294 if (exp.X_op == O_constant
4295 && skip_past_comma (&input_line_pointer) != FAIL)
4297 unwind.frame_size += exp.X_add_number;
4301 exp.X_op = O_illegal;
4303 if (exp.X_op != O_constant)
4305 as_bad (_("expected <offset>, <opcode>"));
4306 ignore_rest_of_line ();
4312 /* Parse the opcode. */
4317 as_bad (_("unwind opcode too long"));
4318 ignore_rest_of_line ();
4320 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4322 as_bad (_("invalid unwind opcode"));
4323 ignore_rest_of_line ();
4326 op[count++] = exp.X_add_number;
4328 /* Parse the next byte. */
4329 if (skip_past_comma (&input_line_pointer) == FAIL)
4335 /* Add the opcode bytes in reverse order. */
4337 add_unwind_opcode (op[count], 1);
4339 demand_empty_rest_of_line ();
4343 /* Parse a .eabi_attribute directive. */
4346 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4348 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4350 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4351 attributes_set_explicitly[tag] = 1;
4354 /* Emit a tls fix for the symbol. */
4357 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4361 #ifdef md_flush_pending_output
4362 md_flush_pending_output ();
4365 #ifdef md_cons_align
4369 /* Since we're just labelling the code, there's no need to define a
4372 p = obstack_next_free (&frchain_now->frch_obstack);
4373 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4374 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4375 : BFD_RELOC_ARM_TLS_DESCSEQ);
4377 #endif /* OBJ_ELF */
4379 static void s_arm_arch (int);
4380 static void s_arm_object_arch (int);
4381 static void s_arm_cpu (int);
4382 static void s_arm_fpu (int);
4383 static void s_arm_arch_extension (int);
4388 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4395 if (exp.X_op == O_symbol)
4396 exp.X_op = O_secrel;
4398 emit_expr (&exp, 4);
4400 while (*input_line_pointer++ == ',');
4402 input_line_pointer--;
4403 demand_empty_rest_of_line ();
4407 /* This table describes all the machine specific pseudo-ops the assembler
4408 has to support. The fields are:
4409 pseudo-op name without dot
4410 function to call to execute this pseudo-op
4411 Integer arg to pass to the function. */
4413 const pseudo_typeS md_pseudo_table[] =
4415 /* Never called because '.req' does not start a line. */
4416 { "req", s_req, 0 },
4417 /* Following two are likewise never called. */
4420 { "unreq", s_unreq, 0 },
4421 { "bss", s_bss, 0 },
4422 { "align", s_align, 0 },
4423 { "arm", s_arm, 0 },
4424 { "thumb", s_thumb, 0 },
4425 { "code", s_code, 0 },
4426 { "force_thumb", s_force_thumb, 0 },
4427 { "thumb_func", s_thumb_func, 0 },
4428 { "thumb_set", s_thumb_set, 0 },
4429 { "even", s_even, 0 },
4430 { "ltorg", s_ltorg, 0 },
4431 { "pool", s_ltorg, 0 },
4432 { "syntax", s_syntax, 0 },
4433 { "cpu", s_arm_cpu, 0 },
4434 { "arch", s_arm_arch, 0 },
4435 { "object_arch", s_arm_object_arch, 0 },
4436 { "fpu", s_arm_fpu, 0 },
4437 { "arch_extension", s_arm_arch_extension, 0 },
4439 { "word", s_arm_elf_cons, 4 },
4440 { "long", s_arm_elf_cons, 4 },
4441 { "inst.n", s_arm_elf_inst, 2 },
4442 { "inst.w", s_arm_elf_inst, 4 },
4443 { "inst", s_arm_elf_inst, 0 },
4444 { "rel31", s_arm_rel31, 0 },
4445 { "fnstart", s_arm_unwind_fnstart, 0 },
4446 { "fnend", s_arm_unwind_fnend, 0 },
4447 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4448 { "personality", s_arm_unwind_personality, 0 },
4449 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4450 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4451 { "save", s_arm_unwind_save, 0 },
4452 { "vsave", s_arm_unwind_save, 1 },
4453 { "movsp", s_arm_unwind_movsp, 0 },
4454 { "pad", s_arm_unwind_pad, 0 },
4455 { "setfp", s_arm_unwind_setfp, 0 },
4456 { "unwind_raw", s_arm_unwind_raw, 0 },
4457 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4458 { "tlsdescseq", s_arm_tls_descseq, 0 },
4462 /* These are used for dwarf. */
4466 /* These are used for dwarf2. */
4467 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4468 { "loc", dwarf2_directive_loc, 0 },
4469 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4471 { "extend", float_cons, 'x' },
4472 { "ldouble", float_cons, 'x' },
4473 { "packed", float_cons, 'p' },
4475 {"secrel32", pe_directive_secrel, 0},
4480 /* Parser functions used exclusively in instruction operands. */
4482 /* Generic immediate-value read function for use in insn parsing.
4483 STR points to the beginning of the immediate (the leading #);
4484 VAL receives the value; if the value is outside [MIN, MAX]
4485 issue an error. PREFIX_OPT is true if the immediate prefix is
4489 parse_immediate (char **str, int *val, int min, int max,
4490 bfd_boolean prefix_opt)
4493 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4494 if (exp.X_op != O_constant)
4496 inst.error = _("constant expression required");
4500 if (exp.X_add_number < min || exp.X_add_number > max)
4502 inst.error = _("immediate value out of range");
4506 *val = exp.X_add_number;
4510 /* Less-generic immediate-value read function with the possibility of loading a
4511 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4512 instructions. Puts the result directly in inst.operands[i]. */
4515 parse_big_immediate (char **str, int i)
4520 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4522 if (exp.X_op == O_constant)
4524 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4525 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4526 O_constant. We have to be careful not to break compilation for
4527 32-bit X_add_number, though. */
4528 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4530 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4531 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4532 inst.operands[i].regisimm = 1;
4535 else if (exp.X_op == O_big
4536 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4538 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4540 /* Bignums have their least significant bits in
4541 generic_bignum[0]. Make sure we put 32 bits in imm and
4542 32 bits in reg, in a (hopefully) portable way. */
4543 gas_assert (parts != 0);
4545 /* Make sure that the number is not too big.
4546 PR 11972: Bignums can now be sign-extended to the
4547 size of a .octa so check that the out of range bits
4548 are all zero or all one. */
4549 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4551 LITTLENUM_TYPE m = -1;
4553 if (generic_bignum[parts * 2] != 0
4554 && generic_bignum[parts * 2] != m)
4557 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4558 if (generic_bignum[j] != generic_bignum[j-1])
4562 inst.operands[i].imm = 0;
4563 for (j = 0; j < parts; j++, idx++)
4564 inst.operands[i].imm |= generic_bignum[idx]
4565 << (LITTLENUM_NUMBER_OF_BITS * j);
4566 inst.operands[i].reg = 0;
4567 for (j = 0; j < parts; j++, idx++)
4568 inst.operands[i].reg |= generic_bignum[idx]
4569 << (LITTLENUM_NUMBER_OF_BITS * j);
4570 inst.operands[i].regisimm = 1;
4580 /* Returns the pseudo-register number of an FPA immediate constant,
4581 or FAIL if there isn't a valid constant here. */
4584 parse_fpa_immediate (char ** str)
4586 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4592 /* First try and match exact strings, this is to guarantee
4593 that some formats will work even for cross assembly. */
4595 for (i = 0; fp_const[i]; i++)
4597 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4601 *str += strlen (fp_const[i]);
4602 if (is_end_of_line[(unsigned char) **str])
4608 /* Just because we didn't get a match doesn't mean that the constant
4609 isn't valid, just that it is in a format that we don't
4610 automatically recognize. Try parsing it with the standard
4611 expression routines. */
4613 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4615 /* Look for a raw floating point number. */
4616 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4617 && is_end_of_line[(unsigned char) *save_in])
4619 for (i = 0; i < NUM_FLOAT_VALS; i++)
4621 for (j = 0; j < MAX_LITTLENUMS; j++)
4623 if (words[j] != fp_values[i][j])
4627 if (j == MAX_LITTLENUMS)
4635 /* Try and parse a more complex expression, this will probably fail
4636 unless the code uses a floating point prefix (eg "0f"). */
4637 save_in = input_line_pointer;
4638 input_line_pointer = *str;
4639 if (expression (&exp) == absolute_section
4640 && exp.X_op == O_big
4641 && exp.X_add_number < 0)
4643 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4645 if (gen_to_words (words, 5, (long) 15) == 0)
4647 for (i = 0; i < NUM_FLOAT_VALS; i++)
4649 for (j = 0; j < MAX_LITTLENUMS; j++)
4651 if (words[j] != fp_values[i][j])
4655 if (j == MAX_LITTLENUMS)
4657 *str = input_line_pointer;
4658 input_line_pointer = save_in;
4665 *str = input_line_pointer;
4666 input_line_pointer = save_in;
4667 inst.error = _("invalid FPA immediate expression");
4671 /* Returns 1 if a number has "quarter-precision" float format
4672 0baBbbbbbc defgh000 00000000 00000000. */
4675 is_quarter_float (unsigned imm)
4677 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4678 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4681 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4682 0baBbbbbbc defgh000 00000000 00000000.
4683 The zero and minus-zero cases need special handling, since they can't be
4684 encoded in the "quarter-precision" float format, but can nonetheless be
4685 loaded as integer constants. */
4688 parse_qfloat_immediate (char **ccp, int *immed)
4692 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4693 int found_fpchar = 0;
4695 skip_past_char (&str, '#');
4697 /* We must not accidentally parse an integer as a floating-point number. Make
4698 sure that the value we parse is not an integer by checking for special
4699 characters '.' or 'e'.
4700 FIXME: This is a horrible hack, but doing better is tricky because type
4701 information isn't in a very usable state at parse time. */
4703 skip_whitespace (fpnum);
4705 if (strncmp (fpnum, "0x", 2) == 0)
4709 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4710 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4720 if ((str = atof_ieee (str, 's', words)) != NULL)
4722 unsigned fpword = 0;
4725 /* Our FP word must be 32 bits (single-precision FP). */
4726 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4728 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4732 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4745 /* Shift operands. */
4748 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4751 struct asm_shift_name
4754 enum shift_kind kind;
4757 /* Third argument to parse_shift. */
4758 enum parse_shift_mode
4760 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4761 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4762 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4763 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4764 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4767 /* Parse a <shift> specifier on an ARM data processing instruction.
4768 This has three forms:
4770 (LSL|LSR|ASL|ASR|ROR) Rs
4771 (LSL|LSR|ASL|ASR|ROR) #imm
4774 Note that ASL is assimilated to LSL in the instruction encoding, and
4775 RRX to ROR #0 (which cannot be written as such). */
4778 parse_shift (char **str, int i, enum parse_shift_mode mode)
4780 const struct asm_shift_name *shift_name;
4781 enum shift_kind shift;
4786 for (p = *str; ISALPHA (*p); p++)
4791 inst.error = _("shift expression expected");
4795 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4798 if (shift_name == NULL)
4800 inst.error = _("shift expression expected");
4804 shift = shift_name->kind;
4808 case NO_SHIFT_RESTRICT:
4809 case SHIFT_IMMEDIATE: break;
4811 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4812 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4814 inst.error = _("'LSL' or 'ASR' required");
4819 case SHIFT_LSL_IMMEDIATE:
4820 if (shift != SHIFT_LSL)
4822 inst.error = _("'LSL' required");
4827 case SHIFT_ASR_IMMEDIATE:
4828 if (shift != SHIFT_ASR)
4830 inst.error = _("'ASR' required");
4838 if (shift != SHIFT_RRX)
4840 /* Whitespace can appear here if the next thing is a bare digit. */
4841 skip_whitespace (p);
4843 if (mode == NO_SHIFT_RESTRICT
4844 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4846 inst.operands[i].imm = reg;
4847 inst.operands[i].immisreg = 1;
4849 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4852 inst.operands[i].shift_kind = shift;
4853 inst.operands[i].shifted = 1;
4858 /* Parse a <shifter_operand> for an ARM data processing instruction:
4861 #<immediate>, <rotate>
4865 where <shift> is defined by parse_shift above, and <rotate> is a
4866 multiple of 2 between 0 and 30. Validation of immediate operands
4867 is deferred to md_apply_fix. */
4870 parse_shifter_operand (char **str, int i)
4875 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4877 inst.operands[i].reg = value;
4878 inst.operands[i].isreg = 1;
4880 /* parse_shift will override this if appropriate */
4881 inst.reloc.exp.X_op = O_constant;
4882 inst.reloc.exp.X_add_number = 0;
4884 if (skip_past_comma (str) == FAIL)
4887 /* Shift operation on register. */
4888 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4891 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4894 if (skip_past_comma (str) == SUCCESS)
4896 /* #x, y -- ie explicit rotation by Y. */
4897 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4900 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4902 inst.error = _("constant expression expected");
4906 value = exp.X_add_number;
4907 if (value < 0 || value > 30 || value % 2 != 0)
4909 inst.error = _("invalid rotation");
4912 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4914 inst.error = _("invalid constant");
4918 /* Encode as specified. */
4919 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4923 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4924 inst.reloc.pc_rel = 0;
4928 /* Group relocation information. Each entry in the table contains the
4929 textual name of the relocation as may appear in assembler source
4930 and must end with a colon.
4931 Along with this textual name are the relocation codes to be used if
4932 the corresponding instruction is an ALU instruction (ADD or SUB only),
4933 an LDR, an LDRS, or an LDC. */
4935 struct group_reloc_table_entry
4946 /* Varieties of non-ALU group relocation. */
4953 static struct group_reloc_table_entry group_reloc_table[] =
4954 { /* Program counter relative: */
4956 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4961 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4962 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4963 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4964 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4966 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4971 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4972 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4973 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4974 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4976 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4977 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4978 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4979 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4980 /* Section base relative */
4982 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4987 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4988 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4989 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4990 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4992 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4997 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4998 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4999 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5000 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5002 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5003 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5004 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5005 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5007 /* Given the address of a pointer pointing to the textual name of a group
5008 relocation as may appear in assembler source, attempt to find its details
5009 in group_reloc_table. The pointer will be updated to the character after
5010 the trailing colon. On failure, FAIL will be returned; SUCCESS
5011 otherwise. On success, *entry will be updated to point at the relevant
5012 group_reloc_table entry. */
5015 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5018 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5020 int length = strlen (group_reloc_table[i].name);
5022 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5023 && (*str)[length] == ':')
5025 *out = &group_reloc_table[i];
5026 *str += (length + 1);
5034 /* Parse a <shifter_operand> for an ARM data processing instruction
5035 (as for parse_shifter_operand) where group relocations are allowed:
5038 #<immediate>, <rotate>
5039 #:<group_reloc>:<expression>
5043 where <group_reloc> is one of the strings defined in group_reloc_table.
5044 The hashes are optional.
5046 Everything else is as for parse_shifter_operand. */
5048 static parse_operand_result
5049 parse_shifter_operand_group_reloc (char **str, int i)
5051 /* Determine if we have the sequence of characters #: or just :
5052 coming next. If we do, then we check for a group relocation.
5053 If we don't, punt the whole lot to parse_shifter_operand. */
5055 if (((*str)[0] == '#' && (*str)[1] == ':')
5056 || (*str)[0] == ':')
5058 struct group_reloc_table_entry *entry;
5060 if ((*str)[0] == '#')
5065 /* Try to parse a group relocation. Anything else is an error. */
5066 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5068 inst.error = _("unknown group relocation");
5069 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5072 /* We now have the group relocation table entry corresponding to
5073 the name in the assembler source. Next, we parse the expression. */
5074 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5075 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5077 /* Record the relocation type (always the ALU variant here). */
5078 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5079 gas_assert (inst.reloc.type != 0);
5081 return PARSE_OPERAND_SUCCESS;
5084 return parse_shifter_operand (str, i) == SUCCESS
5085 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5087 /* Never reached. */
5090 /* Parse a Neon alignment expression. Information is written to
5091 inst.operands[i]. We assume the initial ':' has been skipped.
5093 align .imm = align << 8, .immisalign=1, .preind=0 */
5094 static parse_operand_result
5095 parse_neon_alignment (char **str, int i)
5100 my_get_expression (&exp, &p, GE_NO_PREFIX);
5102 if (exp.X_op != O_constant)
5104 inst.error = _("alignment must be constant");
5105 return PARSE_OPERAND_FAIL;
5108 inst.operands[i].imm = exp.X_add_number << 8;
5109 inst.operands[i].immisalign = 1;
5110 /* Alignments are not pre-indexes. */
5111 inst.operands[i].preind = 0;
5114 return PARSE_OPERAND_SUCCESS;
5117 /* Parse all forms of an ARM address expression. Information is written
5118 to inst.operands[i] and/or inst.reloc.
5120 Preindexed addressing (.preind=1):
5122 [Rn, #offset] .reg=Rn .reloc.exp=offset
5123 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5124 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5125 .shift_kind=shift .reloc.exp=shift_imm
5127 These three may have a trailing ! which causes .writeback to be set also.
5129 Postindexed addressing (.postind=1, .writeback=1):
5131 [Rn], #offset .reg=Rn .reloc.exp=offset
5132 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5133 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5134 .shift_kind=shift .reloc.exp=shift_imm
5136 Unindexed addressing (.preind=0, .postind=0):
5138 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5142 [Rn]{!} shorthand for [Rn,#0]{!}
5143 =immediate .isreg=0 .reloc.exp=immediate
5144 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5146 It is the caller's responsibility to check for addressing modes not
5147 supported by the instruction, and to set inst.reloc.type. */
5149 static parse_operand_result
5150 parse_address_main (char **str, int i, int group_relocations,
5151 group_reloc_type group_type)
5156 if (skip_past_char (&p, '[') == FAIL)
5158 if (skip_past_char (&p, '=') == FAIL)
5160 /* Bare address - translate to PC-relative offset. */
5161 inst.reloc.pc_rel = 1;
5162 inst.operands[i].reg = REG_PC;
5163 inst.operands[i].isreg = 1;
5164 inst.operands[i].preind = 1;
5166 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5168 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5169 return PARSE_OPERAND_FAIL;
5172 return PARSE_OPERAND_SUCCESS;
5175 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5176 skip_whitespace (p);
5178 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5180 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5181 return PARSE_OPERAND_FAIL;
5183 inst.operands[i].reg = reg;
5184 inst.operands[i].isreg = 1;
5186 if (skip_past_comma (&p) == SUCCESS)
5188 inst.operands[i].preind = 1;
5191 else if (*p == '-') p++, inst.operands[i].negative = 1;
5193 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5195 inst.operands[i].imm = reg;
5196 inst.operands[i].immisreg = 1;
5198 if (skip_past_comma (&p) == SUCCESS)
5199 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5200 return PARSE_OPERAND_FAIL;
5202 else if (skip_past_char (&p, ':') == SUCCESS)
5204 /* FIXME: '@' should be used here, but it's filtered out by generic
5205 code before we get to see it here. This may be subject to
5207 parse_operand_result result = parse_neon_alignment (&p, i);
5209 if (result != PARSE_OPERAND_SUCCESS)
5214 if (inst.operands[i].negative)
5216 inst.operands[i].negative = 0;
5220 if (group_relocations
5221 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5223 struct group_reloc_table_entry *entry;
5225 /* Skip over the #: or : sequence. */
5231 /* Try to parse a group relocation. Anything else is an
5233 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5235 inst.error = _("unknown group relocation");
5236 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5239 /* We now have the group relocation table entry corresponding to
5240 the name in the assembler source. Next, we parse the
5242 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5243 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5245 /* Record the relocation type. */
5249 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5253 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5257 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5264 if (inst.reloc.type == 0)
5266 inst.error = _("this group relocation is not allowed on this instruction");
5267 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5273 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5274 return PARSE_OPERAND_FAIL;
5275 /* If the offset is 0, find out if it's a +0 or -0. */
5276 if (inst.reloc.exp.X_op == O_constant
5277 && inst.reloc.exp.X_add_number == 0)
5279 skip_whitespace (q);
5283 skip_whitespace (q);
5286 inst.operands[i].negative = 1;
5291 else if (skip_past_char (&p, ':') == SUCCESS)
5293 /* FIXME: '@' should be used here, but it's filtered out by generic code
5294 before we get to see it here. This may be subject to change. */
5295 parse_operand_result result = parse_neon_alignment (&p, i);
5297 if (result != PARSE_OPERAND_SUCCESS)
5301 if (skip_past_char (&p, ']') == FAIL)
5303 inst.error = _("']' expected");
5304 return PARSE_OPERAND_FAIL;
5307 if (skip_past_char (&p, '!') == SUCCESS)
5308 inst.operands[i].writeback = 1;
5310 else if (skip_past_comma (&p) == SUCCESS)
5312 if (skip_past_char (&p, '{') == SUCCESS)
5314 /* [Rn], {expr} - unindexed, with option */
5315 if (parse_immediate (&p, &inst.operands[i].imm,
5316 0, 255, TRUE) == FAIL)
5317 return PARSE_OPERAND_FAIL;
5319 if (skip_past_char (&p, '}') == FAIL)
5321 inst.error = _("'}' expected at end of 'option' field");
5322 return PARSE_OPERAND_FAIL;
5324 if (inst.operands[i].preind)
5326 inst.error = _("cannot combine index with option");
5327 return PARSE_OPERAND_FAIL;
5330 return PARSE_OPERAND_SUCCESS;
5334 inst.operands[i].postind = 1;
5335 inst.operands[i].writeback = 1;
5337 if (inst.operands[i].preind)
5339 inst.error = _("cannot combine pre- and post-indexing");
5340 return PARSE_OPERAND_FAIL;
5344 else if (*p == '-') p++, inst.operands[i].negative = 1;
5346 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5348 /* We might be using the immediate for alignment already. If we
5349 are, OR the register number into the low-order bits. */
5350 if (inst.operands[i].immisalign)
5351 inst.operands[i].imm |= reg;
5353 inst.operands[i].imm = reg;
5354 inst.operands[i].immisreg = 1;
5356 if (skip_past_comma (&p) == SUCCESS)
5357 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5358 return PARSE_OPERAND_FAIL;
5363 if (inst.operands[i].negative)
5365 inst.operands[i].negative = 0;
5368 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5369 return PARSE_OPERAND_FAIL;
5370 /* If the offset is 0, find out if it's a +0 or -0. */
5371 if (inst.reloc.exp.X_op == O_constant
5372 && inst.reloc.exp.X_add_number == 0)
5374 skip_whitespace (q);
5378 skip_whitespace (q);
5381 inst.operands[i].negative = 1;
5387 /* If at this point neither .preind nor .postind is set, we have a
5388 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5389 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5391 inst.operands[i].preind = 1;
5392 inst.reloc.exp.X_op = O_constant;
5393 inst.reloc.exp.X_add_number = 0;
5396 return PARSE_OPERAND_SUCCESS;
5400 parse_address (char **str, int i)
5402 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5406 static parse_operand_result
5407 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5409 return parse_address_main (str, i, 1, type);
5412 /* Parse an operand for a MOVW or MOVT instruction. */
5414 parse_half (char **str)
5419 skip_past_char (&p, '#');
5420 if (strncasecmp (p, ":lower16:", 9) == 0)
5421 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5422 else if (strncasecmp (p, ":upper16:", 9) == 0)
5423 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5425 if (inst.reloc.type != BFD_RELOC_UNUSED)
5428 skip_whitespace (p);
5431 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5434 if (inst.reloc.type == BFD_RELOC_UNUSED)
5436 if (inst.reloc.exp.X_op != O_constant)
5438 inst.error = _("constant expression expected");
5441 if (inst.reloc.exp.X_add_number < 0
5442 || inst.reloc.exp.X_add_number > 0xffff)
5444 inst.error = _("immediate value out of range");
5452 /* Miscellaneous. */
5454 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5455 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5457 parse_psr (char **str, bfd_boolean lhs)
5460 unsigned long psr_field;
5461 const struct asm_psr *psr;
5463 bfd_boolean is_apsr = FALSE;
5464 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5466 /* PR gas/12698: If the user has specified -march=all then m_profile will
5467 be TRUE, but we want to ignore it in this case as we are building for any
5468 CPU type, including non-m variants. */
5469 if (selected_cpu.core == arm_arch_any.core)
5472 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5473 feature for ease of use and backwards compatibility. */
5475 if (strncasecmp (p, "SPSR", 4) == 0)
5478 goto unsupported_psr;
5480 psr_field = SPSR_BIT;
5482 else if (strncasecmp (p, "CPSR", 4) == 0)
5485 goto unsupported_psr;
5489 else if (strncasecmp (p, "APSR", 4) == 0)
5491 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5492 and ARMv7-R architecture CPUs. */
5501 while (ISALNUM (*p) || *p == '_');
5503 if (strncasecmp (start, "iapsr", 5) == 0
5504 || strncasecmp (start, "eapsr", 5) == 0
5505 || strncasecmp (start, "xpsr", 4) == 0
5506 || strncasecmp (start, "psr", 3) == 0)
5507 p = start + strcspn (start, "rR") + 1;
5509 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5515 /* If APSR is being written, a bitfield may be specified. Note that
5516 APSR itself is handled above. */
5517 if (psr->field <= 3)
5519 psr_field = psr->field;
5525 /* M-profile MSR instructions have the mask field set to "10", except
5526 *PSR variants which modify APSR, which may use a different mask (and
5527 have been handled already). Do that by setting the PSR_f field
5529 return psr->field | (lhs ? PSR_f : 0);
5532 goto unsupported_psr;
5538 /* A suffix follows. */
5544 while (ISALNUM (*p) || *p == '_');
5548 /* APSR uses a notation for bits, rather than fields. */
5549 unsigned int nzcvq_bits = 0;
5550 unsigned int g_bit = 0;
5553 for (bit = start; bit != p; bit++)
5555 switch (TOLOWER (*bit))
5558 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5562 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5566 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5570 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5574 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5578 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5582 inst.error = _("unexpected bit specified after APSR");
5587 if (nzcvq_bits == 0x1f)
5592 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5594 inst.error = _("selected processor does not "
5595 "support DSP extension");
5602 if ((nzcvq_bits & 0x20) != 0
5603 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5604 || (g_bit & 0x2) != 0)
5606 inst.error = _("bad bitmask specified after APSR");
5612 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5617 psr_field |= psr->field;
5623 goto error; /* Garbage after "[CS]PSR". */
5625 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5626 is deprecated, but allow it anyway. */
5630 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5633 else if (!m_profile)
5634 /* These bits are never right for M-profile devices: don't set them
5635 (only code paths which read/write APSR reach here). */
5636 psr_field |= (PSR_c | PSR_f);
5642 inst.error = _("selected processor does not support requested special "
5643 "purpose register");
5647 inst.error = _("flag for {c}psr instruction expected");
5651 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5652 value suitable for splatting into the AIF field of the instruction. */
5655 parse_cps_flags (char **str)
5664 case '\0': case ',':
5667 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5668 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5669 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5672 inst.error = _("unrecognized CPS flag");
5677 if (saw_a_flag == 0)
5679 inst.error = _("missing CPS flags");
5687 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5688 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5691 parse_endian_specifier (char **str)
5696 if (strncasecmp (s, "BE", 2))
5698 else if (strncasecmp (s, "LE", 2))
5702 inst.error = _("valid endian specifiers are be or le");
5706 if (ISALNUM (s[2]) || s[2] == '_')
5708 inst.error = _("valid endian specifiers are be or le");
5713 return little_endian;
5716 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5717 value suitable for poking into the rotate field of an sxt or sxta
5718 instruction, or FAIL on error. */
5721 parse_ror (char **str)
5726 if (strncasecmp (s, "ROR", 3) == 0)
5730 inst.error = _("missing rotation field after comma");
5734 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5739 case 0: *str = s; return 0x0;
5740 case 8: *str = s; return 0x1;
5741 case 16: *str = s; return 0x2;
5742 case 24: *str = s; return 0x3;
5745 inst.error = _("rotation can only be 0, 8, 16, or 24");
5750 /* Parse a conditional code (from conds[] below). The value returned is in the
5751 range 0 .. 14, or FAIL. */
5753 parse_cond (char **str)
5756 const struct asm_cond *c;
5758 /* Condition codes are always 2 characters, so matching up to
5759 3 characters is sufficient. */
5764 while (ISALPHA (*q) && n < 3)
5766 cond[n] = TOLOWER (*q);
5771 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5774 inst.error = _("condition required");
5782 /* If the given feature available in the selected CPU, mark it as used.
5783 Returns TRUE iff feature is available. */
5785 mark_feature_used (const arm_feature_set *feature)
5787 /* Ensure the option is valid on the current architecture. */
5788 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5791 /* Add the appropriate architecture feature for the barrier option used.
5794 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5796 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5801 /* Parse an option for a barrier instruction. Returns the encoding for the
5804 parse_barrier (char **str)
5807 const struct asm_barrier_opt *o;
5810 while (ISALPHA (*q))
5813 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5818 if (!mark_feature_used (&o->arch))
5825 /* Parse the operands of a table branch instruction. Similar to a memory
5828 parse_tb (char **str)
5833 if (skip_past_char (&p, '[') == FAIL)
5835 inst.error = _("'[' expected");
5839 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5841 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5844 inst.operands[0].reg = reg;
5846 if (skip_past_comma (&p) == FAIL)
5848 inst.error = _("',' expected");
5852 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5854 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5857 inst.operands[0].imm = reg;
5859 if (skip_past_comma (&p) == SUCCESS)
5861 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5863 if (inst.reloc.exp.X_add_number != 1)
5865 inst.error = _("invalid shift");
5868 inst.operands[0].shifted = 1;
5871 if (skip_past_char (&p, ']') == FAIL)
5873 inst.error = _("']' expected");
5880 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5881 information on the types the operands can take and how they are encoded.
5882 Up to four operands may be read; this function handles setting the
5883 ".present" field for each read operand itself.
5884 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5885 else returns FAIL. */
5888 parse_neon_mov (char **str, int *which_operand)
5890 int i = *which_operand, val;
5891 enum arm_reg_type rtype;
5893 struct neon_type_el optype;
5895 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5897 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5898 inst.operands[i].reg = val;
5899 inst.operands[i].isscalar = 1;
5900 inst.operands[i].vectype = optype;
5901 inst.operands[i++].present = 1;
5903 if (skip_past_comma (&ptr) == FAIL)
5906 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5909 inst.operands[i].reg = val;
5910 inst.operands[i].isreg = 1;
5911 inst.operands[i].present = 1;
5913 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5916 /* Cases 0, 1, 2, 3, 5 (D only). */
5917 if (skip_past_comma (&ptr) == FAIL)
5920 inst.operands[i].reg = val;
5921 inst.operands[i].isreg = 1;
5922 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5923 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5924 inst.operands[i].isvec = 1;
5925 inst.operands[i].vectype = optype;
5926 inst.operands[i++].present = 1;
5928 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5930 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5931 Case 13: VMOV <Sd>, <Rm> */
5932 inst.operands[i].reg = val;
5933 inst.operands[i].isreg = 1;
5934 inst.operands[i].present = 1;
5936 if (rtype == REG_TYPE_NQ)
5938 first_error (_("can't use Neon quad register here"));
5941 else if (rtype != REG_TYPE_VFS)
5944 if (skip_past_comma (&ptr) == FAIL)
5946 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5948 inst.operands[i].reg = val;
5949 inst.operands[i].isreg = 1;
5950 inst.operands[i].present = 1;
5953 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5956 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5957 Case 1: VMOV<c><q> <Dd>, <Dm>
5958 Case 8: VMOV.F32 <Sd>, <Sm>
5959 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5961 inst.operands[i].reg = val;
5962 inst.operands[i].isreg = 1;
5963 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5964 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5965 inst.operands[i].isvec = 1;
5966 inst.operands[i].vectype = optype;
5967 inst.operands[i].present = 1;
5969 if (skip_past_comma (&ptr) == SUCCESS)
5974 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5977 inst.operands[i].reg = val;
5978 inst.operands[i].isreg = 1;
5979 inst.operands[i++].present = 1;
5981 if (skip_past_comma (&ptr) == FAIL)
5984 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5987 inst.operands[i].reg = val;
5988 inst.operands[i].isreg = 1;
5989 inst.operands[i].present = 1;
5992 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5993 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5994 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5995 Case 10: VMOV.F32 <Sd>, #<imm>
5996 Case 11: VMOV.F64 <Dd>, #<imm> */
5997 inst.operands[i].immisfloat = 1;
5998 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5999 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6000 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6004 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6008 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6011 inst.operands[i].reg = val;
6012 inst.operands[i].isreg = 1;
6013 inst.operands[i++].present = 1;
6015 if (skip_past_comma (&ptr) == FAIL)
6018 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6020 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6021 inst.operands[i].reg = val;
6022 inst.operands[i].isscalar = 1;
6023 inst.operands[i].present = 1;
6024 inst.operands[i].vectype = optype;
6026 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6028 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6029 inst.operands[i].reg = val;
6030 inst.operands[i].isreg = 1;
6031 inst.operands[i++].present = 1;
6033 if (skip_past_comma (&ptr) == FAIL)
6036 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6039 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6043 inst.operands[i].reg = val;
6044 inst.operands[i].isreg = 1;
6045 inst.operands[i].isvec = 1;
6046 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6047 inst.operands[i].vectype = optype;
6048 inst.operands[i].present = 1;
6050 if (rtype == REG_TYPE_VFS)
6054 if (skip_past_comma (&ptr) == FAIL)
6056 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6059 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6062 inst.operands[i].reg = val;
6063 inst.operands[i].isreg = 1;
6064 inst.operands[i].isvec = 1;
6065 inst.operands[i].issingle = 1;
6066 inst.operands[i].vectype = optype;
6067 inst.operands[i].present = 1;
6070 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6074 inst.operands[i].reg = val;
6075 inst.operands[i].isreg = 1;
6076 inst.operands[i].isvec = 1;
6077 inst.operands[i].issingle = 1;
6078 inst.operands[i].vectype = optype;
6079 inst.operands[i].present = 1;
6084 first_error (_("parse error"));
6088 /* Successfully parsed the operands. Update args. */
6094 first_error (_("expected comma"));
6098 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6102 /* Use this macro when the operand constraints are different
6103 for ARM and THUMB (e.g. ldrd). */
6104 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6105 ((arm_operand) | ((thumb_operand) << 16))
6107 /* Matcher codes for parse_operands. */
6108 enum operand_parse_code
6110 OP_stop, /* end of line */
6112 OP_RR, /* ARM register */
6113 OP_RRnpc, /* ARM register, not r15 */
6114 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6115 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6116 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6117 optional trailing ! */
6118 OP_RRw, /* ARM register, not r15, optional trailing ! */
6119 OP_RCP, /* Coprocessor number */
6120 OP_RCN, /* Coprocessor register */
6121 OP_RF, /* FPA register */
6122 OP_RVS, /* VFP single precision register */
6123 OP_RVD, /* VFP double precision register (0..15) */
6124 OP_RND, /* Neon double precision register (0..31) */
6125 OP_RNQ, /* Neon quad precision register */
6126 OP_RVSD, /* VFP single or double precision register */
6127 OP_RNDQ, /* Neon double or quad precision register */
6128 OP_RNSDQ, /* Neon single, double or quad precision register */
6129 OP_RNSC, /* Neon scalar D[X] */
6130 OP_RVC, /* VFP control register */
6131 OP_RMF, /* Maverick F register */
6132 OP_RMD, /* Maverick D register */
6133 OP_RMFX, /* Maverick FX register */
6134 OP_RMDX, /* Maverick DX register */
6135 OP_RMAX, /* Maverick AX register */
6136 OP_RMDS, /* Maverick DSPSC register */
6137 OP_RIWR, /* iWMMXt wR register */
6138 OP_RIWC, /* iWMMXt wC register */
6139 OP_RIWG, /* iWMMXt wCG register */
6140 OP_RXA, /* XScale accumulator register */
6142 OP_REGLST, /* ARM register list */
6143 OP_VRSLST, /* VFP single-precision register list */
6144 OP_VRDLST, /* VFP double-precision register list */
6145 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6146 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6147 OP_NSTRLST, /* Neon element/structure list */
6149 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6150 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6151 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6152 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6153 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6154 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6155 OP_VMOV, /* Neon VMOV operands. */
6156 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6157 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6158 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6160 OP_I0, /* immediate zero */
6161 OP_I7, /* immediate value 0 .. 7 */
6162 OP_I15, /* 0 .. 15 */
6163 OP_I16, /* 1 .. 16 */
6164 OP_I16z, /* 0 .. 16 */
6165 OP_I31, /* 0 .. 31 */
6166 OP_I31w, /* 0 .. 31, optional trailing ! */
6167 OP_I32, /* 1 .. 32 */
6168 OP_I32z, /* 0 .. 32 */
6169 OP_I63, /* 0 .. 63 */
6170 OP_I63s, /* -64 .. 63 */
6171 OP_I64, /* 1 .. 64 */
6172 OP_I64z, /* 0 .. 64 */
6173 OP_I255, /* 0 .. 255 */
6175 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6176 OP_I7b, /* 0 .. 7 */
6177 OP_I15b, /* 0 .. 15 */
6178 OP_I31b, /* 0 .. 31 */
6180 OP_SH, /* shifter operand */
6181 OP_SHG, /* shifter operand with possible group relocation */
6182 OP_ADDR, /* Memory address expression (any mode) */
6183 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6184 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6185 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6186 OP_EXP, /* arbitrary expression */
6187 OP_EXPi, /* same, with optional immediate prefix */
6188 OP_EXPr, /* same, with optional relocation suffix */
6189 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6191 OP_CPSF, /* CPS flags */
6192 OP_ENDI, /* Endianness specifier */
6193 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6194 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6195 OP_COND, /* conditional code */
6196 OP_TB, /* Table branch. */
6198 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6200 OP_RRnpc_I0, /* ARM register or literal 0 */
6201 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6202 OP_RR_EXi, /* ARM register or expression with imm prefix */
6203 OP_RF_IF, /* FPA register or immediate */
6204 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6205 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6207 /* Optional operands. */
6208 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6209 OP_oI31b, /* 0 .. 31 */
6210 OP_oI32b, /* 1 .. 32 */
6211 OP_oI32z, /* 0 .. 32 */
6212 OP_oIffffb, /* 0 .. 65535 */
6213 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6215 OP_oRR, /* ARM register */
6216 OP_oRRnpc, /* ARM register, not the PC */
6217 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6218 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6219 OP_oRND, /* Optional Neon double precision register */
6220 OP_oRNQ, /* Optional Neon quad precision register */
6221 OP_oRNDQ, /* Optional Neon double or quad precision register */
6222 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6223 OP_oSHll, /* LSL immediate */
6224 OP_oSHar, /* ASR immediate */
6225 OP_oSHllar, /* LSL or ASR immediate */
6226 OP_oROR, /* ROR 0/8/16/24 */
6227 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6229 /* Some pre-defined mixed (ARM/THUMB) operands. */
6230 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6231 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6232 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6234 OP_FIRST_OPTIONAL = OP_oI7b
6237 /* Generic instruction operand parser. This does no encoding and no
6238 semantic validation; it merely squirrels values away in the inst
6239 structure. Returns SUCCESS or FAIL depending on whether the
6240 specified grammar matched. */
6242 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6244 unsigned const int *upat = pattern;
6245 char *backtrack_pos = 0;
6246 const char *backtrack_error = 0;
6247 int i, val = 0, backtrack_index = 0;
6248 enum arm_reg_type rtype;
6249 parse_operand_result result;
6250 unsigned int op_parse_code;
6252 #define po_char_or_fail(chr) \
6255 if (skip_past_char (&str, chr) == FAIL) \
6260 #define po_reg_or_fail(regtype) \
6263 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6264 & inst.operands[i].vectype); \
6267 first_error (_(reg_expected_msgs[regtype])); \
6270 inst.operands[i].reg = val; \
6271 inst.operands[i].isreg = 1; \
6272 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6273 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6274 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6275 || rtype == REG_TYPE_VFD \
6276 || rtype == REG_TYPE_NQ); \
6280 #define po_reg_or_goto(regtype, label) \
6283 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6284 & inst.operands[i].vectype); \
6288 inst.operands[i].reg = val; \
6289 inst.operands[i].isreg = 1; \
6290 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6291 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6292 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6293 || rtype == REG_TYPE_VFD \
6294 || rtype == REG_TYPE_NQ); \
6298 #define po_imm_or_fail(min, max, popt) \
6301 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6303 inst.operands[i].imm = val; \
6307 #define po_scalar_or_goto(elsz, label) \
6310 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6313 inst.operands[i].reg = val; \
6314 inst.operands[i].isscalar = 1; \
6318 #define po_misc_or_fail(expr) \
6326 #define po_misc_or_fail_no_backtrack(expr) \
6330 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6331 backtrack_pos = 0; \
6332 if (result != PARSE_OPERAND_SUCCESS) \
6337 #define po_barrier_or_imm(str) \
6340 val = parse_barrier (&str); \
6343 if (ISALPHA (*str)) \
6350 if ((inst.instruction & 0xf0) == 0x60 \
6353 /* ISB can only take SY as an option. */ \
6354 inst.error = _("invalid barrier type"); \
6361 skip_whitespace (str);
6363 for (i = 0; upat[i] != OP_stop; i++)
6365 op_parse_code = upat[i];
6366 if (op_parse_code >= 1<<16)
6367 op_parse_code = thumb ? (op_parse_code >> 16)
6368 : (op_parse_code & ((1<<16)-1));
6370 if (op_parse_code >= OP_FIRST_OPTIONAL)
6372 /* Remember where we are in case we need to backtrack. */
6373 gas_assert (!backtrack_pos);
6374 backtrack_pos = str;
6375 backtrack_error = inst.error;
6376 backtrack_index = i;
6379 if (i > 0 && (i > 1 || inst.operands[0].present))
6380 po_char_or_fail (',');
6382 switch (op_parse_code)
6390 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6391 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6392 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6393 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6394 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6395 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6397 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6399 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6401 /* Also accept generic coprocessor regs for unknown registers. */
6403 po_reg_or_fail (REG_TYPE_CN);
6405 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6406 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6407 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6408 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6409 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6410 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6411 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6412 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6413 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6414 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6416 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6418 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6419 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6421 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6423 /* Neon scalar. Using an element size of 8 means that some invalid
6424 scalars are accepted here, so deal with those in later code. */
6425 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6429 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6432 po_imm_or_fail (0, 0, TRUE);
6437 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6442 po_scalar_or_goto (8, try_rr);
6445 po_reg_or_fail (REG_TYPE_RN);
6451 po_scalar_or_goto (8, try_nsdq);
6454 po_reg_or_fail (REG_TYPE_NSDQ);
6460 po_scalar_or_goto (8, try_ndq);
6463 po_reg_or_fail (REG_TYPE_NDQ);
6469 po_scalar_or_goto (8, try_vfd);
6472 po_reg_or_fail (REG_TYPE_VFD);
6477 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6478 not careful then bad things might happen. */
6479 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6484 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6487 /* There's a possibility of getting a 64-bit immediate here, so
6488 we need special handling. */
6489 if (parse_big_immediate (&str, i) == FAIL)
6491 inst.error = _("immediate value is out of range");
6499 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6502 po_imm_or_fail (0, 63, TRUE);
6507 po_char_or_fail ('[');
6508 po_reg_or_fail (REG_TYPE_RN);
6509 po_char_or_fail (']');
6515 po_reg_or_fail (REG_TYPE_RN);
6516 if (skip_past_char (&str, '!') == SUCCESS)
6517 inst.operands[i].writeback = 1;
6521 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6522 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6523 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6524 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6525 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6526 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6527 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6528 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6529 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6530 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6531 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6532 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6534 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6536 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6537 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6539 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6540 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6541 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6542 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6544 /* Immediate variants */
6546 po_char_or_fail ('{');
6547 po_imm_or_fail (0, 255, TRUE);
6548 po_char_or_fail ('}');
6552 /* The expression parser chokes on a trailing !, so we have
6553 to find it first and zap it. */
6556 while (*s && *s != ',')
6561 inst.operands[i].writeback = 1;
6563 po_imm_or_fail (0, 31, TRUE);
6571 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6576 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6581 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6583 if (inst.reloc.exp.X_op == O_symbol)
6585 val = parse_reloc (&str);
6588 inst.error = _("unrecognized relocation suffix");
6591 else if (val != BFD_RELOC_UNUSED)
6593 inst.operands[i].imm = val;
6594 inst.operands[i].hasreloc = 1;
6599 /* Operand for MOVW or MOVT. */
6601 po_misc_or_fail (parse_half (&str));
6604 /* Register or expression. */
6605 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6606 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6608 /* Register or immediate. */
6609 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6610 I0: po_imm_or_fail (0, 0, FALSE); break;
6612 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6614 if (!is_immediate_prefix (*str))
6617 val = parse_fpa_immediate (&str);
6620 /* FPA immediates are encoded as registers 8-15.
6621 parse_fpa_immediate has already applied the offset. */
6622 inst.operands[i].reg = val;
6623 inst.operands[i].isreg = 1;
6626 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6627 I32z: po_imm_or_fail (0, 32, FALSE); break;
6629 /* Two kinds of register. */
6632 struct reg_entry *rege = arm_reg_parse_multi (&str);
6634 || (rege->type != REG_TYPE_MMXWR
6635 && rege->type != REG_TYPE_MMXWC
6636 && rege->type != REG_TYPE_MMXWCG))
6638 inst.error = _("iWMMXt data or control register expected");
6641 inst.operands[i].reg = rege->number;
6642 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6648 struct reg_entry *rege = arm_reg_parse_multi (&str);
6650 || (rege->type != REG_TYPE_MMXWC
6651 && rege->type != REG_TYPE_MMXWCG))
6653 inst.error = _("iWMMXt control register expected");
6656 inst.operands[i].reg = rege->number;
6657 inst.operands[i].isreg = 1;
6662 case OP_CPSF: val = parse_cps_flags (&str); break;
6663 case OP_ENDI: val = parse_endian_specifier (&str); break;
6664 case OP_oROR: val = parse_ror (&str); break;
6665 case OP_COND: val = parse_cond (&str); break;
6666 case OP_oBARRIER_I15:
6667 po_barrier_or_imm (str); break;
6669 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6675 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6676 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6678 inst.error = _("Banked registers are not available with this "
6684 val = parse_psr (&str, op_parse_code == OP_wPSR);
6688 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6691 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6693 if (strncasecmp (str, "APSR_", 5) == 0)
6700 case 'c': found = (found & 1) ? 16 : found | 1; break;
6701 case 'n': found = (found & 2) ? 16 : found | 2; break;
6702 case 'z': found = (found & 4) ? 16 : found | 4; break;
6703 case 'v': found = (found & 8) ? 16 : found | 8; break;
6704 default: found = 16;
6708 inst.operands[i].isvec = 1;
6709 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6710 inst.operands[i].reg = REG_PC;
6717 po_misc_or_fail (parse_tb (&str));
6720 /* Register lists. */
6722 val = parse_reg_list (&str);
6725 inst.operands[1].writeback = 1;
6731 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6735 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6739 /* Allow Q registers too. */
6740 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6745 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6747 inst.operands[i].issingle = 1;
6752 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6757 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6758 &inst.operands[i].vectype);
6761 /* Addressing modes */
6763 po_misc_or_fail (parse_address (&str, i));
6767 po_misc_or_fail_no_backtrack (
6768 parse_address_group_reloc (&str, i, GROUP_LDR));
6772 po_misc_or_fail_no_backtrack (
6773 parse_address_group_reloc (&str, i, GROUP_LDRS));
6777 po_misc_or_fail_no_backtrack (
6778 parse_address_group_reloc (&str, i, GROUP_LDC));
6782 po_misc_or_fail (parse_shifter_operand (&str, i));
6786 po_misc_or_fail_no_backtrack (
6787 parse_shifter_operand_group_reloc (&str, i));
6791 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6795 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6799 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6803 as_fatal (_("unhandled operand code %d"), op_parse_code);
6806 /* Various value-based sanity checks and shared operations. We
6807 do not signal immediate failures for the register constraints;
6808 this allows a syntax error to take precedence. */
6809 switch (op_parse_code)
6817 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6818 inst.error = BAD_PC;
6823 if (inst.operands[i].isreg)
6825 if (inst.operands[i].reg == REG_PC)
6826 inst.error = BAD_PC;
6827 else if (inst.operands[i].reg == REG_SP)
6828 inst.error = BAD_SP;
6833 if (inst.operands[i].isreg
6834 && inst.operands[i].reg == REG_PC
6835 && (inst.operands[i].writeback || thumb))
6836 inst.error = BAD_PC;
6845 case OP_oBARRIER_I15:
6854 inst.operands[i].imm = val;
6861 /* If we get here, this operand was successfully parsed. */
6862 inst.operands[i].present = 1;
6866 inst.error = BAD_ARGS;
6871 /* The parse routine should already have set inst.error, but set a
6872 default here just in case. */
6874 inst.error = _("syntax error");
6878 /* Do not backtrack over a trailing optional argument that
6879 absorbed some text. We will only fail again, with the
6880 'garbage following instruction' error message, which is
6881 probably less helpful than the current one. */
6882 if (backtrack_index == i && backtrack_pos != str
6883 && upat[i+1] == OP_stop)
6886 inst.error = _("syntax error");
6890 /* Try again, skipping the optional argument at backtrack_pos. */
6891 str = backtrack_pos;
6892 inst.error = backtrack_error;
6893 inst.operands[backtrack_index].present = 0;
6894 i = backtrack_index;
6898 /* Check that we have parsed all the arguments. */
6899 if (*str != '\0' && !inst.error)
6900 inst.error = _("garbage following instruction");
6902 return inst.error ? FAIL : SUCCESS;
6905 #undef po_char_or_fail
6906 #undef po_reg_or_fail
6907 #undef po_reg_or_goto
6908 #undef po_imm_or_fail
6909 #undef po_scalar_or_fail
6910 #undef po_barrier_or_imm
6912 /* Shorthand macro for instruction encoding functions issuing errors. */
6913 #define constraint(expr, err) \
6924 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6925 instructions are unpredictable if these registers are used. This
6926 is the BadReg predicate in ARM's Thumb-2 documentation. */
6927 #define reject_bad_reg(reg) \
6929 if (reg == REG_SP || reg == REG_PC) \
6931 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6936 /* If REG is R13 (the stack pointer), warn that its use is
6938 #define warn_deprecated_sp(reg) \
6940 if (warn_on_deprecated && reg == REG_SP) \
6941 as_warn (_("use of r13 is deprecated")); \
6944 /* Functions for operand encoding. ARM, then Thumb. */
6946 #define rotate_left(v, n) (v << n | v >> (32 - n))
6948 /* If VAL can be encoded in the immediate field of an ARM instruction,
6949 return the encoded form. Otherwise, return FAIL. */
6952 encode_arm_immediate (unsigned int val)
6956 for (i = 0; i < 32; i += 2)
6957 if ((a = rotate_left (val, i)) <= 0xff)
6958 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6963 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6964 return the encoded form. Otherwise, return FAIL. */
6966 encode_thumb32_immediate (unsigned int val)
6973 for (i = 1; i <= 24; i++)
6976 if ((val & ~(0xff << i)) == 0)
6977 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6981 if (val == ((a << 16) | a))
6983 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6987 if (val == ((a << 16) | a))
6988 return 0x200 | (a >> 8);
6992 /* Encode a VFP SP or DP register number into inst.instruction. */
6995 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6997 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
7000 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
7003 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7006 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7011 first_error (_("D register out of range for selected VFP version"));
7019 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7023 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7027 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7031 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7035 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7039 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7047 /* Encode a <shift> in an ARM-format instruction. The immediate,
7048 if any, is handled by md_apply_fix. */
7050 encode_arm_shift (int i)
7052 if (inst.operands[i].shift_kind == SHIFT_RRX)
7053 inst.instruction |= SHIFT_ROR << 5;
7056 inst.instruction |= inst.operands[i].shift_kind << 5;
7057 if (inst.operands[i].immisreg)
7059 inst.instruction |= SHIFT_BY_REG;
7060 inst.instruction |= inst.operands[i].imm << 8;
7063 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7068 encode_arm_shifter_operand (int i)
7070 if (inst.operands[i].isreg)
7072 inst.instruction |= inst.operands[i].reg;
7073 encode_arm_shift (i);
7077 inst.instruction |= INST_IMMEDIATE;
7078 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7079 inst.instruction |= inst.operands[i].imm;
7083 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7085 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7088 Generate an error if the operand is not a register. */
7089 constraint (!inst.operands[i].isreg,
7090 _("Instruction does not support =N addresses"));
7092 inst.instruction |= inst.operands[i].reg << 16;
7094 if (inst.operands[i].preind)
7098 inst.error = _("instruction does not accept preindexed addressing");
7101 inst.instruction |= PRE_INDEX;
7102 if (inst.operands[i].writeback)
7103 inst.instruction |= WRITE_BACK;
7106 else if (inst.operands[i].postind)
7108 gas_assert (inst.operands[i].writeback);
7110 inst.instruction |= WRITE_BACK;
7112 else /* unindexed - only for coprocessor */
7114 inst.error = _("instruction does not accept unindexed addressing");
7118 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7119 && (((inst.instruction & 0x000f0000) >> 16)
7120 == ((inst.instruction & 0x0000f000) >> 12)))
7121 as_warn ((inst.instruction & LOAD_BIT)
7122 ? _("destination register same as write-back base")
7123 : _("source register same as write-back base"));
7126 /* inst.operands[i] was set up by parse_address. Encode it into an
7127 ARM-format mode 2 load or store instruction. If is_t is true,
7128 reject forms that cannot be used with a T instruction (i.e. not
7131 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7133 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7135 encode_arm_addr_mode_common (i, is_t);
7137 if (inst.operands[i].immisreg)
7139 constraint ((inst.operands[i].imm == REG_PC
7140 || (is_pc && inst.operands[i].writeback)),
7142 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7143 inst.instruction |= inst.operands[i].imm;
7144 if (!inst.operands[i].negative)
7145 inst.instruction |= INDEX_UP;
7146 if (inst.operands[i].shifted)
7148 if (inst.operands[i].shift_kind == SHIFT_RRX)
7149 inst.instruction |= SHIFT_ROR << 5;
7152 inst.instruction |= inst.operands[i].shift_kind << 5;
7153 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7157 else /* immediate offset in inst.reloc */
7159 if (is_pc && !inst.reloc.pc_rel)
7161 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7163 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7164 cannot use PC in addressing.
7165 PC cannot be used in writeback addressing, either. */
7166 constraint ((is_t || inst.operands[i].writeback),
7169 /* Use of PC in str is deprecated for ARMv7. */
7170 if (warn_on_deprecated
7172 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7173 as_warn (_("use of PC in this instruction is deprecated"));
7176 if (inst.reloc.type == BFD_RELOC_UNUSED)
7178 /* Prefer + for zero encoded value. */
7179 if (!inst.operands[i].negative)
7180 inst.instruction |= INDEX_UP;
7181 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7186 /* inst.operands[i] was set up by parse_address. Encode it into an
7187 ARM-format mode 3 load or store instruction. Reject forms that
7188 cannot be used with such instructions. If is_t is true, reject
7189 forms that cannot be used with a T instruction (i.e. not
7192 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7194 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7196 inst.error = _("instruction does not accept scaled register index");
7200 encode_arm_addr_mode_common (i, is_t);
7202 if (inst.operands[i].immisreg)
7204 constraint ((inst.operands[i].imm == REG_PC
7205 || inst.operands[i].reg == REG_PC),
7207 inst.instruction |= inst.operands[i].imm;
7208 if (!inst.operands[i].negative)
7209 inst.instruction |= INDEX_UP;
7211 else /* immediate offset in inst.reloc */
7213 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7214 && inst.operands[i].writeback),
7216 inst.instruction |= HWOFFSET_IMM;
7217 if (inst.reloc.type == BFD_RELOC_UNUSED)
7219 /* Prefer + for zero encoded value. */
7220 if (!inst.operands[i].negative)
7221 inst.instruction |= INDEX_UP;
7223 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7228 /* inst.operands[i] was set up by parse_address. Encode it into an
7229 ARM-format instruction. Reject all forms which cannot be encoded
7230 into a coprocessor load/store instruction. If wb_ok is false,
7231 reject use of writeback; if unind_ok is false, reject use of
7232 unindexed addressing. If reloc_override is not 0, use it instead
7233 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7234 (in which case it is preserved). */
7237 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7239 inst.instruction |= inst.operands[i].reg << 16;
7241 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7243 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7245 gas_assert (!inst.operands[i].writeback);
7248 inst.error = _("instruction does not support unindexed addressing");
7251 inst.instruction |= inst.operands[i].imm;
7252 inst.instruction |= INDEX_UP;
7256 if (inst.operands[i].preind)
7257 inst.instruction |= PRE_INDEX;
7259 if (inst.operands[i].writeback)
7261 if (inst.operands[i].reg == REG_PC)
7263 inst.error = _("pc may not be used with write-back");
7268 inst.error = _("instruction does not support writeback");
7271 inst.instruction |= WRITE_BACK;
7275 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7276 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7277 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7278 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7281 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7283 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7286 /* Prefer + for zero encoded value. */
7287 if (!inst.operands[i].negative)
7288 inst.instruction |= INDEX_UP;
7293 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7294 Determine whether it can be performed with a move instruction; if
7295 it can, convert inst.instruction to that move instruction and
7296 return TRUE; if it can't, convert inst.instruction to a literal-pool
7297 load and return FALSE. If this is not a valid thing to do in the
7298 current context, set inst.error and return TRUE.
7300 inst.operands[i] describes the destination register. */
7303 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7308 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7312 if ((inst.instruction & tbit) == 0)
7314 inst.error = _("invalid pseudo operation");
7317 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7319 inst.error = _("constant expression expected");
7322 if (inst.reloc.exp.X_op == O_constant)
7326 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7328 /* This can be done with a mov(1) instruction. */
7329 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7330 inst.instruction |= inst.reloc.exp.X_add_number;
7336 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7339 /* This can be done with a mov instruction. */
7340 inst.instruction &= LITERAL_MASK;
7341 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7342 inst.instruction |= value & 0xfff;
7346 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7349 /* This can be done with a mvn instruction. */
7350 inst.instruction &= LITERAL_MASK;
7351 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7352 inst.instruction |= value & 0xfff;
7358 if (add_to_lit_pool () == FAIL)
7360 inst.error = _("literal pool insertion failed");
7363 inst.operands[1].reg = REG_PC;
7364 inst.operands[1].isreg = 1;
7365 inst.operands[1].preind = 1;
7366 inst.reloc.pc_rel = 1;
7367 inst.reloc.type = (thumb_p
7368 ? BFD_RELOC_ARM_THUMB_OFFSET
7370 ? BFD_RELOC_ARM_HWLITERAL
7371 : BFD_RELOC_ARM_LITERAL));
7375 /* Functions for instruction encoding, sorted by sub-architecture.
7376 First some generics; their names are taken from the conventional
7377 bit positions for register arguments in ARM format instructions. */
7387 inst.instruction |= inst.operands[0].reg << 12;
7393 inst.instruction |= inst.operands[0].reg << 12;
7394 inst.instruction |= inst.operands[1].reg;
7400 inst.instruction |= inst.operands[0].reg;
7401 inst.instruction |= inst.operands[1].reg << 16;
7407 inst.instruction |= inst.operands[0].reg << 12;
7408 inst.instruction |= inst.operands[1].reg << 16;
7414 inst.instruction |= inst.operands[0].reg << 16;
7415 inst.instruction |= inst.operands[1].reg << 12;
7419 check_obsolete (const arm_feature_set *feature, const char *msg)
7421 if (ARM_CPU_IS_ANY (cpu_variant))
7423 as_warn ("%s", msg);
7426 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7438 unsigned Rn = inst.operands[2].reg;
7439 /* Enforce restrictions on SWP instruction. */
7440 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7442 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7443 _("Rn must not overlap other operands"));
7445 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7447 if (!check_obsolete (&arm_ext_v8,
7448 _("swp{b} use is obsoleted for ARMv8 and later"))
7449 && warn_on_deprecated
7450 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7451 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7454 inst.instruction |= inst.operands[0].reg << 12;
7455 inst.instruction |= inst.operands[1].reg;
7456 inst.instruction |= Rn << 16;
7462 inst.instruction |= inst.operands[0].reg << 12;
7463 inst.instruction |= inst.operands[1].reg << 16;
7464 inst.instruction |= inst.operands[2].reg;
7470 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7471 constraint (((inst.reloc.exp.X_op != O_constant
7472 && inst.reloc.exp.X_op != O_illegal)
7473 || inst.reloc.exp.X_add_number != 0),
7475 inst.instruction |= inst.operands[0].reg;
7476 inst.instruction |= inst.operands[1].reg << 12;
7477 inst.instruction |= inst.operands[2].reg << 16;
7483 inst.instruction |= inst.operands[0].imm;
7489 inst.instruction |= inst.operands[0].reg << 12;
7490 encode_arm_cp_address (1, TRUE, TRUE, 0);
7493 /* ARM instructions, in alphabetical order by function name (except
7494 that wrapper functions appear immediately after the function they
7497 /* This is a pseudo-op of the form "adr rd, label" to be converted
7498 into a relative address of the form "add rd, pc, #label-.-8". */
7503 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7505 /* Frag hacking will turn this into a sub instruction if the offset turns
7506 out to be negative. */
7507 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7508 inst.reloc.pc_rel = 1;
7509 inst.reloc.exp.X_add_number -= 8;
7512 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7513 into a relative address of the form:
7514 add rd, pc, #low(label-.-8)"
7515 add rd, rd, #high(label-.-8)" */
7520 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7522 /* Frag hacking will turn this into a sub instruction if the offset turns
7523 out to be negative. */
7524 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7525 inst.reloc.pc_rel = 1;
7526 inst.size = INSN_SIZE * 2;
7527 inst.reloc.exp.X_add_number -= 8;
7533 if (!inst.operands[1].present)
7534 inst.operands[1].reg = inst.operands[0].reg;
7535 inst.instruction |= inst.operands[0].reg << 12;
7536 inst.instruction |= inst.operands[1].reg << 16;
7537 encode_arm_shifter_operand (2);
7543 if (inst.operands[0].present)
7545 constraint ((inst.instruction & 0xf0) != 0x40
7546 && inst.operands[0].imm > 0xf
7547 && inst.operands[0].imm < 0x0,
7548 _("bad barrier type"));
7549 inst.instruction |= inst.operands[0].imm;
7552 inst.instruction |= 0xf;
7558 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7559 constraint (msb > 32, _("bit-field extends past end of register"));
7560 /* The instruction encoding stores the LSB and MSB,
7561 not the LSB and width. */
7562 inst.instruction |= inst.operands[0].reg << 12;
7563 inst.instruction |= inst.operands[1].imm << 7;
7564 inst.instruction |= (msb - 1) << 16;
7572 /* #0 in second position is alternative syntax for bfc, which is
7573 the same instruction but with REG_PC in the Rm field. */
7574 if (!inst.operands[1].isreg)
7575 inst.operands[1].reg = REG_PC;
7577 msb = inst.operands[2].imm + inst.operands[3].imm;
7578 constraint (msb > 32, _("bit-field extends past end of register"));
7579 /* The instruction encoding stores the LSB and MSB,
7580 not the LSB and width. */
7581 inst.instruction |= inst.operands[0].reg << 12;
7582 inst.instruction |= inst.operands[1].reg;
7583 inst.instruction |= inst.operands[2].imm << 7;
7584 inst.instruction |= (msb - 1) << 16;
7590 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7591 _("bit-field extends past end of register"));
7592 inst.instruction |= inst.operands[0].reg << 12;
7593 inst.instruction |= inst.operands[1].reg;
7594 inst.instruction |= inst.operands[2].imm << 7;
7595 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7598 /* ARM V5 breakpoint instruction (argument parse)
7599 BKPT <16 bit unsigned immediate>
7600 Instruction is not conditional.
7601 The bit pattern given in insns[] has the COND_ALWAYS condition,
7602 and it is an error if the caller tried to override that. */
7607 /* Top 12 of 16 bits to bits 19:8. */
7608 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7610 /* Bottom 4 of 16 bits to bits 3:0. */
7611 inst.instruction |= inst.operands[0].imm & 0xf;
7615 encode_branch (int default_reloc)
7617 if (inst.operands[0].hasreloc)
7619 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7620 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7621 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7622 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7623 ? BFD_RELOC_ARM_PLT32
7624 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7627 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7628 inst.reloc.pc_rel = 1;
7635 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7636 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7639 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7646 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7648 if (inst.cond == COND_ALWAYS)
7649 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7651 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7655 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7658 /* ARM V5 branch-link-exchange instruction (argument parse)
7659 BLX <target_addr> ie BLX(1)
7660 BLX{<condition>} <Rm> ie BLX(2)
7661 Unfortunately, there are two different opcodes for this mnemonic.
7662 So, the insns[].value is not used, and the code here zaps values
7663 into inst.instruction.
7664 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7669 if (inst.operands[0].isreg)
7671 /* Arg is a register; the opcode provided by insns[] is correct.
7672 It is not illegal to do "blx pc", just useless. */
7673 if (inst.operands[0].reg == REG_PC)
7674 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7676 inst.instruction |= inst.operands[0].reg;
7680 /* Arg is an address; this instruction cannot be executed
7681 conditionally, and the opcode must be adjusted.
7682 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7683 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7684 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7685 inst.instruction = 0xfa000000;
7686 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7693 bfd_boolean want_reloc;
7695 if (inst.operands[0].reg == REG_PC)
7696 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7698 inst.instruction |= inst.operands[0].reg;
7699 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7700 it is for ARMv4t or earlier. */
7701 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7702 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7706 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7711 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7715 /* ARM v5TEJ. Jump to Jazelle code. */
7720 if (inst.operands[0].reg == REG_PC)
7721 as_tsktsk (_("use of r15 in bxj is not really useful"));
7723 inst.instruction |= inst.operands[0].reg;
7726 /* Co-processor data operation:
7727 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7728 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7732 inst.instruction |= inst.operands[0].reg << 8;
7733 inst.instruction |= inst.operands[1].imm << 20;
7734 inst.instruction |= inst.operands[2].reg << 12;
7735 inst.instruction |= inst.operands[3].reg << 16;
7736 inst.instruction |= inst.operands[4].reg;
7737 inst.instruction |= inst.operands[5].imm << 5;
7743 inst.instruction |= inst.operands[0].reg << 16;
7744 encode_arm_shifter_operand (1);
7747 /* Transfer between coprocessor and ARM registers.
7748 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7753 No special properties. */
7755 struct deprecated_coproc_regs_s
7762 arm_feature_set deprecated;
7763 arm_feature_set obsoleted;
7764 const char *dep_msg;
7765 const char *obs_msg;
7768 #define DEPR_ACCESS_V8 \
7769 N_("This coprocessor register access is deprecated in ARMv8")
7771 /* Table of all deprecated coprocessor registers. */
7772 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7774 {15, 0, 7, 10, 5, /* CP15DMB. */
7775 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7776 DEPR_ACCESS_V8, NULL},
7777 {15, 0, 7, 10, 4, /* CP15DSB. */
7778 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7779 DEPR_ACCESS_V8, NULL},
7780 {15, 0, 7, 5, 4, /* CP15ISB. */
7781 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7782 DEPR_ACCESS_V8, NULL},
7783 {14, 6, 1, 0, 0, /* TEEHBR. */
7784 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7785 DEPR_ACCESS_V8, NULL},
7786 {14, 6, 0, 0, 0, /* TEECR. */
7787 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7788 DEPR_ACCESS_V8, NULL},
7791 #undef DEPR_ACCESS_V8
7793 static const size_t deprecated_coproc_reg_count =
7794 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7802 Rd = inst.operands[2].reg;
7805 if (inst.instruction == 0xee000010
7806 || inst.instruction == 0xfe000010)
7808 reject_bad_reg (Rd);
7811 constraint (Rd == REG_SP, BAD_SP);
7816 if (inst.instruction == 0xe000010)
7817 constraint (Rd == REG_PC, BAD_PC);
7820 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7822 const struct deprecated_coproc_regs_s *r =
7823 deprecated_coproc_regs + i;
7825 if (inst.operands[0].reg == r->cp
7826 && inst.operands[1].imm == r->opc1
7827 && inst.operands[3].reg == r->crn
7828 && inst.operands[4].reg == r->crm
7829 && inst.operands[5].imm == r->opc2)
7831 if (! ARM_CPU_IS_ANY (cpu_variant)
7832 && warn_on_deprecated
7833 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7834 as_warn ("%s", r->dep_msg);
7838 inst.instruction |= inst.operands[0].reg << 8;
7839 inst.instruction |= inst.operands[1].imm << 21;
7840 inst.instruction |= Rd << 12;
7841 inst.instruction |= inst.operands[3].reg << 16;
7842 inst.instruction |= inst.operands[4].reg;
7843 inst.instruction |= inst.operands[5].imm << 5;
7846 /* Transfer between coprocessor register and pair of ARM registers.
7847 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7852 Two XScale instructions are special cases of these:
7854 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7855 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7857 Result unpredictable if Rd or Rn is R15. */
7864 Rd = inst.operands[2].reg;
7865 Rn = inst.operands[3].reg;
7869 reject_bad_reg (Rd);
7870 reject_bad_reg (Rn);
7874 constraint (Rd == REG_PC, BAD_PC);
7875 constraint (Rn == REG_PC, BAD_PC);
7878 inst.instruction |= inst.operands[0].reg << 8;
7879 inst.instruction |= inst.operands[1].imm << 4;
7880 inst.instruction |= Rd << 12;
7881 inst.instruction |= Rn << 16;
7882 inst.instruction |= inst.operands[4].reg;
7888 inst.instruction |= inst.operands[0].imm << 6;
7889 if (inst.operands[1].present)
7891 inst.instruction |= CPSI_MMOD;
7892 inst.instruction |= inst.operands[1].imm;
7899 inst.instruction |= inst.operands[0].imm;
7905 unsigned Rd, Rn, Rm;
7907 Rd = inst.operands[0].reg;
7908 Rn = (inst.operands[1].present
7909 ? inst.operands[1].reg : Rd);
7910 Rm = inst.operands[2].reg;
7912 constraint ((Rd == REG_PC), BAD_PC);
7913 constraint ((Rn == REG_PC), BAD_PC);
7914 constraint ((Rm == REG_PC), BAD_PC);
7916 inst.instruction |= Rd << 16;
7917 inst.instruction |= Rn << 0;
7918 inst.instruction |= Rm << 8;
7924 /* There is no IT instruction in ARM mode. We
7925 process it to do the validation as if in
7926 thumb mode, just in case the code gets
7927 assembled for thumb using the unified syntax. */
7932 set_it_insn_type (IT_INSN);
7933 now_it.mask = (inst.instruction & 0xf) | 0x10;
7934 now_it.cc = inst.operands[0].imm;
7938 /* If there is only one register in the register list,
7939 then return its register number. Otherwise return -1. */
7941 only_one_reg_in_list (int range)
7943 int i = ffs (range) - 1;
7944 return (i > 15 || range != (1 << i)) ? -1 : i;
7948 encode_ldmstm(int from_push_pop_mnem)
7950 int base_reg = inst.operands[0].reg;
7951 int range = inst.operands[1].imm;
7954 inst.instruction |= base_reg << 16;
7955 inst.instruction |= range;
7957 if (inst.operands[1].writeback)
7958 inst.instruction |= LDM_TYPE_2_OR_3;
7960 if (inst.operands[0].writeback)
7962 inst.instruction |= WRITE_BACK;
7963 /* Check for unpredictable uses of writeback. */
7964 if (inst.instruction & LOAD_BIT)
7966 /* Not allowed in LDM type 2. */
7967 if ((inst.instruction & LDM_TYPE_2_OR_3)
7968 && ((range & (1 << REG_PC)) == 0))
7969 as_warn (_("writeback of base register is UNPREDICTABLE"));
7970 /* Only allowed if base reg not in list for other types. */
7971 else if (range & (1 << base_reg))
7972 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7976 /* Not allowed for type 2. */
7977 if (inst.instruction & LDM_TYPE_2_OR_3)
7978 as_warn (_("writeback of base register is UNPREDICTABLE"));
7979 /* Only allowed if base reg not in list, or first in list. */
7980 else if ((range & (1 << base_reg))
7981 && (range & ((1 << base_reg) - 1)))
7982 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7986 /* If PUSH/POP has only one register, then use the A2 encoding. */
7987 one_reg = only_one_reg_in_list (range);
7988 if (from_push_pop_mnem && one_reg >= 0)
7990 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7992 inst.instruction &= A_COND_MASK;
7993 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7994 inst.instruction |= one_reg << 12;
8001 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
8004 /* ARMv5TE load-consecutive (argument parse)
8013 constraint (inst.operands[0].reg % 2 != 0,
8014 _("first transfer register must be even"));
8015 constraint (inst.operands[1].present
8016 && inst.operands[1].reg != inst.operands[0].reg + 1,
8017 _("can only transfer two consecutive registers"));
8018 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8019 constraint (!inst.operands[2].isreg, _("'[' expected"));
8021 if (!inst.operands[1].present)
8022 inst.operands[1].reg = inst.operands[0].reg + 1;
8024 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8025 register and the first register written; we have to diagnose
8026 overlap between the base and the second register written here. */
8028 if (inst.operands[2].reg == inst.operands[1].reg
8029 && (inst.operands[2].writeback || inst.operands[2].postind))
8030 as_warn (_("base register written back, and overlaps "
8031 "second transfer register"));
8033 if (!(inst.instruction & V4_STR_BIT))
8035 /* For an index-register load, the index register must not overlap the
8036 destination (even if not write-back). */
8037 if (inst.operands[2].immisreg
8038 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8039 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8040 as_warn (_("index register overlaps transfer register"));
8042 inst.instruction |= inst.operands[0].reg << 12;
8043 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8049 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8050 || inst.operands[1].postind || inst.operands[1].writeback
8051 || inst.operands[1].immisreg || inst.operands[1].shifted
8052 || inst.operands[1].negative
8053 /* This can arise if the programmer has written
8055 or if they have mistakenly used a register name as the last
8058 It is very difficult to distinguish between these two cases
8059 because "rX" might actually be a label. ie the register
8060 name has been occluded by a symbol of the same name. So we
8061 just generate a general 'bad addressing mode' type error
8062 message and leave it up to the programmer to discover the
8063 true cause and fix their mistake. */
8064 || (inst.operands[1].reg == REG_PC),
8067 constraint (inst.reloc.exp.X_op != O_constant
8068 || inst.reloc.exp.X_add_number != 0,
8069 _("offset must be zero in ARM encoding"));
8071 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8073 inst.instruction |= inst.operands[0].reg << 12;
8074 inst.instruction |= inst.operands[1].reg << 16;
8075 inst.reloc.type = BFD_RELOC_UNUSED;
8081 constraint (inst.operands[0].reg % 2 != 0,
8082 _("even register required"));
8083 constraint (inst.operands[1].present
8084 && inst.operands[1].reg != inst.operands[0].reg + 1,
8085 _("can only load two consecutive registers"));
8086 /* If op 1 were present and equal to PC, this function wouldn't
8087 have been called in the first place. */
8088 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8090 inst.instruction |= inst.operands[0].reg << 12;
8091 inst.instruction |= inst.operands[2].reg << 16;
8094 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8095 which is not a multiple of four is UNPREDICTABLE. */
8097 check_ldr_r15_aligned (void)
8099 constraint (!(inst.operands[1].immisreg)
8100 && (inst.operands[0].reg == REG_PC
8101 && inst.operands[1].reg == REG_PC
8102 && (inst.reloc.exp.X_add_number & 0x3)),
8103 _("ldr to register 15 must be 4-byte alligned"));
8109 inst.instruction |= inst.operands[0].reg << 12;
8110 if (!inst.operands[1].isreg)
8111 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8113 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8114 check_ldr_r15_aligned ();
8120 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8122 if (inst.operands[1].preind)
8124 constraint (inst.reloc.exp.X_op != O_constant
8125 || inst.reloc.exp.X_add_number != 0,
8126 _("this instruction requires a post-indexed address"));
8128 inst.operands[1].preind = 0;
8129 inst.operands[1].postind = 1;
8130 inst.operands[1].writeback = 1;
8132 inst.instruction |= inst.operands[0].reg << 12;
8133 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8136 /* Halfword and signed-byte load/store operations. */
8141 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8142 inst.instruction |= inst.operands[0].reg << 12;
8143 if (!inst.operands[1].isreg)
8144 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8146 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8152 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8154 if (inst.operands[1].preind)
8156 constraint (inst.reloc.exp.X_op != O_constant
8157 || inst.reloc.exp.X_add_number != 0,
8158 _("this instruction requires a post-indexed address"));
8160 inst.operands[1].preind = 0;
8161 inst.operands[1].postind = 1;
8162 inst.operands[1].writeback = 1;
8164 inst.instruction |= inst.operands[0].reg << 12;
8165 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8168 /* Co-processor register load/store.
8169 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8173 inst.instruction |= inst.operands[0].reg << 8;
8174 inst.instruction |= inst.operands[1].reg << 12;
8175 encode_arm_cp_address (2, TRUE, TRUE, 0);
8181 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8182 if (inst.operands[0].reg == inst.operands[1].reg
8183 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8184 && !(inst.instruction & 0x00400000))
8185 as_tsktsk (_("Rd and Rm should be different in mla"));
8187 inst.instruction |= inst.operands[0].reg << 16;
8188 inst.instruction |= inst.operands[1].reg;
8189 inst.instruction |= inst.operands[2].reg << 8;
8190 inst.instruction |= inst.operands[3].reg << 12;
8196 inst.instruction |= inst.operands[0].reg << 12;
8197 encode_arm_shifter_operand (1);
8200 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8207 top = (inst.instruction & 0x00400000) != 0;
8208 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8209 _(":lower16: not allowed this instruction"));
8210 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8211 _(":upper16: not allowed instruction"));
8212 inst.instruction |= inst.operands[0].reg << 12;
8213 if (inst.reloc.type == BFD_RELOC_UNUSED)
8215 imm = inst.reloc.exp.X_add_number;
8216 /* The value is in two pieces: 0:11, 16:19. */
8217 inst.instruction |= (imm & 0x00000fff);
8218 inst.instruction |= (imm & 0x0000f000) << 4;
8222 static void do_vfp_nsyn_opcode (const char *);
8225 do_vfp_nsyn_mrs (void)
8227 if (inst.operands[0].isvec)
8229 if (inst.operands[1].reg != 1)
8230 first_error (_("operand 1 must be FPSCR"));
8231 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8232 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8233 do_vfp_nsyn_opcode ("fmstat");
8235 else if (inst.operands[1].isvec)
8236 do_vfp_nsyn_opcode ("fmrx");
8244 do_vfp_nsyn_msr (void)
8246 if (inst.operands[0].isvec)
8247 do_vfp_nsyn_opcode ("fmxr");
8257 unsigned Rt = inst.operands[0].reg;
8259 if (thumb_mode && Rt == REG_SP)
8261 inst.error = BAD_SP;
8265 /* APSR_ sets isvec. All other refs to PC are illegal. */
8266 if (!inst.operands[0].isvec && Rt == REG_PC)
8268 inst.error = BAD_PC;
8272 /* If we get through parsing the register name, we just insert the number
8273 generated into the instruction without further validation. */
8274 inst.instruction |= (inst.operands[1].reg << 16);
8275 inst.instruction |= (Rt << 12);
8281 unsigned Rt = inst.operands[1].reg;
8284 reject_bad_reg (Rt);
8285 else if (Rt == REG_PC)
8287 inst.error = BAD_PC;
8291 /* If we get through parsing the register name, we just insert the number
8292 generated into the instruction without further validation. */
8293 inst.instruction |= (inst.operands[0].reg << 16);
8294 inst.instruction |= (Rt << 12);
8302 if (do_vfp_nsyn_mrs () == SUCCESS)
8305 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8306 inst.instruction |= inst.operands[0].reg << 12;
8308 if (inst.operands[1].isreg)
8310 br = inst.operands[1].reg;
8311 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8312 as_bad (_("bad register for mrs"));
8316 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8317 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8319 _("'APSR', 'CPSR' or 'SPSR' expected"));
8320 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8323 inst.instruction |= br;
8326 /* Two possible forms:
8327 "{C|S}PSR_<field>, Rm",
8328 "{C|S}PSR_f, #expression". */
8333 if (do_vfp_nsyn_msr () == SUCCESS)
8336 inst.instruction |= inst.operands[0].imm;
8337 if (inst.operands[1].isreg)
8338 inst.instruction |= inst.operands[1].reg;
8341 inst.instruction |= INST_IMMEDIATE;
8342 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8343 inst.reloc.pc_rel = 0;
8350 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8352 if (!inst.operands[2].present)
8353 inst.operands[2].reg = inst.operands[0].reg;
8354 inst.instruction |= inst.operands[0].reg << 16;
8355 inst.instruction |= inst.operands[1].reg;
8356 inst.instruction |= inst.operands[2].reg << 8;
8358 if (inst.operands[0].reg == inst.operands[1].reg
8359 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8360 as_tsktsk (_("Rd and Rm should be different in mul"));
8363 /* Long Multiply Parser
8364 UMULL RdLo, RdHi, Rm, Rs
8365 SMULL RdLo, RdHi, Rm, Rs
8366 UMLAL RdLo, RdHi, Rm, Rs
8367 SMLAL RdLo, RdHi, Rm, Rs. */
8372 inst.instruction |= inst.operands[0].reg << 12;
8373 inst.instruction |= inst.operands[1].reg << 16;
8374 inst.instruction |= inst.operands[2].reg;
8375 inst.instruction |= inst.operands[3].reg << 8;
8377 /* rdhi and rdlo must be different. */
8378 if (inst.operands[0].reg == inst.operands[1].reg)
8379 as_tsktsk (_("rdhi and rdlo must be different"));
8381 /* rdhi, rdlo and rm must all be different before armv6. */
8382 if ((inst.operands[0].reg == inst.operands[2].reg
8383 || inst.operands[1].reg == inst.operands[2].reg)
8384 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8385 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8391 if (inst.operands[0].present
8392 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8394 /* Architectural NOP hints are CPSR sets with no bits selected. */
8395 inst.instruction &= 0xf0000000;
8396 inst.instruction |= 0x0320f000;
8397 if (inst.operands[0].present)
8398 inst.instruction |= inst.operands[0].imm;
8402 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8403 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8404 Condition defaults to COND_ALWAYS.
8405 Error if Rd, Rn or Rm are R15. */
8410 inst.instruction |= inst.operands[0].reg << 12;
8411 inst.instruction |= inst.operands[1].reg << 16;
8412 inst.instruction |= inst.operands[2].reg;
8413 if (inst.operands[3].present)
8414 encode_arm_shift (3);
8417 /* ARM V6 PKHTB (Argument Parse). */
8422 if (!inst.operands[3].present)
8424 /* If the shift specifier is omitted, turn the instruction
8425 into pkhbt rd, rm, rn. */
8426 inst.instruction &= 0xfff00010;
8427 inst.instruction |= inst.operands[0].reg << 12;
8428 inst.instruction |= inst.operands[1].reg;
8429 inst.instruction |= inst.operands[2].reg << 16;
8433 inst.instruction |= inst.operands[0].reg << 12;
8434 inst.instruction |= inst.operands[1].reg << 16;
8435 inst.instruction |= inst.operands[2].reg;
8436 encode_arm_shift (3);
8440 /* ARMv5TE: Preload-Cache
8441 MP Extensions: Preload for write
8445 Syntactically, like LDR with B=1, W=0, L=1. */
8450 constraint (!inst.operands[0].isreg,
8451 _("'[' expected after PLD mnemonic"));
8452 constraint (inst.operands[0].postind,
8453 _("post-indexed expression used in preload instruction"));
8454 constraint (inst.operands[0].writeback,
8455 _("writeback used in preload instruction"));
8456 constraint (!inst.operands[0].preind,
8457 _("unindexed addressing used in preload instruction"));
8458 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8461 /* ARMv7: PLI <addr_mode> */
8465 constraint (!inst.operands[0].isreg,
8466 _("'[' expected after PLI mnemonic"));
8467 constraint (inst.operands[0].postind,
8468 _("post-indexed expression used in preload instruction"));
8469 constraint (inst.operands[0].writeback,
8470 _("writeback used in preload instruction"));
8471 constraint (!inst.operands[0].preind,
8472 _("unindexed addressing used in preload instruction"));
8473 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8474 inst.instruction &= ~PRE_INDEX;
8480 inst.operands[1] = inst.operands[0];
8481 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8482 inst.operands[0].isreg = 1;
8483 inst.operands[0].writeback = 1;
8484 inst.operands[0].reg = REG_SP;
8485 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8488 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8489 word at the specified address and the following word
8491 Unconditionally executed.
8492 Error if Rn is R15. */
8497 inst.instruction |= inst.operands[0].reg << 16;
8498 if (inst.operands[0].writeback)
8499 inst.instruction |= WRITE_BACK;
8502 /* ARM V6 ssat (argument parse). */
8507 inst.instruction |= inst.operands[0].reg << 12;
8508 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8509 inst.instruction |= inst.operands[2].reg;
8511 if (inst.operands[3].present)
8512 encode_arm_shift (3);
8515 /* ARM V6 usat (argument parse). */
8520 inst.instruction |= inst.operands[0].reg << 12;
8521 inst.instruction |= inst.operands[1].imm << 16;
8522 inst.instruction |= inst.operands[2].reg;
8524 if (inst.operands[3].present)
8525 encode_arm_shift (3);
8528 /* ARM V6 ssat16 (argument parse). */
8533 inst.instruction |= inst.operands[0].reg << 12;
8534 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8535 inst.instruction |= inst.operands[2].reg;
8541 inst.instruction |= inst.operands[0].reg << 12;
8542 inst.instruction |= inst.operands[1].imm << 16;
8543 inst.instruction |= inst.operands[2].reg;
8546 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8547 preserving the other bits.
8549 setend <endian_specifier>, where <endian_specifier> is either
8555 if (warn_on_deprecated
8556 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8557 as_warn (_("setend use is deprecated for ARMv8"));
8559 if (inst.operands[0].imm)
8560 inst.instruction |= 0x200;
8566 unsigned int Rm = (inst.operands[1].present
8567 ? inst.operands[1].reg
8568 : inst.operands[0].reg);
8570 inst.instruction |= inst.operands[0].reg << 12;
8571 inst.instruction |= Rm;
8572 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8574 inst.instruction |= inst.operands[2].reg << 8;
8575 inst.instruction |= SHIFT_BY_REG;
8576 /* PR 12854: Error on extraneous shifts. */
8577 constraint (inst.operands[2].shifted,
8578 _("extraneous shift as part of operand to shift insn"));
8581 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8587 inst.reloc.type = BFD_RELOC_ARM_SMC;
8588 inst.reloc.pc_rel = 0;
8594 inst.reloc.type = BFD_RELOC_ARM_HVC;
8595 inst.reloc.pc_rel = 0;
8601 inst.reloc.type = BFD_RELOC_ARM_SWI;
8602 inst.reloc.pc_rel = 0;
8605 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8606 SMLAxy{cond} Rd,Rm,Rs,Rn
8607 SMLAWy{cond} Rd,Rm,Rs,Rn
8608 Error if any register is R15. */
8613 inst.instruction |= inst.operands[0].reg << 16;
8614 inst.instruction |= inst.operands[1].reg;
8615 inst.instruction |= inst.operands[2].reg << 8;
8616 inst.instruction |= inst.operands[3].reg << 12;
8619 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8620 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8621 Error if any register is R15.
8622 Warning if Rdlo == Rdhi. */
8627 inst.instruction |= inst.operands[0].reg << 12;
8628 inst.instruction |= inst.operands[1].reg << 16;
8629 inst.instruction |= inst.operands[2].reg;
8630 inst.instruction |= inst.operands[3].reg << 8;
8632 if (inst.operands[0].reg == inst.operands[1].reg)
8633 as_tsktsk (_("rdhi and rdlo must be different"));
8636 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8637 SMULxy{cond} Rd,Rm,Rs
8638 Error if any register is R15. */
8643 inst.instruction |= inst.operands[0].reg << 16;
8644 inst.instruction |= inst.operands[1].reg;
8645 inst.instruction |= inst.operands[2].reg << 8;
8648 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8649 the same for both ARM and Thumb-2. */
8656 if (inst.operands[0].present)
8658 reg = inst.operands[0].reg;
8659 constraint (reg != REG_SP, _("SRS base register must be r13"));
8664 inst.instruction |= reg << 16;
8665 inst.instruction |= inst.operands[1].imm;
8666 if (inst.operands[0].writeback || inst.operands[1].writeback)
8667 inst.instruction |= WRITE_BACK;
8670 /* ARM V6 strex (argument parse). */
8675 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8676 || inst.operands[2].postind || inst.operands[2].writeback
8677 || inst.operands[2].immisreg || inst.operands[2].shifted
8678 || inst.operands[2].negative
8679 /* See comment in do_ldrex(). */
8680 || (inst.operands[2].reg == REG_PC),
8683 constraint (inst.operands[0].reg == inst.operands[1].reg
8684 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8686 constraint (inst.reloc.exp.X_op != O_constant
8687 || inst.reloc.exp.X_add_number != 0,
8688 _("offset must be zero in ARM encoding"));
8690 inst.instruction |= inst.operands[0].reg << 12;
8691 inst.instruction |= inst.operands[1].reg;
8692 inst.instruction |= inst.operands[2].reg << 16;
8693 inst.reloc.type = BFD_RELOC_UNUSED;
8699 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8700 || inst.operands[2].postind || inst.operands[2].writeback
8701 || inst.operands[2].immisreg || inst.operands[2].shifted
8702 || inst.operands[2].negative,
8705 constraint (inst.operands[0].reg == inst.operands[1].reg
8706 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8714 constraint (inst.operands[1].reg % 2 != 0,
8715 _("even register required"));
8716 constraint (inst.operands[2].present
8717 && inst.operands[2].reg != inst.operands[1].reg + 1,
8718 _("can only store two consecutive registers"));
8719 /* If op 2 were present and equal to PC, this function wouldn't
8720 have been called in the first place. */
8721 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8723 constraint (inst.operands[0].reg == inst.operands[1].reg
8724 || inst.operands[0].reg == inst.operands[1].reg + 1
8725 || inst.operands[0].reg == inst.operands[3].reg,
8728 inst.instruction |= inst.operands[0].reg << 12;
8729 inst.instruction |= inst.operands[1].reg;
8730 inst.instruction |= inst.operands[3].reg << 16;
8737 constraint (inst.operands[0].reg == inst.operands[1].reg
8738 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8746 constraint (inst.operands[0].reg == inst.operands[1].reg
8747 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8752 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8753 extends it to 32-bits, and adds the result to a value in another
8754 register. You can specify a rotation by 0, 8, 16, or 24 bits
8755 before extracting the 16-bit value.
8756 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8757 Condition defaults to COND_ALWAYS.
8758 Error if any register uses R15. */
8763 inst.instruction |= inst.operands[0].reg << 12;
8764 inst.instruction |= inst.operands[1].reg << 16;
8765 inst.instruction |= inst.operands[2].reg;
8766 inst.instruction |= inst.operands[3].imm << 10;
8771 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8772 Condition defaults to COND_ALWAYS.
8773 Error if any register uses R15. */
8778 inst.instruction |= inst.operands[0].reg << 12;
8779 inst.instruction |= inst.operands[1].reg;
8780 inst.instruction |= inst.operands[2].imm << 10;
8783 /* VFP instructions. In a logical order: SP variant first, monad
8784 before dyad, arithmetic then move then load/store. */
8787 do_vfp_sp_monadic (void)
8789 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8790 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8794 do_vfp_sp_dyadic (void)
8796 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8797 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8798 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8802 do_vfp_sp_compare_z (void)
8804 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8808 do_vfp_dp_sp_cvt (void)
8810 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8811 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8815 do_vfp_sp_dp_cvt (void)
8817 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8818 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8822 do_vfp_reg_from_sp (void)
8824 inst.instruction |= inst.operands[0].reg << 12;
8825 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8829 do_vfp_reg2_from_sp2 (void)
8831 constraint (inst.operands[2].imm != 2,
8832 _("only two consecutive VFP SP registers allowed here"));
8833 inst.instruction |= inst.operands[0].reg << 12;
8834 inst.instruction |= inst.operands[1].reg << 16;
8835 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8839 do_vfp_sp_from_reg (void)
8841 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8842 inst.instruction |= inst.operands[1].reg << 12;
8846 do_vfp_sp2_from_reg2 (void)
8848 constraint (inst.operands[0].imm != 2,
8849 _("only two consecutive VFP SP registers allowed here"));
8850 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8851 inst.instruction |= inst.operands[1].reg << 12;
8852 inst.instruction |= inst.operands[2].reg << 16;
8856 do_vfp_sp_ldst (void)
8858 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8859 encode_arm_cp_address (1, FALSE, TRUE, 0);
8863 do_vfp_dp_ldst (void)
8865 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8866 encode_arm_cp_address (1, FALSE, TRUE, 0);
8871 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8873 if (inst.operands[0].writeback)
8874 inst.instruction |= WRITE_BACK;
8876 constraint (ldstm_type != VFP_LDSTMIA,
8877 _("this addressing mode requires base-register writeback"));
8878 inst.instruction |= inst.operands[0].reg << 16;
8879 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8880 inst.instruction |= inst.operands[1].imm;
8884 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8888 if (inst.operands[0].writeback)
8889 inst.instruction |= WRITE_BACK;
8891 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8892 _("this addressing mode requires base-register writeback"));
8894 inst.instruction |= inst.operands[0].reg << 16;
8895 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8897 count = inst.operands[1].imm << 1;
8898 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8901 inst.instruction |= count;
8905 do_vfp_sp_ldstmia (void)
8907 vfp_sp_ldstm (VFP_LDSTMIA);
8911 do_vfp_sp_ldstmdb (void)
8913 vfp_sp_ldstm (VFP_LDSTMDB);
8917 do_vfp_dp_ldstmia (void)
8919 vfp_dp_ldstm (VFP_LDSTMIA);
8923 do_vfp_dp_ldstmdb (void)
8925 vfp_dp_ldstm (VFP_LDSTMDB);
8929 do_vfp_xp_ldstmia (void)
8931 vfp_dp_ldstm (VFP_LDSTMIAX);
8935 do_vfp_xp_ldstmdb (void)
8937 vfp_dp_ldstm (VFP_LDSTMDBX);
8941 do_vfp_dp_rd_rm (void)
8943 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8944 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8948 do_vfp_dp_rn_rd (void)
8950 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8951 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8955 do_vfp_dp_rd_rn (void)
8957 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8958 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8962 do_vfp_dp_rd_rn_rm (void)
8964 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8965 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8966 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8972 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8976 do_vfp_dp_rm_rd_rn (void)
8978 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8979 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8980 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8983 /* VFPv3 instructions. */
8985 do_vfp_sp_const (void)
8987 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8988 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8989 inst.instruction |= (inst.operands[1].imm & 0x0f);
8993 do_vfp_dp_const (void)
8995 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8996 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8997 inst.instruction |= (inst.operands[1].imm & 0x0f);
9001 vfp_conv (int srcsize)
9003 int immbits = srcsize - inst.operands[1].imm;
9005 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9007 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9008 i.e. immbits must be in range 0 - 16. */
9009 inst.error = _("immediate value out of range, expected range [0, 16]");
9012 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9014 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9015 i.e. immbits must be in range 0 - 31. */
9016 inst.error = _("immediate value out of range, expected range [1, 32]");
9020 inst.instruction |= (immbits & 1) << 5;
9021 inst.instruction |= (immbits >> 1);
9025 do_vfp_sp_conv_16 (void)
9027 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9032 do_vfp_dp_conv_16 (void)
9034 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9039 do_vfp_sp_conv_32 (void)
9041 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9046 do_vfp_dp_conv_32 (void)
9048 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9052 /* FPA instructions. Also in a logical order. */
9057 inst.instruction |= inst.operands[0].reg << 16;
9058 inst.instruction |= inst.operands[1].reg;
9062 do_fpa_ldmstm (void)
9064 inst.instruction |= inst.operands[0].reg << 12;
9065 switch (inst.operands[1].imm)
9067 case 1: inst.instruction |= CP_T_X; break;
9068 case 2: inst.instruction |= CP_T_Y; break;
9069 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9074 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9076 /* The instruction specified "ea" or "fd", so we can only accept
9077 [Rn]{!}. The instruction does not really support stacking or
9078 unstacking, so we have to emulate these by setting appropriate
9079 bits and offsets. */
9080 constraint (inst.reloc.exp.X_op != O_constant
9081 || inst.reloc.exp.X_add_number != 0,
9082 _("this instruction does not support indexing"));
9084 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9085 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9087 if (!(inst.instruction & INDEX_UP))
9088 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9090 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9092 inst.operands[2].preind = 0;
9093 inst.operands[2].postind = 1;
9097 encode_arm_cp_address (2, TRUE, TRUE, 0);
9100 /* iWMMXt instructions: strictly in alphabetical order. */
9103 do_iwmmxt_tandorc (void)
9105 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9109 do_iwmmxt_textrc (void)
9111 inst.instruction |= inst.operands[0].reg << 12;
9112 inst.instruction |= inst.operands[1].imm;
9116 do_iwmmxt_textrm (void)
9118 inst.instruction |= inst.operands[0].reg << 12;
9119 inst.instruction |= inst.operands[1].reg << 16;
9120 inst.instruction |= inst.operands[2].imm;
9124 do_iwmmxt_tinsr (void)
9126 inst.instruction |= inst.operands[0].reg << 16;
9127 inst.instruction |= inst.operands[1].reg << 12;
9128 inst.instruction |= inst.operands[2].imm;
9132 do_iwmmxt_tmia (void)
9134 inst.instruction |= inst.operands[0].reg << 5;
9135 inst.instruction |= inst.operands[1].reg;
9136 inst.instruction |= inst.operands[2].reg << 12;
9140 do_iwmmxt_waligni (void)
9142 inst.instruction |= inst.operands[0].reg << 12;
9143 inst.instruction |= inst.operands[1].reg << 16;
9144 inst.instruction |= inst.operands[2].reg;
9145 inst.instruction |= inst.operands[3].imm << 20;
9149 do_iwmmxt_wmerge (void)
9151 inst.instruction |= inst.operands[0].reg << 12;
9152 inst.instruction |= inst.operands[1].reg << 16;
9153 inst.instruction |= inst.operands[2].reg;
9154 inst.instruction |= inst.operands[3].imm << 21;
9158 do_iwmmxt_wmov (void)
9160 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9161 inst.instruction |= inst.operands[0].reg << 12;
9162 inst.instruction |= inst.operands[1].reg << 16;
9163 inst.instruction |= inst.operands[1].reg;
9167 do_iwmmxt_wldstbh (void)
9170 inst.instruction |= inst.operands[0].reg << 12;
9172 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9174 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9175 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9179 do_iwmmxt_wldstw (void)
9181 /* RIWR_RIWC clears .isreg for a control register. */
9182 if (!inst.operands[0].isreg)
9184 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9185 inst.instruction |= 0xf0000000;
9188 inst.instruction |= inst.operands[0].reg << 12;
9189 encode_arm_cp_address (1, TRUE, TRUE, 0);
9193 do_iwmmxt_wldstd (void)
9195 inst.instruction |= inst.operands[0].reg << 12;
9196 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9197 && inst.operands[1].immisreg)
9199 inst.instruction &= ~0x1a000ff;
9200 inst.instruction |= (0xf << 28);
9201 if (inst.operands[1].preind)
9202 inst.instruction |= PRE_INDEX;
9203 if (!inst.operands[1].negative)
9204 inst.instruction |= INDEX_UP;
9205 if (inst.operands[1].writeback)
9206 inst.instruction |= WRITE_BACK;
9207 inst.instruction |= inst.operands[1].reg << 16;
9208 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9209 inst.instruction |= inst.operands[1].imm;
9212 encode_arm_cp_address (1, TRUE, FALSE, 0);
9216 do_iwmmxt_wshufh (void)
9218 inst.instruction |= inst.operands[0].reg << 12;
9219 inst.instruction |= inst.operands[1].reg << 16;
9220 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9221 inst.instruction |= (inst.operands[2].imm & 0x0f);
9225 do_iwmmxt_wzero (void)
9227 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9228 inst.instruction |= inst.operands[0].reg;
9229 inst.instruction |= inst.operands[0].reg << 12;
9230 inst.instruction |= inst.operands[0].reg << 16;
9234 do_iwmmxt_wrwrwr_or_imm5 (void)
9236 if (inst.operands[2].isreg)
9239 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9240 _("immediate operand requires iWMMXt2"));
9242 if (inst.operands[2].imm == 0)
9244 switch ((inst.instruction >> 20) & 0xf)
9250 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9251 inst.operands[2].imm = 16;
9252 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9258 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9259 inst.operands[2].imm = 32;
9260 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9267 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9269 wrn = (inst.instruction >> 16) & 0xf;
9270 inst.instruction &= 0xff0fff0f;
9271 inst.instruction |= wrn;
9272 /* Bail out here; the instruction is now assembled. */
9277 /* Map 32 -> 0, etc. */
9278 inst.operands[2].imm &= 0x1f;
9279 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9283 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9284 operations first, then control, shift, and load/store. */
9286 /* Insns like "foo X,Y,Z". */
9289 do_mav_triple (void)
9291 inst.instruction |= inst.operands[0].reg << 16;
9292 inst.instruction |= inst.operands[1].reg;
9293 inst.instruction |= inst.operands[2].reg << 12;
9296 /* Insns like "foo W,X,Y,Z".
9297 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9302 inst.instruction |= inst.operands[0].reg << 5;
9303 inst.instruction |= inst.operands[1].reg << 12;
9304 inst.instruction |= inst.operands[2].reg << 16;
9305 inst.instruction |= inst.operands[3].reg;
9308 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9312 inst.instruction |= inst.operands[1].reg << 12;
9315 /* Maverick shift immediate instructions.
9316 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9317 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9322 int imm = inst.operands[2].imm;
9324 inst.instruction |= inst.operands[0].reg << 12;
9325 inst.instruction |= inst.operands[1].reg << 16;
9327 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9328 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9329 Bit 4 should be 0. */
9330 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9332 inst.instruction |= imm;
9335 /* XScale instructions. Also sorted arithmetic before move. */
9337 /* Xscale multiply-accumulate (argument parse)
9340 MIAxycc acc0,Rm,Rs. */
9345 inst.instruction |= inst.operands[1].reg;
9346 inst.instruction |= inst.operands[2].reg << 12;
9349 /* Xscale move-accumulator-register (argument parse)
9351 MARcc acc0,RdLo,RdHi. */
9356 inst.instruction |= inst.operands[1].reg << 12;
9357 inst.instruction |= inst.operands[2].reg << 16;
9360 /* Xscale move-register-accumulator (argument parse)
9362 MRAcc RdLo,RdHi,acc0. */
9367 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9368 inst.instruction |= inst.operands[0].reg << 12;
9369 inst.instruction |= inst.operands[1].reg << 16;
9372 /* Encoding functions relevant only to Thumb. */
9374 /* inst.operands[i] is a shifted-register operand; encode
9375 it into inst.instruction in the format used by Thumb32. */
9378 encode_thumb32_shifted_operand (int i)
9380 unsigned int value = inst.reloc.exp.X_add_number;
9381 unsigned int shift = inst.operands[i].shift_kind;
9383 constraint (inst.operands[i].immisreg,
9384 _("shift by register not allowed in thumb mode"));
9385 inst.instruction |= inst.operands[i].reg;
9386 if (shift == SHIFT_RRX)
9387 inst.instruction |= SHIFT_ROR << 4;
9390 constraint (inst.reloc.exp.X_op != O_constant,
9391 _("expression too complex"));
9393 constraint (value > 32
9394 || (value == 32 && (shift == SHIFT_LSL
9395 || shift == SHIFT_ROR)),
9396 _("shift expression is too large"));
9400 else if (value == 32)
9403 inst.instruction |= shift << 4;
9404 inst.instruction |= (value & 0x1c) << 10;
9405 inst.instruction |= (value & 0x03) << 6;
9410 /* inst.operands[i] was set up by parse_address. Encode it into a
9411 Thumb32 format load or store instruction. Reject forms that cannot
9412 be used with such instructions. If is_t is true, reject forms that
9413 cannot be used with a T instruction; if is_d is true, reject forms
9414 that cannot be used with a D instruction. If it is a store insn,
9418 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9420 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9422 constraint (!inst.operands[i].isreg,
9423 _("Instruction does not support =N addresses"));
9425 inst.instruction |= inst.operands[i].reg << 16;
9426 if (inst.operands[i].immisreg)
9428 constraint (is_pc, BAD_PC_ADDRESSING);
9429 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9430 constraint (inst.operands[i].negative,
9431 _("Thumb does not support negative register indexing"));
9432 constraint (inst.operands[i].postind,
9433 _("Thumb does not support register post-indexing"));
9434 constraint (inst.operands[i].writeback,
9435 _("Thumb does not support register indexing with writeback"));
9436 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9437 _("Thumb supports only LSL in shifted register indexing"));
9439 inst.instruction |= inst.operands[i].imm;
9440 if (inst.operands[i].shifted)
9442 constraint (inst.reloc.exp.X_op != O_constant,
9443 _("expression too complex"));
9444 constraint (inst.reloc.exp.X_add_number < 0
9445 || inst.reloc.exp.X_add_number > 3,
9446 _("shift out of range"));
9447 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9449 inst.reloc.type = BFD_RELOC_UNUSED;
9451 else if (inst.operands[i].preind)
9453 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9454 constraint (is_t && inst.operands[i].writeback,
9455 _("cannot use writeback with this instruction"));
9456 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
9461 inst.instruction |= 0x01000000;
9462 if (inst.operands[i].writeback)
9463 inst.instruction |= 0x00200000;
9467 inst.instruction |= 0x00000c00;
9468 if (inst.operands[i].writeback)
9469 inst.instruction |= 0x00000100;
9471 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9473 else if (inst.operands[i].postind)
9475 gas_assert (inst.operands[i].writeback);
9476 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9477 constraint (is_t, _("cannot use post-indexing with this instruction"));
9480 inst.instruction |= 0x00200000;
9482 inst.instruction |= 0x00000900;
9483 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9485 else /* unindexed - only for coprocessor */
9486 inst.error = _("instruction does not accept unindexed addressing");
9489 /* Table of Thumb instructions which exist in both 16- and 32-bit
9490 encodings (the latter only in post-V6T2 cores). The index is the
9491 value used in the insns table below. When there is more than one
9492 possible 16-bit encoding for the instruction, this table always
9494 Also contains several pseudo-instructions used during relaxation. */
9495 #define T16_32_TAB \
9496 X(_adc, 4140, eb400000), \
9497 X(_adcs, 4140, eb500000), \
9498 X(_add, 1c00, eb000000), \
9499 X(_adds, 1c00, eb100000), \
9500 X(_addi, 0000, f1000000), \
9501 X(_addis, 0000, f1100000), \
9502 X(_add_pc,000f, f20f0000), \
9503 X(_add_sp,000d, f10d0000), \
9504 X(_adr, 000f, f20f0000), \
9505 X(_and, 4000, ea000000), \
9506 X(_ands, 4000, ea100000), \
9507 X(_asr, 1000, fa40f000), \
9508 X(_asrs, 1000, fa50f000), \
9509 X(_b, e000, f000b000), \
9510 X(_bcond, d000, f0008000), \
9511 X(_bic, 4380, ea200000), \
9512 X(_bics, 4380, ea300000), \
9513 X(_cmn, 42c0, eb100f00), \
9514 X(_cmp, 2800, ebb00f00), \
9515 X(_cpsie, b660, f3af8400), \
9516 X(_cpsid, b670, f3af8600), \
9517 X(_cpy, 4600, ea4f0000), \
9518 X(_dec_sp,80dd, f1ad0d00), \
9519 X(_eor, 4040, ea800000), \
9520 X(_eors, 4040, ea900000), \
9521 X(_inc_sp,00dd, f10d0d00), \
9522 X(_ldmia, c800, e8900000), \
9523 X(_ldr, 6800, f8500000), \
9524 X(_ldrb, 7800, f8100000), \
9525 X(_ldrh, 8800, f8300000), \
9526 X(_ldrsb, 5600, f9100000), \
9527 X(_ldrsh, 5e00, f9300000), \
9528 X(_ldr_pc,4800, f85f0000), \
9529 X(_ldr_pc2,4800, f85f0000), \
9530 X(_ldr_sp,9800, f85d0000), \
9531 X(_lsl, 0000, fa00f000), \
9532 X(_lsls, 0000, fa10f000), \
9533 X(_lsr, 0800, fa20f000), \
9534 X(_lsrs, 0800, fa30f000), \
9535 X(_mov, 2000, ea4f0000), \
9536 X(_movs, 2000, ea5f0000), \
9537 X(_mul, 4340, fb00f000), \
9538 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9539 X(_mvn, 43c0, ea6f0000), \
9540 X(_mvns, 43c0, ea7f0000), \
9541 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9542 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9543 X(_orr, 4300, ea400000), \
9544 X(_orrs, 4300, ea500000), \
9545 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9546 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9547 X(_rev, ba00, fa90f080), \
9548 X(_rev16, ba40, fa90f090), \
9549 X(_revsh, bac0, fa90f0b0), \
9550 X(_ror, 41c0, fa60f000), \
9551 X(_rors, 41c0, fa70f000), \
9552 X(_sbc, 4180, eb600000), \
9553 X(_sbcs, 4180, eb700000), \
9554 X(_stmia, c000, e8800000), \
9555 X(_str, 6000, f8400000), \
9556 X(_strb, 7000, f8000000), \
9557 X(_strh, 8000, f8200000), \
9558 X(_str_sp,9000, f84d0000), \
9559 X(_sub, 1e00, eba00000), \
9560 X(_subs, 1e00, ebb00000), \
9561 X(_subi, 8000, f1a00000), \
9562 X(_subis, 8000, f1b00000), \
9563 X(_sxtb, b240, fa4ff080), \
9564 X(_sxth, b200, fa0ff080), \
9565 X(_tst, 4200, ea100f00), \
9566 X(_uxtb, b2c0, fa5ff080), \
9567 X(_uxth, b280, fa1ff080), \
9568 X(_nop, bf00, f3af8000), \
9569 X(_yield, bf10, f3af8001), \
9570 X(_wfe, bf20, f3af8002), \
9571 X(_wfi, bf30, f3af8003), \
9572 X(_sev, bf40, f3af8004), \
9573 X(_sevl, bf50, f3af8005)
9575 /* To catch errors in encoding functions, the codes are all offset by
9576 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9577 as 16-bit instructions. */
9578 #define X(a,b,c) T_MNEM##a
9579 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9582 #define X(a,b,c) 0x##b
9583 static const unsigned short thumb_op16[] = { T16_32_TAB };
9584 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9587 #define X(a,b,c) 0x##c
9588 static const unsigned int thumb_op32[] = { T16_32_TAB };
9589 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9590 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9594 /* Thumb instruction encoders, in alphabetical order. */
9599 do_t_add_sub_w (void)
9603 Rd = inst.operands[0].reg;
9604 Rn = inst.operands[1].reg;
9606 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9607 is the SP-{plus,minus}-immediate form of the instruction. */
9609 constraint (Rd == REG_PC, BAD_PC);
9611 reject_bad_reg (Rd);
9613 inst.instruction |= (Rn << 16) | (Rd << 8);
9614 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9617 /* Parse an add or subtract instruction. We get here with inst.instruction
9618 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9625 Rd = inst.operands[0].reg;
9626 Rs = (inst.operands[1].present
9627 ? inst.operands[1].reg /* Rd, Rs, foo */
9628 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9631 set_it_insn_type_last ();
9639 flags = (inst.instruction == T_MNEM_adds
9640 || inst.instruction == T_MNEM_subs);
9642 narrow = !in_it_block ();
9644 narrow = in_it_block ();
9645 if (!inst.operands[2].isreg)
9649 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9651 add = (inst.instruction == T_MNEM_add
9652 || inst.instruction == T_MNEM_adds);
9654 if (inst.size_req != 4)
9656 /* Attempt to use a narrow opcode, with relaxation if
9658 if (Rd == REG_SP && Rs == REG_SP && !flags)
9659 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9660 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9661 opcode = T_MNEM_add_sp;
9662 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9663 opcode = T_MNEM_add_pc;
9664 else if (Rd <= 7 && Rs <= 7 && narrow)
9667 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9669 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9673 inst.instruction = THUMB_OP16(opcode);
9674 inst.instruction |= (Rd << 4) | Rs;
9675 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9676 if (inst.size_req != 2)
9677 inst.relax = opcode;
9680 constraint (inst.size_req == 2, BAD_HIREG);
9682 if (inst.size_req == 4
9683 || (inst.size_req != 2 && !opcode))
9687 constraint (add, BAD_PC);
9688 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9689 _("only SUBS PC, LR, #const allowed"));
9690 constraint (inst.reloc.exp.X_op != O_constant,
9691 _("expression too complex"));
9692 constraint (inst.reloc.exp.X_add_number < 0
9693 || inst.reloc.exp.X_add_number > 0xff,
9694 _("immediate value out of range"));
9695 inst.instruction = T2_SUBS_PC_LR
9696 | inst.reloc.exp.X_add_number;
9697 inst.reloc.type = BFD_RELOC_UNUSED;
9700 else if (Rs == REG_PC)
9702 /* Always use addw/subw. */
9703 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9704 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9708 inst.instruction = THUMB_OP32 (inst.instruction);
9709 inst.instruction = (inst.instruction & 0xe1ffffff)
9712 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9714 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9716 inst.instruction |= Rd << 8;
9717 inst.instruction |= Rs << 16;
9722 unsigned int value = inst.reloc.exp.X_add_number;
9723 unsigned int shift = inst.operands[2].shift_kind;
9725 Rn = inst.operands[2].reg;
9726 /* See if we can do this with a 16-bit instruction. */
9727 if (!inst.operands[2].shifted && inst.size_req != 4)
9729 if (Rd > 7 || Rs > 7 || Rn > 7)
9734 inst.instruction = ((inst.instruction == T_MNEM_adds
9735 || inst.instruction == T_MNEM_add)
9738 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9742 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9744 /* Thumb-1 cores (except v6-M) require at least one high
9745 register in a narrow non flag setting add. */
9746 if (Rd > 7 || Rn > 7
9747 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9748 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9755 inst.instruction = T_OPCODE_ADD_HI;
9756 inst.instruction |= (Rd & 8) << 4;
9757 inst.instruction |= (Rd & 7);
9758 inst.instruction |= Rn << 3;
9764 constraint (Rd == REG_PC, BAD_PC);
9765 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9766 constraint (Rs == REG_PC, BAD_PC);
9767 reject_bad_reg (Rn);
9769 /* If we get here, it can't be done in 16 bits. */
9770 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9771 _("shift must be constant"));
9772 inst.instruction = THUMB_OP32 (inst.instruction);
9773 inst.instruction |= Rd << 8;
9774 inst.instruction |= Rs << 16;
9775 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9776 _("shift value over 3 not allowed in thumb mode"));
9777 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9778 _("only LSL shift allowed in thumb mode"));
9779 encode_thumb32_shifted_operand (2);
9784 constraint (inst.instruction == T_MNEM_adds
9785 || inst.instruction == T_MNEM_subs,
9788 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9790 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9791 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9794 inst.instruction = (inst.instruction == T_MNEM_add
9796 inst.instruction |= (Rd << 4) | Rs;
9797 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9801 Rn = inst.operands[2].reg;
9802 constraint (inst.operands[2].shifted, _("unshifted register required"));
9804 /* We now have Rd, Rs, and Rn set to registers. */
9805 if (Rd > 7 || Rs > 7 || Rn > 7)
9807 /* Can't do this for SUB. */
9808 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9809 inst.instruction = T_OPCODE_ADD_HI;
9810 inst.instruction |= (Rd & 8) << 4;
9811 inst.instruction |= (Rd & 7);
9813 inst.instruction |= Rn << 3;
9815 inst.instruction |= Rs << 3;
9817 constraint (1, _("dest must overlap one source register"));
9821 inst.instruction = (inst.instruction == T_MNEM_add
9822 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9823 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9833 Rd = inst.operands[0].reg;
9834 reject_bad_reg (Rd);
9836 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9838 /* Defer to section relaxation. */
9839 inst.relax = inst.instruction;
9840 inst.instruction = THUMB_OP16 (inst.instruction);
9841 inst.instruction |= Rd << 4;
9843 else if (unified_syntax && inst.size_req != 2)
9845 /* Generate a 32-bit opcode. */
9846 inst.instruction = THUMB_OP32 (inst.instruction);
9847 inst.instruction |= Rd << 8;
9848 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9849 inst.reloc.pc_rel = 1;
9853 /* Generate a 16-bit opcode. */
9854 inst.instruction = THUMB_OP16 (inst.instruction);
9855 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9856 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9857 inst.reloc.pc_rel = 1;
9859 inst.instruction |= Rd << 4;
9863 /* Arithmetic instructions for which there is just one 16-bit
9864 instruction encoding, and it allows only two low registers.
9865 For maximal compatibility with ARM syntax, we allow three register
9866 operands even when Thumb-32 instructions are not available, as long
9867 as the first two are identical. For instance, both "sbc r0,r1" and
9868 "sbc r0,r0,r1" are allowed. */
9874 Rd = inst.operands[0].reg;
9875 Rs = (inst.operands[1].present
9876 ? inst.operands[1].reg /* Rd, Rs, foo */
9877 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9878 Rn = inst.operands[2].reg;
9880 reject_bad_reg (Rd);
9881 reject_bad_reg (Rs);
9882 if (inst.operands[2].isreg)
9883 reject_bad_reg (Rn);
9887 if (!inst.operands[2].isreg)
9889 /* For an immediate, we always generate a 32-bit opcode;
9890 section relaxation will shrink it later if possible. */
9891 inst.instruction = THUMB_OP32 (inst.instruction);
9892 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9893 inst.instruction |= Rd << 8;
9894 inst.instruction |= Rs << 16;
9895 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9901 /* See if we can do this with a 16-bit instruction. */
9902 if (THUMB_SETS_FLAGS (inst.instruction))
9903 narrow = !in_it_block ();
9905 narrow = in_it_block ();
9907 if (Rd > 7 || Rn > 7 || Rs > 7)
9909 if (inst.operands[2].shifted)
9911 if (inst.size_req == 4)
9917 inst.instruction = THUMB_OP16 (inst.instruction);
9918 inst.instruction |= Rd;
9919 inst.instruction |= Rn << 3;
9923 /* If we get here, it can't be done in 16 bits. */
9924 constraint (inst.operands[2].shifted
9925 && inst.operands[2].immisreg,
9926 _("shift must be constant"));
9927 inst.instruction = THUMB_OP32 (inst.instruction);
9928 inst.instruction |= Rd << 8;
9929 inst.instruction |= Rs << 16;
9930 encode_thumb32_shifted_operand (2);
9935 /* On its face this is a lie - the instruction does set the
9936 flags. However, the only supported mnemonic in this mode
9938 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9940 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9941 _("unshifted register required"));
9942 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9943 constraint (Rd != Rs,
9944 _("dest and source1 must be the same register"));
9946 inst.instruction = THUMB_OP16 (inst.instruction);
9947 inst.instruction |= Rd;
9948 inst.instruction |= Rn << 3;
9952 /* Similarly, but for instructions where the arithmetic operation is
9953 commutative, so we can allow either of them to be different from
9954 the destination operand in a 16-bit instruction. For instance, all
9955 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9962 Rd = inst.operands[0].reg;
9963 Rs = (inst.operands[1].present
9964 ? inst.operands[1].reg /* Rd, Rs, foo */
9965 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9966 Rn = inst.operands[2].reg;
9968 reject_bad_reg (Rd);
9969 reject_bad_reg (Rs);
9970 if (inst.operands[2].isreg)
9971 reject_bad_reg (Rn);
9975 if (!inst.operands[2].isreg)
9977 /* For an immediate, we always generate a 32-bit opcode;
9978 section relaxation will shrink it later if possible. */
9979 inst.instruction = THUMB_OP32 (inst.instruction);
9980 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9981 inst.instruction |= Rd << 8;
9982 inst.instruction |= Rs << 16;
9983 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9989 /* See if we can do this with a 16-bit instruction. */
9990 if (THUMB_SETS_FLAGS (inst.instruction))
9991 narrow = !in_it_block ();
9993 narrow = in_it_block ();
9995 if (Rd > 7 || Rn > 7 || Rs > 7)
9997 if (inst.operands[2].shifted)
9999 if (inst.size_req == 4)
10006 inst.instruction = THUMB_OP16 (inst.instruction);
10007 inst.instruction |= Rd;
10008 inst.instruction |= Rn << 3;
10013 inst.instruction = THUMB_OP16 (inst.instruction);
10014 inst.instruction |= Rd;
10015 inst.instruction |= Rs << 3;
10020 /* If we get here, it can't be done in 16 bits. */
10021 constraint (inst.operands[2].shifted
10022 && inst.operands[2].immisreg,
10023 _("shift must be constant"));
10024 inst.instruction = THUMB_OP32 (inst.instruction);
10025 inst.instruction |= Rd << 8;
10026 inst.instruction |= Rs << 16;
10027 encode_thumb32_shifted_operand (2);
10032 /* On its face this is a lie - the instruction does set the
10033 flags. However, the only supported mnemonic in this mode
10034 says it doesn't. */
10035 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10037 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10038 _("unshifted register required"));
10039 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10041 inst.instruction = THUMB_OP16 (inst.instruction);
10042 inst.instruction |= Rd;
10045 inst.instruction |= Rn << 3;
10047 inst.instruction |= Rs << 3;
10049 constraint (1, _("dest must overlap one source register"));
10054 do_t_barrier (void)
10056 if (inst.operands[0].present)
10058 constraint ((inst.instruction & 0xf0) != 0x40
10059 && inst.operands[0].imm > 0xf
10060 && inst.operands[0].imm < 0x0,
10061 _("bad barrier type"));
10062 inst.instruction |= inst.operands[0].imm;
10065 inst.instruction |= 0xf;
10072 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10073 constraint (msb > 32, _("bit-field extends past end of register"));
10074 /* The instruction encoding stores the LSB and MSB,
10075 not the LSB and width. */
10076 Rd = inst.operands[0].reg;
10077 reject_bad_reg (Rd);
10078 inst.instruction |= Rd << 8;
10079 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10080 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10081 inst.instruction |= msb - 1;
10090 Rd = inst.operands[0].reg;
10091 reject_bad_reg (Rd);
10093 /* #0 in second position is alternative syntax for bfc, which is
10094 the same instruction but with REG_PC in the Rm field. */
10095 if (!inst.operands[1].isreg)
10099 Rn = inst.operands[1].reg;
10100 reject_bad_reg (Rn);
10103 msb = inst.operands[2].imm + inst.operands[3].imm;
10104 constraint (msb > 32, _("bit-field extends past end of register"));
10105 /* The instruction encoding stores the LSB and MSB,
10106 not the LSB and width. */
10107 inst.instruction |= Rd << 8;
10108 inst.instruction |= Rn << 16;
10109 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10110 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10111 inst.instruction |= msb - 1;
10119 Rd = inst.operands[0].reg;
10120 Rn = inst.operands[1].reg;
10122 reject_bad_reg (Rd);
10123 reject_bad_reg (Rn);
10125 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10126 _("bit-field extends past end of register"));
10127 inst.instruction |= Rd << 8;
10128 inst.instruction |= Rn << 16;
10129 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10130 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10131 inst.instruction |= inst.operands[3].imm - 1;
10134 /* ARM V5 Thumb BLX (argument parse)
10135 BLX <target_addr> which is BLX(1)
10136 BLX <Rm> which is BLX(2)
10137 Unfortunately, there are two different opcodes for this mnemonic.
10138 So, the insns[].value is not used, and the code here zaps values
10139 into inst.instruction.
10141 ??? How to take advantage of the additional two bits of displacement
10142 available in Thumb32 mode? Need new relocation? */
10147 set_it_insn_type_last ();
10149 if (inst.operands[0].isreg)
10151 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10152 /* We have a register, so this is BLX(2). */
10153 inst.instruction |= inst.operands[0].reg << 3;
10157 /* No register. This must be BLX(1). */
10158 inst.instruction = 0xf000e800;
10159 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10171 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10173 if (in_it_block ())
10175 /* Conditional branches inside IT blocks are encoded as unconditional
10177 cond = COND_ALWAYS;
10182 if (cond != COND_ALWAYS)
10183 opcode = T_MNEM_bcond;
10185 opcode = inst.instruction;
10188 && (inst.size_req == 4
10189 || (inst.size_req != 2
10190 && (inst.operands[0].hasreloc
10191 || inst.reloc.exp.X_op == O_constant))))
10193 inst.instruction = THUMB_OP32(opcode);
10194 if (cond == COND_ALWAYS)
10195 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10198 gas_assert (cond != 0xF);
10199 inst.instruction |= cond << 22;
10200 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10205 inst.instruction = THUMB_OP16(opcode);
10206 if (cond == COND_ALWAYS)
10207 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10210 inst.instruction |= cond << 8;
10211 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10213 /* Allow section relaxation. */
10214 if (unified_syntax && inst.size_req != 2)
10215 inst.relax = opcode;
10217 inst.reloc.type = reloc;
10218 inst.reloc.pc_rel = 1;
10221 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10222 between the two is the maximum immediate allowed - which is passed in
10225 do_t_bkpt_hlt1 (int range)
10227 constraint (inst.cond != COND_ALWAYS,
10228 _("instruction is always unconditional"));
10229 if (inst.operands[0].present)
10231 constraint (inst.operands[0].imm > range,
10232 _("immediate value out of range"));
10233 inst.instruction |= inst.operands[0].imm;
10236 set_it_insn_type (NEUTRAL_IT_INSN);
10242 do_t_bkpt_hlt1 (63);
10248 do_t_bkpt_hlt1 (255);
10252 do_t_branch23 (void)
10254 set_it_insn_type_last ();
10255 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10257 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10258 this file. We used to simply ignore the PLT reloc type here --
10259 the branch encoding is now needed to deal with TLSCALL relocs.
10260 So if we see a PLT reloc now, put it back to how it used to be to
10261 keep the preexisting behaviour. */
10262 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10263 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10265 #if defined(OBJ_COFF)
10266 /* If the destination of the branch is a defined symbol which does not have
10267 the THUMB_FUNC attribute, then we must be calling a function which has
10268 the (interfacearm) attribute. We look for the Thumb entry point to that
10269 function and change the branch to refer to that function instead. */
10270 if ( inst.reloc.exp.X_op == O_symbol
10271 && inst.reloc.exp.X_add_symbol != NULL
10272 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10273 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10274 inst.reloc.exp.X_add_symbol =
10275 find_real_start (inst.reloc.exp.X_add_symbol);
10282 set_it_insn_type_last ();
10283 inst.instruction |= inst.operands[0].reg << 3;
10284 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10285 should cause the alignment to be checked once it is known. This is
10286 because BX PC only works if the instruction is word aligned. */
10294 set_it_insn_type_last ();
10295 Rm = inst.operands[0].reg;
10296 reject_bad_reg (Rm);
10297 inst.instruction |= Rm << 16;
10306 Rd = inst.operands[0].reg;
10307 Rm = inst.operands[1].reg;
10309 reject_bad_reg (Rd);
10310 reject_bad_reg (Rm);
10312 inst.instruction |= Rd << 8;
10313 inst.instruction |= Rm << 16;
10314 inst.instruction |= Rm;
10320 set_it_insn_type (OUTSIDE_IT_INSN);
10321 inst.instruction |= inst.operands[0].imm;
10327 set_it_insn_type (OUTSIDE_IT_INSN);
10329 && (inst.operands[1].present || inst.size_req == 4)
10330 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10332 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10333 inst.instruction = 0xf3af8000;
10334 inst.instruction |= imod << 9;
10335 inst.instruction |= inst.operands[0].imm << 5;
10336 if (inst.operands[1].present)
10337 inst.instruction |= 0x100 | inst.operands[1].imm;
10341 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10342 && (inst.operands[0].imm & 4),
10343 _("selected processor does not support 'A' form "
10344 "of this instruction"));
10345 constraint (inst.operands[1].present || inst.size_req == 4,
10346 _("Thumb does not support the 2-argument "
10347 "form of this instruction"));
10348 inst.instruction |= inst.operands[0].imm;
10352 /* THUMB CPY instruction (argument parse). */
10357 if (inst.size_req == 4)
10359 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10360 inst.instruction |= inst.operands[0].reg << 8;
10361 inst.instruction |= inst.operands[1].reg;
10365 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10366 inst.instruction |= (inst.operands[0].reg & 0x7);
10367 inst.instruction |= inst.operands[1].reg << 3;
10374 set_it_insn_type (OUTSIDE_IT_INSN);
10375 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10376 inst.instruction |= inst.operands[0].reg;
10377 inst.reloc.pc_rel = 1;
10378 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10384 inst.instruction |= inst.operands[0].imm;
10390 unsigned Rd, Rn, Rm;
10392 Rd = inst.operands[0].reg;
10393 Rn = (inst.operands[1].present
10394 ? inst.operands[1].reg : Rd);
10395 Rm = inst.operands[2].reg;
10397 reject_bad_reg (Rd);
10398 reject_bad_reg (Rn);
10399 reject_bad_reg (Rm);
10401 inst.instruction |= Rd << 8;
10402 inst.instruction |= Rn << 16;
10403 inst.instruction |= Rm;
10409 if (unified_syntax && inst.size_req == 4)
10410 inst.instruction = THUMB_OP32 (inst.instruction);
10412 inst.instruction = THUMB_OP16 (inst.instruction);
10418 unsigned int cond = inst.operands[0].imm;
10420 set_it_insn_type (IT_INSN);
10421 now_it.mask = (inst.instruction & 0xf) | 0x10;
10423 now_it.warn_deprecated = FALSE;
10425 /* If the condition is a negative condition, invert the mask. */
10426 if ((cond & 0x1) == 0x0)
10428 unsigned int mask = inst.instruction & 0x000f;
10430 if ((mask & 0x7) == 0)
10432 /* No conversion needed. */
10433 now_it.block_length = 1;
10435 else if ((mask & 0x3) == 0)
10438 now_it.block_length = 2;
10440 else if ((mask & 0x1) == 0)
10443 now_it.block_length = 3;
10448 now_it.block_length = 4;
10451 inst.instruction &= 0xfff0;
10452 inst.instruction |= mask;
10455 inst.instruction |= cond << 4;
10458 /* Helper function used for both push/pop and ldm/stm. */
10460 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10464 load = (inst.instruction & (1 << 20)) != 0;
10466 if (mask & (1 << 13))
10467 inst.error = _("SP not allowed in register list");
10469 if ((mask & (1 << base)) != 0
10471 inst.error = _("having the base register in the register list when "
10472 "using write back is UNPREDICTABLE");
10476 if (mask & (1 << 15))
10478 if (mask & (1 << 14))
10479 inst.error = _("LR and PC should not both be in register list");
10481 set_it_insn_type_last ();
10486 if (mask & (1 << 15))
10487 inst.error = _("PC not allowed in register list");
10490 if ((mask & (mask - 1)) == 0)
10492 /* Single register transfers implemented as str/ldr. */
10495 if (inst.instruction & (1 << 23))
10496 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10498 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10502 if (inst.instruction & (1 << 23))
10503 inst.instruction = 0x00800000; /* ia -> [base] */
10505 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10508 inst.instruction |= 0xf8400000;
10510 inst.instruction |= 0x00100000;
10512 mask = ffs (mask) - 1;
10515 else if (writeback)
10516 inst.instruction |= WRITE_BACK;
10518 inst.instruction |= mask;
10519 inst.instruction |= base << 16;
10525 /* This really doesn't seem worth it. */
10526 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10527 _("expression too complex"));
10528 constraint (inst.operands[1].writeback,
10529 _("Thumb load/store multiple does not support {reglist}^"));
10531 if (unified_syntax)
10533 bfd_boolean narrow;
10537 /* See if we can use a 16-bit instruction. */
10538 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10539 && inst.size_req != 4
10540 && !(inst.operands[1].imm & ~0xff))
10542 mask = 1 << inst.operands[0].reg;
10544 if (inst.operands[0].reg <= 7)
10546 if (inst.instruction == T_MNEM_stmia
10547 ? inst.operands[0].writeback
10548 : (inst.operands[0].writeback
10549 == !(inst.operands[1].imm & mask)))
10551 if (inst.instruction == T_MNEM_stmia
10552 && (inst.operands[1].imm & mask)
10553 && (inst.operands[1].imm & (mask - 1)))
10554 as_warn (_("value stored for r%d is UNKNOWN"),
10555 inst.operands[0].reg);
10557 inst.instruction = THUMB_OP16 (inst.instruction);
10558 inst.instruction |= inst.operands[0].reg << 8;
10559 inst.instruction |= inst.operands[1].imm;
10562 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10564 /* This means 1 register in reg list one of 3 situations:
10565 1. Instruction is stmia, but without writeback.
10566 2. lmdia without writeback, but with Rn not in
10568 3. ldmia with writeback, but with Rn in reglist.
10569 Case 3 is UNPREDICTABLE behaviour, so we handle
10570 case 1 and 2 which can be converted into a 16-bit
10571 str or ldr. The SP cases are handled below. */
10572 unsigned long opcode;
10573 /* First, record an error for Case 3. */
10574 if (inst.operands[1].imm & mask
10575 && inst.operands[0].writeback)
10577 _("having the base register in the register list when "
10578 "using write back is UNPREDICTABLE");
10580 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10582 inst.instruction = THUMB_OP16 (opcode);
10583 inst.instruction |= inst.operands[0].reg << 3;
10584 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10588 else if (inst.operands[0] .reg == REG_SP)
10590 if (inst.operands[0].writeback)
10593 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10594 ? T_MNEM_push : T_MNEM_pop);
10595 inst.instruction |= inst.operands[1].imm;
10598 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10601 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10602 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10603 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10611 if (inst.instruction < 0xffff)
10612 inst.instruction = THUMB_OP32 (inst.instruction);
10614 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10615 inst.operands[0].writeback);
10620 constraint (inst.operands[0].reg > 7
10621 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10622 constraint (inst.instruction != T_MNEM_ldmia
10623 && inst.instruction != T_MNEM_stmia,
10624 _("Thumb-2 instruction only valid in unified syntax"));
10625 if (inst.instruction == T_MNEM_stmia)
10627 if (!inst.operands[0].writeback)
10628 as_warn (_("this instruction will write back the base register"));
10629 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10630 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10631 as_warn (_("value stored for r%d is UNKNOWN"),
10632 inst.operands[0].reg);
10636 if (!inst.operands[0].writeback
10637 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10638 as_warn (_("this instruction will write back the base register"));
10639 else if (inst.operands[0].writeback
10640 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10641 as_warn (_("this instruction will not write back the base register"));
10644 inst.instruction = THUMB_OP16 (inst.instruction);
10645 inst.instruction |= inst.operands[0].reg << 8;
10646 inst.instruction |= inst.operands[1].imm;
10653 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10654 || inst.operands[1].postind || inst.operands[1].writeback
10655 || inst.operands[1].immisreg || inst.operands[1].shifted
10656 || inst.operands[1].negative,
10659 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10661 inst.instruction |= inst.operands[0].reg << 12;
10662 inst.instruction |= inst.operands[1].reg << 16;
10663 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10669 if (!inst.operands[1].present)
10671 constraint (inst.operands[0].reg == REG_LR,
10672 _("r14 not allowed as first register "
10673 "when second register is omitted"));
10674 inst.operands[1].reg = inst.operands[0].reg + 1;
10676 constraint (inst.operands[0].reg == inst.operands[1].reg,
10679 inst.instruction |= inst.operands[0].reg << 12;
10680 inst.instruction |= inst.operands[1].reg << 8;
10681 inst.instruction |= inst.operands[2].reg << 16;
10687 unsigned long opcode;
10690 if (inst.operands[0].isreg
10691 && !inst.operands[0].preind
10692 && inst.operands[0].reg == REG_PC)
10693 set_it_insn_type_last ();
10695 opcode = inst.instruction;
10696 if (unified_syntax)
10698 if (!inst.operands[1].isreg)
10700 if (opcode <= 0xffff)
10701 inst.instruction = THUMB_OP32 (opcode);
10702 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10705 if (inst.operands[1].isreg
10706 && !inst.operands[1].writeback
10707 && !inst.operands[1].shifted && !inst.operands[1].postind
10708 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10709 && opcode <= 0xffff
10710 && inst.size_req != 4)
10712 /* Insn may have a 16-bit form. */
10713 Rn = inst.operands[1].reg;
10714 if (inst.operands[1].immisreg)
10716 inst.instruction = THUMB_OP16 (opcode);
10718 if (Rn <= 7 && inst.operands[1].imm <= 7)
10720 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10721 reject_bad_reg (inst.operands[1].imm);
10723 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10724 && opcode != T_MNEM_ldrsb)
10725 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10726 || (Rn == REG_SP && opcode == T_MNEM_str))
10733 if (inst.reloc.pc_rel)
10734 opcode = T_MNEM_ldr_pc2;
10736 opcode = T_MNEM_ldr_pc;
10740 if (opcode == T_MNEM_ldr)
10741 opcode = T_MNEM_ldr_sp;
10743 opcode = T_MNEM_str_sp;
10745 inst.instruction = inst.operands[0].reg << 8;
10749 inst.instruction = inst.operands[0].reg;
10750 inst.instruction |= inst.operands[1].reg << 3;
10752 inst.instruction |= THUMB_OP16 (opcode);
10753 if (inst.size_req == 2)
10754 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10756 inst.relax = opcode;
10760 /* Definitely a 32-bit variant. */
10762 /* Warning for Erratum 752419. */
10763 if (opcode == T_MNEM_ldr
10764 && inst.operands[0].reg == REG_SP
10765 && inst.operands[1].writeback == 1
10766 && !inst.operands[1].immisreg)
10768 if (no_cpu_selected ()
10769 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10770 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10771 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10772 as_warn (_("This instruction may be unpredictable "
10773 "if executed on M-profile cores "
10774 "with interrupts enabled."));
10777 /* Do some validations regarding addressing modes. */
10778 if (inst.operands[1].immisreg)
10779 reject_bad_reg (inst.operands[1].imm);
10781 constraint (inst.operands[1].writeback == 1
10782 && inst.operands[0].reg == inst.operands[1].reg,
10785 inst.instruction = THUMB_OP32 (opcode);
10786 inst.instruction |= inst.operands[0].reg << 12;
10787 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10788 check_ldr_r15_aligned ();
10792 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10794 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10796 /* Only [Rn,Rm] is acceptable. */
10797 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10798 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10799 || inst.operands[1].postind || inst.operands[1].shifted
10800 || inst.operands[1].negative,
10801 _("Thumb does not support this addressing mode"));
10802 inst.instruction = THUMB_OP16 (inst.instruction);
10806 inst.instruction = THUMB_OP16 (inst.instruction);
10807 if (!inst.operands[1].isreg)
10808 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10811 constraint (!inst.operands[1].preind
10812 || inst.operands[1].shifted
10813 || inst.operands[1].writeback,
10814 _("Thumb does not support this addressing mode"));
10815 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10817 constraint (inst.instruction & 0x0600,
10818 _("byte or halfword not valid for base register"));
10819 constraint (inst.operands[1].reg == REG_PC
10820 && !(inst.instruction & THUMB_LOAD_BIT),
10821 _("r15 based store not allowed"));
10822 constraint (inst.operands[1].immisreg,
10823 _("invalid base register for register offset"));
10825 if (inst.operands[1].reg == REG_PC)
10826 inst.instruction = T_OPCODE_LDR_PC;
10827 else if (inst.instruction & THUMB_LOAD_BIT)
10828 inst.instruction = T_OPCODE_LDR_SP;
10830 inst.instruction = T_OPCODE_STR_SP;
10832 inst.instruction |= inst.operands[0].reg << 8;
10833 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10837 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10838 if (!inst.operands[1].immisreg)
10840 /* Immediate offset. */
10841 inst.instruction |= inst.operands[0].reg;
10842 inst.instruction |= inst.operands[1].reg << 3;
10843 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10847 /* Register offset. */
10848 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10849 constraint (inst.operands[1].negative,
10850 _("Thumb does not support this addressing mode"));
10853 switch (inst.instruction)
10855 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10856 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10857 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10858 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10859 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10860 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10861 case 0x5600 /* ldrsb */:
10862 case 0x5e00 /* ldrsh */: break;
10866 inst.instruction |= inst.operands[0].reg;
10867 inst.instruction |= inst.operands[1].reg << 3;
10868 inst.instruction |= inst.operands[1].imm << 6;
10874 if (!inst.operands[1].present)
10876 inst.operands[1].reg = inst.operands[0].reg + 1;
10877 constraint (inst.operands[0].reg == REG_LR,
10878 _("r14 not allowed here"));
10879 constraint (inst.operands[0].reg == REG_R12,
10880 _("r12 not allowed here"));
10883 if (inst.operands[2].writeback
10884 && (inst.operands[0].reg == inst.operands[2].reg
10885 || inst.operands[1].reg == inst.operands[2].reg))
10886 as_warn (_("base register written back, and overlaps "
10887 "one of transfer registers"));
10889 inst.instruction |= inst.operands[0].reg << 12;
10890 inst.instruction |= inst.operands[1].reg << 8;
10891 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10897 inst.instruction |= inst.operands[0].reg << 12;
10898 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10904 unsigned Rd, Rn, Rm, Ra;
10906 Rd = inst.operands[0].reg;
10907 Rn = inst.operands[1].reg;
10908 Rm = inst.operands[2].reg;
10909 Ra = inst.operands[3].reg;
10911 reject_bad_reg (Rd);
10912 reject_bad_reg (Rn);
10913 reject_bad_reg (Rm);
10914 reject_bad_reg (Ra);
10916 inst.instruction |= Rd << 8;
10917 inst.instruction |= Rn << 16;
10918 inst.instruction |= Rm;
10919 inst.instruction |= Ra << 12;
10925 unsigned RdLo, RdHi, Rn, Rm;
10927 RdLo = inst.operands[0].reg;
10928 RdHi = inst.operands[1].reg;
10929 Rn = inst.operands[2].reg;
10930 Rm = inst.operands[3].reg;
10932 reject_bad_reg (RdLo);
10933 reject_bad_reg (RdHi);
10934 reject_bad_reg (Rn);
10935 reject_bad_reg (Rm);
10937 inst.instruction |= RdLo << 12;
10938 inst.instruction |= RdHi << 8;
10939 inst.instruction |= Rn << 16;
10940 inst.instruction |= Rm;
10944 do_t_mov_cmp (void)
10948 Rn = inst.operands[0].reg;
10949 Rm = inst.operands[1].reg;
10952 set_it_insn_type_last ();
10954 if (unified_syntax)
10956 int r0off = (inst.instruction == T_MNEM_mov
10957 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10958 unsigned long opcode;
10959 bfd_boolean narrow;
10960 bfd_boolean low_regs;
10962 low_regs = (Rn <= 7 && Rm <= 7);
10963 opcode = inst.instruction;
10964 if (in_it_block ())
10965 narrow = opcode != T_MNEM_movs;
10967 narrow = opcode != T_MNEM_movs || low_regs;
10968 if (inst.size_req == 4
10969 || inst.operands[1].shifted)
10972 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10973 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10974 && !inst.operands[1].shifted
10978 inst.instruction = T2_SUBS_PC_LR;
10982 if (opcode == T_MNEM_cmp)
10984 constraint (Rn == REG_PC, BAD_PC);
10987 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10989 warn_deprecated_sp (Rm);
10990 /* R15 was documented as a valid choice for Rm in ARMv6,
10991 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10992 tools reject R15, so we do too. */
10993 constraint (Rm == REG_PC, BAD_PC);
10996 reject_bad_reg (Rm);
10998 else if (opcode == T_MNEM_mov
10999 || opcode == T_MNEM_movs)
11001 if (inst.operands[1].isreg)
11003 if (opcode == T_MNEM_movs)
11005 reject_bad_reg (Rn);
11006 reject_bad_reg (Rm);
11010 /* This is mov.n. */
11011 if ((Rn == REG_SP || Rn == REG_PC)
11012 && (Rm == REG_SP || Rm == REG_PC))
11014 as_warn (_("Use of r%u as a source register is "
11015 "deprecated when r%u is the destination "
11016 "register."), Rm, Rn);
11021 /* This is mov.w. */
11022 constraint (Rn == REG_PC, BAD_PC);
11023 constraint (Rm == REG_PC, BAD_PC);
11024 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11028 reject_bad_reg (Rn);
11031 if (!inst.operands[1].isreg)
11033 /* Immediate operand. */
11034 if (!in_it_block () && opcode == T_MNEM_mov)
11036 if (low_regs && narrow)
11038 inst.instruction = THUMB_OP16 (opcode);
11039 inst.instruction |= Rn << 8;
11040 if (inst.size_req == 2)
11041 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11043 inst.relax = opcode;
11047 inst.instruction = THUMB_OP32 (inst.instruction);
11048 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11049 inst.instruction |= Rn << r0off;
11050 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11053 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11054 && (inst.instruction == T_MNEM_mov
11055 || inst.instruction == T_MNEM_movs))
11057 /* Register shifts are encoded as separate shift instructions. */
11058 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11060 if (in_it_block ())
11065 if (inst.size_req == 4)
11068 if (!low_regs || inst.operands[1].imm > 7)
11074 switch (inst.operands[1].shift_kind)
11077 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11080 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11083 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11086 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11092 inst.instruction = opcode;
11095 inst.instruction |= Rn;
11096 inst.instruction |= inst.operands[1].imm << 3;
11101 inst.instruction |= CONDS_BIT;
11103 inst.instruction |= Rn << 8;
11104 inst.instruction |= Rm << 16;
11105 inst.instruction |= inst.operands[1].imm;
11110 /* Some mov with immediate shift have narrow variants.
11111 Register shifts are handled above. */
11112 if (low_regs && inst.operands[1].shifted
11113 && (inst.instruction == T_MNEM_mov
11114 || inst.instruction == T_MNEM_movs))
11116 if (in_it_block ())
11117 narrow = (inst.instruction == T_MNEM_mov);
11119 narrow = (inst.instruction == T_MNEM_movs);
11124 switch (inst.operands[1].shift_kind)
11126 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11127 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11128 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11129 default: narrow = FALSE; break;
11135 inst.instruction |= Rn;
11136 inst.instruction |= Rm << 3;
11137 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11141 inst.instruction = THUMB_OP32 (inst.instruction);
11142 inst.instruction |= Rn << r0off;
11143 encode_thumb32_shifted_operand (1);
11147 switch (inst.instruction)
11150 /* In v4t or v5t a move of two lowregs produces unpredictable
11151 results. Don't allow this. */
11154 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11155 "MOV Rd, Rs with two low registers is not "
11156 "permitted on this architecture");
11157 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11161 inst.instruction = T_OPCODE_MOV_HR;
11162 inst.instruction |= (Rn & 0x8) << 4;
11163 inst.instruction |= (Rn & 0x7);
11164 inst.instruction |= Rm << 3;
11168 /* We know we have low registers at this point.
11169 Generate LSLS Rd, Rs, #0. */
11170 inst.instruction = T_OPCODE_LSL_I;
11171 inst.instruction |= Rn;
11172 inst.instruction |= Rm << 3;
11178 inst.instruction = T_OPCODE_CMP_LR;
11179 inst.instruction |= Rn;
11180 inst.instruction |= Rm << 3;
11184 inst.instruction = T_OPCODE_CMP_HR;
11185 inst.instruction |= (Rn & 0x8) << 4;
11186 inst.instruction |= (Rn & 0x7);
11187 inst.instruction |= Rm << 3;
11194 inst.instruction = THUMB_OP16 (inst.instruction);
11196 /* PR 10443: Do not silently ignore shifted operands. */
11197 constraint (inst.operands[1].shifted,
11198 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11200 if (inst.operands[1].isreg)
11202 if (Rn < 8 && Rm < 8)
11204 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11205 since a MOV instruction produces unpredictable results. */
11206 if (inst.instruction == T_OPCODE_MOV_I8)
11207 inst.instruction = T_OPCODE_ADD_I3;
11209 inst.instruction = T_OPCODE_CMP_LR;
11211 inst.instruction |= Rn;
11212 inst.instruction |= Rm << 3;
11216 if (inst.instruction == T_OPCODE_MOV_I8)
11217 inst.instruction = T_OPCODE_MOV_HR;
11219 inst.instruction = T_OPCODE_CMP_HR;
11225 constraint (Rn > 7,
11226 _("only lo regs allowed with immediate"));
11227 inst.instruction |= Rn << 8;
11228 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11239 top = (inst.instruction & 0x00800000) != 0;
11240 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11242 constraint (top, _(":lower16: not allowed this instruction"));
11243 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11245 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11247 constraint (!top, _(":upper16: not allowed this instruction"));
11248 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11251 Rd = inst.operands[0].reg;
11252 reject_bad_reg (Rd);
11254 inst.instruction |= Rd << 8;
11255 if (inst.reloc.type == BFD_RELOC_UNUSED)
11257 imm = inst.reloc.exp.X_add_number;
11258 inst.instruction |= (imm & 0xf000) << 4;
11259 inst.instruction |= (imm & 0x0800) << 15;
11260 inst.instruction |= (imm & 0x0700) << 4;
11261 inst.instruction |= (imm & 0x00ff);
11266 do_t_mvn_tst (void)
11270 Rn = inst.operands[0].reg;
11271 Rm = inst.operands[1].reg;
11273 if (inst.instruction == T_MNEM_cmp
11274 || inst.instruction == T_MNEM_cmn)
11275 constraint (Rn == REG_PC, BAD_PC);
11277 reject_bad_reg (Rn);
11278 reject_bad_reg (Rm);
11280 if (unified_syntax)
11282 int r0off = (inst.instruction == T_MNEM_mvn
11283 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11284 bfd_boolean narrow;
11286 if (inst.size_req == 4
11287 || inst.instruction > 0xffff
11288 || inst.operands[1].shifted
11289 || Rn > 7 || Rm > 7)
11291 else if (inst.instruction == T_MNEM_cmn)
11293 else if (THUMB_SETS_FLAGS (inst.instruction))
11294 narrow = !in_it_block ();
11296 narrow = in_it_block ();
11298 if (!inst.operands[1].isreg)
11300 /* For an immediate, we always generate a 32-bit opcode;
11301 section relaxation will shrink it later if possible. */
11302 if (inst.instruction < 0xffff)
11303 inst.instruction = THUMB_OP32 (inst.instruction);
11304 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11305 inst.instruction |= Rn << r0off;
11306 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11310 /* See if we can do this with a 16-bit instruction. */
11313 inst.instruction = THUMB_OP16 (inst.instruction);
11314 inst.instruction |= Rn;
11315 inst.instruction |= Rm << 3;
11319 constraint (inst.operands[1].shifted
11320 && inst.operands[1].immisreg,
11321 _("shift must be constant"));
11322 if (inst.instruction < 0xffff)
11323 inst.instruction = THUMB_OP32 (inst.instruction);
11324 inst.instruction |= Rn << r0off;
11325 encode_thumb32_shifted_operand (1);
11331 constraint (inst.instruction > 0xffff
11332 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11333 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11334 _("unshifted register required"));
11335 constraint (Rn > 7 || Rm > 7,
11338 inst.instruction = THUMB_OP16 (inst.instruction);
11339 inst.instruction |= Rn;
11340 inst.instruction |= Rm << 3;
11349 if (do_vfp_nsyn_mrs () == SUCCESS)
11352 Rd = inst.operands[0].reg;
11353 reject_bad_reg (Rd);
11354 inst.instruction |= Rd << 8;
11356 if (inst.operands[1].isreg)
11358 unsigned br = inst.operands[1].reg;
11359 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11360 as_bad (_("bad register for mrs"));
11362 inst.instruction |= br & (0xf << 16);
11363 inst.instruction |= (br & 0x300) >> 4;
11364 inst.instruction |= (br & SPSR_BIT) >> 2;
11368 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11370 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11372 /* PR gas/12698: The constraint is only applied for m_profile.
11373 If the user has specified -march=all, we want to ignore it as
11374 we are building for any CPU type, including non-m variants. */
11375 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11376 constraint ((flags != 0) && m_profile, _("selected processor does "
11377 "not support requested special purpose register"));
11380 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11382 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11383 _("'APSR', 'CPSR' or 'SPSR' expected"));
11385 inst.instruction |= (flags & SPSR_BIT) >> 2;
11386 inst.instruction |= inst.operands[1].imm & 0xff;
11387 inst.instruction |= 0xf0000;
11397 if (do_vfp_nsyn_msr () == SUCCESS)
11400 constraint (!inst.operands[1].isreg,
11401 _("Thumb encoding does not support an immediate here"));
11403 if (inst.operands[0].isreg)
11404 flags = (int)(inst.operands[0].reg);
11406 flags = inst.operands[0].imm;
11408 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11410 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11412 /* PR gas/12698: The constraint is only applied for m_profile.
11413 If the user has specified -march=all, we want to ignore it as
11414 we are building for any CPU type, including non-m variants. */
11415 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11416 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11417 && (bits & ~(PSR_s | PSR_f)) != 0)
11418 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11419 && bits != PSR_f)) && m_profile,
11420 _("selected processor does not support requested special "
11421 "purpose register"));
11424 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11425 "requested special purpose register"));
11427 Rn = inst.operands[1].reg;
11428 reject_bad_reg (Rn);
11430 inst.instruction |= (flags & SPSR_BIT) >> 2;
11431 inst.instruction |= (flags & 0xf0000) >> 8;
11432 inst.instruction |= (flags & 0x300) >> 4;
11433 inst.instruction |= (flags & 0xff);
11434 inst.instruction |= Rn << 16;
11440 bfd_boolean narrow;
11441 unsigned Rd, Rn, Rm;
11443 if (!inst.operands[2].present)
11444 inst.operands[2].reg = inst.operands[0].reg;
11446 Rd = inst.operands[0].reg;
11447 Rn = inst.operands[1].reg;
11448 Rm = inst.operands[2].reg;
11450 if (unified_syntax)
11452 if (inst.size_req == 4
11458 else if (inst.instruction == T_MNEM_muls)
11459 narrow = !in_it_block ();
11461 narrow = in_it_block ();
11465 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11466 constraint (Rn > 7 || Rm > 7,
11473 /* 16-bit MULS/Conditional MUL. */
11474 inst.instruction = THUMB_OP16 (inst.instruction);
11475 inst.instruction |= Rd;
11478 inst.instruction |= Rm << 3;
11480 inst.instruction |= Rn << 3;
11482 constraint (1, _("dest must overlap one source register"));
11486 constraint (inst.instruction != T_MNEM_mul,
11487 _("Thumb-2 MUL must not set flags"));
11489 inst.instruction = THUMB_OP32 (inst.instruction);
11490 inst.instruction |= Rd << 8;
11491 inst.instruction |= Rn << 16;
11492 inst.instruction |= Rm << 0;
11494 reject_bad_reg (Rd);
11495 reject_bad_reg (Rn);
11496 reject_bad_reg (Rm);
11503 unsigned RdLo, RdHi, Rn, Rm;
11505 RdLo = inst.operands[0].reg;
11506 RdHi = inst.operands[1].reg;
11507 Rn = inst.operands[2].reg;
11508 Rm = inst.operands[3].reg;
11510 reject_bad_reg (RdLo);
11511 reject_bad_reg (RdHi);
11512 reject_bad_reg (Rn);
11513 reject_bad_reg (Rm);
11515 inst.instruction |= RdLo << 12;
11516 inst.instruction |= RdHi << 8;
11517 inst.instruction |= Rn << 16;
11518 inst.instruction |= Rm;
11521 as_tsktsk (_("rdhi and rdlo must be different"));
11527 set_it_insn_type (NEUTRAL_IT_INSN);
11529 if (unified_syntax)
11531 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11533 inst.instruction = THUMB_OP32 (inst.instruction);
11534 inst.instruction |= inst.operands[0].imm;
11538 /* PR9722: Check for Thumb2 availability before
11539 generating a thumb2 nop instruction. */
11540 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11542 inst.instruction = THUMB_OP16 (inst.instruction);
11543 inst.instruction |= inst.operands[0].imm << 4;
11546 inst.instruction = 0x46c0;
11551 constraint (inst.operands[0].present,
11552 _("Thumb does not support NOP with hints"));
11553 inst.instruction = 0x46c0;
11560 if (unified_syntax)
11562 bfd_boolean narrow;
11564 if (THUMB_SETS_FLAGS (inst.instruction))
11565 narrow = !in_it_block ();
11567 narrow = in_it_block ();
11568 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11570 if (inst.size_req == 4)
11575 inst.instruction = THUMB_OP32 (inst.instruction);
11576 inst.instruction |= inst.operands[0].reg << 8;
11577 inst.instruction |= inst.operands[1].reg << 16;
11581 inst.instruction = THUMB_OP16 (inst.instruction);
11582 inst.instruction |= inst.operands[0].reg;
11583 inst.instruction |= inst.operands[1].reg << 3;
11588 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11590 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11592 inst.instruction = THUMB_OP16 (inst.instruction);
11593 inst.instruction |= inst.operands[0].reg;
11594 inst.instruction |= inst.operands[1].reg << 3;
11603 Rd = inst.operands[0].reg;
11604 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11606 reject_bad_reg (Rd);
11607 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11608 reject_bad_reg (Rn);
11610 inst.instruction |= Rd << 8;
11611 inst.instruction |= Rn << 16;
11613 if (!inst.operands[2].isreg)
11615 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11616 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11622 Rm = inst.operands[2].reg;
11623 reject_bad_reg (Rm);
11625 constraint (inst.operands[2].shifted
11626 && inst.operands[2].immisreg,
11627 _("shift must be constant"));
11628 encode_thumb32_shifted_operand (2);
11635 unsigned Rd, Rn, Rm;
11637 Rd = inst.operands[0].reg;
11638 Rn = inst.operands[1].reg;
11639 Rm = inst.operands[2].reg;
11641 reject_bad_reg (Rd);
11642 reject_bad_reg (Rn);
11643 reject_bad_reg (Rm);
11645 inst.instruction |= Rd << 8;
11646 inst.instruction |= Rn << 16;
11647 inst.instruction |= Rm;
11648 if (inst.operands[3].present)
11650 unsigned int val = inst.reloc.exp.X_add_number;
11651 constraint (inst.reloc.exp.X_op != O_constant,
11652 _("expression too complex"));
11653 inst.instruction |= (val & 0x1c) << 10;
11654 inst.instruction |= (val & 0x03) << 6;
11661 if (!inst.operands[3].present)
11665 inst.instruction &= ~0x00000020;
11667 /* PR 10168. Swap the Rm and Rn registers. */
11668 Rtmp = inst.operands[1].reg;
11669 inst.operands[1].reg = inst.operands[2].reg;
11670 inst.operands[2].reg = Rtmp;
11678 if (inst.operands[0].immisreg)
11679 reject_bad_reg (inst.operands[0].imm);
11681 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11685 do_t_push_pop (void)
11689 constraint (inst.operands[0].writeback,
11690 _("push/pop do not support {reglist}^"));
11691 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11692 _("expression too complex"));
11694 mask = inst.operands[0].imm;
11695 if ((mask & ~0xff) == 0)
11696 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11697 else if ((inst.instruction == T_MNEM_push
11698 && (mask & ~0xff) == 1 << REG_LR)
11699 || (inst.instruction == T_MNEM_pop
11700 && (mask & ~0xff) == 1 << REG_PC))
11702 inst.instruction = THUMB_OP16 (inst.instruction);
11703 inst.instruction |= THUMB_PP_PC_LR;
11704 inst.instruction |= mask & 0xff;
11706 else if (unified_syntax)
11708 inst.instruction = THUMB_OP32 (inst.instruction);
11709 encode_thumb2_ldmstm (13, mask, TRUE);
11713 inst.error = _("invalid register list to push/pop instruction");
11723 Rd = inst.operands[0].reg;
11724 Rm = inst.operands[1].reg;
11726 reject_bad_reg (Rd);
11727 reject_bad_reg (Rm);
11729 inst.instruction |= Rd << 8;
11730 inst.instruction |= Rm << 16;
11731 inst.instruction |= Rm;
11739 Rd = inst.operands[0].reg;
11740 Rm = inst.operands[1].reg;
11742 reject_bad_reg (Rd);
11743 reject_bad_reg (Rm);
11745 if (Rd <= 7 && Rm <= 7
11746 && inst.size_req != 4)
11748 inst.instruction = THUMB_OP16 (inst.instruction);
11749 inst.instruction |= Rd;
11750 inst.instruction |= Rm << 3;
11752 else if (unified_syntax)
11754 inst.instruction = THUMB_OP32 (inst.instruction);
11755 inst.instruction |= Rd << 8;
11756 inst.instruction |= Rm << 16;
11757 inst.instruction |= Rm;
11760 inst.error = BAD_HIREG;
11768 Rd = inst.operands[0].reg;
11769 Rm = inst.operands[1].reg;
11771 reject_bad_reg (Rd);
11772 reject_bad_reg (Rm);
11774 inst.instruction |= Rd << 8;
11775 inst.instruction |= Rm;
11783 Rd = inst.operands[0].reg;
11784 Rs = (inst.operands[1].present
11785 ? inst.operands[1].reg /* Rd, Rs, foo */
11786 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11788 reject_bad_reg (Rd);
11789 reject_bad_reg (Rs);
11790 if (inst.operands[2].isreg)
11791 reject_bad_reg (inst.operands[2].reg);
11793 inst.instruction |= Rd << 8;
11794 inst.instruction |= Rs << 16;
11795 if (!inst.operands[2].isreg)
11797 bfd_boolean narrow;
11799 if ((inst.instruction & 0x00100000) != 0)
11800 narrow = !in_it_block ();
11802 narrow = in_it_block ();
11804 if (Rd > 7 || Rs > 7)
11807 if (inst.size_req == 4 || !unified_syntax)
11810 if (inst.reloc.exp.X_op != O_constant
11811 || inst.reloc.exp.X_add_number != 0)
11814 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11815 relaxation, but it doesn't seem worth the hassle. */
11818 inst.reloc.type = BFD_RELOC_UNUSED;
11819 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11820 inst.instruction |= Rs << 3;
11821 inst.instruction |= Rd;
11825 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11826 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11830 encode_thumb32_shifted_operand (2);
11836 if (warn_on_deprecated
11837 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11838 as_warn (_("setend use is deprecated for ARMv8"));
11840 set_it_insn_type (OUTSIDE_IT_INSN);
11841 if (inst.operands[0].imm)
11842 inst.instruction |= 0x8;
11848 if (!inst.operands[1].present)
11849 inst.operands[1].reg = inst.operands[0].reg;
11851 if (unified_syntax)
11853 bfd_boolean narrow;
11856 switch (inst.instruction)
11859 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11861 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11863 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11865 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11869 if (THUMB_SETS_FLAGS (inst.instruction))
11870 narrow = !in_it_block ();
11872 narrow = in_it_block ();
11873 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11875 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11877 if (inst.operands[2].isreg
11878 && (inst.operands[1].reg != inst.operands[0].reg
11879 || inst.operands[2].reg > 7))
11881 if (inst.size_req == 4)
11884 reject_bad_reg (inst.operands[0].reg);
11885 reject_bad_reg (inst.operands[1].reg);
11889 if (inst.operands[2].isreg)
11891 reject_bad_reg (inst.operands[2].reg);
11892 inst.instruction = THUMB_OP32 (inst.instruction);
11893 inst.instruction |= inst.operands[0].reg << 8;
11894 inst.instruction |= inst.operands[1].reg << 16;
11895 inst.instruction |= inst.operands[2].reg;
11897 /* PR 12854: Error on extraneous shifts. */
11898 constraint (inst.operands[2].shifted,
11899 _("extraneous shift as part of operand to shift insn"));
11903 inst.operands[1].shifted = 1;
11904 inst.operands[1].shift_kind = shift_kind;
11905 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11906 ? T_MNEM_movs : T_MNEM_mov);
11907 inst.instruction |= inst.operands[0].reg << 8;
11908 encode_thumb32_shifted_operand (1);
11909 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11910 inst.reloc.type = BFD_RELOC_UNUSED;
11915 if (inst.operands[2].isreg)
11917 switch (shift_kind)
11919 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11920 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11921 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11922 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11926 inst.instruction |= inst.operands[0].reg;
11927 inst.instruction |= inst.operands[2].reg << 3;
11929 /* PR 12854: Error on extraneous shifts. */
11930 constraint (inst.operands[2].shifted,
11931 _("extraneous shift as part of operand to shift insn"));
11935 switch (shift_kind)
11937 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11938 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11939 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11942 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11943 inst.instruction |= inst.operands[0].reg;
11944 inst.instruction |= inst.operands[1].reg << 3;
11950 constraint (inst.operands[0].reg > 7
11951 || inst.operands[1].reg > 7, BAD_HIREG);
11952 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11954 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11956 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11957 constraint (inst.operands[0].reg != inst.operands[1].reg,
11958 _("source1 and dest must be same register"));
11960 switch (inst.instruction)
11962 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11963 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11964 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11965 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11969 inst.instruction |= inst.operands[0].reg;
11970 inst.instruction |= inst.operands[2].reg << 3;
11972 /* PR 12854: Error on extraneous shifts. */
11973 constraint (inst.operands[2].shifted,
11974 _("extraneous shift as part of operand to shift insn"));
11978 switch (inst.instruction)
11980 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11981 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11982 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11983 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11986 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11987 inst.instruction |= inst.operands[0].reg;
11988 inst.instruction |= inst.operands[1].reg << 3;
11996 unsigned Rd, Rn, Rm;
11998 Rd = inst.operands[0].reg;
11999 Rn = inst.operands[1].reg;
12000 Rm = inst.operands[2].reg;
12002 reject_bad_reg (Rd);
12003 reject_bad_reg (Rn);
12004 reject_bad_reg (Rm);
12006 inst.instruction |= Rd << 8;
12007 inst.instruction |= Rn << 16;
12008 inst.instruction |= Rm;
12014 unsigned Rd, Rn, Rm;
12016 Rd = inst.operands[0].reg;
12017 Rm = inst.operands[1].reg;
12018 Rn = inst.operands[2].reg;
12020 reject_bad_reg (Rd);
12021 reject_bad_reg (Rn);
12022 reject_bad_reg (Rm);
12024 inst.instruction |= Rd << 8;
12025 inst.instruction |= Rn << 16;
12026 inst.instruction |= Rm;
12032 unsigned int value = inst.reloc.exp.X_add_number;
12033 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12034 _("SMC is not permitted on this architecture"));
12035 constraint (inst.reloc.exp.X_op != O_constant,
12036 _("expression too complex"));
12037 inst.reloc.type = BFD_RELOC_UNUSED;
12038 inst.instruction |= (value & 0xf000) >> 12;
12039 inst.instruction |= (value & 0x0ff0);
12040 inst.instruction |= (value & 0x000f) << 16;
12046 unsigned int value = inst.reloc.exp.X_add_number;
12048 inst.reloc.type = BFD_RELOC_UNUSED;
12049 inst.instruction |= (value & 0x0fff);
12050 inst.instruction |= (value & 0xf000) << 4;
12054 do_t_ssat_usat (int bias)
12058 Rd = inst.operands[0].reg;
12059 Rn = inst.operands[2].reg;
12061 reject_bad_reg (Rd);
12062 reject_bad_reg (Rn);
12064 inst.instruction |= Rd << 8;
12065 inst.instruction |= inst.operands[1].imm - bias;
12066 inst.instruction |= Rn << 16;
12068 if (inst.operands[3].present)
12070 offsetT shift_amount = inst.reloc.exp.X_add_number;
12072 inst.reloc.type = BFD_RELOC_UNUSED;
12074 constraint (inst.reloc.exp.X_op != O_constant,
12075 _("expression too complex"));
12077 if (shift_amount != 0)
12079 constraint (shift_amount > 31,
12080 _("shift expression is too large"));
12082 if (inst.operands[3].shift_kind == SHIFT_ASR)
12083 inst.instruction |= 0x00200000; /* sh bit. */
12085 inst.instruction |= (shift_amount & 0x1c) << 10;
12086 inst.instruction |= (shift_amount & 0x03) << 6;
12094 do_t_ssat_usat (1);
12102 Rd = inst.operands[0].reg;
12103 Rn = inst.operands[2].reg;
12105 reject_bad_reg (Rd);
12106 reject_bad_reg (Rn);
12108 inst.instruction |= Rd << 8;
12109 inst.instruction |= inst.operands[1].imm - 1;
12110 inst.instruction |= Rn << 16;
12116 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12117 || inst.operands[2].postind || inst.operands[2].writeback
12118 || inst.operands[2].immisreg || inst.operands[2].shifted
12119 || inst.operands[2].negative,
12122 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12124 inst.instruction |= inst.operands[0].reg << 8;
12125 inst.instruction |= inst.operands[1].reg << 12;
12126 inst.instruction |= inst.operands[2].reg << 16;
12127 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12133 if (!inst.operands[2].present)
12134 inst.operands[2].reg = inst.operands[1].reg + 1;
12136 constraint (inst.operands[0].reg == inst.operands[1].reg
12137 || inst.operands[0].reg == inst.operands[2].reg
12138 || inst.operands[0].reg == inst.operands[3].reg,
12141 inst.instruction |= inst.operands[0].reg;
12142 inst.instruction |= inst.operands[1].reg << 12;
12143 inst.instruction |= inst.operands[2].reg << 8;
12144 inst.instruction |= inst.operands[3].reg << 16;
12150 unsigned Rd, Rn, Rm;
12152 Rd = inst.operands[0].reg;
12153 Rn = inst.operands[1].reg;
12154 Rm = inst.operands[2].reg;
12156 reject_bad_reg (Rd);
12157 reject_bad_reg (Rn);
12158 reject_bad_reg (Rm);
12160 inst.instruction |= Rd << 8;
12161 inst.instruction |= Rn << 16;
12162 inst.instruction |= Rm;
12163 inst.instruction |= inst.operands[3].imm << 4;
12171 Rd = inst.operands[0].reg;
12172 Rm = inst.operands[1].reg;
12174 reject_bad_reg (Rd);
12175 reject_bad_reg (Rm);
12177 if (inst.instruction <= 0xffff
12178 && inst.size_req != 4
12179 && Rd <= 7 && Rm <= 7
12180 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12182 inst.instruction = THUMB_OP16 (inst.instruction);
12183 inst.instruction |= Rd;
12184 inst.instruction |= Rm << 3;
12186 else if (unified_syntax)
12188 if (inst.instruction <= 0xffff)
12189 inst.instruction = THUMB_OP32 (inst.instruction);
12190 inst.instruction |= Rd << 8;
12191 inst.instruction |= Rm;
12192 inst.instruction |= inst.operands[2].imm << 4;
12196 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12197 _("Thumb encoding does not support rotation"));
12198 constraint (1, BAD_HIREG);
12205 /* We have to do the following check manually as ARM_EXT_OS only applies
12207 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12209 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12210 /* This only applies to the v6m howver, not later architectures. */
12211 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12212 as_bad (_("SVC is not permitted on this architecture"));
12213 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12216 inst.reloc.type = BFD_RELOC_ARM_SWI;
12225 half = (inst.instruction & 0x10) != 0;
12226 set_it_insn_type_last ();
12227 constraint (inst.operands[0].immisreg,
12228 _("instruction requires register index"));
12230 Rn = inst.operands[0].reg;
12231 Rm = inst.operands[0].imm;
12233 constraint (Rn == REG_SP, BAD_SP);
12234 reject_bad_reg (Rm);
12236 constraint (!half && inst.operands[0].shifted,
12237 _("instruction does not allow shifted index"));
12238 inst.instruction |= (Rn << 16) | Rm;
12244 do_t_ssat_usat (0);
12252 Rd = inst.operands[0].reg;
12253 Rn = inst.operands[2].reg;
12255 reject_bad_reg (Rd);
12256 reject_bad_reg (Rn);
12258 inst.instruction |= Rd << 8;
12259 inst.instruction |= inst.operands[1].imm;
12260 inst.instruction |= Rn << 16;
12263 /* Neon instruction encoder helpers. */
12265 /* Encodings for the different types for various Neon opcodes. */
12267 /* An "invalid" code for the following tables. */
12270 struct neon_tab_entry
12273 unsigned float_or_poly;
12274 unsigned scalar_or_imm;
12277 /* Map overloaded Neon opcodes to their respective encodings. */
12278 #define NEON_ENC_TAB \
12279 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12280 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12281 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12282 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12283 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12284 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12285 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12286 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12287 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12288 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12289 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12290 /* Register variants of the following two instructions are encoded as
12291 vcge / vcgt with the operands reversed. */ \
12292 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12293 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12294 X(vfma, N_INV, 0x0000c10, N_INV), \
12295 X(vfms, N_INV, 0x0200c10, N_INV), \
12296 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12297 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12298 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12299 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12300 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12301 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12302 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12303 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12304 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12305 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12306 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12307 X(vshl, 0x0000400, N_INV, 0x0800510), \
12308 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12309 X(vand, 0x0000110, N_INV, 0x0800030), \
12310 X(vbic, 0x0100110, N_INV, 0x0800030), \
12311 X(veor, 0x1000110, N_INV, N_INV), \
12312 X(vorn, 0x0300110, N_INV, 0x0800010), \
12313 X(vorr, 0x0200110, N_INV, 0x0800010), \
12314 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12315 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12316 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12317 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12318 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12319 X(vst1, 0x0000000, 0x0800000, N_INV), \
12320 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12321 X(vst2, 0x0000100, 0x0800100, N_INV), \
12322 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12323 X(vst3, 0x0000200, 0x0800200, N_INV), \
12324 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12325 X(vst4, 0x0000300, 0x0800300, N_INV), \
12326 X(vmovn, 0x1b20200, N_INV, N_INV), \
12327 X(vtrn, 0x1b20080, N_INV, N_INV), \
12328 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12329 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12330 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12331 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12332 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12333 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12334 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12335 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12336 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12337 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12338 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12339 X(vseleq, 0xe000a00, N_INV, N_INV), \
12340 X(vselvs, 0xe100a00, N_INV, N_INV), \
12341 X(vselge, 0xe200a00, N_INV, N_INV), \
12342 X(vselgt, 0xe300a00, N_INV, N_INV), \
12343 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12344 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12345 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12346 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12347 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12348 X(aes, 0x3b00300, N_INV, N_INV), \
12349 X(sha3op, 0x2000c00, N_INV, N_INV), \
12350 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12351 X(sha2op, 0x3ba0380, N_INV, N_INV)
12355 #define X(OPC,I,F,S) N_MNEM_##OPC
12360 static const struct neon_tab_entry neon_enc_tab[] =
12362 #define X(OPC,I,F,S) { (I), (F), (S) }
12367 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12368 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12369 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12370 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12371 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12372 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12373 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12374 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12375 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12376 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12377 #define NEON_ENC_SINGLE_(X) \
12378 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12379 #define NEON_ENC_DOUBLE_(X) \
12380 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12381 #define NEON_ENC_FPV8_(X) \
12382 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12384 #define NEON_ENCODE(type, inst) \
12387 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12388 inst.is_neon = 1; \
12392 #define check_neon_suffixes \
12395 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12397 as_bad (_("invalid neon suffix for non neon instruction")); \
12403 /* Define shapes for instruction operands. The following mnemonic characters
12404 are used in this table:
12406 F - VFP S<n> register
12407 D - Neon D<n> register
12408 Q - Neon Q<n> register
12412 L - D<n> register list
12414 This table is used to generate various data:
12415 - enumerations of the form NS_DDR to be used as arguments to
12417 - a table classifying shapes into single, double, quad, mixed.
12418 - a table used to drive neon_select_shape. */
12420 #define NEON_SHAPE_DEF \
12421 X(3, (D, D, D), DOUBLE), \
12422 X(3, (Q, Q, Q), QUAD), \
12423 X(3, (D, D, I), DOUBLE), \
12424 X(3, (Q, Q, I), QUAD), \
12425 X(3, (D, D, S), DOUBLE), \
12426 X(3, (Q, Q, S), QUAD), \
12427 X(2, (D, D), DOUBLE), \
12428 X(2, (Q, Q), QUAD), \
12429 X(2, (D, S), DOUBLE), \
12430 X(2, (Q, S), QUAD), \
12431 X(2, (D, R), DOUBLE), \
12432 X(2, (Q, R), QUAD), \
12433 X(2, (D, I), DOUBLE), \
12434 X(2, (Q, I), QUAD), \
12435 X(3, (D, L, D), DOUBLE), \
12436 X(2, (D, Q), MIXED), \
12437 X(2, (Q, D), MIXED), \
12438 X(3, (D, Q, I), MIXED), \
12439 X(3, (Q, D, I), MIXED), \
12440 X(3, (Q, D, D), MIXED), \
12441 X(3, (D, Q, Q), MIXED), \
12442 X(3, (Q, Q, D), MIXED), \
12443 X(3, (Q, D, S), MIXED), \
12444 X(3, (D, Q, S), MIXED), \
12445 X(4, (D, D, D, I), DOUBLE), \
12446 X(4, (Q, Q, Q, I), QUAD), \
12447 X(2, (F, F), SINGLE), \
12448 X(3, (F, F, F), SINGLE), \
12449 X(2, (F, I), SINGLE), \
12450 X(2, (F, D), MIXED), \
12451 X(2, (D, F), MIXED), \
12452 X(3, (F, F, I), MIXED), \
12453 X(4, (R, R, F, F), SINGLE), \
12454 X(4, (F, F, R, R), SINGLE), \
12455 X(3, (D, R, R), DOUBLE), \
12456 X(3, (R, R, D), DOUBLE), \
12457 X(2, (S, R), SINGLE), \
12458 X(2, (R, S), SINGLE), \
12459 X(2, (F, R), SINGLE), \
12460 X(2, (R, F), SINGLE)
12462 #define S2(A,B) NS_##A##B
12463 #define S3(A,B,C) NS_##A##B##C
12464 #define S4(A,B,C,D) NS_##A##B##C##D
12466 #define X(N, L, C) S##N L
12479 enum neon_shape_class
12487 #define X(N, L, C) SC_##C
12489 static enum neon_shape_class neon_shape_class[] =
12507 /* Register widths of above. */
12508 static unsigned neon_shape_el_size[] =
12519 struct neon_shape_info
12522 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12525 #define S2(A,B) { SE_##A, SE_##B }
12526 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12527 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12529 #define X(N, L, C) { N, S##N L }
12531 static struct neon_shape_info neon_shape_tab[] =
12541 /* Bit masks used in type checking given instructions.
12542 'N_EQK' means the type must be the same as (or based on in some way) the key
12543 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12544 set, various other bits can be set as well in order to modify the meaning of
12545 the type constraint. */
12547 enum neon_type_mask
12571 N_KEY = 0x1000000, /* Key element (main type specifier). */
12572 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12573 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12574 N_UNT = 0x8000000, /* Must be explicitly untyped. */
12575 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12576 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12577 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12578 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12579 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12580 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12581 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12583 N_MAX_NONSPECIAL = N_P64
12586 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12588 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12589 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12590 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12591 #define N_SUF_32 (N_SU_32 | N_F32)
12592 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12593 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12595 /* Pass this as the first type argument to neon_check_type to ignore types
12597 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12599 /* Select a "shape" for the current instruction (describing register types or
12600 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12601 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12602 function of operand parsing, so this function doesn't need to be called.
12603 Shapes should be listed in order of decreasing length. */
12605 static enum neon_shape
12606 neon_select_shape (enum neon_shape shape, ...)
12609 enum neon_shape first_shape = shape;
12611 /* Fix missing optional operands. FIXME: we don't know at this point how
12612 many arguments we should have, so this makes the assumption that we have
12613 > 1. This is true of all current Neon opcodes, I think, but may not be
12614 true in the future. */
12615 if (!inst.operands[1].present)
12616 inst.operands[1] = inst.operands[0];
12618 va_start (ap, shape);
12620 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12625 for (j = 0; j < neon_shape_tab[shape].els; j++)
12627 if (!inst.operands[j].present)
12633 switch (neon_shape_tab[shape].el[j])
12636 if (!(inst.operands[j].isreg
12637 && inst.operands[j].isvec
12638 && inst.operands[j].issingle
12639 && !inst.operands[j].isquad))
12644 if (!(inst.operands[j].isreg
12645 && inst.operands[j].isvec
12646 && !inst.operands[j].isquad
12647 && !inst.operands[j].issingle))
12652 if (!(inst.operands[j].isreg
12653 && !inst.operands[j].isvec))
12658 if (!(inst.operands[j].isreg
12659 && inst.operands[j].isvec
12660 && inst.operands[j].isquad
12661 && !inst.operands[j].issingle))
12666 if (!(!inst.operands[j].isreg
12667 && !inst.operands[j].isscalar))
12672 if (!(!inst.operands[j].isreg
12673 && inst.operands[j].isscalar))
12683 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12684 /* We've matched all the entries in the shape table, and we don't
12685 have any left over operands which have not been matched. */
12691 if (shape == NS_NULL && first_shape != NS_NULL)
12692 first_error (_("invalid instruction shape"));
12697 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12698 means the Q bit should be set). */
12701 neon_quad (enum neon_shape shape)
12703 return neon_shape_class[shape] == SC_QUAD;
12707 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12710 /* Allow modification to be made to types which are constrained to be
12711 based on the key element, based on bits set alongside N_EQK. */
12712 if ((typebits & N_EQK) != 0)
12714 if ((typebits & N_HLF) != 0)
12716 else if ((typebits & N_DBL) != 0)
12718 if ((typebits & N_SGN) != 0)
12719 *g_type = NT_signed;
12720 else if ((typebits & N_UNS) != 0)
12721 *g_type = NT_unsigned;
12722 else if ((typebits & N_INT) != 0)
12723 *g_type = NT_integer;
12724 else if ((typebits & N_FLT) != 0)
12725 *g_type = NT_float;
12726 else if ((typebits & N_SIZ) != 0)
12727 *g_type = NT_untyped;
12731 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12732 operand type, i.e. the single type specified in a Neon instruction when it
12733 is the only one given. */
12735 static struct neon_type_el
12736 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12738 struct neon_type_el dest = *key;
12740 gas_assert ((thisarg & N_EQK) != 0);
12742 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12747 /* Convert Neon type and size into compact bitmask representation. */
12749 static enum neon_type_mask
12750 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12757 case 8: return N_8;
12758 case 16: return N_16;
12759 case 32: return N_32;
12760 case 64: return N_64;
12768 case 8: return N_I8;
12769 case 16: return N_I16;
12770 case 32: return N_I32;
12771 case 64: return N_I64;
12779 case 16: return N_F16;
12780 case 32: return N_F32;
12781 case 64: return N_F64;
12789 case 8: return N_P8;
12790 case 16: return N_P16;
12791 case 64: return N_P64;
12799 case 8: return N_S8;
12800 case 16: return N_S16;
12801 case 32: return N_S32;
12802 case 64: return N_S64;
12810 case 8: return N_U8;
12811 case 16: return N_U16;
12812 case 32: return N_U32;
12813 case 64: return N_U64;
12824 /* Convert compact Neon bitmask type representation to a type and size. Only
12825 handles the case where a single bit is set in the mask. */
12828 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12829 enum neon_type_mask mask)
12831 if ((mask & N_EQK) != 0)
12834 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12836 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
12838 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12840 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
12845 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12847 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12848 *type = NT_unsigned;
12849 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12850 *type = NT_integer;
12851 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12852 *type = NT_untyped;
12853 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
12855 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
12863 /* Modify a bitmask of allowed types. This is only needed for type
12867 modify_types_allowed (unsigned allowed, unsigned mods)
12870 enum neon_el_type type;
12876 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12878 if (el_type_of_type_chk (&type, &size,
12879 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12881 neon_modify_type_size (mods, &type, &size);
12882 destmask |= type_chk_of_el_type (type, size);
12889 /* Check type and return type classification.
12890 The manual states (paraphrase): If one datatype is given, it indicates the
12892 - the second operand, if there is one
12893 - the operand, if there is no second operand
12894 - the result, if there are no operands.
12895 This isn't quite good enough though, so we use a concept of a "key" datatype
12896 which is set on a per-instruction basis, which is the one which matters when
12897 only one data type is written.
12898 Note: this function has side-effects (e.g. filling in missing operands). All
12899 Neon instructions should call it before performing bit encoding. */
12901 static struct neon_type_el
12902 neon_check_type (unsigned els, enum neon_shape ns, ...)
12905 unsigned i, pass, key_el = 0;
12906 unsigned types[NEON_MAX_TYPE_ELS];
12907 enum neon_el_type k_type = NT_invtype;
12908 unsigned k_size = -1u;
12909 struct neon_type_el badtype = {NT_invtype, -1};
12910 unsigned key_allowed = 0;
12912 /* Optional registers in Neon instructions are always (not) in operand 1.
12913 Fill in the missing operand here, if it was omitted. */
12914 if (els > 1 && !inst.operands[1].present)
12915 inst.operands[1] = inst.operands[0];
12917 /* Suck up all the varargs. */
12919 for (i = 0; i < els; i++)
12921 unsigned thisarg = va_arg (ap, unsigned);
12922 if (thisarg == N_IGNORE_TYPE)
12927 types[i] = thisarg;
12928 if ((thisarg & N_KEY) != 0)
12933 if (inst.vectype.elems > 0)
12934 for (i = 0; i < els; i++)
12935 if (inst.operands[i].vectype.type != NT_invtype)
12937 first_error (_("types specified in both the mnemonic and operands"));
12941 /* Duplicate inst.vectype elements here as necessary.
12942 FIXME: No idea if this is exactly the same as the ARM assembler,
12943 particularly when an insn takes one register and one non-register
12945 if (inst.vectype.elems == 1 && els > 1)
12948 inst.vectype.elems = els;
12949 inst.vectype.el[key_el] = inst.vectype.el[0];
12950 for (j = 0; j < els; j++)
12952 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12955 else if (inst.vectype.elems == 0 && els > 0)
12958 /* No types were given after the mnemonic, so look for types specified
12959 after each operand. We allow some flexibility here; as long as the
12960 "key" operand has a type, we can infer the others. */
12961 for (j = 0; j < els; j++)
12962 if (inst.operands[j].vectype.type != NT_invtype)
12963 inst.vectype.el[j] = inst.operands[j].vectype;
12965 if (inst.operands[key_el].vectype.type != NT_invtype)
12967 for (j = 0; j < els; j++)
12968 if (inst.operands[j].vectype.type == NT_invtype)
12969 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12974 first_error (_("operand types can't be inferred"));
12978 else if (inst.vectype.elems != els)
12980 first_error (_("type specifier has the wrong number of parts"));
12984 for (pass = 0; pass < 2; pass++)
12986 for (i = 0; i < els; i++)
12988 unsigned thisarg = types[i];
12989 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12990 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12991 enum neon_el_type g_type = inst.vectype.el[i].type;
12992 unsigned g_size = inst.vectype.el[i].size;
12994 /* Decay more-specific signed & unsigned types to sign-insensitive
12995 integer types if sign-specific variants are unavailable. */
12996 if ((g_type == NT_signed || g_type == NT_unsigned)
12997 && (types_allowed & N_SU_ALL) == 0)
12998 g_type = NT_integer;
13000 /* If only untyped args are allowed, decay any more specific types to
13001 them. Some instructions only care about signs for some element
13002 sizes, so handle that properly. */
13003 if (((types_allowed & N_UNT) == 0)
13004 && ((g_size == 8 && (types_allowed & N_8) != 0)
13005 || (g_size == 16 && (types_allowed & N_16) != 0)
13006 || (g_size == 32 && (types_allowed & N_32) != 0)
13007 || (g_size == 64 && (types_allowed & N_64) != 0)))
13008 g_type = NT_untyped;
13012 if ((thisarg & N_KEY) != 0)
13016 key_allowed = thisarg & ~N_KEY;
13021 if ((thisarg & N_VFP) != 0)
13023 enum neon_shape_el regshape;
13024 unsigned regwidth, match;
13026 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13029 first_error (_("invalid instruction shape"));
13032 regshape = neon_shape_tab[ns].el[i];
13033 regwidth = neon_shape_el_size[regshape];
13035 /* In VFP mode, operands must match register widths. If we
13036 have a key operand, use its width, else use the width of
13037 the current operand. */
13043 if (regwidth != match)
13045 first_error (_("operand size must match register width"));
13050 if ((thisarg & N_EQK) == 0)
13052 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13054 if ((given_type & types_allowed) == 0)
13056 first_error (_("bad type in Neon instruction"));
13062 enum neon_el_type mod_k_type = k_type;
13063 unsigned mod_k_size = k_size;
13064 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13065 if (g_type != mod_k_type || g_size != mod_k_size)
13067 first_error (_("inconsistent types in Neon instruction"));
13075 return inst.vectype.el[key_el];
13078 /* Neon-style VFP instruction forwarding. */
13080 /* Thumb VFP instructions have 0xE in the condition field. */
13083 do_vfp_cond_or_thumb (void)
13088 inst.instruction |= 0xe0000000;
13090 inst.instruction |= inst.cond << 28;
13093 /* Look up and encode a simple mnemonic, for use as a helper function for the
13094 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13095 etc. It is assumed that operand parsing has already been done, and that the
13096 operands are in the form expected by the given opcode (this isn't necessarily
13097 the same as the form in which they were parsed, hence some massaging must
13098 take place before this function is called).
13099 Checks current arch version against that in the looked-up opcode. */
13102 do_vfp_nsyn_opcode (const char *opname)
13104 const struct asm_opcode *opcode;
13106 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13111 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13112 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13119 inst.instruction = opcode->tvalue;
13120 opcode->tencode ();
13124 inst.instruction = (inst.cond << 28) | opcode->avalue;
13125 opcode->aencode ();
13130 do_vfp_nsyn_add_sub (enum neon_shape rs)
13132 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13137 do_vfp_nsyn_opcode ("fadds");
13139 do_vfp_nsyn_opcode ("fsubs");
13144 do_vfp_nsyn_opcode ("faddd");
13146 do_vfp_nsyn_opcode ("fsubd");
13150 /* Check operand types to see if this is a VFP instruction, and if so call
13154 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13156 enum neon_shape rs;
13157 struct neon_type_el et;
13162 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13163 et = neon_check_type (2, rs,
13164 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13168 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13169 et = neon_check_type (3, rs,
13170 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13177 if (et.type != NT_invtype)
13188 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13190 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13195 do_vfp_nsyn_opcode ("fmacs");
13197 do_vfp_nsyn_opcode ("fnmacs");
13202 do_vfp_nsyn_opcode ("fmacd");
13204 do_vfp_nsyn_opcode ("fnmacd");
13209 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13211 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13216 do_vfp_nsyn_opcode ("ffmas");
13218 do_vfp_nsyn_opcode ("ffnmas");
13223 do_vfp_nsyn_opcode ("ffmad");
13225 do_vfp_nsyn_opcode ("ffnmad");
13230 do_vfp_nsyn_mul (enum neon_shape rs)
13233 do_vfp_nsyn_opcode ("fmuls");
13235 do_vfp_nsyn_opcode ("fmuld");
13239 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13241 int is_neg = (inst.instruction & 0x80) != 0;
13242 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13247 do_vfp_nsyn_opcode ("fnegs");
13249 do_vfp_nsyn_opcode ("fabss");
13254 do_vfp_nsyn_opcode ("fnegd");
13256 do_vfp_nsyn_opcode ("fabsd");
13260 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13261 insns belong to Neon, and are handled elsewhere. */
13264 do_vfp_nsyn_ldm_stm (int is_dbmode)
13266 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13270 do_vfp_nsyn_opcode ("fldmdbs");
13272 do_vfp_nsyn_opcode ("fldmias");
13277 do_vfp_nsyn_opcode ("fstmdbs");
13279 do_vfp_nsyn_opcode ("fstmias");
13284 do_vfp_nsyn_sqrt (void)
13286 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13287 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13290 do_vfp_nsyn_opcode ("fsqrts");
13292 do_vfp_nsyn_opcode ("fsqrtd");
13296 do_vfp_nsyn_div (void)
13298 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13299 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13300 N_F32 | N_F64 | N_KEY | N_VFP);
13303 do_vfp_nsyn_opcode ("fdivs");
13305 do_vfp_nsyn_opcode ("fdivd");
13309 do_vfp_nsyn_nmul (void)
13311 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13312 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13313 N_F32 | N_F64 | N_KEY | N_VFP);
13317 NEON_ENCODE (SINGLE, inst);
13318 do_vfp_sp_dyadic ();
13322 NEON_ENCODE (DOUBLE, inst);
13323 do_vfp_dp_rd_rn_rm ();
13325 do_vfp_cond_or_thumb ();
13329 do_vfp_nsyn_cmp (void)
13331 if (inst.operands[1].isreg)
13333 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13334 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13338 NEON_ENCODE (SINGLE, inst);
13339 do_vfp_sp_monadic ();
13343 NEON_ENCODE (DOUBLE, inst);
13344 do_vfp_dp_rd_rm ();
13349 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13350 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13352 switch (inst.instruction & 0x0fffffff)
13355 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13358 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13366 NEON_ENCODE (SINGLE, inst);
13367 do_vfp_sp_compare_z ();
13371 NEON_ENCODE (DOUBLE, inst);
13375 do_vfp_cond_or_thumb ();
13379 nsyn_insert_sp (void)
13381 inst.operands[1] = inst.operands[0];
13382 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13383 inst.operands[0].reg = REG_SP;
13384 inst.operands[0].isreg = 1;
13385 inst.operands[0].writeback = 1;
13386 inst.operands[0].present = 1;
13390 do_vfp_nsyn_push (void)
13393 if (inst.operands[1].issingle)
13394 do_vfp_nsyn_opcode ("fstmdbs");
13396 do_vfp_nsyn_opcode ("fstmdbd");
13400 do_vfp_nsyn_pop (void)
13403 if (inst.operands[1].issingle)
13404 do_vfp_nsyn_opcode ("fldmias");
13406 do_vfp_nsyn_opcode ("fldmiad");
13409 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13410 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13413 neon_dp_fixup (struct arm_it* insn)
13415 unsigned int i = insn->instruction;
13420 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13431 insn->instruction = i;
13434 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13438 neon_logbits (unsigned x)
13440 return ffs (x) - 4;
13443 #define LOW4(R) ((R) & 0xf)
13444 #define HI1(R) (((R) >> 4) & 1)
13446 /* Encode insns with bit pattern:
13448 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13449 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13451 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13452 different meaning for some instruction. */
13455 neon_three_same (int isquad, int ubit, int size)
13457 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13458 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13459 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13460 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13461 inst.instruction |= LOW4 (inst.operands[2].reg);
13462 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13463 inst.instruction |= (isquad != 0) << 6;
13464 inst.instruction |= (ubit != 0) << 24;
13466 inst.instruction |= neon_logbits (size) << 20;
13468 neon_dp_fixup (&inst);
13471 /* Encode instructions of the form:
13473 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13474 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13476 Don't write size if SIZE == -1. */
13479 neon_two_same (int qbit, int ubit, int size)
13481 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13482 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13483 inst.instruction |= LOW4 (inst.operands[1].reg);
13484 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13485 inst.instruction |= (qbit != 0) << 6;
13486 inst.instruction |= (ubit != 0) << 24;
13489 inst.instruction |= neon_logbits (size) << 18;
13491 neon_dp_fixup (&inst);
13494 /* Neon instruction encoders, in approximate order of appearance. */
13497 do_neon_dyadic_i_su (void)
13499 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13500 struct neon_type_el et = neon_check_type (3, rs,
13501 N_EQK, N_EQK, N_SU_32 | N_KEY);
13502 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13506 do_neon_dyadic_i64_su (void)
13508 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13509 struct neon_type_el et = neon_check_type (3, rs,
13510 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13511 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13515 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13518 unsigned size = et.size >> 3;
13519 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13520 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13521 inst.instruction |= LOW4 (inst.operands[1].reg);
13522 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13523 inst.instruction |= (isquad != 0) << 6;
13524 inst.instruction |= immbits << 16;
13525 inst.instruction |= (size >> 3) << 7;
13526 inst.instruction |= (size & 0x7) << 19;
13528 inst.instruction |= (uval != 0) << 24;
13530 neon_dp_fixup (&inst);
13534 do_neon_shl_imm (void)
13536 if (!inst.operands[2].isreg)
13538 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13539 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13540 NEON_ENCODE (IMMED, inst);
13541 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13545 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13546 struct neon_type_el et = neon_check_type (3, rs,
13547 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13550 /* VSHL/VQSHL 3-register variants have syntax such as:
13552 whereas other 3-register operations encoded by neon_three_same have
13555 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13557 tmp = inst.operands[2].reg;
13558 inst.operands[2].reg = inst.operands[1].reg;
13559 inst.operands[1].reg = tmp;
13560 NEON_ENCODE (INTEGER, inst);
13561 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13566 do_neon_qshl_imm (void)
13568 if (!inst.operands[2].isreg)
13570 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13571 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13573 NEON_ENCODE (IMMED, inst);
13574 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13575 inst.operands[2].imm);
13579 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13580 struct neon_type_el et = neon_check_type (3, rs,
13581 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13584 /* See note in do_neon_shl_imm. */
13585 tmp = inst.operands[2].reg;
13586 inst.operands[2].reg = inst.operands[1].reg;
13587 inst.operands[1].reg = tmp;
13588 NEON_ENCODE (INTEGER, inst);
13589 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13594 do_neon_rshl (void)
13596 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13597 struct neon_type_el et = neon_check_type (3, rs,
13598 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13601 tmp = inst.operands[2].reg;
13602 inst.operands[2].reg = inst.operands[1].reg;
13603 inst.operands[1].reg = tmp;
13604 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13608 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13610 /* Handle .I8 pseudo-instructions. */
13613 /* Unfortunately, this will make everything apart from zero out-of-range.
13614 FIXME is this the intended semantics? There doesn't seem much point in
13615 accepting .I8 if so. */
13616 immediate |= immediate << 8;
13622 if (immediate == (immediate & 0x000000ff))
13624 *immbits = immediate;
13627 else if (immediate == (immediate & 0x0000ff00))
13629 *immbits = immediate >> 8;
13632 else if (immediate == (immediate & 0x00ff0000))
13634 *immbits = immediate >> 16;
13637 else if (immediate == (immediate & 0xff000000))
13639 *immbits = immediate >> 24;
13642 if ((immediate & 0xffff) != (immediate >> 16))
13643 goto bad_immediate;
13644 immediate &= 0xffff;
13647 if (immediate == (immediate & 0x000000ff))
13649 *immbits = immediate;
13652 else if (immediate == (immediate & 0x0000ff00))
13654 *immbits = immediate >> 8;
13659 first_error (_("immediate value out of range"));
13663 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13667 neon_bits_same_in_bytes (unsigned imm)
13669 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13670 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13671 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13672 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13675 /* For immediate of above form, return 0bABCD. */
13678 neon_squash_bits (unsigned imm)
13680 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13681 | ((imm & 0x01000000) >> 21);
13684 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13687 neon_qfloat_bits (unsigned imm)
13689 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13692 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13693 the instruction. *OP is passed as the initial value of the op field, and
13694 may be set to a different value depending on the constant (i.e.
13695 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13696 MVN). If the immediate looks like a repeated pattern then also
13697 try smaller element sizes. */
13700 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13701 unsigned *immbits, int *op, int size,
13702 enum neon_el_type type)
13704 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13706 if (type == NT_float && !float_p)
13709 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13711 if (size != 32 || *op == 1)
13713 *immbits = neon_qfloat_bits (immlo);
13719 if (neon_bits_same_in_bytes (immhi)
13720 && neon_bits_same_in_bytes (immlo))
13724 *immbits = (neon_squash_bits (immhi) << 4)
13725 | neon_squash_bits (immlo);
13730 if (immhi != immlo)
13736 if (immlo == (immlo & 0x000000ff))
13741 else if (immlo == (immlo & 0x0000ff00))
13743 *immbits = immlo >> 8;
13746 else if (immlo == (immlo & 0x00ff0000))
13748 *immbits = immlo >> 16;
13751 else if (immlo == (immlo & 0xff000000))
13753 *immbits = immlo >> 24;
13756 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13758 *immbits = (immlo >> 8) & 0xff;
13761 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13763 *immbits = (immlo >> 16) & 0xff;
13767 if ((immlo & 0xffff) != (immlo >> 16))
13774 if (immlo == (immlo & 0x000000ff))
13779 else if (immlo == (immlo & 0x0000ff00))
13781 *immbits = immlo >> 8;
13785 if ((immlo & 0xff) != (immlo >> 8))
13790 if (immlo == (immlo & 0x000000ff))
13792 /* Don't allow MVN with 8-bit immediate. */
13802 /* Write immediate bits [7:0] to the following locations:
13804 |28/24|23 19|18 16|15 4|3 0|
13805 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13807 This function is used by VMOV/VMVN/VORR/VBIC. */
13810 neon_write_immbits (unsigned immbits)
13812 inst.instruction |= immbits & 0xf;
13813 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13814 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13817 /* Invert low-order SIZE bits of XHI:XLO. */
13820 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13822 unsigned immlo = xlo ? *xlo : 0;
13823 unsigned immhi = xhi ? *xhi : 0;
13828 immlo = (~immlo) & 0xff;
13832 immlo = (~immlo) & 0xffff;
13836 immhi = (~immhi) & 0xffffffff;
13837 /* fall through. */
13840 immlo = (~immlo) & 0xffffffff;
13855 do_neon_logic (void)
13857 if (inst.operands[2].present && inst.operands[2].isreg)
13859 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13860 neon_check_type (3, rs, N_IGNORE_TYPE);
13861 /* U bit and size field were set as part of the bitmask. */
13862 NEON_ENCODE (INTEGER, inst);
13863 neon_three_same (neon_quad (rs), 0, -1);
13867 const int three_ops_form = (inst.operands[2].present
13868 && !inst.operands[2].isreg);
13869 const int immoperand = (three_ops_form ? 2 : 1);
13870 enum neon_shape rs = (three_ops_form
13871 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13872 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13873 struct neon_type_el et = neon_check_type (2, rs,
13874 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13875 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13879 if (et.type == NT_invtype)
13882 if (three_ops_form)
13883 constraint (inst.operands[0].reg != inst.operands[1].reg,
13884 _("first and second operands shall be the same register"));
13886 NEON_ENCODE (IMMED, inst);
13888 immbits = inst.operands[immoperand].imm;
13891 /* .i64 is a pseudo-op, so the immediate must be a repeating
13893 if (immbits != (inst.operands[immoperand].regisimm ?
13894 inst.operands[immoperand].reg : 0))
13896 /* Set immbits to an invalid constant. */
13897 immbits = 0xdeadbeef;
13904 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13908 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13912 /* Pseudo-instruction for VBIC. */
13913 neon_invert_size (&immbits, 0, et.size);
13914 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13918 /* Pseudo-instruction for VORR. */
13919 neon_invert_size (&immbits, 0, et.size);
13920 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13930 inst.instruction |= neon_quad (rs) << 6;
13931 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13932 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13933 inst.instruction |= cmode << 8;
13934 neon_write_immbits (immbits);
13936 neon_dp_fixup (&inst);
13941 do_neon_bitfield (void)
13943 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13944 neon_check_type (3, rs, N_IGNORE_TYPE);
13945 neon_three_same (neon_quad (rs), 0, -1);
13949 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13952 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13953 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13955 if (et.type == NT_float)
13957 NEON_ENCODE (FLOAT, inst);
13958 neon_three_same (neon_quad (rs), 0, -1);
13962 NEON_ENCODE (INTEGER, inst);
13963 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13968 do_neon_dyadic_if_su (void)
13970 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13974 do_neon_dyadic_if_su_d (void)
13976 /* This version only allow D registers, but that constraint is enforced during
13977 operand parsing so we don't need to do anything extra here. */
13978 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13982 do_neon_dyadic_if_i_d (void)
13984 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13985 affected if we specify unsigned args. */
13986 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13989 enum vfp_or_neon_is_neon_bits
13992 NEON_CHECK_ARCH = 2,
13993 NEON_CHECK_ARCH8 = 4
13996 /* Call this function if an instruction which may have belonged to the VFP or
13997 Neon instruction sets, but turned out to be a Neon instruction (due to the
13998 operand types involved, etc.). We have to check and/or fix-up a couple of
14001 - Make sure the user hasn't attempted to make a Neon instruction
14003 - Alter the value in the condition code field if necessary.
14004 - Make sure that the arch supports Neon instructions.
14006 Which of these operations take place depends on bits from enum
14007 vfp_or_neon_is_neon_bits.
14009 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14010 current instruction's condition is COND_ALWAYS, the condition field is
14011 changed to inst.uncond_value. This is necessary because instructions shared
14012 between VFP and Neon may be conditional for the VFP variants only, and the
14013 unconditional Neon version must have, e.g., 0xF in the condition field. */
14016 vfp_or_neon_is_neon (unsigned check)
14018 /* Conditions are always legal in Thumb mode (IT blocks). */
14019 if (!thumb_mode && (check & NEON_CHECK_CC))
14021 if (inst.cond != COND_ALWAYS)
14023 first_error (_(BAD_COND));
14026 if (inst.uncond_value != -1)
14027 inst.instruction |= inst.uncond_value << 28;
14030 if ((check & NEON_CHECK_ARCH)
14031 && !mark_feature_used (&fpu_neon_ext_v1))
14033 first_error (_(BAD_FPU));
14037 if ((check & NEON_CHECK_ARCH8)
14038 && !mark_feature_used (&fpu_neon_ext_armv8))
14040 first_error (_(BAD_FPU));
14048 do_neon_addsub_if_i (void)
14050 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14053 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14056 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14057 affected if we specify unsigned args. */
14058 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14061 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14063 V<op> A,B (A is operand 0, B is operand 2)
14068 so handle that case specially. */
14071 neon_exchange_operands (void)
14073 void *scratch = alloca (sizeof (inst.operands[0]));
14074 if (inst.operands[1].present)
14076 /* Swap operands[1] and operands[2]. */
14077 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14078 inst.operands[1] = inst.operands[2];
14079 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14083 inst.operands[1] = inst.operands[2];
14084 inst.operands[2] = inst.operands[0];
14089 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14091 if (inst.operands[2].isreg)
14094 neon_exchange_operands ();
14095 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14099 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14100 struct neon_type_el et = neon_check_type (2, rs,
14101 N_EQK | N_SIZ, immtypes | N_KEY);
14103 NEON_ENCODE (IMMED, inst);
14104 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14105 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14106 inst.instruction |= LOW4 (inst.operands[1].reg);
14107 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14108 inst.instruction |= neon_quad (rs) << 6;
14109 inst.instruction |= (et.type == NT_float) << 10;
14110 inst.instruction |= neon_logbits (et.size) << 18;
14112 neon_dp_fixup (&inst);
14119 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14123 do_neon_cmp_inv (void)
14125 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14131 neon_compare (N_IF_32, N_IF_32, FALSE);
14134 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14135 scalars, which are encoded in 5 bits, M : Rm.
14136 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14137 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14141 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14143 unsigned regno = NEON_SCALAR_REG (scalar);
14144 unsigned elno = NEON_SCALAR_INDEX (scalar);
14149 if (regno > 7 || elno > 3)
14151 return regno | (elno << 3);
14154 if (regno > 15 || elno > 1)
14156 return regno | (elno << 4);
14160 first_error (_("scalar out of range for multiply instruction"));
14166 /* Encode multiply / multiply-accumulate scalar instructions. */
14169 neon_mul_mac (struct neon_type_el et, int ubit)
14173 /* Give a more helpful error message if we have an invalid type. */
14174 if (et.type == NT_invtype)
14177 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14178 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14179 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14180 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14181 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14182 inst.instruction |= LOW4 (scalar);
14183 inst.instruction |= HI1 (scalar) << 5;
14184 inst.instruction |= (et.type == NT_float) << 8;
14185 inst.instruction |= neon_logbits (et.size) << 20;
14186 inst.instruction |= (ubit != 0) << 24;
14188 neon_dp_fixup (&inst);
14192 do_neon_mac_maybe_scalar (void)
14194 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14197 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14200 if (inst.operands[2].isscalar)
14202 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14203 struct neon_type_el et = neon_check_type (3, rs,
14204 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14205 NEON_ENCODE (SCALAR, inst);
14206 neon_mul_mac (et, neon_quad (rs));
14210 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14211 affected if we specify unsigned args. */
14212 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14217 do_neon_fmac (void)
14219 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14222 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14225 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14231 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14232 struct neon_type_el et = neon_check_type (3, rs,
14233 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14234 neon_three_same (neon_quad (rs), 0, et.size);
14237 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14238 same types as the MAC equivalents. The polynomial type for this instruction
14239 is encoded the same as the integer type. */
14244 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14247 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14250 if (inst.operands[2].isscalar)
14251 do_neon_mac_maybe_scalar ();
14253 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14257 do_neon_qdmulh (void)
14259 if (inst.operands[2].isscalar)
14261 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14262 struct neon_type_el et = neon_check_type (3, rs,
14263 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14264 NEON_ENCODE (SCALAR, inst);
14265 neon_mul_mac (et, neon_quad (rs));
14269 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14270 struct neon_type_el et = neon_check_type (3, rs,
14271 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14272 NEON_ENCODE (INTEGER, inst);
14273 /* The U bit (rounding) comes from bit mask. */
14274 neon_three_same (neon_quad (rs), 0, et.size);
14279 do_neon_fcmp_absolute (void)
14281 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14282 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14283 /* Size field comes from bit mask. */
14284 neon_three_same (neon_quad (rs), 1, -1);
14288 do_neon_fcmp_absolute_inv (void)
14290 neon_exchange_operands ();
14291 do_neon_fcmp_absolute ();
14295 do_neon_step (void)
14297 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14298 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14299 neon_three_same (neon_quad (rs), 0, -1);
14303 do_neon_abs_neg (void)
14305 enum neon_shape rs;
14306 struct neon_type_el et;
14308 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14311 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14314 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14315 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14317 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14318 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14319 inst.instruction |= LOW4 (inst.operands[1].reg);
14320 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14321 inst.instruction |= neon_quad (rs) << 6;
14322 inst.instruction |= (et.type == NT_float) << 10;
14323 inst.instruction |= neon_logbits (et.size) << 18;
14325 neon_dp_fixup (&inst);
14331 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14332 struct neon_type_el et = neon_check_type (2, rs,
14333 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14334 int imm = inst.operands[2].imm;
14335 constraint (imm < 0 || (unsigned)imm >= et.size,
14336 _("immediate out of range for insert"));
14337 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14343 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14344 struct neon_type_el et = neon_check_type (2, rs,
14345 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14346 int imm = inst.operands[2].imm;
14347 constraint (imm < 1 || (unsigned)imm > et.size,
14348 _("immediate out of range for insert"));
14349 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14353 do_neon_qshlu_imm (void)
14355 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14356 struct neon_type_el et = neon_check_type (2, rs,
14357 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14358 int imm = inst.operands[2].imm;
14359 constraint (imm < 0 || (unsigned)imm >= et.size,
14360 _("immediate out of range for shift"));
14361 /* Only encodes the 'U present' variant of the instruction.
14362 In this case, signed types have OP (bit 8) set to 0.
14363 Unsigned types have OP set to 1. */
14364 inst.instruction |= (et.type == NT_unsigned) << 8;
14365 /* The rest of the bits are the same as other immediate shifts. */
14366 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14370 do_neon_qmovn (void)
14372 struct neon_type_el et = neon_check_type (2, NS_DQ,
14373 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14374 /* Saturating move where operands can be signed or unsigned, and the
14375 destination has the same signedness. */
14376 NEON_ENCODE (INTEGER, inst);
14377 if (et.type == NT_unsigned)
14378 inst.instruction |= 0xc0;
14380 inst.instruction |= 0x80;
14381 neon_two_same (0, 1, et.size / 2);
14385 do_neon_qmovun (void)
14387 struct neon_type_el et = neon_check_type (2, NS_DQ,
14388 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14389 /* Saturating move with unsigned results. Operands must be signed. */
14390 NEON_ENCODE (INTEGER, inst);
14391 neon_two_same (0, 1, et.size / 2);
14395 do_neon_rshift_sat_narrow (void)
14397 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14398 or unsigned. If operands are unsigned, results must also be unsigned. */
14399 struct neon_type_el et = neon_check_type (2, NS_DQI,
14400 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14401 int imm = inst.operands[2].imm;
14402 /* This gets the bounds check, size encoding and immediate bits calculation
14406 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14407 VQMOVN.I<size> <Dd>, <Qm>. */
14410 inst.operands[2].present = 0;
14411 inst.instruction = N_MNEM_vqmovn;
14416 constraint (imm < 1 || (unsigned)imm > et.size,
14417 _("immediate out of range"));
14418 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14422 do_neon_rshift_sat_narrow_u (void)
14424 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14425 or unsigned. If operands are unsigned, results must also be unsigned. */
14426 struct neon_type_el et = neon_check_type (2, NS_DQI,
14427 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14428 int imm = inst.operands[2].imm;
14429 /* This gets the bounds check, size encoding and immediate bits calculation
14433 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14434 VQMOVUN.I<size> <Dd>, <Qm>. */
14437 inst.operands[2].present = 0;
14438 inst.instruction = N_MNEM_vqmovun;
14443 constraint (imm < 1 || (unsigned)imm > et.size,
14444 _("immediate out of range"));
14445 /* FIXME: The manual is kind of unclear about what value U should have in
14446 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14448 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14452 do_neon_movn (void)
14454 struct neon_type_el et = neon_check_type (2, NS_DQ,
14455 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14456 NEON_ENCODE (INTEGER, inst);
14457 neon_two_same (0, 1, et.size / 2);
14461 do_neon_rshift_narrow (void)
14463 struct neon_type_el et = neon_check_type (2, NS_DQI,
14464 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14465 int imm = inst.operands[2].imm;
14466 /* This gets the bounds check, size encoding and immediate bits calculation
14470 /* If immediate is zero then we are a pseudo-instruction for
14471 VMOVN.I<size> <Dd>, <Qm> */
14474 inst.operands[2].present = 0;
14475 inst.instruction = N_MNEM_vmovn;
14480 constraint (imm < 1 || (unsigned)imm > et.size,
14481 _("immediate out of range for narrowing operation"));
14482 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14486 do_neon_shll (void)
14488 /* FIXME: Type checking when lengthening. */
14489 struct neon_type_el et = neon_check_type (2, NS_QDI,
14490 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14491 unsigned imm = inst.operands[2].imm;
14493 if (imm == et.size)
14495 /* Maximum shift variant. */
14496 NEON_ENCODE (INTEGER, inst);
14497 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14498 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14499 inst.instruction |= LOW4 (inst.operands[1].reg);
14500 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14501 inst.instruction |= neon_logbits (et.size) << 18;
14503 neon_dp_fixup (&inst);
14507 /* A more-specific type check for non-max versions. */
14508 et = neon_check_type (2, NS_QDI,
14509 N_EQK | N_DBL, N_SU_32 | N_KEY);
14510 NEON_ENCODE (IMMED, inst);
14511 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14515 /* Check the various types for the VCVT instruction, and return which version
14516 the current instruction is. */
14518 #define CVT_FLAVOUR_VAR \
14519 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14520 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14521 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14522 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14523 /* Half-precision conversions. */ \
14524 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14525 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14526 /* VFP instructions. */ \
14527 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14528 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14529 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14530 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14531 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14532 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14533 /* VFP instructions with bitshift. */ \
14534 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14535 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14536 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14537 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14538 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14539 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14540 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14541 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14543 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14544 neon_cvt_flavour_##C,
14546 /* The different types of conversions we can do. */
14547 enum neon_cvt_flavour
14550 neon_cvt_flavour_invalid,
14551 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14556 static enum neon_cvt_flavour
14557 get_neon_cvt_flavour (enum neon_shape rs)
14559 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14560 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14561 if (et.type != NT_invtype) \
14563 inst.error = NULL; \
14564 return (neon_cvt_flavour_##C); \
14567 struct neon_type_el et;
14568 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14569 || rs == NS_FF) ? N_VFP : 0;
14570 /* The instruction versions which take an immediate take one register
14571 argument, which is extended to the width of the full register. Thus the
14572 "source" and "destination" registers must have the same width. Hack that
14573 here by making the size equal to the key (wider, in this case) operand. */
14574 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14578 return neon_cvt_flavour_invalid;
14593 /* Neon-syntax VFP conversions. */
14596 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
14598 const char *opname = 0;
14600 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14602 /* Conversions with immediate bitshift. */
14603 const char *enc[] =
14605 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14611 if (flavour < (int) ARRAY_SIZE (enc))
14613 opname = enc[flavour];
14614 constraint (inst.operands[0].reg != inst.operands[1].reg,
14615 _("operands 0 and 1 must be the same register"));
14616 inst.operands[1] = inst.operands[2];
14617 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14622 /* Conversions without bitshift. */
14623 const char *enc[] =
14625 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14631 if (flavour < (int) ARRAY_SIZE (enc))
14632 opname = enc[flavour];
14636 do_vfp_nsyn_opcode (opname);
14640 do_vfp_nsyn_cvtz (void)
14642 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14643 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14644 const char *enc[] =
14646 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14652 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14653 do_vfp_nsyn_opcode (enc[flavour]);
14657 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
14658 enum neon_cvt_mode mode)
14663 set_it_insn_type (OUTSIDE_IT_INSN);
14667 case neon_cvt_flavour_s32_f64:
14671 case neon_cvt_flavour_s32_f32:
14675 case neon_cvt_flavour_u32_f64:
14679 case neon_cvt_flavour_u32_f32:
14684 first_error (_("invalid instruction shape"));
14690 case neon_cvt_mode_a: rm = 0; break;
14691 case neon_cvt_mode_n: rm = 1; break;
14692 case neon_cvt_mode_p: rm = 2; break;
14693 case neon_cvt_mode_m: rm = 3; break;
14694 default: first_error (_("invalid rounding mode")); return;
14697 NEON_ENCODE (FPV8, inst);
14698 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14699 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
14700 inst.instruction |= sz << 8;
14701 inst.instruction |= op << 7;
14702 inst.instruction |= rm << 16;
14703 inst.instruction |= 0xf0000000;
14704 inst.is_neon = TRUE;
14708 do_neon_cvt_1 (enum neon_cvt_mode mode)
14710 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14711 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14712 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14714 /* PR11109: Handle round-to-zero for VCVT conversions. */
14715 if (mode == neon_cvt_mode_z
14716 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14717 && (flavour == neon_cvt_flavour_s32_f32
14718 || flavour == neon_cvt_flavour_u32_f32
14719 || flavour == neon_cvt_flavour_s32_f64
14720 || flavour == neon_cvt_flavour_u32_f64)
14721 && (rs == NS_FD || rs == NS_FF))
14723 do_vfp_nsyn_cvtz ();
14727 /* VFP rather than Neon conversions. */
14728 if (flavour >= neon_cvt_flavour_first_fp)
14730 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14731 do_vfp_nsyn_cvt (rs, flavour);
14733 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14744 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14746 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14749 /* Fixed-point conversion with #0 immediate is encoded as an
14750 integer conversion. */
14751 if (inst.operands[2].present && inst.operands[2].imm == 0)
14753 immbits = 32 - inst.operands[2].imm;
14754 NEON_ENCODE (IMMED, inst);
14755 if (flavour != neon_cvt_flavour_invalid)
14756 inst.instruction |= enctab[flavour];
14757 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14758 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14759 inst.instruction |= LOW4 (inst.operands[1].reg);
14760 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14761 inst.instruction |= neon_quad (rs) << 6;
14762 inst.instruction |= 1 << 21;
14763 inst.instruction |= immbits << 16;
14765 neon_dp_fixup (&inst);
14771 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
14773 NEON_ENCODE (FLOAT, inst);
14774 set_it_insn_type (OUTSIDE_IT_INSN);
14776 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
14779 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14780 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14781 inst.instruction |= LOW4 (inst.operands[1].reg);
14782 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14783 inst.instruction |= neon_quad (rs) << 6;
14784 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
14785 inst.instruction |= mode << 8;
14787 inst.instruction |= 0xfc000000;
14789 inst.instruction |= 0xf0000000;
14795 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14797 NEON_ENCODE (INTEGER, inst);
14799 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14802 if (flavour != neon_cvt_flavour_invalid)
14803 inst.instruction |= enctab[flavour];
14805 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14806 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14807 inst.instruction |= LOW4 (inst.operands[1].reg);
14808 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14809 inst.instruction |= neon_quad (rs) << 6;
14810 inst.instruction |= 2 << 18;
14812 neon_dp_fixup (&inst);
14817 /* Half-precision conversions for Advanced SIMD -- neon. */
14822 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14824 as_bad (_("operand size must match register width"));
14829 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14831 as_bad (_("operand size must match register width"));
14836 inst.instruction = 0x3b60600;
14838 inst.instruction = 0x3b60700;
14840 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14841 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14842 inst.instruction |= LOW4 (inst.operands[1].reg);
14843 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14844 neon_dp_fixup (&inst);
14848 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14849 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14850 do_vfp_nsyn_cvt (rs, flavour);
14852 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14857 do_neon_cvtr (void)
14859 do_neon_cvt_1 (neon_cvt_mode_x);
14865 do_neon_cvt_1 (neon_cvt_mode_z);
14869 do_neon_cvta (void)
14871 do_neon_cvt_1 (neon_cvt_mode_a);
14875 do_neon_cvtn (void)
14877 do_neon_cvt_1 (neon_cvt_mode_n);
14881 do_neon_cvtp (void)
14883 do_neon_cvt_1 (neon_cvt_mode_p);
14887 do_neon_cvtm (void)
14889 do_neon_cvt_1 (neon_cvt_mode_m);
14893 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
14896 mark_feature_used (&fpu_vfp_ext_armv8);
14898 encode_arm_vfp_reg (inst.operands[0].reg,
14899 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
14900 encode_arm_vfp_reg (inst.operands[1].reg,
14901 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
14902 inst.instruction |= to ? 0x10000 : 0;
14903 inst.instruction |= t ? 0x80 : 0;
14904 inst.instruction |= is_double ? 0x100 : 0;
14905 do_vfp_cond_or_thumb ();
14909 do_neon_cvttb_1 (bfd_boolean t)
14911 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
14915 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
14918 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
14920 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
14923 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
14925 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
14928 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
14930 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
14933 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
14940 do_neon_cvtb (void)
14942 do_neon_cvttb_1 (FALSE);
14947 do_neon_cvtt (void)
14949 do_neon_cvttb_1 (TRUE);
14953 neon_move_immediate (void)
14955 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14956 struct neon_type_el et = neon_check_type (2, rs,
14957 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14958 unsigned immlo, immhi = 0, immbits;
14959 int op, cmode, float_p;
14961 constraint (et.type == NT_invtype,
14962 _("operand size must be specified for immediate VMOV"));
14964 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14965 op = (inst.instruction & (1 << 5)) != 0;
14967 immlo = inst.operands[1].imm;
14968 if (inst.operands[1].regisimm)
14969 immhi = inst.operands[1].reg;
14971 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14972 _("immediate has bits set outside the operand size"));
14974 float_p = inst.operands[1].immisfloat;
14976 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14977 et.size, et.type)) == FAIL)
14979 /* Invert relevant bits only. */
14980 neon_invert_size (&immlo, &immhi, et.size);
14981 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14982 with one or the other; those cases are caught by
14983 neon_cmode_for_move_imm. */
14985 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14986 &op, et.size, et.type)) == FAIL)
14988 first_error (_("immediate out of range"));
14993 inst.instruction &= ~(1 << 5);
14994 inst.instruction |= op << 5;
14996 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14997 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14998 inst.instruction |= neon_quad (rs) << 6;
14999 inst.instruction |= cmode << 8;
15001 neon_write_immbits (immbits);
15007 if (inst.operands[1].isreg)
15009 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15011 NEON_ENCODE (INTEGER, inst);
15012 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15013 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15014 inst.instruction |= LOW4 (inst.operands[1].reg);
15015 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15016 inst.instruction |= neon_quad (rs) << 6;
15020 NEON_ENCODE (IMMED, inst);
15021 neon_move_immediate ();
15024 neon_dp_fixup (&inst);
15027 /* Encode instructions of form:
15029 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15030 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15033 neon_mixed_length (struct neon_type_el et, unsigned size)
15035 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15036 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15037 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15038 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15039 inst.instruction |= LOW4 (inst.operands[2].reg);
15040 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15041 inst.instruction |= (et.type == NT_unsigned) << 24;
15042 inst.instruction |= neon_logbits (size) << 20;
15044 neon_dp_fixup (&inst);
15048 do_neon_dyadic_long (void)
15050 /* FIXME: Type checking for lengthening op. */
15051 struct neon_type_el et = neon_check_type (3, NS_QDD,
15052 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15053 neon_mixed_length (et, et.size);
15057 do_neon_abal (void)
15059 struct neon_type_el et = neon_check_type (3, NS_QDD,
15060 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15061 neon_mixed_length (et, et.size);
15065 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15067 if (inst.operands[2].isscalar)
15069 struct neon_type_el et = neon_check_type (3, NS_QDS,
15070 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
15071 NEON_ENCODE (SCALAR, inst);
15072 neon_mul_mac (et, et.type == NT_unsigned);
15076 struct neon_type_el et = neon_check_type (3, NS_QDD,
15077 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
15078 NEON_ENCODE (INTEGER, inst);
15079 neon_mixed_length (et, et.size);
15084 do_neon_mac_maybe_scalar_long (void)
15086 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15090 do_neon_dyadic_wide (void)
15092 struct neon_type_el et = neon_check_type (3, NS_QQD,
15093 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15094 neon_mixed_length (et, et.size);
15098 do_neon_dyadic_narrow (void)
15100 struct neon_type_el et = neon_check_type (3, NS_QDD,
15101 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
15102 /* Operand sign is unimportant, and the U bit is part of the opcode,
15103 so force the operand type to integer. */
15104 et.type = NT_integer;
15105 neon_mixed_length (et, et.size / 2);
15109 do_neon_mul_sat_scalar_long (void)
15111 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15115 do_neon_vmull (void)
15117 if (inst.operands[2].isscalar)
15118 do_neon_mac_maybe_scalar_long ();
15121 struct neon_type_el et = neon_check_type (3, NS_QDD,
15122 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
15124 if (et.type == NT_poly)
15125 NEON_ENCODE (POLY, inst);
15127 NEON_ENCODE (INTEGER, inst);
15129 /* For polynomial encoding the U bit must be zero, and the size must
15130 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15131 obviously, as 0b10). */
15134 /* Check we're on the correct architecture. */
15135 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15137 _("Instruction form not available on this architecture.");
15142 neon_mixed_length (et, et.size);
15149 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
15150 struct neon_type_el et = neon_check_type (3, rs,
15151 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15152 unsigned imm = (inst.operands[3].imm * et.size) / 8;
15154 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15155 _("shift out of range"));
15156 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15157 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15158 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15159 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15160 inst.instruction |= LOW4 (inst.operands[2].reg);
15161 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15162 inst.instruction |= neon_quad (rs) << 6;
15163 inst.instruction |= imm << 8;
15165 neon_dp_fixup (&inst);
15171 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15172 struct neon_type_el et = neon_check_type (2, rs,
15173 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15174 unsigned op = (inst.instruction >> 7) & 3;
15175 /* N (width of reversed regions) is encoded as part of the bitmask. We
15176 extract it here to check the elements to be reversed are smaller.
15177 Otherwise we'd get a reserved instruction. */
15178 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15179 gas_assert (elsize != 0);
15180 constraint (et.size >= elsize,
15181 _("elements must be smaller than reversal region"));
15182 neon_two_same (neon_quad (rs), 1, et.size);
15188 if (inst.operands[1].isscalar)
15190 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15191 struct neon_type_el et = neon_check_type (2, rs,
15192 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15193 unsigned sizebits = et.size >> 3;
15194 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15195 int logsize = neon_logbits (et.size);
15196 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15198 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15201 NEON_ENCODE (SCALAR, inst);
15202 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15203 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15204 inst.instruction |= LOW4 (dm);
15205 inst.instruction |= HI1 (dm) << 5;
15206 inst.instruction |= neon_quad (rs) << 6;
15207 inst.instruction |= x << 17;
15208 inst.instruction |= sizebits << 16;
15210 neon_dp_fixup (&inst);
15214 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15215 struct neon_type_el et = neon_check_type (2, rs,
15216 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15217 /* Duplicate ARM register to lanes of vector. */
15218 NEON_ENCODE (ARMREG, inst);
15221 case 8: inst.instruction |= 0x400000; break;
15222 case 16: inst.instruction |= 0x000020; break;
15223 case 32: inst.instruction |= 0x000000; break;
15226 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15227 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15228 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15229 inst.instruction |= neon_quad (rs) << 21;
15230 /* The encoding for this instruction is identical for the ARM and Thumb
15231 variants, except for the condition field. */
15232 do_vfp_cond_or_thumb ();
15236 /* VMOV has particularly many variations. It can be one of:
15237 0. VMOV<c><q> <Qd>, <Qm>
15238 1. VMOV<c><q> <Dd>, <Dm>
15239 (Register operations, which are VORR with Rm = Rn.)
15240 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15241 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15243 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15244 (ARM register to scalar.)
15245 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15246 (Two ARM registers to vector.)
15247 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15248 (Scalar to ARM register.)
15249 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15250 (Vector to two ARM registers.)
15251 8. VMOV.F32 <Sd>, <Sm>
15252 9. VMOV.F64 <Dd>, <Dm>
15253 (VFP register moves.)
15254 10. VMOV.F32 <Sd>, #imm
15255 11. VMOV.F64 <Dd>, #imm
15256 (VFP float immediate load.)
15257 12. VMOV <Rd>, <Sm>
15258 (VFP single to ARM reg.)
15259 13. VMOV <Sd>, <Rm>
15260 (ARM reg to VFP single.)
15261 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15262 (Two ARM regs to two VFP singles.)
15263 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15264 (Two VFP singles to two ARM regs.)
15266 These cases can be disambiguated using neon_select_shape, except cases 1/9
15267 and 3/11 which depend on the operand type too.
15269 All the encoded bits are hardcoded by this function.
15271 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15272 Cases 5, 7 may be used with VFPv2 and above.
15274 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15275 can specify a type where it doesn't make sense to, and is ignored). */
15280 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15281 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15283 struct neon_type_el et;
15284 const char *ldconst = 0;
15288 case NS_DD: /* case 1/9. */
15289 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15290 /* It is not an error here if no type is given. */
15292 if (et.type == NT_float && et.size == 64)
15294 do_vfp_nsyn_opcode ("fcpyd");
15297 /* fall through. */
15299 case NS_QQ: /* case 0/1. */
15301 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15303 /* The architecture manual I have doesn't explicitly state which
15304 value the U bit should have for register->register moves, but
15305 the equivalent VORR instruction has U = 0, so do that. */
15306 inst.instruction = 0x0200110;
15307 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15308 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15309 inst.instruction |= LOW4 (inst.operands[1].reg);
15310 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15311 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15312 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15313 inst.instruction |= neon_quad (rs) << 6;
15315 neon_dp_fixup (&inst);
15319 case NS_DI: /* case 3/11. */
15320 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15322 if (et.type == NT_float && et.size == 64)
15324 /* case 11 (fconstd). */
15325 ldconst = "fconstd";
15326 goto encode_fconstd;
15328 /* fall through. */
15330 case NS_QI: /* case 2/3. */
15331 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15333 inst.instruction = 0x0800010;
15334 neon_move_immediate ();
15335 neon_dp_fixup (&inst);
15338 case NS_SR: /* case 4. */
15340 unsigned bcdebits = 0;
15342 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15343 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15345 /* .<size> is optional here, defaulting to .32. */
15346 if (inst.vectype.elems == 0
15347 && inst.operands[0].vectype.type == NT_invtype
15348 && inst.operands[1].vectype.type == NT_invtype)
15350 inst.vectype.el[0].type = NT_untyped;
15351 inst.vectype.el[0].size = 32;
15352 inst.vectype.elems = 1;
15355 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15356 logsize = neon_logbits (et.size);
15358 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15360 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15361 && et.size != 32, _(BAD_FPU));
15362 constraint (et.type == NT_invtype, _("bad type for scalar"));
15363 constraint (x >= 64 / et.size, _("scalar index out of range"));
15367 case 8: bcdebits = 0x8; break;
15368 case 16: bcdebits = 0x1; break;
15369 case 32: bcdebits = 0x0; break;
15373 bcdebits |= x << logsize;
15375 inst.instruction = 0xe000b10;
15376 do_vfp_cond_or_thumb ();
15377 inst.instruction |= LOW4 (dn) << 16;
15378 inst.instruction |= HI1 (dn) << 7;
15379 inst.instruction |= inst.operands[1].reg << 12;
15380 inst.instruction |= (bcdebits & 3) << 5;
15381 inst.instruction |= (bcdebits >> 2) << 21;
15385 case NS_DRR: /* case 5 (fmdrr). */
15386 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15389 inst.instruction = 0xc400b10;
15390 do_vfp_cond_or_thumb ();
15391 inst.instruction |= LOW4 (inst.operands[0].reg);
15392 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15393 inst.instruction |= inst.operands[1].reg << 12;
15394 inst.instruction |= inst.operands[2].reg << 16;
15397 case NS_RS: /* case 6. */
15400 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15401 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15402 unsigned abcdebits = 0;
15404 /* .<dt> is optional here, defaulting to .32. */
15405 if (inst.vectype.elems == 0
15406 && inst.operands[0].vectype.type == NT_invtype
15407 && inst.operands[1].vectype.type == NT_invtype)
15409 inst.vectype.el[0].type = NT_untyped;
15410 inst.vectype.el[0].size = 32;
15411 inst.vectype.elems = 1;
15414 et = neon_check_type (2, NS_NULL,
15415 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15416 logsize = neon_logbits (et.size);
15418 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15420 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15421 && et.size != 32, _(BAD_FPU));
15422 constraint (et.type == NT_invtype, _("bad type for scalar"));
15423 constraint (x >= 64 / et.size, _("scalar index out of range"));
15427 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15428 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15429 case 32: abcdebits = 0x00; break;
15433 abcdebits |= x << logsize;
15434 inst.instruction = 0xe100b10;
15435 do_vfp_cond_or_thumb ();
15436 inst.instruction |= LOW4 (dn) << 16;
15437 inst.instruction |= HI1 (dn) << 7;
15438 inst.instruction |= inst.operands[0].reg << 12;
15439 inst.instruction |= (abcdebits & 3) << 5;
15440 inst.instruction |= (abcdebits >> 2) << 21;
15444 case NS_RRD: /* case 7 (fmrrd). */
15445 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15448 inst.instruction = 0xc500b10;
15449 do_vfp_cond_or_thumb ();
15450 inst.instruction |= inst.operands[0].reg << 12;
15451 inst.instruction |= inst.operands[1].reg << 16;
15452 inst.instruction |= LOW4 (inst.operands[2].reg);
15453 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15456 case NS_FF: /* case 8 (fcpys). */
15457 do_vfp_nsyn_opcode ("fcpys");
15460 case NS_FI: /* case 10 (fconsts). */
15461 ldconst = "fconsts";
15463 if (is_quarter_float (inst.operands[1].imm))
15465 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15466 do_vfp_nsyn_opcode (ldconst);
15469 first_error (_("immediate out of range"));
15472 case NS_RF: /* case 12 (fmrs). */
15473 do_vfp_nsyn_opcode ("fmrs");
15476 case NS_FR: /* case 13 (fmsr). */
15477 do_vfp_nsyn_opcode ("fmsr");
15480 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15481 (one of which is a list), but we have parsed four. Do some fiddling to
15482 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15484 case NS_RRFF: /* case 14 (fmrrs). */
15485 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15486 _("VFP registers must be adjacent"));
15487 inst.operands[2].imm = 2;
15488 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15489 do_vfp_nsyn_opcode ("fmrrs");
15492 case NS_FFRR: /* case 15 (fmsrr). */
15493 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15494 _("VFP registers must be adjacent"));
15495 inst.operands[1] = inst.operands[2];
15496 inst.operands[2] = inst.operands[3];
15497 inst.operands[0].imm = 2;
15498 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15499 do_vfp_nsyn_opcode ("fmsrr");
15503 /* neon_select_shape has determined that the instruction
15504 shape is wrong and has already set the error message. */
15513 do_neon_rshift_round_imm (void)
15515 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15516 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15517 int imm = inst.operands[2].imm;
15519 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15522 inst.operands[2].present = 0;
15527 constraint (imm < 1 || (unsigned)imm > et.size,
15528 _("immediate out of range for shift"));
15529 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15534 do_neon_movl (void)
15536 struct neon_type_el et = neon_check_type (2, NS_QD,
15537 N_EQK | N_DBL, N_SU_32 | N_KEY);
15538 unsigned sizebits = et.size >> 3;
15539 inst.instruction |= sizebits << 19;
15540 neon_two_same (0, et.type == NT_unsigned, -1);
15546 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15547 struct neon_type_el et = neon_check_type (2, rs,
15548 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15549 NEON_ENCODE (INTEGER, inst);
15550 neon_two_same (neon_quad (rs), 1, et.size);
15554 do_neon_zip_uzp (void)
15556 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15557 struct neon_type_el et = neon_check_type (2, rs,
15558 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15559 if (rs == NS_DD && et.size == 32)
15561 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15562 inst.instruction = N_MNEM_vtrn;
15566 neon_two_same (neon_quad (rs), 1, et.size);
15570 do_neon_sat_abs_neg (void)
15572 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15573 struct neon_type_el et = neon_check_type (2, rs,
15574 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15575 neon_two_same (neon_quad (rs), 1, et.size);
15579 do_neon_pair_long (void)
15581 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15582 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15583 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15584 inst.instruction |= (et.type == NT_unsigned) << 7;
15585 neon_two_same (neon_quad (rs), 1, et.size);
15589 do_neon_recip_est (void)
15591 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15592 struct neon_type_el et = neon_check_type (2, rs,
15593 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15594 inst.instruction |= (et.type == NT_float) << 8;
15595 neon_two_same (neon_quad (rs), 1, et.size);
15601 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15602 struct neon_type_el et = neon_check_type (2, rs,
15603 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15604 neon_two_same (neon_quad (rs), 1, et.size);
15610 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15611 struct neon_type_el et = neon_check_type (2, rs,
15612 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15613 neon_two_same (neon_quad (rs), 1, et.size);
15619 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15620 struct neon_type_el et = neon_check_type (2, rs,
15621 N_EQK | N_INT, N_8 | N_KEY);
15622 neon_two_same (neon_quad (rs), 1, et.size);
15628 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15629 neon_two_same (neon_quad (rs), 1, -1);
15633 do_neon_tbl_tbx (void)
15635 unsigned listlenbits;
15636 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15638 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15640 first_error (_("bad list length for table lookup"));
15644 listlenbits = inst.operands[1].imm - 1;
15645 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15646 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15647 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15648 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15649 inst.instruction |= LOW4 (inst.operands[2].reg);
15650 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15651 inst.instruction |= listlenbits << 8;
15653 neon_dp_fixup (&inst);
15657 do_neon_ldm_stm (void)
15659 /* P, U and L bits are part of bitmask. */
15660 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15661 unsigned offsetbits = inst.operands[1].imm * 2;
15663 if (inst.operands[1].issingle)
15665 do_vfp_nsyn_ldm_stm (is_dbmode);
15669 constraint (is_dbmode && !inst.operands[0].writeback,
15670 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15672 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15673 _("register list must contain at least 1 and at most 16 "
15676 inst.instruction |= inst.operands[0].reg << 16;
15677 inst.instruction |= inst.operands[0].writeback << 21;
15678 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15679 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15681 inst.instruction |= offsetbits;
15683 do_vfp_cond_or_thumb ();
15687 do_neon_ldr_str (void)
15689 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15691 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15692 And is UNPREDICTABLE in thumb mode. */
15694 && inst.operands[1].reg == REG_PC
15695 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
15698 inst.error = _("Use of PC here is UNPREDICTABLE");
15699 else if (warn_on_deprecated)
15700 as_warn (_("Use of PC here is deprecated"));
15703 if (inst.operands[0].issingle)
15706 do_vfp_nsyn_opcode ("flds");
15708 do_vfp_nsyn_opcode ("fsts");
15713 do_vfp_nsyn_opcode ("fldd");
15715 do_vfp_nsyn_opcode ("fstd");
15719 /* "interleave" version also handles non-interleaving register VLD1/VST1
15723 do_neon_ld_st_interleave (void)
15725 struct neon_type_el et = neon_check_type (1, NS_NULL,
15726 N_8 | N_16 | N_32 | N_64);
15727 unsigned alignbits = 0;
15729 /* The bits in this table go:
15730 0: register stride of one (0) or two (1)
15731 1,2: register list length, minus one (1, 2, 3, 4).
15732 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15733 We use -1 for invalid entries. */
15734 const int typetable[] =
15736 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15737 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15738 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15739 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15743 if (et.type == NT_invtype)
15746 if (inst.operands[1].immisalign)
15747 switch (inst.operands[1].imm >> 8)
15749 case 64: alignbits = 1; break;
15751 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15752 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15753 goto bad_alignment;
15757 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15758 goto bad_alignment;
15763 first_error (_("bad alignment"));
15767 inst.instruction |= alignbits << 4;
15768 inst.instruction |= neon_logbits (et.size) << 6;
15770 /* Bits [4:6] of the immediate in a list specifier encode register stride
15771 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15772 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15773 up the right value for "type" in a table based on this value and the given
15774 list style, then stick it back. */
15775 idx = ((inst.operands[0].imm >> 4) & 7)
15776 | (((inst.instruction >> 8) & 3) << 3);
15778 typebits = typetable[idx];
15780 constraint (typebits == -1, _("bad list type for instruction"));
15782 inst.instruction &= ~0xf00;
15783 inst.instruction |= typebits << 8;
15786 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15787 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15788 otherwise. The variable arguments are a list of pairs of legal (size, align)
15789 values, terminated with -1. */
15792 neon_alignment_bit (int size, int align, int *do_align, ...)
15795 int result = FAIL, thissize, thisalign;
15797 if (!inst.operands[1].immisalign)
15803 va_start (ap, do_align);
15807 thissize = va_arg (ap, int);
15808 if (thissize == -1)
15810 thisalign = va_arg (ap, int);
15812 if (size == thissize && align == thisalign)
15815 while (result != SUCCESS);
15819 if (result == SUCCESS)
15822 first_error (_("unsupported alignment for instruction"));
15828 do_neon_ld_st_lane (void)
15830 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15831 int align_good, do_align = 0;
15832 int logsize = neon_logbits (et.size);
15833 int align = inst.operands[1].imm >> 8;
15834 int n = (inst.instruction >> 8) & 3;
15835 int max_el = 64 / et.size;
15837 if (et.type == NT_invtype)
15840 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15841 _("bad list length"));
15842 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15843 _("scalar index out of range"));
15844 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15846 _("stride of 2 unavailable when element size is 8"));
15850 case 0: /* VLD1 / VST1. */
15851 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15853 if (align_good == FAIL)
15857 unsigned alignbits = 0;
15860 case 16: alignbits = 0x1; break;
15861 case 32: alignbits = 0x3; break;
15864 inst.instruction |= alignbits << 4;
15868 case 1: /* VLD2 / VST2. */
15869 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15871 if (align_good == FAIL)
15874 inst.instruction |= 1 << 4;
15877 case 2: /* VLD3 / VST3. */
15878 constraint (inst.operands[1].immisalign,
15879 _("can't use alignment with this instruction"));
15882 case 3: /* VLD4 / VST4. */
15883 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15884 16, 64, 32, 64, 32, 128, -1);
15885 if (align_good == FAIL)
15889 unsigned alignbits = 0;
15892 case 8: alignbits = 0x1; break;
15893 case 16: alignbits = 0x1; break;
15894 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15897 inst.instruction |= alignbits << 4;
15904 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15905 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15906 inst.instruction |= 1 << (4 + logsize);
15908 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15909 inst.instruction |= logsize << 10;
15912 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15915 do_neon_ld_dup (void)
15917 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15918 int align_good, do_align = 0;
15920 if (et.type == NT_invtype)
15923 switch ((inst.instruction >> 8) & 3)
15925 case 0: /* VLD1. */
15926 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15927 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15928 &do_align, 16, 16, 32, 32, -1);
15929 if (align_good == FAIL)
15931 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15934 case 2: inst.instruction |= 1 << 5; break;
15935 default: first_error (_("bad list length")); return;
15937 inst.instruction |= neon_logbits (et.size) << 6;
15940 case 1: /* VLD2. */
15941 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15942 &do_align, 8, 16, 16, 32, 32, 64, -1);
15943 if (align_good == FAIL)
15945 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15946 _("bad list length"));
15947 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15948 inst.instruction |= 1 << 5;
15949 inst.instruction |= neon_logbits (et.size) << 6;
15952 case 2: /* VLD3. */
15953 constraint (inst.operands[1].immisalign,
15954 _("can't use alignment with this instruction"));
15955 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15956 _("bad list length"));
15957 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15958 inst.instruction |= 1 << 5;
15959 inst.instruction |= neon_logbits (et.size) << 6;
15962 case 3: /* VLD4. */
15964 int align = inst.operands[1].imm >> 8;
15965 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15966 16, 64, 32, 64, 32, 128, -1);
15967 if (align_good == FAIL)
15969 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15970 _("bad list length"));
15971 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15972 inst.instruction |= 1 << 5;
15973 if (et.size == 32 && align == 128)
15974 inst.instruction |= 0x3 << 6;
15976 inst.instruction |= neon_logbits (et.size) << 6;
15983 inst.instruction |= do_align << 4;
15986 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15987 apart from bits [11:4]. */
15990 do_neon_ldx_stx (void)
15992 if (inst.operands[1].isreg)
15993 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15995 switch (NEON_LANE (inst.operands[0].imm))
15997 case NEON_INTERLEAVE_LANES:
15998 NEON_ENCODE (INTERLV, inst);
15999 do_neon_ld_st_interleave ();
16002 case NEON_ALL_LANES:
16003 NEON_ENCODE (DUP, inst);
16004 if (inst.instruction == N_INV)
16006 first_error ("only loads support such operands");
16013 NEON_ENCODE (LANE, inst);
16014 do_neon_ld_st_lane ();
16017 /* L bit comes from bit mask. */
16018 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16019 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16020 inst.instruction |= inst.operands[1].reg << 16;
16022 if (inst.operands[1].postind)
16024 int postreg = inst.operands[1].imm & 0xf;
16025 constraint (!inst.operands[1].immisreg,
16026 _("post-index must be a register"));
16027 constraint (postreg == 0xd || postreg == 0xf,
16028 _("bad register for post-index"));
16029 inst.instruction |= postreg;
16031 else if (inst.operands[1].writeback)
16033 inst.instruction |= 0xd;
16036 inst.instruction |= 0xf;
16039 inst.instruction |= 0xf9000000;
16041 inst.instruction |= 0xf4000000;
16046 do_vfp_nsyn_fpv8 (enum neon_shape rs)
16048 NEON_ENCODE (FPV8, inst);
16051 do_vfp_sp_dyadic ();
16053 do_vfp_dp_rd_rn_rm ();
16056 inst.instruction |= 0x100;
16058 inst.instruction |= 0xf0000000;
16064 set_it_insn_type (OUTSIDE_IT_INSN);
16066 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16067 first_error (_("invalid instruction shape"));
16073 set_it_insn_type (OUTSIDE_IT_INSN);
16075 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16078 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16081 neon_dyadic_misc (NT_untyped, N_F32, 0);
16085 do_vrint_1 (enum neon_cvt_mode mode)
16087 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16088 struct neon_type_el et;
16093 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16094 if (et.type != NT_invtype)
16096 /* VFP encodings. */
16097 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16098 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16099 set_it_insn_type (OUTSIDE_IT_INSN);
16101 NEON_ENCODE (FPV8, inst);
16103 do_vfp_sp_monadic ();
16105 do_vfp_dp_rd_rm ();
16109 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16110 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16111 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16112 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16113 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16114 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16115 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16119 inst.instruction |= (rs == NS_DD) << 8;
16120 do_vfp_cond_or_thumb ();
16124 /* Neon encodings (or something broken...). */
16126 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16128 if (et.type == NT_invtype)
16131 set_it_insn_type (OUTSIDE_IT_INSN);
16132 NEON_ENCODE (FLOAT, inst);
16134 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16137 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16138 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16139 inst.instruction |= LOW4 (inst.operands[1].reg);
16140 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16141 inst.instruction |= neon_quad (rs) << 6;
16144 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16145 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16146 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16147 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16148 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16149 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16150 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16155 inst.instruction |= 0xfc000000;
16157 inst.instruction |= 0xf0000000;
16164 do_vrint_1 (neon_cvt_mode_x);
16170 do_vrint_1 (neon_cvt_mode_z);
16176 do_vrint_1 (neon_cvt_mode_r);
16182 do_vrint_1 (neon_cvt_mode_a);
16188 do_vrint_1 (neon_cvt_mode_n);
16194 do_vrint_1 (neon_cvt_mode_p);
16200 do_vrint_1 (neon_cvt_mode_m);
16203 /* Crypto v1 instructions. */
16205 do_crypto_2op_1 (unsigned elttype, int op)
16207 set_it_insn_type (OUTSIDE_IT_INSN);
16209 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16215 NEON_ENCODE (INTEGER, inst);
16216 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16217 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16218 inst.instruction |= LOW4 (inst.operands[1].reg);
16219 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16221 inst.instruction |= op << 6;
16224 inst.instruction |= 0xfc000000;
16226 inst.instruction |= 0xf0000000;
16230 do_crypto_3op_1 (int u, int op)
16232 set_it_insn_type (OUTSIDE_IT_INSN);
16234 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16235 N_32 | N_UNT | N_KEY).type == NT_invtype)
16240 NEON_ENCODE (INTEGER, inst);
16241 neon_three_same (1, u, 8 << op);
16247 do_crypto_2op_1 (N_8, 0);
16253 do_crypto_2op_1 (N_8, 1);
16259 do_crypto_2op_1 (N_8, 2);
16265 do_crypto_2op_1 (N_8, 3);
16271 do_crypto_3op_1 (0, 0);
16277 do_crypto_3op_1 (0, 1);
16283 do_crypto_3op_1 (0, 2);
16289 do_crypto_3op_1 (0, 3);
16295 do_crypto_3op_1 (1, 0);
16301 do_crypto_3op_1 (1, 1);
16305 do_sha256su1 (void)
16307 do_crypto_3op_1 (1, 2);
16313 do_crypto_2op_1 (N_32, -1);
16319 do_crypto_2op_1 (N_32, 0);
16323 do_sha256su0 (void)
16325 do_crypto_2op_1 (N_32, 1);
16329 do_crc32_1 (unsigned int poly, unsigned int sz)
16331 unsigned int Rd = inst.operands[0].reg;
16332 unsigned int Rn = inst.operands[1].reg;
16333 unsigned int Rm = inst.operands[2].reg;
16335 set_it_insn_type (OUTSIDE_IT_INSN);
16336 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
16337 inst.instruction |= LOW4 (Rn) << 16;
16338 inst.instruction |= LOW4 (Rm);
16339 inst.instruction |= sz << (thumb_mode ? 4 : 21);
16340 inst.instruction |= poly << (thumb_mode ? 20 : 9);
16342 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
16343 as_warn (UNPRED_REG ("r15"));
16344 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
16345 as_warn (UNPRED_REG ("r13"));
16385 /* Overall per-instruction processing. */
16387 /* We need to be able to fix up arbitrary expressions in some statements.
16388 This is so that we can handle symbols that are an arbitrary distance from
16389 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16390 which returns part of an address in a form which will be valid for
16391 a data instruction. We do this by pushing the expression into a symbol
16392 in the expr_section, and creating a fix for that. */
16395 fix_new_arm (fragS * frag,
16409 /* Create an absolute valued symbol, so we have something to
16410 refer to in the object file. Unfortunately for us, gas's
16411 generic expression parsing will already have folded out
16412 any use of .set foo/.type foo %function that may have
16413 been used to set type information of the target location,
16414 that's being specified symbolically. We have to presume
16415 the user knows what they are doing. */
16419 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16421 symbol = symbol_find_or_make (name);
16422 S_SET_SEGMENT (symbol, absolute_section);
16423 symbol_set_frag (symbol, &zero_address_frag);
16424 S_SET_VALUE (symbol, exp->X_add_number);
16425 exp->X_op = O_symbol;
16426 exp->X_add_symbol = symbol;
16427 exp->X_add_number = 0;
16433 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
16434 (enum bfd_reloc_code_real) reloc);
16438 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
16439 pc_rel, (enum bfd_reloc_code_real) reloc);
16443 /* Mark whether the fix is to a THUMB instruction, or an ARM
16445 new_fix->tc_fix_data = thumb_mode;
16448 /* Create a frg for an instruction requiring relaxation. */
16450 output_relax_insn (void)
16456 /* The size of the instruction is unknown, so tie the debug info to the
16457 start of the instruction. */
16458 dwarf2_emit_insn (0);
16460 switch (inst.reloc.exp.X_op)
16463 sym = inst.reloc.exp.X_add_symbol;
16464 offset = inst.reloc.exp.X_add_number;
16468 offset = inst.reloc.exp.X_add_number;
16471 sym = make_expr_symbol (&inst.reloc.exp);
16475 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16476 inst.relax, sym, offset, NULL/*offset, opcode*/);
16477 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
16480 /* Write a 32-bit thumb instruction to buf. */
16482 put_thumb32_insn (char * buf, unsigned long insn)
16484 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16485 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16489 output_inst (const char * str)
16495 as_bad ("%s -- `%s'", inst.error, str);
16500 output_relax_insn ();
16503 if (inst.size == 0)
16506 to = frag_more (inst.size);
16507 /* PR 9814: Record the thumb mode into the current frag so that we know
16508 what type of NOP padding to use, if necessary. We override any previous
16509 setting so that if the mode has changed then the NOPS that we use will
16510 match the encoding of the last instruction in the frag. */
16511 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
16513 if (thumb_mode && (inst.size > THUMB_SIZE))
16515 gas_assert (inst.size == (2 * THUMB_SIZE));
16516 put_thumb32_insn (to, inst.instruction);
16518 else if (inst.size > INSN_SIZE)
16520 gas_assert (inst.size == (2 * INSN_SIZE));
16521 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16522 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
16525 md_number_to_chars (to, inst.instruction, inst.size);
16527 if (inst.reloc.type != BFD_RELOC_UNUSED)
16528 fix_new_arm (frag_now, to - frag_now->fr_literal,
16529 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16532 dwarf2_emit_insn (inst.size);
16536 output_it_inst (int cond, int mask, char * to)
16538 unsigned long instruction = 0xbf00;
16541 instruction |= mask;
16542 instruction |= cond << 4;
16546 to = frag_more (2);
16548 dwarf2_emit_insn (2);
16552 md_number_to_chars (to, instruction, 2);
16557 /* Tag values used in struct asm_opcode's tag field. */
16560 OT_unconditional, /* Instruction cannot be conditionalized.
16561 The ARM condition field is still 0xE. */
16562 OT_unconditionalF, /* Instruction cannot be conditionalized
16563 and carries 0xF in its ARM condition field. */
16564 OT_csuffix, /* Instruction takes a conditional suffix. */
16565 OT_csuffixF, /* Some forms of the instruction take a conditional
16566 suffix, others place 0xF where the condition field
16568 OT_cinfix3, /* Instruction takes a conditional infix,
16569 beginning at character index 3. (In
16570 unified mode, it becomes a suffix.) */
16571 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16572 tsts, cmps, cmns, and teqs. */
16573 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16574 character index 3, even in unified mode. Used for
16575 legacy instructions where suffix and infix forms
16576 may be ambiguous. */
16577 OT_csuf_or_in3, /* Instruction takes either a conditional
16578 suffix or an infix at character index 3. */
16579 OT_odd_infix_unc, /* This is the unconditional variant of an
16580 instruction that takes a conditional infix
16581 at an unusual position. In unified mode,
16582 this variant will accept a suffix. */
16583 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16584 are the conditional variants of instructions that
16585 take conditional infixes in unusual positions.
16586 The infix appears at character index
16587 (tag - OT_odd_infix_0). These are not accepted
16588 in unified mode. */
16591 /* Subroutine of md_assemble, responsible for looking up the primary
16592 opcode from the mnemonic the user wrote. STR points to the
16593 beginning of the mnemonic.
16595 This is not simply a hash table lookup, because of conditional
16596 variants. Most instructions have conditional variants, which are
16597 expressed with a _conditional affix_ to the mnemonic. If we were
16598 to encode each conditional variant as a literal string in the opcode
16599 table, it would have approximately 20,000 entries.
16601 Most mnemonics take this affix as a suffix, and in unified syntax,
16602 'most' is upgraded to 'all'. However, in the divided syntax, some
16603 instructions take the affix as an infix, notably the s-variants of
16604 the arithmetic instructions. Of those instructions, all but six
16605 have the infix appear after the third character of the mnemonic.
16607 Accordingly, the algorithm for looking up primary opcodes given
16610 1. Look up the identifier in the opcode table.
16611 If we find a match, go to step U.
16613 2. Look up the last two characters of the identifier in the
16614 conditions table. If we find a match, look up the first N-2
16615 characters of the identifier in the opcode table. If we
16616 find a match, go to step CE.
16618 3. Look up the fourth and fifth characters of the identifier in
16619 the conditions table. If we find a match, extract those
16620 characters from the identifier, and look up the remaining
16621 characters in the opcode table. If we find a match, go
16626 U. Examine the tag field of the opcode structure, in case this is
16627 one of the six instructions with its conditional infix in an
16628 unusual place. If it is, the tag tells us where to find the
16629 infix; look it up in the conditions table and set inst.cond
16630 accordingly. Otherwise, this is an unconditional instruction.
16631 Again set inst.cond accordingly. Return the opcode structure.
16633 CE. Examine the tag field to make sure this is an instruction that
16634 should receive a conditional suffix. If it is not, fail.
16635 Otherwise, set inst.cond from the suffix we already looked up,
16636 and return the opcode structure.
16638 CM. Examine the tag field to make sure this is an instruction that
16639 should receive a conditional infix after the third character.
16640 If it is not, fail. Otherwise, undo the edits to the current
16641 line of input and proceed as for case CE. */
16643 static const struct asm_opcode *
16644 opcode_lookup (char **str)
16648 const struct asm_opcode *opcode;
16649 const struct asm_cond *cond;
16652 /* Scan up to the end of the mnemonic, which must end in white space,
16653 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16654 for (base = end = *str; *end != '\0'; end++)
16655 if (*end == ' ' || *end == '.')
16661 /* Handle a possible width suffix and/or Neon type suffix. */
16666 /* The .w and .n suffixes are only valid if the unified syntax is in
16668 if (unified_syntax && end[1] == 'w')
16670 else if (unified_syntax && end[1] == 'n')
16675 inst.vectype.elems = 0;
16677 *str = end + offset;
16679 if (end[offset] == '.')
16681 /* See if we have a Neon type suffix (possible in either unified or
16682 non-unified ARM syntax mode). */
16683 if (parse_neon_type (&inst.vectype, str) == FAIL)
16686 else if (end[offset] != '\0' && end[offset] != ' ')
16692 /* Look for unaffixed or special-case affixed mnemonic. */
16693 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16698 if (opcode->tag < OT_odd_infix_0)
16700 inst.cond = COND_ALWAYS;
16704 if (warn_on_deprecated && unified_syntax)
16705 as_warn (_("conditional infixes are deprecated in unified syntax"));
16706 affix = base + (opcode->tag - OT_odd_infix_0);
16707 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16710 inst.cond = cond->value;
16714 /* Cannot have a conditional suffix on a mnemonic of less than two
16716 if (end - base < 3)
16719 /* Look for suffixed mnemonic. */
16721 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16722 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16724 if (opcode && cond)
16727 switch (opcode->tag)
16729 case OT_cinfix3_legacy:
16730 /* Ignore conditional suffixes matched on infix only mnemonics. */
16734 case OT_cinfix3_deprecated:
16735 case OT_odd_infix_unc:
16736 if (!unified_syntax)
16738 /* else fall through */
16742 case OT_csuf_or_in3:
16743 inst.cond = cond->value;
16746 case OT_unconditional:
16747 case OT_unconditionalF:
16749 inst.cond = cond->value;
16752 /* Delayed diagnostic. */
16753 inst.error = BAD_COND;
16754 inst.cond = COND_ALWAYS;
16763 /* Cannot have a usual-position infix on a mnemonic of less than
16764 six characters (five would be a suffix). */
16765 if (end - base < 6)
16768 /* Look for infixed mnemonic in the usual position. */
16770 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16774 memcpy (save, affix, 2);
16775 memmove (affix, affix + 2, (end - affix) - 2);
16776 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16778 memmove (affix + 2, affix, (end - affix) - 2);
16779 memcpy (affix, save, 2);
16782 && (opcode->tag == OT_cinfix3
16783 || opcode->tag == OT_cinfix3_deprecated
16784 || opcode->tag == OT_csuf_or_in3
16785 || opcode->tag == OT_cinfix3_legacy))
16788 if (warn_on_deprecated && unified_syntax
16789 && (opcode->tag == OT_cinfix3
16790 || opcode->tag == OT_cinfix3_deprecated))
16791 as_warn (_("conditional infixes are deprecated in unified syntax"));
16793 inst.cond = cond->value;
16800 /* This function generates an initial IT instruction, leaving its block
16801 virtually open for the new instructions. Eventually,
16802 the mask will be updated by now_it_add_mask () each time
16803 a new instruction needs to be included in the IT block.
16804 Finally, the block is closed with close_automatic_it_block ().
16805 The block closure can be requested either from md_assemble (),
16806 a tencode (), or due to a label hook. */
16809 new_automatic_it_block (int cond)
16811 now_it.state = AUTOMATIC_IT_BLOCK;
16812 now_it.mask = 0x18;
16814 now_it.block_length = 1;
16815 mapping_state (MAP_THUMB);
16816 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16817 now_it.warn_deprecated = FALSE;
16818 now_it.insn_cond = TRUE;
16821 /* Close an automatic IT block.
16822 See comments in new_automatic_it_block (). */
16825 close_automatic_it_block (void)
16827 now_it.mask = 0x10;
16828 now_it.block_length = 0;
16831 /* Update the mask of the current automatically-generated IT
16832 instruction. See comments in new_automatic_it_block (). */
16835 now_it_add_mask (int cond)
16837 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16838 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16839 | ((bitvalue) << (nbit)))
16840 const int resulting_bit = (cond & 1);
16842 now_it.mask &= 0xf;
16843 now_it.mask = SET_BIT_VALUE (now_it.mask,
16845 (5 - now_it.block_length));
16846 now_it.mask = SET_BIT_VALUE (now_it.mask,
16848 ((5 - now_it.block_length) - 1) );
16849 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16852 #undef SET_BIT_VALUE
16855 /* The IT blocks handling machinery is accessed through the these functions:
16856 it_fsm_pre_encode () from md_assemble ()
16857 set_it_insn_type () optional, from the tencode functions
16858 set_it_insn_type_last () ditto
16859 in_it_block () ditto
16860 it_fsm_post_encode () from md_assemble ()
16861 force_automatic_it_block_close () from label habdling functions
16864 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16865 initializing the IT insn type with a generic initial value depending
16866 on the inst.condition.
16867 2) During the tencode function, two things may happen:
16868 a) The tencode function overrides the IT insn type by
16869 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16870 b) The tencode function queries the IT block state by
16871 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16873 Both set_it_insn_type and in_it_block run the internal FSM state
16874 handling function (handle_it_state), because: a) setting the IT insn
16875 type may incur in an invalid state (exiting the function),
16876 and b) querying the state requires the FSM to be updated.
16877 Specifically we want to avoid creating an IT block for conditional
16878 branches, so it_fsm_pre_encode is actually a guess and we can't
16879 determine whether an IT block is required until the tencode () routine
16880 has decided what type of instruction this actually it.
16881 Because of this, if set_it_insn_type and in_it_block have to be used,
16882 set_it_insn_type has to be called first.
16884 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16885 determines the insn IT type depending on the inst.cond code.
16886 When a tencode () routine encodes an instruction that can be
16887 either outside an IT block, or, in the case of being inside, has to be
16888 the last one, set_it_insn_type_last () will determine the proper
16889 IT instruction type based on the inst.cond code. Otherwise,
16890 set_it_insn_type can be called for overriding that logic or
16891 for covering other cases.
16893 Calling handle_it_state () may not transition the IT block state to
16894 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16895 still queried. Instead, if the FSM determines that the state should
16896 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16897 after the tencode () function: that's what it_fsm_post_encode () does.
16899 Since in_it_block () calls the state handling function to get an
16900 updated state, an error may occur (due to invalid insns combination).
16901 In that case, inst.error is set.
16902 Therefore, inst.error has to be checked after the execution of
16903 the tencode () routine.
16905 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16906 any pending state change (if any) that didn't take place in
16907 handle_it_state () as explained above. */
16910 it_fsm_pre_encode (void)
16912 if (inst.cond != COND_ALWAYS)
16913 inst.it_insn_type = INSIDE_IT_INSN;
16915 inst.it_insn_type = OUTSIDE_IT_INSN;
16917 now_it.state_handled = 0;
16920 /* IT state FSM handling function. */
16923 handle_it_state (void)
16925 now_it.state_handled = 1;
16926 now_it.insn_cond = FALSE;
16928 switch (now_it.state)
16930 case OUTSIDE_IT_BLOCK:
16931 switch (inst.it_insn_type)
16933 case OUTSIDE_IT_INSN:
16936 case INSIDE_IT_INSN:
16937 case INSIDE_IT_LAST_INSN:
16938 if (thumb_mode == 0)
16941 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16942 as_tsktsk (_("Warning: conditional outside an IT block"\
16947 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16948 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16950 /* Automatically generate the IT instruction. */
16951 new_automatic_it_block (inst.cond);
16952 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16953 close_automatic_it_block ();
16957 inst.error = BAD_OUT_IT;
16963 case IF_INSIDE_IT_LAST_INSN:
16964 case NEUTRAL_IT_INSN:
16968 now_it.state = MANUAL_IT_BLOCK;
16969 now_it.block_length = 0;
16974 case AUTOMATIC_IT_BLOCK:
16975 /* Three things may happen now:
16976 a) We should increment current it block size;
16977 b) We should close current it block (closing insn or 4 insns);
16978 c) We should close current it block and start a new one (due
16979 to incompatible conditions or
16980 4 insns-length block reached). */
16982 switch (inst.it_insn_type)
16984 case OUTSIDE_IT_INSN:
16985 /* The closure of the block shall happen immediatelly,
16986 so any in_it_block () call reports the block as closed. */
16987 force_automatic_it_block_close ();
16990 case INSIDE_IT_INSN:
16991 case INSIDE_IT_LAST_INSN:
16992 case IF_INSIDE_IT_LAST_INSN:
16993 now_it.block_length++;
16995 if (now_it.block_length > 4
16996 || !now_it_compatible (inst.cond))
16998 force_automatic_it_block_close ();
16999 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
17000 new_automatic_it_block (inst.cond);
17004 now_it.insn_cond = TRUE;
17005 now_it_add_mask (inst.cond);
17008 if (now_it.state == AUTOMATIC_IT_BLOCK
17009 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
17010 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
17011 close_automatic_it_block ();
17014 case NEUTRAL_IT_INSN:
17015 now_it.block_length++;
17016 now_it.insn_cond = TRUE;
17018 if (now_it.block_length > 4)
17019 force_automatic_it_block_close ();
17021 now_it_add_mask (now_it.cc & 1);
17025 close_automatic_it_block ();
17026 now_it.state = MANUAL_IT_BLOCK;
17031 case MANUAL_IT_BLOCK:
17033 /* Check conditional suffixes. */
17034 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
17037 now_it.mask &= 0x1f;
17038 is_last = (now_it.mask == 0x10);
17039 now_it.insn_cond = TRUE;
17041 switch (inst.it_insn_type)
17043 case OUTSIDE_IT_INSN:
17044 inst.error = BAD_NOT_IT;
17047 case INSIDE_IT_INSN:
17048 if (cond != inst.cond)
17050 inst.error = BAD_IT_COND;
17055 case INSIDE_IT_LAST_INSN:
17056 case IF_INSIDE_IT_LAST_INSN:
17057 if (cond != inst.cond)
17059 inst.error = BAD_IT_COND;
17064 inst.error = BAD_BRANCH;
17069 case NEUTRAL_IT_INSN:
17070 /* The BKPT instruction is unconditional even in an IT block. */
17074 inst.error = BAD_IT_IT;
17084 struct depr_insn_mask
17086 unsigned long pattern;
17087 unsigned long mask;
17088 const char* description;
17091 /* List of 16-bit instruction patterns deprecated in an IT block in
17093 static const struct depr_insn_mask depr_it_insns[] = {
17094 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17095 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17096 { 0xa000, 0xb800, N_("ADR") },
17097 { 0x4800, 0xf800, N_("Literal loads") },
17098 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17099 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17104 it_fsm_post_encode (void)
17108 if (!now_it.state_handled)
17109 handle_it_state ();
17111 if (now_it.insn_cond
17112 && !now_it.warn_deprecated
17113 && warn_on_deprecated
17114 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17116 if (inst.instruction >= 0x10000)
17118 as_warn (_("it blocks containing wide Thumb instructions are "
17119 "deprecated in ARMv8"));
17120 now_it.warn_deprecated = TRUE;
17124 const struct depr_insn_mask *p = depr_it_insns;
17126 while (p->mask != 0)
17128 if ((inst.instruction & p->mask) == p->pattern)
17130 as_warn (_("it blocks containing 16-bit Thumb intsructions "
17131 "of the following class are deprecated in ARMv8: "
17132 "%s"), p->description);
17133 now_it.warn_deprecated = TRUE;
17141 if (now_it.block_length > 1)
17143 as_warn (_("it blocks of more than one conditional instruction are "
17144 "deprecated in ARMv8"));
17145 now_it.warn_deprecated = TRUE;
17149 is_last = (now_it.mask == 0x10);
17152 now_it.state = OUTSIDE_IT_BLOCK;
17158 force_automatic_it_block_close (void)
17160 if (now_it.state == AUTOMATIC_IT_BLOCK)
17162 close_automatic_it_block ();
17163 now_it.state = OUTSIDE_IT_BLOCK;
17171 if (!now_it.state_handled)
17172 handle_it_state ();
17174 return now_it.state != OUTSIDE_IT_BLOCK;
17178 md_assemble (char *str)
17181 const struct asm_opcode * opcode;
17183 /* Align the previous label if needed. */
17184 if (last_label_seen != NULL)
17186 symbol_set_frag (last_label_seen, frag_now);
17187 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17188 S_SET_SEGMENT (last_label_seen, now_seg);
17191 memset (&inst, '\0', sizeof (inst));
17192 inst.reloc.type = BFD_RELOC_UNUSED;
17194 opcode = opcode_lookup (&p);
17197 /* It wasn't an instruction, but it might be a register alias of
17198 the form alias .req reg, or a Neon .dn/.qn directive. */
17199 if (! create_register_alias (str, p)
17200 && ! create_neon_reg_alias (str, p))
17201 as_bad (_("bad instruction `%s'"), str);
17206 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
17207 as_warn (_("s suffix on comparison instruction is deprecated"));
17209 /* The value which unconditional instructions should have in place of the
17210 condition field. */
17211 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17215 arm_feature_set variant;
17217 variant = cpu_variant;
17218 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17219 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17220 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
17221 /* Check that this instruction is supported for this CPU. */
17222 if (!opcode->tvariant
17223 || (thumb_mode == 1
17224 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
17226 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
17229 if (inst.cond != COND_ALWAYS && !unified_syntax
17230 && opcode->tencode != do_t_branch)
17232 as_bad (_("Thumb does not support conditional execution"));
17236 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
17238 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
17239 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17240 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17242 /* Two things are addressed here.
17243 1) Implicit require narrow instructions on Thumb-1.
17244 This avoids relaxation accidentally introducing Thumb-2
17246 2) Reject wide instructions in non Thumb-2 cores. */
17247 if (inst.size_req == 0)
17249 else if (inst.size_req == 4)
17251 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
17257 inst.instruction = opcode->tvalue;
17259 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
17261 /* Prepare the it_insn_type for those encodings that don't set
17263 it_fsm_pre_encode ();
17265 opcode->tencode ();
17267 it_fsm_post_encode ();
17270 if (!(inst.error || inst.relax))
17272 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
17273 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17274 if (inst.size_req && inst.size_req != inst.size)
17276 as_bad (_("cannot honor width suffix -- `%s'"), str);
17281 /* Something has gone badly wrong if we try to relax a fixed size
17283 gas_assert (inst.size_req == 0 || !inst.relax);
17285 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17286 *opcode->tvariant);
17287 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17288 set those bits when Thumb-2 32-bit instructions are seen. ie.
17289 anything other than bl/blx and v6-M instructions.
17290 This is overly pessimistic for relaxable instructions. */
17291 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
17293 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17294 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
17295 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17298 check_neon_suffixes;
17302 mapping_state (MAP_THUMB);
17305 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
17309 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17310 is_bx = (opcode->aencode == do_bx);
17312 /* Check that this instruction is supported for this CPU. */
17313 if (!(is_bx && fix_v4bx)
17314 && !(opcode->avariant &&
17315 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
17317 as_bad (_("selected processor does not support ARM mode `%s'"), str);
17322 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17326 inst.instruction = opcode->avalue;
17327 if (opcode->tag == OT_unconditionalF)
17328 inst.instruction |= 0xF << 28;
17330 inst.instruction |= inst.cond << 28;
17331 inst.size = INSN_SIZE;
17332 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
17334 it_fsm_pre_encode ();
17335 opcode->aencode ();
17336 it_fsm_post_encode ();
17338 /* Arm mode bx is marked as both v4T and v5 because it's still required
17339 on a hypothetical non-thumb v5 core. */
17341 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
17343 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17344 *opcode->avariant);
17346 check_neon_suffixes;
17350 mapping_state (MAP_ARM);
17355 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17363 check_it_blocks_finished (void)
17368 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17369 if (seg_info (sect)->tc_segment_info_data.current_it.state
17370 == MANUAL_IT_BLOCK)
17372 as_warn (_("section '%s' finished with an open IT block."),
17376 if (now_it.state == MANUAL_IT_BLOCK)
17377 as_warn (_("file finished with an open IT block."));
17381 /* Various frobbings of labels and their addresses. */
17384 arm_start_line_hook (void)
17386 last_label_seen = NULL;
17390 arm_frob_label (symbolS * sym)
17392 last_label_seen = sym;
17394 ARM_SET_THUMB (sym, thumb_mode);
17396 #if defined OBJ_COFF || defined OBJ_ELF
17397 ARM_SET_INTERWORK (sym, support_interwork);
17400 force_automatic_it_block_close ();
17402 /* Note - do not allow local symbols (.Lxxx) to be labelled
17403 as Thumb functions. This is because these labels, whilst
17404 they exist inside Thumb code, are not the entry points for
17405 possible ARM->Thumb calls. Also, these labels can be used
17406 as part of a computed goto or switch statement. eg gcc
17407 can generate code that looks like this:
17409 ldr r2, [pc, .Laaa]
17419 The first instruction loads the address of the jump table.
17420 The second instruction converts a table index into a byte offset.
17421 The third instruction gets the jump address out of the table.
17422 The fourth instruction performs the jump.
17424 If the address stored at .Laaa is that of a symbol which has the
17425 Thumb_Func bit set, then the linker will arrange for this address
17426 to have the bottom bit set, which in turn would mean that the
17427 address computation performed by the third instruction would end
17428 up with the bottom bit set. Since the ARM is capable of unaligned
17429 word loads, the instruction would then load the incorrect address
17430 out of the jump table, and chaos would ensue. */
17431 if (label_is_thumb_function_name
17432 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17433 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
17435 /* When the address of a Thumb function is taken the bottom
17436 bit of that address should be set. This will allow
17437 interworking between Arm and Thumb functions to work
17440 THUMB_SET_FUNC (sym, 1);
17442 label_is_thumb_function_name = FALSE;
17445 dwarf2_emit_label (sym);
17449 arm_data_in_code (void)
17451 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
17453 *input_line_pointer = '/';
17454 input_line_pointer += 5;
17455 *input_line_pointer = 0;
17463 arm_canonicalize_symbol_name (char * name)
17467 if (thumb_mode && (len = strlen (name)) > 5
17468 && streq (name + len - 5, "/data"))
17469 *(name + len - 5) = 0;
17474 /* Table of all register names defined by default. The user can
17475 define additional names with .req. Note that all register names
17476 should appear in both upper and lowercase variants. Some registers
17477 also have mixed-case names. */
17479 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17480 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17481 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17482 #define REGSET(p,t) \
17483 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17484 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17485 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17486 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17487 #define REGSETH(p,t) \
17488 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17489 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17490 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17491 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17492 #define REGSET2(p,t) \
17493 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17494 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17495 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17496 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17497 #define SPLRBANK(base,bank,t) \
17498 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17499 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17500 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17501 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17502 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17503 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17505 static const struct reg_entry reg_names[] =
17507 /* ARM integer registers. */
17508 REGSET(r, RN), REGSET(R, RN),
17510 /* ATPCS synonyms. */
17511 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17512 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17513 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
17515 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17516 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17517 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
17519 /* Well-known aliases. */
17520 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17521 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17523 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17524 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17526 /* Coprocessor numbers. */
17527 REGSET(p, CP), REGSET(P, CP),
17529 /* Coprocessor register numbers. The "cr" variants are for backward
17531 REGSET(c, CN), REGSET(C, CN),
17532 REGSET(cr, CN), REGSET(CR, CN),
17534 /* ARM banked registers. */
17535 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17536 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17537 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17538 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17539 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17540 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17541 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17543 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17544 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17545 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17546 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17547 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
17548 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
17549 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17550 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17552 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17553 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17554 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17555 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17556 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17557 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17558 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
17559 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
17560 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17562 /* FPA registers. */
17563 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17564 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17566 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17567 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17569 /* VFP SP registers. */
17570 REGSET(s,VFS), REGSET(S,VFS),
17571 REGSETH(s,VFS), REGSETH(S,VFS),
17573 /* VFP DP Registers. */
17574 REGSET(d,VFD), REGSET(D,VFD),
17575 /* Extra Neon DP registers. */
17576 REGSETH(d,VFD), REGSETH(D,VFD),
17578 /* Neon QP registers. */
17579 REGSET2(q,NQ), REGSET2(Q,NQ),
17581 /* VFP control registers. */
17582 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17583 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
17584 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17585 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17586 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17587 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
17589 /* Maverick DSP coprocessor registers. */
17590 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17591 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17593 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17594 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17595 REGDEF(dspsc,0,DSPSC),
17597 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17598 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17599 REGDEF(DSPSC,0,DSPSC),
17601 /* iWMMXt data registers - p0, c0-15. */
17602 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17604 /* iWMMXt control registers - p1, c0-3. */
17605 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17606 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17607 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17608 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17610 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17611 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17612 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17613 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17614 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17616 /* XScale accumulator registers. */
17617 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17623 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17624 within psr_required_here. */
17625 static const struct asm_psr psrs[] =
17627 /* Backward compatibility notation. Note that "all" is no longer
17628 truly all possible PSR bits. */
17629 {"all", PSR_c | PSR_f},
17633 /* Individual flags. */
17639 /* Combinations of flags. */
17640 {"fs", PSR_f | PSR_s},
17641 {"fx", PSR_f | PSR_x},
17642 {"fc", PSR_f | PSR_c},
17643 {"sf", PSR_s | PSR_f},
17644 {"sx", PSR_s | PSR_x},
17645 {"sc", PSR_s | PSR_c},
17646 {"xf", PSR_x | PSR_f},
17647 {"xs", PSR_x | PSR_s},
17648 {"xc", PSR_x | PSR_c},
17649 {"cf", PSR_c | PSR_f},
17650 {"cs", PSR_c | PSR_s},
17651 {"cx", PSR_c | PSR_x},
17652 {"fsx", PSR_f | PSR_s | PSR_x},
17653 {"fsc", PSR_f | PSR_s | PSR_c},
17654 {"fxs", PSR_f | PSR_x | PSR_s},
17655 {"fxc", PSR_f | PSR_x | PSR_c},
17656 {"fcs", PSR_f | PSR_c | PSR_s},
17657 {"fcx", PSR_f | PSR_c | PSR_x},
17658 {"sfx", PSR_s | PSR_f | PSR_x},
17659 {"sfc", PSR_s | PSR_f | PSR_c},
17660 {"sxf", PSR_s | PSR_x | PSR_f},
17661 {"sxc", PSR_s | PSR_x | PSR_c},
17662 {"scf", PSR_s | PSR_c | PSR_f},
17663 {"scx", PSR_s | PSR_c | PSR_x},
17664 {"xfs", PSR_x | PSR_f | PSR_s},
17665 {"xfc", PSR_x | PSR_f | PSR_c},
17666 {"xsf", PSR_x | PSR_s | PSR_f},
17667 {"xsc", PSR_x | PSR_s | PSR_c},
17668 {"xcf", PSR_x | PSR_c | PSR_f},
17669 {"xcs", PSR_x | PSR_c | PSR_s},
17670 {"cfs", PSR_c | PSR_f | PSR_s},
17671 {"cfx", PSR_c | PSR_f | PSR_x},
17672 {"csf", PSR_c | PSR_s | PSR_f},
17673 {"csx", PSR_c | PSR_s | PSR_x},
17674 {"cxf", PSR_c | PSR_x | PSR_f},
17675 {"cxs", PSR_c | PSR_x | PSR_s},
17676 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17677 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17678 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17679 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17680 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17681 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17682 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17683 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17684 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17685 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17686 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17687 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17688 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17689 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17690 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17691 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17692 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17693 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17694 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17695 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17696 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17697 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17698 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17699 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17702 /* Table of V7M psr names. */
17703 static const struct asm_psr v7m_psrs[] =
17705 {"apsr", 0 }, {"APSR", 0 },
17706 {"iapsr", 1 }, {"IAPSR", 1 },
17707 {"eapsr", 2 }, {"EAPSR", 2 },
17708 {"psr", 3 }, {"PSR", 3 },
17709 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17710 {"ipsr", 5 }, {"IPSR", 5 },
17711 {"epsr", 6 }, {"EPSR", 6 },
17712 {"iepsr", 7 }, {"IEPSR", 7 },
17713 {"msp", 8 }, {"MSP", 8 },
17714 {"psp", 9 }, {"PSP", 9 },
17715 {"primask", 16}, {"PRIMASK", 16},
17716 {"basepri", 17}, {"BASEPRI", 17},
17717 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17718 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17719 {"faultmask", 19}, {"FAULTMASK", 19},
17720 {"control", 20}, {"CONTROL", 20}
17723 /* Table of all shift-in-operand names. */
17724 static const struct asm_shift_name shift_names [] =
17726 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17727 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17728 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17729 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17730 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17731 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17734 /* Table of all explicit relocation names. */
17736 static struct reloc_entry reloc_names[] =
17738 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17739 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17740 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17741 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17742 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17743 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17744 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17745 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17746 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17747 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17748 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17749 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17750 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17751 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17752 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17753 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17754 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17755 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17759 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17760 static const struct asm_cond conds[] =
17764 {"cs", 0x2}, {"hs", 0x2},
17765 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17779 #define UL_BARRIER(L,U,CODE,FEAT) \
17780 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17781 { U, CODE, ARM_FEATURE (FEAT, 0) }
17783 static struct asm_barrier_opt barrier_opt_names[] =
17785 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17786 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17787 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17788 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17789 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17790 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17791 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17792 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17793 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17794 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17795 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17796 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17797 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17798 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17799 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17800 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
17805 /* Table of ARM-format instructions. */
17807 /* Macros for gluing together operand strings. N.B. In all cases
17808 other than OPS0, the trailing OP_stop comes from default
17809 zero-initialization of the unspecified elements of the array. */
17810 #define OPS0() { OP_stop, }
17811 #define OPS1(a) { OP_##a, }
17812 #define OPS2(a,b) { OP_##a,OP_##b, }
17813 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17814 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17815 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17816 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17818 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17819 This is useful when mixing operands for ARM and THUMB, i.e. using the
17820 MIX_ARM_THUMB_OPERANDS macro.
17821 In order to use these macros, prefix the number of operands with _
17823 #define OPS_1(a) { a, }
17824 #define OPS_2(a,b) { a,b, }
17825 #define OPS_3(a,b,c) { a,b,c, }
17826 #define OPS_4(a,b,c,d) { a,b,c,d, }
17827 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17828 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17830 /* These macros abstract out the exact format of the mnemonic table and
17831 save some repeated characters. */
17833 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17834 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17835 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17836 THUMB_VARIANT, do_##ae, do_##te }
17838 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17839 a T_MNEM_xyz enumerator. */
17840 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17841 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17842 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17843 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17845 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17846 infix after the third character. */
17847 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17848 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17849 THUMB_VARIANT, do_##ae, do_##te }
17850 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17851 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17852 THUMB_VARIANT, do_##ae, do_##te }
17853 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17854 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17855 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17856 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17857 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17858 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17859 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17860 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17862 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17863 field is still 0xE. Many of the Thumb variants can be executed
17864 conditionally, so this is checked separately. */
17865 #define TUE(mnem, op, top, nops, ops, ae, te) \
17866 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17867 THUMB_VARIANT, do_##ae, do_##te }
17869 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
17870 Used by mnemonics that have very minimal differences in the encoding for
17871 ARM and Thumb variants and can be handled in a common function. */
17872 #define TUEc(mnem, op, top, nops, ops, en) \
17873 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17874 THUMB_VARIANT, do_##en, do_##en }
17876 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17877 condition code field. */
17878 #define TUF(mnem, op, top, nops, ops, ae, te) \
17879 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17880 THUMB_VARIANT, do_##ae, do_##te }
17882 /* ARM-only variants of all the above. */
17883 #define CE(mnem, op, nops, ops, ae) \
17884 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17886 #define C3(mnem, op, nops, ops, ae) \
17887 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17889 /* Legacy mnemonics that always have conditional infix after the third
17891 #define CL(mnem, op, nops, ops, ae) \
17892 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17893 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17895 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17896 #define cCE(mnem, op, nops, ops, ae) \
17897 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17899 /* Legacy coprocessor instructions where conditional infix and conditional
17900 suffix are ambiguous. For consistency this includes all FPA instructions,
17901 not just the potentially ambiguous ones. */
17902 #define cCL(mnem, op, nops, ops, ae) \
17903 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17904 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17906 /* Coprocessor, takes either a suffix or a position-3 infix
17907 (for an FPA corner case). */
17908 #define C3E(mnem, op, nops, ops, ae) \
17909 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17910 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17912 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17913 { m1 #m2 m3, OPS##nops ops, \
17914 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17915 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17917 #define CM(m1, m2, op, nops, ops, ae) \
17918 xCM_ (m1, , m2, op, nops, ops, ae), \
17919 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17920 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17921 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17922 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17923 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17924 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17925 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17926 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17927 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17928 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17929 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17930 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17931 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17932 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17933 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17934 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17935 xCM_ (m1, le, m2, op, nops, ops, ae), \
17936 xCM_ (m1, al, m2, op, nops, ops, ae)
17938 #define UE(mnem, op, nops, ops, ae) \
17939 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17941 #define UF(mnem, op, nops, ops, ae) \
17942 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17944 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17945 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17946 use the same encoding function for each. */
17947 #define NUF(mnem, op, nops, ops, enc) \
17948 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17949 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17951 /* Neon data processing, version which indirects through neon_enc_tab for
17952 the various overloaded versions of opcodes. */
17953 #define nUF(mnem, op, nops, ops, enc) \
17954 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17955 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17957 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17959 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17960 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17961 THUMB_VARIANT, do_##enc, do_##enc }
17963 #define NCE(mnem, op, nops, ops, enc) \
17964 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17966 #define NCEF(mnem, op, nops, ops, enc) \
17967 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17969 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17970 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17971 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17972 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17974 #define nCE(mnem, op, nops, ops, enc) \
17975 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17977 #define nCEF(mnem, op, nops, ops, enc) \
17978 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17982 static const struct asm_opcode insns[] =
17984 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17985 #define THUMB_VARIANT &arm_ext_v4t
17986 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17987 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17988 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17989 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17990 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17991 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17992 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17993 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17994 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17995 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17996 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17997 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17998 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17999 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
18000 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
18001 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
18003 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18004 for setting PSR flag bits. They are obsolete in V6 and do not
18005 have Thumb equivalents. */
18006 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18007 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18008 CL("tstp", 110f000, 2, (RR, SH), cmp),
18009 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18010 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18011 CL("cmpp", 150f000, 2, (RR, SH), cmp),
18012 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18013 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18014 CL("cmnp", 170f000, 2, (RR, SH), cmp),
18016 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
18017 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
18018 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
18019 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
18021 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
18022 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18023 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
18025 OP_ADDRGLDR),ldst, t_ldst),
18026 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18028 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18029 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18030 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18031 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18032 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18033 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18035 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
18036 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
18037 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
18038 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
18041 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
18042 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
18043 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
18045 /* Thumb-compatibility pseudo ops. */
18046 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
18047 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
18048 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
18049 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
18050 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
18051 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
18052 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
18053 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
18054 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
18055 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
18056 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
18057 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
18059 /* These may simplify to neg. */
18060 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
18061 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
18063 #undef THUMB_VARIANT
18064 #define THUMB_VARIANT & arm_ext_v6
18066 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
18068 /* V1 instructions with no Thumb analogue prior to V6T2. */
18069 #undef THUMB_VARIANT
18070 #define THUMB_VARIANT & arm_ext_v6t2
18072 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18073 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18074 CL("teqp", 130f000, 2, (RR, SH), cmp),
18076 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18077 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18078 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18079 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18081 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18082 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18084 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18085 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18087 /* V1 instructions with no Thumb analogue at all. */
18088 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
18089 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18091 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18092 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18093 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18094 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18095 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18096 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18097 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18098 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18101 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18102 #undef THUMB_VARIANT
18103 #define THUMB_VARIANT & arm_ext_v4t
18105 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18106 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18108 #undef THUMB_VARIANT
18109 #define THUMB_VARIANT & arm_ext_v6t2
18111 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18112 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18114 /* Generic coprocessor instructions. */
18115 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18116 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18117 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18118 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18119 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18120 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18121 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
18124 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18126 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18127 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18130 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18131 #undef THUMB_VARIANT
18132 #define THUMB_VARIANT & arm_ext_msr
18134 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18135 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
18138 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18139 #undef THUMB_VARIANT
18140 #define THUMB_VARIANT & arm_ext_v6t2
18142 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18143 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18144 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18145 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18146 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18147 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18148 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18149 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18152 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18153 #undef THUMB_VARIANT
18154 #define THUMB_VARIANT & arm_ext_v4t
18156 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18157 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18158 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18159 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18160 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18161 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18164 #define ARM_VARIANT & arm_ext_v4t_5
18166 /* ARM Architecture 4T. */
18167 /* Note: bx (and blx) are required on V5, even if the processor does
18168 not support Thumb. */
18169 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
18172 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18173 #undef THUMB_VARIANT
18174 #define THUMB_VARIANT & arm_ext_v5t
18176 /* Note: blx has 2 variants; the .value coded here is for
18177 BLX(2). Only this variant has conditional execution. */
18178 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18179 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
18181 #undef THUMB_VARIANT
18182 #define THUMB_VARIANT & arm_ext_v6t2
18184 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18185 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18186 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18187 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18188 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18189 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18190 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18191 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18194 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18195 #undef THUMB_VARIANT
18196 #define THUMB_VARIANT &arm_ext_v5exp
18198 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18199 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18200 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18201 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18203 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18204 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18206 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18207 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18208 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18209 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18211 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18212 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18213 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18214 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18216 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18217 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18219 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18220 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18221 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18222 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18225 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18226 #undef THUMB_VARIANT
18227 #define THUMB_VARIANT &arm_ext_v6t2
18229 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
18230 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18232 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18233 ADDRGLDRS), ldrd, t_ldstd),
18235 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18236 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18239 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18241 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
18244 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18245 #undef THUMB_VARIANT
18246 #define THUMB_VARIANT & arm_ext_v6
18248 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18249 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18250 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18251 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18252 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18253 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18254 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18255 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18256 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18257 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
18259 #undef THUMB_VARIANT
18260 #define THUMB_VARIANT & arm_ext_v6t2
18262 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18263 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18265 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18266 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18268 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18269 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
18271 /* ARM V6 not included in V7M. */
18272 #undef THUMB_VARIANT
18273 #define THUMB_VARIANT & arm_ext_v6_notm
18274 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18275 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18276 UF(rfeib, 9900a00, 1, (RRw), rfe),
18277 UF(rfeda, 8100a00, 1, (RRw), rfe),
18278 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18279 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18280 UF(rfefa, 8100a00, 1, (RRw), rfe),
18281 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18282 UF(rfeed, 9900a00, 1, (RRw), rfe),
18283 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18284 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18285 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18286 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
18287 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
18288 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
18289 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
18290 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18291 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18293 /* ARM V6 not included in V7M (eg. integer SIMD). */
18294 #undef THUMB_VARIANT
18295 #define THUMB_VARIANT & arm_ext_v6_dsp
18296 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18297 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18298 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18299 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18300 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18301 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18302 /* Old name for QASX. */
18303 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18304 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18305 /* Old name for QSAX. */
18306 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18307 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18308 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18309 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18310 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18311 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18312 /* Old name for SASX. */
18313 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18314 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18315 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18316 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18317 /* Old name for SHASX. */
18318 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18319 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18320 /* Old name for SHSAX. */
18321 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18322 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18323 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18324 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18325 /* Old name for SSAX. */
18326 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18327 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18328 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18329 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18330 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18331 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18332 /* Old name for UASX. */
18333 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18334 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18335 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18336 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18337 /* Old name for UHASX. */
18338 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18339 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18340 /* Old name for UHSAX. */
18341 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18342 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18343 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18344 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18345 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18346 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18347 /* Old name for UQASX. */
18348 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18349 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18350 /* Old name for UQSAX. */
18351 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18352 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18353 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18354 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18355 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18356 /* Old name for USAX. */
18357 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18358 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18359 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18360 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18361 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18362 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18363 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18364 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18365 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18366 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18367 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18368 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18369 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18370 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18371 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18372 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18373 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18374 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18375 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18376 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18377 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18378 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18379 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18380 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18381 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18382 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18383 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18384 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18385 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18386 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18387 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18388 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18389 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18390 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
18393 #define ARM_VARIANT & arm_ext_v6k
18394 #undef THUMB_VARIANT
18395 #define THUMB_VARIANT & arm_ext_v6k
18397 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18398 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18399 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18400 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
18402 #undef THUMB_VARIANT
18403 #define THUMB_VARIANT & arm_ext_v6_notm
18404 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18406 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18407 RRnpcb), strexd, t_strexd),
18409 #undef THUMB_VARIANT
18410 #define THUMB_VARIANT & arm_ext_v6t2
18411 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18413 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18415 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18417 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18419 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
18422 #define ARM_VARIANT & arm_ext_sec
18423 #undef THUMB_VARIANT
18424 #define THUMB_VARIANT & arm_ext_sec
18426 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
18429 #define ARM_VARIANT & arm_ext_virt
18430 #undef THUMB_VARIANT
18431 #define THUMB_VARIANT & arm_ext_virt
18433 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18434 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18437 #define ARM_VARIANT & arm_ext_v6t2
18438 #undef THUMB_VARIANT
18439 #define THUMB_VARIANT & arm_ext_v6t2
18441 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18442 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18443 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18444 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18446 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18447 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18448 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18449 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
18451 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18452 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18453 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18454 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18456 /* Thumb-only instructions. */
18458 #define ARM_VARIANT NULL
18459 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18460 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
18462 /* ARM does not really have an IT instruction, so always allow it.
18463 The opcode is copied from Thumb in order to allow warnings in
18464 -mimplicit-it=[never | arm] modes. */
18466 #define ARM_VARIANT & arm_ext_v1
18468 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18469 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18470 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18471 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18472 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18473 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18474 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18475 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18476 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18477 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18478 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18479 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18480 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18481 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18482 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
18483 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18484 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18485 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
18487 /* Thumb2 only instructions. */
18489 #define ARM_VARIANT NULL
18491 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18492 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18493 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18494 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18495 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18496 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
18498 /* Hardware division instructions. */
18500 #define ARM_VARIANT & arm_ext_adiv
18501 #undef THUMB_VARIANT
18502 #define THUMB_VARIANT & arm_ext_div
18504 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18505 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
18507 /* ARM V6M/V7 instructions. */
18509 #define ARM_VARIANT & arm_ext_barrier
18510 #undef THUMB_VARIANT
18511 #define THUMB_VARIANT & arm_ext_barrier
18513 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
18514 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
18515 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
18517 /* ARM V7 instructions. */
18519 #define ARM_VARIANT & arm_ext_v7
18520 #undef THUMB_VARIANT
18521 #define THUMB_VARIANT & arm_ext_v7
18523 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18524 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
18527 #define ARM_VARIANT & arm_ext_mp
18528 #undef THUMB_VARIANT
18529 #define THUMB_VARIANT & arm_ext_mp
18531 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18533 /* AArchv8 instructions. */
18535 #define ARM_VARIANT & arm_ext_v8
18536 #undef THUMB_VARIANT
18537 #define THUMB_VARIANT & arm_ext_v8
18539 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
18540 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
18541 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18542 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
18544 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18545 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18546 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18548 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
18550 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18552 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18554 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18555 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18556 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18557 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18558 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18559 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18561 /* ARMv8 T32 only. */
18563 #define ARM_VARIANT NULL
18564 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18565 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18566 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18568 /* FP for ARMv8. */
18570 #define ARM_VARIANT & fpu_vfp_ext_armv8
18571 #undef THUMB_VARIANT
18572 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18574 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18575 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18576 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18577 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
18578 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18579 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18580 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
18581 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
18582 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
18583 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
18584 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
18585 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
18586 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
18587 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
18588 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
18589 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
18590 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
18592 /* Crypto v1 extensions. */
18594 #define ARM_VARIANT & fpu_crypto_ext_armv8
18595 #undef THUMB_VARIANT
18596 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18598 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
18599 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
18600 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
18601 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
18602 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
18603 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
18604 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
18605 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
18606 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
18607 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
18608 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
18609 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
18610 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
18611 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
18614 #define ARM_VARIANT & crc_ext_armv8
18615 #undef THUMB_VARIANT
18616 #define THUMB_VARIANT & crc_ext_armv8
18617 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
18618 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
18619 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
18620 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
18621 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
18622 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
18625 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18626 #undef THUMB_VARIANT
18627 #define THUMB_VARIANT NULL
18629 cCE("wfs", e200110, 1, (RR), rd),
18630 cCE("rfs", e300110, 1, (RR), rd),
18631 cCE("wfc", e400110, 1, (RR), rd),
18632 cCE("rfc", e500110, 1, (RR), rd),
18634 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18635 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18636 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18637 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18639 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18640 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18641 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18642 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18644 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18645 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18646 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18647 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18648 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18649 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18650 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18651 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18652 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18653 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18654 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18655 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18657 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18658 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18659 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18660 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18661 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18662 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18663 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18664 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18665 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18666 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18667 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18668 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18670 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18671 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18672 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18673 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18674 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18675 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18676 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18677 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18678 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18679 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18680 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18681 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18683 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18684 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18685 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18686 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18687 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18688 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18689 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18690 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18691 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18692 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18693 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18694 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18696 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18697 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18698 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18699 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18700 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18701 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18702 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18703 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18704 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18705 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18706 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18707 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18709 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18710 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18711 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18712 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18713 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18714 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18715 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18716 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18717 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18718 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18719 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18720 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18722 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18723 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18724 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18725 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18726 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18727 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18728 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18729 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18730 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18731 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18732 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18733 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18735 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18736 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18737 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18738 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18739 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18740 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18741 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18742 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18743 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18744 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18745 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18746 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18748 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18749 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18750 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18751 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18752 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18753 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18754 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18755 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18756 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18757 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18758 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18759 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18761 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18762 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18763 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18764 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18765 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18766 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18767 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18768 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18769 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18770 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18771 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18772 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18774 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18775 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18776 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18777 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18778 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18779 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18780 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18781 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18782 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18783 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18784 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18785 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18787 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18788 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18789 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18790 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18791 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18792 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18793 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18794 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18795 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18796 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18797 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18798 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18800 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18801 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18802 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18803 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18804 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18805 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18806 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18807 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18808 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18809 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18810 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18811 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18813 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18814 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18815 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18816 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18817 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18818 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18819 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18820 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18821 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18822 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18823 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18824 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18826 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18827 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18828 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18829 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18830 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18831 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18832 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18833 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18834 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18835 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18836 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18837 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18839 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18840 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18841 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18842 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18843 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18844 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18845 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18846 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18847 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18848 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18849 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18850 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18852 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18853 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18854 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18855 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18856 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18857 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18858 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18859 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18860 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18861 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18862 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18863 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18865 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18866 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18867 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18868 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18869 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18870 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18871 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18872 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18873 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18874 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18875 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18876 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18878 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18879 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18880 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18881 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18882 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18883 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18884 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18885 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18886 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18887 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18888 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18889 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18891 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18892 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18893 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18894 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18895 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18896 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18897 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18898 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18899 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18900 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18901 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18902 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18904 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18905 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18906 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18907 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18908 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18909 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18910 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18911 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18912 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18913 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18914 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18915 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18917 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18918 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18919 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18920 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18921 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18922 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18923 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18924 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18925 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18926 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18927 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18928 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18930 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18931 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18932 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18933 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18934 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18935 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18936 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18937 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18938 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18939 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18940 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18941 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18943 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18944 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18945 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18946 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18947 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18948 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18949 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18950 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18951 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18952 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18953 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18954 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18956 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18957 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18958 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18959 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18960 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18961 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18962 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18963 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18964 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18965 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18966 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18967 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18969 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18970 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18971 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18972 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18973 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18974 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18975 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18976 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18977 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18978 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18979 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18980 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18982 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18983 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18984 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18985 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18986 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18987 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18988 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18989 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18990 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18991 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18992 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18993 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18995 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18996 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18997 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18998 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18999 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19000 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19001 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19002 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19003 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19004 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19005 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19006 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19008 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19009 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19010 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19011 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19012 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19013 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19014 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19015 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19016 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19017 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19018 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19019 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19021 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
19022 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
19023 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
19024 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
19026 cCL("flts", e000110, 2, (RF, RR), rn_rd),
19027 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
19028 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
19029 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
19030 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
19031 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
19032 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
19033 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
19034 cCL("flte", e080110, 2, (RF, RR), rn_rd),
19035 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
19036 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
19037 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
19039 /* The implementation of the FIX instruction is broken on some
19040 assemblers, in that it accepts a precision specifier as well as a
19041 rounding specifier, despite the fact that this is meaningless.
19042 To be more compatible, we accept it as well, though of course it
19043 does not set any bits. */
19044 cCE("fix", e100110, 2, (RR, RF), rd_rm),
19045 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
19046 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
19047 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
19048 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
19049 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
19050 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
19051 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
19052 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
19053 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
19054 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
19055 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
19056 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
19058 /* Instructions that were new with the real FPA, call them V2. */
19060 #define ARM_VARIANT & fpu_fpa_ext_v2
19062 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19063 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19064 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19065 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19066 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19067 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19070 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19072 /* Moves and type conversions. */
19073 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
19074 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
19075 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
19076 cCE("fmstat", ef1fa10, 0, (), noargs),
19077 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
19078 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
19079 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
19080 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
19081 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
19082 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19083 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
19084 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19085 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
19086 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
19088 /* Memory operations. */
19089 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19090 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19091 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19092 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19093 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19094 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19095 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19096 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19097 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19098 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19099 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19100 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19101 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19102 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19103 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19104 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19105 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19106 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19108 /* Monadic operations. */
19109 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19110 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19111 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
19113 /* Dyadic operations. */
19114 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19115 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19116 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19117 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19118 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19119 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19120 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19121 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19122 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19125 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19126 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19127 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19128 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
19130 /* Double precision load/store are still present on single precision
19131 implementations. */
19132 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19133 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19134 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19135 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19136 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19137 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19138 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19139 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19140 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19141 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19144 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19146 /* Moves and type conversions. */
19147 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19148 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19149 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19150 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19151 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19152 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19153 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19154 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19155 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19156 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19157 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19158 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19159 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19161 /* Monadic operations. */
19162 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19163 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19164 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19166 /* Dyadic operations. */
19167 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19168 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19169 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19170 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19171 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19172 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19173 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19174 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19175 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19178 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19179 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19180 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19181 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
19184 #define ARM_VARIANT & fpu_vfp_ext_v2
19186 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19187 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19188 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19189 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
19191 /* Instructions which may belong to either the Neon or VFP instruction sets.
19192 Individual encoder functions perform additional architecture checks. */
19194 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19195 #undef THUMB_VARIANT
19196 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19198 /* These mnemonics are unique to VFP. */
19199 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19200 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
19201 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19202 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19203 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19204 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19205 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19206 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19207 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19208 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19210 /* Mnemonics shared by Neon and VFP. */
19211 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19212 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19213 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19215 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19216 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19218 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19219 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19221 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19222 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19223 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19224 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19225 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19226 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19227 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19228 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19230 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
19231 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
19232 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19233 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
19236 /* NOTE: All VMOV encoding is special-cased! */
19237 NCE(vmov, 0, 1, (VMOV), neon_mov),
19238 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19240 #undef THUMB_VARIANT
19241 #define THUMB_VARIANT & fpu_neon_ext_v1
19243 #define ARM_VARIANT & fpu_neon_ext_v1
19245 /* Data processing with three registers of the same length. */
19246 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19247 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19248 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19249 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19250 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19251 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19252 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19253 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19254 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19255 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19256 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19257 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19258 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19259 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19260 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19261 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19262 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19263 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19264 /* If not immediate, fall back to neon_dyadic_i64_su.
19265 shl_imm should accept I8 I16 I32 I64,
19266 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19267 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19268 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19269 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19270 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
19271 /* Logic ops, types optional & ignored. */
19272 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19273 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19274 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19275 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19276 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19277 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19278 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19279 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19280 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19281 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
19282 /* Bitfield ops, untyped. */
19283 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19284 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19285 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19286 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19287 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19288 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19289 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19290 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19291 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19292 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19293 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19294 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19295 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19296 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19297 back to neon_dyadic_if_su. */
19298 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19299 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19300 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19301 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19302 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19303 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19304 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19305 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19306 /* Comparison. Type I8 I16 I32 F32. */
19307 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19308 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
19309 /* As above, D registers only. */
19310 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19311 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19312 /* Int and float variants, signedness unimportant. */
19313 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19314 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19315 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
19316 /* Add/sub take types I8 I16 I32 I64 F32. */
19317 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19318 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19319 /* vtst takes sizes 8, 16, 32. */
19320 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19321 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19322 /* VMUL takes I8 I16 I32 F32 P8. */
19323 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
19324 /* VQD{R}MULH takes S16 S32. */
19325 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19326 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19327 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19328 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19329 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19330 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19331 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19332 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19333 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19334 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19335 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19336 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19337 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19338 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19339 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19340 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19342 /* Two address, int/float. Types S8 S16 S32 F32. */
19343 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
19344 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19346 /* Data processing with two registers and a shift amount. */
19347 /* Right shifts, and variants with rounding.
19348 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19349 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19350 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19351 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19352 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19353 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19354 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19355 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19356 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19357 /* Shift and insert. Sizes accepted 8 16 32 64. */
19358 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19359 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19360 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19361 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19362 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19363 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19364 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19365 /* Right shift immediate, saturating & narrowing, with rounding variants.
19366 Types accepted S16 S32 S64 U16 U32 U64. */
19367 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19368 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19369 /* As above, unsigned. Types accepted S16 S32 S64. */
19370 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19371 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19372 /* Right shift narrowing. Types accepted I16 I32 I64. */
19373 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19374 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19375 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19376 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
19377 /* CVT with optional immediate for fixed-point variant. */
19378 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
19380 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19381 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
19383 /* Data processing, three registers of different lengths. */
19384 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19385 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19386 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19387 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19388 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19389 /* If not scalar, fall back to neon_dyadic_long.
19390 Vector types as above, scalar types S16 S32 U16 U32. */
19391 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19392 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19393 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19394 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19395 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19396 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19397 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19398 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19399 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19400 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19401 /* Saturating doubling multiplies. Types S16 S32. */
19402 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19403 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19404 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19405 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19406 S16 S32 U16 U32. */
19407 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
19409 /* Extract. Size 8. */
19410 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19411 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
19413 /* Two registers, miscellaneous. */
19414 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19415 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19416 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19417 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19418 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19419 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19420 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19421 /* Vector replicate. Sizes 8 16 32. */
19422 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19423 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
19424 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19425 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19426 /* VMOVN. Types I16 I32 I64. */
19427 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
19428 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19429 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
19430 /* VQMOVUN. Types S16 S32 S64. */
19431 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
19432 /* VZIP / VUZP. Sizes 8 16 32. */
19433 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19434 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19435 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19436 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19437 /* VQABS / VQNEG. Types S8 S16 S32. */
19438 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19439 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19440 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19441 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19442 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19443 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19444 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19445 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19446 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19447 /* Reciprocal estimates. Types U32 F32. */
19448 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19449 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19450 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19451 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19452 /* VCLS. Types S8 S16 S32. */
19453 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19454 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19455 /* VCLZ. Types I8 I16 I32. */
19456 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19457 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19458 /* VCNT. Size 8. */
19459 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19460 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19461 /* Two address, untyped. */
19462 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19463 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19464 /* VTRN. Sizes 8 16 32. */
19465 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19466 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
19468 /* Table lookup. Size 8. */
19469 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19470 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19472 #undef THUMB_VARIANT
19473 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19475 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19477 /* Neon element/structure load/store. */
19478 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19479 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19480 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19481 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19482 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19483 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19484 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19485 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19487 #undef THUMB_VARIANT
19488 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
19490 #define ARM_VARIANT &fpu_vfp_ext_v3xd
19491 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19492 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19493 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19494 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19495 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19496 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19497 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19498 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19499 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19501 #undef THUMB_VARIANT
19502 #define THUMB_VARIANT & fpu_vfp_ext_v3
19504 #define ARM_VARIANT & fpu_vfp_ext_v3
19506 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
19507 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19508 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19509 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19510 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19511 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19512 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19513 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19514 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19517 #define ARM_VARIANT &fpu_vfp_ext_fma
19518 #undef THUMB_VARIANT
19519 #define THUMB_VARIANT &fpu_vfp_ext_fma
19520 /* Mnemonics shared by Neon and VFP. These are included in the
19521 VFP FMA variant; NEON and VFP FMA always includes the NEON
19522 FMA instructions. */
19523 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19524 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19525 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19526 the v form should always be used. */
19527 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19528 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19529 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19530 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19531 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19532 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19534 #undef THUMB_VARIANT
19536 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19538 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19539 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19540 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19541 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19542 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19543 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19544 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19545 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
19548 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19550 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19551 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19552 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19553 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19554 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19555 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19556 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19557 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19558 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19559 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19560 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19561 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19562 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19563 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19564 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19565 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19566 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19567 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19568 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19569 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19570 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19571 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19572 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19573 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19574 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19575 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19576 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
19577 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
19578 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
19579 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19580 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19581 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19582 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19583 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19584 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19585 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19586 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19587 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19588 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19589 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19590 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19591 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19592 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19593 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19594 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19595 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19596 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19597 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19598 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19599 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19600 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19601 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19602 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19603 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19604 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19605 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19606 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19607 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19608 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19609 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19610 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19611 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19612 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19613 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19614 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19615 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19616 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19617 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19618 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19619 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19620 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19621 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19622 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19623 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19624 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19625 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19626 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19627 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19628 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19629 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19630 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19631 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19632 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19633 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19634 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19635 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19636 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19637 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19638 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19639 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19640 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19641 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19642 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19643 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19644 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19645 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19646 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19647 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19648 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19649 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19650 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19651 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19652 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19653 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19654 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19655 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19656 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19657 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19658 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19659 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19660 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19661 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19662 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19663 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19664 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19665 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19666 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19667 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19668 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19669 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19670 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19671 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19672 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19673 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19674 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19675 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19676 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19677 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19678 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19679 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19680 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19681 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19682 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19683 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19684 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19685 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19686 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19687 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19688 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19689 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19690 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19691 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19692 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19693 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19694 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19695 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19696 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19697 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19698 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19699 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19700 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19701 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19702 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19703 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19704 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19705 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19706 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19707 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19708 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19709 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19710 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19711 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
19714 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19716 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19717 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19718 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19719 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19720 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19721 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19722 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19723 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19724 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19725 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19726 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19727 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19728 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19729 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19730 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19731 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19732 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19733 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19734 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19735 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19736 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19737 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19738 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19739 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19740 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19741 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19742 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19743 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19744 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19745 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19746 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19747 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19748 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19749 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19750 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19751 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19752 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19753 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19754 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19755 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19756 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19757 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19758 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19759 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19760 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19761 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19762 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19763 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19764 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19765 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19766 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19767 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19768 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19769 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19770 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19771 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19772 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19775 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19777 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19778 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19779 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19780 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19781 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19782 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19783 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19784 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19785 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19786 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19787 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19788 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19789 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19790 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19791 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
19792 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
19793 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
19794 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
19795 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
19796 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
19797 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
19798 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
19799 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
19800 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
19801 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19802 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19803 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19804 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19805 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19806 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
19807 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19808 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19809 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19810 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19811 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
19812 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
19813 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
19814 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
19815 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
19816 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
19817 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19818 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19819 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
19820 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
19821 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19822 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19823 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19824 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19825 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19826 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19827 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19828 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19829 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19830 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19831 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19832 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19833 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19834 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19835 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19836 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19837 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19838 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19839 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19840 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19841 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19842 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19843 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19844 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19845 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19846 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19847 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19848 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19849 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19850 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19851 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19852 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19855 #undef THUMB_VARIANT
19881 /* MD interface: bits in the object file. */
19883 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19884 for use in the a.out file, and stores them in the array pointed to by buf.
19885 This knows about the endian-ness of the target machine and does
19886 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19887 2 (short) and 4 (long) Floating numbers are put out as a series of
19888 LITTLENUMS (shorts, here at least). */
19891 md_number_to_chars (char * buf, valueT val, int n)
19893 if (target_big_endian)
19894 number_to_chars_bigendian (buf, val, n);
19896 number_to_chars_littleendian (buf, val, n);
19900 md_chars_to_number (char * buf, int n)
19903 unsigned char * where = (unsigned char *) buf;
19905 if (target_big_endian)
19910 result |= (*where++ & 255);
19918 result |= (where[n] & 255);
19925 /* MD interface: Sections. */
19927 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19928 that an rs_machine_dependent frag may reach. */
19931 arm_frag_max_var (fragS *fragp)
19933 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19934 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19936 Note that we generate relaxable instructions even for cases that don't
19937 really need it, like an immediate that's a trivial constant. So we're
19938 overestimating the instruction size for some of those cases. Rather
19939 than putting more intelligence here, it would probably be better to
19940 avoid generating a relaxation frag in the first place when it can be
19941 determined up front that a short instruction will suffice. */
19943 gas_assert (fragp->fr_type == rs_machine_dependent);
19947 /* Estimate the size of a frag before relaxing. Assume everything fits in
19951 md_estimate_size_before_relax (fragS * fragp,
19952 segT segtype ATTRIBUTE_UNUSED)
19958 /* Convert a machine dependent frag. */
19961 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19963 unsigned long insn;
19964 unsigned long old_op;
19972 buf = fragp->fr_literal + fragp->fr_fix;
19974 old_op = bfd_get_16(abfd, buf);
19975 if (fragp->fr_symbol)
19977 exp.X_op = O_symbol;
19978 exp.X_add_symbol = fragp->fr_symbol;
19982 exp.X_op = O_constant;
19984 exp.X_add_number = fragp->fr_offset;
19985 opcode = fragp->fr_subtype;
19988 case T_MNEM_ldr_pc:
19989 case T_MNEM_ldr_pc2:
19990 case T_MNEM_ldr_sp:
19991 case T_MNEM_str_sp:
19998 if (fragp->fr_var == 4)
20000 insn = THUMB_OP32 (opcode);
20001 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
20003 insn |= (old_op & 0x700) << 4;
20007 insn |= (old_op & 7) << 12;
20008 insn |= (old_op & 0x38) << 13;
20010 insn |= 0x00000c00;
20011 put_thumb32_insn (buf, insn);
20012 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
20016 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
20018 pc_rel = (opcode == T_MNEM_ldr_pc2);
20021 if (fragp->fr_var == 4)
20023 insn = THUMB_OP32 (opcode);
20024 insn |= (old_op & 0xf0) << 4;
20025 put_thumb32_insn (buf, insn);
20026 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
20030 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20031 exp.X_add_number -= 4;
20039 if (fragp->fr_var == 4)
20041 int r0off = (opcode == T_MNEM_mov
20042 || opcode == T_MNEM_movs) ? 0 : 8;
20043 insn = THUMB_OP32 (opcode);
20044 insn = (insn & 0xe1ffffff) | 0x10000000;
20045 insn |= (old_op & 0x700) << r0off;
20046 put_thumb32_insn (buf, insn);
20047 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20051 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
20056 if (fragp->fr_var == 4)
20058 insn = THUMB_OP32(opcode);
20059 put_thumb32_insn (buf, insn);
20060 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
20063 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
20067 if (fragp->fr_var == 4)
20069 insn = THUMB_OP32(opcode);
20070 insn |= (old_op & 0xf00) << 14;
20071 put_thumb32_insn (buf, insn);
20072 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
20075 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
20078 case T_MNEM_add_sp:
20079 case T_MNEM_add_pc:
20080 case T_MNEM_inc_sp:
20081 case T_MNEM_dec_sp:
20082 if (fragp->fr_var == 4)
20084 /* ??? Choose between add and addw. */
20085 insn = THUMB_OP32 (opcode);
20086 insn |= (old_op & 0xf0) << 4;
20087 put_thumb32_insn (buf, insn);
20088 if (opcode == T_MNEM_add_pc)
20089 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20091 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20094 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20102 if (fragp->fr_var == 4)
20104 insn = THUMB_OP32 (opcode);
20105 insn |= (old_op & 0xf0) << 4;
20106 insn |= (old_op & 0xf) << 16;
20107 put_thumb32_insn (buf, insn);
20108 if (insn & (1 << 20))
20109 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20111 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20114 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20120 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
20121 (enum bfd_reloc_code_real) reloc_type);
20122 fixp->fx_file = fragp->fr_file;
20123 fixp->fx_line = fragp->fr_line;
20124 fragp->fr_fix += fragp->fr_var;
20127 /* Return the size of a relaxable immediate operand instruction.
20128 SHIFT and SIZE specify the form of the allowable immediate. */
20130 relax_immediate (fragS *fragp, int size, int shift)
20136 /* ??? Should be able to do better than this. */
20137 if (fragp->fr_symbol)
20140 low = (1 << shift) - 1;
20141 mask = (1 << (shift + size)) - (1 << shift);
20142 offset = fragp->fr_offset;
20143 /* Force misaligned offsets to 32-bit variant. */
20146 if (offset & ~mask)
20151 /* Get the address of a symbol during relaxation. */
20153 relaxed_symbol_addr (fragS *fragp, long stretch)
20159 sym = fragp->fr_symbol;
20160 sym_frag = symbol_get_frag (sym);
20161 know (S_GET_SEGMENT (sym) != absolute_section
20162 || sym_frag == &zero_address_frag);
20163 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20165 /* If frag has yet to be reached on this pass, assume it will
20166 move by STRETCH just as we did. If this is not so, it will
20167 be because some frag between grows, and that will force
20171 && sym_frag->relax_marker != fragp->relax_marker)
20175 /* Adjust stretch for any alignment frag. Note that if have
20176 been expanding the earlier code, the symbol may be
20177 defined in what appears to be an earlier frag. FIXME:
20178 This doesn't handle the fr_subtype field, which specifies
20179 a maximum number of bytes to skip when doing an
20181 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20183 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20186 stretch = - ((- stretch)
20187 & ~ ((1 << (int) f->fr_offset) - 1));
20189 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20201 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20204 relax_adr (fragS *fragp, asection *sec, long stretch)
20209 /* Assume worst case for symbols not known to be in the same section. */
20210 if (fragp->fr_symbol == NULL
20211 || !S_IS_DEFINED (fragp->fr_symbol)
20212 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20213 || S_IS_WEAK (fragp->fr_symbol))
20216 val = relaxed_symbol_addr (fragp, stretch);
20217 addr = fragp->fr_address + fragp->fr_fix;
20218 addr = (addr + 4) & ~3;
20219 /* Force misaligned targets to 32-bit variant. */
20223 if (val < 0 || val > 1020)
20228 /* Return the size of a relaxable add/sub immediate instruction. */
20230 relax_addsub (fragS *fragp, asection *sec)
20235 buf = fragp->fr_literal + fragp->fr_fix;
20236 op = bfd_get_16(sec->owner, buf);
20237 if ((op & 0xf) == ((op >> 4) & 0xf))
20238 return relax_immediate (fragp, 8, 0);
20240 return relax_immediate (fragp, 3, 0);
20244 /* Return the size of a relaxable branch instruction. BITS is the
20245 size of the offset field in the narrow instruction. */
20248 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
20254 /* Assume worst case for symbols not known to be in the same section. */
20255 if (!S_IS_DEFINED (fragp->fr_symbol)
20256 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20257 || S_IS_WEAK (fragp->fr_symbol))
20261 if (S_IS_DEFINED (fragp->fr_symbol)
20262 && ARM_IS_FUNC (fragp->fr_symbol))
20265 /* PR 12532. Global symbols with default visibility might
20266 be preempted, so do not relax relocations to them. */
20267 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
20268 && (! S_IS_LOCAL (fragp->fr_symbol)))
20272 val = relaxed_symbol_addr (fragp, stretch);
20273 addr = fragp->fr_address + fragp->fr_fix + 4;
20276 /* Offset is a signed value *2 */
20278 if (val >= limit || val < -limit)
20284 /* Relax a machine dependent frag. This returns the amount by which
20285 the current size of the frag should change. */
20288 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
20293 oldsize = fragp->fr_var;
20294 switch (fragp->fr_subtype)
20296 case T_MNEM_ldr_pc2:
20297 newsize = relax_adr (fragp, sec, stretch);
20299 case T_MNEM_ldr_pc:
20300 case T_MNEM_ldr_sp:
20301 case T_MNEM_str_sp:
20302 newsize = relax_immediate (fragp, 8, 2);
20306 newsize = relax_immediate (fragp, 5, 2);
20310 newsize = relax_immediate (fragp, 5, 1);
20314 newsize = relax_immediate (fragp, 5, 0);
20317 newsize = relax_adr (fragp, sec, stretch);
20323 newsize = relax_immediate (fragp, 8, 0);
20326 newsize = relax_branch (fragp, sec, 11, stretch);
20329 newsize = relax_branch (fragp, sec, 8, stretch);
20331 case T_MNEM_add_sp:
20332 case T_MNEM_add_pc:
20333 newsize = relax_immediate (fragp, 8, 2);
20335 case T_MNEM_inc_sp:
20336 case T_MNEM_dec_sp:
20337 newsize = relax_immediate (fragp, 7, 2);
20343 newsize = relax_addsub (fragp, sec);
20349 fragp->fr_var = newsize;
20350 /* Freeze wide instructions that are at or before the same location as
20351 in the previous pass. This avoids infinite loops.
20352 Don't freeze them unconditionally because targets may be artificially
20353 misaligned by the expansion of preceding frags. */
20354 if (stretch <= 0 && newsize > 2)
20356 md_convert_frag (sec->owner, sec, fragp);
20360 return newsize - oldsize;
20363 /* Round up a section size to the appropriate boundary. */
20366 md_section_align (segT segment ATTRIBUTE_UNUSED,
20369 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20370 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20372 /* For a.out, force the section size to be aligned. If we don't do
20373 this, BFD will align it for us, but it will not write out the
20374 final bytes of the section. This may be a bug in BFD, but it is
20375 easier to fix it here since that is how the other a.out targets
20379 align = bfd_get_section_alignment (stdoutput, segment);
20380 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20387 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20388 of an rs_align_code fragment. */
20391 arm_handle_align (fragS * fragP)
20393 static char const arm_noop[2][2][4] =
20396 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20397 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20400 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20401 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20404 static char const thumb_noop[2][2][2] =
20407 {0xc0, 0x46}, /* LE */
20408 {0x46, 0xc0}, /* BE */
20411 {0x00, 0xbf}, /* LE */
20412 {0xbf, 0x00} /* BE */
20415 static char const wide_thumb_noop[2][4] =
20416 { /* Wide Thumb-2 */
20417 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20418 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20421 unsigned bytes, fix, noop_size;
20424 const char *narrow_noop = NULL;
20429 if (fragP->fr_type != rs_align_code)
20432 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20433 p = fragP->fr_literal + fragP->fr_fix;
20436 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20437 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
20439 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
20441 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
20443 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
20445 narrow_noop = thumb_noop[1][target_big_endian];
20446 noop = wide_thumb_noop[target_big_endian];
20449 noop = thumb_noop[0][target_big_endian];
20457 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
20458 [target_big_endian];
20465 fragP->fr_var = noop_size;
20467 if (bytes & (noop_size - 1))
20469 fix = bytes & (noop_size - 1);
20471 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20473 memset (p, 0, fix);
20480 if (bytes & noop_size)
20482 /* Insert a narrow noop. */
20483 memcpy (p, narrow_noop, noop_size);
20485 bytes -= noop_size;
20489 /* Use wide noops for the remainder */
20493 while (bytes >= noop_size)
20495 memcpy (p, noop, noop_size);
20497 bytes -= noop_size;
20501 fragP->fr_fix += fix;
20504 /* Called from md_do_align. Used to create an alignment
20505 frag in a code section. */
20508 arm_frag_align_code (int n, int max)
20512 /* We assume that there will never be a requirement
20513 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20514 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
20519 _("alignments greater than %d bytes not supported in .text sections."),
20520 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20521 as_fatal ("%s", err_msg);
20524 p = frag_var (rs_align_code,
20525 MAX_MEM_FOR_RS_ALIGN_CODE,
20527 (relax_substateT) max,
20534 /* Perform target specific initialisation of a frag.
20535 Note - despite the name this initialisation is not done when the frag
20536 is created, but only when its type is assigned. A frag can be created
20537 and used a long time before its type is set, so beware of assuming that
20538 this initialisationis performed first. */
20542 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20544 /* Record whether this frag is in an ARM or a THUMB area. */
20545 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20548 #else /* OBJ_ELF is defined. */
20550 arm_init_frag (fragS * fragP, int max_chars)
20552 /* If the current ARM vs THUMB mode has not already
20553 been recorded into this frag then do so now. */
20554 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20556 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20558 /* Record a mapping symbol for alignment frags. We will delete this
20559 later if the alignment ends up empty. */
20560 switch (fragP->fr_type)
20563 case rs_align_test:
20565 mapping_state_2 (MAP_DATA, max_chars);
20567 case rs_align_code:
20568 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20576 /* When we change sections we need to issue a new mapping symbol. */
20579 arm_elf_change_section (void)
20581 /* Link an unlinked unwind index table section to the .text section. */
20582 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20583 && elf_linked_to_section (now_seg) == NULL)
20584 elf_linked_to_section (now_seg) = text_section;
20588 arm_elf_section_type (const char * str, size_t len)
20590 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20591 return SHT_ARM_EXIDX;
20596 /* Code to deal with unwinding tables. */
20598 static void add_unwind_adjustsp (offsetT);
20600 /* Generate any deferred unwind frame offset. */
20603 flush_pending_unwind (void)
20607 offset = unwind.pending_offset;
20608 unwind.pending_offset = 0;
20610 add_unwind_adjustsp (offset);
20613 /* Add an opcode to this list for this function. Two-byte opcodes should
20614 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20618 add_unwind_opcode (valueT op, int length)
20620 /* Add any deferred stack adjustment. */
20621 if (unwind.pending_offset)
20622 flush_pending_unwind ();
20624 unwind.sp_restored = 0;
20626 if (unwind.opcode_count + length > unwind.opcode_alloc)
20628 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20629 if (unwind.opcodes)
20630 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
20631 unwind.opcode_alloc);
20633 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
20638 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20640 unwind.opcode_count++;
20644 /* Add unwind opcodes to adjust the stack pointer. */
20647 add_unwind_adjustsp (offsetT offset)
20651 if (offset > 0x200)
20653 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20658 /* Long form: 0xb2, uleb128. */
20659 /* This might not fit in a word so add the individual bytes,
20660 remembering the list is built in reverse order. */
20661 o = (valueT) ((offset - 0x204) >> 2);
20663 add_unwind_opcode (0, 1);
20665 /* Calculate the uleb128 encoding of the offset. */
20669 bytes[n] = o & 0x7f;
20675 /* Add the insn. */
20677 add_unwind_opcode (bytes[n - 1], 1);
20678 add_unwind_opcode (0xb2, 1);
20680 else if (offset > 0x100)
20682 /* Two short opcodes. */
20683 add_unwind_opcode (0x3f, 1);
20684 op = (offset - 0x104) >> 2;
20685 add_unwind_opcode (op, 1);
20687 else if (offset > 0)
20689 /* Short opcode. */
20690 op = (offset - 4) >> 2;
20691 add_unwind_opcode (op, 1);
20693 else if (offset < 0)
20696 while (offset > 0x100)
20698 add_unwind_opcode (0x7f, 1);
20701 op = ((offset - 4) >> 2) | 0x40;
20702 add_unwind_opcode (op, 1);
20706 /* Finish the list of unwind opcodes for this function. */
20708 finish_unwind_opcodes (void)
20712 if (unwind.fp_used)
20714 /* Adjust sp as necessary. */
20715 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20716 flush_pending_unwind ();
20718 /* After restoring sp from the frame pointer. */
20719 op = 0x90 | unwind.fp_reg;
20720 add_unwind_opcode (op, 1);
20723 flush_pending_unwind ();
20727 /* Start an exception table entry. If idx is nonzero this is an index table
20731 start_unwind_section (const segT text_seg, int idx)
20733 const char * text_name;
20734 const char * prefix;
20735 const char * prefix_once;
20736 const char * group_name;
20740 size_t sec_name_len;
20747 prefix = ELF_STRING_ARM_unwind;
20748 prefix_once = ELF_STRING_ARM_unwind_once;
20749 type = SHT_ARM_EXIDX;
20753 prefix = ELF_STRING_ARM_unwind_info;
20754 prefix_once = ELF_STRING_ARM_unwind_info_once;
20755 type = SHT_PROGBITS;
20758 text_name = segment_name (text_seg);
20759 if (streq (text_name, ".text"))
20762 if (strncmp (text_name, ".gnu.linkonce.t.",
20763 strlen (".gnu.linkonce.t.")) == 0)
20765 prefix = prefix_once;
20766 text_name += strlen (".gnu.linkonce.t.");
20769 prefix_len = strlen (prefix);
20770 text_len = strlen (text_name);
20771 sec_name_len = prefix_len + text_len;
20772 sec_name = (char *) xmalloc (sec_name_len + 1);
20773 memcpy (sec_name, prefix, prefix_len);
20774 memcpy (sec_name + prefix_len, text_name, text_len);
20775 sec_name[prefix_len + text_len] = '\0';
20781 /* Handle COMDAT group. */
20782 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20784 group_name = elf_group_name (text_seg);
20785 if (group_name == NULL)
20787 as_bad (_("Group section `%s' has no group signature"),
20788 segment_name (text_seg));
20789 ignore_rest_of_line ();
20792 flags |= SHF_GROUP;
20796 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20798 /* Set the section link for index tables. */
20800 elf_linked_to_section (now_seg) = text_seg;
20804 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20805 personality routine data. Returns zero, or the index table value for
20806 and inline entry. */
20809 create_unwind_entry (int have_data)
20814 /* The current word of data. */
20816 /* The number of bytes left in this word. */
20819 finish_unwind_opcodes ();
20821 /* Remember the current text section. */
20822 unwind.saved_seg = now_seg;
20823 unwind.saved_subseg = now_subseg;
20825 start_unwind_section (now_seg, 0);
20827 if (unwind.personality_routine == NULL)
20829 if (unwind.personality_index == -2)
20832 as_bad (_("handlerdata in cantunwind frame"));
20833 return 1; /* EXIDX_CANTUNWIND. */
20836 /* Use a default personality routine if none is specified. */
20837 if (unwind.personality_index == -1)
20839 if (unwind.opcode_count > 3)
20840 unwind.personality_index = 1;
20842 unwind.personality_index = 0;
20845 /* Space for the personality routine entry. */
20846 if (unwind.personality_index == 0)
20848 if (unwind.opcode_count > 3)
20849 as_bad (_("too many unwind opcodes for personality routine 0"));
20853 /* All the data is inline in the index table. */
20856 while (unwind.opcode_count > 0)
20858 unwind.opcode_count--;
20859 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20863 /* Pad with "finish" opcodes. */
20865 data = (data << 8) | 0xb0;
20872 /* We get two opcodes "free" in the first word. */
20873 size = unwind.opcode_count - 2;
20877 gas_assert (unwind.personality_index == -1);
20879 /* An extra byte is required for the opcode count. */
20880 size = unwind.opcode_count + 1;
20883 size = (size + 3) >> 2;
20885 as_bad (_("too many unwind opcodes"));
20887 frag_align (2, 0, 0);
20888 record_alignment (now_seg, 2);
20889 unwind.table_entry = expr_build_dot ();
20891 /* Allocate the table entry. */
20892 ptr = frag_more ((size << 2) + 4);
20893 /* PR 13449: Zero the table entries in case some of them are not used. */
20894 memset (ptr, 0, (size << 2) + 4);
20895 where = frag_now_fix () - ((size << 2) + 4);
20897 switch (unwind.personality_index)
20900 /* ??? Should this be a PLT generating relocation? */
20901 /* Custom personality routine. */
20902 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20903 BFD_RELOC_ARM_PREL31);
20908 /* Set the first byte to the number of additional words. */
20909 data = size > 0 ? size - 1 : 0;
20913 /* ABI defined personality routines. */
20915 /* Three opcodes bytes are packed into the first word. */
20922 /* The size and first two opcode bytes go in the first word. */
20923 data = ((0x80 + unwind.personality_index) << 8) | size;
20928 /* Should never happen. */
20932 /* Pack the opcodes into words (MSB first), reversing the list at the same
20934 while (unwind.opcode_count > 0)
20938 md_number_to_chars (ptr, data, 4);
20943 unwind.opcode_count--;
20945 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20948 /* Finish off the last word. */
20951 /* Pad with "finish" opcodes. */
20953 data = (data << 8) | 0xb0;
20955 md_number_to_chars (ptr, data, 4);
20960 /* Add an empty descriptor if there is no user-specified data. */
20961 ptr = frag_more (4);
20962 md_number_to_chars (ptr, 0, 4);
20969 /* Initialize the DWARF-2 unwind information for this procedure. */
20972 tc_arm_frame_initial_instructions (void)
20974 cfi_add_CFA_def_cfa (REG_SP, 0);
20976 #endif /* OBJ_ELF */
20978 /* Convert REGNAME to a DWARF-2 register number. */
20981 tc_arm_regname_to_dw2regnum (char *regname)
20983 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20993 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20997 exp.X_op = O_secrel;
20998 exp.X_add_symbol = symbol;
20999 exp.X_add_number = 0;
21000 emit_expr (&exp, size);
21004 /* MD interface: Symbol and relocation handling. */
21006 /* Return the address within the segment that a PC-relative fixup is
21007 relative to. For ARM, PC-relative fixups applied to instructions
21008 are generally relative to the location of the fixup plus 8 bytes.
21009 Thumb branches are offset by 4, and Thumb loads relative to PC
21010 require special handling. */
21013 md_pcrel_from_section (fixS * fixP, segT seg)
21015 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
21017 /* If this is pc-relative and we are going to emit a relocation
21018 then we just want to put out any pipeline compensation that the linker
21019 will need. Otherwise we want to use the calculated base.
21020 For WinCE we skip the bias for externals as well, since this
21021 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21023 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
21024 || (arm_force_relocation (fixP)
21026 && !S_IS_EXTERNAL (fixP->fx_addsy)
21032 switch (fixP->fx_r_type)
21034 /* PC relative addressing on the Thumb is slightly odd as the
21035 bottom two bits of the PC are forced to zero for the
21036 calculation. This happens *after* application of the
21037 pipeline offset. However, Thumb adrl already adjusts for
21038 this, so we need not do it again. */
21039 case BFD_RELOC_ARM_THUMB_ADD:
21042 case BFD_RELOC_ARM_THUMB_OFFSET:
21043 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21044 case BFD_RELOC_ARM_T32_ADD_PC12:
21045 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21046 return (base + 4) & ~3;
21048 /* Thumb branches are simply offset by +4. */
21049 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21050 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21051 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21052 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21053 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21056 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21058 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21059 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21060 && ARM_IS_FUNC (fixP->fx_addsy)
21061 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21062 base = fixP->fx_where + fixP->fx_frag->fr_address;
21065 /* BLX is like branches above, but forces the low two bits of PC to
21067 case BFD_RELOC_THUMB_PCREL_BLX:
21069 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21070 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21071 && THUMB_IS_FUNC (fixP->fx_addsy)
21072 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21073 base = fixP->fx_where + fixP->fx_frag->fr_address;
21074 return (base + 4) & ~3;
21076 /* ARM mode branches are offset by +8. However, the Windows CE
21077 loader expects the relocation not to take this into account. */
21078 case BFD_RELOC_ARM_PCREL_BLX:
21080 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21081 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21082 && ARM_IS_FUNC (fixP->fx_addsy)
21083 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21084 base = fixP->fx_where + fixP->fx_frag->fr_address;
21087 case BFD_RELOC_ARM_PCREL_CALL:
21089 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21090 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21091 && THUMB_IS_FUNC (fixP->fx_addsy)
21092 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21093 base = fixP->fx_where + fixP->fx_frag->fr_address;
21096 case BFD_RELOC_ARM_PCREL_BRANCH:
21097 case BFD_RELOC_ARM_PCREL_JUMP:
21098 case BFD_RELOC_ARM_PLT32:
21100 /* When handling fixups immediately, because we have already
21101 discovered the value of a symbol, or the address of the frag involved
21102 we must account for the offset by +8, as the OS loader will never see the reloc.
21103 see fixup_segment() in write.c
21104 The S_IS_EXTERNAL test handles the case of global symbols.
21105 Those need the calculated base, not just the pipe compensation the linker will need. */
21107 && fixP->fx_addsy != NULL
21108 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21109 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21117 /* ARM mode loads relative to PC are also offset by +8. Unlike
21118 branches, the Windows CE loader *does* expect the relocation
21119 to take this into account. */
21120 case BFD_RELOC_ARM_OFFSET_IMM:
21121 case BFD_RELOC_ARM_OFFSET_IMM8:
21122 case BFD_RELOC_ARM_HWLITERAL:
21123 case BFD_RELOC_ARM_LITERAL:
21124 case BFD_RELOC_ARM_CP_OFF_IMM:
21128 /* Other PC-relative relocations are un-offset. */
21134 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21135 Otherwise we have no need to default values of symbols. */
21138 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
21141 if (name[0] == '_' && name[1] == 'G'
21142 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21146 if (symbol_find (name))
21147 as_bad (_("GOT already in the symbol table"));
21149 GOT_symbol = symbol_new (name, undefined_section,
21150 (valueT) 0, & zero_address_frag);
21160 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21161 computed as two separate immediate values, added together. We
21162 already know that this value cannot be computed by just one ARM
21165 static unsigned int
21166 validate_immediate_twopart (unsigned int val,
21167 unsigned int * highpart)
21172 for (i = 0; i < 32; i += 2)
21173 if (((a = rotate_left (val, i)) & 0xff) != 0)
21179 * highpart = (a >> 8) | ((i + 24) << 7);
21181 else if (a & 0xff0000)
21183 if (a & 0xff000000)
21185 * highpart = (a >> 16) | ((i + 16) << 7);
21189 gas_assert (a & 0xff000000);
21190 * highpart = (a >> 24) | ((i + 8) << 7);
21193 return (a & 0xff) | (i << 7);
21200 validate_offset_imm (unsigned int val, int hwse)
21202 if ((hwse && val > 255) || val > 4095)
21207 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21208 negative immediate constant by altering the instruction. A bit of
21213 by inverting the second operand, and
21216 by negating the second operand. */
21219 negate_data_op (unsigned long * instruction,
21220 unsigned long value)
21223 unsigned long negated, inverted;
21225 negated = encode_arm_immediate (-value);
21226 inverted = encode_arm_immediate (~value);
21228 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21231 /* First negates. */
21232 case OPCODE_SUB: /* ADD <-> SUB */
21233 new_inst = OPCODE_ADD;
21238 new_inst = OPCODE_SUB;
21242 case OPCODE_CMP: /* CMP <-> CMN */
21243 new_inst = OPCODE_CMN;
21248 new_inst = OPCODE_CMP;
21252 /* Now Inverted ops. */
21253 case OPCODE_MOV: /* MOV <-> MVN */
21254 new_inst = OPCODE_MVN;
21259 new_inst = OPCODE_MOV;
21263 case OPCODE_AND: /* AND <-> BIC */
21264 new_inst = OPCODE_BIC;
21269 new_inst = OPCODE_AND;
21273 case OPCODE_ADC: /* ADC <-> SBC */
21274 new_inst = OPCODE_SBC;
21279 new_inst = OPCODE_ADC;
21283 /* We cannot do anything. */
21288 if (value == (unsigned) FAIL)
21291 *instruction &= OPCODE_MASK;
21292 *instruction |= new_inst << DATA_OP_SHIFT;
21296 /* Like negate_data_op, but for Thumb-2. */
21298 static unsigned int
21299 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
21303 unsigned int negated, inverted;
21305 negated = encode_thumb32_immediate (-value);
21306 inverted = encode_thumb32_immediate (~value);
21308 rd = (*instruction >> 8) & 0xf;
21309 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21312 /* ADD <-> SUB. Includes CMP <-> CMN. */
21313 case T2_OPCODE_SUB:
21314 new_inst = T2_OPCODE_ADD;
21318 case T2_OPCODE_ADD:
21319 new_inst = T2_OPCODE_SUB;
21323 /* ORR <-> ORN. Includes MOV <-> MVN. */
21324 case T2_OPCODE_ORR:
21325 new_inst = T2_OPCODE_ORN;
21329 case T2_OPCODE_ORN:
21330 new_inst = T2_OPCODE_ORR;
21334 /* AND <-> BIC. TST has no inverted equivalent. */
21335 case T2_OPCODE_AND:
21336 new_inst = T2_OPCODE_BIC;
21343 case T2_OPCODE_BIC:
21344 new_inst = T2_OPCODE_AND;
21349 case T2_OPCODE_ADC:
21350 new_inst = T2_OPCODE_SBC;
21354 case T2_OPCODE_SBC:
21355 new_inst = T2_OPCODE_ADC;
21359 /* We cannot do anything. */
21364 if (value == (unsigned int)FAIL)
21367 *instruction &= T2_OPCODE_MASK;
21368 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21372 /* Read a 32-bit thumb instruction from buf. */
21373 static unsigned long
21374 get_thumb32_insn (char * buf)
21376 unsigned long insn;
21377 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21378 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21384 /* We usually want to set the low bit on the address of thumb function
21385 symbols. In particular .word foo - . should have the low bit set.
21386 Generic code tries to fold the difference of two symbols to
21387 a constant. Prevent this and force a relocation when the first symbols
21388 is a thumb function. */
21391 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21393 if (op == O_subtract
21394 && l->X_op == O_symbol
21395 && r->X_op == O_symbol
21396 && THUMB_IS_FUNC (l->X_add_symbol))
21398 l->X_op = O_subtract;
21399 l->X_op_symbol = r->X_add_symbol;
21400 l->X_add_number -= r->X_add_number;
21404 /* Process as normal. */
21408 /* Encode Thumb2 unconditional branches and calls. The encoding
21409 for the 2 are identical for the immediate values. */
21412 encode_thumb2_b_bl_offset (char * buf, offsetT value)
21414 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21417 addressT S, I1, I2, lo, hi;
21419 S = (value >> 24) & 0x01;
21420 I1 = (value >> 23) & 0x01;
21421 I2 = (value >> 22) & 0x01;
21422 hi = (value >> 12) & 0x3ff;
21423 lo = (value >> 1) & 0x7ff;
21424 newval = md_chars_to_number (buf, THUMB_SIZE);
21425 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21426 newval |= (S << 10) | hi;
21427 newval2 &= ~T2I1I2MASK;
21428 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21429 md_number_to_chars (buf, newval, THUMB_SIZE);
21430 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21434 md_apply_fix (fixS * fixP,
21438 offsetT value = * valP;
21440 unsigned int newimm;
21441 unsigned long temp;
21443 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
21445 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
21447 /* Note whether this will delete the relocation. */
21449 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21452 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21453 consistency with the behaviour on 32-bit hosts. Remember value
21455 value &= 0xffffffff;
21456 value ^= 0x80000000;
21457 value -= 0x80000000;
21460 fixP->fx_addnumber = value;
21462 /* Same treatment for fixP->fx_offset. */
21463 fixP->fx_offset &= 0xffffffff;
21464 fixP->fx_offset ^= 0x80000000;
21465 fixP->fx_offset -= 0x80000000;
21467 switch (fixP->fx_r_type)
21469 case BFD_RELOC_NONE:
21470 /* This will need to go in the object file. */
21474 case BFD_RELOC_ARM_IMMEDIATE:
21475 /* We claim that this fixup has been processed here,
21476 even if in fact we generate an error because we do
21477 not have a reloc for it, so tc_gen_reloc will reject it. */
21480 if (fixP->fx_addsy)
21482 const char *msg = 0;
21484 if (! S_IS_DEFINED (fixP->fx_addsy))
21485 msg = _("undefined symbol %s used as an immediate value");
21486 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21487 msg = _("symbol %s is in a different section");
21488 else if (S_IS_WEAK (fixP->fx_addsy))
21489 msg = _("symbol %s is weak and may be overridden later");
21493 as_bad_where (fixP->fx_file, fixP->fx_line,
21494 msg, S_GET_NAME (fixP->fx_addsy));
21499 temp = md_chars_to_number (buf, INSN_SIZE);
21501 /* If the offset is negative, we should use encoding A2 for ADR. */
21502 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21503 newimm = negate_data_op (&temp, value);
21506 newimm = encode_arm_immediate (value);
21508 /* If the instruction will fail, see if we can fix things up by
21509 changing the opcode. */
21510 if (newimm == (unsigned int) FAIL)
21511 newimm = negate_data_op (&temp, value);
21514 if (newimm == (unsigned int) FAIL)
21516 as_bad_where (fixP->fx_file, fixP->fx_line,
21517 _("invalid constant (%lx) after fixup"),
21518 (unsigned long) value);
21522 newimm |= (temp & 0xfffff000);
21523 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21526 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21528 unsigned int highpart = 0;
21529 unsigned int newinsn = 0xe1a00000; /* nop. */
21531 if (fixP->fx_addsy)
21533 const char *msg = 0;
21535 if (! S_IS_DEFINED (fixP->fx_addsy))
21536 msg = _("undefined symbol %s used as an immediate value");
21537 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21538 msg = _("symbol %s is in a different section");
21539 else if (S_IS_WEAK (fixP->fx_addsy))
21540 msg = _("symbol %s is weak and may be overridden later");
21544 as_bad_where (fixP->fx_file, fixP->fx_line,
21545 msg, S_GET_NAME (fixP->fx_addsy));
21550 newimm = encode_arm_immediate (value);
21551 temp = md_chars_to_number (buf, INSN_SIZE);
21553 /* If the instruction will fail, see if we can fix things up by
21554 changing the opcode. */
21555 if (newimm == (unsigned int) FAIL
21556 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21558 /* No ? OK - try using two ADD instructions to generate
21560 newimm = validate_immediate_twopart (value, & highpart);
21562 /* Yes - then make sure that the second instruction is
21564 if (newimm != (unsigned int) FAIL)
21566 /* Still No ? Try using a negated value. */
21567 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21568 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21569 /* Otherwise - give up. */
21572 as_bad_where (fixP->fx_file, fixP->fx_line,
21573 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21578 /* Replace the first operand in the 2nd instruction (which
21579 is the PC) with the destination register. We have
21580 already added in the PC in the first instruction and we
21581 do not want to do it again. */
21582 newinsn &= ~ 0xf0000;
21583 newinsn |= ((newinsn & 0x0f000) << 4);
21586 newimm |= (temp & 0xfffff000);
21587 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21589 highpart |= (newinsn & 0xfffff000);
21590 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21594 case BFD_RELOC_ARM_OFFSET_IMM:
21595 if (!fixP->fx_done && seg->use_rela_p)
21598 case BFD_RELOC_ARM_LITERAL:
21604 if (validate_offset_imm (value, 0) == FAIL)
21606 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21607 as_bad_where (fixP->fx_file, fixP->fx_line,
21608 _("invalid literal constant: pool needs to be closer"));
21610 as_bad_where (fixP->fx_file, fixP->fx_line,
21611 _("bad immediate value for offset (%ld)"),
21616 newval = md_chars_to_number (buf, INSN_SIZE);
21618 newval &= 0xfffff000;
21621 newval &= 0xff7ff000;
21622 newval |= value | (sign ? INDEX_UP : 0);
21624 md_number_to_chars (buf, newval, INSN_SIZE);
21627 case BFD_RELOC_ARM_OFFSET_IMM8:
21628 case BFD_RELOC_ARM_HWLITERAL:
21634 if (validate_offset_imm (value, 1) == FAIL)
21636 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21637 as_bad_where (fixP->fx_file, fixP->fx_line,
21638 _("invalid literal constant: pool needs to be closer"));
21640 as_bad_where (fixP->fx_file, fixP->fx_line,
21641 _("bad immediate value for 8-bit offset (%ld)"),
21646 newval = md_chars_to_number (buf, INSN_SIZE);
21648 newval &= 0xfffff0f0;
21651 newval &= 0xff7ff0f0;
21652 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21654 md_number_to_chars (buf, newval, INSN_SIZE);
21657 case BFD_RELOC_ARM_T32_OFFSET_U8:
21658 if (value < 0 || value > 1020 || value % 4 != 0)
21659 as_bad_where (fixP->fx_file, fixP->fx_line,
21660 _("bad immediate value for offset (%ld)"), (long) value);
21663 newval = md_chars_to_number (buf+2, THUMB_SIZE);
21665 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21668 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21669 /* This is a complicated relocation used for all varieties of Thumb32
21670 load/store instruction with immediate offset:
21672 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21673 *4, optional writeback(W)
21674 (doubleword load/store)
21676 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21677 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21678 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21679 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21680 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21682 Uppercase letters indicate bits that are already encoded at
21683 this point. Lowercase letters are our problem. For the
21684 second block of instructions, the secondary opcode nybble
21685 (bits 8..11) is present, and bit 23 is zero, even if this is
21686 a PC-relative operation. */
21687 newval = md_chars_to_number (buf, THUMB_SIZE);
21689 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
21691 if ((newval & 0xf0000000) == 0xe0000000)
21693 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21695 newval |= (1 << 23);
21698 if (value % 4 != 0)
21700 as_bad_where (fixP->fx_file, fixP->fx_line,
21701 _("offset not a multiple of 4"));
21707 as_bad_where (fixP->fx_file, fixP->fx_line,
21708 _("offset out of range"));
21713 else if ((newval & 0x000f0000) == 0x000f0000)
21715 /* PC-relative, 12-bit offset. */
21717 newval |= (1 << 23);
21722 as_bad_where (fixP->fx_file, fixP->fx_line,
21723 _("offset out of range"));
21728 else if ((newval & 0x00000100) == 0x00000100)
21730 /* Writeback: 8-bit, +/- offset. */
21732 newval |= (1 << 9);
21737 as_bad_where (fixP->fx_file, fixP->fx_line,
21738 _("offset out of range"));
21743 else if ((newval & 0x00000f00) == 0x00000e00)
21745 /* T-instruction: positive 8-bit offset. */
21746 if (value < 0 || value > 0xff)
21748 as_bad_where (fixP->fx_file, fixP->fx_line,
21749 _("offset out of range"));
21757 /* Positive 12-bit or negative 8-bit offset. */
21761 newval |= (1 << 23);
21771 as_bad_where (fixP->fx_file, fixP->fx_line,
21772 _("offset out of range"));
21779 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21780 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21783 case BFD_RELOC_ARM_SHIFT_IMM:
21784 newval = md_chars_to_number (buf, INSN_SIZE);
21785 if (((unsigned long) value) > 32
21787 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21789 as_bad_where (fixP->fx_file, fixP->fx_line,
21790 _("shift expression is too large"));
21795 /* Shifts of zero must be done as lsl. */
21797 else if (value == 32)
21799 newval &= 0xfffff07f;
21800 newval |= (value & 0x1f) << 7;
21801 md_number_to_chars (buf, newval, INSN_SIZE);
21804 case BFD_RELOC_ARM_T32_IMMEDIATE:
21805 case BFD_RELOC_ARM_T32_ADD_IMM:
21806 case BFD_RELOC_ARM_T32_IMM12:
21807 case BFD_RELOC_ARM_T32_ADD_PC12:
21808 /* We claim that this fixup has been processed here,
21809 even if in fact we generate an error because we do
21810 not have a reloc for it, so tc_gen_reloc will reject it. */
21814 && ! S_IS_DEFINED (fixP->fx_addsy))
21816 as_bad_where (fixP->fx_file, fixP->fx_line,
21817 _("undefined symbol %s used as an immediate value"),
21818 S_GET_NAME (fixP->fx_addsy));
21822 newval = md_chars_to_number (buf, THUMB_SIZE);
21824 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21827 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21828 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21830 newimm = encode_thumb32_immediate (value);
21831 if (newimm == (unsigned int) FAIL)
21832 newimm = thumb32_negate_data_op (&newval, value);
21834 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21835 && newimm == (unsigned int) FAIL)
21837 /* Turn add/sum into addw/subw. */
21838 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21839 newval = (newval & 0xfeffffff) | 0x02000000;
21840 /* No flat 12-bit imm encoding for addsw/subsw. */
21841 if ((newval & 0x00100000) == 0)
21843 /* 12 bit immediate for addw/subw. */
21847 newval ^= 0x00a00000;
21850 newimm = (unsigned int) FAIL;
21856 if (newimm == (unsigned int)FAIL)
21858 as_bad_where (fixP->fx_file, fixP->fx_line,
21859 _("invalid constant (%lx) after fixup"),
21860 (unsigned long) value);
21864 newval |= (newimm & 0x800) << 15;
21865 newval |= (newimm & 0x700) << 4;
21866 newval |= (newimm & 0x0ff);
21868 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21869 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21872 case BFD_RELOC_ARM_SMC:
21873 if (((unsigned long) value) > 0xffff)
21874 as_bad_where (fixP->fx_file, fixP->fx_line,
21875 _("invalid smc expression"));
21876 newval = md_chars_to_number (buf, INSN_SIZE);
21877 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21878 md_number_to_chars (buf, newval, INSN_SIZE);
21881 case BFD_RELOC_ARM_HVC:
21882 if (((unsigned long) value) > 0xffff)
21883 as_bad_where (fixP->fx_file, fixP->fx_line,
21884 _("invalid hvc expression"));
21885 newval = md_chars_to_number (buf, INSN_SIZE);
21886 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21887 md_number_to_chars (buf, newval, INSN_SIZE);
21890 case BFD_RELOC_ARM_SWI:
21891 if (fixP->tc_fix_data != 0)
21893 if (((unsigned long) value) > 0xff)
21894 as_bad_where (fixP->fx_file, fixP->fx_line,
21895 _("invalid swi expression"));
21896 newval = md_chars_to_number (buf, THUMB_SIZE);
21898 md_number_to_chars (buf, newval, THUMB_SIZE);
21902 if (((unsigned long) value) > 0x00ffffff)
21903 as_bad_where (fixP->fx_file, fixP->fx_line,
21904 _("invalid swi expression"));
21905 newval = md_chars_to_number (buf, INSN_SIZE);
21907 md_number_to_chars (buf, newval, INSN_SIZE);
21911 case BFD_RELOC_ARM_MULTI:
21912 if (((unsigned long) value) > 0xffff)
21913 as_bad_where (fixP->fx_file, fixP->fx_line,
21914 _("invalid expression in load/store multiple"));
21915 newval = value | md_chars_to_number (buf, INSN_SIZE);
21916 md_number_to_chars (buf, newval, INSN_SIZE);
21920 case BFD_RELOC_ARM_PCREL_CALL:
21922 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21924 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21925 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21926 && THUMB_IS_FUNC (fixP->fx_addsy))
21927 /* Flip the bl to blx. This is a simple flip
21928 bit here because we generate PCREL_CALL for
21929 unconditional bls. */
21931 newval = md_chars_to_number (buf, INSN_SIZE);
21932 newval = newval | 0x10000000;
21933 md_number_to_chars (buf, newval, INSN_SIZE);
21939 goto arm_branch_common;
21941 case BFD_RELOC_ARM_PCREL_JUMP:
21942 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21944 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21945 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21946 && THUMB_IS_FUNC (fixP->fx_addsy))
21948 /* This would map to a bl<cond>, b<cond>,
21949 b<always> to a Thumb function. We
21950 need to force a relocation for this particular
21952 newval = md_chars_to_number (buf, INSN_SIZE);
21956 case BFD_RELOC_ARM_PLT32:
21958 case BFD_RELOC_ARM_PCREL_BRANCH:
21960 goto arm_branch_common;
21962 case BFD_RELOC_ARM_PCREL_BLX:
21965 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21967 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21968 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21969 && ARM_IS_FUNC (fixP->fx_addsy))
21971 /* Flip the blx to a bl and warn. */
21972 const char *name = S_GET_NAME (fixP->fx_addsy);
21973 newval = 0xeb000000;
21974 as_warn_where (fixP->fx_file, fixP->fx_line,
21975 _("blx to '%s' an ARM ISA state function changed to bl"),
21977 md_number_to_chars (buf, newval, INSN_SIZE);
21983 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21984 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21988 /* We are going to store value (shifted right by two) in the
21989 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21990 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21991 also be be clear. */
21993 as_bad_where (fixP->fx_file, fixP->fx_line,
21994 _("misaligned branch destination"));
21995 if ((value & (offsetT)0xfe000000) != (offsetT)0
21996 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21997 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21999 if (fixP->fx_done || !seg->use_rela_p)
22001 newval = md_chars_to_number (buf, INSN_SIZE);
22002 newval |= (value >> 2) & 0x00ffffff;
22003 /* Set the H bit on BLX instructions. */
22007 newval |= 0x01000000;
22009 newval &= ~0x01000000;
22011 md_number_to_chars (buf, newval, INSN_SIZE);
22015 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
22016 /* CBZ can only branch forward. */
22018 /* Attempts to use CBZ to branch to the next instruction
22019 (which, strictly speaking, are prohibited) will be turned into
22022 FIXME: It may be better to remove the instruction completely and
22023 perform relaxation. */
22026 newval = md_chars_to_number (buf, THUMB_SIZE);
22027 newval = 0xbf00; /* NOP encoding T1 */
22028 md_number_to_chars (buf, newval, THUMB_SIZE);
22033 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22035 if (fixP->fx_done || !seg->use_rela_p)
22037 newval = md_chars_to_number (buf, THUMB_SIZE);
22038 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
22039 md_number_to_chars (buf, newval, THUMB_SIZE);
22044 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
22045 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
22046 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22048 if (fixP->fx_done || !seg->use_rela_p)
22050 newval = md_chars_to_number (buf, THUMB_SIZE);
22051 newval |= (value & 0x1ff) >> 1;
22052 md_number_to_chars (buf, newval, THUMB_SIZE);
22056 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
22057 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
22058 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22060 if (fixP->fx_done || !seg->use_rela_p)
22062 newval = md_chars_to_number (buf, THUMB_SIZE);
22063 newval |= (value & 0xfff) >> 1;
22064 md_number_to_chars (buf, newval, THUMB_SIZE);
22068 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22070 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22071 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22072 && ARM_IS_FUNC (fixP->fx_addsy)
22073 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22075 /* Force a relocation for a branch 20 bits wide. */
22078 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
22079 as_bad_where (fixP->fx_file, fixP->fx_line,
22080 _("conditional branch out of range"));
22082 if (fixP->fx_done || !seg->use_rela_p)
22085 addressT S, J1, J2, lo, hi;
22087 S = (value & 0x00100000) >> 20;
22088 J2 = (value & 0x00080000) >> 19;
22089 J1 = (value & 0x00040000) >> 18;
22090 hi = (value & 0x0003f000) >> 12;
22091 lo = (value & 0x00000ffe) >> 1;
22093 newval = md_chars_to_number (buf, THUMB_SIZE);
22094 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22095 newval |= (S << 10) | hi;
22096 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22097 md_number_to_chars (buf, newval, THUMB_SIZE);
22098 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22102 case BFD_RELOC_THUMB_PCREL_BLX:
22103 /* If there is a blx from a thumb state function to
22104 another thumb function flip this to a bl and warn
22108 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22109 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22110 && THUMB_IS_FUNC (fixP->fx_addsy))
22112 const char *name = S_GET_NAME (fixP->fx_addsy);
22113 as_warn_where (fixP->fx_file, fixP->fx_line,
22114 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22116 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22117 newval = newval | 0x1000;
22118 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22119 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22124 goto thumb_bl_common;
22126 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22127 /* A bl from Thumb state ISA to an internal ARM state function
22128 is converted to a blx. */
22130 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22131 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22132 && ARM_IS_FUNC (fixP->fx_addsy)
22133 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22135 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22136 newval = newval & ~0x1000;
22137 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22138 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22144 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22145 /* For a BLX instruction, make sure that the relocation is rounded up
22146 to a word boundary. This follows the semantics of the instruction
22147 which specifies that bit 1 of the target address will come from bit
22148 1 of the base address. */
22149 value = (value + 3) & ~ 3;
22152 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22153 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22154 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22157 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22159 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22160 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22161 else if ((value & ~0x1ffffff)
22162 && ((value & ~0x1ffffff) != ~0x1ffffff))
22163 as_bad_where (fixP->fx_file, fixP->fx_line,
22164 _("Thumb2 branch out of range"));
22167 if (fixP->fx_done || !seg->use_rela_p)
22168 encode_thumb2_b_bl_offset (buf, value);
22172 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22173 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22174 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22176 if (fixP->fx_done || !seg->use_rela_p)
22177 encode_thumb2_b_bl_offset (buf, value);
22182 if (fixP->fx_done || !seg->use_rela_p)
22183 md_number_to_chars (buf, value, 1);
22187 if (fixP->fx_done || !seg->use_rela_p)
22188 md_number_to_chars (buf, value, 2);
22192 case BFD_RELOC_ARM_TLS_CALL:
22193 case BFD_RELOC_ARM_THM_TLS_CALL:
22194 case BFD_RELOC_ARM_TLS_DESCSEQ:
22195 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22196 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22199 case BFD_RELOC_ARM_TLS_GOTDESC:
22200 case BFD_RELOC_ARM_TLS_GD32:
22201 case BFD_RELOC_ARM_TLS_LE32:
22202 case BFD_RELOC_ARM_TLS_IE32:
22203 case BFD_RELOC_ARM_TLS_LDM32:
22204 case BFD_RELOC_ARM_TLS_LDO32:
22205 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22208 case BFD_RELOC_ARM_GOT32:
22209 case BFD_RELOC_ARM_GOTOFF:
22210 if (fixP->fx_done || !seg->use_rela_p)
22211 md_number_to_chars (buf, 0, 4);
22214 case BFD_RELOC_ARM_GOT_PREL:
22215 if (fixP->fx_done || !seg->use_rela_p)
22216 md_number_to_chars (buf, value, 4);
22219 case BFD_RELOC_ARM_TARGET2:
22220 /* TARGET2 is not partial-inplace, so we need to write the
22221 addend here for REL targets, because it won't be written out
22222 during reloc processing later. */
22223 if (fixP->fx_done || !seg->use_rela_p)
22224 md_number_to_chars (buf, fixP->fx_offset, 4);
22228 case BFD_RELOC_RVA:
22230 case BFD_RELOC_ARM_TARGET1:
22231 case BFD_RELOC_ARM_ROSEGREL32:
22232 case BFD_RELOC_ARM_SBREL32:
22233 case BFD_RELOC_32_PCREL:
22235 case BFD_RELOC_32_SECREL:
22237 if (fixP->fx_done || !seg->use_rela_p)
22239 /* For WinCE we only do this for pcrel fixups. */
22240 if (fixP->fx_done || fixP->fx_pcrel)
22242 md_number_to_chars (buf, value, 4);
22246 case BFD_RELOC_ARM_PREL31:
22247 if (fixP->fx_done || !seg->use_rela_p)
22249 newval = md_chars_to_number (buf, 4) & 0x80000000;
22250 if ((value ^ (value >> 1)) & 0x40000000)
22252 as_bad_where (fixP->fx_file, fixP->fx_line,
22253 _("rel31 relocation overflow"));
22255 newval |= value & 0x7fffffff;
22256 md_number_to_chars (buf, newval, 4);
22261 case BFD_RELOC_ARM_CP_OFF_IMM:
22262 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22263 if (value < -1023 || value > 1023 || (value & 3))
22264 as_bad_where (fixP->fx_file, fixP->fx_line,
22265 _("co-processor offset out of range"));
22270 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22271 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22272 newval = md_chars_to_number (buf, INSN_SIZE);
22274 newval = get_thumb32_insn (buf);
22276 newval &= 0xffffff00;
22279 newval &= 0xff7fff00;
22280 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22282 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22283 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22284 md_number_to_chars (buf, newval, INSN_SIZE);
22286 put_thumb32_insn (buf, newval);
22289 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
22290 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
22291 if (value < -255 || value > 255)
22292 as_bad_where (fixP->fx_file, fixP->fx_line,
22293 _("co-processor offset out of range"));
22295 goto cp_off_common;
22297 case BFD_RELOC_ARM_THUMB_OFFSET:
22298 newval = md_chars_to_number (buf, THUMB_SIZE);
22299 /* Exactly what ranges, and where the offset is inserted depends
22300 on the type of instruction, we can establish this from the
22302 switch (newval >> 12)
22304 case 4: /* PC load. */
22305 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22306 forced to zero for these loads; md_pcrel_from has already
22307 compensated for this. */
22309 as_bad_where (fixP->fx_file, fixP->fx_line,
22310 _("invalid offset, target not word aligned (0x%08lX)"),
22311 (((unsigned long) fixP->fx_frag->fr_address
22312 + (unsigned long) fixP->fx_where) & ~3)
22313 + (unsigned long) value);
22315 if (value & ~0x3fc)
22316 as_bad_where (fixP->fx_file, fixP->fx_line,
22317 _("invalid offset, value too big (0x%08lX)"),
22320 newval |= value >> 2;
22323 case 9: /* SP load/store. */
22324 if (value & ~0x3fc)
22325 as_bad_where (fixP->fx_file, fixP->fx_line,
22326 _("invalid offset, value too big (0x%08lX)"),
22328 newval |= value >> 2;
22331 case 6: /* Word load/store. */
22333 as_bad_where (fixP->fx_file, fixP->fx_line,
22334 _("invalid offset, value too big (0x%08lX)"),
22336 newval |= value << 4; /* 6 - 2. */
22339 case 7: /* Byte load/store. */
22341 as_bad_where (fixP->fx_file, fixP->fx_line,
22342 _("invalid offset, value too big (0x%08lX)"),
22344 newval |= value << 6;
22347 case 8: /* Halfword load/store. */
22349 as_bad_where (fixP->fx_file, fixP->fx_line,
22350 _("invalid offset, value too big (0x%08lX)"),
22352 newval |= value << 5; /* 6 - 1. */
22356 as_bad_where (fixP->fx_file, fixP->fx_line,
22357 "Unable to process relocation for thumb opcode: %lx",
22358 (unsigned long) newval);
22361 md_number_to_chars (buf, newval, THUMB_SIZE);
22364 case BFD_RELOC_ARM_THUMB_ADD:
22365 /* This is a complicated relocation, since we use it for all of
22366 the following immediate relocations:
22370 9bit ADD/SUB SP word-aligned
22371 10bit ADD PC/SP word-aligned
22373 The type of instruction being processed is encoded in the
22380 newval = md_chars_to_number (buf, THUMB_SIZE);
22382 int rd = (newval >> 4) & 0xf;
22383 int rs = newval & 0xf;
22384 int subtract = !!(newval & 0x8000);
22386 /* Check for HI regs, only very restricted cases allowed:
22387 Adjusting SP, and using PC or SP to get an address. */
22388 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22389 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22390 as_bad_where (fixP->fx_file, fixP->fx_line,
22391 _("invalid Hi register with immediate"));
22393 /* If value is negative, choose the opposite instruction. */
22397 subtract = !subtract;
22399 as_bad_where (fixP->fx_file, fixP->fx_line,
22400 _("immediate value out of range"));
22405 if (value & ~0x1fc)
22406 as_bad_where (fixP->fx_file, fixP->fx_line,
22407 _("invalid immediate for stack address calculation"));
22408 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22409 newval |= value >> 2;
22411 else if (rs == REG_PC || rs == REG_SP)
22413 if (subtract || value & ~0x3fc)
22414 as_bad_where (fixP->fx_file, fixP->fx_line,
22415 _("invalid immediate for address calculation (value = 0x%08lX)"),
22416 (unsigned long) value);
22417 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22419 newval |= value >> 2;
22424 as_bad_where (fixP->fx_file, fixP->fx_line,
22425 _("immediate value out of range"));
22426 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22427 newval |= (rd << 8) | value;
22432 as_bad_where (fixP->fx_file, fixP->fx_line,
22433 _("immediate value out of range"));
22434 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22435 newval |= rd | (rs << 3) | (value << 6);
22438 md_number_to_chars (buf, newval, THUMB_SIZE);
22441 case BFD_RELOC_ARM_THUMB_IMM:
22442 newval = md_chars_to_number (buf, THUMB_SIZE);
22443 if (value < 0 || value > 255)
22444 as_bad_where (fixP->fx_file, fixP->fx_line,
22445 _("invalid immediate: %ld is out of range"),
22448 md_number_to_chars (buf, newval, THUMB_SIZE);
22451 case BFD_RELOC_ARM_THUMB_SHIFT:
22452 /* 5bit shift value (0..32). LSL cannot take 32. */
22453 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22454 temp = newval & 0xf800;
22455 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22456 as_bad_where (fixP->fx_file, fixP->fx_line,
22457 _("invalid shift value: %ld"), (long) value);
22458 /* Shifts of zero must be encoded as LSL. */
22460 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22461 /* Shifts of 32 are encoded as zero. */
22462 else if (value == 32)
22464 newval |= value << 6;
22465 md_number_to_chars (buf, newval, THUMB_SIZE);
22468 case BFD_RELOC_VTABLE_INHERIT:
22469 case BFD_RELOC_VTABLE_ENTRY:
22473 case BFD_RELOC_ARM_MOVW:
22474 case BFD_RELOC_ARM_MOVT:
22475 case BFD_RELOC_ARM_THUMB_MOVW:
22476 case BFD_RELOC_ARM_THUMB_MOVT:
22477 if (fixP->fx_done || !seg->use_rela_p)
22479 /* REL format relocations are limited to a 16-bit addend. */
22480 if (!fixP->fx_done)
22482 if (value < -0x8000 || value > 0x7fff)
22483 as_bad_where (fixP->fx_file, fixP->fx_line,
22484 _("offset out of range"));
22486 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22487 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22492 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22493 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22495 newval = get_thumb32_insn (buf);
22496 newval &= 0xfbf08f00;
22497 newval |= (value & 0xf000) << 4;
22498 newval |= (value & 0x0800) << 15;
22499 newval |= (value & 0x0700) << 4;
22500 newval |= (value & 0x00ff);
22501 put_thumb32_insn (buf, newval);
22505 newval = md_chars_to_number (buf, 4);
22506 newval &= 0xfff0f000;
22507 newval |= value & 0x0fff;
22508 newval |= (value & 0xf000) << 4;
22509 md_number_to_chars (buf, newval, 4);
22514 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22515 case BFD_RELOC_ARM_ALU_PC_G0:
22516 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22517 case BFD_RELOC_ARM_ALU_PC_G1:
22518 case BFD_RELOC_ARM_ALU_PC_G2:
22519 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22520 case BFD_RELOC_ARM_ALU_SB_G0:
22521 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22522 case BFD_RELOC_ARM_ALU_SB_G1:
22523 case BFD_RELOC_ARM_ALU_SB_G2:
22524 gas_assert (!fixP->fx_done);
22525 if (!seg->use_rela_p)
22528 bfd_vma encoded_addend;
22529 bfd_vma addend_abs = abs (value);
22531 /* Check that the absolute value of the addend can be
22532 expressed as an 8-bit constant plus a rotation. */
22533 encoded_addend = encode_arm_immediate (addend_abs);
22534 if (encoded_addend == (unsigned int) FAIL)
22535 as_bad_where (fixP->fx_file, fixP->fx_line,
22536 _("the offset 0x%08lX is not representable"),
22537 (unsigned long) addend_abs);
22539 /* Extract the instruction. */
22540 insn = md_chars_to_number (buf, INSN_SIZE);
22542 /* If the addend is positive, use an ADD instruction.
22543 Otherwise use a SUB. Take care not to destroy the S bit. */
22544 insn &= 0xff1fffff;
22550 /* Place the encoded addend into the first 12 bits of the
22552 insn &= 0xfffff000;
22553 insn |= encoded_addend;
22555 /* Update the instruction. */
22556 md_number_to_chars (buf, insn, INSN_SIZE);
22560 case BFD_RELOC_ARM_LDR_PC_G0:
22561 case BFD_RELOC_ARM_LDR_PC_G1:
22562 case BFD_RELOC_ARM_LDR_PC_G2:
22563 case BFD_RELOC_ARM_LDR_SB_G0:
22564 case BFD_RELOC_ARM_LDR_SB_G1:
22565 case BFD_RELOC_ARM_LDR_SB_G2:
22566 gas_assert (!fixP->fx_done);
22567 if (!seg->use_rela_p)
22570 bfd_vma addend_abs = abs (value);
22572 /* Check that the absolute value of the addend can be
22573 encoded in 12 bits. */
22574 if (addend_abs >= 0x1000)
22575 as_bad_where (fixP->fx_file, fixP->fx_line,
22576 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22577 (unsigned long) addend_abs);
22579 /* Extract the instruction. */
22580 insn = md_chars_to_number (buf, INSN_SIZE);
22582 /* If the addend is negative, clear bit 23 of the instruction.
22583 Otherwise set it. */
22585 insn &= ~(1 << 23);
22589 /* Place the absolute value of the addend into the first 12 bits
22590 of the instruction. */
22591 insn &= 0xfffff000;
22592 insn |= addend_abs;
22594 /* Update the instruction. */
22595 md_number_to_chars (buf, insn, INSN_SIZE);
22599 case BFD_RELOC_ARM_LDRS_PC_G0:
22600 case BFD_RELOC_ARM_LDRS_PC_G1:
22601 case BFD_RELOC_ARM_LDRS_PC_G2:
22602 case BFD_RELOC_ARM_LDRS_SB_G0:
22603 case BFD_RELOC_ARM_LDRS_SB_G1:
22604 case BFD_RELOC_ARM_LDRS_SB_G2:
22605 gas_assert (!fixP->fx_done);
22606 if (!seg->use_rela_p)
22609 bfd_vma addend_abs = abs (value);
22611 /* Check that the absolute value of the addend can be
22612 encoded in 8 bits. */
22613 if (addend_abs >= 0x100)
22614 as_bad_where (fixP->fx_file, fixP->fx_line,
22615 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22616 (unsigned long) addend_abs);
22618 /* Extract the instruction. */
22619 insn = md_chars_to_number (buf, INSN_SIZE);
22621 /* If the addend is negative, clear bit 23 of the instruction.
22622 Otherwise set it. */
22624 insn &= ~(1 << 23);
22628 /* Place the first four bits of the absolute value of the addend
22629 into the first 4 bits of the instruction, and the remaining
22630 four into bits 8 .. 11. */
22631 insn &= 0xfffff0f0;
22632 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22634 /* Update the instruction. */
22635 md_number_to_chars (buf, insn, INSN_SIZE);
22639 case BFD_RELOC_ARM_LDC_PC_G0:
22640 case BFD_RELOC_ARM_LDC_PC_G1:
22641 case BFD_RELOC_ARM_LDC_PC_G2:
22642 case BFD_RELOC_ARM_LDC_SB_G0:
22643 case BFD_RELOC_ARM_LDC_SB_G1:
22644 case BFD_RELOC_ARM_LDC_SB_G2:
22645 gas_assert (!fixP->fx_done);
22646 if (!seg->use_rela_p)
22649 bfd_vma addend_abs = abs (value);
22651 /* Check that the absolute value of the addend is a multiple of
22652 four and, when divided by four, fits in 8 bits. */
22653 if (addend_abs & 0x3)
22654 as_bad_where (fixP->fx_file, fixP->fx_line,
22655 _("bad offset 0x%08lX (must be word-aligned)"),
22656 (unsigned long) addend_abs);
22658 if ((addend_abs >> 2) > 0xff)
22659 as_bad_where (fixP->fx_file, fixP->fx_line,
22660 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22661 (unsigned long) addend_abs);
22663 /* Extract the instruction. */
22664 insn = md_chars_to_number (buf, INSN_SIZE);
22666 /* If the addend is negative, clear bit 23 of the instruction.
22667 Otherwise set it. */
22669 insn &= ~(1 << 23);
22673 /* Place the addend (divided by four) into the first eight
22674 bits of the instruction. */
22675 insn &= 0xfffffff0;
22676 insn |= addend_abs >> 2;
22678 /* Update the instruction. */
22679 md_number_to_chars (buf, insn, INSN_SIZE);
22683 case BFD_RELOC_ARM_V4BX:
22684 /* This will need to go in the object file. */
22688 case BFD_RELOC_UNUSED:
22690 as_bad_where (fixP->fx_file, fixP->fx_line,
22691 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22695 /* Translate internal representation of relocation info to BFD target
22699 tc_gen_reloc (asection *section, fixS *fixp)
22702 bfd_reloc_code_real_type code;
22704 reloc = (arelent *) xmalloc (sizeof (arelent));
22706 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
22707 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22708 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
22710 if (fixp->fx_pcrel)
22712 if (section->use_rela_p)
22713 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22715 fixp->fx_offset = reloc->address;
22717 reloc->addend = fixp->fx_offset;
22719 switch (fixp->fx_r_type)
22722 if (fixp->fx_pcrel)
22724 code = BFD_RELOC_8_PCREL;
22729 if (fixp->fx_pcrel)
22731 code = BFD_RELOC_16_PCREL;
22736 if (fixp->fx_pcrel)
22738 code = BFD_RELOC_32_PCREL;
22742 case BFD_RELOC_ARM_MOVW:
22743 if (fixp->fx_pcrel)
22745 code = BFD_RELOC_ARM_MOVW_PCREL;
22749 case BFD_RELOC_ARM_MOVT:
22750 if (fixp->fx_pcrel)
22752 code = BFD_RELOC_ARM_MOVT_PCREL;
22756 case BFD_RELOC_ARM_THUMB_MOVW:
22757 if (fixp->fx_pcrel)
22759 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22763 case BFD_RELOC_ARM_THUMB_MOVT:
22764 if (fixp->fx_pcrel)
22766 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22770 case BFD_RELOC_NONE:
22771 case BFD_RELOC_ARM_PCREL_BRANCH:
22772 case BFD_RELOC_ARM_PCREL_BLX:
22773 case BFD_RELOC_RVA:
22774 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22775 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22776 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22777 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22778 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22779 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22780 case BFD_RELOC_VTABLE_ENTRY:
22781 case BFD_RELOC_VTABLE_INHERIT:
22783 case BFD_RELOC_32_SECREL:
22785 code = fixp->fx_r_type;
22788 case BFD_RELOC_THUMB_PCREL_BLX:
22790 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22791 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22794 code = BFD_RELOC_THUMB_PCREL_BLX;
22797 case BFD_RELOC_ARM_LITERAL:
22798 case BFD_RELOC_ARM_HWLITERAL:
22799 /* If this is called then the a literal has
22800 been referenced across a section boundary. */
22801 as_bad_where (fixp->fx_file, fixp->fx_line,
22802 _("literal referenced across section boundary"));
22806 case BFD_RELOC_ARM_TLS_CALL:
22807 case BFD_RELOC_ARM_THM_TLS_CALL:
22808 case BFD_RELOC_ARM_TLS_DESCSEQ:
22809 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22810 case BFD_RELOC_ARM_GOT32:
22811 case BFD_RELOC_ARM_GOTOFF:
22812 case BFD_RELOC_ARM_GOT_PREL:
22813 case BFD_RELOC_ARM_PLT32:
22814 case BFD_RELOC_ARM_TARGET1:
22815 case BFD_RELOC_ARM_ROSEGREL32:
22816 case BFD_RELOC_ARM_SBREL32:
22817 case BFD_RELOC_ARM_PREL31:
22818 case BFD_RELOC_ARM_TARGET2:
22819 case BFD_RELOC_ARM_TLS_LE32:
22820 case BFD_RELOC_ARM_TLS_LDO32:
22821 case BFD_RELOC_ARM_PCREL_CALL:
22822 case BFD_RELOC_ARM_PCREL_JUMP:
22823 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22824 case BFD_RELOC_ARM_ALU_PC_G0:
22825 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22826 case BFD_RELOC_ARM_ALU_PC_G1:
22827 case BFD_RELOC_ARM_ALU_PC_G2:
22828 case BFD_RELOC_ARM_LDR_PC_G0:
22829 case BFD_RELOC_ARM_LDR_PC_G1:
22830 case BFD_RELOC_ARM_LDR_PC_G2:
22831 case BFD_RELOC_ARM_LDRS_PC_G0:
22832 case BFD_RELOC_ARM_LDRS_PC_G1:
22833 case BFD_RELOC_ARM_LDRS_PC_G2:
22834 case BFD_RELOC_ARM_LDC_PC_G0:
22835 case BFD_RELOC_ARM_LDC_PC_G1:
22836 case BFD_RELOC_ARM_LDC_PC_G2:
22837 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22838 case BFD_RELOC_ARM_ALU_SB_G0:
22839 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22840 case BFD_RELOC_ARM_ALU_SB_G1:
22841 case BFD_RELOC_ARM_ALU_SB_G2:
22842 case BFD_RELOC_ARM_LDR_SB_G0:
22843 case BFD_RELOC_ARM_LDR_SB_G1:
22844 case BFD_RELOC_ARM_LDR_SB_G2:
22845 case BFD_RELOC_ARM_LDRS_SB_G0:
22846 case BFD_RELOC_ARM_LDRS_SB_G1:
22847 case BFD_RELOC_ARM_LDRS_SB_G2:
22848 case BFD_RELOC_ARM_LDC_SB_G0:
22849 case BFD_RELOC_ARM_LDC_SB_G1:
22850 case BFD_RELOC_ARM_LDC_SB_G2:
22851 case BFD_RELOC_ARM_V4BX:
22852 code = fixp->fx_r_type;
22855 case BFD_RELOC_ARM_TLS_GOTDESC:
22856 case BFD_RELOC_ARM_TLS_GD32:
22857 case BFD_RELOC_ARM_TLS_IE32:
22858 case BFD_RELOC_ARM_TLS_LDM32:
22859 /* BFD will include the symbol's address in the addend.
22860 But we don't want that, so subtract it out again here. */
22861 if (!S_IS_COMMON (fixp->fx_addsy))
22862 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22863 code = fixp->fx_r_type;
22867 case BFD_RELOC_ARM_IMMEDIATE:
22868 as_bad_where (fixp->fx_file, fixp->fx_line,
22869 _("internal relocation (type: IMMEDIATE) not fixed up"));
22872 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22873 as_bad_where (fixp->fx_file, fixp->fx_line,
22874 _("ADRL used for a symbol not defined in the same file"));
22877 case BFD_RELOC_ARM_OFFSET_IMM:
22878 if (section->use_rela_p)
22880 code = fixp->fx_r_type;
22884 if (fixp->fx_addsy != NULL
22885 && !S_IS_DEFINED (fixp->fx_addsy)
22886 && S_IS_LOCAL (fixp->fx_addsy))
22888 as_bad_where (fixp->fx_file, fixp->fx_line,
22889 _("undefined local label `%s'"),
22890 S_GET_NAME (fixp->fx_addsy));
22894 as_bad_where (fixp->fx_file, fixp->fx_line,
22895 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22902 switch (fixp->fx_r_type)
22904 case BFD_RELOC_NONE: type = "NONE"; break;
22905 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22906 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22907 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22908 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22909 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22910 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22911 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22912 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22913 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22914 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22915 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22916 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22917 default: type = _("<unknown>"); break;
22919 as_bad_where (fixp->fx_file, fixp->fx_line,
22920 _("cannot represent %s relocation in this object file format"),
22927 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22929 && fixp->fx_addsy == GOT_symbol)
22931 code = BFD_RELOC_ARM_GOTPC;
22932 reloc->addend = fixp->fx_offset = reloc->address;
22936 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22938 if (reloc->howto == NULL)
22940 as_bad_where (fixp->fx_file, fixp->fx_line,
22941 _("cannot represent %s relocation in this object file format"),
22942 bfd_get_reloc_code_name (code));
22946 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22947 vtable entry to be used in the relocation's section offset. */
22948 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22949 reloc->address = fixp->fx_offset;
22954 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22957 cons_fix_new_arm (fragS * frag,
22962 bfd_reloc_code_real_type type;
22966 FIXME: @@ Should look at CPU word size. */
22970 type = BFD_RELOC_8;
22973 type = BFD_RELOC_16;
22977 type = BFD_RELOC_32;
22980 type = BFD_RELOC_64;
22985 if (exp->X_op == O_secrel)
22987 exp->X_op = O_symbol;
22988 type = BFD_RELOC_32_SECREL;
22992 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22995 #if defined (OBJ_COFF)
22997 arm_validate_fix (fixS * fixP)
22999 /* If the destination of the branch is a defined symbol which does not have
23000 the THUMB_FUNC attribute, then we must be calling a function which has
23001 the (interfacearm) attribute. We look for the Thumb entry point to that
23002 function and change the branch to refer to that function instead. */
23003 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
23004 && fixP->fx_addsy != NULL
23005 && S_IS_DEFINED (fixP->fx_addsy)
23006 && ! THUMB_IS_FUNC (fixP->fx_addsy))
23008 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
23015 arm_force_relocation (struct fix * fixp)
23017 #if defined (OBJ_COFF) && defined (TE_PE)
23018 if (fixp->fx_r_type == BFD_RELOC_RVA)
23022 /* In case we have a call or a branch to a function in ARM ISA mode from
23023 a thumb function or vice-versa force the relocation. These relocations
23024 are cleared off for some cores that might have blx and simple transformations
23028 switch (fixp->fx_r_type)
23030 case BFD_RELOC_ARM_PCREL_JUMP:
23031 case BFD_RELOC_ARM_PCREL_CALL:
23032 case BFD_RELOC_THUMB_PCREL_BLX:
23033 if (THUMB_IS_FUNC (fixp->fx_addsy))
23037 case BFD_RELOC_ARM_PCREL_BLX:
23038 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23039 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23040 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23041 if (ARM_IS_FUNC (fixp->fx_addsy))
23050 /* Resolve these relocations even if the symbol is extern or weak.
23051 Technically this is probably wrong due to symbol preemption.
23052 In practice these relocations do not have enough range to be useful
23053 at dynamic link time, and some code (e.g. in the Linux kernel)
23054 expects these references to be resolved. */
23055 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
23056 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
23057 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
23058 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
23059 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23060 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
23061 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
23062 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
23063 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23064 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
23065 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
23066 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
23067 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
23068 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
23071 /* Always leave these relocations for the linker. */
23072 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23073 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23074 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23077 /* Always generate relocations against function symbols. */
23078 if (fixp->fx_r_type == BFD_RELOC_32
23080 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
23083 return generic_force_reloc (fixp);
23086 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23087 /* Relocations against function names must be left unadjusted,
23088 so that the linker can use this information to generate interworking
23089 stubs. The MIPS version of this function
23090 also prevents relocations that are mips-16 specific, but I do not
23091 know why it does this.
23094 There is one other problem that ought to be addressed here, but
23095 which currently is not: Taking the address of a label (rather
23096 than a function) and then later jumping to that address. Such
23097 addresses also ought to have their bottom bit set (assuming that
23098 they reside in Thumb code), but at the moment they will not. */
23101 arm_fix_adjustable (fixS * fixP)
23103 if (fixP->fx_addsy == NULL)
23106 /* Preserve relocations against symbols with function type. */
23107 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
23110 if (THUMB_IS_FUNC (fixP->fx_addsy)
23111 && fixP->fx_subsy == NULL)
23114 /* We need the symbol name for the VTABLE entries. */
23115 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23116 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23119 /* Don't allow symbols to be discarded on GOT related relocs. */
23120 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23121 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23122 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23123 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23124 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23125 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23126 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23127 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
23128 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23129 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23130 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23131 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23132 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
23133 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
23136 /* Similarly for group relocations. */
23137 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23138 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23139 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23142 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23143 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23144 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23145 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23146 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23147 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23148 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23149 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23150 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
23155 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23160 elf32_arm_target_format (void)
23163 return (target_big_endian
23164 ? "elf32-bigarm-symbian"
23165 : "elf32-littlearm-symbian");
23166 #elif defined (TE_VXWORKS)
23167 return (target_big_endian
23168 ? "elf32-bigarm-vxworks"
23169 : "elf32-littlearm-vxworks");
23170 #elif defined (TE_NACL)
23171 return (target_big_endian
23172 ? "elf32-bigarm-nacl"
23173 : "elf32-littlearm-nacl");
23175 if (target_big_endian)
23176 return "elf32-bigarm";
23178 return "elf32-littlearm";
23183 armelf_frob_symbol (symbolS * symp,
23186 elf_frob_symbol (symp, puntp);
23190 /* MD interface: Finalization. */
23195 literal_pool * pool;
23197 /* Ensure that all the IT blocks are properly closed. */
23198 check_it_blocks_finished ();
23200 for (pool = list_of_pools; pool; pool = pool->next)
23202 /* Put it at the end of the relevant section. */
23203 subseg_set (pool->section, pool->sub_section);
23205 arm_elf_change_section ();
23212 /* Remove any excess mapping symbols generated for alignment frags in
23213 SEC. We may have created a mapping symbol before a zero byte
23214 alignment; remove it if there's a mapping symbol after the
23217 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23218 void *dummy ATTRIBUTE_UNUSED)
23220 segment_info_type *seginfo = seg_info (sec);
23223 if (seginfo == NULL || seginfo->frchainP == NULL)
23226 for (fragp = seginfo->frchainP->frch_root;
23228 fragp = fragp->fr_next)
23230 symbolS *sym = fragp->tc_frag_data.last_map;
23231 fragS *next = fragp->fr_next;
23233 /* Variable-sized frags have been converted to fixed size by
23234 this point. But if this was variable-sized to start with,
23235 there will be a fixed-size frag after it. So don't handle
23237 if (sym == NULL || next == NULL)
23240 if (S_GET_VALUE (sym) < next->fr_address)
23241 /* Not at the end of this frag. */
23243 know (S_GET_VALUE (sym) == next->fr_address);
23247 if (next->tc_frag_data.first_map != NULL)
23249 /* Next frag starts with a mapping symbol. Discard this
23251 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23255 if (next->fr_next == NULL)
23257 /* This mapping symbol is at the end of the section. Discard
23259 know (next->fr_fix == 0 && next->fr_var == 0);
23260 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23264 /* As long as we have empty frags without any mapping symbols,
23266 /* If the next frag is non-empty and does not start with a
23267 mapping symbol, then this mapping symbol is required. */
23268 if (next->fr_address != next->fr_next->fr_address)
23271 next = next->fr_next;
23273 while (next != NULL);
23278 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23282 arm_adjust_symtab (void)
23287 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23289 if (ARM_IS_THUMB (sym))
23291 if (THUMB_IS_FUNC (sym))
23293 /* Mark the symbol as a Thumb function. */
23294 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23295 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23296 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
23298 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23299 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23301 as_bad (_("%s: unexpected function type: %d"),
23302 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23304 else switch (S_GET_STORAGE_CLASS (sym))
23307 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23310 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23313 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23321 if (ARM_IS_INTERWORK (sym))
23322 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
23329 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23331 if (ARM_IS_THUMB (sym))
23333 elf_symbol_type * elf_sym;
23335 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23336 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
23338 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23339 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
23341 /* If it's a .thumb_func, declare it as so,
23342 otherwise tag label as .code 16. */
23343 if (THUMB_IS_FUNC (sym))
23344 elf_sym->internal_elf_sym.st_target_internal
23345 = ST_BRANCH_TO_THUMB;
23346 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23347 elf_sym->internal_elf_sym.st_info =
23348 ELF_ST_INFO (bind, STT_ARM_16BIT);
23353 /* Remove any overlapping mapping symbols generated by alignment frags. */
23354 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
23355 /* Now do generic ELF adjustments. */
23356 elf_adjust_symtab ();
23360 /* MD interface: Initialization. */
23363 set_constant_flonums (void)
23367 for (i = 0; i < NUM_FLOAT_VALS; i++)
23368 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23372 /* Auto-select Thumb mode if it's the only available instruction set for the
23373 given architecture. */
23376 autoselect_thumb_from_cpu_variant (void)
23378 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23379 opcode_select (16);
23388 if ( (arm_ops_hsh = hash_new ()) == NULL
23389 || (arm_cond_hsh = hash_new ()) == NULL
23390 || (arm_shift_hsh = hash_new ()) == NULL
23391 || (arm_psr_hsh = hash_new ()) == NULL
23392 || (arm_v7m_psr_hsh = hash_new ()) == NULL
23393 || (arm_reg_hsh = hash_new ()) == NULL
23394 || (arm_reloc_hsh = hash_new ()) == NULL
23395 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
23396 as_fatal (_("virtual memory exhausted"));
23398 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
23399 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
23400 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
23401 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
23402 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
23403 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
23404 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
23405 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
23406 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
23407 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
23408 (void *) (v7m_psrs + i));
23409 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
23410 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
23412 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23414 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
23415 (void *) (barrier_opt_names + i));
23417 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23419 struct reloc_entry * entry = reloc_names + i;
23421 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23422 /* This makes encode_branch() use the EABI versions of this relocation. */
23423 entry->reloc = BFD_RELOC_UNUSED;
23425 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23429 set_constant_flonums ();
23431 /* Set the cpu variant based on the command-line options. We prefer
23432 -mcpu= over -march= if both are set (as for GCC); and we prefer
23433 -mfpu= over any other way of setting the floating point unit.
23434 Use of legacy options with new options are faulted. */
23437 if (mcpu_cpu_opt || march_cpu_opt)
23438 as_bad (_("use of old and new-style options to set CPU type"));
23440 mcpu_cpu_opt = legacy_cpu;
23442 else if (!mcpu_cpu_opt)
23443 mcpu_cpu_opt = march_cpu_opt;
23448 as_bad (_("use of old and new-style options to set FPU type"));
23450 mfpu_opt = legacy_fpu;
23452 else if (!mfpu_opt)
23454 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23455 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23456 /* Some environments specify a default FPU. If they don't, infer it
23457 from the processor. */
23459 mfpu_opt = mcpu_fpu_opt;
23461 mfpu_opt = march_fpu_opt;
23463 mfpu_opt = &fpu_default;
23469 if (mcpu_cpu_opt != NULL)
23470 mfpu_opt = &fpu_default;
23471 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
23472 mfpu_opt = &fpu_arch_vfp_v2;
23474 mfpu_opt = &fpu_arch_fpa;
23480 mcpu_cpu_opt = &cpu_default;
23481 selected_cpu = cpu_default;
23485 selected_cpu = *mcpu_cpu_opt;
23487 mcpu_cpu_opt = &arm_arch_any;
23490 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23492 autoselect_thumb_from_cpu_variant ();
23494 arm_arch_used = thumb_arch_used = arm_arch_none;
23496 #if defined OBJ_COFF || defined OBJ_ELF
23498 unsigned int flags = 0;
23500 #if defined OBJ_ELF
23501 flags = meabi_flags;
23503 switch (meabi_flags)
23505 case EF_ARM_EABI_UNKNOWN:
23507 /* Set the flags in the private structure. */
23508 if (uses_apcs_26) flags |= F_APCS26;
23509 if (support_interwork) flags |= F_INTERWORK;
23510 if (uses_apcs_float) flags |= F_APCS_FLOAT;
23511 if (pic_code) flags |= F_PIC;
23512 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
23513 flags |= F_SOFT_FLOAT;
23515 switch (mfloat_abi_opt)
23517 case ARM_FLOAT_ABI_SOFT:
23518 case ARM_FLOAT_ABI_SOFTFP:
23519 flags |= F_SOFT_FLOAT;
23522 case ARM_FLOAT_ABI_HARD:
23523 if (flags & F_SOFT_FLOAT)
23524 as_bad (_("hard-float conflicts with specified fpu"));
23528 /* Using pure-endian doubles (even if soft-float). */
23529 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
23530 flags |= F_VFP_FLOAT;
23532 #if defined OBJ_ELF
23533 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
23534 flags |= EF_ARM_MAVERICK_FLOAT;
23537 case EF_ARM_EABI_VER4:
23538 case EF_ARM_EABI_VER5:
23539 /* No additional flags to set. */
23546 bfd_set_private_flags (stdoutput, flags);
23548 /* We have run out flags in the COFF header to encode the
23549 status of ATPCS support, so instead we create a dummy,
23550 empty, debug section called .arm.atpcs. */
23555 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23559 bfd_set_section_flags
23560 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23561 bfd_set_section_size (stdoutput, sec, 0);
23562 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23568 /* Record the CPU type as well. */
23569 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23570 mach = bfd_mach_arm_iWMMXt2;
23571 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
23572 mach = bfd_mach_arm_iWMMXt;
23573 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
23574 mach = bfd_mach_arm_XScale;
23575 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
23576 mach = bfd_mach_arm_ep9312;
23577 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
23578 mach = bfd_mach_arm_5TE;
23579 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
23581 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23582 mach = bfd_mach_arm_5T;
23584 mach = bfd_mach_arm_5;
23586 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
23588 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23589 mach = bfd_mach_arm_4T;
23591 mach = bfd_mach_arm_4;
23593 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
23594 mach = bfd_mach_arm_3M;
23595 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23596 mach = bfd_mach_arm_3;
23597 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23598 mach = bfd_mach_arm_2a;
23599 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23600 mach = bfd_mach_arm_2;
23602 mach = bfd_mach_arm_unknown;
23604 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23607 /* Command line processing. */
23610 Invocation line includes a switch not recognized by the base assembler.
23611 See if it's a processor-specific option.
23613 This routine is somewhat complicated by the need for backwards
23614 compatibility (since older releases of gcc can't be changed).
23615 The new options try to make the interface as compatible as
23618 New options (supported) are:
23620 -mcpu=<cpu name> Assemble for selected processor
23621 -march=<architecture name> Assemble for selected architecture
23622 -mfpu=<fpu architecture> Assemble for selected FPU.
23623 -EB/-mbig-endian Big-endian
23624 -EL/-mlittle-endian Little-endian
23625 -k Generate PIC code
23626 -mthumb Start in Thumb mode
23627 -mthumb-interwork Code supports ARM/Thumb interworking
23629 -m[no-]warn-deprecated Warn about deprecated features
23631 For now we will also provide support for:
23633 -mapcs-32 32-bit Program counter
23634 -mapcs-26 26-bit Program counter
23635 -macps-float Floats passed in FP registers
23636 -mapcs-reentrant Reentrant code
23638 (sometime these will probably be replaced with -mapcs=<list of options>
23639 and -matpcs=<list of options>)
23641 The remaining options are only supported for back-wards compatibility.
23642 Cpu variants, the arm part is optional:
23643 -m[arm]1 Currently not supported.
23644 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23645 -m[arm]3 Arm 3 processor
23646 -m[arm]6[xx], Arm 6 processors
23647 -m[arm]7[xx][t][[d]m] Arm 7 processors
23648 -m[arm]8[10] Arm 8 processors
23649 -m[arm]9[20][tdmi] Arm 9 processors
23650 -mstrongarm[110[0]] StrongARM processors
23651 -mxscale XScale processors
23652 -m[arm]v[2345[t[e]]] Arm architectures
23653 -mall All (except the ARM1)
23655 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23656 -mfpe-old (No float load/store multiples)
23657 -mvfpxd VFP Single precision
23659 -mno-fpu Disable all floating point instructions
23661 The following CPU names are recognized:
23662 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23663 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23664 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23665 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23666 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23667 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23668 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23672 const char * md_shortopts = "m:k";
23674 #ifdef ARM_BI_ENDIAN
23675 #define OPTION_EB (OPTION_MD_BASE + 0)
23676 #define OPTION_EL (OPTION_MD_BASE + 1)
23678 #if TARGET_BYTES_BIG_ENDIAN
23679 #define OPTION_EB (OPTION_MD_BASE + 0)
23681 #define OPTION_EL (OPTION_MD_BASE + 1)
23684 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23686 struct option md_longopts[] =
23689 {"EB", no_argument, NULL, OPTION_EB},
23692 {"EL", no_argument, NULL, OPTION_EL},
23694 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
23695 {NULL, no_argument, NULL, 0}
23698 size_t md_longopts_size = sizeof (md_longopts);
23700 struct arm_option_table
23702 char *option; /* Option name to match. */
23703 char *help; /* Help information. */
23704 int *var; /* Variable to change. */
23705 int value; /* What to change it to. */
23706 char *deprecated; /* If non-null, print this message. */
23709 struct arm_option_table arm_opts[] =
23711 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23712 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23713 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23714 &support_interwork, 1, NULL},
23715 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23716 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23717 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23719 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23720 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23721 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23722 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23725 /* These are recognized by the assembler, but have no affect on code. */
23726 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23727 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
23729 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23730 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23731 &warn_on_deprecated, 0, NULL},
23732 {NULL, NULL, NULL, 0, NULL}
23735 struct arm_legacy_option_table
23737 char *option; /* Option name to match. */
23738 const arm_feature_set **var; /* Variable to change. */
23739 const arm_feature_set value; /* What to change it to. */
23740 char *deprecated; /* If non-null, print this message. */
23743 const struct arm_legacy_option_table arm_legacy_opts[] =
23745 /* DON'T add any new processors to this list -- we want the whole list
23746 to go away... Add them to the processors table instead. */
23747 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23748 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23749 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23750 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23751 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23752 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23753 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23754 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23755 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23756 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23757 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23758 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23759 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23760 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23761 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23762 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23763 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23764 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23765 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23766 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23767 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23768 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23769 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23770 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23771 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23772 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23773 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23774 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23775 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23776 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23777 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23778 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23779 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23780 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23781 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23782 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23783 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23784 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23785 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23786 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23787 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23788 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23789 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23790 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23791 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23792 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23793 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23794 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23795 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23796 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23797 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23798 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23799 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23800 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23801 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23802 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23803 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23804 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23805 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23806 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23807 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23808 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23809 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23810 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23811 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23812 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23813 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23814 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23815 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23816 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23817 N_("use -mcpu=strongarm110")},
23818 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23819 N_("use -mcpu=strongarm1100")},
23820 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23821 N_("use -mcpu=strongarm1110")},
23822 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23823 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23824 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23826 /* Architecture variants -- don't add any more to this list either. */
23827 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23828 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23829 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23830 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23831 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23832 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23833 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23834 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23835 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23836 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23837 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23838 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23839 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23840 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23841 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23842 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23843 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23844 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23846 /* Floating point variants -- don't add any more to this list either. */
23847 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23848 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23849 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23850 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23851 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23853 {NULL, NULL, ARM_ARCH_NONE, NULL}
23856 struct arm_cpu_option_table
23860 const arm_feature_set value;
23861 /* For some CPUs we assume an FPU unless the user explicitly sets
23863 const arm_feature_set default_fpu;
23864 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23866 const char *canonical_name;
23869 /* This list should, at a minimum, contain all the cpu names
23870 recognized by GCC. */
23871 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23872 static const struct arm_cpu_option_table arm_cpus[] =
23874 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23875 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23876 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23877 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23878 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23879 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23880 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23881 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23882 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23883 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23884 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23885 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23886 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23887 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23888 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23889 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23890 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23891 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23892 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23893 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23894 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23895 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23896 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23897 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23898 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23899 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23900 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23901 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23902 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23903 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23904 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23905 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23906 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23907 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23908 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23909 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23910 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23911 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23912 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23913 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23914 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23915 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23916 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23917 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23918 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23919 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23920 /* For V5 or later processors we default to using VFP; but the user
23921 should really set the FPU type explicitly. */
23922 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23923 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23924 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23925 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23926 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23927 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23928 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23929 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23930 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23931 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23932 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23933 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23934 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23935 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23936 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23937 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23938 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23939 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23940 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23941 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23943 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23944 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23945 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23946 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23947 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23948 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23949 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23950 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23951 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23953 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23954 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23955 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23956 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23957 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23958 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23959 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23960 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23961 FPU_NONE, "Cortex-A5"),
23962 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23963 FPU_ARCH_NEON_VFP_V4,
23965 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23966 ARM_FEATURE (0, FPU_VFP_V3
23967 | FPU_NEON_EXT_V1),
23969 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23970 ARM_FEATURE (0, FPU_VFP_V3
23971 | FPU_NEON_EXT_V1),
23973 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23974 FPU_ARCH_NEON_VFP_V4,
23976 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23978 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23980 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23981 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23983 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23984 FPU_NONE, "Cortex-R5"),
23985 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
23986 FPU_ARCH_VFP_V3D16,
23988 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23989 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23990 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23991 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23992 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
23993 /* ??? XSCALE is really an architecture. */
23994 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23995 /* ??? iwmmxt is not a processor. */
23996 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23997 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23998 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24000 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
24001 FPU_ARCH_MAVERICK, "ARM920T"),
24002 /* Marvell processors. */
24003 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0),
24004 FPU_ARCH_VFP_V3D16, NULL),
24006 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
24010 struct arm_arch_option_table
24014 const arm_feature_set value;
24015 const arm_feature_set default_fpu;
24018 /* This list should, at a minimum, contain all the architecture names
24019 recognized by GCC. */
24020 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24021 static const struct arm_arch_option_table arm_archs[] =
24023 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
24024 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
24025 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
24026 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
24027 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
24028 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
24029 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
24030 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
24031 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
24032 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
24033 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
24034 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
24035 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
24036 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
24037 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
24038 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
24039 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
24040 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
24041 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
24042 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
24043 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
24044 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
24045 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
24046 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
24047 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
24048 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
24049 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
24050 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
24051 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
24052 /* The official spelling of the ARMv7 profile variants is the dashed form.
24053 Accept the non-dashed form for compatibility with old toolchains. */
24054 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24055 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24056 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24057 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24058 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24059 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24060 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
24061 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
24062 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
24063 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
24064 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
24065 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24067 #undef ARM_ARCH_OPT
24069 /* ISA extensions in the co-processor and main instruction set space. */
24070 struct arm_option_extension_value_table
24074 const arm_feature_set value;
24075 const arm_feature_set allowed_archs;
24078 /* The following table must be in alphabetical order with a NULL last entry.
24080 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
24081 static const struct arm_option_extension_value_table arm_extensions[] =
24083 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (ARM_EXT_V8, 0)),
24084 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24085 ARM_FEATURE (ARM_EXT_V8, 0)),
24086 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
24087 ARM_FEATURE (ARM_EXT_V8, 0)),
24088 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
24089 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24090 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
24091 ARM_EXT_OPT ("iwmmxt2",
24092 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
24093 ARM_EXT_OPT ("maverick",
24094 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
24095 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
24096 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24097 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
24098 ARM_FEATURE (ARM_EXT_V8, 0)),
24099 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
24100 ARM_FEATURE (ARM_EXT_V6M, 0)),
24101 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
24102 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
24103 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
24105 ARM_FEATURE (ARM_EXT_V7A, 0)),
24106 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24107 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24111 /* ISA floating-point and Advanced SIMD extensions. */
24112 struct arm_option_fpu_value_table
24115 const arm_feature_set value;
24118 /* This list should, at a minimum, contain all the fpu names
24119 recognized by GCC. */
24120 static const struct arm_option_fpu_value_table arm_fpus[] =
24122 {"softfpa", FPU_NONE},
24123 {"fpe", FPU_ARCH_FPE},
24124 {"fpe2", FPU_ARCH_FPE},
24125 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24126 {"fpa", FPU_ARCH_FPA},
24127 {"fpa10", FPU_ARCH_FPA},
24128 {"fpa11", FPU_ARCH_FPA},
24129 {"arm7500fe", FPU_ARCH_FPA},
24130 {"softvfp", FPU_ARCH_VFP},
24131 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24132 {"vfp", FPU_ARCH_VFP_V2},
24133 {"vfp9", FPU_ARCH_VFP_V2},
24134 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
24135 {"vfp10", FPU_ARCH_VFP_V2},
24136 {"vfp10-r0", FPU_ARCH_VFP_V1},
24137 {"vfpxd", FPU_ARCH_VFP_V1xD},
24138 {"vfpv2", FPU_ARCH_VFP_V2},
24139 {"vfpv3", FPU_ARCH_VFP_V3},
24140 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
24141 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
24142 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24143 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24144 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
24145 {"arm1020t", FPU_ARCH_VFP_V1},
24146 {"arm1020e", FPU_ARCH_VFP_V2},
24147 {"arm1136jfs", FPU_ARCH_VFP_V2},
24148 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24149 {"maverick", FPU_ARCH_MAVERICK},
24150 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
24151 {"neon-fp16", FPU_ARCH_NEON_FP16},
24152 {"vfpv4", FPU_ARCH_VFP_V4},
24153 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
24154 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
24155 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
24156 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24157 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24158 {"crypto-neon-fp-armv8",
24159 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
24160 {NULL, ARM_ARCH_NONE}
24163 struct arm_option_value_table
24169 static const struct arm_option_value_table arm_float_abis[] =
24171 {"hard", ARM_FLOAT_ABI_HARD},
24172 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24173 {"soft", ARM_FLOAT_ABI_SOFT},
24178 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24179 static const struct arm_option_value_table arm_eabis[] =
24181 {"gnu", EF_ARM_EABI_UNKNOWN},
24182 {"4", EF_ARM_EABI_VER4},
24183 {"5", EF_ARM_EABI_VER5},
24188 struct arm_long_option_table
24190 char * option; /* Substring to match. */
24191 char * help; /* Help information. */
24192 int (* func) (char * subopt); /* Function to decode sub-option. */
24193 char * deprecated; /* If non-null, print this message. */
24197 arm_parse_extension (char *str, const arm_feature_set **opt_p)
24199 arm_feature_set *ext_set = (arm_feature_set *)
24200 xmalloc (sizeof (arm_feature_set));
24202 /* We insist on extensions being specified in alphabetical order, and with
24203 extensions being added before being removed. We achieve this by having
24204 the global ARM_EXTENSIONS table in alphabetical order, and using the
24205 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24206 or removing it (0) and only allowing it to change in the order
24208 const struct arm_option_extension_value_table * opt = NULL;
24209 int adding_value = -1;
24211 /* Copy the feature set, so that we can modify it. */
24212 *ext_set = **opt_p;
24215 while (str != NULL && *str != 0)
24222 as_bad (_("invalid architectural extension"));
24227 ext = strchr (str, '+');
24232 len = strlen (str);
24234 if (len >= 2 && strncmp (str, "no", 2) == 0)
24236 if (adding_value != 0)
24239 opt = arm_extensions;
24247 if (adding_value == -1)
24250 opt = arm_extensions;
24252 else if (adding_value != 1)
24254 as_bad (_("must specify extensions to add before specifying "
24255 "those to remove"));
24262 as_bad (_("missing architectural extension"));
24266 gas_assert (adding_value != -1);
24267 gas_assert (opt != NULL);
24269 /* Scan over the options table trying to find an exact match. */
24270 for (; opt->name != NULL; opt++)
24271 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24273 /* Check we can apply the extension to this architecture. */
24274 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24276 as_bad (_("extension does not apply to the base architecture"));
24280 /* Add or remove the extension. */
24282 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
24284 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
24289 if (opt->name == NULL)
24291 /* Did we fail to find an extension because it wasn't specified in
24292 alphabetical order, or because it does not exist? */
24294 for (opt = arm_extensions; opt->name != NULL; opt++)
24295 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24298 if (opt->name == NULL)
24299 as_bad (_("unknown architectural extension `%s'"), str);
24301 as_bad (_("architectural extensions must be specified in "
24302 "alphabetical order"));
24308 /* We should skip the extension we've just matched the next time
24320 arm_parse_cpu (char *str)
24322 const struct arm_cpu_option_table *opt;
24323 char *ext = strchr (str, '+');
24329 len = strlen (str);
24333 as_bad (_("missing cpu name `%s'"), str);
24337 for (opt = arm_cpus; opt->name != NULL; opt++)
24338 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24340 mcpu_cpu_opt = &opt->value;
24341 mcpu_fpu_opt = &opt->default_fpu;
24342 if (opt->canonical_name)
24343 strcpy (selected_cpu_name, opt->canonical_name);
24348 for (i = 0; i < len; i++)
24349 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24350 selected_cpu_name[i] = 0;
24354 return arm_parse_extension (ext, &mcpu_cpu_opt);
24359 as_bad (_("unknown cpu `%s'"), str);
24364 arm_parse_arch (char *str)
24366 const struct arm_arch_option_table *opt;
24367 char *ext = strchr (str, '+');
24373 len = strlen (str);
24377 as_bad (_("missing architecture name `%s'"), str);
24381 for (opt = arm_archs; opt->name != NULL; opt++)
24382 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24384 march_cpu_opt = &opt->value;
24385 march_fpu_opt = &opt->default_fpu;
24386 strcpy (selected_cpu_name, opt->name);
24389 return arm_parse_extension (ext, &march_cpu_opt);
24394 as_bad (_("unknown architecture `%s'\n"), str);
24399 arm_parse_fpu (char * str)
24401 const struct arm_option_fpu_value_table * opt;
24403 for (opt = arm_fpus; opt->name != NULL; opt++)
24404 if (streq (opt->name, str))
24406 mfpu_opt = &opt->value;
24410 as_bad (_("unknown floating point format `%s'\n"), str);
24415 arm_parse_float_abi (char * str)
24417 const struct arm_option_value_table * opt;
24419 for (opt = arm_float_abis; opt->name != NULL; opt++)
24420 if (streq (opt->name, str))
24422 mfloat_abi_opt = opt->value;
24426 as_bad (_("unknown floating point abi `%s'\n"), str);
24432 arm_parse_eabi (char * str)
24434 const struct arm_option_value_table *opt;
24436 for (opt = arm_eabis; opt->name != NULL; opt++)
24437 if (streq (opt->name, str))
24439 meabi_flags = opt->value;
24442 as_bad (_("unknown EABI `%s'\n"), str);
24448 arm_parse_it_mode (char * str)
24450 bfd_boolean ret = TRUE;
24452 if (streq ("arm", str))
24453 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24454 else if (streq ("thumb", str))
24455 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24456 else if (streq ("always", str))
24457 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24458 else if (streq ("never", str))
24459 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24462 as_bad (_("unknown implicit IT mode `%s', should be "\
24463 "arm, thumb, always, or never."), str);
24470 struct arm_long_option_table arm_long_opts[] =
24472 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24473 arm_parse_cpu, NULL},
24474 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24475 arm_parse_arch, NULL},
24476 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24477 arm_parse_fpu, NULL},
24478 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24479 arm_parse_float_abi, NULL},
24481 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24482 arm_parse_eabi, NULL},
24484 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24485 arm_parse_it_mode, NULL},
24486 {NULL, NULL, 0, NULL}
24490 md_parse_option (int c, char * arg)
24492 struct arm_option_table *opt;
24493 const struct arm_legacy_option_table *fopt;
24494 struct arm_long_option_table *lopt;
24500 target_big_endian = 1;
24506 target_big_endian = 0;
24510 case OPTION_FIX_V4BX:
24515 /* Listing option. Just ignore these, we don't support additional
24520 for (opt = arm_opts; opt->option != NULL; opt++)
24522 if (c == opt->option[0]
24523 && ((arg == NULL && opt->option[1] == 0)
24524 || streq (arg, opt->option + 1)))
24526 /* If the option is deprecated, tell the user. */
24527 if (warn_on_deprecated && opt->deprecated != NULL)
24528 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24529 arg ? arg : "", _(opt->deprecated));
24531 if (opt->var != NULL)
24532 *opt->var = opt->value;
24538 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
24540 if (c == fopt->option[0]
24541 && ((arg == NULL && fopt->option[1] == 0)
24542 || streq (arg, fopt->option + 1)))
24544 /* If the option is deprecated, tell the user. */
24545 if (warn_on_deprecated && fopt->deprecated != NULL)
24546 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24547 arg ? arg : "", _(fopt->deprecated));
24549 if (fopt->var != NULL)
24550 *fopt->var = &fopt->value;
24556 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24558 /* These options are expected to have an argument. */
24559 if (c == lopt->option[0]
24561 && strncmp (arg, lopt->option + 1,
24562 strlen (lopt->option + 1)) == 0)
24564 /* If the option is deprecated, tell the user. */
24565 if (warn_on_deprecated && lopt->deprecated != NULL)
24566 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24567 _(lopt->deprecated));
24569 /* Call the sup-option parser. */
24570 return lopt->func (arg + strlen (lopt->option) - 1);
24581 md_show_usage (FILE * fp)
24583 struct arm_option_table *opt;
24584 struct arm_long_option_table *lopt;
24586 fprintf (fp, _(" ARM-specific assembler options:\n"));
24588 for (opt = arm_opts; opt->option != NULL; opt++)
24589 if (opt->help != NULL)
24590 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
24592 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24593 if (lopt->help != NULL)
24594 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
24598 -EB assemble code for a big-endian cpu\n"));
24603 -EL assemble code for a little-endian cpu\n"));
24607 --fix-v4bx Allow BX in ARMv4 code\n"));
24615 arm_feature_set flags;
24616 } cpu_arch_ver_table;
24618 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24619 least features first. */
24620 static const cpu_arch_ver_table cpu_arch_ver[] =
24626 {4, ARM_ARCH_V5TE},
24627 {5, ARM_ARCH_V5TEJ},
24631 {11, ARM_ARCH_V6M},
24632 {12, ARM_ARCH_V6SM},
24633 {8, ARM_ARCH_V6T2},
24634 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
24635 {10, ARM_ARCH_V7R},
24636 {10, ARM_ARCH_V7M},
24637 {14, ARM_ARCH_V8A},
24641 /* Set an attribute if it has not already been set by the user. */
24643 aeabi_set_attribute_int (int tag, int value)
24646 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24647 || !attributes_set_explicitly[tag])
24648 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24652 aeabi_set_attribute_string (int tag, const char *value)
24655 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24656 || !attributes_set_explicitly[tag])
24657 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24660 /* Set the public EABI object attributes. */
24662 aeabi_set_public_attributes (void)
24667 int fp16_optional = 0;
24668 arm_feature_set flags;
24669 arm_feature_set tmp;
24670 const cpu_arch_ver_table *p;
24672 /* Choose the architecture based on the capabilities of the requested cpu
24673 (if any) and/or the instructions actually used. */
24674 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24675 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24676 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
24678 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24679 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24681 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24682 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24684 /* Allow the user to override the reported architecture. */
24687 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24688 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24691 /* We need to make sure that the attributes do not identify us as v6S-M
24692 when the only v6S-M feature in use is the Operating System Extensions. */
24693 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24694 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
24695 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
24699 for (p = cpu_arch_ver; p->val; p++)
24701 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24704 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24708 /* The table lookup above finds the last architecture to contribute
24709 a new feature. Unfortunately, Tag13 is a subset of the union of
24710 v6T2 and v7-M, so it is never seen as contributing a new feature.
24711 We can not search for the last entry which is entirely used,
24712 because if no CPU is specified we build up only those flags
24713 actually used. Perhaps we should separate out the specified
24714 and implicit cases. Avoid taking this path for -march=all by
24715 checking for contradictory v7-A / v7-M features. */
24717 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24718 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24719 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24722 /* Tag_CPU_name. */
24723 if (selected_cpu_name[0])
24727 q = selected_cpu_name;
24728 if (strncmp (q, "armv", 4) == 0)
24733 for (i = 0; q[i]; i++)
24734 q[i] = TOUPPER (q[i]);
24736 aeabi_set_attribute_string (Tag_CPU_name, q);
24739 /* Tag_CPU_arch. */
24740 aeabi_set_attribute_int (Tag_CPU_arch, arch);
24742 /* Tag_CPU_arch_profile. */
24743 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
24745 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
24747 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
24752 if (profile != '\0')
24753 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
24755 /* Tag_ARM_ISA_use. */
24756 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24758 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
24760 /* Tag_THUMB_ISA_use. */
24761 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24763 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24764 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
24766 /* Tag_VFP_arch. */
24767 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24768 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24769 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
24770 aeabi_set_attribute_int (Tag_VFP_arch,
24771 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24773 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
24776 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24778 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
24780 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24783 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24784 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24785 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24786 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24787 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24789 /* Tag_ABI_HardFP_use. */
24790 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24791 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24792 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24794 /* Tag_WMMX_arch. */
24795 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24796 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24797 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24798 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24800 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24801 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24802 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24803 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24805 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24807 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24811 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24816 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24817 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24818 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24822 We set Tag_DIV_use to two when integer divide instructions have been used
24823 in ARM state, or when Thumb integer divide instructions have been used,
24824 but we have no architecture profile set, nor have we any ARM instructions.
24826 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24829 For new architectures we will have to check these tests. */
24830 gas_assert (arch <= TAG_CPU_ARCH_V8);
24831 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24832 aeabi_set_attribute_int (Tag_DIV_use, 0);
24833 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24834 || (profile == '\0'
24835 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24836 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24837 aeabi_set_attribute_int (Tag_DIV_use, 2);
24839 /* Tag_MP_extension_use. */
24840 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24841 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24843 /* Tag Virtualization_use. */
24844 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24846 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24849 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24852 /* Add the default contents for the .ARM.attributes section. */
24856 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24859 aeabi_set_public_attributes ();
24861 #endif /* OBJ_ELF */
24864 /* Parse a .cpu directive. */
24867 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24869 const struct arm_cpu_option_table *opt;
24873 name = input_line_pointer;
24874 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24875 input_line_pointer++;
24876 saved_char = *input_line_pointer;
24877 *input_line_pointer = 0;
24879 /* Skip the first "all" entry. */
24880 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24881 if (streq (opt->name, name))
24883 mcpu_cpu_opt = &opt->value;
24884 selected_cpu = opt->value;
24885 if (opt->canonical_name)
24886 strcpy (selected_cpu_name, opt->canonical_name);
24890 for (i = 0; opt->name[i]; i++)
24891 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24893 selected_cpu_name[i] = 0;
24895 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24896 *input_line_pointer = saved_char;
24897 demand_empty_rest_of_line ();
24900 as_bad (_("unknown cpu `%s'"), name);
24901 *input_line_pointer = saved_char;
24902 ignore_rest_of_line ();
24906 /* Parse a .arch directive. */
24909 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24911 const struct arm_arch_option_table *opt;
24915 name = input_line_pointer;
24916 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24917 input_line_pointer++;
24918 saved_char = *input_line_pointer;
24919 *input_line_pointer = 0;
24921 /* Skip the first "all" entry. */
24922 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24923 if (streq (opt->name, name))
24925 mcpu_cpu_opt = &opt->value;
24926 selected_cpu = opt->value;
24927 strcpy (selected_cpu_name, opt->name);
24928 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24929 *input_line_pointer = saved_char;
24930 demand_empty_rest_of_line ();
24934 as_bad (_("unknown architecture `%s'\n"), name);
24935 *input_line_pointer = saved_char;
24936 ignore_rest_of_line ();
24940 /* Parse a .object_arch directive. */
24943 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24945 const struct arm_arch_option_table *opt;
24949 name = input_line_pointer;
24950 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24951 input_line_pointer++;
24952 saved_char = *input_line_pointer;
24953 *input_line_pointer = 0;
24955 /* Skip the first "all" entry. */
24956 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24957 if (streq (opt->name, name))
24959 object_arch = &opt->value;
24960 *input_line_pointer = saved_char;
24961 demand_empty_rest_of_line ();
24965 as_bad (_("unknown architecture `%s'\n"), name);
24966 *input_line_pointer = saved_char;
24967 ignore_rest_of_line ();
24970 /* Parse a .arch_extension directive. */
24973 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24975 const struct arm_option_extension_value_table *opt;
24978 int adding_value = 1;
24980 name = input_line_pointer;
24981 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24982 input_line_pointer++;
24983 saved_char = *input_line_pointer;
24984 *input_line_pointer = 0;
24986 if (strlen (name) >= 2
24987 && strncmp (name, "no", 2) == 0)
24993 for (opt = arm_extensions; opt->name != NULL; opt++)
24994 if (streq (opt->name, name))
24996 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
24998 as_bad (_("architectural extension `%s' is not allowed for the "
24999 "current base architecture"), name);
25004 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
25006 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
25008 mcpu_cpu_opt = &selected_cpu;
25009 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25010 *input_line_pointer = saved_char;
25011 demand_empty_rest_of_line ();
25015 if (opt->name == NULL)
25016 as_bad (_("unknown architecture `%s'\n"), name);
25018 *input_line_pointer = saved_char;
25019 ignore_rest_of_line ();
25022 /* Parse a .fpu directive. */
25025 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
25027 const struct arm_option_fpu_value_table *opt;
25031 name = input_line_pointer;
25032 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25033 input_line_pointer++;
25034 saved_char = *input_line_pointer;
25035 *input_line_pointer = 0;
25037 for (opt = arm_fpus; opt->name != NULL; opt++)
25038 if (streq (opt->name, name))
25040 mfpu_opt = &opt->value;
25041 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25042 *input_line_pointer = saved_char;
25043 demand_empty_rest_of_line ();
25047 as_bad (_("unknown floating point format `%s'\n"), name);
25048 *input_line_pointer = saved_char;
25049 ignore_rest_of_line ();
25052 /* Copy symbol information. */
25055 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
25057 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
25061 /* Given a symbolic attribute NAME, return the proper integer value.
25062 Returns -1 if the attribute is not known. */
25065 arm_convert_symbolic_attribute (const char *name)
25067 static const struct
25072 attribute_table[] =
25074 /* When you modify this table you should
25075 also modify the list in doc/c-arm.texi. */
25076 #define T(tag) {#tag, tag}
25077 T (Tag_CPU_raw_name),
25080 T (Tag_CPU_arch_profile),
25081 T (Tag_ARM_ISA_use),
25082 T (Tag_THUMB_ISA_use),
25086 T (Tag_Advanced_SIMD_arch),
25087 T (Tag_PCS_config),
25088 T (Tag_ABI_PCS_R9_use),
25089 T (Tag_ABI_PCS_RW_data),
25090 T (Tag_ABI_PCS_RO_data),
25091 T (Tag_ABI_PCS_GOT_use),
25092 T (Tag_ABI_PCS_wchar_t),
25093 T (Tag_ABI_FP_rounding),
25094 T (Tag_ABI_FP_denormal),
25095 T (Tag_ABI_FP_exceptions),
25096 T (Tag_ABI_FP_user_exceptions),
25097 T (Tag_ABI_FP_number_model),
25098 T (Tag_ABI_align_needed),
25099 T (Tag_ABI_align8_needed),
25100 T (Tag_ABI_align_preserved),
25101 T (Tag_ABI_align8_preserved),
25102 T (Tag_ABI_enum_size),
25103 T (Tag_ABI_HardFP_use),
25104 T (Tag_ABI_VFP_args),
25105 T (Tag_ABI_WMMX_args),
25106 T (Tag_ABI_optimization_goals),
25107 T (Tag_ABI_FP_optimization_goals),
25108 T (Tag_compatibility),
25109 T (Tag_CPU_unaligned_access),
25110 T (Tag_FP_HP_extension),
25111 T (Tag_VFP_HP_extension),
25112 T (Tag_ABI_FP_16bit_format),
25113 T (Tag_MPextension_use),
25115 T (Tag_nodefaults),
25116 T (Tag_also_compatible_with),
25117 T (Tag_conformance),
25119 T (Tag_Virtualization_use),
25120 /* We deliberately do not include Tag_MPextension_use_legacy. */
25128 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
25129 if (streq (name, attribute_table[i].name))
25130 return attribute_table[i].tag;
25136 /* Apply sym value for relocations only in the case that
25137 they are for local symbols and you have the respective
25138 architectural feature for blx and simple switches. */
25140 arm_apply_sym_value (struct fix * fixP)
25143 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
25144 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
25146 switch (fixP->fx_r_type)
25148 case BFD_RELOC_ARM_PCREL_BLX:
25149 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25150 if (ARM_IS_FUNC (fixP->fx_addsy))
25154 case BFD_RELOC_ARM_PCREL_CALL:
25155 case BFD_RELOC_THUMB_PCREL_BLX:
25156 if (THUMB_IS_FUNC (fixP->fx_addsy))
25167 #endif /* OBJ_ELF */