1 /* tc-arc.c -- Assembler for the ARC
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "struc-symbol.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "safe-ctype.h"
30 #include "opcode/arc.h"
33 /* Defines section. */
35 #define MAX_INSN_FIXUPS 2
36 #define MAX_CONSTR_STR 20
37 #define FRAG_MAX_GROWTH 8
40 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42 # define pr_debug(fmt, args...)
45 #define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
46 #define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
47 #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
48 (SUB_OPCODE (x) == 0x28))
50 /* Equal to MAX_PRECISION in atof-ieee.c. */
51 #define MAX_LITTLENUMS 6
53 /* Enum used to enumerate the relaxable ins operands. */
58 REGISTER_S, /* Register for short instruction(s). */
59 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
60 REGISTER_DUP, /* Duplication of previous operand of type register. */
94 #define regno(x) ((x) & 0x3F)
95 #define is_ir_num(x) (((x) & ~0x3F) == 0)
96 #define is_code_density_p(op) (((op)->subclass == CD1 || (op)->subclass == CD2))
97 #define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
98 #define is_kernel_insn_p(op) (((op)->class == KERNEL))
100 /* Generic assembler global variables which must be defined by all
103 /* Characters which always start a comment. */
104 const char comment_chars[] = "#;";
106 /* Characters which start a comment at the beginning of a line. */
107 const char line_comment_chars[] = "#";
109 /* Characters which may be used to separate multiple commands on a
111 const char line_separator_chars[] = "`";
113 /* Characters which are used to indicate an exponent in a floating
115 const char EXP_CHARS[] = "eE";
117 /* Chars that mean this number is a floating point constant
118 As in 0f12.456 or 0d1.2345e12. */
119 const char FLT_CHARS[] = "rRsSfFdD";
122 extern int target_big_endian;
123 const char *arc_target_format = DEFAULT_TARGET_FORMAT;
124 static int byte_order = DEFAULT_BYTE_ORDER;
126 /* By default relaxation is disabled. */
127 static int relaxation_state = 0;
129 extern int arc_get_mach (char *);
131 /* Forward declarations. */
132 static void arc_lcomm (int);
133 static void arc_option (int);
134 static void arc_extra_reloc (int);
137 const pseudo_typeS md_pseudo_table[] =
139 /* Make sure that .word is 32 bits. */
142 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
143 { "lcomm", arc_lcomm, 0 },
144 { "lcommon", arc_lcomm, 0 },
145 { "cpu", arc_option, 0 },
147 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
148 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
153 const char *md_shortopts = "";
157 OPTION_EB = OPTION_MD_BASE,
170 /* The following options are deprecated and provided here only for
171 compatibility reasons. */
197 struct option md_longopts[] =
199 { "EB", no_argument, NULL, OPTION_EB },
200 { "EL", no_argument, NULL, OPTION_EL },
201 { "mcpu", required_argument, NULL, OPTION_MCPU },
202 { "mA6", no_argument, NULL, OPTION_ARC600 },
203 { "mARC600", no_argument, NULL, OPTION_ARC600 },
204 { "mARC601", no_argument, NULL, OPTION_ARC601 },
205 { "mARC700", no_argument, NULL, OPTION_ARC700 },
206 { "mA7", no_argument, NULL, OPTION_ARC700 },
207 { "mEM", no_argument, NULL, OPTION_ARCEM },
208 { "mHS", no_argument, NULL, OPTION_ARCHS },
209 { "mcode-density", no_argument, NULL, OPTION_CD },
210 { "mrelax", no_argument, NULL, OPTION_RELAX },
212 /* The following options are deprecated and provided here only for
213 compatibility reasons. */
214 { "mav2em", no_argument, NULL, OPTION_ARCEM },
215 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
216 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
217 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
218 { "mswap", no_argument, NULL, OPTION_SWAP },
219 { "mnorm", no_argument, NULL, OPTION_NORM },
220 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
221 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
222 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
223 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
224 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
225 { "mea", no_argument, NULL, OPTION_EA },
226 { "mEA", no_argument, NULL, OPTION_EA },
227 { "mmul64", no_argument, NULL, OPTION_MUL64 },
228 { "msimd", no_argument, NULL, OPTION_SIMD},
229 { "mspfp", no_argument, NULL, OPTION_SPFP},
230 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
231 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
232 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
233 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
234 { "mdpfp", no_argument, NULL, OPTION_DPFP},
235 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
236 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
237 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
238 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
239 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
240 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
241 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
242 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
243 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
244 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
245 { "mcrc", no_argument, NULL, OPTION_CRC},
246 { "mdvbf", no_argument, NULL, OPTION_DVBF},
247 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
248 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
249 { "mlock", no_argument, NULL, OPTION_LOCK},
250 { "mswape", no_argument, NULL, OPTION_SWAPE},
251 { "mrtsc", no_argument, NULL, OPTION_RTSC},
252 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
254 { NULL, no_argument, NULL, 0 }
257 size_t md_longopts_size = sizeof (md_longopts);
259 /* Local data and data types. */
261 /* Used since new relocation types are introduced in this
262 file (DUMMY_RELOC_LITUSE_*). */
263 typedef int extended_bfd_reloc_code_real_type;
269 extended_bfd_reloc_code_real_type reloc;
271 /* index into arc_operands. */
272 unsigned int opindex;
274 /* PC-relative, used by internals fixups. */
277 /* TRUE if this fixup is for LIMM operand. */
285 struct arc_fixup fixups[MAX_INSN_FIXUPS];
287 bfd_boolean short_insn; /* Boolean value: TRUE if current insn is
289 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
291 bfd_boolean relax; /* Boolean value: TRUE if needs
295 /* Structure to hold any last two instructions. */
296 static struct arc_last_insn
298 /* Saved instruction opcode. */
299 const struct arc_opcode *opcode;
301 /* Boolean value: TRUE if current insn is short. */
302 bfd_boolean has_limm;
304 /* Boolean value: TRUE if current insn has delay slot. */
305 bfd_boolean has_delay_slot;
308 /* Forward declaration. */
309 static void assemble_insn
310 (const struct arc_opcode *, const expressionS *, int,
311 const struct arc_flags *, int, struct arc_insn *);
313 /* The cpu for which we are generating code. */
314 static unsigned arc_target;
315 static const char *arc_target_name;
316 static unsigned arc_features;
318 /* The default architecture. */
319 static int arc_mach_type;
321 /* Non-zero if the cpu type has been explicitly specified. */
322 static int mach_type_specified_p = 0;
324 /* The hash table of instruction opcodes. */
325 static struct hash_control *arc_opcode_hash;
327 /* The hash table of register symbols. */
328 static struct hash_control *arc_reg_hash;
330 /* A table of CPU names and opcode sets. */
331 static const struct cpu_type
341 { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600,
342 E_ARC_MACH_ARC600, 0x00},
343 { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
344 E_ARC_MACH_ARC700, 0x00},
345 { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400,
346 E_ARC_MACH_NPS400, 0x00},
347 { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
348 EF_ARC_CPU_ARCV2EM, ARC_CD},
349 { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
350 EF_ARC_CPU_ARCV2HS, ARC_CD},
354 /* Used by the arc_reloc_op table. Order is important. */
355 #define O_gotoff O_md1 /* @gotoff relocation. */
356 #define O_gotpc O_md2 /* @gotpc relocation. */
357 #define O_plt O_md3 /* @plt relocation. */
358 #define O_sda O_md4 /* @sda relocation. */
359 #define O_pcl O_md5 /* @pcl relocation. */
360 #define O_tlsgd O_md6 /* @tlsgd relocation. */
361 #define O_tlsie O_md7 /* @tlsie relocation. */
362 #define O_tpoff9 O_md8 /* @tpoff9 relocation. */
363 #define O_tpoff O_md9 /* @tpoff relocation. */
364 #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
365 #define O_dtpoff O_md11 /* @dtpoff relocation. */
366 #define O_last O_dtpoff
368 /* Used to define a bracket as operand in tokens. */
369 #define O_bracket O_md32
371 /* Dummy relocation, to be sorted out. */
372 #define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
374 #define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
376 /* A table to map the spelling of a relocation operand into an appropriate
377 bfd_reloc_code_real_type type. The table is assumed to be ordered such
378 that op-O_literal indexes into it. */
379 #define ARC_RELOC_TABLE(op) \
380 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
382 : (int) (op) - (int) O_gotoff) ])
384 #define DEF(NAME, RELOC, REQ) \
385 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
387 static const struct arc_reloc_op_tag
389 /* String to lookup. */
391 /* Size of the string. */
393 /* Which operator to use. */
395 extended_bfd_reloc_code_real_type reloc;
396 /* Allows complex relocation expression like identifier@reloc +
398 unsigned int complex_expr : 1;
402 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
403 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
404 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
405 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
406 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
407 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
408 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
409 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
410 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
411 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
412 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 0),
415 static const int arc_num_reloc_op
416 = sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
418 /* Structure for relaxable instruction that have to be swapped with a
419 smaller alternative instruction. */
420 struct arc_relaxable_ins
422 /* Mnemonic that should be checked. */
423 const char *mnemonic_r;
425 /* Operands that should be checked.
426 Indexes of operands from operand array. */
427 enum rlx_operand_type operands[6];
429 /* Flags that should be checked. */
430 unsigned flag_classes[5];
432 /* Mnemonic (smaller) alternative to be used later for relaxation. */
433 const char *mnemonic_alt;
435 /* Index of operand that generic relaxation has to check. */
438 /* Base subtype index used. */
439 enum arc_rlx_types subtype;
442 #define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
443 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
444 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
448 #define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
449 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
450 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
455 /* ARC relaxation table. */
456 const relax_typeS md_relax_table[] =
463 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL),
464 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE),
468 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B),
469 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE),
474 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6),
475 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM),
476 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
478 /* LD_S a, [b, u7] ->
479 LD<zz><.x><.aa><.di> a, [b, s9] ->
480 LD<zz><.x><.aa><.di> a, [b, limm] */
481 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9),
482 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM),
483 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE),
488 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12),
489 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM),
490 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
494 SUB<.f> a, b, limm. */
495 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6),
496 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM),
497 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
499 /* MPY<.f> a, b, u6 ->
500 MPY<.f> a, b, limm. */
501 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM),
502 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
504 /* MOV<.f><.cc> b, u6 ->
505 MOV<.f><.cc> b, limm. */
506 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM),
507 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
509 /* ADD<.f><.cc> b, b, u6 ->
510 ADD<.f><.cc> b, b, limm. */
511 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM),
512 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
515 /* Order of this table's entries matters! */
516 const struct arc_relaxable_ins arc_relaxable_insns[] =
518 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
519 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
520 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
521 2, ARC_RLX_ADD_RRU6},
522 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
524 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
526 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
527 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
528 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
529 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
530 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
531 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
532 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
533 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
535 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
537 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
541 const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
543 /* Flags to set in the elf header. */
544 static flagword arc_eflag = 0x00;
546 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
547 symbolS * GOT_symbol = 0;
549 /* Set to TRUE when we assemble instructions. */
550 static bfd_boolean assembling_insn = FALSE;
552 /* Functions implementation. */
554 /* Like md_number_to_chars but used for limms. The 4-byte limm value,
555 is encoded as 'middle-endian' for a little-endian target. FIXME!
556 this function is used for regular 4 byte instructions as well. */
559 md_number_to_chars_midend (char *buf, valueT val, int n)
563 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
564 md_number_to_chars (buf + 2, (val & 0xffff), 2);
568 md_number_to_chars (buf, val, n);
572 /* Select an appropriate entry from CPU_TYPES based on ARG and initialise
573 the relevant static global variables. */
576 arc_select_cpu (const char *arg)
581 for (i = 0; cpu_types[i].name; ++i)
583 if (!strcasecmp (cpu_types[i].name, arg))
585 arc_target = cpu_types[i].flags;
586 arc_target_name = cpu_types[i].name;
587 arc_features = cpu_types[i].features;
588 arc_mach_type = cpu_types[i].mach;
589 cpu_flags = cpu_types[i].eflags;
594 if (!cpu_types[i].name)
595 as_fatal (_("unknown architecture: %s\n"), arg);
596 gas_assert (cpu_flags != 0);
597 arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
600 /* Here ends all the ARCompact extension instruction assembling
604 arc_extra_reloc (int r_type)
607 symbolS *sym, *lab = NULL;
609 if (*input_line_pointer == '@')
610 input_line_pointer++;
611 c = get_symbol_name (&sym_name);
612 sym = symbol_find_or_make (sym_name);
613 restore_line_pointer (c);
614 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
616 ++input_line_pointer;
618 c = get_symbol_name (&lab_name);
619 lab = symbol_find_or_make (lab_name);
620 restore_line_pointer (c);
623 /* These relocations exist as a mechanism for the compiler to tell the
624 linker how to patch the code if the tls model is optimised. However,
625 the relocation itself does not require any space within the assembler
626 fragment, and so we pass a size of 0.
628 The lines that generate these relocations look like this:
630 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
632 The '.tls_gd_ld @.tdata' is processed first and generates the
633 additional relocation, while the 'bl __tls_get_addr@plt' is processed
634 second and generates the additional branch.
636 It is possible that the additional relocation generated by the
637 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
638 while the 'bl __tls_get_addr@plt' will be generated as the first thing
639 in the next fragment. This will be fine; both relocations will still
640 appear to be at the same address in the generated object file.
641 However, this only works as the additional relocation is generated
642 with size of 0 bytes. */
644 = fix_new (frag_now, /* Which frag? */
645 frag_now_fix (), /* Where in that frag? */
646 0, /* size: 1, 2, or 4 usually. */
647 sym, /* X_add_symbol. */
648 0, /* X_add_number. */
649 FALSE, /* TRUE if PC-relative relocation. */
650 r_type /* Relocation type. */);
651 fixP->fx_subsy = lab;
655 arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
656 symbolS *symbolP, addressT size)
661 if (*input_line_pointer == ',')
663 align = parse_align (1);
665 if (align == (addressT) -1)
680 bss_alloc (symbolP, size, align);
681 S_CLEAR_EXTERNAL (symbolP);
687 arc_lcomm (int ignore)
689 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
692 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
695 /* Select the cpu we're assembling for. */
698 arc_option (int ignore ATTRIBUTE_UNUSED)
704 c = get_symbol_name (&cpu);
705 mach = arc_get_mach (cpu);
710 if (!mach_type_specified_p)
712 if ((!strcmp ("ARC600", cpu))
713 || (!strcmp ("ARC601", cpu))
714 || (!strcmp ("A6", cpu)))
716 md_parse_option (OPTION_MCPU, "arc600");
718 else if ((!strcmp ("ARC700", cpu))
719 || (!strcmp ("A7", cpu)))
721 md_parse_option (OPTION_MCPU, "arc700");
723 else if (!strcmp ("EM", cpu))
725 md_parse_option (OPTION_MCPU, "arcem");
727 else if (!strcmp ("HS", cpu))
729 md_parse_option (OPTION_MCPU, "archs");
732 as_fatal ("could not find the architecture");
734 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
735 as_fatal ("could not set architecture and machine");
738 if (arc_mach_type != mach)
739 as_warn ("Command-line value overrides \".cpu\" directive");
741 restore_line_pointer (c);
742 demand_empty_rest_of_line ();
746 restore_line_pointer (c);
747 as_bad ("invalid identifier for \".cpu\"");
748 ignore_rest_of_line ();
751 /* Smartly print an expression. */
754 debug_exp (expressionS *t)
756 const char *name ATTRIBUTE_UNUSED;
757 const char *namemd ATTRIBUTE_UNUSED;
759 pr_debug ("debug_exp: ");
763 default: name = "unknown"; break;
764 case O_illegal: name = "O_illegal"; break;
765 case O_absent: name = "O_absent"; break;
766 case O_constant: name = "O_constant"; break;
767 case O_symbol: name = "O_symbol"; break;
768 case O_symbol_rva: name = "O_symbol_rva"; break;
769 case O_register: name = "O_register"; break;
770 case O_big: name = "O_big"; break;
771 case O_uminus: name = "O_uminus"; break;
772 case O_bit_not: name = "O_bit_not"; break;
773 case O_logical_not: name = "O_logical_not"; break;
774 case O_multiply: name = "O_multiply"; break;
775 case O_divide: name = "O_divide"; break;
776 case O_modulus: name = "O_modulus"; break;
777 case O_left_shift: name = "O_left_shift"; break;
778 case O_right_shift: name = "O_right_shift"; break;
779 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
780 case O_bit_or_not: name = "O_bit_or_not"; break;
781 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
782 case O_bit_and: name = "O_bit_and"; break;
783 case O_add: name = "O_add"; break;
784 case O_subtract: name = "O_subtract"; break;
785 case O_eq: name = "O_eq"; break;
786 case O_ne: name = "O_ne"; break;
787 case O_lt: name = "O_lt"; break;
788 case O_le: name = "O_le"; break;
789 case O_ge: name = "O_ge"; break;
790 case O_gt: name = "O_gt"; break;
791 case O_logical_and: name = "O_logical_and"; break;
792 case O_logical_or: name = "O_logical_or"; break;
793 case O_index: name = "O_index"; break;
794 case O_bracket: name = "O_bracket"; break;
799 default: namemd = "unknown"; break;
800 case O_gotoff: namemd = "O_gotoff"; break;
801 case O_gotpc: namemd = "O_gotpc"; break;
802 case O_plt: namemd = "O_plt"; break;
803 case O_sda: namemd = "O_sda"; break;
804 case O_pcl: namemd = "O_pcl"; break;
805 case O_tlsgd: namemd = "O_tlsgd"; break;
806 case O_tlsie: namemd = "O_tlsie"; break;
807 case O_tpoff9: namemd = "O_tpoff9"; break;
808 case O_tpoff: namemd = "O_tpoff"; break;
809 case O_dtpoff9: namemd = "O_dtpoff9"; break;
810 case O_dtpoff: namemd = "O_dtpoff"; break;
813 pr_debug ("%s (%s, %s, %d, %s)", name,
814 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
815 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
816 (int) t->X_add_number,
817 (t->X_md) ? namemd : "--");
822 /* Parse the arguments to an opcode. */
825 tokenize_arguments (char *str,
829 char *old_input_line_pointer;
830 bfd_boolean saw_comma = FALSE;
831 bfd_boolean saw_arg = FALSE;
836 const struct arc_reloc_op_tag *r;
840 memset (tok, 0, sizeof (*tok) * ntok);
842 /* Save and restore input_line_pointer around this function. */
843 old_input_line_pointer = input_line_pointer;
844 input_line_pointer = str;
846 while (*input_line_pointer)
849 switch (*input_line_pointer)
855 input_line_pointer++;
856 if (saw_comma || !saw_arg)
863 ++input_line_pointer;
867 tok->X_op = O_bracket;
874 input_line_pointer++;
878 tok->X_op = O_bracket;
884 /* We have labels, function names and relocations, all
885 starting with @ symbol. Sort them out. */
886 if (saw_arg && !saw_comma)
890 tok->X_op = O_symbol;
891 tok->X_md = O_absent;
893 if (*input_line_pointer != '@')
894 goto normalsymbol; /* This is not a relocation. */
898 /* A relocation opernad has the following form
899 @identifier@relocation_type. The identifier is already
901 if (tok->X_op != O_symbol)
903 as_bad (_("No valid label relocation operand"));
907 /* Parse @relocation_type. */
908 input_line_pointer++;
909 c = get_symbol_name (&reloc_name);
910 len = input_line_pointer - reloc_name;
913 as_bad (_("No relocation operand"));
917 /* Go through known relocation and try to find a match. */
918 r = &arc_reloc_op[0];
919 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
921 && memcmp (reloc_name, r->name, len) == 0)
925 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
929 *input_line_pointer = c;
930 SKIP_WHITESPACE_AFTER_NAME ();
931 /* Extra check for TLS: base. */
932 if (*input_line_pointer == '@')
935 if (tok->X_op_symbol != NULL
936 || tok->X_op != O_symbol)
938 as_bad (_("Unable to parse TLS base: %s"),
942 input_line_pointer++;
944 c = get_symbol_name (&sym_name);
945 base = symbol_find_or_make (sym_name);
946 tok->X_op = O_subtract;
947 tok->X_op_symbol = base;
948 restore_line_pointer (c);
949 tmpE.X_add_number = 0;
951 else if ((*input_line_pointer != '+')
952 && (*input_line_pointer != '-'))
954 tmpE.X_add_number = 0;
958 /* Parse the constant of a complex relocation expression
959 like @identifier@reloc +/- const. */
960 if (! r->complex_expr)
962 as_bad (_("@%s is not a complex relocation."), r->name);
966 if (tmpE.X_op != O_constant)
968 as_bad (_("Bad expression: @%s + %s."),
969 r->name, input_line_pointer);
975 tok->X_add_number = tmpE.X_add_number;
986 /* Can be a register. */
987 ++input_line_pointer;
991 if (saw_arg && !saw_comma)
994 tok->X_op = O_absent;
995 tok->X_md = O_absent;
998 /* Legacy: There are cases when we have
999 identifier@relocation_type, if it is the case parse the
1000 relocation type as well. */
1001 if (*input_line_pointer == '@')
1007 if (tok->X_op == O_illegal || tok->X_op == O_absent)
1019 if (saw_comma || brk_lvl)
1021 input_line_pointer = old_input_line_pointer;
1027 as_bad (_("Brackets in operand field incorrect"));
1029 as_bad (_("extra comma"));
1031 as_bad (_("missing argument"));
1033 as_bad (_("missing comma or colon"));
1034 input_line_pointer = old_input_line_pointer;
1038 /* Parse the flags to a structure. */
1041 tokenize_flags (const char *str,
1042 struct arc_flags flags[],
1045 char *old_input_line_pointer;
1046 bfd_boolean saw_flg = FALSE;
1047 bfd_boolean saw_dot = FALSE;
1051 memset (flags, 0, sizeof (*flags) * nflg);
1053 /* Save and restore input_line_pointer around this function. */
1054 old_input_line_pointer = input_line_pointer;
1055 input_line_pointer = (char *) str;
1057 while (*input_line_pointer)
1059 switch (*input_line_pointer)
1066 input_line_pointer++;
1074 if (saw_flg && !saw_dot)
1077 if (num_flags >= nflg)
1080 flgnamelen = strspn (input_line_pointer, "abcdefghilmnopqrstvwxz");
1081 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
1084 memcpy (flags->name, input_line_pointer, flgnamelen);
1086 input_line_pointer += flgnamelen;
1096 input_line_pointer = old_input_line_pointer;
1101 as_bad (_("extra dot"));
1103 as_bad (_("unrecognized flag"));
1105 as_bad (_("failed to parse flags"));
1106 input_line_pointer = old_input_line_pointer;
1110 /* Apply the fixups in order. */
1113 apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
1117 for (i = 0; i < insn->nfixups; i++)
1119 struct arc_fixup *fixup = &insn->fixups[i];
1120 int size, pcrel, offset = 0;
1122 /* FIXME! the reloc size is wrong in the BFD file.
1123 When it is fixed please delete me. */
1124 size = (insn->short_insn && !fixup->islong) ? 2 : 4;
1127 offset = (insn->short_insn) ? 2 : 4;
1129 /* Some fixups are only used internally, thus no howto. */
1130 if ((int) fixup->reloc == 0)
1131 as_fatal (_("Unhandled reloc type"));
1133 if ((int) fixup->reloc < 0)
1135 /* FIXME! the reloc size is wrong in the BFD file.
1136 When it is fixed please enable me.
1137 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1138 pcrel = fixup->pcrel;
1142 reloc_howto_type *reloc_howto =
1143 bfd_reloc_type_lookup (stdoutput,
1144 (bfd_reloc_code_real_type) fixup->reloc);
1145 gas_assert (reloc_howto);
1147 /* FIXME! the reloc size is wrong in the BFD file.
1148 When it is fixed please enable me.
1149 size = bfd_get_reloc_size (reloc_howto); */
1150 pcrel = reloc_howto->pc_relative;
1153 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1155 fragP->fr_file, fragP->fr_line,
1156 (fixup->reloc < 0) ? "Internal" :
1157 bfd_get_reloc_code_name (fixup->reloc),
1160 fix_new_exp (fragP, fix + offset,
1161 size, &fixup->exp, pcrel, fixup->reloc);
1163 /* Check for ZOLs, and update symbol info if any. */
1164 if (LP_INSN (insn->insn))
1166 gas_assert (fixup->exp.X_add_symbol);
1167 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
1172 /* Actually output an instruction with its fixup. */
1175 emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
1179 pr_debug ("Emit insn : 0x%x\n", insn->insn);
1180 pr_debug ("\tShort : 0x%d\n", insn->short_insn);
1181 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
1183 /* Write out the instruction. */
1184 if (insn->short_insn)
1190 md_number_to_chars (f, insn->insn, 2);
1191 md_number_to_chars_midend (f + 2, insn->limm, 4);
1192 dwarf2_emit_insn (6);
1198 md_number_to_chars (f, insn->insn, 2);
1199 dwarf2_emit_insn (2);
1208 md_number_to_chars_midend (f, insn->insn, 4);
1209 md_number_to_chars_midend (f + 4, insn->limm, 4);
1210 dwarf2_emit_insn (8);
1216 md_number_to_chars_midend (f, insn->insn, 4);
1217 dwarf2_emit_insn (4);
1222 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1226 emit_insn1 (struct arc_insn *insn)
1228 /* How frag_var's args are currently configured:
1229 - rs_machine_dependent, to dictate it's a relaxation frag.
1230 - FRAG_MAX_GROWTH, maximum size of instruction
1231 - 0, variable size that might grow...unused by generic relaxation.
1232 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1233 - s, opand expression.
1234 - 0, offset but it's unused.
1235 - 0, opcode but it's unused. */
1236 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1237 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1239 if (frag_room () < FRAG_MAX_GROWTH)
1241 /* Handle differently when frag literal memory is exhausted.
1242 This is used because when there's not enough memory left in
1243 the current frag, a new frag is created and the information
1244 we put into frag_now->tc_frag_data is disregarded. */
1246 struct arc_relax_type relax_info_copy;
1247 relax_substateT subtype = frag_now->fr_subtype;
1249 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1250 sizeof (struct arc_relax_type));
1252 frag_wane (frag_now);
1253 frag_grow (FRAG_MAX_GROWTH);
1255 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1256 sizeof (struct arc_relax_type));
1258 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1262 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1263 frag_now->fr_subtype, s, 0, 0);
1267 emit_insn (struct arc_insn *insn)
1272 emit_insn0 (insn, NULL, FALSE);
1275 /* Check whether a symbol involves a register. */
1278 contains_register (symbolS *sym)
1282 expressionS *ex = symbol_get_value_expression (sym);
1284 return ((O_register == ex->X_op)
1285 && !contains_register (ex->X_add_symbol)
1286 && !contains_register (ex->X_op_symbol));
1292 /* Returns the register number within a symbol. */
1295 get_register (symbolS *sym)
1297 if (!contains_register (sym))
1300 expressionS *ex = symbol_get_value_expression (sym);
1301 return regno (ex->X_add_number);
1304 /* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1305 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
1308 generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1315 case BFD_RELOC_ARC_SDA_LDST:
1316 case BFD_RELOC_ARC_SDA_LDST1:
1317 case BFD_RELOC_ARC_SDA_LDST2:
1318 case BFD_RELOC_ARC_SDA16_LD:
1319 case BFD_RELOC_ARC_SDA16_LD1:
1320 case BFD_RELOC_ARC_SDA16_LD2:
1321 case BFD_RELOC_ARC_SDA16_ST2:
1322 case BFD_RELOC_ARC_SDA32_ME:
1329 /* Allocates a tok entry. */
1332 allocate_tok (expressionS *tok, int ntok, int cidx)
1334 if (ntok > MAX_INSN_ARGS - 2)
1335 return 0; /* No space left. */
1338 return 0; /* Incorect args. */
1340 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
1343 return 1; /* Success. */
1344 return allocate_tok (tok, ntok - 1, cidx);
1347 /* Search forward through all variants of an opcode looking for a
1350 static const struct arc_opcode *
1351 find_opcode_match (const struct arc_opcode *first_opcode,
1354 struct arc_flags *first_pflag,
1358 const struct arc_opcode *opcode = first_opcode;
1360 int got_cpu_match = 0;
1361 expressionS bktok[MAX_INSN_ARGS];
1365 memset (&emptyE, 0, sizeof (emptyE));
1366 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1371 const unsigned char *opidx;
1372 const unsigned char *flgidx;
1373 int tokidx = 0, lnflg, i;
1374 const expressionS *t = &emptyE;
1376 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1377 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
1379 /* Don't match opcodes that don't exist on this
1381 if (!(opcode->cpu & arc_target))
1384 if (is_code_density_p (opcode) && !(arc_features & ARC_CD))
1390 /* Check the operands. */
1391 for (opidx = opcode->operands; *opidx; ++opidx)
1393 const struct arc_operand *operand = &arc_operands[*opidx];
1395 /* Only take input from real operands. */
1396 if ((operand->flags & ARC_OPERAND_FAKE)
1397 && !(operand->flags & ARC_OPERAND_BRAKET))
1400 /* When we expect input, make sure we have it. */
1404 /* Match operand type with expression type. */
1405 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1407 case ARC_OPERAND_IR:
1408 /* Check to be a register. */
1409 if ((tok[tokidx].X_op != O_register
1410 || !is_ir_num (tok[tokidx].X_add_number))
1411 && !(operand->flags & ARC_OPERAND_IGNORE))
1414 /* If expect duplicate, make sure it is duplicate. */
1415 if (operand->flags & ARC_OPERAND_DUPLICATE)
1417 /* Check for duplicate. */
1418 if (t->X_op != O_register
1419 || !is_ir_num (t->X_add_number)
1420 || (regno (t->X_add_number) !=
1421 regno (tok[tokidx].X_add_number)))
1425 /* Special handling? */
1426 if (operand->insert)
1428 const char *errmsg = NULL;
1429 (*operand->insert)(0,
1430 regno (tok[tokidx].X_add_number),
1434 if (operand->flags & ARC_OPERAND_IGNORE)
1436 /* Missing argument, create one. */
1437 if (!allocate_tok (tok, ntok - 1, tokidx))
1440 tok[tokidx].X_op = O_absent;
1451 case ARC_OPERAND_BRAKET:
1452 /* Check if bracket is also in opcode table as
1454 if (tok[tokidx].X_op != O_bracket)
1458 case ARC_OPERAND_LIMM:
1459 case ARC_OPERAND_SIGNED:
1460 case ARC_OPERAND_UNSIGNED:
1461 switch (tok[tokidx].X_op)
1469 /* Got an (too) early bracket, check if it is an
1470 ignored operand. N.B. This procedure works only
1471 when bracket is the last operand! */
1472 if (!(operand->flags & ARC_OPERAND_IGNORE))
1474 /* Insert the missing operand. */
1475 if (!allocate_tok (tok, ntok - 1, tokidx))
1478 tok[tokidx].X_op = O_absent;
1483 /* Check the range. */
1484 if (operand->bits != 32
1485 && !(operand->flags & ARC_OPERAND_NCHK))
1487 offsetT min, max, val;
1488 val = tok[tokidx].X_add_number;
1490 if (operand->flags & ARC_OPERAND_SIGNED)
1492 max = (1 << (operand->bits - 1)) - 1;
1493 min = -(1 << (operand->bits - 1));
1497 max = (1 << operand->bits) - 1;
1501 if (val < min || val > max)
1504 /* Check alignmets. */
1505 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1509 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1513 else if (operand->flags & ARC_OPERAND_NCHK)
1515 if (operand->insert)
1517 const char *errmsg = NULL;
1518 (*operand->insert)(0,
1519 tok[tokidx].X_add_number,
1530 /* Check if it is register range. */
1531 if ((tok[tokidx].X_add_number == 0)
1532 && contains_register (tok[tokidx].X_add_symbol)
1533 && contains_register (tok[tokidx].X_op_symbol))
1537 regs = get_register (tok[tokidx].X_add_symbol);
1539 regs |= get_register (tok[tokidx].X_op_symbol);
1540 if (operand->insert)
1542 const char *errmsg = NULL;
1543 (*operand->insert)(0,
1554 if (operand->default_reloc == 0)
1555 goto match_failed; /* The operand needs relocation. */
1557 /* Relocs requiring long immediate. FIXME! make it
1558 generic and move it to a function. */
1559 switch (tok[tokidx].X_md)
1568 if (!(operand->flags & ARC_OPERAND_LIMM))
1571 if (!generic_reloc_p (operand->default_reloc))
1578 /* If expect duplicate, make sure it is duplicate. */
1579 if (operand->flags & ARC_OPERAND_DUPLICATE)
1581 if (t->X_op == O_illegal
1582 || t->X_op == O_absent
1583 || t->X_op == O_register
1584 || (t->X_add_number != tok[tokidx].X_add_number))
1591 /* Everything else should have been fake. */
1599 /* Setup ready for flag parsing. */
1601 for (i = 0; i < nflgs; i++)
1602 first_pflag [i].code = 0;
1604 /* Check the flags. Iterate over the valid flag classes. */
1605 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1607 /* Get a valid flag class. */
1608 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1609 const unsigned *flgopridx;
1612 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1614 const struct arc_flag_operand *flg_operand;
1615 struct arc_flags *pflag = first_pflag;
1617 flg_operand = &arc_flag_operands[*flgopridx];
1618 for (i = 0; i < nflgs; i++, pflag++)
1620 /* Match against the parsed flags. */
1621 if (!strcmp (flg_operand->name, pflag->name))
1623 if (pflag->code != 0)
1626 pflag->code = *flgopridx;
1628 break; /* goto next flag class and parsed flag. */
1633 if (cl_flags->class == F_CLASS_REQUIRED && cl_matches == 0)
1635 if (cl_flags->class == F_CLASS_OPTIONAL && cl_matches > 1)
1638 /* Did I check all the parsed flags? */
1643 /* Possible match -- did we use all of our input? */
1653 /* Restore the original parameters. */
1654 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
1657 while (++opcode - arc_opcodes < (int) arc_num_opcodes
1658 && !strcmp (opcode->name, first_opcode->name));
1661 *pcpumatch = got_cpu_match;
1666 /* Swap operand tokens. */
1669 swap_operand (expressionS *operand_array,
1671 unsigned destination)
1673 expressionS cpy_operand;
1674 expressionS *src_operand;
1675 expressionS *dst_operand;
1678 if (source == destination)
1681 src_operand = &operand_array[source];
1682 dst_operand = &operand_array[destination];
1683 size = sizeof (expressionS);
1685 /* Make copy of operand to swap with and swap. */
1686 memcpy (&cpy_operand, dst_operand, size);
1687 memcpy (dst_operand, src_operand, size);
1688 memcpy (src_operand, &cpy_operand, size);
1691 /* Check if *op matches *tok type.
1692 Returns FALSE if they don't match, TRUE if they match. */
1695 pseudo_operand_match (const expressionS *tok,
1696 const struct arc_operand_operation *op)
1698 offsetT min, max, val;
1700 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
1706 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
1708 else if (!(operand_real->flags & ARC_OPERAND_IR))
1710 val = tok->X_add_number + op->count;
1711 if (operand_real->flags & ARC_OPERAND_SIGNED)
1713 max = (1 << (operand_real->bits - 1)) - 1;
1714 min = -(1 << (operand_real->bits - 1));
1718 max = (1 << operand_real->bits) - 1;
1721 if (min <= val && val <= max)
1727 /* Handle all symbols as long immediates or signed 9. */
1728 if (operand_real->flags & ARC_OPERAND_LIMM ||
1729 ((operand_real->flags & ARC_OPERAND_SIGNED) && operand_real->bits == 9))
1734 if (operand_real->flags & ARC_OPERAND_IR)
1739 if (operand_real->flags & ARC_OPERAND_BRAKET)
1750 /* Find pseudo instruction in array. */
1752 static const struct arc_pseudo_insn *
1753 find_pseudo_insn (const char *opname,
1755 const expressionS *tok)
1757 const struct arc_pseudo_insn *pseudo_insn = NULL;
1758 const struct arc_operand_operation *op;
1762 for (i = 0; i < arc_num_pseudo_insn; ++i)
1764 pseudo_insn = &arc_pseudo_insns[i];
1765 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
1767 op = pseudo_insn->operand;
1768 for (j = 0; j < ntok; ++j)
1769 if (!pseudo_operand_match (&tok[j], &op[j]))
1772 /* Found the right instruction. */
1780 /* Assumes the expressionS *tok is of sufficient size. */
1782 static const struct arc_opcode *
1783 find_special_case_pseudo (const char *opname,
1787 struct arc_flags *pflags)
1789 const struct arc_pseudo_insn *pseudo_insn = NULL;
1790 const struct arc_operand_operation *operand_pseudo;
1791 const struct arc_operand *operand_real;
1793 char construct_operand[MAX_CONSTR_STR];
1795 /* Find whether opname is in pseudo instruction array. */
1796 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
1798 if (pseudo_insn == NULL)
1801 /* Handle flag, Limited to one flag at the moment. */
1802 if (pseudo_insn->flag_r != NULL)
1803 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
1804 MAX_INSN_FLGS - *nflgs);
1806 /* Handle operand operations. */
1807 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
1809 operand_pseudo = &pseudo_insn->operand[i];
1810 operand_real = &arc_operands[operand_pseudo->operand_idx];
1812 if (operand_real->flags & ARC_OPERAND_BRAKET &&
1813 !operand_pseudo->needs_insert)
1816 /* Has to be inserted (i.e. this token does not exist yet). */
1817 if (operand_pseudo->needs_insert)
1819 if (operand_real->flags & ARC_OPERAND_BRAKET)
1821 tok[i].X_op = O_bracket;
1826 /* Check if operand is a register or constant and handle it
1828 if (operand_real->flags & ARC_OPERAND_IR)
1829 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
1830 operand_pseudo->count);
1832 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
1833 operand_pseudo->count);
1835 tokenize_arguments (construct_operand, &tok[i], 1);
1839 else if (operand_pseudo->count)
1841 /* Operand number has to be adjusted accordingly (by operand
1843 switch (tok[i].X_op)
1846 tok[i].X_add_number += operand_pseudo->count;
1859 /* Swap operands if necessary. Only supports one swap at the
1861 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
1863 operand_pseudo = &pseudo_insn->operand[i];
1865 if (operand_pseudo->swap_operand_idx == i)
1868 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
1870 /* Prevent a swap back later by breaking out. */
1874 return (const struct arc_opcode *)
1875 hash_find (arc_opcode_hash, pseudo_insn->mnemonic_r);
1878 static const struct arc_opcode *
1879 find_special_case_flag (const char *opname,
1881 struct arc_flags *pflags)
1885 unsigned flag_idx, flag_arr_idx;
1886 size_t flaglen, oplen;
1887 const struct arc_flag_special *arc_flag_special_opcode;
1888 const struct arc_opcode *opcode;
1890 /* Search for special case instruction. */
1891 for (i = 0; i < arc_num_flag_special; i++)
1893 arc_flag_special_opcode = &arc_flag_special_cases[i];
1894 oplen = strlen (arc_flag_special_opcode->name);
1896 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
1899 /* Found a potential special case instruction, now test for
1901 for (flag_arr_idx = 0;; ++flag_arr_idx)
1903 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
1905 break; /* End of array, nothing found. */
1907 flagnm = arc_flag_operands[flag_idx].name;
1908 flaglen = strlen (flagnm);
1909 if (strcmp (opname + oplen, flagnm) == 0)
1911 opcode = (const struct arc_opcode *)
1912 hash_find (arc_opcode_hash,
1913 arc_flag_special_opcode->name);
1915 if (*nflgs + 1 > MAX_INSN_FLGS)
1917 memcpy (pflags[*nflgs].name, flagnm, flaglen);
1918 pflags[*nflgs].name[flaglen] = '\0';
1927 /* Used to find special case opcode. */
1929 static const struct arc_opcode *
1930 find_special_case (const char *opname,
1932 struct arc_flags *pflags,
1936 const struct arc_opcode *opcode;
1938 opcode = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
1941 opcode = find_special_case_flag (opname, nflgs, pflags);
1947 preprocess_operands (const struct arc_opcode *opcode,
1955 const struct arc_aux_reg *auxr;
1957 for (i = 0; i < ntok; i++)
1959 switch (tok[i].X_op)
1963 break; /* Throw and error. */
1966 if (opcode->class != AUXREG)
1968 /* Convert the symbol to a constant if possible. */
1969 p = S_GET_NAME (tok[i].X_add_symbol);
1972 auxr = &arc_aux_regs[0];
1973 for (j = 0; j < arc_num_aux_regs; j++, auxr++)
1974 if (len == auxr->length
1975 && strcasecmp (auxr->name, p) == 0)
1977 tok[i].X_op = O_constant;
1978 tok[i].X_add_number = auxr->address;
1988 /* Given an opcode name, pre-tockenized set of argumenst and the
1989 opcode flags, take it all the way through emission. */
1992 assemble_tokens (const char *opname,
1995 struct arc_flags *pflags,
1998 bfd_boolean found_something = FALSE;
1999 const struct arc_opcode *opcode;
2002 /* Search opcodes. */
2003 opcode = (const struct arc_opcode *) hash_find (arc_opcode_hash, opname);
2005 /* Couldn't find opcode conventional way, try special cases. */
2007 opcode = find_special_case (opname, &nflgs, pflags, tok, &ntok);
2011 pr_debug ("%s:%d: assemble_tokens: %s trying opcode 0x%08X\n",
2012 frag_now->fr_file, frag_now->fr_line, opcode->name,
2015 preprocess_operands (opcode, tok, ntok);
2017 found_something = TRUE;
2018 opcode = find_opcode_match (opcode, tok, &ntok, pflags, nflgs, &cpumatch);
2021 struct arc_insn insn;
2022 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2028 if (found_something)
2031 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
2033 as_bad (_("opcode '%s' not supported for target %s"), opname,
2037 as_bad (_("unknown opcode '%s'"), opname);
2040 /* The public interface to the instruction assembler. */
2043 md_assemble (char *str)
2046 expressionS tok[MAX_INSN_ARGS];
2049 struct arc_flags flags[MAX_INSN_FLGS];
2051 /* Split off the opcode. */
2052 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
2053 opname = xmalloc (opnamelen + 1);
2054 memcpy (opname, str, opnamelen);
2055 opname[opnamelen] = '\0';
2057 /* Signalize we are assmbling the instructions. */
2058 assembling_insn = TRUE;
2060 /* Tokenize the flags. */
2061 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2063 as_bad (_("syntax error"));
2067 /* Scan up to the end of the mnemonic which must end in space or end
2070 for (; *str != '\0'; str++)
2074 /* Tokenize the rest of the line. */
2075 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
2077 as_bad (_("syntax error"));
2081 /* Finish it off. */
2082 assemble_tokens (opname, tok, ntok, flags, nflg);
2083 assembling_insn = FALSE;
2086 /* Callback to insert a register into the hash table. */
2089 declare_register (const char *name, int number)
2092 symbolS *regS = symbol_create (name, reg_section,
2093 number, &zero_address_frag);
2095 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2097 as_fatal ("Inserting \"%s\" into register table failed: %s",
2101 /* Construct symbols for each of the general registers. */
2104 declare_register_set (void)
2107 for (i = 0; i < 64; ++i)
2111 sprintf (name, "r%d", i);
2112 declare_register (name, i);
2113 if ((i & 0x01) == 0)
2115 sprintf (name, "r%dr%d", i, i+1);
2116 declare_register (name, i);
2121 /* Port-specific assembler initialization. This function is called
2122 once, at assembler startup time. */
2129 if (!mach_type_specified_p)
2130 arc_select_cpu ("arc700");
2132 /* The endianness can be chosen "at the factory". */
2133 target_big_endian = byte_order == BIG_ENDIAN;
2135 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
2136 as_warn (_("could not set architecture and machine"));
2138 /* Set elf header flags. */
2139 bfd_set_private_flags (stdoutput, arc_eflag);
2141 /* Set up a hash table for the instructions. */
2142 arc_opcode_hash = hash_new ();
2143 if (arc_opcode_hash == NULL)
2144 as_fatal (_("Virtual memory exhausted"));
2146 /* Initialize the hash table with the insns. */
2147 for (i = 0; i < arc_num_opcodes;)
2149 const char *name, *retval;
2151 name = arc_opcodes[i].name;
2152 retval = hash_insert (arc_opcode_hash, name, (void *) &arc_opcodes[i]);
2154 as_fatal (_("internal error: can't hash opcode '%s': %s"),
2157 while (++i < arc_num_opcodes
2158 && (arc_opcodes[i].name == name
2159 || !strcmp (arc_opcodes[i].name, name)))
2163 /* Register declaration. */
2164 arc_reg_hash = hash_new ();
2165 if (arc_reg_hash == NULL)
2166 as_fatal (_("Virtual memory exhausted"));
2168 declare_register_set ();
2169 declare_register ("gp", 26);
2170 declare_register ("fp", 27);
2171 declare_register ("sp", 28);
2172 declare_register ("ilink", 29);
2173 declare_register ("ilink1", 29);
2174 declare_register ("ilink2", 30);
2175 declare_register ("blink", 31);
2177 declare_register ("mlo", 57);
2178 declare_register ("mmid", 58);
2179 declare_register ("mhi", 59);
2181 declare_register ("acc1", 56);
2182 declare_register ("acc2", 57);
2184 declare_register ("lp_count", 60);
2185 declare_register ("pcl", 63);
2187 /* Initialize the last instructions. */
2188 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
2191 /* Write a value out to the object file, using the appropriate
2195 md_number_to_chars (char *buf,
2199 if (target_big_endian)
2200 number_to_chars_bigendian (buf, val, n);
2202 number_to_chars_littleendian (buf, val, n);
2205 /* Round up a section size to the appropriate boundary. */
2208 md_section_align (segT segment,
2211 int align = bfd_get_section_alignment (stdoutput, segment);
2213 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
2216 /* The location from which a PC relative jump should be calculated,
2217 given a PC relative reloc. */
2220 md_pcrel_from_section (fixS *fixP,
2223 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
2225 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
2227 if (fixP->fx_addsy != (symbolS *) NULL
2228 && (!S_IS_DEFINED (fixP->fx_addsy)
2229 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2231 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
2233 /* The symbol is undefined (or is defined but not in this section).
2234 Let the linker figure it out. */
2238 if ((int) fixP->fx_r_type < 0)
2240 /* These are the "internal" relocations. Align them to
2241 32 bit boundary (PCL), for the moment. */
2246 switch (fixP->fx_r_type)
2248 case BFD_RELOC_ARC_PC32:
2249 /* The hardware calculates relative to the start of the
2250 insn, but this relocation is relative to location of the
2251 LIMM, compensate. The base always needs to be
2252 substracted by 4 as we do not support this type of PCrel
2253 relocation for short instructions. */
2256 case BFD_RELOC_ARC_PLT32:
2257 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2258 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2259 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2260 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2262 case BFD_RELOC_ARC_S21H_PCREL:
2263 case BFD_RELOC_ARC_S25H_PCREL:
2264 case BFD_RELOC_ARC_S13_PCREL:
2265 case BFD_RELOC_ARC_S21W_PCREL:
2266 case BFD_RELOC_ARC_S25W_PCREL:
2270 as_bad_where (fixP->fx_file, fixP->fx_line,
2271 _("unhandled reloc %s in md_pcrel_from_section"),
2272 bfd_get_reloc_code_name (fixP->fx_r_type));
2277 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
2278 fixP->fx_frag->fr_address, fixP->fx_where, base,
2279 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2280 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2285 /* Given a BFD relocation find the coresponding operand. */
2287 static const struct arc_operand *
2288 find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2292 for (i = 0; i < arc_num_operands; i++)
2293 if (arc_operands[i].default_reloc == reloc)
2294 return &arc_operands[i];
2298 /* Insert an operand value into an instruction. */
2301 insert_operand (unsigned insn,
2302 const struct arc_operand *operand,
2307 offsetT min = 0, max = 0;
2309 if (operand->bits != 32
2310 && !(operand->flags & ARC_OPERAND_NCHK)
2311 && !(operand->flags & ARC_OPERAND_FAKE))
2313 if (operand->flags & ARC_OPERAND_SIGNED)
2315 max = (1 << (operand->bits - 1)) - 1;
2316 min = -(1 << (operand->bits - 1));
2320 max = (1 << operand->bits) - 1;
2324 if (val < min || val > max)
2325 as_bad_value_out_of_range (_("operand"),
2326 val, min, max, file, line);
2329 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2330 min, val, max, insn);
2332 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2334 as_bad_where (file, line,
2335 _("Unaligned operand. Needs to be 32bit aligned"));
2337 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2339 as_bad_where (file, line,
2340 _("Unaligned operand. Needs to be 16bit aligned"));
2342 if (operand->insert)
2344 const char *errmsg = NULL;
2346 insn = (*operand->insert) (insn, val, &errmsg);
2348 as_warn_where (file, line, "%s", errmsg);
2352 if (operand->flags & ARC_OPERAND_TRUNCATE)
2354 if (operand->flags & ARC_OPERAND_ALIGNED32)
2356 if (operand->flags & ARC_OPERAND_ALIGNED16)
2359 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2364 /* Apply a fixup to the object code. At this point all symbol values
2365 should be fully resolved, and we attempt to completely resolve the
2366 reloc. If we can not do that, we determine the correct reloc code
2367 and put it back in the fixup. To indicate that a fixup has been
2368 eliminated, set fixP->fx_done. */
2371 md_apply_fix (fixS *fixP,
2375 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2376 valueT value = *valP;
2378 symbolS *fx_addsy, *fx_subsy;
2380 segT add_symbol_segment = absolute_section;
2381 segT sub_symbol_segment = absolute_section;
2382 const struct arc_operand *operand = NULL;
2383 extended_bfd_reloc_code_real_type reloc;
2385 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2386 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2387 ((int) fixP->fx_r_type < 0) ? "Internal":
2388 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2391 fx_addsy = fixP->fx_addsy;
2392 fx_subsy = fixP->fx_subsy;
2397 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
2401 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2402 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2403 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2405 resolve_symbol_value (fx_subsy);
2406 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
2408 if (sub_symbol_segment == absolute_section)
2410 /* The symbol is really a constant. */
2411 fx_offset -= S_GET_VALUE (fx_subsy);
2416 as_bad_where (fixP->fx_file, fixP->fx_line,
2417 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2418 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2419 segment_name (add_symbol_segment),
2420 S_GET_NAME (fx_subsy),
2421 segment_name (sub_symbol_segment));
2427 && !S_IS_WEAK (fx_addsy))
2429 if (add_symbol_segment == seg
2432 value += S_GET_VALUE (fx_addsy);
2433 value -= md_pcrel_from_section (fixP, seg);
2435 fixP->fx_pcrel = FALSE;
2437 else if (add_symbol_segment == absolute_section)
2439 value = fixP->fx_offset;
2440 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2442 fixP->fx_pcrel = FALSE;
2447 fixP->fx_done = TRUE;
2452 && ((S_IS_DEFINED (fx_addsy)
2453 && S_GET_SEGMENT (fx_addsy) != seg)
2454 || S_IS_WEAK (fx_addsy)))
2455 value += md_pcrel_from_section (fixP, seg);
2457 switch (fixP->fx_r_type)
2459 case BFD_RELOC_ARC_32_ME:
2460 /* This is a pc-relative value in a LIMM. Adjust it to the
2461 address of the instruction not to the address of the
2462 LIMM. Note: it is not anylonger valid this afirmation as
2463 the linker consider ARC_PC32 a fixup to entire 64 bit
2465 fixP->fx_offset += fixP->fx_frag->fr_address;
2468 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2470 case BFD_RELOC_ARC_PC32:
2471 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
2474 if ((int) fixP->fx_r_type < 0)
2475 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2481 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2482 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2483 ((int) fixP->fx_r_type < 0) ? "Internal":
2484 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2488 /* Now check for TLS relocations. */
2489 reloc = fixP->fx_r_type;
2492 case BFD_RELOC_ARC_TLS_DTPOFF:
2493 case BFD_RELOC_ARC_TLS_LE_32:
2497 case BFD_RELOC_ARC_TLS_GD_GOT:
2498 case BFD_RELOC_ARC_TLS_IE_GOT:
2499 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2502 case BFD_RELOC_ARC_TLS_GD_LD:
2503 gas_assert (!fixP->fx_offset);
2506 = (S_GET_VALUE (fixP->fx_subsy)
2507 - fixP->fx_frag->fr_address- fixP->fx_where);
2508 fixP->fx_subsy = NULL;
2510 case BFD_RELOC_ARC_TLS_GD_CALL:
2511 /* These two relocs are there just to allow ld to change the tls
2512 model for this symbol, by patching the code. The offset -
2513 and scale, if any - will be installed by the linker. */
2514 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2517 case BFD_RELOC_ARC_TLS_LE_S9:
2518 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
2519 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2531 /* Addjust the value if we have a constant. */
2534 /* For hosts with longs bigger than 32-bits make sure that the top
2535 bits of a 32-bit negative value read in by the parser are set,
2536 so that the correct comparisons are made. */
2537 if (value & 0x80000000)
2538 value |= (-1L << 31);
2540 reloc = fixP->fx_r_type;
2548 case BFD_RELOC_ARC_32_PCREL:
2549 md_number_to_chars (fixpos, value, fixP->fx_size);
2552 case BFD_RELOC_ARC_GOTPC32:
2553 /* I cannot fix an GOTPC relocation because I need to relax it
2554 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2555 as_bad (_("Unsupported operation on reloc"));
2558 case BFD_RELOC_ARC_TLS_DTPOFF:
2559 case BFD_RELOC_ARC_TLS_LE_32:
2560 gas_assert (!fixP->fx_addsy);
2561 gas_assert (!fixP->fx_subsy);
2563 case BFD_RELOC_ARC_GOTOFF:
2564 case BFD_RELOC_ARC_32_ME:
2565 case BFD_RELOC_ARC_PC32:
2566 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2569 case BFD_RELOC_ARC_PLT32:
2570 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2573 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2574 reloc = BFD_RELOC_ARC_S25W_PCREL;
2577 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2578 reloc = BFD_RELOC_ARC_S21H_PCREL;
2581 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2582 reloc = BFD_RELOC_ARC_S25W_PCREL;
2585 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2586 reloc = BFD_RELOC_ARC_S21W_PCREL;
2588 case BFD_RELOC_ARC_S25W_PCREL:
2589 case BFD_RELOC_ARC_S21W_PCREL:
2590 case BFD_RELOC_ARC_S21H_PCREL:
2591 case BFD_RELOC_ARC_S25H_PCREL:
2592 case BFD_RELOC_ARC_S13_PCREL:
2594 operand = find_operand_for_reloc (reloc);
2595 gas_assert (operand);
2600 if ((int) fixP->fx_r_type >= 0)
2601 as_fatal (_("unhandled relocation type %s"),
2602 bfd_get_reloc_code_name (fixP->fx_r_type));
2604 /* The rest of these fixups needs to be completely resolved as
2606 if (fixP->fx_addsy != 0
2607 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
2608 as_bad_where (fixP->fx_file, fixP->fx_line,
2609 _("non-absolute expression in constant field"));
2611 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
2612 operand = &arc_operands[-(int) fixP->fx_r_type];
2617 if (target_big_endian)
2619 switch (fixP->fx_size)
2622 insn = bfd_getb32 (fixpos);
2625 insn = bfd_getb16 (fixpos);
2628 as_bad_where (fixP->fx_file, fixP->fx_line,
2629 _("unknown fixup size"));
2635 switch (fixP->fx_size)
2638 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
2641 insn = bfd_getl16 (fixpos);
2644 as_bad_where (fixP->fx_file, fixP->fx_line,
2645 _("unknown fixup size"));
2649 insn = insert_operand (insn, operand, (offsetT) value,
2650 fixP->fx_file, fixP->fx_line);
2652 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
2655 /* Prepare machine-dependent frags for relaxation.
2657 Called just before relaxation starts. Any symbol that is now undefined
2658 will not become defined.
2660 Return the correct fr_subtype in the frag.
2662 Return the initial "guess for fr_var" to caller. The guess for fr_var
2663 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
2664 or fr_var contributes to our returned value.
2666 Although it may not be explicit in the frag, pretend
2667 fr_var starts with a value. */
2670 md_estimate_size_before_relax (fragS *fragP,
2675 /* If the symbol is not located within the same section AND it's not
2676 an absolute section, use the maximum. OR if the symbol is a
2677 constant AND the insn is by nature not pc-rel, use the maximum.
2678 OR if the symbol is being equated against another symbol, use the
2679 maximum. OR if the symbol is weak use the maximum. */
2680 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
2681 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
2682 || (symbol_constant_p (fragP->fr_symbol)
2683 && !fragP->tc_frag_data.pcrel)
2684 || symbol_equated_p (fragP->fr_symbol)
2685 || S_IS_WEAK (fragP->fr_symbol))
2687 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
2688 ++fragP->fr_subtype;
2691 growth = md_relax_table[fragP->fr_subtype].rlx_length;
2692 fragP->fr_var = growth;
2694 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
2695 fragP->fr_file, fragP->fr_line, growth);
2700 /* Translate internal representation of relocation info to BFD target
2704 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
2708 bfd_reloc_code_real_type code;
2710 reloc = (arelent *) xmalloc (sizeof (* reloc));
2711 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2712 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
2713 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
2715 /* Make sure none of our internal relocations make it this far.
2716 They'd better have been fully resolved by this point. */
2717 gas_assert ((int) fixP->fx_r_type > 0);
2719 code = fixP->fx_r_type;
2721 /* if we have something like add gp, pcl,
2722 _GLOBAL_OFFSET_TABLE_@gotpc. */
2723 if (code == BFD_RELOC_ARC_GOTPC32
2725 && fixP->fx_addsy == GOT_symbol)
2726 code = BFD_RELOC_ARC_GOTPC;
2728 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
2729 if (reloc->howto == NULL)
2731 as_bad_where (fixP->fx_file, fixP->fx_line,
2732 _("cannot represent `%s' relocation in object file"),
2733 bfd_get_reloc_code_name (code));
2737 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
2738 as_fatal (_("internal error? cannot generate `%s' relocation"),
2739 bfd_get_reloc_code_name (code));
2741 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
2743 if (code == BFD_RELOC_ARC_TLS_DTPOFF
2744 || code == BFD_RELOC_ARC_TLS_DTPOFF_S9)
2747 = fixP->fx_subsy ? symbol_get_bfdsym (fixP->fx_subsy) : NULL;
2748 /* We just want to store a 24 bit index, but we have to wait
2749 till after write_contents has been called via
2750 bfd_map_over_sections before we can get the index from
2751 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
2752 function is elf32-arc.c has to pick up the slack.
2753 Unfortunately, this leads to problems with hosts that have
2754 pointers wider than long (bfd_vma). There would be various
2755 ways to handle this, all error-prone :-( */
2756 reloc->addend = (bfd_vma) sym;
2757 if ((asymbol *) reloc->addend != sym)
2759 as_bad ("Can't store pointer\n");
2764 reloc->addend = fixP->fx_offset;
2769 /* Perform post-processing of machine-dependent frags after relaxation.
2770 Called after relaxation is finished.
2771 In: Address of frag.
2772 fr_type == rs_machine_dependent.
2773 fr_subtype is what the address relaxed to.
2775 Out: Any fixS:s and constants are set up. */
2778 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
2779 segT segment ATTRIBUTE_UNUSED,
2782 const relax_typeS *table_entry;
2784 const struct arc_opcode *opcode;
2785 struct arc_insn insn;
2787 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
2789 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
2790 dest = fragP->fr_literal + fix;
2791 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
2793 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
2794 fragP->fr_file, fragP->fr_line,
2795 fragP->fr_subtype, fix, fragP->fr_var);
2797 if (fragP->fr_subtype <= 0
2798 && fragP->fr_subtype >= arc_num_relax_opcodes)
2799 as_fatal (_("no relaxation found for this instruction."));
2801 opcode = &arc_relax_opcodes[fragP->fr_subtype];
2803 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
2804 relax_arg->nflg, &insn);
2806 apply_fixups (&insn, fragP, fix);
2808 size = insn.short_insn ? (insn.has_limm ? 6 : 2) : (insn.has_limm ? 8 : 4);
2809 gas_assert (table_entry->rlx_length == size);
2810 emit_insn0 (&insn, dest, TRUE);
2812 fragP->fr_fix += table_entry->rlx_length;
2816 /* We have no need to default values of symbols. We could catch
2817 register names here, but that is handled by inserting them all in
2818 the symbol table to begin with. */
2821 md_undefined_symbol (char *name)
2823 /* The arc abi demands that a GOT[0] should be referencible as
2824 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
2825 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
2827 && (*(name+1) == 'G')
2828 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
2830 && (*(name+1) == 'D')
2831 && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
2835 if (symbol_find (name))
2836 as_bad ("GOT already in symbol table");
2838 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
2839 (valueT) 0, &zero_address_frag);
2846 /* Turn a string in input_line_pointer into a floating point constant
2847 of type type, and store the appropriate bytes in *litP. The number
2848 of LITTLENUMS emitted is stored in *sizeP. An error message is
2849 returned, or NULL on OK. */
2852 md_atof (int type, char *litP, int *sizeP)
2854 return ieee_md_atof (type, litP, sizeP, target_big_endian);
2857 /* Called for any expression that can not be recognized. When the
2858 function is called, `input_line_pointer' will point to the start of
2862 md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
2864 char *p = input_line_pointer;
2867 input_line_pointer++;
2868 expressionP->X_op = O_symbol;
2869 expression (expressionP);
2873 /* This function is called from the function 'expression', it attempts
2874 to parse special names (in our case register names). It fills in
2875 the expression with the identified register. It returns TRUE if
2876 it is a register and FALSE otherwise. */
2879 arc_parse_name (const char *name,
2880 struct expressionS *e)
2884 if (!assembling_insn)
2887 /* Handle only registers. */
2888 if (e->X_op != O_absent)
2891 sym = hash_find (arc_reg_hash, name);
2894 e->X_op = O_register;
2895 e->X_add_number = S_GET_VALUE (sym);
2902 Invocation line includes a switch not recognized by the base assembler.
2903 See if it's a processor-specific option.
2905 New options (supported) are:
2907 -mcpu=<cpu name> Assemble for selected processor
2908 -EB/-mbig-endian Big-endian
2909 -EL/-mlittle-endian Little-endian
2910 -mrelax Enable relaxation
2912 The following CPU names are recognized:
2913 arc700, av2em, av2hs. */
2916 md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
2922 return md_parse_option (OPTION_MCPU, "arc600");
2925 return md_parse_option (OPTION_MCPU, "arc700");
2928 return md_parse_option (OPTION_MCPU, "arcem");
2931 return md_parse_option (OPTION_MCPU, "archs");
2935 arc_select_cpu (arg);
2936 mach_type_specified_p = 1;
2941 arc_target_format = "elf32-bigarc";
2942 byte_order = BIG_ENDIAN;
2946 arc_target_format = "elf32-littlearc";
2947 byte_order = LITTLE_ENDIAN;
2951 /* This option has an effect only on ARC EM. */
2952 if (arc_target & ARC_OPCODE_ARCv2EM)
2953 arc_features |= ARC_CD;
2957 relaxation_state = 1;
2960 case OPTION_USER_MODE:
2961 case OPTION_LD_EXT_MASK:
2964 case OPTION_BARREL_SHIFT:
2965 case OPTION_MIN_MAX:
2972 case OPTION_XMAC_D16:
2973 case OPTION_XMAC_24:
2974 case OPTION_DSP_PACKA:
2977 case OPTION_TELEPHONY:
2978 case OPTION_XYMEMORY:
2983 /* Dummy options are accepted but have no effect. */
2994 md_show_usage (FILE *stream)
2996 fprintf (stream, _("ARC-specific assembler options:\n"));
2998 fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3000 " -mcode-density\t enable code density option for ARC EM\n");
3002 fprintf (stream, _("\
3003 -EB assemble code for a big-endian cpu\n"));
3004 fprintf (stream, _("\
3005 -EL assemble code for a little-endian cpu\n"));
3006 fprintf (stream, _("\
3007 -mrelax Enable relaxation\n"));
3011 /* Find the proper relocation for the given opcode. */
3013 static extended_bfd_reloc_code_real_type
3014 find_reloc (const char *name,
3015 const char *opcodename,
3016 const struct arc_flags *pflags,
3018 extended_bfd_reloc_code_real_type reloc)
3022 bfd_boolean found_flag, tmp;
3023 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3025 for (i = 0; i < arc_num_equiv_tab; i++)
3027 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3029 /* Find the entry. */
3030 if (strcmp (name, r->name))
3032 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3039 unsigned * psflg = (unsigned *)r->flags;
3043 for (j = 0; j < nflg; j++)
3044 if (!strcmp (pflags[j].name,
3045 arc_flag_operands[*psflg].name))
3066 if (reloc != r->oldreloc)
3073 if (ret == BFD_RELOC_UNUSED)
3074 as_bad (_("Unable to find %s relocation for instruction %s"),
3079 /* All the symbol types that are allowed to be used for
3083 may_relax_expr (expressionS tok)
3085 /* Check if we have unrelaxable relocs. */
3110 /* Checks if flags are in line with relaxable insn. */
3113 relaxable_flag (const struct arc_relaxable_ins *ins,
3114 const struct arc_flags *pflags,
3117 unsigned flag_class,
3122 const struct arc_flag_operand *flag_opand;
3123 int i, counttrue = 0;
3125 /* Iterate through flags classes. */
3126 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3128 /* Iterate through flags in flag class. */
3129 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3132 flag_opand = &arc_flag_operands[flag];
3133 /* Iterate through flags in ins to compare. */
3134 for (i = 0; i < nflgs; ++i)
3136 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3147 /* If counttrue == nflgs, then all flags have been found. */
3148 return (counttrue == nflgs ? TRUE : FALSE);
3151 /* Checks if operands are in line with relaxable insn. */
3154 relaxable_operand (const struct arc_relaxable_ins *ins,
3155 const expressionS *tok,
3158 const enum rlx_operand_type *operand = &ins->operands[0];
3161 while (*operand != EMPTY)
3163 const expressionS *epr = &tok[i];
3165 if (i != 0 && i >= ntok)
3171 if (!(epr->X_op == O_multiply
3172 || epr->X_op == O_divide
3173 || epr->X_op == O_modulus
3174 || epr->X_op == O_add
3175 || epr->X_op == O_subtract
3176 || epr->X_op == O_symbol))
3182 || (epr->X_add_number != tok[i - 1].X_add_number))
3186 if (epr->X_op != O_register)
3191 if (epr->X_op != O_register)
3194 switch (epr->X_add_number)
3196 case 0: case 1: case 2: case 3:
3197 case 12: case 13: case 14: case 15:
3204 case REGISTER_NO_GP:
3205 if ((epr->X_op != O_register)
3206 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3211 if (epr->X_op != O_bracket)
3216 /* Don't understand, bail out. */
3222 operand = &ins->operands[i];
3225 return (i == ntok ? TRUE : FALSE);
3228 /* Return TRUE if this OPDCODE is a candidate for relaxation. */
3231 relax_insn_p (const struct arc_opcode *opcode,
3232 const expressionS *tok,
3234 const struct arc_flags *pflags,
3238 bfd_boolean rv = FALSE;
3240 /* Check the relaxation table. */
3241 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3243 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3245 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3246 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3247 && relaxable_operand (arc_rlx_ins, tok, ntok)
3248 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3251 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3252 memcpy (&frag_now->tc_frag_data.tok, tok,
3253 sizeof (expressionS) * ntok);
3254 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3255 sizeof (struct arc_flags) * nflg);
3256 frag_now->tc_frag_data.nflg = nflg;
3257 frag_now->tc_frag_data.ntok = ntok;
3265 /* Turn an opcode description and a set of arguments into
3266 an instruction and a fixup. */
3269 assemble_insn (const struct arc_opcode *opcode,
3270 const expressionS *tok,
3272 const struct arc_flags *pflags,
3274 struct arc_insn *insn)
3276 const expressionS *reloc_exp = NULL;
3278 const unsigned char *argidx;
3281 unsigned char pcrel = 0;
3282 bfd_boolean needGOTSymbol;
3283 bfd_boolean has_delay_slot = FALSE;
3284 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3286 memset (insn, 0, sizeof (*insn));
3287 image = opcode->opcode;
3289 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3290 frag_now->fr_file, frag_now->fr_line, opcode->name,
3293 /* Handle operands. */
3294 for (argidx = opcode->operands; *argidx; ++argidx)
3296 const struct arc_operand *operand = &arc_operands[*argidx];
3297 const expressionS *t = (const expressionS *) 0;
3299 if ((operand->flags & ARC_OPERAND_FAKE)
3300 && !(operand->flags & ARC_OPERAND_BRAKET))
3303 if (operand->flags & ARC_OPERAND_DUPLICATE)
3305 /* Duplicate operand, already inserted. */
3317 /* Regardless if we have a reloc or not mark the instruction
3318 limm if it is the case. */
3319 if (operand->flags & ARC_OPERAND_LIMM)
3320 insn->has_limm = TRUE;
3325 image = insert_operand (image, operand, regno (t->X_add_number),
3330 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3332 if (operand->flags & ARC_OPERAND_LIMM)
3333 insn->limm = t->X_add_number;
3337 /* Ignore brackets. */
3341 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3345 /* Maybe register range. */
3346 if ((t->X_add_number == 0)
3347 && contains_register (t->X_add_symbol)
3348 && contains_register (t->X_op_symbol))
3352 regs = get_register (t->X_add_symbol);
3354 regs |= get_register (t->X_op_symbol);
3355 image = insert_operand (image, operand, regs, NULL, 0);
3360 /* This operand needs a relocation. */
3361 needGOTSymbol = FALSE;
3366 needGOTSymbol = TRUE;
3367 reloc = find_reloc ("plt", opcode->name,
3369 operand->default_reloc);
3374 needGOTSymbol = TRUE;
3375 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3378 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3379 if (ARC_SHORT (opcode->mask))
3380 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3381 _("Unable to use @pcl relocation for insn %s"),
3385 reloc = find_reloc ("sda", opcode->name,
3387 operand->default_reloc);
3391 needGOTSymbol = TRUE;
3396 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3399 case O_tpoff9: /*FIXME! Check for the conditionality of
3401 case O_dtpoff9: /*FIXME! Check for the conditionality of
3403 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3407 /* Just consider the default relocation. */
3408 reloc = operand->default_reloc;
3412 if (needGOTSymbol && (GOT_symbol == NULL))
3413 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3420 /* sanity checks. */
3421 reloc_howto_type *reloc_howto
3422 = bfd_reloc_type_lookup (stdoutput,
3423 (bfd_reloc_code_real_type) reloc);
3424 unsigned reloc_bitsize = reloc_howto->bitsize;
3425 if (reloc_howto->rightshift)
3426 reloc_bitsize -= reloc_howto->rightshift;
3427 if (reloc_bitsize != operand->bits)
3429 as_bad (_("invalid relocation %s for field"),
3430 bfd_get_reloc_code_name (reloc));
3435 if (insn->nfixups >= MAX_INSN_FIXUPS)
3436 as_fatal (_("too many fixups"));
3438 struct arc_fixup *fixup;
3439 fixup = &insn->fixups[insn->nfixups++];
3441 fixup->reloc = reloc;
3442 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
3443 fixup->pcrel = pcrel;
3444 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
3451 for (i = 0; i < nflg; i++)
3453 const struct arc_flag_operand *flg_operand =
3454 &arc_flag_operands[pflags[i].code];
3456 /* Check if the instruction has a delay slot. */
3457 if (!strcmp (flg_operand->name, "d"))
3458 has_delay_slot = TRUE;
3460 /* There is an exceptional case when we cannot insert a flag
3461 just as it is. The .T flag must be handled in relation with
3462 the relative address. */
3463 if (!strcmp (flg_operand->name, "t")
3464 || !strcmp (flg_operand->name, "nt"))
3466 unsigned bitYoperand = 0;
3467 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3468 if (!strcmp (flg_operand->name, "t"))
3469 if (!strcmp (opcode->name, "bbit0")
3470 || !strcmp (opcode->name, "bbit1"))
3471 bitYoperand = arc_NToperand;
3473 bitYoperand = arc_Toperand;
3475 if (!strcmp (opcode->name, "bbit0")
3476 || !strcmp (opcode->name, "bbit1"))
3477 bitYoperand = arc_Toperand;
3479 bitYoperand = arc_NToperand;
3481 gas_assert (reloc_exp != NULL);
3482 if (reloc_exp->X_op == O_constant)
3484 /* Check if we have a constant and solved it
3486 offsetT val = reloc_exp->X_add_number;
3487 image |= insert_operand (image, &arc_operands[bitYoperand],
3492 struct arc_fixup *fixup;
3494 if (insn->nfixups >= MAX_INSN_FIXUPS)
3495 as_fatal (_("too many fixups"));
3497 fixup = &insn->fixups[insn->nfixups++];
3498 fixup->exp = *reloc_exp;
3499 fixup->reloc = -bitYoperand;
3500 fixup->pcrel = pcrel;
3501 fixup->islong = FALSE;
3505 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
3506 << flg_operand->shift;
3509 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
3511 /* Short instruction? */
3512 insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE;
3516 /* Update last insn status. */
3517 arc_last_insns[1] = arc_last_insns[0];
3518 arc_last_insns[0].opcode = opcode;
3519 arc_last_insns[0].has_limm = insn->has_limm;
3520 arc_last_insns[0].has_delay_slot = has_delay_slot;
3522 /* Check if the current instruction is legally used. */
3523 if (arc_last_insns[1].has_delay_slot
3524 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3525 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3526 _("A jump/branch instruction in delay slot."));
3530 arc_handle_align (fragS* fragP)
3532 if ((fragP)->fr_type == rs_align_code)
3534 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
3535 valueT count = ((fragP)->fr_next->fr_address
3536 - (fragP)->fr_address - (fragP)->fr_fix);
3538 (fragP)->fr_var = 2;
3540 if (count & 1)/* Padding in the gap till the next 2-byte
3541 boundary with 0s. */
3546 /* Writing nop_s. */
3547 md_number_to_chars (dest, NOP_OPCODE_S, 2);
3551 /* Here we decide which fixups can be adjusted to make them relative
3552 to the beginning of the section instead of the symbol. Basically
3553 we need to make sure that the dynamic relocations are done
3554 correctly, so in some cases we force the original symbol to be
3558 tc_arc_fix_adjustable (fixS *fixP)
3561 /* Prevent all adjustments to global symbols. */
3562 if (S_IS_EXTERNAL (fixP->fx_addsy))
3564 if (S_IS_WEAK (fixP->fx_addsy))
3567 /* Adjust_reloc_syms doesn't know about the GOT. */
3568 switch (fixP->fx_r_type)
3570 case BFD_RELOC_ARC_GOTPC32:
3571 case BFD_RELOC_ARC_PLT32:
3572 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3573 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3574 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3575 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3585 /* Compute the reloc type of an expression EXP. */
3588 arc_check_reloc (expressionS *exp,
3589 bfd_reloc_code_real_type *r_type_p)
3591 if (*r_type_p == BFD_RELOC_32
3592 && exp->X_op == O_subtract
3593 && exp->X_op_symbol != NULL
3594 && exp->X_op_symbol->bsym->section == now_seg)
3595 *r_type_p = BFD_RELOC_ARC_32_PCREL;
3599 /* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3602 arc_cons_fix_new (fragS *frag,
3606 bfd_reloc_code_real_type r_type)
3608 r_type = BFD_RELOC_UNUSED;
3613 r_type = BFD_RELOC_8;
3617 r_type = BFD_RELOC_16;
3621 r_type = BFD_RELOC_24;
3625 r_type = BFD_RELOC_32;
3626 arc_check_reloc (exp, &r_type);
3630 r_type = BFD_RELOC_64;
3634 as_bad (_("unsupported BFD relocation size %u"), size);
3635 r_type = BFD_RELOC_UNUSED;
3638 fix_new_exp (frag, off, size, exp, 0, r_type);
3641 /* The actual routine that checks the ZOL conditions. */
3644 check_zol (symbolS *s)
3646 switch (arc_mach_type)
3648 case bfd_mach_arc_arcv2:
3649 if (arc_target & ARC_OPCODE_ARCv2EM)
3652 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
3653 || arc_last_insns[1].has_delay_slot)
3654 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3658 case bfd_mach_arc_arc600:
3660 if (is_kernel_insn_p (arc_last_insns[0].opcode))
3661 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3664 if (arc_last_insns[0].has_limm
3665 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3666 as_bad (_("A jump instruction with long immediate detected at the \
3667 end of the ZOL label @%s"), S_GET_NAME (s));
3670 case bfd_mach_arc_nps400:
3671 case bfd_mach_arc_arc700:
3672 if (arc_last_insns[0].has_delay_slot)
3673 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3682 /* If ZOL end check the last two instruction for illegals. */
3684 arc_frob_label (symbolS * sym)
3686 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
3689 dwarf2_emit_label (sym);
3692 /* Used because generic relaxation assumes a pc-rel value whilst we
3693 also relax instructions that use an absolute value resolved out of
3694 relative values (if that makes any sense). An example: 'add r1,
3695 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
3696 but if they're in the same section we can subtract the section
3697 offset relocation which ends up in a resolved value. So if @.L2 is
3698 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
3699 .text + 0x40 = 0x10. */
3701 arc_pcrel_adjust (fragS *fragP)
3703 if (!fragP->tc_frag_data.pcrel)
3704 return fragP->fr_address + fragP->fr_fix;
3709 /* Initialize the DWARF-2 unwind information for this procedure. */
3712 tc_arc_frame_initial_instructions (void)
3714 /* Stack pointer is register 28. */
3715 cfi_add_CFA_def_cfa_register (28);
3719 tc_arc_regname_to_dw2regnum (char *regname)
3723 sym = hash_find (arc_reg_hash, regname);
3725 return S_GET_VALUE (sym);