1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set *mcpu_cpu_opt = NULL;
53 static const aarch64_feature_set *march_cpu_opt = NULL;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default = CPU_DEFAULT;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS *GOT_symbol;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_LP64;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
91 /* Bits for DEFINED field in vector_type_el. */
93 #define NTA_HASINDEX 2
94 #define NTA_HASVARWIDTH 4
98 enum vector_el_type type;
99 unsigned char defined;
104 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
108 bfd_reloc_code_real_type type;
111 enum aarch64_opnd opnd;
113 unsigned need_libopcodes_p : 1;
116 struct aarch64_instruction
118 /* libopcodes structure for instruction intermediate representation. */
120 /* Record assembly errors found during the parsing. */
123 enum aarch64_operand_error_kind kind;
126 /* The condition that appears in the assembly line. */
128 /* Relocation information (including the GAS internal fixup). */
130 /* Need to generate an immediate in the literal pool. */
131 unsigned gen_lit_pool : 1;
134 typedef struct aarch64_instruction aarch64_instruction;
136 static aarch64_instruction inst;
138 static bfd_boolean parse_operands (char *, const aarch64_opcode *);
139 static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
141 /* Diagnostics inline function utilites.
143 These are lightweight utlities which should only be called by parse_operands
144 and other parsers. GAS processes each assembly line by parsing it against
145 instruction template(s), in the case of multiple templates (for the same
146 mnemonic name), those templates are tried one by one until one succeeds or
147 all fail. An assembly line may fail a few templates before being
148 successfully parsed; an error saved here in most cases is not a user error
149 but an error indicating the current template is not the right template.
150 Therefore it is very important that errors can be saved at a low cost during
151 the parsing; we don't want to slow down the whole parsing by recording
152 non-user errors in detail.
154 Remember that the objective is to help GAS pick up the most approapriate
155 error message in the case of multiple templates, e.g. FMOV which has 8
161 inst.parsing_error.kind = AARCH64_OPDE_NIL;
162 inst.parsing_error.error = NULL;
165 static inline bfd_boolean
168 return inst.parsing_error.kind != AARCH64_OPDE_NIL;
171 static inline const char *
172 get_error_message (void)
174 return inst.parsing_error.error;
177 static inline enum aarch64_operand_error_kind
178 get_error_kind (void)
180 return inst.parsing_error.kind;
184 set_error (enum aarch64_operand_error_kind kind, const char *error)
186 inst.parsing_error.kind = kind;
187 inst.parsing_error.error = error;
191 set_recoverable_error (const char *error)
193 set_error (AARCH64_OPDE_RECOVERABLE, error);
196 /* Use the DESC field of the corresponding aarch64_operand entry to compose
197 the error message. */
199 set_default_error (void)
201 set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
205 set_syntax_error (const char *error)
207 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
211 set_first_syntax_error (const char *error)
214 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
218 set_fatal_syntax_error (const char *error)
220 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
223 /* Number of littlenums required to hold an extended precision number. */
224 #define MAX_LITTLENUMS 6
226 /* Return value for certain parsers when the parsing fails; those parsers
227 return the information of the parsed result, e.g. register number, on
229 #define PARSE_FAIL -1
231 /* This is an invalid condition code that means no conditional field is
233 #define COND_ALWAYS 0x10
237 const char *template;
243 const char *template;
250 bfd_reloc_code_real_type reloc;
253 /* Macros to define the register types and masks for the purpose
256 #undef AARCH64_REG_TYPES
257 #define AARCH64_REG_TYPES \
258 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
259 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
260 BASIC_REG_TYPE(SP_32) /* wsp */ \
261 BASIC_REG_TYPE(SP_64) /* sp */ \
262 BASIC_REG_TYPE(Z_32) /* wzr */ \
263 BASIC_REG_TYPE(Z_64) /* xzr */ \
264 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
265 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
266 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
267 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
268 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
269 BASIC_REG_TYPE(CN) /* c[0-7] */ \
270 BASIC_REG_TYPE(VN) /* v[0-31] */ \
271 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
272 BASIC_REG_TYPE(PN) /* p[0-15] */ \
273 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
274 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
275 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
276 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
277 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
278 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
279 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
280 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
281 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
282 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
283 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
284 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
285 /* Typecheck: any [BHSDQ]P FP. */ \
286 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
287 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
288 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
289 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
291 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
292 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
293 /* Any integer register; used for error messages only. */ \
294 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
295 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
296 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
297 /* Pseudo type to mark the end of the enumerator sequence. */ \
300 #undef BASIC_REG_TYPE
301 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
302 #undef MULTI_REG_TYPE
303 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
305 /* Register type enumerators. */
306 typedef enum aarch64_reg_type_
308 /* A list of REG_TYPE_*. */
312 #undef BASIC_REG_TYPE
313 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
315 #define REG_TYPE(T) (1 << REG_TYPE_##T)
316 #undef MULTI_REG_TYPE
317 #define MULTI_REG_TYPE(T,V) V,
319 /* Structure for a hash table entry for a register. */
323 unsigned char number;
324 ENUM_BITFIELD (aarch64_reg_type_) type : 8;
325 unsigned char builtin;
328 /* Values indexed by aarch64_reg_type to assist the type checking. */
329 static const unsigned reg_type_masks[] =
334 #undef BASIC_REG_TYPE
336 #undef MULTI_REG_TYPE
337 #undef AARCH64_REG_TYPES
339 /* Diagnostics used when we don't get a register of the expected type.
340 Note: this has to synchronized with aarch64_reg_type definitions
343 get_reg_expected_msg (aarch64_reg_type reg_type)
350 msg = N_("integer 32-bit register expected");
353 msg = N_("integer 64-bit register expected");
356 msg = N_("integer register expected");
358 case REG_TYPE_R64_SP:
359 msg = N_("64-bit integer or SP register expected");
362 msg = N_("integer or zero register expected");
365 msg = N_("integer or SP register expected");
367 case REG_TYPE_R_Z_SP:
368 msg = N_("integer, zero or SP register expected");
371 msg = N_("8-bit SIMD scalar register expected");
374 msg = N_("16-bit SIMD scalar or floating-point half precision "
375 "register expected");
378 msg = N_("32-bit SIMD scalar or floating-point single precision "
379 "register expected");
382 msg = N_("64-bit SIMD scalar or floating-point double precision "
383 "register expected");
386 msg = N_("128-bit SIMD scalar or floating-point quad precision "
387 "register expected");
390 msg = N_("C0 - C15 expected");
392 case REG_TYPE_R_Z_BHSDQ_V:
393 msg = N_("register expected");
395 case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
396 msg = N_("SIMD scalar or floating-point register expected");
398 case REG_TYPE_VN: /* any V reg */
399 msg = N_("vector register expected");
402 msg = N_("SVE vector register expected");
405 msg = N_("SVE predicate register expected");
408 as_fatal (_("invalid register type %d"), reg_type);
413 /* Some well known registers that we refer to directly elsewhere. */
416 /* Instructions take 4 bytes in the object file. */
419 static struct hash_control *aarch64_ops_hsh;
420 static struct hash_control *aarch64_cond_hsh;
421 static struct hash_control *aarch64_shift_hsh;
422 static struct hash_control *aarch64_sys_regs_hsh;
423 static struct hash_control *aarch64_pstatefield_hsh;
424 static struct hash_control *aarch64_sys_regs_ic_hsh;
425 static struct hash_control *aarch64_sys_regs_dc_hsh;
426 static struct hash_control *aarch64_sys_regs_at_hsh;
427 static struct hash_control *aarch64_sys_regs_tlbi_hsh;
428 static struct hash_control *aarch64_reg_hsh;
429 static struct hash_control *aarch64_barrier_opt_hsh;
430 static struct hash_control *aarch64_nzcv_hsh;
431 static struct hash_control *aarch64_pldop_hsh;
432 static struct hash_control *aarch64_hint_opt_hsh;
434 /* Stuff needed to resolve the label ambiguity
443 static symbolS *last_label_seen;
445 /* Literal pool structure. Held on a per-section
446 and per-sub-section basis. */
448 #define MAX_LITERAL_POOL_SIZE 1024
449 typedef struct literal_expression
452 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
453 LITTLENUM_TYPE * bignum;
454 } literal_expression;
456 typedef struct literal_pool
458 literal_expression literals[MAX_LITERAL_POOL_SIZE];
459 unsigned int next_free_entry;
465 struct literal_pool *next;
468 /* Pointer to a linked list of literal pools. */
469 static literal_pool *list_of_pools = NULL;
473 /* This array holds the chars that always start a comment. If the
474 pre-processor is disabled, these aren't very useful. */
475 const char comment_chars[] = "";
477 /* This array holds the chars that only start a comment at the beginning of
478 a line. If the line seems to have the form '# 123 filename'
479 .line and .file directives will appear in the pre-processed output. */
480 /* Note that input_file.c hand checks for '#' at the beginning of the
481 first line of the input file. This is because the compiler outputs
482 #NO_APP at the beginning of its output. */
483 /* Also note that comments like this one will always work. */
484 const char line_comment_chars[] = "#";
486 const char line_separator_chars[] = ";";
488 /* Chars that can be used to separate mant
489 from exp in floating point numbers. */
490 const char EXP_CHARS[] = "eE";
492 /* Chars that mean this number is a floating point constant. */
496 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
498 /* Prefix character that indicates the start of an immediate value. */
499 #define is_immediate_prefix(C) ((C) == '#')
501 /* Separator character handling. */
503 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
505 static inline bfd_boolean
506 skip_past_char (char **str, char c)
517 #define skip_past_comma(str) skip_past_char (str, ',')
519 /* Arithmetic expressions (possibly involving symbols). */
521 static bfd_boolean in_my_get_expression_p = FALSE;
523 /* Third argument to my_get_expression. */
524 #define GE_NO_PREFIX 0
525 #define GE_OPT_PREFIX 1
527 /* Return TRUE if the string pointed by *STR is successfully parsed
528 as an valid expression; *EP will be filled with the information of
529 such an expression. Otherwise return FALSE. */
532 my_get_expression (expressionS * ep, char **str, int prefix_mode,
537 int prefix_present_p = 0;
544 if (is_immediate_prefix (**str))
547 prefix_present_p = 1;
554 memset (ep, 0, sizeof (expressionS));
556 save_in = input_line_pointer;
557 input_line_pointer = *str;
558 in_my_get_expression_p = TRUE;
559 seg = expression (ep);
560 in_my_get_expression_p = FALSE;
562 if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
564 /* We found a bad expression in md_operand(). */
565 *str = input_line_pointer;
566 input_line_pointer = save_in;
567 if (prefix_present_p && ! error_p ())
568 set_fatal_syntax_error (_("bad expression"));
570 set_first_syntax_error (_("bad expression"));
575 if (seg != absolute_section
576 && seg != text_section
577 && seg != data_section
578 && seg != bss_section && seg != undefined_section)
580 set_syntax_error (_("bad segment"));
581 *str = input_line_pointer;
582 input_line_pointer = save_in;
589 *str = input_line_pointer;
590 input_line_pointer = save_in;
594 /* Turn a string in input_line_pointer into a floating point constant
595 of type TYPE, and store the appropriate bytes in *LITP. The number
596 of LITTLENUMS emitted is stored in *SIZEP. An error message is
597 returned, or NULL on OK. */
600 md_atof (int type, char *litP, int *sizeP)
602 return ieee_md_atof (type, litP, sizeP, target_big_endian);
605 /* We handle all bad expressions here, so that we can report the faulty
606 instruction in the error message. */
608 md_operand (expressionS * exp)
610 if (in_my_get_expression_p)
611 exp->X_op = O_illegal;
614 /* Immediate values. */
616 /* Errors may be set multiple times during parsing or bit encoding
617 (particularly in the Neon bits), but usually the earliest error which is set
618 will be the most meaningful. Avoid overwriting it with later (cascading)
619 errors by calling this function. */
622 first_error (const char *error)
625 set_syntax_error (error);
628 /* Similiar to first_error, but this function accepts formatted error
631 first_error_fmt (const char *format, ...)
636 /* N.B. this single buffer will not cause error messages for different
637 instructions to pollute each other; this is because at the end of
638 processing of each assembly line, error message if any will be
639 collected by as_bad. */
640 static char buffer[size];
644 int ret ATTRIBUTE_UNUSED;
645 va_start (args, format);
646 ret = vsnprintf (buffer, size, format, args);
647 know (ret <= size - 1 && ret >= 0);
649 set_syntax_error (buffer);
653 /* Register parsing. */
655 /* Generic register parser which is called by other specialized
657 CCP points to what should be the beginning of a register name.
658 If it is indeed a valid register name, advance CCP over it and
659 return the reg_entry structure; otherwise return NULL.
660 It does not issue diagnostics. */
663 parse_reg (char **ccp)
669 #ifdef REGISTER_PREFIX
670 if (*start != REGISTER_PREFIX)
676 if (!ISALPHA (*p) || !is_name_beginner (*p))
681 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
683 reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start);
692 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
695 aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
697 return (reg_type_masks[type] & (1 << reg->type)) != 0;
700 /* Try to parse a base or offset register. Return the register entry
701 on success, setting *QUALIFIER to the register qualifier. Return null
704 Note that this function does not issue any diagnostics. */
706 static const reg_entry *
707 aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
710 const reg_entry *reg = parse_reg (&str);
720 *qualifier = AARCH64_OPND_QLF_W;
726 *qualifier = AARCH64_OPND_QLF_X;
738 /* Parse the qualifier of a vector register or vector element of type
739 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
740 succeeds; otherwise return FALSE.
742 Accept only one occurrence of:
743 8b 16b 2h 4h 8h 2s 4s 1d 2d
746 parse_vector_type_for_operand (aarch64_reg_type reg_type,
747 struct vector_type_el *parsed_type, char **str)
751 unsigned element_size;
752 enum vector_el_type type;
755 gas_assert (*ptr == '.');
758 if (reg_type == REG_TYPE_ZN || reg_type == REG_TYPE_PN || !ISDIGIT (*ptr))
763 width = strtoul (ptr, &ptr, 10);
764 if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
766 first_error_fmt (_("bad size %d in vector width specifier"), width);
771 switch (TOLOWER (*ptr))
799 first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
801 first_error (_("missing element size"));
804 if (width != 0 && width * element_size != 64 && width * element_size != 128
805 && !(width == 2 && element_size == 16))
808 ("invalid element size %d and vector size combination %c"),
814 parsed_type->type = type;
815 parsed_type->width = width;
822 /* *STR contains an SVE zero/merge predication suffix. Parse it into
823 *PARSED_TYPE and point *STR at the end of the suffix. */
826 parse_predication_for_operand (struct vector_type_el *parsed_type, char **str)
831 gas_assert (*ptr == '/');
833 switch (TOLOWER (*ptr))
836 parsed_type->type = NT_zero;
839 parsed_type->type = NT_merge;
842 if (*ptr != '\0' && *ptr != ',')
843 first_error_fmt (_("unexpected character `%c' in predication type"),
846 first_error (_("missing predication type"));
849 parsed_type->width = 0;
854 /* Parse a register of the type TYPE.
856 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
857 name or the parsed register is not of TYPE.
859 Otherwise return the register number, and optionally fill in the actual
860 type of the register in *RTYPE when multiple alternatives were given, and
861 return the register shape and element index information in *TYPEINFO.
863 IN_REG_LIST should be set with TRUE if the caller is parsing a register
867 parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
868 struct vector_type_el *typeinfo, bfd_boolean in_reg_list)
871 const reg_entry *reg = parse_reg (&str);
872 struct vector_type_el atype;
873 struct vector_type_el parsetype;
874 bfd_boolean is_typed_vecreg = FALSE;
877 atype.type = NT_invtype;
885 set_default_error ();
889 if (! aarch64_check_reg_type (reg, type))
891 DEBUG_TRACE ("reg type check failed");
892 set_default_error ();
897 if ((type == REG_TYPE_VN || type == REG_TYPE_ZN || type == REG_TYPE_PN)
898 && (*str == '.' || (type == REG_TYPE_PN && *str == '/')))
902 if (!parse_vector_type_for_operand (type, &parsetype, &str))
907 if (!parse_predication_for_operand (&parsetype, &str))
911 /* Register if of the form Vn.[bhsdq]. */
912 is_typed_vecreg = TRUE;
914 if (type == REG_TYPE_ZN || type == REG_TYPE_PN)
916 /* The width is always variable; we don't allow an integer width
918 gas_assert (parsetype.width == 0);
919 atype.defined |= NTA_HASVARWIDTH | NTA_HASTYPE;
921 else if (parsetype.width == 0)
922 /* Expect index. In the new scheme we cannot have
923 Vn.[bhsdq] represent a scalar. Therefore any
924 Vn.[bhsdq] should have an index following it.
925 Except in reglists ofcourse. */
926 atype.defined |= NTA_HASINDEX;
928 atype.defined |= NTA_HASTYPE;
930 atype.type = parsetype.type;
931 atype.width = parsetype.width;
934 if (skip_past_char (&str, '['))
938 /* Reject Sn[index] syntax. */
939 if (!is_typed_vecreg)
941 first_error (_("this type of register can't be indexed"));
945 if (in_reg_list == TRUE)
947 first_error (_("index not allowed inside register list"));
951 atype.defined |= NTA_HASINDEX;
953 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
955 if (exp.X_op != O_constant)
957 first_error (_("constant expression required"));
961 if (! skip_past_char (&str, ']'))
964 atype.index = exp.X_add_number;
966 else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
968 /* Indexed vector register expected. */
969 first_error (_("indexed vector register expected"));
973 /* A vector reg Vn should be typed or indexed. */
974 if (type == REG_TYPE_VN && atype.defined == 0)
976 first_error (_("invalid use of vector register"));
992 Return the register number on success; return PARSE_FAIL otherwise.
994 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
995 the register (e.g. NEON double or quad reg when either has been requested).
997 If this is a NEON vector register with additional type information, fill
998 in the struct pointed to by VECTYPE (if non-NULL).
1000 This parser does not handle register list. */
1003 aarch64_reg_parse (char **ccp, aarch64_reg_type type,
1004 aarch64_reg_type *rtype, struct vector_type_el *vectype)
1006 struct vector_type_el atype;
1008 int reg = parse_typed_reg (&str, type, rtype, &atype,
1009 /*in_reg_list= */ FALSE);
1011 if (reg == PARSE_FAIL)
1022 static inline bfd_boolean
1023 eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2)
1027 && e1.defined == e2.defined
1028 && e1.width == e2.width && e1.index == e2.index;
1031 /* This function parses a list of vector registers of type TYPE.
1032 On success, it returns the parsed register list information in the
1033 following encoded format:
1035 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1036 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1038 The information of the register shape and/or index is returned in
1041 It returns PARSE_FAIL if the register list is invalid.
1043 The list contains one to four registers.
1044 Each register can be one of:
1047 All <T> should be identical.
1048 All <index> should be identical.
1049 There are restrictions on <Vt> numbers which are checked later
1050 (by reg_list_valid_p). */
1053 parse_vector_reg_list (char **ccp, aarch64_reg_type type,
1054 struct vector_type_el *vectype)
1058 struct vector_type_el typeinfo, typeinfo_first;
1063 bfd_boolean error = FALSE;
1064 bfd_boolean expect_index = FALSE;
1068 set_syntax_error (_("expecting {"));
1074 typeinfo_first.defined = 0;
1075 typeinfo_first.type = NT_invtype;
1076 typeinfo_first.width = -1;
1077 typeinfo_first.index = 0;
1086 str++; /* skip over '-' */
1089 val = parse_typed_reg (&str, type, NULL, &typeinfo,
1090 /*in_reg_list= */ TRUE);
1091 if (val == PARSE_FAIL)
1093 set_first_syntax_error (_("invalid vector register in list"));
1097 /* reject [bhsd]n */
1098 if (type == REG_TYPE_VN && typeinfo.defined == 0)
1100 set_first_syntax_error (_("invalid scalar register in list"));
1105 if (typeinfo.defined & NTA_HASINDEX)
1106 expect_index = TRUE;
1110 if (val < val_range)
1112 set_first_syntax_error
1113 (_("invalid range in vector register list"));
1122 typeinfo_first = typeinfo;
1123 else if (! eq_vector_type_el (typeinfo_first, typeinfo))
1125 set_first_syntax_error
1126 (_("type mismatch in vector register list"));
1131 for (i = val_range; i <= val; i++)
1133 ret_val |= i << (5 * nb_regs);
1138 while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
1140 skip_whitespace (str);
1143 set_first_syntax_error (_("end of vector register list not found"));
1148 skip_whitespace (str);
1152 if (skip_past_char (&str, '['))
1156 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1157 if (exp.X_op != O_constant)
1159 set_first_syntax_error (_("constant expression required."));
1162 if (! skip_past_char (&str, ']'))
1165 typeinfo_first.index = exp.X_add_number;
1169 set_first_syntax_error (_("expected index"));
1176 set_first_syntax_error (_("too many registers in vector register list"));
1179 else if (nb_regs == 0)
1181 set_first_syntax_error (_("empty vector register list"));
1187 *vectype = typeinfo_first;
1189 return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1);
1192 /* Directives: register aliases. */
1195 insert_reg_alias (char *str, int number, aarch64_reg_type type)
1200 if ((new = hash_find (aarch64_reg_hsh, str)) != 0)
1203 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1206 /* Only warn about a redefinition if it's not defined as the
1208 else if (new->number != number || new->type != type)
1209 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1214 name = xstrdup (str);
1215 new = XNEW (reg_entry);
1218 new->number = number;
1220 new->builtin = FALSE;
1222 if (hash_insert (aarch64_reg_hsh, name, (void *) new))
1228 /* Look for the .req directive. This is of the form:
1230 new_register_name .req existing_register_name
1232 If we find one, or if it looks sufficiently like one that we want to
1233 handle any error here, return TRUE. Otherwise return FALSE. */
1236 create_register_alias (char *newname, char *p)
1238 const reg_entry *old;
1239 char *oldname, *nbuf;
1242 /* The input scrubber ensures that whitespace after the mnemonic is
1243 collapsed to single spaces. */
1245 if (strncmp (oldname, " .req ", 6) != 0)
1249 if (*oldname == '\0')
1252 old = hash_find (aarch64_reg_hsh, oldname);
1255 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1259 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1260 the desired alias name, and p points to its end. If not, then
1261 the desired alias name is in the global original_case_string. */
1262 #ifdef TC_CASE_SENSITIVE
1265 newname = original_case_string;
1266 nlen = strlen (newname);
1269 nbuf = xmemdup0 (newname, nlen);
1271 /* Create aliases under the new name as stated; an all-lowercase
1272 version of the new name; and an all-uppercase version of the new
1274 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
1276 for (p = nbuf; *p; p++)
1279 if (strncmp (nbuf, newname, nlen))
1281 /* If this attempt to create an additional alias fails, do not bother
1282 trying to create the all-lower case alias. We will fail and issue
1283 a second, duplicate error message. This situation arises when the
1284 programmer does something like:
1287 The second .req creates the "Foo" alias but then fails to create
1288 the artificial FOO alias because it has already been created by the
1290 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
1297 for (p = nbuf; *p; p++)
1300 if (strncmp (nbuf, newname, nlen))
1301 insert_reg_alias (nbuf, old->number, old->type);
1308 /* Should never be called, as .req goes between the alias and the
1309 register name, not at the beginning of the line. */
1311 s_req (int a ATTRIBUTE_UNUSED)
1313 as_bad (_("invalid syntax for .req directive"));
1316 /* The .unreq directive deletes an alias which was previously defined
1317 by .req. For example:
1323 s_unreq (int a ATTRIBUTE_UNUSED)
1328 name = input_line_pointer;
1330 while (*input_line_pointer != 0
1331 && *input_line_pointer != ' ' && *input_line_pointer != '\n')
1332 ++input_line_pointer;
1334 saved_char = *input_line_pointer;
1335 *input_line_pointer = 0;
1338 as_bad (_("invalid syntax for .unreq directive"));
1341 reg_entry *reg = hash_find (aarch64_reg_hsh, name);
1344 as_bad (_("unknown register alias '%s'"), name);
1345 else if (reg->builtin)
1346 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1353 hash_delete (aarch64_reg_hsh, name, FALSE);
1354 free ((char *) reg->name);
1357 /* Also locate the all upper case and all lower case versions.
1358 Do not complain if we cannot find one or the other as it
1359 was probably deleted above. */
1361 nbuf = strdup (name);
1362 for (p = nbuf; *p; p++)
1364 reg = hash_find (aarch64_reg_hsh, nbuf);
1367 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1368 free ((char *) reg->name);
1372 for (p = nbuf; *p; p++)
1374 reg = hash_find (aarch64_reg_hsh, nbuf);
1377 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1378 free ((char *) reg->name);
1386 *input_line_pointer = saved_char;
1387 demand_empty_rest_of_line ();
1390 /* Directives: Instruction set selection. */
1393 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1394 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1395 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1396 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1398 /* Create a new mapping symbol for the transition to STATE. */
1401 make_mapping_symbol (enum mstate state, valueT value, fragS * frag)
1404 const char *symname;
1411 type = BSF_NO_FLAGS;
1415 type = BSF_NO_FLAGS;
1421 symbolP = symbol_new (symname, now_seg, value, frag);
1422 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1424 /* Save the mapping symbols for future reference. Also check that
1425 we do not place two mapping symbols at the same offset within a
1426 frag. We'll handle overlap between frags in
1427 check_mapping_symbols.
1429 If .fill or other data filling directive generates zero sized data,
1430 the mapping symbol for the following code will have the same value
1431 as the one generated for the data filling directive. In this case,
1432 we replace the old symbol with the new one at the same address. */
1435 if (frag->tc_frag_data.first_map != NULL)
1437 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
1438 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP,
1441 frag->tc_frag_data.first_map = symbolP;
1443 if (frag->tc_frag_data.last_map != NULL)
1445 know (S_GET_VALUE (frag->tc_frag_data.last_map) <=
1446 S_GET_VALUE (symbolP));
1447 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
1448 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP,
1451 frag->tc_frag_data.last_map = symbolP;
1454 /* We must sometimes convert a region marked as code to data during
1455 code alignment, if an odd number of bytes have to be padded. The
1456 code mapping symbol is pushed to an aligned address. */
1459 insert_data_mapping_symbol (enum mstate state,
1460 valueT value, fragS * frag, offsetT bytes)
1462 /* If there was already a mapping symbol, remove it. */
1463 if (frag->tc_frag_data.last_map != NULL
1464 && S_GET_VALUE (frag->tc_frag_data.last_map) ==
1465 frag->fr_address + value)
1467 symbolS *symp = frag->tc_frag_data.last_map;
1471 know (frag->tc_frag_data.first_map == symp);
1472 frag->tc_frag_data.first_map = NULL;
1474 frag->tc_frag_data.last_map = NULL;
1475 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
1478 make_mapping_symbol (MAP_DATA, value, frag);
1479 make_mapping_symbol (state, value + bytes, frag);
1482 static void mapping_state_2 (enum mstate state, int max_chars);
1484 /* Set the mapping state to STATE. Only call this when about to
1485 emit some STATE bytes to the file. */
1488 mapping_state (enum mstate state)
1490 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1492 if (state == MAP_INSN)
1493 /* AArch64 instructions require 4-byte alignment. When emitting
1494 instructions into any section, record the appropriate section
1496 record_alignment (now_seg, 2);
1498 if (mapstate == state)
1499 /* The mapping symbol has already been emitted.
1500 There is nothing else to do. */
1503 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1504 if (TRANSITION (MAP_UNDEFINED, MAP_DATA) && !subseg_text_p (now_seg))
1505 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1506 evaluated later in the next else. */
1508 else if (TRANSITION (MAP_UNDEFINED, MAP_INSN))
1510 /* Only add the symbol if the offset is > 0:
1511 if we're at the first frag, check it's size > 0;
1512 if we're not at the first frag, then for sure
1513 the offset is > 0. */
1514 struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root;
1515 const int add_symbol = (frag_now != frag_first)
1516 || (frag_now_fix () > 0);
1519 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
1523 mapping_state_2 (state, 0);
1526 /* Same as mapping_state, but MAX_CHARS bytes have already been
1527 allocated. Put the mapping symbol that far back. */
1530 mapping_state_2 (enum mstate state, int max_chars)
1532 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1534 if (!SEG_NORMAL (now_seg))
1537 if (mapstate == state)
1538 /* The mapping symbol has already been emitted.
1539 There is nothing else to do. */
1542 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1543 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
1546 #define mapping_state(x) /* nothing */
1547 #define mapping_state_2(x, y) /* nothing */
1550 /* Directives: sectioning and alignment. */
1553 s_bss (int ignore ATTRIBUTE_UNUSED)
1555 /* We don't support putting frags in the BSS segment, we fake it by
1556 marking in_bss, then looking at s_skip for clues. */
1557 subseg_set (bss_section, 0);
1558 demand_empty_rest_of_line ();
1559 mapping_state (MAP_DATA);
1563 s_even (int ignore ATTRIBUTE_UNUSED)
1565 /* Never make frag if expect extra pass. */
1567 frag_align (1, 0, 0);
1569 record_alignment (now_seg, 1);
1571 demand_empty_rest_of_line ();
1574 /* Directives: Literal pools. */
1576 static literal_pool *
1577 find_literal_pool (int size)
1581 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1583 if (pool->section == now_seg
1584 && pool->sub_section == now_subseg && pool->size == size)
1591 static literal_pool *
1592 find_or_make_literal_pool (int size)
1594 /* Next literal pool ID number. */
1595 static unsigned int latest_pool_num = 1;
1598 pool = find_literal_pool (size);
1602 /* Create a new pool. */
1603 pool = XNEW (literal_pool);
1607 /* Currently we always put the literal pool in the current text
1608 section. If we were generating "small" model code where we
1609 knew that all code and initialised data was within 1MB then
1610 we could output literals to mergeable, read-only data
1613 pool->next_free_entry = 0;
1614 pool->section = now_seg;
1615 pool->sub_section = now_subseg;
1617 pool->next = list_of_pools;
1618 pool->symbol = NULL;
1620 /* Add it to the list. */
1621 list_of_pools = pool;
1624 /* New pools, and emptied pools, will have a NULL symbol. */
1625 if (pool->symbol == NULL)
1627 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1628 (valueT) 0, &zero_address_frag);
1629 pool->id = latest_pool_num++;
1636 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1637 Return TRUE on success, otherwise return FALSE. */
1639 add_to_lit_pool (expressionS *exp, int size)
1644 pool = find_or_make_literal_pool (size);
1646 /* Check if this literal value is already in the pool. */
1647 for (entry = 0; entry < pool->next_free_entry; entry++)
1649 expressionS * litexp = & pool->literals[entry].exp;
1651 if ((litexp->X_op == exp->X_op)
1652 && (exp->X_op == O_constant)
1653 && (litexp->X_add_number == exp->X_add_number)
1654 && (litexp->X_unsigned == exp->X_unsigned))
1657 if ((litexp->X_op == exp->X_op)
1658 && (exp->X_op == O_symbol)
1659 && (litexp->X_add_number == exp->X_add_number)
1660 && (litexp->X_add_symbol == exp->X_add_symbol)
1661 && (litexp->X_op_symbol == exp->X_op_symbol))
1665 /* Do we need to create a new entry? */
1666 if (entry == pool->next_free_entry)
1668 if (entry >= MAX_LITERAL_POOL_SIZE)
1670 set_syntax_error (_("literal pool overflow"));
1674 pool->literals[entry].exp = *exp;
1675 pool->next_free_entry += 1;
1676 if (exp->X_op == O_big)
1678 /* PR 16688: Bignums are held in a single global array. We must
1679 copy and preserve that value now, before it is overwritten. */
1680 pool->literals[entry].bignum = XNEWVEC (LITTLENUM_TYPE,
1682 memcpy (pool->literals[entry].bignum, generic_bignum,
1683 CHARS_PER_LITTLENUM * exp->X_add_number);
1686 pool->literals[entry].bignum = NULL;
1689 exp->X_op = O_symbol;
1690 exp->X_add_number = ((int) entry) * size;
1691 exp->X_add_symbol = pool->symbol;
1696 /* Can't use symbol_new here, so have to create a symbol and then at
1697 a later date assign it a value. Thats what these functions do. */
1700 symbol_locate (symbolS * symbolP,
1701 const char *name,/* It is copied, the caller can modify. */
1702 segT segment, /* Segment identifier (SEG_<something>). */
1703 valueT valu, /* Symbol value. */
1704 fragS * frag) /* Associated fragment. */
1707 char *preserved_copy_of_name;
1709 name_length = strlen (name) + 1; /* +1 for \0. */
1710 obstack_grow (¬es, name, name_length);
1711 preserved_copy_of_name = obstack_finish (¬es);
1713 #ifdef tc_canonicalize_symbol_name
1714 preserved_copy_of_name =
1715 tc_canonicalize_symbol_name (preserved_copy_of_name);
1718 S_SET_NAME (symbolP, preserved_copy_of_name);
1720 S_SET_SEGMENT (symbolP, segment);
1721 S_SET_VALUE (symbolP, valu);
1722 symbol_clear_list_pointers (symbolP);
1724 symbol_set_frag (symbolP, frag);
1726 /* Link to end of symbol chain. */
1728 extern int symbol_table_frozen;
1730 if (symbol_table_frozen)
1734 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1736 obj_symbol_new_hook (symbolP);
1738 #ifdef tc_symbol_new_hook
1739 tc_symbol_new_hook (symbolP);
1743 verify_symbol_chain (symbol_rootP, symbol_lastP);
1744 #endif /* DEBUG_SYMS */
1749 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1756 for (align = 2; align <= 4; align++)
1758 int size = 1 << align;
1760 pool = find_literal_pool (size);
1761 if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
1764 /* Align pool as you have word accesses.
1765 Only make a frag if we have to. */
1767 frag_align (align, 0, 0);
1769 mapping_state (MAP_DATA);
1771 record_alignment (now_seg, align);
1773 sprintf (sym_name, "$$lit_\002%x", pool->id);
1775 symbol_locate (pool->symbol, sym_name, now_seg,
1776 (valueT) frag_now_fix (), frag_now);
1777 symbol_table_insert (pool->symbol);
1779 for (entry = 0; entry < pool->next_free_entry; entry++)
1781 expressionS * exp = & pool->literals[entry].exp;
1783 if (exp->X_op == O_big)
1785 /* PR 16688: Restore the global bignum value. */
1786 gas_assert (pool->literals[entry].bignum != NULL);
1787 memcpy (generic_bignum, pool->literals[entry].bignum,
1788 CHARS_PER_LITTLENUM * exp->X_add_number);
1791 /* First output the expression in the instruction to the pool. */
1792 emit_expr (exp, size); /* .word|.xword */
1794 if (exp->X_op == O_big)
1796 free (pool->literals[entry].bignum);
1797 pool->literals[entry].bignum = NULL;
1801 /* Mark the pool as empty. */
1802 pool->next_free_entry = 0;
1803 pool->symbol = NULL;
1808 /* Forward declarations for functions below, in the MD interface
1810 static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int);
1811 static struct reloc_table_entry * find_reloc_table_entry (char **);
1813 /* Directives: Data. */
1814 /* N.B. the support for relocation suffix in this directive needs to be
1815 implemented properly. */
1818 s_aarch64_elf_cons (int nbytes)
1822 #ifdef md_flush_pending_output
1823 md_flush_pending_output ();
1826 if (is_it_end_of_statement ())
1828 demand_empty_rest_of_line ();
1832 #ifdef md_cons_align
1833 md_cons_align (nbytes);
1836 mapping_state (MAP_DATA);
1839 struct reloc_table_entry *reloc;
1843 if (exp.X_op != O_symbol)
1844 emit_expr (&exp, (unsigned int) nbytes);
1847 skip_past_char (&input_line_pointer, '#');
1848 if (skip_past_char (&input_line_pointer, ':'))
1850 reloc = find_reloc_table_entry (&input_line_pointer);
1852 as_bad (_("unrecognized relocation suffix"));
1854 as_bad (_("unimplemented relocation suffix"));
1855 ignore_rest_of_line ();
1859 emit_expr (&exp, (unsigned int) nbytes);
1862 while (*input_line_pointer++ == ',');
1864 /* Put terminator back into stream. */
1865 input_line_pointer--;
1866 demand_empty_rest_of_line ();
1869 #endif /* OBJ_ELF */
1871 /* Output a 32-bit word, but mark as an instruction. */
1874 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
1878 #ifdef md_flush_pending_output
1879 md_flush_pending_output ();
1882 if (is_it_end_of_statement ())
1884 demand_empty_rest_of_line ();
1888 /* Sections are assumed to start aligned. In executable section, there is no
1889 MAP_DATA symbol pending. So we only align the address during
1890 MAP_DATA --> MAP_INSN transition.
1891 For other sections, this is not guaranteed. */
1892 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1893 if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA)
1894 frag_align_code (2, 0);
1897 mapping_state (MAP_INSN);
1903 if (exp.X_op != O_constant)
1905 as_bad (_("constant expression required"));
1906 ignore_rest_of_line ();
1910 if (target_big_endian)
1912 unsigned int val = exp.X_add_number;
1913 exp.X_add_number = SWAP_32 (val);
1915 emit_expr (&exp, 4);
1917 while (*input_line_pointer++ == ',');
1919 /* Put terminator back into stream. */
1920 input_line_pointer--;
1921 demand_empty_rest_of_line ();
1925 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1928 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED)
1934 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1935 BFD_RELOC_AARCH64_TLSDESC_ADD);
1937 demand_empty_rest_of_line ();
1940 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1943 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
1947 /* Since we're just labelling the code, there's no need to define a
1950 /* Make sure there is enough room in this frag for the following
1951 blr. This trick only works if the blr follows immediately after
1952 the .tlsdesc directive. */
1954 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1955 BFD_RELOC_AARCH64_TLSDESC_CALL);
1957 demand_empty_rest_of_line ();
1960 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1963 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED)
1969 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1970 BFD_RELOC_AARCH64_TLSDESC_LDR);
1972 demand_empty_rest_of_line ();
1974 #endif /* OBJ_ELF */
1976 static void s_aarch64_arch (int);
1977 static void s_aarch64_cpu (int);
1978 static void s_aarch64_arch_extension (int);
1980 /* This table describes all the machine specific pseudo-ops the assembler
1981 has to support. The fields are:
1982 pseudo-op name without dot
1983 function to call to execute this pseudo-op
1984 Integer arg to pass to the function. */
1986 const pseudo_typeS md_pseudo_table[] = {
1987 /* Never called because '.req' does not start a line. */
1989 {"unreq", s_unreq, 0},
1991 {"even", s_even, 0},
1992 {"ltorg", s_ltorg, 0},
1993 {"pool", s_ltorg, 0},
1994 {"cpu", s_aarch64_cpu, 0},
1995 {"arch", s_aarch64_arch, 0},
1996 {"arch_extension", s_aarch64_arch_extension, 0},
1997 {"inst", s_aarch64_inst, 0},
1999 {"tlsdescadd", s_tlsdescadd, 0},
2000 {"tlsdesccall", s_tlsdesccall, 0},
2001 {"tlsdescldr", s_tlsdescldr, 0},
2002 {"word", s_aarch64_elf_cons, 4},
2003 {"long", s_aarch64_elf_cons, 4},
2004 {"xword", s_aarch64_elf_cons, 8},
2005 {"dword", s_aarch64_elf_cons, 8},
2011 /* Check whether STR points to a register name followed by a comma or the
2012 end of line; REG_TYPE indicates which register types are checked
2013 against. Return TRUE if STR is such a register name; otherwise return
2014 FALSE. The function does not intend to produce any diagnostics, but since
2015 the register parser aarch64_reg_parse, which is called by this function,
2016 does produce diagnostics, we call clear_error to clear any diagnostics
2017 that may be generated by aarch64_reg_parse.
2018 Also, the function returns FALSE directly if there is any user error
2019 present at the function entry. This prevents the existing diagnostics
2020 state from being spoiled.
2021 The function currently serves parse_constant_immediate and
2022 parse_big_immediate only. */
2024 reg_name_p (char *str, aarch64_reg_type reg_type)
2028 /* Prevent the diagnostics state from being spoiled. */
2032 reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
2034 /* Clear the parsing error that may be set by the reg parser. */
2037 if (reg == PARSE_FAIL)
2040 skip_whitespace (str);
2041 if (*str == ',' || is_end_of_line[(unsigned int) *str])
2047 /* Parser functions used exclusively in instruction operands. */
2049 /* Parse an immediate expression which may not be constant.
2051 To prevent the expression parser from pushing a register name
2052 into the symbol table as an undefined symbol, firstly a check is
2053 done to find out whether STR is a register of type REG_TYPE followed
2054 by a comma or the end of line. Return FALSE if STR is such a string. */
2057 parse_immediate_expression (char **str, expressionS *exp,
2058 aarch64_reg_type reg_type)
2060 if (reg_name_p (*str, reg_type))
2062 set_recoverable_error (_("immediate operand required"));
2066 my_get_expression (exp, str, GE_OPT_PREFIX, 1);
2068 if (exp->X_op == O_absent)
2070 set_fatal_syntax_error (_("missing immediate expression"));
2077 /* Constant immediate-value read function for use in insn parsing.
2078 STR points to the beginning of the immediate (with the optional
2079 leading #); *VAL receives the value. REG_TYPE says which register
2080 names should be treated as registers rather than as symbolic immediates.
2082 Return TRUE on success; otherwise return FALSE. */
2085 parse_constant_immediate (char **str, int64_t *val, aarch64_reg_type reg_type)
2089 if (! parse_immediate_expression (str, &exp, reg_type))
2092 if (exp.X_op != O_constant)
2094 set_syntax_error (_("constant expression required"));
2098 *val = exp.X_add_number;
2103 encode_imm_float_bits (uint32_t imm)
2105 return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2106 | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2109 /* Return TRUE if the single-precision floating-point value encoded in IMM
2110 can be expressed in the AArch64 8-bit signed floating-point format with
2111 3-bit exponent and normalized 4 bits of precision; in other words, the
2112 floating-point value must be expressable as
2113 (+/-) n / 16 * power (2, r)
2114 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2117 aarch64_imm_float_p (uint32_t imm)
2119 /* If a single-precision floating-point value has the following bit
2120 pattern, it can be expressed in the AArch64 8-bit floating-point
2123 3 32222222 2221111111111
2124 1 09876543 21098765432109876543210
2125 n Eeeeeexx xxxx0000000000000000000
2127 where n, e and each x are either 0 or 1 independently, with
2132 /* Prepare the pattern for 'Eeeeee'. */
2133 if (((imm >> 30) & 0x1) == 0)
2134 pattern = 0x3e000000;
2136 pattern = 0x40000000;
2138 return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */
2139 && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */
2142 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2143 as an IEEE float without any loss of precision. Store the value in
2147 can_convert_double_to_float (uint64_t imm, uint32_t *fpword)
2149 /* If a double-precision floating-point value has the following bit
2150 pattern, it can be expressed in a float:
2152 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2153 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2154 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2156 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2157 if Eeee_eeee != 1111_1111
2159 where n, e, s and S are either 0 or 1 independently and where ~ is the
2163 uint32_t high32 = imm >> 32;
2164 uint32_t low32 = imm;
2166 /* Lower 29 bits need to be 0s. */
2167 if ((imm & 0x1fffffff) != 0)
2170 /* Prepare the pattern for 'Eeeeeeeee'. */
2171 if (((high32 >> 30) & 0x1) == 0)
2172 pattern = 0x38000000;
2174 pattern = 0x40000000;
2177 if ((high32 & 0x78000000) != pattern)
2180 /* Check Eeee_eeee != 1111_1111. */
2181 if ((high32 & 0x7ff00000) == 0x47f00000)
2184 *fpword = ((high32 & 0xc0000000) /* 1 n bit and 1 E bit. */
2185 | ((high32 << 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2186 | (low32 >> 29)); /* 3 S bits. */
2190 /* Parse a floating-point immediate. Return TRUE on success and return the
2191 value in *IMMED in the format of IEEE754 single-precision encoding.
2192 *CCP points to the start of the string; DP_P is TRUE when the immediate
2193 is expected to be in double-precision (N.B. this only matters when
2194 hexadecimal representation is involved). REG_TYPE says which register
2195 names should be treated as registers rather than as symbolic immediates.
2197 This routine accepts any IEEE float; it is up to the callers to reject
2201 parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p,
2202 aarch64_reg_type reg_type)
2206 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2207 int found_fpchar = 0;
2209 unsigned fpword = 0;
2210 bfd_boolean hex_p = FALSE;
2212 skip_past_char (&str, '#');
2215 skip_whitespace (fpnum);
2217 if (strncmp (fpnum, "0x", 2) == 0)
2219 /* Support the hexadecimal representation of the IEEE754 encoding.
2220 Double-precision is expected when DP_P is TRUE, otherwise the
2221 representation should be in single-precision. */
2222 if (! parse_constant_immediate (&str, &val, reg_type))
2227 if (!can_convert_double_to_float (val, &fpword))
2230 else if ((uint64_t) val > 0xffffffff)
2239 if (reg_name_p (str, reg_type))
2241 set_recoverable_error (_("immediate operand required"));
2245 /* We must not accidentally parse an integer as a floating-point number.
2246 Make sure that the value we parse is not an integer by checking for
2247 special characters '.' or 'e'. */
2248 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
2249 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
2263 if ((str = atof_ieee (str, 's', words)) == NULL)
2266 /* Our FP word must be 32 bits (single-precision FP). */
2267 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
2269 fpword <<= LITTLENUM_NUMBER_OF_BITS;
2279 set_fatal_syntax_error (_("invalid floating-point constant"));
2283 /* Less-generic immediate-value read function with the possibility of loading
2284 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2287 To prevent the expression parser from pushing a register name into the
2288 symbol table as an undefined symbol, a check is firstly done to find
2289 out whether STR is a register of type REG_TYPE followed by a comma or
2290 the end of line. Return FALSE if STR is such a register. */
2293 parse_big_immediate (char **str, int64_t *imm, aarch64_reg_type reg_type)
2297 if (reg_name_p (ptr, reg_type))
2299 set_syntax_error (_("immediate operand required"));
2303 my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
2305 if (inst.reloc.exp.X_op == O_constant)
2306 *imm = inst.reloc.exp.X_add_number;
2313 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2314 if NEED_LIBOPCODES is non-zero, the fixup will need
2315 assistance from the libopcodes. */
2318 aarch64_set_gas_internal_fixup (struct reloc *reloc,
2319 const aarch64_opnd_info *operand,
2320 int need_libopcodes_p)
2322 reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2323 reloc->opnd = operand->type;
2324 if (need_libopcodes_p)
2325 reloc->need_libopcodes_p = 1;
2328 /* Return TRUE if the instruction needs to be fixed up later internally by
2329 the GAS; otherwise return FALSE. */
2331 static inline bfd_boolean
2332 aarch64_gas_internal_fixup_p (void)
2334 return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2337 /* Assign the immediate value to the relavant field in *OPERAND if
2338 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2339 needs an internal fixup in a later stage.
2340 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2341 IMM.VALUE that may get assigned with the constant. */
2343 assign_imm_if_const_or_fixup_later (struct reloc *reloc,
2344 aarch64_opnd_info *operand,
2346 int need_libopcodes_p,
2349 if (reloc->exp.X_op == O_constant)
2352 operand->addr.offset.imm = reloc->exp.X_add_number;
2354 operand->imm.value = reloc->exp.X_add_number;
2355 reloc->type = BFD_RELOC_UNUSED;
2359 aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p);
2360 /* Tell libopcodes to ignore this operand or not. This is helpful
2361 when one of the operands needs to be fixed up later but we need
2362 libopcodes to check the other operands. */
2363 operand->skip = skip_p;
2367 /* Relocation modifiers. Each entry in the table contains the textual
2368 name for the relocation which may be placed before a symbol used as
2369 a load/store offset, or add immediate. It must be surrounded by a
2370 leading and trailing colon, for example:
2372 ldr x0, [x1, #:rello:varsym]
2373 add x0, x1, #:rello:varsym */
2375 struct reloc_table_entry
2379 bfd_reloc_code_real_type adr_type;
2380 bfd_reloc_code_real_type adrp_type;
2381 bfd_reloc_code_real_type movw_type;
2382 bfd_reloc_code_real_type add_type;
2383 bfd_reloc_code_real_type ldst_type;
2384 bfd_reloc_code_real_type ld_literal_type;
2387 static struct reloc_table_entry reloc_table[] = {
2388 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2393 BFD_RELOC_AARCH64_ADD_LO12,
2394 BFD_RELOC_AARCH64_LDST_LO12,
2397 /* Higher 21 bits of pc-relative page offset: ADRP */
2400 BFD_RELOC_AARCH64_ADR_HI21_PCREL,
2406 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2409 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
2415 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2419 BFD_RELOC_AARCH64_MOVW_G0,
2424 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2428 BFD_RELOC_AARCH64_MOVW_G0_S,
2433 /* Less significant bits 0-15 of address/value: MOVK, no check */
2437 BFD_RELOC_AARCH64_MOVW_G0_NC,
2442 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2446 BFD_RELOC_AARCH64_MOVW_G1,
2451 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2455 BFD_RELOC_AARCH64_MOVW_G1_S,
2460 /* Less significant bits 16-31 of address/value: MOVK, no check */
2464 BFD_RELOC_AARCH64_MOVW_G1_NC,
2469 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2473 BFD_RELOC_AARCH64_MOVW_G2,
2478 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2482 BFD_RELOC_AARCH64_MOVW_G2_S,
2487 /* Less significant bits 32-47 of address/value: MOVK, no check */
2491 BFD_RELOC_AARCH64_MOVW_G2_NC,
2496 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2500 BFD_RELOC_AARCH64_MOVW_G3,
2505 /* Get to the page containing GOT entry for a symbol. */
2508 BFD_RELOC_AARCH64_ADR_GOT_PAGE,
2512 BFD_RELOC_AARCH64_GOT_LD_PREL19},
2514 /* 12 bit offset into the page containing GOT entry for that symbol. */
2520 BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
2523 /* 0-15 bits of address/value: MOVk, no check. */
2527 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC,
2532 /* Most significant bits 16-31 of address/value: MOVZ. */
2536 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1,
2541 /* 15 bit offset into the page containing GOT entry for that symbol. */
2547 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15,
2550 /* Get to the page containing GOT TLS entry for a symbol */
2551 {"gottprel_g0_nc", 0,
2554 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
2559 /* Get to the page containing GOT TLS entry for a symbol */
2563 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
2568 /* Get to the page containing GOT TLS entry for a symbol */
2570 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21, /* adr_type */
2571 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
2577 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2582 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
2586 /* Lower 16 bits address/value: MOVk. */
2590 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC,
2595 /* Most significant bits 16-31 of address/value: MOVZ. */
2599 BFD_RELOC_AARCH64_TLSGD_MOVW_G1,
2604 /* Get to the page containing GOT TLS entry for a symbol */
2606 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21, /* adr_type */
2607 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21,
2611 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19},
2613 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2618 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
2619 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
2622 /* Get to the page containing GOT TLS entry for a symbol.
2623 The same as GD, we allocate two consecutive GOT slots
2624 for module index and module offset, the only difference
2625 with GD is the module offset should be intialized to
2626 zero without any outstanding runtime relocation. */
2628 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21, /* adr_type */
2629 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21,
2635 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2636 {"tlsldm_lo12_nc", 0,
2640 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC,
2644 /* 12 bit offset into the module TLS base address. */
2649 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12,
2650 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12,
2653 /* Same as dtprel_lo12, no overflow check. */
2654 {"dtprel_lo12_nc", 0,
2658 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC,
2659 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC,
2662 /* bits[23:12] of offset to the module TLS base address. */
2667 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12,
2671 /* bits[15:0] of offset to the module TLS base address. */
2675 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0,
2680 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2684 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC,
2689 /* bits[31:16] of offset to the module TLS base address. */
2693 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1,
2698 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2702 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC,
2707 /* bits[47:32] of offset to the module TLS base address. */
2711 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2,
2716 /* Lower 16 bit offset into GOT entry for a symbol */
2717 {"tlsdesc_off_g0_nc", 0,
2720 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
2725 /* Higher 16 bit offset into GOT entry for a symbol */
2726 {"tlsdesc_off_g1", 0,
2729 BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
2734 /* Get to the page containing GOT TLS entry for a symbol */
2737 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
2741 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19},
2743 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2744 {"gottprel_lo12", 0,
2749 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC,
2752 /* Get tp offset for a symbol. */
2757 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2761 /* Get tp offset for a symbol. */
2766 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2770 /* Get tp offset for a symbol. */
2775 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
2779 /* Get tp offset for a symbol. */
2780 {"tprel_lo12_nc", 0,
2784 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
2788 /* Most significant bits 32-47 of address/value: MOVZ. */
2792 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
2797 /* Most significant bits 16-31 of address/value: MOVZ. */
2801 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
2806 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2810 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
2815 /* Most significant bits 0-15 of address/value: MOVZ. */
2819 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
2824 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2828 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
2833 /* 15bit offset from got entry to base address of GOT table. */
2839 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15,
2842 /* 14bit offset from got entry to base address of GOT table. */
2848 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14,
2852 /* Given the address of a pointer pointing to the textual name of a
2853 relocation as may appear in assembler source, attempt to find its
2854 details in reloc_table. The pointer will be updated to the character
2855 after the trailing colon. On failure, NULL will be returned;
2856 otherwise return the reloc_table_entry. */
2858 static struct reloc_table_entry *
2859 find_reloc_table_entry (char **str)
2862 for (i = 0; i < ARRAY_SIZE (reloc_table); i++)
2864 int length = strlen (reloc_table[i].name);
2866 if (strncasecmp (reloc_table[i].name, *str, length) == 0
2867 && (*str)[length] == ':')
2869 *str += (length + 1);
2870 return &reloc_table[i];
2877 /* Mode argument to parse_shift and parser_shifter_operand. */
2878 enum parse_shift_mode
2880 SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2882 SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2884 SHIFTED_LSL, /* bare "lsl #n" */
2885 SHIFTED_LSL_MSL, /* "lsl|msl #n" */
2886 SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */
2889 /* Parse a <shift> operator on an AArch64 data processing instruction.
2890 Return TRUE on success; otherwise return FALSE. */
2892 parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
2894 const struct aarch64_name_value_pair *shift_op;
2895 enum aarch64_modifier_kind kind;
2901 for (p = *str; ISALPHA (*p); p++)
2906 set_syntax_error (_("shift expression expected"));
2910 shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str);
2912 if (shift_op == NULL)
2914 set_syntax_error (_("shift operator expected"));
2918 kind = aarch64_get_operand_modifier (shift_op);
2920 if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
2922 set_syntax_error (_("invalid use of 'MSL'"));
2928 case SHIFTED_LOGIC_IMM:
2929 if (aarch64_extend_operator_p (kind) == TRUE)
2931 set_syntax_error (_("extending shift is not permitted"));
2936 case SHIFTED_ARITH_IMM:
2937 if (kind == AARCH64_MOD_ROR)
2939 set_syntax_error (_("'ROR' shift is not permitted"));
2945 if (kind != AARCH64_MOD_LSL)
2947 set_syntax_error (_("only 'LSL' shift is permitted"));
2952 case SHIFTED_REG_OFFSET:
2953 if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
2954 && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX)
2956 set_fatal_syntax_error
2957 (_("invalid shift for the register offset addressing mode"));
2962 case SHIFTED_LSL_MSL:
2963 if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
2965 set_syntax_error (_("invalid shift operator"));
2974 /* Whitespace can appear here if the next thing is a bare digit. */
2975 skip_whitespace (p);
2977 /* Parse shift amount. */
2979 if (mode == SHIFTED_REG_OFFSET && *p == ']')
2980 exp.X_op = O_absent;
2983 if (is_immediate_prefix (*p))
2988 my_get_expression (&exp, &p, GE_NO_PREFIX, 0);
2990 if (exp.X_op == O_absent)
2992 if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
2994 set_syntax_error (_("missing shift amount"));
2997 operand->shifter.amount = 0;
2999 else if (exp.X_op != O_constant)
3001 set_syntax_error (_("constant shift amount required"));
3004 else if (exp.X_add_number < 0 || exp.X_add_number > 63)
3006 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3011 operand->shifter.amount = exp.X_add_number;
3012 operand->shifter.amount_present = 1;
3015 operand->shifter.operator_present = 1;
3016 operand->shifter.kind = kind;
3022 /* Parse a <shifter_operand> for a data processing instruction:
3025 #<immediate>, LSL #imm
3027 Validation of immediate operands is deferred to md_apply_fix.
3029 Return TRUE on success; otherwise return FALSE. */
3032 parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
3033 enum parse_shift_mode mode)
3037 if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
3042 /* Accept an immediate expression. */
3043 if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
3046 /* Accept optional LSL for arithmetic immediate values. */
3047 if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
3048 if (! parse_shift (&p, operand, SHIFTED_LSL))
3051 /* Not accept any shifter for logical immediate values. */
3052 if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
3053 && parse_shift (&p, operand, mode))
3055 set_syntax_error (_("unexpected shift operator"));
3063 /* Parse a <shifter_operand> for a data processing instruction:
3068 #<immediate>, LSL #imm
3070 where <shift> is handled by parse_shift above, and the last two
3071 cases are handled by the function above.
3073 Validation of immediate operands is deferred to md_apply_fix.
3075 Return TRUE on success; otherwise return FALSE. */
3078 parse_shifter_operand (char **str, aarch64_opnd_info *operand,
3079 enum parse_shift_mode mode)
3081 const reg_entry *reg;
3082 aarch64_opnd_qualifier_t qualifier;
3083 enum aarch64_operand_class opd_class
3084 = aarch64_get_operand_class (operand->type);
3086 reg = aarch64_reg_parse_32_64 (str, &qualifier);
3089 if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
3091 set_syntax_error (_("unexpected register in the immediate operand"));
3095 if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
3097 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z)));
3101 operand->reg.regno = reg->number;
3102 operand->qualifier = qualifier;
3104 /* Accept optional shift operation on register. */
3105 if (! skip_past_comma (str))
3108 if (! parse_shift (str, operand, mode))
3113 else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
3116 (_("integer register expected in the extended/shifted operand "
3121 /* We have a shifted immediate variable. */
3122 return parse_shifter_operand_imm (str, operand, mode);
3125 /* Return TRUE on success; return FALSE otherwise. */
3128 parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
3129 enum parse_shift_mode mode)
3133 /* Determine if we have the sequence of characters #: or just :
3134 coming next. If we do, then we check for a :rello: relocation
3135 modifier. If we don't, punt the whole lot to
3136 parse_shifter_operand. */
3138 if ((p[0] == '#' && p[1] == ':') || p[0] == ':')
3140 struct reloc_table_entry *entry;
3148 /* Try to parse a relocation. Anything else is an error. */
3149 if (!(entry = find_reloc_table_entry (str)))
3151 set_syntax_error (_("unknown relocation modifier"));
3155 if (entry->add_type == 0)
3158 (_("this relocation modifier is not allowed on this instruction"));
3162 /* Save str before we decompose it. */
3165 /* Next, we parse the expression. */
3166 if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
3169 /* Record the relocation type (use the ADD variant here). */
3170 inst.reloc.type = entry->add_type;
3171 inst.reloc.pc_rel = entry->pc_rel;
3173 /* If str is empty, we've reached the end, stop here. */
3177 /* Otherwise, we have a shifted reloc modifier, so rewind to
3178 recover the variable name and continue parsing for the shifter. */
3180 return parse_shifter_operand_imm (str, operand, mode);
3183 return parse_shifter_operand (str, operand, mode);
3186 /* Parse all forms of an address expression. Information is written
3187 to *OPERAND and/or inst.reloc.
3189 The A64 instruction set has the following addressing modes:
3192 [base] // in SIMD ld/st structure
3193 [base{,#0}] // in ld/st exclusive
3195 [base,Xm{,LSL #imm}]
3196 [base,Xm,SXTX {#imm}]
3197 [base,Wm,(S|U)XTW {#imm}]
3202 [base],Xm // in SIMD ld/st structure
3203 PC-relative (literal)
3207 (As a convenience, the notation "=immediate" is permitted in conjunction
3208 with the pc-relative literal load instructions to automatically place an
3209 immediate value or symbolic address in a nearby literal pool and generate
3210 a hidden label which references it.)
3212 Upon a successful parsing, the address structure in *OPERAND will be
3213 filled in the following way:
3215 .base_regno = <base>
3216 .offset.is_reg // 1 if the offset is a register
3218 .offset.regno = <Rm>
3220 For different addressing modes defined in the A64 ISA:
3223 .pcrel=0; .preind=1; .postind=0; .writeback=0
3225 .pcrel=0; .preind=1; .postind=0; .writeback=1
3227 .pcrel=0; .preind=0; .postind=1; .writeback=1
3228 PC-relative (literal)
3229 .pcrel=1; .preind=1; .postind=0; .writeback=0
3231 The shift/extension information, if any, will be stored in .shifter.
3233 It is the caller's responsibility to check for addressing modes not
3234 supported by the instruction, and to set inst.reloc.type. */
3237 parse_address_main (char **str, aarch64_opnd_info *operand)
3240 const reg_entry *reg;
3241 aarch64_opnd_qualifier_t base_qualifier;
3242 aarch64_opnd_qualifier_t offset_qualifier;
3243 expressionS *exp = &inst.reloc.exp;
3245 if (! skip_past_char (&p, '['))
3247 /* =immediate or label. */
3248 operand->addr.pcrel = 1;
3249 operand->addr.preind = 1;
3251 /* #:<reloc_op>:<symbol> */
3252 skip_past_char (&p, '#');
3253 if (skip_past_char (&p, ':'))
3255 bfd_reloc_code_real_type ty;
3256 struct reloc_table_entry *entry;
3258 /* Try to parse a relocation modifier. Anything else is
3260 entry = find_reloc_table_entry (&p);
3263 set_syntax_error (_("unknown relocation modifier"));
3267 switch (operand->type)
3269 case AARCH64_OPND_ADDR_PCREL21:
3271 ty = entry->adr_type;
3275 ty = entry->ld_literal_type;
3282 (_("this relocation modifier is not allowed on this "
3288 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3290 set_syntax_error (_("invalid relocation expression"));
3294 /* #:<reloc_op>:<expr> */
3295 /* Record the relocation type. */
3296 inst.reloc.type = ty;
3297 inst.reloc.pc_rel = entry->pc_rel;
3302 if (skip_past_char (&p, '='))
3303 /* =immediate; need to generate the literal in the literal pool. */
3304 inst.gen_lit_pool = 1;
3306 if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3308 set_syntax_error (_("invalid address"));
3319 reg = aarch64_reg_parse_32_64 (&p, &base_qualifier);
3320 if (!reg || !aarch64_check_reg_type (reg, REG_TYPE_R64_SP))
3322 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R64_SP)));
3325 operand->addr.base_regno = reg->number;
3328 if (skip_past_comma (&p))
3331 operand->addr.preind = 1;
3333 reg = aarch64_reg_parse_32_64 (&p, &offset_qualifier);
3336 if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
3338 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z)));
3343 operand->addr.offset.regno = reg->number;
3344 operand->addr.offset.is_reg = 1;
3345 /* Shifted index. */
3346 if (skip_past_comma (&p))
3349 if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
3350 /* Use the diagnostics set in parse_shift, so not set new
3351 error message here. */
3355 [base,Xm{,LSL #imm}]
3356 [base,Xm,SXTX {#imm}]
3357 [base,Wm,(S|U)XTW {#imm}] */
3358 if (operand->shifter.kind == AARCH64_MOD_NONE
3359 || operand->shifter.kind == AARCH64_MOD_LSL
3360 || operand->shifter.kind == AARCH64_MOD_SXTX)
3362 if (offset_qualifier == AARCH64_OPND_QLF_W)
3364 set_syntax_error (_("invalid use of 32-bit register offset"));
3368 else if (offset_qualifier == AARCH64_OPND_QLF_X)
3370 set_syntax_error (_("invalid use of 64-bit register offset"));
3376 /* [Xn,#:<reloc_op>:<symbol> */
3377 skip_past_char (&p, '#');
3378 if (skip_past_char (&p, ':'))
3380 struct reloc_table_entry *entry;
3382 /* Try to parse a relocation modifier. Anything else is
3384 if (!(entry = find_reloc_table_entry (&p)))
3386 set_syntax_error (_("unknown relocation modifier"));
3390 if (entry->ldst_type == 0)
3393 (_("this relocation modifier is not allowed on this "
3398 /* [Xn,#:<reloc_op>: */
3399 /* We now have the group relocation table entry corresponding to
3400 the name in the assembler source. Next, we parse the
3402 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3404 set_syntax_error (_("invalid relocation expression"));
3408 /* [Xn,#:<reloc_op>:<expr> */
3409 /* Record the load/store relocation type. */
3410 inst.reloc.type = entry->ldst_type;
3411 inst.reloc.pc_rel = entry->pc_rel;
3413 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3415 set_syntax_error (_("invalid expression in the address"));
3422 if (! skip_past_char (&p, ']'))
3424 set_syntax_error (_("']' expected"));
3428 if (skip_past_char (&p, '!'))
3430 if (operand->addr.preind && operand->addr.offset.is_reg)
3432 set_syntax_error (_("register offset not allowed in pre-indexed "
3433 "addressing mode"));
3437 operand->addr.writeback = 1;
3439 else if (skip_past_comma (&p))
3442 operand->addr.postind = 1;
3443 operand->addr.writeback = 1;
3445 if (operand->addr.preind)
3447 set_syntax_error (_("cannot combine pre- and post-indexing"));
3451 reg = aarch64_reg_parse_32_64 (&p, &offset_qualifier);
3455 if (!aarch64_check_reg_type (reg, REG_TYPE_R_64))
3457 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
3461 operand->addr.offset.regno = reg->number;
3462 operand->addr.offset.is_reg = 1;
3464 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3467 set_syntax_error (_("invalid expression in the address"));
3472 /* If at this point neither .preind nor .postind is set, we have a
3473 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3474 if (operand->addr.preind == 0 && operand->addr.postind == 0)
3476 if (operand->addr.writeback)
3479 set_syntax_error (_("missing offset in the pre-indexed address"));
3482 operand->addr.preind = 1;
3483 inst.reloc.exp.X_op = O_constant;
3484 inst.reloc.exp.X_add_number = 0;
3491 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3494 parse_address (char **str, aarch64_opnd_info *operand)
3496 return parse_address_main (str, operand);
3499 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3500 Return TRUE on success; otherwise return FALSE. */
3502 parse_half (char **str, int *internal_fixup_p)
3506 skip_past_char (&p, '#');
3508 gas_assert (internal_fixup_p);
3509 *internal_fixup_p = 0;
3513 struct reloc_table_entry *entry;
3515 /* Try to parse a relocation. Anything else is an error. */
3517 if (!(entry = find_reloc_table_entry (&p)))
3519 set_syntax_error (_("unknown relocation modifier"));
3523 if (entry->movw_type == 0)
3526 (_("this relocation modifier is not allowed on this instruction"));
3530 inst.reloc.type = entry->movw_type;
3533 *internal_fixup_p = 1;
3535 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3542 /* Parse an operand for an ADRP instruction:
3544 Return TRUE on success; otherwise return FALSE. */
3547 parse_adrp (char **str)
3554 struct reloc_table_entry *entry;
3556 /* Try to parse a relocation. Anything else is an error. */
3558 if (!(entry = find_reloc_table_entry (&p)))
3560 set_syntax_error (_("unknown relocation modifier"));
3564 if (entry->adrp_type == 0)
3567 (_("this relocation modifier is not allowed on this instruction"));
3571 inst.reloc.type = entry->adrp_type;
3574 inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
3576 inst.reloc.pc_rel = 1;
3578 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3585 /* Miscellaneous. */
3587 /* Parse an option for a preload instruction. Returns the encoding for the
3588 option, or PARSE_FAIL. */
3591 parse_pldop (char **str)
3594 const struct aarch64_name_value_pair *o;
3597 while (ISALNUM (*q))
3600 o = hash_find_n (aarch64_pldop_hsh, p, q - p);
3608 /* Parse an option for a barrier instruction. Returns the encoding for the
3609 option, or PARSE_FAIL. */
3612 parse_barrier (char **str)
3615 const asm_barrier_opt *o;
3618 while (ISALPHA (*q))
3621 o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p);
3629 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3630 return 0 if successful. Otherwise return PARSE_FAIL. */
3633 parse_barrier_psb (char **str,
3634 const struct aarch64_name_value_pair ** hint_opt)
3637 const struct aarch64_name_value_pair *o;
3640 while (ISALPHA (*q))
3643 o = hash_find_n (aarch64_hint_opt_hsh, p, q - p);
3646 set_fatal_syntax_error
3647 ( _("unknown or missing option to PSB"));
3651 if (o->value != 0x11)
3653 /* PSB only accepts option name 'CSYNC'. */
3655 (_("the specified option is not accepted for PSB"));
3664 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3665 Returns the encoding for the option, or PARSE_FAIL.
3667 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3668 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3670 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3671 field, otherwise as a system register.
3675 parse_sys_reg (char **str, struct hash_control *sys_regs,
3676 int imple_defined_p, int pstatefield_p)
3680 const aarch64_sys_reg *o;
3684 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3686 *p++ = TOLOWER (*q);
3688 /* Assert that BUF be large enough. */
3689 gas_assert (p - buf == q - *str);
3691 o = hash_find (sys_regs, buf);
3694 if (!imple_defined_p)
3698 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3699 unsigned int op0, op1, cn, cm, op2;
3701 if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2)
3704 if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
3706 value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
3711 if (pstatefield_p && !aarch64_pstatefield_supported_p (cpu_variant, o))
3712 as_bad (_("selected processor does not support PSTATE field "
3714 if (!pstatefield_p && !aarch64_sys_reg_supported_p (cpu_variant, o))
3715 as_bad (_("selected processor does not support system register "
3717 if (aarch64_sys_reg_deprecated_p (o))
3718 as_warn (_("system register name '%s' is deprecated and may be "
3719 "removed in a future release"), buf);
3727 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3728 for the option, or NULL. */
3730 static const aarch64_sys_ins_reg *
3731 parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
3735 const aarch64_sys_ins_reg *o;
3738 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3740 *p++ = TOLOWER (*q);
3743 o = hash_find (sys_ins_regs, buf);
3747 if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
3748 as_bad (_("selected processor does not support system register "
3755 #define po_char_or_fail(chr) do { \
3756 if (! skip_past_char (&str, chr)) \
3760 #define po_reg_or_fail(regtype) do { \
3761 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3762 if (val == PARSE_FAIL) \
3764 set_default_error (); \
3769 #define po_int_reg_or_fail(reg_type) do { \
3770 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
3771 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
3773 set_default_error (); \
3776 info->reg.regno = reg->number; \
3777 info->qualifier = qualifier; \
3780 #define po_imm_nc_or_fail() do { \
3781 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3785 #define po_imm_or_fail(min, max) do { \
3786 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3788 if (val < min || val > max) \
3790 set_fatal_syntax_error (_("immediate value out of range "\
3791 #min " to "#max)); \
3796 #define po_misc_or_fail(expr) do { \
3801 /* encode the 12-bit imm field of Add/sub immediate */
3802 static inline uint32_t
3803 encode_addsub_imm (uint32_t imm)
3808 /* encode the shift amount field of Add/sub immediate */
3809 static inline uint32_t
3810 encode_addsub_imm_shift_amount (uint32_t cnt)
3816 /* encode the imm field of Adr instruction */
3817 static inline uint32_t
3818 encode_adr_imm (uint32_t imm)
3820 return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */
3821 | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3824 /* encode the immediate field of Move wide immediate */
3825 static inline uint32_t
3826 encode_movw_imm (uint32_t imm)
3831 /* encode the 26-bit offset of unconditional branch */
3832 static inline uint32_t
3833 encode_branch_ofs_26 (uint32_t ofs)
3835 return ofs & ((1 << 26) - 1);
3838 /* encode the 19-bit offset of conditional branch and compare & branch */
3839 static inline uint32_t
3840 encode_cond_branch_ofs_19 (uint32_t ofs)
3842 return (ofs & ((1 << 19) - 1)) << 5;
3845 /* encode the 19-bit offset of ld literal */
3846 static inline uint32_t
3847 encode_ld_lit_ofs_19 (uint32_t ofs)
3849 return (ofs & ((1 << 19) - 1)) << 5;
3852 /* Encode the 14-bit offset of test & branch. */
3853 static inline uint32_t
3854 encode_tst_branch_ofs_14 (uint32_t ofs)
3856 return (ofs & ((1 << 14) - 1)) << 5;
3859 /* Encode the 16-bit imm field of svc/hvc/smc. */
3860 static inline uint32_t
3861 encode_svc_imm (uint32_t imm)
3866 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3867 static inline uint32_t
3868 reencode_addsub_switch_add_sub (uint32_t opcode)
3870 return opcode ^ (1 << 30);
3873 static inline uint32_t
3874 reencode_movzn_to_movz (uint32_t opcode)
3876 return opcode | (1 << 30);
3879 static inline uint32_t
3880 reencode_movzn_to_movn (uint32_t opcode)
3882 return opcode & ~(1 << 30);
3885 /* Overall per-instruction processing. */
3887 /* We need to be able to fix up arbitrary expressions in some statements.
3888 This is so that we can handle symbols that are an arbitrary distance from
3889 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3890 which returns part of an address in a form which will be valid for
3891 a data instruction. We do this by pushing the expression into a symbol
3892 in the expr_section, and creating a fix for that. */
3895 fix_new_aarch64 (fragS * frag,
3897 short int size, expressionS * exp, int pc_rel, int reloc)
3907 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
3911 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
3918 /* Diagnostics on operands errors. */
3920 /* By default, output verbose error message.
3921 Disable the verbose error message by -mno-verbose-error. */
3922 static int verbose_error_p = 1;
3924 #ifdef DEBUG_AARCH64
3925 /* N.B. this is only for the purpose of debugging. */
3926 const char* operand_mismatch_kind_names[] =
3929 "AARCH64_OPDE_RECOVERABLE",
3930 "AARCH64_OPDE_SYNTAX_ERROR",
3931 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3932 "AARCH64_OPDE_INVALID_VARIANT",
3933 "AARCH64_OPDE_OUT_OF_RANGE",
3934 "AARCH64_OPDE_UNALIGNED",
3935 "AARCH64_OPDE_REG_LIST",
3936 "AARCH64_OPDE_OTHER_ERROR",
3938 #endif /* DEBUG_AARCH64 */
3940 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3942 When multiple errors of different kinds are found in the same assembly
3943 line, only the error of the highest severity will be picked up for
3944 issuing the diagnostics. */
3946 static inline bfd_boolean
3947 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
3948 enum aarch64_operand_error_kind rhs)
3950 gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL);
3951 gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE);
3952 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
3953 gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
3954 gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
3955 gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
3956 gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
3957 gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
3961 /* Helper routine to get the mnemonic name from the assembly instruction
3962 line; should only be called for the diagnosis purpose, as there is
3963 string copy operation involved, which may affect the runtime
3964 performance if used in elsewhere. */
3967 get_mnemonic_name (const char *str)
3969 static char mnemonic[32];
3972 /* Get the first 15 bytes and assume that the full name is included. */
3973 strncpy (mnemonic, str, 31);
3974 mnemonic[31] = '\0';
3976 /* Scan up to the end of the mnemonic, which must end in white space,
3977 '.', or end of string. */
3978 for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr)
3983 /* Append '...' to the truncated long name. */
3984 if (ptr - mnemonic == 31)
3985 mnemonic[28] = mnemonic[29] = mnemonic[30] = '.';
3991 reset_aarch64_instruction (aarch64_instruction *instruction)
3993 memset (instruction, '\0', sizeof (aarch64_instruction));
3994 instruction->reloc.type = BFD_RELOC_UNUSED;
3997 /* Data strutures storing one user error in the assembly code related to
4000 struct operand_error_record
4002 const aarch64_opcode *opcode;
4003 aarch64_operand_error detail;
4004 struct operand_error_record *next;
4007 typedef struct operand_error_record operand_error_record;
4009 struct operand_errors
4011 operand_error_record *head;
4012 operand_error_record *tail;
4015 typedef struct operand_errors operand_errors;
4017 /* Top-level data structure reporting user errors for the current line of
4019 The way md_assemble works is that all opcodes sharing the same mnemonic
4020 name are iterated to find a match to the assembly line. In this data
4021 structure, each of the such opcodes will have one operand_error_record
4022 allocated and inserted. In other words, excessive errors related with
4023 a single opcode are disregarded. */
4024 operand_errors operand_error_report;
4026 /* Free record nodes. */
4027 static operand_error_record *free_opnd_error_record_nodes = NULL;
4029 /* Initialize the data structure that stores the operand mismatch
4030 information on assembling one line of the assembly code. */
4032 init_operand_error_report (void)
4034 if (operand_error_report.head != NULL)
4036 gas_assert (operand_error_report.tail != NULL);
4037 operand_error_report.tail->next = free_opnd_error_record_nodes;
4038 free_opnd_error_record_nodes = operand_error_report.head;
4039 operand_error_report.head = NULL;
4040 operand_error_report.tail = NULL;
4043 gas_assert (operand_error_report.tail == NULL);
4046 /* Return TRUE if some operand error has been recorded during the
4047 parsing of the current assembly line using the opcode *OPCODE;
4048 otherwise return FALSE. */
4049 static inline bfd_boolean
4050 opcode_has_operand_error_p (const aarch64_opcode *opcode)
4052 operand_error_record *record = operand_error_report.head;
4053 return record && record->opcode == opcode;
4056 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4057 OPCODE field is initialized with OPCODE.
4058 N.B. only one record for each opcode, i.e. the maximum of one error is
4059 recorded for each instruction template. */
4062 add_operand_error_record (const operand_error_record* new_record)
4064 const aarch64_opcode *opcode = new_record->opcode;
4065 operand_error_record* record = operand_error_report.head;
4067 /* The record may have been created for this opcode. If not, we need
4069 if (! opcode_has_operand_error_p (opcode))
4071 /* Get one empty record. */
4072 if (free_opnd_error_record_nodes == NULL)
4074 record = XNEW (operand_error_record);
4078 record = free_opnd_error_record_nodes;
4079 free_opnd_error_record_nodes = record->next;
4081 record->opcode = opcode;
4082 /* Insert at the head. */
4083 record->next = operand_error_report.head;
4084 operand_error_report.head = record;
4085 if (operand_error_report.tail == NULL)
4086 operand_error_report.tail = record;
4088 else if (record->detail.kind != AARCH64_OPDE_NIL
4089 && record->detail.index <= new_record->detail.index
4090 && operand_error_higher_severity_p (record->detail.kind,
4091 new_record->detail.kind))
4093 /* In the case of multiple errors found on operands related with a
4094 single opcode, only record the error of the leftmost operand and
4095 only if the error is of higher severity. */
4096 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4097 " the existing error %s on operand %d",
4098 operand_mismatch_kind_names[new_record->detail.kind],
4099 new_record->detail.index,
4100 operand_mismatch_kind_names[record->detail.kind],
4101 record->detail.index);
4105 record->detail = new_record->detail;
4109 record_operand_error_info (const aarch64_opcode *opcode,
4110 aarch64_operand_error *error_info)
4112 operand_error_record record;
4113 record.opcode = opcode;
4114 record.detail = *error_info;
4115 add_operand_error_record (&record);
4118 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4119 error message *ERROR, for operand IDX (count from 0). */
4122 record_operand_error (const aarch64_opcode *opcode, int idx,
4123 enum aarch64_operand_error_kind kind,
4126 aarch64_operand_error info;
4127 memset(&info, 0, sizeof (info));
4131 record_operand_error_info (opcode, &info);
4135 record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
4136 enum aarch64_operand_error_kind kind,
4137 const char* error, const int *extra_data)
4139 aarch64_operand_error info;
4143 info.data[0] = extra_data[0];
4144 info.data[1] = extra_data[1];
4145 info.data[2] = extra_data[2];
4146 record_operand_error_info (opcode, &info);
4150 record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx,
4151 const char* error, int lower_bound,
4154 int data[3] = {lower_bound, upper_bound, 0};
4155 record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE,
4159 /* Remove the operand error record for *OPCODE. */
4160 static void ATTRIBUTE_UNUSED
4161 remove_operand_error_record (const aarch64_opcode *opcode)
4163 if (opcode_has_operand_error_p (opcode))
4165 operand_error_record* record = operand_error_report.head;
4166 gas_assert (record != NULL && operand_error_report.tail != NULL);
4167 operand_error_report.head = record->next;
4168 record->next = free_opnd_error_record_nodes;
4169 free_opnd_error_record_nodes = record;
4170 if (operand_error_report.head == NULL)
4172 gas_assert (operand_error_report.tail == record);
4173 operand_error_report.tail = NULL;
4178 /* Given the instruction in *INSTR, return the index of the best matched
4179 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4181 Return -1 if there is no qualifier sequence; return the first match
4182 if there is multiple matches found. */
4185 find_best_match (const aarch64_inst *instr,
4186 const aarch64_opnd_qualifier_seq_t *qualifiers_list)
4188 int i, num_opnds, max_num_matched, idx;
4190 num_opnds = aarch64_num_of_operands (instr->opcode);
4193 DEBUG_TRACE ("no operand");
4197 max_num_matched = 0;
4200 /* For each pattern. */
4201 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4204 const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
4206 /* Most opcodes has much fewer patterns in the list. */
4207 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
4209 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
4213 for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers)
4214 if (*qualifiers == instr->operands[j].qualifier)
4217 if (num_matched > max_num_matched)
4219 max_num_matched = num_matched;
4224 DEBUG_TRACE ("return with %d", idx);
4228 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4229 corresponding operands in *INSTR. */
4232 assign_qualifier_sequence (aarch64_inst *instr,
4233 const aarch64_opnd_qualifier_t *qualifiers)
4236 int num_opnds = aarch64_num_of_operands (instr->opcode);
4237 gas_assert (num_opnds);
4238 for (i = 0; i < num_opnds; ++i, ++qualifiers)
4239 instr->operands[i].qualifier = *qualifiers;
4242 /* Print operands for the diagnosis purpose. */
4245 print_operands (char *buf, const aarch64_opcode *opcode,
4246 const aarch64_opnd_info *opnds)
4250 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
4254 /* We regard the opcode operand info more, however we also look into
4255 the inst->operands to support the disassembling of the optional
4257 The two operand code should be the same in all cases, apart from
4258 when the operand can be optional. */
4259 if (opcode->operands[i] == AARCH64_OPND_NIL
4260 || opnds[i].type == AARCH64_OPND_NIL)
4263 /* Generate the operand string in STR. */
4264 aarch64_print_operand (str, sizeof (str), 0, opcode, opnds, i, NULL, NULL);
4268 strcat (buf, i == 0 ? " " : ",");
4270 /* Append the operand string. */
4275 /* Send to stderr a string as information. */
4278 output_info (const char *format, ...)
4284 file = as_where (&line);
4288 fprintf (stderr, "%s:%u: ", file, line);
4290 fprintf (stderr, "%s: ", file);
4292 fprintf (stderr, _("Info: "));
4293 va_start (args, format);
4294 vfprintf (stderr, format, args);
4296 (void) putc ('\n', stderr);
4299 /* Output one operand error record. */
4302 output_operand_error_record (const operand_error_record *record, char *str)
4304 const aarch64_operand_error *detail = &record->detail;
4305 int idx = detail->index;
4306 const aarch64_opcode *opcode = record->opcode;
4307 enum aarch64_opnd opd_code = (idx >= 0 ? opcode->operands[idx]
4308 : AARCH64_OPND_NIL);
4310 switch (detail->kind)
4312 case AARCH64_OPDE_NIL:
4316 case AARCH64_OPDE_SYNTAX_ERROR:
4317 case AARCH64_OPDE_RECOVERABLE:
4318 case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
4319 case AARCH64_OPDE_OTHER_ERROR:
4320 /* Use the prepared error message if there is, otherwise use the
4321 operand description string to describe the error. */
4322 if (detail->error != NULL)
4325 as_bad (_("%s -- `%s'"), detail->error, str);
4327 as_bad (_("%s at operand %d -- `%s'"),
4328 detail->error, idx + 1, str);
4332 gas_assert (idx >= 0);
4333 as_bad (_("operand %d should be %s -- `%s'"), idx + 1,
4334 aarch64_get_operand_desc (opd_code), str);
4338 case AARCH64_OPDE_INVALID_VARIANT:
4339 as_bad (_("operand mismatch -- `%s'"), str);
4340 if (verbose_error_p)
4342 /* We will try to correct the erroneous instruction and also provide
4343 more information e.g. all other valid variants.
4345 The string representation of the corrected instruction and other
4346 valid variants are generated by
4348 1) obtaining the intermediate representation of the erroneous
4350 2) manipulating the IR, e.g. replacing the operand qualifier;
4351 3) printing out the instruction by calling the printer functions
4352 shared with the disassembler.
4354 The limitation of this method is that the exact input assembly
4355 line cannot be accurately reproduced in some cases, for example an
4356 optional operand present in the actual assembly line will be
4357 omitted in the output; likewise for the optional syntax rules,
4358 e.g. the # before the immediate. Another limitation is that the
4359 assembly symbols and relocation operations in the assembly line
4360 currently cannot be printed out in the error report. Last but not
4361 least, when there is other error(s) co-exist with this error, the
4362 'corrected' instruction may be still incorrect, e.g. given
4363 'ldnp h0,h1,[x0,#6]!'
4364 this diagnosis will provide the version:
4365 'ldnp s0,s1,[x0,#6]!'
4366 which is still not right. */
4367 size_t len = strlen (get_mnemonic_name (str));
4371 aarch64_inst *inst_base = &inst.base;
4372 const aarch64_opnd_qualifier_seq_t *qualifiers_list;
4375 reset_aarch64_instruction (&inst);
4376 inst_base->opcode = opcode;
4378 /* Reset the error report so that there is no side effect on the
4379 following operand parsing. */
4380 init_operand_error_report ();
4383 result = parse_operands (str + len, opcode)
4384 && programmer_friendly_fixup (&inst);
4385 gas_assert (result);
4386 result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
4388 gas_assert (!result);
4390 /* Find the most matched qualifier sequence. */
4391 qlf_idx = find_best_match (inst_base, opcode->qualifiers_list);
4392 gas_assert (qlf_idx > -1);
4394 /* Assign the qualifiers. */
4395 assign_qualifier_sequence (inst_base,
4396 opcode->qualifiers_list[qlf_idx]);
4398 /* Print the hint. */
4399 output_info (_(" did you mean this?"));
4400 snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str));
4401 print_operands (buf, opcode, inst_base->operands);
4402 output_info (_(" %s"), buf);
4404 /* Print out other variant(s) if there is any. */
4406 !empty_qualifier_sequence_p (opcode->qualifiers_list[1]))
4407 output_info (_(" other valid variant(s):"));
4409 /* For each pattern. */
4410 qualifiers_list = opcode->qualifiers_list;
4411 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4413 /* Most opcodes has much fewer patterns in the list.
4414 First NIL qualifier indicates the end in the list. */
4415 if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
4420 /* Mnemonics name. */
4421 snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str));
4423 /* Assign the qualifiers. */
4424 assign_qualifier_sequence (inst_base, *qualifiers_list);
4426 /* Print instruction. */
4427 print_operands (buf, opcode, inst_base->operands);
4429 output_info (_(" %s"), buf);
4435 case AARCH64_OPDE_UNTIED_OPERAND:
4436 as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
4437 detail->index + 1, str);
4440 case AARCH64_OPDE_OUT_OF_RANGE:
4441 if (detail->data[0] != detail->data[1])
4442 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4443 detail->error ? detail->error : _("immediate value"),
4444 detail->data[0], detail->data[1], idx + 1, str);
4446 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4447 detail->error ? detail->error : _("immediate value"),
4448 detail->data[0], idx + 1, str);
4451 case AARCH64_OPDE_REG_LIST:
4452 if (detail->data[0] == 1)
4453 as_bad (_("invalid number of registers in the list; "
4454 "only 1 register is expected at operand %d -- `%s'"),
4457 as_bad (_("invalid number of registers in the list; "
4458 "%d registers are expected at operand %d -- `%s'"),
4459 detail->data[0], idx + 1, str);
4462 case AARCH64_OPDE_UNALIGNED:
4463 as_bad (_("immediate value should be a multiple of "
4464 "%d at operand %d -- `%s'"),
4465 detail->data[0], idx + 1, str);
4474 /* Process and output the error message about the operand mismatching.
4476 When this function is called, the operand error information had
4477 been collected for an assembly line and there will be multiple
4478 errors in the case of mulitple instruction templates; output the
4479 error message that most closely describes the problem. */
4482 output_operand_error_report (char *str)
4484 int largest_error_pos;
4485 const char *msg = NULL;
4486 enum aarch64_operand_error_kind kind;
4487 operand_error_record *curr;
4488 operand_error_record *head = operand_error_report.head;
4489 operand_error_record *record = NULL;
4491 /* No error to report. */
4495 gas_assert (head != NULL && operand_error_report.tail != NULL);
4497 /* Only one error. */
4498 if (head == operand_error_report.tail)
4500 DEBUG_TRACE ("single opcode entry with error kind: %s",
4501 operand_mismatch_kind_names[head->detail.kind]);
4502 output_operand_error_record (head, str);
4506 /* Find the error kind of the highest severity. */
4507 DEBUG_TRACE ("multiple opcode entres with error kind");
4508 kind = AARCH64_OPDE_NIL;
4509 for (curr = head; curr != NULL; curr = curr->next)
4511 gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
4512 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
4513 if (operand_error_higher_severity_p (curr->detail.kind, kind))
4514 kind = curr->detail.kind;
4516 gas_assert (kind != AARCH64_OPDE_NIL);
4518 /* Pick up one of errors of KIND to report. */
4519 largest_error_pos = -2; /* Index can be -1 which means unknown index. */
4520 for (curr = head; curr != NULL; curr = curr->next)
4522 if (curr->detail.kind != kind)
4524 /* If there are multiple errors, pick up the one with the highest
4525 mismatching operand index. In the case of multiple errors with
4526 the equally highest operand index, pick up the first one or the
4527 first one with non-NULL error message. */
4528 if (curr->detail.index > largest_error_pos
4529 || (curr->detail.index == largest_error_pos && msg == NULL
4530 && curr->detail.error != NULL))
4532 largest_error_pos = curr->detail.index;
4534 msg = record->detail.error;
4538 gas_assert (largest_error_pos != -2 && record != NULL);
4539 DEBUG_TRACE ("Pick up error kind %s to report",
4540 operand_mismatch_kind_names[record->detail.kind]);
4543 output_operand_error_record (record, str);
4546 /* Write an AARCH64 instruction to buf - always little-endian. */
4548 put_aarch64_insn (char *buf, uint32_t insn)
4550 unsigned char *where = (unsigned char *) buf;
4552 where[1] = insn >> 8;
4553 where[2] = insn >> 16;
4554 where[3] = insn >> 24;
4558 get_aarch64_insn (char *buf)
4560 unsigned char *where = (unsigned char *) buf;
4562 result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
4567 output_inst (struct aarch64_inst *new_inst)
4571 to = frag_more (INSN_SIZE);
4573 frag_now->tc_frag_data.recorded = 1;
4575 put_aarch64_insn (to, inst.base.value);
4577 if (inst.reloc.type != BFD_RELOC_UNUSED)
4579 fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal,
4580 INSN_SIZE, &inst.reloc.exp,
4583 DEBUG_TRACE ("Prepared relocation fix up");
4584 /* Don't check the addend value against the instruction size,
4585 that's the job of our code in md_apply_fix(). */
4586 fixp->fx_no_overflow = 1;
4587 if (new_inst != NULL)
4588 fixp->tc_fix_data.inst = new_inst;
4589 if (aarch64_gas_internal_fixup_p ())
4591 gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL);
4592 fixp->tc_fix_data.opnd = inst.reloc.opnd;
4593 fixp->fx_addnumber = inst.reloc.flags;
4597 dwarf2_emit_insn (INSN_SIZE);
4600 /* Link together opcodes of the same name. */
4604 aarch64_opcode *opcode;
4605 struct templates *next;
4608 typedef struct templates templates;
4611 lookup_mnemonic (const char *start, int len)
4613 templates *templ = NULL;
4615 templ = hash_find_n (aarch64_ops_hsh, start, len);
4619 /* Subroutine of md_assemble, responsible for looking up the primary
4620 opcode from the mnemonic the user wrote. STR points to the
4621 beginning of the mnemonic. */
4624 opcode_lookup (char **str)
4627 const aarch64_cond *cond;
4631 /* Scan up to the end of the mnemonic, which must end in white space,
4632 '.', or end of string. */
4633 for (base = end = *str; is_part_of_name(*end); end++)
4640 inst.cond = COND_ALWAYS;
4642 /* Handle a possible condition. */
4645 cond = hash_find_n (aarch64_cond_hsh, end + 1, 2);
4648 inst.cond = cond->value;
4662 if (inst.cond == COND_ALWAYS)
4664 /* Look for unaffixed mnemonic. */
4665 return lookup_mnemonic (base, len);
4669 /* append ".c" to mnemonic if conditional */
4670 memcpy (condname, base, len);
4671 memcpy (condname + len, ".c", 2);
4674 return lookup_mnemonic (base, len);
4680 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4681 to a corresponding operand qualifier. */
4683 static inline aarch64_opnd_qualifier_t
4684 vectype_to_qualifier (const struct vector_type_el *vectype)
4686 /* Element size in bytes indexed by vector_el_type. */
4687 const unsigned char ele_size[5]
4689 const unsigned int ele_base [5] =
4691 AARCH64_OPND_QLF_V_8B,
4692 AARCH64_OPND_QLF_V_2H,
4693 AARCH64_OPND_QLF_V_2S,
4694 AARCH64_OPND_QLF_V_1D,
4695 AARCH64_OPND_QLF_V_1Q
4698 if (!vectype->defined || vectype->type == NT_invtype)
4699 goto vectype_conversion_fail;
4701 if (vectype->type == NT_zero)
4702 return AARCH64_OPND_QLF_P_Z;
4703 if (vectype->type == NT_merge)
4704 return AARCH64_OPND_QLF_P_M;
4706 gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
4708 if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
4709 /* Vector element register. */
4710 return AARCH64_OPND_QLF_S_B + vectype->type;
4713 /* Vector register. */
4714 int reg_size = ele_size[vectype->type] * vectype->width;
4717 if (reg_size != 16 && reg_size != 8 && reg_size != 4)
4718 goto vectype_conversion_fail;
4720 /* The conversion is by calculating the offset from the base operand
4721 qualifier for the vector type. The operand qualifiers are regular
4722 enough that the offset can established by shifting the vector width by
4723 a vector-type dependent amount. */
4725 if (vectype->type == NT_b)
4727 else if (vectype->type == NT_h || vectype->type == NT_s)
4729 else if (vectype->type >= NT_d)
4734 offset = ele_base [vectype->type] + (vectype->width >> shift);
4735 gas_assert (AARCH64_OPND_QLF_V_8B <= offset
4736 && offset <= AARCH64_OPND_QLF_V_1Q);
4740 vectype_conversion_fail:
4741 first_error (_("bad vector arrangement type"));
4742 return AARCH64_OPND_QLF_NIL;
4745 /* Process an optional operand that is found omitted from the assembly line.
4746 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4747 instruction's opcode entry while IDX is the index of this omitted operand.
4751 process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
4752 int idx, aarch64_opnd_info *operand)
4754 aarch64_insn default_value = get_optional_operand_default_value (opcode);
4755 gas_assert (optional_operand_p (opcode, idx));
4756 gas_assert (!operand->present);
4760 case AARCH64_OPND_Rd:
4761 case AARCH64_OPND_Rn:
4762 case AARCH64_OPND_Rm:
4763 case AARCH64_OPND_Rt:
4764 case AARCH64_OPND_Rt2:
4765 case AARCH64_OPND_Rs:
4766 case AARCH64_OPND_Ra:
4767 case AARCH64_OPND_Rt_SYS:
4768 case AARCH64_OPND_Rd_SP:
4769 case AARCH64_OPND_Rn_SP:
4770 case AARCH64_OPND_Fd:
4771 case AARCH64_OPND_Fn:
4772 case AARCH64_OPND_Fm:
4773 case AARCH64_OPND_Fa:
4774 case AARCH64_OPND_Ft:
4775 case AARCH64_OPND_Ft2:
4776 case AARCH64_OPND_Sd:
4777 case AARCH64_OPND_Sn:
4778 case AARCH64_OPND_Sm:
4779 case AARCH64_OPND_Vd:
4780 case AARCH64_OPND_Vn:
4781 case AARCH64_OPND_Vm:
4782 case AARCH64_OPND_VdD1:
4783 case AARCH64_OPND_VnD1:
4784 operand->reg.regno = default_value;
4787 case AARCH64_OPND_Ed:
4788 case AARCH64_OPND_En:
4789 case AARCH64_OPND_Em:
4790 operand->reglane.regno = default_value;
4793 case AARCH64_OPND_IDX:
4794 case AARCH64_OPND_BIT_NUM:
4795 case AARCH64_OPND_IMMR:
4796 case AARCH64_OPND_IMMS:
4797 case AARCH64_OPND_SHLL_IMM:
4798 case AARCH64_OPND_IMM_VLSL:
4799 case AARCH64_OPND_IMM_VLSR:
4800 case AARCH64_OPND_CCMP_IMM:
4801 case AARCH64_OPND_FBITS:
4802 case AARCH64_OPND_UIMM4:
4803 case AARCH64_OPND_UIMM3_OP1:
4804 case AARCH64_OPND_UIMM3_OP2:
4805 case AARCH64_OPND_IMM:
4806 case AARCH64_OPND_WIDTH:
4807 case AARCH64_OPND_UIMM7:
4808 case AARCH64_OPND_NZCV:
4809 operand->imm.value = default_value;
4812 case AARCH64_OPND_EXCEPTION:
4813 inst.reloc.type = BFD_RELOC_UNUSED;
4816 case AARCH64_OPND_BARRIER_ISB:
4817 operand->barrier = aarch64_barrier_options + default_value;
4824 /* Process the relocation type for move wide instructions.
4825 Return TRUE on success; otherwise return FALSE. */
4828 process_movw_reloc_info (void)
4833 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
4835 if (inst.base.opcode->op == OP_MOVK)
4836 switch (inst.reloc.type)
4838 case BFD_RELOC_AARCH64_MOVW_G0_S:
4839 case BFD_RELOC_AARCH64_MOVW_G1_S:
4840 case BFD_RELOC_AARCH64_MOVW_G2_S:
4841 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
4842 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4843 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4844 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4846 (_("the specified relocation type is not allowed for MOVK"));
4852 switch (inst.reloc.type)
4854 case BFD_RELOC_AARCH64_MOVW_G0:
4855 case BFD_RELOC_AARCH64_MOVW_G0_NC:
4856 case BFD_RELOC_AARCH64_MOVW_G0_S:
4857 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
4858 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
4859 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
4860 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
4861 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
4862 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
4863 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4864 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4867 case BFD_RELOC_AARCH64_MOVW_G1:
4868 case BFD_RELOC_AARCH64_MOVW_G1_NC:
4869 case BFD_RELOC_AARCH64_MOVW_G1_S:
4870 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
4871 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
4872 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
4873 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
4874 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
4875 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
4876 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4877 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4880 case BFD_RELOC_AARCH64_MOVW_G2:
4881 case BFD_RELOC_AARCH64_MOVW_G2_NC:
4882 case BFD_RELOC_AARCH64_MOVW_G2_S:
4883 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
4884 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4887 set_fatal_syntax_error
4888 (_("the specified relocation type is not allowed for 32-bit "
4894 case BFD_RELOC_AARCH64_MOVW_G3:
4897 set_fatal_syntax_error
4898 (_("the specified relocation type is not allowed for 32-bit "
4905 /* More cases should be added when more MOVW-related relocation types
4906 are supported in GAS. */
4907 gas_assert (aarch64_gas_internal_fixup_p ());
4908 /* The shift amount should have already been set by the parser. */
4911 inst.base.operands[1].shifter.amount = shift;
4915 /* A primitive log caculator. */
4917 static inline unsigned int
4918 get_logsz (unsigned int size)
4920 const unsigned char ls[16] =
4921 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4927 gas_assert (ls[size - 1] != (unsigned char)-1);
4928 return ls[size - 1];
4931 /* Determine and return the real reloc type code for an instruction
4932 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4934 static inline bfd_reloc_code_real_type
4935 ldst_lo12_determine_real_reloc_type (void)
4938 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
4939 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
4941 const bfd_reloc_code_real_type reloc_ldst_lo12[3][5] = {
4943 BFD_RELOC_AARCH64_LDST8_LO12,
4944 BFD_RELOC_AARCH64_LDST16_LO12,
4945 BFD_RELOC_AARCH64_LDST32_LO12,
4946 BFD_RELOC_AARCH64_LDST64_LO12,
4947 BFD_RELOC_AARCH64_LDST128_LO12
4950 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12,
4951 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12,
4952 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12,
4953 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12,
4954 BFD_RELOC_AARCH64_NONE
4957 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC,
4958 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC,
4959 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
4960 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
4961 BFD_RELOC_AARCH64_NONE
4965 gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
4966 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4968 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC));
4969 gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
4971 if (opd1_qlf == AARCH64_OPND_QLF_NIL)
4973 aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list,
4975 gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
4977 logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
4978 if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4979 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
4980 gas_assert (logsz <= 3);
4982 gas_assert (logsz <= 4);
4984 /* In reloc.c, these pseudo relocation types should be defined in similar
4985 order as above reloc_ldst_lo12 array. Because the array index calcuation
4986 below relies on this. */
4987 return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
4990 /* Check whether a register list REGINFO is valid. The registers must be
4991 numbered in increasing order (modulo 32), in increments of one or two.
4993 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4996 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4999 reg_list_valid_p (uint32_t reginfo, int accept_alternate)
5001 uint32_t i, nb_regs, prev_regno, incr;
5003 nb_regs = 1 + (reginfo & 0x3);
5005 prev_regno = reginfo & 0x1f;
5006 incr = accept_alternate ? 2 : 1;
5008 for (i = 1; i < nb_regs; ++i)
5010 uint32_t curr_regno;
5012 curr_regno = reginfo & 0x1f;
5013 if (curr_regno != ((prev_regno + incr) & 0x1f))
5015 prev_regno = curr_regno;
5021 /* Generic instruction operand parser. This does no encoding and no
5022 semantic validation; it merely squirrels values away in the inst
5023 structure. Returns TRUE or FALSE depending on whether the
5024 specified grammar matched. */
5027 parse_operands (char *str, const aarch64_opcode *opcode)
5030 char *backtrack_pos = 0;
5031 const enum aarch64_opnd *operands = opcode->operands;
5032 aarch64_reg_type imm_reg_type;
5035 skip_whitespace (str);
5037 imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
5039 for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
5042 const reg_entry *reg;
5043 int comma_skipped_p = 0;
5044 aarch64_reg_type rtype;
5045 struct vector_type_el vectype;
5046 aarch64_opnd_qualifier_t qualifier;
5047 aarch64_opnd_info *info = &inst.base.operands[i];
5048 aarch64_reg_type reg_type;
5050 DEBUG_TRACE ("parse operand %d", i);
5052 /* Assign the operand code. */
5053 info->type = operands[i];
5055 if (optional_operand_p (opcode, i))
5057 /* Remember where we are in case we need to backtrack. */
5058 gas_assert (!backtrack_pos);
5059 backtrack_pos = str;
5062 /* Expect comma between operands; the backtrack mechanizm will take
5063 care of cases of omitted optional operand. */
5064 if (i > 0 && ! skip_past_char (&str, ','))
5066 set_syntax_error (_("comma expected between operands"));
5070 comma_skipped_p = 1;
5072 switch (operands[i])
5074 case AARCH64_OPND_Rd:
5075 case AARCH64_OPND_Rn:
5076 case AARCH64_OPND_Rm:
5077 case AARCH64_OPND_Rt:
5078 case AARCH64_OPND_Rt2:
5079 case AARCH64_OPND_Rs:
5080 case AARCH64_OPND_Ra:
5081 case AARCH64_OPND_Rt_SYS:
5082 case AARCH64_OPND_PAIRREG:
5083 po_int_reg_or_fail (REG_TYPE_R_Z);
5086 case AARCH64_OPND_Rd_SP:
5087 case AARCH64_OPND_Rn_SP:
5088 po_int_reg_or_fail (REG_TYPE_R_SP);
5091 case AARCH64_OPND_Rm_EXT:
5092 case AARCH64_OPND_Rm_SFT:
5093 po_misc_or_fail (parse_shifter_operand
5094 (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT
5096 : SHIFTED_LOGIC_IMM)));
5097 if (!info->shifter.operator_present)
5099 /* Default to LSL if not present. Libopcodes prefers shifter
5100 kind to be explicit. */
5101 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5102 info->shifter.kind = AARCH64_MOD_LSL;
5103 /* For Rm_EXT, libopcodes will carry out further check on whether
5104 or not stack pointer is used in the instruction (Recall that
5105 "the extend operator is not optional unless at least one of
5106 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5110 case AARCH64_OPND_Fd:
5111 case AARCH64_OPND_Fn:
5112 case AARCH64_OPND_Fm:
5113 case AARCH64_OPND_Fa:
5114 case AARCH64_OPND_Ft:
5115 case AARCH64_OPND_Ft2:
5116 case AARCH64_OPND_Sd:
5117 case AARCH64_OPND_Sn:
5118 case AARCH64_OPND_Sm:
5119 val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
5120 if (val == PARSE_FAIL)
5122 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
5125 gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
5127 info->reg.regno = val;
5128 info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
5131 case AARCH64_OPND_SVE_Pd:
5132 case AARCH64_OPND_SVE_Pg3:
5133 case AARCH64_OPND_SVE_Pg4_5:
5134 case AARCH64_OPND_SVE_Pg4_10:
5135 case AARCH64_OPND_SVE_Pg4_16:
5136 case AARCH64_OPND_SVE_Pm:
5137 case AARCH64_OPND_SVE_Pn:
5138 case AARCH64_OPND_SVE_Pt:
5139 reg_type = REG_TYPE_PN;
5142 case AARCH64_OPND_SVE_Za_5:
5143 case AARCH64_OPND_SVE_Za_16:
5144 case AARCH64_OPND_SVE_Zd:
5145 case AARCH64_OPND_SVE_Zm_5:
5146 case AARCH64_OPND_SVE_Zm_16:
5147 case AARCH64_OPND_SVE_Zn:
5148 case AARCH64_OPND_SVE_Zt:
5149 reg_type = REG_TYPE_ZN;
5152 case AARCH64_OPND_Vd:
5153 case AARCH64_OPND_Vn:
5154 case AARCH64_OPND_Vm:
5155 reg_type = REG_TYPE_VN;
5157 val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
5158 if (val == PARSE_FAIL)
5160 first_error (_(get_reg_expected_msg (reg_type)));
5163 if (vectype.defined & NTA_HASINDEX)
5166 info->reg.regno = val;
5167 if ((reg_type == REG_TYPE_PN || reg_type == REG_TYPE_ZN)
5168 && vectype.type == NT_invtype)
5169 /* Unqualified Pn and Zn registers are allowed in certain
5170 contexts. Rely on F_STRICT qualifier checking to catch
5172 info->qualifier = AARCH64_OPND_QLF_NIL;
5175 info->qualifier = vectype_to_qualifier (&vectype);
5176 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5181 case AARCH64_OPND_VdD1:
5182 case AARCH64_OPND_VnD1:
5183 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
5184 if (val == PARSE_FAIL)
5186 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
5189 if (vectype.type != NT_d || vectype.index != 1)
5191 set_fatal_syntax_error
5192 (_("the top half of a 128-bit FP/SIMD register is expected"));
5195 info->reg.regno = val;
5196 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5197 here; it is correct for the purpose of encoding/decoding since
5198 only the register number is explicitly encoded in the related
5199 instructions, although this appears a bit hacky. */
5200 info->qualifier = AARCH64_OPND_QLF_S_D;
5203 case AARCH64_OPND_SVE_Zn_INDEX:
5204 reg_type = REG_TYPE_ZN;
5205 goto vector_reg_index;
5207 case AARCH64_OPND_Ed:
5208 case AARCH64_OPND_En:
5209 case AARCH64_OPND_Em:
5210 reg_type = REG_TYPE_VN;
5212 val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
5213 if (val == PARSE_FAIL)
5215 first_error (_(get_reg_expected_msg (reg_type)));
5218 if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
5221 info->reglane.regno = val;
5222 info->reglane.index = vectype.index;
5223 info->qualifier = vectype_to_qualifier (&vectype);
5224 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5228 case AARCH64_OPND_SVE_ZnxN:
5229 case AARCH64_OPND_SVE_ZtxN:
5230 reg_type = REG_TYPE_ZN;
5231 goto vector_reg_list;
5233 case AARCH64_OPND_LVn:
5234 case AARCH64_OPND_LVt:
5235 case AARCH64_OPND_LVt_AL:
5236 case AARCH64_OPND_LEt:
5237 reg_type = REG_TYPE_VN;
5239 if (reg_type == REG_TYPE_ZN
5240 && get_opcode_dependent_value (opcode) == 1
5243 val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
5244 if (val == PARSE_FAIL)
5246 first_error (_(get_reg_expected_msg (reg_type)));
5249 info->reglist.first_regno = val;
5250 info->reglist.num_regs = 1;
5254 val = parse_vector_reg_list (&str, reg_type, &vectype);
5255 if (val == PARSE_FAIL)
5257 if (! reg_list_valid_p (val, /* accept_alternate */ 0))
5259 set_fatal_syntax_error (_("invalid register list"));
5262 info->reglist.first_regno = (val >> 2) & 0x1f;
5263 info->reglist.num_regs = (val & 0x3) + 1;
5265 if (operands[i] == AARCH64_OPND_LEt)
5267 if (!(vectype.defined & NTA_HASINDEX))
5269 info->reglist.has_index = 1;
5270 info->reglist.index = vectype.index;
5274 if (vectype.defined & NTA_HASINDEX)
5276 if (!(vectype.defined & NTA_HASTYPE))
5278 if (reg_type == REG_TYPE_ZN)
5279 set_fatal_syntax_error (_("missing type suffix"));
5283 info->qualifier = vectype_to_qualifier (&vectype);
5284 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5288 case AARCH64_OPND_Cn:
5289 case AARCH64_OPND_Cm:
5290 po_reg_or_fail (REG_TYPE_CN);
5293 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN)));
5296 inst.base.operands[i].reg.regno = val;
5299 case AARCH64_OPND_SHLL_IMM:
5300 case AARCH64_OPND_IMM_VLSR:
5301 po_imm_or_fail (1, 64);
5302 info->imm.value = val;
5305 case AARCH64_OPND_CCMP_IMM:
5306 case AARCH64_OPND_FBITS:
5307 case AARCH64_OPND_UIMM4:
5308 case AARCH64_OPND_UIMM3_OP1:
5309 case AARCH64_OPND_UIMM3_OP2:
5310 case AARCH64_OPND_IMM_VLSL:
5311 case AARCH64_OPND_IMM:
5312 case AARCH64_OPND_WIDTH:
5313 po_imm_nc_or_fail ();
5314 info->imm.value = val;
5317 case AARCH64_OPND_UIMM7:
5318 po_imm_or_fail (0, 127);
5319 info->imm.value = val;
5322 case AARCH64_OPND_IDX:
5323 case AARCH64_OPND_BIT_NUM:
5324 case AARCH64_OPND_IMMR:
5325 case AARCH64_OPND_IMMS:
5326 po_imm_or_fail (0, 63);
5327 info->imm.value = val;
5330 case AARCH64_OPND_IMM0:
5331 po_imm_nc_or_fail ();
5334 set_fatal_syntax_error (_("immediate zero expected"));
5337 info->imm.value = 0;
5340 case AARCH64_OPND_FPIMM0:
5343 bfd_boolean res1 = FALSE, res2 = FALSE;
5344 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5345 it is probably not worth the effort to support it. */
5346 if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE,
5349 || !(res2 = parse_constant_immediate (&str, &val,
5352 if ((res1 && qfloat == 0) || (res2 && val == 0))
5354 info->imm.value = 0;
5355 info->imm.is_fp = 1;
5358 set_fatal_syntax_error (_("immediate zero expected"));
5362 case AARCH64_OPND_IMM_MOV:
5365 if (reg_name_p (str, REG_TYPE_R_Z_SP) ||
5366 reg_name_p (str, REG_TYPE_VN))
5369 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5371 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5372 later. fix_mov_imm_insn will try to determine a machine
5373 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5374 message if the immediate cannot be moved by a single
5376 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5377 inst.base.operands[i].skip = 1;
5381 case AARCH64_OPND_SIMD_IMM:
5382 case AARCH64_OPND_SIMD_IMM_SFT:
5383 if (! parse_big_immediate (&str, &val, imm_reg_type))
5385 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5387 /* need_libopcodes_p */ 1,
5390 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5391 shift, we don't check it here; we leave the checking to
5392 the libopcodes (operand_general_constraint_met_p). By
5393 doing this, we achieve better diagnostics. */
5394 if (skip_past_comma (&str)
5395 && ! parse_shift (&str, info, SHIFTED_LSL_MSL))
5397 if (!info->shifter.operator_present
5398 && info->type == AARCH64_OPND_SIMD_IMM_SFT)
5400 /* Default to LSL if not present. Libopcodes prefers shifter
5401 kind to be explicit. */
5402 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5403 info->shifter.kind = AARCH64_MOD_LSL;
5407 case AARCH64_OPND_FPIMM:
5408 case AARCH64_OPND_SIMD_FPIMM:
5412 = (aarch64_get_qualifier_esize (inst.base.operands[0].qualifier)
5414 if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type)
5415 || !aarch64_imm_float_p (qfloat))
5418 set_fatal_syntax_error (_("invalid floating-point"
5422 inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat);
5423 inst.base.operands[i].imm.is_fp = 1;
5427 case AARCH64_OPND_LIMM:
5428 po_misc_or_fail (parse_shifter_operand (&str, info,
5429 SHIFTED_LOGIC_IMM));
5430 if (info->shifter.operator_present)
5432 set_fatal_syntax_error
5433 (_("shift not allowed for bitmask immediate"));
5436 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5438 /* need_libopcodes_p */ 1,
5442 case AARCH64_OPND_AIMM:
5443 if (opcode->op == OP_ADD)
5444 /* ADD may have relocation types. */
5445 po_misc_or_fail (parse_shifter_operand_reloc (&str, info,
5446 SHIFTED_ARITH_IMM));
5448 po_misc_or_fail (parse_shifter_operand (&str, info,
5449 SHIFTED_ARITH_IMM));
5450 switch (inst.reloc.type)
5452 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
5453 info->shifter.amount = 12;
5455 case BFD_RELOC_UNUSED:
5456 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
5457 if (info->shifter.kind != AARCH64_MOD_NONE)
5458 inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT;
5459 inst.reloc.pc_rel = 0;
5464 info->imm.value = 0;
5465 if (!info->shifter.operator_present)
5467 /* Default to LSL if not present. Libopcodes prefers shifter
5468 kind to be explicit. */
5469 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5470 info->shifter.kind = AARCH64_MOD_LSL;
5474 case AARCH64_OPND_HALF:
5476 /* #<imm16> or relocation. */
5477 int internal_fixup_p;
5478 po_misc_or_fail (parse_half (&str, &internal_fixup_p));
5479 if (internal_fixup_p)
5480 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
5481 skip_whitespace (str);
5482 if (skip_past_comma (&str))
5484 /* {, LSL #<shift>} */
5485 if (! aarch64_gas_internal_fixup_p ())
5487 set_fatal_syntax_error (_("can't mix relocation modifier "
5488 "with explicit shift"));
5491 po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
5494 inst.base.operands[i].shifter.amount = 0;
5495 inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
5496 inst.base.operands[i].imm.value = 0;
5497 if (! process_movw_reloc_info ())
5502 case AARCH64_OPND_EXCEPTION:
5503 po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp,
5505 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5507 /* need_libopcodes_p */ 0,
5511 case AARCH64_OPND_NZCV:
5513 const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4);
5517 info->imm.value = nzcv->value;
5520 po_imm_or_fail (0, 15);
5521 info->imm.value = val;
5525 case AARCH64_OPND_COND:
5526 case AARCH64_OPND_COND1:
5527 info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
5529 if (info->cond == NULL)
5531 set_syntax_error (_("invalid condition"));
5534 else if (operands[i] == AARCH64_OPND_COND1
5535 && (info->cond->value & 0xe) == 0xe)
5537 /* Not allow AL or NV. */
5538 set_default_error ();
5543 case AARCH64_OPND_ADDR_ADRP:
5544 po_misc_or_fail (parse_adrp (&str));
5545 /* Clear the value as operand needs to be relocated. */
5546 info->imm.value = 0;
5549 case AARCH64_OPND_ADDR_PCREL14:
5550 case AARCH64_OPND_ADDR_PCREL19:
5551 case AARCH64_OPND_ADDR_PCREL21:
5552 case AARCH64_OPND_ADDR_PCREL26:
5553 po_misc_or_fail (parse_address (&str, info));
5554 if (!info->addr.pcrel)
5556 set_syntax_error (_("invalid pc-relative address"));
5559 if (inst.gen_lit_pool
5560 && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT))
5562 /* Only permit "=value" in the literal load instructions.
5563 The literal will be generated by programmer_friendly_fixup. */
5564 set_syntax_error (_("invalid use of \"=immediate\""));
5567 if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str))
5569 set_syntax_error (_("unrecognized relocation suffix"));
5572 if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
5574 info->imm.value = inst.reloc.exp.X_add_number;
5575 inst.reloc.type = BFD_RELOC_UNUSED;
5579 info->imm.value = 0;
5580 if (inst.reloc.type == BFD_RELOC_UNUSED)
5581 switch (opcode->iclass)
5585 /* e.g. CBZ or B.COND */
5586 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5587 inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
5591 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
5592 inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
5596 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
5598 (opcode->op == OP_BL) ? BFD_RELOC_AARCH64_CALL26
5599 : BFD_RELOC_AARCH64_JUMP26;
5602 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5603 inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
5606 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
5607 inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
5613 inst.reloc.pc_rel = 1;
5617 case AARCH64_OPND_ADDR_SIMPLE:
5618 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
5620 /* [<Xn|SP>{, #<simm>}] */
5622 /* First use the normal address-parsing routines, to get
5623 the usual syntax errors. */
5624 po_misc_or_fail (parse_address (&str, info));
5625 if (info->addr.pcrel || info->addr.offset.is_reg
5626 || !info->addr.preind || info->addr.postind
5627 || info->addr.writeback)
5629 set_syntax_error (_("invalid addressing mode"));
5633 /* Then retry, matching the specific syntax of these addresses. */
5635 po_char_or_fail ('[');
5636 po_reg_or_fail (REG_TYPE_R64_SP);
5637 /* Accept optional ", #0". */
5638 if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
5639 && skip_past_char (&str, ','))
5641 skip_past_char (&str, '#');
5642 if (! skip_past_char (&str, '0'))
5644 set_fatal_syntax_error
5645 (_("the optional immediate offset can only be 0"));
5649 po_char_or_fail (']');
5653 case AARCH64_OPND_ADDR_REGOFF:
5654 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5655 po_misc_or_fail (parse_address (&str, info));
5656 if (info->addr.pcrel || !info->addr.offset.is_reg
5657 || !info->addr.preind || info->addr.postind
5658 || info->addr.writeback)
5660 set_syntax_error (_("invalid addressing mode"));
5663 if (!info->shifter.operator_present)
5665 /* Default to LSL if not present. Libopcodes prefers shifter
5666 kind to be explicit. */
5667 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5668 info->shifter.kind = AARCH64_MOD_LSL;
5670 /* Qualifier to be deduced by libopcodes. */
5673 case AARCH64_OPND_ADDR_SIMM7:
5674 po_misc_or_fail (parse_address (&str, info));
5675 if (info->addr.pcrel || info->addr.offset.is_reg
5676 || (!info->addr.preind && !info->addr.postind))
5678 set_syntax_error (_("invalid addressing mode"));
5681 if (inst.reloc.type != BFD_RELOC_UNUSED)
5683 set_syntax_error (_("relocation not allowed"));
5686 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5688 /* need_libopcodes_p */ 1,
5692 case AARCH64_OPND_ADDR_SIMM9:
5693 case AARCH64_OPND_ADDR_SIMM9_2:
5694 po_misc_or_fail (parse_address (&str, info));
5695 if (info->addr.pcrel || info->addr.offset.is_reg
5696 || (!info->addr.preind && !info->addr.postind)
5697 || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
5698 && info->addr.writeback))
5700 set_syntax_error (_("invalid addressing mode"));
5703 if (inst.reloc.type != BFD_RELOC_UNUSED)
5705 set_syntax_error (_("relocation not allowed"));
5708 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5710 /* need_libopcodes_p */ 1,
5714 case AARCH64_OPND_ADDR_UIMM12:
5715 po_misc_or_fail (parse_address (&str, info));
5716 if (info->addr.pcrel || info->addr.offset.is_reg
5717 || !info->addr.preind || info->addr.writeback)
5719 set_syntax_error (_("invalid addressing mode"));
5722 if (inst.reloc.type == BFD_RELOC_UNUSED)
5723 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5724 else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
5726 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12)
5728 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC))
5729 inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
5730 /* Leave qualifier to be determined by libopcodes. */
5733 case AARCH64_OPND_SIMD_ADDR_POST:
5734 /* [<Xn|SP>], <Xm|#<amount>> */
5735 po_misc_or_fail (parse_address (&str, info));
5736 if (!info->addr.postind || !info->addr.writeback)
5738 set_syntax_error (_("invalid addressing mode"));
5741 if (!info->addr.offset.is_reg)
5743 if (inst.reloc.exp.X_op == O_constant)
5744 info->addr.offset.imm = inst.reloc.exp.X_add_number;
5747 set_fatal_syntax_error
5748 (_("writeback value should be an immediate constant"));
5755 case AARCH64_OPND_SYSREG:
5756 if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0))
5759 set_syntax_error (_("unknown or missing system register name"));
5762 inst.base.operands[i].sysreg = val;
5765 case AARCH64_OPND_PSTATEFIELD:
5766 if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1))
5769 set_syntax_error (_("unknown or missing PSTATE field name"));
5772 inst.base.operands[i].pstatefield = val;
5775 case AARCH64_OPND_SYSREG_IC:
5776 inst.base.operands[i].sysins_op =
5777 parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
5779 case AARCH64_OPND_SYSREG_DC:
5780 inst.base.operands[i].sysins_op =
5781 parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
5783 case AARCH64_OPND_SYSREG_AT:
5784 inst.base.operands[i].sysins_op =
5785 parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
5787 case AARCH64_OPND_SYSREG_TLBI:
5788 inst.base.operands[i].sysins_op =
5789 parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
5791 if (inst.base.operands[i].sysins_op == NULL)
5793 set_fatal_syntax_error ( _("unknown or missing operation name"));
5798 case AARCH64_OPND_BARRIER:
5799 case AARCH64_OPND_BARRIER_ISB:
5800 val = parse_barrier (&str);
5801 if (val != PARSE_FAIL
5802 && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf)
5804 /* ISB only accepts options name 'sy'. */
5806 (_("the specified option is not accepted in ISB"));
5807 /* Turn off backtrack as this optional operand is present. */
5811 /* This is an extension to accept a 0..15 immediate. */
5812 if (val == PARSE_FAIL)
5813 po_imm_or_fail (0, 15);
5814 info->barrier = aarch64_barrier_options + val;
5817 case AARCH64_OPND_PRFOP:
5818 val = parse_pldop (&str);
5819 /* This is an extension to accept a 0..31 immediate. */
5820 if (val == PARSE_FAIL)
5821 po_imm_or_fail (0, 31);
5822 inst.base.operands[i].prfop = aarch64_prfops + val;
5825 case AARCH64_OPND_BARRIER_PSB:
5826 val = parse_barrier_psb (&str, &(info->hint_option));
5827 if (val == PARSE_FAIL)
5832 as_fatal (_("unhandled operand code %d"), operands[i]);
5835 /* If we get here, this operand was successfully parsed. */
5836 inst.base.operands[i].present = 1;
5840 /* The parse routine should already have set the error, but in case
5841 not, set a default one here. */
5843 set_default_error ();
5845 if (! backtrack_pos)
5846 goto parse_operands_return;
5849 /* We reach here because this operand is marked as optional, and
5850 either no operand was supplied or the operand was supplied but it
5851 was syntactically incorrect. In the latter case we report an
5852 error. In the former case we perform a few more checks before
5853 dropping through to the code to insert the default operand. */
5855 char *tmp = backtrack_pos;
5856 char endchar = END_OF_INSN;
5858 if (i != (aarch64_num_of_operands (opcode) - 1))
5860 skip_past_char (&tmp, ',');
5862 if (*tmp != endchar)
5863 /* The user has supplied an operand in the wrong format. */
5864 goto parse_operands_return;
5866 /* Make sure there is not a comma before the optional operand.
5867 For example the fifth operand of 'sys' is optional:
5869 sys #0,c0,c0,#0, <--- wrong
5870 sys #0,c0,c0,#0 <--- correct. */
5871 if (comma_skipped_p && i && endchar == END_OF_INSN)
5873 set_fatal_syntax_error
5874 (_("unexpected comma before the omitted optional operand"));
5875 goto parse_operands_return;
5879 /* Reaching here means we are dealing with an optional operand that is
5880 omitted from the assembly line. */
5881 gas_assert (optional_operand_p (opcode, i));
5883 process_omitted_operand (operands[i], opcode, i, info);
5885 /* Try again, skipping the optional operand at backtrack_pos. */
5886 str = backtrack_pos;
5889 /* Clear any error record after the omitted optional operand has been
5890 successfully handled. */
5894 /* Check if we have parsed all the operands. */
5895 if (*str != '\0' && ! error_p ())
5897 /* Set I to the index of the last present operand; this is
5898 for the purpose of diagnostics. */
5899 for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i)
5901 set_fatal_syntax_error
5902 (_("unexpected characters following instruction"));
5905 parse_operands_return:
5909 DEBUG_TRACE ("parsing FAIL: %s - %s",
5910 operand_mismatch_kind_names[get_error_kind ()],
5911 get_error_message ());
5912 /* Record the operand error properly; this is useful when there
5913 are multiple instruction templates for a mnemonic name, so that
5914 later on, we can select the error that most closely describes
5916 record_operand_error (opcode, i, get_error_kind (),
5917 get_error_message ());
5922 DEBUG_TRACE ("parsing SUCCESS");
5927 /* It does some fix-up to provide some programmer friendly feature while
5928 keeping the libopcodes happy, i.e. libopcodes only accepts
5929 the preferred architectural syntax.
5930 Return FALSE if there is any failure; otherwise return TRUE. */
5933 programmer_friendly_fixup (aarch64_instruction *instr)
5935 aarch64_inst *base = &instr->base;
5936 const aarch64_opcode *opcode = base->opcode;
5937 enum aarch64_op op = opcode->op;
5938 aarch64_opnd_info *operands = base->operands;
5940 DEBUG_TRACE ("enter");
5942 switch (opcode->iclass)
5945 /* TBNZ Xn|Wn, #uimm6, label
5946 Test and Branch Not Zero: conditionally jumps to label if bit number
5947 uimm6 in register Xn is not zero. The bit number implies the width of
5948 the register, which may be written and should be disassembled as Wn if
5949 uimm is less than 32. */
5950 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
5952 if (operands[1].imm.value >= 32)
5954 record_operand_out_of_range_error (opcode, 1, _("immediate value"),
5958 operands[0].qualifier = AARCH64_OPND_QLF_X;
5962 /* LDR Wt, label | =value
5963 As a convenience assemblers will typically permit the notation
5964 "=value" in conjunction with the pc-relative literal load instructions
5965 to automatically place an immediate value or symbolic address in a
5966 nearby literal pool and generate a hidden label which references it.
5967 ISREG has been set to 0 in the case of =value. */
5968 if (instr->gen_lit_pool
5969 && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT))
5971 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
5972 if (op == OP_LDRSW_LIT)
5974 if (instr->reloc.exp.X_op != O_constant
5975 && instr->reloc.exp.X_op != O_big
5976 && instr->reloc.exp.X_op != O_symbol)
5978 record_operand_error (opcode, 1,
5979 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
5980 _("constant expression expected"));
5983 if (! add_to_lit_pool (&instr->reloc.exp, size))
5985 record_operand_error (opcode, 1,
5986 AARCH64_OPDE_OTHER_ERROR,
5987 _("literal pool insertion failed"));
5995 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5996 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5997 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5998 A programmer-friendly assembler should accept a destination Xd in
5999 place of Wd, however that is not the preferred form for disassembly.
6001 if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW)
6002 && operands[1].qualifier == AARCH64_OPND_QLF_W
6003 && operands[0].qualifier == AARCH64_OPND_QLF_X)
6004 operands[0].qualifier = AARCH64_OPND_QLF_W;
6009 /* In the 64-bit form, the final register operand is written as Wm
6010 for all but the (possibly omitted) UXTX/LSL and SXTX
6012 As a programmer-friendly assembler, we accept e.g.
6013 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6014 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6015 int idx = aarch64_operand_index (opcode->operands,
6016 AARCH64_OPND_Rm_EXT);
6017 gas_assert (idx == 1 || idx == 2);
6018 if (operands[0].qualifier == AARCH64_OPND_QLF_X
6019 && operands[idx].qualifier == AARCH64_OPND_QLF_X
6020 && operands[idx].shifter.kind != AARCH64_MOD_LSL
6021 && operands[idx].shifter.kind != AARCH64_MOD_UXTX
6022 && operands[idx].shifter.kind != AARCH64_MOD_SXTX)
6023 operands[idx].qualifier = AARCH64_OPND_QLF_W;
6031 DEBUG_TRACE ("exit with SUCCESS");
6035 /* Check for loads and stores that will cause unpredictable behavior. */
6038 warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
6040 aarch64_inst *base = &instr->base;
6041 const aarch64_opcode *opcode = base->opcode;
6042 const aarch64_opnd_info *opnds = base->operands;
6043 switch (opcode->iclass)
6049 /* Loading/storing the base register is unpredictable if writeback. */
6050 if ((aarch64_get_operand_class (opnds[0].type)
6051 == AARCH64_OPND_CLASS_INT_REG)
6052 && opnds[0].reg.regno == opnds[1].addr.base_regno
6053 && opnds[1].addr.base_regno != REG_SP
6054 && opnds[1].addr.writeback)
6055 as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
6058 case ldstnapair_offs:
6059 case ldstpair_indexed:
6060 /* Loading/storing the base register is unpredictable if writeback. */
6061 if ((aarch64_get_operand_class (opnds[0].type)
6062 == AARCH64_OPND_CLASS_INT_REG)
6063 && (opnds[0].reg.regno == opnds[2].addr.base_regno
6064 || opnds[1].reg.regno == opnds[2].addr.base_regno)
6065 && opnds[2].addr.base_regno != REG_SP
6066 && opnds[2].addr.writeback)
6067 as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
6068 /* Load operations must load different registers. */
6069 if ((opcode->opcode & (1 << 22))
6070 && opnds[0].reg.regno == opnds[1].reg.regno)
6071 as_warn (_("unpredictable load of register pair -- `%s'"), str);
6078 /* A wrapper function to interface with libopcodes on encoding and
6079 record the error message if there is any.
6081 Return TRUE on success; otherwise return FALSE. */
6084 do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
6087 aarch64_operand_error error_info;
6088 error_info.kind = AARCH64_OPDE_NIL;
6089 if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
6093 gas_assert (error_info.kind != AARCH64_OPDE_NIL);
6094 record_operand_error_info (opcode, &error_info);
6099 #ifdef DEBUG_AARCH64
6101 dump_opcode_operands (const aarch64_opcode *opcode)
6104 while (opcode->operands[i] != AARCH64_OPND_NIL)
6106 aarch64_verbose ("\t\t opnd%d: %s", i,
6107 aarch64_get_operand_name (opcode->operands[i])[0] != '\0'
6108 ? aarch64_get_operand_name (opcode->operands[i])
6109 : aarch64_get_operand_desc (opcode->operands[i]));
6113 #endif /* DEBUG_AARCH64 */
6115 /* This is the guts of the machine-dependent assembler. STR points to a
6116 machine dependent instruction. This function is supposed to emit
6117 the frags/bytes it assembles to. */
6120 md_assemble (char *str)
6123 templates *template;
6124 aarch64_opcode *opcode;
6125 aarch64_inst *inst_base;
6126 unsigned saved_cond;
6128 /* Align the previous label if needed. */
6129 if (last_label_seen != NULL)
6131 symbol_set_frag (last_label_seen, frag_now);
6132 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6133 S_SET_SEGMENT (last_label_seen, now_seg);
6136 inst.reloc.type = BFD_RELOC_UNUSED;
6138 DEBUG_TRACE ("\n\n");
6139 DEBUG_TRACE ("==============================");
6140 DEBUG_TRACE ("Enter md_assemble with %s", str);
6142 template = opcode_lookup (&p);
6145 /* It wasn't an instruction, but it might be a register alias of
6146 the form alias .req reg directive. */
6147 if (!create_register_alias (str, p))
6148 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
6153 skip_whitespace (p);
6156 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6157 get_mnemonic_name (str), str);
6161 init_operand_error_report ();
6163 /* Sections are assumed to start aligned. In executable section, there is no
6164 MAP_DATA symbol pending. So we only align the address during
6165 MAP_DATA --> MAP_INSN transition.
6166 For other sections, this is not guaranteed. */
6167 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
6168 if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA)
6169 frag_align_code (2, 0);
6171 saved_cond = inst.cond;
6172 reset_aarch64_instruction (&inst);
6173 inst.cond = saved_cond;
6175 /* Iterate through all opcode entries with the same mnemonic name. */
6178 opcode = template->opcode;
6180 DEBUG_TRACE ("opcode %s found", opcode->name);
6181 #ifdef DEBUG_AARCH64
6183 dump_opcode_operands (opcode);
6184 #endif /* DEBUG_AARCH64 */
6186 mapping_state (MAP_INSN);
6188 inst_base = &inst.base;
6189 inst_base->opcode = opcode;
6191 /* Truly conditionally executed instructions, e.g. b.cond. */
6192 if (opcode->flags & F_COND)
6194 gas_assert (inst.cond != COND_ALWAYS);
6195 inst_base->cond = get_cond_from_value (inst.cond);
6196 DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]);
6198 else if (inst.cond != COND_ALWAYS)
6200 /* It shouldn't arrive here, where the assembly looks like a
6201 conditional instruction but the found opcode is unconditional. */
6206 if (parse_operands (p, opcode)
6207 && programmer_friendly_fixup (&inst)
6208 && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
6210 /* Check that this instruction is supported for this CPU. */
6211 if (!opcode->avariant
6212 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant))
6214 as_bad (_("selected processor does not support `%s'"), str);
6218 warn_unpredictable_ldst (&inst, str);
6220 if (inst.reloc.type == BFD_RELOC_UNUSED
6221 || !inst.reloc.need_libopcodes_p)
6225 /* If there is relocation generated for the instruction,
6226 store the instruction information for the future fix-up. */
6227 struct aarch64_inst *copy;
6228 gas_assert (inst.reloc.type != BFD_RELOC_UNUSED);
6229 copy = XNEW (struct aarch64_inst);
6230 memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
6236 template = template->next;
6237 if (template != NULL)
6239 reset_aarch64_instruction (&inst);
6240 inst.cond = saved_cond;
6243 while (template != NULL);
6245 /* Issue the error messages if any. */
6246 output_operand_error_report (str);
6249 /* Various frobbings of labels and their addresses. */
6252 aarch64_start_line_hook (void)
6254 last_label_seen = NULL;
6258 aarch64_frob_label (symbolS * sym)
6260 last_label_seen = sym;
6262 dwarf2_emit_label (sym);
6266 aarch64_data_in_code (void)
6268 if (!strncmp (input_line_pointer + 1, "data:", 5))
6270 *input_line_pointer = '/';
6271 input_line_pointer += 5;
6272 *input_line_pointer = 0;
6280 aarch64_canonicalize_symbol_name (char *name)
6284 if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data"))
6285 *(name + len - 5) = 0;
6290 /* Table of all register names defined by default. The user can
6291 define additional names with .req. Note that all register names
6292 should appear in both upper and lowercase variants. Some registers
6293 also have mixed-case names. */
6295 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6296 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6297 #define REGSET16(p,t) \
6298 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6299 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6300 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6301 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
6302 #define REGSET31(p,t) \
6304 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6305 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6306 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6307 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6308 #define REGSET(p,t) \
6309 REGSET31(p,t), REGNUM(p,31,t)
6311 /* These go into aarch64_reg_hsh hash-table. */
6312 static const reg_entry reg_names[] = {
6313 /* Integer registers. */
6314 REGSET31 (x, R_64), REGSET31 (X, R_64),
6315 REGSET31 (w, R_32), REGSET31 (W, R_32),
6317 REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
6318 REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
6320 REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
6321 REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
6323 /* Coprocessor register numbers. */
6324 REGSET (c, CN), REGSET (C, CN),
6326 /* Floating-point single precision registers. */
6327 REGSET (s, FP_S), REGSET (S, FP_S),
6329 /* Floating-point double precision registers. */
6330 REGSET (d, FP_D), REGSET (D, FP_D),
6332 /* Floating-point half precision registers. */
6333 REGSET (h, FP_H), REGSET (H, FP_H),
6335 /* Floating-point byte precision registers. */
6336 REGSET (b, FP_B), REGSET (B, FP_B),
6338 /* Floating-point quad precision registers. */
6339 REGSET (q, FP_Q), REGSET (Q, FP_Q),
6341 /* FP/SIMD registers. */
6342 REGSET (v, VN), REGSET (V, VN),
6344 /* SVE vector registers. */
6345 REGSET (z, ZN), REGSET (Z, ZN),
6347 /* SVE predicate registers. */
6348 REGSET16 (p, PN), REGSET16 (P, PN)
6365 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6366 static const asm_nzcv nzcv_names[] = {
6367 {"nzcv", B (n, z, c, v)},
6368 {"nzcV", B (n, z, c, V)},
6369 {"nzCv", B (n, z, C, v)},
6370 {"nzCV", B (n, z, C, V)},
6371 {"nZcv", B (n, Z, c, v)},
6372 {"nZcV", B (n, Z, c, V)},
6373 {"nZCv", B (n, Z, C, v)},
6374 {"nZCV", B (n, Z, C, V)},
6375 {"Nzcv", B (N, z, c, v)},
6376 {"NzcV", B (N, z, c, V)},
6377 {"NzCv", B (N, z, C, v)},
6378 {"NzCV", B (N, z, C, V)},
6379 {"NZcv", B (N, Z, c, v)},
6380 {"NZcV", B (N, Z, c, V)},
6381 {"NZCv", B (N, Z, C, v)},
6382 {"NZCV", B (N, Z, C, V)}
6395 /* MD interface: bits in the object file. */
6397 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6398 for use in the a.out file, and stores them in the array pointed to by buf.
6399 This knows about the endian-ness of the target machine and does
6400 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6401 2 (short) and 4 (long) Floating numbers are put out as a series of
6402 LITTLENUMS (shorts, here at least). */
6405 md_number_to_chars (char *buf, valueT val, int n)
6407 if (target_big_endian)
6408 number_to_chars_bigendian (buf, val, n);
6410 number_to_chars_littleendian (buf, val, n);
6413 /* MD interface: Sections. */
6415 /* Estimate the size of a frag before relaxing. Assume everything fits in
6419 md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED)
6425 /* Round up a section size to the appropriate boundary. */
6428 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
6433 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6434 of an rs_align_code fragment.
6436 Here we fill the frag with the appropriate info for padding the
6437 output stream. The resulting frag will consist of a fixed (fr_fix)
6438 and of a repeating (fr_var) part.
6440 The fixed content is always emitted before the repeating content and
6441 these two parts are used as follows in constructing the output:
6442 - the fixed part will be used to align to a valid instruction word
6443 boundary, in case that we start at a misaligned address; as no
6444 executable instruction can live at the misaligned location, we
6445 simply fill with zeros;
6446 - the variable part will be used to cover the remaining padding and
6447 we fill using the AArch64 NOP instruction.
6449 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6450 enough storage space for up to 3 bytes for padding the back to a valid
6451 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6454 aarch64_handle_align (fragS * fragP)
6456 /* NOP = d503201f */
6457 /* AArch64 instructions are always little-endian. */
6458 static unsigned char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6460 int bytes, fix, noop_size;
6463 if (fragP->fr_type != rs_align_code)
6466 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
6467 p = fragP->fr_literal + fragP->fr_fix;
6470 gas_assert (fragP->tc_frag_data.recorded);
6473 noop_size = sizeof (aarch64_noop);
6475 fix = bytes & (noop_size - 1);
6479 insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
6483 fragP->fr_fix += fix;
6487 memcpy (p, aarch64_noop, noop_size);
6488 fragP->fr_var = noop_size;
6491 /* Perform target specific initialisation of a frag.
6492 Note - despite the name this initialisation is not done when the frag
6493 is created, but only when its type is assigned. A frag can be created
6494 and used a long time before its type is set, so beware of assuming that
6495 this initialisationis performed first. */
6499 aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED,
6500 int max_chars ATTRIBUTE_UNUSED)
6504 #else /* OBJ_ELF is defined. */
6506 aarch64_init_frag (fragS * fragP, int max_chars)
6508 /* Record a mapping symbol for alignment frags. We will delete this
6509 later if the alignment ends up empty. */
6510 if (!fragP->tc_frag_data.recorded)
6511 fragP->tc_frag_data.recorded = 1;
6513 switch (fragP->fr_type)
6517 mapping_state_2 (MAP_DATA, max_chars);
6520 /* PR 20364: We can get alignment frags in code sections,
6521 so do not just assume that we should use the MAP_DATA state. */
6522 mapping_state_2 (subseg_text_p (now_seg) ? MAP_INSN : MAP_DATA, max_chars);
6525 mapping_state_2 (MAP_INSN, max_chars);
6532 /* Initialize the DWARF-2 unwind information for this procedure. */
6535 tc_aarch64_frame_initial_instructions (void)
6537 cfi_add_CFA_def_cfa (REG_SP, 0);
6539 #endif /* OBJ_ELF */
6541 /* Convert REGNAME to a DWARF-2 register number. */
6544 tc_aarch64_regname_to_dw2regnum (char *regname)
6546 const reg_entry *reg = parse_reg (®name);
6552 case REG_TYPE_SP_32:
6553 case REG_TYPE_SP_64:
6563 return reg->number + 64;
6571 /* Implement DWARF2_ADDR_SIZE. */
6574 aarch64_dwarf2_addr_size (void)
6576 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6580 return bfd_arch_bits_per_address (stdoutput) / 8;
6583 /* MD interface: Symbol and relocation handling. */
6585 /* Return the address within the segment that a PC-relative fixup is
6586 relative to. For AArch64 PC-relative fixups applied to instructions
6587 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6590 md_pcrel_from_section (fixS * fixP, segT seg)
6592 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
6594 /* If this is pc-relative and we are going to emit a relocation
6595 then we just want to put out any pipeline compensation that the linker
6596 will need. Otherwise we want to use the calculated base. */
6598 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
6599 || aarch64_force_relocation (fixP)))
6602 /* AArch64 should be consistent for all pc-relative relocations. */
6603 return base + AARCH64_PCREL_OFFSET;
6606 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6607 Otherwise we have no need to default values of symbols. */
6610 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
6613 if (name[0] == '_' && name[1] == 'G'
6614 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
6618 if (symbol_find (name))
6619 as_bad (_("GOT already in the symbol table"));
6621 GOT_symbol = symbol_new (name, undefined_section,
6622 (valueT) 0, &zero_address_frag);
6632 /* Return non-zero if the indicated VALUE has overflowed the maximum
6633 range expressible by a unsigned number with the indicated number of
6637 unsigned_overflow (valueT value, unsigned bits)
6640 if (bits >= sizeof (valueT) * 8)
6642 lim = (valueT) 1 << bits;
6643 return (value >= lim);
6647 /* Return non-zero if the indicated VALUE has overflowed the maximum
6648 range expressible by an signed number with the indicated number of
6652 signed_overflow (offsetT value, unsigned bits)
6655 if (bits >= sizeof (offsetT) * 8)
6657 lim = (offsetT) 1 << (bits - 1);
6658 return (value < -lim || value >= lim);
6661 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6662 unsigned immediate offset load/store instruction, try to encode it as
6663 an unscaled, 9-bit, signed immediate offset load/store instruction.
6664 Return TRUE if it is successful; otherwise return FALSE.
6666 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6667 in response to the standard LDR/STR mnemonics when the immediate offset is
6668 unambiguous, i.e. when it is negative or unaligned. */
6671 try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
6674 enum aarch64_op new_op;
6675 const aarch64_opcode *new_opcode;
6677 gas_assert (instr->opcode->iclass == ldst_pos);
6679 switch (instr->opcode->op)
6681 case OP_LDRB_POS:new_op = OP_LDURB; break;
6682 case OP_STRB_POS: new_op = OP_STURB; break;
6683 case OP_LDRSB_POS: new_op = OP_LDURSB; break;
6684 case OP_LDRH_POS: new_op = OP_LDURH; break;
6685 case OP_STRH_POS: new_op = OP_STURH; break;
6686 case OP_LDRSH_POS: new_op = OP_LDURSH; break;
6687 case OP_LDR_POS: new_op = OP_LDUR; break;
6688 case OP_STR_POS: new_op = OP_STUR; break;
6689 case OP_LDRF_POS: new_op = OP_LDURV; break;
6690 case OP_STRF_POS: new_op = OP_STURV; break;
6691 case OP_LDRSW_POS: new_op = OP_LDURSW; break;
6692 case OP_PRFM_POS: new_op = OP_PRFUM; break;
6693 default: new_op = OP_NIL; break;
6696 if (new_op == OP_NIL)
6699 new_opcode = aarch64_get_opcode (new_op);
6700 gas_assert (new_opcode != NULL);
6702 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6703 instr->opcode->op, new_opcode->op);
6705 aarch64_replace_opcode (instr, new_opcode);
6707 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6708 qualifier matching may fail because the out-of-date qualifier will
6709 prevent the operand being updated with a new and correct qualifier. */
6710 idx = aarch64_operand_index (instr->opcode->operands,
6711 AARCH64_OPND_ADDR_SIMM9);
6712 gas_assert (idx == 1);
6713 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
6715 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6717 if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
6723 /* Called by fix_insn to fix a MOV immediate alias instruction.
6725 Operand for a generic move immediate instruction, which is an alias
6726 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6727 a 32-bit/64-bit immediate value into general register. An assembler error
6728 shall result if the immediate cannot be created by a single one of these
6729 instructions. If there is a choice, then to ensure reversability an
6730 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6733 fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
6735 const aarch64_opcode *opcode;
6737 /* Need to check if the destination is SP/ZR. The check has to be done
6738 before any aarch64_replace_opcode. */
6739 int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]);
6740 int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]);
6742 instr->operands[1].imm.value = value;
6743 instr->operands[1].skip = 0;
6747 /* Try the MOVZ alias. */
6748 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
6749 aarch64_replace_opcode (instr, opcode);
6750 if (aarch64_opcode_encode (instr->opcode, instr,
6751 &instr->value, NULL, NULL))
6753 put_aarch64_insn (buf, instr->value);
6756 /* Try the MOVK alias. */
6757 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
6758 aarch64_replace_opcode (instr, opcode);
6759 if (aarch64_opcode_encode (instr->opcode, instr,
6760 &instr->value, NULL, NULL))
6762 put_aarch64_insn (buf, instr->value);
6767 if (try_mov_bitmask_p)
6769 /* Try the ORR alias. */
6770 opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
6771 aarch64_replace_opcode (instr, opcode);
6772 if (aarch64_opcode_encode (instr->opcode, instr,
6773 &instr->value, NULL, NULL))
6775 put_aarch64_insn (buf, instr->value);
6780 as_bad_where (fixP->fx_file, fixP->fx_line,
6781 _("immediate cannot be moved by a single instruction"));
6784 /* An instruction operand which is immediate related may have symbol used
6785 in the assembly, e.g.
6788 .set u32, 0x00ffff00
6790 At the time when the assembly instruction is parsed, a referenced symbol,
6791 like 'u32' in the above example may not have been seen; a fixS is created
6792 in such a case and is handled here after symbols have been resolved.
6793 Instruction is fixed up with VALUE using the information in *FIXP plus
6794 extra information in FLAGS.
6796 This function is called by md_apply_fix to fix up instructions that need
6797 a fix-up described above but does not involve any linker-time relocation. */
6800 fix_insn (fixS *fixP, uint32_t flags, offsetT value)
6804 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6805 enum aarch64_opnd opnd = fixP->tc_fix_data.opnd;
6806 aarch64_inst *new_inst = fixP->tc_fix_data.inst;
6810 /* Now the instruction is about to be fixed-up, so the operand that
6811 was previously marked as 'ignored' needs to be unmarked in order
6812 to get the encoding done properly. */
6813 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6814 new_inst->operands[idx].skip = 0;
6817 gas_assert (opnd != AARCH64_OPND_NIL);
6821 case AARCH64_OPND_EXCEPTION:
6822 if (unsigned_overflow (value, 16))
6823 as_bad_where (fixP->fx_file, fixP->fx_line,
6824 _("immediate out of range"));
6825 insn = get_aarch64_insn (buf);
6826 insn |= encode_svc_imm (value);
6827 put_aarch64_insn (buf, insn);
6830 case AARCH64_OPND_AIMM:
6831 /* ADD or SUB with immediate.
6832 NOTE this assumes we come here with a add/sub shifted reg encoding
6833 3 322|2222|2 2 2 21111 111111
6834 1 098|7654|3 2 1 09876 543210 98765 43210
6835 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6836 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6837 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6838 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6840 3 322|2222|2 2 221111111111
6841 1 098|7654|3 2 109876543210 98765 43210
6842 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6843 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6844 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6845 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6846 Fields sf Rn Rd are already set. */
6847 insn = get_aarch64_insn (buf);
6851 insn = reencode_addsub_switch_add_sub (insn);
6855 if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0
6856 && unsigned_overflow (value, 12))
6858 /* Try to shift the value by 12 to make it fit. */
6859 if (((value >> 12) << 12) == value
6860 && ! unsigned_overflow (value, 12 + 12))
6863 insn |= encode_addsub_imm_shift_amount (1);
6867 if (unsigned_overflow (value, 12))
6868 as_bad_where (fixP->fx_file, fixP->fx_line,
6869 _("immediate out of range"));
6871 insn |= encode_addsub_imm (value);
6873 put_aarch64_insn (buf, insn);
6876 case AARCH64_OPND_SIMD_IMM:
6877 case AARCH64_OPND_SIMD_IMM_SFT:
6878 case AARCH64_OPND_LIMM:
6879 /* Bit mask immediate. */
6880 gas_assert (new_inst != NULL);
6881 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6882 new_inst->operands[idx].imm.value = value;
6883 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6884 &new_inst->value, NULL, NULL))
6885 put_aarch64_insn (buf, new_inst->value);
6887 as_bad_where (fixP->fx_file, fixP->fx_line,
6888 _("invalid immediate"));
6891 case AARCH64_OPND_HALF:
6892 /* 16-bit unsigned immediate. */
6893 if (unsigned_overflow (value, 16))
6894 as_bad_where (fixP->fx_file, fixP->fx_line,
6895 _("immediate out of range"));
6896 insn = get_aarch64_insn (buf);
6897 insn |= encode_movw_imm (value & 0xffff);
6898 put_aarch64_insn (buf, insn);
6901 case AARCH64_OPND_IMM_MOV:
6902 /* Operand for a generic move immediate instruction, which is
6903 an alias instruction that generates a single MOVZ, MOVN or ORR
6904 instruction to loads a 32-bit/64-bit immediate value into general
6905 register. An assembler error shall result if the immediate cannot be
6906 created by a single one of these instructions. If there is a choice,
6907 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6908 and MOVZ or MOVN to ORR. */
6909 gas_assert (new_inst != NULL);
6910 fix_mov_imm_insn (fixP, buf, new_inst, value);
6913 case AARCH64_OPND_ADDR_SIMM7:
6914 case AARCH64_OPND_ADDR_SIMM9:
6915 case AARCH64_OPND_ADDR_SIMM9_2:
6916 case AARCH64_OPND_ADDR_UIMM12:
6917 /* Immediate offset in an address. */
6918 insn = get_aarch64_insn (buf);
6920 gas_assert (new_inst != NULL && new_inst->value == insn);
6921 gas_assert (new_inst->opcode->operands[1] == opnd
6922 || new_inst->opcode->operands[2] == opnd);
6924 /* Get the index of the address operand. */
6925 if (new_inst->opcode->operands[1] == opnd)
6926 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6929 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6932 /* Update the resolved offset value. */
6933 new_inst->operands[idx].addr.offset.imm = value;
6935 /* Encode/fix-up. */
6936 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6937 &new_inst->value, NULL, NULL))
6939 put_aarch64_insn (buf, new_inst->value);
6942 else if (new_inst->opcode->iclass == ldst_pos
6943 && try_to_encode_as_unscaled_ldst (new_inst))
6945 put_aarch64_insn (buf, new_inst->value);
6949 as_bad_where (fixP->fx_file, fixP->fx_line,
6950 _("immediate offset out of range"));
6955 as_fatal (_("unhandled operand code %d"), opnd);
6959 /* Apply a fixup (fixP) to segment data, once it has been determined
6960 by our caller that we have all the info we need to fix it up.
6962 Parameter valP is the pointer to the value of the bits. */
6965 md_apply_fix (fixS * fixP, valueT * valP, segT seg)
6967 offsetT value = *valP;
6969 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6971 unsigned flags = fixP->fx_addnumber;
6973 DEBUG_TRACE ("\n\n");
6974 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6975 DEBUG_TRACE ("Enter md_apply_fix");
6977 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
6979 /* Note whether this will delete the relocation. */
6981 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
6984 /* Process the relocations. */
6985 switch (fixP->fx_r_type)
6987 case BFD_RELOC_NONE:
6988 /* This will need to go in the object file. */
6993 case BFD_RELOC_8_PCREL:
6994 if (fixP->fx_done || !seg->use_rela_p)
6995 md_number_to_chars (buf, value, 1);
6999 case BFD_RELOC_16_PCREL:
7000 if (fixP->fx_done || !seg->use_rela_p)
7001 md_number_to_chars (buf, value, 2);
7005 case BFD_RELOC_32_PCREL:
7006 if (fixP->fx_done || !seg->use_rela_p)
7007 md_number_to_chars (buf, value, 4);
7011 case BFD_RELOC_64_PCREL:
7012 if (fixP->fx_done || !seg->use_rela_p)
7013 md_number_to_chars (buf, value, 8);
7016 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
7017 /* We claim that these fixups have been processed here, even if
7018 in fact we generate an error because we do not have a reloc
7019 for them, so tc_gen_reloc() will reject them. */
7021 if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy))
7023 as_bad_where (fixP->fx_file, fixP->fx_line,
7024 _("undefined symbol %s used as an immediate value"),
7025 S_GET_NAME (fixP->fx_addsy));
7026 goto apply_fix_return;
7028 fix_insn (fixP, flags, value);
7031 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
7032 if (fixP->fx_done || !seg->use_rela_p)
7035 as_bad_where (fixP->fx_file, fixP->fx_line,
7036 _("pc-relative load offset not word aligned"));
7037 if (signed_overflow (value, 21))
7038 as_bad_where (fixP->fx_file, fixP->fx_line,
7039 _("pc-relative load offset out of range"));
7040 insn = get_aarch64_insn (buf);
7041 insn |= encode_ld_lit_ofs_19 (value >> 2);
7042 put_aarch64_insn (buf, insn);
7046 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
7047 if (fixP->fx_done || !seg->use_rela_p)
7049 if (signed_overflow (value, 21))
7050 as_bad_where (fixP->fx_file, fixP->fx_line,
7051 _("pc-relative address offset out of range"));
7052 insn = get_aarch64_insn (buf);
7053 insn |= encode_adr_imm (value);
7054 put_aarch64_insn (buf, insn);
7058 case BFD_RELOC_AARCH64_BRANCH19:
7059 if (fixP->fx_done || !seg->use_rela_p)
7062 as_bad_where (fixP->fx_file, fixP->fx_line,
7063 _("conditional branch target not word aligned"));
7064 if (signed_overflow (value, 21))
7065 as_bad_where (fixP->fx_file, fixP->fx_line,
7066 _("conditional branch out of range"));
7067 insn = get_aarch64_insn (buf);
7068 insn |= encode_cond_branch_ofs_19 (value >> 2);
7069 put_aarch64_insn (buf, insn);
7073 case BFD_RELOC_AARCH64_TSTBR14:
7074 if (fixP->fx_done || !seg->use_rela_p)
7077 as_bad_where (fixP->fx_file, fixP->fx_line,
7078 _("conditional branch target not word aligned"));
7079 if (signed_overflow (value, 16))
7080 as_bad_where (fixP->fx_file, fixP->fx_line,
7081 _("conditional branch out of range"));
7082 insn = get_aarch64_insn (buf);
7083 insn |= encode_tst_branch_ofs_14 (value >> 2);
7084 put_aarch64_insn (buf, insn);
7088 case BFD_RELOC_AARCH64_CALL26:
7089 case BFD_RELOC_AARCH64_JUMP26:
7090 if (fixP->fx_done || !seg->use_rela_p)
7093 as_bad_where (fixP->fx_file, fixP->fx_line,
7094 _("branch target not word aligned"));
7095 if (signed_overflow (value, 28))
7096 as_bad_where (fixP->fx_file, fixP->fx_line,
7097 _("branch out of range"));
7098 insn = get_aarch64_insn (buf);
7099 insn |= encode_branch_ofs_26 (value >> 2);
7100 put_aarch64_insn (buf, insn);
7104 case BFD_RELOC_AARCH64_MOVW_G0:
7105 case BFD_RELOC_AARCH64_MOVW_G0_NC:
7106 case BFD_RELOC_AARCH64_MOVW_G0_S:
7107 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
7110 case BFD_RELOC_AARCH64_MOVW_G1:
7111 case BFD_RELOC_AARCH64_MOVW_G1_NC:
7112 case BFD_RELOC_AARCH64_MOVW_G1_S:
7113 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
7116 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
7118 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7119 /* Should always be exported to object file, see
7120 aarch64_force_relocation(). */
7121 gas_assert (!fixP->fx_done);
7122 gas_assert (seg->use_rela_p);
7124 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7126 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7127 /* Should always be exported to object file, see
7128 aarch64_force_relocation(). */
7129 gas_assert (!fixP->fx_done);
7130 gas_assert (seg->use_rela_p);
7132 case BFD_RELOC_AARCH64_MOVW_G2:
7133 case BFD_RELOC_AARCH64_MOVW_G2_NC:
7134 case BFD_RELOC_AARCH64_MOVW_G2_S:
7137 case BFD_RELOC_AARCH64_MOVW_G3:
7140 if (fixP->fx_done || !seg->use_rela_p)
7142 insn = get_aarch64_insn (buf);
7146 /* REL signed addend must fit in 16 bits */
7147 if (signed_overflow (value, 16))
7148 as_bad_where (fixP->fx_file, fixP->fx_line,
7149 _("offset out of range"));
7153 /* Check for overflow and scale. */
7154 switch (fixP->fx_r_type)
7156 case BFD_RELOC_AARCH64_MOVW_G0:
7157 case BFD_RELOC_AARCH64_MOVW_G1:
7158 case BFD_RELOC_AARCH64_MOVW_G2:
7159 case BFD_RELOC_AARCH64_MOVW_G3:
7160 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
7161 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7162 if (unsigned_overflow (value, scale + 16))
7163 as_bad_where (fixP->fx_file, fixP->fx_line,
7164 _("unsigned value out of range"));
7166 case BFD_RELOC_AARCH64_MOVW_G0_S:
7167 case BFD_RELOC_AARCH64_MOVW_G1_S:
7168 case BFD_RELOC_AARCH64_MOVW_G2_S:
7169 /* NOTE: We can only come here with movz or movn. */
7170 if (signed_overflow (value, scale + 16))
7171 as_bad_where (fixP->fx_file, fixP->fx_line,
7172 _("signed value out of range"));
7175 /* Force use of MOVN. */
7177 insn = reencode_movzn_to_movn (insn);
7181 /* Force use of MOVZ. */
7182 insn = reencode_movzn_to_movz (insn);
7186 /* Unchecked relocations. */
7192 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7193 insn |= encode_movw_imm (value & 0xffff);
7195 put_aarch64_insn (buf, insn);
7199 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
7200 fixP->fx_r_type = (ilp32_p
7201 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7202 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);
7203 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7204 /* Should always be exported to object file, see
7205 aarch64_force_relocation(). */
7206 gas_assert (!fixP->fx_done);
7207 gas_assert (seg->use_rela_p);
7210 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
7211 fixP->fx_r_type = (ilp32_p
7212 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7213 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC);
7214 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7215 /* Should always be exported to object file, see
7216 aarch64_force_relocation(). */
7217 gas_assert (!fixP->fx_done);
7218 gas_assert (seg->use_rela_p);
7221 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
7222 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
7223 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
7224 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
7225 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
7226 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
7227 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
7228 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
7229 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
7230 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
7231 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
7232 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
7233 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
7234 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
7235 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
7236 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
7237 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
7238 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
7239 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
7240 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
7241 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
7242 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
7243 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
7244 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
7245 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
7246 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
7247 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
7248 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
7249 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
7250 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
7251 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
7252 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
7253 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
7254 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
7255 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
7256 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
7257 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
7258 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
7259 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
7260 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
7261 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
7262 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
7263 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
7264 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
7265 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7266 /* Should always be exported to object file, see
7267 aarch64_force_relocation(). */
7268 gas_assert (!fixP->fx_done);
7269 gas_assert (seg->use_rela_p);
7272 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
7273 /* Should always be exported to object file, see
7274 aarch64_force_relocation(). */
7275 fixP->fx_r_type = (ilp32_p
7276 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7277 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC);
7278 gas_assert (!fixP->fx_done);
7279 gas_assert (seg->use_rela_p);
7282 case BFD_RELOC_AARCH64_ADD_LO12:
7283 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
7284 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
7285 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
7286 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
7287 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
7288 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
7289 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
7290 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
7291 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
7292 case BFD_RELOC_AARCH64_LDST128_LO12:
7293 case BFD_RELOC_AARCH64_LDST16_LO12:
7294 case BFD_RELOC_AARCH64_LDST32_LO12:
7295 case BFD_RELOC_AARCH64_LDST64_LO12:
7296 case BFD_RELOC_AARCH64_LDST8_LO12:
7297 /* Should always be exported to object file, see
7298 aarch64_force_relocation(). */
7299 gas_assert (!fixP->fx_done);
7300 gas_assert (seg->use_rela_p);
7303 case BFD_RELOC_AARCH64_TLSDESC_ADD:
7304 case BFD_RELOC_AARCH64_TLSDESC_CALL:
7305 case BFD_RELOC_AARCH64_TLSDESC_LDR:
7308 case BFD_RELOC_UNUSED:
7309 /* An error will already have been reported. */
7313 as_bad_where (fixP->fx_file, fixP->fx_line,
7314 _("unexpected %s fixup"),
7315 bfd_get_reloc_code_name (fixP->fx_r_type));
7320 /* Free the allocated the struct aarch64_inst.
7321 N.B. currently there are very limited number of fix-up types actually use
7322 this field, so the impact on the performance should be minimal . */
7323 if (fixP->tc_fix_data.inst != NULL)
7324 free (fixP->tc_fix_data.inst);
7329 /* Translate internal representation of relocation info to BFD target
7333 tc_gen_reloc (asection * section, fixS * fixp)
7336 bfd_reloc_code_real_type code;
7338 reloc = XNEW (arelent);
7340 reloc->sym_ptr_ptr = XNEW (asymbol *);
7341 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7342 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
7346 if (section->use_rela_p)
7347 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
7349 fixp->fx_offset = reloc->address;
7351 reloc->addend = fixp->fx_offset;
7353 code = fixp->fx_r_type;
7358 code = BFD_RELOC_16_PCREL;
7363 code = BFD_RELOC_32_PCREL;
7368 code = BFD_RELOC_64_PCREL;
7375 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
7376 if (reloc->howto == NULL)
7378 as_bad_where (fixp->fx_file, fixp->fx_line,
7380 ("cannot represent %s relocation in this object file format"),
7381 bfd_get_reloc_code_name (code));
7388 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7391 cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp)
7393 bfd_reloc_code_real_type type;
7397 FIXME: @@ Should look at CPU word size. */
7404 type = BFD_RELOC_16;
7407 type = BFD_RELOC_32;
7410 type = BFD_RELOC_64;
7413 as_bad (_("cannot do %u-byte relocation"), size);
7414 type = BFD_RELOC_UNUSED;
7418 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
7422 aarch64_force_relocation (struct fix *fixp)
7424 switch (fixp->fx_r_type)
7426 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
7427 /* Perform these "immediate" internal relocations
7428 even if the symbol is extern or weak. */
7431 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
7432 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
7433 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
7434 /* Pseudo relocs that need to be fixed up according to
7438 case BFD_RELOC_AARCH64_ADD_LO12:
7439 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
7440 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
7441 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
7442 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
7443 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
7444 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
7445 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
7446 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
7447 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
7448 case BFD_RELOC_AARCH64_LDST128_LO12:
7449 case BFD_RELOC_AARCH64_LDST16_LO12:
7450 case BFD_RELOC_AARCH64_LDST32_LO12:
7451 case BFD_RELOC_AARCH64_LDST64_LO12:
7452 case BFD_RELOC_AARCH64_LDST8_LO12:
7453 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
7454 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
7455 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
7456 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
7457 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
7458 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
7459 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
7460 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7461 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
7462 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
7463 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
7464 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
7465 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
7466 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
7467 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
7468 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
7469 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
7470 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
7471 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
7472 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
7473 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
7474 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
7475 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
7476 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
7477 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
7478 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
7479 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
7480 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
7481 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
7482 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
7483 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
7484 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
7485 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
7486 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
7487 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
7488 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
7489 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
7490 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
7491 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
7492 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
7493 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
7494 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
7495 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
7496 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
7497 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
7498 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
7499 /* Always leave these relocations for the linker. */
7506 return generic_force_reloc (fixp);
7512 elf64_aarch64_target_format (void)
7514 if (strcmp (TARGET_OS, "cloudabi") == 0)
7516 /* FIXME: What to do for ilp32_p ? */
7517 return target_big_endian ? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7519 if (target_big_endian)
7520 return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
7522 return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";
7526 aarch64elf_frob_symbol (symbolS * symp, int *puntp)
7528 elf_frob_symbol (symp, puntp);
7532 /* MD interface: Finalization. */
7534 /* A good place to do this, although this was probably not intended
7535 for this kind of use. We need to dump the literal pool before
7536 references are made to a null symbol pointer. */
7539 aarch64_cleanup (void)
7543 for (pool = list_of_pools; pool; pool = pool->next)
7545 /* Put it at the end of the relevant section. */
7546 subseg_set (pool->section, pool->sub_section);
7552 /* Remove any excess mapping symbols generated for alignment frags in
7553 SEC. We may have created a mapping symbol before a zero byte
7554 alignment; remove it if there's a mapping symbol after the
7557 check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec,
7558 void *dummy ATTRIBUTE_UNUSED)
7560 segment_info_type *seginfo = seg_info (sec);
7563 if (seginfo == NULL || seginfo->frchainP == NULL)
7566 for (fragp = seginfo->frchainP->frch_root;
7567 fragp != NULL; fragp = fragp->fr_next)
7569 symbolS *sym = fragp->tc_frag_data.last_map;
7570 fragS *next = fragp->fr_next;
7572 /* Variable-sized frags have been converted to fixed size by
7573 this point. But if this was variable-sized to start with,
7574 there will be a fixed-size frag after it. So don't handle
7576 if (sym == NULL || next == NULL)
7579 if (S_GET_VALUE (sym) < next->fr_address)
7580 /* Not at the end of this frag. */
7582 know (S_GET_VALUE (sym) == next->fr_address);
7586 if (next->tc_frag_data.first_map != NULL)
7588 /* Next frag starts with a mapping symbol. Discard this
7590 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
7594 if (next->fr_next == NULL)
7596 /* This mapping symbol is at the end of the section. Discard
7598 know (next->fr_fix == 0 && next->fr_var == 0);
7599 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
7603 /* As long as we have empty frags without any mapping symbols,
7605 /* If the next frag is non-empty and does not start with a
7606 mapping symbol, then this mapping symbol is required. */
7607 if (next->fr_address != next->fr_next->fr_address)
7610 next = next->fr_next;
7612 while (next != NULL);
7617 /* Adjust the symbol table. */
7620 aarch64_adjust_symtab (void)
7623 /* Remove any overlapping mapping symbols generated by alignment frags. */
7624 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
7625 /* Now do generic ELF adjustments. */
7626 elf_adjust_symtab ();
7631 checked_hash_insert (struct hash_control *table, const char *key, void *value)
7633 const char *hash_err;
7635 hash_err = hash_insert (table, key, value);
7637 printf ("Internal Error: Can't hash %s\n", key);
7641 fill_instruction_hash_table (void)
7643 aarch64_opcode *opcode = aarch64_opcode_table;
7645 while (opcode->name != NULL)
7647 templates *templ, *new_templ;
7648 templ = hash_find (aarch64_ops_hsh, opcode->name);
7650 new_templ = XNEW (templates);
7651 new_templ->opcode = opcode;
7652 new_templ->next = NULL;
7655 checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ);
7658 new_templ->next = templ->next;
7659 templ->next = new_templ;
7666 convert_to_upper (char *dst, const char *src, size_t num)
7669 for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src)
7670 *dst = TOUPPER (*src);
7674 /* Assume STR point to a lower-case string, allocate, convert and return
7675 the corresponding upper-case string. */
7676 static inline const char*
7677 get_upper_str (const char *str)
7680 size_t len = strlen (str);
7681 ret = XNEWVEC (char, len + 1);
7682 convert_to_upper (ret, str, len);
7686 /* MD interface: Initialization. */
7694 if ((aarch64_ops_hsh = hash_new ()) == NULL
7695 || (aarch64_cond_hsh = hash_new ()) == NULL
7696 || (aarch64_shift_hsh = hash_new ()) == NULL
7697 || (aarch64_sys_regs_hsh = hash_new ()) == NULL
7698 || (aarch64_pstatefield_hsh = hash_new ()) == NULL
7699 || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
7700 || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
7701 || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
7702 || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
7703 || (aarch64_reg_hsh = hash_new ()) == NULL
7704 || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
7705 || (aarch64_nzcv_hsh = hash_new ()) == NULL
7706 || (aarch64_pldop_hsh = hash_new ()) == NULL
7707 || (aarch64_hint_opt_hsh = hash_new ()) == NULL)
7708 as_fatal (_("virtual memory exhausted"));
7710 fill_instruction_hash_table ();
7712 for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
7713 checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
7714 (void *) (aarch64_sys_regs + i));
7716 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
7717 checked_hash_insert (aarch64_pstatefield_hsh,
7718 aarch64_pstatefields[i].name,
7719 (void *) (aarch64_pstatefields + i));
7721 for (i = 0; aarch64_sys_regs_ic[i].name != NULL; i++)
7722 checked_hash_insert (aarch64_sys_regs_ic_hsh,
7723 aarch64_sys_regs_ic[i].name,
7724 (void *) (aarch64_sys_regs_ic + i));
7726 for (i = 0; aarch64_sys_regs_dc[i].name != NULL; i++)
7727 checked_hash_insert (aarch64_sys_regs_dc_hsh,
7728 aarch64_sys_regs_dc[i].name,
7729 (void *) (aarch64_sys_regs_dc + i));
7731 for (i = 0; aarch64_sys_regs_at[i].name != NULL; i++)
7732 checked_hash_insert (aarch64_sys_regs_at_hsh,
7733 aarch64_sys_regs_at[i].name,
7734 (void *) (aarch64_sys_regs_at + i));
7736 for (i = 0; aarch64_sys_regs_tlbi[i].name != NULL; i++)
7737 checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
7738 aarch64_sys_regs_tlbi[i].name,
7739 (void *) (aarch64_sys_regs_tlbi + i));
7741 for (i = 0; i < ARRAY_SIZE (reg_names); i++)
7742 checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
7743 (void *) (reg_names + i));
7745 for (i = 0; i < ARRAY_SIZE (nzcv_names); i++)
7746 checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template,
7747 (void *) (nzcv_names + i));
7749 for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++)
7751 const char *name = aarch64_operand_modifiers[i].name;
7752 checked_hash_insert (aarch64_shift_hsh, name,
7753 (void *) (aarch64_operand_modifiers + i));
7754 /* Also hash the name in the upper case. */
7755 checked_hash_insert (aarch64_shift_hsh, get_upper_str (name),
7756 (void *) (aarch64_operand_modifiers + i));
7759 for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++)
7762 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7763 the same condition code. */
7764 for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j)
7766 const char *name = aarch64_conds[i].names[j];
7769 checked_hash_insert (aarch64_cond_hsh, name,
7770 (void *) (aarch64_conds + i));
7771 /* Also hash the name in the upper case. */
7772 checked_hash_insert (aarch64_cond_hsh, get_upper_str (name),
7773 (void *) (aarch64_conds + i));
7777 for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++)
7779 const char *name = aarch64_barrier_options[i].name;
7780 /* Skip xx00 - the unallocated values of option. */
7783 checked_hash_insert (aarch64_barrier_opt_hsh, name,
7784 (void *) (aarch64_barrier_options + i));
7785 /* Also hash the name in the upper case. */
7786 checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
7787 (void *) (aarch64_barrier_options + i));
7790 for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
7792 const char* name = aarch64_prfops[i].name;
7793 /* Skip the unallocated hint encodings. */
7796 checked_hash_insert (aarch64_pldop_hsh, name,
7797 (void *) (aarch64_prfops + i));
7798 /* Also hash the name in the upper case. */
7799 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
7800 (void *) (aarch64_prfops + i));
7803 for (i = 0; aarch64_hint_options[i].name != NULL; i++)
7805 const char* name = aarch64_hint_options[i].name;
7807 checked_hash_insert (aarch64_hint_opt_hsh, name,
7808 (void *) (aarch64_hint_options + i));
7809 /* Also hash the name in the upper case. */
7810 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
7811 (void *) (aarch64_hint_options + i));
7814 /* Set the cpu variant based on the command-line options. */
7816 mcpu_cpu_opt = march_cpu_opt;
7819 mcpu_cpu_opt = &cpu_default;
7821 cpu_variant = *mcpu_cpu_opt;
7823 /* Record the CPU type. */
7824 mach = ilp32_p ? bfd_mach_aarch64_ilp32 : bfd_mach_aarch64;
7826 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
7829 /* Command line processing. */
7831 const char *md_shortopts = "m:";
7833 #ifdef AARCH64_BI_ENDIAN
7834 #define OPTION_EB (OPTION_MD_BASE + 0)
7835 #define OPTION_EL (OPTION_MD_BASE + 1)
7837 #if TARGET_BYTES_BIG_ENDIAN
7838 #define OPTION_EB (OPTION_MD_BASE + 0)
7840 #define OPTION_EL (OPTION_MD_BASE + 1)
7844 struct option md_longopts[] = {
7846 {"EB", no_argument, NULL, OPTION_EB},
7849 {"EL", no_argument, NULL, OPTION_EL},
7851 {NULL, no_argument, NULL, 0}
7854 size_t md_longopts_size = sizeof (md_longopts);
7856 struct aarch64_option_table
7858 const char *option; /* Option name to match. */
7859 const char *help; /* Help information. */
7860 int *var; /* Variable to change. */
7861 int value; /* What to change it to. */
7862 char *deprecated; /* If non-null, print this message. */
7865 static struct aarch64_option_table aarch64_opts[] = {
7866 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
7867 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
7869 #ifdef DEBUG_AARCH64
7870 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL},
7871 #endif /* DEBUG_AARCH64 */
7872 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1,
7874 {"mno-verbose-error", N_("do not output verbose error messages"),
7875 &verbose_error_p, 0, NULL},
7876 {NULL, NULL, NULL, 0, NULL}
7879 struct aarch64_cpu_option_table
7882 const aarch64_feature_set value;
7883 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7885 const char *canonical_name;
7888 /* This list should, at a minimum, contain all the cpu names
7889 recognized by GCC. */
7890 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
7891 {"all", AARCH64_ANY, NULL},
7892 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
7893 AARCH64_FEATURE_CRC), "Cortex-A35"},
7894 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,
7895 AARCH64_FEATURE_CRC), "Cortex-A53"},
7896 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8,
7897 AARCH64_FEATURE_CRC), "Cortex-A57"},
7898 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8,
7899 AARCH64_FEATURE_CRC), "Cortex-A72"},
7900 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8,
7901 AARCH64_FEATURE_CRC), "Cortex-A73"},
7902 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
7903 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
7904 "Samsung Exynos M1"},
7905 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8,
7906 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
7907 "Qualcomm QDF24XX"},
7908 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8,
7909 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
7911 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1,
7912 AARCH64_FEATURE_CRYPTO),
7914 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7915 in earlier releases and is superseded by 'xgene1' in all
7917 {"xgene-1", AARCH64_ARCH_V8, "APM X-Gene 1"},
7918 {"xgene1", AARCH64_ARCH_V8, "APM X-Gene 1"},
7919 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8,
7920 AARCH64_FEATURE_CRC), "APM X-Gene 2"},
7921 {"generic", AARCH64_ARCH_V8, NULL},
7923 {NULL, AARCH64_ARCH_NONE, NULL}
7926 struct aarch64_arch_option_table
7929 const aarch64_feature_set value;
7932 /* This list should, at a minimum, contain all the architecture names
7933 recognized by GCC. */
7934 static const struct aarch64_arch_option_table aarch64_archs[] = {
7935 {"all", AARCH64_ANY},
7936 {"armv8-a", AARCH64_ARCH_V8},
7937 {"armv8.1-a", AARCH64_ARCH_V8_1},
7938 {"armv8.2-a", AARCH64_ARCH_V8_2},
7939 {NULL, AARCH64_ARCH_NONE}
7942 /* ISA extensions. */
7943 struct aarch64_option_cpu_value_table
7946 const aarch64_feature_set value;
7947 const aarch64_feature_set require; /* Feature dependencies. */
7950 static const struct aarch64_option_cpu_value_table aarch64_features[] = {
7951 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0),
7953 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0),
7955 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0),
7957 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0),
7959 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0),
7961 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0),
7963 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0),
7965 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0),
7967 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0),
7968 AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
7969 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16, 0),
7970 AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
7971 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
7973 {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
7976 struct aarch64_long_option_table
7978 const char *option; /* Substring to match. */
7979 const char *help; /* Help information. */
7980 int (*func) (const char *subopt); /* Function to decode sub-option. */
7981 char *deprecated; /* If non-null, print this message. */
7984 /* Transitive closure of features depending on set. */
7985 static aarch64_feature_set
7986 aarch64_feature_disable_set (aarch64_feature_set set)
7988 const struct aarch64_option_cpu_value_table *opt;
7989 aarch64_feature_set prev = 0;
7991 while (prev != set) {
7993 for (opt = aarch64_features; opt->name != NULL; opt++)
7994 if (AARCH64_CPU_HAS_ANY_FEATURES (opt->require, set))
7995 AARCH64_MERGE_FEATURE_SETS (set, set, opt->value);
8000 /* Transitive closure of dependencies of set. */
8001 static aarch64_feature_set
8002 aarch64_feature_enable_set (aarch64_feature_set set)
8004 const struct aarch64_option_cpu_value_table *opt;
8005 aarch64_feature_set prev = 0;
8007 while (prev != set) {
8009 for (opt = aarch64_features; opt->name != NULL; opt++)
8010 if (AARCH64_CPU_HAS_FEATURE (set, opt->value))
8011 AARCH64_MERGE_FEATURE_SETS (set, set, opt->require);
8017 aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p,
8018 bfd_boolean ext_only)
8020 /* We insist on extensions being added before being removed. We achieve
8021 this by using the ADDING_VALUE variable to indicate whether we are
8022 adding an extension (1) or removing it (0) and only allowing it to
8023 change in the order -1 -> 1 -> 0. */
8024 int adding_value = -1;
8025 aarch64_feature_set *ext_set = XNEW (aarch64_feature_set);
8027 /* Copy the feature set, so that we can modify it. */
8031 while (str != NULL && *str != 0)
8033 const struct aarch64_option_cpu_value_table *opt;
8034 const char *ext = NULL;
8041 as_bad (_("invalid architectural extension"));
8045 ext = strchr (++str, '+');
8051 optlen = strlen (str);
8053 if (optlen >= 2 && strncmp (str, "no", 2) == 0)
8055 if (adding_value != 0)
8060 else if (optlen > 0)
8062 if (adding_value == -1)
8064 else if (adding_value != 1)
8066 as_bad (_("must specify extensions to add before specifying "
8067 "those to remove"));
8074 as_bad (_("missing architectural extension"));
8078 gas_assert (adding_value != -1);
8080 for (opt = aarch64_features; opt->name != NULL; opt++)
8081 if (strncmp (opt->name, str, optlen) == 0)
8083 aarch64_feature_set set;
8085 /* Add or remove the extension. */
8088 set = aarch64_feature_enable_set (opt->value);
8089 AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, set);
8093 set = aarch64_feature_disable_set (opt->value);
8094 AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, set);
8099 if (opt->name == NULL)
8101 as_bad (_("unknown architectural extension `%s'"), str);
8112 aarch64_parse_cpu (const char *str)
8114 const struct aarch64_cpu_option_table *opt;
8115 const char *ext = strchr (str, '+');
8121 optlen = strlen (str);
8125 as_bad (_("missing cpu name `%s'"), str);
8129 for (opt = aarch64_cpus; opt->name != NULL; opt++)
8130 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
8132 mcpu_cpu_opt = &opt->value;
8134 return aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE);
8139 as_bad (_("unknown cpu `%s'"), str);
8144 aarch64_parse_arch (const char *str)
8146 const struct aarch64_arch_option_table *opt;
8147 const char *ext = strchr (str, '+');
8153 optlen = strlen (str);
8157 as_bad (_("missing architecture name `%s'"), str);
8161 for (opt = aarch64_archs; opt->name != NULL; opt++)
8162 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
8164 march_cpu_opt = &opt->value;
8166 return aarch64_parse_features (ext, &march_cpu_opt, FALSE);
8171 as_bad (_("unknown architecture `%s'\n"), str);
8176 struct aarch64_option_abi_value_table
8179 enum aarch64_abi_type value;
8182 static const struct aarch64_option_abi_value_table aarch64_abis[] = {
8183 {"ilp32", AARCH64_ABI_ILP32},
8184 {"lp64", AARCH64_ABI_LP64},
8188 aarch64_parse_abi (const char *str)
8194 as_bad (_("missing abi name `%s'"), str);
8198 for (i = 0; i < ARRAY_SIZE (aarch64_abis); i++)
8199 if (strcmp (str, aarch64_abis[i].name) == 0)
8201 aarch64_abi = aarch64_abis[i].value;
8205 as_bad (_("unknown abi `%s'\n"), str);
8209 static struct aarch64_long_option_table aarch64_long_opts[] = {
8211 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8212 aarch64_parse_abi, NULL},
8213 #endif /* OBJ_ELF */
8214 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8215 aarch64_parse_cpu, NULL},
8216 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8217 aarch64_parse_arch, NULL},
8218 {NULL, NULL, 0, NULL}
8222 md_parse_option (int c, const char *arg)
8224 struct aarch64_option_table *opt;
8225 struct aarch64_long_option_table *lopt;
8231 target_big_endian = 1;
8237 target_big_endian = 0;
8242 /* Listing option. Just ignore these, we don't support additional
8247 for (opt = aarch64_opts; opt->option != NULL; opt++)
8249 if (c == opt->option[0]
8250 && ((arg == NULL && opt->option[1] == 0)
8251 || streq (arg, opt->option + 1)))
8253 /* If the option is deprecated, tell the user. */
8254 if (opt->deprecated != NULL)
8255 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
8256 arg ? arg : "", _(opt->deprecated));
8258 if (opt->var != NULL)
8259 *opt->var = opt->value;
8265 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
8267 /* These options are expected to have an argument. */
8268 if (c == lopt->option[0]
8270 && strncmp (arg, lopt->option + 1,
8271 strlen (lopt->option + 1)) == 0)
8273 /* If the option is deprecated, tell the user. */
8274 if (lopt->deprecated != NULL)
8275 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
8276 _(lopt->deprecated));
8278 /* Call the sup-option parser. */
8279 return lopt->func (arg + strlen (lopt->option) - 1);
8290 md_show_usage (FILE * fp)
8292 struct aarch64_option_table *opt;
8293 struct aarch64_long_option_table *lopt;
8295 fprintf (fp, _(" AArch64-specific assembler options:\n"));
8297 for (opt = aarch64_opts; opt->option != NULL; opt++)
8298 if (opt->help != NULL)
8299 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
8301 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
8302 if (lopt->help != NULL)
8303 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
8307 -EB assemble code for a big-endian cpu\n"));
8312 -EL assemble code for a little-endian cpu\n"));
8316 /* Parse a .cpu directive. */
8319 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
8321 const struct aarch64_cpu_option_table *opt;
8327 name = input_line_pointer;
8328 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8329 input_line_pointer++;
8330 saved_char = *input_line_pointer;
8331 *input_line_pointer = 0;
8333 ext = strchr (name, '+');
8336 optlen = ext - name;
8338 optlen = strlen (name);
8340 /* Skip the first "all" entry. */
8341 for (opt = aarch64_cpus + 1; opt->name != NULL; opt++)
8342 if (strlen (opt->name) == optlen
8343 && strncmp (name, opt->name, optlen) == 0)
8345 mcpu_cpu_opt = &opt->value;
8347 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
8350 cpu_variant = *mcpu_cpu_opt;
8352 *input_line_pointer = saved_char;
8353 demand_empty_rest_of_line ();
8356 as_bad (_("unknown cpu `%s'"), name);
8357 *input_line_pointer = saved_char;
8358 ignore_rest_of_line ();
8362 /* Parse a .arch directive. */
8365 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
8367 const struct aarch64_arch_option_table *opt;
8373 name = input_line_pointer;
8374 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8375 input_line_pointer++;
8376 saved_char = *input_line_pointer;
8377 *input_line_pointer = 0;
8379 ext = strchr (name, '+');
8382 optlen = ext - name;
8384 optlen = strlen (name);
8386 /* Skip the first "all" entry. */
8387 for (opt = aarch64_archs + 1; opt->name != NULL; opt++)
8388 if (strlen (opt->name) == optlen
8389 && strncmp (name, opt->name, optlen) == 0)
8391 mcpu_cpu_opt = &opt->value;
8393 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
8396 cpu_variant = *mcpu_cpu_opt;
8398 *input_line_pointer = saved_char;
8399 demand_empty_rest_of_line ();
8403 as_bad (_("unknown architecture `%s'\n"), name);
8404 *input_line_pointer = saved_char;
8405 ignore_rest_of_line ();
8408 /* Parse a .arch_extension directive. */
8411 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED)
8414 char *ext = input_line_pointer;;
8416 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8417 input_line_pointer++;
8418 saved_char = *input_line_pointer;
8419 *input_line_pointer = 0;
8421 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, TRUE))
8424 cpu_variant = *mcpu_cpu_opt;
8426 *input_line_pointer = saved_char;
8427 demand_empty_rest_of_line ();
8430 /* Copy symbol information. */
8433 aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
8435 AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);