1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set *mcpu_cpu_opt = NULL;
53 static const aarch64_feature_set *march_cpu_opt = NULL;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default = CPU_DEFAULT;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS *GOT_symbol;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_LP64;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
91 /* Bits for DEFINED field in vector_type_el. */
93 #define NTA_HASINDEX 2
94 #define NTA_HASVARWIDTH 4
98 enum vector_el_type type;
99 unsigned char defined;
104 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
108 bfd_reloc_code_real_type type;
111 enum aarch64_opnd opnd;
113 unsigned need_libopcodes_p : 1;
116 struct aarch64_instruction
118 /* libopcodes structure for instruction intermediate representation. */
120 /* Record assembly errors found during the parsing. */
123 enum aarch64_operand_error_kind kind;
126 /* The condition that appears in the assembly line. */
128 /* Relocation information (including the GAS internal fixup). */
130 /* Need to generate an immediate in the literal pool. */
131 unsigned gen_lit_pool : 1;
134 typedef struct aarch64_instruction aarch64_instruction;
136 static aarch64_instruction inst;
138 static bfd_boolean parse_operands (char *, const aarch64_opcode *);
139 static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
141 /* Diagnostics inline function utilites.
143 These are lightweight utlities which should only be called by parse_operands
144 and other parsers. GAS processes each assembly line by parsing it against
145 instruction template(s), in the case of multiple templates (for the same
146 mnemonic name), those templates are tried one by one until one succeeds or
147 all fail. An assembly line may fail a few templates before being
148 successfully parsed; an error saved here in most cases is not a user error
149 but an error indicating the current template is not the right template.
150 Therefore it is very important that errors can be saved at a low cost during
151 the parsing; we don't want to slow down the whole parsing by recording
152 non-user errors in detail.
154 Remember that the objective is to help GAS pick up the most approapriate
155 error message in the case of multiple templates, e.g. FMOV which has 8
161 inst.parsing_error.kind = AARCH64_OPDE_NIL;
162 inst.parsing_error.error = NULL;
165 static inline bfd_boolean
168 return inst.parsing_error.kind != AARCH64_OPDE_NIL;
171 static inline const char *
172 get_error_message (void)
174 return inst.parsing_error.error;
177 static inline enum aarch64_operand_error_kind
178 get_error_kind (void)
180 return inst.parsing_error.kind;
184 set_error (enum aarch64_operand_error_kind kind, const char *error)
186 inst.parsing_error.kind = kind;
187 inst.parsing_error.error = error;
191 set_recoverable_error (const char *error)
193 set_error (AARCH64_OPDE_RECOVERABLE, error);
196 /* Use the DESC field of the corresponding aarch64_operand entry to compose
197 the error message. */
199 set_default_error (void)
201 set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
205 set_syntax_error (const char *error)
207 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
211 set_first_syntax_error (const char *error)
214 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
218 set_fatal_syntax_error (const char *error)
220 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
223 /* Number of littlenums required to hold an extended precision number. */
224 #define MAX_LITTLENUMS 6
226 /* Return value for certain parsers when the parsing fails; those parsers
227 return the information of the parsed result, e.g. register number, on
229 #define PARSE_FAIL -1
231 /* This is an invalid condition code that means no conditional field is
233 #define COND_ALWAYS 0x10
237 const char *template;
243 const char *template;
250 bfd_reloc_code_real_type reloc;
253 /* Macros to define the register types and masks for the purpose
256 #undef AARCH64_REG_TYPES
257 #define AARCH64_REG_TYPES \
258 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
259 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
260 BASIC_REG_TYPE(SP_32) /* wsp */ \
261 BASIC_REG_TYPE(SP_64) /* sp */ \
262 BASIC_REG_TYPE(Z_32) /* wzr */ \
263 BASIC_REG_TYPE(Z_64) /* xzr */ \
264 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
265 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
266 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
267 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
268 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
269 BASIC_REG_TYPE(CN) /* c[0-7] */ \
270 BASIC_REG_TYPE(VN) /* v[0-31] */ \
271 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
272 BASIC_REG_TYPE(PN) /* p[0-15] */ \
273 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
274 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
275 /* Typecheck: same, plus SVE registers. */ \
276 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
278 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
279 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
280 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
281 /* Typecheck: same, plus SVE registers. */ \
282 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
283 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
285 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
286 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
287 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
288 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
289 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
291 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
292 /* Typecheck: any [BHSDQ]P FP. */ \
293 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
294 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
295 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
296 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
298 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
299 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
300 /* Any integer register; used for error messages only. */ \
301 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
302 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
303 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
304 /* Pseudo type to mark the end of the enumerator sequence. */ \
307 #undef BASIC_REG_TYPE
308 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
309 #undef MULTI_REG_TYPE
310 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
312 /* Register type enumerators. */
313 typedef enum aarch64_reg_type_
315 /* A list of REG_TYPE_*. */
319 #undef BASIC_REG_TYPE
320 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
322 #define REG_TYPE(T) (1 << REG_TYPE_##T)
323 #undef MULTI_REG_TYPE
324 #define MULTI_REG_TYPE(T,V) V,
326 /* Structure for a hash table entry for a register. */
330 unsigned char number;
331 ENUM_BITFIELD (aarch64_reg_type_) type : 8;
332 unsigned char builtin;
335 /* Values indexed by aarch64_reg_type to assist the type checking. */
336 static const unsigned reg_type_masks[] =
341 #undef BASIC_REG_TYPE
343 #undef MULTI_REG_TYPE
344 #undef AARCH64_REG_TYPES
346 /* Diagnostics used when we don't get a register of the expected type.
347 Note: this has to synchronized with aarch64_reg_type definitions
350 get_reg_expected_msg (aarch64_reg_type reg_type)
357 msg = N_("integer 32-bit register expected");
360 msg = N_("integer 64-bit register expected");
363 msg = N_("integer register expected");
365 case REG_TYPE_R64_SP:
366 msg = N_("64-bit integer or SP register expected");
368 case REG_TYPE_SVE_BASE:
369 msg = N_("base register expected");
372 msg = N_("integer or zero register expected");
374 case REG_TYPE_SVE_OFFSET:
375 msg = N_("offset register expected");
378 msg = N_("integer or SP register expected");
380 case REG_TYPE_R_Z_SP:
381 msg = N_("integer, zero or SP register expected");
384 msg = N_("8-bit SIMD scalar register expected");
387 msg = N_("16-bit SIMD scalar or floating-point half precision "
388 "register expected");
391 msg = N_("32-bit SIMD scalar or floating-point single precision "
392 "register expected");
395 msg = N_("64-bit SIMD scalar or floating-point double precision "
396 "register expected");
399 msg = N_("128-bit SIMD scalar or floating-point quad precision "
400 "register expected");
403 msg = N_("C0 - C15 expected");
405 case REG_TYPE_R_Z_BHSDQ_V:
406 msg = N_("register expected");
408 case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
409 msg = N_("SIMD scalar or floating-point register expected");
411 case REG_TYPE_VN: /* any V reg */
412 msg = N_("vector register expected");
415 msg = N_("SVE vector register expected");
418 msg = N_("SVE predicate register expected");
421 as_fatal (_("invalid register type %d"), reg_type);
426 /* Some well known registers that we refer to directly elsewhere. */
429 /* Instructions take 4 bytes in the object file. */
432 static struct hash_control *aarch64_ops_hsh;
433 static struct hash_control *aarch64_cond_hsh;
434 static struct hash_control *aarch64_shift_hsh;
435 static struct hash_control *aarch64_sys_regs_hsh;
436 static struct hash_control *aarch64_pstatefield_hsh;
437 static struct hash_control *aarch64_sys_regs_ic_hsh;
438 static struct hash_control *aarch64_sys_regs_dc_hsh;
439 static struct hash_control *aarch64_sys_regs_at_hsh;
440 static struct hash_control *aarch64_sys_regs_tlbi_hsh;
441 static struct hash_control *aarch64_reg_hsh;
442 static struct hash_control *aarch64_barrier_opt_hsh;
443 static struct hash_control *aarch64_nzcv_hsh;
444 static struct hash_control *aarch64_pldop_hsh;
445 static struct hash_control *aarch64_hint_opt_hsh;
447 /* Stuff needed to resolve the label ambiguity
456 static symbolS *last_label_seen;
458 /* Literal pool structure. Held on a per-section
459 and per-sub-section basis. */
461 #define MAX_LITERAL_POOL_SIZE 1024
462 typedef struct literal_expression
465 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
466 LITTLENUM_TYPE * bignum;
467 } literal_expression;
469 typedef struct literal_pool
471 literal_expression literals[MAX_LITERAL_POOL_SIZE];
472 unsigned int next_free_entry;
478 struct literal_pool *next;
481 /* Pointer to a linked list of literal pools. */
482 static literal_pool *list_of_pools = NULL;
486 /* This array holds the chars that always start a comment. If the
487 pre-processor is disabled, these aren't very useful. */
488 const char comment_chars[] = "";
490 /* This array holds the chars that only start a comment at the beginning of
491 a line. If the line seems to have the form '# 123 filename'
492 .line and .file directives will appear in the pre-processed output. */
493 /* Note that input_file.c hand checks for '#' at the beginning of the
494 first line of the input file. This is because the compiler outputs
495 #NO_APP at the beginning of its output. */
496 /* Also note that comments like this one will always work. */
497 const char line_comment_chars[] = "#";
499 const char line_separator_chars[] = ";";
501 /* Chars that can be used to separate mant
502 from exp in floating point numbers. */
503 const char EXP_CHARS[] = "eE";
505 /* Chars that mean this number is a floating point constant. */
509 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
511 /* Prefix character that indicates the start of an immediate value. */
512 #define is_immediate_prefix(C) ((C) == '#')
514 /* Separator character handling. */
516 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
518 static inline bfd_boolean
519 skip_past_char (char **str, char c)
530 #define skip_past_comma(str) skip_past_char (str, ',')
532 /* Arithmetic expressions (possibly involving symbols). */
534 static bfd_boolean in_my_get_expression_p = FALSE;
536 /* Third argument to my_get_expression. */
537 #define GE_NO_PREFIX 0
538 #define GE_OPT_PREFIX 1
540 /* Return TRUE if the string pointed by *STR is successfully parsed
541 as an valid expression; *EP will be filled with the information of
542 such an expression. Otherwise return FALSE. */
545 my_get_expression (expressionS * ep, char **str, int prefix_mode,
550 int prefix_present_p = 0;
557 if (is_immediate_prefix (**str))
560 prefix_present_p = 1;
567 memset (ep, 0, sizeof (expressionS));
569 save_in = input_line_pointer;
570 input_line_pointer = *str;
571 in_my_get_expression_p = TRUE;
572 seg = expression (ep);
573 in_my_get_expression_p = FALSE;
575 if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
577 /* We found a bad expression in md_operand(). */
578 *str = input_line_pointer;
579 input_line_pointer = save_in;
580 if (prefix_present_p && ! error_p ())
581 set_fatal_syntax_error (_("bad expression"));
583 set_first_syntax_error (_("bad expression"));
588 if (seg != absolute_section
589 && seg != text_section
590 && seg != data_section
591 && seg != bss_section && seg != undefined_section)
593 set_syntax_error (_("bad segment"));
594 *str = input_line_pointer;
595 input_line_pointer = save_in;
602 *str = input_line_pointer;
603 input_line_pointer = save_in;
607 /* Turn a string in input_line_pointer into a floating point constant
608 of type TYPE, and store the appropriate bytes in *LITP. The number
609 of LITTLENUMS emitted is stored in *SIZEP. An error message is
610 returned, or NULL on OK. */
613 md_atof (int type, char *litP, int *sizeP)
615 return ieee_md_atof (type, litP, sizeP, target_big_endian);
618 /* We handle all bad expressions here, so that we can report the faulty
619 instruction in the error message. */
621 md_operand (expressionS * exp)
623 if (in_my_get_expression_p)
624 exp->X_op = O_illegal;
627 /* Immediate values. */
629 /* Errors may be set multiple times during parsing or bit encoding
630 (particularly in the Neon bits), but usually the earliest error which is set
631 will be the most meaningful. Avoid overwriting it with later (cascading)
632 errors by calling this function. */
635 first_error (const char *error)
638 set_syntax_error (error);
641 /* Similiar to first_error, but this function accepts formatted error
644 first_error_fmt (const char *format, ...)
649 /* N.B. this single buffer will not cause error messages for different
650 instructions to pollute each other; this is because at the end of
651 processing of each assembly line, error message if any will be
652 collected by as_bad. */
653 static char buffer[size];
657 int ret ATTRIBUTE_UNUSED;
658 va_start (args, format);
659 ret = vsnprintf (buffer, size, format, args);
660 know (ret <= size - 1 && ret >= 0);
662 set_syntax_error (buffer);
666 /* Register parsing. */
668 /* Generic register parser which is called by other specialized
670 CCP points to what should be the beginning of a register name.
671 If it is indeed a valid register name, advance CCP over it and
672 return the reg_entry structure; otherwise return NULL.
673 It does not issue diagnostics. */
676 parse_reg (char **ccp)
682 #ifdef REGISTER_PREFIX
683 if (*start != REGISTER_PREFIX)
689 if (!ISALPHA (*p) || !is_name_beginner (*p))
694 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
696 reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start);
705 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
708 aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
710 return (reg_type_masks[type] & (1 << reg->type)) != 0;
713 /* Try to parse a base or offset register. Allow SVE base and offset
714 registers if REG_TYPE includes SVE registers. Return the register
715 entry on success, setting *QUALIFIER to the register qualifier.
716 Return null otherwise.
718 Note that this function does not issue any diagnostics. */
720 static const reg_entry *
721 aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type,
722 aarch64_opnd_qualifier_t *qualifier)
725 const reg_entry *reg = parse_reg (&str);
735 *qualifier = AARCH64_OPND_QLF_W;
741 *qualifier = AARCH64_OPND_QLF_X;
745 if ((reg_type_masks[reg_type] & (1 << REG_TYPE_ZN)) == 0
748 switch (TOLOWER (str[1]))
751 *qualifier = AARCH64_OPND_QLF_S_S;
754 *qualifier = AARCH64_OPND_QLF_S_D;
771 /* Try to parse a base or offset register. Return the register entry
772 on success, setting *QUALIFIER to the register qualifier. Return null
775 Note that this function does not issue any diagnostics. */
777 static const reg_entry *
778 aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
780 return aarch64_addr_reg_parse (ccp, REG_TYPE_R_Z_SP, qualifier);
783 /* Parse the qualifier of a vector register or vector element of type
784 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
785 succeeds; otherwise return FALSE.
787 Accept only one occurrence of:
788 8b 16b 2h 4h 8h 2s 4s 1d 2d
791 parse_vector_type_for_operand (aarch64_reg_type reg_type,
792 struct vector_type_el *parsed_type, char **str)
796 unsigned element_size;
797 enum vector_el_type type;
800 gas_assert (*ptr == '.');
803 if (reg_type == REG_TYPE_ZN || reg_type == REG_TYPE_PN || !ISDIGIT (*ptr))
808 width = strtoul (ptr, &ptr, 10);
809 if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
811 first_error_fmt (_("bad size %d in vector width specifier"), width);
816 switch (TOLOWER (*ptr))
844 first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
846 first_error (_("missing element size"));
849 if (width != 0 && width * element_size != 64 && width * element_size != 128
850 && !(width == 2 && element_size == 16))
853 ("invalid element size %d and vector size combination %c"),
859 parsed_type->type = type;
860 parsed_type->width = width;
867 /* *STR contains an SVE zero/merge predication suffix. Parse it into
868 *PARSED_TYPE and point *STR at the end of the suffix. */
871 parse_predication_for_operand (struct vector_type_el *parsed_type, char **str)
876 gas_assert (*ptr == '/');
878 switch (TOLOWER (*ptr))
881 parsed_type->type = NT_zero;
884 parsed_type->type = NT_merge;
887 if (*ptr != '\0' && *ptr != ',')
888 first_error_fmt (_("unexpected character `%c' in predication type"),
891 first_error (_("missing predication type"));
894 parsed_type->width = 0;
899 /* Parse a register of the type TYPE.
901 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
902 name or the parsed register is not of TYPE.
904 Otherwise return the register number, and optionally fill in the actual
905 type of the register in *RTYPE when multiple alternatives were given, and
906 return the register shape and element index information in *TYPEINFO.
908 IN_REG_LIST should be set with TRUE if the caller is parsing a register
912 parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
913 struct vector_type_el *typeinfo, bfd_boolean in_reg_list)
916 const reg_entry *reg = parse_reg (&str);
917 struct vector_type_el atype;
918 struct vector_type_el parsetype;
919 bfd_boolean is_typed_vecreg = FALSE;
922 atype.type = NT_invtype;
930 set_default_error ();
934 if (! aarch64_check_reg_type (reg, type))
936 DEBUG_TRACE ("reg type check failed");
937 set_default_error ();
942 if ((type == REG_TYPE_VN || type == REG_TYPE_ZN || type == REG_TYPE_PN)
943 && (*str == '.' || (type == REG_TYPE_PN && *str == '/')))
947 if (!parse_vector_type_for_operand (type, &parsetype, &str))
952 if (!parse_predication_for_operand (&parsetype, &str))
956 /* Register if of the form Vn.[bhsdq]. */
957 is_typed_vecreg = TRUE;
959 if (type == REG_TYPE_ZN || type == REG_TYPE_PN)
961 /* The width is always variable; we don't allow an integer width
963 gas_assert (parsetype.width == 0);
964 atype.defined |= NTA_HASVARWIDTH | NTA_HASTYPE;
966 else if (parsetype.width == 0)
967 /* Expect index. In the new scheme we cannot have
968 Vn.[bhsdq] represent a scalar. Therefore any
969 Vn.[bhsdq] should have an index following it.
970 Except in reglists ofcourse. */
971 atype.defined |= NTA_HASINDEX;
973 atype.defined |= NTA_HASTYPE;
975 atype.type = parsetype.type;
976 atype.width = parsetype.width;
979 if (skip_past_char (&str, '['))
983 /* Reject Sn[index] syntax. */
984 if (!is_typed_vecreg)
986 first_error (_("this type of register can't be indexed"));
990 if (in_reg_list == TRUE)
992 first_error (_("index not allowed inside register list"));
996 atype.defined |= NTA_HASINDEX;
998 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1000 if (exp.X_op != O_constant)
1002 first_error (_("constant expression required"));
1006 if (! skip_past_char (&str, ']'))
1009 atype.index = exp.X_add_number;
1011 else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
1013 /* Indexed vector register expected. */
1014 first_error (_("indexed vector register expected"));
1018 /* A vector reg Vn should be typed or indexed. */
1019 if (type == REG_TYPE_VN && atype.defined == 0)
1021 first_error (_("invalid use of vector register"));
1037 Return the register number on success; return PARSE_FAIL otherwise.
1039 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1040 the register (e.g. NEON double or quad reg when either has been requested).
1042 If this is a NEON vector register with additional type information, fill
1043 in the struct pointed to by VECTYPE (if non-NULL).
1045 This parser does not handle register list. */
1048 aarch64_reg_parse (char **ccp, aarch64_reg_type type,
1049 aarch64_reg_type *rtype, struct vector_type_el *vectype)
1051 struct vector_type_el atype;
1053 int reg = parse_typed_reg (&str, type, rtype, &atype,
1054 /*in_reg_list= */ FALSE);
1056 if (reg == PARSE_FAIL)
1067 static inline bfd_boolean
1068 eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2)
1072 && e1.defined == e2.defined
1073 && e1.width == e2.width && e1.index == e2.index;
1076 /* This function parses a list of vector registers of type TYPE.
1077 On success, it returns the parsed register list information in the
1078 following encoded format:
1080 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1081 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1083 The information of the register shape and/or index is returned in
1086 It returns PARSE_FAIL if the register list is invalid.
1088 The list contains one to four registers.
1089 Each register can be one of:
1092 All <T> should be identical.
1093 All <index> should be identical.
1094 There are restrictions on <Vt> numbers which are checked later
1095 (by reg_list_valid_p). */
1098 parse_vector_reg_list (char **ccp, aarch64_reg_type type,
1099 struct vector_type_el *vectype)
1103 struct vector_type_el typeinfo, typeinfo_first;
1108 bfd_boolean error = FALSE;
1109 bfd_boolean expect_index = FALSE;
1113 set_syntax_error (_("expecting {"));
1119 typeinfo_first.defined = 0;
1120 typeinfo_first.type = NT_invtype;
1121 typeinfo_first.width = -1;
1122 typeinfo_first.index = 0;
1131 str++; /* skip over '-' */
1134 val = parse_typed_reg (&str, type, NULL, &typeinfo,
1135 /*in_reg_list= */ TRUE);
1136 if (val == PARSE_FAIL)
1138 set_first_syntax_error (_("invalid vector register in list"));
1142 /* reject [bhsd]n */
1143 if (type == REG_TYPE_VN && typeinfo.defined == 0)
1145 set_first_syntax_error (_("invalid scalar register in list"));
1150 if (typeinfo.defined & NTA_HASINDEX)
1151 expect_index = TRUE;
1155 if (val < val_range)
1157 set_first_syntax_error
1158 (_("invalid range in vector register list"));
1167 typeinfo_first = typeinfo;
1168 else if (! eq_vector_type_el (typeinfo_first, typeinfo))
1170 set_first_syntax_error
1171 (_("type mismatch in vector register list"));
1176 for (i = val_range; i <= val; i++)
1178 ret_val |= i << (5 * nb_regs);
1183 while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
1185 skip_whitespace (str);
1188 set_first_syntax_error (_("end of vector register list not found"));
1193 skip_whitespace (str);
1197 if (skip_past_char (&str, '['))
1201 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1202 if (exp.X_op != O_constant)
1204 set_first_syntax_error (_("constant expression required."));
1207 if (! skip_past_char (&str, ']'))
1210 typeinfo_first.index = exp.X_add_number;
1214 set_first_syntax_error (_("expected index"));
1221 set_first_syntax_error (_("too many registers in vector register list"));
1224 else if (nb_regs == 0)
1226 set_first_syntax_error (_("empty vector register list"));
1232 *vectype = typeinfo_first;
1234 return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1);
1237 /* Directives: register aliases. */
1240 insert_reg_alias (char *str, int number, aarch64_reg_type type)
1245 if ((new = hash_find (aarch64_reg_hsh, str)) != 0)
1248 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1251 /* Only warn about a redefinition if it's not defined as the
1253 else if (new->number != number || new->type != type)
1254 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1259 name = xstrdup (str);
1260 new = XNEW (reg_entry);
1263 new->number = number;
1265 new->builtin = FALSE;
1267 if (hash_insert (aarch64_reg_hsh, name, (void *) new))
1273 /* Look for the .req directive. This is of the form:
1275 new_register_name .req existing_register_name
1277 If we find one, or if it looks sufficiently like one that we want to
1278 handle any error here, return TRUE. Otherwise return FALSE. */
1281 create_register_alias (char *newname, char *p)
1283 const reg_entry *old;
1284 char *oldname, *nbuf;
1287 /* The input scrubber ensures that whitespace after the mnemonic is
1288 collapsed to single spaces. */
1290 if (strncmp (oldname, " .req ", 6) != 0)
1294 if (*oldname == '\0')
1297 old = hash_find (aarch64_reg_hsh, oldname);
1300 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1304 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1305 the desired alias name, and p points to its end. If not, then
1306 the desired alias name is in the global original_case_string. */
1307 #ifdef TC_CASE_SENSITIVE
1310 newname = original_case_string;
1311 nlen = strlen (newname);
1314 nbuf = xmemdup0 (newname, nlen);
1316 /* Create aliases under the new name as stated; an all-lowercase
1317 version of the new name; and an all-uppercase version of the new
1319 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
1321 for (p = nbuf; *p; p++)
1324 if (strncmp (nbuf, newname, nlen))
1326 /* If this attempt to create an additional alias fails, do not bother
1327 trying to create the all-lower case alias. We will fail and issue
1328 a second, duplicate error message. This situation arises when the
1329 programmer does something like:
1332 The second .req creates the "Foo" alias but then fails to create
1333 the artificial FOO alias because it has already been created by the
1335 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
1342 for (p = nbuf; *p; p++)
1345 if (strncmp (nbuf, newname, nlen))
1346 insert_reg_alias (nbuf, old->number, old->type);
1353 /* Should never be called, as .req goes between the alias and the
1354 register name, not at the beginning of the line. */
1356 s_req (int a ATTRIBUTE_UNUSED)
1358 as_bad (_("invalid syntax for .req directive"));
1361 /* The .unreq directive deletes an alias which was previously defined
1362 by .req. For example:
1368 s_unreq (int a ATTRIBUTE_UNUSED)
1373 name = input_line_pointer;
1375 while (*input_line_pointer != 0
1376 && *input_line_pointer != ' ' && *input_line_pointer != '\n')
1377 ++input_line_pointer;
1379 saved_char = *input_line_pointer;
1380 *input_line_pointer = 0;
1383 as_bad (_("invalid syntax for .unreq directive"));
1386 reg_entry *reg = hash_find (aarch64_reg_hsh, name);
1389 as_bad (_("unknown register alias '%s'"), name);
1390 else if (reg->builtin)
1391 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1398 hash_delete (aarch64_reg_hsh, name, FALSE);
1399 free ((char *) reg->name);
1402 /* Also locate the all upper case and all lower case versions.
1403 Do not complain if we cannot find one or the other as it
1404 was probably deleted above. */
1406 nbuf = strdup (name);
1407 for (p = nbuf; *p; p++)
1409 reg = hash_find (aarch64_reg_hsh, nbuf);
1412 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1413 free ((char *) reg->name);
1417 for (p = nbuf; *p; p++)
1419 reg = hash_find (aarch64_reg_hsh, nbuf);
1422 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1423 free ((char *) reg->name);
1431 *input_line_pointer = saved_char;
1432 demand_empty_rest_of_line ();
1435 /* Directives: Instruction set selection. */
1438 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1439 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1440 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1441 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1443 /* Create a new mapping symbol for the transition to STATE. */
1446 make_mapping_symbol (enum mstate state, valueT value, fragS * frag)
1449 const char *symname;
1456 type = BSF_NO_FLAGS;
1460 type = BSF_NO_FLAGS;
1466 symbolP = symbol_new (symname, now_seg, value, frag);
1467 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1469 /* Save the mapping symbols for future reference. Also check that
1470 we do not place two mapping symbols at the same offset within a
1471 frag. We'll handle overlap between frags in
1472 check_mapping_symbols.
1474 If .fill or other data filling directive generates zero sized data,
1475 the mapping symbol for the following code will have the same value
1476 as the one generated for the data filling directive. In this case,
1477 we replace the old symbol with the new one at the same address. */
1480 if (frag->tc_frag_data.first_map != NULL)
1482 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
1483 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP,
1486 frag->tc_frag_data.first_map = symbolP;
1488 if (frag->tc_frag_data.last_map != NULL)
1490 know (S_GET_VALUE (frag->tc_frag_data.last_map) <=
1491 S_GET_VALUE (symbolP));
1492 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
1493 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP,
1496 frag->tc_frag_data.last_map = symbolP;
1499 /* We must sometimes convert a region marked as code to data during
1500 code alignment, if an odd number of bytes have to be padded. The
1501 code mapping symbol is pushed to an aligned address. */
1504 insert_data_mapping_symbol (enum mstate state,
1505 valueT value, fragS * frag, offsetT bytes)
1507 /* If there was already a mapping symbol, remove it. */
1508 if (frag->tc_frag_data.last_map != NULL
1509 && S_GET_VALUE (frag->tc_frag_data.last_map) ==
1510 frag->fr_address + value)
1512 symbolS *symp = frag->tc_frag_data.last_map;
1516 know (frag->tc_frag_data.first_map == symp);
1517 frag->tc_frag_data.first_map = NULL;
1519 frag->tc_frag_data.last_map = NULL;
1520 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
1523 make_mapping_symbol (MAP_DATA, value, frag);
1524 make_mapping_symbol (state, value + bytes, frag);
1527 static void mapping_state_2 (enum mstate state, int max_chars);
1529 /* Set the mapping state to STATE. Only call this when about to
1530 emit some STATE bytes to the file. */
1533 mapping_state (enum mstate state)
1535 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1537 if (state == MAP_INSN)
1538 /* AArch64 instructions require 4-byte alignment. When emitting
1539 instructions into any section, record the appropriate section
1541 record_alignment (now_seg, 2);
1543 if (mapstate == state)
1544 /* The mapping symbol has already been emitted.
1545 There is nothing else to do. */
1548 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1549 if (TRANSITION (MAP_UNDEFINED, MAP_DATA) && !subseg_text_p (now_seg))
1550 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1551 evaluated later in the next else. */
1553 else if (TRANSITION (MAP_UNDEFINED, MAP_INSN))
1555 /* Only add the symbol if the offset is > 0:
1556 if we're at the first frag, check it's size > 0;
1557 if we're not at the first frag, then for sure
1558 the offset is > 0. */
1559 struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root;
1560 const int add_symbol = (frag_now != frag_first)
1561 || (frag_now_fix () > 0);
1564 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
1568 mapping_state_2 (state, 0);
1571 /* Same as mapping_state, but MAX_CHARS bytes have already been
1572 allocated. Put the mapping symbol that far back. */
1575 mapping_state_2 (enum mstate state, int max_chars)
1577 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1579 if (!SEG_NORMAL (now_seg))
1582 if (mapstate == state)
1583 /* The mapping symbol has already been emitted.
1584 There is nothing else to do. */
1587 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1588 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
1591 #define mapping_state(x) /* nothing */
1592 #define mapping_state_2(x, y) /* nothing */
1595 /* Directives: sectioning and alignment. */
1598 s_bss (int ignore ATTRIBUTE_UNUSED)
1600 /* We don't support putting frags in the BSS segment, we fake it by
1601 marking in_bss, then looking at s_skip for clues. */
1602 subseg_set (bss_section, 0);
1603 demand_empty_rest_of_line ();
1604 mapping_state (MAP_DATA);
1608 s_even (int ignore ATTRIBUTE_UNUSED)
1610 /* Never make frag if expect extra pass. */
1612 frag_align (1, 0, 0);
1614 record_alignment (now_seg, 1);
1616 demand_empty_rest_of_line ();
1619 /* Directives: Literal pools. */
1621 static literal_pool *
1622 find_literal_pool (int size)
1626 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1628 if (pool->section == now_seg
1629 && pool->sub_section == now_subseg && pool->size == size)
1636 static literal_pool *
1637 find_or_make_literal_pool (int size)
1639 /* Next literal pool ID number. */
1640 static unsigned int latest_pool_num = 1;
1643 pool = find_literal_pool (size);
1647 /* Create a new pool. */
1648 pool = XNEW (literal_pool);
1652 /* Currently we always put the literal pool in the current text
1653 section. If we were generating "small" model code where we
1654 knew that all code and initialised data was within 1MB then
1655 we could output literals to mergeable, read-only data
1658 pool->next_free_entry = 0;
1659 pool->section = now_seg;
1660 pool->sub_section = now_subseg;
1662 pool->next = list_of_pools;
1663 pool->symbol = NULL;
1665 /* Add it to the list. */
1666 list_of_pools = pool;
1669 /* New pools, and emptied pools, will have a NULL symbol. */
1670 if (pool->symbol == NULL)
1672 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1673 (valueT) 0, &zero_address_frag);
1674 pool->id = latest_pool_num++;
1681 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1682 Return TRUE on success, otherwise return FALSE. */
1684 add_to_lit_pool (expressionS *exp, int size)
1689 pool = find_or_make_literal_pool (size);
1691 /* Check if this literal value is already in the pool. */
1692 for (entry = 0; entry < pool->next_free_entry; entry++)
1694 expressionS * litexp = & pool->literals[entry].exp;
1696 if ((litexp->X_op == exp->X_op)
1697 && (exp->X_op == O_constant)
1698 && (litexp->X_add_number == exp->X_add_number)
1699 && (litexp->X_unsigned == exp->X_unsigned))
1702 if ((litexp->X_op == exp->X_op)
1703 && (exp->X_op == O_symbol)
1704 && (litexp->X_add_number == exp->X_add_number)
1705 && (litexp->X_add_symbol == exp->X_add_symbol)
1706 && (litexp->X_op_symbol == exp->X_op_symbol))
1710 /* Do we need to create a new entry? */
1711 if (entry == pool->next_free_entry)
1713 if (entry >= MAX_LITERAL_POOL_SIZE)
1715 set_syntax_error (_("literal pool overflow"));
1719 pool->literals[entry].exp = *exp;
1720 pool->next_free_entry += 1;
1721 if (exp->X_op == O_big)
1723 /* PR 16688: Bignums are held in a single global array. We must
1724 copy and preserve that value now, before it is overwritten. */
1725 pool->literals[entry].bignum = XNEWVEC (LITTLENUM_TYPE,
1727 memcpy (pool->literals[entry].bignum, generic_bignum,
1728 CHARS_PER_LITTLENUM * exp->X_add_number);
1731 pool->literals[entry].bignum = NULL;
1734 exp->X_op = O_symbol;
1735 exp->X_add_number = ((int) entry) * size;
1736 exp->X_add_symbol = pool->symbol;
1741 /* Can't use symbol_new here, so have to create a symbol and then at
1742 a later date assign it a value. Thats what these functions do. */
1745 symbol_locate (symbolS * symbolP,
1746 const char *name,/* It is copied, the caller can modify. */
1747 segT segment, /* Segment identifier (SEG_<something>). */
1748 valueT valu, /* Symbol value. */
1749 fragS * frag) /* Associated fragment. */
1752 char *preserved_copy_of_name;
1754 name_length = strlen (name) + 1; /* +1 for \0. */
1755 obstack_grow (¬es, name, name_length);
1756 preserved_copy_of_name = obstack_finish (¬es);
1758 #ifdef tc_canonicalize_symbol_name
1759 preserved_copy_of_name =
1760 tc_canonicalize_symbol_name (preserved_copy_of_name);
1763 S_SET_NAME (symbolP, preserved_copy_of_name);
1765 S_SET_SEGMENT (symbolP, segment);
1766 S_SET_VALUE (symbolP, valu);
1767 symbol_clear_list_pointers (symbolP);
1769 symbol_set_frag (symbolP, frag);
1771 /* Link to end of symbol chain. */
1773 extern int symbol_table_frozen;
1775 if (symbol_table_frozen)
1779 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1781 obj_symbol_new_hook (symbolP);
1783 #ifdef tc_symbol_new_hook
1784 tc_symbol_new_hook (symbolP);
1788 verify_symbol_chain (symbol_rootP, symbol_lastP);
1789 #endif /* DEBUG_SYMS */
1794 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1801 for (align = 2; align <= 4; align++)
1803 int size = 1 << align;
1805 pool = find_literal_pool (size);
1806 if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
1809 /* Align pool as you have word accesses.
1810 Only make a frag if we have to. */
1812 frag_align (align, 0, 0);
1814 mapping_state (MAP_DATA);
1816 record_alignment (now_seg, align);
1818 sprintf (sym_name, "$$lit_\002%x", pool->id);
1820 symbol_locate (pool->symbol, sym_name, now_seg,
1821 (valueT) frag_now_fix (), frag_now);
1822 symbol_table_insert (pool->symbol);
1824 for (entry = 0; entry < pool->next_free_entry; entry++)
1826 expressionS * exp = & pool->literals[entry].exp;
1828 if (exp->X_op == O_big)
1830 /* PR 16688: Restore the global bignum value. */
1831 gas_assert (pool->literals[entry].bignum != NULL);
1832 memcpy (generic_bignum, pool->literals[entry].bignum,
1833 CHARS_PER_LITTLENUM * exp->X_add_number);
1836 /* First output the expression in the instruction to the pool. */
1837 emit_expr (exp, size); /* .word|.xword */
1839 if (exp->X_op == O_big)
1841 free (pool->literals[entry].bignum);
1842 pool->literals[entry].bignum = NULL;
1846 /* Mark the pool as empty. */
1847 pool->next_free_entry = 0;
1848 pool->symbol = NULL;
1853 /* Forward declarations for functions below, in the MD interface
1855 static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int);
1856 static struct reloc_table_entry * find_reloc_table_entry (char **);
1858 /* Directives: Data. */
1859 /* N.B. the support for relocation suffix in this directive needs to be
1860 implemented properly. */
1863 s_aarch64_elf_cons (int nbytes)
1867 #ifdef md_flush_pending_output
1868 md_flush_pending_output ();
1871 if (is_it_end_of_statement ())
1873 demand_empty_rest_of_line ();
1877 #ifdef md_cons_align
1878 md_cons_align (nbytes);
1881 mapping_state (MAP_DATA);
1884 struct reloc_table_entry *reloc;
1888 if (exp.X_op != O_symbol)
1889 emit_expr (&exp, (unsigned int) nbytes);
1892 skip_past_char (&input_line_pointer, '#');
1893 if (skip_past_char (&input_line_pointer, ':'))
1895 reloc = find_reloc_table_entry (&input_line_pointer);
1897 as_bad (_("unrecognized relocation suffix"));
1899 as_bad (_("unimplemented relocation suffix"));
1900 ignore_rest_of_line ();
1904 emit_expr (&exp, (unsigned int) nbytes);
1907 while (*input_line_pointer++ == ',');
1909 /* Put terminator back into stream. */
1910 input_line_pointer--;
1911 demand_empty_rest_of_line ();
1914 #endif /* OBJ_ELF */
1916 /* Output a 32-bit word, but mark as an instruction. */
1919 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
1923 #ifdef md_flush_pending_output
1924 md_flush_pending_output ();
1927 if (is_it_end_of_statement ())
1929 demand_empty_rest_of_line ();
1933 /* Sections are assumed to start aligned. In executable section, there is no
1934 MAP_DATA symbol pending. So we only align the address during
1935 MAP_DATA --> MAP_INSN transition.
1936 For other sections, this is not guaranteed. */
1937 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1938 if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA)
1939 frag_align_code (2, 0);
1942 mapping_state (MAP_INSN);
1948 if (exp.X_op != O_constant)
1950 as_bad (_("constant expression required"));
1951 ignore_rest_of_line ();
1955 if (target_big_endian)
1957 unsigned int val = exp.X_add_number;
1958 exp.X_add_number = SWAP_32 (val);
1960 emit_expr (&exp, 4);
1962 while (*input_line_pointer++ == ',');
1964 /* Put terminator back into stream. */
1965 input_line_pointer--;
1966 demand_empty_rest_of_line ();
1970 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1973 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED)
1979 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1980 BFD_RELOC_AARCH64_TLSDESC_ADD);
1982 demand_empty_rest_of_line ();
1985 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1988 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
1992 /* Since we're just labelling the code, there's no need to define a
1995 /* Make sure there is enough room in this frag for the following
1996 blr. This trick only works if the blr follows immediately after
1997 the .tlsdesc directive. */
1999 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
2000 BFD_RELOC_AARCH64_TLSDESC_CALL);
2002 demand_empty_rest_of_line ();
2005 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2008 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED)
2014 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
2015 BFD_RELOC_AARCH64_TLSDESC_LDR);
2017 demand_empty_rest_of_line ();
2019 #endif /* OBJ_ELF */
2021 static void s_aarch64_arch (int);
2022 static void s_aarch64_cpu (int);
2023 static void s_aarch64_arch_extension (int);
2025 /* This table describes all the machine specific pseudo-ops the assembler
2026 has to support. The fields are:
2027 pseudo-op name without dot
2028 function to call to execute this pseudo-op
2029 Integer arg to pass to the function. */
2031 const pseudo_typeS md_pseudo_table[] = {
2032 /* Never called because '.req' does not start a line. */
2034 {"unreq", s_unreq, 0},
2036 {"even", s_even, 0},
2037 {"ltorg", s_ltorg, 0},
2038 {"pool", s_ltorg, 0},
2039 {"cpu", s_aarch64_cpu, 0},
2040 {"arch", s_aarch64_arch, 0},
2041 {"arch_extension", s_aarch64_arch_extension, 0},
2042 {"inst", s_aarch64_inst, 0},
2044 {"tlsdescadd", s_tlsdescadd, 0},
2045 {"tlsdesccall", s_tlsdesccall, 0},
2046 {"tlsdescldr", s_tlsdescldr, 0},
2047 {"word", s_aarch64_elf_cons, 4},
2048 {"long", s_aarch64_elf_cons, 4},
2049 {"xword", s_aarch64_elf_cons, 8},
2050 {"dword", s_aarch64_elf_cons, 8},
2056 /* Check whether STR points to a register name followed by a comma or the
2057 end of line; REG_TYPE indicates which register types are checked
2058 against. Return TRUE if STR is such a register name; otherwise return
2059 FALSE. The function does not intend to produce any diagnostics, but since
2060 the register parser aarch64_reg_parse, which is called by this function,
2061 does produce diagnostics, we call clear_error to clear any diagnostics
2062 that may be generated by aarch64_reg_parse.
2063 Also, the function returns FALSE directly if there is any user error
2064 present at the function entry. This prevents the existing diagnostics
2065 state from being spoiled.
2066 The function currently serves parse_constant_immediate and
2067 parse_big_immediate only. */
2069 reg_name_p (char *str, aarch64_reg_type reg_type)
2073 /* Prevent the diagnostics state from being spoiled. */
2077 reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
2079 /* Clear the parsing error that may be set by the reg parser. */
2082 if (reg == PARSE_FAIL)
2085 skip_whitespace (str);
2086 if (*str == ',' || is_end_of_line[(unsigned int) *str])
2092 /* Parser functions used exclusively in instruction operands. */
2094 /* Parse an immediate expression which may not be constant.
2096 To prevent the expression parser from pushing a register name
2097 into the symbol table as an undefined symbol, firstly a check is
2098 done to find out whether STR is a register of type REG_TYPE followed
2099 by a comma or the end of line. Return FALSE if STR is such a string. */
2102 parse_immediate_expression (char **str, expressionS *exp,
2103 aarch64_reg_type reg_type)
2105 if (reg_name_p (*str, reg_type))
2107 set_recoverable_error (_("immediate operand required"));
2111 my_get_expression (exp, str, GE_OPT_PREFIX, 1);
2113 if (exp->X_op == O_absent)
2115 set_fatal_syntax_error (_("missing immediate expression"));
2122 /* Constant immediate-value read function for use in insn parsing.
2123 STR points to the beginning of the immediate (with the optional
2124 leading #); *VAL receives the value. REG_TYPE says which register
2125 names should be treated as registers rather than as symbolic immediates.
2127 Return TRUE on success; otherwise return FALSE. */
2130 parse_constant_immediate (char **str, int64_t *val, aarch64_reg_type reg_type)
2134 if (! parse_immediate_expression (str, &exp, reg_type))
2137 if (exp.X_op != O_constant)
2139 set_syntax_error (_("constant expression required"));
2143 *val = exp.X_add_number;
2148 encode_imm_float_bits (uint32_t imm)
2150 return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2151 | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2154 /* Return TRUE if the single-precision floating-point value encoded in IMM
2155 can be expressed in the AArch64 8-bit signed floating-point format with
2156 3-bit exponent and normalized 4 bits of precision; in other words, the
2157 floating-point value must be expressable as
2158 (+/-) n / 16 * power (2, r)
2159 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2162 aarch64_imm_float_p (uint32_t imm)
2164 /* If a single-precision floating-point value has the following bit
2165 pattern, it can be expressed in the AArch64 8-bit floating-point
2168 3 32222222 2221111111111
2169 1 09876543 21098765432109876543210
2170 n Eeeeeexx xxxx0000000000000000000
2172 where n, e and each x are either 0 or 1 independently, with
2177 /* Prepare the pattern for 'Eeeeee'. */
2178 if (((imm >> 30) & 0x1) == 0)
2179 pattern = 0x3e000000;
2181 pattern = 0x40000000;
2183 return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */
2184 && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */
2187 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2188 as an IEEE float without any loss of precision. Store the value in
2192 can_convert_double_to_float (uint64_t imm, uint32_t *fpword)
2194 /* If a double-precision floating-point value has the following bit
2195 pattern, it can be expressed in a float:
2197 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2198 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2199 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2201 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2202 if Eeee_eeee != 1111_1111
2204 where n, e, s and S are either 0 or 1 independently and where ~ is the
2208 uint32_t high32 = imm >> 32;
2209 uint32_t low32 = imm;
2211 /* Lower 29 bits need to be 0s. */
2212 if ((imm & 0x1fffffff) != 0)
2215 /* Prepare the pattern for 'Eeeeeeeee'. */
2216 if (((high32 >> 30) & 0x1) == 0)
2217 pattern = 0x38000000;
2219 pattern = 0x40000000;
2222 if ((high32 & 0x78000000) != pattern)
2225 /* Check Eeee_eeee != 1111_1111. */
2226 if ((high32 & 0x7ff00000) == 0x47f00000)
2229 *fpword = ((high32 & 0xc0000000) /* 1 n bit and 1 E bit. */
2230 | ((high32 << 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2231 | (low32 >> 29)); /* 3 S bits. */
2235 /* Parse a floating-point immediate. Return TRUE on success and return the
2236 value in *IMMED in the format of IEEE754 single-precision encoding.
2237 *CCP points to the start of the string; DP_P is TRUE when the immediate
2238 is expected to be in double-precision (N.B. this only matters when
2239 hexadecimal representation is involved). REG_TYPE says which register
2240 names should be treated as registers rather than as symbolic immediates.
2242 This routine accepts any IEEE float; it is up to the callers to reject
2246 parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p,
2247 aarch64_reg_type reg_type)
2251 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2252 int found_fpchar = 0;
2254 unsigned fpword = 0;
2255 bfd_boolean hex_p = FALSE;
2257 skip_past_char (&str, '#');
2260 skip_whitespace (fpnum);
2262 if (strncmp (fpnum, "0x", 2) == 0)
2264 /* Support the hexadecimal representation of the IEEE754 encoding.
2265 Double-precision is expected when DP_P is TRUE, otherwise the
2266 representation should be in single-precision. */
2267 if (! parse_constant_immediate (&str, &val, reg_type))
2272 if (!can_convert_double_to_float (val, &fpword))
2275 else if ((uint64_t) val > 0xffffffff)
2284 if (reg_name_p (str, reg_type))
2286 set_recoverable_error (_("immediate operand required"));
2290 /* We must not accidentally parse an integer as a floating-point number.
2291 Make sure that the value we parse is not an integer by checking for
2292 special characters '.' or 'e'. */
2293 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
2294 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
2308 if ((str = atof_ieee (str, 's', words)) == NULL)
2311 /* Our FP word must be 32 bits (single-precision FP). */
2312 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
2314 fpword <<= LITTLENUM_NUMBER_OF_BITS;
2324 set_fatal_syntax_error (_("invalid floating-point constant"));
2328 /* Less-generic immediate-value read function with the possibility of loading
2329 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2332 To prevent the expression parser from pushing a register name into the
2333 symbol table as an undefined symbol, a check is firstly done to find
2334 out whether STR is a register of type REG_TYPE followed by a comma or
2335 the end of line. Return FALSE if STR is such a register. */
2338 parse_big_immediate (char **str, int64_t *imm, aarch64_reg_type reg_type)
2342 if (reg_name_p (ptr, reg_type))
2344 set_syntax_error (_("immediate operand required"));
2348 my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
2350 if (inst.reloc.exp.X_op == O_constant)
2351 *imm = inst.reloc.exp.X_add_number;
2358 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2359 if NEED_LIBOPCODES is non-zero, the fixup will need
2360 assistance from the libopcodes. */
2363 aarch64_set_gas_internal_fixup (struct reloc *reloc,
2364 const aarch64_opnd_info *operand,
2365 int need_libopcodes_p)
2367 reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2368 reloc->opnd = operand->type;
2369 if (need_libopcodes_p)
2370 reloc->need_libopcodes_p = 1;
2373 /* Return TRUE if the instruction needs to be fixed up later internally by
2374 the GAS; otherwise return FALSE. */
2376 static inline bfd_boolean
2377 aarch64_gas_internal_fixup_p (void)
2379 return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2382 /* Assign the immediate value to the relavant field in *OPERAND if
2383 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2384 needs an internal fixup in a later stage.
2385 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2386 IMM.VALUE that may get assigned with the constant. */
2388 assign_imm_if_const_or_fixup_later (struct reloc *reloc,
2389 aarch64_opnd_info *operand,
2391 int need_libopcodes_p,
2394 if (reloc->exp.X_op == O_constant)
2397 operand->addr.offset.imm = reloc->exp.X_add_number;
2399 operand->imm.value = reloc->exp.X_add_number;
2400 reloc->type = BFD_RELOC_UNUSED;
2404 aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p);
2405 /* Tell libopcodes to ignore this operand or not. This is helpful
2406 when one of the operands needs to be fixed up later but we need
2407 libopcodes to check the other operands. */
2408 operand->skip = skip_p;
2412 /* Relocation modifiers. Each entry in the table contains the textual
2413 name for the relocation which may be placed before a symbol used as
2414 a load/store offset, or add immediate. It must be surrounded by a
2415 leading and trailing colon, for example:
2417 ldr x0, [x1, #:rello:varsym]
2418 add x0, x1, #:rello:varsym */
2420 struct reloc_table_entry
2424 bfd_reloc_code_real_type adr_type;
2425 bfd_reloc_code_real_type adrp_type;
2426 bfd_reloc_code_real_type movw_type;
2427 bfd_reloc_code_real_type add_type;
2428 bfd_reloc_code_real_type ldst_type;
2429 bfd_reloc_code_real_type ld_literal_type;
2432 static struct reloc_table_entry reloc_table[] = {
2433 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2438 BFD_RELOC_AARCH64_ADD_LO12,
2439 BFD_RELOC_AARCH64_LDST_LO12,
2442 /* Higher 21 bits of pc-relative page offset: ADRP */
2445 BFD_RELOC_AARCH64_ADR_HI21_PCREL,
2451 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2454 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
2460 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2464 BFD_RELOC_AARCH64_MOVW_G0,
2469 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2473 BFD_RELOC_AARCH64_MOVW_G0_S,
2478 /* Less significant bits 0-15 of address/value: MOVK, no check */
2482 BFD_RELOC_AARCH64_MOVW_G0_NC,
2487 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2491 BFD_RELOC_AARCH64_MOVW_G1,
2496 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2500 BFD_RELOC_AARCH64_MOVW_G1_S,
2505 /* Less significant bits 16-31 of address/value: MOVK, no check */
2509 BFD_RELOC_AARCH64_MOVW_G1_NC,
2514 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2518 BFD_RELOC_AARCH64_MOVW_G2,
2523 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2527 BFD_RELOC_AARCH64_MOVW_G2_S,
2532 /* Less significant bits 32-47 of address/value: MOVK, no check */
2536 BFD_RELOC_AARCH64_MOVW_G2_NC,
2541 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2545 BFD_RELOC_AARCH64_MOVW_G3,
2550 /* Get to the page containing GOT entry for a symbol. */
2553 BFD_RELOC_AARCH64_ADR_GOT_PAGE,
2557 BFD_RELOC_AARCH64_GOT_LD_PREL19},
2559 /* 12 bit offset into the page containing GOT entry for that symbol. */
2565 BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
2568 /* 0-15 bits of address/value: MOVk, no check. */
2572 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC,
2577 /* Most significant bits 16-31 of address/value: MOVZ. */
2581 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1,
2586 /* 15 bit offset into the page containing GOT entry for that symbol. */
2592 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15,
2595 /* Get to the page containing GOT TLS entry for a symbol */
2596 {"gottprel_g0_nc", 0,
2599 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
2604 /* Get to the page containing GOT TLS entry for a symbol */
2608 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
2613 /* Get to the page containing GOT TLS entry for a symbol */
2615 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21, /* adr_type */
2616 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
2622 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2627 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
2631 /* Lower 16 bits address/value: MOVk. */
2635 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC,
2640 /* Most significant bits 16-31 of address/value: MOVZ. */
2644 BFD_RELOC_AARCH64_TLSGD_MOVW_G1,
2649 /* Get to the page containing GOT TLS entry for a symbol */
2651 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21, /* adr_type */
2652 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21,
2656 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19},
2658 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2663 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
2664 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
2667 /* Get to the page containing GOT TLS entry for a symbol.
2668 The same as GD, we allocate two consecutive GOT slots
2669 for module index and module offset, the only difference
2670 with GD is the module offset should be intialized to
2671 zero without any outstanding runtime relocation. */
2673 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21, /* adr_type */
2674 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21,
2680 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2681 {"tlsldm_lo12_nc", 0,
2685 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC,
2689 /* 12 bit offset into the module TLS base address. */
2694 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12,
2695 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12,
2698 /* Same as dtprel_lo12, no overflow check. */
2699 {"dtprel_lo12_nc", 0,
2703 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC,
2704 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC,
2707 /* bits[23:12] of offset to the module TLS base address. */
2712 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12,
2716 /* bits[15:0] of offset to the module TLS base address. */
2720 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0,
2725 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2729 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC,
2734 /* bits[31:16] of offset to the module TLS base address. */
2738 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1,
2743 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2747 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC,
2752 /* bits[47:32] of offset to the module TLS base address. */
2756 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2,
2761 /* Lower 16 bit offset into GOT entry for a symbol */
2762 {"tlsdesc_off_g0_nc", 0,
2765 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
2770 /* Higher 16 bit offset into GOT entry for a symbol */
2771 {"tlsdesc_off_g1", 0,
2774 BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
2779 /* Get to the page containing GOT TLS entry for a symbol */
2782 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
2786 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19},
2788 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2789 {"gottprel_lo12", 0,
2794 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC,
2797 /* Get tp offset for a symbol. */
2802 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2806 /* Get tp offset for a symbol. */
2811 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2815 /* Get tp offset for a symbol. */
2820 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
2824 /* Get tp offset for a symbol. */
2825 {"tprel_lo12_nc", 0,
2829 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
2833 /* Most significant bits 32-47 of address/value: MOVZ. */
2837 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
2842 /* Most significant bits 16-31 of address/value: MOVZ. */
2846 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
2851 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2855 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
2860 /* Most significant bits 0-15 of address/value: MOVZ. */
2864 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
2869 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2873 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
2878 /* 15bit offset from got entry to base address of GOT table. */
2884 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15,
2887 /* 14bit offset from got entry to base address of GOT table. */
2893 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14,
2897 /* Given the address of a pointer pointing to the textual name of a
2898 relocation as may appear in assembler source, attempt to find its
2899 details in reloc_table. The pointer will be updated to the character
2900 after the trailing colon. On failure, NULL will be returned;
2901 otherwise return the reloc_table_entry. */
2903 static struct reloc_table_entry *
2904 find_reloc_table_entry (char **str)
2907 for (i = 0; i < ARRAY_SIZE (reloc_table); i++)
2909 int length = strlen (reloc_table[i].name);
2911 if (strncasecmp (reloc_table[i].name, *str, length) == 0
2912 && (*str)[length] == ':')
2914 *str += (length + 1);
2915 return &reloc_table[i];
2922 /* Mode argument to parse_shift and parser_shifter_operand. */
2923 enum parse_shift_mode
2925 SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2927 SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2929 SHIFTED_LSL, /* bare "lsl #n" */
2930 SHIFTED_MUL, /* bare "mul #n" */
2931 SHIFTED_LSL_MSL, /* "lsl|msl #n" */
2932 SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */
2935 /* Parse a <shift> operator on an AArch64 data processing instruction.
2936 Return TRUE on success; otherwise return FALSE. */
2938 parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
2940 const struct aarch64_name_value_pair *shift_op;
2941 enum aarch64_modifier_kind kind;
2947 for (p = *str; ISALPHA (*p); p++)
2952 set_syntax_error (_("shift expression expected"));
2956 shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str);
2958 if (shift_op == NULL)
2960 set_syntax_error (_("shift operator expected"));
2964 kind = aarch64_get_operand_modifier (shift_op);
2966 if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
2968 set_syntax_error (_("invalid use of 'MSL'"));
2972 if (kind == AARCH64_MOD_MUL
2973 && mode != SHIFTED_MUL)
2975 set_syntax_error (_("invalid use of 'MUL'"));
2981 case SHIFTED_LOGIC_IMM:
2982 if (aarch64_extend_operator_p (kind) == TRUE)
2984 set_syntax_error (_("extending shift is not permitted"));
2989 case SHIFTED_ARITH_IMM:
2990 if (kind == AARCH64_MOD_ROR)
2992 set_syntax_error (_("'ROR' shift is not permitted"));
2998 if (kind != AARCH64_MOD_LSL)
3000 set_syntax_error (_("only 'LSL' shift is permitted"));
3006 if (kind != AARCH64_MOD_MUL)
3008 set_syntax_error (_("only 'MUL' is permitted"));
3013 case SHIFTED_REG_OFFSET:
3014 if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
3015 && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX)
3017 set_fatal_syntax_error
3018 (_("invalid shift for the register offset addressing mode"));
3023 case SHIFTED_LSL_MSL:
3024 if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
3026 set_syntax_error (_("invalid shift operator"));
3035 /* Whitespace can appear here if the next thing is a bare digit. */
3036 skip_whitespace (p);
3038 /* Parse shift amount. */
3040 if (mode == SHIFTED_REG_OFFSET && *p == ']')
3041 exp.X_op = O_absent;
3044 if (is_immediate_prefix (*p))
3049 my_get_expression (&exp, &p, GE_NO_PREFIX, 0);
3051 if (exp.X_op == O_absent)
3053 if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
3055 set_syntax_error (_("missing shift amount"));
3058 operand->shifter.amount = 0;
3060 else if (exp.X_op != O_constant)
3062 set_syntax_error (_("constant shift amount required"));
3065 /* For parsing purposes, MUL #n has no inherent range. The range
3066 depends on the operand and will be checked by operand-specific
3068 else if (kind != AARCH64_MOD_MUL
3069 && (exp.X_add_number < 0 || exp.X_add_number > 63))
3071 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3076 operand->shifter.amount = exp.X_add_number;
3077 operand->shifter.amount_present = 1;
3080 operand->shifter.operator_present = 1;
3081 operand->shifter.kind = kind;
3087 /* Parse a <shifter_operand> for a data processing instruction:
3090 #<immediate>, LSL #imm
3092 Validation of immediate operands is deferred to md_apply_fix.
3094 Return TRUE on success; otherwise return FALSE. */
3097 parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
3098 enum parse_shift_mode mode)
3102 if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
3107 /* Accept an immediate expression. */
3108 if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
3111 /* Accept optional LSL for arithmetic immediate values. */
3112 if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
3113 if (! parse_shift (&p, operand, SHIFTED_LSL))
3116 /* Not accept any shifter for logical immediate values. */
3117 if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
3118 && parse_shift (&p, operand, mode))
3120 set_syntax_error (_("unexpected shift operator"));
3128 /* Parse a <shifter_operand> for a data processing instruction:
3133 #<immediate>, LSL #imm
3135 where <shift> is handled by parse_shift above, and the last two
3136 cases are handled by the function above.
3138 Validation of immediate operands is deferred to md_apply_fix.
3140 Return TRUE on success; otherwise return FALSE. */
3143 parse_shifter_operand (char **str, aarch64_opnd_info *operand,
3144 enum parse_shift_mode mode)
3146 const reg_entry *reg;
3147 aarch64_opnd_qualifier_t qualifier;
3148 enum aarch64_operand_class opd_class
3149 = aarch64_get_operand_class (operand->type);
3151 reg = aarch64_reg_parse_32_64 (str, &qualifier);
3154 if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
3156 set_syntax_error (_("unexpected register in the immediate operand"));
3160 if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
3162 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z)));
3166 operand->reg.regno = reg->number;
3167 operand->qualifier = qualifier;
3169 /* Accept optional shift operation on register. */
3170 if (! skip_past_comma (str))
3173 if (! parse_shift (str, operand, mode))
3178 else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
3181 (_("integer register expected in the extended/shifted operand "
3186 /* We have a shifted immediate variable. */
3187 return parse_shifter_operand_imm (str, operand, mode);
3190 /* Return TRUE on success; return FALSE otherwise. */
3193 parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
3194 enum parse_shift_mode mode)
3198 /* Determine if we have the sequence of characters #: or just :
3199 coming next. If we do, then we check for a :rello: relocation
3200 modifier. If we don't, punt the whole lot to
3201 parse_shifter_operand. */
3203 if ((p[0] == '#' && p[1] == ':') || p[0] == ':')
3205 struct reloc_table_entry *entry;
3213 /* Try to parse a relocation. Anything else is an error. */
3214 if (!(entry = find_reloc_table_entry (str)))
3216 set_syntax_error (_("unknown relocation modifier"));
3220 if (entry->add_type == 0)
3223 (_("this relocation modifier is not allowed on this instruction"));
3227 /* Save str before we decompose it. */
3230 /* Next, we parse the expression. */
3231 if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
3234 /* Record the relocation type (use the ADD variant here). */
3235 inst.reloc.type = entry->add_type;
3236 inst.reloc.pc_rel = entry->pc_rel;
3238 /* If str is empty, we've reached the end, stop here. */
3242 /* Otherwise, we have a shifted reloc modifier, so rewind to
3243 recover the variable name and continue parsing for the shifter. */
3245 return parse_shifter_operand_imm (str, operand, mode);
3248 return parse_shifter_operand (str, operand, mode);
3251 /* Parse all forms of an address expression. Information is written
3252 to *OPERAND and/or inst.reloc.
3254 The A64 instruction set has the following addressing modes:
3257 [base] // in SIMD ld/st structure
3258 [base{,#0}] // in ld/st exclusive
3260 [base,Xm{,LSL #imm}]
3261 [base,Xm,SXTX {#imm}]
3262 [base,Wm,(S|U)XTW {#imm}]
3267 [base],Xm // in SIMD ld/st structure
3268 PC-relative (literal)
3271 [base,Zm.D{,LSL #imm}]
3272 [base,Zm.S,(S|U)XTW {#imm}]
3273 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3276 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3277 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3278 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3280 (As a convenience, the notation "=immediate" is permitted in conjunction
3281 with the pc-relative literal load instructions to automatically place an
3282 immediate value or symbolic address in a nearby literal pool and generate
3283 a hidden label which references it.)
3285 Upon a successful parsing, the address structure in *OPERAND will be
3286 filled in the following way:
3288 .base_regno = <base>
3289 .offset.is_reg // 1 if the offset is a register
3291 .offset.regno = <Rm>
3293 For different addressing modes defined in the A64 ISA:
3296 .pcrel=0; .preind=1; .postind=0; .writeback=0
3298 .pcrel=0; .preind=1; .postind=0; .writeback=1
3300 .pcrel=0; .preind=0; .postind=1; .writeback=1
3301 PC-relative (literal)
3302 .pcrel=1; .preind=1; .postind=0; .writeback=0
3304 The shift/extension information, if any, will be stored in .shifter.
3305 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3306 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3307 corresponding register.
3309 BASE_TYPE says which types of base register should be accepted and
3310 OFFSET_TYPE says the same for offset registers. In all other respects,
3311 it is the caller's responsibility to check for addressing modes not
3312 supported by the instruction, and to set inst.reloc.type. */
3315 parse_address_main (char **str, aarch64_opnd_info *operand,
3316 aarch64_opnd_qualifier_t *base_qualifier,
3317 aarch64_opnd_qualifier_t *offset_qualifier,
3318 aarch64_reg_type base_type, aarch64_reg_type offset_type)
3321 const reg_entry *reg;
3322 expressionS *exp = &inst.reloc.exp;
3324 *base_qualifier = AARCH64_OPND_QLF_NIL;
3325 *offset_qualifier = AARCH64_OPND_QLF_NIL;
3326 if (! skip_past_char (&p, '['))
3328 /* =immediate or label. */
3329 operand->addr.pcrel = 1;
3330 operand->addr.preind = 1;
3332 /* #:<reloc_op>:<symbol> */
3333 skip_past_char (&p, '#');
3334 if (skip_past_char (&p, ':'))
3336 bfd_reloc_code_real_type ty;
3337 struct reloc_table_entry *entry;
3339 /* Try to parse a relocation modifier. Anything else is
3341 entry = find_reloc_table_entry (&p);
3344 set_syntax_error (_("unknown relocation modifier"));
3348 switch (operand->type)
3350 case AARCH64_OPND_ADDR_PCREL21:
3352 ty = entry->adr_type;
3356 ty = entry->ld_literal_type;
3363 (_("this relocation modifier is not allowed on this "
3369 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3371 set_syntax_error (_("invalid relocation expression"));
3375 /* #:<reloc_op>:<expr> */
3376 /* Record the relocation type. */
3377 inst.reloc.type = ty;
3378 inst.reloc.pc_rel = entry->pc_rel;
3383 if (skip_past_char (&p, '='))
3384 /* =immediate; need to generate the literal in the literal pool. */
3385 inst.gen_lit_pool = 1;
3387 if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3389 set_syntax_error (_("invalid address"));
3400 reg = aarch64_addr_reg_parse (&p, base_type, base_qualifier);
3401 if (!reg || !aarch64_check_reg_type (reg, base_type))
3403 set_syntax_error (_(get_reg_expected_msg (base_type)));
3406 operand->addr.base_regno = reg->number;
3409 if (skip_past_comma (&p))
3412 operand->addr.preind = 1;
3414 reg = aarch64_addr_reg_parse (&p, offset_type, offset_qualifier);
3417 if (!aarch64_check_reg_type (reg, offset_type))
3419 set_syntax_error (_(get_reg_expected_msg (offset_type)));
3424 operand->addr.offset.regno = reg->number;
3425 operand->addr.offset.is_reg = 1;
3426 /* Shifted index. */
3427 if (skip_past_comma (&p))
3430 if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
3431 /* Use the diagnostics set in parse_shift, so not set new
3432 error message here. */
3436 [base,Xm{,LSL #imm}]
3437 [base,Xm,SXTX {#imm}]
3438 [base,Wm,(S|U)XTW {#imm}] */
3439 if (operand->shifter.kind == AARCH64_MOD_NONE
3440 || operand->shifter.kind == AARCH64_MOD_LSL
3441 || operand->shifter.kind == AARCH64_MOD_SXTX)
3443 if (*offset_qualifier == AARCH64_OPND_QLF_W)
3445 set_syntax_error (_("invalid use of 32-bit register offset"));
3448 if (aarch64_get_qualifier_esize (*base_qualifier)
3449 != aarch64_get_qualifier_esize (*offset_qualifier))
3451 set_syntax_error (_("offset has different size from base"));
3455 else if (*offset_qualifier == AARCH64_OPND_QLF_X)
3457 set_syntax_error (_("invalid use of 64-bit register offset"));
3463 /* [Xn,#:<reloc_op>:<symbol> */
3464 skip_past_char (&p, '#');
3465 if (skip_past_char (&p, ':'))
3467 struct reloc_table_entry *entry;
3469 /* Try to parse a relocation modifier. Anything else is
3471 if (!(entry = find_reloc_table_entry (&p)))
3473 set_syntax_error (_("unknown relocation modifier"));
3477 if (entry->ldst_type == 0)
3480 (_("this relocation modifier is not allowed on this "
3485 /* [Xn,#:<reloc_op>: */
3486 /* We now have the group relocation table entry corresponding to
3487 the name in the assembler source. Next, we parse the
3489 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3491 set_syntax_error (_("invalid relocation expression"));
3495 /* [Xn,#:<reloc_op>:<expr> */
3496 /* Record the load/store relocation type. */
3497 inst.reloc.type = entry->ldst_type;
3498 inst.reloc.pc_rel = entry->pc_rel;
3500 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3502 set_syntax_error (_("invalid expression in the address"));
3509 if (! skip_past_char (&p, ']'))
3511 set_syntax_error (_("']' expected"));
3515 if (skip_past_char (&p, '!'))
3517 if (operand->addr.preind && operand->addr.offset.is_reg)
3519 set_syntax_error (_("register offset not allowed in pre-indexed "
3520 "addressing mode"));
3524 operand->addr.writeback = 1;
3526 else if (skip_past_comma (&p))
3529 operand->addr.postind = 1;
3530 operand->addr.writeback = 1;
3532 if (operand->addr.preind)
3534 set_syntax_error (_("cannot combine pre- and post-indexing"));
3538 reg = aarch64_reg_parse_32_64 (&p, offset_qualifier);
3542 if (!aarch64_check_reg_type (reg, REG_TYPE_R_64))
3544 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
3548 operand->addr.offset.regno = reg->number;
3549 operand->addr.offset.is_reg = 1;
3551 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3554 set_syntax_error (_("invalid expression in the address"));
3559 /* If at this point neither .preind nor .postind is set, we have a
3560 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3561 if (operand->addr.preind == 0 && operand->addr.postind == 0)
3563 if (operand->addr.writeback)
3566 set_syntax_error (_("missing offset in the pre-indexed address"));
3569 operand->addr.preind = 1;
3570 inst.reloc.exp.X_op = O_constant;
3571 inst.reloc.exp.X_add_number = 0;
3578 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3581 parse_address (char **str, aarch64_opnd_info *operand)
3583 aarch64_opnd_qualifier_t base_qualifier, offset_qualifier;
3584 return parse_address_main (str, operand, &base_qualifier, &offset_qualifier,
3585 REG_TYPE_R64_SP, REG_TYPE_R_Z);
3588 /* Parse an address in which SVE vector registers are allowed.
3589 The arguments have the same meaning as for parse_address_main.
3590 Return TRUE on success. */
3592 parse_sve_address (char **str, aarch64_opnd_info *operand,
3593 aarch64_opnd_qualifier_t *base_qualifier,
3594 aarch64_opnd_qualifier_t *offset_qualifier)
3596 return parse_address_main (str, operand, base_qualifier, offset_qualifier,
3597 REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET);
3600 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3601 Return TRUE on success; otherwise return FALSE. */
3603 parse_half (char **str, int *internal_fixup_p)
3607 skip_past_char (&p, '#');
3609 gas_assert (internal_fixup_p);
3610 *internal_fixup_p = 0;
3614 struct reloc_table_entry *entry;
3616 /* Try to parse a relocation. Anything else is an error. */
3618 if (!(entry = find_reloc_table_entry (&p)))
3620 set_syntax_error (_("unknown relocation modifier"));
3624 if (entry->movw_type == 0)
3627 (_("this relocation modifier is not allowed on this instruction"));
3631 inst.reloc.type = entry->movw_type;
3634 *internal_fixup_p = 1;
3636 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3643 /* Parse an operand for an ADRP instruction:
3645 Return TRUE on success; otherwise return FALSE. */
3648 parse_adrp (char **str)
3655 struct reloc_table_entry *entry;
3657 /* Try to parse a relocation. Anything else is an error. */
3659 if (!(entry = find_reloc_table_entry (&p)))
3661 set_syntax_error (_("unknown relocation modifier"));
3665 if (entry->adrp_type == 0)
3668 (_("this relocation modifier is not allowed on this instruction"));
3672 inst.reloc.type = entry->adrp_type;
3675 inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
3677 inst.reloc.pc_rel = 1;
3679 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3686 /* Miscellaneous. */
3688 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3689 of SIZE tokens in which index I gives the token for field value I,
3690 or is null if field value I is invalid. REG_TYPE says which register
3691 names should be treated as registers rather than as symbolic immediates.
3693 Return true on success, moving *STR past the operand and storing the
3694 field value in *VAL. */
3697 parse_enum_string (char **str, int64_t *val, const char *const *array,
3698 size_t size, aarch64_reg_type reg_type)
3704 /* Match C-like tokens. */
3706 while (ISALNUM (*q))
3709 for (i = 0; i < size; ++i)
3711 && strncasecmp (array[i], p, q - p) == 0
3712 && array[i][q - p] == 0)
3719 if (!parse_immediate_expression (&p, &exp, reg_type))
3722 if (exp.X_op == O_constant
3723 && (uint64_t) exp.X_add_number < size)
3725 *val = exp.X_add_number;
3730 /* Use the default error for this operand. */
3734 /* Parse an option for a preload instruction. Returns the encoding for the
3735 option, or PARSE_FAIL. */
3738 parse_pldop (char **str)
3741 const struct aarch64_name_value_pair *o;
3744 while (ISALNUM (*q))
3747 o = hash_find_n (aarch64_pldop_hsh, p, q - p);
3755 /* Parse an option for a barrier instruction. Returns the encoding for the
3756 option, or PARSE_FAIL. */
3759 parse_barrier (char **str)
3762 const asm_barrier_opt *o;
3765 while (ISALPHA (*q))
3768 o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p);
3776 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3777 return 0 if successful. Otherwise return PARSE_FAIL. */
3780 parse_barrier_psb (char **str,
3781 const struct aarch64_name_value_pair ** hint_opt)
3784 const struct aarch64_name_value_pair *o;
3787 while (ISALPHA (*q))
3790 o = hash_find_n (aarch64_hint_opt_hsh, p, q - p);
3793 set_fatal_syntax_error
3794 ( _("unknown or missing option to PSB"));
3798 if (o->value != 0x11)
3800 /* PSB only accepts option name 'CSYNC'. */
3802 (_("the specified option is not accepted for PSB"));
3811 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3812 Returns the encoding for the option, or PARSE_FAIL.
3814 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3815 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3817 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3818 field, otherwise as a system register.
3822 parse_sys_reg (char **str, struct hash_control *sys_regs,
3823 int imple_defined_p, int pstatefield_p)
3827 const aarch64_sys_reg *o;
3831 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3833 *p++ = TOLOWER (*q);
3835 /* Assert that BUF be large enough. */
3836 gas_assert (p - buf == q - *str);
3838 o = hash_find (sys_regs, buf);
3841 if (!imple_defined_p)
3845 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3846 unsigned int op0, op1, cn, cm, op2;
3848 if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2)
3851 if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
3853 value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
3858 if (pstatefield_p && !aarch64_pstatefield_supported_p (cpu_variant, o))
3859 as_bad (_("selected processor does not support PSTATE field "
3861 if (!pstatefield_p && !aarch64_sys_reg_supported_p (cpu_variant, o))
3862 as_bad (_("selected processor does not support system register "
3864 if (aarch64_sys_reg_deprecated_p (o))
3865 as_warn (_("system register name '%s' is deprecated and may be "
3866 "removed in a future release"), buf);
3874 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3875 for the option, or NULL. */
3877 static const aarch64_sys_ins_reg *
3878 parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
3882 const aarch64_sys_ins_reg *o;
3885 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3887 *p++ = TOLOWER (*q);
3890 o = hash_find (sys_ins_regs, buf);
3894 if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
3895 as_bad (_("selected processor does not support system register "
3902 #define po_char_or_fail(chr) do { \
3903 if (! skip_past_char (&str, chr)) \
3907 #define po_reg_or_fail(regtype) do { \
3908 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3909 if (val == PARSE_FAIL) \
3911 set_default_error (); \
3916 #define po_int_reg_or_fail(reg_type) do { \
3917 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
3918 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
3920 set_default_error (); \
3923 info->reg.regno = reg->number; \
3924 info->qualifier = qualifier; \
3927 #define po_imm_nc_or_fail() do { \
3928 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3932 #define po_imm_or_fail(min, max) do { \
3933 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3935 if (val < min || val > max) \
3937 set_fatal_syntax_error (_("immediate value out of range "\
3938 #min " to "#max)); \
3943 #define po_enum_or_fail(array) do { \
3944 if (!parse_enum_string (&str, &val, array, \
3945 ARRAY_SIZE (array), imm_reg_type)) \
3949 #define po_misc_or_fail(expr) do { \
3954 /* encode the 12-bit imm field of Add/sub immediate */
3955 static inline uint32_t
3956 encode_addsub_imm (uint32_t imm)
3961 /* encode the shift amount field of Add/sub immediate */
3962 static inline uint32_t
3963 encode_addsub_imm_shift_amount (uint32_t cnt)
3969 /* encode the imm field of Adr instruction */
3970 static inline uint32_t
3971 encode_adr_imm (uint32_t imm)
3973 return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */
3974 | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3977 /* encode the immediate field of Move wide immediate */
3978 static inline uint32_t
3979 encode_movw_imm (uint32_t imm)
3984 /* encode the 26-bit offset of unconditional branch */
3985 static inline uint32_t
3986 encode_branch_ofs_26 (uint32_t ofs)
3988 return ofs & ((1 << 26) - 1);
3991 /* encode the 19-bit offset of conditional branch and compare & branch */
3992 static inline uint32_t
3993 encode_cond_branch_ofs_19 (uint32_t ofs)
3995 return (ofs & ((1 << 19) - 1)) << 5;
3998 /* encode the 19-bit offset of ld literal */
3999 static inline uint32_t
4000 encode_ld_lit_ofs_19 (uint32_t ofs)
4002 return (ofs & ((1 << 19) - 1)) << 5;
4005 /* Encode the 14-bit offset of test & branch. */
4006 static inline uint32_t
4007 encode_tst_branch_ofs_14 (uint32_t ofs)
4009 return (ofs & ((1 << 14) - 1)) << 5;
4012 /* Encode the 16-bit imm field of svc/hvc/smc. */
4013 static inline uint32_t
4014 encode_svc_imm (uint32_t imm)
4019 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4020 static inline uint32_t
4021 reencode_addsub_switch_add_sub (uint32_t opcode)
4023 return opcode ^ (1 << 30);
4026 static inline uint32_t
4027 reencode_movzn_to_movz (uint32_t opcode)
4029 return opcode | (1 << 30);
4032 static inline uint32_t
4033 reencode_movzn_to_movn (uint32_t opcode)
4035 return opcode & ~(1 << 30);
4038 /* Overall per-instruction processing. */
4040 /* We need to be able to fix up arbitrary expressions in some statements.
4041 This is so that we can handle symbols that are an arbitrary distance from
4042 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4043 which returns part of an address in a form which will be valid for
4044 a data instruction. We do this by pushing the expression into a symbol
4045 in the expr_section, and creating a fix for that. */
4048 fix_new_aarch64 (fragS * frag,
4050 short int size, expressionS * exp, int pc_rel, int reloc)
4060 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
4064 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
4071 /* Diagnostics on operands errors. */
4073 /* By default, output verbose error message.
4074 Disable the verbose error message by -mno-verbose-error. */
4075 static int verbose_error_p = 1;
4077 #ifdef DEBUG_AARCH64
4078 /* N.B. this is only for the purpose of debugging. */
4079 const char* operand_mismatch_kind_names[] =
4082 "AARCH64_OPDE_RECOVERABLE",
4083 "AARCH64_OPDE_SYNTAX_ERROR",
4084 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4085 "AARCH64_OPDE_INVALID_VARIANT",
4086 "AARCH64_OPDE_OUT_OF_RANGE",
4087 "AARCH64_OPDE_UNALIGNED",
4088 "AARCH64_OPDE_REG_LIST",
4089 "AARCH64_OPDE_OTHER_ERROR",
4091 #endif /* DEBUG_AARCH64 */
4093 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4095 When multiple errors of different kinds are found in the same assembly
4096 line, only the error of the highest severity will be picked up for
4097 issuing the diagnostics. */
4099 static inline bfd_boolean
4100 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
4101 enum aarch64_operand_error_kind rhs)
4103 gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL);
4104 gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE);
4105 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
4106 gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
4107 gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
4108 gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
4109 gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
4110 gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
4114 /* Helper routine to get the mnemonic name from the assembly instruction
4115 line; should only be called for the diagnosis purpose, as there is
4116 string copy operation involved, which may affect the runtime
4117 performance if used in elsewhere. */
4120 get_mnemonic_name (const char *str)
4122 static char mnemonic[32];
4125 /* Get the first 15 bytes and assume that the full name is included. */
4126 strncpy (mnemonic, str, 31);
4127 mnemonic[31] = '\0';
4129 /* Scan up to the end of the mnemonic, which must end in white space,
4130 '.', or end of string. */
4131 for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr)
4136 /* Append '...' to the truncated long name. */
4137 if (ptr - mnemonic == 31)
4138 mnemonic[28] = mnemonic[29] = mnemonic[30] = '.';
4144 reset_aarch64_instruction (aarch64_instruction *instruction)
4146 memset (instruction, '\0', sizeof (aarch64_instruction));
4147 instruction->reloc.type = BFD_RELOC_UNUSED;
4150 /* Data strutures storing one user error in the assembly code related to
4153 struct operand_error_record
4155 const aarch64_opcode *opcode;
4156 aarch64_operand_error detail;
4157 struct operand_error_record *next;
4160 typedef struct operand_error_record operand_error_record;
4162 struct operand_errors
4164 operand_error_record *head;
4165 operand_error_record *tail;
4168 typedef struct operand_errors operand_errors;
4170 /* Top-level data structure reporting user errors for the current line of
4172 The way md_assemble works is that all opcodes sharing the same mnemonic
4173 name are iterated to find a match to the assembly line. In this data
4174 structure, each of the such opcodes will have one operand_error_record
4175 allocated and inserted. In other words, excessive errors related with
4176 a single opcode are disregarded. */
4177 operand_errors operand_error_report;
4179 /* Free record nodes. */
4180 static operand_error_record *free_opnd_error_record_nodes = NULL;
4182 /* Initialize the data structure that stores the operand mismatch
4183 information on assembling one line of the assembly code. */
4185 init_operand_error_report (void)
4187 if (operand_error_report.head != NULL)
4189 gas_assert (operand_error_report.tail != NULL);
4190 operand_error_report.tail->next = free_opnd_error_record_nodes;
4191 free_opnd_error_record_nodes = operand_error_report.head;
4192 operand_error_report.head = NULL;
4193 operand_error_report.tail = NULL;
4196 gas_assert (operand_error_report.tail == NULL);
4199 /* Return TRUE if some operand error has been recorded during the
4200 parsing of the current assembly line using the opcode *OPCODE;
4201 otherwise return FALSE. */
4202 static inline bfd_boolean
4203 opcode_has_operand_error_p (const aarch64_opcode *opcode)
4205 operand_error_record *record = operand_error_report.head;
4206 return record && record->opcode == opcode;
4209 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4210 OPCODE field is initialized with OPCODE.
4211 N.B. only one record for each opcode, i.e. the maximum of one error is
4212 recorded for each instruction template. */
4215 add_operand_error_record (const operand_error_record* new_record)
4217 const aarch64_opcode *opcode = new_record->opcode;
4218 operand_error_record* record = operand_error_report.head;
4220 /* The record may have been created for this opcode. If not, we need
4222 if (! opcode_has_operand_error_p (opcode))
4224 /* Get one empty record. */
4225 if (free_opnd_error_record_nodes == NULL)
4227 record = XNEW (operand_error_record);
4231 record = free_opnd_error_record_nodes;
4232 free_opnd_error_record_nodes = record->next;
4234 record->opcode = opcode;
4235 /* Insert at the head. */
4236 record->next = operand_error_report.head;
4237 operand_error_report.head = record;
4238 if (operand_error_report.tail == NULL)
4239 operand_error_report.tail = record;
4241 else if (record->detail.kind != AARCH64_OPDE_NIL
4242 && record->detail.index <= new_record->detail.index
4243 && operand_error_higher_severity_p (record->detail.kind,
4244 new_record->detail.kind))
4246 /* In the case of multiple errors found on operands related with a
4247 single opcode, only record the error of the leftmost operand and
4248 only if the error is of higher severity. */
4249 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4250 " the existing error %s on operand %d",
4251 operand_mismatch_kind_names[new_record->detail.kind],
4252 new_record->detail.index,
4253 operand_mismatch_kind_names[record->detail.kind],
4254 record->detail.index);
4258 record->detail = new_record->detail;
4262 record_operand_error_info (const aarch64_opcode *opcode,
4263 aarch64_operand_error *error_info)
4265 operand_error_record record;
4266 record.opcode = opcode;
4267 record.detail = *error_info;
4268 add_operand_error_record (&record);
4271 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4272 error message *ERROR, for operand IDX (count from 0). */
4275 record_operand_error (const aarch64_opcode *opcode, int idx,
4276 enum aarch64_operand_error_kind kind,
4279 aarch64_operand_error info;
4280 memset(&info, 0, sizeof (info));
4284 record_operand_error_info (opcode, &info);
4288 record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
4289 enum aarch64_operand_error_kind kind,
4290 const char* error, const int *extra_data)
4292 aarch64_operand_error info;
4296 info.data[0] = extra_data[0];
4297 info.data[1] = extra_data[1];
4298 info.data[2] = extra_data[2];
4299 record_operand_error_info (opcode, &info);
4303 record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx,
4304 const char* error, int lower_bound,
4307 int data[3] = {lower_bound, upper_bound, 0};
4308 record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE,
4312 /* Remove the operand error record for *OPCODE. */
4313 static void ATTRIBUTE_UNUSED
4314 remove_operand_error_record (const aarch64_opcode *opcode)
4316 if (opcode_has_operand_error_p (opcode))
4318 operand_error_record* record = operand_error_report.head;
4319 gas_assert (record != NULL && operand_error_report.tail != NULL);
4320 operand_error_report.head = record->next;
4321 record->next = free_opnd_error_record_nodes;
4322 free_opnd_error_record_nodes = record;
4323 if (operand_error_report.head == NULL)
4325 gas_assert (operand_error_report.tail == record);
4326 operand_error_report.tail = NULL;
4331 /* Given the instruction in *INSTR, return the index of the best matched
4332 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4334 Return -1 if there is no qualifier sequence; return the first match
4335 if there is multiple matches found. */
4338 find_best_match (const aarch64_inst *instr,
4339 const aarch64_opnd_qualifier_seq_t *qualifiers_list)
4341 int i, num_opnds, max_num_matched, idx;
4343 num_opnds = aarch64_num_of_operands (instr->opcode);
4346 DEBUG_TRACE ("no operand");
4350 max_num_matched = 0;
4353 /* For each pattern. */
4354 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4357 const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
4359 /* Most opcodes has much fewer patterns in the list. */
4360 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
4362 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
4366 for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers)
4367 if (*qualifiers == instr->operands[j].qualifier)
4370 if (num_matched > max_num_matched)
4372 max_num_matched = num_matched;
4377 DEBUG_TRACE ("return with %d", idx);
4381 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4382 corresponding operands in *INSTR. */
4385 assign_qualifier_sequence (aarch64_inst *instr,
4386 const aarch64_opnd_qualifier_t *qualifiers)
4389 int num_opnds = aarch64_num_of_operands (instr->opcode);
4390 gas_assert (num_opnds);
4391 for (i = 0; i < num_opnds; ++i, ++qualifiers)
4392 instr->operands[i].qualifier = *qualifiers;
4395 /* Print operands for the diagnosis purpose. */
4398 print_operands (char *buf, const aarch64_opcode *opcode,
4399 const aarch64_opnd_info *opnds)
4403 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
4407 /* We regard the opcode operand info more, however we also look into
4408 the inst->operands to support the disassembling of the optional
4410 The two operand code should be the same in all cases, apart from
4411 when the operand can be optional. */
4412 if (opcode->operands[i] == AARCH64_OPND_NIL
4413 || opnds[i].type == AARCH64_OPND_NIL)
4416 /* Generate the operand string in STR. */
4417 aarch64_print_operand (str, sizeof (str), 0, opcode, opnds, i, NULL, NULL);
4421 strcat (buf, i == 0 ? " " : ",");
4423 /* Append the operand string. */
4428 /* Send to stderr a string as information. */
4431 output_info (const char *format, ...)
4437 file = as_where (&line);
4441 fprintf (stderr, "%s:%u: ", file, line);
4443 fprintf (stderr, "%s: ", file);
4445 fprintf (stderr, _("Info: "));
4446 va_start (args, format);
4447 vfprintf (stderr, format, args);
4449 (void) putc ('\n', stderr);
4452 /* Output one operand error record. */
4455 output_operand_error_record (const operand_error_record *record, char *str)
4457 const aarch64_operand_error *detail = &record->detail;
4458 int idx = detail->index;
4459 const aarch64_opcode *opcode = record->opcode;
4460 enum aarch64_opnd opd_code = (idx >= 0 ? opcode->operands[idx]
4461 : AARCH64_OPND_NIL);
4463 switch (detail->kind)
4465 case AARCH64_OPDE_NIL:
4469 case AARCH64_OPDE_SYNTAX_ERROR:
4470 case AARCH64_OPDE_RECOVERABLE:
4471 case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
4472 case AARCH64_OPDE_OTHER_ERROR:
4473 /* Use the prepared error message if there is, otherwise use the
4474 operand description string to describe the error. */
4475 if (detail->error != NULL)
4478 as_bad (_("%s -- `%s'"), detail->error, str);
4480 as_bad (_("%s at operand %d -- `%s'"),
4481 detail->error, idx + 1, str);
4485 gas_assert (idx >= 0);
4486 as_bad (_("operand %d should be %s -- `%s'"), idx + 1,
4487 aarch64_get_operand_desc (opd_code), str);
4491 case AARCH64_OPDE_INVALID_VARIANT:
4492 as_bad (_("operand mismatch -- `%s'"), str);
4493 if (verbose_error_p)
4495 /* We will try to correct the erroneous instruction and also provide
4496 more information e.g. all other valid variants.
4498 The string representation of the corrected instruction and other
4499 valid variants are generated by
4501 1) obtaining the intermediate representation of the erroneous
4503 2) manipulating the IR, e.g. replacing the operand qualifier;
4504 3) printing out the instruction by calling the printer functions
4505 shared with the disassembler.
4507 The limitation of this method is that the exact input assembly
4508 line cannot be accurately reproduced in some cases, for example an
4509 optional operand present in the actual assembly line will be
4510 omitted in the output; likewise for the optional syntax rules,
4511 e.g. the # before the immediate. Another limitation is that the
4512 assembly symbols and relocation operations in the assembly line
4513 currently cannot be printed out in the error report. Last but not
4514 least, when there is other error(s) co-exist with this error, the
4515 'corrected' instruction may be still incorrect, e.g. given
4516 'ldnp h0,h1,[x0,#6]!'
4517 this diagnosis will provide the version:
4518 'ldnp s0,s1,[x0,#6]!'
4519 which is still not right. */
4520 size_t len = strlen (get_mnemonic_name (str));
4524 aarch64_inst *inst_base = &inst.base;
4525 const aarch64_opnd_qualifier_seq_t *qualifiers_list;
4528 reset_aarch64_instruction (&inst);
4529 inst_base->opcode = opcode;
4531 /* Reset the error report so that there is no side effect on the
4532 following operand parsing. */
4533 init_operand_error_report ();
4536 result = parse_operands (str + len, opcode)
4537 && programmer_friendly_fixup (&inst);
4538 gas_assert (result);
4539 result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
4541 gas_assert (!result);
4543 /* Find the most matched qualifier sequence. */
4544 qlf_idx = find_best_match (inst_base, opcode->qualifiers_list);
4545 gas_assert (qlf_idx > -1);
4547 /* Assign the qualifiers. */
4548 assign_qualifier_sequence (inst_base,
4549 opcode->qualifiers_list[qlf_idx]);
4551 /* Print the hint. */
4552 output_info (_(" did you mean this?"));
4553 snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str));
4554 print_operands (buf, opcode, inst_base->operands);
4555 output_info (_(" %s"), buf);
4557 /* Print out other variant(s) if there is any. */
4559 !empty_qualifier_sequence_p (opcode->qualifiers_list[1]))
4560 output_info (_(" other valid variant(s):"));
4562 /* For each pattern. */
4563 qualifiers_list = opcode->qualifiers_list;
4564 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4566 /* Most opcodes has much fewer patterns in the list.
4567 First NIL qualifier indicates the end in the list. */
4568 if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
4573 /* Mnemonics name. */
4574 snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str));
4576 /* Assign the qualifiers. */
4577 assign_qualifier_sequence (inst_base, *qualifiers_list);
4579 /* Print instruction. */
4580 print_operands (buf, opcode, inst_base->operands);
4582 output_info (_(" %s"), buf);
4588 case AARCH64_OPDE_UNTIED_OPERAND:
4589 as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
4590 detail->index + 1, str);
4593 case AARCH64_OPDE_OUT_OF_RANGE:
4594 if (detail->data[0] != detail->data[1])
4595 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4596 detail->error ? detail->error : _("immediate value"),
4597 detail->data[0], detail->data[1], idx + 1, str);
4599 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4600 detail->error ? detail->error : _("immediate value"),
4601 detail->data[0], idx + 1, str);
4604 case AARCH64_OPDE_REG_LIST:
4605 if (detail->data[0] == 1)
4606 as_bad (_("invalid number of registers in the list; "
4607 "only 1 register is expected at operand %d -- `%s'"),
4610 as_bad (_("invalid number of registers in the list; "
4611 "%d registers are expected at operand %d -- `%s'"),
4612 detail->data[0], idx + 1, str);
4615 case AARCH64_OPDE_UNALIGNED:
4616 as_bad (_("immediate value should be a multiple of "
4617 "%d at operand %d -- `%s'"),
4618 detail->data[0], idx + 1, str);
4627 /* Process and output the error message about the operand mismatching.
4629 When this function is called, the operand error information had
4630 been collected for an assembly line and there will be multiple
4631 errors in the case of mulitple instruction templates; output the
4632 error message that most closely describes the problem. */
4635 output_operand_error_report (char *str)
4637 int largest_error_pos;
4638 const char *msg = NULL;
4639 enum aarch64_operand_error_kind kind;
4640 operand_error_record *curr;
4641 operand_error_record *head = operand_error_report.head;
4642 operand_error_record *record = NULL;
4644 /* No error to report. */
4648 gas_assert (head != NULL && operand_error_report.tail != NULL);
4650 /* Only one error. */
4651 if (head == operand_error_report.tail)
4653 DEBUG_TRACE ("single opcode entry with error kind: %s",
4654 operand_mismatch_kind_names[head->detail.kind]);
4655 output_operand_error_record (head, str);
4659 /* Find the error kind of the highest severity. */
4660 DEBUG_TRACE ("multiple opcode entres with error kind");
4661 kind = AARCH64_OPDE_NIL;
4662 for (curr = head; curr != NULL; curr = curr->next)
4664 gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
4665 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
4666 if (operand_error_higher_severity_p (curr->detail.kind, kind))
4667 kind = curr->detail.kind;
4669 gas_assert (kind != AARCH64_OPDE_NIL);
4671 /* Pick up one of errors of KIND to report. */
4672 largest_error_pos = -2; /* Index can be -1 which means unknown index. */
4673 for (curr = head; curr != NULL; curr = curr->next)
4675 if (curr->detail.kind != kind)
4677 /* If there are multiple errors, pick up the one with the highest
4678 mismatching operand index. In the case of multiple errors with
4679 the equally highest operand index, pick up the first one or the
4680 first one with non-NULL error message. */
4681 if (curr->detail.index > largest_error_pos
4682 || (curr->detail.index == largest_error_pos && msg == NULL
4683 && curr->detail.error != NULL))
4685 largest_error_pos = curr->detail.index;
4687 msg = record->detail.error;
4691 gas_assert (largest_error_pos != -2 && record != NULL);
4692 DEBUG_TRACE ("Pick up error kind %s to report",
4693 operand_mismatch_kind_names[record->detail.kind]);
4696 output_operand_error_record (record, str);
4699 /* Write an AARCH64 instruction to buf - always little-endian. */
4701 put_aarch64_insn (char *buf, uint32_t insn)
4703 unsigned char *where = (unsigned char *) buf;
4705 where[1] = insn >> 8;
4706 where[2] = insn >> 16;
4707 where[3] = insn >> 24;
4711 get_aarch64_insn (char *buf)
4713 unsigned char *where = (unsigned char *) buf;
4715 result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
4720 output_inst (struct aarch64_inst *new_inst)
4724 to = frag_more (INSN_SIZE);
4726 frag_now->tc_frag_data.recorded = 1;
4728 put_aarch64_insn (to, inst.base.value);
4730 if (inst.reloc.type != BFD_RELOC_UNUSED)
4732 fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal,
4733 INSN_SIZE, &inst.reloc.exp,
4736 DEBUG_TRACE ("Prepared relocation fix up");
4737 /* Don't check the addend value against the instruction size,
4738 that's the job of our code in md_apply_fix(). */
4739 fixp->fx_no_overflow = 1;
4740 if (new_inst != NULL)
4741 fixp->tc_fix_data.inst = new_inst;
4742 if (aarch64_gas_internal_fixup_p ())
4744 gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL);
4745 fixp->tc_fix_data.opnd = inst.reloc.opnd;
4746 fixp->fx_addnumber = inst.reloc.flags;
4750 dwarf2_emit_insn (INSN_SIZE);
4753 /* Link together opcodes of the same name. */
4757 aarch64_opcode *opcode;
4758 struct templates *next;
4761 typedef struct templates templates;
4764 lookup_mnemonic (const char *start, int len)
4766 templates *templ = NULL;
4768 templ = hash_find_n (aarch64_ops_hsh, start, len);
4772 /* Subroutine of md_assemble, responsible for looking up the primary
4773 opcode from the mnemonic the user wrote. STR points to the
4774 beginning of the mnemonic. */
4777 opcode_lookup (char **str)
4780 const aarch64_cond *cond;
4784 /* Scan up to the end of the mnemonic, which must end in white space,
4785 '.', or end of string. */
4786 for (base = end = *str; is_part_of_name(*end); end++)
4793 inst.cond = COND_ALWAYS;
4795 /* Handle a possible condition. */
4798 cond = hash_find_n (aarch64_cond_hsh, end + 1, 2);
4801 inst.cond = cond->value;
4815 if (inst.cond == COND_ALWAYS)
4817 /* Look for unaffixed mnemonic. */
4818 return lookup_mnemonic (base, len);
4822 /* append ".c" to mnemonic if conditional */
4823 memcpy (condname, base, len);
4824 memcpy (condname + len, ".c", 2);
4827 return lookup_mnemonic (base, len);
4833 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4834 to a corresponding operand qualifier. */
4836 static inline aarch64_opnd_qualifier_t
4837 vectype_to_qualifier (const struct vector_type_el *vectype)
4839 /* Element size in bytes indexed by vector_el_type. */
4840 const unsigned char ele_size[5]
4842 const unsigned int ele_base [5] =
4844 AARCH64_OPND_QLF_V_8B,
4845 AARCH64_OPND_QLF_V_2H,
4846 AARCH64_OPND_QLF_V_2S,
4847 AARCH64_OPND_QLF_V_1D,
4848 AARCH64_OPND_QLF_V_1Q
4851 if (!vectype->defined || vectype->type == NT_invtype)
4852 goto vectype_conversion_fail;
4854 if (vectype->type == NT_zero)
4855 return AARCH64_OPND_QLF_P_Z;
4856 if (vectype->type == NT_merge)
4857 return AARCH64_OPND_QLF_P_M;
4859 gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
4861 if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
4862 /* Vector element register. */
4863 return AARCH64_OPND_QLF_S_B + vectype->type;
4866 /* Vector register. */
4867 int reg_size = ele_size[vectype->type] * vectype->width;
4870 if (reg_size != 16 && reg_size != 8 && reg_size != 4)
4871 goto vectype_conversion_fail;
4873 /* The conversion is by calculating the offset from the base operand
4874 qualifier for the vector type. The operand qualifiers are regular
4875 enough that the offset can established by shifting the vector width by
4876 a vector-type dependent amount. */
4878 if (vectype->type == NT_b)
4880 else if (vectype->type == NT_h || vectype->type == NT_s)
4882 else if (vectype->type >= NT_d)
4887 offset = ele_base [vectype->type] + (vectype->width >> shift);
4888 gas_assert (AARCH64_OPND_QLF_V_8B <= offset
4889 && offset <= AARCH64_OPND_QLF_V_1Q);
4893 vectype_conversion_fail:
4894 first_error (_("bad vector arrangement type"));
4895 return AARCH64_OPND_QLF_NIL;
4898 /* Process an optional operand that is found omitted from the assembly line.
4899 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4900 instruction's opcode entry while IDX is the index of this omitted operand.
4904 process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
4905 int idx, aarch64_opnd_info *operand)
4907 aarch64_insn default_value = get_optional_operand_default_value (opcode);
4908 gas_assert (optional_operand_p (opcode, idx));
4909 gas_assert (!operand->present);
4913 case AARCH64_OPND_Rd:
4914 case AARCH64_OPND_Rn:
4915 case AARCH64_OPND_Rm:
4916 case AARCH64_OPND_Rt:
4917 case AARCH64_OPND_Rt2:
4918 case AARCH64_OPND_Rs:
4919 case AARCH64_OPND_Ra:
4920 case AARCH64_OPND_Rt_SYS:
4921 case AARCH64_OPND_Rd_SP:
4922 case AARCH64_OPND_Rn_SP:
4923 case AARCH64_OPND_Fd:
4924 case AARCH64_OPND_Fn:
4925 case AARCH64_OPND_Fm:
4926 case AARCH64_OPND_Fa:
4927 case AARCH64_OPND_Ft:
4928 case AARCH64_OPND_Ft2:
4929 case AARCH64_OPND_Sd:
4930 case AARCH64_OPND_Sn:
4931 case AARCH64_OPND_Sm:
4932 case AARCH64_OPND_Vd:
4933 case AARCH64_OPND_Vn:
4934 case AARCH64_OPND_Vm:
4935 case AARCH64_OPND_VdD1:
4936 case AARCH64_OPND_VnD1:
4937 operand->reg.regno = default_value;
4940 case AARCH64_OPND_Ed:
4941 case AARCH64_OPND_En:
4942 case AARCH64_OPND_Em:
4943 operand->reglane.regno = default_value;
4946 case AARCH64_OPND_IDX:
4947 case AARCH64_OPND_BIT_NUM:
4948 case AARCH64_OPND_IMMR:
4949 case AARCH64_OPND_IMMS:
4950 case AARCH64_OPND_SHLL_IMM:
4951 case AARCH64_OPND_IMM_VLSL:
4952 case AARCH64_OPND_IMM_VLSR:
4953 case AARCH64_OPND_CCMP_IMM:
4954 case AARCH64_OPND_FBITS:
4955 case AARCH64_OPND_UIMM4:
4956 case AARCH64_OPND_UIMM3_OP1:
4957 case AARCH64_OPND_UIMM3_OP2:
4958 case AARCH64_OPND_IMM:
4959 case AARCH64_OPND_WIDTH:
4960 case AARCH64_OPND_UIMM7:
4961 case AARCH64_OPND_NZCV:
4962 case AARCH64_OPND_SVE_PATTERN:
4963 case AARCH64_OPND_SVE_PRFOP:
4964 operand->imm.value = default_value;
4967 case AARCH64_OPND_SVE_PATTERN_SCALED:
4968 operand->imm.value = default_value;
4969 operand->shifter.kind = AARCH64_MOD_MUL;
4970 operand->shifter.amount = 1;
4973 case AARCH64_OPND_EXCEPTION:
4974 inst.reloc.type = BFD_RELOC_UNUSED;
4977 case AARCH64_OPND_BARRIER_ISB:
4978 operand->barrier = aarch64_barrier_options + default_value;
4985 /* Process the relocation type for move wide instructions.
4986 Return TRUE on success; otherwise return FALSE. */
4989 process_movw_reloc_info (void)
4994 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
4996 if (inst.base.opcode->op == OP_MOVK)
4997 switch (inst.reloc.type)
4999 case BFD_RELOC_AARCH64_MOVW_G0_S:
5000 case BFD_RELOC_AARCH64_MOVW_G1_S:
5001 case BFD_RELOC_AARCH64_MOVW_G2_S:
5002 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
5003 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
5004 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
5005 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
5007 (_("the specified relocation type is not allowed for MOVK"));
5013 switch (inst.reloc.type)
5015 case BFD_RELOC_AARCH64_MOVW_G0:
5016 case BFD_RELOC_AARCH64_MOVW_G0_NC:
5017 case BFD_RELOC_AARCH64_MOVW_G0_S:
5018 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
5019 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
5020 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
5021 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
5022 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
5023 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
5024 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
5025 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
5028 case BFD_RELOC_AARCH64_MOVW_G1:
5029 case BFD_RELOC_AARCH64_MOVW_G1_NC:
5030 case BFD_RELOC_AARCH64_MOVW_G1_S:
5031 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
5032 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
5033 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
5034 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
5035 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
5036 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
5037 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
5038 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
5041 case BFD_RELOC_AARCH64_MOVW_G2:
5042 case BFD_RELOC_AARCH64_MOVW_G2_NC:
5043 case BFD_RELOC_AARCH64_MOVW_G2_S:
5044 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
5045 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
5048 set_fatal_syntax_error
5049 (_("the specified relocation type is not allowed for 32-bit "
5055 case BFD_RELOC_AARCH64_MOVW_G3:
5058 set_fatal_syntax_error
5059 (_("the specified relocation type is not allowed for 32-bit "
5066 /* More cases should be added when more MOVW-related relocation types
5067 are supported in GAS. */
5068 gas_assert (aarch64_gas_internal_fixup_p ());
5069 /* The shift amount should have already been set by the parser. */
5072 inst.base.operands[1].shifter.amount = shift;
5076 /* A primitive log caculator. */
5078 static inline unsigned int
5079 get_logsz (unsigned int size)
5081 const unsigned char ls[16] =
5082 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5088 gas_assert (ls[size - 1] != (unsigned char)-1);
5089 return ls[size - 1];
5092 /* Determine and return the real reloc type code for an instruction
5093 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5095 static inline bfd_reloc_code_real_type
5096 ldst_lo12_determine_real_reloc_type (void)
5099 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
5100 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
5102 const bfd_reloc_code_real_type reloc_ldst_lo12[3][5] = {
5104 BFD_RELOC_AARCH64_LDST8_LO12,
5105 BFD_RELOC_AARCH64_LDST16_LO12,
5106 BFD_RELOC_AARCH64_LDST32_LO12,
5107 BFD_RELOC_AARCH64_LDST64_LO12,
5108 BFD_RELOC_AARCH64_LDST128_LO12
5111 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12,
5112 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12,
5113 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12,
5114 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12,
5115 BFD_RELOC_AARCH64_NONE
5118 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC,
5119 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC,
5120 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
5121 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
5122 BFD_RELOC_AARCH64_NONE
5126 gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
5127 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5129 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC));
5130 gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
5132 if (opd1_qlf == AARCH64_OPND_QLF_NIL)
5134 aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list,
5136 gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
5138 logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
5139 if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5140 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
5141 gas_assert (logsz <= 3);
5143 gas_assert (logsz <= 4);
5145 /* In reloc.c, these pseudo relocation types should be defined in similar
5146 order as above reloc_ldst_lo12 array. Because the array index calcuation
5147 below relies on this. */
5148 return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
5151 /* Check whether a register list REGINFO is valid. The registers must be
5152 numbered in increasing order (modulo 32), in increments of one or two.
5154 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5157 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5160 reg_list_valid_p (uint32_t reginfo, int accept_alternate)
5162 uint32_t i, nb_regs, prev_regno, incr;
5164 nb_regs = 1 + (reginfo & 0x3);
5166 prev_regno = reginfo & 0x1f;
5167 incr = accept_alternate ? 2 : 1;
5169 for (i = 1; i < nb_regs; ++i)
5171 uint32_t curr_regno;
5173 curr_regno = reginfo & 0x1f;
5174 if (curr_regno != ((prev_regno + incr) & 0x1f))
5176 prev_regno = curr_regno;
5182 /* Generic instruction operand parser. This does no encoding and no
5183 semantic validation; it merely squirrels values away in the inst
5184 structure. Returns TRUE or FALSE depending on whether the
5185 specified grammar matched. */
5188 parse_operands (char *str, const aarch64_opcode *opcode)
5191 char *backtrack_pos = 0;
5192 const enum aarch64_opnd *operands = opcode->operands;
5193 aarch64_reg_type imm_reg_type;
5196 skip_whitespace (str);
5198 imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
5200 for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
5203 const reg_entry *reg;
5204 int comma_skipped_p = 0;
5205 aarch64_reg_type rtype;
5206 struct vector_type_el vectype;
5207 aarch64_opnd_qualifier_t qualifier, base_qualifier, offset_qualifier;
5208 aarch64_opnd_info *info = &inst.base.operands[i];
5209 aarch64_reg_type reg_type;
5211 DEBUG_TRACE ("parse operand %d", i);
5213 /* Assign the operand code. */
5214 info->type = operands[i];
5216 if (optional_operand_p (opcode, i))
5218 /* Remember where we are in case we need to backtrack. */
5219 gas_assert (!backtrack_pos);
5220 backtrack_pos = str;
5223 /* Expect comma between operands; the backtrack mechanizm will take
5224 care of cases of omitted optional operand. */
5225 if (i > 0 && ! skip_past_char (&str, ','))
5227 set_syntax_error (_("comma expected between operands"));
5231 comma_skipped_p = 1;
5233 switch (operands[i])
5235 case AARCH64_OPND_Rd:
5236 case AARCH64_OPND_Rn:
5237 case AARCH64_OPND_Rm:
5238 case AARCH64_OPND_Rt:
5239 case AARCH64_OPND_Rt2:
5240 case AARCH64_OPND_Rs:
5241 case AARCH64_OPND_Ra:
5242 case AARCH64_OPND_Rt_SYS:
5243 case AARCH64_OPND_PAIRREG:
5244 po_int_reg_or_fail (REG_TYPE_R_Z);
5247 case AARCH64_OPND_Rd_SP:
5248 case AARCH64_OPND_Rn_SP:
5249 po_int_reg_or_fail (REG_TYPE_R_SP);
5252 case AARCH64_OPND_Rm_EXT:
5253 case AARCH64_OPND_Rm_SFT:
5254 po_misc_or_fail (parse_shifter_operand
5255 (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT
5257 : SHIFTED_LOGIC_IMM)));
5258 if (!info->shifter.operator_present)
5260 /* Default to LSL if not present. Libopcodes prefers shifter
5261 kind to be explicit. */
5262 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5263 info->shifter.kind = AARCH64_MOD_LSL;
5264 /* For Rm_EXT, libopcodes will carry out further check on whether
5265 or not stack pointer is used in the instruction (Recall that
5266 "the extend operator is not optional unless at least one of
5267 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5271 case AARCH64_OPND_Fd:
5272 case AARCH64_OPND_Fn:
5273 case AARCH64_OPND_Fm:
5274 case AARCH64_OPND_Fa:
5275 case AARCH64_OPND_Ft:
5276 case AARCH64_OPND_Ft2:
5277 case AARCH64_OPND_Sd:
5278 case AARCH64_OPND_Sn:
5279 case AARCH64_OPND_Sm:
5280 val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
5281 if (val == PARSE_FAIL)
5283 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
5286 gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
5288 info->reg.regno = val;
5289 info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
5292 case AARCH64_OPND_SVE_Pd:
5293 case AARCH64_OPND_SVE_Pg3:
5294 case AARCH64_OPND_SVE_Pg4_5:
5295 case AARCH64_OPND_SVE_Pg4_10:
5296 case AARCH64_OPND_SVE_Pg4_16:
5297 case AARCH64_OPND_SVE_Pm:
5298 case AARCH64_OPND_SVE_Pn:
5299 case AARCH64_OPND_SVE_Pt:
5300 reg_type = REG_TYPE_PN;
5303 case AARCH64_OPND_SVE_Za_5:
5304 case AARCH64_OPND_SVE_Za_16:
5305 case AARCH64_OPND_SVE_Zd:
5306 case AARCH64_OPND_SVE_Zm_5:
5307 case AARCH64_OPND_SVE_Zm_16:
5308 case AARCH64_OPND_SVE_Zn:
5309 case AARCH64_OPND_SVE_Zt:
5310 reg_type = REG_TYPE_ZN;
5313 case AARCH64_OPND_Vd:
5314 case AARCH64_OPND_Vn:
5315 case AARCH64_OPND_Vm:
5316 reg_type = REG_TYPE_VN;
5318 val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
5319 if (val == PARSE_FAIL)
5321 first_error (_(get_reg_expected_msg (reg_type)));
5324 if (vectype.defined & NTA_HASINDEX)
5327 info->reg.regno = val;
5328 if ((reg_type == REG_TYPE_PN || reg_type == REG_TYPE_ZN)
5329 && vectype.type == NT_invtype)
5330 /* Unqualified Pn and Zn registers are allowed in certain
5331 contexts. Rely on F_STRICT qualifier checking to catch
5333 info->qualifier = AARCH64_OPND_QLF_NIL;
5336 info->qualifier = vectype_to_qualifier (&vectype);
5337 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5342 case AARCH64_OPND_VdD1:
5343 case AARCH64_OPND_VnD1:
5344 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
5345 if (val == PARSE_FAIL)
5347 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
5350 if (vectype.type != NT_d || vectype.index != 1)
5352 set_fatal_syntax_error
5353 (_("the top half of a 128-bit FP/SIMD register is expected"));
5356 info->reg.regno = val;
5357 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5358 here; it is correct for the purpose of encoding/decoding since
5359 only the register number is explicitly encoded in the related
5360 instructions, although this appears a bit hacky. */
5361 info->qualifier = AARCH64_OPND_QLF_S_D;
5364 case AARCH64_OPND_SVE_Zn_INDEX:
5365 reg_type = REG_TYPE_ZN;
5366 goto vector_reg_index;
5368 case AARCH64_OPND_Ed:
5369 case AARCH64_OPND_En:
5370 case AARCH64_OPND_Em:
5371 reg_type = REG_TYPE_VN;
5373 val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
5374 if (val == PARSE_FAIL)
5376 first_error (_(get_reg_expected_msg (reg_type)));
5379 if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
5382 info->reglane.regno = val;
5383 info->reglane.index = vectype.index;
5384 info->qualifier = vectype_to_qualifier (&vectype);
5385 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5389 case AARCH64_OPND_SVE_ZnxN:
5390 case AARCH64_OPND_SVE_ZtxN:
5391 reg_type = REG_TYPE_ZN;
5392 goto vector_reg_list;
5394 case AARCH64_OPND_LVn:
5395 case AARCH64_OPND_LVt:
5396 case AARCH64_OPND_LVt_AL:
5397 case AARCH64_OPND_LEt:
5398 reg_type = REG_TYPE_VN;
5400 if (reg_type == REG_TYPE_ZN
5401 && get_opcode_dependent_value (opcode) == 1
5404 val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
5405 if (val == PARSE_FAIL)
5407 first_error (_(get_reg_expected_msg (reg_type)));
5410 info->reglist.first_regno = val;
5411 info->reglist.num_regs = 1;
5415 val = parse_vector_reg_list (&str, reg_type, &vectype);
5416 if (val == PARSE_FAIL)
5418 if (! reg_list_valid_p (val, /* accept_alternate */ 0))
5420 set_fatal_syntax_error (_("invalid register list"));
5423 info->reglist.first_regno = (val >> 2) & 0x1f;
5424 info->reglist.num_regs = (val & 0x3) + 1;
5426 if (operands[i] == AARCH64_OPND_LEt)
5428 if (!(vectype.defined & NTA_HASINDEX))
5430 info->reglist.has_index = 1;
5431 info->reglist.index = vectype.index;
5435 if (vectype.defined & NTA_HASINDEX)
5437 if (!(vectype.defined & NTA_HASTYPE))
5439 if (reg_type == REG_TYPE_ZN)
5440 set_fatal_syntax_error (_("missing type suffix"));
5444 info->qualifier = vectype_to_qualifier (&vectype);
5445 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5449 case AARCH64_OPND_Cn:
5450 case AARCH64_OPND_Cm:
5451 po_reg_or_fail (REG_TYPE_CN);
5454 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN)));
5457 inst.base.operands[i].reg.regno = val;
5460 case AARCH64_OPND_SHLL_IMM:
5461 case AARCH64_OPND_IMM_VLSR:
5462 po_imm_or_fail (1, 64);
5463 info->imm.value = val;
5466 case AARCH64_OPND_CCMP_IMM:
5467 case AARCH64_OPND_FBITS:
5468 case AARCH64_OPND_UIMM4:
5469 case AARCH64_OPND_UIMM3_OP1:
5470 case AARCH64_OPND_UIMM3_OP2:
5471 case AARCH64_OPND_IMM_VLSL:
5472 case AARCH64_OPND_IMM:
5473 case AARCH64_OPND_WIDTH:
5474 po_imm_nc_or_fail ();
5475 info->imm.value = val;
5478 case AARCH64_OPND_SVE_PATTERN:
5479 po_enum_or_fail (aarch64_sve_pattern_array);
5480 info->imm.value = val;
5483 case AARCH64_OPND_SVE_PATTERN_SCALED:
5484 po_enum_or_fail (aarch64_sve_pattern_array);
5485 info->imm.value = val;
5486 if (skip_past_comma (&str)
5487 && !parse_shift (&str, info, SHIFTED_MUL))
5489 if (!info->shifter.operator_present)
5491 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5492 info->shifter.kind = AARCH64_MOD_MUL;
5493 info->shifter.amount = 1;
5497 case AARCH64_OPND_SVE_PRFOP:
5498 po_enum_or_fail (aarch64_sve_prfop_array);
5499 info->imm.value = val;
5502 case AARCH64_OPND_UIMM7:
5503 po_imm_or_fail (0, 127);
5504 info->imm.value = val;
5507 case AARCH64_OPND_IDX:
5508 case AARCH64_OPND_BIT_NUM:
5509 case AARCH64_OPND_IMMR:
5510 case AARCH64_OPND_IMMS:
5511 po_imm_or_fail (0, 63);
5512 info->imm.value = val;
5515 case AARCH64_OPND_IMM0:
5516 po_imm_nc_or_fail ();
5519 set_fatal_syntax_error (_("immediate zero expected"));
5522 info->imm.value = 0;
5525 case AARCH64_OPND_FPIMM0:
5528 bfd_boolean res1 = FALSE, res2 = FALSE;
5529 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5530 it is probably not worth the effort to support it. */
5531 if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE,
5534 || !(res2 = parse_constant_immediate (&str, &val,
5537 if ((res1 && qfloat == 0) || (res2 && val == 0))
5539 info->imm.value = 0;
5540 info->imm.is_fp = 1;
5543 set_fatal_syntax_error (_("immediate zero expected"));
5547 case AARCH64_OPND_IMM_MOV:
5550 if (reg_name_p (str, REG_TYPE_R_Z_SP) ||
5551 reg_name_p (str, REG_TYPE_VN))
5554 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5556 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5557 later. fix_mov_imm_insn will try to determine a machine
5558 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5559 message if the immediate cannot be moved by a single
5561 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5562 inst.base.operands[i].skip = 1;
5566 case AARCH64_OPND_SIMD_IMM:
5567 case AARCH64_OPND_SIMD_IMM_SFT:
5568 if (! parse_big_immediate (&str, &val, imm_reg_type))
5570 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5572 /* need_libopcodes_p */ 1,
5575 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5576 shift, we don't check it here; we leave the checking to
5577 the libopcodes (operand_general_constraint_met_p). By
5578 doing this, we achieve better diagnostics. */
5579 if (skip_past_comma (&str)
5580 && ! parse_shift (&str, info, SHIFTED_LSL_MSL))
5582 if (!info->shifter.operator_present
5583 && info->type == AARCH64_OPND_SIMD_IMM_SFT)
5585 /* Default to LSL if not present. Libopcodes prefers shifter
5586 kind to be explicit. */
5587 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5588 info->shifter.kind = AARCH64_MOD_LSL;
5592 case AARCH64_OPND_FPIMM:
5593 case AARCH64_OPND_SIMD_FPIMM:
5597 = (aarch64_get_qualifier_esize (inst.base.operands[0].qualifier)
5599 if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type)
5600 || !aarch64_imm_float_p (qfloat))
5603 set_fatal_syntax_error (_("invalid floating-point"
5607 inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat);
5608 inst.base.operands[i].imm.is_fp = 1;
5612 case AARCH64_OPND_LIMM:
5613 po_misc_or_fail (parse_shifter_operand (&str, info,
5614 SHIFTED_LOGIC_IMM));
5615 if (info->shifter.operator_present)
5617 set_fatal_syntax_error
5618 (_("shift not allowed for bitmask immediate"));
5621 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5623 /* need_libopcodes_p */ 1,
5627 case AARCH64_OPND_AIMM:
5628 if (opcode->op == OP_ADD)
5629 /* ADD may have relocation types. */
5630 po_misc_or_fail (parse_shifter_operand_reloc (&str, info,
5631 SHIFTED_ARITH_IMM));
5633 po_misc_or_fail (parse_shifter_operand (&str, info,
5634 SHIFTED_ARITH_IMM));
5635 switch (inst.reloc.type)
5637 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
5638 info->shifter.amount = 12;
5640 case BFD_RELOC_UNUSED:
5641 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
5642 if (info->shifter.kind != AARCH64_MOD_NONE)
5643 inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT;
5644 inst.reloc.pc_rel = 0;
5649 info->imm.value = 0;
5650 if (!info->shifter.operator_present)
5652 /* Default to LSL if not present. Libopcodes prefers shifter
5653 kind to be explicit. */
5654 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5655 info->shifter.kind = AARCH64_MOD_LSL;
5659 case AARCH64_OPND_HALF:
5661 /* #<imm16> or relocation. */
5662 int internal_fixup_p;
5663 po_misc_or_fail (parse_half (&str, &internal_fixup_p));
5664 if (internal_fixup_p)
5665 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
5666 skip_whitespace (str);
5667 if (skip_past_comma (&str))
5669 /* {, LSL #<shift>} */
5670 if (! aarch64_gas_internal_fixup_p ())
5672 set_fatal_syntax_error (_("can't mix relocation modifier "
5673 "with explicit shift"));
5676 po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
5679 inst.base.operands[i].shifter.amount = 0;
5680 inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
5681 inst.base.operands[i].imm.value = 0;
5682 if (! process_movw_reloc_info ())
5687 case AARCH64_OPND_EXCEPTION:
5688 po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp,
5690 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5692 /* need_libopcodes_p */ 0,
5696 case AARCH64_OPND_NZCV:
5698 const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4);
5702 info->imm.value = nzcv->value;
5705 po_imm_or_fail (0, 15);
5706 info->imm.value = val;
5710 case AARCH64_OPND_COND:
5711 case AARCH64_OPND_COND1:
5712 info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
5714 if (info->cond == NULL)
5716 set_syntax_error (_("invalid condition"));
5719 else if (operands[i] == AARCH64_OPND_COND1
5720 && (info->cond->value & 0xe) == 0xe)
5722 /* Not allow AL or NV. */
5723 set_default_error ();
5728 case AARCH64_OPND_ADDR_ADRP:
5729 po_misc_or_fail (parse_adrp (&str));
5730 /* Clear the value as operand needs to be relocated. */
5731 info->imm.value = 0;
5734 case AARCH64_OPND_ADDR_PCREL14:
5735 case AARCH64_OPND_ADDR_PCREL19:
5736 case AARCH64_OPND_ADDR_PCREL21:
5737 case AARCH64_OPND_ADDR_PCREL26:
5738 po_misc_or_fail (parse_address (&str, info));
5739 if (!info->addr.pcrel)
5741 set_syntax_error (_("invalid pc-relative address"));
5744 if (inst.gen_lit_pool
5745 && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT))
5747 /* Only permit "=value" in the literal load instructions.
5748 The literal will be generated by programmer_friendly_fixup. */
5749 set_syntax_error (_("invalid use of \"=immediate\""));
5752 if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str))
5754 set_syntax_error (_("unrecognized relocation suffix"));
5757 if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
5759 info->imm.value = inst.reloc.exp.X_add_number;
5760 inst.reloc.type = BFD_RELOC_UNUSED;
5764 info->imm.value = 0;
5765 if (inst.reloc.type == BFD_RELOC_UNUSED)
5766 switch (opcode->iclass)
5770 /* e.g. CBZ or B.COND */
5771 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5772 inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
5776 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
5777 inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
5781 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
5783 (opcode->op == OP_BL) ? BFD_RELOC_AARCH64_CALL26
5784 : BFD_RELOC_AARCH64_JUMP26;
5787 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5788 inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
5791 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
5792 inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
5798 inst.reloc.pc_rel = 1;
5802 case AARCH64_OPND_ADDR_SIMPLE:
5803 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
5805 /* [<Xn|SP>{, #<simm>}] */
5807 /* First use the normal address-parsing routines, to get
5808 the usual syntax errors. */
5809 po_misc_or_fail (parse_address (&str, info));
5810 if (info->addr.pcrel || info->addr.offset.is_reg
5811 || !info->addr.preind || info->addr.postind
5812 || info->addr.writeback)
5814 set_syntax_error (_("invalid addressing mode"));
5818 /* Then retry, matching the specific syntax of these addresses. */
5820 po_char_or_fail ('[');
5821 po_reg_or_fail (REG_TYPE_R64_SP);
5822 /* Accept optional ", #0". */
5823 if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
5824 && skip_past_char (&str, ','))
5826 skip_past_char (&str, '#');
5827 if (! skip_past_char (&str, '0'))
5829 set_fatal_syntax_error
5830 (_("the optional immediate offset can only be 0"));
5834 po_char_or_fail (']');
5838 case AARCH64_OPND_ADDR_REGOFF:
5839 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5840 po_misc_or_fail (parse_address (&str, info));
5842 if (info->addr.pcrel || !info->addr.offset.is_reg
5843 || !info->addr.preind || info->addr.postind
5844 || info->addr.writeback)
5846 set_syntax_error (_("invalid addressing mode"));
5849 if (!info->shifter.operator_present)
5851 /* Default to LSL if not present. Libopcodes prefers shifter
5852 kind to be explicit. */
5853 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5854 info->shifter.kind = AARCH64_MOD_LSL;
5856 /* Qualifier to be deduced by libopcodes. */
5859 case AARCH64_OPND_ADDR_SIMM7:
5860 po_misc_or_fail (parse_address (&str, info));
5861 if (info->addr.pcrel || info->addr.offset.is_reg
5862 || (!info->addr.preind && !info->addr.postind))
5864 set_syntax_error (_("invalid addressing mode"));
5867 if (inst.reloc.type != BFD_RELOC_UNUSED)
5869 set_syntax_error (_("relocation not allowed"));
5872 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5874 /* need_libopcodes_p */ 1,
5878 case AARCH64_OPND_ADDR_SIMM9:
5879 case AARCH64_OPND_ADDR_SIMM9_2:
5880 po_misc_or_fail (parse_address (&str, info));
5881 if (info->addr.pcrel || info->addr.offset.is_reg
5882 || (!info->addr.preind && !info->addr.postind)
5883 || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
5884 && info->addr.writeback))
5886 set_syntax_error (_("invalid addressing mode"));
5889 if (inst.reloc.type != BFD_RELOC_UNUSED)
5891 set_syntax_error (_("relocation not allowed"));
5894 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5896 /* need_libopcodes_p */ 1,
5900 case AARCH64_OPND_ADDR_UIMM12:
5901 po_misc_or_fail (parse_address (&str, info));
5902 if (info->addr.pcrel || info->addr.offset.is_reg
5903 || !info->addr.preind || info->addr.writeback)
5905 set_syntax_error (_("invalid addressing mode"));
5908 if (inst.reloc.type == BFD_RELOC_UNUSED)
5909 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5910 else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
5912 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12)
5914 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC))
5915 inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
5916 /* Leave qualifier to be determined by libopcodes. */
5919 case AARCH64_OPND_SIMD_ADDR_POST:
5920 /* [<Xn|SP>], <Xm|#<amount>> */
5921 po_misc_or_fail (parse_address (&str, info));
5922 if (!info->addr.postind || !info->addr.writeback)
5924 set_syntax_error (_("invalid addressing mode"));
5927 if (!info->addr.offset.is_reg)
5929 if (inst.reloc.exp.X_op == O_constant)
5930 info->addr.offset.imm = inst.reloc.exp.X_add_number;
5933 set_fatal_syntax_error
5934 (_("writeback value should be an immediate constant"));
5941 case AARCH64_OPND_SVE_ADDR_RI_U6:
5942 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
5943 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
5944 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
5946 but recognizing SVE registers. */
5947 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
5948 &offset_qualifier));
5949 if (base_qualifier != AARCH64_OPND_QLF_X)
5951 set_syntax_error (_("invalid addressing mode"));
5955 if (info->addr.pcrel || info->addr.offset.is_reg
5956 || !info->addr.preind || info->addr.writeback)
5958 set_syntax_error (_("invalid addressing mode"));
5961 if (inst.reloc.type != BFD_RELOC_UNUSED
5962 || inst.reloc.exp.X_op != O_constant)
5964 /* Make sure this has priority over
5965 "invalid addressing mode". */
5966 set_fatal_syntax_error (_("constant offset required"));
5969 info->addr.offset.imm = inst.reloc.exp.X_add_number;
5972 case AARCH64_OPND_SVE_ADDR_RR:
5973 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
5974 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
5975 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
5976 case AARCH64_OPND_SVE_ADDR_RX:
5977 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
5978 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
5979 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
5980 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
5981 but recognizing SVE registers. */
5982 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
5983 &offset_qualifier));
5984 if (base_qualifier != AARCH64_OPND_QLF_X
5985 || offset_qualifier != AARCH64_OPND_QLF_X)
5987 set_syntax_error (_("invalid addressing mode"));
5992 case AARCH64_OPND_SVE_ADDR_RZ:
5993 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
5994 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
5995 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
5996 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
5997 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
5998 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
5999 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
6000 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
6001 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
6002 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
6003 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
6004 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6005 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6006 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
6007 &offset_qualifier));
6008 if (base_qualifier != AARCH64_OPND_QLF_X
6009 || (offset_qualifier != AARCH64_OPND_QLF_S_S
6010 && offset_qualifier != AARCH64_OPND_QLF_S_D))
6012 set_syntax_error (_("invalid addressing mode"));
6015 info->qualifier = offset_qualifier;
6018 case AARCH64_OPND_SVE_ADDR_ZI_U5:
6019 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
6020 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
6021 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
6022 /* [Z<n>.<T>{, #imm}] */
6023 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
6024 &offset_qualifier));
6025 if (base_qualifier != AARCH64_OPND_QLF_S_S
6026 && base_qualifier != AARCH64_OPND_QLF_S_D)
6028 set_syntax_error (_("invalid addressing mode"));
6031 info->qualifier = base_qualifier;
6034 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
6035 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
6036 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
6037 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6038 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6042 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6044 here since we get better error messages by leaving it to
6045 the qualifier checking routines. */
6046 po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
6047 &offset_qualifier));
6048 if ((base_qualifier != AARCH64_OPND_QLF_S_S
6049 && base_qualifier != AARCH64_OPND_QLF_S_D)
6050 || offset_qualifier != base_qualifier)
6052 set_syntax_error (_("invalid addressing mode"));
6055 info->qualifier = base_qualifier;
6058 case AARCH64_OPND_SYSREG:
6059 if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0))
6062 set_syntax_error (_("unknown or missing system register name"));
6065 inst.base.operands[i].sysreg = val;
6068 case AARCH64_OPND_PSTATEFIELD:
6069 if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1))
6072 set_syntax_error (_("unknown or missing PSTATE field name"));
6075 inst.base.operands[i].pstatefield = val;
6078 case AARCH64_OPND_SYSREG_IC:
6079 inst.base.operands[i].sysins_op =
6080 parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
6082 case AARCH64_OPND_SYSREG_DC:
6083 inst.base.operands[i].sysins_op =
6084 parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
6086 case AARCH64_OPND_SYSREG_AT:
6087 inst.base.operands[i].sysins_op =
6088 parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
6090 case AARCH64_OPND_SYSREG_TLBI:
6091 inst.base.operands[i].sysins_op =
6092 parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
6094 if (inst.base.operands[i].sysins_op == NULL)
6096 set_fatal_syntax_error ( _("unknown or missing operation name"));
6101 case AARCH64_OPND_BARRIER:
6102 case AARCH64_OPND_BARRIER_ISB:
6103 val = parse_barrier (&str);
6104 if (val != PARSE_FAIL
6105 && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf)
6107 /* ISB only accepts options name 'sy'. */
6109 (_("the specified option is not accepted in ISB"));
6110 /* Turn off backtrack as this optional operand is present. */
6114 /* This is an extension to accept a 0..15 immediate. */
6115 if (val == PARSE_FAIL)
6116 po_imm_or_fail (0, 15);
6117 info->barrier = aarch64_barrier_options + val;
6120 case AARCH64_OPND_PRFOP:
6121 val = parse_pldop (&str);
6122 /* This is an extension to accept a 0..31 immediate. */
6123 if (val == PARSE_FAIL)
6124 po_imm_or_fail (0, 31);
6125 inst.base.operands[i].prfop = aarch64_prfops + val;
6128 case AARCH64_OPND_BARRIER_PSB:
6129 val = parse_barrier_psb (&str, &(info->hint_option));
6130 if (val == PARSE_FAIL)
6135 as_fatal (_("unhandled operand code %d"), operands[i]);
6138 /* If we get here, this operand was successfully parsed. */
6139 inst.base.operands[i].present = 1;
6143 /* The parse routine should already have set the error, but in case
6144 not, set a default one here. */
6146 set_default_error ();
6148 if (! backtrack_pos)
6149 goto parse_operands_return;
6152 /* We reach here because this operand is marked as optional, and
6153 either no operand was supplied or the operand was supplied but it
6154 was syntactically incorrect. In the latter case we report an
6155 error. In the former case we perform a few more checks before
6156 dropping through to the code to insert the default operand. */
6158 char *tmp = backtrack_pos;
6159 char endchar = END_OF_INSN;
6161 if (i != (aarch64_num_of_operands (opcode) - 1))
6163 skip_past_char (&tmp, ',');
6165 if (*tmp != endchar)
6166 /* The user has supplied an operand in the wrong format. */
6167 goto parse_operands_return;
6169 /* Make sure there is not a comma before the optional operand.
6170 For example the fifth operand of 'sys' is optional:
6172 sys #0,c0,c0,#0, <--- wrong
6173 sys #0,c0,c0,#0 <--- correct. */
6174 if (comma_skipped_p && i && endchar == END_OF_INSN)
6176 set_fatal_syntax_error
6177 (_("unexpected comma before the omitted optional operand"));
6178 goto parse_operands_return;
6182 /* Reaching here means we are dealing with an optional operand that is
6183 omitted from the assembly line. */
6184 gas_assert (optional_operand_p (opcode, i));
6186 process_omitted_operand (operands[i], opcode, i, info);
6188 /* Try again, skipping the optional operand at backtrack_pos. */
6189 str = backtrack_pos;
6192 /* Clear any error record after the omitted optional operand has been
6193 successfully handled. */
6197 /* Check if we have parsed all the operands. */
6198 if (*str != '\0' && ! error_p ())
6200 /* Set I to the index of the last present operand; this is
6201 for the purpose of diagnostics. */
6202 for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i)
6204 set_fatal_syntax_error
6205 (_("unexpected characters following instruction"));
6208 parse_operands_return:
6212 DEBUG_TRACE ("parsing FAIL: %s - %s",
6213 operand_mismatch_kind_names[get_error_kind ()],
6214 get_error_message ());
6215 /* Record the operand error properly; this is useful when there
6216 are multiple instruction templates for a mnemonic name, so that
6217 later on, we can select the error that most closely describes
6219 record_operand_error (opcode, i, get_error_kind (),
6220 get_error_message ());
6225 DEBUG_TRACE ("parsing SUCCESS");
6230 /* It does some fix-up to provide some programmer friendly feature while
6231 keeping the libopcodes happy, i.e. libopcodes only accepts
6232 the preferred architectural syntax.
6233 Return FALSE if there is any failure; otherwise return TRUE. */
6236 programmer_friendly_fixup (aarch64_instruction *instr)
6238 aarch64_inst *base = &instr->base;
6239 const aarch64_opcode *opcode = base->opcode;
6240 enum aarch64_op op = opcode->op;
6241 aarch64_opnd_info *operands = base->operands;
6243 DEBUG_TRACE ("enter");
6245 switch (opcode->iclass)
6248 /* TBNZ Xn|Wn, #uimm6, label
6249 Test and Branch Not Zero: conditionally jumps to label if bit number
6250 uimm6 in register Xn is not zero. The bit number implies the width of
6251 the register, which may be written and should be disassembled as Wn if
6252 uimm is less than 32. */
6253 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
6255 if (operands[1].imm.value >= 32)
6257 record_operand_out_of_range_error (opcode, 1, _("immediate value"),
6261 operands[0].qualifier = AARCH64_OPND_QLF_X;
6265 /* LDR Wt, label | =value
6266 As a convenience assemblers will typically permit the notation
6267 "=value" in conjunction with the pc-relative literal load instructions
6268 to automatically place an immediate value or symbolic address in a
6269 nearby literal pool and generate a hidden label which references it.
6270 ISREG has been set to 0 in the case of =value. */
6271 if (instr->gen_lit_pool
6272 && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT))
6274 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
6275 if (op == OP_LDRSW_LIT)
6277 if (instr->reloc.exp.X_op != O_constant
6278 && instr->reloc.exp.X_op != O_big
6279 && instr->reloc.exp.X_op != O_symbol)
6281 record_operand_error (opcode, 1,
6282 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
6283 _("constant expression expected"));
6286 if (! add_to_lit_pool (&instr->reloc.exp, size))
6288 record_operand_error (opcode, 1,
6289 AARCH64_OPDE_OTHER_ERROR,
6290 _("literal pool insertion failed"));
6298 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6299 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6300 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6301 A programmer-friendly assembler should accept a destination Xd in
6302 place of Wd, however that is not the preferred form for disassembly.
6304 if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW)
6305 && operands[1].qualifier == AARCH64_OPND_QLF_W
6306 && operands[0].qualifier == AARCH64_OPND_QLF_X)
6307 operands[0].qualifier = AARCH64_OPND_QLF_W;
6312 /* In the 64-bit form, the final register operand is written as Wm
6313 for all but the (possibly omitted) UXTX/LSL and SXTX
6315 As a programmer-friendly assembler, we accept e.g.
6316 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6317 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6318 int idx = aarch64_operand_index (opcode->operands,
6319 AARCH64_OPND_Rm_EXT);
6320 gas_assert (idx == 1 || idx == 2);
6321 if (operands[0].qualifier == AARCH64_OPND_QLF_X
6322 && operands[idx].qualifier == AARCH64_OPND_QLF_X
6323 && operands[idx].shifter.kind != AARCH64_MOD_LSL
6324 && operands[idx].shifter.kind != AARCH64_MOD_UXTX
6325 && operands[idx].shifter.kind != AARCH64_MOD_SXTX)
6326 operands[idx].qualifier = AARCH64_OPND_QLF_W;
6334 DEBUG_TRACE ("exit with SUCCESS");
6338 /* Check for loads and stores that will cause unpredictable behavior. */
6341 warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
6343 aarch64_inst *base = &instr->base;
6344 const aarch64_opcode *opcode = base->opcode;
6345 const aarch64_opnd_info *opnds = base->operands;
6346 switch (opcode->iclass)
6352 /* Loading/storing the base register is unpredictable if writeback. */
6353 if ((aarch64_get_operand_class (opnds[0].type)
6354 == AARCH64_OPND_CLASS_INT_REG)
6355 && opnds[0].reg.regno == opnds[1].addr.base_regno
6356 && opnds[1].addr.base_regno != REG_SP
6357 && opnds[1].addr.writeback)
6358 as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
6361 case ldstnapair_offs:
6362 case ldstpair_indexed:
6363 /* Loading/storing the base register is unpredictable if writeback. */
6364 if ((aarch64_get_operand_class (opnds[0].type)
6365 == AARCH64_OPND_CLASS_INT_REG)
6366 && (opnds[0].reg.regno == opnds[2].addr.base_regno
6367 || opnds[1].reg.regno == opnds[2].addr.base_regno)
6368 && opnds[2].addr.base_regno != REG_SP
6369 && opnds[2].addr.writeback)
6370 as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
6371 /* Load operations must load different registers. */
6372 if ((opcode->opcode & (1 << 22))
6373 && opnds[0].reg.regno == opnds[1].reg.regno)
6374 as_warn (_("unpredictable load of register pair -- `%s'"), str);
6381 /* A wrapper function to interface with libopcodes on encoding and
6382 record the error message if there is any.
6384 Return TRUE on success; otherwise return FALSE. */
6387 do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
6390 aarch64_operand_error error_info;
6391 error_info.kind = AARCH64_OPDE_NIL;
6392 if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
6396 gas_assert (error_info.kind != AARCH64_OPDE_NIL);
6397 record_operand_error_info (opcode, &error_info);
6402 #ifdef DEBUG_AARCH64
6404 dump_opcode_operands (const aarch64_opcode *opcode)
6407 while (opcode->operands[i] != AARCH64_OPND_NIL)
6409 aarch64_verbose ("\t\t opnd%d: %s", i,
6410 aarch64_get_operand_name (opcode->operands[i])[0] != '\0'
6411 ? aarch64_get_operand_name (opcode->operands[i])
6412 : aarch64_get_operand_desc (opcode->operands[i]));
6416 #endif /* DEBUG_AARCH64 */
6418 /* This is the guts of the machine-dependent assembler. STR points to a
6419 machine dependent instruction. This function is supposed to emit
6420 the frags/bytes it assembles to. */
6423 md_assemble (char *str)
6426 templates *template;
6427 aarch64_opcode *opcode;
6428 aarch64_inst *inst_base;
6429 unsigned saved_cond;
6431 /* Align the previous label if needed. */
6432 if (last_label_seen != NULL)
6434 symbol_set_frag (last_label_seen, frag_now);
6435 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6436 S_SET_SEGMENT (last_label_seen, now_seg);
6439 inst.reloc.type = BFD_RELOC_UNUSED;
6441 DEBUG_TRACE ("\n\n");
6442 DEBUG_TRACE ("==============================");
6443 DEBUG_TRACE ("Enter md_assemble with %s", str);
6445 template = opcode_lookup (&p);
6448 /* It wasn't an instruction, but it might be a register alias of
6449 the form alias .req reg directive. */
6450 if (!create_register_alias (str, p))
6451 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
6456 skip_whitespace (p);
6459 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6460 get_mnemonic_name (str), str);
6464 init_operand_error_report ();
6466 /* Sections are assumed to start aligned. In executable section, there is no
6467 MAP_DATA symbol pending. So we only align the address during
6468 MAP_DATA --> MAP_INSN transition.
6469 For other sections, this is not guaranteed. */
6470 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
6471 if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA)
6472 frag_align_code (2, 0);
6474 saved_cond = inst.cond;
6475 reset_aarch64_instruction (&inst);
6476 inst.cond = saved_cond;
6478 /* Iterate through all opcode entries with the same mnemonic name. */
6481 opcode = template->opcode;
6483 DEBUG_TRACE ("opcode %s found", opcode->name);
6484 #ifdef DEBUG_AARCH64
6486 dump_opcode_operands (opcode);
6487 #endif /* DEBUG_AARCH64 */
6489 mapping_state (MAP_INSN);
6491 inst_base = &inst.base;
6492 inst_base->opcode = opcode;
6494 /* Truly conditionally executed instructions, e.g. b.cond. */
6495 if (opcode->flags & F_COND)
6497 gas_assert (inst.cond != COND_ALWAYS);
6498 inst_base->cond = get_cond_from_value (inst.cond);
6499 DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]);
6501 else if (inst.cond != COND_ALWAYS)
6503 /* It shouldn't arrive here, where the assembly looks like a
6504 conditional instruction but the found opcode is unconditional. */
6509 if (parse_operands (p, opcode)
6510 && programmer_friendly_fixup (&inst)
6511 && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
6513 /* Check that this instruction is supported for this CPU. */
6514 if (!opcode->avariant
6515 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant))
6517 as_bad (_("selected processor does not support `%s'"), str);
6521 warn_unpredictable_ldst (&inst, str);
6523 if (inst.reloc.type == BFD_RELOC_UNUSED
6524 || !inst.reloc.need_libopcodes_p)
6528 /* If there is relocation generated for the instruction,
6529 store the instruction information for the future fix-up. */
6530 struct aarch64_inst *copy;
6531 gas_assert (inst.reloc.type != BFD_RELOC_UNUSED);
6532 copy = XNEW (struct aarch64_inst);
6533 memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
6539 template = template->next;
6540 if (template != NULL)
6542 reset_aarch64_instruction (&inst);
6543 inst.cond = saved_cond;
6546 while (template != NULL);
6548 /* Issue the error messages if any. */
6549 output_operand_error_report (str);
6552 /* Various frobbings of labels and their addresses. */
6555 aarch64_start_line_hook (void)
6557 last_label_seen = NULL;
6561 aarch64_frob_label (symbolS * sym)
6563 last_label_seen = sym;
6565 dwarf2_emit_label (sym);
6569 aarch64_data_in_code (void)
6571 if (!strncmp (input_line_pointer + 1, "data:", 5))
6573 *input_line_pointer = '/';
6574 input_line_pointer += 5;
6575 *input_line_pointer = 0;
6583 aarch64_canonicalize_symbol_name (char *name)
6587 if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data"))
6588 *(name + len - 5) = 0;
6593 /* Table of all register names defined by default. The user can
6594 define additional names with .req. Note that all register names
6595 should appear in both upper and lowercase variants. Some registers
6596 also have mixed-case names. */
6598 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6599 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6600 #define REGSET16(p,t) \
6601 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6602 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6603 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6604 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
6605 #define REGSET31(p,t) \
6607 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6608 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6609 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6610 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6611 #define REGSET(p,t) \
6612 REGSET31(p,t), REGNUM(p,31,t)
6614 /* These go into aarch64_reg_hsh hash-table. */
6615 static const reg_entry reg_names[] = {
6616 /* Integer registers. */
6617 REGSET31 (x, R_64), REGSET31 (X, R_64),
6618 REGSET31 (w, R_32), REGSET31 (W, R_32),
6620 REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
6621 REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
6623 REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
6624 REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
6626 /* Coprocessor register numbers. */
6627 REGSET (c, CN), REGSET (C, CN),
6629 /* Floating-point single precision registers. */
6630 REGSET (s, FP_S), REGSET (S, FP_S),
6632 /* Floating-point double precision registers. */
6633 REGSET (d, FP_D), REGSET (D, FP_D),
6635 /* Floating-point half precision registers. */
6636 REGSET (h, FP_H), REGSET (H, FP_H),
6638 /* Floating-point byte precision registers. */
6639 REGSET (b, FP_B), REGSET (B, FP_B),
6641 /* Floating-point quad precision registers. */
6642 REGSET (q, FP_Q), REGSET (Q, FP_Q),
6644 /* FP/SIMD registers. */
6645 REGSET (v, VN), REGSET (V, VN),
6647 /* SVE vector registers. */
6648 REGSET (z, ZN), REGSET (Z, ZN),
6650 /* SVE predicate registers. */
6651 REGSET16 (p, PN), REGSET16 (P, PN)
6668 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6669 static const asm_nzcv nzcv_names[] = {
6670 {"nzcv", B (n, z, c, v)},
6671 {"nzcV", B (n, z, c, V)},
6672 {"nzCv", B (n, z, C, v)},
6673 {"nzCV", B (n, z, C, V)},
6674 {"nZcv", B (n, Z, c, v)},
6675 {"nZcV", B (n, Z, c, V)},
6676 {"nZCv", B (n, Z, C, v)},
6677 {"nZCV", B (n, Z, C, V)},
6678 {"Nzcv", B (N, z, c, v)},
6679 {"NzcV", B (N, z, c, V)},
6680 {"NzCv", B (N, z, C, v)},
6681 {"NzCV", B (N, z, C, V)},
6682 {"NZcv", B (N, Z, c, v)},
6683 {"NZcV", B (N, Z, c, V)},
6684 {"NZCv", B (N, Z, C, v)},
6685 {"NZCV", B (N, Z, C, V)}
6698 /* MD interface: bits in the object file. */
6700 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6701 for use in the a.out file, and stores them in the array pointed to by buf.
6702 This knows about the endian-ness of the target machine and does
6703 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6704 2 (short) and 4 (long) Floating numbers are put out as a series of
6705 LITTLENUMS (shorts, here at least). */
6708 md_number_to_chars (char *buf, valueT val, int n)
6710 if (target_big_endian)
6711 number_to_chars_bigendian (buf, val, n);
6713 number_to_chars_littleendian (buf, val, n);
6716 /* MD interface: Sections. */
6718 /* Estimate the size of a frag before relaxing. Assume everything fits in
6722 md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED)
6728 /* Round up a section size to the appropriate boundary. */
6731 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
6736 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6737 of an rs_align_code fragment.
6739 Here we fill the frag with the appropriate info for padding the
6740 output stream. The resulting frag will consist of a fixed (fr_fix)
6741 and of a repeating (fr_var) part.
6743 The fixed content is always emitted before the repeating content and
6744 these two parts are used as follows in constructing the output:
6745 - the fixed part will be used to align to a valid instruction word
6746 boundary, in case that we start at a misaligned address; as no
6747 executable instruction can live at the misaligned location, we
6748 simply fill with zeros;
6749 - the variable part will be used to cover the remaining padding and
6750 we fill using the AArch64 NOP instruction.
6752 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6753 enough storage space for up to 3 bytes for padding the back to a valid
6754 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6757 aarch64_handle_align (fragS * fragP)
6759 /* NOP = d503201f */
6760 /* AArch64 instructions are always little-endian. */
6761 static unsigned char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6763 int bytes, fix, noop_size;
6766 if (fragP->fr_type != rs_align_code)
6769 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
6770 p = fragP->fr_literal + fragP->fr_fix;
6773 gas_assert (fragP->tc_frag_data.recorded);
6776 noop_size = sizeof (aarch64_noop);
6778 fix = bytes & (noop_size - 1);
6782 insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
6786 fragP->fr_fix += fix;
6790 memcpy (p, aarch64_noop, noop_size);
6791 fragP->fr_var = noop_size;
6794 /* Perform target specific initialisation of a frag.
6795 Note - despite the name this initialisation is not done when the frag
6796 is created, but only when its type is assigned. A frag can be created
6797 and used a long time before its type is set, so beware of assuming that
6798 this initialisationis performed first. */
6802 aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED,
6803 int max_chars ATTRIBUTE_UNUSED)
6807 #else /* OBJ_ELF is defined. */
6809 aarch64_init_frag (fragS * fragP, int max_chars)
6811 /* Record a mapping symbol for alignment frags. We will delete this
6812 later if the alignment ends up empty. */
6813 if (!fragP->tc_frag_data.recorded)
6814 fragP->tc_frag_data.recorded = 1;
6816 switch (fragP->fr_type)
6820 mapping_state_2 (MAP_DATA, max_chars);
6823 /* PR 20364: We can get alignment frags in code sections,
6824 so do not just assume that we should use the MAP_DATA state. */
6825 mapping_state_2 (subseg_text_p (now_seg) ? MAP_INSN : MAP_DATA, max_chars);
6828 mapping_state_2 (MAP_INSN, max_chars);
6835 /* Initialize the DWARF-2 unwind information for this procedure. */
6838 tc_aarch64_frame_initial_instructions (void)
6840 cfi_add_CFA_def_cfa (REG_SP, 0);
6842 #endif /* OBJ_ELF */
6844 /* Convert REGNAME to a DWARF-2 register number. */
6847 tc_aarch64_regname_to_dw2regnum (char *regname)
6849 const reg_entry *reg = parse_reg (®name);
6855 case REG_TYPE_SP_32:
6856 case REG_TYPE_SP_64:
6866 return reg->number + 64;
6874 /* Implement DWARF2_ADDR_SIZE. */
6877 aarch64_dwarf2_addr_size (void)
6879 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6883 return bfd_arch_bits_per_address (stdoutput) / 8;
6886 /* MD interface: Symbol and relocation handling. */
6888 /* Return the address within the segment that a PC-relative fixup is
6889 relative to. For AArch64 PC-relative fixups applied to instructions
6890 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6893 md_pcrel_from_section (fixS * fixP, segT seg)
6895 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
6897 /* If this is pc-relative and we are going to emit a relocation
6898 then we just want to put out any pipeline compensation that the linker
6899 will need. Otherwise we want to use the calculated base. */
6901 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
6902 || aarch64_force_relocation (fixP)))
6905 /* AArch64 should be consistent for all pc-relative relocations. */
6906 return base + AARCH64_PCREL_OFFSET;
6909 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6910 Otherwise we have no need to default values of symbols. */
6913 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
6916 if (name[0] == '_' && name[1] == 'G'
6917 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
6921 if (symbol_find (name))
6922 as_bad (_("GOT already in the symbol table"));
6924 GOT_symbol = symbol_new (name, undefined_section,
6925 (valueT) 0, &zero_address_frag);
6935 /* Return non-zero if the indicated VALUE has overflowed the maximum
6936 range expressible by a unsigned number with the indicated number of
6940 unsigned_overflow (valueT value, unsigned bits)
6943 if (bits >= sizeof (valueT) * 8)
6945 lim = (valueT) 1 << bits;
6946 return (value >= lim);
6950 /* Return non-zero if the indicated VALUE has overflowed the maximum
6951 range expressible by an signed number with the indicated number of
6955 signed_overflow (offsetT value, unsigned bits)
6958 if (bits >= sizeof (offsetT) * 8)
6960 lim = (offsetT) 1 << (bits - 1);
6961 return (value < -lim || value >= lim);
6964 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6965 unsigned immediate offset load/store instruction, try to encode it as
6966 an unscaled, 9-bit, signed immediate offset load/store instruction.
6967 Return TRUE if it is successful; otherwise return FALSE.
6969 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6970 in response to the standard LDR/STR mnemonics when the immediate offset is
6971 unambiguous, i.e. when it is negative or unaligned. */
6974 try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
6977 enum aarch64_op new_op;
6978 const aarch64_opcode *new_opcode;
6980 gas_assert (instr->opcode->iclass == ldst_pos);
6982 switch (instr->opcode->op)
6984 case OP_LDRB_POS:new_op = OP_LDURB; break;
6985 case OP_STRB_POS: new_op = OP_STURB; break;
6986 case OP_LDRSB_POS: new_op = OP_LDURSB; break;
6987 case OP_LDRH_POS: new_op = OP_LDURH; break;
6988 case OP_STRH_POS: new_op = OP_STURH; break;
6989 case OP_LDRSH_POS: new_op = OP_LDURSH; break;
6990 case OP_LDR_POS: new_op = OP_LDUR; break;
6991 case OP_STR_POS: new_op = OP_STUR; break;
6992 case OP_LDRF_POS: new_op = OP_LDURV; break;
6993 case OP_STRF_POS: new_op = OP_STURV; break;
6994 case OP_LDRSW_POS: new_op = OP_LDURSW; break;
6995 case OP_PRFM_POS: new_op = OP_PRFUM; break;
6996 default: new_op = OP_NIL; break;
6999 if (new_op == OP_NIL)
7002 new_opcode = aarch64_get_opcode (new_op);
7003 gas_assert (new_opcode != NULL);
7005 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7006 instr->opcode->op, new_opcode->op);
7008 aarch64_replace_opcode (instr, new_opcode);
7010 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7011 qualifier matching may fail because the out-of-date qualifier will
7012 prevent the operand being updated with a new and correct qualifier. */
7013 idx = aarch64_operand_index (instr->opcode->operands,
7014 AARCH64_OPND_ADDR_SIMM9);
7015 gas_assert (idx == 1);
7016 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
7018 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7020 if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
7026 /* Called by fix_insn to fix a MOV immediate alias instruction.
7028 Operand for a generic move immediate instruction, which is an alias
7029 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7030 a 32-bit/64-bit immediate value into general register. An assembler error
7031 shall result if the immediate cannot be created by a single one of these
7032 instructions. If there is a choice, then to ensure reversability an
7033 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7036 fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
7038 const aarch64_opcode *opcode;
7040 /* Need to check if the destination is SP/ZR. The check has to be done
7041 before any aarch64_replace_opcode. */
7042 int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]);
7043 int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]);
7045 instr->operands[1].imm.value = value;
7046 instr->operands[1].skip = 0;
7050 /* Try the MOVZ alias. */
7051 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
7052 aarch64_replace_opcode (instr, opcode);
7053 if (aarch64_opcode_encode (instr->opcode, instr,
7054 &instr->value, NULL, NULL))
7056 put_aarch64_insn (buf, instr->value);
7059 /* Try the MOVK alias. */
7060 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
7061 aarch64_replace_opcode (instr, opcode);
7062 if (aarch64_opcode_encode (instr->opcode, instr,
7063 &instr->value, NULL, NULL))
7065 put_aarch64_insn (buf, instr->value);
7070 if (try_mov_bitmask_p)
7072 /* Try the ORR alias. */
7073 opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
7074 aarch64_replace_opcode (instr, opcode);
7075 if (aarch64_opcode_encode (instr->opcode, instr,
7076 &instr->value, NULL, NULL))
7078 put_aarch64_insn (buf, instr->value);
7083 as_bad_where (fixP->fx_file, fixP->fx_line,
7084 _("immediate cannot be moved by a single instruction"));
7087 /* An instruction operand which is immediate related may have symbol used
7088 in the assembly, e.g.
7091 .set u32, 0x00ffff00
7093 At the time when the assembly instruction is parsed, a referenced symbol,
7094 like 'u32' in the above example may not have been seen; a fixS is created
7095 in such a case and is handled here after symbols have been resolved.
7096 Instruction is fixed up with VALUE using the information in *FIXP plus
7097 extra information in FLAGS.
7099 This function is called by md_apply_fix to fix up instructions that need
7100 a fix-up described above but does not involve any linker-time relocation. */
7103 fix_insn (fixS *fixP, uint32_t flags, offsetT value)
7107 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
7108 enum aarch64_opnd opnd = fixP->tc_fix_data.opnd;
7109 aarch64_inst *new_inst = fixP->tc_fix_data.inst;
7113 /* Now the instruction is about to be fixed-up, so the operand that
7114 was previously marked as 'ignored' needs to be unmarked in order
7115 to get the encoding done properly. */
7116 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
7117 new_inst->operands[idx].skip = 0;
7120 gas_assert (opnd != AARCH64_OPND_NIL);
7124 case AARCH64_OPND_EXCEPTION:
7125 if (unsigned_overflow (value, 16))
7126 as_bad_where (fixP->fx_file, fixP->fx_line,
7127 _("immediate out of range"));
7128 insn = get_aarch64_insn (buf);
7129 insn |= encode_svc_imm (value);
7130 put_aarch64_insn (buf, insn);
7133 case AARCH64_OPND_AIMM:
7134 /* ADD or SUB with immediate.
7135 NOTE this assumes we come here with a add/sub shifted reg encoding
7136 3 322|2222|2 2 2 21111 111111
7137 1 098|7654|3 2 1 09876 543210 98765 43210
7138 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7139 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7140 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7141 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7143 3 322|2222|2 2 221111111111
7144 1 098|7654|3 2 109876543210 98765 43210
7145 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7146 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7147 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7148 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7149 Fields sf Rn Rd are already set. */
7150 insn = get_aarch64_insn (buf);
7154 insn = reencode_addsub_switch_add_sub (insn);
7158 if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0
7159 && unsigned_overflow (value, 12))
7161 /* Try to shift the value by 12 to make it fit. */
7162 if (((value >> 12) << 12) == value
7163 && ! unsigned_overflow (value, 12 + 12))
7166 insn |= encode_addsub_imm_shift_amount (1);
7170 if (unsigned_overflow (value, 12))
7171 as_bad_where (fixP->fx_file, fixP->fx_line,
7172 _("immediate out of range"));
7174 insn |= encode_addsub_imm (value);
7176 put_aarch64_insn (buf, insn);
7179 case AARCH64_OPND_SIMD_IMM:
7180 case AARCH64_OPND_SIMD_IMM_SFT:
7181 case AARCH64_OPND_LIMM:
7182 /* Bit mask immediate. */
7183 gas_assert (new_inst != NULL);
7184 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
7185 new_inst->operands[idx].imm.value = value;
7186 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
7187 &new_inst->value, NULL, NULL))
7188 put_aarch64_insn (buf, new_inst->value);
7190 as_bad_where (fixP->fx_file, fixP->fx_line,
7191 _("invalid immediate"));
7194 case AARCH64_OPND_HALF:
7195 /* 16-bit unsigned immediate. */
7196 if (unsigned_overflow (value, 16))
7197 as_bad_where (fixP->fx_file, fixP->fx_line,
7198 _("immediate out of range"));
7199 insn = get_aarch64_insn (buf);
7200 insn |= encode_movw_imm (value & 0xffff);
7201 put_aarch64_insn (buf, insn);
7204 case AARCH64_OPND_IMM_MOV:
7205 /* Operand for a generic move immediate instruction, which is
7206 an alias instruction that generates a single MOVZ, MOVN or ORR
7207 instruction to loads a 32-bit/64-bit immediate value into general
7208 register. An assembler error shall result if the immediate cannot be
7209 created by a single one of these instructions. If there is a choice,
7210 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7211 and MOVZ or MOVN to ORR. */
7212 gas_assert (new_inst != NULL);
7213 fix_mov_imm_insn (fixP, buf, new_inst, value);
7216 case AARCH64_OPND_ADDR_SIMM7:
7217 case AARCH64_OPND_ADDR_SIMM9:
7218 case AARCH64_OPND_ADDR_SIMM9_2:
7219 case AARCH64_OPND_ADDR_UIMM12:
7220 /* Immediate offset in an address. */
7221 insn = get_aarch64_insn (buf);
7223 gas_assert (new_inst != NULL && new_inst->value == insn);
7224 gas_assert (new_inst->opcode->operands[1] == opnd
7225 || new_inst->opcode->operands[2] == opnd);
7227 /* Get the index of the address operand. */
7228 if (new_inst->opcode->operands[1] == opnd)
7229 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7232 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7235 /* Update the resolved offset value. */
7236 new_inst->operands[idx].addr.offset.imm = value;
7238 /* Encode/fix-up. */
7239 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
7240 &new_inst->value, NULL, NULL))
7242 put_aarch64_insn (buf, new_inst->value);
7245 else if (new_inst->opcode->iclass == ldst_pos
7246 && try_to_encode_as_unscaled_ldst (new_inst))
7248 put_aarch64_insn (buf, new_inst->value);
7252 as_bad_where (fixP->fx_file, fixP->fx_line,
7253 _("immediate offset out of range"));
7258 as_fatal (_("unhandled operand code %d"), opnd);
7262 /* Apply a fixup (fixP) to segment data, once it has been determined
7263 by our caller that we have all the info we need to fix it up.
7265 Parameter valP is the pointer to the value of the bits. */
7268 md_apply_fix (fixS * fixP, valueT * valP, segT seg)
7270 offsetT value = *valP;
7272 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
7274 unsigned flags = fixP->fx_addnumber;
7276 DEBUG_TRACE ("\n\n");
7277 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7278 DEBUG_TRACE ("Enter md_apply_fix");
7280 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
7282 /* Note whether this will delete the relocation. */
7284 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
7287 /* Process the relocations. */
7288 switch (fixP->fx_r_type)
7290 case BFD_RELOC_NONE:
7291 /* This will need to go in the object file. */
7296 case BFD_RELOC_8_PCREL:
7297 if (fixP->fx_done || !seg->use_rela_p)
7298 md_number_to_chars (buf, value, 1);
7302 case BFD_RELOC_16_PCREL:
7303 if (fixP->fx_done || !seg->use_rela_p)
7304 md_number_to_chars (buf, value, 2);
7308 case BFD_RELOC_32_PCREL:
7309 if (fixP->fx_done || !seg->use_rela_p)
7310 md_number_to_chars (buf, value, 4);
7314 case BFD_RELOC_64_PCREL:
7315 if (fixP->fx_done || !seg->use_rela_p)
7316 md_number_to_chars (buf, value, 8);
7319 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
7320 /* We claim that these fixups have been processed here, even if
7321 in fact we generate an error because we do not have a reloc
7322 for them, so tc_gen_reloc() will reject them. */
7324 if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy))
7326 as_bad_where (fixP->fx_file, fixP->fx_line,
7327 _("undefined symbol %s used as an immediate value"),
7328 S_GET_NAME (fixP->fx_addsy));
7329 goto apply_fix_return;
7331 fix_insn (fixP, flags, value);
7334 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
7335 if (fixP->fx_done || !seg->use_rela_p)
7338 as_bad_where (fixP->fx_file, fixP->fx_line,
7339 _("pc-relative load offset not word aligned"));
7340 if (signed_overflow (value, 21))
7341 as_bad_where (fixP->fx_file, fixP->fx_line,
7342 _("pc-relative load offset out of range"));
7343 insn = get_aarch64_insn (buf);
7344 insn |= encode_ld_lit_ofs_19 (value >> 2);
7345 put_aarch64_insn (buf, insn);
7349 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
7350 if (fixP->fx_done || !seg->use_rela_p)
7352 if (signed_overflow (value, 21))
7353 as_bad_where (fixP->fx_file, fixP->fx_line,
7354 _("pc-relative address offset out of range"));
7355 insn = get_aarch64_insn (buf);
7356 insn |= encode_adr_imm (value);
7357 put_aarch64_insn (buf, insn);
7361 case BFD_RELOC_AARCH64_BRANCH19:
7362 if (fixP->fx_done || !seg->use_rela_p)
7365 as_bad_where (fixP->fx_file, fixP->fx_line,
7366 _("conditional branch target not word aligned"));
7367 if (signed_overflow (value, 21))
7368 as_bad_where (fixP->fx_file, fixP->fx_line,
7369 _("conditional branch out of range"));
7370 insn = get_aarch64_insn (buf);
7371 insn |= encode_cond_branch_ofs_19 (value >> 2);
7372 put_aarch64_insn (buf, insn);
7376 case BFD_RELOC_AARCH64_TSTBR14:
7377 if (fixP->fx_done || !seg->use_rela_p)
7380 as_bad_where (fixP->fx_file, fixP->fx_line,
7381 _("conditional branch target not word aligned"));
7382 if (signed_overflow (value, 16))
7383 as_bad_where (fixP->fx_file, fixP->fx_line,
7384 _("conditional branch out of range"));
7385 insn = get_aarch64_insn (buf);
7386 insn |= encode_tst_branch_ofs_14 (value >> 2);
7387 put_aarch64_insn (buf, insn);
7391 case BFD_RELOC_AARCH64_CALL26:
7392 case BFD_RELOC_AARCH64_JUMP26:
7393 if (fixP->fx_done || !seg->use_rela_p)
7396 as_bad_where (fixP->fx_file, fixP->fx_line,
7397 _("branch target not word aligned"));
7398 if (signed_overflow (value, 28))
7399 as_bad_where (fixP->fx_file, fixP->fx_line,
7400 _("branch out of range"));
7401 insn = get_aarch64_insn (buf);
7402 insn |= encode_branch_ofs_26 (value >> 2);
7403 put_aarch64_insn (buf, insn);
7407 case BFD_RELOC_AARCH64_MOVW_G0:
7408 case BFD_RELOC_AARCH64_MOVW_G0_NC:
7409 case BFD_RELOC_AARCH64_MOVW_G0_S:
7410 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
7413 case BFD_RELOC_AARCH64_MOVW_G1:
7414 case BFD_RELOC_AARCH64_MOVW_G1_NC:
7415 case BFD_RELOC_AARCH64_MOVW_G1_S:
7416 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
7419 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
7421 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7422 /* Should always be exported to object file, see
7423 aarch64_force_relocation(). */
7424 gas_assert (!fixP->fx_done);
7425 gas_assert (seg->use_rela_p);
7427 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7429 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7430 /* Should always be exported to object file, see
7431 aarch64_force_relocation(). */
7432 gas_assert (!fixP->fx_done);
7433 gas_assert (seg->use_rela_p);
7435 case BFD_RELOC_AARCH64_MOVW_G2:
7436 case BFD_RELOC_AARCH64_MOVW_G2_NC:
7437 case BFD_RELOC_AARCH64_MOVW_G2_S:
7440 case BFD_RELOC_AARCH64_MOVW_G3:
7443 if (fixP->fx_done || !seg->use_rela_p)
7445 insn = get_aarch64_insn (buf);
7449 /* REL signed addend must fit in 16 bits */
7450 if (signed_overflow (value, 16))
7451 as_bad_where (fixP->fx_file, fixP->fx_line,
7452 _("offset out of range"));
7456 /* Check for overflow and scale. */
7457 switch (fixP->fx_r_type)
7459 case BFD_RELOC_AARCH64_MOVW_G0:
7460 case BFD_RELOC_AARCH64_MOVW_G1:
7461 case BFD_RELOC_AARCH64_MOVW_G2:
7462 case BFD_RELOC_AARCH64_MOVW_G3:
7463 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
7464 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7465 if (unsigned_overflow (value, scale + 16))
7466 as_bad_where (fixP->fx_file, fixP->fx_line,
7467 _("unsigned value out of range"));
7469 case BFD_RELOC_AARCH64_MOVW_G0_S:
7470 case BFD_RELOC_AARCH64_MOVW_G1_S:
7471 case BFD_RELOC_AARCH64_MOVW_G2_S:
7472 /* NOTE: We can only come here with movz or movn. */
7473 if (signed_overflow (value, scale + 16))
7474 as_bad_where (fixP->fx_file, fixP->fx_line,
7475 _("signed value out of range"));
7478 /* Force use of MOVN. */
7480 insn = reencode_movzn_to_movn (insn);
7484 /* Force use of MOVZ. */
7485 insn = reencode_movzn_to_movz (insn);
7489 /* Unchecked relocations. */
7495 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7496 insn |= encode_movw_imm (value & 0xffff);
7498 put_aarch64_insn (buf, insn);
7502 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
7503 fixP->fx_r_type = (ilp32_p
7504 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7505 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);
7506 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7507 /* Should always be exported to object file, see
7508 aarch64_force_relocation(). */
7509 gas_assert (!fixP->fx_done);
7510 gas_assert (seg->use_rela_p);
7513 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
7514 fixP->fx_r_type = (ilp32_p
7515 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7516 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC);
7517 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7518 /* Should always be exported to object file, see
7519 aarch64_force_relocation(). */
7520 gas_assert (!fixP->fx_done);
7521 gas_assert (seg->use_rela_p);
7524 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
7525 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
7526 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
7527 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
7528 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
7529 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
7530 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
7531 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
7532 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
7533 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
7534 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
7535 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
7536 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
7537 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
7538 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
7539 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
7540 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
7541 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
7542 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
7543 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
7544 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
7545 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
7546 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
7547 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
7548 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
7549 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
7550 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
7551 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
7552 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
7553 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
7554 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
7555 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
7556 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
7557 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
7558 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
7559 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
7560 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
7561 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
7562 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
7563 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
7564 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
7565 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
7566 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
7567 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
7568 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7569 /* Should always be exported to object file, see
7570 aarch64_force_relocation(). */
7571 gas_assert (!fixP->fx_done);
7572 gas_assert (seg->use_rela_p);
7575 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
7576 /* Should always be exported to object file, see
7577 aarch64_force_relocation(). */
7578 fixP->fx_r_type = (ilp32_p
7579 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7580 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC);
7581 gas_assert (!fixP->fx_done);
7582 gas_assert (seg->use_rela_p);
7585 case BFD_RELOC_AARCH64_ADD_LO12:
7586 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
7587 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
7588 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
7589 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
7590 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
7591 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
7592 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
7593 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
7594 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
7595 case BFD_RELOC_AARCH64_LDST128_LO12:
7596 case BFD_RELOC_AARCH64_LDST16_LO12:
7597 case BFD_RELOC_AARCH64_LDST32_LO12:
7598 case BFD_RELOC_AARCH64_LDST64_LO12:
7599 case BFD_RELOC_AARCH64_LDST8_LO12:
7600 /* Should always be exported to object file, see
7601 aarch64_force_relocation(). */
7602 gas_assert (!fixP->fx_done);
7603 gas_assert (seg->use_rela_p);
7606 case BFD_RELOC_AARCH64_TLSDESC_ADD:
7607 case BFD_RELOC_AARCH64_TLSDESC_CALL:
7608 case BFD_RELOC_AARCH64_TLSDESC_LDR:
7611 case BFD_RELOC_UNUSED:
7612 /* An error will already have been reported. */
7616 as_bad_where (fixP->fx_file, fixP->fx_line,
7617 _("unexpected %s fixup"),
7618 bfd_get_reloc_code_name (fixP->fx_r_type));
7623 /* Free the allocated the struct aarch64_inst.
7624 N.B. currently there are very limited number of fix-up types actually use
7625 this field, so the impact on the performance should be minimal . */
7626 if (fixP->tc_fix_data.inst != NULL)
7627 free (fixP->tc_fix_data.inst);
7632 /* Translate internal representation of relocation info to BFD target
7636 tc_gen_reloc (asection * section, fixS * fixp)
7639 bfd_reloc_code_real_type code;
7641 reloc = XNEW (arelent);
7643 reloc->sym_ptr_ptr = XNEW (asymbol *);
7644 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7645 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
7649 if (section->use_rela_p)
7650 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
7652 fixp->fx_offset = reloc->address;
7654 reloc->addend = fixp->fx_offset;
7656 code = fixp->fx_r_type;
7661 code = BFD_RELOC_16_PCREL;
7666 code = BFD_RELOC_32_PCREL;
7671 code = BFD_RELOC_64_PCREL;
7678 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
7679 if (reloc->howto == NULL)
7681 as_bad_where (fixp->fx_file, fixp->fx_line,
7683 ("cannot represent %s relocation in this object file format"),
7684 bfd_get_reloc_code_name (code));
7691 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7694 cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp)
7696 bfd_reloc_code_real_type type;
7700 FIXME: @@ Should look at CPU word size. */
7707 type = BFD_RELOC_16;
7710 type = BFD_RELOC_32;
7713 type = BFD_RELOC_64;
7716 as_bad (_("cannot do %u-byte relocation"), size);
7717 type = BFD_RELOC_UNUSED;
7721 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
7725 aarch64_force_relocation (struct fix *fixp)
7727 switch (fixp->fx_r_type)
7729 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
7730 /* Perform these "immediate" internal relocations
7731 even if the symbol is extern or weak. */
7734 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
7735 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
7736 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
7737 /* Pseudo relocs that need to be fixed up according to
7741 case BFD_RELOC_AARCH64_ADD_LO12:
7742 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
7743 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
7744 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
7745 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
7746 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
7747 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
7748 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
7749 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
7750 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
7751 case BFD_RELOC_AARCH64_LDST128_LO12:
7752 case BFD_RELOC_AARCH64_LDST16_LO12:
7753 case BFD_RELOC_AARCH64_LDST32_LO12:
7754 case BFD_RELOC_AARCH64_LDST64_LO12:
7755 case BFD_RELOC_AARCH64_LDST8_LO12:
7756 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
7757 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
7758 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
7759 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
7760 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
7761 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
7762 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
7763 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7764 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
7765 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
7766 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
7767 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
7768 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
7769 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
7770 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
7771 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
7772 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
7773 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
7774 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
7775 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
7776 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
7777 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
7778 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
7779 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
7780 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
7781 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
7782 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
7783 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
7784 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
7785 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
7786 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
7787 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
7788 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
7789 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
7790 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
7791 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
7792 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
7793 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
7794 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
7795 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
7796 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
7797 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
7798 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
7799 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
7800 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
7801 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
7802 /* Always leave these relocations for the linker. */
7809 return generic_force_reloc (fixp);
7815 elf64_aarch64_target_format (void)
7817 if (strcmp (TARGET_OS, "cloudabi") == 0)
7819 /* FIXME: What to do for ilp32_p ? */
7820 return target_big_endian ? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7822 if (target_big_endian)
7823 return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
7825 return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";
7829 aarch64elf_frob_symbol (symbolS * symp, int *puntp)
7831 elf_frob_symbol (symp, puntp);
7835 /* MD interface: Finalization. */
7837 /* A good place to do this, although this was probably not intended
7838 for this kind of use. We need to dump the literal pool before
7839 references are made to a null symbol pointer. */
7842 aarch64_cleanup (void)
7846 for (pool = list_of_pools; pool; pool = pool->next)
7848 /* Put it at the end of the relevant section. */
7849 subseg_set (pool->section, pool->sub_section);
7855 /* Remove any excess mapping symbols generated for alignment frags in
7856 SEC. We may have created a mapping symbol before a zero byte
7857 alignment; remove it if there's a mapping symbol after the
7860 check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec,
7861 void *dummy ATTRIBUTE_UNUSED)
7863 segment_info_type *seginfo = seg_info (sec);
7866 if (seginfo == NULL || seginfo->frchainP == NULL)
7869 for (fragp = seginfo->frchainP->frch_root;
7870 fragp != NULL; fragp = fragp->fr_next)
7872 symbolS *sym = fragp->tc_frag_data.last_map;
7873 fragS *next = fragp->fr_next;
7875 /* Variable-sized frags have been converted to fixed size by
7876 this point. But if this was variable-sized to start with,
7877 there will be a fixed-size frag after it. So don't handle
7879 if (sym == NULL || next == NULL)
7882 if (S_GET_VALUE (sym) < next->fr_address)
7883 /* Not at the end of this frag. */
7885 know (S_GET_VALUE (sym) == next->fr_address);
7889 if (next->tc_frag_data.first_map != NULL)
7891 /* Next frag starts with a mapping symbol. Discard this
7893 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
7897 if (next->fr_next == NULL)
7899 /* This mapping symbol is at the end of the section. Discard
7901 know (next->fr_fix == 0 && next->fr_var == 0);
7902 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
7906 /* As long as we have empty frags without any mapping symbols,
7908 /* If the next frag is non-empty and does not start with a
7909 mapping symbol, then this mapping symbol is required. */
7910 if (next->fr_address != next->fr_next->fr_address)
7913 next = next->fr_next;
7915 while (next != NULL);
7920 /* Adjust the symbol table. */
7923 aarch64_adjust_symtab (void)
7926 /* Remove any overlapping mapping symbols generated by alignment frags. */
7927 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
7928 /* Now do generic ELF adjustments. */
7929 elf_adjust_symtab ();
7934 checked_hash_insert (struct hash_control *table, const char *key, void *value)
7936 const char *hash_err;
7938 hash_err = hash_insert (table, key, value);
7940 printf ("Internal Error: Can't hash %s\n", key);
7944 fill_instruction_hash_table (void)
7946 aarch64_opcode *opcode = aarch64_opcode_table;
7948 while (opcode->name != NULL)
7950 templates *templ, *new_templ;
7951 templ = hash_find (aarch64_ops_hsh, opcode->name);
7953 new_templ = XNEW (templates);
7954 new_templ->opcode = opcode;
7955 new_templ->next = NULL;
7958 checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ);
7961 new_templ->next = templ->next;
7962 templ->next = new_templ;
7969 convert_to_upper (char *dst, const char *src, size_t num)
7972 for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src)
7973 *dst = TOUPPER (*src);
7977 /* Assume STR point to a lower-case string, allocate, convert and return
7978 the corresponding upper-case string. */
7979 static inline const char*
7980 get_upper_str (const char *str)
7983 size_t len = strlen (str);
7984 ret = XNEWVEC (char, len + 1);
7985 convert_to_upper (ret, str, len);
7989 /* MD interface: Initialization. */
7997 if ((aarch64_ops_hsh = hash_new ()) == NULL
7998 || (aarch64_cond_hsh = hash_new ()) == NULL
7999 || (aarch64_shift_hsh = hash_new ()) == NULL
8000 || (aarch64_sys_regs_hsh = hash_new ()) == NULL
8001 || (aarch64_pstatefield_hsh = hash_new ()) == NULL
8002 || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
8003 || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
8004 || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
8005 || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
8006 || (aarch64_reg_hsh = hash_new ()) == NULL
8007 || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
8008 || (aarch64_nzcv_hsh = hash_new ()) == NULL
8009 || (aarch64_pldop_hsh = hash_new ()) == NULL
8010 || (aarch64_hint_opt_hsh = hash_new ()) == NULL)
8011 as_fatal (_("virtual memory exhausted"));
8013 fill_instruction_hash_table ();
8015 for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
8016 checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
8017 (void *) (aarch64_sys_regs + i));
8019 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
8020 checked_hash_insert (aarch64_pstatefield_hsh,
8021 aarch64_pstatefields[i].name,
8022 (void *) (aarch64_pstatefields + i));
8024 for (i = 0; aarch64_sys_regs_ic[i].name != NULL; i++)
8025 checked_hash_insert (aarch64_sys_regs_ic_hsh,
8026 aarch64_sys_regs_ic[i].name,
8027 (void *) (aarch64_sys_regs_ic + i));
8029 for (i = 0; aarch64_sys_regs_dc[i].name != NULL; i++)
8030 checked_hash_insert (aarch64_sys_regs_dc_hsh,
8031 aarch64_sys_regs_dc[i].name,
8032 (void *) (aarch64_sys_regs_dc + i));
8034 for (i = 0; aarch64_sys_regs_at[i].name != NULL; i++)
8035 checked_hash_insert (aarch64_sys_regs_at_hsh,
8036 aarch64_sys_regs_at[i].name,
8037 (void *) (aarch64_sys_regs_at + i));
8039 for (i = 0; aarch64_sys_regs_tlbi[i].name != NULL; i++)
8040 checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
8041 aarch64_sys_regs_tlbi[i].name,
8042 (void *) (aarch64_sys_regs_tlbi + i));
8044 for (i = 0; i < ARRAY_SIZE (reg_names); i++)
8045 checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
8046 (void *) (reg_names + i));
8048 for (i = 0; i < ARRAY_SIZE (nzcv_names); i++)
8049 checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template,
8050 (void *) (nzcv_names + i));
8052 for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++)
8054 const char *name = aarch64_operand_modifiers[i].name;
8055 checked_hash_insert (aarch64_shift_hsh, name,
8056 (void *) (aarch64_operand_modifiers + i));
8057 /* Also hash the name in the upper case. */
8058 checked_hash_insert (aarch64_shift_hsh, get_upper_str (name),
8059 (void *) (aarch64_operand_modifiers + i));
8062 for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++)
8065 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8066 the same condition code. */
8067 for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j)
8069 const char *name = aarch64_conds[i].names[j];
8072 checked_hash_insert (aarch64_cond_hsh, name,
8073 (void *) (aarch64_conds + i));
8074 /* Also hash the name in the upper case. */
8075 checked_hash_insert (aarch64_cond_hsh, get_upper_str (name),
8076 (void *) (aarch64_conds + i));
8080 for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++)
8082 const char *name = aarch64_barrier_options[i].name;
8083 /* Skip xx00 - the unallocated values of option. */
8086 checked_hash_insert (aarch64_barrier_opt_hsh, name,
8087 (void *) (aarch64_barrier_options + i));
8088 /* Also hash the name in the upper case. */
8089 checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
8090 (void *) (aarch64_barrier_options + i));
8093 for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
8095 const char* name = aarch64_prfops[i].name;
8096 /* Skip the unallocated hint encodings. */
8099 checked_hash_insert (aarch64_pldop_hsh, name,
8100 (void *) (aarch64_prfops + i));
8101 /* Also hash the name in the upper case. */
8102 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
8103 (void *) (aarch64_prfops + i));
8106 for (i = 0; aarch64_hint_options[i].name != NULL; i++)
8108 const char* name = aarch64_hint_options[i].name;
8110 checked_hash_insert (aarch64_hint_opt_hsh, name,
8111 (void *) (aarch64_hint_options + i));
8112 /* Also hash the name in the upper case. */
8113 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
8114 (void *) (aarch64_hint_options + i));
8117 /* Set the cpu variant based on the command-line options. */
8119 mcpu_cpu_opt = march_cpu_opt;
8122 mcpu_cpu_opt = &cpu_default;
8124 cpu_variant = *mcpu_cpu_opt;
8126 /* Record the CPU type. */
8127 mach = ilp32_p ? bfd_mach_aarch64_ilp32 : bfd_mach_aarch64;
8129 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
8132 /* Command line processing. */
8134 const char *md_shortopts = "m:";
8136 #ifdef AARCH64_BI_ENDIAN
8137 #define OPTION_EB (OPTION_MD_BASE + 0)
8138 #define OPTION_EL (OPTION_MD_BASE + 1)
8140 #if TARGET_BYTES_BIG_ENDIAN
8141 #define OPTION_EB (OPTION_MD_BASE + 0)
8143 #define OPTION_EL (OPTION_MD_BASE + 1)
8147 struct option md_longopts[] = {
8149 {"EB", no_argument, NULL, OPTION_EB},
8152 {"EL", no_argument, NULL, OPTION_EL},
8154 {NULL, no_argument, NULL, 0}
8157 size_t md_longopts_size = sizeof (md_longopts);
8159 struct aarch64_option_table
8161 const char *option; /* Option name to match. */
8162 const char *help; /* Help information. */
8163 int *var; /* Variable to change. */
8164 int value; /* What to change it to. */
8165 char *deprecated; /* If non-null, print this message. */
8168 static struct aarch64_option_table aarch64_opts[] = {
8169 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
8170 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
8172 #ifdef DEBUG_AARCH64
8173 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL},
8174 #endif /* DEBUG_AARCH64 */
8175 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1,
8177 {"mno-verbose-error", N_("do not output verbose error messages"),
8178 &verbose_error_p, 0, NULL},
8179 {NULL, NULL, NULL, 0, NULL}
8182 struct aarch64_cpu_option_table
8185 const aarch64_feature_set value;
8186 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8188 const char *canonical_name;
8191 /* This list should, at a minimum, contain all the cpu names
8192 recognized by GCC. */
8193 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
8194 {"all", AARCH64_ANY, NULL},
8195 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
8196 AARCH64_FEATURE_CRC), "Cortex-A35"},
8197 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,
8198 AARCH64_FEATURE_CRC), "Cortex-A53"},
8199 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8,
8200 AARCH64_FEATURE_CRC), "Cortex-A57"},
8201 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8,
8202 AARCH64_FEATURE_CRC), "Cortex-A72"},
8203 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8,
8204 AARCH64_FEATURE_CRC), "Cortex-A73"},
8205 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
8206 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
8207 "Samsung Exynos M1"},
8208 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8,
8209 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
8210 "Qualcomm QDF24XX"},
8211 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8,
8212 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
8214 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1,
8215 AARCH64_FEATURE_CRYPTO),
8217 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8218 in earlier releases and is superseded by 'xgene1' in all
8220 {"xgene-1", AARCH64_ARCH_V8, "APM X-Gene 1"},
8221 {"xgene1", AARCH64_ARCH_V8, "APM X-Gene 1"},
8222 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8,
8223 AARCH64_FEATURE_CRC), "APM X-Gene 2"},
8224 {"generic", AARCH64_ARCH_V8, NULL},
8226 {NULL, AARCH64_ARCH_NONE, NULL}
8229 struct aarch64_arch_option_table
8232 const aarch64_feature_set value;
8235 /* This list should, at a minimum, contain all the architecture names
8236 recognized by GCC. */
8237 static const struct aarch64_arch_option_table aarch64_archs[] = {
8238 {"all", AARCH64_ANY},
8239 {"armv8-a", AARCH64_ARCH_V8},
8240 {"armv8.1-a", AARCH64_ARCH_V8_1},
8241 {"armv8.2-a", AARCH64_ARCH_V8_2},
8242 {NULL, AARCH64_ARCH_NONE}
8245 /* ISA extensions. */
8246 struct aarch64_option_cpu_value_table
8249 const aarch64_feature_set value;
8250 const aarch64_feature_set require; /* Feature dependencies. */
8253 static const struct aarch64_option_cpu_value_table aarch64_features[] = {
8254 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0),
8256 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0),
8258 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0),
8260 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0),
8262 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0),
8264 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0),
8266 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0),
8268 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0),
8270 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0),
8271 AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
8272 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16, 0),
8273 AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
8274 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
8276 {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
8279 struct aarch64_long_option_table
8281 const char *option; /* Substring to match. */
8282 const char *help; /* Help information. */
8283 int (*func) (const char *subopt); /* Function to decode sub-option. */
8284 char *deprecated; /* If non-null, print this message. */
8287 /* Transitive closure of features depending on set. */
8288 static aarch64_feature_set
8289 aarch64_feature_disable_set (aarch64_feature_set set)
8291 const struct aarch64_option_cpu_value_table *opt;
8292 aarch64_feature_set prev = 0;
8294 while (prev != set) {
8296 for (opt = aarch64_features; opt->name != NULL; opt++)
8297 if (AARCH64_CPU_HAS_ANY_FEATURES (opt->require, set))
8298 AARCH64_MERGE_FEATURE_SETS (set, set, opt->value);
8303 /* Transitive closure of dependencies of set. */
8304 static aarch64_feature_set
8305 aarch64_feature_enable_set (aarch64_feature_set set)
8307 const struct aarch64_option_cpu_value_table *opt;
8308 aarch64_feature_set prev = 0;
8310 while (prev != set) {
8312 for (opt = aarch64_features; opt->name != NULL; opt++)
8313 if (AARCH64_CPU_HAS_FEATURE (set, opt->value))
8314 AARCH64_MERGE_FEATURE_SETS (set, set, opt->require);
8320 aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p,
8321 bfd_boolean ext_only)
8323 /* We insist on extensions being added before being removed. We achieve
8324 this by using the ADDING_VALUE variable to indicate whether we are
8325 adding an extension (1) or removing it (0) and only allowing it to
8326 change in the order -1 -> 1 -> 0. */
8327 int adding_value = -1;
8328 aarch64_feature_set *ext_set = XNEW (aarch64_feature_set);
8330 /* Copy the feature set, so that we can modify it. */
8334 while (str != NULL && *str != 0)
8336 const struct aarch64_option_cpu_value_table *opt;
8337 const char *ext = NULL;
8344 as_bad (_("invalid architectural extension"));
8348 ext = strchr (++str, '+');
8354 optlen = strlen (str);
8356 if (optlen >= 2 && strncmp (str, "no", 2) == 0)
8358 if (adding_value != 0)
8363 else if (optlen > 0)
8365 if (adding_value == -1)
8367 else if (adding_value != 1)
8369 as_bad (_("must specify extensions to add before specifying "
8370 "those to remove"));
8377 as_bad (_("missing architectural extension"));
8381 gas_assert (adding_value != -1);
8383 for (opt = aarch64_features; opt->name != NULL; opt++)
8384 if (strncmp (opt->name, str, optlen) == 0)
8386 aarch64_feature_set set;
8388 /* Add or remove the extension. */
8391 set = aarch64_feature_enable_set (opt->value);
8392 AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, set);
8396 set = aarch64_feature_disable_set (opt->value);
8397 AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, set);
8402 if (opt->name == NULL)
8404 as_bad (_("unknown architectural extension `%s'"), str);
8415 aarch64_parse_cpu (const char *str)
8417 const struct aarch64_cpu_option_table *opt;
8418 const char *ext = strchr (str, '+');
8424 optlen = strlen (str);
8428 as_bad (_("missing cpu name `%s'"), str);
8432 for (opt = aarch64_cpus; opt->name != NULL; opt++)
8433 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
8435 mcpu_cpu_opt = &opt->value;
8437 return aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE);
8442 as_bad (_("unknown cpu `%s'"), str);
8447 aarch64_parse_arch (const char *str)
8449 const struct aarch64_arch_option_table *opt;
8450 const char *ext = strchr (str, '+');
8456 optlen = strlen (str);
8460 as_bad (_("missing architecture name `%s'"), str);
8464 for (opt = aarch64_archs; opt->name != NULL; opt++)
8465 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
8467 march_cpu_opt = &opt->value;
8469 return aarch64_parse_features (ext, &march_cpu_opt, FALSE);
8474 as_bad (_("unknown architecture `%s'\n"), str);
8479 struct aarch64_option_abi_value_table
8482 enum aarch64_abi_type value;
8485 static const struct aarch64_option_abi_value_table aarch64_abis[] = {
8486 {"ilp32", AARCH64_ABI_ILP32},
8487 {"lp64", AARCH64_ABI_LP64},
8491 aarch64_parse_abi (const char *str)
8497 as_bad (_("missing abi name `%s'"), str);
8501 for (i = 0; i < ARRAY_SIZE (aarch64_abis); i++)
8502 if (strcmp (str, aarch64_abis[i].name) == 0)
8504 aarch64_abi = aarch64_abis[i].value;
8508 as_bad (_("unknown abi `%s'\n"), str);
8512 static struct aarch64_long_option_table aarch64_long_opts[] = {
8514 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8515 aarch64_parse_abi, NULL},
8516 #endif /* OBJ_ELF */
8517 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8518 aarch64_parse_cpu, NULL},
8519 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8520 aarch64_parse_arch, NULL},
8521 {NULL, NULL, 0, NULL}
8525 md_parse_option (int c, const char *arg)
8527 struct aarch64_option_table *opt;
8528 struct aarch64_long_option_table *lopt;
8534 target_big_endian = 1;
8540 target_big_endian = 0;
8545 /* Listing option. Just ignore these, we don't support additional
8550 for (opt = aarch64_opts; opt->option != NULL; opt++)
8552 if (c == opt->option[0]
8553 && ((arg == NULL && opt->option[1] == 0)
8554 || streq (arg, opt->option + 1)))
8556 /* If the option is deprecated, tell the user. */
8557 if (opt->deprecated != NULL)
8558 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
8559 arg ? arg : "", _(opt->deprecated));
8561 if (opt->var != NULL)
8562 *opt->var = opt->value;
8568 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
8570 /* These options are expected to have an argument. */
8571 if (c == lopt->option[0]
8573 && strncmp (arg, lopt->option + 1,
8574 strlen (lopt->option + 1)) == 0)
8576 /* If the option is deprecated, tell the user. */
8577 if (lopt->deprecated != NULL)
8578 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
8579 _(lopt->deprecated));
8581 /* Call the sup-option parser. */
8582 return lopt->func (arg + strlen (lopt->option) - 1);
8593 md_show_usage (FILE * fp)
8595 struct aarch64_option_table *opt;
8596 struct aarch64_long_option_table *lopt;
8598 fprintf (fp, _(" AArch64-specific assembler options:\n"));
8600 for (opt = aarch64_opts; opt->option != NULL; opt++)
8601 if (opt->help != NULL)
8602 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
8604 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
8605 if (lopt->help != NULL)
8606 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
8610 -EB assemble code for a big-endian cpu\n"));
8615 -EL assemble code for a little-endian cpu\n"));
8619 /* Parse a .cpu directive. */
8622 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
8624 const struct aarch64_cpu_option_table *opt;
8630 name = input_line_pointer;
8631 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8632 input_line_pointer++;
8633 saved_char = *input_line_pointer;
8634 *input_line_pointer = 0;
8636 ext = strchr (name, '+');
8639 optlen = ext - name;
8641 optlen = strlen (name);
8643 /* Skip the first "all" entry. */
8644 for (opt = aarch64_cpus + 1; opt->name != NULL; opt++)
8645 if (strlen (opt->name) == optlen
8646 && strncmp (name, opt->name, optlen) == 0)
8648 mcpu_cpu_opt = &opt->value;
8650 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
8653 cpu_variant = *mcpu_cpu_opt;
8655 *input_line_pointer = saved_char;
8656 demand_empty_rest_of_line ();
8659 as_bad (_("unknown cpu `%s'"), name);
8660 *input_line_pointer = saved_char;
8661 ignore_rest_of_line ();
8665 /* Parse a .arch directive. */
8668 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
8670 const struct aarch64_arch_option_table *opt;
8676 name = input_line_pointer;
8677 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8678 input_line_pointer++;
8679 saved_char = *input_line_pointer;
8680 *input_line_pointer = 0;
8682 ext = strchr (name, '+');
8685 optlen = ext - name;
8687 optlen = strlen (name);
8689 /* Skip the first "all" entry. */
8690 for (opt = aarch64_archs + 1; opt->name != NULL; opt++)
8691 if (strlen (opt->name) == optlen
8692 && strncmp (name, opt->name, optlen) == 0)
8694 mcpu_cpu_opt = &opt->value;
8696 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
8699 cpu_variant = *mcpu_cpu_opt;
8701 *input_line_pointer = saved_char;
8702 demand_empty_rest_of_line ();
8706 as_bad (_("unknown architecture `%s'\n"), name);
8707 *input_line_pointer = saved_char;
8708 ignore_rest_of_line ();
8711 /* Parse a .arch_extension directive. */
8714 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED)
8717 char *ext = input_line_pointer;;
8719 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8720 input_line_pointer++;
8721 saved_char = *input_line_pointer;
8722 *input_line_pointer = 0;
8724 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, TRUE))
8727 cpu_variant = *mcpu_cpu_opt;
8729 *input_line_pointer = saved_char;
8730 demand_empty_rest_of_line ();
8733 /* Copy symbol information. */
8736 aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
8738 AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);