1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2015 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set *mcpu_cpu_opt = NULL;
53 static const aarch64_feature_set *march_cpu_opt = NULL;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default = CPU_DEFAULT;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS *GOT_symbol;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_LP64;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type;
96 unsigned char defined;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type;
108 enum aarch64_opnd opnd;
110 unsigned need_libopcodes_p : 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool : 1;
131 typedef struct aarch64_instruction aarch64_instruction;
133 static aarch64_instruction inst;
135 static bfd_boolean parse_operands (char *, const aarch64_opcode *);
136 static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst.parsing_error.kind = AARCH64_OPDE_NIL;
159 inst.parsing_error.error = NULL;
162 static inline bfd_boolean
165 return inst.parsing_error.kind != AARCH64_OPDE_NIL;
168 static inline const char *
169 get_error_message (void)
171 return inst.parsing_error.error;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst.parsing_error.kind;
181 set_error (enum aarch64_operand_error_kind kind, const char *error)
183 inst.parsing_error.kind = kind;
184 inst.parsing_error.error = error;
188 set_recoverable_error (const char *error)
190 set_error (AARCH64_OPDE_RECOVERABLE, error);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
202 set_syntax_error (const char *error)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
208 set_first_syntax_error (const char *error)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
215 set_fatal_syntax_error (const char *error)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number;
256 unsigned char builtin;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type)
339 msg = N_("integer 32-bit register expected");
342 msg = N_("integer 64-bit register expected");
345 msg = N_("integer register expected");
347 case REG_TYPE_R_Z_SP:
348 msg = N_("integer, zero or SP register expected");
351 msg = N_("8-bit SIMD scalar register expected");
354 msg = N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg = N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg = N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg = N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg = N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V:
373 msg = N_("register expected");
375 case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
376 msg = N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN: /* any V reg */
379 msg = N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control *aarch64_ops_hsh;
397 static struct hash_control *aarch64_cond_hsh;
398 static struct hash_control *aarch64_shift_hsh;
399 static struct hash_control *aarch64_sys_regs_hsh;
400 static struct hash_control *aarch64_pstatefield_hsh;
401 static struct hash_control *aarch64_sys_regs_ic_hsh;
402 static struct hash_control *aarch64_sys_regs_dc_hsh;
403 static struct hash_control *aarch64_sys_regs_at_hsh;
404 static struct hash_control *aarch64_sys_regs_tlbi_hsh;
405 static struct hash_control *aarch64_reg_hsh;
406 static struct hash_control *aarch64_barrier_opt_hsh;
407 static struct hash_control *aarch64_nzcv_hsh;
408 static struct hash_control *aarch64_pldop_hsh;
410 /* Stuff needed to resolve the label ambiguity
419 static symbolS *last_label_seen;
421 /* Literal pool structure. Held on a per-section
422 and per-sub-section basis. */
424 #define MAX_LITERAL_POOL_SIZE 1024
425 typedef struct literal_expression
428 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
429 LITTLENUM_TYPE * bignum;
430 } literal_expression;
432 typedef struct literal_pool
434 literal_expression literals[MAX_LITERAL_POOL_SIZE];
435 unsigned int next_free_entry;
441 struct literal_pool *next;
444 /* Pointer to a linked list of literal pools. */
445 static literal_pool *list_of_pools = NULL;
449 /* This array holds the chars that always start a comment. If the
450 pre-processor is disabled, these aren't very useful. */
451 const char comment_chars[] = "";
453 /* This array holds the chars that only start a comment at the beginning of
454 a line. If the line seems to have the form '# 123 filename'
455 .line and .file directives will appear in the pre-processed output. */
456 /* Note that input_file.c hand checks for '#' at the beginning of the
457 first line of the input file. This is because the compiler outputs
458 #NO_APP at the beginning of its output. */
459 /* Also note that comments like this one will always work. */
460 const char line_comment_chars[] = "#";
462 const char line_separator_chars[] = ";";
464 /* Chars that can be used to separate mant
465 from exp in floating point numbers. */
466 const char EXP_CHARS[] = "eE";
468 /* Chars that mean this number is a floating point constant. */
472 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
474 /* Prefix character that indicates the start of an immediate value. */
475 #define is_immediate_prefix(C) ((C) == '#')
477 /* Separator character handling. */
479 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
481 static inline bfd_boolean
482 skip_past_char (char **str, char c)
493 #define skip_past_comma(str) skip_past_char (str, ',')
495 /* Arithmetic expressions (possibly involving symbols). */
497 static bfd_boolean in_my_get_expression_p = FALSE;
499 /* Third argument to my_get_expression. */
500 #define GE_NO_PREFIX 0
501 #define GE_OPT_PREFIX 1
503 /* Return TRUE if the string pointed by *STR is successfully parsed
504 as an valid expression; *EP will be filled with the information of
505 such an expression. Otherwise return FALSE. */
508 my_get_expression (expressionS * ep, char **str, int prefix_mode,
513 int prefix_present_p = 0;
520 if (is_immediate_prefix (**str))
523 prefix_present_p = 1;
530 memset (ep, 0, sizeof (expressionS));
532 save_in = input_line_pointer;
533 input_line_pointer = *str;
534 in_my_get_expression_p = TRUE;
535 seg = expression (ep);
536 in_my_get_expression_p = FALSE;
538 if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
540 /* We found a bad expression in md_operand(). */
541 *str = input_line_pointer;
542 input_line_pointer = save_in;
543 if (prefix_present_p && ! error_p ())
544 set_fatal_syntax_error (_("bad expression"));
546 set_first_syntax_error (_("bad expression"));
551 if (seg != absolute_section
552 && seg != text_section
553 && seg != data_section
554 && seg != bss_section && seg != undefined_section)
556 set_syntax_error (_("bad segment"));
557 *str = input_line_pointer;
558 input_line_pointer = save_in;
565 *str = input_line_pointer;
566 input_line_pointer = save_in;
570 /* Turn a string in input_line_pointer into a floating point constant
571 of type TYPE, and store the appropriate bytes in *LITP. The number
572 of LITTLENUMS emitted is stored in *SIZEP. An error message is
573 returned, or NULL on OK. */
576 md_atof (int type, char *litP, int *sizeP)
578 return ieee_md_atof (type, litP, sizeP, target_big_endian);
581 /* We handle all bad expressions here, so that we can report the faulty
582 instruction in the error message. */
584 md_operand (expressionS * exp)
586 if (in_my_get_expression_p)
587 exp->X_op = O_illegal;
590 /* Immediate values. */
592 /* Errors may be set multiple times during parsing or bit encoding
593 (particularly in the Neon bits), but usually the earliest error which is set
594 will be the most meaningful. Avoid overwriting it with later (cascading)
595 errors by calling this function. */
598 first_error (const char *error)
601 set_syntax_error (error);
604 /* Similiar to first_error, but this function accepts formatted error
607 first_error_fmt (const char *format, ...)
612 /* N.B. this single buffer will not cause error messages for different
613 instructions to pollute each other; this is because at the end of
614 processing of each assembly line, error message if any will be
615 collected by as_bad. */
616 static char buffer[size];
620 int ret ATTRIBUTE_UNUSED;
621 va_start (args, format);
622 ret = vsnprintf (buffer, size, format, args);
623 know (ret <= size - 1 && ret >= 0);
625 set_syntax_error (buffer);
629 /* Register parsing. */
631 /* Generic register parser which is called by other specialized
633 CCP points to what should be the beginning of a register name.
634 If it is indeed a valid register name, advance CCP over it and
635 return the reg_entry structure; otherwise return NULL.
636 It does not issue diagnostics. */
639 parse_reg (char **ccp)
645 #ifdef REGISTER_PREFIX
646 if (*start != REGISTER_PREFIX)
652 if (!ISALPHA (*p) || !is_name_beginner (*p))
657 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
659 reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start);
668 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
671 aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
673 if (reg->type == type)
678 case REG_TYPE_R64_SP: /* 64-bit integer reg (inc SP exc XZR). */
679 case REG_TYPE_R_Z_SP: /* Integer reg (inc {X}SP inc [WX]ZR). */
680 case REG_TYPE_R_Z_BHSDQ_V: /* Any register apart from Cn. */
681 case REG_TYPE_BHSDQ: /* Any [BHSDQ]P FP or SIMD scalar register. */
682 case REG_TYPE_VN: /* Vector register. */
683 gas_assert (reg->type < REG_TYPE_MAX && type < REG_TYPE_MAX);
684 return ((reg_type_masks[reg->type] & reg_type_masks[type])
685 == reg_type_masks[reg->type]);
687 as_fatal ("unhandled type %d", type);
692 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
693 Return the register number otherwise. *ISREG32 is set to one if the
694 register is 32-bit wide; *ISREGZERO is set to one if the register is
695 of type Z_32 or Z_64.
696 Note that this function does not issue any diagnostics. */
699 aarch64_reg_parse_32_64 (char **ccp, int reject_sp, int reject_rz,
700 int *isreg32, int *isregzero)
703 const reg_entry *reg = parse_reg (&str);
708 if (! aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP))
717 *isreg32 = reg->type == REG_TYPE_SP_32;
722 *isreg32 = reg->type == REG_TYPE_R_32;
729 *isreg32 = reg->type == REG_TYPE_Z_32;
741 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
742 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
743 otherwise return FALSE.
745 Accept only one occurrence of:
746 8b 16b 4h 8h 2s 4s 1d 2d
749 parse_neon_type_for_operand (struct neon_type_el *parsed_type, char **str)
753 unsigned element_size;
754 enum neon_el_type type;
764 width = strtoul (ptr, &ptr, 10);
765 if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
767 first_error_fmt (_("bad size %d in vector width specifier"), width);
772 switch (TOLOWER (*ptr))
800 first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
802 first_error (_("missing element size"));
805 if (width != 0 && width * element_size != 64 && width * element_size != 128)
808 ("invalid element size %d and vector size combination %c"),
814 parsed_type->type = type;
815 parsed_type->width = width;
822 /* Parse a single type, e.g. ".8b", leading period included.
823 Only applicable to Vn registers.
825 Return TRUE on success; otherwise return FALSE. */
827 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
833 if (! parse_neon_type_for_operand (vectype, &str))
835 first_error (_("vector type expected"));
847 /* Parse a register of the type TYPE.
849 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
850 name or the parsed register is not of TYPE.
852 Otherwise return the register number, and optionally fill in the actual
853 type of the register in *RTYPE when multiple alternatives were given, and
854 return the register shape and element index information in *TYPEINFO.
856 IN_REG_LIST should be set with TRUE if the caller is parsing a register
860 parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
861 struct neon_type_el *typeinfo, bfd_boolean in_reg_list)
864 const reg_entry *reg = parse_reg (&str);
865 struct neon_type_el atype;
866 struct neon_type_el parsetype;
867 bfd_boolean is_typed_vecreg = FALSE;
870 atype.type = NT_invtype;
878 set_default_error ();
882 if (! aarch64_check_reg_type (reg, type))
884 DEBUG_TRACE ("reg type check failed");
885 set_default_error ();
890 if (type == REG_TYPE_VN
891 && parse_neon_operand_type (&parsetype, &str))
893 /* Register if of the form Vn.[bhsdq]. */
894 is_typed_vecreg = TRUE;
896 if (parsetype.width == 0)
897 /* Expect index. In the new scheme we cannot have
898 Vn.[bhsdq] represent a scalar. Therefore any
899 Vn.[bhsdq] should have an index following it.
900 Except in reglists ofcourse. */
901 atype.defined |= NTA_HASINDEX;
903 atype.defined |= NTA_HASTYPE;
905 atype.type = parsetype.type;
906 atype.width = parsetype.width;
909 if (skip_past_char (&str, '['))
913 /* Reject Sn[index] syntax. */
914 if (!is_typed_vecreg)
916 first_error (_("this type of register can't be indexed"));
920 if (in_reg_list == TRUE)
922 first_error (_("index not allowed inside register list"));
926 atype.defined |= NTA_HASINDEX;
928 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
930 if (exp.X_op != O_constant)
932 first_error (_("constant expression required"));
936 if (! skip_past_char (&str, ']'))
939 atype.index = exp.X_add_number;
941 else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
943 /* Indexed vector register expected. */
944 first_error (_("indexed vector register expected"));
948 /* A vector reg Vn should be typed or indexed. */
949 if (type == REG_TYPE_VN && atype.defined == 0)
951 first_error (_("invalid use of vector register"));
967 Return the register number on success; return PARSE_FAIL otherwise.
969 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
970 the register (e.g. NEON double or quad reg when either has been requested).
972 If this is a NEON vector register with additional type information, fill
973 in the struct pointed to by VECTYPE (if non-NULL).
975 This parser does not handle register list. */
978 aarch64_reg_parse (char **ccp, aarch64_reg_type type,
979 aarch64_reg_type *rtype, struct neon_type_el *vectype)
981 struct neon_type_el atype;
983 int reg = parse_typed_reg (&str, type, rtype, &atype,
984 /*in_reg_list= */ FALSE);
986 if (reg == PARSE_FAIL)
997 static inline bfd_boolean
998 eq_neon_type_el (struct neon_type_el e1, struct neon_type_el e2)
1002 && e1.defined == e2.defined
1003 && e1.width == e2.width && e1.index == e2.index;
1006 /* This function parses the NEON register list. On success, it returns
1007 the parsed register list information in the following encoded format:
1009 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1010 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1012 The information of the register shape and/or index is returned in
1015 It returns PARSE_FAIL if the register list is invalid.
1017 The list contains one to four registers.
1018 Each register can be one of:
1021 All <T> should be identical.
1022 All <index> should be identical.
1023 There are restrictions on <Vt> numbers which are checked later
1024 (by reg_list_valid_p). */
1027 parse_neon_reg_list (char **ccp, struct neon_type_el *vectype)
1031 struct neon_type_el typeinfo, typeinfo_first;
1036 bfd_boolean error = FALSE;
1037 bfd_boolean expect_index = FALSE;
1041 set_syntax_error (_("expecting {"));
1047 typeinfo_first.defined = 0;
1048 typeinfo_first.type = NT_invtype;
1049 typeinfo_first.width = -1;
1050 typeinfo_first.index = 0;
1059 str++; /* skip over '-' */
1062 val = parse_typed_reg (&str, REG_TYPE_VN, NULL, &typeinfo,
1063 /*in_reg_list= */ TRUE);
1064 if (val == PARSE_FAIL)
1066 set_first_syntax_error (_("invalid vector register in list"));
1070 /* reject [bhsd]n */
1071 if (typeinfo.defined == 0)
1073 set_first_syntax_error (_("invalid scalar register in list"));
1078 if (typeinfo.defined & NTA_HASINDEX)
1079 expect_index = TRUE;
1083 if (val < val_range)
1085 set_first_syntax_error
1086 (_("invalid range in vector register list"));
1095 typeinfo_first = typeinfo;
1096 else if (! eq_neon_type_el (typeinfo_first, typeinfo))
1098 set_first_syntax_error
1099 (_("type mismatch in vector register list"));
1104 for (i = val_range; i <= val; i++)
1106 ret_val |= i << (5 * nb_regs);
1111 while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
1113 skip_whitespace (str);
1116 set_first_syntax_error (_("end of vector register list not found"));
1121 skip_whitespace (str);
1125 if (skip_past_char (&str, '['))
1129 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1130 if (exp.X_op != O_constant)
1132 set_first_syntax_error (_("constant expression required."));
1135 if (! skip_past_char (&str, ']'))
1138 typeinfo_first.index = exp.X_add_number;
1142 set_first_syntax_error (_("expected index"));
1149 set_first_syntax_error (_("too many registers in vector register list"));
1152 else if (nb_regs == 0)
1154 set_first_syntax_error (_("empty vector register list"));
1160 *vectype = typeinfo_first;
1162 return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1);
1165 /* Directives: register aliases. */
1168 insert_reg_alias (char *str, int number, aarch64_reg_type type)
1173 if ((new = hash_find (aarch64_reg_hsh, str)) != 0)
1176 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1179 /* Only warn about a redefinition if it's not defined as the
1181 else if (new->number != number || new->type != type)
1182 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1187 name = xstrdup (str);
1188 new = xmalloc (sizeof (reg_entry));
1191 new->number = number;
1193 new->builtin = FALSE;
1195 if (hash_insert (aarch64_reg_hsh, name, (void *) new))
1201 /* Look for the .req directive. This is of the form:
1203 new_register_name .req existing_register_name
1205 If we find one, or if it looks sufficiently like one that we want to
1206 handle any error here, return TRUE. Otherwise return FALSE. */
1209 create_register_alias (char *newname, char *p)
1211 const reg_entry *old;
1212 char *oldname, *nbuf;
1215 /* The input scrubber ensures that whitespace after the mnemonic is
1216 collapsed to single spaces. */
1218 if (strncmp (oldname, " .req ", 6) != 0)
1222 if (*oldname == '\0')
1225 old = hash_find (aarch64_reg_hsh, oldname);
1228 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1232 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1233 the desired alias name, and p points to its end. If not, then
1234 the desired alias name is in the global original_case_string. */
1235 #ifdef TC_CASE_SENSITIVE
1238 newname = original_case_string;
1239 nlen = strlen (newname);
1242 nbuf = alloca (nlen + 1);
1243 memcpy (nbuf, newname, nlen);
1246 /* Create aliases under the new name as stated; an all-lowercase
1247 version of the new name; and an all-uppercase version of the new
1249 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
1251 for (p = nbuf; *p; p++)
1254 if (strncmp (nbuf, newname, nlen))
1256 /* If this attempt to create an additional alias fails, do not bother
1257 trying to create the all-lower case alias. We will fail and issue
1258 a second, duplicate error message. This situation arises when the
1259 programmer does something like:
1262 The second .req creates the "Foo" alias but then fails to create
1263 the artificial FOO alias because it has already been created by the
1265 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
1269 for (p = nbuf; *p; p++)
1272 if (strncmp (nbuf, newname, nlen))
1273 insert_reg_alias (nbuf, old->number, old->type);
1279 /* Should never be called, as .req goes between the alias and the
1280 register name, not at the beginning of the line. */
1282 s_req (int a ATTRIBUTE_UNUSED)
1284 as_bad (_("invalid syntax for .req directive"));
1287 /* The .unreq directive deletes an alias which was previously defined
1288 by .req. For example:
1294 s_unreq (int a ATTRIBUTE_UNUSED)
1299 name = input_line_pointer;
1301 while (*input_line_pointer != 0
1302 && *input_line_pointer != ' ' && *input_line_pointer != '\n')
1303 ++input_line_pointer;
1305 saved_char = *input_line_pointer;
1306 *input_line_pointer = 0;
1309 as_bad (_("invalid syntax for .unreq directive"));
1312 reg_entry *reg = hash_find (aarch64_reg_hsh, name);
1315 as_bad (_("unknown register alias '%s'"), name);
1316 else if (reg->builtin)
1317 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1324 hash_delete (aarch64_reg_hsh, name, FALSE);
1325 free ((char *) reg->name);
1328 /* Also locate the all upper case and all lower case versions.
1329 Do not complain if we cannot find one or the other as it
1330 was probably deleted above. */
1332 nbuf = strdup (name);
1333 for (p = nbuf; *p; p++)
1335 reg = hash_find (aarch64_reg_hsh, nbuf);
1338 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1339 free ((char *) reg->name);
1343 for (p = nbuf; *p; p++)
1345 reg = hash_find (aarch64_reg_hsh, nbuf);
1348 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1349 free ((char *) reg->name);
1357 *input_line_pointer = saved_char;
1358 demand_empty_rest_of_line ();
1361 /* Directives: Instruction set selection. */
1364 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1365 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1366 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1367 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1369 /* Create a new mapping symbol for the transition to STATE. */
1372 make_mapping_symbol (enum mstate state, valueT value, fragS * frag)
1375 const char *symname;
1382 type = BSF_NO_FLAGS;
1386 type = BSF_NO_FLAGS;
1392 symbolP = symbol_new (symname, now_seg, value, frag);
1393 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1395 /* Save the mapping symbols for future reference. Also check that
1396 we do not place two mapping symbols at the same offset within a
1397 frag. We'll handle overlap between frags in
1398 check_mapping_symbols.
1400 If .fill or other data filling directive generates zero sized data,
1401 the mapping symbol for the following code will have the same value
1402 as the one generated for the data filling directive. In this case,
1403 we replace the old symbol with the new one at the same address. */
1406 if (frag->tc_frag_data.first_map != NULL)
1408 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
1409 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP,
1412 frag->tc_frag_data.first_map = symbolP;
1414 if (frag->tc_frag_data.last_map != NULL)
1416 know (S_GET_VALUE (frag->tc_frag_data.last_map) <=
1417 S_GET_VALUE (symbolP));
1418 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
1419 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP,
1422 frag->tc_frag_data.last_map = symbolP;
1425 /* We must sometimes convert a region marked as code to data during
1426 code alignment, if an odd number of bytes have to be padded. The
1427 code mapping symbol is pushed to an aligned address. */
1430 insert_data_mapping_symbol (enum mstate state,
1431 valueT value, fragS * frag, offsetT bytes)
1433 /* If there was already a mapping symbol, remove it. */
1434 if (frag->tc_frag_data.last_map != NULL
1435 && S_GET_VALUE (frag->tc_frag_data.last_map) ==
1436 frag->fr_address + value)
1438 symbolS *symp = frag->tc_frag_data.last_map;
1442 know (frag->tc_frag_data.first_map == symp);
1443 frag->tc_frag_data.first_map = NULL;
1445 frag->tc_frag_data.last_map = NULL;
1446 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
1449 make_mapping_symbol (MAP_DATA, value, frag);
1450 make_mapping_symbol (state, value + bytes, frag);
1453 static void mapping_state_2 (enum mstate state, int max_chars);
1455 /* Set the mapping state to STATE. Only call this when about to
1456 emit some STATE bytes to the file. */
1459 mapping_state (enum mstate state)
1461 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1463 if (state == MAP_INSN)
1464 /* AArch64 instructions require 4-byte alignment. When emitting
1465 instructions into any section, record the appropriate section
1467 record_alignment (now_seg, 2);
1469 if (mapstate == state)
1470 /* The mapping symbol has already been emitted.
1471 There is nothing else to do. */
1474 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1475 if (TRANSITION (MAP_UNDEFINED, MAP_DATA) && !subseg_text_p (now_seg))
1476 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1477 evaluated later in the next else. */
1479 else if (TRANSITION (MAP_UNDEFINED, MAP_INSN))
1481 /* Only add the symbol if the offset is > 0:
1482 if we're at the first frag, check it's size > 0;
1483 if we're not at the first frag, then for sure
1484 the offset is > 0. */
1485 struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root;
1486 const int add_symbol = (frag_now != frag_first)
1487 || (frag_now_fix () > 0);
1490 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
1494 mapping_state_2 (state, 0);
1497 /* Same as mapping_state, but MAX_CHARS bytes have already been
1498 allocated. Put the mapping symbol that far back. */
1501 mapping_state_2 (enum mstate state, int max_chars)
1503 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1505 if (!SEG_NORMAL (now_seg))
1508 if (mapstate == state)
1509 /* The mapping symbol has already been emitted.
1510 There is nothing else to do. */
1513 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1514 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
1517 #define mapping_state(x) /* nothing */
1518 #define mapping_state_2(x, y) /* nothing */
1521 /* Directives: sectioning and alignment. */
1524 s_bss (int ignore ATTRIBUTE_UNUSED)
1526 /* We don't support putting frags in the BSS segment, we fake it by
1527 marking in_bss, then looking at s_skip for clues. */
1528 subseg_set (bss_section, 0);
1529 demand_empty_rest_of_line ();
1530 mapping_state (MAP_DATA);
1534 s_even (int ignore ATTRIBUTE_UNUSED)
1536 /* Never make frag if expect extra pass. */
1538 frag_align (1, 0, 0);
1540 record_alignment (now_seg, 1);
1542 demand_empty_rest_of_line ();
1545 /* Directives: Literal pools. */
1547 static literal_pool *
1548 find_literal_pool (int size)
1552 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1554 if (pool->section == now_seg
1555 && pool->sub_section == now_subseg && pool->size == size)
1562 static literal_pool *
1563 find_or_make_literal_pool (int size)
1565 /* Next literal pool ID number. */
1566 static unsigned int latest_pool_num = 1;
1569 pool = find_literal_pool (size);
1573 /* Create a new pool. */
1574 pool = xmalloc (sizeof (*pool));
1578 /* Currently we always put the literal pool in the current text
1579 section. If we were generating "small" model code where we
1580 knew that all code and initialised data was within 1MB then
1581 we could output literals to mergeable, read-only data
1584 pool->next_free_entry = 0;
1585 pool->section = now_seg;
1586 pool->sub_section = now_subseg;
1588 pool->next = list_of_pools;
1589 pool->symbol = NULL;
1591 /* Add it to the list. */
1592 list_of_pools = pool;
1595 /* New pools, and emptied pools, will have a NULL symbol. */
1596 if (pool->symbol == NULL)
1598 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1599 (valueT) 0, &zero_address_frag);
1600 pool->id = latest_pool_num++;
1607 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1608 Return TRUE on success, otherwise return FALSE. */
1610 add_to_lit_pool (expressionS *exp, int size)
1615 pool = find_or_make_literal_pool (size);
1617 /* Check if this literal value is already in the pool. */
1618 for (entry = 0; entry < pool->next_free_entry; entry++)
1620 expressionS * litexp = & pool->literals[entry].exp;
1622 if ((litexp->X_op == exp->X_op)
1623 && (exp->X_op == O_constant)
1624 && (litexp->X_add_number == exp->X_add_number)
1625 && (litexp->X_unsigned == exp->X_unsigned))
1628 if ((litexp->X_op == exp->X_op)
1629 && (exp->X_op == O_symbol)
1630 && (litexp->X_add_number == exp->X_add_number)
1631 && (litexp->X_add_symbol == exp->X_add_symbol)
1632 && (litexp->X_op_symbol == exp->X_op_symbol))
1636 /* Do we need to create a new entry? */
1637 if (entry == pool->next_free_entry)
1639 if (entry >= MAX_LITERAL_POOL_SIZE)
1641 set_syntax_error (_("literal pool overflow"));
1645 pool->literals[entry].exp = *exp;
1646 pool->next_free_entry += 1;
1647 if (exp->X_op == O_big)
1649 /* PR 16688: Bignums are held in a single global array. We must
1650 copy and preserve that value now, before it is overwritten. */
1651 pool->literals[entry].bignum = xmalloc (CHARS_PER_LITTLENUM * exp->X_add_number);
1652 memcpy (pool->literals[entry].bignum, generic_bignum,
1653 CHARS_PER_LITTLENUM * exp->X_add_number);
1656 pool->literals[entry].bignum = NULL;
1659 exp->X_op = O_symbol;
1660 exp->X_add_number = ((int) entry) * size;
1661 exp->X_add_symbol = pool->symbol;
1666 /* Can't use symbol_new here, so have to create a symbol and then at
1667 a later date assign it a value. Thats what these functions do. */
1670 symbol_locate (symbolS * symbolP,
1671 const char *name,/* It is copied, the caller can modify. */
1672 segT segment, /* Segment identifier (SEG_<something>). */
1673 valueT valu, /* Symbol value. */
1674 fragS * frag) /* Associated fragment. */
1677 char *preserved_copy_of_name;
1679 name_length = strlen (name) + 1; /* +1 for \0. */
1680 obstack_grow (¬es, name, name_length);
1681 preserved_copy_of_name = obstack_finish (¬es);
1683 #ifdef tc_canonicalize_symbol_name
1684 preserved_copy_of_name =
1685 tc_canonicalize_symbol_name (preserved_copy_of_name);
1688 S_SET_NAME (symbolP, preserved_copy_of_name);
1690 S_SET_SEGMENT (symbolP, segment);
1691 S_SET_VALUE (symbolP, valu);
1692 symbol_clear_list_pointers (symbolP);
1694 symbol_set_frag (symbolP, frag);
1696 /* Link to end of symbol chain. */
1698 extern int symbol_table_frozen;
1700 if (symbol_table_frozen)
1704 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1706 obj_symbol_new_hook (symbolP);
1708 #ifdef tc_symbol_new_hook
1709 tc_symbol_new_hook (symbolP);
1713 verify_symbol_chain (symbol_rootP, symbol_lastP);
1714 #endif /* DEBUG_SYMS */
1719 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1726 for (align = 2; align <= 4; align++)
1728 int size = 1 << align;
1730 pool = find_literal_pool (size);
1731 if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
1734 mapping_state (MAP_DATA);
1736 /* Align pool as you have word accesses.
1737 Only make a frag if we have to. */
1739 frag_align (align, 0, 0);
1741 record_alignment (now_seg, align);
1743 sprintf (sym_name, "$$lit_\002%x", pool->id);
1745 symbol_locate (pool->symbol, sym_name, now_seg,
1746 (valueT) frag_now_fix (), frag_now);
1747 symbol_table_insert (pool->symbol);
1749 for (entry = 0; entry < pool->next_free_entry; entry++)
1751 expressionS * exp = & pool->literals[entry].exp;
1753 if (exp->X_op == O_big)
1755 /* PR 16688: Restore the global bignum value. */
1756 gas_assert (pool->literals[entry].bignum != NULL);
1757 memcpy (generic_bignum, pool->literals[entry].bignum,
1758 CHARS_PER_LITTLENUM * exp->X_add_number);
1761 /* First output the expression in the instruction to the pool. */
1762 emit_expr (exp, size); /* .word|.xword */
1764 if (exp->X_op == O_big)
1766 free (pool->literals[entry].bignum);
1767 pool->literals[entry].bignum = NULL;
1771 /* Mark the pool as empty. */
1772 pool->next_free_entry = 0;
1773 pool->symbol = NULL;
1778 /* Forward declarations for functions below, in the MD interface
1780 static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int);
1781 static struct reloc_table_entry * find_reloc_table_entry (char **);
1783 /* Directives: Data. */
1784 /* N.B. the support for relocation suffix in this directive needs to be
1785 implemented properly. */
1788 s_aarch64_elf_cons (int nbytes)
1792 #ifdef md_flush_pending_output
1793 md_flush_pending_output ();
1796 if (is_it_end_of_statement ())
1798 demand_empty_rest_of_line ();
1802 #ifdef md_cons_align
1803 md_cons_align (nbytes);
1806 mapping_state (MAP_DATA);
1809 struct reloc_table_entry *reloc;
1813 if (exp.X_op != O_symbol)
1814 emit_expr (&exp, (unsigned int) nbytes);
1817 skip_past_char (&input_line_pointer, '#');
1818 if (skip_past_char (&input_line_pointer, ':'))
1820 reloc = find_reloc_table_entry (&input_line_pointer);
1822 as_bad (_("unrecognized relocation suffix"));
1824 as_bad (_("unimplemented relocation suffix"));
1825 ignore_rest_of_line ();
1829 emit_expr (&exp, (unsigned int) nbytes);
1832 while (*input_line_pointer++ == ',');
1834 /* Put terminator back into stream. */
1835 input_line_pointer--;
1836 demand_empty_rest_of_line ();
1839 #endif /* OBJ_ELF */
1841 /* Output a 32-bit word, but mark as an instruction. */
1844 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
1848 #ifdef md_flush_pending_output
1849 md_flush_pending_output ();
1852 if (is_it_end_of_statement ())
1854 demand_empty_rest_of_line ();
1858 /* Sections are assumed to start aligned. In executable section, there is no
1859 MAP_DATA symbol pending. So we only align the address during
1860 MAP_DATA --> MAP_INSN transition.
1861 For other sections, this is not guaranteed. */
1862 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1863 if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA)
1864 frag_align_code (2, 0);
1867 mapping_state (MAP_INSN);
1873 if (exp.X_op != O_constant)
1875 as_bad (_("constant expression required"));
1876 ignore_rest_of_line ();
1880 if (target_big_endian)
1882 unsigned int val = exp.X_add_number;
1883 exp.X_add_number = SWAP_32 (val);
1885 emit_expr (&exp, 4);
1887 while (*input_line_pointer++ == ',');
1889 /* Put terminator back into stream. */
1890 input_line_pointer--;
1891 demand_empty_rest_of_line ();
1895 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1898 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED)
1904 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1905 BFD_RELOC_AARCH64_TLSDESC_ADD);
1907 demand_empty_rest_of_line ();
1910 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1913 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
1917 /* Since we're just labelling the code, there's no need to define a
1920 /* Make sure there is enough room in this frag for the following
1921 blr. This trick only works if the blr follows immediately after
1922 the .tlsdesc directive. */
1924 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1925 BFD_RELOC_AARCH64_TLSDESC_CALL);
1927 demand_empty_rest_of_line ();
1930 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1933 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED)
1939 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1940 BFD_RELOC_AARCH64_TLSDESC_LDR);
1942 demand_empty_rest_of_line ();
1944 #endif /* OBJ_ELF */
1946 static void s_aarch64_arch (int);
1947 static void s_aarch64_cpu (int);
1948 static void s_aarch64_arch_extension (int);
1950 /* This table describes all the machine specific pseudo-ops the assembler
1951 has to support. The fields are:
1952 pseudo-op name without dot
1953 function to call to execute this pseudo-op
1954 Integer arg to pass to the function. */
1956 const pseudo_typeS md_pseudo_table[] = {
1957 /* Never called because '.req' does not start a line. */
1959 {"unreq", s_unreq, 0},
1961 {"even", s_even, 0},
1962 {"ltorg", s_ltorg, 0},
1963 {"pool", s_ltorg, 0},
1964 {"cpu", s_aarch64_cpu, 0},
1965 {"arch", s_aarch64_arch, 0},
1966 {"arch_extension", s_aarch64_arch_extension, 0},
1967 {"inst", s_aarch64_inst, 0},
1969 {"tlsdescadd", s_tlsdescadd, 0},
1970 {"tlsdesccall", s_tlsdesccall, 0},
1971 {"tlsdescldr", s_tlsdescldr, 0},
1972 {"word", s_aarch64_elf_cons, 4},
1973 {"long", s_aarch64_elf_cons, 4},
1974 {"xword", s_aarch64_elf_cons, 8},
1975 {"dword", s_aarch64_elf_cons, 8},
1981 /* Check whether STR points to a register name followed by a comma or the
1982 end of line; REG_TYPE indicates which register types are checked
1983 against. Return TRUE if STR is such a register name; otherwise return
1984 FALSE. The function does not intend to produce any diagnostics, but since
1985 the register parser aarch64_reg_parse, which is called by this function,
1986 does produce diagnostics, we call clear_error to clear any diagnostics
1987 that may be generated by aarch64_reg_parse.
1988 Also, the function returns FALSE directly if there is any user error
1989 present at the function entry. This prevents the existing diagnostics
1990 state from being spoiled.
1991 The function currently serves parse_constant_immediate and
1992 parse_big_immediate only. */
1994 reg_name_p (char *str, aarch64_reg_type reg_type)
1998 /* Prevent the diagnostics state from being spoiled. */
2002 reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
2004 /* Clear the parsing error that may be set by the reg parser. */
2007 if (reg == PARSE_FAIL)
2010 skip_whitespace (str);
2011 if (*str == ',' || is_end_of_line[(unsigned int) *str])
2017 /* Parser functions used exclusively in instruction operands. */
2019 /* Parse an immediate expression which may not be constant.
2021 To prevent the expression parser from pushing a register name
2022 into the symbol table as an undefined symbol, firstly a check is
2023 done to find out whether STR is a valid register name followed
2024 by a comma or the end of line. Return FALSE if STR is such a
2028 parse_immediate_expression (char **str, expressionS *exp)
2030 if (reg_name_p (*str, REG_TYPE_R_Z_BHSDQ_V))
2032 set_recoverable_error (_("immediate operand required"));
2036 my_get_expression (exp, str, GE_OPT_PREFIX, 1);
2038 if (exp->X_op == O_absent)
2040 set_fatal_syntax_error (_("missing immediate expression"));
2047 /* Constant immediate-value read function for use in insn parsing.
2048 STR points to the beginning of the immediate (with the optional
2049 leading #); *VAL receives the value.
2051 Return TRUE on success; otherwise return FALSE. */
2054 parse_constant_immediate (char **str, int64_t * val)
2058 if (! parse_immediate_expression (str, &exp))
2061 if (exp.X_op != O_constant)
2063 set_syntax_error (_("constant expression required"));
2067 *val = exp.X_add_number;
2072 encode_imm_float_bits (uint32_t imm)
2074 return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2075 | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2078 /* Return TRUE if the single-precision floating-point value encoded in IMM
2079 can be expressed in the AArch64 8-bit signed floating-point format with
2080 3-bit exponent and normalized 4 bits of precision; in other words, the
2081 floating-point value must be expressable as
2082 (+/-) n / 16 * power (2, r)
2083 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2086 aarch64_imm_float_p (uint32_t imm)
2088 /* If a single-precision floating-point value has the following bit
2089 pattern, it can be expressed in the AArch64 8-bit floating-point
2092 3 32222222 2221111111111
2093 1 09876543 21098765432109876543210
2094 n Eeeeeexx xxxx0000000000000000000
2096 where n, e and each x are either 0 or 1 independently, with
2101 /* Prepare the pattern for 'Eeeeee'. */
2102 if (((imm >> 30) & 0x1) == 0)
2103 pattern = 0x3e000000;
2105 pattern = 0x40000000;
2107 return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */
2108 && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */
2111 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2113 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2114 8-bit signed floating-point format with 3-bit exponent and normalized 4
2115 bits of precision (i.e. can be used in an FMOV instruction); return the
2116 equivalent single-precision encoding in *FPWORD.
2118 Otherwise return FALSE. */
2121 aarch64_double_precision_fmovable (uint64_t imm, uint32_t *fpword)
2123 /* If a double-precision floating-point value has the following bit
2124 pattern, it can be expressed in the AArch64 8-bit floating-point
2127 6 66655555555 554444444...21111111111
2128 3 21098765432 109876543...098765432109876543210
2129 n Eeeeeeeeexx xxxx00000...000000000000000000000
2131 where n, e and each x are either 0 or 1 independently, with
2135 uint32_t high32 = imm >> 32;
2137 /* Lower 32 bits need to be 0s. */
2138 if ((imm & 0xffffffff) != 0)
2141 /* Prepare the pattern for 'Eeeeeeeee'. */
2142 if (((high32 >> 30) & 0x1) == 0)
2143 pattern = 0x3fc00000;
2145 pattern = 0x40000000;
2147 if ((high32 & 0xffff) == 0 /* bits 32 - 47 are 0. */
2148 && (high32 & 0x7fc00000) == pattern) /* bits 54 - 61 == ~ bit 62. */
2150 /* Convert to the single-precision encoding.
2152 n Eeeeeeeeexx xxxx00000...000000000000000000000
2154 n Eeeeeexx xxxx0000000000000000000. */
2155 *fpword = ((high32 & 0xfe000000) /* nEeeeee. */
2156 | (((high32 >> 16) & 0x3f) << 19)); /* xxxxxx. */
2163 /* Parse a floating-point immediate. Return TRUE on success and return the
2164 value in *IMMED in the format of IEEE754 single-precision encoding.
2165 *CCP points to the start of the string; DP_P is TRUE when the immediate
2166 is expected to be in double-precision (N.B. this only matters when
2167 hexadecimal representation is involved).
2169 N.B. 0.0 is accepted by this function. */
2172 parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p)
2176 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2177 int found_fpchar = 0;
2179 unsigned fpword = 0;
2180 bfd_boolean hex_p = FALSE;
2182 skip_past_char (&str, '#');
2185 skip_whitespace (fpnum);
2187 if (strncmp (fpnum, "0x", 2) == 0)
2189 /* Support the hexadecimal representation of the IEEE754 encoding.
2190 Double-precision is expected when DP_P is TRUE, otherwise the
2191 representation should be in single-precision. */
2192 if (! parse_constant_immediate (&str, &val))
2197 if (! aarch64_double_precision_fmovable (val, &fpword))
2200 else if ((uint64_t) val > 0xffffffff)
2209 /* We must not accidentally parse an integer as a floating-point number.
2210 Make sure that the value we parse is not an integer by checking for
2211 special characters '.' or 'e'. */
2212 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
2213 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
2227 if ((str = atof_ieee (str, 's', words)) == NULL)
2230 /* Our FP word must be 32 bits (single-precision FP). */
2231 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
2233 fpword <<= LITTLENUM_NUMBER_OF_BITS;
2238 if (aarch64_imm_float_p (fpword) || (fpword & 0x7fffffff) == 0)
2246 set_fatal_syntax_error (_("invalid floating-point constant"));
2250 /* Less-generic immediate-value read function with the possibility of loading
2251 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2254 To prevent the expression parser from pushing a register name into the
2255 symbol table as an undefined symbol, a check is firstly done to find
2256 out whether STR is a valid register name followed by a comma or the end
2257 of line. Return FALSE if STR is such a register. */
2260 parse_big_immediate (char **str, int64_t *imm)
2264 if (reg_name_p (ptr, REG_TYPE_R_Z_BHSDQ_V))
2266 set_syntax_error (_("immediate operand required"));
2270 my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
2272 if (inst.reloc.exp.X_op == O_constant)
2273 *imm = inst.reloc.exp.X_add_number;
2280 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2281 if NEED_LIBOPCODES is non-zero, the fixup will need
2282 assistance from the libopcodes. */
2285 aarch64_set_gas_internal_fixup (struct reloc *reloc,
2286 const aarch64_opnd_info *operand,
2287 int need_libopcodes_p)
2289 reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2290 reloc->opnd = operand->type;
2291 if (need_libopcodes_p)
2292 reloc->need_libopcodes_p = 1;
2295 /* Return TRUE if the instruction needs to be fixed up later internally by
2296 the GAS; otherwise return FALSE. */
2298 static inline bfd_boolean
2299 aarch64_gas_internal_fixup_p (void)
2301 return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2304 /* Assign the immediate value to the relavant field in *OPERAND if
2305 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2306 needs an internal fixup in a later stage.
2307 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2308 IMM.VALUE that may get assigned with the constant. */
2310 assign_imm_if_const_or_fixup_later (struct reloc *reloc,
2311 aarch64_opnd_info *operand,
2313 int need_libopcodes_p,
2316 if (reloc->exp.X_op == O_constant)
2319 operand->addr.offset.imm = reloc->exp.X_add_number;
2321 operand->imm.value = reloc->exp.X_add_number;
2322 reloc->type = BFD_RELOC_UNUSED;
2326 aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p);
2327 /* Tell libopcodes to ignore this operand or not. This is helpful
2328 when one of the operands needs to be fixed up later but we need
2329 libopcodes to check the other operands. */
2330 operand->skip = skip_p;
2334 /* Relocation modifiers. Each entry in the table contains the textual
2335 name for the relocation which may be placed before a symbol used as
2336 a load/store offset, or add immediate. It must be surrounded by a
2337 leading and trailing colon, for example:
2339 ldr x0, [x1, #:rello:varsym]
2340 add x0, x1, #:rello:varsym */
2342 struct reloc_table_entry
2346 bfd_reloc_code_real_type adr_type;
2347 bfd_reloc_code_real_type adrp_type;
2348 bfd_reloc_code_real_type movw_type;
2349 bfd_reloc_code_real_type add_type;
2350 bfd_reloc_code_real_type ldst_type;
2351 bfd_reloc_code_real_type ld_literal_type;
2354 static struct reloc_table_entry reloc_table[] = {
2355 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2360 BFD_RELOC_AARCH64_ADD_LO12,
2361 BFD_RELOC_AARCH64_LDST_LO12,
2364 /* Higher 21 bits of pc-relative page offset: ADRP */
2367 BFD_RELOC_AARCH64_ADR_HI21_PCREL,
2373 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2376 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
2382 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2386 BFD_RELOC_AARCH64_MOVW_G0,
2391 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2395 BFD_RELOC_AARCH64_MOVW_G0_S,
2400 /* Less significant bits 0-15 of address/value: MOVK, no check */
2404 BFD_RELOC_AARCH64_MOVW_G0_NC,
2409 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2413 BFD_RELOC_AARCH64_MOVW_G1,
2418 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2422 BFD_RELOC_AARCH64_MOVW_G1_S,
2427 /* Less significant bits 16-31 of address/value: MOVK, no check */
2431 BFD_RELOC_AARCH64_MOVW_G1_NC,
2436 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2440 BFD_RELOC_AARCH64_MOVW_G2,
2445 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2449 BFD_RELOC_AARCH64_MOVW_G2_S,
2454 /* Less significant bits 32-47 of address/value: MOVK, no check */
2458 BFD_RELOC_AARCH64_MOVW_G2_NC,
2463 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2467 BFD_RELOC_AARCH64_MOVW_G3,
2472 /* Get to the page containing GOT entry for a symbol. */
2475 BFD_RELOC_AARCH64_ADR_GOT_PAGE,
2479 BFD_RELOC_AARCH64_GOT_LD_PREL19},
2481 /* 12 bit offset into the page containing GOT entry for that symbol. */
2487 BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
2490 /* 0-15 bits of address/value: MOVk, no check. */
2494 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC,
2499 /* Most significant bits 16-31 of address/value: MOVZ. */
2503 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1,
2508 /* 15 bit offset into the page containing GOT entry for that symbol. */
2514 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15,
2517 /* Get to the page containing GOT TLS entry for a symbol */
2518 {"gottprel_g0_nc", 0,
2521 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
2526 /* Get to the page containing GOT TLS entry for a symbol */
2530 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
2535 /* Get to the page containing GOT TLS entry for a symbol */
2537 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21, /* adr_type */
2538 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
2544 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2549 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
2553 /* Lower 16 bits address/value: MOVk. */
2557 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC,
2562 /* Most significant bits 16-31 of address/value: MOVZ. */
2566 BFD_RELOC_AARCH64_TLSGD_MOVW_G1,
2571 /* Get to the page containing GOT TLS entry for a symbol */
2573 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21, /* adr_type */
2574 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21,
2578 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19},
2580 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2585 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
2586 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
2589 /* Get to the page containing GOT TLS entry for a symbol.
2590 The same as GD, we allocate two consecutive GOT slots
2591 for module index and module offset, the only difference
2592 with GD is the module offset should be intialized to
2593 zero without any outstanding runtime relocation. */
2595 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21, /* adr_type */
2596 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21,
2602 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2603 {"tlsldm_lo12_nc", 0,
2607 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC,
2611 /* 12 bit offset into the module TLS base address. */
2616 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12,
2617 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12,
2620 /* Same as dtprel_lo12, no overflow check. */
2621 {"dtprel_lo12_nc", 0,
2625 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC,
2626 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC,
2629 /* bits[23:12] of offset to the module TLS base address. */
2634 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12,
2638 /* bits[15:0] of offset to the module TLS base address. */
2642 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0,
2647 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2651 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC,
2656 /* bits[31:16] of offset to the module TLS base address. */
2660 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1,
2665 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2669 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC,
2674 /* bits[47:32] of offset to the module TLS base address. */
2678 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2,
2683 /* Lower 16 bit offset into GOT entry for a symbol */
2684 {"tlsdesc_off_g0_nc", 0,
2687 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
2692 /* Higher 16 bit offset into GOT entry for a symbol */
2693 {"tlsdesc_off_g1", 0,
2696 BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
2701 /* Get to the page containing GOT TLS entry for a symbol */
2704 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
2708 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19},
2710 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2711 {"gottprel_lo12", 0,
2716 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC,
2719 /* Get tp offset for a symbol. */
2724 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2728 /* Get tp offset for a symbol. */
2733 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2737 /* Get tp offset for a symbol. */
2742 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
2746 /* Get tp offset for a symbol. */
2747 {"tprel_lo12_nc", 0,
2751 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
2755 /* Most significant bits 32-47 of address/value: MOVZ. */
2759 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
2764 /* Most significant bits 16-31 of address/value: MOVZ. */
2768 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
2773 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2777 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
2782 /* Most significant bits 0-15 of address/value: MOVZ. */
2786 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
2791 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2795 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
2800 /* 15bit offset from got entry to base address of GOT table. */
2806 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15,
2809 /* 14bit offset from got entry to base address of GOT table. */
2815 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14,
2819 /* Given the address of a pointer pointing to the textual name of a
2820 relocation as may appear in assembler source, attempt to find its
2821 details in reloc_table. The pointer will be updated to the character
2822 after the trailing colon. On failure, NULL will be returned;
2823 otherwise return the reloc_table_entry. */
2825 static struct reloc_table_entry *
2826 find_reloc_table_entry (char **str)
2829 for (i = 0; i < ARRAY_SIZE (reloc_table); i++)
2831 int length = strlen (reloc_table[i].name);
2833 if (strncasecmp (reloc_table[i].name, *str, length) == 0
2834 && (*str)[length] == ':')
2836 *str += (length + 1);
2837 return &reloc_table[i];
2844 /* Mode argument to parse_shift and parser_shifter_operand. */
2845 enum parse_shift_mode
2847 SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2849 SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2851 SHIFTED_LSL, /* bare "lsl #n" */
2852 SHIFTED_LSL_MSL, /* "lsl|msl #n" */
2853 SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */
2856 /* Parse a <shift> operator on an AArch64 data processing instruction.
2857 Return TRUE on success; otherwise return FALSE. */
2859 parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
2861 const struct aarch64_name_value_pair *shift_op;
2862 enum aarch64_modifier_kind kind;
2868 for (p = *str; ISALPHA (*p); p++)
2873 set_syntax_error (_("shift expression expected"));
2877 shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str);
2879 if (shift_op == NULL)
2881 set_syntax_error (_("shift operator expected"));
2885 kind = aarch64_get_operand_modifier (shift_op);
2887 if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
2889 set_syntax_error (_("invalid use of 'MSL'"));
2895 case SHIFTED_LOGIC_IMM:
2896 if (aarch64_extend_operator_p (kind) == TRUE)
2898 set_syntax_error (_("extending shift is not permitted"));
2903 case SHIFTED_ARITH_IMM:
2904 if (kind == AARCH64_MOD_ROR)
2906 set_syntax_error (_("'ROR' shift is not permitted"));
2912 if (kind != AARCH64_MOD_LSL)
2914 set_syntax_error (_("only 'LSL' shift is permitted"));
2919 case SHIFTED_REG_OFFSET:
2920 if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
2921 && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX)
2923 set_fatal_syntax_error
2924 (_("invalid shift for the register offset addressing mode"));
2929 case SHIFTED_LSL_MSL:
2930 if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
2932 set_syntax_error (_("invalid shift operator"));
2941 /* Whitespace can appear here if the next thing is a bare digit. */
2942 skip_whitespace (p);
2944 /* Parse shift amount. */
2946 if (mode == SHIFTED_REG_OFFSET && *p == ']')
2947 exp.X_op = O_absent;
2950 if (is_immediate_prefix (*p))
2955 my_get_expression (&exp, &p, GE_NO_PREFIX, 0);
2957 if (exp.X_op == O_absent)
2959 if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
2961 set_syntax_error (_("missing shift amount"));
2964 operand->shifter.amount = 0;
2966 else if (exp.X_op != O_constant)
2968 set_syntax_error (_("constant shift amount required"));
2971 else if (exp.X_add_number < 0 || exp.X_add_number > 63)
2973 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2978 operand->shifter.amount = exp.X_add_number;
2979 operand->shifter.amount_present = 1;
2982 operand->shifter.operator_present = 1;
2983 operand->shifter.kind = kind;
2989 /* Parse a <shifter_operand> for a data processing instruction:
2992 #<immediate>, LSL #imm
2994 Validation of immediate operands is deferred to md_apply_fix.
2996 Return TRUE on success; otherwise return FALSE. */
2999 parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
3000 enum parse_shift_mode mode)
3004 if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
3009 /* Accept an immediate expression. */
3010 if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
3013 /* Accept optional LSL for arithmetic immediate values. */
3014 if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
3015 if (! parse_shift (&p, operand, SHIFTED_LSL))
3018 /* Not accept any shifter for logical immediate values. */
3019 if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
3020 && parse_shift (&p, operand, mode))
3022 set_syntax_error (_("unexpected shift operator"));
3030 /* Parse a <shifter_operand> for a data processing instruction:
3035 #<immediate>, LSL #imm
3037 where <shift> is handled by parse_shift above, and the last two
3038 cases are handled by the function above.
3040 Validation of immediate operands is deferred to md_apply_fix.
3042 Return TRUE on success; otherwise return FALSE. */
3045 parse_shifter_operand (char **str, aarch64_opnd_info *operand,
3046 enum parse_shift_mode mode)
3049 int isreg32, isregzero;
3050 enum aarch64_operand_class opd_class
3051 = aarch64_get_operand_class (operand->type);
3054 aarch64_reg_parse_32_64 (str, 0, 0, &isreg32, &isregzero)) != PARSE_FAIL)
3056 if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
3058 set_syntax_error (_("unexpected register in the immediate operand"));
3062 if (!isregzero && reg == REG_SP)
3064 set_syntax_error (BAD_SP);
3068 operand->reg.regno = reg;
3069 operand->qualifier = isreg32 ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
3071 /* Accept optional shift operation on register. */
3072 if (! skip_past_comma (str))
3075 if (! parse_shift (str, operand, mode))
3080 else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
3083 (_("integer register expected in the extended/shifted operand "
3088 /* We have a shifted immediate variable. */
3089 return parse_shifter_operand_imm (str, operand, mode);
3092 /* Return TRUE on success; return FALSE otherwise. */
3095 parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
3096 enum parse_shift_mode mode)
3100 /* Determine if we have the sequence of characters #: or just :
3101 coming next. If we do, then we check for a :rello: relocation
3102 modifier. If we don't, punt the whole lot to
3103 parse_shifter_operand. */
3105 if ((p[0] == '#' && p[1] == ':') || p[0] == ':')
3107 struct reloc_table_entry *entry;
3115 /* Try to parse a relocation. Anything else is an error. */
3116 if (!(entry = find_reloc_table_entry (str)))
3118 set_syntax_error (_("unknown relocation modifier"));
3122 if (entry->add_type == 0)
3125 (_("this relocation modifier is not allowed on this instruction"));
3129 /* Save str before we decompose it. */
3132 /* Next, we parse the expression. */
3133 if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
3136 /* Record the relocation type (use the ADD variant here). */
3137 inst.reloc.type = entry->add_type;
3138 inst.reloc.pc_rel = entry->pc_rel;
3140 /* If str is empty, we've reached the end, stop here. */
3144 /* Otherwise, we have a shifted reloc modifier, so rewind to
3145 recover the variable name and continue parsing for the shifter. */
3147 return parse_shifter_operand_imm (str, operand, mode);
3150 return parse_shifter_operand (str, operand, mode);
3153 /* Parse all forms of an address expression. Information is written
3154 to *OPERAND and/or inst.reloc.
3156 The A64 instruction set has the following addressing modes:
3159 [base] // in SIMD ld/st structure
3160 [base{,#0}] // in ld/st exclusive
3162 [base,Xm{,LSL #imm}]
3163 [base,Xm,SXTX {#imm}]
3164 [base,Wm,(S|U)XTW {#imm}]
3169 [base],Xm // in SIMD ld/st structure
3170 PC-relative (literal)
3174 (As a convenience, the notation "=immediate" is permitted in conjunction
3175 with the pc-relative literal load instructions to automatically place an
3176 immediate value or symbolic address in a nearby literal pool and generate
3177 a hidden label which references it.)
3179 Upon a successful parsing, the address structure in *OPERAND will be
3180 filled in the following way:
3182 .base_regno = <base>
3183 .offset.is_reg // 1 if the offset is a register
3185 .offset.regno = <Rm>
3187 For different addressing modes defined in the A64 ISA:
3190 .pcrel=0; .preind=1; .postind=0; .writeback=0
3192 .pcrel=0; .preind=1; .postind=0; .writeback=1
3194 .pcrel=0; .preind=0; .postind=1; .writeback=1
3195 PC-relative (literal)
3196 .pcrel=1; .preind=1; .postind=0; .writeback=0
3198 The shift/extension information, if any, will be stored in .shifter.
3200 It is the caller's responsibility to check for addressing modes not
3201 supported by the instruction, and to set inst.reloc.type. */
3204 parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
3205 int accept_reg_post_index)
3209 int isreg32, isregzero;
3210 expressionS *exp = &inst.reloc.exp;
3212 if (! skip_past_char (&p, '['))
3214 /* =immediate or label. */
3215 operand->addr.pcrel = 1;
3216 operand->addr.preind = 1;
3218 /* #:<reloc_op>:<symbol> */
3219 skip_past_char (&p, '#');
3220 if (reloc && skip_past_char (&p, ':'))
3222 bfd_reloc_code_real_type ty;
3223 struct reloc_table_entry *entry;
3225 /* Try to parse a relocation modifier. Anything else is
3227 entry = find_reloc_table_entry (&p);
3230 set_syntax_error (_("unknown relocation modifier"));
3234 switch (operand->type)
3236 case AARCH64_OPND_ADDR_PCREL21:
3238 ty = entry->adr_type;
3242 ty = entry->ld_literal_type;
3249 (_("this relocation modifier is not allowed on this "
3255 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3257 set_syntax_error (_("invalid relocation expression"));
3261 /* #:<reloc_op>:<expr> */
3262 /* Record the relocation type. */
3263 inst.reloc.type = ty;
3264 inst.reloc.pc_rel = entry->pc_rel;
3269 if (skip_past_char (&p, '='))
3270 /* =immediate; need to generate the literal in the literal pool. */
3271 inst.gen_lit_pool = 1;
3273 if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3275 set_syntax_error (_("invalid address"));
3286 /* Accept SP and reject ZR */
3287 reg = aarch64_reg_parse_32_64 (&p, 0, 1, &isreg32, &isregzero);
3288 if (reg == PARSE_FAIL || isreg32)
3290 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
3293 operand->addr.base_regno = reg;
3296 if (skip_past_comma (&p))
3299 operand->addr.preind = 1;
3301 /* Reject SP and accept ZR */
3302 reg = aarch64_reg_parse_32_64 (&p, 1, 0, &isreg32, &isregzero);
3303 if (reg != PARSE_FAIL)
3306 operand->addr.offset.regno = reg;
3307 operand->addr.offset.is_reg = 1;
3308 /* Shifted index. */
3309 if (skip_past_comma (&p))
3312 if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
3313 /* Use the diagnostics set in parse_shift, so not set new
3314 error message here. */
3318 [base,Xm{,LSL #imm}]
3319 [base,Xm,SXTX {#imm}]
3320 [base,Wm,(S|U)XTW {#imm}] */
3321 if (operand->shifter.kind == AARCH64_MOD_NONE
3322 || operand->shifter.kind == AARCH64_MOD_LSL
3323 || operand->shifter.kind == AARCH64_MOD_SXTX)
3327 set_syntax_error (_("invalid use of 32-bit register offset"));
3333 set_syntax_error (_("invalid use of 64-bit register offset"));
3339 /* [Xn,#:<reloc_op>:<symbol> */
3340 skip_past_char (&p, '#');
3341 if (reloc && skip_past_char (&p, ':'))
3343 struct reloc_table_entry *entry;
3345 /* Try to parse a relocation modifier. Anything else is
3347 if (!(entry = find_reloc_table_entry (&p)))
3349 set_syntax_error (_("unknown relocation modifier"));
3353 if (entry->ldst_type == 0)
3356 (_("this relocation modifier is not allowed on this "
3361 /* [Xn,#:<reloc_op>: */
3362 /* We now have the group relocation table entry corresponding to
3363 the name in the assembler source. Next, we parse the
3365 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3367 set_syntax_error (_("invalid relocation expression"));
3371 /* [Xn,#:<reloc_op>:<expr> */
3372 /* Record the load/store relocation type. */
3373 inst.reloc.type = entry->ldst_type;
3374 inst.reloc.pc_rel = entry->pc_rel;
3376 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3378 set_syntax_error (_("invalid expression in the address"));
3385 if (! skip_past_char (&p, ']'))
3387 set_syntax_error (_("']' expected"));
3391 if (skip_past_char (&p, '!'))
3393 if (operand->addr.preind && operand->addr.offset.is_reg)
3395 set_syntax_error (_("register offset not allowed in pre-indexed "
3396 "addressing mode"));
3400 operand->addr.writeback = 1;
3402 else if (skip_past_comma (&p))
3405 operand->addr.postind = 1;
3406 operand->addr.writeback = 1;
3408 if (operand->addr.preind)
3410 set_syntax_error (_("cannot combine pre- and post-indexing"));
3414 if (accept_reg_post_index
3415 && (reg = aarch64_reg_parse_32_64 (&p, 1, 1, &isreg32,
3416 &isregzero)) != PARSE_FAIL)
3421 set_syntax_error (_("invalid 32-bit register offset"));
3424 operand->addr.offset.regno = reg;
3425 operand->addr.offset.is_reg = 1;
3427 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3430 set_syntax_error (_("invalid expression in the address"));
3435 /* If at this point neither .preind nor .postind is set, we have a
3436 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3437 if (operand->addr.preind == 0 && operand->addr.postind == 0)
3439 if (operand->addr.writeback)
3442 set_syntax_error (_("missing offset in the pre-indexed address"));
3445 operand->addr.preind = 1;
3446 inst.reloc.exp.X_op = O_constant;
3447 inst.reloc.exp.X_add_number = 0;
3454 /* Return TRUE on success; otherwise return FALSE. */
3456 parse_address (char **str, aarch64_opnd_info *operand,
3457 int accept_reg_post_index)
3459 return parse_address_main (str, operand, 0, accept_reg_post_index);
3462 /* Return TRUE on success; otherwise return FALSE. */
3464 parse_address_reloc (char **str, aarch64_opnd_info *operand)
3466 return parse_address_main (str, operand, 1, 0);
3469 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3470 Return TRUE on success; otherwise return FALSE. */
3472 parse_half (char **str, int *internal_fixup_p)
3478 skip_past_char (&p, '#');
3480 gas_assert (internal_fixup_p);
3481 *internal_fixup_p = 0;
3485 struct reloc_table_entry *entry;
3487 /* Try to parse a relocation. Anything else is an error. */
3489 if (!(entry = find_reloc_table_entry (&p)))
3491 set_syntax_error (_("unknown relocation modifier"));
3495 if (entry->movw_type == 0)
3498 (_("this relocation modifier is not allowed on this instruction"));
3502 inst.reloc.type = entry->movw_type;
3505 *internal_fixup_p = 1;
3507 /* Avoid parsing a register as a general symbol. */
3509 if (aarch64_reg_parse_32_64 (&p, 0, 0, &dummy, &dummy) != PARSE_FAIL)
3513 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3520 /* Parse an operand for an ADRP instruction:
3522 Return TRUE on success; otherwise return FALSE. */
3525 parse_adrp (char **str)
3532 struct reloc_table_entry *entry;
3534 /* Try to parse a relocation. Anything else is an error. */
3536 if (!(entry = find_reloc_table_entry (&p)))
3538 set_syntax_error (_("unknown relocation modifier"));
3542 if (entry->adrp_type == 0)
3545 (_("this relocation modifier is not allowed on this instruction"));
3549 inst.reloc.type = entry->adrp_type;
3552 inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
3554 inst.reloc.pc_rel = 1;
3556 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3563 /* Miscellaneous. */
3565 /* Parse an option for a preload instruction. Returns the encoding for the
3566 option, or PARSE_FAIL. */
3569 parse_pldop (char **str)
3572 const struct aarch64_name_value_pair *o;
3575 while (ISALNUM (*q))
3578 o = hash_find_n (aarch64_pldop_hsh, p, q - p);
3586 /* Parse an option for a barrier instruction. Returns the encoding for the
3587 option, or PARSE_FAIL. */
3590 parse_barrier (char **str)
3593 const asm_barrier_opt *o;
3596 while (ISALPHA (*q))
3599 o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p);
3607 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3608 Returns the encoding for the option, or PARSE_FAIL.
3610 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3611 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3613 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3614 field, otherwise as a system register.
3618 parse_sys_reg (char **str, struct hash_control *sys_regs,
3619 int imple_defined_p, int pstatefield_p)
3623 const aarch64_sys_reg *o;
3627 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3629 *p++ = TOLOWER (*q);
3631 /* Assert that BUF be large enough. */
3632 gas_assert (p - buf == q - *str);
3634 o = hash_find (sys_regs, buf);
3637 if (!imple_defined_p)
3641 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3642 unsigned int op0, op1, cn, cm, op2;
3644 if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2)
3647 if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
3649 value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
3654 if (pstatefield_p && !aarch64_pstatefield_supported_p (cpu_variant, o))
3655 as_bad (_("selected processor does not support PSTATE field "
3657 if (!pstatefield_p && !aarch64_sys_reg_supported_p (cpu_variant, o))
3658 as_bad (_("selected processor does not support system register "
3660 if (aarch64_sys_reg_deprecated_p (o))
3661 as_warn (_("system register name '%s' is deprecated and may be "
3662 "removed in a future release"), buf);
3670 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3671 for the option, or NULL. */
3673 static const aarch64_sys_ins_reg *
3674 parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
3678 const aarch64_sys_ins_reg *o;
3681 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3683 *p++ = TOLOWER (*q);
3686 o = hash_find (sys_ins_regs, buf);
3694 #define po_char_or_fail(chr) do { \
3695 if (! skip_past_char (&str, chr)) \
3699 #define po_reg_or_fail(regtype) do { \
3700 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3701 if (val == PARSE_FAIL) \
3703 set_default_error (); \
3708 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3709 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3710 &isreg32, &isregzero); \
3711 if (val == PARSE_FAIL) \
3713 set_default_error (); \
3716 info->reg.regno = val; \
3718 info->qualifier = AARCH64_OPND_QLF_W; \
3720 info->qualifier = AARCH64_OPND_QLF_X; \
3723 #define po_imm_nc_or_fail() do { \
3724 if (! parse_constant_immediate (&str, &val)) \
3728 #define po_imm_or_fail(min, max) do { \
3729 if (! parse_constant_immediate (&str, &val)) \
3731 if (val < min || val > max) \
3733 set_fatal_syntax_error (_("immediate value out of range "\
3734 #min " to "#max)); \
3739 #define po_misc_or_fail(expr) do { \
3744 /* encode the 12-bit imm field of Add/sub immediate */
3745 static inline uint32_t
3746 encode_addsub_imm (uint32_t imm)
3751 /* encode the shift amount field of Add/sub immediate */
3752 static inline uint32_t
3753 encode_addsub_imm_shift_amount (uint32_t cnt)
3759 /* encode the imm field of Adr instruction */
3760 static inline uint32_t
3761 encode_adr_imm (uint32_t imm)
3763 return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */
3764 | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3767 /* encode the immediate field of Move wide immediate */
3768 static inline uint32_t
3769 encode_movw_imm (uint32_t imm)
3774 /* encode the 26-bit offset of unconditional branch */
3775 static inline uint32_t
3776 encode_branch_ofs_26 (uint32_t ofs)
3778 return ofs & ((1 << 26) - 1);
3781 /* encode the 19-bit offset of conditional branch and compare & branch */
3782 static inline uint32_t
3783 encode_cond_branch_ofs_19 (uint32_t ofs)
3785 return (ofs & ((1 << 19) - 1)) << 5;
3788 /* encode the 19-bit offset of ld literal */
3789 static inline uint32_t
3790 encode_ld_lit_ofs_19 (uint32_t ofs)
3792 return (ofs & ((1 << 19) - 1)) << 5;
3795 /* Encode the 14-bit offset of test & branch. */
3796 static inline uint32_t
3797 encode_tst_branch_ofs_14 (uint32_t ofs)
3799 return (ofs & ((1 << 14) - 1)) << 5;
3802 /* Encode the 16-bit imm field of svc/hvc/smc. */
3803 static inline uint32_t
3804 encode_svc_imm (uint32_t imm)
3809 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3810 static inline uint32_t
3811 reencode_addsub_switch_add_sub (uint32_t opcode)
3813 return opcode ^ (1 << 30);
3816 static inline uint32_t
3817 reencode_movzn_to_movz (uint32_t opcode)
3819 return opcode | (1 << 30);
3822 static inline uint32_t
3823 reencode_movzn_to_movn (uint32_t opcode)
3825 return opcode & ~(1 << 30);
3828 /* Overall per-instruction processing. */
3830 /* We need to be able to fix up arbitrary expressions in some statements.
3831 This is so that we can handle symbols that are an arbitrary distance from
3832 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3833 which returns part of an address in a form which will be valid for
3834 a data instruction. We do this by pushing the expression into a symbol
3835 in the expr_section, and creating a fix for that. */
3838 fix_new_aarch64 (fragS * frag,
3840 short int size, expressionS * exp, int pc_rel, int reloc)
3850 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
3854 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
3861 /* Diagnostics on operands errors. */
3863 /* By default, output verbose error message.
3864 Disable the verbose error message by -mno-verbose-error. */
3865 static int verbose_error_p = 1;
3867 #ifdef DEBUG_AARCH64
3868 /* N.B. this is only for the purpose of debugging. */
3869 const char* operand_mismatch_kind_names[] =
3872 "AARCH64_OPDE_RECOVERABLE",
3873 "AARCH64_OPDE_SYNTAX_ERROR",
3874 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3875 "AARCH64_OPDE_INVALID_VARIANT",
3876 "AARCH64_OPDE_OUT_OF_RANGE",
3877 "AARCH64_OPDE_UNALIGNED",
3878 "AARCH64_OPDE_REG_LIST",
3879 "AARCH64_OPDE_OTHER_ERROR",
3881 #endif /* DEBUG_AARCH64 */
3883 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3885 When multiple errors of different kinds are found in the same assembly
3886 line, only the error of the highest severity will be picked up for
3887 issuing the diagnostics. */
3889 static inline bfd_boolean
3890 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
3891 enum aarch64_operand_error_kind rhs)
3893 gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL);
3894 gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE);
3895 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
3896 gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
3897 gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
3898 gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
3899 gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
3900 gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
3904 /* Helper routine to get the mnemonic name from the assembly instruction
3905 line; should only be called for the diagnosis purpose, as there is
3906 string copy operation involved, which may affect the runtime
3907 performance if used in elsewhere. */
3910 get_mnemonic_name (const char *str)
3912 static char mnemonic[32];
3915 /* Get the first 15 bytes and assume that the full name is included. */
3916 strncpy (mnemonic, str, 31);
3917 mnemonic[31] = '\0';
3919 /* Scan up to the end of the mnemonic, which must end in white space,
3920 '.', or end of string. */
3921 for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr)
3926 /* Append '...' to the truncated long name. */
3927 if (ptr - mnemonic == 31)
3928 mnemonic[28] = mnemonic[29] = mnemonic[30] = '.';
3934 reset_aarch64_instruction (aarch64_instruction *instruction)
3936 memset (instruction, '\0', sizeof (aarch64_instruction));
3937 instruction->reloc.type = BFD_RELOC_UNUSED;
3940 /* Data strutures storing one user error in the assembly code related to
3943 struct operand_error_record
3945 const aarch64_opcode *opcode;
3946 aarch64_operand_error detail;
3947 struct operand_error_record *next;
3950 typedef struct operand_error_record operand_error_record;
3952 struct operand_errors
3954 operand_error_record *head;
3955 operand_error_record *tail;
3958 typedef struct operand_errors operand_errors;
3960 /* Top-level data structure reporting user errors for the current line of
3962 The way md_assemble works is that all opcodes sharing the same mnemonic
3963 name are iterated to find a match to the assembly line. In this data
3964 structure, each of the such opcodes will have one operand_error_record
3965 allocated and inserted. In other words, excessive errors related with
3966 a single opcode are disregarded. */
3967 operand_errors operand_error_report;
3969 /* Free record nodes. */
3970 static operand_error_record *free_opnd_error_record_nodes = NULL;
3972 /* Initialize the data structure that stores the operand mismatch
3973 information on assembling one line of the assembly code. */
3975 init_operand_error_report (void)
3977 if (operand_error_report.head != NULL)
3979 gas_assert (operand_error_report.tail != NULL);
3980 operand_error_report.tail->next = free_opnd_error_record_nodes;
3981 free_opnd_error_record_nodes = operand_error_report.head;
3982 operand_error_report.head = NULL;
3983 operand_error_report.tail = NULL;
3986 gas_assert (operand_error_report.tail == NULL);
3989 /* Return TRUE if some operand error has been recorded during the
3990 parsing of the current assembly line using the opcode *OPCODE;
3991 otherwise return FALSE. */
3992 static inline bfd_boolean
3993 opcode_has_operand_error_p (const aarch64_opcode *opcode)
3995 operand_error_record *record = operand_error_report.head;
3996 return record && record->opcode == opcode;
3999 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4000 OPCODE field is initialized with OPCODE.
4001 N.B. only one record for each opcode, i.e. the maximum of one error is
4002 recorded for each instruction template. */
4005 add_operand_error_record (const operand_error_record* new_record)
4007 const aarch64_opcode *opcode = new_record->opcode;
4008 operand_error_record* record = operand_error_report.head;
4010 /* The record may have been created for this opcode. If not, we need
4012 if (! opcode_has_operand_error_p (opcode))
4014 /* Get one empty record. */
4015 if (free_opnd_error_record_nodes == NULL)
4017 record = xmalloc (sizeof (operand_error_record));
4023 record = free_opnd_error_record_nodes;
4024 free_opnd_error_record_nodes = record->next;
4026 record->opcode = opcode;
4027 /* Insert at the head. */
4028 record->next = operand_error_report.head;
4029 operand_error_report.head = record;
4030 if (operand_error_report.tail == NULL)
4031 operand_error_report.tail = record;
4033 else if (record->detail.kind != AARCH64_OPDE_NIL
4034 && record->detail.index <= new_record->detail.index
4035 && operand_error_higher_severity_p (record->detail.kind,
4036 new_record->detail.kind))
4038 /* In the case of multiple errors found on operands related with a
4039 single opcode, only record the error of the leftmost operand and
4040 only if the error is of higher severity. */
4041 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4042 " the existing error %s on operand %d",
4043 operand_mismatch_kind_names[new_record->detail.kind],
4044 new_record->detail.index,
4045 operand_mismatch_kind_names[record->detail.kind],
4046 record->detail.index);
4050 record->detail = new_record->detail;
4054 record_operand_error_info (const aarch64_opcode *opcode,
4055 aarch64_operand_error *error_info)
4057 operand_error_record record;
4058 record.opcode = opcode;
4059 record.detail = *error_info;
4060 add_operand_error_record (&record);
4063 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4064 error message *ERROR, for operand IDX (count from 0). */
4067 record_operand_error (const aarch64_opcode *opcode, int idx,
4068 enum aarch64_operand_error_kind kind,
4071 aarch64_operand_error info;
4072 memset(&info, 0, sizeof (info));
4076 record_operand_error_info (opcode, &info);
4080 record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
4081 enum aarch64_operand_error_kind kind,
4082 const char* error, const int *extra_data)
4084 aarch64_operand_error info;
4088 info.data[0] = extra_data[0];
4089 info.data[1] = extra_data[1];
4090 info.data[2] = extra_data[2];
4091 record_operand_error_info (opcode, &info);
4095 record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx,
4096 const char* error, int lower_bound,
4099 int data[3] = {lower_bound, upper_bound, 0};
4100 record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE,
4104 /* Remove the operand error record for *OPCODE. */
4105 static void ATTRIBUTE_UNUSED
4106 remove_operand_error_record (const aarch64_opcode *opcode)
4108 if (opcode_has_operand_error_p (opcode))
4110 operand_error_record* record = operand_error_report.head;
4111 gas_assert (record != NULL && operand_error_report.tail != NULL);
4112 operand_error_report.head = record->next;
4113 record->next = free_opnd_error_record_nodes;
4114 free_opnd_error_record_nodes = record;
4115 if (operand_error_report.head == NULL)
4117 gas_assert (operand_error_report.tail == record);
4118 operand_error_report.tail = NULL;
4123 /* Given the instruction in *INSTR, return the index of the best matched
4124 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4126 Return -1 if there is no qualifier sequence; return the first match
4127 if there is multiple matches found. */
4130 find_best_match (const aarch64_inst *instr,
4131 const aarch64_opnd_qualifier_seq_t *qualifiers_list)
4133 int i, num_opnds, max_num_matched, idx;
4135 num_opnds = aarch64_num_of_operands (instr->opcode);
4138 DEBUG_TRACE ("no operand");
4142 max_num_matched = 0;
4145 /* For each pattern. */
4146 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4149 const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
4151 /* Most opcodes has much fewer patterns in the list. */
4152 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
4154 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
4155 if (i != 0 && idx == -1)
4156 /* If nothing has been matched, return the 1st sequence. */
4161 for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers)
4162 if (*qualifiers == instr->operands[j].qualifier)
4165 if (num_matched > max_num_matched)
4167 max_num_matched = num_matched;
4172 DEBUG_TRACE ("return with %d", idx);
4176 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4177 corresponding operands in *INSTR. */
4180 assign_qualifier_sequence (aarch64_inst *instr,
4181 const aarch64_opnd_qualifier_t *qualifiers)
4184 int num_opnds = aarch64_num_of_operands (instr->opcode);
4185 gas_assert (num_opnds);
4186 for (i = 0; i < num_opnds; ++i, ++qualifiers)
4187 instr->operands[i].qualifier = *qualifiers;
4190 /* Print operands for the diagnosis purpose. */
4193 print_operands (char *buf, const aarch64_opcode *opcode,
4194 const aarch64_opnd_info *opnds)
4198 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
4200 const size_t size = 128;
4203 /* We regard the opcode operand info more, however we also look into
4204 the inst->operands to support the disassembling of the optional
4206 The two operand code should be the same in all cases, apart from
4207 when the operand can be optional. */
4208 if (opcode->operands[i] == AARCH64_OPND_NIL
4209 || opnds[i].type == AARCH64_OPND_NIL)
4212 /* Generate the operand string in STR. */
4213 aarch64_print_operand (str, size, 0, opcode, opnds, i, NULL, NULL);
4217 strcat (buf, i == 0 ? " " : ",");
4219 /* Append the operand string. */
4224 /* Send to stderr a string as information. */
4227 output_info (const char *format, ...)
4233 as_where (&file, &line);
4237 fprintf (stderr, "%s:%u: ", file, line);
4239 fprintf (stderr, "%s: ", file);
4241 fprintf (stderr, _("Info: "));
4242 va_start (args, format);
4243 vfprintf (stderr, format, args);
4245 (void) putc ('\n', stderr);
4248 /* Output one operand error record. */
4251 output_operand_error_record (const operand_error_record *record, char *str)
4253 const aarch64_operand_error *detail = &record->detail;
4254 int idx = detail->index;
4255 const aarch64_opcode *opcode = record->opcode;
4256 enum aarch64_opnd opd_code = (idx >= 0 ? opcode->operands[idx]
4257 : AARCH64_OPND_NIL);
4259 switch (detail->kind)
4261 case AARCH64_OPDE_NIL:
4265 case AARCH64_OPDE_SYNTAX_ERROR:
4266 case AARCH64_OPDE_RECOVERABLE:
4267 case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
4268 case AARCH64_OPDE_OTHER_ERROR:
4269 /* Use the prepared error message if there is, otherwise use the
4270 operand description string to describe the error. */
4271 if (detail->error != NULL)
4274 as_bad (_("%s -- `%s'"), detail->error, str);
4276 as_bad (_("%s at operand %d -- `%s'"),
4277 detail->error, idx + 1, str);
4281 gas_assert (idx >= 0);
4282 as_bad (_("operand %d should be %s -- `%s'"), idx + 1,
4283 aarch64_get_operand_desc (opd_code), str);
4287 case AARCH64_OPDE_INVALID_VARIANT:
4288 as_bad (_("operand mismatch -- `%s'"), str);
4289 if (verbose_error_p)
4291 /* We will try to correct the erroneous instruction and also provide
4292 more information e.g. all other valid variants.
4294 The string representation of the corrected instruction and other
4295 valid variants are generated by
4297 1) obtaining the intermediate representation of the erroneous
4299 2) manipulating the IR, e.g. replacing the operand qualifier;
4300 3) printing out the instruction by calling the printer functions
4301 shared with the disassembler.
4303 The limitation of this method is that the exact input assembly
4304 line cannot be accurately reproduced in some cases, for example an
4305 optional operand present in the actual assembly line will be
4306 omitted in the output; likewise for the optional syntax rules,
4307 e.g. the # before the immediate. Another limitation is that the
4308 assembly symbols and relocation operations in the assembly line
4309 currently cannot be printed out in the error report. Last but not
4310 least, when there is other error(s) co-exist with this error, the
4311 'corrected' instruction may be still incorrect, e.g. given
4312 'ldnp h0,h1,[x0,#6]!'
4313 this diagnosis will provide the version:
4314 'ldnp s0,s1,[x0,#6]!'
4315 which is still not right. */
4316 size_t len = strlen (get_mnemonic_name (str));
4319 const size_t size = 2048;
4321 aarch64_inst *inst_base = &inst.base;
4322 const aarch64_opnd_qualifier_seq_t *qualifiers_list;
4325 reset_aarch64_instruction (&inst);
4326 inst_base->opcode = opcode;
4328 /* Reset the error report so that there is no side effect on the
4329 following operand parsing. */
4330 init_operand_error_report ();
4333 result = parse_operands (str + len, opcode)
4334 && programmer_friendly_fixup (&inst);
4335 gas_assert (result);
4336 result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
4338 gas_assert (!result);
4340 /* Find the most matched qualifier sequence. */
4341 qlf_idx = find_best_match (inst_base, opcode->qualifiers_list);
4342 gas_assert (qlf_idx > -1);
4344 /* Assign the qualifiers. */
4345 assign_qualifier_sequence (inst_base,
4346 opcode->qualifiers_list[qlf_idx]);
4348 /* Print the hint. */
4349 output_info (_(" did you mean this?"));
4350 snprintf (buf, size, "\t%s", get_mnemonic_name (str));
4351 print_operands (buf, opcode, inst_base->operands);
4352 output_info (_(" %s"), buf);
4354 /* Print out other variant(s) if there is any. */
4356 !empty_qualifier_sequence_p (opcode->qualifiers_list[1]))
4357 output_info (_(" other valid variant(s):"));
4359 /* For each pattern. */
4360 qualifiers_list = opcode->qualifiers_list;
4361 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4363 /* Most opcodes has much fewer patterns in the list.
4364 First NIL qualifier indicates the end in the list. */
4365 if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
4370 /* Mnemonics name. */
4371 snprintf (buf, size, "\t%s", get_mnemonic_name (str));
4373 /* Assign the qualifiers. */
4374 assign_qualifier_sequence (inst_base, *qualifiers_list);
4376 /* Print instruction. */
4377 print_operands (buf, opcode, inst_base->operands);
4379 output_info (_(" %s"), buf);
4385 case AARCH64_OPDE_OUT_OF_RANGE:
4386 if (detail->data[0] != detail->data[1])
4387 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4388 detail->error ? detail->error : _("immediate value"),
4389 detail->data[0], detail->data[1], idx + 1, str);
4391 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4392 detail->error ? detail->error : _("immediate value"),
4393 detail->data[0], idx + 1, str);
4396 case AARCH64_OPDE_REG_LIST:
4397 if (detail->data[0] == 1)
4398 as_bad (_("invalid number of registers in the list; "
4399 "only 1 register is expected at operand %d -- `%s'"),
4402 as_bad (_("invalid number of registers in the list; "
4403 "%d registers are expected at operand %d -- `%s'"),
4404 detail->data[0], idx + 1, str);
4407 case AARCH64_OPDE_UNALIGNED:
4408 as_bad (_("immediate value should be a multiple of "
4409 "%d at operand %d -- `%s'"),
4410 detail->data[0], idx + 1, str);
4419 /* Process and output the error message about the operand mismatching.
4421 When this function is called, the operand error information had
4422 been collected for an assembly line and there will be multiple
4423 errors in the case of mulitple instruction templates; output the
4424 error message that most closely describes the problem. */
4427 output_operand_error_report (char *str)
4429 int largest_error_pos;
4430 const char *msg = NULL;
4431 enum aarch64_operand_error_kind kind;
4432 operand_error_record *curr;
4433 operand_error_record *head = operand_error_report.head;
4434 operand_error_record *record = NULL;
4436 /* No error to report. */
4440 gas_assert (head != NULL && operand_error_report.tail != NULL);
4442 /* Only one error. */
4443 if (head == operand_error_report.tail)
4445 DEBUG_TRACE ("single opcode entry with error kind: %s",
4446 operand_mismatch_kind_names[head->detail.kind]);
4447 output_operand_error_record (head, str);
4451 /* Find the error kind of the highest severity. */
4452 DEBUG_TRACE ("multiple opcode entres with error kind");
4453 kind = AARCH64_OPDE_NIL;
4454 for (curr = head; curr != NULL; curr = curr->next)
4456 gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
4457 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
4458 if (operand_error_higher_severity_p (curr->detail.kind, kind))
4459 kind = curr->detail.kind;
4461 gas_assert (kind != AARCH64_OPDE_NIL);
4463 /* Pick up one of errors of KIND to report. */
4464 largest_error_pos = -2; /* Index can be -1 which means unknown index. */
4465 for (curr = head; curr != NULL; curr = curr->next)
4467 if (curr->detail.kind != kind)
4469 /* If there are multiple errors, pick up the one with the highest
4470 mismatching operand index. In the case of multiple errors with
4471 the equally highest operand index, pick up the first one or the
4472 first one with non-NULL error message. */
4473 if (curr->detail.index > largest_error_pos
4474 || (curr->detail.index == largest_error_pos && msg == NULL
4475 && curr->detail.error != NULL))
4477 largest_error_pos = curr->detail.index;
4479 msg = record->detail.error;
4483 gas_assert (largest_error_pos != -2 && record != NULL);
4484 DEBUG_TRACE ("Pick up error kind %s to report",
4485 operand_mismatch_kind_names[record->detail.kind]);
4488 output_operand_error_record (record, str);
4491 /* Write an AARCH64 instruction to buf - always little-endian. */
4493 put_aarch64_insn (char *buf, uint32_t insn)
4495 unsigned char *where = (unsigned char *) buf;
4497 where[1] = insn >> 8;
4498 where[2] = insn >> 16;
4499 where[3] = insn >> 24;
4503 get_aarch64_insn (char *buf)
4505 unsigned char *where = (unsigned char *) buf;
4507 result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
4512 output_inst (struct aarch64_inst *new_inst)
4516 to = frag_more (INSN_SIZE);
4518 frag_now->tc_frag_data.recorded = 1;
4520 put_aarch64_insn (to, inst.base.value);
4522 if (inst.reloc.type != BFD_RELOC_UNUSED)
4524 fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal,
4525 INSN_SIZE, &inst.reloc.exp,
4528 DEBUG_TRACE ("Prepared relocation fix up");
4529 /* Don't check the addend value against the instruction size,
4530 that's the job of our code in md_apply_fix(). */
4531 fixp->fx_no_overflow = 1;
4532 if (new_inst != NULL)
4533 fixp->tc_fix_data.inst = new_inst;
4534 if (aarch64_gas_internal_fixup_p ())
4536 gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL);
4537 fixp->tc_fix_data.opnd = inst.reloc.opnd;
4538 fixp->fx_addnumber = inst.reloc.flags;
4542 dwarf2_emit_insn (INSN_SIZE);
4545 /* Link together opcodes of the same name. */
4549 aarch64_opcode *opcode;
4550 struct templates *next;
4553 typedef struct templates templates;
4556 lookup_mnemonic (const char *start, int len)
4558 templates *templ = NULL;
4560 templ = hash_find_n (aarch64_ops_hsh, start, len);
4564 /* Subroutine of md_assemble, responsible for looking up the primary
4565 opcode from the mnemonic the user wrote. STR points to the
4566 beginning of the mnemonic. */
4569 opcode_lookup (char **str)
4572 const aarch64_cond *cond;
4576 /* Scan up to the end of the mnemonic, which must end in white space,
4577 '.', or end of string. */
4578 for (base = end = *str; is_part_of_name(*end); end++)
4585 inst.cond = COND_ALWAYS;
4587 /* Handle a possible condition. */
4590 cond = hash_find_n (aarch64_cond_hsh, end + 1, 2);
4593 inst.cond = cond->value;
4607 if (inst.cond == COND_ALWAYS)
4609 /* Look for unaffixed mnemonic. */
4610 return lookup_mnemonic (base, len);
4614 /* append ".c" to mnemonic if conditional */
4615 memcpy (condname, base, len);
4616 memcpy (condname + len, ".c", 2);
4619 return lookup_mnemonic (base, len);
4625 /* Internal helper routine converting a vector neon_type_el structure
4626 *VECTYPE to a corresponding operand qualifier. */
4628 static inline aarch64_opnd_qualifier_t
4629 vectype_to_qualifier (const struct neon_type_el *vectype)
4631 /* Element size in bytes indexed by neon_el_type. */
4632 const unsigned char ele_size[5]
4635 if (!vectype->defined || vectype->type == NT_invtype)
4636 goto vectype_conversion_fail;
4638 gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
4640 if (vectype->defined & NTA_HASINDEX)
4641 /* Vector element register. */
4642 return AARCH64_OPND_QLF_S_B + vectype->type;
4645 /* Vector register. */
4646 int reg_size = ele_size[vectype->type] * vectype->width;
4648 if (reg_size != 16 && reg_size != 8)
4649 goto vectype_conversion_fail;
4650 /* The conversion is calculated based on the relation of the order of
4651 qualifiers to the vector element size and vector register size. */
4652 offset = (vectype->type == NT_q)
4653 ? 8 : (vectype->type << 1) + (reg_size >> 4);
4654 gas_assert (offset <= 8);
4655 return AARCH64_OPND_QLF_V_8B + offset;
4658 vectype_conversion_fail:
4659 first_error (_("bad vector arrangement type"));
4660 return AARCH64_OPND_QLF_NIL;
4663 /* Process an optional operand that is found omitted from the assembly line.
4664 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4665 instruction's opcode entry while IDX is the index of this omitted operand.
4669 process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
4670 int idx, aarch64_opnd_info *operand)
4672 aarch64_insn default_value = get_optional_operand_default_value (opcode);
4673 gas_assert (optional_operand_p (opcode, idx));
4674 gas_assert (!operand->present);
4678 case AARCH64_OPND_Rd:
4679 case AARCH64_OPND_Rn:
4680 case AARCH64_OPND_Rm:
4681 case AARCH64_OPND_Rt:
4682 case AARCH64_OPND_Rt2:
4683 case AARCH64_OPND_Rs:
4684 case AARCH64_OPND_Ra:
4685 case AARCH64_OPND_Rt_SYS:
4686 case AARCH64_OPND_Rd_SP:
4687 case AARCH64_OPND_Rn_SP:
4688 case AARCH64_OPND_Fd:
4689 case AARCH64_OPND_Fn:
4690 case AARCH64_OPND_Fm:
4691 case AARCH64_OPND_Fa:
4692 case AARCH64_OPND_Ft:
4693 case AARCH64_OPND_Ft2:
4694 case AARCH64_OPND_Sd:
4695 case AARCH64_OPND_Sn:
4696 case AARCH64_OPND_Sm:
4697 case AARCH64_OPND_Vd:
4698 case AARCH64_OPND_Vn:
4699 case AARCH64_OPND_Vm:
4700 case AARCH64_OPND_VdD1:
4701 case AARCH64_OPND_VnD1:
4702 operand->reg.regno = default_value;
4705 case AARCH64_OPND_Ed:
4706 case AARCH64_OPND_En:
4707 case AARCH64_OPND_Em:
4708 operand->reglane.regno = default_value;
4711 case AARCH64_OPND_IDX:
4712 case AARCH64_OPND_BIT_NUM:
4713 case AARCH64_OPND_IMMR:
4714 case AARCH64_OPND_IMMS:
4715 case AARCH64_OPND_SHLL_IMM:
4716 case AARCH64_OPND_IMM_VLSL:
4717 case AARCH64_OPND_IMM_VLSR:
4718 case AARCH64_OPND_CCMP_IMM:
4719 case AARCH64_OPND_FBITS:
4720 case AARCH64_OPND_UIMM4:
4721 case AARCH64_OPND_UIMM3_OP1:
4722 case AARCH64_OPND_UIMM3_OP2:
4723 case AARCH64_OPND_IMM:
4724 case AARCH64_OPND_WIDTH:
4725 case AARCH64_OPND_UIMM7:
4726 case AARCH64_OPND_NZCV:
4727 operand->imm.value = default_value;
4730 case AARCH64_OPND_EXCEPTION:
4731 inst.reloc.type = BFD_RELOC_UNUSED;
4734 case AARCH64_OPND_BARRIER_ISB:
4735 operand->barrier = aarch64_barrier_options + default_value;
4742 /* Process the relocation type for move wide instructions.
4743 Return TRUE on success; otherwise return FALSE. */
4746 process_movw_reloc_info (void)
4751 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
4753 if (inst.base.opcode->op == OP_MOVK)
4754 switch (inst.reloc.type)
4756 case BFD_RELOC_AARCH64_MOVW_G0_S:
4757 case BFD_RELOC_AARCH64_MOVW_G1_S:
4758 case BFD_RELOC_AARCH64_MOVW_G2_S:
4759 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
4760 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4761 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4762 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4764 (_("the specified relocation type is not allowed for MOVK"));
4770 switch (inst.reloc.type)
4772 case BFD_RELOC_AARCH64_MOVW_G0:
4773 case BFD_RELOC_AARCH64_MOVW_G0_NC:
4774 case BFD_RELOC_AARCH64_MOVW_G0_S:
4775 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
4776 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
4777 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
4778 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
4779 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
4780 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
4781 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4782 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4785 case BFD_RELOC_AARCH64_MOVW_G1:
4786 case BFD_RELOC_AARCH64_MOVW_G1_NC:
4787 case BFD_RELOC_AARCH64_MOVW_G1_S:
4788 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
4789 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
4790 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
4791 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
4792 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
4793 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
4794 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4795 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4798 case BFD_RELOC_AARCH64_MOVW_G2:
4799 case BFD_RELOC_AARCH64_MOVW_G2_NC:
4800 case BFD_RELOC_AARCH64_MOVW_G2_S:
4801 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
4802 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4805 set_fatal_syntax_error
4806 (_("the specified relocation type is not allowed for 32-bit "
4812 case BFD_RELOC_AARCH64_MOVW_G3:
4815 set_fatal_syntax_error
4816 (_("the specified relocation type is not allowed for 32-bit "
4823 /* More cases should be added when more MOVW-related relocation types
4824 are supported in GAS. */
4825 gas_assert (aarch64_gas_internal_fixup_p ());
4826 /* The shift amount should have already been set by the parser. */
4829 inst.base.operands[1].shifter.amount = shift;
4833 /* A primitive log caculator. */
4835 static inline unsigned int
4836 get_logsz (unsigned int size)
4838 const unsigned char ls[16] =
4839 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4845 gas_assert (ls[size - 1] != (unsigned char)-1);
4846 return ls[size - 1];
4849 /* Determine and return the real reloc type code for an instruction
4850 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4852 static inline bfd_reloc_code_real_type
4853 ldst_lo12_determine_real_reloc_type (void)
4856 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
4857 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
4859 const bfd_reloc_code_real_type reloc_ldst_lo12[3][5] = {
4861 BFD_RELOC_AARCH64_LDST8_LO12,
4862 BFD_RELOC_AARCH64_LDST16_LO12,
4863 BFD_RELOC_AARCH64_LDST32_LO12,
4864 BFD_RELOC_AARCH64_LDST64_LO12,
4865 BFD_RELOC_AARCH64_LDST128_LO12
4868 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12,
4869 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12,
4870 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12,
4871 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12,
4872 BFD_RELOC_AARCH64_NONE
4875 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC,
4876 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC,
4877 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
4878 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
4879 BFD_RELOC_AARCH64_NONE
4883 gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
4884 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4886 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC));
4887 gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
4889 if (opd1_qlf == AARCH64_OPND_QLF_NIL)
4891 aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list,
4893 gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
4895 logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
4896 if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4897 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
4898 gas_assert (logsz <= 3);
4900 gas_assert (logsz <= 4);
4902 /* In reloc.c, these pseudo relocation types should be defined in similar
4903 order as above reloc_ldst_lo12 array. Because the array index calcuation
4904 below relies on this. */
4905 return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
4908 /* Check whether a register list REGINFO is valid. The registers must be
4909 numbered in increasing order (modulo 32), in increments of one or two.
4911 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4914 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4917 reg_list_valid_p (uint32_t reginfo, int accept_alternate)
4919 uint32_t i, nb_regs, prev_regno, incr;
4921 nb_regs = 1 + (reginfo & 0x3);
4923 prev_regno = reginfo & 0x1f;
4924 incr = accept_alternate ? 2 : 1;
4926 for (i = 1; i < nb_regs; ++i)
4928 uint32_t curr_regno;
4930 curr_regno = reginfo & 0x1f;
4931 if (curr_regno != ((prev_regno + incr) & 0x1f))
4933 prev_regno = curr_regno;
4939 /* Generic instruction operand parser. This does no encoding and no
4940 semantic validation; it merely squirrels values away in the inst
4941 structure. Returns TRUE or FALSE depending on whether the
4942 specified grammar matched. */
4945 parse_operands (char *str, const aarch64_opcode *opcode)
4948 char *backtrack_pos = 0;
4949 const enum aarch64_opnd *operands = opcode->operands;
4952 skip_whitespace (str);
4954 for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
4957 int isreg32, isregzero;
4958 int comma_skipped_p = 0;
4959 aarch64_reg_type rtype;
4960 struct neon_type_el vectype;
4961 aarch64_opnd_info *info = &inst.base.operands[i];
4963 DEBUG_TRACE ("parse operand %d", i);
4965 /* Assign the operand code. */
4966 info->type = operands[i];
4968 if (optional_operand_p (opcode, i))
4970 /* Remember where we are in case we need to backtrack. */
4971 gas_assert (!backtrack_pos);
4972 backtrack_pos = str;
4975 /* Expect comma between operands; the backtrack mechanizm will take
4976 care of cases of omitted optional operand. */
4977 if (i > 0 && ! skip_past_char (&str, ','))
4979 set_syntax_error (_("comma expected between operands"));
4983 comma_skipped_p = 1;
4985 switch (operands[i])
4987 case AARCH64_OPND_Rd:
4988 case AARCH64_OPND_Rn:
4989 case AARCH64_OPND_Rm:
4990 case AARCH64_OPND_Rt:
4991 case AARCH64_OPND_Rt2:
4992 case AARCH64_OPND_Rs:
4993 case AARCH64_OPND_Ra:
4994 case AARCH64_OPND_Rt_SYS:
4995 case AARCH64_OPND_PAIRREG:
4996 po_int_reg_or_fail (1, 0);
4999 case AARCH64_OPND_Rd_SP:
5000 case AARCH64_OPND_Rn_SP:
5001 po_int_reg_or_fail (0, 1);
5004 case AARCH64_OPND_Rm_EXT:
5005 case AARCH64_OPND_Rm_SFT:
5006 po_misc_or_fail (parse_shifter_operand
5007 (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT
5009 : SHIFTED_LOGIC_IMM)));
5010 if (!info->shifter.operator_present)
5012 /* Default to LSL if not present. Libopcodes prefers shifter
5013 kind to be explicit. */
5014 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5015 info->shifter.kind = AARCH64_MOD_LSL;
5016 /* For Rm_EXT, libopcodes will carry out further check on whether
5017 or not stack pointer is used in the instruction (Recall that
5018 "the extend operator is not optional unless at least one of
5019 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5023 case AARCH64_OPND_Fd:
5024 case AARCH64_OPND_Fn:
5025 case AARCH64_OPND_Fm:
5026 case AARCH64_OPND_Fa:
5027 case AARCH64_OPND_Ft:
5028 case AARCH64_OPND_Ft2:
5029 case AARCH64_OPND_Sd:
5030 case AARCH64_OPND_Sn:
5031 case AARCH64_OPND_Sm:
5032 val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
5033 if (val == PARSE_FAIL)
5035 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
5038 gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
5040 info->reg.regno = val;
5041 info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
5044 case AARCH64_OPND_Vd:
5045 case AARCH64_OPND_Vn:
5046 case AARCH64_OPND_Vm:
5047 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
5048 if (val == PARSE_FAIL)
5050 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
5053 if (vectype.defined & NTA_HASINDEX)
5056 info->reg.regno = val;
5057 info->qualifier = vectype_to_qualifier (&vectype);
5058 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5062 case AARCH64_OPND_VdD1:
5063 case AARCH64_OPND_VnD1:
5064 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
5065 if (val == PARSE_FAIL)
5067 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
5070 if (vectype.type != NT_d || vectype.index != 1)
5072 set_fatal_syntax_error
5073 (_("the top half of a 128-bit FP/SIMD register is expected"));
5076 info->reg.regno = val;
5077 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5078 here; it is correct for the purpose of encoding/decoding since
5079 only the register number is explicitly encoded in the related
5080 instructions, although this appears a bit hacky. */
5081 info->qualifier = AARCH64_OPND_QLF_S_D;
5084 case AARCH64_OPND_Ed:
5085 case AARCH64_OPND_En:
5086 case AARCH64_OPND_Em:
5087 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
5088 if (val == PARSE_FAIL)
5090 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
5093 if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
5096 info->reglane.regno = val;
5097 info->reglane.index = vectype.index;
5098 info->qualifier = vectype_to_qualifier (&vectype);
5099 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5103 case AARCH64_OPND_LVn:
5104 case AARCH64_OPND_LVt:
5105 case AARCH64_OPND_LVt_AL:
5106 case AARCH64_OPND_LEt:
5107 if ((val = parse_neon_reg_list (&str, &vectype)) == PARSE_FAIL)
5109 if (! reg_list_valid_p (val, /* accept_alternate */ 0))
5111 set_fatal_syntax_error (_("invalid register list"));
5114 info->reglist.first_regno = (val >> 2) & 0x1f;
5115 info->reglist.num_regs = (val & 0x3) + 1;
5116 if (operands[i] == AARCH64_OPND_LEt)
5118 if (!(vectype.defined & NTA_HASINDEX))
5120 info->reglist.has_index = 1;
5121 info->reglist.index = vectype.index;
5123 else if (!(vectype.defined & NTA_HASTYPE))
5125 info->qualifier = vectype_to_qualifier (&vectype);
5126 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5130 case AARCH64_OPND_Cn:
5131 case AARCH64_OPND_Cm:
5132 po_reg_or_fail (REG_TYPE_CN);
5135 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN)));
5138 inst.base.operands[i].reg.regno = val;
5141 case AARCH64_OPND_SHLL_IMM:
5142 case AARCH64_OPND_IMM_VLSR:
5143 po_imm_or_fail (1, 64);
5144 info->imm.value = val;
5147 case AARCH64_OPND_CCMP_IMM:
5148 case AARCH64_OPND_FBITS:
5149 case AARCH64_OPND_UIMM4:
5150 case AARCH64_OPND_UIMM3_OP1:
5151 case AARCH64_OPND_UIMM3_OP2:
5152 case AARCH64_OPND_IMM_VLSL:
5153 case AARCH64_OPND_IMM:
5154 case AARCH64_OPND_WIDTH:
5155 po_imm_nc_or_fail ();
5156 info->imm.value = val;
5159 case AARCH64_OPND_UIMM7:
5160 po_imm_or_fail (0, 127);
5161 info->imm.value = val;
5164 case AARCH64_OPND_IDX:
5165 case AARCH64_OPND_BIT_NUM:
5166 case AARCH64_OPND_IMMR:
5167 case AARCH64_OPND_IMMS:
5168 po_imm_or_fail (0, 63);
5169 info->imm.value = val;
5172 case AARCH64_OPND_IMM0:
5173 po_imm_nc_or_fail ();
5176 set_fatal_syntax_error (_("immediate zero expected"));
5179 info->imm.value = 0;
5182 case AARCH64_OPND_FPIMM0:
5185 bfd_boolean res1 = FALSE, res2 = FALSE;
5186 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5187 it is probably not worth the effort to support it. */
5188 if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE))
5189 && !(res2 = parse_constant_immediate (&str, &val)))
5191 if ((res1 && qfloat == 0) || (res2 && val == 0))
5193 info->imm.value = 0;
5194 info->imm.is_fp = 1;
5197 set_fatal_syntax_error (_("immediate zero expected"));
5201 case AARCH64_OPND_IMM_MOV:
5204 if (reg_name_p (str, REG_TYPE_R_Z_SP) ||
5205 reg_name_p (str, REG_TYPE_VN))
5208 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5210 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5211 later. fix_mov_imm_insn will try to determine a machine
5212 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5213 message if the immediate cannot be moved by a single
5215 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5216 inst.base.operands[i].skip = 1;
5220 case AARCH64_OPND_SIMD_IMM:
5221 case AARCH64_OPND_SIMD_IMM_SFT:
5222 if (! parse_big_immediate (&str, &val))
5224 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5226 /* need_libopcodes_p */ 1,
5229 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5230 shift, we don't check it here; we leave the checking to
5231 the libopcodes (operand_general_constraint_met_p). By
5232 doing this, we achieve better diagnostics. */
5233 if (skip_past_comma (&str)
5234 && ! parse_shift (&str, info, SHIFTED_LSL_MSL))
5236 if (!info->shifter.operator_present
5237 && info->type == AARCH64_OPND_SIMD_IMM_SFT)
5239 /* Default to LSL if not present. Libopcodes prefers shifter
5240 kind to be explicit. */
5241 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5242 info->shifter.kind = AARCH64_MOD_LSL;
5246 case AARCH64_OPND_FPIMM:
5247 case AARCH64_OPND_SIMD_FPIMM:
5251 = (aarch64_get_qualifier_esize (inst.base.operands[0].qualifier)
5253 if (! parse_aarch64_imm_float (&str, &qfloat, dp_p))
5257 set_fatal_syntax_error (_("invalid floating-point constant"));
5260 inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat);
5261 inst.base.operands[i].imm.is_fp = 1;
5265 case AARCH64_OPND_LIMM:
5266 po_misc_or_fail (parse_shifter_operand (&str, info,
5267 SHIFTED_LOGIC_IMM));
5268 if (info->shifter.operator_present)
5270 set_fatal_syntax_error
5271 (_("shift not allowed for bitmask immediate"));
5274 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5276 /* need_libopcodes_p */ 1,
5280 case AARCH64_OPND_AIMM:
5281 if (opcode->op == OP_ADD)
5282 /* ADD may have relocation types. */
5283 po_misc_or_fail (parse_shifter_operand_reloc (&str, info,
5284 SHIFTED_ARITH_IMM));
5286 po_misc_or_fail (parse_shifter_operand (&str, info,
5287 SHIFTED_ARITH_IMM));
5288 switch (inst.reloc.type)
5290 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
5291 info->shifter.amount = 12;
5293 case BFD_RELOC_UNUSED:
5294 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
5295 if (info->shifter.kind != AARCH64_MOD_NONE)
5296 inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT;
5297 inst.reloc.pc_rel = 0;
5302 info->imm.value = 0;
5303 if (!info->shifter.operator_present)
5305 /* Default to LSL if not present. Libopcodes prefers shifter
5306 kind to be explicit. */
5307 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5308 info->shifter.kind = AARCH64_MOD_LSL;
5312 case AARCH64_OPND_HALF:
5314 /* #<imm16> or relocation. */
5315 int internal_fixup_p;
5316 po_misc_or_fail (parse_half (&str, &internal_fixup_p));
5317 if (internal_fixup_p)
5318 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
5319 skip_whitespace (str);
5320 if (skip_past_comma (&str))
5322 /* {, LSL #<shift>} */
5323 if (! aarch64_gas_internal_fixup_p ())
5325 set_fatal_syntax_error (_("can't mix relocation modifier "
5326 "with explicit shift"));
5329 po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
5332 inst.base.operands[i].shifter.amount = 0;
5333 inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
5334 inst.base.operands[i].imm.value = 0;
5335 if (! process_movw_reloc_info ())
5340 case AARCH64_OPND_EXCEPTION:
5341 po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp));
5342 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5344 /* need_libopcodes_p */ 0,
5348 case AARCH64_OPND_NZCV:
5350 const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4);
5354 info->imm.value = nzcv->value;
5357 po_imm_or_fail (0, 15);
5358 info->imm.value = val;
5362 case AARCH64_OPND_COND:
5363 case AARCH64_OPND_COND1:
5364 info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
5366 if (info->cond == NULL)
5368 set_syntax_error (_("invalid condition"));
5371 else if (operands[i] == AARCH64_OPND_COND1
5372 && (info->cond->value & 0xe) == 0xe)
5374 /* Not allow AL or NV. */
5375 set_default_error ();
5380 case AARCH64_OPND_ADDR_ADRP:
5381 po_misc_or_fail (parse_adrp (&str));
5382 /* Clear the value as operand needs to be relocated. */
5383 info->imm.value = 0;
5386 case AARCH64_OPND_ADDR_PCREL14:
5387 case AARCH64_OPND_ADDR_PCREL19:
5388 case AARCH64_OPND_ADDR_PCREL21:
5389 case AARCH64_OPND_ADDR_PCREL26:
5390 po_misc_or_fail (parse_address_reloc (&str, info));
5391 if (!info->addr.pcrel)
5393 set_syntax_error (_("invalid pc-relative address"));
5396 if (inst.gen_lit_pool
5397 && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT))
5399 /* Only permit "=value" in the literal load instructions.
5400 The literal will be generated by programmer_friendly_fixup. */
5401 set_syntax_error (_("invalid use of \"=immediate\""));
5404 if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str))
5406 set_syntax_error (_("unrecognized relocation suffix"));
5409 if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
5411 info->imm.value = inst.reloc.exp.X_add_number;
5412 inst.reloc.type = BFD_RELOC_UNUSED;
5416 info->imm.value = 0;
5417 if (inst.reloc.type == BFD_RELOC_UNUSED)
5418 switch (opcode->iclass)
5422 /* e.g. CBZ or B.COND */
5423 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5424 inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
5428 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
5429 inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
5433 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
5435 (opcode->op == OP_BL) ? BFD_RELOC_AARCH64_CALL26
5436 : BFD_RELOC_AARCH64_JUMP26;
5439 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5440 inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
5443 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
5444 inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
5450 inst.reloc.pc_rel = 1;
5454 case AARCH64_OPND_ADDR_SIMPLE:
5455 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
5456 /* [<Xn|SP>{, #<simm>}] */
5457 po_char_or_fail ('[');
5458 po_reg_or_fail (REG_TYPE_R64_SP);
5459 /* Accept optional ", #0". */
5460 if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
5461 && skip_past_char (&str, ','))
5463 skip_past_char (&str, '#');
5464 if (! skip_past_char (&str, '0'))
5466 set_fatal_syntax_error
5467 (_("the optional immediate offset can only be 0"));
5471 po_char_or_fail (']');
5472 info->addr.base_regno = val;
5475 case AARCH64_OPND_ADDR_REGOFF:
5476 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5477 po_misc_or_fail (parse_address (&str, info, 0));
5478 if (info->addr.pcrel || !info->addr.offset.is_reg
5479 || !info->addr.preind || info->addr.postind
5480 || info->addr.writeback)
5482 set_syntax_error (_("invalid addressing mode"));
5485 if (!info->shifter.operator_present)
5487 /* Default to LSL if not present. Libopcodes prefers shifter
5488 kind to be explicit. */
5489 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5490 info->shifter.kind = AARCH64_MOD_LSL;
5492 /* Qualifier to be deduced by libopcodes. */
5495 case AARCH64_OPND_ADDR_SIMM7:
5496 po_misc_or_fail (parse_address (&str, info, 0));
5497 if (info->addr.pcrel || info->addr.offset.is_reg
5498 || (!info->addr.preind && !info->addr.postind))
5500 set_syntax_error (_("invalid addressing mode"));
5503 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5505 /* need_libopcodes_p */ 1,
5509 case AARCH64_OPND_ADDR_SIMM9:
5510 case AARCH64_OPND_ADDR_SIMM9_2:
5511 po_misc_or_fail (parse_address_reloc (&str, info));
5512 if (info->addr.pcrel || info->addr.offset.is_reg
5513 || (!info->addr.preind && !info->addr.postind)
5514 || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
5515 && info->addr.writeback))
5517 set_syntax_error (_("invalid addressing mode"));
5520 if (inst.reloc.type != BFD_RELOC_UNUSED)
5522 set_syntax_error (_("relocation not allowed"));
5525 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5527 /* need_libopcodes_p */ 1,
5531 case AARCH64_OPND_ADDR_UIMM12:
5532 po_misc_or_fail (parse_address_reloc (&str, info));
5533 if (info->addr.pcrel || info->addr.offset.is_reg
5534 || !info->addr.preind || info->addr.writeback)
5536 set_syntax_error (_("invalid addressing mode"));
5539 if (inst.reloc.type == BFD_RELOC_UNUSED)
5540 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5541 else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
5543 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12)
5545 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC))
5546 inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
5547 /* Leave qualifier to be determined by libopcodes. */
5550 case AARCH64_OPND_SIMD_ADDR_POST:
5551 /* [<Xn|SP>], <Xm|#<amount>> */
5552 po_misc_or_fail (parse_address (&str, info, 1));
5553 if (!info->addr.postind || !info->addr.writeback)
5555 set_syntax_error (_("invalid addressing mode"));
5558 if (!info->addr.offset.is_reg)
5560 if (inst.reloc.exp.X_op == O_constant)
5561 info->addr.offset.imm = inst.reloc.exp.X_add_number;
5564 set_fatal_syntax_error
5565 (_("writeback value should be an immediate constant"));
5572 case AARCH64_OPND_SYSREG:
5573 if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0))
5576 set_syntax_error (_("unknown or missing system register name"));
5579 inst.base.operands[i].sysreg = val;
5582 case AARCH64_OPND_PSTATEFIELD:
5583 if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1))
5586 set_syntax_error (_("unknown or missing PSTATE field name"));
5589 inst.base.operands[i].pstatefield = val;
5592 case AARCH64_OPND_SYSREG_IC:
5593 inst.base.operands[i].sysins_op =
5594 parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
5596 case AARCH64_OPND_SYSREG_DC:
5597 inst.base.operands[i].sysins_op =
5598 parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
5600 case AARCH64_OPND_SYSREG_AT:
5601 inst.base.operands[i].sysins_op =
5602 parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
5604 case AARCH64_OPND_SYSREG_TLBI:
5605 inst.base.operands[i].sysins_op =
5606 parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
5608 if (inst.base.operands[i].sysins_op == NULL)
5610 set_fatal_syntax_error ( _("unknown or missing operation name"));
5615 case AARCH64_OPND_BARRIER:
5616 case AARCH64_OPND_BARRIER_ISB:
5617 val = parse_barrier (&str);
5618 if (val != PARSE_FAIL
5619 && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf)
5621 /* ISB only accepts options name 'sy'. */
5623 (_("the specified option is not accepted in ISB"));
5624 /* Turn off backtrack as this optional operand is present. */
5628 /* This is an extension to accept a 0..15 immediate. */
5629 if (val == PARSE_FAIL)
5630 po_imm_or_fail (0, 15);
5631 info->barrier = aarch64_barrier_options + val;
5634 case AARCH64_OPND_PRFOP:
5635 val = parse_pldop (&str);
5636 /* This is an extension to accept a 0..31 immediate. */
5637 if (val == PARSE_FAIL)
5638 po_imm_or_fail (0, 31);
5639 inst.base.operands[i].prfop = aarch64_prfops + val;
5643 as_fatal (_("unhandled operand code %d"), operands[i]);
5646 /* If we get here, this operand was successfully parsed. */
5647 inst.base.operands[i].present = 1;
5651 /* The parse routine should already have set the error, but in case
5652 not, set a default one here. */
5654 set_default_error ();
5656 if (! backtrack_pos)
5657 goto parse_operands_return;
5660 /* We reach here because this operand is marked as optional, and
5661 either no operand was supplied or the operand was supplied but it
5662 was syntactically incorrect. In the latter case we report an
5663 error. In the former case we perform a few more checks before
5664 dropping through to the code to insert the default operand. */
5666 char *tmp = backtrack_pos;
5667 char endchar = END_OF_INSN;
5669 if (i != (aarch64_num_of_operands (opcode) - 1))
5671 skip_past_char (&tmp, ',');
5673 if (*tmp != endchar)
5674 /* The user has supplied an operand in the wrong format. */
5675 goto parse_operands_return;
5677 /* Make sure there is not a comma before the optional operand.
5678 For example the fifth operand of 'sys' is optional:
5680 sys #0,c0,c0,#0, <--- wrong
5681 sys #0,c0,c0,#0 <--- correct. */
5682 if (comma_skipped_p && i && endchar == END_OF_INSN)
5684 set_fatal_syntax_error
5685 (_("unexpected comma before the omitted optional operand"));
5686 goto parse_operands_return;
5690 /* Reaching here means we are dealing with an optional operand that is
5691 omitted from the assembly line. */
5692 gas_assert (optional_operand_p (opcode, i));
5694 process_omitted_operand (operands[i], opcode, i, info);
5696 /* Try again, skipping the optional operand at backtrack_pos. */
5697 str = backtrack_pos;
5700 /* Clear any error record after the omitted optional operand has been
5701 successfully handled. */
5705 /* Check if we have parsed all the operands. */
5706 if (*str != '\0' && ! error_p ())
5708 /* Set I to the index of the last present operand; this is
5709 for the purpose of diagnostics. */
5710 for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i)
5712 set_fatal_syntax_error
5713 (_("unexpected characters following instruction"));
5716 parse_operands_return:
5720 DEBUG_TRACE ("parsing FAIL: %s - %s",
5721 operand_mismatch_kind_names[get_error_kind ()],
5722 get_error_message ());
5723 /* Record the operand error properly; this is useful when there
5724 are multiple instruction templates for a mnemonic name, so that
5725 later on, we can select the error that most closely describes
5727 record_operand_error (opcode, i, get_error_kind (),
5728 get_error_message ());
5733 DEBUG_TRACE ("parsing SUCCESS");
5738 /* It does some fix-up to provide some programmer friendly feature while
5739 keeping the libopcodes happy, i.e. libopcodes only accepts
5740 the preferred architectural syntax.
5741 Return FALSE if there is any failure; otherwise return TRUE. */
5744 programmer_friendly_fixup (aarch64_instruction *instr)
5746 aarch64_inst *base = &instr->base;
5747 const aarch64_opcode *opcode = base->opcode;
5748 enum aarch64_op op = opcode->op;
5749 aarch64_opnd_info *operands = base->operands;
5751 DEBUG_TRACE ("enter");
5753 switch (opcode->iclass)
5756 /* TBNZ Xn|Wn, #uimm6, label
5757 Test and Branch Not Zero: conditionally jumps to label if bit number
5758 uimm6 in register Xn is not zero. The bit number implies the width of
5759 the register, which may be written and should be disassembled as Wn if
5760 uimm is less than 32. */
5761 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
5763 if (operands[1].imm.value >= 32)
5765 record_operand_out_of_range_error (opcode, 1, _("immediate value"),
5769 operands[0].qualifier = AARCH64_OPND_QLF_X;
5773 /* LDR Wt, label | =value
5774 As a convenience assemblers will typically permit the notation
5775 "=value" in conjunction with the pc-relative literal load instructions
5776 to automatically place an immediate value or symbolic address in a
5777 nearby literal pool and generate a hidden label which references it.
5778 ISREG has been set to 0 in the case of =value. */
5779 if (instr->gen_lit_pool
5780 && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT))
5782 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
5783 if (op == OP_LDRSW_LIT)
5785 if (instr->reloc.exp.X_op != O_constant
5786 && instr->reloc.exp.X_op != O_big
5787 && instr->reloc.exp.X_op != O_symbol)
5789 record_operand_error (opcode, 1,
5790 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
5791 _("constant expression expected"));
5794 if (! add_to_lit_pool (&instr->reloc.exp, size))
5796 record_operand_error (opcode, 1,
5797 AARCH64_OPDE_OTHER_ERROR,
5798 _("literal pool insertion failed"));
5806 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5807 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5808 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5809 A programmer-friendly assembler should accept a destination Xd in
5810 place of Wd, however that is not the preferred form for disassembly.
5812 if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW)
5813 && operands[1].qualifier == AARCH64_OPND_QLF_W
5814 && operands[0].qualifier == AARCH64_OPND_QLF_X)
5815 operands[0].qualifier = AARCH64_OPND_QLF_W;
5820 /* In the 64-bit form, the final register operand is written as Wm
5821 for all but the (possibly omitted) UXTX/LSL and SXTX
5823 As a programmer-friendly assembler, we accept e.g.
5824 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5825 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5826 int idx = aarch64_operand_index (opcode->operands,
5827 AARCH64_OPND_Rm_EXT);
5828 gas_assert (idx == 1 || idx == 2);
5829 if (operands[0].qualifier == AARCH64_OPND_QLF_X
5830 && operands[idx].qualifier == AARCH64_OPND_QLF_X
5831 && operands[idx].shifter.kind != AARCH64_MOD_LSL
5832 && operands[idx].shifter.kind != AARCH64_MOD_UXTX
5833 && operands[idx].shifter.kind != AARCH64_MOD_SXTX)
5834 operands[idx].qualifier = AARCH64_OPND_QLF_W;
5842 DEBUG_TRACE ("exit with SUCCESS");
5846 /* Check for loads and stores that will cause unpredictable behavior. */
5849 warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
5851 aarch64_inst *base = &instr->base;
5852 const aarch64_opcode *opcode = base->opcode;
5853 const aarch64_opnd_info *opnds = base->operands;
5854 switch (opcode->iclass)
5860 /* Loading/storing the base register is unpredictable if writeback. */
5861 if ((aarch64_get_operand_class (opnds[0].type)
5862 == AARCH64_OPND_CLASS_INT_REG)
5863 && opnds[0].reg.regno == opnds[1].addr.base_regno
5864 && opnds[1].addr.base_regno != REG_SP
5865 && opnds[1].addr.writeback)
5866 as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
5869 case ldstnapair_offs:
5870 case ldstpair_indexed:
5871 /* Loading/storing the base register is unpredictable if writeback. */
5872 if ((aarch64_get_operand_class (opnds[0].type)
5873 == AARCH64_OPND_CLASS_INT_REG)
5874 && (opnds[0].reg.regno == opnds[2].addr.base_regno
5875 || opnds[1].reg.regno == opnds[2].addr.base_regno)
5876 && opnds[2].addr.base_regno != REG_SP
5877 && opnds[2].addr.writeback)
5878 as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
5879 /* Load operations must load different registers. */
5880 if ((opcode->opcode & (1 << 22))
5881 && opnds[0].reg.regno == opnds[1].reg.regno)
5882 as_warn (_("unpredictable load of register pair -- `%s'"), str);
5889 /* A wrapper function to interface with libopcodes on encoding and
5890 record the error message if there is any.
5892 Return TRUE on success; otherwise return FALSE. */
5895 do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
5898 aarch64_operand_error error_info;
5899 error_info.kind = AARCH64_OPDE_NIL;
5900 if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
5904 gas_assert (error_info.kind != AARCH64_OPDE_NIL);
5905 record_operand_error_info (opcode, &error_info);
5910 #ifdef DEBUG_AARCH64
5912 dump_opcode_operands (const aarch64_opcode *opcode)
5915 while (opcode->operands[i] != AARCH64_OPND_NIL)
5917 aarch64_verbose ("\t\t opnd%d: %s", i,
5918 aarch64_get_operand_name (opcode->operands[i])[0] != '\0'
5919 ? aarch64_get_operand_name (opcode->operands[i])
5920 : aarch64_get_operand_desc (opcode->operands[i]));
5924 #endif /* DEBUG_AARCH64 */
5926 /* This is the guts of the machine-dependent assembler. STR points to a
5927 machine dependent instruction. This function is supposed to emit
5928 the frags/bytes it assembles to. */
5931 md_assemble (char *str)
5934 templates *template;
5935 aarch64_opcode *opcode;
5936 aarch64_inst *inst_base;
5937 unsigned saved_cond;
5939 /* Align the previous label if needed. */
5940 if (last_label_seen != NULL)
5942 symbol_set_frag (last_label_seen, frag_now);
5943 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
5944 S_SET_SEGMENT (last_label_seen, now_seg);
5947 inst.reloc.type = BFD_RELOC_UNUSED;
5949 DEBUG_TRACE ("\n\n");
5950 DEBUG_TRACE ("==============================");
5951 DEBUG_TRACE ("Enter md_assemble with %s", str);
5953 template = opcode_lookup (&p);
5956 /* It wasn't an instruction, but it might be a register alias of
5957 the form alias .req reg directive. */
5958 if (!create_register_alias (str, p))
5959 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
5964 skip_whitespace (p);
5967 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5968 get_mnemonic_name (str), str);
5972 init_operand_error_report ();
5974 /* Sections are assumed to start aligned. In executable section, there is no
5975 MAP_DATA symbol pending. So we only align the address during
5976 MAP_DATA --> MAP_INSN transition.
5977 For other sections, this is not guaranteed. */
5978 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
5979 if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA)
5980 frag_align_code (2, 0);
5982 saved_cond = inst.cond;
5983 reset_aarch64_instruction (&inst);
5984 inst.cond = saved_cond;
5986 /* Iterate through all opcode entries with the same mnemonic name. */
5989 opcode = template->opcode;
5991 DEBUG_TRACE ("opcode %s found", opcode->name);
5992 #ifdef DEBUG_AARCH64
5994 dump_opcode_operands (opcode);
5995 #endif /* DEBUG_AARCH64 */
5997 mapping_state (MAP_INSN);
5999 inst_base = &inst.base;
6000 inst_base->opcode = opcode;
6002 /* Truly conditionally executed instructions, e.g. b.cond. */
6003 if (opcode->flags & F_COND)
6005 gas_assert (inst.cond != COND_ALWAYS);
6006 inst_base->cond = get_cond_from_value (inst.cond);
6007 DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]);
6009 else if (inst.cond != COND_ALWAYS)
6011 /* It shouldn't arrive here, where the assembly looks like a
6012 conditional instruction but the found opcode is unconditional. */
6017 if (parse_operands (p, opcode)
6018 && programmer_friendly_fixup (&inst)
6019 && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
6021 /* Check that this instruction is supported for this CPU. */
6022 if (!opcode->avariant
6023 || !AARCH64_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
6025 as_bad (_("selected processor does not support `%s'"), str);
6029 warn_unpredictable_ldst (&inst, str);
6031 if (inst.reloc.type == BFD_RELOC_UNUSED
6032 || !inst.reloc.need_libopcodes_p)
6036 /* If there is relocation generated for the instruction,
6037 store the instruction information for the future fix-up. */
6038 struct aarch64_inst *copy;
6039 gas_assert (inst.reloc.type != BFD_RELOC_UNUSED);
6040 if ((copy = xmalloc (sizeof (struct aarch64_inst))) == NULL)
6042 memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
6048 template = template->next;
6049 if (template != NULL)
6051 reset_aarch64_instruction (&inst);
6052 inst.cond = saved_cond;
6055 while (template != NULL);
6057 /* Issue the error messages if any. */
6058 output_operand_error_report (str);
6061 /* Various frobbings of labels and their addresses. */
6064 aarch64_start_line_hook (void)
6066 last_label_seen = NULL;
6070 aarch64_frob_label (symbolS * sym)
6072 last_label_seen = sym;
6074 dwarf2_emit_label (sym);
6078 aarch64_data_in_code (void)
6080 if (!strncmp (input_line_pointer + 1, "data:", 5))
6082 *input_line_pointer = '/';
6083 input_line_pointer += 5;
6084 *input_line_pointer = 0;
6092 aarch64_canonicalize_symbol_name (char *name)
6096 if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data"))
6097 *(name + len - 5) = 0;
6102 /* Table of all register names defined by default. The user can
6103 define additional names with .req. Note that all register names
6104 should appear in both upper and lowercase variants. Some registers
6105 also have mixed-case names. */
6107 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6108 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6109 #define REGSET31(p,t) \
6110 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6111 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6112 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6113 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6114 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6115 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6116 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6117 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6118 #define REGSET(p,t) \
6119 REGSET31(p,t), REGNUM(p,31,t)
6121 /* These go into aarch64_reg_hsh hash-table. */
6122 static const reg_entry reg_names[] = {
6123 /* Integer registers. */
6124 REGSET31 (x, R_64), REGSET31 (X, R_64),
6125 REGSET31 (w, R_32), REGSET31 (W, R_32),
6127 REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
6128 REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
6130 REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
6131 REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
6133 /* Coprocessor register numbers. */
6134 REGSET (c, CN), REGSET (C, CN),
6136 /* Floating-point single precision registers. */
6137 REGSET (s, FP_S), REGSET (S, FP_S),
6139 /* Floating-point double precision registers. */
6140 REGSET (d, FP_D), REGSET (D, FP_D),
6142 /* Floating-point half precision registers. */
6143 REGSET (h, FP_H), REGSET (H, FP_H),
6145 /* Floating-point byte precision registers. */
6146 REGSET (b, FP_B), REGSET (B, FP_B),
6148 /* Floating-point quad precision registers. */
6149 REGSET (q, FP_Q), REGSET (Q, FP_Q),
6151 /* FP/SIMD registers. */
6152 REGSET (v, VN), REGSET (V, VN),
6167 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6168 static const asm_nzcv nzcv_names[] = {
6169 {"nzcv", B (n, z, c, v)},
6170 {"nzcV", B (n, z, c, V)},
6171 {"nzCv", B (n, z, C, v)},
6172 {"nzCV", B (n, z, C, V)},
6173 {"nZcv", B (n, Z, c, v)},
6174 {"nZcV", B (n, Z, c, V)},
6175 {"nZCv", B (n, Z, C, v)},
6176 {"nZCV", B (n, Z, C, V)},
6177 {"Nzcv", B (N, z, c, v)},
6178 {"NzcV", B (N, z, c, V)},
6179 {"NzCv", B (N, z, C, v)},
6180 {"NzCV", B (N, z, C, V)},
6181 {"NZcv", B (N, Z, c, v)},
6182 {"NZcV", B (N, Z, c, V)},
6183 {"NZCv", B (N, Z, C, v)},
6184 {"NZCV", B (N, Z, C, V)}
6197 /* MD interface: bits in the object file. */
6199 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6200 for use in the a.out file, and stores them in the array pointed to by buf.
6201 This knows about the endian-ness of the target machine and does
6202 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6203 2 (short) and 4 (long) Floating numbers are put out as a series of
6204 LITTLENUMS (shorts, here at least). */
6207 md_number_to_chars (char *buf, valueT val, int n)
6209 if (target_big_endian)
6210 number_to_chars_bigendian (buf, val, n);
6212 number_to_chars_littleendian (buf, val, n);
6215 /* MD interface: Sections. */
6217 /* Estimate the size of a frag before relaxing. Assume everything fits in
6221 md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED)
6227 /* Round up a section size to the appropriate boundary. */
6230 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
6235 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6236 of an rs_align_code fragment.
6238 Here we fill the frag with the appropriate info for padding the
6239 output stream. The resulting frag will consist of a fixed (fr_fix)
6240 and of a repeating (fr_var) part.
6242 The fixed content is always emitted before the repeating content and
6243 these two parts are used as follows in constructing the output:
6244 - the fixed part will be used to align to a valid instruction word
6245 boundary, in case that we start at a misaligned address; as no
6246 executable instruction can live at the misaligned location, we
6247 simply fill with zeros;
6248 - the variable part will be used to cover the remaining padding and
6249 we fill using the AArch64 NOP instruction.
6251 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6252 enough storage space for up to 3 bytes for padding the back to a valid
6253 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6256 aarch64_handle_align (fragS * fragP)
6258 /* NOP = d503201f */
6259 /* AArch64 instructions are always little-endian. */
6260 static char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6262 int bytes, fix, noop_size;
6265 if (fragP->fr_type != rs_align_code)
6268 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
6269 p = fragP->fr_literal + fragP->fr_fix;
6272 gas_assert (fragP->tc_frag_data.recorded);
6275 noop_size = sizeof (aarch64_noop);
6277 fix = bytes & (noop_size - 1);
6281 insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
6285 fragP->fr_fix += fix;
6289 memcpy (p, aarch64_noop, noop_size);
6290 fragP->fr_var = noop_size;
6293 /* Perform target specific initialisation of a frag.
6294 Note - despite the name this initialisation is not done when the frag
6295 is created, but only when its type is assigned. A frag can be created
6296 and used a long time before its type is set, so beware of assuming that
6297 this initialisationis performed first. */
6301 aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED,
6302 int max_chars ATTRIBUTE_UNUSED)
6306 #else /* OBJ_ELF is defined. */
6308 aarch64_init_frag (fragS * fragP, int max_chars)
6310 /* Record a mapping symbol for alignment frags. We will delete this
6311 later if the alignment ends up empty. */
6312 if (!fragP->tc_frag_data.recorded)
6313 fragP->tc_frag_data.recorded = 1;
6315 switch (fragP->fr_type)
6320 mapping_state_2 (MAP_DATA, max_chars);
6323 mapping_state_2 (MAP_INSN, max_chars);
6330 /* Initialize the DWARF-2 unwind information for this procedure. */
6333 tc_aarch64_frame_initial_instructions (void)
6335 cfi_add_CFA_def_cfa (REG_SP, 0);
6337 #endif /* OBJ_ELF */
6339 /* Convert REGNAME to a DWARF-2 register number. */
6342 tc_aarch64_regname_to_dw2regnum (char *regname)
6344 const reg_entry *reg = parse_reg (®name);
6350 case REG_TYPE_SP_32:
6351 case REG_TYPE_SP_64:
6361 return reg->number + 64;
6369 /* Implement DWARF2_ADDR_SIZE. */
6372 aarch64_dwarf2_addr_size (void)
6374 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6378 return bfd_arch_bits_per_address (stdoutput) / 8;
6381 /* MD interface: Symbol and relocation handling. */
6383 /* Return the address within the segment that a PC-relative fixup is
6384 relative to. For AArch64 PC-relative fixups applied to instructions
6385 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6388 md_pcrel_from_section (fixS * fixP, segT seg)
6390 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
6392 /* If this is pc-relative and we are going to emit a relocation
6393 then we just want to put out any pipeline compensation that the linker
6394 will need. Otherwise we want to use the calculated base. */
6396 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
6397 || aarch64_force_relocation (fixP)))
6400 /* AArch64 should be consistent for all pc-relative relocations. */
6401 return base + AARCH64_PCREL_OFFSET;
6404 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6405 Otherwise we have no need to default values of symbols. */
6408 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
6411 if (name[0] == '_' && name[1] == 'G'
6412 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
6416 if (symbol_find (name))
6417 as_bad (_("GOT already in the symbol table"));
6419 GOT_symbol = symbol_new (name, undefined_section,
6420 (valueT) 0, &zero_address_frag);
6430 /* Return non-zero if the indicated VALUE has overflowed the maximum
6431 range expressible by a unsigned number with the indicated number of
6435 unsigned_overflow (valueT value, unsigned bits)
6438 if (bits >= sizeof (valueT) * 8)
6440 lim = (valueT) 1 << bits;
6441 return (value >= lim);
6445 /* Return non-zero if the indicated VALUE has overflowed the maximum
6446 range expressible by an signed number with the indicated number of
6450 signed_overflow (offsetT value, unsigned bits)
6453 if (bits >= sizeof (offsetT) * 8)
6455 lim = (offsetT) 1 << (bits - 1);
6456 return (value < -lim || value >= lim);
6459 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6460 unsigned immediate offset load/store instruction, try to encode it as
6461 an unscaled, 9-bit, signed immediate offset load/store instruction.
6462 Return TRUE if it is successful; otherwise return FALSE.
6464 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6465 in response to the standard LDR/STR mnemonics when the immediate offset is
6466 unambiguous, i.e. when it is negative or unaligned. */
6469 try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
6472 enum aarch64_op new_op;
6473 const aarch64_opcode *new_opcode;
6475 gas_assert (instr->opcode->iclass == ldst_pos);
6477 switch (instr->opcode->op)
6479 case OP_LDRB_POS:new_op = OP_LDURB; break;
6480 case OP_STRB_POS: new_op = OP_STURB; break;
6481 case OP_LDRSB_POS: new_op = OP_LDURSB; break;
6482 case OP_LDRH_POS: new_op = OP_LDURH; break;
6483 case OP_STRH_POS: new_op = OP_STURH; break;
6484 case OP_LDRSH_POS: new_op = OP_LDURSH; break;
6485 case OP_LDR_POS: new_op = OP_LDUR; break;
6486 case OP_STR_POS: new_op = OP_STUR; break;
6487 case OP_LDRF_POS: new_op = OP_LDURV; break;
6488 case OP_STRF_POS: new_op = OP_STURV; break;
6489 case OP_LDRSW_POS: new_op = OP_LDURSW; break;
6490 case OP_PRFM_POS: new_op = OP_PRFUM; break;
6491 default: new_op = OP_NIL; break;
6494 if (new_op == OP_NIL)
6497 new_opcode = aarch64_get_opcode (new_op);
6498 gas_assert (new_opcode != NULL);
6500 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6501 instr->opcode->op, new_opcode->op);
6503 aarch64_replace_opcode (instr, new_opcode);
6505 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6506 qualifier matching may fail because the out-of-date qualifier will
6507 prevent the operand being updated with a new and correct qualifier. */
6508 idx = aarch64_operand_index (instr->opcode->operands,
6509 AARCH64_OPND_ADDR_SIMM9);
6510 gas_assert (idx == 1);
6511 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
6513 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6515 if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
6521 /* Called by fix_insn to fix a MOV immediate alias instruction.
6523 Operand for a generic move immediate instruction, which is an alias
6524 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6525 a 32-bit/64-bit immediate value into general register. An assembler error
6526 shall result if the immediate cannot be created by a single one of these
6527 instructions. If there is a choice, then to ensure reversability an
6528 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6531 fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
6533 const aarch64_opcode *opcode;
6535 /* Need to check if the destination is SP/ZR. The check has to be done
6536 before any aarch64_replace_opcode. */
6537 int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]);
6538 int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]);
6540 instr->operands[1].imm.value = value;
6541 instr->operands[1].skip = 0;
6545 /* Try the MOVZ alias. */
6546 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
6547 aarch64_replace_opcode (instr, opcode);
6548 if (aarch64_opcode_encode (instr->opcode, instr,
6549 &instr->value, NULL, NULL))
6551 put_aarch64_insn (buf, instr->value);
6554 /* Try the MOVK alias. */
6555 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
6556 aarch64_replace_opcode (instr, opcode);
6557 if (aarch64_opcode_encode (instr->opcode, instr,
6558 &instr->value, NULL, NULL))
6560 put_aarch64_insn (buf, instr->value);
6565 if (try_mov_bitmask_p)
6567 /* Try the ORR alias. */
6568 opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
6569 aarch64_replace_opcode (instr, opcode);
6570 if (aarch64_opcode_encode (instr->opcode, instr,
6571 &instr->value, NULL, NULL))
6573 put_aarch64_insn (buf, instr->value);
6578 as_bad_where (fixP->fx_file, fixP->fx_line,
6579 _("immediate cannot be moved by a single instruction"));
6582 /* An instruction operand which is immediate related may have symbol used
6583 in the assembly, e.g.
6586 .set u32, 0x00ffff00
6588 At the time when the assembly instruction is parsed, a referenced symbol,
6589 like 'u32' in the above example may not have been seen; a fixS is created
6590 in such a case and is handled here after symbols have been resolved.
6591 Instruction is fixed up with VALUE using the information in *FIXP plus
6592 extra information in FLAGS.
6594 This function is called by md_apply_fix to fix up instructions that need
6595 a fix-up described above but does not involve any linker-time relocation. */
6598 fix_insn (fixS *fixP, uint32_t flags, offsetT value)
6602 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6603 enum aarch64_opnd opnd = fixP->tc_fix_data.opnd;
6604 aarch64_inst *new_inst = fixP->tc_fix_data.inst;
6608 /* Now the instruction is about to be fixed-up, so the operand that
6609 was previously marked as 'ignored' needs to be unmarked in order
6610 to get the encoding done properly. */
6611 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6612 new_inst->operands[idx].skip = 0;
6615 gas_assert (opnd != AARCH64_OPND_NIL);
6619 case AARCH64_OPND_EXCEPTION:
6620 if (unsigned_overflow (value, 16))
6621 as_bad_where (fixP->fx_file, fixP->fx_line,
6622 _("immediate out of range"));
6623 insn = get_aarch64_insn (buf);
6624 insn |= encode_svc_imm (value);
6625 put_aarch64_insn (buf, insn);
6628 case AARCH64_OPND_AIMM:
6629 /* ADD or SUB with immediate.
6630 NOTE this assumes we come here with a add/sub shifted reg encoding
6631 3 322|2222|2 2 2 21111 111111
6632 1 098|7654|3 2 1 09876 543210 98765 43210
6633 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6634 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6635 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6636 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6638 3 322|2222|2 2 221111111111
6639 1 098|7654|3 2 109876543210 98765 43210
6640 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6641 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6642 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6643 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6644 Fields sf Rn Rd are already set. */
6645 insn = get_aarch64_insn (buf);
6649 insn = reencode_addsub_switch_add_sub (insn);
6653 if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0
6654 && unsigned_overflow (value, 12))
6656 /* Try to shift the value by 12 to make it fit. */
6657 if (((value >> 12) << 12) == value
6658 && ! unsigned_overflow (value, 12 + 12))
6661 insn |= encode_addsub_imm_shift_amount (1);
6665 if (unsigned_overflow (value, 12))
6666 as_bad_where (fixP->fx_file, fixP->fx_line,
6667 _("immediate out of range"));
6669 insn |= encode_addsub_imm (value);
6671 put_aarch64_insn (buf, insn);
6674 case AARCH64_OPND_SIMD_IMM:
6675 case AARCH64_OPND_SIMD_IMM_SFT:
6676 case AARCH64_OPND_LIMM:
6677 /* Bit mask immediate. */
6678 gas_assert (new_inst != NULL);
6679 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6680 new_inst->operands[idx].imm.value = value;
6681 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6682 &new_inst->value, NULL, NULL))
6683 put_aarch64_insn (buf, new_inst->value);
6685 as_bad_where (fixP->fx_file, fixP->fx_line,
6686 _("invalid immediate"));
6689 case AARCH64_OPND_HALF:
6690 /* 16-bit unsigned immediate. */
6691 if (unsigned_overflow (value, 16))
6692 as_bad_where (fixP->fx_file, fixP->fx_line,
6693 _("immediate out of range"));
6694 insn = get_aarch64_insn (buf);
6695 insn |= encode_movw_imm (value & 0xffff);
6696 put_aarch64_insn (buf, insn);
6699 case AARCH64_OPND_IMM_MOV:
6700 /* Operand for a generic move immediate instruction, which is
6701 an alias instruction that generates a single MOVZ, MOVN or ORR
6702 instruction to loads a 32-bit/64-bit immediate value into general
6703 register. An assembler error shall result if the immediate cannot be
6704 created by a single one of these instructions. If there is a choice,
6705 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6706 and MOVZ or MOVN to ORR. */
6707 gas_assert (new_inst != NULL);
6708 fix_mov_imm_insn (fixP, buf, new_inst, value);
6711 case AARCH64_OPND_ADDR_SIMM7:
6712 case AARCH64_OPND_ADDR_SIMM9:
6713 case AARCH64_OPND_ADDR_SIMM9_2:
6714 case AARCH64_OPND_ADDR_UIMM12:
6715 /* Immediate offset in an address. */
6716 insn = get_aarch64_insn (buf);
6718 gas_assert (new_inst != NULL && new_inst->value == insn);
6719 gas_assert (new_inst->opcode->operands[1] == opnd
6720 || new_inst->opcode->operands[2] == opnd);
6722 /* Get the index of the address operand. */
6723 if (new_inst->opcode->operands[1] == opnd)
6724 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6727 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6730 /* Update the resolved offset value. */
6731 new_inst->operands[idx].addr.offset.imm = value;
6733 /* Encode/fix-up. */
6734 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6735 &new_inst->value, NULL, NULL))
6737 put_aarch64_insn (buf, new_inst->value);
6740 else if (new_inst->opcode->iclass == ldst_pos
6741 && try_to_encode_as_unscaled_ldst (new_inst))
6743 put_aarch64_insn (buf, new_inst->value);
6747 as_bad_where (fixP->fx_file, fixP->fx_line,
6748 _("immediate offset out of range"));
6753 as_fatal (_("unhandled operand code %d"), opnd);
6757 /* Apply a fixup (fixP) to segment data, once it has been determined
6758 by our caller that we have all the info we need to fix it up.
6760 Parameter valP is the pointer to the value of the bits. */
6763 md_apply_fix (fixS * fixP, valueT * valP, segT seg)
6765 offsetT value = *valP;
6767 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6769 unsigned flags = fixP->fx_addnumber;
6771 DEBUG_TRACE ("\n\n");
6772 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6773 DEBUG_TRACE ("Enter md_apply_fix");
6775 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
6777 /* Note whether this will delete the relocation. */
6779 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
6782 /* Process the relocations. */
6783 switch (fixP->fx_r_type)
6785 case BFD_RELOC_NONE:
6786 /* This will need to go in the object file. */
6791 case BFD_RELOC_8_PCREL:
6792 if (fixP->fx_done || !seg->use_rela_p)
6793 md_number_to_chars (buf, value, 1);
6797 case BFD_RELOC_16_PCREL:
6798 if (fixP->fx_done || !seg->use_rela_p)
6799 md_number_to_chars (buf, value, 2);
6803 case BFD_RELOC_32_PCREL:
6804 if (fixP->fx_done || !seg->use_rela_p)
6805 md_number_to_chars (buf, value, 4);
6809 case BFD_RELOC_64_PCREL:
6810 if (fixP->fx_done || !seg->use_rela_p)
6811 md_number_to_chars (buf, value, 8);
6814 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
6815 /* We claim that these fixups have been processed here, even if
6816 in fact we generate an error because we do not have a reloc
6817 for them, so tc_gen_reloc() will reject them. */
6819 if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy))
6821 as_bad_where (fixP->fx_file, fixP->fx_line,
6822 _("undefined symbol %s used as an immediate value"),
6823 S_GET_NAME (fixP->fx_addsy));
6824 goto apply_fix_return;
6826 fix_insn (fixP, flags, value);
6829 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
6830 if (fixP->fx_done || !seg->use_rela_p)
6833 as_bad_where (fixP->fx_file, fixP->fx_line,
6834 _("pc-relative load offset not word aligned"));
6835 if (signed_overflow (value, 21))
6836 as_bad_where (fixP->fx_file, fixP->fx_line,
6837 _("pc-relative load offset out of range"));
6838 insn = get_aarch64_insn (buf);
6839 insn |= encode_ld_lit_ofs_19 (value >> 2);
6840 put_aarch64_insn (buf, insn);
6844 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
6845 if (fixP->fx_done || !seg->use_rela_p)
6847 if (signed_overflow (value, 21))
6848 as_bad_where (fixP->fx_file, fixP->fx_line,
6849 _("pc-relative address offset out of range"));
6850 insn = get_aarch64_insn (buf);
6851 insn |= encode_adr_imm (value);
6852 put_aarch64_insn (buf, insn);
6856 case BFD_RELOC_AARCH64_BRANCH19:
6857 if (fixP->fx_done || !seg->use_rela_p)
6860 as_bad_where (fixP->fx_file, fixP->fx_line,
6861 _("conditional branch target not word aligned"));
6862 if (signed_overflow (value, 21))
6863 as_bad_where (fixP->fx_file, fixP->fx_line,
6864 _("conditional branch out of range"));
6865 insn = get_aarch64_insn (buf);
6866 insn |= encode_cond_branch_ofs_19 (value >> 2);
6867 put_aarch64_insn (buf, insn);
6871 case BFD_RELOC_AARCH64_TSTBR14:
6872 if (fixP->fx_done || !seg->use_rela_p)
6875 as_bad_where (fixP->fx_file, fixP->fx_line,
6876 _("conditional branch target not word aligned"));
6877 if (signed_overflow (value, 16))
6878 as_bad_where (fixP->fx_file, fixP->fx_line,
6879 _("conditional branch out of range"));
6880 insn = get_aarch64_insn (buf);
6881 insn |= encode_tst_branch_ofs_14 (value >> 2);
6882 put_aarch64_insn (buf, insn);
6886 case BFD_RELOC_AARCH64_CALL26:
6887 case BFD_RELOC_AARCH64_JUMP26:
6888 if (fixP->fx_done || !seg->use_rela_p)
6891 as_bad_where (fixP->fx_file, fixP->fx_line,
6892 _("branch target not word aligned"));
6893 if (signed_overflow (value, 28))
6894 as_bad_where (fixP->fx_file, fixP->fx_line,
6895 _("branch out of range"));
6896 insn = get_aarch64_insn (buf);
6897 insn |= encode_branch_ofs_26 (value >> 2);
6898 put_aarch64_insn (buf, insn);
6902 case BFD_RELOC_AARCH64_MOVW_G0:
6903 case BFD_RELOC_AARCH64_MOVW_G0_NC:
6904 case BFD_RELOC_AARCH64_MOVW_G0_S:
6905 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
6908 case BFD_RELOC_AARCH64_MOVW_G1:
6909 case BFD_RELOC_AARCH64_MOVW_G1_NC:
6910 case BFD_RELOC_AARCH64_MOVW_G1_S:
6911 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
6914 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
6916 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6917 /* Should always be exported to object file, see
6918 aarch64_force_relocation(). */
6919 gas_assert (!fixP->fx_done);
6920 gas_assert (seg->use_rela_p);
6922 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
6924 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6925 /* Should always be exported to object file, see
6926 aarch64_force_relocation(). */
6927 gas_assert (!fixP->fx_done);
6928 gas_assert (seg->use_rela_p);
6930 case BFD_RELOC_AARCH64_MOVW_G2:
6931 case BFD_RELOC_AARCH64_MOVW_G2_NC:
6932 case BFD_RELOC_AARCH64_MOVW_G2_S:
6935 case BFD_RELOC_AARCH64_MOVW_G3:
6938 if (fixP->fx_done || !seg->use_rela_p)
6940 insn = get_aarch64_insn (buf);
6944 /* REL signed addend must fit in 16 bits */
6945 if (signed_overflow (value, 16))
6946 as_bad_where (fixP->fx_file, fixP->fx_line,
6947 _("offset out of range"));
6951 /* Check for overflow and scale. */
6952 switch (fixP->fx_r_type)
6954 case BFD_RELOC_AARCH64_MOVW_G0:
6955 case BFD_RELOC_AARCH64_MOVW_G1:
6956 case BFD_RELOC_AARCH64_MOVW_G2:
6957 case BFD_RELOC_AARCH64_MOVW_G3:
6958 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
6959 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
6960 if (unsigned_overflow (value, scale + 16))
6961 as_bad_where (fixP->fx_file, fixP->fx_line,
6962 _("unsigned value out of range"));
6964 case BFD_RELOC_AARCH64_MOVW_G0_S:
6965 case BFD_RELOC_AARCH64_MOVW_G1_S:
6966 case BFD_RELOC_AARCH64_MOVW_G2_S:
6967 /* NOTE: We can only come here with movz or movn. */
6968 if (signed_overflow (value, scale + 16))
6969 as_bad_where (fixP->fx_file, fixP->fx_line,
6970 _("signed value out of range"));
6973 /* Force use of MOVN. */
6975 insn = reencode_movzn_to_movn (insn);
6979 /* Force use of MOVZ. */
6980 insn = reencode_movzn_to_movz (insn);
6984 /* Unchecked relocations. */
6990 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6991 insn |= encode_movw_imm (value & 0xffff);
6993 put_aarch64_insn (buf, insn);
6997 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
6998 fixP->fx_r_type = (ilp32_p
6999 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7000 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);
7001 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7002 /* Should always be exported to object file, see
7003 aarch64_force_relocation(). */
7004 gas_assert (!fixP->fx_done);
7005 gas_assert (seg->use_rela_p);
7008 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
7009 fixP->fx_r_type = (ilp32_p
7010 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7011 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC);
7012 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7013 /* Should always be exported to object file, see
7014 aarch64_force_relocation(). */
7015 gas_assert (!fixP->fx_done);
7016 gas_assert (seg->use_rela_p);
7019 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
7020 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
7021 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
7022 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
7023 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
7024 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
7025 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
7026 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
7027 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
7028 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
7029 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
7030 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
7031 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
7032 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
7033 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
7034 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
7035 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
7036 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
7037 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
7038 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
7039 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
7040 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
7041 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
7042 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
7043 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
7044 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
7045 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
7046 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
7047 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
7048 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
7049 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
7050 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
7051 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
7052 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
7053 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
7054 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
7055 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
7056 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
7057 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
7058 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
7059 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
7060 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
7061 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
7062 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
7063 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7064 /* Should always be exported to object file, see
7065 aarch64_force_relocation(). */
7066 gas_assert (!fixP->fx_done);
7067 gas_assert (seg->use_rela_p);
7070 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
7071 /* Should always be exported to object file, see
7072 aarch64_force_relocation(). */
7073 fixP->fx_r_type = (ilp32_p
7074 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7075 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC);
7076 gas_assert (!fixP->fx_done);
7077 gas_assert (seg->use_rela_p);
7080 case BFD_RELOC_AARCH64_ADD_LO12:
7081 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
7082 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
7083 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
7084 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
7085 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
7086 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
7087 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
7088 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
7089 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
7090 case BFD_RELOC_AARCH64_LDST128_LO12:
7091 case BFD_RELOC_AARCH64_LDST16_LO12:
7092 case BFD_RELOC_AARCH64_LDST32_LO12:
7093 case BFD_RELOC_AARCH64_LDST64_LO12:
7094 case BFD_RELOC_AARCH64_LDST8_LO12:
7095 /* Should always be exported to object file, see
7096 aarch64_force_relocation(). */
7097 gas_assert (!fixP->fx_done);
7098 gas_assert (seg->use_rela_p);
7101 case BFD_RELOC_AARCH64_TLSDESC_ADD:
7102 case BFD_RELOC_AARCH64_TLSDESC_CALL:
7103 case BFD_RELOC_AARCH64_TLSDESC_LDR:
7106 case BFD_RELOC_UNUSED:
7107 /* An error will already have been reported. */
7111 as_bad_where (fixP->fx_file, fixP->fx_line,
7112 _("unexpected %s fixup"),
7113 bfd_get_reloc_code_name (fixP->fx_r_type));
7118 /* Free the allocated the struct aarch64_inst.
7119 N.B. currently there are very limited number of fix-up types actually use
7120 this field, so the impact on the performance should be minimal . */
7121 if (fixP->tc_fix_data.inst != NULL)
7122 free (fixP->tc_fix_data.inst);
7127 /* Translate internal representation of relocation info to BFD target
7131 tc_gen_reloc (asection * section, fixS * fixp)
7134 bfd_reloc_code_real_type code;
7136 reloc = xmalloc (sizeof (arelent));
7138 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
7139 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7140 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
7144 if (section->use_rela_p)
7145 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
7147 fixp->fx_offset = reloc->address;
7149 reloc->addend = fixp->fx_offset;
7151 code = fixp->fx_r_type;
7156 code = BFD_RELOC_16_PCREL;
7161 code = BFD_RELOC_32_PCREL;
7166 code = BFD_RELOC_64_PCREL;
7173 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
7174 if (reloc->howto == NULL)
7176 as_bad_where (fixp->fx_file, fixp->fx_line,
7178 ("cannot represent %s relocation in this object file format"),
7179 bfd_get_reloc_code_name (code));
7186 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7189 cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp)
7191 bfd_reloc_code_real_type type;
7195 FIXME: @@ Should look at CPU word size. */
7202 type = BFD_RELOC_16;
7205 type = BFD_RELOC_32;
7208 type = BFD_RELOC_64;
7211 as_bad (_("cannot do %u-byte relocation"), size);
7212 type = BFD_RELOC_UNUSED;
7216 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
7220 aarch64_force_relocation (struct fix *fixp)
7222 switch (fixp->fx_r_type)
7224 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
7225 /* Perform these "immediate" internal relocations
7226 even if the symbol is extern or weak. */
7229 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
7230 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
7231 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
7232 /* Pseudo relocs that need to be fixed up according to
7236 case BFD_RELOC_AARCH64_ADD_LO12:
7237 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
7238 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
7239 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
7240 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
7241 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
7242 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
7243 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
7244 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
7245 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
7246 case BFD_RELOC_AARCH64_LDST128_LO12:
7247 case BFD_RELOC_AARCH64_LDST16_LO12:
7248 case BFD_RELOC_AARCH64_LDST32_LO12:
7249 case BFD_RELOC_AARCH64_LDST64_LO12:
7250 case BFD_RELOC_AARCH64_LDST8_LO12:
7251 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
7252 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
7253 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
7254 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
7255 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
7256 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
7257 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
7258 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7259 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
7260 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
7261 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
7262 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
7263 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
7264 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
7265 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
7266 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
7267 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
7268 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
7269 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
7270 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
7271 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
7272 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
7273 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
7274 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
7275 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
7276 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
7277 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
7278 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
7279 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
7280 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
7281 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
7282 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
7283 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
7284 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
7285 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
7286 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
7287 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
7288 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
7289 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
7290 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
7291 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
7292 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
7293 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
7294 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
7295 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
7296 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
7297 /* Always leave these relocations for the linker. */
7304 return generic_force_reloc (fixp);
7310 elf64_aarch64_target_format (void)
7312 if (strcmp (TARGET_OS, "cloudabi") == 0)
7314 /* FIXME: What to do for ilp32_p ? */
7315 return target_big_endian ? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7317 if (target_big_endian)
7318 return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
7320 return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";
7324 aarch64elf_frob_symbol (symbolS * symp, int *puntp)
7326 elf_frob_symbol (symp, puntp);
7330 /* MD interface: Finalization. */
7332 /* A good place to do this, although this was probably not intended
7333 for this kind of use. We need to dump the literal pool before
7334 references are made to a null symbol pointer. */
7337 aarch64_cleanup (void)
7341 for (pool = list_of_pools; pool; pool = pool->next)
7343 /* Put it at the end of the relevant section. */
7344 subseg_set (pool->section, pool->sub_section);
7350 /* Remove any excess mapping symbols generated for alignment frags in
7351 SEC. We may have created a mapping symbol before a zero byte
7352 alignment; remove it if there's a mapping symbol after the
7355 check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec,
7356 void *dummy ATTRIBUTE_UNUSED)
7358 segment_info_type *seginfo = seg_info (sec);
7361 if (seginfo == NULL || seginfo->frchainP == NULL)
7364 for (fragp = seginfo->frchainP->frch_root;
7365 fragp != NULL; fragp = fragp->fr_next)
7367 symbolS *sym = fragp->tc_frag_data.last_map;
7368 fragS *next = fragp->fr_next;
7370 /* Variable-sized frags have been converted to fixed size by
7371 this point. But if this was variable-sized to start with,
7372 there will be a fixed-size frag after it. So don't handle
7374 if (sym == NULL || next == NULL)
7377 if (S_GET_VALUE (sym) < next->fr_address)
7378 /* Not at the end of this frag. */
7380 know (S_GET_VALUE (sym) == next->fr_address);
7384 if (next->tc_frag_data.first_map != NULL)
7386 /* Next frag starts with a mapping symbol. Discard this
7388 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
7392 if (next->fr_next == NULL)
7394 /* This mapping symbol is at the end of the section. Discard
7396 know (next->fr_fix == 0 && next->fr_var == 0);
7397 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
7401 /* As long as we have empty frags without any mapping symbols,
7403 /* If the next frag is non-empty and does not start with a
7404 mapping symbol, then this mapping symbol is required. */
7405 if (next->fr_address != next->fr_next->fr_address)
7408 next = next->fr_next;
7410 while (next != NULL);
7415 /* Adjust the symbol table. */
7418 aarch64_adjust_symtab (void)
7421 /* Remove any overlapping mapping symbols generated by alignment frags. */
7422 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
7423 /* Now do generic ELF adjustments. */
7424 elf_adjust_symtab ();
7429 checked_hash_insert (struct hash_control *table, const char *key, void *value)
7431 const char *hash_err;
7433 hash_err = hash_insert (table, key, value);
7435 printf ("Internal Error: Can't hash %s\n", key);
7439 fill_instruction_hash_table (void)
7441 aarch64_opcode *opcode = aarch64_opcode_table;
7443 while (opcode->name != NULL)
7445 templates *templ, *new_templ;
7446 templ = hash_find (aarch64_ops_hsh, opcode->name);
7448 new_templ = (templates *) xmalloc (sizeof (templates));
7449 new_templ->opcode = opcode;
7450 new_templ->next = NULL;
7453 checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ);
7456 new_templ->next = templ->next;
7457 templ->next = new_templ;
7464 convert_to_upper (char *dst, const char *src, size_t num)
7467 for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src)
7468 *dst = TOUPPER (*src);
7472 /* Assume STR point to a lower-case string, allocate, convert and return
7473 the corresponding upper-case string. */
7474 static inline const char*
7475 get_upper_str (const char *str)
7478 size_t len = strlen (str);
7479 if ((ret = xmalloc (len + 1)) == NULL)
7481 convert_to_upper (ret, str, len);
7485 /* MD interface: Initialization. */
7493 if ((aarch64_ops_hsh = hash_new ()) == NULL
7494 || (aarch64_cond_hsh = hash_new ()) == NULL
7495 || (aarch64_shift_hsh = hash_new ()) == NULL
7496 || (aarch64_sys_regs_hsh = hash_new ()) == NULL
7497 || (aarch64_pstatefield_hsh = hash_new ()) == NULL
7498 || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
7499 || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
7500 || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
7501 || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
7502 || (aarch64_reg_hsh = hash_new ()) == NULL
7503 || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
7504 || (aarch64_nzcv_hsh = hash_new ()) == NULL
7505 || (aarch64_pldop_hsh = hash_new ()) == NULL)
7506 as_fatal (_("virtual memory exhausted"));
7508 fill_instruction_hash_table ();
7510 for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
7511 checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
7512 (void *) (aarch64_sys_regs + i));
7514 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
7515 checked_hash_insert (aarch64_pstatefield_hsh,
7516 aarch64_pstatefields[i].name,
7517 (void *) (aarch64_pstatefields + i));
7519 for (i = 0; aarch64_sys_regs_ic[i].name != NULL; i++)
7520 checked_hash_insert (aarch64_sys_regs_ic_hsh,
7521 aarch64_sys_regs_ic[i].name,
7522 (void *) (aarch64_sys_regs_ic + i));
7524 for (i = 0; aarch64_sys_regs_dc[i].name != NULL; i++)
7525 checked_hash_insert (aarch64_sys_regs_dc_hsh,
7526 aarch64_sys_regs_dc[i].name,
7527 (void *) (aarch64_sys_regs_dc + i));
7529 for (i = 0; aarch64_sys_regs_at[i].name != NULL; i++)
7530 checked_hash_insert (aarch64_sys_regs_at_hsh,
7531 aarch64_sys_regs_at[i].name,
7532 (void *) (aarch64_sys_regs_at + i));
7534 for (i = 0; aarch64_sys_regs_tlbi[i].name != NULL; i++)
7535 checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
7536 aarch64_sys_regs_tlbi[i].name,
7537 (void *) (aarch64_sys_regs_tlbi + i));
7539 for (i = 0; i < ARRAY_SIZE (reg_names); i++)
7540 checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
7541 (void *) (reg_names + i));
7543 for (i = 0; i < ARRAY_SIZE (nzcv_names); i++)
7544 checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template,
7545 (void *) (nzcv_names + i));
7547 for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++)
7549 const char *name = aarch64_operand_modifiers[i].name;
7550 checked_hash_insert (aarch64_shift_hsh, name,
7551 (void *) (aarch64_operand_modifiers + i));
7552 /* Also hash the name in the upper case. */
7553 checked_hash_insert (aarch64_shift_hsh, get_upper_str (name),
7554 (void *) (aarch64_operand_modifiers + i));
7557 for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++)
7560 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7561 the same condition code. */
7562 for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j)
7564 const char *name = aarch64_conds[i].names[j];
7567 checked_hash_insert (aarch64_cond_hsh, name,
7568 (void *) (aarch64_conds + i));
7569 /* Also hash the name in the upper case. */
7570 checked_hash_insert (aarch64_cond_hsh, get_upper_str (name),
7571 (void *) (aarch64_conds + i));
7575 for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++)
7577 const char *name = aarch64_barrier_options[i].name;
7578 /* Skip xx00 - the unallocated values of option. */
7581 checked_hash_insert (aarch64_barrier_opt_hsh, name,
7582 (void *) (aarch64_barrier_options + i));
7583 /* Also hash the name in the upper case. */
7584 checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
7585 (void *) (aarch64_barrier_options + i));
7588 for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
7590 const char* name = aarch64_prfops[i].name;
7591 /* Skip the unallocated hint encodings. */
7594 checked_hash_insert (aarch64_pldop_hsh, name,
7595 (void *) (aarch64_prfops + i));
7596 /* Also hash the name in the upper case. */
7597 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
7598 (void *) (aarch64_prfops + i));
7601 /* Set the cpu variant based on the command-line options. */
7603 mcpu_cpu_opt = march_cpu_opt;
7606 mcpu_cpu_opt = &cpu_default;
7608 cpu_variant = *mcpu_cpu_opt;
7610 /* Record the CPU type. */
7611 mach = ilp32_p ? bfd_mach_aarch64_ilp32 : bfd_mach_aarch64;
7613 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
7616 /* Command line processing. */
7618 const char *md_shortopts = "m:";
7620 #ifdef AARCH64_BI_ENDIAN
7621 #define OPTION_EB (OPTION_MD_BASE + 0)
7622 #define OPTION_EL (OPTION_MD_BASE + 1)
7624 #if TARGET_BYTES_BIG_ENDIAN
7625 #define OPTION_EB (OPTION_MD_BASE + 0)
7627 #define OPTION_EL (OPTION_MD_BASE + 1)
7631 struct option md_longopts[] = {
7633 {"EB", no_argument, NULL, OPTION_EB},
7636 {"EL", no_argument, NULL, OPTION_EL},
7638 {NULL, no_argument, NULL, 0}
7641 size_t md_longopts_size = sizeof (md_longopts);
7643 struct aarch64_option_table
7645 char *option; /* Option name to match. */
7646 char *help; /* Help information. */
7647 int *var; /* Variable to change. */
7648 int value; /* What to change it to. */
7649 char *deprecated; /* If non-null, print this message. */
7652 static struct aarch64_option_table aarch64_opts[] = {
7653 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
7654 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
7656 #ifdef DEBUG_AARCH64
7657 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL},
7658 #endif /* DEBUG_AARCH64 */
7659 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1,
7661 {"mno-verbose-error", N_("do not output verbose error messages"),
7662 &verbose_error_p, 0, NULL},
7663 {NULL, NULL, NULL, 0, NULL}
7666 struct aarch64_cpu_option_table
7669 const aarch64_feature_set value;
7670 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7672 const char *canonical_name;
7675 /* This list should, at a minimum, contain all the cpu names
7676 recognized by GCC. */
7677 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
7678 {"all", AARCH64_ANY, NULL},
7679 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
7680 AARCH64_FEATURE_CRC), "Cortex-A35"},
7681 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,
7682 AARCH64_FEATURE_CRC), "Cortex-A53"},
7683 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8,
7684 AARCH64_FEATURE_CRC), "Cortex-A57"},
7685 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8,
7686 AARCH64_FEATURE_CRC), "Cortex-A72"},
7687 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
7688 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
7689 "Samsung Exynos M1"},
7690 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8,
7691 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
7692 "Qualcomm QDF24XX"},
7693 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8,
7694 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
7696 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7697 in earlier releases and is superseded by 'xgene1' in all
7699 {"xgene-1", AARCH64_ARCH_V8, "APM X-Gene 1"},
7700 {"xgene1", AARCH64_ARCH_V8, "APM X-Gene 1"},
7701 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8,
7702 AARCH64_FEATURE_CRC), "APM X-Gene 2"},
7703 {"generic", AARCH64_ARCH_V8, NULL},
7705 {NULL, AARCH64_ARCH_NONE, NULL}
7708 struct aarch64_arch_option_table
7711 const aarch64_feature_set value;
7714 /* This list should, at a minimum, contain all the architecture names
7715 recognized by GCC. */
7716 static const struct aarch64_arch_option_table aarch64_archs[] = {
7717 {"all", AARCH64_ANY},
7718 {"armv8-a", AARCH64_ARCH_V8},
7719 {"armv8.1-a", AARCH64_ARCH_V8_1},
7720 {"armv8.2-a", AARCH64_ARCH_V8_2},
7721 {NULL, AARCH64_ARCH_NONE}
7724 /* ISA extensions. */
7725 struct aarch64_option_cpu_value_table
7728 const aarch64_feature_set value;
7731 static const struct aarch64_option_cpu_value_table aarch64_features[] = {
7732 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0)},
7733 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0)},
7734 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
7735 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0)},
7736 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
7737 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0)},
7738 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0)},
7739 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
7740 | AARCH64_FEATURE_RDMA, 0)},
7741 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
7742 | AARCH64_FEATURE_FP, 0)},
7743 {NULL, AARCH64_ARCH_NONE}
7746 struct aarch64_long_option_table
7748 char *option; /* Substring to match. */
7749 char *help; /* Help information. */
7750 int (*func) (char *subopt); /* Function to decode sub-option. */
7751 char *deprecated; /* If non-null, print this message. */
7755 aarch64_parse_features (char *str, const aarch64_feature_set **opt_p,
7756 bfd_boolean ext_only)
7758 /* We insist on extensions being added before being removed. We achieve
7759 this by using the ADDING_VALUE variable to indicate whether we are
7760 adding an extension (1) or removing it (0) and only allowing it to
7761 change in the order -1 -> 1 -> 0. */
7762 int adding_value = -1;
7763 aarch64_feature_set *ext_set = xmalloc (sizeof (aarch64_feature_set));
7765 /* Copy the feature set, so that we can modify it. */
7769 while (str != NULL && *str != 0)
7771 const struct aarch64_option_cpu_value_table *opt;
7779 as_bad (_("invalid architectural extension"));
7783 ext = strchr (++str, '+');
7789 optlen = strlen (str);
7791 if (optlen >= 2 && strncmp (str, "no", 2) == 0)
7793 if (adding_value != 0)
7798 else if (optlen > 0)
7800 if (adding_value == -1)
7802 else if (adding_value != 1)
7804 as_bad (_("must specify extensions to add before specifying "
7805 "those to remove"));
7812 as_bad (_("missing architectural extension"));
7816 gas_assert (adding_value != -1);
7818 for (opt = aarch64_features; opt->name != NULL; opt++)
7819 if (strncmp (opt->name, str, optlen) == 0)
7821 /* Add or remove the extension. */
7823 AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
7825 AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
7829 if (opt->name == NULL)
7831 as_bad (_("unknown architectural extension `%s'"), str);
7842 aarch64_parse_cpu (char *str)
7844 const struct aarch64_cpu_option_table *opt;
7845 char *ext = strchr (str, '+');
7851 optlen = strlen (str);
7855 as_bad (_("missing cpu name `%s'"), str);
7859 for (opt = aarch64_cpus; opt->name != NULL; opt++)
7860 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7862 mcpu_cpu_opt = &opt->value;
7864 return aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE);
7869 as_bad (_("unknown cpu `%s'"), str);
7874 aarch64_parse_arch (char *str)
7876 const struct aarch64_arch_option_table *opt;
7877 char *ext = strchr (str, '+');
7883 optlen = strlen (str);
7887 as_bad (_("missing architecture name `%s'"), str);
7891 for (opt = aarch64_archs; opt->name != NULL; opt++)
7892 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7894 march_cpu_opt = &opt->value;
7896 return aarch64_parse_features (ext, &march_cpu_opt, FALSE);
7901 as_bad (_("unknown architecture `%s'\n"), str);
7906 struct aarch64_option_abi_value_table
7909 enum aarch64_abi_type value;
7912 static const struct aarch64_option_abi_value_table aarch64_abis[] = {
7913 {"ilp32", AARCH64_ABI_ILP32},
7914 {"lp64", AARCH64_ABI_LP64},
7919 aarch64_parse_abi (char *str)
7921 const struct aarch64_option_abi_value_table *opt;
7922 size_t optlen = strlen (str);
7926 as_bad (_("missing abi name `%s'"), str);
7930 for (opt = aarch64_abis; opt->name != NULL; opt++)
7931 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7933 aarch64_abi = opt->value;
7937 as_bad (_("unknown abi `%s'\n"), str);
7941 static struct aarch64_long_option_table aarch64_long_opts[] = {
7943 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
7944 aarch64_parse_abi, NULL},
7945 #endif /* OBJ_ELF */
7946 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7947 aarch64_parse_cpu, NULL},
7948 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7949 aarch64_parse_arch, NULL},
7950 {NULL, NULL, 0, NULL}
7954 md_parse_option (int c, char *arg)
7956 struct aarch64_option_table *opt;
7957 struct aarch64_long_option_table *lopt;
7963 target_big_endian = 1;
7969 target_big_endian = 0;
7974 /* Listing option. Just ignore these, we don't support additional
7979 for (opt = aarch64_opts; opt->option != NULL; opt++)
7981 if (c == opt->option[0]
7982 && ((arg == NULL && opt->option[1] == 0)
7983 || streq (arg, opt->option + 1)))
7985 /* If the option is deprecated, tell the user. */
7986 if (opt->deprecated != NULL)
7987 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
7988 arg ? arg : "", _(opt->deprecated));
7990 if (opt->var != NULL)
7991 *opt->var = opt->value;
7997 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
7999 /* These options are expected to have an argument. */
8000 if (c == lopt->option[0]
8002 && strncmp (arg, lopt->option + 1,
8003 strlen (lopt->option + 1)) == 0)
8005 /* If the option is deprecated, tell the user. */
8006 if (lopt->deprecated != NULL)
8007 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
8008 _(lopt->deprecated));
8010 /* Call the sup-option parser. */
8011 return lopt->func (arg + strlen (lopt->option) - 1);
8022 md_show_usage (FILE * fp)
8024 struct aarch64_option_table *opt;
8025 struct aarch64_long_option_table *lopt;
8027 fprintf (fp, _(" AArch64-specific assembler options:\n"));
8029 for (opt = aarch64_opts; opt->option != NULL; opt++)
8030 if (opt->help != NULL)
8031 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
8033 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
8034 if (lopt->help != NULL)
8035 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
8039 -EB assemble code for a big-endian cpu\n"));
8044 -EL assemble code for a little-endian cpu\n"));
8048 /* Parse a .cpu directive. */
8051 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
8053 const struct aarch64_cpu_option_table *opt;
8059 name = input_line_pointer;
8060 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8061 input_line_pointer++;
8062 saved_char = *input_line_pointer;
8063 *input_line_pointer = 0;
8065 ext = strchr (name, '+');
8068 optlen = ext - name;
8070 optlen = strlen (name);
8072 /* Skip the first "all" entry. */
8073 for (opt = aarch64_cpus + 1; opt->name != NULL; opt++)
8074 if (strlen (opt->name) == optlen
8075 && strncmp (name, opt->name, optlen) == 0)
8077 mcpu_cpu_opt = &opt->value;
8079 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
8082 cpu_variant = *mcpu_cpu_opt;
8084 *input_line_pointer = saved_char;
8085 demand_empty_rest_of_line ();
8088 as_bad (_("unknown cpu `%s'"), name);
8089 *input_line_pointer = saved_char;
8090 ignore_rest_of_line ();
8094 /* Parse a .arch directive. */
8097 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
8099 const struct aarch64_arch_option_table *opt;
8105 name = input_line_pointer;
8106 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8107 input_line_pointer++;
8108 saved_char = *input_line_pointer;
8109 *input_line_pointer = 0;
8111 ext = strchr (name, '+');
8114 optlen = ext - name;
8116 optlen = strlen (name);
8118 /* Skip the first "all" entry. */
8119 for (opt = aarch64_archs + 1; opt->name != NULL; opt++)
8120 if (strlen (opt->name) == optlen
8121 && strncmp (name, opt->name, optlen) == 0)
8123 mcpu_cpu_opt = &opt->value;
8125 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
8128 cpu_variant = *mcpu_cpu_opt;
8130 *input_line_pointer = saved_char;
8131 demand_empty_rest_of_line ();
8135 as_bad (_("unknown architecture `%s'\n"), name);
8136 *input_line_pointer = saved_char;
8137 ignore_rest_of_line ();
8140 /* Parse a .arch_extension directive. */
8143 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED)
8146 char *ext = input_line_pointer;;
8148 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8149 input_line_pointer++;
8150 saved_char = *input_line_pointer;
8151 *input_line_pointer = 0;
8153 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, TRUE))
8156 cpu_variant = *mcpu_cpu_opt;
8158 *input_line_pointer = saved_char;
8159 demand_empty_rest_of_line ();
8162 /* Copy symbol information. */
8165 aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
8167 AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);