1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the license, or
12 (at your option) any later version.
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "bfd_stdint.h"
28 #include "safe-ctype.h"
33 #include "elf/aarch64.h"
34 #include "dw2gencfi.h"
37 #include "dwarf2dbg.h"
39 /* Types of processor to assemble for. */
41 #define CPU_DEFAULT AARCH64_ARCH_V8
44 #define streq(a, b) (strcmp (a, b) == 0)
46 static aarch64_feature_set cpu_variant;
48 /* Variables that we set while parsing command-line options. Once all
49 options have been read we re-process these values to set the real
51 static const aarch64_feature_set *mcpu_cpu_opt = NULL;
52 static const aarch64_feature_set *march_cpu_opt = NULL;
54 /* Constants for known architecture features. */
55 static const aarch64_feature_set cpu_default = CPU_DEFAULT;
57 static const aarch64_feature_set aarch64_arch_any = AARCH64_ANY;
58 static const aarch64_feature_set aarch64_arch_none = AARCH64_ARCH_NONE;
61 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
62 static symbolS *GOT_symbol;
64 /* Which ABI to use. */
71 /* AArch64 ABI for the output file. */
72 static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_LP64;
74 /* When non-zero, program to a 32-bit model, in which the C data types
75 int, long and all pointer types are 32-bit objects (ILP32); or to a
76 64-bit model, in which the C int type is 32-bits but the C long type
77 and all pointer types are 64-bit objects (LP64). */
78 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
91 /* Bits for DEFINED field in neon_type_el. */
93 #define NTA_HASINDEX 2
97 enum neon_el_type type;
98 unsigned char defined;
103 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
107 bfd_reloc_code_real_type type;
110 enum aarch64_opnd opnd;
112 unsigned need_libopcodes_p : 1;
115 struct aarch64_instruction
117 /* libopcodes structure for instruction intermediate representation. */
119 /* Record assembly errors found during the parsing. */
122 enum aarch64_operand_error_kind kind;
125 /* The condition that appears in the assembly line. */
127 /* Relocation information (including the GAS internal fixup). */
129 /* Need to generate an immediate in the literal pool. */
130 unsigned gen_lit_pool : 1;
133 typedef struct aarch64_instruction aarch64_instruction;
135 static aarch64_instruction inst;
137 static bfd_boolean parse_operands (char *, const aarch64_opcode *);
138 static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
140 /* Diagnostics inline function utilites.
142 These are lightweight utlities which should only be called by parse_operands
143 and other parsers. GAS processes each assembly line by parsing it against
144 instruction template(s), in the case of multiple templates (for the same
145 mnemonic name), those templates are tried one by one until one succeeds or
146 all fail. An assembly line may fail a few templates before being
147 successfully parsed; an error saved here in most cases is not a user error
148 but an error indicating the current template is not the right template.
149 Therefore it is very important that errors can be saved at a low cost during
150 the parsing; we don't want to slow down the whole parsing by recording
151 non-user errors in detail.
153 Remember that the objective is to help GAS pick up the most approapriate
154 error message in the case of multiple templates, e.g. FMOV which has 8
160 inst.parsing_error.kind = AARCH64_OPDE_NIL;
161 inst.parsing_error.error = NULL;
164 static inline bfd_boolean
167 return inst.parsing_error.kind != AARCH64_OPDE_NIL;
170 static inline const char *
171 get_error_message (void)
173 return inst.parsing_error.error;
177 set_error_message (const char *error)
179 inst.parsing_error.error = error;
182 static inline enum aarch64_operand_error_kind
183 get_error_kind (void)
185 return inst.parsing_error.kind;
189 set_error_kind (enum aarch64_operand_error_kind kind)
191 inst.parsing_error.kind = kind;
195 set_error (enum aarch64_operand_error_kind kind, const char *error)
197 inst.parsing_error.kind = kind;
198 inst.parsing_error.error = error;
202 set_recoverable_error (const char *error)
204 set_error (AARCH64_OPDE_RECOVERABLE, error);
207 /* Use the DESC field of the corresponding aarch64_operand entry to compose
208 the error message. */
210 set_default_error (void)
212 set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
216 set_syntax_error (const char *error)
218 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
222 set_first_syntax_error (const char *error)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
229 set_fatal_syntax_error (const char *error)
231 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
234 /* Number of littlenums required to hold an extended precision number. */
235 #define MAX_LITTLENUMS 6
237 /* Return value for certain parsers when the parsing fails; those parsers
238 return the information of the parsed result, e.g. register number, on
240 #define PARSE_FAIL -1
242 /* This is an invalid condition code that means no conditional field is
244 #define COND_ALWAYS 0x10
248 const char *template;
254 const char *template;
261 bfd_reloc_code_real_type reloc;
264 /* Structure for a hash table entry for a register. */
268 unsigned char number;
270 unsigned char builtin;
273 /* Macros to define the register types and masks for the purpose
276 #undef AARCH64_REG_TYPES
277 #define AARCH64_REG_TYPES \
278 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
279 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
280 BASIC_REG_TYPE(SP_32) /* wsp */ \
281 BASIC_REG_TYPE(SP_64) /* sp */ \
282 BASIC_REG_TYPE(Z_32) /* wzr */ \
283 BASIC_REG_TYPE(Z_64) /* xzr */ \
284 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
285 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
286 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
287 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
288 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
289 BASIC_REG_TYPE(CN) /* c[0-7] */ \
290 BASIC_REG_TYPE(VN) /* v[0-31] */ \
291 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
292 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
293 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
294 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
295 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
296 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
297 /* Typecheck: any [BHSDQ]P FP. */ \
298 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
299 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
300 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
301 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
302 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
303 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
304 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
305 /* Any integer register; used for error messages only. */ \
306 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
307 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
308 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
309 /* Pseudo type to mark the end of the enumerator sequence. */ \
312 #undef BASIC_REG_TYPE
313 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
317 /* Register type enumerators. */
320 /* A list of REG_TYPE_*. */
324 #undef BASIC_REG_TYPE
325 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
327 #define REG_TYPE(T) (1 << REG_TYPE_##T)
328 #undef MULTI_REG_TYPE
329 #define MULTI_REG_TYPE(T,V) V,
331 /* Values indexed by aarch64_reg_type to assist the type checking. */
332 static const unsigned reg_type_masks[] =
337 #undef BASIC_REG_TYPE
339 #undef MULTI_REG_TYPE
340 #undef AARCH64_REG_TYPES
342 /* Diagnostics used when we don't get a register of the expected type.
343 Note: this has to synchronized with aarch64_reg_type definitions
346 get_reg_expected_msg (aarch64_reg_type reg_type)
353 msg = N_("integer 32-bit register expected");
356 msg = N_("integer 64-bit register expected");
359 msg = N_("integer register expected");
361 case REG_TYPE_R_Z_SP:
362 msg = N_("integer, zero or SP register expected");
365 msg = N_("8-bit SIMD scalar register expected");
368 msg = N_("16-bit SIMD scalar or floating-point half precision "
369 "register expected");
372 msg = N_("32-bit SIMD scalar or floating-point single precision "
373 "register expected");
376 msg = N_("64-bit SIMD scalar or floating-point double precision "
377 "register expected");
380 msg = N_("128-bit SIMD scalar or floating-point quad precision "
381 "register expected");
384 msg = N_("C0 - C15 expected");
386 case REG_TYPE_R_Z_BHSDQ_V:
387 msg = N_("register expected");
389 case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
390 msg = N_("SIMD scalar or floating-point register expected");
392 case REG_TYPE_VN: /* any V reg */
393 msg = N_("vector register expected");
396 as_fatal (_("invalid register type %d"), reg_type);
401 /* Some well known registers that we refer to directly elsewhere. */
404 /* Instructions take 4 bytes in the object file. */
407 /* Define some common error messages. */
408 #define BAD_SP _("SP not allowed here")
410 static struct hash_control *aarch64_ops_hsh;
411 static struct hash_control *aarch64_cond_hsh;
412 static struct hash_control *aarch64_shift_hsh;
413 static struct hash_control *aarch64_sys_regs_hsh;
414 static struct hash_control *aarch64_pstatefield_hsh;
415 static struct hash_control *aarch64_sys_regs_ic_hsh;
416 static struct hash_control *aarch64_sys_regs_dc_hsh;
417 static struct hash_control *aarch64_sys_regs_at_hsh;
418 static struct hash_control *aarch64_sys_regs_tlbi_hsh;
419 static struct hash_control *aarch64_reg_hsh;
420 static struct hash_control *aarch64_barrier_opt_hsh;
421 static struct hash_control *aarch64_nzcv_hsh;
422 static struct hash_control *aarch64_pldop_hsh;
424 /* Stuff needed to resolve the label ambiguity
433 static symbolS *last_label_seen;
435 /* Literal pool structure. Held on a per-section
436 and per-sub-section basis. */
438 #define MAX_LITERAL_POOL_SIZE 1024
439 typedef struct literal_pool
441 expressionS literals[MAX_LITERAL_POOL_SIZE];
442 unsigned int next_free_entry;
448 struct literal_pool *next;
451 /* Pointer to a linked list of literal pools. */
452 static literal_pool *list_of_pools = NULL;
456 /* This array holds the chars that always start a comment. If the
457 pre-processor is disabled, these aren't very useful. */
458 const char comment_chars[] = "";
460 /* This array holds the chars that only start a comment at the beginning of
461 a line. If the line seems to have the form '# 123 filename'
462 .line and .file directives will appear in the pre-processed output. */
463 /* Note that input_file.c hand checks for '#' at the beginning of the
464 first line of the input file. This is because the compiler outputs
465 #NO_APP at the beginning of its output. */
466 /* Also note that comments like this one will always work. */
467 const char line_comment_chars[] = "#";
469 const char line_separator_chars[] = ";";
471 /* Chars that can be used to separate mant
472 from exp in floating point numbers. */
473 const char EXP_CHARS[] = "eE";
475 /* Chars that mean this number is a floating point constant. */
479 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
481 /* Prefix character that indicates the start of an immediate value. */
482 #define is_immediate_prefix(C) ((C) == '#')
484 /* Separator character handling. */
486 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
488 static inline bfd_boolean
489 skip_past_char (char **str, char c)
500 #define skip_past_comma(str) skip_past_char (str, ',')
502 /* Arithmetic expressions (possibly involving symbols). */
504 static bfd_boolean in_my_get_expression_p = FALSE;
506 /* Third argument to my_get_expression. */
507 #define GE_NO_PREFIX 0
508 #define GE_OPT_PREFIX 1
510 /* Return TRUE if the string pointed by *STR is successfully parsed
511 as an valid expression; *EP will be filled with the information of
512 such an expression. Otherwise return FALSE. */
515 my_get_expression (expressionS * ep, char **str, int prefix_mode,
520 int prefix_present_p = 0;
527 if (is_immediate_prefix (**str))
530 prefix_present_p = 1;
537 memset (ep, 0, sizeof (expressionS));
539 save_in = input_line_pointer;
540 input_line_pointer = *str;
541 in_my_get_expression_p = TRUE;
542 seg = expression (ep);
543 in_my_get_expression_p = FALSE;
545 if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
547 /* We found a bad expression in md_operand(). */
548 *str = input_line_pointer;
549 input_line_pointer = save_in;
550 if (prefix_present_p && ! error_p ())
551 set_fatal_syntax_error (_("bad expression"));
553 set_first_syntax_error (_("bad expression"));
558 if (seg != absolute_section
559 && seg != text_section
560 && seg != data_section
561 && seg != bss_section && seg != undefined_section)
563 set_syntax_error (_("bad segment"));
564 *str = input_line_pointer;
565 input_line_pointer = save_in;
572 *str = input_line_pointer;
573 input_line_pointer = save_in;
577 /* Turn a string in input_line_pointer into a floating point constant
578 of type TYPE, and store the appropriate bytes in *LITP. The number
579 of LITTLENUMS emitted is stored in *SIZEP. An error message is
580 returned, or NULL on OK. */
583 md_atof (int type, char *litP, int *sizeP)
585 return ieee_md_atof (type, litP, sizeP, target_big_endian);
588 /* We handle all bad expressions here, so that we can report the faulty
589 instruction in the error message. */
591 md_operand (expressionS * exp)
593 if (in_my_get_expression_p)
594 exp->X_op = O_illegal;
597 /* Immediate values. */
599 /* Errors may be set multiple times during parsing or bit encoding
600 (particularly in the Neon bits), but usually the earliest error which is set
601 will be the most meaningful. Avoid overwriting it with later (cascading)
602 errors by calling this function. */
605 first_error (const char *error)
608 set_syntax_error (error);
611 /* Similiar to first_error, but this function accepts formatted error
614 first_error_fmt (const char *format, ...)
619 /* N.B. this single buffer will not cause error messages for different
620 instructions to pollute each other; this is because at the end of
621 processing of each assembly line, error message if any will be
622 collected by as_bad. */
623 static char buffer[size];
627 int ret ATTRIBUTE_UNUSED;
628 va_start (args, format);
629 ret = vsnprintf (buffer, size, format, args);
630 know (ret <= size - 1 && ret >= 0);
632 set_syntax_error (buffer);
636 /* Register parsing. */
638 /* Generic register parser which is called by other specialized
640 CCP points to what should be the beginning of a register name.
641 If it is indeed a valid register name, advance CCP over it and
642 return the reg_entry structure; otherwise return NULL.
643 It does not issue diagnostics. */
646 parse_reg (char **ccp)
652 #ifdef REGISTER_PREFIX
653 if (*start != REGISTER_PREFIX)
659 if (!ISALPHA (*p) || !is_name_beginner (*p))
664 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
666 reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start);
675 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
678 aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
680 if (reg->type == type)
685 case REG_TYPE_R64_SP: /* 64-bit integer reg (inc SP exc XZR). */
686 case REG_TYPE_R_Z_SP: /* Integer reg (inc {X}SP inc [WX]ZR). */
687 case REG_TYPE_R_Z_BHSDQ_V: /* Any register apart from Cn. */
688 case REG_TYPE_BHSDQ: /* Any [BHSDQ]P FP or SIMD scalar register. */
689 case REG_TYPE_VN: /* Vector register. */
690 gas_assert (reg->type < REG_TYPE_MAX && type < REG_TYPE_MAX);
691 return ((reg_type_masks[reg->type] & reg_type_masks[type])
692 == reg_type_masks[reg->type]);
694 as_fatal ("unhandled type %d", type);
699 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
700 Return the register number otherwise. *ISREG32 is set to one if the
701 register is 32-bit wide; *ISREGZERO is set to one if the register is
702 of type Z_32 or Z_64.
703 Note that this function does not issue any diagnostics. */
706 aarch64_reg_parse_32_64 (char **ccp, int reject_sp, int reject_rz,
707 int *isreg32, int *isregzero)
710 const reg_entry *reg = parse_reg (&str);
715 if (! aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP))
724 *isreg32 = reg->type == REG_TYPE_SP_32;
729 *isreg32 = reg->type == REG_TYPE_R_32;
736 *isreg32 = reg->type == REG_TYPE_Z_32;
748 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
749 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
750 otherwise return FALSE.
752 Accept only one occurrence of:
753 8b 16b 4h 8h 2s 4s 1d 2d
756 parse_neon_type_for_operand (struct neon_type_el *parsed_type, char **str)
760 unsigned element_size;
761 enum neon_el_type type;
771 width = strtoul (ptr, &ptr, 10);
772 if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
774 first_error_fmt (_("bad size %d in vector width specifier"), width);
779 switch (TOLOWER (*ptr))
807 first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
809 first_error (_("missing element size"));
812 if (width != 0 && width * element_size != 64 && width * element_size != 128)
815 ("invalid element size %d and vector size combination %c"),
821 parsed_type->type = type;
822 parsed_type->width = width;
829 /* Parse a single type, e.g. ".8b", leading period included.
830 Only applicable to Vn registers.
832 Return TRUE on success; otherwise return FALSE. */
834 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
840 if (! parse_neon_type_for_operand (vectype, &str))
842 first_error (_("vector type expected"));
854 /* Parse a register of the type TYPE.
856 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
857 name or the parsed register is not of TYPE.
859 Otherwise return the register number, and optionally fill in the actual
860 type of the register in *RTYPE when multiple alternatives were given, and
861 return the register shape and element index information in *TYPEINFO.
863 IN_REG_LIST should be set with TRUE if the caller is parsing a register
867 parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
868 struct neon_type_el *typeinfo, bfd_boolean in_reg_list)
871 const reg_entry *reg = parse_reg (&str);
872 struct neon_type_el atype;
873 struct neon_type_el parsetype;
874 bfd_boolean is_typed_vecreg = FALSE;
877 atype.type = NT_invtype;
885 set_default_error ();
889 if (! aarch64_check_reg_type (reg, type))
891 DEBUG_TRACE ("reg type check failed");
892 set_default_error ();
897 if (type == REG_TYPE_VN
898 && parse_neon_operand_type (&parsetype, &str))
900 /* Register if of the form Vn.[bhsdq]. */
901 is_typed_vecreg = TRUE;
903 if (parsetype.width == 0)
904 /* Expect index. In the new scheme we cannot have
905 Vn.[bhsdq] represent a scalar. Therefore any
906 Vn.[bhsdq] should have an index following it.
907 Except in reglists ofcourse. */
908 atype.defined |= NTA_HASINDEX;
910 atype.defined |= NTA_HASTYPE;
912 atype.type = parsetype.type;
913 atype.width = parsetype.width;
916 if (skip_past_char (&str, '['))
920 /* Reject Sn[index] syntax. */
921 if (!is_typed_vecreg)
923 first_error (_("this type of register can't be indexed"));
927 if (in_reg_list == TRUE)
929 first_error (_("index not allowed inside register list"));
933 atype.defined |= NTA_HASINDEX;
935 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
937 if (exp.X_op != O_constant)
939 first_error (_("constant expression required"));
943 if (! skip_past_char (&str, ']'))
946 atype.index = exp.X_add_number;
948 else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
950 /* Indexed vector register expected. */
951 first_error (_("indexed vector register expected"));
955 /* A vector reg Vn should be typed or indexed. */
956 if (type == REG_TYPE_VN && atype.defined == 0)
958 first_error (_("invalid use of vector register"));
974 Return the register number on success; return PARSE_FAIL otherwise.
976 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
977 the register (e.g. NEON double or quad reg when either has been requested).
979 If this is a NEON vector register with additional type information, fill
980 in the struct pointed to by VECTYPE (if non-NULL).
982 This parser does not handle register list. */
985 aarch64_reg_parse (char **ccp, aarch64_reg_type type,
986 aarch64_reg_type *rtype, struct neon_type_el *vectype)
988 struct neon_type_el atype;
990 int reg = parse_typed_reg (&str, type, rtype, &atype,
991 /*in_reg_list= */ FALSE);
993 if (reg == PARSE_FAIL)
1004 static inline bfd_boolean
1005 eq_neon_type_el (struct neon_type_el e1, struct neon_type_el e2)
1009 && e1.defined == e2.defined
1010 && e1.width == e2.width && e1.index == e2.index;
1013 /* This function parses the NEON register list. On success, it returns
1014 the parsed register list information in the following encoded format:
1016 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1017 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1019 The information of the register shape and/or index is returned in
1022 It returns PARSE_FAIL if the register list is invalid.
1024 The list contains one to four registers.
1025 Each register can be one of:
1028 All <T> should be identical.
1029 All <index> should be identical.
1030 There are restrictions on <Vt> numbers which are checked later
1031 (by reg_list_valid_p). */
1034 parse_neon_reg_list (char **ccp, struct neon_type_el *vectype)
1038 struct neon_type_el typeinfo, typeinfo_first;
1043 bfd_boolean error = FALSE;
1044 bfd_boolean expect_index = FALSE;
1048 set_syntax_error (_("expecting {"));
1054 typeinfo_first.defined = 0;
1055 typeinfo_first.type = NT_invtype;
1056 typeinfo_first.width = -1;
1057 typeinfo_first.index = 0;
1066 str++; /* skip over '-' */
1069 val = parse_typed_reg (&str, REG_TYPE_VN, NULL, &typeinfo,
1070 /*in_reg_list= */ TRUE);
1071 if (val == PARSE_FAIL)
1073 set_first_syntax_error (_("invalid vector register in list"));
1077 /* reject [bhsd]n */
1078 if (typeinfo.defined == 0)
1080 set_first_syntax_error (_("invalid scalar register in list"));
1085 if (typeinfo.defined & NTA_HASINDEX)
1086 expect_index = TRUE;
1090 if (val < val_range)
1092 set_first_syntax_error
1093 (_("invalid range in vector register list"));
1102 typeinfo_first = typeinfo;
1103 else if (! eq_neon_type_el (typeinfo_first, typeinfo))
1105 set_first_syntax_error
1106 (_("type mismatch in vector register list"));
1111 for (i = val_range; i <= val; i++)
1113 ret_val |= i << (5 * nb_regs);
1118 while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
1120 skip_whitespace (str);
1123 set_first_syntax_error (_("end of vector register list not found"));
1128 skip_whitespace (str);
1132 if (skip_past_char (&str, '['))
1136 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1137 if (exp.X_op != O_constant)
1139 set_first_syntax_error (_("constant expression required."));
1142 if (! skip_past_char (&str, ']'))
1145 typeinfo_first.index = exp.X_add_number;
1149 set_first_syntax_error (_("expected index"));
1156 set_first_syntax_error (_("too many registers in vector register list"));
1159 else if (nb_regs == 0)
1161 set_first_syntax_error (_("empty vector register list"));
1167 *vectype = typeinfo_first;
1169 return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1);
1172 /* Directives: register aliases. */
1175 insert_reg_alias (char *str, int number, aarch64_reg_type type)
1180 if ((new = hash_find (aarch64_reg_hsh, str)) != 0)
1183 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1186 /* Only warn about a redefinition if it's not defined as the
1188 else if (new->number != number || new->type != type)
1189 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1194 name = xstrdup (str);
1195 new = xmalloc (sizeof (reg_entry));
1198 new->number = number;
1200 new->builtin = FALSE;
1202 if (hash_insert (aarch64_reg_hsh, name, (void *) new))
1208 /* Look for the .req directive. This is of the form:
1210 new_register_name .req existing_register_name
1212 If we find one, or if it looks sufficiently like one that we want to
1213 handle any error here, return TRUE. Otherwise return FALSE. */
1216 create_register_alias (char *newname, char *p)
1218 const reg_entry *old;
1219 char *oldname, *nbuf;
1222 /* The input scrubber ensures that whitespace after the mnemonic is
1223 collapsed to single spaces. */
1225 if (strncmp (oldname, " .req ", 6) != 0)
1229 if (*oldname == '\0')
1232 old = hash_find (aarch64_reg_hsh, oldname);
1235 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1239 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1240 the desired alias name, and p points to its end. If not, then
1241 the desired alias name is in the global original_case_string. */
1242 #ifdef TC_CASE_SENSITIVE
1245 newname = original_case_string;
1246 nlen = strlen (newname);
1249 nbuf = alloca (nlen + 1);
1250 memcpy (nbuf, newname, nlen);
1253 /* Create aliases under the new name as stated; an all-lowercase
1254 version of the new name; and an all-uppercase version of the new
1256 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
1258 for (p = nbuf; *p; p++)
1261 if (strncmp (nbuf, newname, nlen))
1263 /* If this attempt to create an additional alias fails, do not bother
1264 trying to create the all-lower case alias. We will fail and issue
1265 a second, duplicate error message. This situation arises when the
1266 programmer does something like:
1269 The second .req creates the "Foo" alias but then fails to create
1270 the artificial FOO alias because it has already been created by the
1272 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
1276 for (p = nbuf; *p; p++)
1279 if (strncmp (nbuf, newname, nlen))
1280 insert_reg_alias (nbuf, old->number, old->type);
1286 /* Should never be called, as .req goes between the alias and the
1287 register name, not at the beginning of the line. */
1289 s_req (int a ATTRIBUTE_UNUSED)
1291 as_bad (_("invalid syntax for .req directive"));
1294 /* The .unreq directive deletes an alias which was previously defined
1295 by .req. For example:
1301 s_unreq (int a ATTRIBUTE_UNUSED)
1306 name = input_line_pointer;
1308 while (*input_line_pointer != 0
1309 && *input_line_pointer != ' ' && *input_line_pointer != '\n')
1310 ++input_line_pointer;
1312 saved_char = *input_line_pointer;
1313 *input_line_pointer = 0;
1316 as_bad (_("invalid syntax for .unreq directive"));
1319 reg_entry *reg = hash_find (aarch64_reg_hsh, name);
1322 as_bad (_("unknown register alias '%s'"), name);
1323 else if (reg->builtin)
1324 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1331 hash_delete (aarch64_reg_hsh, name, FALSE);
1332 free ((char *) reg->name);
1335 /* Also locate the all upper case and all lower case versions.
1336 Do not complain if we cannot find one or the other as it
1337 was probably deleted above. */
1339 nbuf = strdup (name);
1340 for (p = nbuf; *p; p++)
1342 reg = hash_find (aarch64_reg_hsh, nbuf);
1345 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1346 free ((char *) reg->name);
1350 for (p = nbuf; *p; p++)
1352 reg = hash_find (aarch64_reg_hsh, nbuf);
1355 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1356 free ((char *) reg->name);
1364 *input_line_pointer = saved_char;
1365 demand_empty_rest_of_line ();
1368 /* Directives: Instruction set selection. */
1371 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1372 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1373 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1374 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1376 /* Create a new mapping symbol for the transition to STATE. */
1379 make_mapping_symbol (enum mstate state, valueT value, fragS * frag)
1382 const char *symname;
1389 type = BSF_NO_FLAGS;
1393 type = BSF_NO_FLAGS;
1399 symbolP = symbol_new (symname, now_seg, value, frag);
1400 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1402 /* Save the mapping symbols for future reference. Also check that
1403 we do not place two mapping symbols at the same offset within a
1404 frag. We'll handle overlap between frags in
1405 check_mapping_symbols.
1407 If .fill or other data filling directive generates zero sized data,
1408 the mapping symbol for the following code will have the same value
1409 as the one generated for the data filling directive. In this case,
1410 we replace the old symbol with the new one at the same address. */
1413 if (frag->tc_frag_data.first_map != NULL)
1415 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
1416 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP,
1419 frag->tc_frag_data.first_map = symbolP;
1421 if (frag->tc_frag_data.last_map != NULL)
1423 know (S_GET_VALUE (frag->tc_frag_data.last_map) <=
1424 S_GET_VALUE (symbolP));
1425 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
1426 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP,
1429 frag->tc_frag_data.last_map = symbolP;
1432 /* We must sometimes convert a region marked as code to data during
1433 code alignment, if an odd number of bytes have to be padded. The
1434 code mapping symbol is pushed to an aligned address. */
1437 insert_data_mapping_symbol (enum mstate state,
1438 valueT value, fragS * frag, offsetT bytes)
1440 /* If there was already a mapping symbol, remove it. */
1441 if (frag->tc_frag_data.last_map != NULL
1442 && S_GET_VALUE (frag->tc_frag_data.last_map) ==
1443 frag->fr_address + value)
1445 symbolS *symp = frag->tc_frag_data.last_map;
1449 know (frag->tc_frag_data.first_map == symp);
1450 frag->tc_frag_data.first_map = NULL;
1452 frag->tc_frag_data.last_map = NULL;
1453 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
1456 make_mapping_symbol (MAP_DATA, value, frag);
1457 make_mapping_symbol (state, value + bytes, frag);
1460 static void mapping_state_2 (enum mstate state, int max_chars);
1462 /* Set the mapping state to STATE. Only call this when about to
1463 emit some STATE bytes to the file. */
1466 mapping_state (enum mstate state)
1468 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1470 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1472 if (mapstate == state)
1473 /* The mapping symbol has already been emitted.
1474 There is nothing else to do. */
1476 else if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
1477 /* This case will be evaluated later in the next else. */
1479 else if (TRANSITION (MAP_UNDEFINED, MAP_INSN))
1481 /* Only add the symbol if the offset is > 0:
1482 if we're at the first frag, check it's size > 0;
1483 if we're not at the first frag, then for sure
1484 the offset is > 0. */
1485 struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root;
1486 const int add_symbol = (frag_now != frag_first)
1487 || (frag_now_fix () > 0);
1490 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
1493 mapping_state_2 (state, 0);
1497 /* Same as mapping_state, but MAX_CHARS bytes have already been
1498 allocated. Put the mapping symbol that far back. */
1501 mapping_state_2 (enum mstate state, int max_chars)
1503 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1505 if (!SEG_NORMAL (now_seg))
1508 if (mapstate == state)
1509 /* The mapping symbol has already been emitted.
1510 There is nothing else to do. */
1513 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1514 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
1517 #define mapping_state(x) /* nothing */
1518 #define mapping_state_2(x, y) /* nothing */
1521 /* Directives: sectioning and alignment. */
1524 s_bss (int ignore ATTRIBUTE_UNUSED)
1526 /* We don't support putting frags in the BSS segment, we fake it by
1527 marking in_bss, then looking at s_skip for clues. */
1528 subseg_set (bss_section, 0);
1529 demand_empty_rest_of_line ();
1530 mapping_state (MAP_DATA);
1534 s_even (int ignore ATTRIBUTE_UNUSED)
1536 /* Never make frag if expect extra pass. */
1538 frag_align (1, 0, 0);
1540 record_alignment (now_seg, 1);
1542 demand_empty_rest_of_line ();
1545 /* Directives: Literal pools. */
1547 static literal_pool *
1548 find_literal_pool (int size)
1552 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1554 if (pool->section == now_seg
1555 && pool->sub_section == now_subseg && pool->size == size)
1562 static literal_pool *
1563 find_or_make_literal_pool (int size)
1565 /* Next literal pool ID number. */
1566 static unsigned int latest_pool_num = 1;
1569 pool = find_literal_pool (size);
1573 /* Create a new pool. */
1574 pool = xmalloc (sizeof (*pool));
1578 /* Currently we always put the literal pool in the current text
1579 section. If we were generating "small" model code where we
1580 knew that all code and initialised data was within 1MB then
1581 we could output literals to mergeable, read-only data
1584 pool->next_free_entry = 0;
1585 pool->section = now_seg;
1586 pool->sub_section = now_subseg;
1588 pool->next = list_of_pools;
1589 pool->symbol = NULL;
1591 /* Add it to the list. */
1592 list_of_pools = pool;
1595 /* New pools, and emptied pools, will have a NULL symbol. */
1596 if (pool->symbol == NULL)
1598 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1599 (valueT) 0, &zero_address_frag);
1600 pool->id = latest_pool_num++;
1607 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1608 Return TRUE on success, otherwise return FALSE. */
1610 add_to_lit_pool (expressionS *exp, int size)
1615 pool = find_or_make_literal_pool (size);
1617 /* Check if this literal value is already in the pool. */
1618 for (entry = 0; entry < pool->next_free_entry; entry++)
1620 if ((pool->literals[entry].X_op == exp->X_op)
1621 && (exp->X_op == O_constant)
1622 && (pool->literals[entry].X_add_number == exp->X_add_number)
1623 && (pool->literals[entry].X_unsigned == exp->X_unsigned))
1626 if ((pool->literals[entry].X_op == exp->X_op)
1627 && (exp->X_op == O_symbol)
1628 && (pool->literals[entry].X_add_number == exp->X_add_number)
1629 && (pool->literals[entry].X_add_symbol == exp->X_add_symbol)
1630 && (pool->literals[entry].X_op_symbol == exp->X_op_symbol))
1634 /* Do we need to create a new entry? */
1635 if (entry == pool->next_free_entry)
1637 if (entry >= MAX_LITERAL_POOL_SIZE)
1639 set_syntax_error (_("literal pool overflow"));
1643 pool->literals[entry] = *exp;
1644 pool->next_free_entry += 1;
1647 exp->X_op = O_symbol;
1648 exp->X_add_number = ((int) entry) * size;
1649 exp->X_add_symbol = pool->symbol;
1654 /* Can't use symbol_new here, so have to create a symbol and then at
1655 a later date assign it a value. Thats what these functions do. */
1658 symbol_locate (symbolS * symbolP,
1659 const char *name,/* It is copied, the caller can modify. */
1660 segT segment, /* Segment identifier (SEG_<something>). */
1661 valueT valu, /* Symbol value. */
1662 fragS * frag) /* Associated fragment. */
1664 unsigned int name_length;
1665 char *preserved_copy_of_name;
1667 name_length = strlen (name) + 1; /* +1 for \0. */
1668 obstack_grow (¬es, name, name_length);
1669 preserved_copy_of_name = obstack_finish (¬es);
1671 #ifdef tc_canonicalize_symbol_name
1672 preserved_copy_of_name =
1673 tc_canonicalize_symbol_name (preserved_copy_of_name);
1676 S_SET_NAME (symbolP, preserved_copy_of_name);
1678 S_SET_SEGMENT (symbolP, segment);
1679 S_SET_VALUE (symbolP, valu);
1680 symbol_clear_list_pointers (symbolP);
1682 symbol_set_frag (symbolP, frag);
1684 /* Link to end of symbol chain. */
1686 extern int symbol_table_frozen;
1688 if (symbol_table_frozen)
1692 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1694 obj_symbol_new_hook (symbolP);
1696 #ifdef tc_symbol_new_hook
1697 tc_symbol_new_hook (symbolP);
1701 verify_symbol_chain (symbol_rootP, symbol_lastP);
1702 #endif /* DEBUG_SYMS */
1707 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1714 for (align = 2; align <= 4; align++)
1716 int size = 1 << align;
1718 pool = find_literal_pool (size);
1719 if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
1722 mapping_state (MAP_DATA);
1724 /* Align pool as you have word accesses.
1725 Only make a frag if we have to. */
1727 frag_align (align, 0, 0);
1729 record_alignment (now_seg, align);
1731 sprintf (sym_name, "$$lit_\002%x", pool->id);
1733 symbol_locate (pool->symbol, sym_name, now_seg,
1734 (valueT) frag_now_fix (), frag_now);
1735 symbol_table_insert (pool->symbol);
1737 for (entry = 0; entry < pool->next_free_entry; entry++)
1738 /* First output the expression in the instruction to the pool. */
1739 emit_expr (&(pool->literals[entry]), size); /* .word|.xword */
1741 /* Mark the pool as empty. */
1742 pool->next_free_entry = 0;
1743 pool->symbol = NULL;
1748 /* Forward declarations for functions below, in the MD interface
1750 static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int);
1751 static struct reloc_table_entry * find_reloc_table_entry (char **);
1753 /* Directives: Data. */
1754 /* N.B. the support for relocation suffix in this directive needs to be
1755 implemented properly. */
1758 s_aarch64_elf_cons (int nbytes)
1762 #ifdef md_flush_pending_output
1763 md_flush_pending_output ();
1766 if (is_it_end_of_statement ())
1768 demand_empty_rest_of_line ();
1772 #ifdef md_cons_align
1773 md_cons_align (nbytes);
1776 mapping_state (MAP_DATA);
1779 struct reloc_table_entry *reloc;
1783 if (exp.X_op != O_symbol)
1784 emit_expr (&exp, (unsigned int) nbytes);
1787 skip_past_char (&input_line_pointer, '#');
1788 if (skip_past_char (&input_line_pointer, ':'))
1790 reloc = find_reloc_table_entry (&input_line_pointer);
1792 as_bad (_("unrecognized relocation suffix"));
1794 as_bad (_("unimplemented relocation suffix"));
1795 ignore_rest_of_line ();
1799 emit_expr (&exp, (unsigned int) nbytes);
1802 while (*input_line_pointer++ == ',');
1804 /* Put terminator back into stream. */
1805 input_line_pointer--;
1806 demand_empty_rest_of_line ();
1809 #endif /* OBJ_ELF */
1811 /* Output a 32-bit word, but mark as an instruction. */
1814 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
1818 #ifdef md_flush_pending_output
1819 md_flush_pending_output ();
1822 if (is_it_end_of_statement ())
1824 demand_empty_rest_of_line ();
1829 frag_align_code (2, 0);
1831 mapping_state (MAP_INSN);
1837 if (exp.X_op != O_constant)
1839 as_bad (_("constant expression required"));
1840 ignore_rest_of_line ();
1844 if (target_big_endian)
1846 unsigned int val = exp.X_add_number;
1847 exp.X_add_number = SWAP_32 (val);
1849 emit_expr (&exp, 4);
1851 while (*input_line_pointer++ == ',');
1853 /* Put terminator back into stream. */
1854 input_line_pointer--;
1855 demand_empty_rest_of_line ();
1859 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1862 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
1866 /* Since we're just labelling the code, there's no need to define a
1869 /* Make sure there is enough room in this frag for the following
1870 blr. This trick only works if the blr follows immediately after
1871 the .tlsdesc directive. */
1873 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1874 BFD_RELOC_AARCH64_TLSDESC_CALL);
1876 demand_empty_rest_of_line ();
1878 #endif /* OBJ_ELF */
1880 static void s_aarch64_arch (int);
1881 static void s_aarch64_cpu (int);
1883 /* This table describes all the machine specific pseudo-ops the assembler
1884 has to support. The fields are:
1885 pseudo-op name without dot
1886 function to call to execute this pseudo-op
1887 Integer arg to pass to the function. */
1889 const pseudo_typeS md_pseudo_table[] = {
1890 /* Never called because '.req' does not start a line. */
1892 {"unreq", s_unreq, 0},
1894 {"even", s_even, 0},
1895 {"ltorg", s_ltorg, 0},
1896 {"pool", s_ltorg, 0},
1897 {"cpu", s_aarch64_cpu, 0},
1898 {"arch", s_aarch64_arch, 0},
1899 {"inst", s_aarch64_inst, 0},
1901 {"tlsdesccall", s_tlsdesccall, 0},
1902 {"word", s_aarch64_elf_cons, 4},
1903 {"long", s_aarch64_elf_cons, 4},
1904 {"xword", s_aarch64_elf_cons, 8},
1905 {"dword", s_aarch64_elf_cons, 8},
1911 /* Check whether STR points to a register name followed by a comma or the
1912 end of line; REG_TYPE indicates which register types are checked
1913 against. Return TRUE if STR is such a register name; otherwise return
1914 FALSE. The function does not intend to produce any diagnostics, but since
1915 the register parser aarch64_reg_parse, which is called by this function,
1916 does produce diagnostics, we call clear_error to clear any diagnostics
1917 that may be generated by aarch64_reg_parse.
1918 Also, the function returns FALSE directly if there is any user error
1919 present at the function entry. This prevents the existing diagnostics
1920 state from being spoiled.
1921 The function currently serves parse_constant_immediate and
1922 parse_big_immediate only. */
1924 reg_name_p (char *str, aarch64_reg_type reg_type)
1928 /* Prevent the diagnostics state from being spoiled. */
1932 reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
1934 /* Clear the parsing error that may be set by the reg parser. */
1937 if (reg == PARSE_FAIL)
1940 skip_whitespace (str);
1941 if (*str == ',' || is_end_of_line[(unsigned int) *str])
1947 /* Parser functions used exclusively in instruction operands. */
1949 /* Parse an immediate expression which may not be constant.
1951 To prevent the expression parser from pushing a register name
1952 into the symbol table as an undefined symbol, firstly a check is
1953 done to find out whether STR is a valid register name followed
1954 by a comma or the end of line. Return FALSE if STR is such a
1958 parse_immediate_expression (char **str, expressionS *exp)
1960 if (reg_name_p (*str, REG_TYPE_R_Z_BHSDQ_V))
1962 set_recoverable_error (_("immediate operand required"));
1966 my_get_expression (exp, str, GE_OPT_PREFIX, 1);
1968 if (exp->X_op == O_absent)
1970 set_fatal_syntax_error (_("missing immediate expression"));
1977 /* Constant immediate-value read function for use in insn parsing.
1978 STR points to the beginning of the immediate (with the optional
1979 leading #); *VAL receives the value.
1981 Return TRUE on success; otherwise return FALSE. */
1984 parse_constant_immediate (char **str, int64_t * val)
1988 if (! parse_immediate_expression (str, &exp))
1991 if (exp.X_op != O_constant)
1993 set_syntax_error (_("constant expression required"));
1997 *val = exp.X_add_number;
2002 encode_imm_float_bits (uint32_t imm)
2004 return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2005 | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2008 /* Return TRUE if the single-precision floating-point value encoded in IMM
2009 can be expressed in the AArch64 8-bit signed floating-point format with
2010 3-bit exponent and normalized 4 bits of precision; in other words, the
2011 floating-point value must be expressable as
2012 (+/-) n / 16 * power (2, r)
2013 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2016 aarch64_imm_float_p (uint32_t imm)
2018 /* If a single-precision floating-point value has the following bit
2019 pattern, it can be expressed in the AArch64 8-bit floating-point
2022 3 32222222 2221111111111
2023 1 09876543 21098765432109876543210
2024 n Eeeeeexx xxxx0000000000000000000
2026 where n, e and each x are either 0 or 1 independently, with
2031 /* Prepare the pattern for 'Eeeeee'. */
2032 if (((imm >> 30) & 0x1) == 0)
2033 pattern = 0x3e000000;
2035 pattern = 0x40000000;
2037 return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */
2038 && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */
2041 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2043 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2044 8-bit signed floating-point format with 3-bit exponent and normalized 4
2045 bits of precision (i.e. can be used in an FMOV instruction); return the
2046 equivalent single-precision encoding in *FPWORD.
2048 Otherwise return FALSE. */
2051 aarch64_double_precision_fmovable (uint64_t imm, uint32_t *fpword)
2053 /* If a double-precision floating-point value has the following bit
2054 pattern, it can be expressed in the AArch64 8-bit floating-point
2057 6 66655555555 554444444...21111111111
2058 3 21098765432 109876543...098765432109876543210
2059 n Eeeeeeeeexx xxxx00000...000000000000000000000
2061 where n, e and each x are either 0 or 1 independently, with
2065 uint32_t high32 = imm >> 32;
2067 /* Lower 32 bits need to be 0s. */
2068 if ((imm & 0xffffffff) != 0)
2071 /* Prepare the pattern for 'Eeeeeeeee'. */
2072 if (((high32 >> 30) & 0x1) == 0)
2073 pattern = 0x3fc00000;
2075 pattern = 0x40000000;
2077 if ((high32 & 0xffff) == 0 /* bits 32 - 47 are 0. */
2078 && (high32 & 0x7fc00000) == pattern) /* bits 54 - 61 == ~ bit 62. */
2080 /* Convert to the single-precision encoding.
2082 n Eeeeeeeeexx xxxx00000...000000000000000000000
2084 n Eeeeeexx xxxx0000000000000000000. */
2085 *fpword = ((high32 & 0xfe000000) /* nEeeeee. */
2086 | (((high32 >> 16) & 0x3f) << 19)); /* xxxxxx. */
2093 /* Parse a floating-point immediate. Return TRUE on success and return the
2094 value in *IMMED in the format of IEEE754 single-precision encoding.
2095 *CCP points to the start of the string; DP_P is TRUE when the immediate
2096 is expected to be in double-precision (N.B. this only matters when
2097 hexadecimal representation is involved).
2099 N.B. 0.0 is accepted by this function. */
2102 parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p)
2106 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2107 int found_fpchar = 0;
2109 unsigned fpword = 0;
2110 bfd_boolean hex_p = FALSE;
2112 skip_past_char (&str, '#');
2115 skip_whitespace (fpnum);
2117 if (strncmp (fpnum, "0x", 2) == 0)
2119 /* Support the hexadecimal representation of the IEEE754 encoding.
2120 Double-precision is expected when DP_P is TRUE, otherwise the
2121 representation should be in single-precision. */
2122 if (! parse_constant_immediate (&str, &val))
2127 if (! aarch64_double_precision_fmovable (val, &fpword))
2130 else if ((uint64_t) val > 0xffffffff)
2139 /* We must not accidentally parse an integer as a floating-point number.
2140 Make sure that the value we parse is not an integer by checking for
2141 special characters '.' or 'e'. */
2142 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
2143 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
2157 if ((str = atof_ieee (str, 's', words)) == NULL)
2160 /* Our FP word must be 32 bits (single-precision FP). */
2161 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
2163 fpword <<= LITTLENUM_NUMBER_OF_BITS;
2168 if (aarch64_imm_float_p (fpword) || (fpword & 0x7fffffff) == 0)
2176 set_fatal_syntax_error (_("invalid floating-point constant"));
2180 /* Less-generic immediate-value read function with the possibility of loading
2181 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2184 To prevent the expression parser from pushing a register name into the
2185 symbol table as an undefined symbol, a check is firstly done to find
2186 out whether STR is a valid register name followed by a comma or the end
2187 of line. Return FALSE if STR is such a register. */
2190 parse_big_immediate (char **str, int64_t *imm)
2194 if (reg_name_p (ptr, REG_TYPE_R_Z_BHSDQ_V))
2196 set_syntax_error (_("immediate operand required"));
2200 my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
2202 if (inst.reloc.exp.X_op == O_constant)
2203 *imm = inst.reloc.exp.X_add_number;
2210 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2211 if NEED_LIBOPCODES is non-zero, the fixup will need
2212 assistance from the libopcodes. */
2215 aarch64_set_gas_internal_fixup (struct reloc *reloc,
2216 const aarch64_opnd_info *operand,
2217 int need_libopcodes_p)
2219 reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2220 reloc->opnd = operand->type;
2221 if (need_libopcodes_p)
2222 reloc->need_libopcodes_p = 1;
2225 /* Return TRUE if the instruction needs to be fixed up later internally by
2226 the GAS; otherwise return FALSE. */
2228 static inline bfd_boolean
2229 aarch64_gas_internal_fixup_p (void)
2231 return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2234 /* Assign the immediate value to the relavant field in *OPERAND if
2235 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2236 needs an internal fixup in a later stage.
2237 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2238 IMM.VALUE that may get assigned with the constant. */
2240 assign_imm_if_const_or_fixup_later (struct reloc *reloc,
2241 aarch64_opnd_info *operand,
2243 int need_libopcodes_p,
2246 if (reloc->exp.X_op == O_constant)
2249 operand->addr.offset.imm = reloc->exp.X_add_number;
2251 operand->imm.value = reloc->exp.X_add_number;
2252 reloc->type = BFD_RELOC_UNUSED;
2256 aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p);
2257 /* Tell libopcodes to ignore this operand or not. This is helpful
2258 when one of the operands needs to be fixed up later but we need
2259 libopcodes to check the other operands. */
2260 operand->skip = skip_p;
2264 /* Relocation modifiers. Each entry in the table contains the textual
2265 name for the relocation which may be placed before a symbol used as
2266 a load/store offset, or add immediate. It must be surrounded by a
2267 leading and trailing colon, for example:
2269 ldr x0, [x1, #:rello:varsym]
2270 add x0, x1, #:rello:varsym */
2272 struct reloc_table_entry
2276 bfd_reloc_code_real_type adrp_type;
2277 bfd_reloc_code_real_type movw_type;
2278 bfd_reloc_code_real_type add_type;
2279 bfd_reloc_code_real_type ldst_type;
2282 static struct reloc_table_entry reloc_table[] = {
2283 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2287 BFD_RELOC_AARCH64_ADD_LO12,
2288 BFD_RELOC_AARCH64_LDST_LO12},
2290 /* Higher 21 bits of pc-relative page offset: ADRP */
2292 BFD_RELOC_AARCH64_ADR_HI21_PCREL,
2297 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2299 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
2304 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2307 BFD_RELOC_AARCH64_MOVW_G0,
2311 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2314 BFD_RELOC_AARCH64_MOVW_G0_S,
2318 /* Less significant bits 0-15 of address/value: MOVK, no check */
2321 BFD_RELOC_AARCH64_MOVW_G0_NC,
2325 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2328 BFD_RELOC_AARCH64_MOVW_G1,
2332 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2335 BFD_RELOC_AARCH64_MOVW_G1_S,
2339 /* Less significant bits 16-31 of address/value: MOVK, no check */
2342 BFD_RELOC_AARCH64_MOVW_G1_NC,
2346 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2349 BFD_RELOC_AARCH64_MOVW_G2,
2353 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2356 BFD_RELOC_AARCH64_MOVW_G2_S,
2360 /* Less significant bits 32-47 of address/value: MOVK, no check */
2363 BFD_RELOC_AARCH64_MOVW_G2_NC,
2367 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2370 BFD_RELOC_AARCH64_MOVW_G3,
2374 /* Get to the page containing GOT entry for a symbol. */
2376 BFD_RELOC_AARCH64_ADR_GOT_PAGE,
2379 BFD_RELOC_AARCH64_GOT_LD_PREL19},
2381 /* 12 bit offset into the page containing GOT entry for that symbol. */
2386 BFD_RELOC_AARCH64_LD_GOT_LO12_NC},
2388 /* Get to the page containing GOT TLS entry for a symbol */
2390 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
2395 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2399 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
2402 /* Get to the page containing GOT TLS entry for a symbol */
2404 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21,
2409 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2413 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
2414 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC},
2416 /* Get to the page containing GOT TLS entry for a symbol */
2418 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
2423 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2424 {"gottprel_lo12", 0,
2428 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC},
2430 /* Get tp offset for a symbol. */
2434 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2437 /* Get tp offset for a symbol. */
2441 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2444 /* Get tp offset for a symbol. */
2448 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
2451 /* Get tp offset for a symbol. */
2452 {"tprel_lo12_nc", 0,
2455 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
2458 /* Most significant bits 32-47 of address/value: MOVZ. */
2461 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
2465 /* Most significant bits 16-31 of address/value: MOVZ. */
2468 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
2472 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2475 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
2479 /* Most significant bits 0-15 of address/value: MOVZ. */
2482 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
2486 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2489 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
2494 /* Given the address of a pointer pointing to the textual name of a
2495 relocation as may appear in assembler source, attempt to find its
2496 details in reloc_table. The pointer will be updated to the character
2497 after the trailing colon. On failure, NULL will be returned;
2498 otherwise return the reloc_table_entry. */
2500 static struct reloc_table_entry *
2501 find_reloc_table_entry (char **str)
2504 for (i = 0; i < ARRAY_SIZE (reloc_table); i++)
2506 int length = strlen (reloc_table[i].name);
2508 if (strncasecmp (reloc_table[i].name, *str, length) == 0
2509 && (*str)[length] == ':')
2511 *str += (length + 1);
2512 return &reloc_table[i];
2519 /* Mode argument to parse_shift and parser_shifter_operand. */
2520 enum parse_shift_mode
2522 SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2524 SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2526 SHIFTED_LSL, /* bare "lsl #n" */
2527 SHIFTED_LSL_MSL, /* "lsl|msl #n" */
2528 SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */
2531 /* Parse a <shift> operator on an AArch64 data processing instruction.
2532 Return TRUE on success; otherwise return FALSE. */
2534 parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
2536 const struct aarch64_name_value_pair *shift_op;
2537 enum aarch64_modifier_kind kind;
2543 for (p = *str; ISALPHA (*p); p++)
2548 set_syntax_error (_("shift expression expected"));
2552 shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str);
2554 if (shift_op == NULL)
2556 set_syntax_error (_("shift operator expected"));
2560 kind = aarch64_get_operand_modifier (shift_op);
2562 if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
2564 set_syntax_error (_("invalid use of 'MSL'"));
2570 case SHIFTED_LOGIC_IMM:
2571 if (aarch64_extend_operator_p (kind) == TRUE)
2573 set_syntax_error (_("extending shift is not permitted"));
2578 case SHIFTED_ARITH_IMM:
2579 if (kind == AARCH64_MOD_ROR)
2581 set_syntax_error (_("'ROR' shift is not permitted"));
2587 if (kind != AARCH64_MOD_LSL)
2589 set_syntax_error (_("only 'LSL' shift is permitted"));
2594 case SHIFTED_REG_OFFSET:
2595 if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
2596 && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX)
2598 set_fatal_syntax_error
2599 (_("invalid shift for the register offset addressing mode"));
2604 case SHIFTED_LSL_MSL:
2605 if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
2607 set_syntax_error (_("invalid shift operator"));
2616 /* Whitespace can appear here if the next thing is a bare digit. */
2617 skip_whitespace (p);
2619 /* Parse shift amount. */
2621 if (mode == SHIFTED_REG_OFFSET && *p == ']')
2622 exp.X_op = O_absent;
2625 if (is_immediate_prefix (*p))
2630 my_get_expression (&exp, &p, GE_NO_PREFIX, 0);
2632 if (exp.X_op == O_absent)
2634 if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
2636 set_syntax_error (_("missing shift amount"));
2639 operand->shifter.amount = 0;
2641 else if (exp.X_op != O_constant)
2643 set_syntax_error (_("constant shift amount required"));
2646 else if (exp.X_add_number < 0 || exp.X_add_number > 63)
2648 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2653 operand->shifter.amount = exp.X_add_number;
2654 operand->shifter.amount_present = 1;
2657 operand->shifter.operator_present = 1;
2658 operand->shifter.kind = kind;
2664 /* Parse a <shifter_operand> for a data processing instruction:
2667 #<immediate>, LSL #imm
2669 Validation of immediate operands is deferred to md_apply_fix.
2671 Return TRUE on success; otherwise return FALSE. */
2674 parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
2675 enum parse_shift_mode mode)
2679 if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
2684 /* Accept an immediate expression. */
2685 if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
2688 /* Accept optional LSL for arithmetic immediate values. */
2689 if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
2690 if (! parse_shift (&p, operand, SHIFTED_LSL))
2693 /* Not accept any shifter for logical immediate values. */
2694 if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
2695 && parse_shift (&p, operand, mode))
2697 set_syntax_error (_("unexpected shift operator"));
2705 /* Parse a <shifter_operand> for a data processing instruction:
2710 #<immediate>, LSL #imm
2712 where <shift> is handled by parse_shift above, and the last two
2713 cases are handled by the function above.
2715 Validation of immediate operands is deferred to md_apply_fix.
2717 Return TRUE on success; otherwise return FALSE. */
2720 parse_shifter_operand (char **str, aarch64_opnd_info *operand,
2721 enum parse_shift_mode mode)
2724 int isreg32, isregzero;
2725 enum aarch64_operand_class opd_class
2726 = aarch64_get_operand_class (operand->type);
2729 aarch64_reg_parse_32_64 (str, 0, 0, &isreg32, &isregzero)) != PARSE_FAIL)
2731 if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
2733 set_syntax_error (_("unexpected register in the immediate operand"));
2737 if (!isregzero && reg == REG_SP)
2739 set_syntax_error (BAD_SP);
2743 operand->reg.regno = reg;
2744 operand->qualifier = isreg32 ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
2746 /* Accept optional shift operation on register. */
2747 if (! skip_past_comma (str))
2750 if (! parse_shift (str, operand, mode))
2755 else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
2758 (_("integer register expected in the extended/shifted operand "
2763 /* We have a shifted immediate variable. */
2764 return parse_shifter_operand_imm (str, operand, mode);
2767 /* Return TRUE on success; return FALSE otherwise. */
2770 parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
2771 enum parse_shift_mode mode)
2775 /* Determine if we have the sequence of characters #: or just :
2776 coming next. If we do, then we check for a :rello: relocation
2777 modifier. If we don't, punt the whole lot to
2778 parse_shifter_operand. */
2780 if ((p[0] == '#' && p[1] == ':') || p[0] == ':')
2782 struct reloc_table_entry *entry;
2790 /* Try to parse a relocation. Anything else is an error. */
2791 if (!(entry = find_reloc_table_entry (str)))
2793 set_syntax_error (_("unknown relocation modifier"));
2797 if (entry->add_type == 0)
2800 (_("this relocation modifier is not allowed on this instruction"));
2804 /* Save str before we decompose it. */
2807 /* Next, we parse the expression. */
2808 if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
2811 /* Record the relocation type (use the ADD variant here). */
2812 inst.reloc.type = entry->add_type;
2813 inst.reloc.pc_rel = entry->pc_rel;
2815 /* If str is empty, we've reached the end, stop here. */
2819 /* Otherwise, we have a shifted reloc modifier, so rewind to
2820 recover the variable name and continue parsing for the shifter. */
2822 return parse_shifter_operand_imm (str, operand, mode);
2825 return parse_shifter_operand (str, operand, mode);
2828 /* Parse all forms of an address expression. Information is written
2829 to *OPERAND and/or inst.reloc.
2831 The A64 instruction set has the following addressing modes:
2834 [base] // in SIMD ld/st structure
2835 [base{,#0}] // in ld/st exclusive
2837 [base,Xm{,LSL #imm}]
2838 [base,Xm,SXTX {#imm}]
2839 [base,Wm,(S|U)XTW {#imm}]
2844 [base],Xm // in SIMD ld/st structure
2845 PC-relative (literal)
2849 (As a convenience, the notation "=immediate" is permitted in conjunction
2850 with the pc-relative literal load instructions to automatically place an
2851 immediate value or symbolic address in a nearby literal pool and generate
2852 a hidden label which references it.)
2854 Upon a successful parsing, the address structure in *OPERAND will be
2855 filled in the following way:
2857 .base_regno = <base>
2858 .offset.is_reg // 1 if the offset is a register
2860 .offset.regno = <Rm>
2862 For different addressing modes defined in the A64 ISA:
2865 .pcrel=0; .preind=1; .postind=0; .writeback=0
2867 .pcrel=0; .preind=1; .postind=0; .writeback=1
2869 .pcrel=0; .preind=0; .postind=1; .writeback=1
2870 PC-relative (literal)
2871 .pcrel=1; .preind=1; .postind=0; .writeback=0
2873 The shift/extension information, if any, will be stored in .shifter.
2875 It is the caller's responsibility to check for addressing modes not
2876 supported by the instruction, and to set inst.reloc.type. */
2879 parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
2880 int accept_reg_post_index)
2884 int isreg32, isregzero;
2885 expressionS *exp = &inst.reloc.exp;
2887 if (! skip_past_char (&p, '['))
2889 /* =immediate or label. */
2890 operand->addr.pcrel = 1;
2891 operand->addr.preind = 1;
2893 /* #:<reloc_op>:<symbol> */
2894 skip_past_char (&p, '#');
2895 if (reloc && skip_past_char (&p, ':'))
2897 struct reloc_table_entry *entry;
2899 /* Try to parse a relocation modifier. Anything else is
2901 entry = find_reloc_table_entry (&p);
2904 set_syntax_error (_("unknown relocation modifier"));
2908 if (entry->ldst_type == 0)
2911 (_("this relocation modifier is not allowed on this "
2917 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
2919 set_syntax_error (_("invalid relocation expression"));
2923 /* #:<reloc_op>:<expr> */
2924 /* Record the load/store relocation type. */
2925 inst.reloc.type = entry->ldst_type;
2926 inst.reloc.pc_rel = entry->pc_rel;
2931 if (skip_past_char (&p, '='))
2932 /* =immediate; need to generate the literal in the literal pool. */
2933 inst.gen_lit_pool = 1;
2935 if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1))
2937 set_syntax_error (_("invalid address"));
2948 /* Accept SP and reject ZR */
2949 reg = aarch64_reg_parse_32_64 (&p, 0, 1, &isreg32, &isregzero);
2950 if (reg == PARSE_FAIL || isreg32)
2952 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
2955 operand->addr.base_regno = reg;
2958 if (skip_past_comma (&p))
2961 operand->addr.preind = 1;
2963 /* Reject SP and accept ZR */
2964 reg = aarch64_reg_parse_32_64 (&p, 1, 0, &isreg32, &isregzero);
2965 if (reg != PARSE_FAIL)
2968 operand->addr.offset.regno = reg;
2969 operand->addr.offset.is_reg = 1;
2970 /* Shifted index. */
2971 if (skip_past_comma (&p))
2974 if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
2975 /* Use the diagnostics set in parse_shift, so not set new
2976 error message here. */
2980 [base,Xm{,LSL #imm}]
2981 [base,Xm,SXTX {#imm}]
2982 [base,Wm,(S|U)XTW {#imm}] */
2983 if (operand->shifter.kind == AARCH64_MOD_NONE
2984 || operand->shifter.kind == AARCH64_MOD_LSL
2985 || operand->shifter.kind == AARCH64_MOD_SXTX)
2989 set_syntax_error (_("invalid use of 32-bit register offset"));
2995 set_syntax_error (_("invalid use of 64-bit register offset"));
3001 /* [Xn,#:<reloc_op>:<symbol> */
3002 skip_past_char (&p, '#');
3003 if (reloc && skip_past_char (&p, ':'))
3005 struct reloc_table_entry *entry;
3007 /* Try to parse a relocation modifier. Anything else is
3009 if (!(entry = find_reloc_table_entry (&p)))
3011 set_syntax_error (_("unknown relocation modifier"));
3015 if (entry->ldst_type == 0)
3018 (_("this relocation modifier is not allowed on this "
3023 /* [Xn,#:<reloc_op>: */
3024 /* We now have the group relocation table entry corresponding to
3025 the name in the assembler source. Next, we parse the
3027 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3029 set_syntax_error (_("invalid relocation expression"));
3033 /* [Xn,#:<reloc_op>:<expr> */
3034 /* Record the load/store relocation type. */
3035 inst.reloc.type = entry->ldst_type;
3036 inst.reloc.pc_rel = entry->pc_rel;
3038 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3040 set_syntax_error (_("invalid expression in the address"));
3047 if (! skip_past_char (&p, ']'))
3049 set_syntax_error (_("']' expected"));
3053 if (skip_past_char (&p, '!'))
3055 if (operand->addr.preind && operand->addr.offset.is_reg)
3057 set_syntax_error (_("register offset not allowed in pre-indexed "
3058 "addressing mode"));
3062 operand->addr.writeback = 1;
3064 else if (skip_past_comma (&p))
3067 operand->addr.postind = 1;
3068 operand->addr.writeback = 1;
3070 if (operand->addr.preind)
3072 set_syntax_error (_("cannot combine pre- and post-indexing"));
3076 if (accept_reg_post_index
3077 && (reg = aarch64_reg_parse_32_64 (&p, 1, 1, &isreg32,
3078 &isregzero)) != PARSE_FAIL)
3083 set_syntax_error (_("invalid 32-bit register offset"));
3086 operand->addr.offset.regno = reg;
3087 operand->addr.offset.is_reg = 1;
3089 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3092 set_syntax_error (_("invalid expression in the address"));
3097 /* If at this point neither .preind nor .postind is set, we have a
3098 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3099 if (operand->addr.preind == 0 && operand->addr.postind == 0)
3101 if (operand->addr.writeback)
3104 set_syntax_error (_("missing offset in the pre-indexed address"));
3107 operand->addr.preind = 1;
3108 inst.reloc.exp.X_op = O_constant;
3109 inst.reloc.exp.X_add_number = 0;
3116 /* Return TRUE on success; otherwise return FALSE. */
3118 parse_address (char **str, aarch64_opnd_info *operand,
3119 int accept_reg_post_index)
3121 return parse_address_main (str, operand, 0, accept_reg_post_index);
3124 /* Return TRUE on success; otherwise return FALSE. */
3126 parse_address_reloc (char **str, aarch64_opnd_info *operand)
3128 return parse_address_main (str, operand, 1, 0);
3131 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3132 Return TRUE on success; otherwise return FALSE. */
3134 parse_half (char **str, int *internal_fixup_p)
3140 skip_past_char (&p, '#');
3142 gas_assert (internal_fixup_p);
3143 *internal_fixup_p = 0;
3147 struct reloc_table_entry *entry;
3149 /* Try to parse a relocation. Anything else is an error. */
3151 if (!(entry = find_reloc_table_entry (&p)))
3153 set_syntax_error (_("unknown relocation modifier"));
3157 if (entry->movw_type == 0)
3160 (_("this relocation modifier is not allowed on this instruction"));
3164 inst.reloc.type = entry->movw_type;
3167 *internal_fixup_p = 1;
3169 /* Avoid parsing a register as a general symbol. */
3171 if (aarch64_reg_parse_32_64 (&p, 0, 0, &dummy, &dummy) != PARSE_FAIL)
3175 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3182 /* Parse an operand for an ADRP instruction:
3184 Return TRUE on success; otherwise return FALSE. */
3187 parse_adrp (char **str)
3194 struct reloc_table_entry *entry;
3196 /* Try to parse a relocation. Anything else is an error. */
3198 if (!(entry = find_reloc_table_entry (&p)))
3200 set_syntax_error (_("unknown relocation modifier"));
3204 if (entry->adrp_type == 0)
3207 (_("this relocation modifier is not allowed on this instruction"));
3211 inst.reloc.type = entry->adrp_type;
3214 inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
3216 inst.reloc.pc_rel = 1;
3218 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3225 /* Miscellaneous. */
3227 /* Parse an option for a preload instruction. Returns the encoding for the
3228 option, or PARSE_FAIL. */
3231 parse_pldop (char **str)
3234 const struct aarch64_name_value_pair *o;
3237 while (ISALNUM (*q))
3240 o = hash_find_n (aarch64_pldop_hsh, p, q - p);
3248 /* Parse an option for a barrier instruction. Returns the encoding for the
3249 option, or PARSE_FAIL. */
3252 parse_barrier (char **str)
3255 const asm_barrier_opt *o;
3258 while (ISALPHA (*q))
3261 o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p);
3269 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3270 Returns the encoding for the option, or PARSE_FAIL.
3272 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3273 implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
3276 parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
3280 const aarch64_sys_reg *o;
3284 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3286 *p++ = TOLOWER (*q);
3288 /* Assert that BUF be large enough. */
3289 gas_assert (p - buf == q - *str);
3291 o = hash_find (sys_regs, buf);
3294 if (!imple_defined_p)
3298 /* Parse S3_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
3300 unsigned int op0, op1, cn, cm, op2;
3301 if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
3303 /* The architecture specifies the encoding space for implementation
3304 defined registers as:
3306 11 xxx 1x11 xxxx xxx
3307 For convenience GAS accepts a wider encoding space, as follows:
3309 11 xxx xxxx xxxx xxx */
3310 if (op0 != 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
3312 value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
3317 if (aarch64_sys_reg_deprecated_p (o))
3318 as_warn (_("system register name '%s' is deprecated and may be "
3319 "removed in a future release"), buf);
3327 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3328 for the option, or NULL. */
3330 static const aarch64_sys_ins_reg *
3331 parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
3335 const aarch64_sys_ins_reg *o;
3338 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3340 *p++ = TOLOWER (*q);
3343 o = hash_find (sys_ins_regs, buf);
3351 #define po_char_or_fail(chr) do { \
3352 if (! skip_past_char (&str, chr)) \
3356 #define po_reg_or_fail(regtype) do { \
3357 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3358 if (val == PARSE_FAIL) \
3360 set_default_error (); \
3365 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3366 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3367 &isreg32, &isregzero); \
3368 if (val == PARSE_FAIL) \
3370 set_default_error (); \
3373 info->reg.regno = val; \
3375 info->qualifier = AARCH64_OPND_QLF_W; \
3377 info->qualifier = AARCH64_OPND_QLF_X; \
3380 #define po_imm_nc_or_fail() do { \
3381 if (! parse_constant_immediate (&str, &val)) \
3385 #define po_imm_or_fail(min, max) do { \
3386 if (! parse_constant_immediate (&str, &val)) \
3388 if (val < min || val > max) \
3390 set_fatal_syntax_error (_("immediate value out of range "\
3391 #min " to "#max)); \
3396 #define po_misc_or_fail(expr) do { \
3401 /* encode the 12-bit imm field of Add/sub immediate */
3402 static inline uint32_t
3403 encode_addsub_imm (uint32_t imm)
3408 /* encode the shift amount field of Add/sub immediate */
3409 static inline uint32_t
3410 encode_addsub_imm_shift_amount (uint32_t cnt)
3416 /* encode the imm field of Adr instruction */
3417 static inline uint32_t
3418 encode_adr_imm (uint32_t imm)
3420 return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */
3421 | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3424 /* encode the immediate field of Move wide immediate */
3425 static inline uint32_t
3426 encode_movw_imm (uint32_t imm)
3431 /* encode the 26-bit offset of unconditional branch */
3432 static inline uint32_t
3433 encode_branch_ofs_26 (uint32_t ofs)
3435 return ofs & ((1 << 26) - 1);
3438 /* encode the 19-bit offset of conditional branch and compare & branch */
3439 static inline uint32_t
3440 encode_cond_branch_ofs_19 (uint32_t ofs)
3442 return (ofs & ((1 << 19) - 1)) << 5;
3445 /* encode the 19-bit offset of ld literal */
3446 static inline uint32_t
3447 encode_ld_lit_ofs_19 (uint32_t ofs)
3449 return (ofs & ((1 << 19) - 1)) << 5;
3452 /* Encode the 14-bit offset of test & branch. */
3453 static inline uint32_t
3454 encode_tst_branch_ofs_14 (uint32_t ofs)
3456 return (ofs & ((1 << 14) - 1)) << 5;
3459 /* Encode the 16-bit imm field of svc/hvc/smc. */
3460 static inline uint32_t
3461 encode_svc_imm (uint32_t imm)
3466 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3467 static inline uint32_t
3468 reencode_addsub_switch_add_sub (uint32_t opcode)
3470 return opcode ^ (1 << 30);
3473 static inline uint32_t
3474 reencode_movzn_to_movz (uint32_t opcode)
3476 return opcode | (1 << 30);
3479 static inline uint32_t
3480 reencode_movzn_to_movn (uint32_t opcode)
3482 return opcode & ~(1 << 30);
3485 /* Overall per-instruction processing. */
3487 /* We need to be able to fix up arbitrary expressions in some statements.
3488 This is so that we can handle symbols that are an arbitrary distance from
3489 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3490 which returns part of an address in a form which will be valid for
3491 a data instruction. We do this by pushing the expression into a symbol
3492 in the expr_section, and creating a fix for that. */
3495 fix_new_aarch64 (fragS * frag,
3497 short int size, expressionS * exp, int pc_rel, int reloc)
3507 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
3511 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
3518 /* Diagnostics on operands errors. */
3520 /* By default, output one-line error message only.
3521 Enable the verbose error message by -merror-verbose. */
3522 static int verbose_error_p = 0;
3524 #ifdef DEBUG_AARCH64
3525 /* N.B. this is only for the purpose of debugging. */
3526 const char* operand_mismatch_kind_names[] =
3529 "AARCH64_OPDE_RECOVERABLE",
3530 "AARCH64_OPDE_SYNTAX_ERROR",
3531 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3532 "AARCH64_OPDE_INVALID_VARIANT",
3533 "AARCH64_OPDE_OUT_OF_RANGE",
3534 "AARCH64_OPDE_UNALIGNED",
3535 "AARCH64_OPDE_REG_LIST",
3536 "AARCH64_OPDE_OTHER_ERROR",
3538 #endif /* DEBUG_AARCH64 */
3540 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3542 When multiple errors of different kinds are found in the same assembly
3543 line, only the error of the highest severity will be picked up for
3544 issuing the diagnostics. */
3546 static inline bfd_boolean
3547 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
3548 enum aarch64_operand_error_kind rhs)
3550 gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL);
3551 gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE);
3552 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
3553 gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
3554 gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
3555 gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
3556 gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
3557 gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
3561 /* Helper routine to get the mnemonic name from the assembly instruction
3562 line; should only be called for the diagnosis purpose, as there is
3563 string copy operation involved, which may affect the runtime
3564 performance if used in elsewhere. */
3567 get_mnemonic_name (const char *str)
3569 static char mnemonic[32];
3572 /* Get the first 15 bytes and assume that the full name is included. */
3573 strncpy (mnemonic, str, 31);
3574 mnemonic[31] = '\0';
3576 /* Scan up to the end of the mnemonic, which must end in white space,
3577 '.', or end of string. */
3578 for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr)
3583 /* Append '...' to the truncated long name. */
3584 if (ptr - mnemonic == 31)
3585 mnemonic[28] = mnemonic[29] = mnemonic[30] = '.';
3591 reset_aarch64_instruction (aarch64_instruction *instruction)
3593 memset (instruction, '\0', sizeof (aarch64_instruction));
3594 instruction->reloc.type = BFD_RELOC_UNUSED;
3597 /* Data strutures storing one user error in the assembly code related to
3600 struct operand_error_record
3602 const aarch64_opcode *opcode;
3603 aarch64_operand_error detail;
3604 struct operand_error_record *next;
3607 typedef struct operand_error_record operand_error_record;
3609 struct operand_errors
3611 operand_error_record *head;
3612 operand_error_record *tail;
3615 typedef struct operand_errors operand_errors;
3617 /* Top-level data structure reporting user errors for the current line of
3619 The way md_assemble works is that all opcodes sharing the same mnemonic
3620 name are iterated to find a match to the assembly line. In this data
3621 structure, each of the such opcodes will have one operand_error_record
3622 allocated and inserted. In other words, excessive errors related with
3623 a single opcode are disregarded. */
3624 operand_errors operand_error_report;
3626 /* Free record nodes. */
3627 static operand_error_record *free_opnd_error_record_nodes = NULL;
3629 /* Initialize the data structure that stores the operand mismatch
3630 information on assembling one line of the assembly code. */
3632 init_operand_error_report (void)
3634 if (operand_error_report.head != NULL)
3636 gas_assert (operand_error_report.tail != NULL);
3637 operand_error_report.tail->next = free_opnd_error_record_nodes;
3638 free_opnd_error_record_nodes = operand_error_report.head;
3639 operand_error_report.head = NULL;
3640 operand_error_report.tail = NULL;
3643 gas_assert (operand_error_report.tail == NULL);
3646 /* Return TRUE if some operand error has been recorded during the
3647 parsing of the current assembly line using the opcode *OPCODE;
3648 otherwise return FALSE. */
3649 static inline bfd_boolean
3650 opcode_has_operand_error_p (const aarch64_opcode *opcode)
3652 operand_error_record *record = operand_error_report.head;
3653 return record && record->opcode == opcode;
3656 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3657 OPCODE field is initialized with OPCODE.
3658 N.B. only one record for each opcode, i.e. the maximum of one error is
3659 recorded for each instruction template. */
3662 add_operand_error_record (const operand_error_record* new_record)
3664 const aarch64_opcode *opcode = new_record->opcode;
3665 operand_error_record* record = operand_error_report.head;
3667 /* The record may have been created for this opcode. If not, we need
3669 if (! opcode_has_operand_error_p (opcode))
3671 /* Get one empty record. */
3672 if (free_opnd_error_record_nodes == NULL)
3674 record = xmalloc (sizeof (operand_error_record));
3680 record = free_opnd_error_record_nodes;
3681 free_opnd_error_record_nodes = record->next;
3683 record->opcode = opcode;
3684 /* Insert at the head. */
3685 record->next = operand_error_report.head;
3686 operand_error_report.head = record;
3687 if (operand_error_report.tail == NULL)
3688 operand_error_report.tail = record;
3690 else if (record->detail.kind != AARCH64_OPDE_NIL
3691 && record->detail.index <= new_record->detail.index
3692 && operand_error_higher_severity_p (record->detail.kind,
3693 new_record->detail.kind))
3695 /* In the case of multiple errors found on operands related with a
3696 single opcode, only record the error of the leftmost operand and
3697 only if the error is of higher severity. */
3698 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3699 " the existing error %s on operand %d",
3700 operand_mismatch_kind_names[new_record->detail.kind],
3701 new_record->detail.index,
3702 operand_mismatch_kind_names[record->detail.kind],
3703 record->detail.index);
3707 record->detail = new_record->detail;
3711 record_operand_error_info (const aarch64_opcode *opcode,
3712 aarch64_operand_error *error_info)
3714 operand_error_record record;
3715 record.opcode = opcode;
3716 record.detail = *error_info;
3717 add_operand_error_record (&record);
3720 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3721 error message *ERROR, for operand IDX (count from 0). */
3724 record_operand_error (const aarch64_opcode *opcode, int idx,
3725 enum aarch64_operand_error_kind kind,
3728 aarch64_operand_error info;
3729 memset(&info, 0, sizeof (info));
3733 record_operand_error_info (opcode, &info);
3737 record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
3738 enum aarch64_operand_error_kind kind,
3739 const char* error, const int *extra_data)
3741 aarch64_operand_error info;
3745 info.data[0] = extra_data[0];
3746 info.data[1] = extra_data[1];
3747 info.data[2] = extra_data[2];
3748 record_operand_error_info (opcode, &info);
3752 record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx,
3753 const char* error, int lower_bound,
3756 int data[3] = {lower_bound, upper_bound, 0};
3757 record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE,
3761 /* Remove the operand error record for *OPCODE. */
3762 static void ATTRIBUTE_UNUSED
3763 remove_operand_error_record (const aarch64_opcode *opcode)
3765 if (opcode_has_operand_error_p (opcode))
3767 operand_error_record* record = operand_error_report.head;
3768 gas_assert (record != NULL && operand_error_report.tail != NULL);
3769 operand_error_report.head = record->next;
3770 record->next = free_opnd_error_record_nodes;
3771 free_opnd_error_record_nodes = record;
3772 if (operand_error_report.head == NULL)
3774 gas_assert (operand_error_report.tail == record);
3775 operand_error_report.tail = NULL;
3780 /* Given the instruction in *INSTR, return the index of the best matched
3781 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3783 Return -1 if there is no qualifier sequence; return the first match
3784 if there is multiple matches found. */
3787 find_best_match (const aarch64_inst *instr,
3788 const aarch64_opnd_qualifier_seq_t *qualifiers_list)
3790 int i, num_opnds, max_num_matched, idx;
3792 num_opnds = aarch64_num_of_operands (instr->opcode);
3795 DEBUG_TRACE ("no operand");
3799 max_num_matched = 0;
3802 /* For each pattern. */
3803 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
3806 const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
3808 /* Most opcodes has much fewer patterns in the list. */
3809 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
3811 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
3812 if (i != 0 && idx == -1)
3813 /* If nothing has been matched, return the 1st sequence. */
3818 for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers)
3819 if (*qualifiers == instr->operands[j].qualifier)
3822 if (num_matched > max_num_matched)
3824 max_num_matched = num_matched;
3829 DEBUG_TRACE ("return with %d", idx);
3833 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3834 corresponding operands in *INSTR. */
3837 assign_qualifier_sequence (aarch64_inst *instr,
3838 const aarch64_opnd_qualifier_t *qualifiers)
3841 int num_opnds = aarch64_num_of_operands (instr->opcode);
3842 gas_assert (num_opnds);
3843 for (i = 0; i < num_opnds; ++i, ++qualifiers)
3844 instr->operands[i].qualifier = *qualifiers;
3847 /* Print operands for the diagnosis purpose. */
3850 print_operands (char *buf, const aarch64_opcode *opcode,
3851 const aarch64_opnd_info *opnds)
3855 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3857 const size_t size = 128;
3860 /* We regard the opcode operand info more, however we also look into
3861 the inst->operands to support the disassembling of the optional
3863 The two operand code should be the same in all cases, apart from
3864 when the operand can be optional. */
3865 if (opcode->operands[i] == AARCH64_OPND_NIL
3866 || opnds[i].type == AARCH64_OPND_NIL)
3869 /* Generate the operand string in STR. */
3870 aarch64_print_operand (str, size, 0, opcode, opnds, i, NULL, NULL);
3874 strcat (buf, i == 0 ? " " : ",");
3876 /* Append the operand string. */
3881 /* Send to stderr a string as information. */
3884 output_info (const char *format, ...)
3890 as_where (&file, &line);
3894 fprintf (stderr, "%s:%u: ", file, line);
3896 fprintf (stderr, "%s: ", file);
3898 fprintf (stderr, _("Info: "));
3899 va_start (args, format);
3900 vfprintf (stderr, format, args);
3902 (void) putc ('\n', stderr);
3905 /* Output one operand error record. */
3908 output_operand_error_record (const operand_error_record *record, char *str)
3910 int idx = record->detail.index;
3911 const aarch64_opcode *opcode = record->opcode;
3912 enum aarch64_opnd opd_code = (idx != -1 ? opcode->operands[idx]
3913 : AARCH64_OPND_NIL);
3914 const aarch64_operand_error *detail = &record->detail;
3916 switch (detail->kind)
3918 case AARCH64_OPDE_NIL:
3922 case AARCH64_OPDE_SYNTAX_ERROR:
3923 case AARCH64_OPDE_RECOVERABLE:
3924 case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
3925 case AARCH64_OPDE_OTHER_ERROR:
3926 gas_assert (idx >= 0);
3927 /* Use the prepared error message if there is, otherwise use the
3928 operand description string to describe the error. */
3929 if (detail->error != NULL)
3931 if (detail->index == -1)
3932 as_bad (_("%s -- `%s'"), detail->error, str);
3934 as_bad (_("%s at operand %d -- `%s'"),
3935 detail->error, detail->index + 1, str);
3938 as_bad (_("operand %d should be %s -- `%s'"), idx + 1,
3939 aarch64_get_operand_desc (opd_code), str);
3942 case AARCH64_OPDE_INVALID_VARIANT:
3943 as_bad (_("operand mismatch -- `%s'"), str);
3944 if (verbose_error_p)
3946 /* We will try to correct the erroneous instruction and also provide
3947 more information e.g. all other valid variants.
3949 The string representation of the corrected instruction and other
3950 valid variants are generated by
3952 1) obtaining the intermediate representation of the erroneous
3954 2) manipulating the IR, e.g. replacing the operand qualifier;
3955 3) printing out the instruction by calling the printer functions
3956 shared with the disassembler.
3958 The limitation of this method is that the exact input assembly
3959 line cannot be accurately reproduced in some cases, for example an
3960 optional operand present in the actual assembly line will be
3961 omitted in the output; likewise for the optional syntax rules,
3962 e.g. the # before the immediate. Another limitation is that the
3963 assembly symbols and relocation operations in the assembly line
3964 currently cannot be printed out in the error report. Last but not
3965 least, when there is other error(s) co-exist with this error, the
3966 'corrected' instruction may be still incorrect, e.g. given
3967 'ldnp h0,h1,[x0,#6]!'
3968 this diagnosis will provide the version:
3969 'ldnp s0,s1,[x0,#6]!'
3970 which is still not right. */
3971 size_t len = strlen (get_mnemonic_name (str));
3974 const size_t size = 2048;
3976 aarch64_inst *inst_base = &inst.base;
3977 const aarch64_opnd_qualifier_seq_t *qualifiers_list;
3980 reset_aarch64_instruction (&inst);
3981 inst_base->opcode = opcode;
3983 /* Reset the error report so that there is no side effect on the
3984 following operand parsing. */
3985 init_operand_error_report ();
3988 result = parse_operands (str + len, opcode)
3989 && programmer_friendly_fixup (&inst);
3990 gas_assert (result);
3991 result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
3993 gas_assert (!result);
3995 /* Find the most matched qualifier sequence. */
3996 qlf_idx = find_best_match (inst_base, opcode->qualifiers_list);
3997 gas_assert (qlf_idx > -1);
3999 /* Assign the qualifiers. */
4000 assign_qualifier_sequence (inst_base,
4001 opcode->qualifiers_list[qlf_idx]);
4003 /* Print the hint. */
4004 output_info (_(" did you mean this?"));
4005 snprintf (buf, size, "\t%s", get_mnemonic_name (str));
4006 print_operands (buf, opcode, inst_base->operands);
4007 output_info (_(" %s"), buf);
4009 /* Print out other variant(s) if there is any. */
4011 !empty_qualifier_sequence_p (opcode->qualifiers_list[1]))
4012 output_info (_(" other valid variant(s):"));
4014 /* For each pattern. */
4015 qualifiers_list = opcode->qualifiers_list;
4016 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4018 /* Most opcodes has much fewer patterns in the list.
4019 First NIL qualifier indicates the end in the list. */
4020 if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
4025 /* Mnemonics name. */
4026 snprintf (buf, size, "\t%s", get_mnemonic_name (str));
4028 /* Assign the qualifiers. */
4029 assign_qualifier_sequence (inst_base, *qualifiers_list);
4031 /* Print instruction. */
4032 print_operands (buf, opcode, inst_base->operands);
4034 output_info (_(" %s"), buf);
4040 case AARCH64_OPDE_OUT_OF_RANGE:
4041 if (detail->data[0] != detail->data[1])
4042 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4043 detail->error ? detail->error : _("immediate value"),
4044 detail->data[0], detail->data[1], detail->index + 1, str);
4046 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4047 detail->error ? detail->error : _("immediate value"),
4048 detail->data[0], detail->index + 1, str);
4051 case AARCH64_OPDE_REG_LIST:
4052 if (detail->data[0] == 1)
4053 as_bad (_("invalid number of registers in the list; "
4054 "only 1 register is expected at operand %d -- `%s'"),
4055 detail->index + 1, str);
4057 as_bad (_("invalid number of registers in the list; "
4058 "%d registers are expected at operand %d -- `%s'"),
4059 detail->data[0], detail->index + 1, str);
4062 case AARCH64_OPDE_UNALIGNED:
4063 as_bad (_("immediate value should be a multiple of "
4064 "%d at operand %d -- `%s'"),
4065 detail->data[0], detail->index + 1, str);
4074 /* Process and output the error message about the operand mismatching.
4076 When this function is called, the operand error information had
4077 been collected for an assembly line and there will be multiple
4078 errors in the case of mulitple instruction templates; output the
4079 error message that most closely describes the problem. */
4082 output_operand_error_report (char *str)
4084 int largest_error_pos;
4085 const char *msg = NULL;
4086 enum aarch64_operand_error_kind kind;
4087 operand_error_record *curr;
4088 operand_error_record *head = operand_error_report.head;
4089 operand_error_record *record = NULL;
4091 /* No error to report. */
4095 gas_assert (head != NULL && operand_error_report.tail != NULL);
4097 /* Only one error. */
4098 if (head == operand_error_report.tail)
4100 DEBUG_TRACE ("single opcode entry with error kind: %s",
4101 operand_mismatch_kind_names[head->detail.kind]);
4102 output_operand_error_record (head, str);
4106 /* Find the error kind of the highest severity. */
4107 DEBUG_TRACE ("multiple opcode entres with error kind");
4108 kind = AARCH64_OPDE_NIL;
4109 for (curr = head; curr != NULL; curr = curr->next)
4111 gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
4112 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
4113 if (operand_error_higher_severity_p (curr->detail.kind, kind))
4114 kind = curr->detail.kind;
4116 gas_assert (kind != AARCH64_OPDE_NIL);
4118 /* Pick up one of errors of KIND to report. */
4119 largest_error_pos = -2; /* Index can be -1 which means unknown index. */
4120 for (curr = head; curr != NULL; curr = curr->next)
4122 if (curr->detail.kind != kind)
4124 /* If there are multiple errors, pick up the one with the highest
4125 mismatching operand index. In the case of multiple errors with
4126 the equally highest operand index, pick up the first one or the
4127 first one with non-NULL error message. */
4128 if (curr->detail.index > largest_error_pos
4129 || (curr->detail.index == largest_error_pos && msg == NULL
4130 && curr->detail.error != NULL))
4132 largest_error_pos = curr->detail.index;
4134 msg = record->detail.error;
4138 gas_assert (largest_error_pos != -2 && record != NULL);
4139 DEBUG_TRACE ("Pick up error kind %s to report",
4140 operand_mismatch_kind_names[record->detail.kind]);
4143 output_operand_error_record (record, str);
4146 /* Write an AARCH64 instruction to buf - always little-endian. */
4148 put_aarch64_insn (char *buf, uint32_t insn)
4150 unsigned char *where = (unsigned char *) buf;
4152 where[1] = insn >> 8;
4153 where[2] = insn >> 16;
4154 where[3] = insn >> 24;
4158 get_aarch64_insn (char *buf)
4160 unsigned char *where = (unsigned char *) buf;
4162 result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
4167 output_inst (struct aarch64_inst *new_inst)
4171 to = frag_more (INSN_SIZE);
4173 frag_now->tc_frag_data.recorded = 1;
4175 put_aarch64_insn (to, inst.base.value);
4177 if (inst.reloc.type != BFD_RELOC_UNUSED)
4179 fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal,
4180 INSN_SIZE, &inst.reloc.exp,
4183 DEBUG_TRACE ("Prepared relocation fix up");
4184 /* Don't check the addend value against the instruction size,
4185 that's the job of our code in md_apply_fix(). */
4186 fixp->fx_no_overflow = 1;
4187 if (new_inst != NULL)
4188 fixp->tc_fix_data.inst = new_inst;
4189 if (aarch64_gas_internal_fixup_p ())
4191 gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL);
4192 fixp->tc_fix_data.opnd = inst.reloc.opnd;
4193 fixp->fx_addnumber = inst.reloc.flags;
4197 dwarf2_emit_insn (INSN_SIZE);
4200 /* Link together opcodes of the same name. */
4204 aarch64_opcode *opcode;
4205 struct templates *next;
4208 typedef struct templates templates;
4211 lookup_mnemonic (const char *start, int len)
4213 templates *templ = NULL;
4215 templ = hash_find_n (aarch64_ops_hsh, start, len);
4219 /* Subroutine of md_assemble, responsible for looking up the primary
4220 opcode from the mnemonic the user wrote. STR points to the
4221 beginning of the mnemonic. */
4224 opcode_lookup (char **str)
4227 const aarch64_cond *cond;
4231 /* Scan up to the end of the mnemonic, which must end in white space,
4232 '.', or end of string. */
4233 for (base = end = *str; is_part_of_name(*end); end++)
4240 inst.cond = COND_ALWAYS;
4242 /* Handle a possible condition. */
4245 cond = hash_find_n (aarch64_cond_hsh, end + 1, 2);
4248 inst.cond = cond->value;
4262 if (inst.cond == COND_ALWAYS)
4264 /* Look for unaffixed mnemonic. */
4265 return lookup_mnemonic (base, len);
4269 /* append ".c" to mnemonic if conditional */
4270 memcpy (condname, base, len);
4271 memcpy (condname + len, ".c", 2);
4274 return lookup_mnemonic (base, len);
4280 /* Internal helper routine converting a vector neon_type_el structure
4281 *VECTYPE to a corresponding operand qualifier. */
4283 static inline aarch64_opnd_qualifier_t
4284 vectype_to_qualifier (const struct neon_type_el *vectype)
4286 /* Element size in bytes indexed by neon_el_type. */
4287 const unsigned char ele_size[5]
4290 if (!vectype->defined || vectype->type == NT_invtype)
4291 goto vectype_conversion_fail;
4293 gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
4295 if (vectype->defined & NTA_HASINDEX)
4296 /* Vector element register. */
4297 return AARCH64_OPND_QLF_S_B + vectype->type;
4300 /* Vector register. */
4301 int reg_size = ele_size[vectype->type] * vectype->width;
4303 if (reg_size != 16 && reg_size != 8)
4304 goto vectype_conversion_fail;
4305 /* The conversion is calculated based on the relation of the order of
4306 qualifiers to the vector element size and vector register size. */
4307 offset = (vectype->type == NT_q)
4308 ? 8 : (vectype->type << 1) + (reg_size >> 4);
4309 gas_assert (offset <= 8);
4310 return AARCH64_OPND_QLF_V_8B + offset;
4313 vectype_conversion_fail:
4314 first_error (_("bad vector arrangement type"));
4315 return AARCH64_OPND_QLF_NIL;
4318 /* Process an optional operand that is found omitted from the assembly line.
4319 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4320 instruction's opcode entry while IDX is the index of this omitted operand.
4324 process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
4325 int idx, aarch64_opnd_info *operand)
4327 aarch64_insn default_value = get_optional_operand_default_value (opcode);
4328 gas_assert (optional_operand_p (opcode, idx));
4329 gas_assert (!operand->present);
4333 case AARCH64_OPND_Rd:
4334 case AARCH64_OPND_Rn:
4335 case AARCH64_OPND_Rm:
4336 case AARCH64_OPND_Rt:
4337 case AARCH64_OPND_Rt2:
4338 case AARCH64_OPND_Rs:
4339 case AARCH64_OPND_Ra:
4340 case AARCH64_OPND_Rt_SYS:
4341 case AARCH64_OPND_Rd_SP:
4342 case AARCH64_OPND_Rn_SP:
4343 case AARCH64_OPND_Fd:
4344 case AARCH64_OPND_Fn:
4345 case AARCH64_OPND_Fm:
4346 case AARCH64_OPND_Fa:
4347 case AARCH64_OPND_Ft:
4348 case AARCH64_OPND_Ft2:
4349 case AARCH64_OPND_Sd:
4350 case AARCH64_OPND_Sn:
4351 case AARCH64_OPND_Sm:
4352 case AARCH64_OPND_Vd:
4353 case AARCH64_OPND_Vn:
4354 case AARCH64_OPND_Vm:
4355 case AARCH64_OPND_VdD1:
4356 case AARCH64_OPND_VnD1:
4357 operand->reg.regno = default_value;
4360 case AARCH64_OPND_Ed:
4361 case AARCH64_OPND_En:
4362 case AARCH64_OPND_Em:
4363 operand->reglane.regno = default_value;
4366 case AARCH64_OPND_IDX:
4367 case AARCH64_OPND_BIT_NUM:
4368 case AARCH64_OPND_IMMR:
4369 case AARCH64_OPND_IMMS:
4370 case AARCH64_OPND_SHLL_IMM:
4371 case AARCH64_OPND_IMM_VLSL:
4372 case AARCH64_OPND_IMM_VLSR:
4373 case AARCH64_OPND_CCMP_IMM:
4374 case AARCH64_OPND_FBITS:
4375 case AARCH64_OPND_UIMM4:
4376 case AARCH64_OPND_UIMM3_OP1:
4377 case AARCH64_OPND_UIMM3_OP2:
4378 case AARCH64_OPND_IMM:
4379 case AARCH64_OPND_WIDTH:
4380 case AARCH64_OPND_UIMM7:
4381 case AARCH64_OPND_NZCV:
4382 operand->imm.value = default_value;
4385 case AARCH64_OPND_EXCEPTION:
4386 inst.reloc.type = BFD_RELOC_UNUSED;
4389 case AARCH64_OPND_BARRIER_ISB:
4390 operand->barrier = aarch64_barrier_options + default_value;
4397 /* Process the relocation type for move wide instructions.
4398 Return TRUE on success; otherwise return FALSE. */
4401 process_movw_reloc_info (void)
4406 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
4408 if (inst.base.opcode->op == OP_MOVK)
4409 switch (inst.reloc.type)
4411 case BFD_RELOC_AARCH64_MOVW_G0_S:
4412 case BFD_RELOC_AARCH64_MOVW_G1_S:
4413 case BFD_RELOC_AARCH64_MOVW_G2_S:
4414 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4415 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4416 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4417 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4418 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4420 (_("the specified relocation type is not allowed for MOVK"));
4426 switch (inst.reloc.type)
4428 case BFD_RELOC_AARCH64_MOVW_G0:
4429 case BFD_RELOC_AARCH64_MOVW_G0_S:
4430 case BFD_RELOC_AARCH64_MOVW_G0_NC:
4431 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4432 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4435 case BFD_RELOC_AARCH64_MOVW_G1:
4436 case BFD_RELOC_AARCH64_MOVW_G1_S:
4437 case BFD_RELOC_AARCH64_MOVW_G1_NC:
4438 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4439 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4442 case BFD_RELOC_AARCH64_MOVW_G2:
4443 case BFD_RELOC_AARCH64_MOVW_G2_S:
4444 case BFD_RELOC_AARCH64_MOVW_G2_NC:
4445 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4448 set_fatal_syntax_error
4449 (_("the specified relocation type is not allowed for 32-bit "
4455 case BFD_RELOC_AARCH64_MOVW_G3:
4458 set_fatal_syntax_error
4459 (_("the specified relocation type is not allowed for 32-bit "
4466 /* More cases should be added when more MOVW-related relocation types
4467 are supported in GAS. */
4468 gas_assert (aarch64_gas_internal_fixup_p ());
4469 /* The shift amount should have already been set by the parser. */
4472 inst.base.operands[1].shifter.amount = shift;
4476 /* A primitive log caculator. */
4478 static inline unsigned int
4479 get_logsz (unsigned int size)
4481 const unsigned char ls[16] =
4482 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4488 gas_assert (ls[size - 1] != (unsigned char)-1);
4489 return ls[size - 1];
4492 /* Determine and return the real reloc type code for an instruction
4493 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4495 static inline bfd_reloc_code_real_type
4496 ldst_lo12_determine_real_reloc_type (void)
4499 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
4500 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
4502 const bfd_reloc_code_real_type reloc_ldst_lo12[5] = {
4503 BFD_RELOC_AARCH64_LDST8_LO12, BFD_RELOC_AARCH64_LDST16_LO12,
4504 BFD_RELOC_AARCH64_LDST32_LO12, BFD_RELOC_AARCH64_LDST64_LO12,
4505 BFD_RELOC_AARCH64_LDST128_LO12
4508 gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12);
4509 gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
4511 if (opd1_qlf == AARCH64_OPND_QLF_NIL)
4513 aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list,
4515 gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
4517 logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
4518 gas_assert (logsz >= 0 && logsz <= 4);
4520 return reloc_ldst_lo12[logsz];
4523 /* Check whether a register list REGINFO is valid. The registers must be
4524 numbered in increasing order (modulo 32), in increments of one or two.
4526 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4529 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4532 reg_list_valid_p (uint32_t reginfo, int accept_alternate)
4534 uint32_t i, nb_regs, prev_regno, incr;
4536 nb_regs = 1 + (reginfo & 0x3);
4538 prev_regno = reginfo & 0x1f;
4539 incr = accept_alternate ? 2 : 1;
4541 for (i = 1; i < nb_regs; ++i)
4543 uint32_t curr_regno;
4545 curr_regno = reginfo & 0x1f;
4546 if (curr_regno != ((prev_regno + incr) & 0x1f))
4548 prev_regno = curr_regno;
4554 /* Generic instruction operand parser. This does no encoding and no
4555 semantic validation; it merely squirrels values away in the inst
4556 structure. Returns TRUE or FALSE depending on whether the
4557 specified grammar matched. */
4560 parse_operands (char *str, const aarch64_opcode *opcode)
4563 char *backtrack_pos = 0;
4564 const enum aarch64_opnd *operands = opcode->operands;
4567 skip_whitespace (str);
4569 for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
4572 int isreg32, isregzero;
4573 int comma_skipped_p = 0;
4574 aarch64_reg_type rtype;
4575 struct neon_type_el vectype;
4576 aarch64_opnd_info *info = &inst.base.operands[i];
4578 DEBUG_TRACE ("parse operand %d", i);
4580 /* Assign the operand code. */
4581 info->type = operands[i];
4583 if (optional_operand_p (opcode, i))
4585 /* Remember where we are in case we need to backtrack. */
4586 gas_assert (!backtrack_pos);
4587 backtrack_pos = str;
4590 /* Expect comma between operands; the backtrack mechanizm will take
4591 care of cases of omitted optional operand. */
4592 if (i > 0 && ! skip_past_char (&str, ','))
4594 set_syntax_error (_("comma expected between operands"));
4598 comma_skipped_p = 1;
4600 switch (operands[i])
4602 case AARCH64_OPND_Rd:
4603 case AARCH64_OPND_Rn:
4604 case AARCH64_OPND_Rm:
4605 case AARCH64_OPND_Rt:
4606 case AARCH64_OPND_Rt2:
4607 case AARCH64_OPND_Rs:
4608 case AARCH64_OPND_Ra:
4609 case AARCH64_OPND_Rt_SYS:
4610 po_int_reg_or_fail (1, 0);
4613 case AARCH64_OPND_Rd_SP:
4614 case AARCH64_OPND_Rn_SP:
4615 po_int_reg_or_fail (0, 1);
4618 case AARCH64_OPND_Rm_EXT:
4619 case AARCH64_OPND_Rm_SFT:
4620 po_misc_or_fail (parse_shifter_operand
4621 (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT
4623 : SHIFTED_LOGIC_IMM)));
4624 if (!info->shifter.operator_present)
4626 /* Default to LSL if not present. Libopcodes prefers shifter
4627 kind to be explicit. */
4628 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4629 info->shifter.kind = AARCH64_MOD_LSL;
4630 /* For Rm_EXT, libopcodes will carry out further check on whether
4631 or not stack pointer is used in the instruction (Recall that
4632 "the extend operator is not optional unless at least one of
4633 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4637 case AARCH64_OPND_Fd:
4638 case AARCH64_OPND_Fn:
4639 case AARCH64_OPND_Fm:
4640 case AARCH64_OPND_Fa:
4641 case AARCH64_OPND_Ft:
4642 case AARCH64_OPND_Ft2:
4643 case AARCH64_OPND_Sd:
4644 case AARCH64_OPND_Sn:
4645 case AARCH64_OPND_Sm:
4646 val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
4647 if (val == PARSE_FAIL)
4649 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
4652 gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
4654 info->reg.regno = val;
4655 info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
4658 case AARCH64_OPND_Vd:
4659 case AARCH64_OPND_Vn:
4660 case AARCH64_OPND_Vm:
4661 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4662 if (val == PARSE_FAIL)
4664 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4667 if (vectype.defined & NTA_HASINDEX)
4670 info->reg.regno = val;
4671 info->qualifier = vectype_to_qualifier (&vectype);
4672 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4676 case AARCH64_OPND_VdD1:
4677 case AARCH64_OPND_VnD1:
4678 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4679 if (val == PARSE_FAIL)
4681 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4684 if (vectype.type != NT_d || vectype.index != 1)
4686 set_fatal_syntax_error
4687 (_("the top half of a 128-bit FP/SIMD register is expected"));
4690 info->reg.regno = val;
4691 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4692 here; it is correct for the purpose of encoding/decoding since
4693 only the register number is explicitly encoded in the related
4694 instructions, although this appears a bit hacky. */
4695 info->qualifier = AARCH64_OPND_QLF_S_D;
4698 case AARCH64_OPND_Ed:
4699 case AARCH64_OPND_En:
4700 case AARCH64_OPND_Em:
4701 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4702 if (val == PARSE_FAIL)
4704 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4707 if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
4710 info->reglane.regno = val;
4711 info->reglane.index = vectype.index;
4712 info->qualifier = vectype_to_qualifier (&vectype);
4713 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4717 case AARCH64_OPND_LVn:
4718 case AARCH64_OPND_LVt:
4719 case AARCH64_OPND_LVt_AL:
4720 case AARCH64_OPND_LEt:
4721 if ((val = parse_neon_reg_list (&str, &vectype)) == PARSE_FAIL)
4723 if (! reg_list_valid_p (val, /* accept_alternate */ 0))
4725 set_fatal_syntax_error (_("invalid register list"));
4728 info->reglist.first_regno = (val >> 2) & 0x1f;
4729 info->reglist.num_regs = (val & 0x3) + 1;
4730 if (operands[i] == AARCH64_OPND_LEt)
4732 if (!(vectype.defined & NTA_HASINDEX))
4734 info->reglist.has_index = 1;
4735 info->reglist.index = vectype.index;
4737 else if (!(vectype.defined & NTA_HASTYPE))
4739 info->qualifier = vectype_to_qualifier (&vectype);
4740 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4744 case AARCH64_OPND_Cn:
4745 case AARCH64_OPND_Cm:
4746 po_reg_or_fail (REG_TYPE_CN);
4749 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN)));
4752 inst.base.operands[i].reg.regno = val;
4755 case AARCH64_OPND_SHLL_IMM:
4756 case AARCH64_OPND_IMM_VLSR:
4757 po_imm_or_fail (1, 64);
4758 info->imm.value = val;
4761 case AARCH64_OPND_CCMP_IMM:
4762 case AARCH64_OPND_FBITS:
4763 case AARCH64_OPND_UIMM4:
4764 case AARCH64_OPND_UIMM3_OP1:
4765 case AARCH64_OPND_UIMM3_OP2:
4766 case AARCH64_OPND_IMM_VLSL:
4767 case AARCH64_OPND_IMM:
4768 case AARCH64_OPND_WIDTH:
4769 po_imm_nc_or_fail ();
4770 info->imm.value = val;
4773 case AARCH64_OPND_UIMM7:
4774 po_imm_or_fail (0, 127);
4775 info->imm.value = val;
4778 case AARCH64_OPND_IDX:
4779 case AARCH64_OPND_BIT_NUM:
4780 case AARCH64_OPND_IMMR:
4781 case AARCH64_OPND_IMMS:
4782 po_imm_or_fail (0, 63);
4783 info->imm.value = val;
4786 case AARCH64_OPND_IMM0:
4787 po_imm_nc_or_fail ();
4790 set_fatal_syntax_error (_("immediate zero expected"));
4793 info->imm.value = 0;
4796 case AARCH64_OPND_FPIMM0:
4799 bfd_boolean res1 = FALSE, res2 = FALSE;
4800 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4801 it is probably not worth the effort to support it. */
4802 if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE))
4803 && !(res2 = parse_constant_immediate (&str, &val)))
4805 if ((res1 && qfloat == 0) || (res2 && val == 0))
4807 info->imm.value = 0;
4808 info->imm.is_fp = 1;
4811 set_fatal_syntax_error (_("immediate zero expected"));
4815 case AARCH64_OPND_IMM_MOV:
4818 if (reg_name_p (str, REG_TYPE_R_Z_SP) ||
4819 reg_name_p (str, REG_TYPE_VN))
4822 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
4824 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4825 later. fix_mov_imm_insn will try to determine a machine
4826 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4827 message if the immediate cannot be moved by a single
4829 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
4830 inst.base.operands[i].skip = 1;
4834 case AARCH64_OPND_SIMD_IMM:
4835 case AARCH64_OPND_SIMD_IMM_SFT:
4836 if (! parse_big_immediate (&str, &val))
4838 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4840 /* need_libopcodes_p */ 1,
4843 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4844 shift, we don't check it here; we leave the checking to
4845 the libopcodes (operand_general_constraint_met_p). By
4846 doing this, we achieve better diagnostics. */
4847 if (skip_past_comma (&str)
4848 && ! parse_shift (&str, info, SHIFTED_LSL_MSL))
4850 if (!info->shifter.operator_present
4851 && info->type == AARCH64_OPND_SIMD_IMM_SFT)
4853 /* Default to LSL if not present. Libopcodes prefers shifter
4854 kind to be explicit. */
4855 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4856 info->shifter.kind = AARCH64_MOD_LSL;
4860 case AARCH64_OPND_FPIMM:
4861 case AARCH64_OPND_SIMD_FPIMM:
4865 = (aarch64_get_qualifier_esize (inst.base.operands[0].qualifier)
4867 if (! parse_aarch64_imm_float (&str, &qfloat, dp_p))
4871 set_fatal_syntax_error (_("invalid floating-point constant"));
4874 inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat);
4875 inst.base.operands[i].imm.is_fp = 1;
4879 case AARCH64_OPND_LIMM:
4880 po_misc_or_fail (parse_shifter_operand (&str, info,
4881 SHIFTED_LOGIC_IMM));
4882 if (info->shifter.operator_present)
4884 set_fatal_syntax_error
4885 (_("shift not allowed for bitmask immediate"));
4888 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4890 /* need_libopcodes_p */ 1,
4894 case AARCH64_OPND_AIMM:
4895 if (opcode->op == OP_ADD)
4896 /* ADD may have relocation types. */
4897 po_misc_or_fail (parse_shifter_operand_reloc (&str, info,
4898 SHIFTED_ARITH_IMM));
4900 po_misc_or_fail (parse_shifter_operand (&str, info,
4901 SHIFTED_ARITH_IMM));
4902 switch (inst.reloc.type)
4904 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
4905 info->shifter.amount = 12;
4907 case BFD_RELOC_UNUSED:
4908 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
4909 if (info->shifter.kind != AARCH64_MOD_NONE)
4910 inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT;
4911 inst.reloc.pc_rel = 0;
4916 info->imm.value = 0;
4917 if (!info->shifter.operator_present)
4919 /* Default to LSL if not present. Libopcodes prefers shifter
4920 kind to be explicit. */
4921 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4922 info->shifter.kind = AARCH64_MOD_LSL;
4926 case AARCH64_OPND_HALF:
4928 /* #<imm16> or relocation. */
4929 int internal_fixup_p;
4930 po_misc_or_fail (parse_half (&str, &internal_fixup_p));
4931 if (internal_fixup_p)
4932 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
4933 skip_whitespace (str);
4934 if (skip_past_comma (&str))
4936 /* {, LSL #<shift>} */
4937 if (! aarch64_gas_internal_fixup_p ())
4939 set_fatal_syntax_error (_("can't mix relocation modifier "
4940 "with explicit shift"));
4943 po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
4946 inst.base.operands[i].shifter.amount = 0;
4947 inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
4948 inst.base.operands[i].imm.value = 0;
4949 if (! process_movw_reloc_info ())
4954 case AARCH64_OPND_EXCEPTION:
4955 po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp));
4956 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4958 /* need_libopcodes_p */ 0,
4962 case AARCH64_OPND_NZCV:
4964 const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4);
4968 info->imm.value = nzcv->value;
4971 po_imm_or_fail (0, 15);
4972 info->imm.value = val;
4976 case AARCH64_OPND_COND:
4977 case AARCH64_OPND_COND1:
4978 info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
4980 if (info->cond == NULL)
4982 set_syntax_error (_("invalid condition"));
4985 else if (operands[i] == AARCH64_OPND_COND1
4986 && (info->cond->value & 0xe) == 0xe)
4988 /* Not allow AL or NV. */
4989 set_default_error ();
4994 case AARCH64_OPND_ADDR_ADRP:
4995 po_misc_or_fail (parse_adrp (&str));
4996 /* Clear the value as operand needs to be relocated. */
4997 info->imm.value = 0;
5000 case AARCH64_OPND_ADDR_PCREL14:
5001 case AARCH64_OPND_ADDR_PCREL19:
5002 case AARCH64_OPND_ADDR_PCREL21:
5003 case AARCH64_OPND_ADDR_PCREL26:
5004 po_misc_or_fail (parse_address_reloc (&str, info));
5005 if (!info->addr.pcrel)
5007 set_syntax_error (_("invalid pc-relative address"));
5010 if (inst.gen_lit_pool
5011 && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT))
5013 /* Only permit "=value" in the literal load instructions.
5014 The literal will be generated by programmer_friendly_fixup. */
5015 set_syntax_error (_("invalid use of \"=immediate\""));
5018 if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str))
5020 set_syntax_error (_("unrecognized relocation suffix"));
5023 if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
5025 info->imm.value = inst.reloc.exp.X_add_number;
5026 inst.reloc.type = BFD_RELOC_UNUSED;
5030 info->imm.value = 0;
5031 if (inst.reloc.type == BFD_RELOC_UNUSED)
5032 switch (opcode->iclass)
5036 /* e.g. CBZ or B.COND */
5037 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5038 inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
5042 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
5043 inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
5047 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
5049 (opcode->op == OP_BL) ? BFD_RELOC_AARCH64_CALL26
5050 : BFD_RELOC_AARCH64_JUMP26;
5053 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5054 inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
5057 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
5058 inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
5064 inst.reloc.pc_rel = 1;
5068 case AARCH64_OPND_ADDR_SIMPLE:
5069 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
5070 /* [<Xn|SP>{, #<simm>}] */
5071 po_char_or_fail ('[');
5072 po_reg_or_fail (REG_TYPE_R64_SP);
5073 /* Accept optional ", #0". */
5074 if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
5075 && skip_past_char (&str, ','))
5077 skip_past_char (&str, '#');
5078 if (! skip_past_char (&str, '0'))
5080 set_fatal_syntax_error
5081 (_("the optional immediate offset can only be 0"));
5085 po_char_or_fail (']');
5086 info->addr.base_regno = val;
5089 case AARCH64_OPND_ADDR_REGOFF:
5090 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5091 po_misc_or_fail (parse_address (&str, info, 0));
5092 if (info->addr.pcrel || !info->addr.offset.is_reg
5093 || !info->addr.preind || info->addr.postind
5094 || info->addr.writeback)
5096 set_syntax_error (_("invalid addressing mode"));
5099 if (!info->shifter.operator_present)
5101 /* Default to LSL if not present. Libopcodes prefers shifter
5102 kind to be explicit. */
5103 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5104 info->shifter.kind = AARCH64_MOD_LSL;
5106 /* Qualifier to be deduced by libopcodes. */
5109 case AARCH64_OPND_ADDR_SIMM7:
5110 po_misc_or_fail (parse_address (&str, info, 0));
5111 if (info->addr.pcrel || info->addr.offset.is_reg
5112 || (!info->addr.preind && !info->addr.postind))
5114 set_syntax_error (_("invalid addressing mode"));
5117 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5119 /* need_libopcodes_p */ 1,
5123 case AARCH64_OPND_ADDR_SIMM9:
5124 case AARCH64_OPND_ADDR_SIMM9_2:
5125 po_misc_or_fail (parse_address_reloc (&str, info));
5126 if (info->addr.pcrel || info->addr.offset.is_reg
5127 || (!info->addr.preind && !info->addr.postind)
5128 || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
5129 && info->addr.writeback))
5131 set_syntax_error (_("invalid addressing mode"));
5134 if (inst.reloc.type != BFD_RELOC_UNUSED)
5136 set_syntax_error (_("relocation not allowed"));
5139 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5141 /* need_libopcodes_p */ 1,
5145 case AARCH64_OPND_ADDR_UIMM12:
5146 po_misc_or_fail (parse_address_reloc (&str, info));
5147 if (info->addr.pcrel || info->addr.offset.is_reg
5148 || !info->addr.preind || info->addr.writeback)
5150 set_syntax_error (_("invalid addressing mode"));
5153 if (inst.reloc.type == BFD_RELOC_UNUSED)
5154 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5155 else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12)
5156 inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
5157 /* Leave qualifier to be determined by libopcodes. */
5160 case AARCH64_OPND_SIMD_ADDR_POST:
5161 /* [<Xn|SP>], <Xm|#<amount>> */
5162 po_misc_or_fail (parse_address (&str, info, 1));
5163 if (!info->addr.postind || !info->addr.writeback)
5165 set_syntax_error (_("invalid addressing mode"));
5168 if (!info->addr.offset.is_reg)
5170 if (inst.reloc.exp.X_op == O_constant)
5171 info->addr.offset.imm = inst.reloc.exp.X_add_number;
5174 set_fatal_syntax_error
5175 (_("writeback value should be an immediate constant"));
5182 case AARCH64_OPND_SYSREG:
5183 if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1))
5186 set_syntax_error (_("unknown or missing system register name"));
5189 inst.base.operands[i].sysreg = val;
5192 case AARCH64_OPND_PSTATEFIELD:
5193 if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0))
5196 set_syntax_error (_("unknown or missing PSTATE field name"));
5199 inst.base.operands[i].pstatefield = val;
5202 case AARCH64_OPND_SYSREG_IC:
5203 inst.base.operands[i].sysins_op =
5204 parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
5206 case AARCH64_OPND_SYSREG_DC:
5207 inst.base.operands[i].sysins_op =
5208 parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
5210 case AARCH64_OPND_SYSREG_AT:
5211 inst.base.operands[i].sysins_op =
5212 parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
5214 case AARCH64_OPND_SYSREG_TLBI:
5215 inst.base.operands[i].sysins_op =
5216 parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
5218 if (inst.base.operands[i].sysins_op == NULL)
5220 set_fatal_syntax_error ( _("unknown or missing operation name"));
5225 case AARCH64_OPND_BARRIER:
5226 case AARCH64_OPND_BARRIER_ISB:
5227 val = parse_barrier (&str);
5228 if (val != PARSE_FAIL
5229 && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf)
5231 /* ISB only accepts options name 'sy'. */
5233 (_("the specified option is not accepted in ISB"));
5234 /* Turn off backtrack as this optional operand is present. */
5238 /* This is an extension to accept a 0..15 immediate. */
5239 if (val == PARSE_FAIL)
5240 po_imm_or_fail (0, 15);
5241 info->barrier = aarch64_barrier_options + val;
5244 case AARCH64_OPND_PRFOP:
5245 val = parse_pldop (&str);
5246 /* This is an extension to accept a 0..31 immediate. */
5247 if (val == PARSE_FAIL)
5248 po_imm_or_fail (0, 31);
5249 inst.base.operands[i].prfop = aarch64_prfops + val;
5253 as_fatal (_("unhandled operand code %d"), operands[i]);
5256 /* If we get here, this operand was successfully parsed. */
5257 inst.base.operands[i].present = 1;
5261 /* The parse routine should already have set the error, but in case
5262 not, set a default one here. */
5264 set_default_error ();
5266 if (! backtrack_pos)
5267 goto parse_operands_return;
5269 /* Reaching here means we are dealing with an optional operand that is
5270 omitted from the assembly line. */
5271 gas_assert (optional_operand_p (opcode, i));
5273 process_omitted_operand (operands[i], opcode, i, info);
5275 /* Try again, skipping the optional operand at backtrack_pos. */
5276 str = backtrack_pos;
5279 /* If this is the last operand that is optional and omitted, but without
5280 the presence of a comma. */
5281 if (i && comma_skipped_p && i == aarch64_num_of_operands (opcode) - 1)
5283 set_fatal_syntax_error
5284 (_("unexpected comma before the omitted optional operand"));
5285 goto parse_operands_return;
5288 /* Clear any error record after the omitted optional operand has been
5289 successfully handled. */
5293 /* Check if we have parsed all the operands. */
5294 if (*str != '\0' && ! error_p ())
5296 /* Set I to the index of the last present operand; this is
5297 for the purpose of diagnostics. */
5298 for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i)
5300 set_fatal_syntax_error
5301 (_("unexpected characters following instruction"));
5304 parse_operands_return:
5308 DEBUG_TRACE ("parsing FAIL: %s - %s",
5309 operand_mismatch_kind_names[get_error_kind ()],
5310 get_error_message ());
5311 /* Record the operand error properly; this is useful when there
5312 are multiple instruction templates for a mnemonic name, so that
5313 later on, we can select the error that most closely describes
5315 record_operand_error (opcode, i, get_error_kind (),
5316 get_error_message ());
5321 DEBUG_TRACE ("parsing SUCCESS");
5326 /* It does some fix-up to provide some programmer friendly feature while
5327 keeping the libopcodes happy, i.e. libopcodes only accepts
5328 the preferred architectural syntax.
5329 Return FALSE if there is any failure; otherwise return TRUE. */
5332 programmer_friendly_fixup (aarch64_instruction *instr)
5334 aarch64_inst *base = &instr->base;
5335 const aarch64_opcode *opcode = base->opcode;
5336 enum aarch64_op op = opcode->op;
5337 aarch64_opnd_info *operands = base->operands;
5339 DEBUG_TRACE ("enter");
5341 switch (opcode->iclass)
5344 /* TBNZ Xn|Wn, #uimm6, label
5345 Test and Branch Not Zero: conditionally jumps to label if bit number
5346 uimm6 in register Xn is not zero. The bit number implies the width of
5347 the register, which may be written and should be disassembled as Wn if
5348 uimm is less than 32. */
5349 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
5351 if (operands[1].imm.value >= 32)
5353 record_operand_out_of_range_error (opcode, 1, _("immediate value"),
5357 operands[0].qualifier = AARCH64_OPND_QLF_X;
5361 /* LDR Wt, label | =value
5362 As a convenience assemblers will typically permit the notation
5363 "=value" in conjunction with the pc-relative literal load instructions
5364 to automatically place an immediate value or symbolic address in a
5365 nearby literal pool and generate a hidden label which references it.
5366 ISREG has been set to 0 in the case of =value. */
5367 if (instr->gen_lit_pool
5368 && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT))
5370 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
5371 if (op == OP_LDRSW_LIT)
5373 if (instr->reloc.exp.X_op != O_constant
5374 && instr->reloc.exp.X_op != O_big
5375 && instr->reloc.exp.X_op != O_symbol)
5377 record_operand_error (opcode, 1,
5378 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
5379 _("constant expression expected"));
5382 if (! add_to_lit_pool (&instr->reloc.exp, size))
5384 record_operand_error (opcode, 1,
5385 AARCH64_OPDE_OTHER_ERROR,
5386 _("literal pool insertion failed"));
5394 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5395 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5396 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5397 A programmer-friendly assembler should accept a destination Xd in
5398 place of Wd, however that is not the preferred form for disassembly.
5400 if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW)
5401 && operands[1].qualifier == AARCH64_OPND_QLF_W
5402 && operands[0].qualifier == AARCH64_OPND_QLF_X)
5403 operands[0].qualifier = AARCH64_OPND_QLF_W;
5408 /* In the 64-bit form, the final register operand is written as Wm
5409 for all but the (possibly omitted) UXTX/LSL and SXTX
5411 As a programmer-friendly assembler, we accept e.g.
5412 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5413 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5414 int idx = aarch64_operand_index (opcode->operands,
5415 AARCH64_OPND_Rm_EXT);
5416 gas_assert (idx == 1 || idx == 2);
5417 if (operands[0].qualifier == AARCH64_OPND_QLF_X
5418 && operands[idx].qualifier == AARCH64_OPND_QLF_X
5419 && operands[idx].shifter.kind != AARCH64_MOD_LSL
5420 && operands[idx].shifter.kind != AARCH64_MOD_UXTX
5421 && operands[idx].shifter.kind != AARCH64_MOD_SXTX)
5422 operands[idx].qualifier = AARCH64_OPND_QLF_W;
5430 DEBUG_TRACE ("exit with SUCCESS");
5434 /* A wrapper function to interface with libopcodes on encoding and
5435 record the error message if there is any.
5437 Return TRUE on success; otherwise return FALSE. */
5440 do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
5443 aarch64_operand_error error_info;
5444 error_info.kind = AARCH64_OPDE_NIL;
5445 if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
5449 gas_assert (error_info.kind != AARCH64_OPDE_NIL);
5450 record_operand_error_info (opcode, &error_info);
5455 #ifdef DEBUG_AARCH64
5457 dump_opcode_operands (const aarch64_opcode *opcode)
5460 while (opcode->operands[i] != AARCH64_OPND_NIL)
5462 aarch64_verbose ("\t\t opnd%d: %s", i,
5463 aarch64_get_operand_name (opcode->operands[i])[0] != '\0'
5464 ? aarch64_get_operand_name (opcode->operands[i])
5465 : aarch64_get_operand_desc (opcode->operands[i]));
5469 #endif /* DEBUG_AARCH64 */
5471 /* This is the guts of the machine-dependent assembler. STR points to a
5472 machine dependent instruction. This function is supposed to emit
5473 the frags/bytes it assembles to. */
5476 md_assemble (char *str)
5479 templates *template;
5480 aarch64_opcode *opcode;
5481 aarch64_inst *inst_base;
5482 unsigned saved_cond;
5484 /* Align the previous label if needed. */
5485 if (last_label_seen != NULL)
5487 symbol_set_frag (last_label_seen, frag_now);
5488 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
5489 S_SET_SEGMENT (last_label_seen, now_seg);
5492 inst.reloc.type = BFD_RELOC_UNUSED;
5494 DEBUG_TRACE ("\n\n");
5495 DEBUG_TRACE ("==============================");
5496 DEBUG_TRACE ("Enter md_assemble with %s", str);
5498 template = opcode_lookup (&p);
5501 /* It wasn't an instruction, but it might be a register alias of
5502 the form alias .req reg directive. */
5503 if (!create_register_alias (str, p))
5504 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
5509 skip_whitespace (p);
5512 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5513 get_mnemonic_name (str), str);
5517 init_operand_error_report ();
5519 saved_cond = inst.cond;
5520 reset_aarch64_instruction (&inst);
5521 inst.cond = saved_cond;
5523 /* Iterate through all opcode entries with the same mnemonic name. */
5526 opcode = template->opcode;
5528 DEBUG_TRACE ("opcode %s found", opcode->name);
5529 #ifdef DEBUG_AARCH64
5531 dump_opcode_operands (opcode);
5532 #endif /* DEBUG_AARCH64 */
5534 /* Check that this instruction is supported for this CPU. */
5535 if (!opcode->avariant
5536 || !AARCH64_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
5538 as_bad (_("selected processor does not support `%s'"), str);
5542 mapping_state (MAP_INSN);
5544 inst_base = &inst.base;
5545 inst_base->opcode = opcode;
5547 /* Truly conditionally executed instructions, e.g. b.cond. */
5548 if (opcode->flags & F_COND)
5550 gas_assert (inst.cond != COND_ALWAYS);
5551 inst_base->cond = get_cond_from_value (inst.cond);
5552 DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]);
5554 else if (inst.cond != COND_ALWAYS)
5556 /* It shouldn't arrive here, where the assembly looks like a
5557 conditional instruction but the found opcode is unconditional. */
5562 if (parse_operands (p, opcode)
5563 && programmer_friendly_fixup (&inst)
5564 && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
5566 if (inst.reloc.type == BFD_RELOC_UNUSED
5567 || !inst.reloc.need_libopcodes_p)
5571 /* If there is relocation generated for the instruction,
5572 store the instruction information for the future fix-up. */
5573 struct aarch64_inst *copy;
5574 gas_assert (inst.reloc.type != BFD_RELOC_UNUSED);
5575 if ((copy = xmalloc (sizeof (struct aarch64_inst))) == NULL)
5577 memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
5583 template = template->next;
5584 if (template != NULL)
5586 reset_aarch64_instruction (&inst);
5587 inst.cond = saved_cond;
5590 while (template != NULL);
5592 /* Issue the error messages if any. */
5593 output_operand_error_report (str);
5596 /* Various frobbings of labels and their addresses. */
5599 aarch64_start_line_hook (void)
5601 last_label_seen = NULL;
5605 aarch64_frob_label (symbolS * sym)
5607 last_label_seen = sym;
5609 dwarf2_emit_label (sym);
5613 aarch64_data_in_code (void)
5615 if (!strncmp (input_line_pointer + 1, "data:", 5))
5617 *input_line_pointer = '/';
5618 input_line_pointer += 5;
5619 *input_line_pointer = 0;
5627 aarch64_canonicalize_symbol_name (char *name)
5631 if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data"))
5632 *(name + len - 5) = 0;
5637 /* Table of all register names defined by default. The user can
5638 define additional names with .req. Note that all register names
5639 should appear in both upper and lowercase variants. Some registers
5640 also have mixed-case names. */
5642 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5643 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5644 #define REGSET31(p,t) \
5645 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5646 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5647 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5648 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5649 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5650 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5651 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5652 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5653 #define REGSET(p,t) \
5654 REGSET31(p,t), REGNUM(p,31,t)
5656 /* These go into aarch64_reg_hsh hash-table. */
5657 static const reg_entry reg_names[] = {
5658 /* Integer registers. */
5659 REGSET31 (x, R_64), REGSET31 (X, R_64),
5660 REGSET31 (w, R_32), REGSET31 (W, R_32),
5662 REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
5663 REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
5665 REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
5666 REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
5668 /* Coprocessor register numbers. */
5669 REGSET (c, CN), REGSET (C, CN),
5671 /* Floating-point single precision registers. */
5672 REGSET (s, FP_S), REGSET (S, FP_S),
5674 /* Floating-point double precision registers. */
5675 REGSET (d, FP_D), REGSET (D, FP_D),
5677 /* Floating-point half precision registers. */
5678 REGSET (h, FP_H), REGSET (H, FP_H),
5680 /* Floating-point byte precision registers. */
5681 REGSET (b, FP_B), REGSET (B, FP_B),
5683 /* Floating-point quad precision registers. */
5684 REGSET (q, FP_Q), REGSET (Q, FP_Q),
5686 /* FP/SIMD registers. */
5687 REGSET (v, VN), REGSET (V, VN),
5702 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5703 static const asm_nzcv nzcv_names[] = {
5704 {"nzcv", B (n, z, c, v)},
5705 {"nzcV", B (n, z, c, V)},
5706 {"nzCv", B (n, z, C, v)},
5707 {"nzCV", B (n, z, C, V)},
5708 {"nZcv", B (n, Z, c, v)},
5709 {"nZcV", B (n, Z, c, V)},
5710 {"nZCv", B (n, Z, C, v)},
5711 {"nZCV", B (n, Z, C, V)},
5712 {"Nzcv", B (N, z, c, v)},
5713 {"NzcV", B (N, z, c, V)},
5714 {"NzCv", B (N, z, C, v)},
5715 {"NzCV", B (N, z, C, V)},
5716 {"NZcv", B (N, Z, c, v)},
5717 {"NZcV", B (N, Z, c, V)},
5718 {"NZCv", B (N, Z, C, v)},
5719 {"NZCV", B (N, Z, C, V)}
5732 /* MD interface: bits in the object file. */
5734 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5735 for use in the a.out file, and stores them in the array pointed to by buf.
5736 This knows about the endian-ness of the target machine and does
5737 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5738 2 (short) and 4 (long) Floating numbers are put out as a series of
5739 LITTLENUMS (shorts, here at least). */
5742 md_number_to_chars (char *buf, valueT val, int n)
5744 if (target_big_endian)
5745 number_to_chars_bigendian (buf, val, n);
5747 number_to_chars_littleendian (buf, val, n);
5750 /* MD interface: Sections. */
5752 /* Estimate the size of a frag before relaxing. Assume everything fits in
5756 md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED)
5762 /* Round up a section size to the appropriate boundary. */
5765 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5770 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5771 of an rs_align_code fragment. */
5774 aarch64_handle_align (fragS * fragP)
5776 /* NOP = d503201f */
5777 /* AArch64 instructions are always little-endian. */
5778 static char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
5780 int bytes, fix, noop_size;
5784 if (fragP->fr_type != rs_align_code)
5787 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5788 p = fragP->fr_literal + fragP->fr_fix;
5791 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
5792 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
5795 gas_assert (fragP->tc_frag_data.recorded);
5798 noop = aarch64_noop;
5799 noop_size = sizeof (aarch64_noop);
5800 fragP->fr_var = noop_size;
5802 if (bytes & (noop_size - 1))
5804 fix = bytes & (noop_size - 1);
5806 insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
5813 while (bytes >= noop_size)
5815 memcpy (p, noop, noop_size);
5821 fragP->fr_fix += fix;
5824 /* Called from md_do_align. Used to create an alignment
5825 frag in a code section. */
5828 aarch64_frag_align_code (int n, int max)
5832 /* We assume that there will never be a requirement
5833 to support alignments greater than x bytes. */
5834 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
5836 ("alignments greater than %d bytes not supported in .text sections"),
5837 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
5839 p = frag_var (rs_align_code,
5840 MAX_MEM_FOR_RS_ALIGN_CODE,
5842 (relax_substateT) max,
5843 (symbolS *) NULL, (offsetT) n, (char *) NULL);
5847 /* Perform target specific initialisation of a frag.
5848 Note - despite the name this initialisation is not done when the frag
5849 is created, but only when its type is assigned. A frag can be created
5850 and used a long time before its type is set, so beware of assuming that
5851 this initialisationis performed first. */
5855 aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED,
5856 int max_chars ATTRIBUTE_UNUSED)
5860 #else /* OBJ_ELF is defined. */
5862 aarch64_init_frag (fragS * fragP, int max_chars)
5864 /* Record a mapping symbol for alignment frags. We will delete this
5865 later if the alignment ends up empty. */
5866 if (!fragP->tc_frag_data.recorded)
5868 fragP->tc_frag_data.recorded = 1;
5869 switch (fragP->fr_type)
5874 mapping_state_2 (MAP_DATA, max_chars);
5877 mapping_state_2 (MAP_INSN, max_chars);
5885 /* Initialize the DWARF-2 unwind information for this procedure. */
5888 tc_aarch64_frame_initial_instructions (void)
5890 cfi_add_CFA_def_cfa (REG_SP, 0);
5892 #endif /* OBJ_ELF */
5894 /* Convert REGNAME to a DWARF-2 register number. */
5897 tc_aarch64_regname_to_dw2regnum (char *regname)
5899 const reg_entry *reg = parse_reg (®name);
5905 case REG_TYPE_SP_32:
5906 case REG_TYPE_SP_64:
5921 /* Implement DWARF2_ADDR_SIZE. */
5924 aarch64_dwarf2_addr_size (void)
5926 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5930 return bfd_arch_bits_per_address (stdoutput) / 8;
5933 /* MD interface: Symbol and relocation handling. */
5935 /* Return the address within the segment that a PC-relative fixup is
5936 relative to. For AArch64 PC-relative fixups applied to instructions
5937 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
5940 md_pcrel_from_section (fixS * fixP, segT seg)
5942 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
5944 /* If this is pc-relative and we are going to emit a relocation
5945 then we just want to put out any pipeline compensation that the linker
5946 will need. Otherwise we want to use the calculated base. */
5948 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5949 || aarch64_force_relocation (fixP)))
5952 /* AArch64 should be consistent for all pc-relative relocations. */
5953 return base + AARCH64_PCREL_OFFSET;
5956 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5957 Otherwise we have no need to default values of symbols. */
5960 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5963 if (name[0] == '_' && name[1] == 'G'
5964 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5968 if (symbol_find (name))
5969 as_bad (_("GOT already in the symbol table"));
5971 GOT_symbol = symbol_new (name, undefined_section,
5972 (valueT) 0, &zero_address_frag);
5982 /* Return non-zero if the indicated VALUE has overflowed the maximum
5983 range expressible by a unsigned number with the indicated number of
5987 unsigned_overflow (valueT value, unsigned bits)
5990 if (bits >= sizeof (valueT) * 8)
5992 lim = (valueT) 1 << bits;
5993 return (value >= lim);
5997 /* Return non-zero if the indicated VALUE has overflowed the maximum
5998 range expressible by an signed number with the indicated number of
6002 signed_overflow (offsetT value, unsigned bits)
6005 if (bits >= sizeof (offsetT) * 8)
6007 lim = (offsetT) 1 << (bits - 1);
6008 return (value < -lim || value >= lim);
6011 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6012 unsigned immediate offset load/store instruction, try to encode it as
6013 an unscaled, 9-bit, signed immediate offset load/store instruction.
6014 Return TRUE if it is successful; otherwise return FALSE.
6016 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6017 in response to the standard LDR/STR mnemonics when the immediate offset is
6018 unambiguous, i.e. when it is negative or unaligned. */
6021 try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
6024 enum aarch64_op new_op;
6025 const aarch64_opcode *new_opcode;
6027 gas_assert (instr->opcode->iclass == ldst_pos);
6029 switch (instr->opcode->op)
6031 case OP_LDRB_POS:new_op = OP_LDURB; break;
6032 case OP_STRB_POS: new_op = OP_STURB; break;
6033 case OP_LDRSB_POS: new_op = OP_LDURSB; break;
6034 case OP_LDRH_POS: new_op = OP_LDURH; break;
6035 case OP_STRH_POS: new_op = OP_STURH; break;
6036 case OP_LDRSH_POS: new_op = OP_LDURSH; break;
6037 case OP_LDR_POS: new_op = OP_LDUR; break;
6038 case OP_STR_POS: new_op = OP_STUR; break;
6039 case OP_LDRF_POS: new_op = OP_LDURV; break;
6040 case OP_STRF_POS: new_op = OP_STURV; break;
6041 case OP_LDRSW_POS: new_op = OP_LDURSW; break;
6042 case OP_PRFM_POS: new_op = OP_PRFUM; break;
6043 default: new_op = OP_NIL; break;
6046 if (new_op == OP_NIL)
6049 new_opcode = aarch64_get_opcode (new_op);
6050 gas_assert (new_opcode != NULL);
6052 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6053 instr->opcode->op, new_opcode->op);
6055 aarch64_replace_opcode (instr, new_opcode);
6057 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6058 qualifier matching may fail because the out-of-date qualifier will
6059 prevent the operand being updated with a new and correct qualifier. */
6060 idx = aarch64_operand_index (instr->opcode->operands,
6061 AARCH64_OPND_ADDR_SIMM9);
6062 gas_assert (idx == 1);
6063 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
6065 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6067 if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
6073 /* Called by fix_insn to fix a MOV immediate alias instruction.
6075 Operand for a generic move immediate instruction, which is an alias
6076 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6077 a 32-bit/64-bit immediate value into general register. An assembler error
6078 shall result if the immediate cannot be created by a single one of these
6079 instructions. If there is a choice, then to ensure reversability an
6080 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6083 fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
6085 const aarch64_opcode *opcode;
6087 /* Need to check if the destination is SP/ZR. The check has to be done
6088 before any aarch64_replace_opcode. */
6089 int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]);
6090 int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]);
6092 instr->operands[1].imm.value = value;
6093 instr->operands[1].skip = 0;
6097 /* Try the MOVZ alias. */
6098 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
6099 aarch64_replace_opcode (instr, opcode);
6100 if (aarch64_opcode_encode (instr->opcode, instr,
6101 &instr->value, NULL, NULL))
6103 put_aarch64_insn (buf, instr->value);
6106 /* Try the MOVK alias. */
6107 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
6108 aarch64_replace_opcode (instr, opcode);
6109 if (aarch64_opcode_encode (instr->opcode, instr,
6110 &instr->value, NULL, NULL))
6112 put_aarch64_insn (buf, instr->value);
6117 if (try_mov_bitmask_p)
6119 /* Try the ORR alias. */
6120 opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
6121 aarch64_replace_opcode (instr, opcode);
6122 if (aarch64_opcode_encode (instr->opcode, instr,
6123 &instr->value, NULL, NULL))
6125 put_aarch64_insn (buf, instr->value);
6130 as_bad_where (fixP->fx_file, fixP->fx_line,
6131 _("immediate cannot be moved by a single instruction"));
6134 /* An instruction operand which is immediate related may have symbol used
6135 in the assembly, e.g.
6138 .set u32, 0x00ffff00
6140 At the time when the assembly instruction is parsed, a referenced symbol,
6141 like 'u32' in the above example may not have been seen; a fixS is created
6142 in such a case and is handled here after symbols have been resolved.
6143 Instruction is fixed up with VALUE using the information in *FIXP plus
6144 extra information in FLAGS.
6146 This function is called by md_apply_fix to fix up instructions that need
6147 a fix-up described above but does not involve any linker-time relocation. */
6150 fix_insn (fixS *fixP, uint32_t flags, offsetT value)
6154 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6155 enum aarch64_opnd opnd = fixP->tc_fix_data.opnd;
6156 aarch64_inst *new_inst = fixP->tc_fix_data.inst;
6160 /* Now the instruction is about to be fixed-up, so the operand that
6161 was previously marked as 'ignored' needs to be unmarked in order
6162 to get the encoding done properly. */
6163 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6164 new_inst->operands[idx].skip = 0;
6167 gas_assert (opnd != AARCH64_OPND_NIL);
6171 case AARCH64_OPND_EXCEPTION:
6172 if (unsigned_overflow (value, 16))
6173 as_bad_where (fixP->fx_file, fixP->fx_line,
6174 _("immediate out of range"));
6175 insn = get_aarch64_insn (buf);
6176 insn |= encode_svc_imm (value);
6177 put_aarch64_insn (buf, insn);
6180 case AARCH64_OPND_AIMM:
6181 /* ADD or SUB with immediate.
6182 NOTE this assumes we come here with a add/sub shifted reg encoding
6183 3 322|2222|2 2 2 21111 111111
6184 1 098|7654|3 2 1 09876 543210 98765 43210
6185 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6186 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6187 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6188 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6190 3 322|2222|2 2 221111111111
6191 1 098|7654|3 2 109876543210 98765 43210
6192 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6193 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6194 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6195 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6196 Fields sf Rn Rd are already set. */
6197 insn = get_aarch64_insn (buf);
6201 insn = reencode_addsub_switch_add_sub (insn);
6205 if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0
6206 && unsigned_overflow (value, 12))
6208 /* Try to shift the value by 12 to make it fit. */
6209 if (((value >> 12) << 12) == value
6210 && ! unsigned_overflow (value, 12 + 12))
6213 insn |= encode_addsub_imm_shift_amount (1);
6217 if (unsigned_overflow (value, 12))
6218 as_bad_where (fixP->fx_file, fixP->fx_line,
6219 _("immediate out of range"));
6221 insn |= encode_addsub_imm (value);
6223 put_aarch64_insn (buf, insn);
6226 case AARCH64_OPND_SIMD_IMM:
6227 case AARCH64_OPND_SIMD_IMM_SFT:
6228 case AARCH64_OPND_LIMM:
6229 /* Bit mask immediate. */
6230 gas_assert (new_inst != NULL);
6231 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6232 new_inst->operands[idx].imm.value = value;
6233 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6234 &new_inst->value, NULL, NULL))
6235 put_aarch64_insn (buf, new_inst->value);
6237 as_bad_where (fixP->fx_file, fixP->fx_line,
6238 _("invalid immediate"));
6241 case AARCH64_OPND_HALF:
6242 /* 16-bit unsigned immediate. */
6243 if (unsigned_overflow (value, 16))
6244 as_bad_where (fixP->fx_file, fixP->fx_line,
6245 _("immediate out of range"));
6246 insn = get_aarch64_insn (buf);
6247 insn |= encode_movw_imm (value & 0xffff);
6248 put_aarch64_insn (buf, insn);
6251 case AARCH64_OPND_IMM_MOV:
6252 /* Operand for a generic move immediate instruction, which is
6253 an alias instruction that generates a single MOVZ, MOVN or ORR
6254 instruction to loads a 32-bit/64-bit immediate value into general
6255 register. An assembler error shall result if the immediate cannot be
6256 created by a single one of these instructions. If there is a choice,
6257 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6258 and MOVZ or MOVN to ORR. */
6259 gas_assert (new_inst != NULL);
6260 fix_mov_imm_insn (fixP, buf, new_inst, value);
6263 case AARCH64_OPND_ADDR_SIMM7:
6264 case AARCH64_OPND_ADDR_SIMM9:
6265 case AARCH64_OPND_ADDR_SIMM9_2:
6266 case AARCH64_OPND_ADDR_UIMM12:
6267 /* Immediate offset in an address. */
6268 insn = get_aarch64_insn (buf);
6270 gas_assert (new_inst != NULL && new_inst->value == insn);
6271 gas_assert (new_inst->opcode->operands[1] == opnd
6272 || new_inst->opcode->operands[2] == opnd);
6274 /* Get the index of the address operand. */
6275 if (new_inst->opcode->operands[1] == opnd)
6276 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6279 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6282 /* Update the resolved offset value. */
6283 new_inst->operands[idx].addr.offset.imm = value;
6285 /* Encode/fix-up. */
6286 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6287 &new_inst->value, NULL, NULL))
6289 put_aarch64_insn (buf, new_inst->value);
6292 else if (new_inst->opcode->iclass == ldst_pos
6293 && try_to_encode_as_unscaled_ldst (new_inst))
6295 put_aarch64_insn (buf, new_inst->value);
6299 as_bad_where (fixP->fx_file, fixP->fx_line,
6300 _("immediate offset out of range"));
6305 as_fatal (_("unhandled operand code %d"), opnd);
6309 /* Apply a fixup (fixP) to segment data, once it has been determined
6310 by our caller that we have all the info we need to fix it up.
6312 Parameter valP is the pointer to the value of the bits. */
6315 md_apply_fix (fixS * fixP, valueT * valP, segT seg)
6317 offsetT value = *valP;
6319 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6321 unsigned flags = fixP->fx_addnumber;
6323 DEBUG_TRACE ("\n\n");
6324 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6325 DEBUG_TRACE ("Enter md_apply_fix");
6327 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
6329 /* Note whether this will delete the relocation. */
6331 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
6334 /* Process the relocations. */
6335 switch (fixP->fx_r_type)
6337 case BFD_RELOC_NONE:
6338 /* This will need to go in the object file. */
6343 case BFD_RELOC_8_PCREL:
6344 if (fixP->fx_done || !seg->use_rela_p)
6345 md_number_to_chars (buf, value, 1);
6349 case BFD_RELOC_16_PCREL:
6350 if (fixP->fx_done || !seg->use_rela_p)
6351 md_number_to_chars (buf, value, 2);
6355 case BFD_RELOC_32_PCREL:
6356 if (fixP->fx_done || !seg->use_rela_p)
6357 md_number_to_chars (buf, value, 4);
6361 case BFD_RELOC_64_PCREL:
6362 if (fixP->fx_done || !seg->use_rela_p)
6363 md_number_to_chars (buf, value, 8);
6366 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
6367 /* We claim that these fixups have been processed here, even if
6368 in fact we generate an error because we do not have a reloc
6369 for them, so tc_gen_reloc() will reject them. */
6371 if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy))
6373 as_bad_where (fixP->fx_file, fixP->fx_line,
6374 _("undefined symbol %s used as an immediate value"),
6375 S_GET_NAME (fixP->fx_addsy));
6376 goto apply_fix_return;
6378 fix_insn (fixP, flags, value);
6381 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
6382 if (fixP->fx_done || !seg->use_rela_p)
6385 as_bad_where (fixP->fx_file, fixP->fx_line,
6386 _("pc-relative load offset not word aligned"));
6387 if (signed_overflow (value, 21))
6388 as_bad_where (fixP->fx_file, fixP->fx_line,
6389 _("pc-relative load offset out of range"));
6390 insn = get_aarch64_insn (buf);
6391 insn |= encode_ld_lit_ofs_19 (value >> 2);
6392 put_aarch64_insn (buf, insn);
6396 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
6397 if (fixP->fx_done || !seg->use_rela_p)
6399 if (signed_overflow (value, 21))
6400 as_bad_where (fixP->fx_file, fixP->fx_line,
6401 _("pc-relative address offset out of range"));
6402 insn = get_aarch64_insn (buf);
6403 insn |= encode_adr_imm (value);
6404 put_aarch64_insn (buf, insn);
6408 case BFD_RELOC_AARCH64_BRANCH19:
6409 if (fixP->fx_done || !seg->use_rela_p)
6412 as_bad_where (fixP->fx_file, fixP->fx_line,
6413 _("conditional branch target not word aligned"));
6414 if (signed_overflow (value, 21))
6415 as_bad_where (fixP->fx_file, fixP->fx_line,
6416 _("conditional branch out of range"));
6417 insn = get_aarch64_insn (buf);
6418 insn |= encode_cond_branch_ofs_19 (value >> 2);
6419 put_aarch64_insn (buf, insn);
6423 case BFD_RELOC_AARCH64_TSTBR14:
6424 if (fixP->fx_done || !seg->use_rela_p)
6427 as_bad_where (fixP->fx_file, fixP->fx_line,
6428 _("conditional branch target not word aligned"));
6429 if (signed_overflow (value, 16))
6430 as_bad_where (fixP->fx_file, fixP->fx_line,
6431 _("conditional branch out of range"));
6432 insn = get_aarch64_insn (buf);
6433 insn |= encode_tst_branch_ofs_14 (value >> 2);
6434 put_aarch64_insn (buf, insn);
6438 case BFD_RELOC_AARCH64_JUMP26:
6439 case BFD_RELOC_AARCH64_CALL26:
6440 if (fixP->fx_done || !seg->use_rela_p)
6443 as_bad_where (fixP->fx_file, fixP->fx_line,
6444 _("branch target not word aligned"));
6445 if (signed_overflow (value, 28))
6446 as_bad_where (fixP->fx_file, fixP->fx_line,
6447 _("branch out of range"));
6448 insn = get_aarch64_insn (buf);
6449 insn |= encode_branch_ofs_26 (value >> 2);
6450 put_aarch64_insn (buf, insn);
6454 case BFD_RELOC_AARCH64_MOVW_G0:
6455 case BFD_RELOC_AARCH64_MOVW_G0_S:
6456 case BFD_RELOC_AARCH64_MOVW_G0_NC:
6459 case BFD_RELOC_AARCH64_MOVW_G1:
6460 case BFD_RELOC_AARCH64_MOVW_G1_S:
6461 case BFD_RELOC_AARCH64_MOVW_G1_NC:
6464 case BFD_RELOC_AARCH64_MOVW_G2:
6465 case BFD_RELOC_AARCH64_MOVW_G2_S:
6466 case BFD_RELOC_AARCH64_MOVW_G2_NC:
6469 case BFD_RELOC_AARCH64_MOVW_G3:
6472 if (fixP->fx_done || !seg->use_rela_p)
6474 insn = get_aarch64_insn (buf);
6478 /* REL signed addend must fit in 16 bits */
6479 if (signed_overflow (value, 16))
6480 as_bad_where (fixP->fx_file, fixP->fx_line,
6481 _("offset out of range"));
6485 /* Check for overflow and scale. */
6486 switch (fixP->fx_r_type)
6488 case BFD_RELOC_AARCH64_MOVW_G0:
6489 case BFD_RELOC_AARCH64_MOVW_G1:
6490 case BFD_RELOC_AARCH64_MOVW_G2:
6491 case BFD_RELOC_AARCH64_MOVW_G3:
6492 if (unsigned_overflow (value, scale + 16))
6493 as_bad_where (fixP->fx_file, fixP->fx_line,
6494 _("unsigned value out of range"));
6496 case BFD_RELOC_AARCH64_MOVW_G0_S:
6497 case BFD_RELOC_AARCH64_MOVW_G1_S:
6498 case BFD_RELOC_AARCH64_MOVW_G2_S:
6499 /* NOTE: We can only come here with movz or movn. */
6500 if (signed_overflow (value, scale + 16))
6501 as_bad_where (fixP->fx_file, fixP->fx_line,
6502 _("signed value out of range"));
6505 /* Force use of MOVN. */
6507 insn = reencode_movzn_to_movn (insn);
6511 /* Force use of MOVZ. */
6512 insn = reencode_movzn_to_movz (insn);
6516 /* Unchecked relocations. */
6522 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6523 insn |= encode_movw_imm (value & 0xffff);
6525 put_aarch64_insn (buf, insn);
6529 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
6530 fixP->fx_r_type = (ilp32_p
6531 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6532 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);
6533 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6534 /* Should always be exported to object file, see
6535 aarch64_force_relocation(). */
6536 gas_assert (!fixP->fx_done);
6537 gas_assert (seg->use_rela_p);
6540 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
6541 fixP->fx_r_type = (ilp32_p
6542 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6543 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC);
6544 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6545 /* Should always be exported to object file, see
6546 aarch64_force_relocation(). */
6547 gas_assert (!fixP->fx_done);
6548 gas_assert (seg->use_rela_p);
6551 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
6552 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
6553 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
6554 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
6555 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
6556 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
6557 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
6558 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
6559 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
6560 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
6561 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
6562 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
6563 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
6564 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
6565 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
6566 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
6567 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
6568 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6569 /* Should always be exported to object file, see
6570 aarch64_force_relocation(). */
6571 gas_assert (!fixP->fx_done);
6572 gas_assert (seg->use_rela_p);
6575 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
6576 /* Should always be exported to object file, see
6577 aarch64_force_relocation(). */
6578 fixP->fx_r_type = (ilp32_p
6579 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6580 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC);
6581 gas_assert (!fixP->fx_done);
6582 gas_assert (seg->use_rela_p);
6585 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
6586 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
6587 case BFD_RELOC_AARCH64_ADD_LO12:
6588 case BFD_RELOC_AARCH64_LDST8_LO12:
6589 case BFD_RELOC_AARCH64_LDST16_LO12:
6590 case BFD_RELOC_AARCH64_LDST32_LO12:
6591 case BFD_RELOC_AARCH64_LDST64_LO12:
6592 case BFD_RELOC_AARCH64_LDST128_LO12:
6593 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
6594 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
6595 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
6596 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
6597 /* Should always be exported to object file, see
6598 aarch64_force_relocation(). */
6599 gas_assert (!fixP->fx_done);
6600 gas_assert (seg->use_rela_p);
6603 case BFD_RELOC_AARCH64_TLSDESC_ADD:
6604 case BFD_RELOC_AARCH64_TLSDESC_LDR:
6605 case BFD_RELOC_AARCH64_TLSDESC_CALL:
6609 as_bad_where (fixP->fx_file, fixP->fx_line,
6610 _("unexpected %s fixup"),
6611 bfd_get_reloc_code_name (fixP->fx_r_type));
6616 /* Free the allocated the struct aarch64_inst.
6617 N.B. currently there are very limited number of fix-up types actually use
6618 this field, so the impact on the performance should be minimal . */
6619 if (fixP->tc_fix_data.inst != NULL)
6620 free (fixP->tc_fix_data.inst);
6625 /* Translate internal representation of relocation info to BFD target
6629 tc_gen_reloc (asection * section, fixS * fixp)
6632 bfd_reloc_code_real_type code;
6634 reloc = xmalloc (sizeof (arelent));
6636 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
6637 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6638 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6642 if (section->use_rela_p)
6643 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
6645 fixp->fx_offset = reloc->address;
6647 reloc->addend = fixp->fx_offset;
6649 code = fixp->fx_r_type;
6654 code = BFD_RELOC_16_PCREL;
6659 code = BFD_RELOC_32_PCREL;
6664 code = BFD_RELOC_64_PCREL;
6671 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6672 if (reloc->howto == NULL)
6674 as_bad_where (fixp->fx_file, fixp->fx_line,
6676 ("cannot represent %s relocation in this object file format"),
6677 bfd_get_reloc_code_name (code));
6684 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6687 cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp)
6689 bfd_reloc_code_real_type type;
6693 FIXME: @@ Should look at CPU word size. */
6700 type = BFD_RELOC_16;
6703 type = BFD_RELOC_32;
6706 type = BFD_RELOC_64;
6709 as_bad (_("cannot do %u-byte relocation"), size);
6710 type = BFD_RELOC_UNUSED;
6714 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6718 aarch64_force_relocation (struct fix *fixp)
6720 switch (fixp->fx_r_type)
6722 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
6723 /* Perform these "immediate" internal relocations
6724 even if the symbol is extern or weak. */
6727 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
6728 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
6729 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
6730 /* Pseudo relocs that need to be fixed up according to
6734 case BFD_RELOC_AARCH64_ADD_LO12:
6735 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
6736 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
6737 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
6738 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
6739 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
6740 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
6741 case BFD_RELOC_AARCH64_LDST128_LO12:
6742 case BFD_RELOC_AARCH64_LDST16_LO12:
6743 case BFD_RELOC_AARCH64_LDST32_LO12:
6744 case BFD_RELOC_AARCH64_LDST64_LO12:
6745 case BFD_RELOC_AARCH64_LDST8_LO12:
6746 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
6747 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
6748 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
6749 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
6750 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
6751 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
6752 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
6753 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
6754 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
6755 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
6756 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
6757 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
6758 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
6759 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
6760 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
6761 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
6762 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
6763 /* Always leave these relocations for the linker. */
6770 return generic_force_reloc (fixp);
6776 elf64_aarch64_target_format (void)
6778 if (target_big_endian)
6779 return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
6781 return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";
6785 aarch64elf_frob_symbol (symbolS * symp, int *puntp)
6787 elf_frob_symbol (symp, puntp);
6791 /* MD interface: Finalization. */
6793 /* A good place to do this, although this was probably not intended
6794 for this kind of use. We need to dump the literal pool before
6795 references are made to a null symbol pointer. */
6798 aarch64_cleanup (void)
6802 for (pool = list_of_pools; pool; pool = pool->next)
6804 /* Put it at the end of the relevant section. */
6805 subseg_set (pool->section, pool->sub_section);
6811 /* Remove any excess mapping symbols generated for alignment frags in
6812 SEC. We may have created a mapping symbol before a zero byte
6813 alignment; remove it if there's a mapping symbol after the
6816 check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec,
6817 void *dummy ATTRIBUTE_UNUSED)
6819 segment_info_type *seginfo = seg_info (sec);
6822 if (seginfo == NULL || seginfo->frchainP == NULL)
6825 for (fragp = seginfo->frchainP->frch_root;
6826 fragp != NULL; fragp = fragp->fr_next)
6828 symbolS *sym = fragp->tc_frag_data.last_map;
6829 fragS *next = fragp->fr_next;
6831 /* Variable-sized frags have been converted to fixed size by
6832 this point. But if this was variable-sized to start with,
6833 there will be a fixed-size frag after it. So don't handle
6835 if (sym == NULL || next == NULL)
6838 if (S_GET_VALUE (sym) < next->fr_address)
6839 /* Not at the end of this frag. */
6841 know (S_GET_VALUE (sym) == next->fr_address);
6845 if (next->tc_frag_data.first_map != NULL)
6847 /* Next frag starts with a mapping symbol. Discard this
6849 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
6853 if (next->fr_next == NULL)
6855 /* This mapping symbol is at the end of the section. Discard
6857 know (next->fr_fix == 0 && next->fr_var == 0);
6858 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
6862 /* As long as we have empty frags without any mapping symbols,
6864 /* If the next frag is non-empty and does not start with a
6865 mapping symbol, then this mapping symbol is required. */
6866 if (next->fr_address != next->fr_next->fr_address)
6869 next = next->fr_next;
6871 while (next != NULL);
6876 /* Adjust the symbol table. */
6879 aarch64_adjust_symtab (void)
6882 /* Remove any overlapping mapping symbols generated by alignment frags. */
6883 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
6884 /* Now do generic ELF adjustments. */
6885 elf_adjust_symtab ();
6890 checked_hash_insert (struct hash_control *table, const char *key, void *value)
6892 const char *hash_err;
6894 hash_err = hash_insert (table, key, value);
6896 printf ("Internal Error: Can't hash %s\n", key);
6900 fill_instruction_hash_table (void)
6902 aarch64_opcode *opcode = aarch64_opcode_table;
6904 while (opcode->name != NULL)
6906 templates *templ, *new_templ;
6907 templ = hash_find (aarch64_ops_hsh, opcode->name);
6909 new_templ = (templates *) xmalloc (sizeof (templates));
6910 new_templ->opcode = opcode;
6911 new_templ->next = NULL;
6914 checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ);
6917 new_templ->next = templ->next;
6918 templ->next = new_templ;
6925 convert_to_upper (char *dst, const char *src, size_t num)
6928 for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src)
6929 *dst = TOUPPER (*src);
6933 /* Assume STR point to a lower-case string, allocate, convert and return
6934 the corresponding upper-case string. */
6935 static inline const char*
6936 get_upper_str (const char *str)
6939 size_t len = strlen (str);
6940 if ((ret = xmalloc (len + 1)) == NULL)
6942 convert_to_upper (ret, str, len);
6946 /* MD interface: Initialization. */
6954 if ((aarch64_ops_hsh = hash_new ()) == NULL
6955 || (aarch64_cond_hsh = hash_new ()) == NULL
6956 || (aarch64_shift_hsh = hash_new ()) == NULL
6957 || (aarch64_sys_regs_hsh = hash_new ()) == NULL
6958 || (aarch64_pstatefield_hsh = hash_new ()) == NULL
6959 || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
6960 || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
6961 || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
6962 || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
6963 || (aarch64_reg_hsh = hash_new ()) == NULL
6964 || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
6965 || (aarch64_nzcv_hsh = hash_new ()) == NULL
6966 || (aarch64_pldop_hsh = hash_new ()) == NULL)
6967 as_fatal (_("virtual memory exhausted"));
6969 fill_instruction_hash_table ();
6971 for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
6972 checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
6973 (void *) (aarch64_sys_regs + i));
6975 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
6976 checked_hash_insert (aarch64_pstatefield_hsh,
6977 aarch64_pstatefields[i].name,
6978 (void *) (aarch64_pstatefields + i));
6980 for (i = 0; aarch64_sys_regs_ic[i].template != NULL; i++)
6981 checked_hash_insert (aarch64_sys_regs_ic_hsh,
6982 aarch64_sys_regs_ic[i].template,
6983 (void *) (aarch64_sys_regs_ic + i));
6985 for (i = 0; aarch64_sys_regs_dc[i].template != NULL; i++)
6986 checked_hash_insert (aarch64_sys_regs_dc_hsh,
6987 aarch64_sys_regs_dc[i].template,
6988 (void *) (aarch64_sys_regs_dc + i));
6990 for (i = 0; aarch64_sys_regs_at[i].template != NULL; i++)
6991 checked_hash_insert (aarch64_sys_regs_at_hsh,
6992 aarch64_sys_regs_at[i].template,
6993 (void *) (aarch64_sys_regs_at + i));
6995 for (i = 0; aarch64_sys_regs_tlbi[i].template != NULL; i++)
6996 checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
6997 aarch64_sys_regs_tlbi[i].template,
6998 (void *) (aarch64_sys_regs_tlbi + i));
7000 for (i = 0; i < ARRAY_SIZE (reg_names); i++)
7001 checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
7002 (void *) (reg_names + i));
7004 for (i = 0; i < ARRAY_SIZE (nzcv_names); i++)
7005 checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template,
7006 (void *) (nzcv_names + i));
7008 for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++)
7010 const char *name = aarch64_operand_modifiers[i].name;
7011 checked_hash_insert (aarch64_shift_hsh, name,
7012 (void *) (aarch64_operand_modifiers + i));
7013 /* Also hash the name in the upper case. */
7014 checked_hash_insert (aarch64_shift_hsh, get_upper_str (name),
7015 (void *) (aarch64_operand_modifiers + i));
7018 for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++)
7021 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7022 the same condition code. */
7023 for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j)
7025 const char *name = aarch64_conds[i].names[j];
7028 checked_hash_insert (aarch64_cond_hsh, name,
7029 (void *) (aarch64_conds + i));
7030 /* Also hash the name in the upper case. */
7031 checked_hash_insert (aarch64_cond_hsh, get_upper_str (name),
7032 (void *) (aarch64_conds + i));
7036 for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++)
7038 const char *name = aarch64_barrier_options[i].name;
7039 /* Skip xx00 - the unallocated values of option. */
7042 checked_hash_insert (aarch64_barrier_opt_hsh, name,
7043 (void *) (aarch64_barrier_options + i));
7044 /* Also hash the name in the upper case. */
7045 checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
7046 (void *) (aarch64_barrier_options + i));
7049 for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
7051 const char* name = aarch64_prfops[i].name;
7052 /* Skip the unallocated hint encodings. */
7055 checked_hash_insert (aarch64_pldop_hsh, name,
7056 (void *) (aarch64_prfops + i));
7057 /* Also hash the name in the upper case. */
7058 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
7059 (void *) (aarch64_prfops + i));
7062 /* Set the cpu variant based on the command-line options. */
7064 mcpu_cpu_opt = march_cpu_opt;
7067 mcpu_cpu_opt = &cpu_default;
7069 cpu_variant = *mcpu_cpu_opt;
7071 /* Record the CPU type. */
7072 mach = ilp32_p ? bfd_mach_aarch64_ilp32 : bfd_mach_aarch64;
7074 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
7077 /* Command line processing. */
7079 const char *md_shortopts = "m:";
7081 #ifdef AARCH64_BI_ENDIAN
7082 #define OPTION_EB (OPTION_MD_BASE + 0)
7083 #define OPTION_EL (OPTION_MD_BASE + 1)
7085 #if TARGET_BYTES_BIG_ENDIAN
7086 #define OPTION_EB (OPTION_MD_BASE + 0)
7088 #define OPTION_EL (OPTION_MD_BASE + 1)
7092 struct option md_longopts[] = {
7094 {"EB", no_argument, NULL, OPTION_EB},
7097 {"EL", no_argument, NULL, OPTION_EL},
7099 {NULL, no_argument, NULL, 0}
7102 size_t md_longopts_size = sizeof (md_longopts);
7104 struct aarch64_option_table
7106 char *option; /* Option name to match. */
7107 char *help; /* Help information. */
7108 int *var; /* Variable to change. */
7109 int value; /* What to change it to. */
7110 char *deprecated; /* If non-null, print this message. */
7113 static struct aarch64_option_table aarch64_opts[] = {
7114 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
7115 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
7117 #ifdef DEBUG_AARCH64
7118 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL},
7119 #endif /* DEBUG_AARCH64 */
7120 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1,
7122 {NULL, NULL, NULL, 0, NULL}
7125 struct aarch64_cpu_option_table
7128 const aarch64_feature_set value;
7129 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7131 const char *canonical_name;
7134 /* This list should, at a minimum, contain all the cpu names
7135 recognized by GCC. */
7136 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
7137 {"all", AARCH64_ANY, NULL},
7138 {"cortex-a53", AARCH64_ARCH_V8, "Cortex-A53"},
7139 {"cortex-a57", AARCH64_ARCH_V8, "Cortex-A57"},
7140 {"generic", AARCH64_ARCH_V8, NULL},
7142 /* These two are example CPUs supported in GCC, once we have real
7143 CPUs they will be removed. */
7144 {"example-1", AARCH64_ARCH_V8, NULL},
7145 {"example-2", AARCH64_ARCH_V8, NULL},
7147 {NULL, AARCH64_ARCH_NONE, NULL}
7150 struct aarch64_arch_option_table
7153 const aarch64_feature_set value;
7156 /* This list should, at a minimum, contain all the architecture names
7157 recognized by GCC. */
7158 static const struct aarch64_arch_option_table aarch64_archs[] = {
7159 {"all", AARCH64_ANY},
7160 {"armv8-a", AARCH64_ARCH_V8},
7161 {NULL, AARCH64_ARCH_NONE}
7164 /* ISA extensions. */
7165 struct aarch64_option_cpu_value_table
7168 const aarch64_feature_set value;
7171 static const struct aarch64_option_cpu_value_table aarch64_features[] = {
7172 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0)},
7173 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0)},
7174 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
7175 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
7176 {NULL, AARCH64_ARCH_NONE}
7179 struct aarch64_long_option_table
7181 char *option; /* Substring to match. */
7182 char *help; /* Help information. */
7183 int (*func) (char *subopt); /* Function to decode sub-option. */
7184 char *deprecated; /* If non-null, print this message. */
7188 aarch64_parse_features (char *str, const aarch64_feature_set **opt_p)
7190 /* We insist on extensions being added before being removed. We achieve
7191 this by using the ADDING_VALUE variable to indicate whether we are
7192 adding an extension (1) or removing it (0) and only allowing it to
7193 change in the order -1 -> 1 -> 0. */
7194 int adding_value = -1;
7195 aarch64_feature_set *ext_set = xmalloc (sizeof (aarch64_feature_set));
7197 /* Copy the feature set, so that we can modify it. */
7201 while (str != NULL && *str != 0)
7203 const struct aarch64_option_cpu_value_table *opt;
7209 as_bad (_("invalid architectural extension"));
7214 ext = strchr (str, '+');
7219 optlen = strlen (str);
7221 if (optlen >= 2 && strncmp (str, "no", 2) == 0)
7223 if (adding_value != 0)
7228 else if (optlen > 0)
7230 if (adding_value == -1)
7232 else if (adding_value != 1)
7234 as_bad (_("must specify extensions to add before specifying "
7235 "those to remove"));
7242 as_bad (_("missing architectural extension"));
7246 gas_assert (adding_value != -1);
7248 for (opt = aarch64_features; opt->name != NULL; opt++)
7249 if (strncmp (opt->name, str, optlen) == 0)
7251 /* Add or remove the extension. */
7253 AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
7255 AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
7259 if (opt->name == NULL)
7261 as_bad (_("unknown architectural extension `%s'"), str);
7272 aarch64_parse_cpu (char *str)
7274 const struct aarch64_cpu_option_table *opt;
7275 char *ext = strchr (str, '+');
7281 optlen = strlen (str);
7285 as_bad (_("missing cpu name `%s'"), str);
7289 for (opt = aarch64_cpus; opt->name != NULL; opt++)
7290 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7292 mcpu_cpu_opt = &opt->value;
7294 return aarch64_parse_features (ext, &mcpu_cpu_opt);
7299 as_bad (_("unknown cpu `%s'"), str);
7304 aarch64_parse_arch (char *str)
7306 const struct aarch64_arch_option_table *opt;
7307 char *ext = strchr (str, '+');
7313 optlen = strlen (str);
7317 as_bad (_("missing architecture name `%s'"), str);
7321 for (opt = aarch64_archs; opt->name != NULL; opt++)
7322 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7324 march_cpu_opt = &opt->value;
7326 return aarch64_parse_features (ext, &march_cpu_opt);
7331 as_bad (_("unknown architecture `%s'\n"), str);
7336 struct aarch64_option_abi_value_table
7339 enum aarch64_abi_type value;
7342 static const struct aarch64_option_abi_value_table aarch64_abis[] = {
7343 {"ilp32", AARCH64_ABI_ILP32},
7344 {"lp64", AARCH64_ABI_LP64},
7349 aarch64_parse_abi (char *str)
7351 const struct aarch64_option_abi_value_table *opt;
7352 size_t optlen = strlen (str);
7356 as_bad (_("missing abi name `%s'"), str);
7360 for (opt = aarch64_abis; opt->name != NULL; opt++)
7361 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7363 aarch64_abi = opt->value;
7367 as_bad (_("unknown abi `%s'\n"), str);
7371 static struct aarch64_long_option_table aarch64_long_opts[] = {
7373 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
7374 aarch64_parse_abi, NULL},
7375 #endif /* OBJ_ELF */
7376 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7377 aarch64_parse_cpu, NULL},
7378 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7379 aarch64_parse_arch, NULL},
7380 {NULL, NULL, 0, NULL}
7384 md_parse_option (int c, char *arg)
7386 struct aarch64_option_table *opt;
7387 struct aarch64_long_option_table *lopt;
7393 target_big_endian = 1;
7399 target_big_endian = 0;
7404 /* Listing option. Just ignore these, we don't support additional
7409 for (opt = aarch64_opts; opt->option != NULL; opt++)
7411 if (c == opt->option[0]
7412 && ((arg == NULL && opt->option[1] == 0)
7413 || streq (arg, opt->option + 1)))
7415 /* If the option is deprecated, tell the user. */
7416 if (opt->deprecated != NULL)
7417 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
7418 arg ? arg : "", _(opt->deprecated));
7420 if (opt->var != NULL)
7421 *opt->var = opt->value;
7427 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
7429 /* These options are expected to have an argument. */
7430 if (c == lopt->option[0]
7432 && strncmp (arg, lopt->option + 1,
7433 strlen (lopt->option + 1)) == 0)
7435 /* If the option is deprecated, tell the user. */
7436 if (lopt->deprecated != NULL)
7437 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
7438 _(lopt->deprecated));
7440 /* Call the sup-option parser. */
7441 return lopt->func (arg + strlen (lopt->option) - 1);
7452 md_show_usage (FILE * fp)
7454 struct aarch64_option_table *opt;
7455 struct aarch64_long_option_table *lopt;
7457 fprintf (fp, _(" AArch64-specific assembler options:\n"));
7459 for (opt = aarch64_opts; opt->option != NULL; opt++)
7460 if (opt->help != NULL)
7461 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
7463 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
7464 if (lopt->help != NULL)
7465 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
7469 -EB assemble code for a big-endian cpu\n"));
7474 -EL assemble code for a little-endian cpu\n"));
7478 /* Parse a .cpu directive. */
7481 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
7483 const struct aarch64_cpu_option_table *opt;
7489 name = input_line_pointer;
7490 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7491 input_line_pointer++;
7492 saved_char = *input_line_pointer;
7493 *input_line_pointer = 0;
7495 ext = strchr (name, '+');
7498 optlen = ext - name;
7500 optlen = strlen (name);
7502 /* Skip the first "all" entry. */
7503 for (opt = aarch64_cpus + 1; opt->name != NULL; opt++)
7504 if (strlen (opt->name) == optlen
7505 && strncmp (name, opt->name, optlen) == 0)
7507 mcpu_cpu_opt = &opt->value;
7509 if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
7512 cpu_variant = *mcpu_cpu_opt;
7514 *input_line_pointer = saved_char;
7515 demand_empty_rest_of_line ();
7518 as_bad (_("unknown cpu `%s'"), name);
7519 *input_line_pointer = saved_char;
7520 ignore_rest_of_line ();
7524 /* Parse a .arch directive. */
7527 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
7529 const struct aarch64_arch_option_table *opt;
7535 name = input_line_pointer;
7536 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7537 input_line_pointer++;
7538 saved_char = *input_line_pointer;
7539 *input_line_pointer = 0;
7541 ext = strchr (name, '+');
7544 optlen = ext - name;
7546 optlen = strlen (name);
7548 /* Skip the first "all" entry. */
7549 for (opt = aarch64_archs + 1; opt->name != NULL; opt++)
7550 if (strlen (opt->name) == optlen
7551 && strncmp (name, opt->name, optlen) == 0)
7553 mcpu_cpu_opt = &opt->value;
7555 if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
7558 cpu_variant = *mcpu_cpu_opt;
7560 *input_line_pointer = saved_char;
7561 demand_empty_rest_of_line ();
7565 as_bad (_("unknown architecture `%s'\n"), name);
7566 *input_line_pointer = saved_char;
7567 ignore_rest_of_line ();
7570 /* Copy symbol information. */
7573 aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
7575 AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);