1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set *mcpu_cpu_opt = NULL;
53 static const aarch64_feature_set *march_cpu_opt = NULL;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default = CPU_DEFAULT;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS *GOT_symbol;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_LP64;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in vector_type_el. */
91 #define NTA_HASINDEX 2
95 enum vector_el_type type;
96 unsigned char defined;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type;
108 enum aarch64_opnd opnd;
110 unsigned need_libopcodes_p : 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool : 1;
131 typedef struct aarch64_instruction aarch64_instruction;
133 static aarch64_instruction inst;
135 static bfd_boolean parse_operands (char *, const aarch64_opcode *);
136 static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst.parsing_error.kind = AARCH64_OPDE_NIL;
159 inst.parsing_error.error = NULL;
162 static inline bfd_boolean
165 return inst.parsing_error.kind != AARCH64_OPDE_NIL;
168 static inline const char *
169 get_error_message (void)
171 return inst.parsing_error.error;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst.parsing_error.kind;
181 set_error (enum aarch64_operand_error_kind kind, const char *error)
183 inst.parsing_error.kind = kind;
184 inst.parsing_error.error = error;
188 set_recoverable_error (const char *error)
190 set_error (AARCH64_OPDE_RECOVERABLE, error);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
202 set_syntax_error (const char *error)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
208 set_first_syntax_error (const char *error)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
215 set_fatal_syntax_error (const char *error)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc;
250 /* Macros to define the register types and masks for the purpose
253 #undef AARCH64_REG_TYPES
254 #define AARCH64_REG_TYPES \
255 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
256 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
257 BASIC_REG_TYPE(SP_32) /* wsp */ \
258 BASIC_REG_TYPE(SP_64) /* sp */ \
259 BASIC_REG_TYPE(Z_32) /* wzr */ \
260 BASIC_REG_TYPE(Z_64) /* xzr */ \
261 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
262 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
263 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
264 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
265 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
266 BASIC_REG_TYPE(CN) /* c[0-7] */ \
267 BASIC_REG_TYPE(VN) /* v[0-31] */ \
268 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
269 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
270 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
271 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
272 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
273 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
274 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
275 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
276 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
277 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
278 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
279 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
280 /* Typecheck: any [BHSDQ]P FP. */ \
281 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
282 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
283 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
284 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
285 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
286 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
287 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
288 /* Any integer register; used for error messages only. */ \
289 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
290 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
291 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
292 /* Pseudo type to mark the end of the enumerator sequence. */ \
295 #undef BASIC_REG_TYPE
296 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
297 #undef MULTI_REG_TYPE
298 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
300 /* Register type enumerators. */
301 typedef enum aarch64_reg_type_
303 /* A list of REG_TYPE_*. */
307 #undef BASIC_REG_TYPE
308 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
310 #define REG_TYPE(T) (1 << REG_TYPE_##T)
311 #undef MULTI_REG_TYPE
312 #define MULTI_REG_TYPE(T,V) V,
314 /* Structure for a hash table entry for a register. */
318 unsigned char number;
319 ENUM_BITFIELD (aarch64_reg_type_) type : 8;
320 unsigned char builtin;
323 /* Values indexed by aarch64_reg_type to assist the type checking. */
324 static const unsigned reg_type_masks[] =
329 #undef BASIC_REG_TYPE
331 #undef MULTI_REG_TYPE
332 #undef AARCH64_REG_TYPES
334 /* Diagnostics used when we don't get a register of the expected type.
335 Note: this has to synchronized with aarch64_reg_type definitions
338 get_reg_expected_msg (aarch64_reg_type reg_type)
345 msg = N_("integer 32-bit register expected");
348 msg = N_("integer 64-bit register expected");
351 msg = N_("integer register expected");
353 case REG_TYPE_R64_SP:
354 msg = N_("64-bit integer or SP register expected");
357 msg = N_("integer or zero register expected");
360 msg = N_("integer or SP register expected");
362 case REG_TYPE_R_Z_SP:
363 msg = N_("integer, zero or SP register expected");
366 msg = N_("8-bit SIMD scalar register expected");
369 msg = N_("16-bit SIMD scalar or floating-point half precision "
370 "register expected");
373 msg = N_("32-bit SIMD scalar or floating-point single precision "
374 "register expected");
377 msg = N_("64-bit SIMD scalar or floating-point double precision "
378 "register expected");
381 msg = N_("128-bit SIMD scalar or floating-point quad precision "
382 "register expected");
385 msg = N_("C0 - C15 expected");
387 case REG_TYPE_R_Z_BHSDQ_V:
388 msg = N_("register expected");
390 case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
391 msg = N_("SIMD scalar or floating-point register expected");
393 case REG_TYPE_VN: /* any V reg */
394 msg = N_("vector register expected");
397 as_fatal (_("invalid register type %d"), reg_type);
402 /* Some well known registers that we refer to directly elsewhere. */
405 /* Instructions take 4 bytes in the object file. */
408 static struct hash_control *aarch64_ops_hsh;
409 static struct hash_control *aarch64_cond_hsh;
410 static struct hash_control *aarch64_shift_hsh;
411 static struct hash_control *aarch64_sys_regs_hsh;
412 static struct hash_control *aarch64_pstatefield_hsh;
413 static struct hash_control *aarch64_sys_regs_ic_hsh;
414 static struct hash_control *aarch64_sys_regs_dc_hsh;
415 static struct hash_control *aarch64_sys_regs_at_hsh;
416 static struct hash_control *aarch64_sys_regs_tlbi_hsh;
417 static struct hash_control *aarch64_reg_hsh;
418 static struct hash_control *aarch64_barrier_opt_hsh;
419 static struct hash_control *aarch64_nzcv_hsh;
420 static struct hash_control *aarch64_pldop_hsh;
421 static struct hash_control *aarch64_hint_opt_hsh;
423 /* Stuff needed to resolve the label ambiguity
432 static symbolS *last_label_seen;
434 /* Literal pool structure. Held on a per-section
435 and per-sub-section basis. */
437 #define MAX_LITERAL_POOL_SIZE 1024
438 typedef struct literal_expression
441 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
442 LITTLENUM_TYPE * bignum;
443 } literal_expression;
445 typedef struct literal_pool
447 literal_expression literals[MAX_LITERAL_POOL_SIZE];
448 unsigned int next_free_entry;
454 struct literal_pool *next;
457 /* Pointer to a linked list of literal pools. */
458 static literal_pool *list_of_pools = NULL;
462 /* This array holds the chars that always start a comment. If the
463 pre-processor is disabled, these aren't very useful. */
464 const char comment_chars[] = "";
466 /* This array holds the chars that only start a comment at the beginning of
467 a line. If the line seems to have the form '# 123 filename'
468 .line and .file directives will appear in the pre-processed output. */
469 /* Note that input_file.c hand checks for '#' at the beginning of the
470 first line of the input file. This is because the compiler outputs
471 #NO_APP at the beginning of its output. */
472 /* Also note that comments like this one will always work. */
473 const char line_comment_chars[] = "#";
475 const char line_separator_chars[] = ";";
477 /* Chars that can be used to separate mant
478 from exp in floating point numbers. */
479 const char EXP_CHARS[] = "eE";
481 /* Chars that mean this number is a floating point constant. */
485 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
487 /* Prefix character that indicates the start of an immediate value. */
488 #define is_immediate_prefix(C) ((C) == '#')
490 /* Separator character handling. */
492 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
494 static inline bfd_boolean
495 skip_past_char (char **str, char c)
506 #define skip_past_comma(str) skip_past_char (str, ',')
508 /* Arithmetic expressions (possibly involving symbols). */
510 static bfd_boolean in_my_get_expression_p = FALSE;
512 /* Third argument to my_get_expression. */
513 #define GE_NO_PREFIX 0
514 #define GE_OPT_PREFIX 1
516 /* Return TRUE if the string pointed by *STR is successfully parsed
517 as an valid expression; *EP will be filled with the information of
518 such an expression. Otherwise return FALSE. */
521 my_get_expression (expressionS * ep, char **str, int prefix_mode,
526 int prefix_present_p = 0;
533 if (is_immediate_prefix (**str))
536 prefix_present_p = 1;
543 memset (ep, 0, sizeof (expressionS));
545 save_in = input_line_pointer;
546 input_line_pointer = *str;
547 in_my_get_expression_p = TRUE;
548 seg = expression (ep);
549 in_my_get_expression_p = FALSE;
551 if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
553 /* We found a bad expression in md_operand(). */
554 *str = input_line_pointer;
555 input_line_pointer = save_in;
556 if (prefix_present_p && ! error_p ())
557 set_fatal_syntax_error (_("bad expression"));
559 set_first_syntax_error (_("bad expression"));
564 if (seg != absolute_section
565 && seg != text_section
566 && seg != data_section
567 && seg != bss_section && seg != undefined_section)
569 set_syntax_error (_("bad segment"));
570 *str = input_line_pointer;
571 input_line_pointer = save_in;
578 *str = input_line_pointer;
579 input_line_pointer = save_in;
583 /* Turn a string in input_line_pointer into a floating point constant
584 of type TYPE, and store the appropriate bytes in *LITP. The number
585 of LITTLENUMS emitted is stored in *SIZEP. An error message is
586 returned, or NULL on OK. */
589 md_atof (int type, char *litP, int *sizeP)
591 return ieee_md_atof (type, litP, sizeP, target_big_endian);
594 /* We handle all bad expressions here, so that we can report the faulty
595 instruction in the error message. */
597 md_operand (expressionS * exp)
599 if (in_my_get_expression_p)
600 exp->X_op = O_illegal;
603 /* Immediate values. */
605 /* Errors may be set multiple times during parsing or bit encoding
606 (particularly in the Neon bits), but usually the earliest error which is set
607 will be the most meaningful. Avoid overwriting it with later (cascading)
608 errors by calling this function. */
611 first_error (const char *error)
614 set_syntax_error (error);
617 /* Similiar to first_error, but this function accepts formatted error
620 first_error_fmt (const char *format, ...)
625 /* N.B. this single buffer will not cause error messages for different
626 instructions to pollute each other; this is because at the end of
627 processing of each assembly line, error message if any will be
628 collected by as_bad. */
629 static char buffer[size];
633 int ret ATTRIBUTE_UNUSED;
634 va_start (args, format);
635 ret = vsnprintf (buffer, size, format, args);
636 know (ret <= size - 1 && ret >= 0);
638 set_syntax_error (buffer);
642 /* Register parsing. */
644 /* Generic register parser which is called by other specialized
646 CCP points to what should be the beginning of a register name.
647 If it is indeed a valid register name, advance CCP over it and
648 return the reg_entry structure; otherwise return NULL.
649 It does not issue diagnostics. */
652 parse_reg (char **ccp)
658 #ifdef REGISTER_PREFIX
659 if (*start != REGISTER_PREFIX)
665 if (!ISALPHA (*p) || !is_name_beginner (*p))
670 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
672 reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start);
681 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
684 aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
686 return (reg_type_masks[type] & (1 << reg->type)) != 0;
689 /* Try to parse a base or offset register. Return the register entry
690 on success, setting *QUALIFIER to the register qualifier. Return null
693 Note that this function does not issue any diagnostics. */
695 static const reg_entry *
696 aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
699 const reg_entry *reg = parse_reg (&str);
709 *qualifier = AARCH64_OPND_QLF_W;
715 *qualifier = AARCH64_OPND_QLF_X;
727 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
728 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
729 otherwise return FALSE.
731 Accept only one occurrence of:
732 8b 16b 2h 4h 8h 2s 4s 1d 2d
735 parse_vector_type_for_operand (struct vector_type_el *parsed_type, char **str)
739 unsigned element_size;
740 enum vector_el_type type;
750 width = strtoul (ptr, &ptr, 10);
751 if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
753 first_error_fmt (_("bad size %d in vector width specifier"), width);
758 switch (TOLOWER (*ptr))
786 first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
788 first_error (_("missing element size"));
791 if (width != 0 && width * element_size != 64 && width * element_size != 128
792 && !(width == 2 && element_size == 16))
795 ("invalid element size %d and vector size combination %c"),
801 parsed_type->type = type;
802 parsed_type->width = width;
809 /* Parse a register of the type TYPE.
811 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
812 name or the parsed register is not of TYPE.
814 Otherwise return the register number, and optionally fill in the actual
815 type of the register in *RTYPE when multiple alternatives were given, and
816 return the register shape and element index information in *TYPEINFO.
818 IN_REG_LIST should be set with TRUE if the caller is parsing a register
822 parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
823 struct vector_type_el *typeinfo, bfd_boolean in_reg_list)
826 const reg_entry *reg = parse_reg (&str);
827 struct vector_type_el atype;
828 struct vector_type_el parsetype;
829 bfd_boolean is_typed_vecreg = FALSE;
832 atype.type = NT_invtype;
840 set_default_error ();
844 if (! aarch64_check_reg_type (reg, type))
846 DEBUG_TRACE ("reg type check failed");
847 set_default_error ();
852 if (type == REG_TYPE_VN && *str == '.')
854 if (!parse_vector_type_for_operand (&parsetype, &str))
857 /* Register if of the form Vn.[bhsdq]. */
858 is_typed_vecreg = TRUE;
860 if (parsetype.width == 0)
861 /* Expect index. In the new scheme we cannot have
862 Vn.[bhsdq] represent a scalar. Therefore any
863 Vn.[bhsdq] should have an index following it.
864 Except in reglists ofcourse. */
865 atype.defined |= NTA_HASINDEX;
867 atype.defined |= NTA_HASTYPE;
869 atype.type = parsetype.type;
870 atype.width = parsetype.width;
873 if (skip_past_char (&str, '['))
877 /* Reject Sn[index] syntax. */
878 if (!is_typed_vecreg)
880 first_error (_("this type of register can't be indexed"));
884 if (in_reg_list == TRUE)
886 first_error (_("index not allowed inside register list"));
890 atype.defined |= NTA_HASINDEX;
892 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
894 if (exp.X_op != O_constant)
896 first_error (_("constant expression required"));
900 if (! skip_past_char (&str, ']'))
903 atype.index = exp.X_add_number;
905 else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
907 /* Indexed vector register expected. */
908 first_error (_("indexed vector register expected"));
912 /* A vector reg Vn should be typed or indexed. */
913 if (type == REG_TYPE_VN && atype.defined == 0)
915 first_error (_("invalid use of vector register"));
931 Return the register number on success; return PARSE_FAIL otherwise.
933 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
934 the register (e.g. NEON double or quad reg when either has been requested).
936 If this is a NEON vector register with additional type information, fill
937 in the struct pointed to by VECTYPE (if non-NULL).
939 This parser does not handle register list. */
942 aarch64_reg_parse (char **ccp, aarch64_reg_type type,
943 aarch64_reg_type *rtype, struct vector_type_el *vectype)
945 struct vector_type_el atype;
947 int reg = parse_typed_reg (&str, type, rtype, &atype,
948 /*in_reg_list= */ FALSE);
950 if (reg == PARSE_FAIL)
961 static inline bfd_boolean
962 eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2)
966 && e1.defined == e2.defined
967 && e1.width == e2.width && e1.index == e2.index;
970 /* This function parses a list of vector registers of type TYPE.
971 On success, it returns the parsed register list information in the
972 following encoded format:
974 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
975 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
977 The information of the register shape and/or index is returned in
980 It returns PARSE_FAIL if the register list is invalid.
982 The list contains one to four registers.
983 Each register can be one of:
986 All <T> should be identical.
987 All <index> should be identical.
988 There are restrictions on <Vt> numbers which are checked later
989 (by reg_list_valid_p). */
992 parse_vector_reg_list (char **ccp, aarch64_reg_type type,
993 struct vector_type_el *vectype)
997 struct vector_type_el typeinfo, typeinfo_first;
1002 bfd_boolean error = FALSE;
1003 bfd_boolean expect_index = FALSE;
1007 set_syntax_error (_("expecting {"));
1013 typeinfo_first.defined = 0;
1014 typeinfo_first.type = NT_invtype;
1015 typeinfo_first.width = -1;
1016 typeinfo_first.index = 0;
1025 str++; /* skip over '-' */
1028 val = parse_typed_reg (&str, type, NULL, &typeinfo,
1029 /*in_reg_list= */ TRUE);
1030 if (val == PARSE_FAIL)
1032 set_first_syntax_error (_("invalid vector register in list"));
1036 /* reject [bhsd]n */
1037 if (typeinfo.defined == 0)
1039 set_first_syntax_error (_("invalid scalar register in list"));
1044 if (typeinfo.defined & NTA_HASINDEX)
1045 expect_index = TRUE;
1049 if (val < val_range)
1051 set_first_syntax_error
1052 (_("invalid range in vector register list"));
1061 typeinfo_first = typeinfo;
1062 else if (! eq_vector_type_el (typeinfo_first, typeinfo))
1064 set_first_syntax_error
1065 (_("type mismatch in vector register list"));
1070 for (i = val_range; i <= val; i++)
1072 ret_val |= i << (5 * nb_regs);
1077 while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
1079 skip_whitespace (str);
1082 set_first_syntax_error (_("end of vector register list not found"));
1087 skip_whitespace (str);
1091 if (skip_past_char (&str, '['))
1095 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1096 if (exp.X_op != O_constant)
1098 set_first_syntax_error (_("constant expression required."));
1101 if (! skip_past_char (&str, ']'))
1104 typeinfo_first.index = exp.X_add_number;
1108 set_first_syntax_error (_("expected index"));
1115 set_first_syntax_error (_("too many registers in vector register list"));
1118 else if (nb_regs == 0)
1120 set_first_syntax_error (_("empty vector register list"));
1126 *vectype = typeinfo_first;
1128 return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1);
1131 /* Directives: register aliases. */
1134 insert_reg_alias (char *str, int number, aarch64_reg_type type)
1139 if ((new = hash_find (aarch64_reg_hsh, str)) != 0)
1142 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1145 /* Only warn about a redefinition if it's not defined as the
1147 else if (new->number != number || new->type != type)
1148 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1153 name = xstrdup (str);
1154 new = XNEW (reg_entry);
1157 new->number = number;
1159 new->builtin = FALSE;
1161 if (hash_insert (aarch64_reg_hsh, name, (void *) new))
1167 /* Look for the .req directive. This is of the form:
1169 new_register_name .req existing_register_name
1171 If we find one, or if it looks sufficiently like one that we want to
1172 handle any error here, return TRUE. Otherwise return FALSE. */
1175 create_register_alias (char *newname, char *p)
1177 const reg_entry *old;
1178 char *oldname, *nbuf;
1181 /* The input scrubber ensures that whitespace after the mnemonic is
1182 collapsed to single spaces. */
1184 if (strncmp (oldname, " .req ", 6) != 0)
1188 if (*oldname == '\0')
1191 old = hash_find (aarch64_reg_hsh, oldname);
1194 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1198 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1199 the desired alias name, and p points to its end. If not, then
1200 the desired alias name is in the global original_case_string. */
1201 #ifdef TC_CASE_SENSITIVE
1204 newname = original_case_string;
1205 nlen = strlen (newname);
1208 nbuf = xmemdup0 (newname, nlen);
1210 /* Create aliases under the new name as stated; an all-lowercase
1211 version of the new name; and an all-uppercase version of the new
1213 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
1215 for (p = nbuf; *p; p++)
1218 if (strncmp (nbuf, newname, nlen))
1220 /* If this attempt to create an additional alias fails, do not bother
1221 trying to create the all-lower case alias. We will fail and issue
1222 a second, duplicate error message. This situation arises when the
1223 programmer does something like:
1226 The second .req creates the "Foo" alias but then fails to create
1227 the artificial FOO alias because it has already been created by the
1229 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
1236 for (p = nbuf; *p; p++)
1239 if (strncmp (nbuf, newname, nlen))
1240 insert_reg_alias (nbuf, old->number, old->type);
1247 /* Should never be called, as .req goes between the alias and the
1248 register name, not at the beginning of the line. */
1250 s_req (int a ATTRIBUTE_UNUSED)
1252 as_bad (_("invalid syntax for .req directive"));
1255 /* The .unreq directive deletes an alias which was previously defined
1256 by .req. For example:
1262 s_unreq (int a ATTRIBUTE_UNUSED)
1267 name = input_line_pointer;
1269 while (*input_line_pointer != 0
1270 && *input_line_pointer != ' ' && *input_line_pointer != '\n')
1271 ++input_line_pointer;
1273 saved_char = *input_line_pointer;
1274 *input_line_pointer = 0;
1277 as_bad (_("invalid syntax for .unreq directive"));
1280 reg_entry *reg = hash_find (aarch64_reg_hsh, name);
1283 as_bad (_("unknown register alias '%s'"), name);
1284 else if (reg->builtin)
1285 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1292 hash_delete (aarch64_reg_hsh, name, FALSE);
1293 free ((char *) reg->name);
1296 /* Also locate the all upper case and all lower case versions.
1297 Do not complain if we cannot find one or the other as it
1298 was probably deleted above. */
1300 nbuf = strdup (name);
1301 for (p = nbuf; *p; p++)
1303 reg = hash_find (aarch64_reg_hsh, nbuf);
1306 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1307 free ((char *) reg->name);
1311 for (p = nbuf; *p; p++)
1313 reg = hash_find (aarch64_reg_hsh, nbuf);
1316 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1317 free ((char *) reg->name);
1325 *input_line_pointer = saved_char;
1326 demand_empty_rest_of_line ();
1329 /* Directives: Instruction set selection. */
1332 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1333 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1334 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1335 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1337 /* Create a new mapping symbol for the transition to STATE. */
1340 make_mapping_symbol (enum mstate state, valueT value, fragS * frag)
1343 const char *symname;
1350 type = BSF_NO_FLAGS;
1354 type = BSF_NO_FLAGS;
1360 symbolP = symbol_new (symname, now_seg, value, frag);
1361 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1363 /* Save the mapping symbols for future reference. Also check that
1364 we do not place two mapping symbols at the same offset within a
1365 frag. We'll handle overlap between frags in
1366 check_mapping_symbols.
1368 If .fill or other data filling directive generates zero sized data,
1369 the mapping symbol for the following code will have the same value
1370 as the one generated for the data filling directive. In this case,
1371 we replace the old symbol with the new one at the same address. */
1374 if (frag->tc_frag_data.first_map != NULL)
1376 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
1377 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP,
1380 frag->tc_frag_data.first_map = symbolP;
1382 if (frag->tc_frag_data.last_map != NULL)
1384 know (S_GET_VALUE (frag->tc_frag_data.last_map) <=
1385 S_GET_VALUE (symbolP));
1386 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
1387 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP,
1390 frag->tc_frag_data.last_map = symbolP;
1393 /* We must sometimes convert a region marked as code to data during
1394 code alignment, if an odd number of bytes have to be padded. The
1395 code mapping symbol is pushed to an aligned address. */
1398 insert_data_mapping_symbol (enum mstate state,
1399 valueT value, fragS * frag, offsetT bytes)
1401 /* If there was already a mapping symbol, remove it. */
1402 if (frag->tc_frag_data.last_map != NULL
1403 && S_GET_VALUE (frag->tc_frag_data.last_map) ==
1404 frag->fr_address + value)
1406 symbolS *symp = frag->tc_frag_data.last_map;
1410 know (frag->tc_frag_data.first_map == symp);
1411 frag->tc_frag_data.first_map = NULL;
1413 frag->tc_frag_data.last_map = NULL;
1414 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
1417 make_mapping_symbol (MAP_DATA, value, frag);
1418 make_mapping_symbol (state, value + bytes, frag);
1421 static void mapping_state_2 (enum mstate state, int max_chars);
1423 /* Set the mapping state to STATE. Only call this when about to
1424 emit some STATE bytes to the file. */
1427 mapping_state (enum mstate state)
1429 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1431 if (state == MAP_INSN)
1432 /* AArch64 instructions require 4-byte alignment. When emitting
1433 instructions into any section, record the appropriate section
1435 record_alignment (now_seg, 2);
1437 if (mapstate == state)
1438 /* The mapping symbol has already been emitted.
1439 There is nothing else to do. */
1442 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1443 if (TRANSITION (MAP_UNDEFINED, MAP_DATA) && !subseg_text_p (now_seg))
1444 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1445 evaluated later in the next else. */
1447 else if (TRANSITION (MAP_UNDEFINED, MAP_INSN))
1449 /* Only add the symbol if the offset is > 0:
1450 if we're at the first frag, check it's size > 0;
1451 if we're not at the first frag, then for sure
1452 the offset is > 0. */
1453 struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root;
1454 const int add_symbol = (frag_now != frag_first)
1455 || (frag_now_fix () > 0);
1458 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
1462 mapping_state_2 (state, 0);
1465 /* Same as mapping_state, but MAX_CHARS bytes have already been
1466 allocated. Put the mapping symbol that far back. */
1469 mapping_state_2 (enum mstate state, int max_chars)
1471 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1473 if (!SEG_NORMAL (now_seg))
1476 if (mapstate == state)
1477 /* The mapping symbol has already been emitted.
1478 There is nothing else to do. */
1481 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1482 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
1485 #define mapping_state(x) /* nothing */
1486 #define mapping_state_2(x, y) /* nothing */
1489 /* Directives: sectioning and alignment. */
1492 s_bss (int ignore ATTRIBUTE_UNUSED)
1494 /* We don't support putting frags in the BSS segment, we fake it by
1495 marking in_bss, then looking at s_skip for clues. */
1496 subseg_set (bss_section, 0);
1497 demand_empty_rest_of_line ();
1498 mapping_state (MAP_DATA);
1502 s_even (int ignore ATTRIBUTE_UNUSED)
1504 /* Never make frag if expect extra pass. */
1506 frag_align (1, 0, 0);
1508 record_alignment (now_seg, 1);
1510 demand_empty_rest_of_line ();
1513 /* Directives: Literal pools. */
1515 static literal_pool *
1516 find_literal_pool (int size)
1520 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1522 if (pool->section == now_seg
1523 && pool->sub_section == now_subseg && pool->size == size)
1530 static literal_pool *
1531 find_or_make_literal_pool (int size)
1533 /* Next literal pool ID number. */
1534 static unsigned int latest_pool_num = 1;
1537 pool = find_literal_pool (size);
1541 /* Create a new pool. */
1542 pool = XNEW (literal_pool);
1546 /* Currently we always put the literal pool in the current text
1547 section. If we were generating "small" model code where we
1548 knew that all code and initialised data was within 1MB then
1549 we could output literals to mergeable, read-only data
1552 pool->next_free_entry = 0;
1553 pool->section = now_seg;
1554 pool->sub_section = now_subseg;
1556 pool->next = list_of_pools;
1557 pool->symbol = NULL;
1559 /* Add it to the list. */
1560 list_of_pools = pool;
1563 /* New pools, and emptied pools, will have a NULL symbol. */
1564 if (pool->symbol == NULL)
1566 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1567 (valueT) 0, &zero_address_frag);
1568 pool->id = latest_pool_num++;
1575 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1576 Return TRUE on success, otherwise return FALSE. */
1578 add_to_lit_pool (expressionS *exp, int size)
1583 pool = find_or_make_literal_pool (size);
1585 /* Check if this literal value is already in the pool. */
1586 for (entry = 0; entry < pool->next_free_entry; entry++)
1588 expressionS * litexp = & pool->literals[entry].exp;
1590 if ((litexp->X_op == exp->X_op)
1591 && (exp->X_op == O_constant)
1592 && (litexp->X_add_number == exp->X_add_number)
1593 && (litexp->X_unsigned == exp->X_unsigned))
1596 if ((litexp->X_op == exp->X_op)
1597 && (exp->X_op == O_symbol)
1598 && (litexp->X_add_number == exp->X_add_number)
1599 && (litexp->X_add_symbol == exp->X_add_symbol)
1600 && (litexp->X_op_symbol == exp->X_op_symbol))
1604 /* Do we need to create a new entry? */
1605 if (entry == pool->next_free_entry)
1607 if (entry >= MAX_LITERAL_POOL_SIZE)
1609 set_syntax_error (_("literal pool overflow"));
1613 pool->literals[entry].exp = *exp;
1614 pool->next_free_entry += 1;
1615 if (exp->X_op == O_big)
1617 /* PR 16688: Bignums are held in a single global array. We must
1618 copy and preserve that value now, before it is overwritten. */
1619 pool->literals[entry].bignum = XNEWVEC (LITTLENUM_TYPE,
1621 memcpy (pool->literals[entry].bignum, generic_bignum,
1622 CHARS_PER_LITTLENUM * exp->X_add_number);
1625 pool->literals[entry].bignum = NULL;
1628 exp->X_op = O_symbol;
1629 exp->X_add_number = ((int) entry) * size;
1630 exp->X_add_symbol = pool->symbol;
1635 /* Can't use symbol_new here, so have to create a symbol and then at
1636 a later date assign it a value. Thats what these functions do. */
1639 symbol_locate (symbolS * symbolP,
1640 const char *name,/* It is copied, the caller can modify. */
1641 segT segment, /* Segment identifier (SEG_<something>). */
1642 valueT valu, /* Symbol value. */
1643 fragS * frag) /* Associated fragment. */
1646 char *preserved_copy_of_name;
1648 name_length = strlen (name) + 1; /* +1 for \0. */
1649 obstack_grow (¬es, name, name_length);
1650 preserved_copy_of_name = obstack_finish (¬es);
1652 #ifdef tc_canonicalize_symbol_name
1653 preserved_copy_of_name =
1654 tc_canonicalize_symbol_name (preserved_copy_of_name);
1657 S_SET_NAME (symbolP, preserved_copy_of_name);
1659 S_SET_SEGMENT (symbolP, segment);
1660 S_SET_VALUE (symbolP, valu);
1661 symbol_clear_list_pointers (symbolP);
1663 symbol_set_frag (symbolP, frag);
1665 /* Link to end of symbol chain. */
1667 extern int symbol_table_frozen;
1669 if (symbol_table_frozen)
1673 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1675 obj_symbol_new_hook (symbolP);
1677 #ifdef tc_symbol_new_hook
1678 tc_symbol_new_hook (symbolP);
1682 verify_symbol_chain (symbol_rootP, symbol_lastP);
1683 #endif /* DEBUG_SYMS */
1688 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1695 for (align = 2; align <= 4; align++)
1697 int size = 1 << align;
1699 pool = find_literal_pool (size);
1700 if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
1703 /* Align pool as you have word accesses.
1704 Only make a frag if we have to. */
1706 frag_align (align, 0, 0);
1708 mapping_state (MAP_DATA);
1710 record_alignment (now_seg, align);
1712 sprintf (sym_name, "$$lit_\002%x", pool->id);
1714 symbol_locate (pool->symbol, sym_name, now_seg,
1715 (valueT) frag_now_fix (), frag_now);
1716 symbol_table_insert (pool->symbol);
1718 for (entry = 0; entry < pool->next_free_entry; entry++)
1720 expressionS * exp = & pool->literals[entry].exp;
1722 if (exp->X_op == O_big)
1724 /* PR 16688: Restore the global bignum value. */
1725 gas_assert (pool->literals[entry].bignum != NULL);
1726 memcpy (generic_bignum, pool->literals[entry].bignum,
1727 CHARS_PER_LITTLENUM * exp->X_add_number);
1730 /* First output the expression in the instruction to the pool. */
1731 emit_expr (exp, size); /* .word|.xword */
1733 if (exp->X_op == O_big)
1735 free (pool->literals[entry].bignum);
1736 pool->literals[entry].bignum = NULL;
1740 /* Mark the pool as empty. */
1741 pool->next_free_entry = 0;
1742 pool->symbol = NULL;
1747 /* Forward declarations for functions below, in the MD interface
1749 static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int);
1750 static struct reloc_table_entry * find_reloc_table_entry (char **);
1752 /* Directives: Data. */
1753 /* N.B. the support for relocation suffix in this directive needs to be
1754 implemented properly. */
1757 s_aarch64_elf_cons (int nbytes)
1761 #ifdef md_flush_pending_output
1762 md_flush_pending_output ();
1765 if (is_it_end_of_statement ())
1767 demand_empty_rest_of_line ();
1771 #ifdef md_cons_align
1772 md_cons_align (nbytes);
1775 mapping_state (MAP_DATA);
1778 struct reloc_table_entry *reloc;
1782 if (exp.X_op != O_symbol)
1783 emit_expr (&exp, (unsigned int) nbytes);
1786 skip_past_char (&input_line_pointer, '#');
1787 if (skip_past_char (&input_line_pointer, ':'))
1789 reloc = find_reloc_table_entry (&input_line_pointer);
1791 as_bad (_("unrecognized relocation suffix"));
1793 as_bad (_("unimplemented relocation suffix"));
1794 ignore_rest_of_line ();
1798 emit_expr (&exp, (unsigned int) nbytes);
1801 while (*input_line_pointer++ == ',');
1803 /* Put terminator back into stream. */
1804 input_line_pointer--;
1805 demand_empty_rest_of_line ();
1808 #endif /* OBJ_ELF */
1810 /* Output a 32-bit word, but mark as an instruction. */
1813 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
1817 #ifdef md_flush_pending_output
1818 md_flush_pending_output ();
1821 if (is_it_end_of_statement ())
1823 demand_empty_rest_of_line ();
1827 /* Sections are assumed to start aligned. In executable section, there is no
1828 MAP_DATA symbol pending. So we only align the address during
1829 MAP_DATA --> MAP_INSN transition.
1830 For other sections, this is not guaranteed. */
1831 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1832 if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA)
1833 frag_align_code (2, 0);
1836 mapping_state (MAP_INSN);
1842 if (exp.X_op != O_constant)
1844 as_bad (_("constant expression required"));
1845 ignore_rest_of_line ();
1849 if (target_big_endian)
1851 unsigned int val = exp.X_add_number;
1852 exp.X_add_number = SWAP_32 (val);
1854 emit_expr (&exp, 4);
1856 while (*input_line_pointer++ == ',');
1858 /* Put terminator back into stream. */
1859 input_line_pointer--;
1860 demand_empty_rest_of_line ();
1864 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1867 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED)
1873 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1874 BFD_RELOC_AARCH64_TLSDESC_ADD);
1876 demand_empty_rest_of_line ();
1879 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1882 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
1886 /* Since we're just labelling the code, there's no need to define a
1889 /* Make sure there is enough room in this frag for the following
1890 blr. This trick only works if the blr follows immediately after
1891 the .tlsdesc directive. */
1893 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1894 BFD_RELOC_AARCH64_TLSDESC_CALL);
1896 demand_empty_rest_of_line ();
1899 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1902 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED)
1908 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1909 BFD_RELOC_AARCH64_TLSDESC_LDR);
1911 demand_empty_rest_of_line ();
1913 #endif /* OBJ_ELF */
1915 static void s_aarch64_arch (int);
1916 static void s_aarch64_cpu (int);
1917 static void s_aarch64_arch_extension (int);
1919 /* This table describes all the machine specific pseudo-ops the assembler
1920 has to support. The fields are:
1921 pseudo-op name without dot
1922 function to call to execute this pseudo-op
1923 Integer arg to pass to the function. */
1925 const pseudo_typeS md_pseudo_table[] = {
1926 /* Never called because '.req' does not start a line. */
1928 {"unreq", s_unreq, 0},
1930 {"even", s_even, 0},
1931 {"ltorg", s_ltorg, 0},
1932 {"pool", s_ltorg, 0},
1933 {"cpu", s_aarch64_cpu, 0},
1934 {"arch", s_aarch64_arch, 0},
1935 {"arch_extension", s_aarch64_arch_extension, 0},
1936 {"inst", s_aarch64_inst, 0},
1938 {"tlsdescadd", s_tlsdescadd, 0},
1939 {"tlsdesccall", s_tlsdesccall, 0},
1940 {"tlsdescldr", s_tlsdescldr, 0},
1941 {"word", s_aarch64_elf_cons, 4},
1942 {"long", s_aarch64_elf_cons, 4},
1943 {"xword", s_aarch64_elf_cons, 8},
1944 {"dword", s_aarch64_elf_cons, 8},
1950 /* Check whether STR points to a register name followed by a comma or the
1951 end of line; REG_TYPE indicates which register types are checked
1952 against. Return TRUE if STR is such a register name; otherwise return
1953 FALSE. The function does not intend to produce any diagnostics, but since
1954 the register parser aarch64_reg_parse, which is called by this function,
1955 does produce diagnostics, we call clear_error to clear any diagnostics
1956 that may be generated by aarch64_reg_parse.
1957 Also, the function returns FALSE directly if there is any user error
1958 present at the function entry. This prevents the existing diagnostics
1959 state from being spoiled.
1960 The function currently serves parse_constant_immediate and
1961 parse_big_immediate only. */
1963 reg_name_p (char *str, aarch64_reg_type reg_type)
1967 /* Prevent the diagnostics state from being spoiled. */
1971 reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
1973 /* Clear the parsing error that may be set by the reg parser. */
1976 if (reg == PARSE_FAIL)
1979 skip_whitespace (str);
1980 if (*str == ',' || is_end_of_line[(unsigned int) *str])
1986 /* Parser functions used exclusively in instruction operands. */
1988 /* Parse an immediate expression which may not be constant.
1990 To prevent the expression parser from pushing a register name
1991 into the symbol table as an undefined symbol, firstly a check is
1992 done to find out whether STR is a register of type REG_TYPE followed
1993 by a comma or the end of line. Return FALSE if STR is such a string. */
1996 parse_immediate_expression (char **str, expressionS *exp,
1997 aarch64_reg_type reg_type)
1999 if (reg_name_p (*str, reg_type))
2001 set_recoverable_error (_("immediate operand required"));
2005 my_get_expression (exp, str, GE_OPT_PREFIX, 1);
2007 if (exp->X_op == O_absent)
2009 set_fatal_syntax_error (_("missing immediate expression"));
2016 /* Constant immediate-value read function for use in insn parsing.
2017 STR points to the beginning of the immediate (with the optional
2018 leading #); *VAL receives the value. REG_TYPE says which register
2019 names should be treated as registers rather than as symbolic immediates.
2021 Return TRUE on success; otherwise return FALSE. */
2024 parse_constant_immediate (char **str, int64_t *val, aarch64_reg_type reg_type)
2028 if (! parse_immediate_expression (str, &exp, reg_type))
2031 if (exp.X_op != O_constant)
2033 set_syntax_error (_("constant expression required"));
2037 *val = exp.X_add_number;
2042 encode_imm_float_bits (uint32_t imm)
2044 return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2045 | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2048 /* Return TRUE if the single-precision floating-point value encoded in IMM
2049 can be expressed in the AArch64 8-bit signed floating-point format with
2050 3-bit exponent and normalized 4 bits of precision; in other words, the
2051 floating-point value must be expressable as
2052 (+/-) n / 16 * power (2, r)
2053 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2056 aarch64_imm_float_p (uint32_t imm)
2058 /* If a single-precision floating-point value has the following bit
2059 pattern, it can be expressed in the AArch64 8-bit floating-point
2062 3 32222222 2221111111111
2063 1 09876543 21098765432109876543210
2064 n Eeeeeexx xxxx0000000000000000000
2066 where n, e and each x are either 0 or 1 independently, with
2071 /* Prepare the pattern for 'Eeeeee'. */
2072 if (((imm >> 30) & 0x1) == 0)
2073 pattern = 0x3e000000;
2075 pattern = 0x40000000;
2077 return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */
2078 && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */
2081 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2082 as an IEEE float without any loss of precision. Store the value in
2086 can_convert_double_to_float (uint64_t imm, uint32_t *fpword)
2088 /* If a double-precision floating-point value has the following bit
2089 pattern, it can be expressed in a float:
2091 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2092 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2093 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2095 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2096 if Eeee_eeee != 1111_1111
2098 where n, e, s and S are either 0 or 1 independently and where ~ is the
2102 uint32_t high32 = imm >> 32;
2103 uint32_t low32 = imm;
2105 /* Lower 29 bits need to be 0s. */
2106 if ((imm & 0x1fffffff) != 0)
2109 /* Prepare the pattern for 'Eeeeeeeee'. */
2110 if (((high32 >> 30) & 0x1) == 0)
2111 pattern = 0x38000000;
2113 pattern = 0x40000000;
2116 if ((high32 & 0x78000000) != pattern)
2119 /* Check Eeee_eeee != 1111_1111. */
2120 if ((high32 & 0x7ff00000) == 0x47f00000)
2123 *fpword = ((high32 & 0xc0000000) /* 1 n bit and 1 E bit. */
2124 | ((high32 << 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2125 | (low32 >> 29)); /* 3 S bits. */
2129 /* Parse a floating-point immediate. Return TRUE on success and return the
2130 value in *IMMED in the format of IEEE754 single-precision encoding.
2131 *CCP points to the start of the string; DP_P is TRUE when the immediate
2132 is expected to be in double-precision (N.B. this only matters when
2133 hexadecimal representation is involved). REG_TYPE says which register
2134 names should be treated as registers rather than as symbolic immediates.
2136 This routine accepts any IEEE float; it is up to the callers to reject
2140 parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p,
2141 aarch64_reg_type reg_type)
2145 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2146 int found_fpchar = 0;
2148 unsigned fpword = 0;
2149 bfd_boolean hex_p = FALSE;
2151 skip_past_char (&str, '#');
2154 skip_whitespace (fpnum);
2156 if (strncmp (fpnum, "0x", 2) == 0)
2158 /* Support the hexadecimal representation of the IEEE754 encoding.
2159 Double-precision is expected when DP_P is TRUE, otherwise the
2160 representation should be in single-precision. */
2161 if (! parse_constant_immediate (&str, &val, reg_type))
2166 if (!can_convert_double_to_float (val, &fpword))
2169 else if ((uint64_t) val > 0xffffffff)
2178 if (reg_name_p (str, reg_type))
2180 set_recoverable_error (_("immediate operand required"));
2184 /* We must not accidentally parse an integer as a floating-point number.
2185 Make sure that the value we parse is not an integer by checking for
2186 special characters '.' or 'e'. */
2187 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
2188 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
2202 if ((str = atof_ieee (str, 's', words)) == NULL)
2205 /* Our FP word must be 32 bits (single-precision FP). */
2206 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
2208 fpword <<= LITTLENUM_NUMBER_OF_BITS;
2218 set_fatal_syntax_error (_("invalid floating-point constant"));
2222 /* Less-generic immediate-value read function with the possibility of loading
2223 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2226 To prevent the expression parser from pushing a register name into the
2227 symbol table as an undefined symbol, a check is firstly done to find
2228 out whether STR is a register of type REG_TYPE followed by a comma or
2229 the end of line. Return FALSE if STR is such a register. */
2232 parse_big_immediate (char **str, int64_t *imm, aarch64_reg_type reg_type)
2236 if (reg_name_p (ptr, reg_type))
2238 set_syntax_error (_("immediate operand required"));
2242 my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
2244 if (inst.reloc.exp.X_op == O_constant)
2245 *imm = inst.reloc.exp.X_add_number;
2252 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2253 if NEED_LIBOPCODES is non-zero, the fixup will need
2254 assistance from the libopcodes. */
2257 aarch64_set_gas_internal_fixup (struct reloc *reloc,
2258 const aarch64_opnd_info *operand,
2259 int need_libopcodes_p)
2261 reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2262 reloc->opnd = operand->type;
2263 if (need_libopcodes_p)
2264 reloc->need_libopcodes_p = 1;
2267 /* Return TRUE if the instruction needs to be fixed up later internally by
2268 the GAS; otherwise return FALSE. */
2270 static inline bfd_boolean
2271 aarch64_gas_internal_fixup_p (void)
2273 return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2276 /* Assign the immediate value to the relavant field in *OPERAND if
2277 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2278 needs an internal fixup in a later stage.
2279 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2280 IMM.VALUE that may get assigned with the constant. */
2282 assign_imm_if_const_or_fixup_later (struct reloc *reloc,
2283 aarch64_opnd_info *operand,
2285 int need_libopcodes_p,
2288 if (reloc->exp.X_op == O_constant)
2291 operand->addr.offset.imm = reloc->exp.X_add_number;
2293 operand->imm.value = reloc->exp.X_add_number;
2294 reloc->type = BFD_RELOC_UNUSED;
2298 aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p);
2299 /* Tell libopcodes to ignore this operand or not. This is helpful
2300 when one of the operands needs to be fixed up later but we need
2301 libopcodes to check the other operands. */
2302 operand->skip = skip_p;
2306 /* Relocation modifiers. Each entry in the table contains the textual
2307 name for the relocation which may be placed before a symbol used as
2308 a load/store offset, or add immediate. It must be surrounded by a
2309 leading and trailing colon, for example:
2311 ldr x0, [x1, #:rello:varsym]
2312 add x0, x1, #:rello:varsym */
2314 struct reloc_table_entry
2318 bfd_reloc_code_real_type adr_type;
2319 bfd_reloc_code_real_type adrp_type;
2320 bfd_reloc_code_real_type movw_type;
2321 bfd_reloc_code_real_type add_type;
2322 bfd_reloc_code_real_type ldst_type;
2323 bfd_reloc_code_real_type ld_literal_type;
2326 static struct reloc_table_entry reloc_table[] = {
2327 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2332 BFD_RELOC_AARCH64_ADD_LO12,
2333 BFD_RELOC_AARCH64_LDST_LO12,
2336 /* Higher 21 bits of pc-relative page offset: ADRP */
2339 BFD_RELOC_AARCH64_ADR_HI21_PCREL,
2345 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2348 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
2354 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2358 BFD_RELOC_AARCH64_MOVW_G0,
2363 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2367 BFD_RELOC_AARCH64_MOVW_G0_S,
2372 /* Less significant bits 0-15 of address/value: MOVK, no check */
2376 BFD_RELOC_AARCH64_MOVW_G0_NC,
2381 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2385 BFD_RELOC_AARCH64_MOVW_G1,
2390 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2394 BFD_RELOC_AARCH64_MOVW_G1_S,
2399 /* Less significant bits 16-31 of address/value: MOVK, no check */
2403 BFD_RELOC_AARCH64_MOVW_G1_NC,
2408 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2412 BFD_RELOC_AARCH64_MOVW_G2,
2417 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2421 BFD_RELOC_AARCH64_MOVW_G2_S,
2426 /* Less significant bits 32-47 of address/value: MOVK, no check */
2430 BFD_RELOC_AARCH64_MOVW_G2_NC,
2435 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2439 BFD_RELOC_AARCH64_MOVW_G3,
2444 /* Get to the page containing GOT entry for a symbol. */
2447 BFD_RELOC_AARCH64_ADR_GOT_PAGE,
2451 BFD_RELOC_AARCH64_GOT_LD_PREL19},
2453 /* 12 bit offset into the page containing GOT entry for that symbol. */
2459 BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
2462 /* 0-15 bits of address/value: MOVk, no check. */
2466 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC,
2471 /* Most significant bits 16-31 of address/value: MOVZ. */
2475 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1,
2480 /* 15 bit offset into the page containing GOT entry for that symbol. */
2486 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15,
2489 /* Get to the page containing GOT TLS entry for a symbol */
2490 {"gottprel_g0_nc", 0,
2493 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
2498 /* Get to the page containing GOT TLS entry for a symbol */
2502 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
2507 /* Get to the page containing GOT TLS entry for a symbol */
2509 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21, /* adr_type */
2510 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
2516 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2521 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
2525 /* Lower 16 bits address/value: MOVk. */
2529 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC,
2534 /* Most significant bits 16-31 of address/value: MOVZ. */
2538 BFD_RELOC_AARCH64_TLSGD_MOVW_G1,
2543 /* Get to the page containing GOT TLS entry for a symbol */
2545 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21, /* adr_type */
2546 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21,
2550 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19},
2552 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2557 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
2558 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
2561 /* Get to the page containing GOT TLS entry for a symbol.
2562 The same as GD, we allocate two consecutive GOT slots
2563 for module index and module offset, the only difference
2564 with GD is the module offset should be intialized to
2565 zero without any outstanding runtime relocation. */
2567 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21, /* adr_type */
2568 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21,
2574 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2575 {"tlsldm_lo12_nc", 0,
2579 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC,
2583 /* 12 bit offset into the module TLS base address. */
2588 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12,
2589 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12,
2592 /* Same as dtprel_lo12, no overflow check. */
2593 {"dtprel_lo12_nc", 0,
2597 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC,
2598 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC,
2601 /* bits[23:12] of offset to the module TLS base address. */
2606 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12,
2610 /* bits[15:0] of offset to the module TLS base address. */
2614 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0,
2619 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2623 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC,
2628 /* bits[31:16] of offset to the module TLS base address. */
2632 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1,
2637 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2641 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC,
2646 /* bits[47:32] of offset to the module TLS base address. */
2650 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2,
2655 /* Lower 16 bit offset into GOT entry for a symbol */
2656 {"tlsdesc_off_g0_nc", 0,
2659 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
2664 /* Higher 16 bit offset into GOT entry for a symbol */
2665 {"tlsdesc_off_g1", 0,
2668 BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
2673 /* Get to the page containing GOT TLS entry for a symbol */
2676 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
2680 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19},
2682 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2683 {"gottprel_lo12", 0,
2688 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC,
2691 /* Get tp offset for a symbol. */
2696 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2700 /* Get tp offset for a symbol. */
2705 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2709 /* Get tp offset for a symbol. */
2714 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
2718 /* Get tp offset for a symbol. */
2719 {"tprel_lo12_nc", 0,
2723 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
2727 /* Most significant bits 32-47 of address/value: MOVZ. */
2731 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
2736 /* Most significant bits 16-31 of address/value: MOVZ. */
2740 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
2745 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2749 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
2754 /* Most significant bits 0-15 of address/value: MOVZ. */
2758 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
2763 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2767 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
2772 /* 15bit offset from got entry to base address of GOT table. */
2778 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15,
2781 /* 14bit offset from got entry to base address of GOT table. */
2787 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14,
2791 /* Given the address of a pointer pointing to the textual name of a
2792 relocation as may appear in assembler source, attempt to find its
2793 details in reloc_table. The pointer will be updated to the character
2794 after the trailing colon. On failure, NULL will be returned;
2795 otherwise return the reloc_table_entry. */
2797 static struct reloc_table_entry *
2798 find_reloc_table_entry (char **str)
2801 for (i = 0; i < ARRAY_SIZE (reloc_table); i++)
2803 int length = strlen (reloc_table[i].name);
2805 if (strncasecmp (reloc_table[i].name, *str, length) == 0
2806 && (*str)[length] == ':')
2808 *str += (length + 1);
2809 return &reloc_table[i];
2816 /* Mode argument to parse_shift and parser_shifter_operand. */
2817 enum parse_shift_mode
2819 SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2821 SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2823 SHIFTED_LSL, /* bare "lsl #n" */
2824 SHIFTED_LSL_MSL, /* "lsl|msl #n" */
2825 SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */
2828 /* Parse a <shift> operator on an AArch64 data processing instruction.
2829 Return TRUE on success; otherwise return FALSE. */
2831 parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
2833 const struct aarch64_name_value_pair *shift_op;
2834 enum aarch64_modifier_kind kind;
2840 for (p = *str; ISALPHA (*p); p++)
2845 set_syntax_error (_("shift expression expected"));
2849 shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str);
2851 if (shift_op == NULL)
2853 set_syntax_error (_("shift operator expected"));
2857 kind = aarch64_get_operand_modifier (shift_op);
2859 if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
2861 set_syntax_error (_("invalid use of 'MSL'"));
2867 case SHIFTED_LOGIC_IMM:
2868 if (aarch64_extend_operator_p (kind) == TRUE)
2870 set_syntax_error (_("extending shift is not permitted"));
2875 case SHIFTED_ARITH_IMM:
2876 if (kind == AARCH64_MOD_ROR)
2878 set_syntax_error (_("'ROR' shift is not permitted"));
2884 if (kind != AARCH64_MOD_LSL)
2886 set_syntax_error (_("only 'LSL' shift is permitted"));
2891 case SHIFTED_REG_OFFSET:
2892 if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
2893 && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX)
2895 set_fatal_syntax_error
2896 (_("invalid shift for the register offset addressing mode"));
2901 case SHIFTED_LSL_MSL:
2902 if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
2904 set_syntax_error (_("invalid shift operator"));
2913 /* Whitespace can appear here if the next thing is a bare digit. */
2914 skip_whitespace (p);
2916 /* Parse shift amount. */
2918 if (mode == SHIFTED_REG_OFFSET && *p == ']')
2919 exp.X_op = O_absent;
2922 if (is_immediate_prefix (*p))
2927 my_get_expression (&exp, &p, GE_NO_PREFIX, 0);
2929 if (exp.X_op == O_absent)
2931 if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
2933 set_syntax_error (_("missing shift amount"));
2936 operand->shifter.amount = 0;
2938 else if (exp.X_op != O_constant)
2940 set_syntax_error (_("constant shift amount required"));
2943 else if (exp.X_add_number < 0 || exp.X_add_number > 63)
2945 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2950 operand->shifter.amount = exp.X_add_number;
2951 operand->shifter.amount_present = 1;
2954 operand->shifter.operator_present = 1;
2955 operand->shifter.kind = kind;
2961 /* Parse a <shifter_operand> for a data processing instruction:
2964 #<immediate>, LSL #imm
2966 Validation of immediate operands is deferred to md_apply_fix.
2968 Return TRUE on success; otherwise return FALSE. */
2971 parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
2972 enum parse_shift_mode mode)
2976 if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
2981 /* Accept an immediate expression. */
2982 if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
2985 /* Accept optional LSL for arithmetic immediate values. */
2986 if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
2987 if (! parse_shift (&p, operand, SHIFTED_LSL))
2990 /* Not accept any shifter for logical immediate values. */
2991 if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
2992 && parse_shift (&p, operand, mode))
2994 set_syntax_error (_("unexpected shift operator"));
3002 /* Parse a <shifter_operand> for a data processing instruction:
3007 #<immediate>, LSL #imm
3009 where <shift> is handled by parse_shift above, and the last two
3010 cases are handled by the function above.
3012 Validation of immediate operands is deferred to md_apply_fix.
3014 Return TRUE on success; otherwise return FALSE. */
3017 parse_shifter_operand (char **str, aarch64_opnd_info *operand,
3018 enum parse_shift_mode mode)
3020 const reg_entry *reg;
3021 aarch64_opnd_qualifier_t qualifier;
3022 enum aarch64_operand_class opd_class
3023 = aarch64_get_operand_class (operand->type);
3025 reg = aarch64_reg_parse_32_64 (str, &qualifier);
3028 if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
3030 set_syntax_error (_("unexpected register in the immediate operand"));
3034 if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
3036 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z)));
3040 operand->reg.regno = reg->number;
3041 operand->qualifier = qualifier;
3043 /* Accept optional shift operation on register. */
3044 if (! skip_past_comma (str))
3047 if (! parse_shift (str, operand, mode))
3052 else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
3055 (_("integer register expected in the extended/shifted operand "
3060 /* We have a shifted immediate variable. */
3061 return parse_shifter_operand_imm (str, operand, mode);
3064 /* Return TRUE on success; return FALSE otherwise. */
3067 parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
3068 enum parse_shift_mode mode)
3072 /* Determine if we have the sequence of characters #: or just :
3073 coming next. If we do, then we check for a :rello: relocation
3074 modifier. If we don't, punt the whole lot to
3075 parse_shifter_operand. */
3077 if ((p[0] == '#' && p[1] == ':') || p[0] == ':')
3079 struct reloc_table_entry *entry;
3087 /* Try to parse a relocation. Anything else is an error. */
3088 if (!(entry = find_reloc_table_entry (str)))
3090 set_syntax_error (_("unknown relocation modifier"));
3094 if (entry->add_type == 0)
3097 (_("this relocation modifier is not allowed on this instruction"));
3101 /* Save str before we decompose it. */
3104 /* Next, we parse the expression. */
3105 if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
3108 /* Record the relocation type (use the ADD variant here). */
3109 inst.reloc.type = entry->add_type;
3110 inst.reloc.pc_rel = entry->pc_rel;
3112 /* If str is empty, we've reached the end, stop here. */
3116 /* Otherwise, we have a shifted reloc modifier, so rewind to
3117 recover the variable name and continue parsing for the shifter. */
3119 return parse_shifter_operand_imm (str, operand, mode);
3122 return parse_shifter_operand (str, operand, mode);
3125 /* Parse all forms of an address expression. Information is written
3126 to *OPERAND and/or inst.reloc.
3128 The A64 instruction set has the following addressing modes:
3131 [base] // in SIMD ld/st structure
3132 [base{,#0}] // in ld/st exclusive
3134 [base,Xm{,LSL #imm}]
3135 [base,Xm,SXTX {#imm}]
3136 [base,Wm,(S|U)XTW {#imm}]
3141 [base],Xm // in SIMD ld/st structure
3142 PC-relative (literal)
3146 (As a convenience, the notation "=immediate" is permitted in conjunction
3147 with the pc-relative literal load instructions to automatically place an
3148 immediate value or symbolic address in a nearby literal pool and generate
3149 a hidden label which references it.)
3151 Upon a successful parsing, the address structure in *OPERAND will be
3152 filled in the following way:
3154 .base_regno = <base>
3155 .offset.is_reg // 1 if the offset is a register
3157 .offset.regno = <Rm>
3159 For different addressing modes defined in the A64 ISA:
3162 .pcrel=0; .preind=1; .postind=0; .writeback=0
3164 .pcrel=0; .preind=1; .postind=0; .writeback=1
3166 .pcrel=0; .preind=0; .postind=1; .writeback=1
3167 PC-relative (literal)
3168 .pcrel=1; .preind=1; .postind=0; .writeback=0
3170 The shift/extension information, if any, will be stored in .shifter.
3172 It is the caller's responsibility to check for addressing modes not
3173 supported by the instruction, and to set inst.reloc.type. */
3176 parse_address_main (char **str, aarch64_opnd_info *operand)
3179 const reg_entry *reg;
3180 aarch64_opnd_qualifier_t base_qualifier;
3181 aarch64_opnd_qualifier_t offset_qualifier;
3182 expressionS *exp = &inst.reloc.exp;
3184 if (! skip_past_char (&p, '['))
3186 /* =immediate or label. */
3187 operand->addr.pcrel = 1;
3188 operand->addr.preind = 1;
3190 /* #:<reloc_op>:<symbol> */
3191 skip_past_char (&p, '#');
3192 if (skip_past_char (&p, ':'))
3194 bfd_reloc_code_real_type ty;
3195 struct reloc_table_entry *entry;
3197 /* Try to parse a relocation modifier. Anything else is
3199 entry = find_reloc_table_entry (&p);
3202 set_syntax_error (_("unknown relocation modifier"));
3206 switch (operand->type)
3208 case AARCH64_OPND_ADDR_PCREL21:
3210 ty = entry->adr_type;
3214 ty = entry->ld_literal_type;
3221 (_("this relocation modifier is not allowed on this "
3227 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3229 set_syntax_error (_("invalid relocation expression"));
3233 /* #:<reloc_op>:<expr> */
3234 /* Record the relocation type. */
3235 inst.reloc.type = ty;
3236 inst.reloc.pc_rel = entry->pc_rel;
3241 if (skip_past_char (&p, '='))
3242 /* =immediate; need to generate the literal in the literal pool. */
3243 inst.gen_lit_pool = 1;
3245 if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3247 set_syntax_error (_("invalid address"));
3258 reg = aarch64_reg_parse_32_64 (&p, &base_qualifier);
3259 if (!reg || !aarch64_check_reg_type (reg, REG_TYPE_R64_SP))
3261 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R64_SP)));
3264 operand->addr.base_regno = reg->number;
3267 if (skip_past_comma (&p))
3270 operand->addr.preind = 1;
3272 reg = aarch64_reg_parse_32_64 (&p, &offset_qualifier);
3275 if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
3277 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z)));
3282 operand->addr.offset.regno = reg->number;
3283 operand->addr.offset.is_reg = 1;
3284 /* Shifted index. */
3285 if (skip_past_comma (&p))
3288 if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
3289 /* Use the diagnostics set in parse_shift, so not set new
3290 error message here. */
3294 [base,Xm{,LSL #imm}]
3295 [base,Xm,SXTX {#imm}]
3296 [base,Wm,(S|U)XTW {#imm}] */
3297 if (operand->shifter.kind == AARCH64_MOD_NONE
3298 || operand->shifter.kind == AARCH64_MOD_LSL
3299 || operand->shifter.kind == AARCH64_MOD_SXTX)
3301 if (offset_qualifier == AARCH64_OPND_QLF_W)
3303 set_syntax_error (_("invalid use of 32-bit register offset"));
3307 else if (offset_qualifier == AARCH64_OPND_QLF_X)
3309 set_syntax_error (_("invalid use of 64-bit register offset"));
3315 /* [Xn,#:<reloc_op>:<symbol> */
3316 skip_past_char (&p, '#');
3317 if (skip_past_char (&p, ':'))
3319 struct reloc_table_entry *entry;
3321 /* Try to parse a relocation modifier. Anything else is
3323 if (!(entry = find_reloc_table_entry (&p)))
3325 set_syntax_error (_("unknown relocation modifier"));
3329 if (entry->ldst_type == 0)
3332 (_("this relocation modifier is not allowed on this "
3337 /* [Xn,#:<reloc_op>: */
3338 /* We now have the group relocation table entry corresponding to
3339 the name in the assembler source. Next, we parse the
3341 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3343 set_syntax_error (_("invalid relocation expression"));
3347 /* [Xn,#:<reloc_op>:<expr> */
3348 /* Record the load/store relocation type. */
3349 inst.reloc.type = entry->ldst_type;
3350 inst.reloc.pc_rel = entry->pc_rel;
3352 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3354 set_syntax_error (_("invalid expression in the address"));
3361 if (! skip_past_char (&p, ']'))
3363 set_syntax_error (_("']' expected"));
3367 if (skip_past_char (&p, '!'))
3369 if (operand->addr.preind && operand->addr.offset.is_reg)
3371 set_syntax_error (_("register offset not allowed in pre-indexed "
3372 "addressing mode"));
3376 operand->addr.writeback = 1;
3378 else if (skip_past_comma (&p))
3381 operand->addr.postind = 1;
3382 operand->addr.writeback = 1;
3384 if (operand->addr.preind)
3386 set_syntax_error (_("cannot combine pre- and post-indexing"));
3390 reg = aarch64_reg_parse_32_64 (&p, &offset_qualifier);
3394 if (!aarch64_check_reg_type (reg, REG_TYPE_R_64))
3396 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
3400 operand->addr.offset.regno = reg->number;
3401 operand->addr.offset.is_reg = 1;
3403 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3406 set_syntax_error (_("invalid expression in the address"));
3411 /* If at this point neither .preind nor .postind is set, we have a
3412 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3413 if (operand->addr.preind == 0 && operand->addr.postind == 0)
3415 if (operand->addr.writeback)
3418 set_syntax_error (_("missing offset in the pre-indexed address"));
3421 operand->addr.preind = 1;
3422 inst.reloc.exp.X_op = O_constant;
3423 inst.reloc.exp.X_add_number = 0;
3430 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3433 parse_address (char **str, aarch64_opnd_info *operand)
3435 return parse_address_main (str, operand);
3438 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3439 Return TRUE on success; otherwise return FALSE. */
3441 parse_half (char **str, int *internal_fixup_p)
3445 skip_past_char (&p, '#');
3447 gas_assert (internal_fixup_p);
3448 *internal_fixup_p = 0;
3452 struct reloc_table_entry *entry;
3454 /* Try to parse a relocation. Anything else is an error. */
3456 if (!(entry = find_reloc_table_entry (&p)))
3458 set_syntax_error (_("unknown relocation modifier"));
3462 if (entry->movw_type == 0)
3465 (_("this relocation modifier is not allowed on this instruction"));
3469 inst.reloc.type = entry->movw_type;
3472 *internal_fixup_p = 1;
3474 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3481 /* Parse an operand for an ADRP instruction:
3483 Return TRUE on success; otherwise return FALSE. */
3486 parse_adrp (char **str)
3493 struct reloc_table_entry *entry;
3495 /* Try to parse a relocation. Anything else is an error. */
3497 if (!(entry = find_reloc_table_entry (&p)))
3499 set_syntax_error (_("unknown relocation modifier"));
3503 if (entry->adrp_type == 0)
3506 (_("this relocation modifier is not allowed on this instruction"));
3510 inst.reloc.type = entry->adrp_type;
3513 inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
3515 inst.reloc.pc_rel = 1;
3517 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3524 /* Miscellaneous. */
3526 /* Parse an option for a preload instruction. Returns the encoding for the
3527 option, or PARSE_FAIL. */
3530 parse_pldop (char **str)
3533 const struct aarch64_name_value_pair *o;
3536 while (ISALNUM (*q))
3539 o = hash_find_n (aarch64_pldop_hsh, p, q - p);
3547 /* Parse an option for a barrier instruction. Returns the encoding for the
3548 option, or PARSE_FAIL. */
3551 parse_barrier (char **str)
3554 const asm_barrier_opt *o;
3557 while (ISALPHA (*q))
3560 o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p);
3568 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3569 return 0 if successful. Otherwise return PARSE_FAIL. */
3572 parse_barrier_psb (char **str,
3573 const struct aarch64_name_value_pair ** hint_opt)
3576 const struct aarch64_name_value_pair *o;
3579 while (ISALPHA (*q))
3582 o = hash_find_n (aarch64_hint_opt_hsh, p, q - p);
3585 set_fatal_syntax_error
3586 ( _("unknown or missing option to PSB"));
3590 if (o->value != 0x11)
3592 /* PSB only accepts option name 'CSYNC'. */
3594 (_("the specified option is not accepted for PSB"));
3603 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3604 Returns the encoding for the option, or PARSE_FAIL.
3606 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3607 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3609 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3610 field, otherwise as a system register.
3614 parse_sys_reg (char **str, struct hash_control *sys_regs,
3615 int imple_defined_p, int pstatefield_p)
3619 const aarch64_sys_reg *o;
3623 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3625 *p++ = TOLOWER (*q);
3627 /* Assert that BUF be large enough. */
3628 gas_assert (p - buf == q - *str);
3630 o = hash_find (sys_regs, buf);
3633 if (!imple_defined_p)
3637 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3638 unsigned int op0, op1, cn, cm, op2;
3640 if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2)
3643 if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
3645 value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
3650 if (pstatefield_p && !aarch64_pstatefield_supported_p (cpu_variant, o))
3651 as_bad (_("selected processor does not support PSTATE field "
3653 if (!pstatefield_p && !aarch64_sys_reg_supported_p (cpu_variant, o))
3654 as_bad (_("selected processor does not support system register "
3656 if (aarch64_sys_reg_deprecated_p (o))
3657 as_warn (_("system register name '%s' is deprecated and may be "
3658 "removed in a future release"), buf);
3666 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3667 for the option, or NULL. */
3669 static const aarch64_sys_ins_reg *
3670 parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
3674 const aarch64_sys_ins_reg *o;
3677 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3679 *p++ = TOLOWER (*q);
3682 o = hash_find (sys_ins_regs, buf);
3686 if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
3687 as_bad (_("selected processor does not support system register "
3694 #define po_char_or_fail(chr) do { \
3695 if (! skip_past_char (&str, chr)) \
3699 #define po_reg_or_fail(regtype) do { \
3700 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3701 if (val == PARSE_FAIL) \
3703 set_default_error (); \
3708 #define po_int_reg_or_fail(reg_type) do { \
3709 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
3710 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
3712 set_default_error (); \
3715 info->reg.regno = reg->number; \
3716 info->qualifier = qualifier; \
3719 #define po_imm_nc_or_fail() do { \
3720 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3724 #define po_imm_or_fail(min, max) do { \
3725 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
3727 if (val < min || val > max) \
3729 set_fatal_syntax_error (_("immediate value out of range "\
3730 #min " to "#max)); \
3735 #define po_misc_or_fail(expr) do { \
3740 /* encode the 12-bit imm field of Add/sub immediate */
3741 static inline uint32_t
3742 encode_addsub_imm (uint32_t imm)
3747 /* encode the shift amount field of Add/sub immediate */
3748 static inline uint32_t
3749 encode_addsub_imm_shift_amount (uint32_t cnt)
3755 /* encode the imm field of Adr instruction */
3756 static inline uint32_t
3757 encode_adr_imm (uint32_t imm)
3759 return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */
3760 | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3763 /* encode the immediate field of Move wide immediate */
3764 static inline uint32_t
3765 encode_movw_imm (uint32_t imm)
3770 /* encode the 26-bit offset of unconditional branch */
3771 static inline uint32_t
3772 encode_branch_ofs_26 (uint32_t ofs)
3774 return ofs & ((1 << 26) - 1);
3777 /* encode the 19-bit offset of conditional branch and compare & branch */
3778 static inline uint32_t
3779 encode_cond_branch_ofs_19 (uint32_t ofs)
3781 return (ofs & ((1 << 19) - 1)) << 5;
3784 /* encode the 19-bit offset of ld literal */
3785 static inline uint32_t
3786 encode_ld_lit_ofs_19 (uint32_t ofs)
3788 return (ofs & ((1 << 19) - 1)) << 5;
3791 /* Encode the 14-bit offset of test & branch. */
3792 static inline uint32_t
3793 encode_tst_branch_ofs_14 (uint32_t ofs)
3795 return (ofs & ((1 << 14) - 1)) << 5;
3798 /* Encode the 16-bit imm field of svc/hvc/smc. */
3799 static inline uint32_t
3800 encode_svc_imm (uint32_t imm)
3805 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3806 static inline uint32_t
3807 reencode_addsub_switch_add_sub (uint32_t opcode)
3809 return opcode ^ (1 << 30);
3812 static inline uint32_t
3813 reencode_movzn_to_movz (uint32_t opcode)
3815 return opcode | (1 << 30);
3818 static inline uint32_t
3819 reencode_movzn_to_movn (uint32_t opcode)
3821 return opcode & ~(1 << 30);
3824 /* Overall per-instruction processing. */
3826 /* We need to be able to fix up arbitrary expressions in some statements.
3827 This is so that we can handle symbols that are an arbitrary distance from
3828 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3829 which returns part of an address in a form which will be valid for
3830 a data instruction. We do this by pushing the expression into a symbol
3831 in the expr_section, and creating a fix for that. */
3834 fix_new_aarch64 (fragS * frag,
3836 short int size, expressionS * exp, int pc_rel, int reloc)
3846 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
3850 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
3857 /* Diagnostics on operands errors. */
3859 /* By default, output verbose error message.
3860 Disable the verbose error message by -mno-verbose-error. */
3861 static int verbose_error_p = 1;
3863 #ifdef DEBUG_AARCH64
3864 /* N.B. this is only for the purpose of debugging. */
3865 const char* operand_mismatch_kind_names[] =
3868 "AARCH64_OPDE_RECOVERABLE",
3869 "AARCH64_OPDE_SYNTAX_ERROR",
3870 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3871 "AARCH64_OPDE_INVALID_VARIANT",
3872 "AARCH64_OPDE_OUT_OF_RANGE",
3873 "AARCH64_OPDE_UNALIGNED",
3874 "AARCH64_OPDE_REG_LIST",
3875 "AARCH64_OPDE_OTHER_ERROR",
3877 #endif /* DEBUG_AARCH64 */
3879 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3881 When multiple errors of different kinds are found in the same assembly
3882 line, only the error of the highest severity will be picked up for
3883 issuing the diagnostics. */
3885 static inline bfd_boolean
3886 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
3887 enum aarch64_operand_error_kind rhs)
3889 gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL);
3890 gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE);
3891 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
3892 gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
3893 gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
3894 gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
3895 gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
3896 gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
3900 /* Helper routine to get the mnemonic name from the assembly instruction
3901 line; should only be called for the diagnosis purpose, as there is
3902 string copy operation involved, which may affect the runtime
3903 performance if used in elsewhere. */
3906 get_mnemonic_name (const char *str)
3908 static char mnemonic[32];
3911 /* Get the first 15 bytes and assume that the full name is included. */
3912 strncpy (mnemonic, str, 31);
3913 mnemonic[31] = '\0';
3915 /* Scan up to the end of the mnemonic, which must end in white space,
3916 '.', or end of string. */
3917 for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr)
3922 /* Append '...' to the truncated long name. */
3923 if (ptr - mnemonic == 31)
3924 mnemonic[28] = mnemonic[29] = mnemonic[30] = '.';
3930 reset_aarch64_instruction (aarch64_instruction *instruction)
3932 memset (instruction, '\0', sizeof (aarch64_instruction));
3933 instruction->reloc.type = BFD_RELOC_UNUSED;
3936 /* Data strutures storing one user error in the assembly code related to
3939 struct operand_error_record
3941 const aarch64_opcode *opcode;
3942 aarch64_operand_error detail;
3943 struct operand_error_record *next;
3946 typedef struct operand_error_record operand_error_record;
3948 struct operand_errors
3950 operand_error_record *head;
3951 operand_error_record *tail;
3954 typedef struct operand_errors operand_errors;
3956 /* Top-level data structure reporting user errors for the current line of
3958 The way md_assemble works is that all opcodes sharing the same mnemonic
3959 name are iterated to find a match to the assembly line. In this data
3960 structure, each of the such opcodes will have one operand_error_record
3961 allocated and inserted. In other words, excessive errors related with
3962 a single opcode are disregarded. */
3963 operand_errors operand_error_report;
3965 /* Free record nodes. */
3966 static operand_error_record *free_opnd_error_record_nodes = NULL;
3968 /* Initialize the data structure that stores the operand mismatch
3969 information on assembling one line of the assembly code. */
3971 init_operand_error_report (void)
3973 if (operand_error_report.head != NULL)
3975 gas_assert (operand_error_report.tail != NULL);
3976 operand_error_report.tail->next = free_opnd_error_record_nodes;
3977 free_opnd_error_record_nodes = operand_error_report.head;
3978 operand_error_report.head = NULL;
3979 operand_error_report.tail = NULL;
3982 gas_assert (operand_error_report.tail == NULL);
3985 /* Return TRUE if some operand error has been recorded during the
3986 parsing of the current assembly line using the opcode *OPCODE;
3987 otherwise return FALSE. */
3988 static inline bfd_boolean
3989 opcode_has_operand_error_p (const aarch64_opcode *opcode)
3991 operand_error_record *record = operand_error_report.head;
3992 return record && record->opcode == opcode;
3995 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3996 OPCODE field is initialized with OPCODE.
3997 N.B. only one record for each opcode, i.e. the maximum of one error is
3998 recorded for each instruction template. */
4001 add_operand_error_record (const operand_error_record* new_record)
4003 const aarch64_opcode *opcode = new_record->opcode;
4004 operand_error_record* record = operand_error_report.head;
4006 /* The record may have been created for this opcode. If not, we need
4008 if (! opcode_has_operand_error_p (opcode))
4010 /* Get one empty record. */
4011 if (free_opnd_error_record_nodes == NULL)
4013 record = XNEW (operand_error_record);
4017 record = free_opnd_error_record_nodes;
4018 free_opnd_error_record_nodes = record->next;
4020 record->opcode = opcode;
4021 /* Insert at the head. */
4022 record->next = operand_error_report.head;
4023 operand_error_report.head = record;
4024 if (operand_error_report.tail == NULL)
4025 operand_error_report.tail = record;
4027 else if (record->detail.kind != AARCH64_OPDE_NIL
4028 && record->detail.index <= new_record->detail.index
4029 && operand_error_higher_severity_p (record->detail.kind,
4030 new_record->detail.kind))
4032 /* In the case of multiple errors found on operands related with a
4033 single opcode, only record the error of the leftmost operand and
4034 only if the error is of higher severity. */
4035 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4036 " the existing error %s on operand %d",
4037 operand_mismatch_kind_names[new_record->detail.kind],
4038 new_record->detail.index,
4039 operand_mismatch_kind_names[record->detail.kind],
4040 record->detail.index);
4044 record->detail = new_record->detail;
4048 record_operand_error_info (const aarch64_opcode *opcode,
4049 aarch64_operand_error *error_info)
4051 operand_error_record record;
4052 record.opcode = opcode;
4053 record.detail = *error_info;
4054 add_operand_error_record (&record);
4057 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4058 error message *ERROR, for operand IDX (count from 0). */
4061 record_operand_error (const aarch64_opcode *opcode, int idx,
4062 enum aarch64_operand_error_kind kind,
4065 aarch64_operand_error info;
4066 memset(&info, 0, sizeof (info));
4070 record_operand_error_info (opcode, &info);
4074 record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
4075 enum aarch64_operand_error_kind kind,
4076 const char* error, const int *extra_data)
4078 aarch64_operand_error info;
4082 info.data[0] = extra_data[0];
4083 info.data[1] = extra_data[1];
4084 info.data[2] = extra_data[2];
4085 record_operand_error_info (opcode, &info);
4089 record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx,
4090 const char* error, int lower_bound,
4093 int data[3] = {lower_bound, upper_bound, 0};
4094 record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE,
4098 /* Remove the operand error record for *OPCODE. */
4099 static void ATTRIBUTE_UNUSED
4100 remove_operand_error_record (const aarch64_opcode *opcode)
4102 if (opcode_has_operand_error_p (opcode))
4104 operand_error_record* record = operand_error_report.head;
4105 gas_assert (record != NULL && operand_error_report.tail != NULL);
4106 operand_error_report.head = record->next;
4107 record->next = free_opnd_error_record_nodes;
4108 free_opnd_error_record_nodes = record;
4109 if (operand_error_report.head == NULL)
4111 gas_assert (operand_error_report.tail == record);
4112 operand_error_report.tail = NULL;
4117 /* Given the instruction in *INSTR, return the index of the best matched
4118 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4120 Return -1 if there is no qualifier sequence; return the first match
4121 if there is multiple matches found. */
4124 find_best_match (const aarch64_inst *instr,
4125 const aarch64_opnd_qualifier_seq_t *qualifiers_list)
4127 int i, num_opnds, max_num_matched, idx;
4129 num_opnds = aarch64_num_of_operands (instr->opcode);
4132 DEBUG_TRACE ("no operand");
4136 max_num_matched = 0;
4139 /* For each pattern. */
4140 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4143 const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
4145 /* Most opcodes has much fewer patterns in the list. */
4146 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
4148 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
4152 for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers)
4153 if (*qualifiers == instr->operands[j].qualifier)
4156 if (num_matched > max_num_matched)
4158 max_num_matched = num_matched;
4163 DEBUG_TRACE ("return with %d", idx);
4167 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4168 corresponding operands in *INSTR. */
4171 assign_qualifier_sequence (aarch64_inst *instr,
4172 const aarch64_opnd_qualifier_t *qualifiers)
4175 int num_opnds = aarch64_num_of_operands (instr->opcode);
4176 gas_assert (num_opnds);
4177 for (i = 0; i < num_opnds; ++i, ++qualifiers)
4178 instr->operands[i].qualifier = *qualifiers;
4181 /* Print operands for the diagnosis purpose. */
4184 print_operands (char *buf, const aarch64_opcode *opcode,
4185 const aarch64_opnd_info *opnds)
4189 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
4193 /* We regard the opcode operand info more, however we also look into
4194 the inst->operands to support the disassembling of the optional
4196 The two operand code should be the same in all cases, apart from
4197 when the operand can be optional. */
4198 if (opcode->operands[i] == AARCH64_OPND_NIL
4199 || opnds[i].type == AARCH64_OPND_NIL)
4202 /* Generate the operand string in STR. */
4203 aarch64_print_operand (str, sizeof (str), 0, opcode, opnds, i, NULL, NULL);
4207 strcat (buf, i == 0 ? " " : ",");
4209 /* Append the operand string. */
4214 /* Send to stderr a string as information. */
4217 output_info (const char *format, ...)
4223 file = as_where (&line);
4227 fprintf (stderr, "%s:%u: ", file, line);
4229 fprintf (stderr, "%s: ", file);
4231 fprintf (stderr, _("Info: "));
4232 va_start (args, format);
4233 vfprintf (stderr, format, args);
4235 (void) putc ('\n', stderr);
4238 /* Output one operand error record. */
4241 output_operand_error_record (const operand_error_record *record, char *str)
4243 const aarch64_operand_error *detail = &record->detail;
4244 int idx = detail->index;
4245 const aarch64_opcode *opcode = record->opcode;
4246 enum aarch64_opnd opd_code = (idx >= 0 ? opcode->operands[idx]
4247 : AARCH64_OPND_NIL);
4249 switch (detail->kind)
4251 case AARCH64_OPDE_NIL:
4255 case AARCH64_OPDE_SYNTAX_ERROR:
4256 case AARCH64_OPDE_RECOVERABLE:
4257 case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
4258 case AARCH64_OPDE_OTHER_ERROR:
4259 /* Use the prepared error message if there is, otherwise use the
4260 operand description string to describe the error. */
4261 if (detail->error != NULL)
4264 as_bad (_("%s -- `%s'"), detail->error, str);
4266 as_bad (_("%s at operand %d -- `%s'"),
4267 detail->error, idx + 1, str);
4271 gas_assert (idx >= 0);
4272 as_bad (_("operand %d should be %s -- `%s'"), idx + 1,
4273 aarch64_get_operand_desc (opd_code), str);
4277 case AARCH64_OPDE_INVALID_VARIANT:
4278 as_bad (_("operand mismatch -- `%s'"), str);
4279 if (verbose_error_p)
4281 /* We will try to correct the erroneous instruction and also provide
4282 more information e.g. all other valid variants.
4284 The string representation of the corrected instruction and other
4285 valid variants are generated by
4287 1) obtaining the intermediate representation of the erroneous
4289 2) manipulating the IR, e.g. replacing the operand qualifier;
4290 3) printing out the instruction by calling the printer functions
4291 shared with the disassembler.
4293 The limitation of this method is that the exact input assembly
4294 line cannot be accurately reproduced in some cases, for example an
4295 optional operand present in the actual assembly line will be
4296 omitted in the output; likewise for the optional syntax rules,
4297 e.g. the # before the immediate. Another limitation is that the
4298 assembly symbols and relocation operations in the assembly line
4299 currently cannot be printed out in the error report. Last but not
4300 least, when there is other error(s) co-exist with this error, the
4301 'corrected' instruction may be still incorrect, e.g. given
4302 'ldnp h0,h1,[x0,#6]!'
4303 this diagnosis will provide the version:
4304 'ldnp s0,s1,[x0,#6]!'
4305 which is still not right. */
4306 size_t len = strlen (get_mnemonic_name (str));
4310 aarch64_inst *inst_base = &inst.base;
4311 const aarch64_opnd_qualifier_seq_t *qualifiers_list;
4314 reset_aarch64_instruction (&inst);
4315 inst_base->opcode = opcode;
4317 /* Reset the error report so that there is no side effect on the
4318 following operand parsing. */
4319 init_operand_error_report ();
4322 result = parse_operands (str + len, opcode)
4323 && programmer_friendly_fixup (&inst);
4324 gas_assert (result);
4325 result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
4327 gas_assert (!result);
4329 /* Find the most matched qualifier sequence. */
4330 qlf_idx = find_best_match (inst_base, opcode->qualifiers_list);
4331 gas_assert (qlf_idx > -1);
4333 /* Assign the qualifiers. */
4334 assign_qualifier_sequence (inst_base,
4335 opcode->qualifiers_list[qlf_idx]);
4337 /* Print the hint. */
4338 output_info (_(" did you mean this?"));
4339 snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str));
4340 print_operands (buf, opcode, inst_base->operands);
4341 output_info (_(" %s"), buf);
4343 /* Print out other variant(s) if there is any. */
4345 !empty_qualifier_sequence_p (opcode->qualifiers_list[1]))
4346 output_info (_(" other valid variant(s):"));
4348 /* For each pattern. */
4349 qualifiers_list = opcode->qualifiers_list;
4350 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4352 /* Most opcodes has much fewer patterns in the list.
4353 First NIL qualifier indicates the end in the list. */
4354 if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
4359 /* Mnemonics name. */
4360 snprintf (buf, sizeof (buf), "\t%s", get_mnemonic_name (str));
4362 /* Assign the qualifiers. */
4363 assign_qualifier_sequence (inst_base, *qualifiers_list);
4365 /* Print instruction. */
4366 print_operands (buf, opcode, inst_base->operands);
4368 output_info (_(" %s"), buf);
4374 case AARCH64_OPDE_UNTIED_OPERAND:
4375 as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
4376 detail->index + 1, str);
4379 case AARCH64_OPDE_OUT_OF_RANGE:
4380 if (detail->data[0] != detail->data[1])
4381 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4382 detail->error ? detail->error : _("immediate value"),
4383 detail->data[0], detail->data[1], idx + 1, str);
4385 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4386 detail->error ? detail->error : _("immediate value"),
4387 detail->data[0], idx + 1, str);
4390 case AARCH64_OPDE_REG_LIST:
4391 if (detail->data[0] == 1)
4392 as_bad (_("invalid number of registers in the list; "
4393 "only 1 register is expected at operand %d -- `%s'"),
4396 as_bad (_("invalid number of registers in the list; "
4397 "%d registers are expected at operand %d -- `%s'"),
4398 detail->data[0], idx + 1, str);
4401 case AARCH64_OPDE_UNALIGNED:
4402 as_bad (_("immediate value should be a multiple of "
4403 "%d at operand %d -- `%s'"),
4404 detail->data[0], idx + 1, str);
4413 /* Process and output the error message about the operand mismatching.
4415 When this function is called, the operand error information had
4416 been collected for an assembly line and there will be multiple
4417 errors in the case of mulitple instruction templates; output the
4418 error message that most closely describes the problem. */
4421 output_operand_error_report (char *str)
4423 int largest_error_pos;
4424 const char *msg = NULL;
4425 enum aarch64_operand_error_kind kind;
4426 operand_error_record *curr;
4427 operand_error_record *head = operand_error_report.head;
4428 operand_error_record *record = NULL;
4430 /* No error to report. */
4434 gas_assert (head != NULL && operand_error_report.tail != NULL);
4436 /* Only one error. */
4437 if (head == operand_error_report.tail)
4439 DEBUG_TRACE ("single opcode entry with error kind: %s",
4440 operand_mismatch_kind_names[head->detail.kind]);
4441 output_operand_error_record (head, str);
4445 /* Find the error kind of the highest severity. */
4446 DEBUG_TRACE ("multiple opcode entres with error kind");
4447 kind = AARCH64_OPDE_NIL;
4448 for (curr = head; curr != NULL; curr = curr->next)
4450 gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
4451 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
4452 if (operand_error_higher_severity_p (curr->detail.kind, kind))
4453 kind = curr->detail.kind;
4455 gas_assert (kind != AARCH64_OPDE_NIL);
4457 /* Pick up one of errors of KIND to report. */
4458 largest_error_pos = -2; /* Index can be -1 which means unknown index. */
4459 for (curr = head; curr != NULL; curr = curr->next)
4461 if (curr->detail.kind != kind)
4463 /* If there are multiple errors, pick up the one with the highest
4464 mismatching operand index. In the case of multiple errors with
4465 the equally highest operand index, pick up the first one or the
4466 first one with non-NULL error message. */
4467 if (curr->detail.index > largest_error_pos
4468 || (curr->detail.index == largest_error_pos && msg == NULL
4469 && curr->detail.error != NULL))
4471 largest_error_pos = curr->detail.index;
4473 msg = record->detail.error;
4477 gas_assert (largest_error_pos != -2 && record != NULL);
4478 DEBUG_TRACE ("Pick up error kind %s to report",
4479 operand_mismatch_kind_names[record->detail.kind]);
4482 output_operand_error_record (record, str);
4485 /* Write an AARCH64 instruction to buf - always little-endian. */
4487 put_aarch64_insn (char *buf, uint32_t insn)
4489 unsigned char *where = (unsigned char *) buf;
4491 where[1] = insn >> 8;
4492 where[2] = insn >> 16;
4493 where[3] = insn >> 24;
4497 get_aarch64_insn (char *buf)
4499 unsigned char *where = (unsigned char *) buf;
4501 result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
4506 output_inst (struct aarch64_inst *new_inst)
4510 to = frag_more (INSN_SIZE);
4512 frag_now->tc_frag_data.recorded = 1;
4514 put_aarch64_insn (to, inst.base.value);
4516 if (inst.reloc.type != BFD_RELOC_UNUSED)
4518 fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal,
4519 INSN_SIZE, &inst.reloc.exp,
4522 DEBUG_TRACE ("Prepared relocation fix up");
4523 /* Don't check the addend value against the instruction size,
4524 that's the job of our code in md_apply_fix(). */
4525 fixp->fx_no_overflow = 1;
4526 if (new_inst != NULL)
4527 fixp->tc_fix_data.inst = new_inst;
4528 if (aarch64_gas_internal_fixup_p ())
4530 gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL);
4531 fixp->tc_fix_data.opnd = inst.reloc.opnd;
4532 fixp->fx_addnumber = inst.reloc.flags;
4536 dwarf2_emit_insn (INSN_SIZE);
4539 /* Link together opcodes of the same name. */
4543 aarch64_opcode *opcode;
4544 struct templates *next;
4547 typedef struct templates templates;
4550 lookup_mnemonic (const char *start, int len)
4552 templates *templ = NULL;
4554 templ = hash_find_n (aarch64_ops_hsh, start, len);
4558 /* Subroutine of md_assemble, responsible for looking up the primary
4559 opcode from the mnemonic the user wrote. STR points to the
4560 beginning of the mnemonic. */
4563 opcode_lookup (char **str)
4566 const aarch64_cond *cond;
4570 /* Scan up to the end of the mnemonic, which must end in white space,
4571 '.', or end of string. */
4572 for (base = end = *str; is_part_of_name(*end); end++)
4579 inst.cond = COND_ALWAYS;
4581 /* Handle a possible condition. */
4584 cond = hash_find_n (aarch64_cond_hsh, end + 1, 2);
4587 inst.cond = cond->value;
4601 if (inst.cond == COND_ALWAYS)
4603 /* Look for unaffixed mnemonic. */
4604 return lookup_mnemonic (base, len);
4608 /* append ".c" to mnemonic if conditional */
4609 memcpy (condname, base, len);
4610 memcpy (condname + len, ".c", 2);
4613 return lookup_mnemonic (base, len);
4619 /* Internal helper routine converting a vector_type_el structure *VECTYPE
4620 to a corresponding operand qualifier. */
4622 static inline aarch64_opnd_qualifier_t
4623 vectype_to_qualifier (const struct vector_type_el *vectype)
4625 /* Element size in bytes indexed by vector_el_type. */
4626 const unsigned char ele_size[5]
4628 const unsigned int ele_base [5] =
4630 AARCH64_OPND_QLF_V_8B,
4631 AARCH64_OPND_QLF_V_2H,
4632 AARCH64_OPND_QLF_V_2S,
4633 AARCH64_OPND_QLF_V_1D,
4634 AARCH64_OPND_QLF_V_1Q
4637 if (!vectype->defined || vectype->type == NT_invtype)
4638 goto vectype_conversion_fail;
4640 gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
4642 if (vectype->defined & NTA_HASINDEX)
4643 /* Vector element register. */
4644 return AARCH64_OPND_QLF_S_B + vectype->type;
4647 /* Vector register. */
4648 int reg_size = ele_size[vectype->type] * vectype->width;
4651 if (reg_size != 16 && reg_size != 8 && reg_size != 4)
4652 goto vectype_conversion_fail;
4654 /* The conversion is by calculating the offset from the base operand
4655 qualifier for the vector type. The operand qualifiers are regular
4656 enough that the offset can established by shifting the vector width by
4657 a vector-type dependent amount. */
4659 if (vectype->type == NT_b)
4661 else if (vectype->type == NT_h || vectype->type == NT_s)
4663 else if (vectype->type >= NT_d)
4668 offset = ele_base [vectype->type] + (vectype->width >> shift);
4669 gas_assert (AARCH64_OPND_QLF_V_8B <= offset
4670 && offset <= AARCH64_OPND_QLF_V_1Q);
4674 vectype_conversion_fail:
4675 first_error (_("bad vector arrangement type"));
4676 return AARCH64_OPND_QLF_NIL;
4679 /* Process an optional operand that is found omitted from the assembly line.
4680 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4681 instruction's opcode entry while IDX is the index of this omitted operand.
4685 process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
4686 int idx, aarch64_opnd_info *operand)
4688 aarch64_insn default_value = get_optional_operand_default_value (opcode);
4689 gas_assert (optional_operand_p (opcode, idx));
4690 gas_assert (!operand->present);
4694 case AARCH64_OPND_Rd:
4695 case AARCH64_OPND_Rn:
4696 case AARCH64_OPND_Rm:
4697 case AARCH64_OPND_Rt:
4698 case AARCH64_OPND_Rt2:
4699 case AARCH64_OPND_Rs:
4700 case AARCH64_OPND_Ra:
4701 case AARCH64_OPND_Rt_SYS:
4702 case AARCH64_OPND_Rd_SP:
4703 case AARCH64_OPND_Rn_SP:
4704 case AARCH64_OPND_Fd:
4705 case AARCH64_OPND_Fn:
4706 case AARCH64_OPND_Fm:
4707 case AARCH64_OPND_Fa:
4708 case AARCH64_OPND_Ft:
4709 case AARCH64_OPND_Ft2:
4710 case AARCH64_OPND_Sd:
4711 case AARCH64_OPND_Sn:
4712 case AARCH64_OPND_Sm:
4713 case AARCH64_OPND_Vd:
4714 case AARCH64_OPND_Vn:
4715 case AARCH64_OPND_Vm:
4716 case AARCH64_OPND_VdD1:
4717 case AARCH64_OPND_VnD1:
4718 operand->reg.regno = default_value;
4721 case AARCH64_OPND_Ed:
4722 case AARCH64_OPND_En:
4723 case AARCH64_OPND_Em:
4724 operand->reglane.regno = default_value;
4727 case AARCH64_OPND_IDX:
4728 case AARCH64_OPND_BIT_NUM:
4729 case AARCH64_OPND_IMMR:
4730 case AARCH64_OPND_IMMS:
4731 case AARCH64_OPND_SHLL_IMM:
4732 case AARCH64_OPND_IMM_VLSL:
4733 case AARCH64_OPND_IMM_VLSR:
4734 case AARCH64_OPND_CCMP_IMM:
4735 case AARCH64_OPND_FBITS:
4736 case AARCH64_OPND_UIMM4:
4737 case AARCH64_OPND_UIMM3_OP1:
4738 case AARCH64_OPND_UIMM3_OP2:
4739 case AARCH64_OPND_IMM:
4740 case AARCH64_OPND_WIDTH:
4741 case AARCH64_OPND_UIMM7:
4742 case AARCH64_OPND_NZCV:
4743 operand->imm.value = default_value;
4746 case AARCH64_OPND_EXCEPTION:
4747 inst.reloc.type = BFD_RELOC_UNUSED;
4750 case AARCH64_OPND_BARRIER_ISB:
4751 operand->barrier = aarch64_barrier_options + default_value;
4758 /* Process the relocation type for move wide instructions.
4759 Return TRUE on success; otherwise return FALSE. */
4762 process_movw_reloc_info (void)
4767 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
4769 if (inst.base.opcode->op == OP_MOVK)
4770 switch (inst.reloc.type)
4772 case BFD_RELOC_AARCH64_MOVW_G0_S:
4773 case BFD_RELOC_AARCH64_MOVW_G1_S:
4774 case BFD_RELOC_AARCH64_MOVW_G2_S:
4775 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
4776 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4777 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4778 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4780 (_("the specified relocation type is not allowed for MOVK"));
4786 switch (inst.reloc.type)
4788 case BFD_RELOC_AARCH64_MOVW_G0:
4789 case BFD_RELOC_AARCH64_MOVW_G0_NC:
4790 case BFD_RELOC_AARCH64_MOVW_G0_S:
4791 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
4792 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
4793 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
4794 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
4795 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
4796 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
4797 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4798 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4801 case BFD_RELOC_AARCH64_MOVW_G1:
4802 case BFD_RELOC_AARCH64_MOVW_G1_NC:
4803 case BFD_RELOC_AARCH64_MOVW_G1_S:
4804 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
4805 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
4806 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
4807 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
4808 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
4809 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
4810 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4811 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4814 case BFD_RELOC_AARCH64_MOVW_G2:
4815 case BFD_RELOC_AARCH64_MOVW_G2_NC:
4816 case BFD_RELOC_AARCH64_MOVW_G2_S:
4817 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
4818 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4821 set_fatal_syntax_error
4822 (_("the specified relocation type is not allowed for 32-bit "
4828 case BFD_RELOC_AARCH64_MOVW_G3:
4831 set_fatal_syntax_error
4832 (_("the specified relocation type is not allowed for 32-bit "
4839 /* More cases should be added when more MOVW-related relocation types
4840 are supported in GAS. */
4841 gas_assert (aarch64_gas_internal_fixup_p ());
4842 /* The shift amount should have already been set by the parser. */
4845 inst.base.operands[1].shifter.amount = shift;
4849 /* A primitive log caculator. */
4851 static inline unsigned int
4852 get_logsz (unsigned int size)
4854 const unsigned char ls[16] =
4855 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4861 gas_assert (ls[size - 1] != (unsigned char)-1);
4862 return ls[size - 1];
4865 /* Determine and return the real reloc type code for an instruction
4866 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4868 static inline bfd_reloc_code_real_type
4869 ldst_lo12_determine_real_reloc_type (void)
4872 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
4873 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
4875 const bfd_reloc_code_real_type reloc_ldst_lo12[3][5] = {
4877 BFD_RELOC_AARCH64_LDST8_LO12,
4878 BFD_RELOC_AARCH64_LDST16_LO12,
4879 BFD_RELOC_AARCH64_LDST32_LO12,
4880 BFD_RELOC_AARCH64_LDST64_LO12,
4881 BFD_RELOC_AARCH64_LDST128_LO12
4884 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12,
4885 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12,
4886 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12,
4887 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12,
4888 BFD_RELOC_AARCH64_NONE
4891 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC,
4892 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC,
4893 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
4894 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
4895 BFD_RELOC_AARCH64_NONE
4899 gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
4900 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4902 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC));
4903 gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
4905 if (opd1_qlf == AARCH64_OPND_QLF_NIL)
4907 aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list,
4909 gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
4911 logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
4912 if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4913 || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
4914 gas_assert (logsz <= 3);
4916 gas_assert (logsz <= 4);
4918 /* In reloc.c, these pseudo relocation types should be defined in similar
4919 order as above reloc_ldst_lo12 array. Because the array index calcuation
4920 below relies on this. */
4921 return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
4924 /* Check whether a register list REGINFO is valid. The registers must be
4925 numbered in increasing order (modulo 32), in increments of one or two.
4927 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4930 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4933 reg_list_valid_p (uint32_t reginfo, int accept_alternate)
4935 uint32_t i, nb_regs, prev_regno, incr;
4937 nb_regs = 1 + (reginfo & 0x3);
4939 prev_regno = reginfo & 0x1f;
4940 incr = accept_alternate ? 2 : 1;
4942 for (i = 1; i < nb_regs; ++i)
4944 uint32_t curr_regno;
4946 curr_regno = reginfo & 0x1f;
4947 if (curr_regno != ((prev_regno + incr) & 0x1f))
4949 prev_regno = curr_regno;
4955 /* Generic instruction operand parser. This does no encoding and no
4956 semantic validation; it merely squirrels values away in the inst
4957 structure. Returns TRUE or FALSE depending on whether the
4958 specified grammar matched. */
4961 parse_operands (char *str, const aarch64_opcode *opcode)
4964 char *backtrack_pos = 0;
4965 const enum aarch64_opnd *operands = opcode->operands;
4966 aarch64_reg_type imm_reg_type;
4969 skip_whitespace (str);
4971 imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
4973 for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
4976 const reg_entry *reg;
4977 int comma_skipped_p = 0;
4978 aarch64_reg_type rtype;
4979 struct vector_type_el vectype;
4980 aarch64_opnd_qualifier_t qualifier;
4981 aarch64_opnd_info *info = &inst.base.operands[i];
4983 DEBUG_TRACE ("parse operand %d", i);
4985 /* Assign the operand code. */
4986 info->type = operands[i];
4988 if (optional_operand_p (opcode, i))
4990 /* Remember where we are in case we need to backtrack. */
4991 gas_assert (!backtrack_pos);
4992 backtrack_pos = str;
4995 /* Expect comma between operands; the backtrack mechanizm will take
4996 care of cases of omitted optional operand. */
4997 if (i > 0 && ! skip_past_char (&str, ','))
4999 set_syntax_error (_("comma expected between operands"));
5003 comma_skipped_p = 1;
5005 switch (operands[i])
5007 case AARCH64_OPND_Rd:
5008 case AARCH64_OPND_Rn:
5009 case AARCH64_OPND_Rm:
5010 case AARCH64_OPND_Rt:
5011 case AARCH64_OPND_Rt2:
5012 case AARCH64_OPND_Rs:
5013 case AARCH64_OPND_Ra:
5014 case AARCH64_OPND_Rt_SYS:
5015 case AARCH64_OPND_PAIRREG:
5016 po_int_reg_or_fail (REG_TYPE_R_Z);
5019 case AARCH64_OPND_Rd_SP:
5020 case AARCH64_OPND_Rn_SP:
5021 po_int_reg_or_fail (REG_TYPE_R_SP);
5024 case AARCH64_OPND_Rm_EXT:
5025 case AARCH64_OPND_Rm_SFT:
5026 po_misc_or_fail (parse_shifter_operand
5027 (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT
5029 : SHIFTED_LOGIC_IMM)));
5030 if (!info->shifter.operator_present)
5032 /* Default to LSL if not present. Libopcodes prefers shifter
5033 kind to be explicit. */
5034 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5035 info->shifter.kind = AARCH64_MOD_LSL;
5036 /* For Rm_EXT, libopcodes will carry out further check on whether
5037 or not stack pointer is used in the instruction (Recall that
5038 "the extend operator is not optional unless at least one of
5039 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5043 case AARCH64_OPND_Fd:
5044 case AARCH64_OPND_Fn:
5045 case AARCH64_OPND_Fm:
5046 case AARCH64_OPND_Fa:
5047 case AARCH64_OPND_Ft:
5048 case AARCH64_OPND_Ft2:
5049 case AARCH64_OPND_Sd:
5050 case AARCH64_OPND_Sn:
5051 case AARCH64_OPND_Sm:
5052 val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
5053 if (val == PARSE_FAIL)
5055 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
5058 gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
5060 info->reg.regno = val;
5061 info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
5064 case AARCH64_OPND_Vd:
5065 case AARCH64_OPND_Vn:
5066 case AARCH64_OPND_Vm:
5067 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
5068 if (val == PARSE_FAIL)
5070 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
5073 if (vectype.defined & NTA_HASINDEX)
5076 info->reg.regno = val;
5077 info->qualifier = vectype_to_qualifier (&vectype);
5078 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5082 case AARCH64_OPND_VdD1:
5083 case AARCH64_OPND_VnD1:
5084 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
5085 if (val == PARSE_FAIL)
5087 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
5090 if (vectype.type != NT_d || vectype.index != 1)
5092 set_fatal_syntax_error
5093 (_("the top half of a 128-bit FP/SIMD register is expected"));
5096 info->reg.regno = val;
5097 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5098 here; it is correct for the purpose of encoding/decoding since
5099 only the register number is explicitly encoded in the related
5100 instructions, although this appears a bit hacky. */
5101 info->qualifier = AARCH64_OPND_QLF_S_D;
5104 case AARCH64_OPND_Ed:
5105 case AARCH64_OPND_En:
5106 case AARCH64_OPND_Em:
5107 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
5108 if (val == PARSE_FAIL)
5110 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
5113 if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
5116 info->reglane.regno = val;
5117 info->reglane.index = vectype.index;
5118 info->qualifier = vectype_to_qualifier (&vectype);
5119 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5123 case AARCH64_OPND_LVn:
5124 case AARCH64_OPND_LVt:
5125 case AARCH64_OPND_LVt_AL:
5126 case AARCH64_OPND_LEt:
5127 if ((val = parse_vector_reg_list (&str, REG_TYPE_VN,
5128 &vectype)) == PARSE_FAIL)
5130 if (! reg_list_valid_p (val, /* accept_alternate */ 0))
5132 set_fatal_syntax_error (_("invalid register list"));
5135 info->reglist.first_regno = (val >> 2) & 0x1f;
5136 info->reglist.num_regs = (val & 0x3) + 1;
5137 if (operands[i] == AARCH64_OPND_LEt)
5139 if (!(vectype.defined & NTA_HASINDEX))
5141 info->reglist.has_index = 1;
5142 info->reglist.index = vectype.index;
5144 else if (!(vectype.defined & NTA_HASTYPE))
5146 info->qualifier = vectype_to_qualifier (&vectype);
5147 if (info->qualifier == AARCH64_OPND_QLF_NIL)
5151 case AARCH64_OPND_Cn:
5152 case AARCH64_OPND_Cm:
5153 po_reg_or_fail (REG_TYPE_CN);
5156 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN)));
5159 inst.base.operands[i].reg.regno = val;
5162 case AARCH64_OPND_SHLL_IMM:
5163 case AARCH64_OPND_IMM_VLSR:
5164 po_imm_or_fail (1, 64);
5165 info->imm.value = val;
5168 case AARCH64_OPND_CCMP_IMM:
5169 case AARCH64_OPND_FBITS:
5170 case AARCH64_OPND_UIMM4:
5171 case AARCH64_OPND_UIMM3_OP1:
5172 case AARCH64_OPND_UIMM3_OP2:
5173 case AARCH64_OPND_IMM_VLSL:
5174 case AARCH64_OPND_IMM:
5175 case AARCH64_OPND_WIDTH:
5176 po_imm_nc_or_fail ();
5177 info->imm.value = val;
5180 case AARCH64_OPND_UIMM7:
5181 po_imm_or_fail (0, 127);
5182 info->imm.value = val;
5185 case AARCH64_OPND_IDX:
5186 case AARCH64_OPND_BIT_NUM:
5187 case AARCH64_OPND_IMMR:
5188 case AARCH64_OPND_IMMS:
5189 po_imm_or_fail (0, 63);
5190 info->imm.value = val;
5193 case AARCH64_OPND_IMM0:
5194 po_imm_nc_or_fail ();
5197 set_fatal_syntax_error (_("immediate zero expected"));
5200 info->imm.value = 0;
5203 case AARCH64_OPND_FPIMM0:
5206 bfd_boolean res1 = FALSE, res2 = FALSE;
5207 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5208 it is probably not worth the effort to support it. */
5209 if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE,
5212 || !(res2 = parse_constant_immediate (&str, &val,
5215 if ((res1 && qfloat == 0) || (res2 && val == 0))
5217 info->imm.value = 0;
5218 info->imm.is_fp = 1;
5221 set_fatal_syntax_error (_("immediate zero expected"));
5225 case AARCH64_OPND_IMM_MOV:
5228 if (reg_name_p (str, REG_TYPE_R_Z_SP) ||
5229 reg_name_p (str, REG_TYPE_VN))
5232 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5234 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5235 later. fix_mov_imm_insn will try to determine a machine
5236 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5237 message if the immediate cannot be moved by a single
5239 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5240 inst.base.operands[i].skip = 1;
5244 case AARCH64_OPND_SIMD_IMM:
5245 case AARCH64_OPND_SIMD_IMM_SFT:
5246 if (! parse_big_immediate (&str, &val, imm_reg_type))
5248 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5250 /* need_libopcodes_p */ 1,
5253 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5254 shift, we don't check it here; we leave the checking to
5255 the libopcodes (operand_general_constraint_met_p). By
5256 doing this, we achieve better diagnostics. */
5257 if (skip_past_comma (&str)
5258 && ! parse_shift (&str, info, SHIFTED_LSL_MSL))
5260 if (!info->shifter.operator_present
5261 && info->type == AARCH64_OPND_SIMD_IMM_SFT)
5263 /* Default to LSL if not present. Libopcodes prefers shifter
5264 kind to be explicit. */
5265 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5266 info->shifter.kind = AARCH64_MOD_LSL;
5270 case AARCH64_OPND_FPIMM:
5271 case AARCH64_OPND_SIMD_FPIMM:
5275 = (aarch64_get_qualifier_esize (inst.base.operands[0].qualifier)
5277 if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type)
5278 || !aarch64_imm_float_p (qfloat))
5281 set_fatal_syntax_error (_("invalid floating-point"
5285 inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat);
5286 inst.base.operands[i].imm.is_fp = 1;
5290 case AARCH64_OPND_LIMM:
5291 po_misc_or_fail (parse_shifter_operand (&str, info,
5292 SHIFTED_LOGIC_IMM));
5293 if (info->shifter.operator_present)
5295 set_fatal_syntax_error
5296 (_("shift not allowed for bitmask immediate"));
5299 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5301 /* need_libopcodes_p */ 1,
5305 case AARCH64_OPND_AIMM:
5306 if (opcode->op == OP_ADD)
5307 /* ADD may have relocation types. */
5308 po_misc_or_fail (parse_shifter_operand_reloc (&str, info,
5309 SHIFTED_ARITH_IMM));
5311 po_misc_or_fail (parse_shifter_operand (&str, info,
5312 SHIFTED_ARITH_IMM));
5313 switch (inst.reloc.type)
5315 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
5316 info->shifter.amount = 12;
5318 case BFD_RELOC_UNUSED:
5319 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
5320 if (info->shifter.kind != AARCH64_MOD_NONE)
5321 inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT;
5322 inst.reloc.pc_rel = 0;
5327 info->imm.value = 0;
5328 if (!info->shifter.operator_present)
5330 /* Default to LSL if not present. Libopcodes prefers shifter
5331 kind to be explicit. */
5332 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5333 info->shifter.kind = AARCH64_MOD_LSL;
5337 case AARCH64_OPND_HALF:
5339 /* #<imm16> or relocation. */
5340 int internal_fixup_p;
5341 po_misc_or_fail (parse_half (&str, &internal_fixup_p));
5342 if (internal_fixup_p)
5343 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
5344 skip_whitespace (str);
5345 if (skip_past_comma (&str))
5347 /* {, LSL #<shift>} */
5348 if (! aarch64_gas_internal_fixup_p ())
5350 set_fatal_syntax_error (_("can't mix relocation modifier "
5351 "with explicit shift"));
5354 po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
5357 inst.base.operands[i].shifter.amount = 0;
5358 inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
5359 inst.base.operands[i].imm.value = 0;
5360 if (! process_movw_reloc_info ())
5365 case AARCH64_OPND_EXCEPTION:
5366 po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp,
5368 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5370 /* need_libopcodes_p */ 0,
5374 case AARCH64_OPND_NZCV:
5376 const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4);
5380 info->imm.value = nzcv->value;
5383 po_imm_or_fail (0, 15);
5384 info->imm.value = val;
5388 case AARCH64_OPND_COND:
5389 case AARCH64_OPND_COND1:
5390 info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
5392 if (info->cond == NULL)
5394 set_syntax_error (_("invalid condition"));
5397 else if (operands[i] == AARCH64_OPND_COND1
5398 && (info->cond->value & 0xe) == 0xe)
5400 /* Not allow AL or NV. */
5401 set_default_error ();
5406 case AARCH64_OPND_ADDR_ADRP:
5407 po_misc_or_fail (parse_adrp (&str));
5408 /* Clear the value as operand needs to be relocated. */
5409 info->imm.value = 0;
5412 case AARCH64_OPND_ADDR_PCREL14:
5413 case AARCH64_OPND_ADDR_PCREL19:
5414 case AARCH64_OPND_ADDR_PCREL21:
5415 case AARCH64_OPND_ADDR_PCREL26:
5416 po_misc_or_fail (parse_address (&str, info));
5417 if (!info->addr.pcrel)
5419 set_syntax_error (_("invalid pc-relative address"));
5422 if (inst.gen_lit_pool
5423 && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT))
5425 /* Only permit "=value" in the literal load instructions.
5426 The literal will be generated by programmer_friendly_fixup. */
5427 set_syntax_error (_("invalid use of \"=immediate\""));
5430 if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str))
5432 set_syntax_error (_("unrecognized relocation suffix"));
5435 if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
5437 info->imm.value = inst.reloc.exp.X_add_number;
5438 inst.reloc.type = BFD_RELOC_UNUSED;
5442 info->imm.value = 0;
5443 if (inst.reloc.type == BFD_RELOC_UNUSED)
5444 switch (opcode->iclass)
5448 /* e.g. CBZ or B.COND */
5449 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5450 inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
5454 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
5455 inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
5459 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
5461 (opcode->op == OP_BL) ? BFD_RELOC_AARCH64_CALL26
5462 : BFD_RELOC_AARCH64_JUMP26;
5465 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5466 inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
5469 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
5470 inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
5476 inst.reloc.pc_rel = 1;
5480 case AARCH64_OPND_ADDR_SIMPLE:
5481 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
5483 /* [<Xn|SP>{, #<simm>}] */
5485 /* First use the normal address-parsing routines, to get
5486 the usual syntax errors. */
5487 po_misc_or_fail (parse_address (&str, info));
5488 if (info->addr.pcrel || info->addr.offset.is_reg
5489 || !info->addr.preind || info->addr.postind
5490 || info->addr.writeback)
5492 set_syntax_error (_("invalid addressing mode"));
5496 /* Then retry, matching the specific syntax of these addresses. */
5498 po_char_or_fail ('[');
5499 po_reg_or_fail (REG_TYPE_R64_SP);
5500 /* Accept optional ", #0". */
5501 if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
5502 && skip_past_char (&str, ','))
5504 skip_past_char (&str, '#');
5505 if (! skip_past_char (&str, '0'))
5507 set_fatal_syntax_error
5508 (_("the optional immediate offset can only be 0"));
5512 po_char_or_fail (']');
5516 case AARCH64_OPND_ADDR_REGOFF:
5517 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5518 po_misc_or_fail (parse_address (&str, info));
5519 if (info->addr.pcrel || !info->addr.offset.is_reg
5520 || !info->addr.preind || info->addr.postind
5521 || info->addr.writeback)
5523 set_syntax_error (_("invalid addressing mode"));
5526 if (!info->shifter.operator_present)
5528 /* Default to LSL if not present. Libopcodes prefers shifter
5529 kind to be explicit. */
5530 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5531 info->shifter.kind = AARCH64_MOD_LSL;
5533 /* Qualifier to be deduced by libopcodes. */
5536 case AARCH64_OPND_ADDR_SIMM7:
5537 po_misc_or_fail (parse_address (&str, info));
5538 if (info->addr.pcrel || info->addr.offset.is_reg
5539 || (!info->addr.preind && !info->addr.postind))
5541 set_syntax_error (_("invalid addressing mode"));
5544 if (inst.reloc.type != BFD_RELOC_UNUSED)
5546 set_syntax_error (_("relocation not allowed"));
5549 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5551 /* need_libopcodes_p */ 1,
5555 case AARCH64_OPND_ADDR_SIMM9:
5556 case AARCH64_OPND_ADDR_SIMM9_2:
5557 po_misc_or_fail (parse_address (&str, info));
5558 if (info->addr.pcrel || info->addr.offset.is_reg
5559 || (!info->addr.preind && !info->addr.postind)
5560 || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
5561 && info->addr.writeback))
5563 set_syntax_error (_("invalid addressing mode"));
5566 if (inst.reloc.type != BFD_RELOC_UNUSED)
5568 set_syntax_error (_("relocation not allowed"));
5571 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5573 /* need_libopcodes_p */ 1,
5577 case AARCH64_OPND_ADDR_UIMM12:
5578 po_misc_or_fail (parse_address (&str, info));
5579 if (info->addr.pcrel || info->addr.offset.is_reg
5580 || !info->addr.preind || info->addr.writeback)
5582 set_syntax_error (_("invalid addressing mode"));
5585 if (inst.reloc.type == BFD_RELOC_UNUSED)
5586 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5587 else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
5589 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12)
5591 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC))
5592 inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
5593 /* Leave qualifier to be determined by libopcodes. */
5596 case AARCH64_OPND_SIMD_ADDR_POST:
5597 /* [<Xn|SP>], <Xm|#<amount>> */
5598 po_misc_or_fail (parse_address (&str, info));
5599 if (!info->addr.postind || !info->addr.writeback)
5601 set_syntax_error (_("invalid addressing mode"));
5604 if (!info->addr.offset.is_reg)
5606 if (inst.reloc.exp.X_op == O_constant)
5607 info->addr.offset.imm = inst.reloc.exp.X_add_number;
5610 set_fatal_syntax_error
5611 (_("writeback value should be an immediate constant"));
5618 case AARCH64_OPND_SYSREG:
5619 if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0))
5622 set_syntax_error (_("unknown or missing system register name"));
5625 inst.base.operands[i].sysreg = val;
5628 case AARCH64_OPND_PSTATEFIELD:
5629 if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1))
5632 set_syntax_error (_("unknown or missing PSTATE field name"));
5635 inst.base.operands[i].pstatefield = val;
5638 case AARCH64_OPND_SYSREG_IC:
5639 inst.base.operands[i].sysins_op =
5640 parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
5642 case AARCH64_OPND_SYSREG_DC:
5643 inst.base.operands[i].sysins_op =
5644 parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
5646 case AARCH64_OPND_SYSREG_AT:
5647 inst.base.operands[i].sysins_op =
5648 parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
5650 case AARCH64_OPND_SYSREG_TLBI:
5651 inst.base.operands[i].sysins_op =
5652 parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
5654 if (inst.base.operands[i].sysins_op == NULL)
5656 set_fatal_syntax_error ( _("unknown or missing operation name"));
5661 case AARCH64_OPND_BARRIER:
5662 case AARCH64_OPND_BARRIER_ISB:
5663 val = parse_barrier (&str);
5664 if (val != PARSE_FAIL
5665 && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf)
5667 /* ISB only accepts options name 'sy'. */
5669 (_("the specified option is not accepted in ISB"));
5670 /* Turn off backtrack as this optional operand is present. */
5674 /* This is an extension to accept a 0..15 immediate. */
5675 if (val == PARSE_FAIL)
5676 po_imm_or_fail (0, 15);
5677 info->barrier = aarch64_barrier_options + val;
5680 case AARCH64_OPND_PRFOP:
5681 val = parse_pldop (&str);
5682 /* This is an extension to accept a 0..31 immediate. */
5683 if (val == PARSE_FAIL)
5684 po_imm_or_fail (0, 31);
5685 inst.base.operands[i].prfop = aarch64_prfops + val;
5688 case AARCH64_OPND_BARRIER_PSB:
5689 val = parse_barrier_psb (&str, &(info->hint_option));
5690 if (val == PARSE_FAIL)
5695 as_fatal (_("unhandled operand code %d"), operands[i]);
5698 /* If we get here, this operand was successfully parsed. */
5699 inst.base.operands[i].present = 1;
5703 /* The parse routine should already have set the error, but in case
5704 not, set a default one here. */
5706 set_default_error ();
5708 if (! backtrack_pos)
5709 goto parse_operands_return;
5712 /* We reach here because this operand is marked as optional, and
5713 either no operand was supplied or the operand was supplied but it
5714 was syntactically incorrect. In the latter case we report an
5715 error. In the former case we perform a few more checks before
5716 dropping through to the code to insert the default operand. */
5718 char *tmp = backtrack_pos;
5719 char endchar = END_OF_INSN;
5721 if (i != (aarch64_num_of_operands (opcode) - 1))
5723 skip_past_char (&tmp, ',');
5725 if (*tmp != endchar)
5726 /* The user has supplied an operand in the wrong format. */
5727 goto parse_operands_return;
5729 /* Make sure there is not a comma before the optional operand.
5730 For example the fifth operand of 'sys' is optional:
5732 sys #0,c0,c0,#0, <--- wrong
5733 sys #0,c0,c0,#0 <--- correct. */
5734 if (comma_skipped_p && i && endchar == END_OF_INSN)
5736 set_fatal_syntax_error
5737 (_("unexpected comma before the omitted optional operand"));
5738 goto parse_operands_return;
5742 /* Reaching here means we are dealing with an optional operand that is
5743 omitted from the assembly line. */
5744 gas_assert (optional_operand_p (opcode, i));
5746 process_omitted_operand (operands[i], opcode, i, info);
5748 /* Try again, skipping the optional operand at backtrack_pos. */
5749 str = backtrack_pos;
5752 /* Clear any error record after the omitted optional operand has been
5753 successfully handled. */
5757 /* Check if we have parsed all the operands. */
5758 if (*str != '\0' && ! error_p ())
5760 /* Set I to the index of the last present operand; this is
5761 for the purpose of diagnostics. */
5762 for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i)
5764 set_fatal_syntax_error
5765 (_("unexpected characters following instruction"));
5768 parse_operands_return:
5772 DEBUG_TRACE ("parsing FAIL: %s - %s",
5773 operand_mismatch_kind_names[get_error_kind ()],
5774 get_error_message ());
5775 /* Record the operand error properly; this is useful when there
5776 are multiple instruction templates for a mnemonic name, so that
5777 later on, we can select the error that most closely describes
5779 record_operand_error (opcode, i, get_error_kind (),
5780 get_error_message ());
5785 DEBUG_TRACE ("parsing SUCCESS");
5790 /* It does some fix-up to provide some programmer friendly feature while
5791 keeping the libopcodes happy, i.e. libopcodes only accepts
5792 the preferred architectural syntax.
5793 Return FALSE if there is any failure; otherwise return TRUE. */
5796 programmer_friendly_fixup (aarch64_instruction *instr)
5798 aarch64_inst *base = &instr->base;
5799 const aarch64_opcode *opcode = base->opcode;
5800 enum aarch64_op op = opcode->op;
5801 aarch64_opnd_info *operands = base->operands;
5803 DEBUG_TRACE ("enter");
5805 switch (opcode->iclass)
5808 /* TBNZ Xn|Wn, #uimm6, label
5809 Test and Branch Not Zero: conditionally jumps to label if bit number
5810 uimm6 in register Xn is not zero. The bit number implies the width of
5811 the register, which may be written and should be disassembled as Wn if
5812 uimm is less than 32. */
5813 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
5815 if (operands[1].imm.value >= 32)
5817 record_operand_out_of_range_error (opcode, 1, _("immediate value"),
5821 operands[0].qualifier = AARCH64_OPND_QLF_X;
5825 /* LDR Wt, label | =value
5826 As a convenience assemblers will typically permit the notation
5827 "=value" in conjunction with the pc-relative literal load instructions
5828 to automatically place an immediate value or symbolic address in a
5829 nearby literal pool and generate a hidden label which references it.
5830 ISREG has been set to 0 in the case of =value. */
5831 if (instr->gen_lit_pool
5832 && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT))
5834 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
5835 if (op == OP_LDRSW_LIT)
5837 if (instr->reloc.exp.X_op != O_constant
5838 && instr->reloc.exp.X_op != O_big
5839 && instr->reloc.exp.X_op != O_symbol)
5841 record_operand_error (opcode, 1,
5842 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
5843 _("constant expression expected"));
5846 if (! add_to_lit_pool (&instr->reloc.exp, size))
5848 record_operand_error (opcode, 1,
5849 AARCH64_OPDE_OTHER_ERROR,
5850 _("literal pool insertion failed"));
5858 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5859 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5860 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5861 A programmer-friendly assembler should accept a destination Xd in
5862 place of Wd, however that is not the preferred form for disassembly.
5864 if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW)
5865 && operands[1].qualifier == AARCH64_OPND_QLF_W
5866 && operands[0].qualifier == AARCH64_OPND_QLF_X)
5867 operands[0].qualifier = AARCH64_OPND_QLF_W;
5872 /* In the 64-bit form, the final register operand is written as Wm
5873 for all but the (possibly omitted) UXTX/LSL and SXTX
5875 As a programmer-friendly assembler, we accept e.g.
5876 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5877 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5878 int idx = aarch64_operand_index (opcode->operands,
5879 AARCH64_OPND_Rm_EXT);
5880 gas_assert (idx == 1 || idx == 2);
5881 if (operands[0].qualifier == AARCH64_OPND_QLF_X
5882 && operands[idx].qualifier == AARCH64_OPND_QLF_X
5883 && operands[idx].shifter.kind != AARCH64_MOD_LSL
5884 && operands[idx].shifter.kind != AARCH64_MOD_UXTX
5885 && operands[idx].shifter.kind != AARCH64_MOD_SXTX)
5886 operands[idx].qualifier = AARCH64_OPND_QLF_W;
5894 DEBUG_TRACE ("exit with SUCCESS");
5898 /* Check for loads and stores that will cause unpredictable behavior. */
5901 warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
5903 aarch64_inst *base = &instr->base;
5904 const aarch64_opcode *opcode = base->opcode;
5905 const aarch64_opnd_info *opnds = base->operands;
5906 switch (opcode->iclass)
5912 /* Loading/storing the base register is unpredictable if writeback. */
5913 if ((aarch64_get_operand_class (opnds[0].type)
5914 == AARCH64_OPND_CLASS_INT_REG)
5915 && opnds[0].reg.regno == opnds[1].addr.base_regno
5916 && opnds[1].addr.base_regno != REG_SP
5917 && opnds[1].addr.writeback)
5918 as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
5921 case ldstnapair_offs:
5922 case ldstpair_indexed:
5923 /* Loading/storing the base register is unpredictable if writeback. */
5924 if ((aarch64_get_operand_class (opnds[0].type)
5925 == AARCH64_OPND_CLASS_INT_REG)
5926 && (opnds[0].reg.regno == opnds[2].addr.base_regno
5927 || opnds[1].reg.regno == opnds[2].addr.base_regno)
5928 && opnds[2].addr.base_regno != REG_SP
5929 && opnds[2].addr.writeback)
5930 as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
5931 /* Load operations must load different registers. */
5932 if ((opcode->opcode & (1 << 22))
5933 && opnds[0].reg.regno == opnds[1].reg.regno)
5934 as_warn (_("unpredictable load of register pair -- `%s'"), str);
5941 /* A wrapper function to interface with libopcodes on encoding and
5942 record the error message if there is any.
5944 Return TRUE on success; otherwise return FALSE. */
5947 do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
5950 aarch64_operand_error error_info;
5951 error_info.kind = AARCH64_OPDE_NIL;
5952 if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
5956 gas_assert (error_info.kind != AARCH64_OPDE_NIL);
5957 record_operand_error_info (opcode, &error_info);
5962 #ifdef DEBUG_AARCH64
5964 dump_opcode_operands (const aarch64_opcode *opcode)
5967 while (opcode->operands[i] != AARCH64_OPND_NIL)
5969 aarch64_verbose ("\t\t opnd%d: %s", i,
5970 aarch64_get_operand_name (opcode->operands[i])[0] != '\0'
5971 ? aarch64_get_operand_name (opcode->operands[i])
5972 : aarch64_get_operand_desc (opcode->operands[i]));
5976 #endif /* DEBUG_AARCH64 */
5978 /* This is the guts of the machine-dependent assembler. STR points to a
5979 machine dependent instruction. This function is supposed to emit
5980 the frags/bytes it assembles to. */
5983 md_assemble (char *str)
5986 templates *template;
5987 aarch64_opcode *opcode;
5988 aarch64_inst *inst_base;
5989 unsigned saved_cond;
5991 /* Align the previous label if needed. */
5992 if (last_label_seen != NULL)
5994 symbol_set_frag (last_label_seen, frag_now);
5995 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
5996 S_SET_SEGMENT (last_label_seen, now_seg);
5999 inst.reloc.type = BFD_RELOC_UNUSED;
6001 DEBUG_TRACE ("\n\n");
6002 DEBUG_TRACE ("==============================");
6003 DEBUG_TRACE ("Enter md_assemble with %s", str);
6005 template = opcode_lookup (&p);
6008 /* It wasn't an instruction, but it might be a register alias of
6009 the form alias .req reg directive. */
6010 if (!create_register_alias (str, p))
6011 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
6016 skip_whitespace (p);
6019 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6020 get_mnemonic_name (str), str);
6024 init_operand_error_report ();
6026 /* Sections are assumed to start aligned. In executable section, there is no
6027 MAP_DATA symbol pending. So we only align the address during
6028 MAP_DATA --> MAP_INSN transition.
6029 For other sections, this is not guaranteed. */
6030 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
6031 if (!need_pass_2 && subseg_text_p (now_seg) && mapstate == MAP_DATA)
6032 frag_align_code (2, 0);
6034 saved_cond = inst.cond;
6035 reset_aarch64_instruction (&inst);
6036 inst.cond = saved_cond;
6038 /* Iterate through all opcode entries with the same mnemonic name. */
6041 opcode = template->opcode;
6043 DEBUG_TRACE ("opcode %s found", opcode->name);
6044 #ifdef DEBUG_AARCH64
6046 dump_opcode_operands (opcode);
6047 #endif /* DEBUG_AARCH64 */
6049 mapping_state (MAP_INSN);
6051 inst_base = &inst.base;
6052 inst_base->opcode = opcode;
6054 /* Truly conditionally executed instructions, e.g. b.cond. */
6055 if (opcode->flags & F_COND)
6057 gas_assert (inst.cond != COND_ALWAYS);
6058 inst_base->cond = get_cond_from_value (inst.cond);
6059 DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]);
6061 else if (inst.cond != COND_ALWAYS)
6063 /* It shouldn't arrive here, where the assembly looks like a
6064 conditional instruction but the found opcode is unconditional. */
6069 if (parse_operands (p, opcode)
6070 && programmer_friendly_fixup (&inst)
6071 && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
6073 /* Check that this instruction is supported for this CPU. */
6074 if (!opcode->avariant
6075 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant))
6077 as_bad (_("selected processor does not support `%s'"), str);
6081 warn_unpredictable_ldst (&inst, str);
6083 if (inst.reloc.type == BFD_RELOC_UNUSED
6084 || !inst.reloc.need_libopcodes_p)
6088 /* If there is relocation generated for the instruction,
6089 store the instruction information for the future fix-up. */
6090 struct aarch64_inst *copy;
6091 gas_assert (inst.reloc.type != BFD_RELOC_UNUSED);
6092 copy = XNEW (struct aarch64_inst);
6093 memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
6099 template = template->next;
6100 if (template != NULL)
6102 reset_aarch64_instruction (&inst);
6103 inst.cond = saved_cond;
6106 while (template != NULL);
6108 /* Issue the error messages if any. */
6109 output_operand_error_report (str);
6112 /* Various frobbings of labels and their addresses. */
6115 aarch64_start_line_hook (void)
6117 last_label_seen = NULL;
6121 aarch64_frob_label (symbolS * sym)
6123 last_label_seen = sym;
6125 dwarf2_emit_label (sym);
6129 aarch64_data_in_code (void)
6131 if (!strncmp (input_line_pointer + 1, "data:", 5))
6133 *input_line_pointer = '/';
6134 input_line_pointer += 5;
6135 *input_line_pointer = 0;
6143 aarch64_canonicalize_symbol_name (char *name)
6147 if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data"))
6148 *(name + len - 5) = 0;
6153 /* Table of all register names defined by default. The user can
6154 define additional names with .req. Note that all register names
6155 should appear in both upper and lowercase variants. Some registers
6156 also have mixed-case names. */
6158 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6159 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6160 #define REGSET31(p,t) \
6161 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6162 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6163 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6164 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6165 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6166 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6167 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6168 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6169 #define REGSET(p,t) \
6170 REGSET31(p,t), REGNUM(p,31,t)
6172 /* These go into aarch64_reg_hsh hash-table. */
6173 static const reg_entry reg_names[] = {
6174 /* Integer registers. */
6175 REGSET31 (x, R_64), REGSET31 (X, R_64),
6176 REGSET31 (w, R_32), REGSET31 (W, R_32),
6178 REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
6179 REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
6181 REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
6182 REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
6184 /* Coprocessor register numbers. */
6185 REGSET (c, CN), REGSET (C, CN),
6187 /* Floating-point single precision registers. */
6188 REGSET (s, FP_S), REGSET (S, FP_S),
6190 /* Floating-point double precision registers. */
6191 REGSET (d, FP_D), REGSET (D, FP_D),
6193 /* Floating-point half precision registers. */
6194 REGSET (h, FP_H), REGSET (H, FP_H),
6196 /* Floating-point byte precision registers. */
6197 REGSET (b, FP_B), REGSET (B, FP_B),
6199 /* Floating-point quad precision registers. */
6200 REGSET (q, FP_Q), REGSET (Q, FP_Q),
6202 /* FP/SIMD registers. */
6203 REGSET (v, VN), REGSET (V, VN),
6218 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6219 static const asm_nzcv nzcv_names[] = {
6220 {"nzcv", B (n, z, c, v)},
6221 {"nzcV", B (n, z, c, V)},
6222 {"nzCv", B (n, z, C, v)},
6223 {"nzCV", B (n, z, C, V)},
6224 {"nZcv", B (n, Z, c, v)},
6225 {"nZcV", B (n, Z, c, V)},
6226 {"nZCv", B (n, Z, C, v)},
6227 {"nZCV", B (n, Z, C, V)},
6228 {"Nzcv", B (N, z, c, v)},
6229 {"NzcV", B (N, z, c, V)},
6230 {"NzCv", B (N, z, C, v)},
6231 {"NzCV", B (N, z, C, V)},
6232 {"NZcv", B (N, Z, c, v)},
6233 {"NZcV", B (N, Z, c, V)},
6234 {"NZCv", B (N, Z, C, v)},
6235 {"NZCV", B (N, Z, C, V)}
6248 /* MD interface: bits in the object file. */
6250 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6251 for use in the a.out file, and stores them in the array pointed to by buf.
6252 This knows about the endian-ness of the target machine and does
6253 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6254 2 (short) and 4 (long) Floating numbers are put out as a series of
6255 LITTLENUMS (shorts, here at least). */
6258 md_number_to_chars (char *buf, valueT val, int n)
6260 if (target_big_endian)
6261 number_to_chars_bigendian (buf, val, n);
6263 number_to_chars_littleendian (buf, val, n);
6266 /* MD interface: Sections. */
6268 /* Estimate the size of a frag before relaxing. Assume everything fits in
6272 md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED)
6278 /* Round up a section size to the appropriate boundary. */
6281 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
6286 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6287 of an rs_align_code fragment.
6289 Here we fill the frag with the appropriate info for padding the
6290 output stream. The resulting frag will consist of a fixed (fr_fix)
6291 and of a repeating (fr_var) part.
6293 The fixed content is always emitted before the repeating content and
6294 these two parts are used as follows in constructing the output:
6295 - the fixed part will be used to align to a valid instruction word
6296 boundary, in case that we start at a misaligned address; as no
6297 executable instruction can live at the misaligned location, we
6298 simply fill with zeros;
6299 - the variable part will be used to cover the remaining padding and
6300 we fill using the AArch64 NOP instruction.
6302 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6303 enough storage space for up to 3 bytes for padding the back to a valid
6304 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6307 aarch64_handle_align (fragS * fragP)
6309 /* NOP = d503201f */
6310 /* AArch64 instructions are always little-endian. */
6311 static unsigned char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6313 int bytes, fix, noop_size;
6316 if (fragP->fr_type != rs_align_code)
6319 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
6320 p = fragP->fr_literal + fragP->fr_fix;
6323 gas_assert (fragP->tc_frag_data.recorded);
6326 noop_size = sizeof (aarch64_noop);
6328 fix = bytes & (noop_size - 1);
6332 insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
6336 fragP->fr_fix += fix;
6340 memcpy (p, aarch64_noop, noop_size);
6341 fragP->fr_var = noop_size;
6344 /* Perform target specific initialisation of a frag.
6345 Note - despite the name this initialisation is not done when the frag
6346 is created, but only when its type is assigned. A frag can be created
6347 and used a long time before its type is set, so beware of assuming that
6348 this initialisationis performed first. */
6352 aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED,
6353 int max_chars ATTRIBUTE_UNUSED)
6357 #else /* OBJ_ELF is defined. */
6359 aarch64_init_frag (fragS * fragP, int max_chars)
6361 /* Record a mapping symbol for alignment frags. We will delete this
6362 later if the alignment ends up empty. */
6363 if (!fragP->tc_frag_data.recorded)
6364 fragP->tc_frag_data.recorded = 1;
6366 switch (fragP->fr_type)
6370 mapping_state_2 (MAP_DATA, max_chars);
6373 /* PR 20364: We can get alignment frags in code sections,
6374 so do not just assume that we should use the MAP_DATA state. */
6375 mapping_state_2 (subseg_text_p (now_seg) ? MAP_INSN : MAP_DATA, max_chars);
6378 mapping_state_2 (MAP_INSN, max_chars);
6385 /* Initialize the DWARF-2 unwind information for this procedure. */
6388 tc_aarch64_frame_initial_instructions (void)
6390 cfi_add_CFA_def_cfa (REG_SP, 0);
6392 #endif /* OBJ_ELF */
6394 /* Convert REGNAME to a DWARF-2 register number. */
6397 tc_aarch64_regname_to_dw2regnum (char *regname)
6399 const reg_entry *reg = parse_reg (®name);
6405 case REG_TYPE_SP_32:
6406 case REG_TYPE_SP_64:
6416 return reg->number + 64;
6424 /* Implement DWARF2_ADDR_SIZE. */
6427 aarch64_dwarf2_addr_size (void)
6429 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6433 return bfd_arch_bits_per_address (stdoutput) / 8;
6436 /* MD interface: Symbol and relocation handling. */
6438 /* Return the address within the segment that a PC-relative fixup is
6439 relative to. For AArch64 PC-relative fixups applied to instructions
6440 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6443 md_pcrel_from_section (fixS * fixP, segT seg)
6445 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
6447 /* If this is pc-relative and we are going to emit a relocation
6448 then we just want to put out any pipeline compensation that the linker
6449 will need. Otherwise we want to use the calculated base. */
6451 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
6452 || aarch64_force_relocation (fixP)))
6455 /* AArch64 should be consistent for all pc-relative relocations. */
6456 return base + AARCH64_PCREL_OFFSET;
6459 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6460 Otherwise we have no need to default values of symbols. */
6463 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
6466 if (name[0] == '_' && name[1] == 'G'
6467 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
6471 if (symbol_find (name))
6472 as_bad (_("GOT already in the symbol table"));
6474 GOT_symbol = symbol_new (name, undefined_section,
6475 (valueT) 0, &zero_address_frag);
6485 /* Return non-zero if the indicated VALUE has overflowed the maximum
6486 range expressible by a unsigned number with the indicated number of
6490 unsigned_overflow (valueT value, unsigned bits)
6493 if (bits >= sizeof (valueT) * 8)
6495 lim = (valueT) 1 << bits;
6496 return (value >= lim);
6500 /* Return non-zero if the indicated VALUE has overflowed the maximum
6501 range expressible by an signed number with the indicated number of
6505 signed_overflow (offsetT value, unsigned bits)
6508 if (bits >= sizeof (offsetT) * 8)
6510 lim = (offsetT) 1 << (bits - 1);
6511 return (value < -lim || value >= lim);
6514 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6515 unsigned immediate offset load/store instruction, try to encode it as
6516 an unscaled, 9-bit, signed immediate offset load/store instruction.
6517 Return TRUE if it is successful; otherwise return FALSE.
6519 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6520 in response to the standard LDR/STR mnemonics when the immediate offset is
6521 unambiguous, i.e. when it is negative or unaligned. */
6524 try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
6527 enum aarch64_op new_op;
6528 const aarch64_opcode *new_opcode;
6530 gas_assert (instr->opcode->iclass == ldst_pos);
6532 switch (instr->opcode->op)
6534 case OP_LDRB_POS:new_op = OP_LDURB; break;
6535 case OP_STRB_POS: new_op = OP_STURB; break;
6536 case OP_LDRSB_POS: new_op = OP_LDURSB; break;
6537 case OP_LDRH_POS: new_op = OP_LDURH; break;
6538 case OP_STRH_POS: new_op = OP_STURH; break;
6539 case OP_LDRSH_POS: new_op = OP_LDURSH; break;
6540 case OP_LDR_POS: new_op = OP_LDUR; break;
6541 case OP_STR_POS: new_op = OP_STUR; break;
6542 case OP_LDRF_POS: new_op = OP_LDURV; break;
6543 case OP_STRF_POS: new_op = OP_STURV; break;
6544 case OP_LDRSW_POS: new_op = OP_LDURSW; break;
6545 case OP_PRFM_POS: new_op = OP_PRFUM; break;
6546 default: new_op = OP_NIL; break;
6549 if (new_op == OP_NIL)
6552 new_opcode = aarch64_get_opcode (new_op);
6553 gas_assert (new_opcode != NULL);
6555 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6556 instr->opcode->op, new_opcode->op);
6558 aarch64_replace_opcode (instr, new_opcode);
6560 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6561 qualifier matching may fail because the out-of-date qualifier will
6562 prevent the operand being updated with a new and correct qualifier. */
6563 idx = aarch64_operand_index (instr->opcode->operands,
6564 AARCH64_OPND_ADDR_SIMM9);
6565 gas_assert (idx == 1);
6566 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
6568 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6570 if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
6576 /* Called by fix_insn to fix a MOV immediate alias instruction.
6578 Operand for a generic move immediate instruction, which is an alias
6579 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6580 a 32-bit/64-bit immediate value into general register. An assembler error
6581 shall result if the immediate cannot be created by a single one of these
6582 instructions. If there is a choice, then to ensure reversability an
6583 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6586 fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
6588 const aarch64_opcode *opcode;
6590 /* Need to check if the destination is SP/ZR. The check has to be done
6591 before any aarch64_replace_opcode. */
6592 int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]);
6593 int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]);
6595 instr->operands[1].imm.value = value;
6596 instr->operands[1].skip = 0;
6600 /* Try the MOVZ alias. */
6601 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
6602 aarch64_replace_opcode (instr, opcode);
6603 if (aarch64_opcode_encode (instr->opcode, instr,
6604 &instr->value, NULL, NULL))
6606 put_aarch64_insn (buf, instr->value);
6609 /* Try the MOVK alias. */
6610 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
6611 aarch64_replace_opcode (instr, opcode);
6612 if (aarch64_opcode_encode (instr->opcode, instr,
6613 &instr->value, NULL, NULL))
6615 put_aarch64_insn (buf, instr->value);
6620 if (try_mov_bitmask_p)
6622 /* Try the ORR alias. */
6623 opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
6624 aarch64_replace_opcode (instr, opcode);
6625 if (aarch64_opcode_encode (instr->opcode, instr,
6626 &instr->value, NULL, NULL))
6628 put_aarch64_insn (buf, instr->value);
6633 as_bad_where (fixP->fx_file, fixP->fx_line,
6634 _("immediate cannot be moved by a single instruction"));
6637 /* An instruction operand which is immediate related may have symbol used
6638 in the assembly, e.g.
6641 .set u32, 0x00ffff00
6643 At the time when the assembly instruction is parsed, a referenced symbol,
6644 like 'u32' in the above example may not have been seen; a fixS is created
6645 in such a case and is handled here after symbols have been resolved.
6646 Instruction is fixed up with VALUE using the information in *FIXP plus
6647 extra information in FLAGS.
6649 This function is called by md_apply_fix to fix up instructions that need
6650 a fix-up described above but does not involve any linker-time relocation. */
6653 fix_insn (fixS *fixP, uint32_t flags, offsetT value)
6657 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6658 enum aarch64_opnd opnd = fixP->tc_fix_data.opnd;
6659 aarch64_inst *new_inst = fixP->tc_fix_data.inst;
6663 /* Now the instruction is about to be fixed-up, so the operand that
6664 was previously marked as 'ignored' needs to be unmarked in order
6665 to get the encoding done properly. */
6666 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6667 new_inst->operands[idx].skip = 0;
6670 gas_assert (opnd != AARCH64_OPND_NIL);
6674 case AARCH64_OPND_EXCEPTION:
6675 if (unsigned_overflow (value, 16))
6676 as_bad_where (fixP->fx_file, fixP->fx_line,
6677 _("immediate out of range"));
6678 insn = get_aarch64_insn (buf);
6679 insn |= encode_svc_imm (value);
6680 put_aarch64_insn (buf, insn);
6683 case AARCH64_OPND_AIMM:
6684 /* ADD or SUB with immediate.
6685 NOTE this assumes we come here with a add/sub shifted reg encoding
6686 3 322|2222|2 2 2 21111 111111
6687 1 098|7654|3 2 1 09876 543210 98765 43210
6688 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6689 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6690 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6691 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6693 3 322|2222|2 2 221111111111
6694 1 098|7654|3 2 109876543210 98765 43210
6695 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6696 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6697 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6698 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6699 Fields sf Rn Rd are already set. */
6700 insn = get_aarch64_insn (buf);
6704 insn = reencode_addsub_switch_add_sub (insn);
6708 if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0
6709 && unsigned_overflow (value, 12))
6711 /* Try to shift the value by 12 to make it fit. */
6712 if (((value >> 12) << 12) == value
6713 && ! unsigned_overflow (value, 12 + 12))
6716 insn |= encode_addsub_imm_shift_amount (1);
6720 if (unsigned_overflow (value, 12))
6721 as_bad_where (fixP->fx_file, fixP->fx_line,
6722 _("immediate out of range"));
6724 insn |= encode_addsub_imm (value);
6726 put_aarch64_insn (buf, insn);
6729 case AARCH64_OPND_SIMD_IMM:
6730 case AARCH64_OPND_SIMD_IMM_SFT:
6731 case AARCH64_OPND_LIMM:
6732 /* Bit mask immediate. */
6733 gas_assert (new_inst != NULL);
6734 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6735 new_inst->operands[idx].imm.value = value;
6736 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6737 &new_inst->value, NULL, NULL))
6738 put_aarch64_insn (buf, new_inst->value);
6740 as_bad_where (fixP->fx_file, fixP->fx_line,
6741 _("invalid immediate"));
6744 case AARCH64_OPND_HALF:
6745 /* 16-bit unsigned immediate. */
6746 if (unsigned_overflow (value, 16))
6747 as_bad_where (fixP->fx_file, fixP->fx_line,
6748 _("immediate out of range"));
6749 insn = get_aarch64_insn (buf);
6750 insn |= encode_movw_imm (value & 0xffff);
6751 put_aarch64_insn (buf, insn);
6754 case AARCH64_OPND_IMM_MOV:
6755 /* Operand for a generic move immediate instruction, which is
6756 an alias instruction that generates a single MOVZ, MOVN or ORR
6757 instruction to loads a 32-bit/64-bit immediate value into general
6758 register. An assembler error shall result if the immediate cannot be
6759 created by a single one of these instructions. If there is a choice,
6760 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6761 and MOVZ or MOVN to ORR. */
6762 gas_assert (new_inst != NULL);
6763 fix_mov_imm_insn (fixP, buf, new_inst, value);
6766 case AARCH64_OPND_ADDR_SIMM7:
6767 case AARCH64_OPND_ADDR_SIMM9:
6768 case AARCH64_OPND_ADDR_SIMM9_2:
6769 case AARCH64_OPND_ADDR_UIMM12:
6770 /* Immediate offset in an address. */
6771 insn = get_aarch64_insn (buf);
6773 gas_assert (new_inst != NULL && new_inst->value == insn);
6774 gas_assert (new_inst->opcode->operands[1] == opnd
6775 || new_inst->opcode->operands[2] == opnd);
6777 /* Get the index of the address operand. */
6778 if (new_inst->opcode->operands[1] == opnd)
6779 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6782 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6785 /* Update the resolved offset value. */
6786 new_inst->operands[idx].addr.offset.imm = value;
6788 /* Encode/fix-up. */
6789 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6790 &new_inst->value, NULL, NULL))
6792 put_aarch64_insn (buf, new_inst->value);
6795 else if (new_inst->opcode->iclass == ldst_pos
6796 && try_to_encode_as_unscaled_ldst (new_inst))
6798 put_aarch64_insn (buf, new_inst->value);
6802 as_bad_where (fixP->fx_file, fixP->fx_line,
6803 _("immediate offset out of range"));
6808 as_fatal (_("unhandled operand code %d"), opnd);
6812 /* Apply a fixup (fixP) to segment data, once it has been determined
6813 by our caller that we have all the info we need to fix it up.
6815 Parameter valP is the pointer to the value of the bits. */
6818 md_apply_fix (fixS * fixP, valueT * valP, segT seg)
6820 offsetT value = *valP;
6822 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6824 unsigned flags = fixP->fx_addnumber;
6826 DEBUG_TRACE ("\n\n");
6827 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6828 DEBUG_TRACE ("Enter md_apply_fix");
6830 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
6832 /* Note whether this will delete the relocation. */
6834 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
6837 /* Process the relocations. */
6838 switch (fixP->fx_r_type)
6840 case BFD_RELOC_NONE:
6841 /* This will need to go in the object file. */
6846 case BFD_RELOC_8_PCREL:
6847 if (fixP->fx_done || !seg->use_rela_p)
6848 md_number_to_chars (buf, value, 1);
6852 case BFD_RELOC_16_PCREL:
6853 if (fixP->fx_done || !seg->use_rela_p)
6854 md_number_to_chars (buf, value, 2);
6858 case BFD_RELOC_32_PCREL:
6859 if (fixP->fx_done || !seg->use_rela_p)
6860 md_number_to_chars (buf, value, 4);
6864 case BFD_RELOC_64_PCREL:
6865 if (fixP->fx_done || !seg->use_rela_p)
6866 md_number_to_chars (buf, value, 8);
6869 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
6870 /* We claim that these fixups have been processed here, even if
6871 in fact we generate an error because we do not have a reloc
6872 for them, so tc_gen_reloc() will reject them. */
6874 if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy))
6876 as_bad_where (fixP->fx_file, fixP->fx_line,
6877 _("undefined symbol %s used as an immediate value"),
6878 S_GET_NAME (fixP->fx_addsy));
6879 goto apply_fix_return;
6881 fix_insn (fixP, flags, value);
6884 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
6885 if (fixP->fx_done || !seg->use_rela_p)
6888 as_bad_where (fixP->fx_file, fixP->fx_line,
6889 _("pc-relative load offset not word aligned"));
6890 if (signed_overflow (value, 21))
6891 as_bad_where (fixP->fx_file, fixP->fx_line,
6892 _("pc-relative load offset out of range"));
6893 insn = get_aarch64_insn (buf);
6894 insn |= encode_ld_lit_ofs_19 (value >> 2);
6895 put_aarch64_insn (buf, insn);
6899 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
6900 if (fixP->fx_done || !seg->use_rela_p)
6902 if (signed_overflow (value, 21))
6903 as_bad_where (fixP->fx_file, fixP->fx_line,
6904 _("pc-relative address offset out of range"));
6905 insn = get_aarch64_insn (buf);
6906 insn |= encode_adr_imm (value);
6907 put_aarch64_insn (buf, insn);
6911 case BFD_RELOC_AARCH64_BRANCH19:
6912 if (fixP->fx_done || !seg->use_rela_p)
6915 as_bad_where (fixP->fx_file, fixP->fx_line,
6916 _("conditional branch target not word aligned"));
6917 if (signed_overflow (value, 21))
6918 as_bad_where (fixP->fx_file, fixP->fx_line,
6919 _("conditional branch out of range"));
6920 insn = get_aarch64_insn (buf);
6921 insn |= encode_cond_branch_ofs_19 (value >> 2);
6922 put_aarch64_insn (buf, insn);
6926 case BFD_RELOC_AARCH64_TSTBR14:
6927 if (fixP->fx_done || !seg->use_rela_p)
6930 as_bad_where (fixP->fx_file, fixP->fx_line,
6931 _("conditional branch target not word aligned"));
6932 if (signed_overflow (value, 16))
6933 as_bad_where (fixP->fx_file, fixP->fx_line,
6934 _("conditional branch out of range"));
6935 insn = get_aarch64_insn (buf);
6936 insn |= encode_tst_branch_ofs_14 (value >> 2);
6937 put_aarch64_insn (buf, insn);
6941 case BFD_RELOC_AARCH64_CALL26:
6942 case BFD_RELOC_AARCH64_JUMP26:
6943 if (fixP->fx_done || !seg->use_rela_p)
6946 as_bad_where (fixP->fx_file, fixP->fx_line,
6947 _("branch target not word aligned"));
6948 if (signed_overflow (value, 28))
6949 as_bad_where (fixP->fx_file, fixP->fx_line,
6950 _("branch out of range"));
6951 insn = get_aarch64_insn (buf);
6952 insn |= encode_branch_ofs_26 (value >> 2);
6953 put_aarch64_insn (buf, insn);
6957 case BFD_RELOC_AARCH64_MOVW_G0:
6958 case BFD_RELOC_AARCH64_MOVW_G0_NC:
6959 case BFD_RELOC_AARCH64_MOVW_G0_S:
6960 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
6963 case BFD_RELOC_AARCH64_MOVW_G1:
6964 case BFD_RELOC_AARCH64_MOVW_G1_NC:
6965 case BFD_RELOC_AARCH64_MOVW_G1_S:
6966 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
6969 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
6971 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6972 /* Should always be exported to object file, see
6973 aarch64_force_relocation(). */
6974 gas_assert (!fixP->fx_done);
6975 gas_assert (seg->use_rela_p);
6977 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
6979 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6980 /* Should always be exported to object file, see
6981 aarch64_force_relocation(). */
6982 gas_assert (!fixP->fx_done);
6983 gas_assert (seg->use_rela_p);
6985 case BFD_RELOC_AARCH64_MOVW_G2:
6986 case BFD_RELOC_AARCH64_MOVW_G2_NC:
6987 case BFD_RELOC_AARCH64_MOVW_G2_S:
6990 case BFD_RELOC_AARCH64_MOVW_G3:
6993 if (fixP->fx_done || !seg->use_rela_p)
6995 insn = get_aarch64_insn (buf);
6999 /* REL signed addend must fit in 16 bits */
7000 if (signed_overflow (value, 16))
7001 as_bad_where (fixP->fx_file, fixP->fx_line,
7002 _("offset out of range"));
7006 /* Check for overflow and scale. */
7007 switch (fixP->fx_r_type)
7009 case BFD_RELOC_AARCH64_MOVW_G0:
7010 case BFD_RELOC_AARCH64_MOVW_G1:
7011 case BFD_RELOC_AARCH64_MOVW_G2:
7012 case BFD_RELOC_AARCH64_MOVW_G3:
7013 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
7014 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7015 if (unsigned_overflow (value, scale + 16))
7016 as_bad_where (fixP->fx_file, fixP->fx_line,
7017 _("unsigned value out of range"));
7019 case BFD_RELOC_AARCH64_MOVW_G0_S:
7020 case BFD_RELOC_AARCH64_MOVW_G1_S:
7021 case BFD_RELOC_AARCH64_MOVW_G2_S:
7022 /* NOTE: We can only come here with movz or movn. */
7023 if (signed_overflow (value, scale + 16))
7024 as_bad_where (fixP->fx_file, fixP->fx_line,
7025 _("signed value out of range"));
7028 /* Force use of MOVN. */
7030 insn = reencode_movzn_to_movn (insn);
7034 /* Force use of MOVZ. */
7035 insn = reencode_movzn_to_movz (insn);
7039 /* Unchecked relocations. */
7045 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7046 insn |= encode_movw_imm (value & 0xffff);
7048 put_aarch64_insn (buf, insn);
7052 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
7053 fixP->fx_r_type = (ilp32_p
7054 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7055 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);
7056 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7057 /* Should always be exported to object file, see
7058 aarch64_force_relocation(). */
7059 gas_assert (!fixP->fx_done);
7060 gas_assert (seg->use_rela_p);
7063 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
7064 fixP->fx_r_type = (ilp32_p
7065 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7066 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC);
7067 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7068 /* Should always be exported to object file, see
7069 aarch64_force_relocation(). */
7070 gas_assert (!fixP->fx_done);
7071 gas_assert (seg->use_rela_p);
7074 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
7075 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
7076 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
7077 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
7078 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
7079 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
7080 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
7081 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
7082 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
7083 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
7084 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
7085 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
7086 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
7087 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
7088 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
7089 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
7090 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
7091 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
7092 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
7093 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
7094 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
7095 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
7096 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
7097 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
7098 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
7099 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
7100 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
7101 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
7102 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
7103 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
7104 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
7105 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
7106 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
7107 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
7108 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
7109 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
7110 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
7111 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
7112 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
7113 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
7114 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
7115 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
7116 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
7117 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
7118 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7119 /* Should always be exported to object file, see
7120 aarch64_force_relocation(). */
7121 gas_assert (!fixP->fx_done);
7122 gas_assert (seg->use_rela_p);
7125 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
7126 /* Should always be exported to object file, see
7127 aarch64_force_relocation(). */
7128 fixP->fx_r_type = (ilp32_p
7129 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7130 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC);
7131 gas_assert (!fixP->fx_done);
7132 gas_assert (seg->use_rela_p);
7135 case BFD_RELOC_AARCH64_ADD_LO12:
7136 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
7137 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
7138 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
7139 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
7140 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
7141 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
7142 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
7143 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
7144 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
7145 case BFD_RELOC_AARCH64_LDST128_LO12:
7146 case BFD_RELOC_AARCH64_LDST16_LO12:
7147 case BFD_RELOC_AARCH64_LDST32_LO12:
7148 case BFD_RELOC_AARCH64_LDST64_LO12:
7149 case BFD_RELOC_AARCH64_LDST8_LO12:
7150 /* Should always be exported to object file, see
7151 aarch64_force_relocation(). */
7152 gas_assert (!fixP->fx_done);
7153 gas_assert (seg->use_rela_p);
7156 case BFD_RELOC_AARCH64_TLSDESC_ADD:
7157 case BFD_RELOC_AARCH64_TLSDESC_CALL:
7158 case BFD_RELOC_AARCH64_TLSDESC_LDR:
7161 case BFD_RELOC_UNUSED:
7162 /* An error will already have been reported. */
7166 as_bad_where (fixP->fx_file, fixP->fx_line,
7167 _("unexpected %s fixup"),
7168 bfd_get_reloc_code_name (fixP->fx_r_type));
7173 /* Free the allocated the struct aarch64_inst.
7174 N.B. currently there are very limited number of fix-up types actually use
7175 this field, so the impact on the performance should be minimal . */
7176 if (fixP->tc_fix_data.inst != NULL)
7177 free (fixP->tc_fix_data.inst);
7182 /* Translate internal representation of relocation info to BFD target
7186 tc_gen_reloc (asection * section, fixS * fixp)
7189 bfd_reloc_code_real_type code;
7191 reloc = XNEW (arelent);
7193 reloc->sym_ptr_ptr = XNEW (asymbol *);
7194 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7195 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
7199 if (section->use_rela_p)
7200 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
7202 fixp->fx_offset = reloc->address;
7204 reloc->addend = fixp->fx_offset;
7206 code = fixp->fx_r_type;
7211 code = BFD_RELOC_16_PCREL;
7216 code = BFD_RELOC_32_PCREL;
7221 code = BFD_RELOC_64_PCREL;
7228 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
7229 if (reloc->howto == NULL)
7231 as_bad_where (fixp->fx_file, fixp->fx_line,
7233 ("cannot represent %s relocation in this object file format"),
7234 bfd_get_reloc_code_name (code));
7241 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7244 cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp)
7246 bfd_reloc_code_real_type type;
7250 FIXME: @@ Should look at CPU word size. */
7257 type = BFD_RELOC_16;
7260 type = BFD_RELOC_32;
7263 type = BFD_RELOC_64;
7266 as_bad (_("cannot do %u-byte relocation"), size);
7267 type = BFD_RELOC_UNUSED;
7271 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
7275 aarch64_force_relocation (struct fix *fixp)
7277 switch (fixp->fx_r_type)
7279 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
7280 /* Perform these "immediate" internal relocations
7281 even if the symbol is extern or weak. */
7284 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
7285 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
7286 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
7287 /* Pseudo relocs that need to be fixed up according to
7291 case BFD_RELOC_AARCH64_ADD_LO12:
7292 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
7293 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
7294 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
7295 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
7296 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
7297 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
7298 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
7299 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
7300 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
7301 case BFD_RELOC_AARCH64_LDST128_LO12:
7302 case BFD_RELOC_AARCH64_LDST16_LO12:
7303 case BFD_RELOC_AARCH64_LDST32_LO12:
7304 case BFD_RELOC_AARCH64_LDST64_LO12:
7305 case BFD_RELOC_AARCH64_LDST8_LO12:
7306 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
7307 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
7308 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
7309 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
7310 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
7311 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
7312 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
7313 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7314 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
7315 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
7316 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
7317 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
7318 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
7319 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
7320 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
7321 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
7322 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
7323 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
7324 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
7325 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
7326 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
7327 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
7328 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
7329 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
7330 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
7331 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
7332 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
7333 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
7334 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
7335 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
7336 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
7337 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
7338 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
7339 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
7340 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
7341 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
7342 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
7343 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
7344 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
7345 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
7346 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
7347 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
7348 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
7349 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
7350 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
7351 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
7352 /* Always leave these relocations for the linker. */
7359 return generic_force_reloc (fixp);
7365 elf64_aarch64_target_format (void)
7367 if (strcmp (TARGET_OS, "cloudabi") == 0)
7369 /* FIXME: What to do for ilp32_p ? */
7370 return target_big_endian ? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7372 if (target_big_endian)
7373 return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
7375 return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";
7379 aarch64elf_frob_symbol (symbolS * symp, int *puntp)
7381 elf_frob_symbol (symp, puntp);
7385 /* MD interface: Finalization. */
7387 /* A good place to do this, although this was probably not intended
7388 for this kind of use. We need to dump the literal pool before
7389 references are made to a null symbol pointer. */
7392 aarch64_cleanup (void)
7396 for (pool = list_of_pools; pool; pool = pool->next)
7398 /* Put it at the end of the relevant section. */
7399 subseg_set (pool->section, pool->sub_section);
7405 /* Remove any excess mapping symbols generated for alignment frags in
7406 SEC. We may have created a mapping symbol before a zero byte
7407 alignment; remove it if there's a mapping symbol after the
7410 check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec,
7411 void *dummy ATTRIBUTE_UNUSED)
7413 segment_info_type *seginfo = seg_info (sec);
7416 if (seginfo == NULL || seginfo->frchainP == NULL)
7419 for (fragp = seginfo->frchainP->frch_root;
7420 fragp != NULL; fragp = fragp->fr_next)
7422 symbolS *sym = fragp->tc_frag_data.last_map;
7423 fragS *next = fragp->fr_next;
7425 /* Variable-sized frags have been converted to fixed size by
7426 this point. But if this was variable-sized to start with,
7427 there will be a fixed-size frag after it. So don't handle
7429 if (sym == NULL || next == NULL)
7432 if (S_GET_VALUE (sym) < next->fr_address)
7433 /* Not at the end of this frag. */
7435 know (S_GET_VALUE (sym) == next->fr_address);
7439 if (next->tc_frag_data.first_map != NULL)
7441 /* Next frag starts with a mapping symbol. Discard this
7443 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
7447 if (next->fr_next == NULL)
7449 /* This mapping symbol is at the end of the section. Discard
7451 know (next->fr_fix == 0 && next->fr_var == 0);
7452 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
7456 /* As long as we have empty frags without any mapping symbols,
7458 /* If the next frag is non-empty and does not start with a
7459 mapping symbol, then this mapping symbol is required. */
7460 if (next->fr_address != next->fr_next->fr_address)
7463 next = next->fr_next;
7465 while (next != NULL);
7470 /* Adjust the symbol table. */
7473 aarch64_adjust_symtab (void)
7476 /* Remove any overlapping mapping symbols generated by alignment frags. */
7477 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
7478 /* Now do generic ELF adjustments. */
7479 elf_adjust_symtab ();
7484 checked_hash_insert (struct hash_control *table, const char *key, void *value)
7486 const char *hash_err;
7488 hash_err = hash_insert (table, key, value);
7490 printf ("Internal Error: Can't hash %s\n", key);
7494 fill_instruction_hash_table (void)
7496 aarch64_opcode *opcode = aarch64_opcode_table;
7498 while (opcode->name != NULL)
7500 templates *templ, *new_templ;
7501 templ = hash_find (aarch64_ops_hsh, opcode->name);
7503 new_templ = XNEW (templates);
7504 new_templ->opcode = opcode;
7505 new_templ->next = NULL;
7508 checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ);
7511 new_templ->next = templ->next;
7512 templ->next = new_templ;
7519 convert_to_upper (char *dst, const char *src, size_t num)
7522 for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src)
7523 *dst = TOUPPER (*src);
7527 /* Assume STR point to a lower-case string, allocate, convert and return
7528 the corresponding upper-case string. */
7529 static inline const char*
7530 get_upper_str (const char *str)
7533 size_t len = strlen (str);
7534 ret = XNEWVEC (char, len + 1);
7535 convert_to_upper (ret, str, len);
7539 /* MD interface: Initialization. */
7547 if ((aarch64_ops_hsh = hash_new ()) == NULL
7548 || (aarch64_cond_hsh = hash_new ()) == NULL
7549 || (aarch64_shift_hsh = hash_new ()) == NULL
7550 || (aarch64_sys_regs_hsh = hash_new ()) == NULL
7551 || (aarch64_pstatefield_hsh = hash_new ()) == NULL
7552 || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
7553 || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
7554 || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
7555 || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
7556 || (aarch64_reg_hsh = hash_new ()) == NULL
7557 || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
7558 || (aarch64_nzcv_hsh = hash_new ()) == NULL
7559 || (aarch64_pldop_hsh = hash_new ()) == NULL
7560 || (aarch64_hint_opt_hsh = hash_new ()) == NULL)
7561 as_fatal (_("virtual memory exhausted"));
7563 fill_instruction_hash_table ();
7565 for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
7566 checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
7567 (void *) (aarch64_sys_regs + i));
7569 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
7570 checked_hash_insert (aarch64_pstatefield_hsh,
7571 aarch64_pstatefields[i].name,
7572 (void *) (aarch64_pstatefields + i));
7574 for (i = 0; aarch64_sys_regs_ic[i].name != NULL; i++)
7575 checked_hash_insert (aarch64_sys_regs_ic_hsh,
7576 aarch64_sys_regs_ic[i].name,
7577 (void *) (aarch64_sys_regs_ic + i));
7579 for (i = 0; aarch64_sys_regs_dc[i].name != NULL; i++)
7580 checked_hash_insert (aarch64_sys_regs_dc_hsh,
7581 aarch64_sys_regs_dc[i].name,
7582 (void *) (aarch64_sys_regs_dc + i));
7584 for (i = 0; aarch64_sys_regs_at[i].name != NULL; i++)
7585 checked_hash_insert (aarch64_sys_regs_at_hsh,
7586 aarch64_sys_regs_at[i].name,
7587 (void *) (aarch64_sys_regs_at + i));
7589 for (i = 0; aarch64_sys_regs_tlbi[i].name != NULL; i++)
7590 checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
7591 aarch64_sys_regs_tlbi[i].name,
7592 (void *) (aarch64_sys_regs_tlbi + i));
7594 for (i = 0; i < ARRAY_SIZE (reg_names); i++)
7595 checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
7596 (void *) (reg_names + i));
7598 for (i = 0; i < ARRAY_SIZE (nzcv_names); i++)
7599 checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template,
7600 (void *) (nzcv_names + i));
7602 for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++)
7604 const char *name = aarch64_operand_modifiers[i].name;
7605 checked_hash_insert (aarch64_shift_hsh, name,
7606 (void *) (aarch64_operand_modifiers + i));
7607 /* Also hash the name in the upper case. */
7608 checked_hash_insert (aarch64_shift_hsh, get_upper_str (name),
7609 (void *) (aarch64_operand_modifiers + i));
7612 for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++)
7615 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7616 the same condition code. */
7617 for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j)
7619 const char *name = aarch64_conds[i].names[j];
7622 checked_hash_insert (aarch64_cond_hsh, name,
7623 (void *) (aarch64_conds + i));
7624 /* Also hash the name in the upper case. */
7625 checked_hash_insert (aarch64_cond_hsh, get_upper_str (name),
7626 (void *) (aarch64_conds + i));
7630 for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++)
7632 const char *name = aarch64_barrier_options[i].name;
7633 /* Skip xx00 - the unallocated values of option. */
7636 checked_hash_insert (aarch64_barrier_opt_hsh, name,
7637 (void *) (aarch64_barrier_options + i));
7638 /* Also hash the name in the upper case. */
7639 checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
7640 (void *) (aarch64_barrier_options + i));
7643 for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
7645 const char* name = aarch64_prfops[i].name;
7646 /* Skip the unallocated hint encodings. */
7649 checked_hash_insert (aarch64_pldop_hsh, name,
7650 (void *) (aarch64_prfops + i));
7651 /* Also hash the name in the upper case. */
7652 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
7653 (void *) (aarch64_prfops + i));
7656 for (i = 0; aarch64_hint_options[i].name != NULL; i++)
7658 const char* name = aarch64_hint_options[i].name;
7660 checked_hash_insert (aarch64_hint_opt_hsh, name,
7661 (void *) (aarch64_hint_options + i));
7662 /* Also hash the name in the upper case. */
7663 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
7664 (void *) (aarch64_hint_options + i));
7667 /* Set the cpu variant based on the command-line options. */
7669 mcpu_cpu_opt = march_cpu_opt;
7672 mcpu_cpu_opt = &cpu_default;
7674 cpu_variant = *mcpu_cpu_opt;
7676 /* Record the CPU type. */
7677 mach = ilp32_p ? bfd_mach_aarch64_ilp32 : bfd_mach_aarch64;
7679 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
7682 /* Command line processing. */
7684 const char *md_shortopts = "m:";
7686 #ifdef AARCH64_BI_ENDIAN
7687 #define OPTION_EB (OPTION_MD_BASE + 0)
7688 #define OPTION_EL (OPTION_MD_BASE + 1)
7690 #if TARGET_BYTES_BIG_ENDIAN
7691 #define OPTION_EB (OPTION_MD_BASE + 0)
7693 #define OPTION_EL (OPTION_MD_BASE + 1)
7697 struct option md_longopts[] = {
7699 {"EB", no_argument, NULL, OPTION_EB},
7702 {"EL", no_argument, NULL, OPTION_EL},
7704 {NULL, no_argument, NULL, 0}
7707 size_t md_longopts_size = sizeof (md_longopts);
7709 struct aarch64_option_table
7711 const char *option; /* Option name to match. */
7712 const char *help; /* Help information. */
7713 int *var; /* Variable to change. */
7714 int value; /* What to change it to. */
7715 char *deprecated; /* If non-null, print this message. */
7718 static struct aarch64_option_table aarch64_opts[] = {
7719 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
7720 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
7722 #ifdef DEBUG_AARCH64
7723 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL},
7724 #endif /* DEBUG_AARCH64 */
7725 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1,
7727 {"mno-verbose-error", N_("do not output verbose error messages"),
7728 &verbose_error_p, 0, NULL},
7729 {NULL, NULL, NULL, 0, NULL}
7732 struct aarch64_cpu_option_table
7735 const aarch64_feature_set value;
7736 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7738 const char *canonical_name;
7741 /* This list should, at a minimum, contain all the cpu names
7742 recognized by GCC. */
7743 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
7744 {"all", AARCH64_ANY, NULL},
7745 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
7746 AARCH64_FEATURE_CRC), "Cortex-A35"},
7747 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,
7748 AARCH64_FEATURE_CRC), "Cortex-A53"},
7749 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8,
7750 AARCH64_FEATURE_CRC), "Cortex-A57"},
7751 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8,
7752 AARCH64_FEATURE_CRC), "Cortex-A72"},
7753 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8,
7754 AARCH64_FEATURE_CRC), "Cortex-A73"},
7755 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
7756 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
7757 "Samsung Exynos M1"},
7758 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8,
7759 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
7760 "Qualcomm QDF24XX"},
7761 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8,
7762 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
7764 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1,
7765 AARCH64_FEATURE_CRYPTO),
7767 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7768 in earlier releases and is superseded by 'xgene1' in all
7770 {"xgene-1", AARCH64_ARCH_V8, "APM X-Gene 1"},
7771 {"xgene1", AARCH64_ARCH_V8, "APM X-Gene 1"},
7772 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8,
7773 AARCH64_FEATURE_CRC), "APM X-Gene 2"},
7774 {"generic", AARCH64_ARCH_V8, NULL},
7776 {NULL, AARCH64_ARCH_NONE, NULL}
7779 struct aarch64_arch_option_table
7782 const aarch64_feature_set value;
7785 /* This list should, at a minimum, contain all the architecture names
7786 recognized by GCC. */
7787 static const struct aarch64_arch_option_table aarch64_archs[] = {
7788 {"all", AARCH64_ANY},
7789 {"armv8-a", AARCH64_ARCH_V8},
7790 {"armv8.1-a", AARCH64_ARCH_V8_1},
7791 {"armv8.2-a", AARCH64_ARCH_V8_2},
7792 {NULL, AARCH64_ARCH_NONE}
7795 /* ISA extensions. */
7796 struct aarch64_option_cpu_value_table
7799 const aarch64_feature_set value;
7800 const aarch64_feature_set require; /* Feature dependencies. */
7803 static const struct aarch64_option_cpu_value_table aarch64_features[] = {
7804 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0),
7806 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0),
7808 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0),
7810 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0),
7812 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0),
7814 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0),
7816 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0),
7818 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0),
7820 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0),
7821 AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
7822 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16, 0),
7823 AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
7824 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
7826 {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
7829 struct aarch64_long_option_table
7831 const char *option; /* Substring to match. */
7832 const char *help; /* Help information. */
7833 int (*func) (const char *subopt); /* Function to decode sub-option. */
7834 char *deprecated; /* If non-null, print this message. */
7837 /* Transitive closure of features depending on set. */
7838 static aarch64_feature_set
7839 aarch64_feature_disable_set (aarch64_feature_set set)
7841 const struct aarch64_option_cpu_value_table *opt;
7842 aarch64_feature_set prev = 0;
7844 while (prev != set) {
7846 for (opt = aarch64_features; opt->name != NULL; opt++)
7847 if (AARCH64_CPU_HAS_ANY_FEATURES (opt->require, set))
7848 AARCH64_MERGE_FEATURE_SETS (set, set, opt->value);
7853 /* Transitive closure of dependencies of set. */
7854 static aarch64_feature_set
7855 aarch64_feature_enable_set (aarch64_feature_set set)
7857 const struct aarch64_option_cpu_value_table *opt;
7858 aarch64_feature_set prev = 0;
7860 while (prev != set) {
7862 for (opt = aarch64_features; opt->name != NULL; opt++)
7863 if (AARCH64_CPU_HAS_FEATURE (set, opt->value))
7864 AARCH64_MERGE_FEATURE_SETS (set, set, opt->require);
7870 aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p,
7871 bfd_boolean ext_only)
7873 /* We insist on extensions being added before being removed. We achieve
7874 this by using the ADDING_VALUE variable to indicate whether we are
7875 adding an extension (1) or removing it (0) and only allowing it to
7876 change in the order -1 -> 1 -> 0. */
7877 int adding_value = -1;
7878 aarch64_feature_set *ext_set = XNEW (aarch64_feature_set);
7880 /* Copy the feature set, so that we can modify it. */
7884 while (str != NULL && *str != 0)
7886 const struct aarch64_option_cpu_value_table *opt;
7887 const char *ext = NULL;
7894 as_bad (_("invalid architectural extension"));
7898 ext = strchr (++str, '+');
7904 optlen = strlen (str);
7906 if (optlen >= 2 && strncmp (str, "no", 2) == 0)
7908 if (adding_value != 0)
7913 else if (optlen > 0)
7915 if (adding_value == -1)
7917 else if (adding_value != 1)
7919 as_bad (_("must specify extensions to add before specifying "
7920 "those to remove"));
7927 as_bad (_("missing architectural extension"));
7931 gas_assert (adding_value != -1);
7933 for (opt = aarch64_features; opt->name != NULL; opt++)
7934 if (strncmp (opt->name, str, optlen) == 0)
7936 aarch64_feature_set set;
7938 /* Add or remove the extension. */
7941 set = aarch64_feature_enable_set (opt->value);
7942 AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, set);
7946 set = aarch64_feature_disable_set (opt->value);
7947 AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, set);
7952 if (opt->name == NULL)
7954 as_bad (_("unknown architectural extension `%s'"), str);
7965 aarch64_parse_cpu (const char *str)
7967 const struct aarch64_cpu_option_table *opt;
7968 const char *ext = strchr (str, '+');
7974 optlen = strlen (str);
7978 as_bad (_("missing cpu name `%s'"), str);
7982 for (opt = aarch64_cpus; opt->name != NULL; opt++)
7983 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7985 mcpu_cpu_opt = &opt->value;
7987 return aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE);
7992 as_bad (_("unknown cpu `%s'"), str);
7997 aarch64_parse_arch (const char *str)
7999 const struct aarch64_arch_option_table *opt;
8000 const char *ext = strchr (str, '+');
8006 optlen = strlen (str);
8010 as_bad (_("missing architecture name `%s'"), str);
8014 for (opt = aarch64_archs; opt->name != NULL; opt++)
8015 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
8017 march_cpu_opt = &opt->value;
8019 return aarch64_parse_features (ext, &march_cpu_opt, FALSE);
8024 as_bad (_("unknown architecture `%s'\n"), str);
8029 struct aarch64_option_abi_value_table
8032 enum aarch64_abi_type value;
8035 static const struct aarch64_option_abi_value_table aarch64_abis[] = {
8036 {"ilp32", AARCH64_ABI_ILP32},
8037 {"lp64", AARCH64_ABI_LP64},
8041 aarch64_parse_abi (const char *str)
8047 as_bad (_("missing abi name `%s'"), str);
8051 for (i = 0; i < ARRAY_SIZE (aarch64_abis); i++)
8052 if (strcmp (str, aarch64_abis[i].name) == 0)
8054 aarch64_abi = aarch64_abis[i].value;
8058 as_bad (_("unknown abi `%s'\n"), str);
8062 static struct aarch64_long_option_table aarch64_long_opts[] = {
8064 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8065 aarch64_parse_abi, NULL},
8066 #endif /* OBJ_ELF */
8067 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8068 aarch64_parse_cpu, NULL},
8069 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8070 aarch64_parse_arch, NULL},
8071 {NULL, NULL, 0, NULL}
8075 md_parse_option (int c, const char *arg)
8077 struct aarch64_option_table *opt;
8078 struct aarch64_long_option_table *lopt;
8084 target_big_endian = 1;
8090 target_big_endian = 0;
8095 /* Listing option. Just ignore these, we don't support additional
8100 for (opt = aarch64_opts; opt->option != NULL; opt++)
8102 if (c == opt->option[0]
8103 && ((arg == NULL && opt->option[1] == 0)
8104 || streq (arg, opt->option + 1)))
8106 /* If the option is deprecated, tell the user. */
8107 if (opt->deprecated != NULL)
8108 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
8109 arg ? arg : "", _(opt->deprecated));
8111 if (opt->var != NULL)
8112 *opt->var = opt->value;
8118 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
8120 /* These options are expected to have an argument. */
8121 if (c == lopt->option[0]
8123 && strncmp (arg, lopt->option + 1,
8124 strlen (lopt->option + 1)) == 0)
8126 /* If the option is deprecated, tell the user. */
8127 if (lopt->deprecated != NULL)
8128 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
8129 _(lopt->deprecated));
8131 /* Call the sup-option parser. */
8132 return lopt->func (arg + strlen (lopt->option) - 1);
8143 md_show_usage (FILE * fp)
8145 struct aarch64_option_table *opt;
8146 struct aarch64_long_option_table *lopt;
8148 fprintf (fp, _(" AArch64-specific assembler options:\n"));
8150 for (opt = aarch64_opts; opt->option != NULL; opt++)
8151 if (opt->help != NULL)
8152 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
8154 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
8155 if (lopt->help != NULL)
8156 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
8160 -EB assemble code for a big-endian cpu\n"));
8165 -EL assemble code for a little-endian cpu\n"));
8169 /* Parse a .cpu directive. */
8172 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
8174 const struct aarch64_cpu_option_table *opt;
8180 name = input_line_pointer;
8181 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8182 input_line_pointer++;
8183 saved_char = *input_line_pointer;
8184 *input_line_pointer = 0;
8186 ext = strchr (name, '+');
8189 optlen = ext - name;
8191 optlen = strlen (name);
8193 /* Skip the first "all" entry. */
8194 for (opt = aarch64_cpus + 1; opt->name != NULL; opt++)
8195 if (strlen (opt->name) == optlen
8196 && strncmp (name, opt->name, optlen) == 0)
8198 mcpu_cpu_opt = &opt->value;
8200 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
8203 cpu_variant = *mcpu_cpu_opt;
8205 *input_line_pointer = saved_char;
8206 demand_empty_rest_of_line ();
8209 as_bad (_("unknown cpu `%s'"), name);
8210 *input_line_pointer = saved_char;
8211 ignore_rest_of_line ();
8215 /* Parse a .arch directive. */
8218 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
8220 const struct aarch64_arch_option_table *opt;
8226 name = input_line_pointer;
8227 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8228 input_line_pointer++;
8229 saved_char = *input_line_pointer;
8230 *input_line_pointer = 0;
8232 ext = strchr (name, '+');
8235 optlen = ext - name;
8237 optlen = strlen (name);
8239 /* Skip the first "all" entry. */
8240 for (opt = aarch64_archs + 1; opt->name != NULL; opt++)
8241 if (strlen (opt->name) == optlen
8242 && strncmp (name, opt->name, optlen) == 0)
8244 mcpu_cpu_opt = &opt->value;
8246 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
8249 cpu_variant = *mcpu_cpu_opt;
8251 *input_line_pointer = saved_char;
8252 demand_empty_rest_of_line ();
8256 as_bad (_("unknown architecture `%s'\n"), name);
8257 *input_line_pointer = saved_char;
8258 ignore_rest_of_line ();
8261 /* Parse a .arch_extension directive. */
8264 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED)
8267 char *ext = input_line_pointer;;
8269 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
8270 input_line_pointer++;
8271 saved_char = *input_line_pointer;
8272 *input_line_pointer = 0;
8274 if (!aarch64_parse_features (ext, &mcpu_cpu_opt, TRUE))
8277 cpu_variant = *mcpu_cpu_opt;
8279 *input_line_pointer = saved_char;
8280 demand_empty_rest_of_line ();
8283 /* Copy symbol information. */
8286 aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
8288 AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);