1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the license, or
12 (at your option) any later version.
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "bfd_stdint.h"
28 #include "safe-ctype.h"
33 #include "elf/aarch64.h"
34 #include "dw2gencfi.h"
37 #include "dwarf2dbg.h"
39 /* Types of processor to assemble for. */
41 #define CPU_DEFAULT AARCH64_ARCH_V8
44 #define streq(a, b) (strcmp (a, b) == 0)
46 static aarch64_feature_set cpu_variant;
48 /* Variables that we set while parsing command-line options. Once all
49 options have been read we re-process these values to set the real
51 static const aarch64_feature_set *mcpu_cpu_opt = NULL;
52 static const aarch64_feature_set *march_cpu_opt = NULL;
54 /* Constants for known architecture features. */
55 static const aarch64_feature_set cpu_default = CPU_DEFAULT;
57 static const aarch64_feature_set aarch64_arch_any = AARCH64_ANY;
58 static const aarch64_feature_set aarch64_arch_none = AARCH64_ARCH_NONE;
61 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
62 static symbolS *GOT_symbol;
64 /* Which ABI to use. */
71 /* AArch64 ABI for the output file. */
72 static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_LP64;
74 /* When non-zero, program to a 32-bit model, in which the C data types
75 int, long and all pointer types are 32-bit objects (ILP32); or to a
76 64-bit model, in which the C int type is 32-bits but the C long type
77 and all pointer types are 64-bit objects (LP64). */
78 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
91 /* Bits for DEFINED field in neon_type_el. */
93 #define NTA_HASINDEX 2
97 enum neon_el_type type;
98 unsigned char defined;
103 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
107 bfd_reloc_code_real_type type;
110 enum aarch64_opnd opnd;
112 unsigned need_libopcodes_p : 1;
115 struct aarch64_instruction
117 /* libopcodes structure for instruction intermediate representation. */
119 /* Record assembly errors found during the parsing. */
122 enum aarch64_operand_error_kind kind;
125 /* The condition that appears in the assembly line. */
127 /* Relocation information (including the GAS internal fixup). */
129 /* Need to generate an immediate in the literal pool. */
130 unsigned gen_lit_pool : 1;
133 typedef struct aarch64_instruction aarch64_instruction;
135 static aarch64_instruction inst;
137 static bfd_boolean parse_operands (char *, const aarch64_opcode *);
138 static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
140 /* Diagnostics inline function utilites.
142 These are lightweight utlities which should only be called by parse_operands
143 and other parsers. GAS processes each assembly line by parsing it against
144 instruction template(s), in the case of multiple templates (for the same
145 mnemonic name), those templates are tried one by one until one succeeds or
146 all fail. An assembly line may fail a few templates before being
147 successfully parsed; an error saved here in most cases is not a user error
148 but an error indicating the current template is not the right template.
149 Therefore it is very important that errors can be saved at a low cost during
150 the parsing; we don't want to slow down the whole parsing by recording
151 non-user errors in detail.
153 Remember that the objective is to help GAS pick up the most approapriate
154 error message in the case of multiple templates, e.g. FMOV which has 8
160 inst.parsing_error.kind = AARCH64_OPDE_NIL;
161 inst.parsing_error.error = NULL;
164 static inline bfd_boolean
167 return inst.parsing_error.kind != AARCH64_OPDE_NIL;
170 static inline const char *
171 get_error_message (void)
173 return inst.parsing_error.error;
177 set_error_message (const char *error)
179 inst.parsing_error.error = error;
182 static inline enum aarch64_operand_error_kind
183 get_error_kind (void)
185 return inst.parsing_error.kind;
189 set_error_kind (enum aarch64_operand_error_kind kind)
191 inst.parsing_error.kind = kind;
195 set_error (enum aarch64_operand_error_kind kind, const char *error)
197 inst.parsing_error.kind = kind;
198 inst.parsing_error.error = error;
202 set_recoverable_error (const char *error)
204 set_error (AARCH64_OPDE_RECOVERABLE, error);
207 /* Use the DESC field of the corresponding aarch64_operand entry to compose
208 the error message. */
210 set_default_error (void)
212 set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
216 set_syntax_error (const char *error)
218 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
222 set_first_syntax_error (const char *error)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
229 set_fatal_syntax_error (const char *error)
231 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
235 set_other_error (const char *error)
237 set_error (AARCH64_OPDE_OTHER_ERROR, error);
240 /* Number of littlenums required to hold an extended precision number. */
241 #define MAX_LITTLENUMS 6
243 /* Return value for certain parsers when the parsing fails; those parsers
244 return the information of the parsed result, e.g. register number, on
246 #define PARSE_FAIL -1
248 /* This is an invalid condition code that means no conditional field is
250 #define COND_ALWAYS 0x10
254 const char *template;
260 const char *template;
267 bfd_reloc_code_real_type reloc;
270 /* Structure for a hash table entry for a register. */
274 unsigned char number;
276 unsigned char builtin;
279 /* Macros to define the register types and masks for the purpose
282 #undef AARCH64_REG_TYPES
283 #define AARCH64_REG_TYPES \
284 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
285 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
286 BASIC_REG_TYPE(SP_32) /* wsp */ \
287 BASIC_REG_TYPE(SP_64) /* sp */ \
288 BASIC_REG_TYPE(Z_32) /* wzr */ \
289 BASIC_REG_TYPE(Z_64) /* xzr */ \
290 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
291 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
292 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
293 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
294 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
295 BASIC_REG_TYPE(CN) /* c[0-7] */ \
296 BASIC_REG_TYPE(VN) /* v[0-31] */ \
297 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
298 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
299 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
300 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
301 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
302 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
303 /* Typecheck: any [BHSDQ]P FP. */ \
304 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
305 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
306 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
307 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
308 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
309 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
310 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
311 /* Any integer register; used for error messages only. */ \
312 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
313 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
314 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
315 /* Pseudo type to mark the end of the enumerator sequence. */ \
318 #undef BASIC_REG_TYPE
319 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
320 #undef MULTI_REG_TYPE
321 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
323 /* Register type enumerators. */
326 /* A list of REG_TYPE_*. */
330 #undef BASIC_REG_TYPE
331 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
333 #define REG_TYPE(T) (1 << REG_TYPE_##T)
334 #undef MULTI_REG_TYPE
335 #define MULTI_REG_TYPE(T,V) V,
337 /* Values indexed by aarch64_reg_type to assist the type checking. */
338 static const unsigned reg_type_masks[] =
343 #undef BASIC_REG_TYPE
345 #undef MULTI_REG_TYPE
346 #undef AARCH64_REG_TYPES
348 /* Diagnostics used when we don't get a register of the expected type.
349 Note: this has to synchronized with aarch64_reg_type definitions
352 get_reg_expected_msg (aarch64_reg_type reg_type)
359 msg = N_("integer 32-bit register expected");
362 msg = N_("integer 64-bit register expected");
365 msg = N_("integer register expected");
367 case REG_TYPE_R_Z_SP:
368 msg = N_("integer, zero or SP register expected");
371 msg = N_("8-bit SIMD scalar register expected");
374 msg = N_("16-bit SIMD scalar or floating-point half precision "
375 "register expected");
378 msg = N_("32-bit SIMD scalar or floating-point single precision "
379 "register expected");
382 msg = N_("64-bit SIMD scalar or floating-point double precision "
383 "register expected");
386 msg = N_("128-bit SIMD scalar or floating-point quad precision "
387 "register expected");
390 msg = N_("C0 - C15 expected");
392 case REG_TYPE_R_Z_BHSDQ_V:
393 msg = N_("register expected");
395 case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
396 msg = N_("SIMD scalar or floating-point register expected");
398 case REG_TYPE_VN: /* any V reg */
399 msg = N_("vector register expected");
402 as_fatal (_("invalid register type %d"), reg_type);
407 /* Some well known registers that we refer to directly elsewhere. */
410 /* Instructions take 4 bytes in the object file. */
413 /* Define some common error messages. */
414 #define BAD_SP _("SP not allowed here")
416 static struct hash_control *aarch64_ops_hsh;
417 static struct hash_control *aarch64_cond_hsh;
418 static struct hash_control *aarch64_shift_hsh;
419 static struct hash_control *aarch64_sys_regs_hsh;
420 static struct hash_control *aarch64_pstatefield_hsh;
421 static struct hash_control *aarch64_sys_regs_ic_hsh;
422 static struct hash_control *aarch64_sys_regs_dc_hsh;
423 static struct hash_control *aarch64_sys_regs_at_hsh;
424 static struct hash_control *aarch64_sys_regs_tlbi_hsh;
425 static struct hash_control *aarch64_reg_hsh;
426 static struct hash_control *aarch64_barrier_opt_hsh;
427 static struct hash_control *aarch64_nzcv_hsh;
428 static struct hash_control *aarch64_pldop_hsh;
430 /* Stuff needed to resolve the label ambiguity
439 static symbolS *last_label_seen;
441 /* Literal pool structure. Held on a per-section
442 and per-sub-section basis. */
444 #define MAX_LITERAL_POOL_SIZE 1024
445 typedef struct literal_pool
447 expressionS literals[MAX_LITERAL_POOL_SIZE];
448 unsigned int next_free_entry;
454 struct literal_pool *next;
457 /* Pointer to a linked list of literal pools. */
458 static literal_pool *list_of_pools = NULL;
462 /* This array holds the chars that always start a comment. If the
463 pre-processor is disabled, these aren't very useful. */
464 const char comment_chars[] = "";
466 /* This array holds the chars that only start a comment at the beginning of
467 a line. If the line seems to have the form '# 123 filename'
468 .line and .file directives will appear in the pre-processed output. */
469 /* Note that input_file.c hand checks for '#' at the beginning of the
470 first line of the input file. This is because the compiler outputs
471 #NO_APP at the beginning of its output. */
472 /* Also note that comments like this one will always work. */
473 const char line_comment_chars[] = "#";
475 const char line_separator_chars[] = ";";
477 /* Chars that can be used to separate mant
478 from exp in floating point numbers. */
479 const char EXP_CHARS[] = "eE";
481 /* Chars that mean this number is a floating point constant. */
485 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
487 /* Prefix character that indicates the start of an immediate value. */
488 #define is_immediate_prefix(C) ((C) == '#')
490 /* Separator character handling. */
492 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
494 static inline bfd_boolean
495 skip_past_char (char **str, char c)
506 #define skip_past_comma(str) skip_past_char (str, ',')
508 /* Arithmetic expressions (possibly involving symbols). */
510 static bfd_boolean in_my_get_expression_p = FALSE;
512 /* Third argument to my_get_expression. */
513 #define GE_NO_PREFIX 0
514 #define GE_OPT_PREFIX 1
516 /* Return TRUE if the string pointed by *STR is successfully parsed
517 as an valid expression; *EP will be filled with the information of
518 such an expression. Otherwise return FALSE. */
521 my_get_expression (expressionS * ep, char **str, int prefix_mode,
526 int prefix_present_p = 0;
533 if (is_immediate_prefix (**str))
536 prefix_present_p = 1;
543 memset (ep, 0, sizeof (expressionS));
545 save_in = input_line_pointer;
546 input_line_pointer = *str;
547 in_my_get_expression_p = TRUE;
548 seg = expression (ep);
549 in_my_get_expression_p = FALSE;
551 if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
553 /* We found a bad expression in md_operand(). */
554 *str = input_line_pointer;
555 input_line_pointer = save_in;
556 if (prefix_present_p && ! error_p ())
557 set_fatal_syntax_error (_("bad expression"));
559 set_first_syntax_error (_("bad expression"));
564 if (seg != absolute_section
565 && seg != text_section
566 && seg != data_section
567 && seg != bss_section && seg != undefined_section)
569 set_syntax_error (_("bad segment"));
570 *str = input_line_pointer;
571 input_line_pointer = save_in;
578 *str = input_line_pointer;
579 input_line_pointer = save_in;
583 /* Turn a string in input_line_pointer into a floating point constant
584 of type TYPE, and store the appropriate bytes in *LITP. The number
585 of LITTLENUMS emitted is stored in *SIZEP. An error message is
586 returned, or NULL on OK. */
589 md_atof (int type, char *litP, int *sizeP)
591 return ieee_md_atof (type, litP, sizeP, target_big_endian);
594 /* We handle all bad expressions here, so that we can report the faulty
595 instruction in the error message. */
597 md_operand (expressionS * exp)
599 if (in_my_get_expression_p)
600 exp->X_op = O_illegal;
603 /* Immediate values. */
605 /* Errors may be set multiple times during parsing or bit encoding
606 (particularly in the Neon bits), but usually the earliest error which is set
607 will be the most meaningful. Avoid overwriting it with later (cascading)
608 errors by calling this function. */
611 first_error (const char *error)
614 set_syntax_error (error);
617 /* Similiar to first_error, but this function accepts formatted error
620 first_error_fmt (const char *format, ...)
625 /* N.B. this single buffer will not cause error messages for different
626 instructions to pollute each other; this is because at the end of
627 processing of each assembly line, error message if any will be
628 collected by as_bad. */
629 static char buffer[size];
633 int ret ATTRIBUTE_UNUSED;
634 va_start (args, format);
635 ret = vsnprintf (buffer, size, format, args);
636 know (ret <= size - 1 && ret >= 0);
638 set_syntax_error (buffer);
642 /* Register parsing. */
644 /* Generic register parser which is called by other specialized
646 CCP points to what should be the beginning of a register name.
647 If it is indeed a valid register name, advance CCP over it and
648 return the reg_entry structure; otherwise return NULL.
649 It does not issue diagnostics. */
652 parse_reg (char **ccp)
658 #ifdef REGISTER_PREFIX
659 if (*start != REGISTER_PREFIX)
665 if (!ISALPHA (*p) || !is_name_beginner (*p))
670 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
672 reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start);
681 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
684 aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
686 if (reg->type == type)
691 case REG_TYPE_R64_SP: /* 64-bit integer reg (inc SP exc XZR). */
692 case REG_TYPE_R_Z_SP: /* Integer reg (inc {X}SP inc [WX]ZR). */
693 case REG_TYPE_R_Z_BHSDQ_V: /* Any register apart from Cn. */
694 case REG_TYPE_BHSDQ: /* Any [BHSDQ]P FP or SIMD scalar register. */
695 case REG_TYPE_VN: /* Vector register. */
696 gas_assert (reg->type < REG_TYPE_MAX && type < REG_TYPE_MAX);
697 return ((reg_type_masks[reg->type] & reg_type_masks[type])
698 == reg_type_masks[reg->type]);
700 as_fatal ("unhandled type %d", type);
705 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
706 Return the register number otherwise. *ISREG32 is set to one if the
707 register is 32-bit wide; *ISREGZERO is set to one if the register is
708 of type Z_32 or Z_64.
709 Note that this function does not issue any diagnostics. */
712 aarch64_reg_parse_32_64 (char **ccp, int reject_sp, int reject_rz,
713 int *isreg32, int *isregzero)
716 const reg_entry *reg = parse_reg (&str);
721 if (! aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP))
730 *isreg32 = reg->type == REG_TYPE_SP_32;
735 *isreg32 = reg->type == REG_TYPE_R_32;
742 *isreg32 = reg->type == REG_TYPE_Z_32;
754 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
755 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
756 otherwise return FALSE.
758 Accept only one occurrence of:
759 8b 16b 4h 8h 2s 4s 1d 2d
762 parse_neon_type_for_operand (struct neon_type_el *parsed_type, char **str)
766 unsigned element_size;
767 enum neon_el_type type;
777 width = strtoul (ptr, &ptr, 10);
778 if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
780 first_error_fmt (_("bad size %d in vector width specifier"), width);
785 switch (TOLOWER (*ptr))
813 first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
815 first_error (_("missing element size"));
818 if (width != 0 && width * element_size != 64 && width * element_size != 128)
821 ("invalid element size %d and vector size combination %c"),
827 parsed_type->type = type;
828 parsed_type->width = width;
835 /* Parse a single type, e.g. ".8b", leading period included.
836 Only applicable to Vn registers.
838 Return TRUE on success; otherwise return FALSE. */
840 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
846 if (! parse_neon_type_for_operand (vectype, &str))
848 first_error (_("vector type expected"));
860 /* Parse a register of the type TYPE.
862 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
863 name or the parsed register is not of TYPE.
865 Otherwise return the register number, and optionally fill in the actual
866 type of the register in *RTYPE when multiple alternatives were given, and
867 return the register shape and element index information in *TYPEINFO.
869 IN_REG_LIST should be set with TRUE if the caller is parsing a register
873 parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
874 struct neon_type_el *typeinfo, bfd_boolean in_reg_list)
877 const reg_entry *reg = parse_reg (&str);
878 struct neon_type_el atype;
879 struct neon_type_el parsetype;
880 bfd_boolean is_typed_vecreg = FALSE;
883 atype.type = NT_invtype;
891 set_default_error ();
895 if (! aarch64_check_reg_type (reg, type))
897 DEBUG_TRACE ("reg type check failed");
898 set_default_error ();
903 if (type == REG_TYPE_VN
904 && parse_neon_operand_type (&parsetype, &str))
906 /* Register if of the form Vn.[bhsdq]. */
907 is_typed_vecreg = TRUE;
909 if (parsetype.width == 0)
910 /* Expect index. In the new scheme we cannot have
911 Vn.[bhsdq] represent a scalar. Therefore any
912 Vn.[bhsdq] should have an index following it.
913 Except in reglists ofcourse. */
914 atype.defined |= NTA_HASINDEX;
916 atype.defined |= NTA_HASTYPE;
918 atype.type = parsetype.type;
919 atype.width = parsetype.width;
922 if (skip_past_char (&str, '['))
926 /* Reject Sn[index] syntax. */
927 if (!is_typed_vecreg)
929 first_error (_("this type of register can't be indexed"));
933 if (in_reg_list == TRUE)
935 first_error (_("index not allowed inside register list"));
939 atype.defined |= NTA_HASINDEX;
941 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
943 if (exp.X_op != O_constant)
945 first_error (_("constant expression required"));
949 if (! skip_past_char (&str, ']'))
952 atype.index = exp.X_add_number;
954 else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
956 /* Indexed vector register expected. */
957 first_error (_("indexed vector register expected"));
961 /* A vector reg Vn should be typed or indexed. */
962 if (type == REG_TYPE_VN && atype.defined == 0)
964 first_error (_("invalid use of vector register"));
980 Return the register number on success; return PARSE_FAIL otherwise.
982 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
983 the register (e.g. NEON double or quad reg when either has been requested).
985 If this is a NEON vector register with additional type information, fill
986 in the struct pointed to by VECTYPE (if non-NULL).
988 This parser does not handle register list. */
991 aarch64_reg_parse (char **ccp, aarch64_reg_type type,
992 aarch64_reg_type *rtype, struct neon_type_el *vectype)
994 struct neon_type_el atype;
996 int reg = parse_typed_reg (&str, type, rtype, &atype,
997 /*in_reg_list= */ FALSE);
999 if (reg == PARSE_FAIL)
1010 static inline bfd_boolean
1011 eq_neon_type_el (struct neon_type_el e1, struct neon_type_el e2)
1015 && e1.defined == e2.defined
1016 && e1.width == e2.width && e1.index == e2.index;
1019 /* This function parses the NEON register list. On success, it returns
1020 the parsed register list information in the following encoded format:
1022 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1023 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1025 The information of the register shape and/or index is returned in
1028 It returns PARSE_FAIL if the register list is invalid.
1030 The list contains one to four registers.
1031 Each register can be one of:
1034 All <T> should be identical.
1035 All <index> should be identical.
1036 There are restrictions on <Vt> numbers which are checked later
1037 (by reg_list_valid_p). */
1040 parse_neon_reg_list (char **ccp, struct neon_type_el *vectype)
1044 struct neon_type_el typeinfo, typeinfo_first;
1049 bfd_boolean error = FALSE;
1050 bfd_boolean expect_index = FALSE;
1054 set_syntax_error (_("expecting {"));
1060 typeinfo_first.defined = 0;
1061 typeinfo_first.type = NT_invtype;
1062 typeinfo_first.width = -1;
1063 typeinfo_first.index = 0;
1072 str++; /* skip over '-' */
1075 val = parse_typed_reg (&str, REG_TYPE_VN, NULL, &typeinfo,
1076 /*in_reg_list= */ TRUE);
1077 if (val == PARSE_FAIL)
1079 set_first_syntax_error (_("invalid vector register in list"));
1083 /* reject [bhsd]n */
1084 if (typeinfo.defined == 0)
1086 set_first_syntax_error (_("invalid scalar register in list"));
1091 if (typeinfo.defined & NTA_HASINDEX)
1092 expect_index = TRUE;
1096 if (val < val_range)
1098 set_first_syntax_error
1099 (_("invalid range in vector register list"));
1108 typeinfo_first = typeinfo;
1109 else if (! eq_neon_type_el (typeinfo_first, typeinfo))
1111 set_first_syntax_error
1112 (_("type mismatch in vector register list"));
1117 for (i = val_range; i <= val; i++)
1119 ret_val |= i << (5 * nb_regs);
1124 while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
1126 skip_whitespace (str);
1129 set_first_syntax_error (_("end of vector register list not found"));
1134 skip_whitespace (str);
1138 if (skip_past_char (&str, '['))
1142 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1143 if (exp.X_op != O_constant)
1145 set_first_syntax_error (_("constant expression required."));
1148 if (! skip_past_char (&str, ']'))
1151 typeinfo_first.index = exp.X_add_number;
1155 set_first_syntax_error (_("expected index"));
1162 set_first_syntax_error (_("too many registers in vector register list"));
1165 else if (nb_regs == 0)
1167 set_first_syntax_error (_("empty vector register list"));
1173 *vectype = typeinfo_first;
1175 return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1);
1178 /* Directives: register aliases. */
1181 insert_reg_alias (char *str, int number, aarch64_reg_type type)
1186 if ((new = hash_find (aarch64_reg_hsh, str)) != 0)
1189 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1192 /* Only warn about a redefinition if it's not defined as the
1194 else if (new->number != number || new->type != type)
1195 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1200 name = xstrdup (str);
1201 new = xmalloc (sizeof (reg_entry));
1204 new->number = number;
1206 new->builtin = FALSE;
1208 if (hash_insert (aarch64_reg_hsh, name, (void *) new))
1214 /* Look for the .req directive. This is of the form:
1216 new_register_name .req existing_register_name
1218 If we find one, or if it looks sufficiently like one that we want to
1219 handle any error here, return TRUE. Otherwise return FALSE. */
1222 create_register_alias (char *newname, char *p)
1224 const reg_entry *old;
1225 char *oldname, *nbuf;
1228 /* The input scrubber ensures that whitespace after the mnemonic is
1229 collapsed to single spaces. */
1231 if (strncmp (oldname, " .req ", 6) != 0)
1235 if (*oldname == '\0')
1238 old = hash_find (aarch64_reg_hsh, oldname);
1241 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1245 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1246 the desired alias name, and p points to its end. If not, then
1247 the desired alias name is in the global original_case_string. */
1248 #ifdef TC_CASE_SENSITIVE
1251 newname = original_case_string;
1252 nlen = strlen (newname);
1255 nbuf = alloca (nlen + 1);
1256 memcpy (nbuf, newname, nlen);
1259 /* Create aliases under the new name as stated; an all-lowercase
1260 version of the new name; and an all-uppercase version of the new
1262 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
1264 for (p = nbuf; *p; p++)
1267 if (strncmp (nbuf, newname, nlen))
1269 /* If this attempt to create an additional alias fails, do not bother
1270 trying to create the all-lower case alias. We will fail and issue
1271 a second, duplicate error message. This situation arises when the
1272 programmer does something like:
1275 The second .req creates the "Foo" alias but then fails to create
1276 the artificial FOO alias because it has already been created by the
1278 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
1282 for (p = nbuf; *p; p++)
1285 if (strncmp (nbuf, newname, nlen))
1286 insert_reg_alias (nbuf, old->number, old->type);
1292 /* Should never be called, as .req goes between the alias and the
1293 register name, not at the beginning of the line. */
1295 s_req (int a ATTRIBUTE_UNUSED)
1297 as_bad (_("invalid syntax for .req directive"));
1300 /* The .unreq directive deletes an alias which was previously defined
1301 by .req. For example:
1307 s_unreq (int a ATTRIBUTE_UNUSED)
1312 name = input_line_pointer;
1314 while (*input_line_pointer != 0
1315 && *input_line_pointer != ' ' && *input_line_pointer != '\n')
1316 ++input_line_pointer;
1318 saved_char = *input_line_pointer;
1319 *input_line_pointer = 0;
1322 as_bad (_("invalid syntax for .unreq directive"));
1325 reg_entry *reg = hash_find (aarch64_reg_hsh, name);
1328 as_bad (_("unknown register alias '%s'"), name);
1329 else if (reg->builtin)
1330 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1337 hash_delete (aarch64_reg_hsh, name, FALSE);
1338 free ((char *) reg->name);
1341 /* Also locate the all upper case and all lower case versions.
1342 Do not complain if we cannot find one or the other as it
1343 was probably deleted above. */
1345 nbuf = strdup (name);
1346 for (p = nbuf; *p; p++)
1348 reg = hash_find (aarch64_reg_hsh, nbuf);
1351 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1352 free ((char *) reg->name);
1356 for (p = nbuf; *p; p++)
1358 reg = hash_find (aarch64_reg_hsh, nbuf);
1361 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1362 free ((char *) reg->name);
1370 *input_line_pointer = saved_char;
1371 demand_empty_rest_of_line ();
1374 /* Directives: Instruction set selection. */
1377 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1378 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1379 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1380 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1382 /* Create a new mapping symbol for the transition to STATE. */
1385 make_mapping_symbol (enum mstate state, valueT value, fragS * frag)
1388 const char *symname;
1395 type = BSF_NO_FLAGS;
1399 type = BSF_NO_FLAGS;
1405 symbolP = symbol_new (symname, now_seg, value, frag);
1406 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1408 /* Save the mapping symbols for future reference. Also check that
1409 we do not place two mapping symbols at the same offset within a
1410 frag. We'll handle overlap between frags in
1411 check_mapping_symbols.
1413 If .fill or other data filling directive generates zero sized data,
1414 the mapping symbol for the following code will have the same value
1415 as the one generated for the data filling directive. In this case,
1416 we replace the old symbol with the new one at the same address. */
1419 if (frag->tc_frag_data.first_map != NULL)
1421 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
1422 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP,
1425 frag->tc_frag_data.first_map = symbolP;
1427 if (frag->tc_frag_data.last_map != NULL)
1429 know (S_GET_VALUE (frag->tc_frag_data.last_map) <=
1430 S_GET_VALUE (symbolP));
1431 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
1432 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP,
1435 frag->tc_frag_data.last_map = symbolP;
1438 /* We must sometimes convert a region marked as code to data during
1439 code alignment, if an odd number of bytes have to be padded. The
1440 code mapping symbol is pushed to an aligned address. */
1443 insert_data_mapping_symbol (enum mstate state,
1444 valueT value, fragS * frag, offsetT bytes)
1446 /* If there was already a mapping symbol, remove it. */
1447 if (frag->tc_frag_data.last_map != NULL
1448 && S_GET_VALUE (frag->tc_frag_data.last_map) ==
1449 frag->fr_address + value)
1451 symbolS *symp = frag->tc_frag_data.last_map;
1455 know (frag->tc_frag_data.first_map == symp);
1456 frag->tc_frag_data.first_map = NULL;
1458 frag->tc_frag_data.last_map = NULL;
1459 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
1462 make_mapping_symbol (MAP_DATA, value, frag);
1463 make_mapping_symbol (state, value + bytes, frag);
1466 static void mapping_state_2 (enum mstate state, int max_chars);
1468 /* Set the mapping state to STATE. Only call this when about to
1469 emit some STATE bytes to the file. */
1472 mapping_state (enum mstate state)
1474 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1476 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1478 if (mapstate == state)
1479 /* The mapping symbol has already been emitted.
1480 There is nothing else to do. */
1482 else if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
1483 /* This case will be evaluated later in the next else. */
1485 else if (TRANSITION (MAP_UNDEFINED, MAP_INSN))
1487 /* Only add the symbol if the offset is > 0:
1488 if we're at the first frag, check it's size > 0;
1489 if we're not at the first frag, then for sure
1490 the offset is > 0. */
1491 struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root;
1492 const int add_symbol = (frag_now != frag_first)
1493 || (frag_now_fix () > 0);
1496 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
1499 mapping_state_2 (state, 0);
1503 /* Same as mapping_state, but MAX_CHARS bytes have already been
1504 allocated. Put the mapping symbol that far back. */
1507 mapping_state_2 (enum mstate state, int max_chars)
1509 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1511 if (!SEG_NORMAL (now_seg))
1514 if (mapstate == state)
1515 /* The mapping symbol has already been emitted.
1516 There is nothing else to do. */
1519 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1520 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
1523 #define mapping_state(x) /* nothing */
1524 #define mapping_state_2(x, y) /* nothing */
1527 /* Directives: sectioning and alignment. */
1530 s_bss (int ignore ATTRIBUTE_UNUSED)
1532 /* We don't support putting frags in the BSS segment, we fake it by
1533 marking in_bss, then looking at s_skip for clues. */
1534 subseg_set (bss_section, 0);
1535 demand_empty_rest_of_line ();
1536 mapping_state (MAP_DATA);
1540 s_even (int ignore ATTRIBUTE_UNUSED)
1542 /* Never make frag if expect extra pass. */
1544 frag_align (1, 0, 0);
1546 record_alignment (now_seg, 1);
1548 demand_empty_rest_of_line ();
1551 /* Directives: Literal pools. */
1553 static literal_pool *
1554 find_literal_pool (int size)
1558 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1560 if (pool->section == now_seg
1561 && pool->sub_section == now_subseg && pool->size == size)
1568 static literal_pool *
1569 find_or_make_literal_pool (int size)
1571 /* Next literal pool ID number. */
1572 static unsigned int latest_pool_num = 1;
1575 pool = find_literal_pool (size);
1579 /* Create a new pool. */
1580 pool = xmalloc (sizeof (*pool));
1584 /* Currently we always put the literal pool in the current text
1585 section. If we were generating "small" model code where we
1586 knew that all code and initialised data was within 1MB then
1587 we could output literals to mergeable, read-only data
1590 pool->next_free_entry = 0;
1591 pool->section = now_seg;
1592 pool->sub_section = now_subseg;
1594 pool->next = list_of_pools;
1595 pool->symbol = NULL;
1597 /* Add it to the list. */
1598 list_of_pools = pool;
1601 /* New pools, and emptied pools, will have a NULL symbol. */
1602 if (pool->symbol == NULL)
1604 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1605 (valueT) 0, &zero_address_frag);
1606 pool->id = latest_pool_num++;
1613 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1614 Return TRUE on success, otherwise return FALSE. */
1616 add_to_lit_pool (expressionS *exp, int size)
1621 pool = find_or_make_literal_pool (size);
1623 /* Check if this literal value is already in the pool. */
1624 for (entry = 0; entry < pool->next_free_entry; entry++)
1626 if ((pool->literals[entry].X_op == exp->X_op)
1627 && (exp->X_op == O_constant)
1628 && (pool->literals[entry].X_add_number == exp->X_add_number)
1629 && (pool->literals[entry].X_unsigned == exp->X_unsigned))
1632 if ((pool->literals[entry].X_op == exp->X_op)
1633 && (exp->X_op == O_symbol)
1634 && (pool->literals[entry].X_add_number == exp->X_add_number)
1635 && (pool->literals[entry].X_add_symbol == exp->X_add_symbol)
1636 && (pool->literals[entry].X_op_symbol == exp->X_op_symbol))
1640 /* Do we need to create a new entry? */
1641 if (entry == pool->next_free_entry)
1643 if (entry >= MAX_LITERAL_POOL_SIZE)
1645 set_syntax_error (_("literal pool overflow"));
1649 pool->literals[entry] = *exp;
1650 pool->next_free_entry += 1;
1653 exp->X_op = O_symbol;
1654 exp->X_add_number = ((int) entry) * size;
1655 exp->X_add_symbol = pool->symbol;
1660 /* Can't use symbol_new here, so have to create a symbol and then at
1661 a later date assign it a value. Thats what these functions do. */
1664 symbol_locate (symbolS * symbolP,
1665 const char *name,/* It is copied, the caller can modify. */
1666 segT segment, /* Segment identifier (SEG_<something>). */
1667 valueT valu, /* Symbol value. */
1668 fragS * frag) /* Associated fragment. */
1670 unsigned int name_length;
1671 char *preserved_copy_of_name;
1673 name_length = strlen (name) + 1; /* +1 for \0. */
1674 obstack_grow (¬es, name, name_length);
1675 preserved_copy_of_name = obstack_finish (¬es);
1677 #ifdef tc_canonicalize_symbol_name
1678 preserved_copy_of_name =
1679 tc_canonicalize_symbol_name (preserved_copy_of_name);
1682 S_SET_NAME (symbolP, preserved_copy_of_name);
1684 S_SET_SEGMENT (symbolP, segment);
1685 S_SET_VALUE (symbolP, valu);
1686 symbol_clear_list_pointers (symbolP);
1688 symbol_set_frag (symbolP, frag);
1690 /* Link to end of symbol chain. */
1692 extern int symbol_table_frozen;
1694 if (symbol_table_frozen)
1698 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1700 obj_symbol_new_hook (symbolP);
1702 #ifdef tc_symbol_new_hook
1703 tc_symbol_new_hook (symbolP);
1707 verify_symbol_chain (symbol_rootP, symbol_lastP);
1708 #endif /* DEBUG_SYMS */
1713 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1720 for (align = 2; align <= 4; align++)
1722 int size = 1 << align;
1724 pool = find_literal_pool (size);
1725 if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
1728 mapping_state (MAP_DATA);
1730 /* Align pool as you have word accesses.
1731 Only make a frag if we have to. */
1733 frag_align (align, 0, 0);
1735 record_alignment (now_seg, align);
1737 sprintf (sym_name, "$$lit_\002%x", pool->id);
1739 symbol_locate (pool->symbol, sym_name, now_seg,
1740 (valueT) frag_now_fix (), frag_now);
1741 symbol_table_insert (pool->symbol);
1743 for (entry = 0; entry < pool->next_free_entry; entry++)
1744 /* First output the expression in the instruction to the pool. */
1745 emit_expr (&(pool->literals[entry]), size); /* .word|.xword */
1747 /* Mark the pool as empty. */
1748 pool->next_free_entry = 0;
1749 pool->symbol = NULL;
1754 /* Forward declarations for functions below, in the MD interface
1756 static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int);
1757 static struct reloc_table_entry * find_reloc_table_entry (char **);
1759 /* Directives: Data. */
1760 /* N.B. the support for relocation suffix in this directive needs to be
1761 implemented properly. */
1764 s_aarch64_elf_cons (int nbytes)
1768 #ifdef md_flush_pending_output
1769 md_flush_pending_output ();
1772 if (is_it_end_of_statement ())
1774 demand_empty_rest_of_line ();
1778 #ifdef md_cons_align
1779 md_cons_align (nbytes);
1782 mapping_state (MAP_DATA);
1785 struct reloc_table_entry *reloc;
1789 if (exp.X_op != O_symbol)
1790 emit_expr (&exp, (unsigned int) nbytes);
1793 skip_past_char (&input_line_pointer, '#');
1794 if (skip_past_char (&input_line_pointer, ':'))
1796 reloc = find_reloc_table_entry (&input_line_pointer);
1798 as_bad (_("unrecognized relocation suffix"));
1800 as_bad (_("unimplemented relocation suffix"));
1801 ignore_rest_of_line ();
1805 emit_expr (&exp, (unsigned int) nbytes);
1808 while (*input_line_pointer++ == ',');
1810 /* Put terminator back into stream. */
1811 input_line_pointer--;
1812 demand_empty_rest_of_line ();
1815 #endif /* OBJ_ELF */
1817 /* Output a 32-bit word, but mark as an instruction. */
1820 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
1824 #ifdef md_flush_pending_output
1825 md_flush_pending_output ();
1828 if (is_it_end_of_statement ())
1830 demand_empty_rest_of_line ();
1835 frag_align_code (2, 0);
1837 mapping_state (MAP_INSN);
1843 if (exp.X_op != O_constant)
1845 as_bad (_("constant expression required"));
1846 ignore_rest_of_line ();
1850 if (target_big_endian)
1852 unsigned int val = exp.X_add_number;
1853 exp.X_add_number = SWAP_32 (val);
1855 emit_expr (&exp, 4);
1857 while (*input_line_pointer++ == ',');
1859 /* Put terminator back into stream. */
1860 input_line_pointer--;
1861 demand_empty_rest_of_line ();
1865 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1868 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
1872 /* Since we're just labelling the code, there's no need to define a
1875 /* Make sure there is enough room in this frag for the following
1876 blr. This trick only works if the blr follows immediately after
1877 the .tlsdesc directive. */
1879 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1880 BFD_RELOC_AARCH64_TLSDESC_CALL);
1882 demand_empty_rest_of_line ();
1884 #endif /* OBJ_ELF */
1886 static void s_aarch64_arch (int);
1887 static void s_aarch64_cpu (int);
1889 /* This table describes all the machine specific pseudo-ops the assembler
1890 has to support. The fields are:
1891 pseudo-op name without dot
1892 function to call to execute this pseudo-op
1893 Integer arg to pass to the function. */
1895 const pseudo_typeS md_pseudo_table[] = {
1896 /* Never called because '.req' does not start a line. */
1898 {"unreq", s_unreq, 0},
1900 {"even", s_even, 0},
1901 {"ltorg", s_ltorg, 0},
1902 {"pool", s_ltorg, 0},
1903 {"cpu", s_aarch64_cpu, 0},
1904 {"arch", s_aarch64_arch, 0},
1905 {"inst", s_aarch64_inst, 0},
1907 {"tlsdesccall", s_tlsdesccall, 0},
1908 {"word", s_aarch64_elf_cons, 4},
1909 {"long", s_aarch64_elf_cons, 4},
1910 {"xword", s_aarch64_elf_cons, 8},
1911 {"dword", s_aarch64_elf_cons, 8},
1917 /* Check whether STR points to a register name followed by a comma or the
1918 end of line; REG_TYPE indicates which register types are checked
1919 against. Return TRUE if STR is such a register name; otherwise return
1920 FALSE. The function does not intend to produce any diagnostics, but since
1921 the register parser aarch64_reg_parse, which is called by this function,
1922 does produce diagnostics, we call clear_error to clear any diagnostics
1923 that may be generated by aarch64_reg_parse.
1924 Also, the function returns FALSE directly if there is any user error
1925 present at the function entry. This prevents the existing diagnostics
1926 state from being spoiled.
1927 The function currently serves parse_constant_immediate and
1928 parse_big_immediate only. */
1930 reg_name_p (char *str, aarch64_reg_type reg_type)
1934 /* Prevent the diagnostics state from being spoiled. */
1938 reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
1940 /* Clear the parsing error that may be set by the reg parser. */
1943 if (reg == PARSE_FAIL)
1946 skip_whitespace (str);
1947 if (*str == ',' || is_end_of_line[(unsigned int) *str])
1953 /* Parser functions used exclusively in instruction operands. */
1955 /* Parse an immediate expression which may not be constant.
1957 To prevent the expression parser from pushing a register name
1958 into the symbol table as an undefined symbol, firstly a check is
1959 done to find out whether STR is a valid register name followed
1960 by a comma or the end of line. Return FALSE if STR is such a
1964 parse_immediate_expression (char **str, expressionS *exp)
1966 if (reg_name_p (*str, REG_TYPE_R_Z_BHSDQ_V))
1968 set_recoverable_error (_("immediate operand required"));
1972 my_get_expression (exp, str, GE_OPT_PREFIX, 1);
1974 if (exp->X_op == O_absent)
1976 set_fatal_syntax_error (_("missing immediate expression"));
1983 /* Constant immediate-value read function for use in insn parsing.
1984 STR points to the beginning of the immediate (with the optional
1985 leading #); *VAL receives the value.
1987 Return TRUE on success; otherwise return FALSE. */
1990 parse_constant_immediate (char **str, int64_t * val)
1994 if (! parse_immediate_expression (str, &exp))
1997 if (exp.X_op != O_constant)
1999 set_syntax_error (_("constant expression required"));
2003 *val = exp.X_add_number;
2008 encode_imm_float_bits (uint32_t imm)
2010 return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2011 | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2014 /* Return TRUE if the single-precision floating-point value encoded in IMM
2015 can be expressed in the AArch64 8-bit signed floating-point format with
2016 3-bit exponent and normalized 4 bits of precision; in other words, the
2017 floating-point value must be expressable as
2018 (+/-) n / 16 * power (2, r)
2019 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2022 aarch64_imm_float_p (uint32_t imm)
2024 /* If a single-precision floating-point value has the following bit
2025 pattern, it can be expressed in the AArch64 8-bit floating-point
2028 3 32222222 2221111111111
2029 1 09876543 21098765432109876543210
2030 n Eeeeeexx xxxx0000000000000000000
2032 where n, e and each x are either 0 or 1 independently, with
2037 /* Prepare the pattern for 'Eeeeee'. */
2038 if (((imm >> 30) & 0x1) == 0)
2039 pattern = 0x3e000000;
2041 pattern = 0x40000000;
2043 return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */
2044 && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */
2047 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2049 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2050 8-bit signed floating-point format with 3-bit exponent and normalized 4
2051 bits of precision (i.e. can be used in an FMOV instruction); return the
2052 equivalent single-precision encoding in *FPWORD.
2054 Otherwise return FALSE. */
2057 aarch64_double_precision_fmovable (uint64_t imm, uint32_t *fpword)
2059 /* If a double-precision floating-point value has the following bit
2060 pattern, it can be expressed in the AArch64 8-bit floating-point
2063 6 66655555555 554444444...21111111111
2064 3 21098765432 109876543...098765432109876543210
2065 n Eeeeeeeeexx xxxx00000...000000000000000000000
2067 where n, e and each x are either 0 or 1 independently, with
2071 uint32_t high32 = imm >> 32;
2073 /* Lower 32 bits need to be 0s. */
2074 if ((imm & 0xffffffff) != 0)
2077 /* Prepare the pattern for 'Eeeeeeeee'. */
2078 if (((high32 >> 30) & 0x1) == 0)
2079 pattern = 0x3fc00000;
2081 pattern = 0x40000000;
2083 if ((high32 & 0xffff) == 0 /* bits 32 - 47 are 0. */
2084 && (high32 & 0x7fc00000) == pattern) /* bits 54 - 61 == ~ bit 62. */
2086 /* Convert to the single-precision encoding.
2088 n Eeeeeeeeexx xxxx00000...000000000000000000000
2090 n Eeeeeexx xxxx0000000000000000000. */
2091 *fpword = ((high32 & 0xfe000000) /* nEeeeee. */
2092 | (((high32 >> 16) & 0x3f) << 19)); /* xxxxxx. */
2099 /* Parse a floating-point immediate. Return TRUE on success and return the
2100 value in *IMMED in the format of IEEE754 single-precision encoding.
2101 *CCP points to the start of the string; DP_P is TRUE when the immediate
2102 is expected to be in double-precision (N.B. this only matters when
2103 hexadecimal representation is involved).
2105 N.B. 0.0 is accepted by this function. */
2108 parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p)
2112 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2113 int found_fpchar = 0;
2115 unsigned fpword = 0;
2116 bfd_boolean hex_p = FALSE;
2118 skip_past_char (&str, '#');
2121 skip_whitespace (fpnum);
2123 if (strncmp (fpnum, "0x", 2) == 0)
2125 /* Support the hexadecimal representation of the IEEE754 encoding.
2126 Double-precision is expected when DP_P is TRUE, otherwise the
2127 representation should be in single-precision. */
2128 if (! parse_constant_immediate (&str, &val))
2133 if (! aarch64_double_precision_fmovable (val, &fpword))
2136 else if ((uint64_t) val > 0xffffffff)
2145 /* We must not accidentally parse an integer as a floating-point number.
2146 Make sure that the value we parse is not an integer by checking for
2147 special characters '.' or 'e'. */
2148 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
2149 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
2163 if ((str = atof_ieee (str, 's', words)) == NULL)
2166 /* Our FP word must be 32 bits (single-precision FP). */
2167 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
2169 fpword <<= LITTLENUM_NUMBER_OF_BITS;
2174 if (aarch64_imm_float_p (fpword) || (fpword & 0x7fffffff) == 0)
2182 set_fatal_syntax_error (_("invalid floating-point constant"));
2186 /* Less-generic immediate-value read function with the possibility of loading
2187 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2190 To prevent the expression parser from pushing a register name into the
2191 symbol table as an undefined symbol, a check is firstly done to find
2192 out whether STR is a valid register name followed by a comma or the end
2193 of line. Return FALSE if STR is such a register. */
2196 parse_big_immediate (char **str, int64_t *imm)
2200 if (reg_name_p (ptr, REG_TYPE_R_Z_BHSDQ_V))
2202 set_syntax_error (_("immediate operand required"));
2206 my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
2208 if (inst.reloc.exp.X_op == O_constant)
2209 *imm = inst.reloc.exp.X_add_number;
2216 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2217 if NEED_LIBOPCODES is non-zero, the fixup will need
2218 assistance from the libopcodes. */
2221 aarch64_set_gas_internal_fixup (struct reloc *reloc,
2222 const aarch64_opnd_info *operand,
2223 int need_libopcodes_p)
2225 reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2226 reloc->opnd = operand->type;
2227 if (need_libopcodes_p)
2228 reloc->need_libopcodes_p = 1;
2231 /* Return TRUE if the instruction needs to be fixed up later internally by
2232 the GAS; otherwise return FALSE. */
2234 static inline bfd_boolean
2235 aarch64_gas_internal_fixup_p (void)
2237 return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2240 /* Assign the immediate value to the relavant field in *OPERAND if
2241 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2242 needs an internal fixup in a later stage.
2243 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2244 IMM.VALUE that may get assigned with the constant. */
2246 assign_imm_if_const_or_fixup_later (struct reloc *reloc,
2247 aarch64_opnd_info *operand,
2249 int need_libopcodes_p,
2252 if (reloc->exp.X_op == O_constant)
2255 operand->addr.offset.imm = reloc->exp.X_add_number;
2257 operand->imm.value = reloc->exp.X_add_number;
2258 reloc->type = BFD_RELOC_UNUSED;
2262 aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p);
2263 /* Tell libopcodes to ignore this operand or not. This is helpful
2264 when one of the operands needs to be fixed up later but we need
2265 libopcodes to check the other operands. */
2266 operand->skip = skip_p;
2270 /* Relocation modifiers. Each entry in the table contains the textual
2271 name for the relocation which may be placed before a symbol used as
2272 a load/store offset, or add immediate. It must be surrounded by a
2273 leading and trailing colon, for example:
2275 ldr x0, [x1, #:rello:varsym]
2276 add x0, x1, #:rello:varsym */
2278 struct reloc_table_entry
2282 bfd_reloc_code_real_type adrp_type;
2283 bfd_reloc_code_real_type movw_type;
2284 bfd_reloc_code_real_type add_type;
2285 bfd_reloc_code_real_type ldst_type;
2288 static struct reloc_table_entry reloc_table[] = {
2289 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2293 BFD_RELOC_AARCH64_ADD_LO12,
2294 BFD_RELOC_AARCH64_LDST_LO12},
2296 /* Higher 21 bits of pc-relative page offset: ADRP */
2298 BFD_RELOC_AARCH64_ADR_HI21_PCREL,
2303 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2305 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
2310 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2313 BFD_RELOC_AARCH64_MOVW_G0,
2317 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2320 BFD_RELOC_AARCH64_MOVW_G0_S,
2324 /* Less significant bits 0-15 of address/value: MOVK, no check */
2327 BFD_RELOC_AARCH64_MOVW_G0_NC,
2331 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2334 BFD_RELOC_AARCH64_MOVW_G1,
2338 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2341 BFD_RELOC_AARCH64_MOVW_G1_S,
2345 /* Less significant bits 16-31 of address/value: MOVK, no check */
2348 BFD_RELOC_AARCH64_MOVW_G1_NC,
2352 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2355 BFD_RELOC_AARCH64_MOVW_G2,
2359 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2362 BFD_RELOC_AARCH64_MOVW_G2_S,
2366 /* Less significant bits 32-47 of address/value: MOVK, no check */
2369 BFD_RELOC_AARCH64_MOVW_G2_NC,
2373 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2376 BFD_RELOC_AARCH64_MOVW_G3,
2380 /* Get to the page containing GOT entry for a symbol. */
2382 BFD_RELOC_AARCH64_ADR_GOT_PAGE,
2385 BFD_RELOC_AARCH64_GOT_LD_PREL19},
2387 /* 12 bit offset into the page containing GOT entry for that symbol. */
2392 BFD_RELOC_AARCH64_LD_GOT_LO12_NC},
2394 /* Get to the page containing GOT TLS entry for a symbol */
2396 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
2401 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2405 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
2408 /* Get to the page containing GOT TLS entry for a symbol */
2410 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21,
2415 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2419 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
2420 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC},
2422 /* Get to the page containing GOT TLS entry for a symbol */
2424 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
2429 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2430 {"gottprel_lo12", 0,
2434 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC},
2436 /* Get tp offset for a symbol. */
2440 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2443 /* Get tp offset for a symbol. */
2447 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2450 /* Get tp offset for a symbol. */
2454 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
2457 /* Get tp offset for a symbol. */
2458 {"tprel_lo12_nc", 0,
2461 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
2464 /* Most significant bits 32-47 of address/value: MOVZ. */
2467 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
2471 /* Most significant bits 16-31 of address/value: MOVZ. */
2474 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
2478 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2481 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
2485 /* Most significant bits 0-15 of address/value: MOVZ. */
2488 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
2492 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2495 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
2500 /* Given the address of a pointer pointing to the textual name of a
2501 relocation as may appear in assembler source, attempt to find its
2502 details in reloc_table. The pointer will be updated to the character
2503 after the trailing colon. On failure, NULL will be returned;
2504 otherwise return the reloc_table_entry. */
2506 static struct reloc_table_entry *
2507 find_reloc_table_entry (char **str)
2510 for (i = 0; i < ARRAY_SIZE (reloc_table); i++)
2512 int length = strlen (reloc_table[i].name);
2514 if (strncasecmp (reloc_table[i].name, *str, length) == 0
2515 && (*str)[length] == ':')
2517 *str += (length + 1);
2518 return &reloc_table[i];
2525 /* Mode argument to parse_shift and parser_shifter_operand. */
2526 enum parse_shift_mode
2528 SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2530 SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2532 SHIFTED_LSL, /* bare "lsl #n" */
2533 SHIFTED_LSL_MSL, /* "lsl|msl #n" */
2534 SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */
2537 /* Parse a <shift> operator on an AArch64 data processing instruction.
2538 Return TRUE on success; otherwise return FALSE. */
2540 parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
2542 const struct aarch64_name_value_pair *shift_op;
2543 enum aarch64_modifier_kind kind;
2549 for (p = *str; ISALPHA (*p); p++)
2554 set_syntax_error (_("shift expression expected"));
2558 shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str);
2560 if (shift_op == NULL)
2562 set_syntax_error (_("shift operator expected"));
2566 kind = aarch64_get_operand_modifier (shift_op);
2568 if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
2570 set_syntax_error (_("invalid use of 'MSL'"));
2576 case SHIFTED_LOGIC_IMM:
2577 if (aarch64_extend_operator_p (kind) == TRUE)
2579 set_syntax_error (_("extending shift is not permitted"));
2584 case SHIFTED_ARITH_IMM:
2585 if (kind == AARCH64_MOD_ROR)
2587 set_syntax_error (_("'ROR' shift is not permitted"));
2593 if (kind != AARCH64_MOD_LSL)
2595 set_syntax_error (_("only 'LSL' shift is permitted"));
2600 case SHIFTED_REG_OFFSET:
2601 if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
2602 && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX)
2604 set_fatal_syntax_error
2605 (_("invalid shift for the register offset addressing mode"));
2610 case SHIFTED_LSL_MSL:
2611 if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
2613 set_syntax_error (_("invalid shift operator"));
2622 /* Whitespace can appear here if the next thing is a bare digit. */
2623 skip_whitespace (p);
2625 /* Parse shift amount. */
2627 if (mode == SHIFTED_REG_OFFSET && *p == ']')
2628 exp.X_op = O_absent;
2631 if (is_immediate_prefix (*p))
2636 my_get_expression (&exp, &p, GE_NO_PREFIX, 0);
2638 if (exp.X_op == O_absent)
2640 if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
2642 set_syntax_error (_("missing shift amount"));
2645 operand->shifter.amount = 0;
2647 else if (exp.X_op != O_constant)
2649 set_syntax_error (_("constant shift amount required"));
2652 else if (exp.X_add_number < 0 || exp.X_add_number > 63)
2654 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2659 operand->shifter.amount = exp.X_add_number;
2660 operand->shifter.amount_present = 1;
2663 operand->shifter.operator_present = 1;
2664 operand->shifter.kind = kind;
2670 /* Parse a <shifter_operand> for a data processing instruction:
2673 #<immediate>, LSL #imm
2675 Validation of immediate operands is deferred to md_apply_fix.
2677 Return TRUE on success; otherwise return FALSE. */
2680 parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
2681 enum parse_shift_mode mode)
2685 if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
2690 /* Accept an immediate expression. */
2691 if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
2694 /* Accept optional LSL for arithmetic immediate values. */
2695 if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
2696 if (! parse_shift (&p, operand, SHIFTED_LSL))
2699 /* Not accept any shifter for logical immediate values. */
2700 if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
2701 && parse_shift (&p, operand, mode))
2703 set_syntax_error (_("unexpected shift operator"));
2711 /* Parse a <shifter_operand> for a data processing instruction:
2716 #<immediate>, LSL #imm
2718 where <shift> is handled by parse_shift above, and the last two
2719 cases are handled by the function above.
2721 Validation of immediate operands is deferred to md_apply_fix.
2723 Return TRUE on success; otherwise return FALSE. */
2726 parse_shifter_operand (char **str, aarch64_opnd_info *operand,
2727 enum parse_shift_mode mode)
2730 int isreg32, isregzero;
2731 enum aarch64_operand_class opd_class
2732 = aarch64_get_operand_class (operand->type);
2735 aarch64_reg_parse_32_64 (str, 0, 0, &isreg32, &isregzero)) != PARSE_FAIL)
2737 if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
2739 set_syntax_error (_("unexpected register in the immediate operand"));
2743 if (!isregzero && reg == REG_SP)
2745 set_syntax_error (BAD_SP);
2749 operand->reg.regno = reg;
2750 operand->qualifier = isreg32 ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
2752 /* Accept optional shift operation on register. */
2753 if (! skip_past_comma (str))
2756 if (! parse_shift (str, operand, mode))
2761 else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
2764 (_("integer register expected in the extended/shifted operand "
2769 /* We have a shifted immediate variable. */
2770 return parse_shifter_operand_imm (str, operand, mode);
2773 /* Return TRUE on success; return FALSE otherwise. */
2776 parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
2777 enum parse_shift_mode mode)
2781 /* Determine if we have the sequence of characters #: or just :
2782 coming next. If we do, then we check for a :rello: relocation
2783 modifier. If we don't, punt the whole lot to
2784 parse_shifter_operand. */
2786 if ((p[0] == '#' && p[1] == ':') || p[0] == ':')
2788 struct reloc_table_entry *entry;
2796 /* Try to parse a relocation. Anything else is an error. */
2797 if (!(entry = find_reloc_table_entry (str)))
2799 set_syntax_error (_("unknown relocation modifier"));
2803 if (entry->add_type == 0)
2806 (_("this relocation modifier is not allowed on this instruction"));
2810 /* Save str before we decompose it. */
2813 /* Next, we parse the expression. */
2814 if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
2817 /* Record the relocation type (use the ADD variant here). */
2818 inst.reloc.type = entry->add_type;
2819 inst.reloc.pc_rel = entry->pc_rel;
2821 /* If str is empty, we've reached the end, stop here. */
2825 /* Otherwise, we have a shifted reloc modifier, so rewind to
2826 recover the variable name and continue parsing for the shifter. */
2828 return parse_shifter_operand_imm (str, operand, mode);
2831 return parse_shifter_operand (str, operand, mode);
2834 /* Parse all forms of an address expression. Information is written
2835 to *OPERAND and/or inst.reloc.
2837 The A64 instruction set has the following addressing modes:
2840 [base] // in SIMD ld/st structure
2841 [base{,#0}] // in ld/st exclusive
2843 [base,Xm{,LSL #imm}]
2844 [base,Xm,SXTX {#imm}]
2845 [base,Wm,(S|U)XTW {#imm}]
2850 [base],Xm // in SIMD ld/st structure
2851 PC-relative (literal)
2855 (As a convenience, the notation "=immediate" is permitted in conjunction
2856 with the pc-relative literal load instructions to automatically place an
2857 immediate value or symbolic address in a nearby literal pool and generate
2858 a hidden label which references it.)
2860 Upon a successful parsing, the address structure in *OPERAND will be
2861 filled in the following way:
2863 .base_regno = <base>
2864 .offset.is_reg // 1 if the offset is a register
2866 .offset.regno = <Rm>
2868 For different addressing modes defined in the A64 ISA:
2871 .pcrel=0; .preind=1; .postind=0; .writeback=0
2873 .pcrel=0; .preind=1; .postind=0; .writeback=1
2875 .pcrel=0; .preind=0; .postind=1; .writeback=1
2876 PC-relative (literal)
2877 .pcrel=1; .preind=1; .postind=0; .writeback=0
2879 The shift/extension information, if any, will be stored in .shifter.
2881 It is the caller's responsibility to check for addressing modes not
2882 supported by the instruction, and to set inst.reloc.type. */
2885 parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
2886 int accept_reg_post_index)
2890 int isreg32, isregzero;
2891 expressionS *exp = &inst.reloc.exp;
2893 if (! skip_past_char (&p, '['))
2895 /* =immediate or label. */
2896 operand->addr.pcrel = 1;
2897 operand->addr.preind = 1;
2899 /* #:<reloc_op>:<symbol> */
2900 skip_past_char (&p, '#');
2901 if (reloc && skip_past_char (&p, ':'))
2903 struct reloc_table_entry *entry;
2905 /* Try to parse a relocation modifier. Anything else is
2907 entry = find_reloc_table_entry (&p);
2910 set_syntax_error (_("unknown relocation modifier"));
2914 if (entry->ldst_type == 0)
2917 (_("this relocation modifier is not allowed on this "
2923 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
2925 set_syntax_error (_("invalid relocation expression"));
2929 /* #:<reloc_op>:<expr> */
2930 /* Record the load/store relocation type. */
2931 inst.reloc.type = entry->ldst_type;
2932 inst.reloc.pc_rel = entry->pc_rel;
2937 if (skip_past_char (&p, '='))
2938 /* =immediate; need to generate the literal in the literal pool. */
2939 inst.gen_lit_pool = 1;
2941 if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1))
2943 set_syntax_error (_("invalid address"));
2954 /* Accept SP and reject ZR */
2955 reg = aarch64_reg_parse_32_64 (&p, 0, 1, &isreg32, &isregzero);
2956 if (reg == PARSE_FAIL || isreg32)
2958 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
2961 operand->addr.base_regno = reg;
2964 if (skip_past_comma (&p))
2967 operand->addr.preind = 1;
2969 /* Reject SP and accept ZR */
2970 reg = aarch64_reg_parse_32_64 (&p, 1, 0, &isreg32, &isregzero);
2971 if (reg != PARSE_FAIL)
2974 operand->addr.offset.regno = reg;
2975 operand->addr.offset.is_reg = 1;
2976 /* Shifted index. */
2977 if (skip_past_comma (&p))
2980 if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
2981 /* Use the diagnostics set in parse_shift, so not set new
2982 error message here. */
2986 [base,Xm{,LSL #imm}]
2987 [base,Xm,SXTX {#imm}]
2988 [base,Wm,(S|U)XTW {#imm}] */
2989 if (operand->shifter.kind == AARCH64_MOD_NONE
2990 || operand->shifter.kind == AARCH64_MOD_LSL
2991 || operand->shifter.kind == AARCH64_MOD_SXTX)
2995 set_syntax_error (_("invalid use of 32-bit register offset"));
3001 set_syntax_error (_("invalid use of 64-bit register offset"));
3007 /* [Xn,#:<reloc_op>:<symbol> */
3008 skip_past_char (&p, '#');
3009 if (reloc && skip_past_char (&p, ':'))
3011 struct reloc_table_entry *entry;
3013 /* Try to parse a relocation modifier. Anything else is
3015 if (!(entry = find_reloc_table_entry (&p)))
3017 set_syntax_error (_("unknown relocation modifier"));
3021 if (entry->ldst_type == 0)
3024 (_("this relocation modifier is not allowed on this "
3029 /* [Xn,#:<reloc_op>: */
3030 /* We now have the group relocation table entry corresponding to
3031 the name in the assembler source. Next, we parse the
3033 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
3035 set_syntax_error (_("invalid relocation expression"));
3039 /* [Xn,#:<reloc_op>:<expr> */
3040 /* Record the load/store relocation type. */
3041 inst.reloc.type = entry->ldst_type;
3042 inst.reloc.pc_rel = entry->pc_rel;
3044 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3046 set_syntax_error (_("invalid expression in the address"));
3053 if (! skip_past_char (&p, ']'))
3055 set_syntax_error (_("']' expected"));
3059 if (skip_past_char (&p, '!'))
3061 if (operand->addr.preind && operand->addr.offset.is_reg)
3063 set_syntax_error (_("register offset not allowed in pre-indexed "
3064 "addressing mode"));
3068 operand->addr.writeback = 1;
3070 else if (skip_past_comma (&p))
3073 operand->addr.postind = 1;
3074 operand->addr.writeback = 1;
3076 if (operand->addr.preind)
3078 set_syntax_error (_("cannot combine pre- and post-indexing"));
3082 if (accept_reg_post_index
3083 && (reg = aarch64_reg_parse_32_64 (&p, 1, 1, &isreg32,
3084 &isregzero)) != PARSE_FAIL)
3089 set_syntax_error (_("invalid 32-bit register offset"));
3092 operand->addr.offset.regno = reg;
3093 operand->addr.offset.is_reg = 1;
3095 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3098 set_syntax_error (_("invalid expression in the address"));
3103 /* If at this point neither .preind nor .postind is set, we have a
3104 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3105 if (operand->addr.preind == 0 && operand->addr.postind == 0)
3107 if (operand->addr.writeback)
3110 set_syntax_error (_("missing offset in the pre-indexed address"));
3113 operand->addr.preind = 1;
3114 inst.reloc.exp.X_op = O_constant;
3115 inst.reloc.exp.X_add_number = 0;
3122 /* Return TRUE on success; otherwise return FALSE. */
3124 parse_address (char **str, aarch64_opnd_info *operand,
3125 int accept_reg_post_index)
3127 return parse_address_main (str, operand, 0, accept_reg_post_index);
3130 /* Return TRUE on success; otherwise return FALSE. */
3132 parse_address_reloc (char **str, aarch64_opnd_info *operand)
3134 return parse_address_main (str, operand, 1, 0);
3137 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3138 Return TRUE on success; otherwise return FALSE. */
3140 parse_half (char **str, int *internal_fixup_p)
3146 skip_past_char (&p, '#');
3148 gas_assert (internal_fixup_p);
3149 *internal_fixup_p = 0;
3153 struct reloc_table_entry *entry;
3155 /* Try to parse a relocation. Anything else is an error. */
3157 if (!(entry = find_reloc_table_entry (&p)))
3159 set_syntax_error (_("unknown relocation modifier"));
3163 if (entry->movw_type == 0)
3166 (_("this relocation modifier is not allowed on this instruction"));
3170 inst.reloc.type = entry->movw_type;
3173 *internal_fixup_p = 1;
3175 /* Avoid parsing a register as a general symbol. */
3177 if (aarch64_reg_parse_32_64 (&p, 0, 0, &dummy, &dummy) != PARSE_FAIL)
3181 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3188 /* Parse an operand for an ADRP instruction:
3190 Return TRUE on success; otherwise return FALSE. */
3193 parse_adrp (char **str)
3200 struct reloc_table_entry *entry;
3202 /* Try to parse a relocation. Anything else is an error. */
3204 if (!(entry = find_reloc_table_entry (&p)))
3206 set_syntax_error (_("unknown relocation modifier"));
3210 if (entry->adrp_type == 0)
3213 (_("this relocation modifier is not allowed on this instruction"));
3217 inst.reloc.type = entry->adrp_type;
3220 inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
3222 inst.reloc.pc_rel = 1;
3224 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3231 /* Miscellaneous. */
3233 /* Parse an option for a preload instruction. Returns the encoding for the
3234 option, or PARSE_FAIL. */
3237 parse_pldop (char **str)
3240 const struct aarch64_name_value_pair *o;
3243 while (ISALNUM (*q))
3246 o = hash_find_n (aarch64_pldop_hsh, p, q - p);
3254 /* Parse an option for a barrier instruction. Returns the encoding for the
3255 option, or PARSE_FAIL. */
3258 parse_barrier (char **str)
3261 const asm_barrier_opt *o;
3264 while (ISALPHA (*q))
3267 o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p);
3275 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3276 Returns the encoding for the option, or PARSE_FAIL. If SYS_REG is not
3277 NULL, return in *SYS_REG the found descriptor.
3279 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3280 implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
3283 parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p,
3284 const aarch64_sys_reg ** sys_reg)
3288 const aarch64_sys_reg *o;
3292 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3294 *p++ = TOLOWER (*q);
3296 /* Assert that BUF be large enough. */
3297 gas_assert (p - buf == q - *str);
3299 o = hash_find (sys_regs, buf);
3302 if (!imple_defined_p)
3306 /* Parse S3_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
3308 unsigned int op0, op1, cn, cm, op2;
3309 if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
3311 /* The architecture specifies the encoding space for implementation
3312 defined registers as:
3314 11 xxx 1x11 xxxx xxx
3315 For convenience GAS accepts a wider encoding space, as follows:
3317 11 xxx xxxx xxxx xxx */
3318 if (op0 != 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
3320 value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
3325 if (aarch64_sys_reg_deprecated_p (o))
3326 as_warn (_("system register name '%s' is deprecated and may be "
3327 "removed in a future release"), buf);
3338 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3339 for the option, or NULL. */
3341 static const aarch64_sys_ins_reg *
3342 parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
3346 const aarch64_sys_ins_reg *o;
3349 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3351 *p++ = TOLOWER (*q);
3354 o = hash_find (sys_ins_regs, buf);
3362 #define po_char_or_fail(chr) do { \
3363 if (! skip_past_char (&str, chr)) \
3367 #define po_reg_or_fail(regtype) do { \
3368 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3369 if (val == PARSE_FAIL) \
3371 set_default_error (); \
3376 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3377 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3378 &isreg32, &isregzero); \
3379 if (val == PARSE_FAIL) \
3381 set_default_error (); \
3384 info->reg.regno = val; \
3386 info->qualifier = AARCH64_OPND_QLF_W; \
3388 info->qualifier = AARCH64_OPND_QLF_X; \
3391 #define po_imm_nc_or_fail() do { \
3392 if (! parse_constant_immediate (&str, &val)) \
3396 #define po_imm_or_fail(min, max) do { \
3397 if (! parse_constant_immediate (&str, &val)) \
3399 if (val < min || val > max) \
3401 set_fatal_syntax_error (_("immediate value out of range "\
3402 #min " to "#max)); \
3407 #define po_misc_or_fail(expr) do { \
3412 /* encode the 12-bit imm field of Add/sub immediate */
3413 static inline uint32_t
3414 encode_addsub_imm (uint32_t imm)
3419 /* encode the shift amount field of Add/sub immediate */
3420 static inline uint32_t
3421 encode_addsub_imm_shift_amount (uint32_t cnt)
3427 /* encode the imm field of Adr instruction */
3428 static inline uint32_t
3429 encode_adr_imm (uint32_t imm)
3431 return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */
3432 | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3435 /* encode the immediate field of Move wide immediate */
3436 static inline uint32_t
3437 encode_movw_imm (uint32_t imm)
3442 /* encode the 26-bit offset of unconditional branch */
3443 static inline uint32_t
3444 encode_branch_ofs_26 (uint32_t ofs)
3446 return ofs & ((1 << 26) - 1);
3449 /* encode the 19-bit offset of conditional branch and compare & branch */
3450 static inline uint32_t
3451 encode_cond_branch_ofs_19 (uint32_t ofs)
3453 return (ofs & ((1 << 19) - 1)) << 5;
3456 /* encode the 19-bit offset of ld literal */
3457 static inline uint32_t
3458 encode_ld_lit_ofs_19 (uint32_t ofs)
3460 return (ofs & ((1 << 19) - 1)) << 5;
3463 /* Encode the 14-bit offset of test & branch. */
3464 static inline uint32_t
3465 encode_tst_branch_ofs_14 (uint32_t ofs)
3467 return (ofs & ((1 << 14) - 1)) << 5;
3470 /* Encode the 16-bit imm field of svc/hvc/smc. */
3471 static inline uint32_t
3472 encode_svc_imm (uint32_t imm)
3477 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3478 static inline uint32_t
3479 reencode_addsub_switch_add_sub (uint32_t opcode)
3481 return opcode ^ (1 << 30);
3484 static inline uint32_t
3485 reencode_movzn_to_movz (uint32_t opcode)
3487 return opcode | (1 << 30);
3490 static inline uint32_t
3491 reencode_movzn_to_movn (uint32_t opcode)
3493 return opcode & ~(1 << 30);
3496 /* Overall per-instruction processing. */
3498 /* We need to be able to fix up arbitrary expressions in some statements.
3499 This is so that we can handle symbols that are an arbitrary distance from
3500 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3501 which returns part of an address in a form which will be valid for
3502 a data instruction. We do this by pushing the expression into a symbol
3503 in the expr_section, and creating a fix for that. */
3506 fix_new_aarch64 (fragS * frag,
3508 short int size, expressionS * exp, int pc_rel, int reloc)
3518 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
3522 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
3529 /* Diagnostics on operands errors. */
3531 /* By default, output one-line error message only.
3532 Enable the verbose error message by -merror-verbose. */
3533 static int verbose_error_p = 0;
3535 #ifdef DEBUG_AARCH64
3536 /* N.B. this is only for the purpose of debugging. */
3537 const char* operand_mismatch_kind_names[] =
3540 "AARCH64_OPDE_RECOVERABLE",
3541 "AARCH64_OPDE_SYNTAX_ERROR",
3542 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3543 "AARCH64_OPDE_INVALID_VARIANT",
3544 "AARCH64_OPDE_OUT_OF_RANGE",
3545 "AARCH64_OPDE_UNALIGNED",
3546 "AARCH64_OPDE_REG_LIST",
3547 "AARCH64_OPDE_OTHER_ERROR",
3549 #endif /* DEBUG_AARCH64 */
3551 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3553 When multiple errors of different kinds are found in the same assembly
3554 line, only the error of the highest severity will be picked up for
3555 issuing the diagnostics. */
3557 static inline bfd_boolean
3558 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
3559 enum aarch64_operand_error_kind rhs)
3561 gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL);
3562 gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE);
3563 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
3564 gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
3565 gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
3566 gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
3567 gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
3568 gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
3572 /* Helper routine to get the mnemonic name from the assembly instruction
3573 line; should only be called for the diagnosis purpose, as there is
3574 string copy operation involved, which may affect the runtime
3575 performance if used in elsewhere. */
3578 get_mnemonic_name (const char *str)
3580 static char mnemonic[32];
3583 /* Get the first 15 bytes and assume that the full name is included. */
3584 strncpy (mnemonic, str, 31);
3585 mnemonic[31] = '\0';
3587 /* Scan up to the end of the mnemonic, which must end in white space,
3588 '.', or end of string. */
3589 for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr)
3594 /* Append '...' to the truncated long name. */
3595 if (ptr - mnemonic == 31)
3596 mnemonic[28] = mnemonic[29] = mnemonic[30] = '.';
3602 reset_aarch64_instruction (aarch64_instruction *instruction)
3604 memset (instruction, '\0', sizeof (aarch64_instruction));
3605 instruction->reloc.type = BFD_RELOC_UNUSED;
3608 /* Data strutures storing one user error in the assembly code related to
3611 struct operand_error_record
3613 const aarch64_opcode *opcode;
3614 aarch64_operand_error detail;
3615 struct operand_error_record *next;
3618 typedef struct operand_error_record operand_error_record;
3620 struct operand_errors
3622 operand_error_record *head;
3623 operand_error_record *tail;
3626 typedef struct operand_errors operand_errors;
3628 /* Top-level data structure reporting user errors for the current line of
3630 The way md_assemble works is that all opcodes sharing the same mnemonic
3631 name are iterated to find a match to the assembly line. In this data
3632 structure, each of the such opcodes will have one operand_error_record
3633 allocated and inserted. In other words, excessive errors related with
3634 a single opcode are disregarded. */
3635 operand_errors operand_error_report;
3637 /* Free record nodes. */
3638 static operand_error_record *free_opnd_error_record_nodes = NULL;
3640 /* Initialize the data structure that stores the operand mismatch
3641 information on assembling one line of the assembly code. */
3643 init_operand_error_report (void)
3645 if (operand_error_report.head != NULL)
3647 gas_assert (operand_error_report.tail != NULL);
3648 operand_error_report.tail->next = free_opnd_error_record_nodes;
3649 free_opnd_error_record_nodes = operand_error_report.head;
3650 operand_error_report.head = NULL;
3651 operand_error_report.tail = NULL;
3654 gas_assert (operand_error_report.tail == NULL);
3657 /* Return TRUE if some operand error has been recorded during the
3658 parsing of the current assembly line using the opcode *OPCODE;
3659 otherwise return FALSE. */
3660 static inline bfd_boolean
3661 opcode_has_operand_error_p (const aarch64_opcode *opcode)
3663 operand_error_record *record = operand_error_report.head;
3664 return record && record->opcode == opcode;
3667 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3668 OPCODE field is initialized with OPCODE.
3669 N.B. only one record for each opcode, i.e. the maximum of one error is
3670 recorded for each instruction template. */
3673 add_operand_error_record (const operand_error_record* new_record)
3675 const aarch64_opcode *opcode = new_record->opcode;
3676 operand_error_record* record = operand_error_report.head;
3678 /* The record may have been created for this opcode. If not, we need
3680 if (! opcode_has_operand_error_p (opcode))
3682 /* Get one empty record. */
3683 if (free_opnd_error_record_nodes == NULL)
3685 record = xmalloc (sizeof (operand_error_record));
3691 record = free_opnd_error_record_nodes;
3692 free_opnd_error_record_nodes = record->next;
3694 record->opcode = opcode;
3695 /* Insert at the head. */
3696 record->next = operand_error_report.head;
3697 operand_error_report.head = record;
3698 if (operand_error_report.tail == NULL)
3699 operand_error_report.tail = record;
3701 else if (record->detail.kind != AARCH64_OPDE_NIL
3702 && record->detail.index <= new_record->detail.index
3703 && operand_error_higher_severity_p (record->detail.kind,
3704 new_record->detail.kind))
3706 /* In the case of multiple errors found on operands related with a
3707 single opcode, only record the error of the leftmost operand and
3708 only if the error is of higher severity. */
3709 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3710 " the existing error %s on operand %d",
3711 operand_mismatch_kind_names[new_record->detail.kind],
3712 new_record->detail.index,
3713 operand_mismatch_kind_names[record->detail.kind],
3714 record->detail.index);
3718 record->detail = new_record->detail;
3722 record_operand_error_info (const aarch64_opcode *opcode,
3723 aarch64_operand_error *error_info)
3725 operand_error_record record;
3726 record.opcode = opcode;
3727 record.detail = *error_info;
3728 add_operand_error_record (&record);
3731 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3732 error message *ERROR, for operand IDX (count from 0). */
3735 record_operand_error (const aarch64_opcode *opcode, int idx,
3736 enum aarch64_operand_error_kind kind,
3739 aarch64_operand_error info;
3740 memset(&info, 0, sizeof (info));
3744 record_operand_error_info (opcode, &info);
3748 record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
3749 enum aarch64_operand_error_kind kind,
3750 const char* error, const int *extra_data)
3752 aarch64_operand_error info;
3756 info.data[0] = extra_data[0];
3757 info.data[1] = extra_data[1];
3758 info.data[2] = extra_data[2];
3759 record_operand_error_info (opcode, &info);
3763 record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx,
3764 const char* error, int lower_bound,
3767 int data[3] = {lower_bound, upper_bound, 0};
3768 record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE,
3772 /* Remove the operand error record for *OPCODE. */
3773 static void ATTRIBUTE_UNUSED
3774 remove_operand_error_record (const aarch64_opcode *opcode)
3776 if (opcode_has_operand_error_p (opcode))
3778 operand_error_record* record = operand_error_report.head;
3779 gas_assert (record != NULL && operand_error_report.tail != NULL);
3780 operand_error_report.head = record->next;
3781 record->next = free_opnd_error_record_nodes;
3782 free_opnd_error_record_nodes = record;
3783 if (operand_error_report.head == NULL)
3785 gas_assert (operand_error_report.tail == record);
3786 operand_error_report.tail = NULL;
3791 /* Given the instruction in *INSTR, return the index of the best matched
3792 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3794 Return -1 if there is no qualifier sequence; return the first match
3795 if there is multiple matches found. */
3798 find_best_match (const aarch64_inst *instr,
3799 const aarch64_opnd_qualifier_seq_t *qualifiers_list)
3801 int i, num_opnds, max_num_matched, idx;
3803 num_opnds = aarch64_num_of_operands (instr->opcode);
3806 DEBUG_TRACE ("no operand");
3810 max_num_matched = 0;
3813 /* For each pattern. */
3814 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
3817 const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
3819 /* Most opcodes has much fewer patterns in the list. */
3820 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
3822 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
3823 if (i != 0 && idx == -1)
3824 /* If nothing has been matched, return the 1st sequence. */
3829 for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers)
3830 if (*qualifiers == instr->operands[j].qualifier)
3833 if (num_matched > max_num_matched)
3835 max_num_matched = num_matched;
3840 DEBUG_TRACE ("return with %d", idx);
3844 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3845 corresponding operands in *INSTR. */
3848 assign_qualifier_sequence (aarch64_inst *instr,
3849 const aarch64_opnd_qualifier_t *qualifiers)
3852 int num_opnds = aarch64_num_of_operands (instr->opcode);
3853 gas_assert (num_opnds);
3854 for (i = 0; i < num_opnds; ++i, ++qualifiers)
3855 instr->operands[i].qualifier = *qualifiers;
3858 /* Print operands for the diagnosis purpose. */
3861 print_operands (char *buf, const aarch64_opcode *opcode,
3862 const aarch64_opnd_info *opnds)
3866 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3868 const size_t size = 128;
3871 /* We regard the opcode operand info more, however we also look into
3872 the inst->operands to support the disassembling of the optional
3874 The two operand code should be the same in all cases, apart from
3875 when the operand can be optional. */
3876 if (opcode->operands[i] == AARCH64_OPND_NIL
3877 || opnds[i].type == AARCH64_OPND_NIL)
3880 /* Generate the operand string in STR. */
3881 aarch64_print_operand (str, size, 0, opcode, opnds, i, NULL, NULL);
3885 strcat (buf, i == 0 ? " " : ",");
3887 /* Append the operand string. */
3892 /* Send to stderr a string as information. */
3895 output_info (const char *format, ...)
3901 as_where (&file, &line);
3905 fprintf (stderr, "%s:%u: ", file, line);
3907 fprintf (stderr, "%s: ", file);
3909 fprintf (stderr, _("Info: "));
3910 va_start (args, format);
3911 vfprintf (stderr, format, args);
3913 (void) putc ('\n', stderr);
3916 /* Output one operand error record. */
3919 output_operand_error_record (const operand_error_record *record, char *str)
3921 int idx = record->detail.index;
3922 const aarch64_opcode *opcode = record->opcode;
3923 enum aarch64_opnd opd_code = (idx != -1 ? opcode->operands[idx]
3924 : AARCH64_OPND_NIL);
3925 const aarch64_operand_error *detail = &record->detail;
3927 switch (detail->kind)
3929 case AARCH64_OPDE_NIL:
3933 case AARCH64_OPDE_SYNTAX_ERROR:
3934 case AARCH64_OPDE_RECOVERABLE:
3935 case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
3936 case AARCH64_OPDE_OTHER_ERROR:
3937 gas_assert (idx >= 0);
3938 /* Use the prepared error message if there is, otherwise use the
3939 operand description string to describe the error. */
3940 if (detail->error != NULL)
3942 if (detail->index == -1)
3943 as_bad (_("%s -- `%s'"), detail->error, str);
3945 as_bad (_("%s at operand %d -- `%s'"),
3946 detail->error, detail->index + 1, str);
3949 as_bad (_("operand %d should be %s -- `%s'"), idx + 1,
3950 aarch64_get_operand_desc (opd_code), str);
3953 case AARCH64_OPDE_INVALID_VARIANT:
3954 as_bad (_("operand mismatch -- `%s'"), str);
3955 if (verbose_error_p)
3957 /* We will try to correct the erroneous instruction and also provide
3958 more information e.g. all other valid variants.
3960 The string representation of the corrected instruction and other
3961 valid variants are generated by
3963 1) obtaining the intermediate representation of the erroneous
3965 2) manipulating the IR, e.g. replacing the operand qualifier;
3966 3) printing out the instruction by calling the printer functions
3967 shared with the disassembler.
3969 The limitation of this method is that the exact input assembly
3970 line cannot be accurately reproduced in some cases, for example an
3971 optional operand present in the actual assembly line will be
3972 omitted in the output; likewise for the optional syntax rules,
3973 e.g. the # before the immediate. Another limitation is that the
3974 assembly symbols and relocation operations in the assembly line
3975 currently cannot be printed out in the error report. Last but not
3976 least, when there is other error(s) co-exist with this error, the
3977 'corrected' instruction may be still incorrect, e.g. given
3978 'ldnp h0,h1,[x0,#6]!'
3979 this diagnosis will provide the version:
3980 'ldnp s0,s1,[x0,#6]!'
3981 which is still not right. */
3982 size_t len = strlen (get_mnemonic_name (str));
3985 const size_t size = 2048;
3987 aarch64_inst *inst_base = &inst.base;
3988 const aarch64_opnd_qualifier_seq_t *qualifiers_list;
3991 reset_aarch64_instruction (&inst);
3992 inst_base->opcode = opcode;
3994 /* Reset the error report so that there is no side effect on the
3995 following operand parsing. */
3996 init_operand_error_report ();
3999 result = parse_operands (str + len, opcode)
4000 && programmer_friendly_fixup (&inst);
4001 gas_assert (result);
4002 result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
4004 gas_assert (!result);
4006 /* Find the most matched qualifier sequence. */
4007 qlf_idx = find_best_match (inst_base, opcode->qualifiers_list);
4008 gas_assert (qlf_idx > -1);
4010 /* Assign the qualifiers. */
4011 assign_qualifier_sequence (inst_base,
4012 opcode->qualifiers_list[qlf_idx]);
4014 /* Print the hint. */
4015 output_info (_(" did you mean this?"));
4016 snprintf (buf, size, "\t%s", get_mnemonic_name (str));
4017 print_operands (buf, opcode, inst_base->operands);
4018 output_info (_(" %s"), buf);
4020 /* Print out other variant(s) if there is any. */
4022 !empty_qualifier_sequence_p (opcode->qualifiers_list[1]))
4023 output_info (_(" other valid variant(s):"));
4025 /* For each pattern. */
4026 qualifiers_list = opcode->qualifiers_list;
4027 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
4029 /* Most opcodes has much fewer patterns in the list.
4030 First NIL qualifier indicates the end in the list. */
4031 if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
4036 /* Mnemonics name. */
4037 snprintf (buf, size, "\t%s", get_mnemonic_name (str));
4039 /* Assign the qualifiers. */
4040 assign_qualifier_sequence (inst_base, *qualifiers_list);
4042 /* Print instruction. */
4043 print_operands (buf, opcode, inst_base->operands);
4045 output_info (_(" %s"), buf);
4051 case AARCH64_OPDE_OUT_OF_RANGE:
4052 if (detail->data[0] != detail->data[1])
4053 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4054 detail->error ? detail->error : _("immediate value"),
4055 detail->data[0], detail->data[1], detail->index + 1, str);
4057 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4058 detail->error ? detail->error : _("immediate value"),
4059 detail->data[0], detail->index + 1, str);
4062 case AARCH64_OPDE_REG_LIST:
4063 if (detail->data[0] == 1)
4064 as_bad (_("invalid number of registers in the list; "
4065 "only 1 register is expected at operand %d -- `%s'"),
4066 detail->index + 1, str);
4068 as_bad (_("invalid number of registers in the list; "
4069 "%d registers are expected at operand %d -- `%s'"),
4070 detail->data[0], detail->index + 1, str);
4073 case AARCH64_OPDE_UNALIGNED:
4074 as_bad (_("immediate value should be a multiple of "
4075 "%d at operand %d -- `%s'"),
4076 detail->data[0], detail->index + 1, str);
4085 /* Process and output the error message about the operand mismatching.
4087 When this function is called, the operand error information had
4088 been collected for an assembly line and there will be multiple
4089 errors in the case of mulitple instruction templates; output the
4090 error message that most closely describes the problem. */
4093 output_operand_error_report (char *str)
4095 int largest_error_pos;
4096 const char *msg = NULL;
4097 enum aarch64_operand_error_kind kind;
4098 operand_error_record *curr;
4099 operand_error_record *head = operand_error_report.head;
4100 operand_error_record *record = NULL;
4102 /* No error to report. */
4106 gas_assert (head != NULL && operand_error_report.tail != NULL);
4108 /* Only one error. */
4109 if (head == operand_error_report.tail)
4111 DEBUG_TRACE ("single opcode entry with error kind: %s",
4112 operand_mismatch_kind_names[head->detail.kind]);
4113 output_operand_error_record (head, str);
4117 /* Find the error kind of the highest severity. */
4118 DEBUG_TRACE ("multiple opcode entres with error kind");
4119 kind = AARCH64_OPDE_NIL;
4120 for (curr = head; curr != NULL; curr = curr->next)
4122 gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
4123 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
4124 if (operand_error_higher_severity_p (curr->detail.kind, kind))
4125 kind = curr->detail.kind;
4127 gas_assert (kind != AARCH64_OPDE_NIL);
4129 /* Pick up one of errors of KIND to report. */
4130 largest_error_pos = -2; /* Index can be -1 which means unknown index. */
4131 for (curr = head; curr != NULL; curr = curr->next)
4133 if (curr->detail.kind != kind)
4135 /* If there are multiple errors, pick up the one with the highest
4136 mismatching operand index. In the case of multiple errors with
4137 the equally highest operand index, pick up the first one or the
4138 first one with non-NULL error message. */
4139 if (curr->detail.index > largest_error_pos
4140 || (curr->detail.index == largest_error_pos && msg == NULL
4141 && curr->detail.error != NULL))
4143 largest_error_pos = curr->detail.index;
4145 msg = record->detail.error;
4149 gas_assert (largest_error_pos != -2 && record != NULL);
4150 DEBUG_TRACE ("Pick up error kind %s to report",
4151 operand_mismatch_kind_names[record->detail.kind]);
4154 output_operand_error_record (record, str);
4157 /* Write an AARCH64 instruction to buf - always little-endian. */
4159 put_aarch64_insn (char *buf, uint32_t insn)
4161 unsigned char *where = (unsigned char *) buf;
4163 where[1] = insn >> 8;
4164 where[2] = insn >> 16;
4165 where[3] = insn >> 24;
4169 get_aarch64_insn (char *buf)
4171 unsigned char *where = (unsigned char *) buf;
4173 result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
4178 output_inst (struct aarch64_inst *new_inst)
4182 to = frag_more (INSN_SIZE);
4184 frag_now->tc_frag_data.recorded = 1;
4186 put_aarch64_insn (to, inst.base.value);
4188 if (inst.reloc.type != BFD_RELOC_UNUSED)
4190 fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal,
4191 INSN_SIZE, &inst.reloc.exp,
4194 DEBUG_TRACE ("Prepared relocation fix up");
4195 /* Don't check the addend value against the instruction size,
4196 that's the job of our code in md_apply_fix(). */
4197 fixp->fx_no_overflow = 1;
4198 if (new_inst != NULL)
4199 fixp->tc_fix_data.inst = new_inst;
4200 if (aarch64_gas_internal_fixup_p ())
4202 gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL);
4203 fixp->tc_fix_data.opnd = inst.reloc.opnd;
4204 fixp->fx_addnumber = inst.reloc.flags;
4208 dwarf2_emit_insn (INSN_SIZE);
4211 /* Link together opcodes of the same name. */
4215 aarch64_opcode *opcode;
4216 struct templates *next;
4219 typedef struct templates templates;
4222 lookup_mnemonic (const char *start, int len)
4224 templates *templ = NULL;
4226 templ = hash_find_n (aarch64_ops_hsh, start, len);
4230 /* Subroutine of md_assemble, responsible for looking up the primary
4231 opcode from the mnemonic the user wrote. STR points to the
4232 beginning of the mnemonic. */
4235 opcode_lookup (char **str)
4238 const aarch64_cond *cond;
4242 /* Scan up to the end of the mnemonic, which must end in white space,
4243 '.', or end of string. */
4244 for (base = end = *str; is_part_of_name(*end); end++)
4251 inst.cond = COND_ALWAYS;
4253 /* Handle a possible condition. */
4256 cond = hash_find_n (aarch64_cond_hsh, end + 1, 2);
4259 inst.cond = cond->value;
4273 if (inst.cond == COND_ALWAYS)
4275 /* Look for unaffixed mnemonic. */
4276 return lookup_mnemonic (base, len);
4280 /* append ".c" to mnemonic if conditional */
4281 memcpy (condname, base, len);
4282 memcpy (condname + len, ".c", 2);
4285 return lookup_mnemonic (base, len);
4291 /* Internal helper routine converting a vector neon_type_el structure
4292 *VECTYPE to a corresponding operand qualifier. */
4294 static inline aarch64_opnd_qualifier_t
4295 vectype_to_qualifier (const struct neon_type_el *vectype)
4297 /* Element size in bytes indexed by neon_el_type. */
4298 const unsigned char ele_size[5]
4301 if (!vectype->defined || vectype->type == NT_invtype)
4302 goto vectype_conversion_fail;
4304 gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
4306 if (vectype->defined & NTA_HASINDEX)
4307 /* Vector element register. */
4308 return AARCH64_OPND_QLF_S_B + vectype->type;
4311 /* Vector register. */
4312 int reg_size = ele_size[vectype->type] * vectype->width;
4314 if (reg_size != 16 && reg_size != 8)
4315 goto vectype_conversion_fail;
4316 /* The conversion is calculated based on the relation of the order of
4317 qualifiers to the vector element size and vector register size. */
4318 offset = (vectype->type == NT_q)
4319 ? 8 : (vectype->type << 1) + (reg_size >> 4);
4320 gas_assert (offset <= 8);
4321 return AARCH64_OPND_QLF_V_8B + offset;
4324 vectype_conversion_fail:
4325 first_error (_("bad vector arrangement type"));
4326 return AARCH64_OPND_QLF_NIL;
4329 /* Process an optional operand that is found omitted from the assembly line.
4330 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4331 instruction's opcode entry while IDX is the index of this omitted operand.
4335 process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
4336 int idx, aarch64_opnd_info *operand)
4338 aarch64_insn default_value = get_optional_operand_default_value (opcode);
4339 gas_assert (optional_operand_p (opcode, idx));
4340 gas_assert (!operand->present);
4344 case AARCH64_OPND_Rd:
4345 case AARCH64_OPND_Rn:
4346 case AARCH64_OPND_Rm:
4347 case AARCH64_OPND_Rt:
4348 case AARCH64_OPND_Rt2:
4349 case AARCH64_OPND_Rs:
4350 case AARCH64_OPND_Ra:
4351 case AARCH64_OPND_Rt_SYS:
4352 case AARCH64_OPND_Rd_SP:
4353 case AARCH64_OPND_Rn_SP:
4354 case AARCH64_OPND_Fd:
4355 case AARCH64_OPND_Fn:
4356 case AARCH64_OPND_Fm:
4357 case AARCH64_OPND_Fa:
4358 case AARCH64_OPND_Ft:
4359 case AARCH64_OPND_Ft2:
4360 case AARCH64_OPND_Sd:
4361 case AARCH64_OPND_Sn:
4362 case AARCH64_OPND_Sm:
4363 case AARCH64_OPND_Vd:
4364 case AARCH64_OPND_Vn:
4365 case AARCH64_OPND_Vm:
4366 case AARCH64_OPND_VdD1:
4367 case AARCH64_OPND_VnD1:
4368 operand->reg.regno = default_value;
4371 case AARCH64_OPND_Ed:
4372 case AARCH64_OPND_En:
4373 case AARCH64_OPND_Em:
4374 operand->reglane.regno = default_value;
4377 case AARCH64_OPND_IDX:
4378 case AARCH64_OPND_BIT_NUM:
4379 case AARCH64_OPND_IMMR:
4380 case AARCH64_OPND_IMMS:
4381 case AARCH64_OPND_SHLL_IMM:
4382 case AARCH64_OPND_IMM_VLSL:
4383 case AARCH64_OPND_IMM_VLSR:
4384 case AARCH64_OPND_CCMP_IMM:
4385 case AARCH64_OPND_FBITS:
4386 case AARCH64_OPND_UIMM4:
4387 case AARCH64_OPND_UIMM3_OP1:
4388 case AARCH64_OPND_UIMM3_OP2:
4389 case AARCH64_OPND_IMM:
4390 case AARCH64_OPND_WIDTH:
4391 case AARCH64_OPND_UIMM7:
4392 case AARCH64_OPND_NZCV:
4393 operand->imm.value = default_value;
4396 case AARCH64_OPND_EXCEPTION:
4397 inst.reloc.type = BFD_RELOC_UNUSED;
4400 case AARCH64_OPND_BARRIER_ISB:
4401 operand->barrier = aarch64_barrier_options + default_value;
4408 /* Process the relocation type for move wide instructions.
4409 Return TRUE on success; otherwise return FALSE. */
4412 process_movw_reloc_info (void)
4417 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
4419 if (inst.base.opcode->op == OP_MOVK)
4420 switch (inst.reloc.type)
4422 case BFD_RELOC_AARCH64_MOVW_G0_S:
4423 case BFD_RELOC_AARCH64_MOVW_G1_S:
4424 case BFD_RELOC_AARCH64_MOVW_G2_S:
4425 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4426 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4427 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4428 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4429 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4431 (_("the specified relocation type is not allowed for MOVK"));
4437 switch (inst.reloc.type)
4439 case BFD_RELOC_AARCH64_MOVW_G0:
4440 case BFD_RELOC_AARCH64_MOVW_G0_S:
4441 case BFD_RELOC_AARCH64_MOVW_G0_NC:
4442 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4443 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4446 case BFD_RELOC_AARCH64_MOVW_G1:
4447 case BFD_RELOC_AARCH64_MOVW_G1_S:
4448 case BFD_RELOC_AARCH64_MOVW_G1_NC:
4449 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4450 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4453 case BFD_RELOC_AARCH64_MOVW_G2:
4454 case BFD_RELOC_AARCH64_MOVW_G2_S:
4455 case BFD_RELOC_AARCH64_MOVW_G2_NC:
4456 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4459 set_fatal_syntax_error
4460 (_("the specified relocation type is not allowed for 32-bit "
4466 case BFD_RELOC_AARCH64_MOVW_G3:
4469 set_fatal_syntax_error
4470 (_("the specified relocation type is not allowed for 32-bit "
4477 /* More cases should be added when more MOVW-related relocation types
4478 are supported in GAS. */
4479 gas_assert (aarch64_gas_internal_fixup_p ());
4480 /* The shift amount should have already been set by the parser. */
4483 inst.base.operands[1].shifter.amount = shift;
4487 /* A primitive log caculator. */
4489 static inline unsigned int
4490 get_logsz (unsigned int size)
4492 const unsigned char ls[16] =
4493 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4499 gas_assert (ls[size - 1] != (unsigned char)-1);
4500 return ls[size - 1];
4503 /* Determine and return the real reloc type code for an instruction
4504 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4506 static inline bfd_reloc_code_real_type
4507 ldst_lo12_determine_real_reloc_type (void)
4510 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
4511 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
4513 const bfd_reloc_code_real_type reloc_ldst_lo12[5] = {
4514 BFD_RELOC_AARCH64_LDST8_LO12, BFD_RELOC_AARCH64_LDST16_LO12,
4515 BFD_RELOC_AARCH64_LDST32_LO12, BFD_RELOC_AARCH64_LDST64_LO12,
4516 BFD_RELOC_AARCH64_LDST128_LO12
4519 gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12);
4520 gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
4522 if (opd1_qlf == AARCH64_OPND_QLF_NIL)
4524 aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list,
4526 gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
4528 logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
4529 gas_assert (logsz >= 0 && logsz <= 4);
4531 return reloc_ldst_lo12[logsz];
4534 /* Check whether a register list REGINFO is valid. The registers must be
4535 numbered in increasing order (modulo 32), in increments of one or two.
4537 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4540 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4543 reg_list_valid_p (uint32_t reginfo, int accept_alternate)
4545 uint32_t i, nb_regs, prev_regno, incr;
4547 nb_regs = 1 + (reginfo & 0x3);
4549 prev_regno = reginfo & 0x1f;
4550 incr = accept_alternate ? 2 : 1;
4552 for (i = 1; i < nb_regs; ++i)
4554 uint32_t curr_regno;
4556 curr_regno = reginfo & 0x1f;
4557 if (curr_regno != ((prev_regno + incr) & 0x1f))
4559 prev_regno = curr_regno;
4565 /* Generic instruction operand parser. This does no encoding and no
4566 semantic validation; it merely squirrels values away in the inst
4567 structure. Returns TRUE or FALSE depending on whether the
4568 specified grammar matched. */
4571 parse_operands (char *str, const aarch64_opcode *opcode)
4574 char *backtrack_pos = 0;
4575 const enum aarch64_opnd *operands = opcode->operands;
4578 skip_whitespace (str);
4580 for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
4583 int isreg32, isregzero;
4584 int comma_skipped_p = 0;
4585 aarch64_reg_type rtype;
4586 struct neon_type_el vectype;
4587 aarch64_opnd_info *info = &inst.base.operands[i];
4589 DEBUG_TRACE ("parse operand %d", i);
4591 /* Assign the operand code. */
4592 info->type = operands[i];
4594 if (optional_operand_p (opcode, i))
4596 /* Remember where we are in case we need to backtrack. */
4597 gas_assert (!backtrack_pos);
4598 backtrack_pos = str;
4601 /* Expect comma between operands; the backtrack mechanizm will take
4602 care of cases of omitted optional operand. */
4603 if (i > 0 && ! skip_past_char (&str, ','))
4605 set_syntax_error (_("comma expected between operands"));
4609 comma_skipped_p = 1;
4611 switch (operands[i])
4613 case AARCH64_OPND_Rd:
4614 case AARCH64_OPND_Rn:
4615 case AARCH64_OPND_Rm:
4616 case AARCH64_OPND_Rt:
4617 case AARCH64_OPND_Rt2:
4618 case AARCH64_OPND_Rs:
4619 case AARCH64_OPND_Ra:
4620 case AARCH64_OPND_Rt_SYS:
4621 po_int_reg_or_fail (1, 0);
4624 case AARCH64_OPND_Rd_SP:
4625 case AARCH64_OPND_Rn_SP:
4626 po_int_reg_or_fail (0, 1);
4629 case AARCH64_OPND_Rm_EXT:
4630 case AARCH64_OPND_Rm_SFT:
4631 po_misc_or_fail (parse_shifter_operand
4632 (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT
4634 : SHIFTED_LOGIC_IMM)));
4635 if (!info->shifter.operator_present)
4637 /* Default to LSL if not present. Libopcodes prefers shifter
4638 kind to be explicit. */
4639 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4640 info->shifter.kind = AARCH64_MOD_LSL;
4641 /* For Rm_EXT, libopcodes will carry out further check on whether
4642 or not stack pointer is used in the instruction (Recall that
4643 "the extend operator is not optional unless at least one of
4644 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4648 case AARCH64_OPND_Fd:
4649 case AARCH64_OPND_Fn:
4650 case AARCH64_OPND_Fm:
4651 case AARCH64_OPND_Fa:
4652 case AARCH64_OPND_Ft:
4653 case AARCH64_OPND_Ft2:
4654 case AARCH64_OPND_Sd:
4655 case AARCH64_OPND_Sn:
4656 case AARCH64_OPND_Sm:
4657 val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
4658 if (val == PARSE_FAIL)
4660 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
4663 gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
4665 info->reg.regno = val;
4666 info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
4669 case AARCH64_OPND_Vd:
4670 case AARCH64_OPND_Vn:
4671 case AARCH64_OPND_Vm:
4672 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4673 if (val == PARSE_FAIL)
4675 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4678 if (vectype.defined & NTA_HASINDEX)
4681 info->reg.regno = val;
4682 info->qualifier = vectype_to_qualifier (&vectype);
4683 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4687 case AARCH64_OPND_VdD1:
4688 case AARCH64_OPND_VnD1:
4689 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4690 if (val == PARSE_FAIL)
4692 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4695 if (vectype.type != NT_d || vectype.index != 1)
4697 set_fatal_syntax_error
4698 (_("the top half of a 128-bit FP/SIMD register is expected"));
4701 info->reg.regno = val;
4702 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4703 here; it is correct for the purpose of encoding/decoding since
4704 only the register number is explicitly encoded in the related
4705 instructions, although this appears a bit hacky. */
4706 info->qualifier = AARCH64_OPND_QLF_S_D;
4709 case AARCH64_OPND_Ed:
4710 case AARCH64_OPND_En:
4711 case AARCH64_OPND_Em:
4712 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4713 if (val == PARSE_FAIL)
4715 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4718 if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
4721 info->reglane.regno = val;
4722 info->reglane.index = vectype.index;
4723 info->qualifier = vectype_to_qualifier (&vectype);
4724 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4728 case AARCH64_OPND_LVn:
4729 case AARCH64_OPND_LVt:
4730 case AARCH64_OPND_LVt_AL:
4731 case AARCH64_OPND_LEt:
4732 if ((val = parse_neon_reg_list (&str, &vectype)) == PARSE_FAIL)
4734 if (! reg_list_valid_p (val, /* accept_alternate */ 0))
4736 set_fatal_syntax_error (_("invalid register list"));
4739 info->reglist.first_regno = (val >> 2) & 0x1f;
4740 info->reglist.num_regs = (val & 0x3) + 1;
4741 if (operands[i] == AARCH64_OPND_LEt)
4743 if (!(vectype.defined & NTA_HASINDEX))
4745 info->reglist.has_index = 1;
4746 info->reglist.index = vectype.index;
4748 else if (!(vectype.defined & NTA_HASTYPE))
4750 info->qualifier = vectype_to_qualifier (&vectype);
4751 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4755 case AARCH64_OPND_Cn:
4756 case AARCH64_OPND_Cm:
4757 po_reg_or_fail (REG_TYPE_CN);
4760 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN)));
4763 inst.base.operands[i].reg.regno = val;
4766 case AARCH64_OPND_SHLL_IMM:
4767 case AARCH64_OPND_IMM_VLSR:
4768 po_imm_or_fail (1, 64);
4769 info->imm.value = val;
4772 case AARCH64_OPND_CCMP_IMM:
4773 case AARCH64_OPND_FBITS:
4774 case AARCH64_OPND_UIMM4:
4775 case AARCH64_OPND_UIMM3_OP1:
4776 case AARCH64_OPND_UIMM3_OP2:
4777 case AARCH64_OPND_IMM_VLSL:
4778 case AARCH64_OPND_IMM:
4779 case AARCH64_OPND_WIDTH:
4780 po_imm_nc_or_fail ();
4781 info->imm.value = val;
4784 case AARCH64_OPND_UIMM7:
4785 po_imm_or_fail (0, 127);
4786 info->imm.value = val;
4789 case AARCH64_OPND_IDX:
4790 case AARCH64_OPND_BIT_NUM:
4791 case AARCH64_OPND_IMMR:
4792 case AARCH64_OPND_IMMS:
4793 po_imm_or_fail (0, 63);
4794 info->imm.value = val;
4797 case AARCH64_OPND_IMM0:
4798 po_imm_nc_or_fail ();
4801 set_fatal_syntax_error (_("immediate zero expected"));
4804 info->imm.value = 0;
4807 case AARCH64_OPND_FPIMM0:
4810 bfd_boolean res1 = FALSE, res2 = FALSE;
4811 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4812 it is probably not worth the effort to support it. */
4813 if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE))
4814 && !(res2 = parse_constant_immediate (&str, &val)))
4816 if ((res1 && qfloat == 0) || (res2 && val == 0))
4818 info->imm.value = 0;
4819 info->imm.is_fp = 1;
4822 set_fatal_syntax_error (_("immediate zero expected"));
4826 case AARCH64_OPND_IMM_MOV:
4829 if (reg_name_p (str, REG_TYPE_R_Z_SP) ||
4830 reg_name_p (str, REG_TYPE_VN))
4833 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
4835 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4836 later. fix_mov_imm_insn will try to determine a machine
4837 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4838 message if the immediate cannot be moved by a single
4840 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
4841 inst.base.operands[i].skip = 1;
4845 case AARCH64_OPND_SIMD_IMM:
4846 case AARCH64_OPND_SIMD_IMM_SFT:
4847 if (! parse_big_immediate (&str, &val))
4849 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4851 /* need_libopcodes_p */ 1,
4854 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4855 shift, we don't check it here; we leave the checking to
4856 the libopcodes (operand_general_constraint_met_p). By
4857 doing this, we achieve better diagnostics. */
4858 if (skip_past_comma (&str)
4859 && ! parse_shift (&str, info, SHIFTED_LSL_MSL))
4861 if (!info->shifter.operator_present
4862 && info->type == AARCH64_OPND_SIMD_IMM_SFT)
4864 /* Default to LSL if not present. Libopcodes prefers shifter
4865 kind to be explicit. */
4866 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4867 info->shifter.kind = AARCH64_MOD_LSL;
4871 case AARCH64_OPND_FPIMM:
4872 case AARCH64_OPND_SIMD_FPIMM:
4876 = (aarch64_get_qualifier_esize (inst.base.operands[0].qualifier)
4878 if (! parse_aarch64_imm_float (&str, &qfloat, dp_p))
4882 set_fatal_syntax_error (_("invalid floating-point constant"));
4885 inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat);
4886 inst.base.operands[i].imm.is_fp = 1;
4890 case AARCH64_OPND_LIMM:
4891 po_misc_or_fail (parse_shifter_operand (&str, info,
4892 SHIFTED_LOGIC_IMM));
4893 if (info->shifter.operator_present)
4895 set_fatal_syntax_error
4896 (_("shift not allowed for bitmask immediate"));
4899 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4901 /* need_libopcodes_p */ 1,
4905 case AARCH64_OPND_AIMM:
4906 if (opcode->op == OP_ADD)
4907 /* ADD may have relocation types. */
4908 po_misc_or_fail (parse_shifter_operand_reloc (&str, info,
4909 SHIFTED_ARITH_IMM));
4911 po_misc_or_fail (parse_shifter_operand (&str, info,
4912 SHIFTED_ARITH_IMM));
4913 switch (inst.reloc.type)
4915 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
4916 info->shifter.amount = 12;
4918 case BFD_RELOC_UNUSED:
4919 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
4920 if (info->shifter.kind != AARCH64_MOD_NONE)
4921 inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT;
4922 inst.reloc.pc_rel = 0;
4927 info->imm.value = 0;
4928 if (!info->shifter.operator_present)
4930 /* Default to LSL if not present. Libopcodes prefers shifter
4931 kind to be explicit. */
4932 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4933 info->shifter.kind = AARCH64_MOD_LSL;
4937 case AARCH64_OPND_HALF:
4939 /* #<imm16> or relocation. */
4940 int internal_fixup_p;
4941 po_misc_or_fail (parse_half (&str, &internal_fixup_p));
4942 if (internal_fixup_p)
4943 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
4944 skip_whitespace (str);
4945 if (skip_past_comma (&str))
4947 /* {, LSL #<shift>} */
4948 if (! aarch64_gas_internal_fixup_p ())
4950 set_fatal_syntax_error (_("can't mix relocation modifier "
4951 "with explicit shift"));
4954 po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
4957 inst.base.operands[i].shifter.amount = 0;
4958 inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
4959 inst.base.operands[i].imm.value = 0;
4960 if (! process_movw_reloc_info ())
4965 case AARCH64_OPND_EXCEPTION:
4966 po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp));
4967 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4969 /* need_libopcodes_p */ 0,
4973 case AARCH64_OPND_NZCV:
4975 const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4);
4979 info->imm.value = nzcv->value;
4982 po_imm_or_fail (0, 15);
4983 info->imm.value = val;
4987 case AARCH64_OPND_COND:
4988 case AARCH64_OPND_COND1:
4989 info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
4991 if (info->cond == NULL)
4993 set_syntax_error (_("invalid condition"));
4996 else if (operands[i] == AARCH64_OPND_COND1
4997 && (info->cond->value & 0xe) == 0xe)
4999 /* Not allow AL or NV. */
5000 set_default_error ();
5005 case AARCH64_OPND_ADDR_ADRP:
5006 po_misc_or_fail (parse_adrp (&str));
5007 /* Clear the value as operand needs to be relocated. */
5008 info->imm.value = 0;
5011 case AARCH64_OPND_ADDR_PCREL14:
5012 case AARCH64_OPND_ADDR_PCREL19:
5013 case AARCH64_OPND_ADDR_PCREL21:
5014 case AARCH64_OPND_ADDR_PCREL26:
5015 po_misc_or_fail (parse_address_reloc (&str, info));
5016 if (!info->addr.pcrel)
5018 set_syntax_error (_("invalid pc-relative address"));
5021 if (inst.gen_lit_pool
5022 && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT))
5024 /* Only permit "=value" in the literal load instructions.
5025 The literal will be generated by programmer_friendly_fixup. */
5026 set_syntax_error (_("invalid use of \"=immediate\""));
5029 if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str))
5031 set_syntax_error (_("unrecognized relocation suffix"));
5034 if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
5036 info->imm.value = inst.reloc.exp.X_add_number;
5037 inst.reloc.type = BFD_RELOC_UNUSED;
5041 info->imm.value = 0;
5042 if (inst.reloc.type == BFD_RELOC_UNUSED)
5043 switch (opcode->iclass)
5047 /* e.g. CBZ or B.COND */
5048 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5049 inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
5053 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
5054 inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
5058 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
5060 (opcode->op == OP_BL) ? BFD_RELOC_AARCH64_CALL26
5061 : BFD_RELOC_AARCH64_JUMP26;
5064 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
5065 inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
5068 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
5069 inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
5075 inst.reloc.pc_rel = 1;
5079 case AARCH64_OPND_ADDR_SIMPLE:
5080 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
5081 /* [<Xn|SP>{, #<simm>}] */
5082 po_char_or_fail ('[');
5083 po_reg_or_fail (REG_TYPE_R64_SP);
5084 /* Accept optional ", #0". */
5085 if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
5086 && skip_past_char (&str, ','))
5088 skip_past_char (&str, '#');
5089 if (! skip_past_char (&str, '0'))
5091 set_fatal_syntax_error
5092 (_("the optional immediate offset can only be 0"));
5096 po_char_or_fail (']');
5097 info->addr.base_regno = val;
5100 case AARCH64_OPND_ADDR_REGOFF:
5101 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5102 po_misc_or_fail (parse_address (&str, info, 0));
5103 if (info->addr.pcrel || !info->addr.offset.is_reg
5104 || !info->addr.preind || info->addr.postind
5105 || info->addr.writeback)
5107 set_syntax_error (_("invalid addressing mode"));
5110 if (!info->shifter.operator_present)
5112 /* Default to LSL if not present. Libopcodes prefers shifter
5113 kind to be explicit. */
5114 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5115 info->shifter.kind = AARCH64_MOD_LSL;
5117 /* Qualifier to be deduced by libopcodes. */
5120 case AARCH64_OPND_ADDR_SIMM7:
5121 po_misc_or_fail (parse_address (&str, info, 0));
5122 if (info->addr.pcrel || info->addr.offset.is_reg
5123 || (!info->addr.preind && !info->addr.postind))
5125 set_syntax_error (_("invalid addressing mode"));
5128 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5130 /* need_libopcodes_p */ 1,
5134 case AARCH64_OPND_ADDR_SIMM9:
5135 case AARCH64_OPND_ADDR_SIMM9_2:
5136 po_misc_or_fail (parse_address_reloc (&str, info));
5137 if (info->addr.pcrel || info->addr.offset.is_reg
5138 || (!info->addr.preind && !info->addr.postind)
5139 || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
5140 && info->addr.writeback))
5142 set_syntax_error (_("invalid addressing mode"));
5145 if (inst.reloc.type != BFD_RELOC_UNUSED)
5147 set_syntax_error (_("relocation not allowed"));
5150 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5152 /* need_libopcodes_p */ 1,
5156 case AARCH64_OPND_ADDR_UIMM12:
5157 po_misc_or_fail (parse_address_reloc (&str, info));
5158 if (info->addr.pcrel || info->addr.offset.is_reg
5159 || !info->addr.preind || info->addr.writeback)
5161 set_syntax_error (_("invalid addressing mode"));
5164 if (inst.reloc.type == BFD_RELOC_UNUSED)
5165 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5166 else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12)
5167 inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
5168 /* Leave qualifier to be determined by libopcodes. */
5171 case AARCH64_OPND_SIMD_ADDR_POST:
5172 /* [<Xn|SP>], <Xm|#<amount>> */
5173 po_misc_or_fail (parse_address (&str, info, 1));
5174 if (!info->addr.postind || !info->addr.writeback)
5176 set_syntax_error (_("invalid addressing mode"));
5179 if (!info->addr.offset.is_reg)
5181 if (inst.reloc.exp.X_op == O_constant)
5182 info->addr.offset.imm = inst.reloc.exp.X_add_number;
5185 set_fatal_syntax_error
5186 (_("writeback value should be an immediate constant"));
5193 case AARCH64_OPND_SYSREG:
5195 const aarch64_sys_reg *sys_reg = NULL;
5196 if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1,
5200 set_syntax_error (_("unknown or missing system register name"));
5203 else if (sys_reg && i == 0 && aarch64_sys_reg_readonly_p (sys_reg))
5205 set_other_error (_("read-only register"));
5208 else if (sys_reg && i == 1 && aarch64_sys_reg_writeonly_p (sys_reg))
5210 set_other_error (_("write-only register"));
5213 inst.base.operands[i].sysreg = val;
5217 case AARCH64_OPND_PSTATEFIELD:
5218 if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, NULL))
5221 set_syntax_error (_("unknown or missing PSTATE field name"));
5224 inst.base.operands[i].pstatefield = val;
5227 case AARCH64_OPND_SYSREG_IC:
5228 inst.base.operands[i].sysins_op =
5229 parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
5231 case AARCH64_OPND_SYSREG_DC:
5232 inst.base.operands[i].sysins_op =
5233 parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
5235 case AARCH64_OPND_SYSREG_AT:
5236 inst.base.operands[i].sysins_op =
5237 parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
5239 case AARCH64_OPND_SYSREG_TLBI:
5240 inst.base.operands[i].sysins_op =
5241 parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
5243 if (inst.base.operands[i].sysins_op == NULL)
5245 set_fatal_syntax_error ( _("unknown or missing operation name"));
5250 case AARCH64_OPND_BARRIER:
5251 case AARCH64_OPND_BARRIER_ISB:
5252 val = parse_barrier (&str);
5253 if (val != PARSE_FAIL
5254 && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf)
5256 /* ISB only accepts options name 'sy'. */
5258 (_("the specified option is not accepted in ISB"));
5259 /* Turn off backtrack as this optional operand is present. */
5263 /* This is an extension to accept a 0..15 immediate. */
5264 if (val == PARSE_FAIL)
5265 po_imm_or_fail (0, 15);
5266 info->barrier = aarch64_barrier_options + val;
5269 case AARCH64_OPND_PRFOP:
5270 val = parse_pldop (&str);
5271 /* This is an extension to accept a 0..31 immediate. */
5272 if (val == PARSE_FAIL)
5273 po_imm_or_fail (0, 31);
5274 inst.base.operands[i].prfop = aarch64_prfops + val;
5278 as_fatal (_("unhandled operand code %d"), operands[i]);
5281 /* If we get here, this operand was successfully parsed. */
5282 inst.base.operands[i].present = 1;
5286 /* The parse routine should already have set the error, but in case
5287 not, set a default one here. */
5289 set_default_error ();
5291 if (! backtrack_pos)
5292 goto parse_operands_return;
5294 /* Reaching here means we are dealing with an optional operand that is
5295 omitted from the assembly line. */
5296 gas_assert (optional_operand_p (opcode, i));
5298 process_omitted_operand (operands[i], opcode, i, info);
5300 /* Try again, skipping the optional operand at backtrack_pos. */
5301 str = backtrack_pos;
5304 /* If this is the last operand that is optional and omitted, but without
5305 the presence of a comma. */
5306 if (i && comma_skipped_p && i == aarch64_num_of_operands (opcode) - 1)
5308 set_fatal_syntax_error
5309 (_("unexpected comma before the omitted optional operand"));
5310 goto parse_operands_return;
5313 /* Clear any error record after the omitted optional operand has been
5314 successfully handled. */
5318 /* Check if we have parsed all the operands. */
5319 if (*str != '\0' && ! error_p ())
5321 /* Set I to the index of the last present operand; this is
5322 for the purpose of diagnostics. */
5323 for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i)
5325 set_fatal_syntax_error
5326 (_("unexpected characters following instruction"));
5329 parse_operands_return:
5333 DEBUG_TRACE ("parsing FAIL: %s - %s",
5334 operand_mismatch_kind_names[get_error_kind ()],
5335 get_error_message ());
5336 /* Record the operand error properly; this is useful when there
5337 are multiple instruction templates for a mnemonic name, so that
5338 later on, we can select the error that most closely describes
5340 record_operand_error (opcode, i, get_error_kind (),
5341 get_error_message ());
5346 DEBUG_TRACE ("parsing SUCCESS");
5351 /* It does some fix-up to provide some programmer friendly feature while
5352 keeping the libopcodes happy, i.e. libopcodes only accepts
5353 the preferred architectural syntax.
5354 Return FALSE if there is any failure; otherwise return TRUE. */
5357 programmer_friendly_fixup (aarch64_instruction *instr)
5359 aarch64_inst *base = &instr->base;
5360 const aarch64_opcode *opcode = base->opcode;
5361 enum aarch64_op op = opcode->op;
5362 aarch64_opnd_info *operands = base->operands;
5364 DEBUG_TRACE ("enter");
5366 switch (opcode->iclass)
5369 /* TBNZ Xn|Wn, #uimm6, label
5370 Test and Branch Not Zero: conditionally jumps to label if bit number
5371 uimm6 in register Xn is not zero. The bit number implies the width of
5372 the register, which may be written and should be disassembled as Wn if
5373 uimm is less than 32. */
5374 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
5376 if (operands[1].imm.value >= 32)
5378 record_operand_out_of_range_error (opcode, 1, _("immediate value"),
5382 operands[0].qualifier = AARCH64_OPND_QLF_X;
5386 /* LDR Wt, label | =value
5387 As a convenience assemblers will typically permit the notation
5388 "=value" in conjunction with the pc-relative literal load instructions
5389 to automatically place an immediate value or symbolic address in a
5390 nearby literal pool and generate a hidden label which references it.
5391 ISREG has been set to 0 in the case of =value. */
5392 if (instr->gen_lit_pool
5393 && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT))
5395 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
5396 if (op == OP_LDRSW_LIT)
5398 if (instr->reloc.exp.X_op != O_constant
5399 && instr->reloc.exp.X_op != O_big
5400 && instr->reloc.exp.X_op != O_symbol)
5402 record_operand_error (opcode, 1,
5403 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
5404 _("constant expression expected"));
5407 if (! add_to_lit_pool (&instr->reloc.exp, size))
5409 record_operand_error (opcode, 1,
5410 AARCH64_OPDE_OTHER_ERROR,
5411 _("literal pool insertion failed"));
5419 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5420 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5421 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5422 A programmer-friendly assembler should accept a destination Xd in
5423 place of Wd, however that is not the preferred form for disassembly.
5425 if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW)
5426 && operands[1].qualifier == AARCH64_OPND_QLF_W
5427 && operands[0].qualifier == AARCH64_OPND_QLF_X)
5428 operands[0].qualifier = AARCH64_OPND_QLF_W;
5433 /* In the 64-bit form, the final register operand is written as Wm
5434 for all but the (possibly omitted) UXTX/LSL and SXTX
5436 As a programmer-friendly assembler, we accept e.g.
5437 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5438 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5439 int idx = aarch64_operand_index (opcode->operands,
5440 AARCH64_OPND_Rm_EXT);
5441 gas_assert (idx == 1 || idx == 2);
5442 if (operands[0].qualifier == AARCH64_OPND_QLF_X
5443 && operands[idx].qualifier == AARCH64_OPND_QLF_X
5444 && operands[idx].shifter.kind != AARCH64_MOD_LSL
5445 && operands[idx].shifter.kind != AARCH64_MOD_UXTX
5446 && operands[idx].shifter.kind != AARCH64_MOD_SXTX)
5447 operands[idx].qualifier = AARCH64_OPND_QLF_W;
5455 DEBUG_TRACE ("exit with SUCCESS");
5459 /* A wrapper function to interface with libopcodes on encoding and
5460 record the error message if there is any.
5462 Return TRUE on success; otherwise return FALSE. */
5465 do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
5468 aarch64_operand_error error_info;
5469 error_info.kind = AARCH64_OPDE_NIL;
5470 if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
5474 gas_assert (error_info.kind != AARCH64_OPDE_NIL);
5475 record_operand_error_info (opcode, &error_info);
5480 #ifdef DEBUG_AARCH64
5482 dump_opcode_operands (const aarch64_opcode *opcode)
5485 while (opcode->operands[i] != AARCH64_OPND_NIL)
5487 aarch64_verbose ("\t\t opnd%d: %s", i,
5488 aarch64_get_operand_name (opcode->operands[i])[0] != '\0'
5489 ? aarch64_get_operand_name (opcode->operands[i])
5490 : aarch64_get_operand_desc (opcode->operands[i]));
5494 #endif /* DEBUG_AARCH64 */
5496 /* This is the guts of the machine-dependent assembler. STR points to a
5497 machine dependent instruction. This function is supposed to emit
5498 the frags/bytes it assembles to. */
5501 md_assemble (char *str)
5504 templates *template;
5505 aarch64_opcode *opcode;
5506 aarch64_inst *inst_base;
5507 unsigned saved_cond;
5509 /* Align the previous label if needed. */
5510 if (last_label_seen != NULL)
5512 symbol_set_frag (last_label_seen, frag_now);
5513 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
5514 S_SET_SEGMENT (last_label_seen, now_seg);
5517 inst.reloc.type = BFD_RELOC_UNUSED;
5519 DEBUG_TRACE ("\n\n");
5520 DEBUG_TRACE ("==============================");
5521 DEBUG_TRACE ("Enter md_assemble with %s", str);
5523 template = opcode_lookup (&p);
5526 /* It wasn't an instruction, but it might be a register alias of
5527 the form alias .req reg directive. */
5528 if (!create_register_alias (str, p))
5529 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
5534 skip_whitespace (p);
5537 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5538 get_mnemonic_name (str), str);
5542 init_operand_error_report ();
5544 saved_cond = inst.cond;
5545 reset_aarch64_instruction (&inst);
5546 inst.cond = saved_cond;
5548 /* Iterate through all opcode entries with the same mnemonic name. */
5551 opcode = template->opcode;
5553 DEBUG_TRACE ("opcode %s found", opcode->name);
5554 #ifdef DEBUG_AARCH64
5556 dump_opcode_operands (opcode);
5557 #endif /* DEBUG_AARCH64 */
5559 /* Check that this instruction is supported for this CPU. */
5560 if (!opcode->avariant
5561 || !AARCH64_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
5563 as_bad (_("selected processor does not support `%s'"), str);
5567 mapping_state (MAP_INSN);
5569 inst_base = &inst.base;
5570 inst_base->opcode = opcode;
5572 /* Truly conditionally executed instructions, e.g. b.cond. */
5573 if (opcode->flags & F_COND)
5575 gas_assert (inst.cond != COND_ALWAYS);
5576 inst_base->cond = get_cond_from_value (inst.cond);
5577 DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]);
5579 else if (inst.cond != COND_ALWAYS)
5581 /* It shouldn't arrive here, where the assembly looks like a
5582 conditional instruction but the found opcode is unconditional. */
5587 if (parse_operands (p, opcode)
5588 && programmer_friendly_fixup (&inst)
5589 && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
5591 if (inst.reloc.type == BFD_RELOC_UNUSED
5592 || !inst.reloc.need_libopcodes_p)
5596 /* If there is relocation generated for the instruction,
5597 store the instruction information for the future fix-up. */
5598 struct aarch64_inst *copy;
5599 gas_assert (inst.reloc.type != BFD_RELOC_UNUSED);
5600 if ((copy = xmalloc (sizeof (struct aarch64_inst))) == NULL)
5602 memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
5608 template = template->next;
5609 if (template != NULL)
5611 reset_aarch64_instruction (&inst);
5612 inst.cond = saved_cond;
5615 while (template != NULL);
5617 /* Issue the error messages if any. */
5618 output_operand_error_report (str);
5621 /* Various frobbings of labels and their addresses. */
5624 aarch64_start_line_hook (void)
5626 last_label_seen = NULL;
5630 aarch64_frob_label (symbolS * sym)
5632 last_label_seen = sym;
5634 dwarf2_emit_label (sym);
5638 aarch64_data_in_code (void)
5640 if (!strncmp (input_line_pointer + 1, "data:", 5))
5642 *input_line_pointer = '/';
5643 input_line_pointer += 5;
5644 *input_line_pointer = 0;
5652 aarch64_canonicalize_symbol_name (char *name)
5656 if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data"))
5657 *(name + len - 5) = 0;
5662 /* Table of all register names defined by default. The user can
5663 define additional names with .req. Note that all register names
5664 should appear in both upper and lowercase variants. Some registers
5665 also have mixed-case names. */
5667 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5668 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5669 #define REGSET31(p,t) \
5670 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5671 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5672 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5673 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5674 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5675 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5676 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5677 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5678 #define REGSET(p,t) \
5679 REGSET31(p,t), REGNUM(p,31,t)
5681 /* These go into aarch64_reg_hsh hash-table. */
5682 static const reg_entry reg_names[] = {
5683 /* Integer registers. */
5684 REGSET31 (x, R_64), REGSET31 (X, R_64),
5685 REGSET31 (w, R_32), REGSET31 (W, R_32),
5687 REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
5688 REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
5690 REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
5691 REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
5693 /* Coprocessor register numbers. */
5694 REGSET (c, CN), REGSET (C, CN),
5696 /* Floating-point single precision registers. */
5697 REGSET (s, FP_S), REGSET (S, FP_S),
5699 /* Floating-point double precision registers. */
5700 REGSET (d, FP_D), REGSET (D, FP_D),
5702 /* Floating-point half precision registers. */
5703 REGSET (h, FP_H), REGSET (H, FP_H),
5705 /* Floating-point byte precision registers. */
5706 REGSET (b, FP_B), REGSET (B, FP_B),
5708 /* Floating-point quad precision registers. */
5709 REGSET (q, FP_Q), REGSET (Q, FP_Q),
5711 /* FP/SIMD registers. */
5712 REGSET (v, VN), REGSET (V, VN),
5727 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5728 static const asm_nzcv nzcv_names[] = {
5729 {"nzcv", B (n, z, c, v)},
5730 {"nzcV", B (n, z, c, V)},
5731 {"nzCv", B (n, z, C, v)},
5732 {"nzCV", B (n, z, C, V)},
5733 {"nZcv", B (n, Z, c, v)},
5734 {"nZcV", B (n, Z, c, V)},
5735 {"nZCv", B (n, Z, C, v)},
5736 {"nZCV", B (n, Z, C, V)},
5737 {"Nzcv", B (N, z, c, v)},
5738 {"NzcV", B (N, z, c, V)},
5739 {"NzCv", B (N, z, C, v)},
5740 {"NzCV", B (N, z, C, V)},
5741 {"NZcv", B (N, Z, c, v)},
5742 {"NZcV", B (N, Z, c, V)},
5743 {"NZCv", B (N, Z, C, v)},
5744 {"NZCV", B (N, Z, C, V)}
5757 /* MD interface: bits in the object file. */
5759 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5760 for use in the a.out file, and stores them in the array pointed to by buf.
5761 This knows about the endian-ness of the target machine and does
5762 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5763 2 (short) and 4 (long) Floating numbers are put out as a series of
5764 LITTLENUMS (shorts, here at least). */
5767 md_number_to_chars (char *buf, valueT val, int n)
5769 if (target_big_endian)
5770 number_to_chars_bigendian (buf, val, n);
5772 number_to_chars_littleendian (buf, val, n);
5775 /* MD interface: Sections. */
5777 /* Estimate the size of a frag before relaxing. Assume everything fits in
5781 md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED)
5787 /* Round up a section size to the appropriate boundary. */
5790 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5795 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5796 of an rs_align_code fragment. */
5799 aarch64_handle_align (fragS * fragP)
5801 /* NOP = d503201f */
5802 /* AArch64 instructions are always little-endian. */
5803 static char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
5805 int bytes, fix, noop_size;
5809 if (fragP->fr_type != rs_align_code)
5812 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5813 p = fragP->fr_literal + fragP->fr_fix;
5816 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
5817 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
5820 gas_assert (fragP->tc_frag_data.recorded);
5823 noop = aarch64_noop;
5824 noop_size = sizeof (aarch64_noop);
5825 fragP->fr_var = noop_size;
5827 if (bytes & (noop_size - 1))
5829 fix = bytes & (noop_size - 1);
5831 insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
5838 while (bytes >= noop_size)
5840 memcpy (p, noop, noop_size);
5846 fragP->fr_fix += fix;
5849 /* Called from md_do_align. Used to create an alignment
5850 frag in a code section. */
5853 aarch64_frag_align_code (int n, int max)
5857 /* We assume that there will never be a requirement
5858 to support alignments greater than x bytes. */
5859 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
5861 ("alignments greater than %d bytes not supported in .text sections"),
5862 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
5864 p = frag_var (rs_align_code,
5865 MAX_MEM_FOR_RS_ALIGN_CODE,
5867 (relax_substateT) max,
5868 (symbolS *) NULL, (offsetT) n, (char *) NULL);
5872 /* Perform target specific initialisation of a frag.
5873 Note - despite the name this initialisation is not done when the frag
5874 is created, but only when its type is assigned. A frag can be created
5875 and used a long time before its type is set, so beware of assuming that
5876 this initialisationis performed first. */
5880 aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED,
5881 int max_chars ATTRIBUTE_UNUSED)
5885 #else /* OBJ_ELF is defined. */
5887 aarch64_init_frag (fragS * fragP, int max_chars)
5889 /* Record a mapping symbol for alignment frags. We will delete this
5890 later if the alignment ends up empty. */
5891 if (!fragP->tc_frag_data.recorded)
5893 fragP->tc_frag_data.recorded = 1;
5894 switch (fragP->fr_type)
5899 mapping_state_2 (MAP_DATA, max_chars);
5902 mapping_state_2 (MAP_INSN, max_chars);
5910 /* Initialize the DWARF-2 unwind information for this procedure. */
5913 tc_aarch64_frame_initial_instructions (void)
5915 cfi_add_CFA_def_cfa (REG_SP, 0);
5917 #endif /* OBJ_ELF */
5919 /* Convert REGNAME to a DWARF-2 register number. */
5922 tc_aarch64_regname_to_dw2regnum (char *regname)
5924 const reg_entry *reg = parse_reg (®name);
5930 case REG_TYPE_SP_32:
5931 case REG_TYPE_SP_64:
5946 /* Implement DWARF2_ADDR_SIZE. */
5949 aarch64_dwarf2_addr_size (void)
5951 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5955 return bfd_arch_bits_per_address (stdoutput) / 8;
5958 /* MD interface: Symbol and relocation handling. */
5960 /* Return the address within the segment that a PC-relative fixup is
5961 relative to. For AArch64 PC-relative fixups applied to instructions
5962 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
5965 md_pcrel_from_section (fixS * fixP, segT seg)
5967 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
5969 /* If this is pc-relative and we are going to emit a relocation
5970 then we just want to put out any pipeline compensation that the linker
5971 will need. Otherwise we want to use the calculated base. */
5973 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5974 || aarch64_force_relocation (fixP)))
5977 /* AArch64 should be consistent for all pc-relative relocations. */
5978 return base + AARCH64_PCREL_OFFSET;
5981 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5982 Otherwise we have no need to default values of symbols. */
5985 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5988 if (name[0] == '_' && name[1] == 'G'
5989 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5993 if (symbol_find (name))
5994 as_bad (_("GOT already in the symbol table"));
5996 GOT_symbol = symbol_new (name, undefined_section,
5997 (valueT) 0, &zero_address_frag);
6007 /* Return non-zero if the indicated VALUE has overflowed the maximum
6008 range expressible by a unsigned number with the indicated number of
6012 unsigned_overflow (valueT value, unsigned bits)
6015 if (bits >= sizeof (valueT) * 8)
6017 lim = (valueT) 1 << bits;
6018 return (value >= lim);
6022 /* Return non-zero if the indicated VALUE has overflowed the maximum
6023 range expressible by an signed number with the indicated number of
6027 signed_overflow (offsetT value, unsigned bits)
6030 if (bits >= sizeof (offsetT) * 8)
6032 lim = (offsetT) 1 << (bits - 1);
6033 return (value < -lim || value >= lim);
6036 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6037 unsigned immediate offset load/store instruction, try to encode it as
6038 an unscaled, 9-bit, signed immediate offset load/store instruction.
6039 Return TRUE if it is successful; otherwise return FALSE.
6041 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6042 in response to the standard LDR/STR mnemonics when the immediate offset is
6043 unambiguous, i.e. when it is negative or unaligned. */
6046 try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
6049 enum aarch64_op new_op;
6050 const aarch64_opcode *new_opcode;
6052 gas_assert (instr->opcode->iclass == ldst_pos);
6054 switch (instr->opcode->op)
6056 case OP_LDRB_POS:new_op = OP_LDURB; break;
6057 case OP_STRB_POS: new_op = OP_STURB; break;
6058 case OP_LDRSB_POS: new_op = OP_LDURSB; break;
6059 case OP_LDRH_POS: new_op = OP_LDURH; break;
6060 case OP_STRH_POS: new_op = OP_STURH; break;
6061 case OP_LDRSH_POS: new_op = OP_LDURSH; break;
6062 case OP_LDR_POS: new_op = OP_LDUR; break;
6063 case OP_STR_POS: new_op = OP_STUR; break;
6064 case OP_LDRF_POS: new_op = OP_LDURV; break;
6065 case OP_STRF_POS: new_op = OP_STURV; break;
6066 case OP_LDRSW_POS: new_op = OP_LDURSW; break;
6067 case OP_PRFM_POS: new_op = OP_PRFUM; break;
6068 default: new_op = OP_NIL; break;
6071 if (new_op == OP_NIL)
6074 new_opcode = aarch64_get_opcode (new_op);
6075 gas_assert (new_opcode != NULL);
6077 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6078 instr->opcode->op, new_opcode->op);
6080 aarch64_replace_opcode (instr, new_opcode);
6082 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6083 qualifier matching may fail because the out-of-date qualifier will
6084 prevent the operand being updated with a new and correct qualifier. */
6085 idx = aarch64_operand_index (instr->opcode->operands,
6086 AARCH64_OPND_ADDR_SIMM9);
6087 gas_assert (idx == 1);
6088 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
6090 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6092 if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
6098 /* Called by fix_insn to fix a MOV immediate alias instruction.
6100 Operand for a generic move immediate instruction, which is an alias
6101 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6102 a 32-bit/64-bit immediate value into general register. An assembler error
6103 shall result if the immediate cannot be created by a single one of these
6104 instructions. If there is a choice, then to ensure reversability an
6105 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6108 fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
6110 const aarch64_opcode *opcode;
6112 /* Need to check if the destination is SP/ZR. The check has to be done
6113 before any aarch64_replace_opcode. */
6114 int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]);
6115 int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]);
6117 instr->operands[1].imm.value = value;
6118 instr->operands[1].skip = 0;
6122 /* Try the MOVZ alias. */
6123 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
6124 aarch64_replace_opcode (instr, opcode);
6125 if (aarch64_opcode_encode (instr->opcode, instr,
6126 &instr->value, NULL, NULL))
6128 put_aarch64_insn (buf, instr->value);
6131 /* Try the MOVK alias. */
6132 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
6133 aarch64_replace_opcode (instr, opcode);
6134 if (aarch64_opcode_encode (instr->opcode, instr,
6135 &instr->value, NULL, NULL))
6137 put_aarch64_insn (buf, instr->value);
6142 if (try_mov_bitmask_p)
6144 /* Try the ORR alias. */
6145 opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
6146 aarch64_replace_opcode (instr, opcode);
6147 if (aarch64_opcode_encode (instr->opcode, instr,
6148 &instr->value, NULL, NULL))
6150 put_aarch64_insn (buf, instr->value);
6155 as_bad_where (fixP->fx_file, fixP->fx_line,
6156 _("immediate cannot be moved by a single instruction"));
6159 /* An instruction operand which is immediate related may have symbol used
6160 in the assembly, e.g.
6163 .set u32, 0x00ffff00
6165 At the time when the assembly instruction is parsed, a referenced symbol,
6166 like 'u32' in the above example may not have been seen; a fixS is created
6167 in such a case and is handled here after symbols have been resolved.
6168 Instruction is fixed up with VALUE using the information in *FIXP plus
6169 extra information in FLAGS.
6171 This function is called by md_apply_fix to fix up instructions that need
6172 a fix-up described above but does not involve any linker-time relocation. */
6175 fix_insn (fixS *fixP, uint32_t flags, offsetT value)
6179 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6180 enum aarch64_opnd opnd = fixP->tc_fix_data.opnd;
6181 aarch64_inst *new_inst = fixP->tc_fix_data.inst;
6185 /* Now the instruction is about to be fixed-up, so the operand that
6186 was previously marked as 'ignored' needs to be unmarked in order
6187 to get the encoding done properly. */
6188 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6189 new_inst->operands[idx].skip = 0;
6192 gas_assert (opnd != AARCH64_OPND_NIL);
6196 case AARCH64_OPND_EXCEPTION:
6197 if (unsigned_overflow (value, 16))
6198 as_bad_where (fixP->fx_file, fixP->fx_line,
6199 _("immediate out of range"));
6200 insn = get_aarch64_insn (buf);
6201 insn |= encode_svc_imm (value);
6202 put_aarch64_insn (buf, insn);
6205 case AARCH64_OPND_AIMM:
6206 /* ADD or SUB with immediate.
6207 NOTE this assumes we come here with a add/sub shifted reg encoding
6208 3 322|2222|2 2 2 21111 111111
6209 1 098|7654|3 2 1 09876 543210 98765 43210
6210 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6211 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6212 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6213 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6215 3 322|2222|2 2 221111111111
6216 1 098|7654|3 2 109876543210 98765 43210
6217 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6218 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6219 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6220 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6221 Fields sf Rn Rd are already set. */
6222 insn = get_aarch64_insn (buf);
6226 insn = reencode_addsub_switch_add_sub (insn);
6230 if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0
6231 && unsigned_overflow (value, 12))
6233 /* Try to shift the value by 12 to make it fit. */
6234 if (((value >> 12) << 12) == value
6235 && ! unsigned_overflow (value, 12 + 12))
6238 insn |= encode_addsub_imm_shift_amount (1);
6242 if (unsigned_overflow (value, 12))
6243 as_bad_where (fixP->fx_file, fixP->fx_line,
6244 _("immediate out of range"));
6246 insn |= encode_addsub_imm (value);
6248 put_aarch64_insn (buf, insn);
6251 case AARCH64_OPND_SIMD_IMM:
6252 case AARCH64_OPND_SIMD_IMM_SFT:
6253 case AARCH64_OPND_LIMM:
6254 /* Bit mask immediate. */
6255 gas_assert (new_inst != NULL);
6256 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6257 new_inst->operands[idx].imm.value = value;
6258 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6259 &new_inst->value, NULL, NULL))
6260 put_aarch64_insn (buf, new_inst->value);
6262 as_bad_where (fixP->fx_file, fixP->fx_line,
6263 _("invalid immediate"));
6266 case AARCH64_OPND_HALF:
6267 /* 16-bit unsigned immediate. */
6268 if (unsigned_overflow (value, 16))
6269 as_bad_where (fixP->fx_file, fixP->fx_line,
6270 _("immediate out of range"));
6271 insn = get_aarch64_insn (buf);
6272 insn |= encode_movw_imm (value & 0xffff);
6273 put_aarch64_insn (buf, insn);
6276 case AARCH64_OPND_IMM_MOV:
6277 /* Operand for a generic move immediate instruction, which is
6278 an alias instruction that generates a single MOVZ, MOVN or ORR
6279 instruction to loads a 32-bit/64-bit immediate value into general
6280 register. An assembler error shall result if the immediate cannot be
6281 created by a single one of these instructions. If there is a choice,
6282 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6283 and MOVZ or MOVN to ORR. */
6284 gas_assert (new_inst != NULL);
6285 fix_mov_imm_insn (fixP, buf, new_inst, value);
6288 case AARCH64_OPND_ADDR_SIMM7:
6289 case AARCH64_OPND_ADDR_SIMM9:
6290 case AARCH64_OPND_ADDR_SIMM9_2:
6291 case AARCH64_OPND_ADDR_UIMM12:
6292 /* Immediate offset in an address. */
6293 insn = get_aarch64_insn (buf);
6295 gas_assert (new_inst != NULL && new_inst->value == insn);
6296 gas_assert (new_inst->opcode->operands[1] == opnd
6297 || new_inst->opcode->operands[2] == opnd);
6299 /* Get the index of the address operand. */
6300 if (new_inst->opcode->operands[1] == opnd)
6301 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6304 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6307 /* Update the resolved offset value. */
6308 new_inst->operands[idx].addr.offset.imm = value;
6310 /* Encode/fix-up. */
6311 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6312 &new_inst->value, NULL, NULL))
6314 put_aarch64_insn (buf, new_inst->value);
6317 else if (new_inst->opcode->iclass == ldst_pos
6318 && try_to_encode_as_unscaled_ldst (new_inst))
6320 put_aarch64_insn (buf, new_inst->value);
6324 as_bad_where (fixP->fx_file, fixP->fx_line,
6325 _("immediate offset out of range"));
6330 as_fatal (_("unhandled operand code %d"), opnd);
6334 /* Apply a fixup (fixP) to segment data, once it has been determined
6335 by our caller that we have all the info we need to fix it up.
6337 Parameter valP is the pointer to the value of the bits. */
6340 md_apply_fix (fixS * fixP, valueT * valP, segT seg)
6342 offsetT value = *valP;
6344 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6346 unsigned flags = fixP->fx_addnumber;
6348 DEBUG_TRACE ("\n\n");
6349 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6350 DEBUG_TRACE ("Enter md_apply_fix");
6352 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
6354 /* Note whether this will delete the relocation. */
6356 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
6359 /* Process the relocations. */
6360 switch (fixP->fx_r_type)
6362 case BFD_RELOC_NONE:
6363 /* This will need to go in the object file. */
6368 case BFD_RELOC_8_PCREL:
6369 if (fixP->fx_done || !seg->use_rela_p)
6370 md_number_to_chars (buf, value, 1);
6374 case BFD_RELOC_16_PCREL:
6375 if (fixP->fx_done || !seg->use_rela_p)
6376 md_number_to_chars (buf, value, 2);
6380 case BFD_RELOC_32_PCREL:
6381 if (fixP->fx_done || !seg->use_rela_p)
6382 md_number_to_chars (buf, value, 4);
6386 case BFD_RELOC_64_PCREL:
6387 if (fixP->fx_done || !seg->use_rela_p)
6388 md_number_to_chars (buf, value, 8);
6391 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
6392 /* We claim that these fixups have been processed here, even if
6393 in fact we generate an error because we do not have a reloc
6394 for them, so tc_gen_reloc() will reject them. */
6396 if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy))
6398 as_bad_where (fixP->fx_file, fixP->fx_line,
6399 _("undefined symbol %s used as an immediate value"),
6400 S_GET_NAME (fixP->fx_addsy));
6401 goto apply_fix_return;
6403 fix_insn (fixP, flags, value);
6406 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
6407 if (fixP->fx_done || !seg->use_rela_p)
6410 as_bad_where (fixP->fx_file, fixP->fx_line,
6411 _("pc-relative load offset not word aligned"));
6412 if (signed_overflow (value, 21))
6413 as_bad_where (fixP->fx_file, fixP->fx_line,
6414 _("pc-relative load offset out of range"));
6415 insn = get_aarch64_insn (buf);
6416 insn |= encode_ld_lit_ofs_19 (value >> 2);
6417 put_aarch64_insn (buf, insn);
6421 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
6422 if (fixP->fx_done || !seg->use_rela_p)
6424 if (signed_overflow (value, 21))
6425 as_bad_where (fixP->fx_file, fixP->fx_line,
6426 _("pc-relative address offset out of range"));
6427 insn = get_aarch64_insn (buf);
6428 insn |= encode_adr_imm (value);
6429 put_aarch64_insn (buf, insn);
6433 case BFD_RELOC_AARCH64_BRANCH19:
6434 if (fixP->fx_done || !seg->use_rela_p)
6437 as_bad_where (fixP->fx_file, fixP->fx_line,
6438 _("conditional branch target not word aligned"));
6439 if (signed_overflow (value, 21))
6440 as_bad_where (fixP->fx_file, fixP->fx_line,
6441 _("conditional branch out of range"));
6442 insn = get_aarch64_insn (buf);
6443 insn |= encode_cond_branch_ofs_19 (value >> 2);
6444 put_aarch64_insn (buf, insn);
6448 case BFD_RELOC_AARCH64_TSTBR14:
6449 if (fixP->fx_done || !seg->use_rela_p)
6452 as_bad_where (fixP->fx_file, fixP->fx_line,
6453 _("conditional branch target not word aligned"));
6454 if (signed_overflow (value, 16))
6455 as_bad_where (fixP->fx_file, fixP->fx_line,
6456 _("conditional branch out of range"));
6457 insn = get_aarch64_insn (buf);
6458 insn |= encode_tst_branch_ofs_14 (value >> 2);
6459 put_aarch64_insn (buf, insn);
6463 case BFD_RELOC_AARCH64_JUMP26:
6464 case BFD_RELOC_AARCH64_CALL26:
6465 if (fixP->fx_done || !seg->use_rela_p)
6468 as_bad_where (fixP->fx_file, fixP->fx_line,
6469 _("branch target not word aligned"));
6470 if (signed_overflow (value, 28))
6471 as_bad_where (fixP->fx_file, fixP->fx_line,
6472 _("branch out of range"));
6473 insn = get_aarch64_insn (buf);
6474 insn |= encode_branch_ofs_26 (value >> 2);
6475 put_aarch64_insn (buf, insn);
6479 case BFD_RELOC_AARCH64_MOVW_G0:
6480 case BFD_RELOC_AARCH64_MOVW_G0_S:
6481 case BFD_RELOC_AARCH64_MOVW_G0_NC:
6484 case BFD_RELOC_AARCH64_MOVW_G1:
6485 case BFD_RELOC_AARCH64_MOVW_G1_S:
6486 case BFD_RELOC_AARCH64_MOVW_G1_NC:
6489 case BFD_RELOC_AARCH64_MOVW_G2:
6490 case BFD_RELOC_AARCH64_MOVW_G2_S:
6491 case BFD_RELOC_AARCH64_MOVW_G2_NC:
6494 case BFD_RELOC_AARCH64_MOVW_G3:
6497 if (fixP->fx_done || !seg->use_rela_p)
6499 insn = get_aarch64_insn (buf);
6503 /* REL signed addend must fit in 16 bits */
6504 if (signed_overflow (value, 16))
6505 as_bad_where (fixP->fx_file, fixP->fx_line,
6506 _("offset out of range"));
6510 /* Check for overflow and scale. */
6511 switch (fixP->fx_r_type)
6513 case BFD_RELOC_AARCH64_MOVW_G0:
6514 case BFD_RELOC_AARCH64_MOVW_G1:
6515 case BFD_RELOC_AARCH64_MOVW_G2:
6516 case BFD_RELOC_AARCH64_MOVW_G3:
6517 if (unsigned_overflow (value, scale + 16))
6518 as_bad_where (fixP->fx_file, fixP->fx_line,
6519 _("unsigned value out of range"));
6521 case BFD_RELOC_AARCH64_MOVW_G0_S:
6522 case BFD_RELOC_AARCH64_MOVW_G1_S:
6523 case BFD_RELOC_AARCH64_MOVW_G2_S:
6524 /* NOTE: We can only come here with movz or movn. */
6525 if (signed_overflow (value, scale + 16))
6526 as_bad_where (fixP->fx_file, fixP->fx_line,
6527 _("signed value out of range"));
6530 /* Force use of MOVN. */
6532 insn = reencode_movzn_to_movn (insn);
6536 /* Force use of MOVZ. */
6537 insn = reencode_movzn_to_movz (insn);
6541 /* Unchecked relocations. */
6547 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6548 insn |= encode_movw_imm (value & 0xffff);
6550 put_aarch64_insn (buf, insn);
6554 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
6555 fixP->fx_r_type = (ilp32_p
6556 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6557 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);
6558 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6559 /* Should always be exported to object file, see
6560 aarch64_force_relocation(). */
6561 gas_assert (!fixP->fx_done);
6562 gas_assert (seg->use_rela_p);
6565 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
6566 fixP->fx_r_type = (ilp32_p
6567 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6568 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC);
6569 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6570 /* Should always be exported to object file, see
6571 aarch64_force_relocation(). */
6572 gas_assert (!fixP->fx_done);
6573 gas_assert (seg->use_rela_p);
6576 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
6577 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
6578 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
6579 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
6580 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
6581 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
6582 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
6583 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
6584 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
6585 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
6586 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
6587 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
6588 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
6589 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
6590 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
6591 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
6592 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
6593 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6594 /* Should always be exported to object file, see
6595 aarch64_force_relocation(). */
6596 gas_assert (!fixP->fx_done);
6597 gas_assert (seg->use_rela_p);
6600 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
6601 /* Should always be exported to object file, see
6602 aarch64_force_relocation(). */
6603 fixP->fx_r_type = (ilp32_p
6604 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6605 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC);
6606 gas_assert (!fixP->fx_done);
6607 gas_assert (seg->use_rela_p);
6610 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
6611 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
6612 case BFD_RELOC_AARCH64_ADD_LO12:
6613 case BFD_RELOC_AARCH64_LDST8_LO12:
6614 case BFD_RELOC_AARCH64_LDST16_LO12:
6615 case BFD_RELOC_AARCH64_LDST32_LO12:
6616 case BFD_RELOC_AARCH64_LDST64_LO12:
6617 case BFD_RELOC_AARCH64_LDST128_LO12:
6618 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
6619 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
6620 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
6621 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
6622 /* Should always be exported to object file, see
6623 aarch64_force_relocation(). */
6624 gas_assert (!fixP->fx_done);
6625 gas_assert (seg->use_rela_p);
6628 case BFD_RELOC_AARCH64_TLSDESC_ADD:
6629 case BFD_RELOC_AARCH64_TLSDESC_LDR:
6630 case BFD_RELOC_AARCH64_TLSDESC_CALL:
6634 as_bad_where (fixP->fx_file, fixP->fx_line,
6635 _("unexpected %s fixup"),
6636 bfd_get_reloc_code_name (fixP->fx_r_type));
6641 /* Free the allocated the struct aarch64_inst.
6642 N.B. currently there are very limited number of fix-up types actually use
6643 this field, so the impact on the performance should be minimal . */
6644 if (fixP->tc_fix_data.inst != NULL)
6645 free (fixP->tc_fix_data.inst);
6650 /* Translate internal representation of relocation info to BFD target
6654 tc_gen_reloc (asection * section, fixS * fixp)
6657 bfd_reloc_code_real_type code;
6659 reloc = xmalloc (sizeof (arelent));
6661 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
6662 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6663 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6667 if (section->use_rela_p)
6668 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
6670 fixp->fx_offset = reloc->address;
6672 reloc->addend = fixp->fx_offset;
6674 code = fixp->fx_r_type;
6679 code = BFD_RELOC_16_PCREL;
6684 code = BFD_RELOC_32_PCREL;
6689 code = BFD_RELOC_64_PCREL;
6696 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6697 if (reloc->howto == NULL)
6699 as_bad_where (fixp->fx_file, fixp->fx_line,
6701 ("cannot represent %s relocation in this object file format"),
6702 bfd_get_reloc_code_name (code));
6709 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6712 cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp)
6714 bfd_reloc_code_real_type type;
6718 FIXME: @@ Should look at CPU word size. */
6725 type = BFD_RELOC_16;
6728 type = BFD_RELOC_32;
6731 type = BFD_RELOC_64;
6734 as_bad (_("cannot do %u-byte relocation"), size);
6735 type = BFD_RELOC_UNUSED;
6739 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6743 aarch64_force_relocation (struct fix *fixp)
6745 switch (fixp->fx_r_type)
6747 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
6748 /* Perform these "immediate" internal relocations
6749 even if the symbol is extern or weak. */
6752 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC:
6753 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
6754 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC:
6755 /* Pseudo relocs that need to be fixed up according to
6759 case BFD_RELOC_AARCH64_ADD_LO12:
6760 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
6761 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
6762 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
6763 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
6764 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
6765 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
6766 case BFD_RELOC_AARCH64_LDST128_LO12:
6767 case BFD_RELOC_AARCH64_LDST16_LO12:
6768 case BFD_RELOC_AARCH64_LDST32_LO12:
6769 case BFD_RELOC_AARCH64_LDST64_LO12:
6770 case BFD_RELOC_AARCH64_LDST8_LO12:
6771 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
6772 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
6773 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
6774 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
6775 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
6776 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
6777 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
6778 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
6779 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
6780 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
6781 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
6782 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
6783 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
6784 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
6785 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
6786 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
6787 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
6788 /* Always leave these relocations for the linker. */
6795 return generic_force_reloc (fixp);
6801 elf64_aarch64_target_format (void)
6803 if (target_big_endian)
6804 return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
6806 return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";
6810 aarch64elf_frob_symbol (symbolS * symp, int *puntp)
6812 elf_frob_symbol (symp, puntp);
6816 /* MD interface: Finalization. */
6818 /* A good place to do this, although this was probably not intended
6819 for this kind of use. We need to dump the literal pool before
6820 references are made to a null symbol pointer. */
6823 aarch64_cleanup (void)
6827 for (pool = list_of_pools; pool; pool = pool->next)
6829 /* Put it at the end of the relevant section. */
6830 subseg_set (pool->section, pool->sub_section);
6836 /* Remove any excess mapping symbols generated for alignment frags in
6837 SEC. We may have created a mapping symbol before a zero byte
6838 alignment; remove it if there's a mapping symbol after the
6841 check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec,
6842 void *dummy ATTRIBUTE_UNUSED)
6844 segment_info_type *seginfo = seg_info (sec);
6847 if (seginfo == NULL || seginfo->frchainP == NULL)
6850 for (fragp = seginfo->frchainP->frch_root;
6851 fragp != NULL; fragp = fragp->fr_next)
6853 symbolS *sym = fragp->tc_frag_data.last_map;
6854 fragS *next = fragp->fr_next;
6856 /* Variable-sized frags have been converted to fixed size by
6857 this point. But if this was variable-sized to start with,
6858 there will be a fixed-size frag after it. So don't handle
6860 if (sym == NULL || next == NULL)
6863 if (S_GET_VALUE (sym) < next->fr_address)
6864 /* Not at the end of this frag. */
6866 know (S_GET_VALUE (sym) == next->fr_address);
6870 if (next->tc_frag_data.first_map != NULL)
6872 /* Next frag starts with a mapping symbol. Discard this
6874 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
6878 if (next->fr_next == NULL)
6880 /* This mapping symbol is at the end of the section. Discard
6882 know (next->fr_fix == 0 && next->fr_var == 0);
6883 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
6887 /* As long as we have empty frags without any mapping symbols,
6889 /* If the next frag is non-empty and does not start with a
6890 mapping symbol, then this mapping symbol is required. */
6891 if (next->fr_address != next->fr_next->fr_address)
6894 next = next->fr_next;
6896 while (next != NULL);
6901 /* Adjust the symbol table. */
6904 aarch64_adjust_symtab (void)
6907 /* Remove any overlapping mapping symbols generated by alignment frags. */
6908 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
6909 /* Now do generic ELF adjustments. */
6910 elf_adjust_symtab ();
6915 checked_hash_insert (struct hash_control *table, const char *key, void *value)
6917 const char *hash_err;
6919 hash_err = hash_insert (table, key, value);
6921 printf ("Internal Error: Can't hash %s\n", key);
6925 fill_instruction_hash_table (void)
6927 aarch64_opcode *opcode = aarch64_opcode_table;
6929 while (opcode->name != NULL)
6931 templates *templ, *new_templ;
6932 templ = hash_find (aarch64_ops_hsh, opcode->name);
6934 new_templ = (templates *) xmalloc (sizeof (templates));
6935 new_templ->opcode = opcode;
6936 new_templ->next = NULL;
6939 checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ);
6942 new_templ->next = templ->next;
6943 templ->next = new_templ;
6950 convert_to_upper (char *dst, const char *src, size_t num)
6953 for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src)
6954 *dst = TOUPPER (*src);
6958 /* Assume STR point to a lower-case string, allocate, convert and return
6959 the corresponding upper-case string. */
6960 static inline const char*
6961 get_upper_str (const char *str)
6964 size_t len = strlen (str);
6965 if ((ret = xmalloc (len + 1)) == NULL)
6967 convert_to_upper (ret, str, len);
6971 /* MD interface: Initialization. */
6979 if ((aarch64_ops_hsh = hash_new ()) == NULL
6980 || (aarch64_cond_hsh = hash_new ()) == NULL
6981 || (aarch64_shift_hsh = hash_new ()) == NULL
6982 || (aarch64_sys_regs_hsh = hash_new ()) == NULL
6983 || (aarch64_pstatefield_hsh = hash_new ()) == NULL
6984 || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
6985 || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
6986 || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
6987 || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
6988 || (aarch64_reg_hsh = hash_new ()) == NULL
6989 || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
6990 || (aarch64_nzcv_hsh = hash_new ()) == NULL
6991 || (aarch64_pldop_hsh = hash_new ()) == NULL)
6992 as_fatal (_("virtual memory exhausted"));
6994 fill_instruction_hash_table ();
6996 for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
6997 checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
6998 (void *) (aarch64_sys_regs + i));
7000 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
7001 checked_hash_insert (aarch64_pstatefield_hsh,
7002 aarch64_pstatefields[i].name,
7003 (void *) (aarch64_pstatefields + i));
7005 for (i = 0; aarch64_sys_regs_ic[i].template != NULL; i++)
7006 checked_hash_insert (aarch64_sys_regs_ic_hsh,
7007 aarch64_sys_regs_ic[i].template,
7008 (void *) (aarch64_sys_regs_ic + i));
7010 for (i = 0; aarch64_sys_regs_dc[i].template != NULL; i++)
7011 checked_hash_insert (aarch64_sys_regs_dc_hsh,
7012 aarch64_sys_regs_dc[i].template,
7013 (void *) (aarch64_sys_regs_dc + i));
7015 for (i = 0; aarch64_sys_regs_at[i].template != NULL; i++)
7016 checked_hash_insert (aarch64_sys_regs_at_hsh,
7017 aarch64_sys_regs_at[i].template,
7018 (void *) (aarch64_sys_regs_at + i));
7020 for (i = 0; aarch64_sys_regs_tlbi[i].template != NULL; i++)
7021 checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
7022 aarch64_sys_regs_tlbi[i].template,
7023 (void *) (aarch64_sys_regs_tlbi + i));
7025 for (i = 0; i < ARRAY_SIZE (reg_names); i++)
7026 checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
7027 (void *) (reg_names + i));
7029 for (i = 0; i < ARRAY_SIZE (nzcv_names); i++)
7030 checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template,
7031 (void *) (nzcv_names + i));
7033 for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++)
7035 const char *name = aarch64_operand_modifiers[i].name;
7036 checked_hash_insert (aarch64_shift_hsh, name,
7037 (void *) (aarch64_operand_modifiers + i));
7038 /* Also hash the name in the upper case. */
7039 checked_hash_insert (aarch64_shift_hsh, get_upper_str (name),
7040 (void *) (aarch64_operand_modifiers + i));
7043 for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++)
7046 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7047 the same condition code. */
7048 for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j)
7050 const char *name = aarch64_conds[i].names[j];
7053 checked_hash_insert (aarch64_cond_hsh, name,
7054 (void *) (aarch64_conds + i));
7055 /* Also hash the name in the upper case. */
7056 checked_hash_insert (aarch64_cond_hsh, get_upper_str (name),
7057 (void *) (aarch64_conds + i));
7061 for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++)
7063 const char *name = aarch64_barrier_options[i].name;
7064 /* Skip xx00 - the unallocated values of option. */
7067 checked_hash_insert (aarch64_barrier_opt_hsh, name,
7068 (void *) (aarch64_barrier_options + i));
7069 /* Also hash the name in the upper case. */
7070 checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
7071 (void *) (aarch64_barrier_options + i));
7074 for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
7076 const char* name = aarch64_prfops[i].name;
7077 /* Skip the unallocated hint encodings. */
7080 checked_hash_insert (aarch64_pldop_hsh, name,
7081 (void *) (aarch64_prfops + i));
7082 /* Also hash the name in the upper case. */
7083 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
7084 (void *) (aarch64_prfops + i));
7087 /* Set the cpu variant based on the command-line options. */
7089 mcpu_cpu_opt = march_cpu_opt;
7092 mcpu_cpu_opt = &cpu_default;
7094 cpu_variant = *mcpu_cpu_opt;
7096 /* Record the CPU type. */
7097 mach = ilp32_p ? bfd_mach_aarch64_ilp32 : bfd_mach_aarch64;
7099 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
7102 /* Command line processing. */
7104 const char *md_shortopts = "m:";
7106 #ifdef AARCH64_BI_ENDIAN
7107 #define OPTION_EB (OPTION_MD_BASE + 0)
7108 #define OPTION_EL (OPTION_MD_BASE + 1)
7110 #if TARGET_BYTES_BIG_ENDIAN
7111 #define OPTION_EB (OPTION_MD_BASE + 0)
7113 #define OPTION_EL (OPTION_MD_BASE + 1)
7117 struct option md_longopts[] = {
7119 {"EB", no_argument, NULL, OPTION_EB},
7122 {"EL", no_argument, NULL, OPTION_EL},
7124 {NULL, no_argument, NULL, 0}
7127 size_t md_longopts_size = sizeof (md_longopts);
7129 struct aarch64_option_table
7131 char *option; /* Option name to match. */
7132 char *help; /* Help information. */
7133 int *var; /* Variable to change. */
7134 int value; /* What to change it to. */
7135 char *deprecated; /* If non-null, print this message. */
7138 static struct aarch64_option_table aarch64_opts[] = {
7139 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
7140 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
7142 #ifdef DEBUG_AARCH64
7143 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL},
7144 #endif /* DEBUG_AARCH64 */
7145 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1,
7147 {NULL, NULL, NULL, 0, NULL}
7150 struct aarch64_cpu_option_table
7153 const aarch64_feature_set value;
7154 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7156 const char *canonical_name;
7159 /* This list should, at a minimum, contain all the cpu names
7160 recognized by GCC. */
7161 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
7162 {"all", AARCH64_ANY, NULL},
7163 {"cortex-a53", AARCH64_ARCH_V8, "Cortex-A53"},
7164 {"cortex-a57", AARCH64_ARCH_V8, "Cortex-A57"},
7165 {"generic", AARCH64_ARCH_V8, NULL},
7167 /* These two are example CPUs supported in GCC, once we have real
7168 CPUs they will be removed. */
7169 {"example-1", AARCH64_ARCH_V8, NULL},
7170 {"example-2", AARCH64_ARCH_V8, NULL},
7172 {NULL, AARCH64_ARCH_NONE, NULL}
7175 struct aarch64_arch_option_table
7178 const aarch64_feature_set value;
7181 /* This list should, at a minimum, contain all the architecture names
7182 recognized by GCC. */
7183 static const struct aarch64_arch_option_table aarch64_archs[] = {
7184 {"all", AARCH64_ANY},
7185 {"armv8-a", AARCH64_ARCH_V8},
7186 {NULL, AARCH64_ARCH_NONE}
7189 /* ISA extensions. */
7190 struct aarch64_option_cpu_value_table
7193 const aarch64_feature_set value;
7196 static const struct aarch64_option_cpu_value_table aarch64_features[] = {
7197 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0)},
7198 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0)},
7199 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
7200 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
7201 {NULL, AARCH64_ARCH_NONE}
7204 struct aarch64_long_option_table
7206 char *option; /* Substring to match. */
7207 char *help; /* Help information. */
7208 int (*func) (char *subopt); /* Function to decode sub-option. */
7209 char *deprecated; /* If non-null, print this message. */
7213 aarch64_parse_features (char *str, const aarch64_feature_set **opt_p)
7215 /* We insist on extensions being added before being removed. We achieve
7216 this by using the ADDING_VALUE variable to indicate whether we are
7217 adding an extension (1) or removing it (0) and only allowing it to
7218 change in the order -1 -> 1 -> 0. */
7219 int adding_value = -1;
7220 aarch64_feature_set *ext_set = xmalloc (sizeof (aarch64_feature_set));
7222 /* Copy the feature set, so that we can modify it. */
7226 while (str != NULL && *str != 0)
7228 const struct aarch64_option_cpu_value_table *opt;
7234 as_bad (_("invalid architectural extension"));
7239 ext = strchr (str, '+');
7244 optlen = strlen (str);
7246 if (optlen >= 2 && strncmp (str, "no", 2) == 0)
7248 if (adding_value != 0)
7253 else if (optlen > 0)
7255 if (adding_value == -1)
7257 else if (adding_value != 1)
7259 as_bad (_("must specify extensions to add before specifying "
7260 "those to remove"));
7267 as_bad (_("missing architectural extension"));
7271 gas_assert (adding_value != -1);
7273 for (opt = aarch64_features; opt->name != NULL; opt++)
7274 if (strncmp (opt->name, str, optlen) == 0)
7276 /* Add or remove the extension. */
7278 AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
7280 AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
7284 if (opt->name == NULL)
7286 as_bad (_("unknown architectural extension `%s'"), str);
7297 aarch64_parse_cpu (char *str)
7299 const struct aarch64_cpu_option_table *opt;
7300 char *ext = strchr (str, '+');
7306 optlen = strlen (str);
7310 as_bad (_("missing cpu name `%s'"), str);
7314 for (opt = aarch64_cpus; opt->name != NULL; opt++)
7315 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7317 mcpu_cpu_opt = &opt->value;
7319 return aarch64_parse_features (ext, &mcpu_cpu_opt);
7324 as_bad (_("unknown cpu `%s'"), str);
7329 aarch64_parse_arch (char *str)
7331 const struct aarch64_arch_option_table *opt;
7332 char *ext = strchr (str, '+');
7338 optlen = strlen (str);
7342 as_bad (_("missing architecture name `%s'"), str);
7346 for (opt = aarch64_archs; opt->name != NULL; opt++)
7347 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7349 march_cpu_opt = &opt->value;
7351 return aarch64_parse_features (ext, &march_cpu_opt);
7356 as_bad (_("unknown architecture `%s'\n"), str);
7361 struct aarch64_option_abi_value_table
7364 enum aarch64_abi_type value;
7367 static const struct aarch64_option_abi_value_table aarch64_abis[] = {
7368 {"ilp32", AARCH64_ABI_ILP32},
7369 {"lp64", AARCH64_ABI_LP64},
7374 aarch64_parse_abi (char *str)
7376 const struct aarch64_option_abi_value_table *opt;
7377 size_t optlen = strlen (str);
7381 as_bad (_("missing abi name `%s'"), str);
7385 for (opt = aarch64_abis; opt->name != NULL; opt++)
7386 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7388 aarch64_abi = opt->value;
7392 as_bad (_("unknown abi `%s'\n"), str);
7396 static struct aarch64_long_option_table aarch64_long_opts[] = {
7398 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
7399 aarch64_parse_abi, NULL},
7400 #endif /* OBJ_ELF */
7401 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7402 aarch64_parse_cpu, NULL},
7403 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7404 aarch64_parse_arch, NULL},
7405 {NULL, NULL, 0, NULL}
7409 md_parse_option (int c, char *arg)
7411 struct aarch64_option_table *opt;
7412 struct aarch64_long_option_table *lopt;
7418 target_big_endian = 1;
7424 target_big_endian = 0;
7429 /* Listing option. Just ignore these, we don't support additional
7434 for (opt = aarch64_opts; opt->option != NULL; opt++)
7436 if (c == opt->option[0]
7437 && ((arg == NULL && opt->option[1] == 0)
7438 || streq (arg, opt->option + 1)))
7440 /* If the option is deprecated, tell the user. */
7441 if (opt->deprecated != NULL)
7442 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
7443 arg ? arg : "", _(opt->deprecated));
7445 if (opt->var != NULL)
7446 *opt->var = opt->value;
7452 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
7454 /* These options are expected to have an argument. */
7455 if (c == lopt->option[0]
7457 && strncmp (arg, lopt->option + 1,
7458 strlen (lopt->option + 1)) == 0)
7460 /* If the option is deprecated, tell the user. */
7461 if (lopt->deprecated != NULL)
7462 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
7463 _(lopt->deprecated));
7465 /* Call the sup-option parser. */
7466 return lopt->func (arg + strlen (lopt->option) - 1);
7477 md_show_usage (FILE * fp)
7479 struct aarch64_option_table *opt;
7480 struct aarch64_long_option_table *lopt;
7482 fprintf (fp, _(" AArch64-specific assembler options:\n"));
7484 for (opt = aarch64_opts; opt->option != NULL; opt++)
7485 if (opt->help != NULL)
7486 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
7488 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
7489 if (lopt->help != NULL)
7490 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
7494 -EB assemble code for a big-endian cpu\n"));
7499 -EL assemble code for a little-endian cpu\n"));
7503 /* Parse a .cpu directive. */
7506 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
7508 const struct aarch64_cpu_option_table *opt;
7514 name = input_line_pointer;
7515 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7516 input_line_pointer++;
7517 saved_char = *input_line_pointer;
7518 *input_line_pointer = 0;
7520 ext = strchr (name, '+');
7523 optlen = ext - name;
7525 optlen = strlen (name);
7527 /* Skip the first "all" entry. */
7528 for (opt = aarch64_cpus + 1; opt->name != NULL; opt++)
7529 if (strlen (opt->name) == optlen
7530 && strncmp (name, opt->name, optlen) == 0)
7532 mcpu_cpu_opt = &opt->value;
7534 if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
7537 cpu_variant = *mcpu_cpu_opt;
7539 *input_line_pointer = saved_char;
7540 demand_empty_rest_of_line ();
7543 as_bad (_("unknown cpu `%s'"), name);
7544 *input_line_pointer = saved_char;
7545 ignore_rest_of_line ();
7549 /* Parse a .arch directive. */
7552 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
7554 const struct aarch64_arch_option_table *opt;
7560 name = input_line_pointer;
7561 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7562 input_line_pointer++;
7563 saved_char = *input_line_pointer;
7564 *input_line_pointer = 0;
7566 ext = strchr (name, '+');
7569 optlen = ext - name;
7571 optlen = strlen (name);
7573 /* Skip the first "all" entry. */
7574 for (opt = aarch64_archs + 1; opt->name != NULL; opt++)
7575 if (strlen (opt->name) == optlen
7576 && strncmp (name, opt->name, optlen) == 0)
7578 mcpu_cpu_opt = &opt->value;
7580 if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
7583 cpu_variant = *mcpu_cpu_opt;
7585 *input_line_pointer = saved_char;
7586 demand_empty_rest_of_line ();
7590 as_bad (_("unknown architecture `%s'\n"), name);
7591 *input_line_pointer = saved_char;
7592 ignore_rest_of_line ();
7595 /* Copy symbol information. */
7598 aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
7600 AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);