1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 #include "bfin-aux.h" /* Opcode generating auxiliaries. */
28 #include "elf/common.h"
31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
32 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
35 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
39 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
43 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
46 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
48 #define LDIMMHALF_R(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
52 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
54 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
55 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
57 #define LDST(ptr, reg, aop, sz, z, w) \
58 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
60 #define LDSTII(ptr, reg, offset, w, op) \
61 bfin_gen_ldstii (ptr, reg, offset, w, op)
63 #define DSPLDST(i, m, reg, aop, w) \
64 bfin_gen_dspldst (i, reg, aop, w, m)
66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
67 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
69 #define LDSTIIFP(offset, reg, w) \
70 bfin_gen_ldstiifp (reg, offset, w)
72 #define LOGI2OP(dst, src, opc) \
73 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
75 #define ALU2OP(dst, src, opc) \
76 bfin_gen_alu2op (dst, src, opc)
78 #define BRCC(t, b, offset) \
79 bfin_gen_brcc (t, b, offset)
81 #define UJUMP(offset) \
82 bfin_gen_ujump (offset)
84 #define PROGCTRL(prgfunc, poprnd) \
85 bfin_gen_progctrl (prgfunc, poprnd)
87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
88 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
90 #define PUSHPOPREG(reg, w) \
91 bfin_gen_pushpopreg (reg, w)
93 #define CALLA(addr, s) \
94 bfin_gen_calla (addr, s)
96 #define LINKAGE(r, framesize) \
97 bfin_gen_linkage (r, framesize)
99 #define COMPI2OPD(dst, src, op) \
100 bfin_gen_compi2opd (dst, src, op)
102 #define COMPI2OPP(dst, src, op) \
103 bfin_gen_compi2opp (dst, src, op)
105 #define DAGMODIK(i, op) \
106 bfin_gen_dagmodik (i, op)
108 #define DAGMODIM(i, m, op, br) \
109 bfin_gen_dagmodim (i, m, op, br)
111 #define COMP3OP(dst, src0, src1, opc) \
112 bfin_gen_comp3op (src0, src1, dst, opc)
114 #define PTR2OP(dst, src, opc) \
115 bfin_gen_ptr2op (dst, src, opc)
117 #define CCFLAG(x, y, opc, i, g) \
118 bfin_gen_ccflag (x, y, opc, i, g)
120 #define CCMV(src, dst, t) \
121 bfin_gen_ccmv (src, dst, t)
123 #define CACTRL(reg, a, op) \
124 bfin_gen_cactrl (reg, a, op)
126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
127 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
129 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
130 #define IS_RANGE(bits, expr, sign, mul) \
131 value_match(expr, bits, sign, mul, 1)
132 #define IS_URANGE(bits, expr, sign, mul) \
133 value_match(expr, bits, sign, mul, 0)
134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
136 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
137 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
139 #define IS_PCREL4(expr) \
140 (value_match (expr, 4, 0, 2, 0))
142 #define IS_LPPCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 0))
145 #define IS_PCREL10(expr) \
146 (value_match (expr, 10, 0, 2, 1))
148 #define IS_PCREL12(expr) \
149 (value_match (expr, 12, 0, 2, 1))
151 #define IS_PCREL24(expr) \
152 (value_match (expr, 24, 0, 2, 1))
155 static int value_match (Expr_Node *, int, int, int, int);
160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
161 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
163 static void notethat (char *, ...);
165 char *current_inputline;
167 int yyerror (char *);
169 void error (char *format, ...)
172 static char buffer[2000];
174 va_start (ap, format);
175 vsprintf (buffer, format, ap);
178 as_bad ("%s", buffer);
187 else if (yytext[0] != ';')
188 error ("%s. Input text was %s.", msg, yytext);
196 in_range_p (Expr_Node *exp, int from, int to, unsigned int mask)
198 int val = EXPR_VALUE (exp);
199 if (exp->type != Expr_Node_Constant)
201 if (val < from || val > to)
203 return (val & mask) == 0;
206 extern int yylex (void);
208 #define imm3(x) EXPR_VALUE (x)
209 #define imm4(x) EXPR_VALUE (x)
210 #define uimm4(x) EXPR_VALUE (x)
211 #define imm5(x) EXPR_VALUE (x)
212 #define uimm5(x) EXPR_VALUE (x)
213 #define imm6(x) EXPR_VALUE (x)
214 #define imm7(x) EXPR_VALUE (x)
215 #define uimm8(x) EXPR_VALUE (x)
216 #define imm16(x) EXPR_VALUE (x)
217 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
218 #define uimm16(x) EXPR_VALUE (x)
220 /* Return true if a value is inside a range. */
221 #define IN_RANGE(x, low, high) \
222 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
224 /* Auxiliary functions. */
227 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
229 if (!IS_DREG (*reg1))
231 yyerror ("Dregs expected");
235 if (reg1->regno != 1 && reg1->regno != 3)
237 yyerror ("Bad register pair");
241 if (imm7 (reg2) != reg1->regno - 1)
243 yyerror ("Bad register pair");
252 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
254 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
255 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
256 return yyerror ("Source multiplication register mismatch");
262 /* Check mac option. */
265 check_macfunc_option (Macfunc *a, Opt_mode *opt)
267 /* Default option is always valid. */
271 if ((a->w == 1 && a->P == 1
272 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
273 && opt->mod != M_S2RND && opt->mod != M_ISS2)
274 || (a->w == 1 && a->P == 0
275 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
276 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
277 && opt->mod != M_ISS2 && opt->mod != M_IH)
278 || (a->w == 0 && a->P == 0
279 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
285 /* Check (vector) mac funcs and ops. */
288 check_macfuncs (Macfunc *aa, Opt_mode *opa,
289 Macfunc *ab, Opt_mode *opb)
291 /* Variables for swapping. */
295 /* The option mode should be put at the end of the second instruction
296 of the vector except M, which should follow MAC1 instruction. */
298 return yyerror ("Bad opt mode");
300 /* If a0macfunc comes before a1macfunc, swap them. */
304 /* (M) is not allowed here. */
306 return yyerror ("(M) not allowed with A0MAC");
308 return yyerror ("Vector AxMACs can't be same");
310 mtmp = *aa; *aa = *ab; *ab = mtmp;
311 otmp = *opa; *opa = *opb; *opb = otmp;
316 return yyerror ("(M) not allowed with A0MAC");
318 return yyerror ("Vector AxMACs can't be same");
321 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
322 assignment_or_macfuncs. */
323 if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
324 && (ab->op == 0 || ab->op == 1 || ab->op == 2))
326 if (check_multiply_halfregs (aa, ab) < 0)
331 /* Only one of the assign_macfuncs has a half reg multiply
332 Evil trick: Just 'OR' their source register codes:
333 We can do that, because we know they were initialized to 0
334 in the rules that don't use multiply_halfregs. */
335 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
336 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
339 if (aa->w == ab->w && aa->P != ab->P)
341 return yyerror ("macfuncs must differ");
342 if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
343 return yyerror ("Destination Dregs must differ by one");
346 /* Make sure mod flags get ORed, too. */
347 opb->mod |= opa->mod;
350 if (check_macfunc_option (aa, opb) < 0
351 && check_macfunc_option (ab, opb) < 0)
352 return yyerror ("bad option");
354 /* Make sure first macfunc has got both P flags ORed. */
362 is_group1 (INSTR_T x)
364 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
365 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
372 is_group2 (INSTR_T x)
374 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
375 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
376 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
377 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
378 || (x->value == 0x0000))
389 if ((x->value & 0xf000) == 0x8000)
391 int aop = ((x->value >> 9) & 0x3);
392 int w = ((x->value >> 11) & 0x1);
398 if (((x->value & 0xFF60) == 0x9E60) || /* dagMODim_0 */
399 ((x->value & 0xFFF0) == 0x9F60)) /* dagMODik_0 */
402 /* decode_dspLDST_0 */
403 if ((x->value & 0xFC00) == 0x9C00)
405 int w = ((x->value >> 9) & 0x1);
414 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
416 int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
417 int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
418 int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
420 if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
421 yyerror ("resource conflict in multi-issue instruction");
423 /* Anomaly 05000074 */
424 if (ENABLE_AC_05000074
425 && dsp32 != NULL && dsp16_grp1 != NULL
426 && (dsp32->value & 0xf780) == 0xc680
427 && ((dsp16_grp1->value & 0xfe40) == 0x9240
428 || (dsp16_grp1->value & 0xfe08) == 0xba08
429 || (dsp16_grp1->value & 0xfc00) == 0xbc00))
430 yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
431 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
433 if (is_store (dsp16_grp1) && is_store (dsp16_grp2))
434 yyerror ("Only one instruction in multi-issue instruction can be a store");
436 return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
448 struct { int r0; int s0; int x0; int aop; } modcodes;
449 struct { int r0; } r0;
456 /* Vector Specific. */
457 %token BYTEOP16P BYTEOP16M
458 %token BYTEOP1P BYTEOP2P BYTEOP3P
459 %token BYTEUNPACK BYTEPACK
462 %token ALIGN8 ALIGN16 ALIGN24
464 %token EXTRACT DEPOSIT EXPADJ SEARCH
465 %token ONES SIGN SIGNBITS
473 %token CCREG BYTE_DREG
474 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
475 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
480 %token RTI RTS RTX RTN RTE
491 %token JUMP JUMP_DOT_S JUMP_DOT_L
498 %token NOT TILDA BANG
504 %token MINUS PLUS STAR SLASH
508 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
509 %token _MINUS_MINUS _PLUS_PLUS
511 /* Shift/rotate ops. */
512 %token SHIFT LSHIFT ASHIFT BXORSHIFT
513 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
515 %token LESS_LESS GREATER_GREATER
516 %token _GREATER_GREATER_GREATER
517 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
520 /* In place operators. */
521 %token ASSIGN _STAR_ASSIGN
522 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
523 %token _MINUS_ASSIGN _PLUS_ASSIGN
525 /* Assignments, comparisons. */
526 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
531 %token FLUSHINV FLUSH
532 %token IFLUSH PREFETCH
549 %token R RND RNDL RNDH RND12 RND20
554 %token BITTGL BITCLR BITSET BITTST BITMUX
557 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
559 /* Semantic auxiliaries. */
562 %token COLON SEMICOLON
563 %token RPAREN LPAREN LBRACK RBRACK
567 %token GOT GOT17M4 FUNCDESC_GOT17M4
577 %type <modcodes> byteop_mod
579 %type <reg> a_plusassign
580 %type <reg> a_minusassign
581 %type <macfunc> multiply_halfregs
582 %type <macfunc> assign_macfunc
583 %type <macfunc> a_macfunc
587 %type <modcodes> vsmod
588 %type <modcodes> ccstat
591 %type <reg> reg_with_postinc
592 %type <reg> reg_with_predec
596 %type <symbol> SYMBOL
599 %type <reg> BYTE_DREG
600 %type <reg> REG_A_DOUBLE_ZERO
601 %type <reg> REG_A_DOUBLE_ONE
603 %type <reg> STATUS_REG
607 %type <modcodes> smod
608 %type <modcodes> b3_op
609 %type <modcodes> rnd_op
610 %type <modcodes> post_op
612 %type <r0> iu_or_nothing
613 %type <r0> plus_minus
617 %type <modcodes> amod0
618 %type <modcodes> amod1
619 %type <modcodes> amod2
621 %type <r0> w32_or_nothing
625 %type <expr> got_or_expr
627 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
629 /* Precedence rules. */
633 %left LESS_LESS GREATER_GREATER
635 %left STAR SLASH PERCENT
646 if (insn == (INSTR_T) 0)
647 return NO_INSN_GENERATED;
648 else if (insn == (INSTR_T) - 1)
649 return SEMANTIC_ERROR;
651 return INSN_GENERATED;
656 /* Parallel instructions. */
657 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
659 if (($1->value & 0xf800) == 0xc000)
661 if (is_group1 ($3) && is_group2 ($5))
662 $$ = gen_multi_instr_1 ($1, $3, $5);
663 else if (is_group2 ($3) && is_group1 ($5))
664 $$ = gen_multi_instr_1 ($1, $5, $3);
666 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
668 else if (($3->value & 0xf800) == 0xc000)
670 if (is_group1 ($1) && is_group2 ($5))
671 $$ = gen_multi_instr_1 ($3, $1, $5);
672 else if (is_group2 ($1) && is_group1 ($5))
673 $$ = gen_multi_instr_1 ($3, $5, $1);
675 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
677 else if (($5->value & 0xf800) == 0xc000)
679 if (is_group1 ($1) && is_group2 ($3))
680 $$ = gen_multi_instr_1 ($5, $1, $3);
681 else if (is_group2 ($1) && is_group1 ($3))
682 $$ = gen_multi_instr_1 ($5, $3, $1);
684 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
687 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
690 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
692 if (($1->value & 0xf800) == 0xc000)
695 $$ = gen_multi_instr_1 ($1, $3, 0);
696 else if (is_group2 ($3))
697 $$ = gen_multi_instr_1 ($1, 0, $3);
699 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
701 else if (($3->value & 0xf800) == 0xc000)
704 $$ = gen_multi_instr_1 ($3, $1, 0);
705 else if (is_group2 ($1))
706 $$ = gen_multi_instr_1 ($3, 0, $1);
708 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
710 else if (is_group1 ($1) && is_group2 ($3))
711 $$ = gen_multi_instr_1 (0, $1, $3);
712 else if (is_group2 ($1) && is_group1 ($3))
713 $$ = gen_multi_instr_1 (0, $3, $1);
715 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
730 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
732 | assign_macfunc opt_mode
736 int h00, h10, h01, h11;
738 if (check_macfunc_option (&$1, &$2) < 0)
739 return yyerror ("bad option");
744 return yyerror ("(m) not allowed with a0 unit");
763 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
764 &$1.dst, op0, &$1.s0, &$1.s1, w0);
770 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
774 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
776 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
783 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
784 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
785 dst, $4.op, &$1.s0, &$1.s1, $4.w);
792 notethat ("dsp32alu: DISALGNEXCPT\n");
793 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
795 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
797 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
799 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
800 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
803 return yyerror ("Register mismatch");
805 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
807 if (!IS_A1 ($4) && IS_A1 ($5))
809 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
810 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
813 return yyerror ("Register mismatch");
815 | A_ZERO_DOT_H ASSIGN HALF_REG
817 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
818 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
820 | A_ONE_DOT_H ASSIGN HALF_REG
822 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
823 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
825 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
826 COLON expr COMMA REG COLON expr RPAREN aligndir
828 if (!IS_DREG ($2) || !IS_DREG ($4))
829 return yyerror ("Dregs expected");
830 else if (!valid_dreg_pair (&$9, $11))
831 return yyerror ("Bad dreg pair");
832 else if (!valid_dreg_pair (&$13, $15))
833 return yyerror ("Bad dreg pair");
836 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (aligndir)\n");
837 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
841 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
842 REG COLON expr RPAREN aligndir
844 if (!IS_DREG ($2) || !IS_DREG ($4))
845 return yyerror ("Dregs expected");
846 else if (!valid_dreg_pair (&$9, $11))
847 return yyerror ("Bad dreg pair");
848 else if (!valid_dreg_pair (&$13, $15))
849 return yyerror ("Bad dreg pair");
852 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
853 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
857 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
859 if (!IS_DREG ($2) || !IS_DREG ($4))
860 return yyerror ("Dregs expected");
861 else if (!valid_dreg_pair (&$8, $10))
862 return yyerror ("Bad dreg pair");
865 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
866 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
869 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
871 if (REG_SAME ($2, $4))
872 return yyerror ("Illegal dest register combination");
874 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
876 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
877 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
880 return yyerror ("Register mismatch");
882 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
883 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
885 if (IS_DREG ($1) && IS_DREG ($7))
887 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
888 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
891 return yyerror ("Register mismatch");
895 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
897 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
898 && IS_A1 ($9) && !IS_A1 ($11))
900 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
901 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
904 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
905 && !IS_A1 ($9) && IS_A1 ($11))
907 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
908 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
911 return yyerror ("Register mismatch");
914 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
917 return yyerror ("Operators must differ");
919 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
920 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
922 notethat ("dsp32alu: dregs = dregs + dregs,"
923 "dregs = dregs - dregs (amod1)\n");
924 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
927 return yyerror ("Register mismatch");
930 /* Bar Operations. */
932 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
934 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
935 return yyerror ("Differing source registers");
937 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
938 return yyerror ("Dregs expected");
941 if ($4.r0 == 1 && $10.r0 == 2)
943 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
944 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
946 else if ($4.r0 == 0 && $10.r0 == 3)
948 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
949 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
952 return yyerror ("Bar operand mismatch");
955 | REG ASSIGN ABS REG vmod
959 if (IS_DREG ($1) && IS_DREG ($4))
963 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
968 /* Vector version of ABS. */
969 notethat ("dsp32alu: dregs = ABS dregs\n");
972 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
975 return yyerror ("Dregs expected");
979 notethat ("dsp32alu: Ax = ABS Ax\n");
980 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
982 | A_ZERO_DOT_L ASSIGN HALF_REG
986 notethat ("dsp32alu: A0.l = reg_half\n");
987 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
990 return yyerror ("A0.l = Rx.l expected");
992 | A_ONE_DOT_L ASSIGN HALF_REG
996 notethat ("dsp32alu: A1.l = reg_half\n");
997 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
1000 return yyerror ("A1.l = Rx.l expected");
1003 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
1005 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1007 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
1008 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
1011 return yyerror ("Dregs expected");
1014 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
1017 return yyerror ("Dregs expected");
1018 else if (!valid_dreg_pair (&$5, $7))
1019 return yyerror ("Bad dreg pair");
1020 else if (!valid_dreg_pair (&$9, $11))
1021 return yyerror ("Bad dreg pair");
1024 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1025 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
1028 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1031 return yyerror ("Dregs expected");
1032 else if (!valid_dreg_pair (&$5, $7))
1033 return yyerror ("Bad dreg pair");
1034 else if (!valid_dreg_pair (&$9, $11))
1035 return yyerror ("Bad dreg pair");
1038 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1039 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1043 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1047 return yyerror ("Dregs expected");
1048 else if (!valid_dreg_pair (&$5, $7))
1049 return yyerror ("Bad dreg pair");
1050 else if (!valid_dreg_pair (&$9, $11))
1051 return yyerror ("Bad dreg pair");
1054 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1055 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1059 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1063 return yyerror ("Dregs expected");
1064 else if (!valid_dreg_pair (&$5, $7))
1065 return yyerror ("Bad dreg pair");
1066 else if (!valid_dreg_pair (&$9, $11))
1067 return yyerror ("Bad dreg pair");
1070 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1071 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1075 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1077 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1079 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1080 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1083 return yyerror ("Dregs expected");
1086 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1087 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1089 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1091 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1092 "SIGN (dregs_hi) * dregs_hi + "
1093 "SIGN (dregs_lo) * dregs_lo \n");
1095 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1098 return yyerror ("Dregs expected");
1100 | REG ASSIGN REG plus_minus REG amod1
1102 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1106 /* No saturation flag specified, generate the 16 bit variant. */
1107 notethat ("COMP3op: dregs = dregs +- dregs\n");
1108 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1112 /* Saturation flag specified, generate the 32 bit variant. */
1113 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1114 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1118 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1120 notethat ("COMP3op: pregs = pregs + pregs\n");
1121 $$ = COMP3OP (&$1, &$3, &$5, 5);
1124 return yyerror ("Dregs expected");
1126 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1130 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1137 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1138 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1141 return yyerror ("Dregs expected");
1144 | a_assign MINUS REG_A
1146 notethat ("dsp32alu: Ax = - Ax\n");
1147 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1149 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1151 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1152 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1153 $6.s0, $6.x0, HL2 ($3, $5));
1155 | a_assign a_assign expr
1157 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1159 notethat ("dsp32alu: A1 = A0 = 0\n");
1160 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1163 return yyerror ("Bad value, 0 expected");
1167 | a_assign REG_A LPAREN S RPAREN
1169 if (REG_SAME ($1, $2))
1171 notethat ("dsp32alu: Ax = Ax (S)\n");
1172 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1175 return yyerror ("Registers must be equal");
1178 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1182 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1183 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1186 return yyerror ("Dregs expected");
1189 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1191 if (IS_DREG ($3) && IS_DREG ($5))
1193 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1194 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1197 return yyerror ("Dregs expected");
1200 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1202 if (IS_DREG ($3) && IS_DREG ($5))
1204 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1205 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1208 return yyerror ("Dregs expected");
1213 if (!REG_SAME ($1, $2))
1215 notethat ("dsp32alu: An = Am\n");
1216 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1219 return yyerror ("Accu reg arguments must differ");
1226 notethat ("dsp32alu: An = dregs\n");
1227 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1230 return yyerror ("Dregs expected");
1233 | REG ASSIGN HALF_REG xpmod
1237 if ($1.regno == REG_A0x && IS_DREG ($3))
1239 notethat ("dsp32alu: A0.x = dregs_lo\n");
1240 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1242 else if ($1.regno == REG_A1x && IS_DREG ($3))
1244 notethat ("dsp32alu: A1.x = dregs_lo\n");
1245 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1247 else if (IS_DREG ($1) && IS_DREG ($3))
1249 notethat ("ALU2op: dregs = dregs_lo\n");
1250 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1253 return yyerror ("Register mismatch");
1256 return yyerror ("Low reg expected");
1259 | HALF_REG ASSIGN expr
1261 notethat ("LDIMMhalf: pregs_half = imm16\n");
1263 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1264 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1265 return yyerror ("Wrong register for load immediate");
1267 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1268 return yyerror ("Constant out of range");
1270 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1275 notethat ("dsp32alu: An = 0\n");
1278 return yyerror ("0 expected");
1280 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1283 | REG ASSIGN expr xpmod1
1285 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1286 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1287 return yyerror ("Wrong register for load immediate");
1291 /* 7 bit immediate value if possible.
1292 We will check for that constant value for efficiency
1293 If it goes to reloc, it will be 16 bit. */
1294 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1296 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1297 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1299 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1301 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1302 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1306 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1307 return yyerror ("Immediate value out of range");
1309 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1311 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1316 /* (z) There is no 7 bit zero extended instruction.
1317 If the expr is a relocation, generate it. */
1319 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1320 return yyerror ("Immediate value out of range");
1322 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1324 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1328 | HALF_REG ASSIGN REG
1331 return yyerror ("Low reg expected");
1333 if (IS_DREG ($1) && $3.regno == REG_A0x)
1335 notethat ("dsp32alu: dregs_lo = A0.x\n");
1336 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1338 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1340 notethat ("dsp32alu: dregs_lo = A1.x\n");
1341 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1344 return yyerror ("Register mismatch");
1347 | REG ASSIGN REG op_bar_op REG amod0
1349 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1351 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1352 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1355 return yyerror ("Register mismatch");
1358 | REG ASSIGN BYTE_DREG xpmod
1360 if (IS_DREG ($1) && IS_DREG ($3))
1362 notethat ("ALU2op: dregs = dregs_byte\n");
1363 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1366 return yyerror ("Register mismatch");
1369 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1371 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1373 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1374 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1377 return yyerror ("Register mismatch");
1380 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1382 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1384 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1385 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1388 return yyerror ("Register mismatch");
1391 | a_minusassign REG_A w32_or_nothing
1393 if (!IS_A1 ($1) && IS_A1 ($2))
1395 notethat ("dsp32alu: A0 -= A1\n");
1396 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1399 return yyerror ("Register mismatch");
1402 | REG _MINUS_ASSIGN expr
1404 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1406 notethat ("dagMODik: iregs -= 4\n");
1407 $$ = DAGMODIK (&$1, 3);
1409 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1411 notethat ("dagMODik: iregs -= 2\n");
1412 $$ = DAGMODIK (&$1, 1);
1415 return yyerror ("Register or value mismatch");
1418 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1420 if (IS_IREG ($1) && IS_MREG ($3))
1422 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1424 $$ = DAGMODIM (&$1, &$3, 0, 1);
1426 else if (IS_PREG ($1) && IS_PREG ($3))
1428 notethat ("PTR2op: pregs += pregs (BREV )\n");
1429 $$ = PTR2OP (&$1, &$3, 5);
1432 return yyerror ("Register mismatch");
1435 | REG _MINUS_ASSIGN REG
1437 if (IS_IREG ($1) && IS_MREG ($3))
1439 notethat ("dagMODim: iregs -= mregs\n");
1440 $$ = DAGMODIM (&$1, &$3, 1, 0);
1442 else if (IS_PREG ($1) && IS_PREG ($3))
1444 notethat ("PTR2op: pregs -= pregs\n");
1445 $$ = PTR2OP (&$1, &$3, 0);
1448 return yyerror ("Register mismatch");
1451 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1453 if (!IS_A1 ($1) && IS_A1 ($3))
1455 notethat ("dsp32alu: A0 += A1 (W32)\n");
1456 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1459 return yyerror ("Register mismatch");
1462 | REG _PLUS_ASSIGN REG
1464 if (IS_IREG ($1) && IS_MREG ($3))
1466 notethat ("dagMODim: iregs += mregs\n");
1467 $$ = DAGMODIM (&$1, &$3, 0, 0);
1470 return yyerror ("iregs += mregs expected");
1473 | REG _PLUS_ASSIGN expr
1477 if (EXPR_VALUE ($3) == 4)
1479 notethat ("dagMODik: iregs += 4\n");
1480 $$ = DAGMODIK (&$1, 2);
1482 else if (EXPR_VALUE ($3) == 2)
1484 notethat ("dagMODik: iregs += 2\n");
1485 $$ = DAGMODIK (&$1, 0);
1488 return yyerror ("iregs += [ 2 | 4 ");
1490 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1492 notethat ("COMPI2opP: pregs += imm7\n");
1493 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1495 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1497 notethat ("COMPI2opD: dregs += imm7\n");
1498 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1500 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1501 return yyerror ("Immediate value out of range");
1503 return yyerror ("Register mismatch");
1506 | REG _STAR_ASSIGN REG
1508 if (IS_DREG ($1) && IS_DREG ($3))
1510 notethat ("ALU2op: dregs *= dregs\n");
1511 $$ = ALU2OP (&$1, &$3, 3);
1514 return yyerror ("Register mismatch");
1517 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1519 if (!valid_dreg_pair (&$3, $5))
1520 return yyerror ("Bad dreg pair");
1521 else if (!valid_dreg_pair (&$7, $9))
1522 return yyerror ("Bad dreg pair");
1525 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1526 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1530 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1532 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1534 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1535 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1538 return yyerror ("Register mismatch");
1541 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1543 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1544 && REG_SAME ($1, $4))
1546 if (EXPR_VALUE ($9) == 1)
1548 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1549 $$ = ALU2OP (&$1, &$6, 4);
1551 else if (EXPR_VALUE ($9) == 2)
1553 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1554 $$ = ALU2OP (&$1, &$6, 5);
1557 return yyerror ("Bad shift value");
1559 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1560 && REG_SAME ($1, $4))
1562 if (EXPR_VALUE ($9) == 1)
1564 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1565 $$ = PTR2OP (&$1, &$6, 6);
1567 else if (EXPR_VALUE ($9) == 2)
1569 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1570 $$ = PTR2OP (&$1, &$6, 7);
1573 return yyerror ("Bad shift value");
1576 return yyerror ("Register mismatch");
1580 | REG ASSIGN REG BAR REG
1582 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1584 notethat ("COMP3op: dregs = dregs | dregs\n");
1585 $$ = COMP3OP (&$1, &$3, &$5, 3);
1588 return yyerror ("Dregs expected");
1590 | REG ASSIGN REG CARET REG
1592 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1594 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1595 $$ = COMP3OP (&$1, &$3, &$5, 4);
1598 return yyerror ("Dregs expected");
1600 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1602 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1604 if (EXPR_VALUE ($8) == 1)
1606 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1607 $$ = COMP3OP (&$1, &$3, &$6, 6);
1609 else if (EXPR_VALUE ($8) == 2)
1611 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1612 $$ = COMP3OP (&$1, &$3, &$6, 7);
1615 return yyerror ("Bad shift value");
1618 return yyerror ("Dregs expected");
1620 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1622 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1624 notethat ("CCflag: CC = A0 == A1\n");
1625 $$ = CCFLAG (0, 0, 5, 0, 0);
1628 return yyerror ("AREGs are in bad order or same");
1630 | CCREG ASSIGN REG_A LESS_THAN REG_A
1632 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1634 notethat ("CCflag: CC = A0 < A1\n");
1635 $$ = CCFLAG (0, 0, 6, 0, 0);
1638 return yyerror ("AREGs are in bad order or same");
1640 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1642 if ((IS_DREG ($3) && IS_DREG ($5))
1643 || (IS_PREG ($3) && IS_PREG ($5)))
1645 notethat ("CCflag: CC = dpregs < dpregs\n");
1646 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1649 return yyerror ("Bad register in comparison");
1651 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1653 if (!IS_DREG ($3) && !IS_PREG ($3))
1654 return yyerror ("Bad register in comparison");
1656 if (($6.r0 == 1 && IS_IMM ($5, 3))
1657 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1659 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1660 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1663 return yyerror ("Bad constant value");
1665 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1667 if ((IS_DREG ($3) && IS_DREG ($5))
1668 || (IS_PREG ($3) && IS_PREG ($5)))
1670 notethat ("CCflag: CC = dpregs == dpregs\n");
1671 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1674 return yyerror ("Bad register in comparison");
1676 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1678 if (!IS_DREG ($3) && !IS_PREG ($3))
1679 return yyerror ("Bad register in comparison");
1683 notethat ("CCflag: CC = dpregs == imm3\n");
1684 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1687 return yyerror ("Bad constant range");
1689 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1691 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1693 notethat ("CCflag: CC = A0 <= A1\n");
1694 $$ = CCFLAG (0, 0, 7, 0, 0);
1697 return yyerror ("AREGs are in bad order or same");
1699 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1701 if ((IS_DREG ($3) && IS_DREG ($5))
1702 || (IS_PREG ($3) && IS_PREG ($5)))
1704 notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
1705 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1706 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1709 return yyerror ("Bad register in comparison");
1711 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1713 if (!IS_DREG ($3) && !IS_PREG ($3))
1714 return yyerror ("Bad register in comparison");
1716 if (($6.r0 == 1 && IS_IMM ($5, 3))
1717 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1719 notethat ("CCflag: CC = dpregs <= (u)imm3\n");
1720 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1723 return yyerror ("Bad constant value");
1726 | REG ASSIGN REG AMPERSAND REG
1728 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1730 notethat ("COMP3op: dregs = dregs & dregs\n");
1731 $$ = COMP3OP (&$1, &$3, &$5, 2);
1734 return yyerror ("Dregs expected");
1739 notethat ("CC2stat operation\n");
1740 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1745 if ((IS_GENREG ($1) && IS_GENREG ($3))
1746 || (IS_GENREG ($1) && IS_DAGREG ($3))
1747 || (IS_DAGREG ($1) && IS_GENREG ($3))
1748 || (IS_DAGREG ($1) && IS_DAGREG ($3))
1749 || (IS_GENREG ($1) && $3.regno == REG_USP)
1750 || ($1.regno == REG_USP && IS_GENREG ($3))
1751 || ($1.regno == REG_USP && $3.regno == REG_USP)
1752 || (IS_DREG ($1) && IS_SYSREG ($3))
1753 || (IS_PREG ($1) && IS_SYSREG ($3))
1754 || (IS_SYSREG ($1) && IS_GENREG ($3))
1755 || (IS_ALLREG ($1) && IS_EMUDAT ($3))
1756 || (IS_EMUDAT ($1) && IS_ALLREG ($3))
1757 || (IS_SYSREG ($1) && $3.regno == REG_USP))
1759 $$ = bfin_gen_regmv (&$3, &$1);
1762 return yyerror ("Unsupported register move");
1769 notethat ("CC2dreg: CC = dregs\n");
1770 $$ = bfin_gen_cc2dreg (1, &$3);
1773 return yyerror ("Only 'CC = Dreg' supported");
1780 notethat ("CC2dreg: dregs = CC\n");
1781 $$ = bfin_gen_cc2dreg (0, &$1);
1784 return yyerror ("Only 'Dreg = CC' supported");
1787 | CCREG _ASSIGN_BANG CCREG
1789 notethat ("CC2dreg: CC =! CC\n");
1790 $$ = bfin_gen_cc2dreg (3, 0);
1795 | HALF_REG ASSIGN multiply_halfregs opt_mode
1797 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1799 if (!IS_H ($1) && $4.MM)
1800 return yyerror ("(M) not allowed with MAC0");
1802 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1803 && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1804 && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1805 return yyerror ("bad option.");
1809 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1810 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1811 &$1, 0, &$3.s0, &$3.s1, 0);
1815 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1816 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1817 &$1, 0, &$3.s0, &$3.s1, 1);
1821 | REG ASSIGN multiply_halfregs opt_mode
1823 /* Odd registers can use (M). */
1825 return yyerror ("Dreg expected");
1827 if (IS_EVEN ($1) && $4.MM)
1828 return yyerror ("(M) not allowed with MAC0");
1830 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1831 && $4.mod != M_S2RND && $4.mod != M_ISS2)
1832 return yyerror ("bad option");
1836 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1838 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1839 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1840 &$1, 0, &$3.s0, &$3.s1, 0);
1844 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1845 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1846 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1847 &$1, 0, &$3.s0, &$3.s1, 1);
1851 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1852 HALF_REG ASSIGN multiply_halfregs opt_mode
1854 if (!IS_DREG ($1) || !IS_DREG ($6))
1855 return yyerror ("Dregs expected");
1857 if (!IS_HCOMPL($1, $6))
1858 return yyerror ("Dest registers mismatch");
1860 if (check_multiply_halfregs (&$3, &$8) < 0)
1863 if ((!IS_H ($1) && $4.MM)
1864 || (!IS_H ($6) && $9.MM))
1865 return yyerror ("(M) not allowed with MAC0");
1867 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1868 "dregs_lo = multiply_halfregs opt_mode\n");
1871 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1872 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1873 &$1, 0, &$3.s0, &$3.s1, 1);
1875 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1876 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1877 &$1, 0, &$3.s0, &$3.s1, 1);
1880 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1882 if (!IS_DREG ($1) || !IS_DREG ($6))
1883 return yyerror ("Dregs expected");
1885 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1886 || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1887 return yyerror ("Dest registers mismatch");
1889 if (check_multiply_halfregs (&$3, &$8) < 0)
1892 if ((IS_EVEN ($1) && $4.MM)
1893 || (IS_EVEN ($6) && $9.MM))
1894 return yyerror ("(M) not allowed with MAC0");
1896 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1897 "dregs = multiply_halfregs opt_mode\n");
1900 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1901 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1902 &$1, 0, &$3.s0, &$3.s1, 1);
1904 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1905 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1906 &$1, 0, &$3.s0, &$3.s1, 1);
1911 | a_assign ASHIFT REG_A BY HALF_REG
1913 if (!REG_SAME ($1, $3))
1914 return yyerror ("Aregs must be same");
1916 if (IS_DREG ($5) && !IS_H ($5))
1918 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1919 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1922 return yyerror ("Dregs expected");
1925 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1927 if (IS_DREG ($6) && !IS_H ($6))
1929 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1930 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1933 return yyerror ("Dregs expected");
1936 | a_assign REG_A LESS_LESS expr
1938 if (!REG_SAME ($1, $2))
1939 return yyerror ("Aregs must be same");
1941 if (IS_UIMM ($4, 5))
1943 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1944 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1947 return yyerror ("Bad shift value");
1950 | REG ASSIGN REG LESS_LESS expr vsmod
1952 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1957 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1958 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1962 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1963 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1966 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1968 if (EXPR_VALUE ($5) == 2)
1970 notethat ("PTR2op: pregs = pregs << 2\n");
1971 $$ = PTR2OP (&$1, &$3, 1);
1973 else if (EXPR_VALUE ($5) == 1)
1975 notethat ("COMP3op: pregs = pregs << 1\n");
1976 $$ = COMP3OP (&$1, &$3, &$3, 5);
1979 return yyerror ("Bad shift value");
1982 return yyerror ("Bad shift value or register");
1984 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1986 if (IS_UIMM ($5, 4))
1990 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
1991 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1995 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1996 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
2000 return yyerror ("Bad shift value");
2002 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
2006 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
2011 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
2012 "dregs_lo (V, .)\n");
2018 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
2020 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
2023 return yyerror ("Dregs expected");
2027 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2029 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2031 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2032 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2035 return yyerror ("Bad shift value or register");
2039 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2041 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2043 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2044 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2046 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2048 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2049 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2052 return yyerror ("Bad shift value or register");
2057 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2059 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2061 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2062 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2065 return yyerror ("Register mismatch");
2068 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2070 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2072 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2073 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2076 return yyerror ("Register mismatch");
2079 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2081 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2083 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2084 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2087 return yyerror ("Register mismatch");
2090 | a_assign REG_A _GREATER_GREATER_GREATER expr
2092 if (!REG_SAME ($1, $2))
2093 return yyerror ("Aregs must be same");
2095 if (IS_UIMM ($4, 5))
2097 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2098 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2101 return yyerror ("Shift value range error");
2103 | a_assign LSHIFT REG_A BY HALF_REG
2105 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2107 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2108 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2111 return yyerror ("Register mismatch");
2114 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2116 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2118 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2119 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2122 return yyerror ("Register mismatch");
2125 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2127 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2129 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2130 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2133 return yyerror ("Register mismatch");
2136 | REG ASSIGN SHIFT REG BY HALF_REG
2138 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2140 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2141 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2144 return yyerror ("Register mismatch");
2147 | a_assign REG_A GREATER_GREATER expr
2149 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2151 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2152 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2155 return yyerror ("Accu register expected");
2158 | REG ASSIGN REG GREATER_GREATER expr vmod
2162 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2164 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2165 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2168 return yyerror ("Register mismatch");
2172 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2174 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2175 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2177 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2179 notethat ("PTR2op: pregs = pregs >> 2\n");
2180 $$ = PTR2OP (&$1, &$3, 3);
2182 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2184 notethat ("PTR2op: pregs = pregs >> 1\n");
2185 $$ = PTR2OP (&$1, &$3, 4);
2188 return yyerror ("Register mismatch");
2191 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2193 if (IS_UIMM ($5, 5))
2195 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2196 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2199 return yyerror ("Register mismatch");
2201 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2203 if (IS_UIMM ($5, 5))
2205 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2206 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2207 $6.s0, HL2 ($1, $3));
2210 return yyerror ("Register or modifier mismatch");
2214 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2216 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2221 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2222 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2226 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2227 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2231 return yyerror ("Register mismatch");
2234 | HALF_REG ASSIGN ONES REG
2236 if (IS_DREG_L ($1) && IS_DREG ($4))
2238 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2239 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2242 return yyerror ("Register mismatch");
2245 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2247 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2249 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2250 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2253 return yyerror ("Register mismatch");
2256 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2259 && $7.regno == REG_A0
2260 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2262 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2263 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2266 return yyerror ("Register mismatch");
2269 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2272 && $7.regno == REG_A0
2273 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2275 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2276 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2279 return yyerror ("Register mismatch");
2282 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2284 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2286 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2287 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2290 return yyerror ("Register mismatch");
2293 | a_assign ROT REG_A BY HALF_REG
2295 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2297 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2298 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2301 return yyerror ("Register mismatch");
2304 | REG ASSIGN ROT REG BY HALF_REG
2306 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2308 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2309 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2312 return yyerror ("Register mismatch");
2315 | a_assign ROT REG_A BY expr
2319 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2320 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2323 return yyerror ("Register mismatch");
2326 | REG ASSIGN ROT REG BY expr
2328 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2330 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2333 return yyerror ("Register mismatch");
2336 | HALF_REG ASSIGN SIGNBITS REG_A
2340 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2341 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2344 return yyerror ("Register mismatch");
2347 | HALF_REG ASSIGN SIGNBITS REG
2349 if (IS_DREG_L ($1) && IS_DREG ($4))
2351 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2352 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2355 return yyerror ("Register mismatch");
2358 | HALF_REG ASSIGN SIGNBITS HALF_REG
2362 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2363 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2366 return yyerror ("Register mismatch");
2369 /* The ASR bit is just inverted here. */
2370 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2372 if (IS_DREG_L ($1) && IS_DREG ($5))
2374 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2375 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2378 return yyerror ("Register mismatch");
2381 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2383 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2385 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2386 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2389 return yyerror ("Register mismatch");
2392 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2394 if (REG_SAME ($3, $5))
2395 return yyerror ("Illegal source register combination");
2397 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2399 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2400 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2403 return yyerror ("Register mismatch");
2406 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2408 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2410 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2411 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2414 return yyerror ("Dregs expected");
2418 /* LOGI2op: BITCLR (dregs, uimm5). */
2419 | BITCLR LPAREN REG COMMA expr RPAREN
2421 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2423 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2424 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2427 return yyerror ("Register mismatch");
2430 /* LOGI2op: BITSET (dregs, uimm5). */
2431 | BITSET LPAREN REG COMMA expr RPAREN
2433 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2435 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2436 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2439 return yyerror ("Register mismatch");
2442 /* LOGI2op: BITTGL (dregs, uimm5). */
2443 | BITTGL LPAREN REG COMMA expr RPAREN
2445 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2447 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2448 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2451 return yyerror ("Register mismatch");
2454 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2456 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2458 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2459 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2462 return yyerror ("Register mismatch or value error");
2465 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2467 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2469 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2470 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2473 return yyerror ("Register mismatch or value error");
2476 | IF BANG CCREG REG ASSIGN REG
2478 if ((IS_DREG ($4) || IS_PREG ($4))
2479 && (IS_DREG ($6) || IS_PREG ($6)))
2481 notethat ("ccMV: IF ! CC gregs = gregs\n");
2482 $$ = CCMV (&$6, &$4, 0);
2485 return yyerror ("Register mismatch");
2488 | IF CCREG REG ASSIGN REG
2490 if ((IS_DREG ($5) || IS_PREG ($5))
2491 && (IS_DREG ($3) || IS_PREG ($3)))
2493 notethat ("ccMV: IF CC gregs = gregs\n");
2494 $$ = CCMV (&$5, &$3, 1);
2497 return yyerror ("Register mismatch");
2500 | IF BANG CCREG JUMP expr
2502 if (IS_PCREL10 ($5))
2504 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2505 $$ = BRCC (0, 0, $5);
2508 return yyerror ("Bad jump offset");
2511 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2513 if (IS_PCREL10 ($5))
2515 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2516 $$ = BRCC (0, 1, $5);
2519 return yyerror ("Bad jump offset");
2522 | IF CCREG JUMP expr
2524 if (IS_PCREL10 ($4))
2526 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2527 $$ = BRCC (1, 0, $4);
2530 return yyerror ("Bad jump offset");
2533 | IF CCREG JUMP expr LPAREN BP RPAREN
2535 if (IS_PCREL10 ($4))
2537 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2538 $$ = BRCC (1, 1, $4);
2541 return yyerror ("Bad jump offset");
2545 notethat ("ProgCtrl: NOP\n");
2546 $$ = PROGCTRL (0, 0);
2551 notethat ("ProgCtrl: RTS\n");
2552 $$ = PROGCTRL (1, 0);
2557 notethat ("ProgCtrl: RTI\n");
2558 $$ = PROGCTRL (1, 1);
2563 notethat ("ProgCtrl: RTX\n");
2564 $$ = PROGCTRL (1, 2);
2569 notethat ("ProgCtrl: RTN\n");
2570 $$ = PROGCTRL (1, 3);
2575 notethat ("ProgCtrl: RTE\n");
2576 $$ = PROGCTRL (1, 4);
2581 notethat ("ProgCtrl: IDLE\n");
2582 $$ = PROGCTRL (2, 0);
2587 notethat ("ProgCtrl: CSYNC\n");
2588 $$ = PROGCTRL (2, 3);
2593 notethat ("ProgCtrl: SSYNC\n");
2594 $$ = PROGCTRL (2, 4);
2599 notethat ("ProgCtrl: EMUEXCPT\n");
2600 $$ = PROGCTRL (2, 5);
2607 notethat ("ProgCtrl: CLI dregs\n");
2608 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2611 return yyerror ("Dreg expected for CLI");
2618 notethat ("ProgCtrl: STI dregs\n");
2619 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2622 return yyerror ("Dreg expected for STI");
2625 | JUMP LPAREN REG RPAREN
2629 notethat ("ProgCtrl: JUMP (pregs )\n");
2630 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2633 return yyerror ("Bad register for indirect jump");
2636 | CALL LPAREN REG RPAREN
2640 notethat ("ProgCtrl: CALL (pregs )\n");
2641 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2644 return yyerror ("Bad register for indirect call");
2647 | CALL LPAREN PC PLUS REG RPAREN
2651 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2652 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2655 return yyerror ("Bad register for indirect call");
2658 | JUMP LPAREN PC PLUS REG RPAREN
2662 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2663 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2666 return yyerror ("Bad register for indirect jump");
2671 if (IS_UIMM ($2, 4))
2673 notethat ("ProgCtrl: RAISE uimm4\n");
2674 $$ = PROGCTRL (9, uimm4 ($2));
2677 return yyerror ("Bad value for RAISE");
2682 notethat ("ProgCtrl: EMUEXCPT\n");
2683 $$ = PROGCTRL (10, uimm4 ($2));
2686 | TESTSET LPAREN REG RPAREN
2690 if ($3.regno == REG_SP || $3.regno == REG_FP)
2691 return yyerror ("Bad register for TESTSET");
2693 notethat ("ProgCtrl: TESTSET (pregs )\n");
2694 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2697 return yyerror ("Preg expected");
2702 if (IS_PCREL12 ($2))
2704 notethat ("UJUMP: JUMP pcrel12\n");
2708 return yyerror ("Bad value for relative jump");
2713 if (IS_PCREL12 ($2))
2715 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2719 return yyerror ("Bad value for relative jump");
2724 if (IS_PCREL24 ($2))
2726 notethat ("CALLa: jump.l pcrel24\n");
2730 return yyerror ("Bad value for long jump");
2735 if (IS_PCREL24 ($2))
2737 notethat ("CALLa: jump.l pcrel24\n");
2741 return yyerror ("Bad value for long jump");
2746 if (IS_PCREL24 ($2))
2748 notethat ("CALLa: CALL pcrel25m2\n");
2752 return yyerror ("Bad call address");
2756 if (IS_PCREL24 ($2))
2758 notethat ("CALLa: CALL pcrel25m2\n");
2762 return yyerror ("Bad call address");
2766 /* ALU2op: DIVQ (dregs, dregs). */
2767 | DIVQ LPAREN REG COMMA REG RPAREN
2769 if (IS_DREG ($3) && IS_DREG ($5))
2770 $$ = ALU2OP (&$3, &$5, 8);
2772 return yyerror ("Bad registers for DIVQ");
2775 | DIVS LPAREN REG COMMA REG RPAREN
2777 if (IS_DREG ($3) && IS_DREG ($5))
2778 $$ = ALU2OP (&$3, &$5, 9);
2780 return yyerror ("Bad registers for DIVS");
2783 | REG ASSIGN MINUS REG vsmod
2785 if (IS_DREG ($1) && IS_DREG ($4))
2787 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2789 notethat ("ALU2op: dregs = - dregs\n");
2790 $$ = ALU2OP (&$1, &$4, 14);
2792 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2794 notethat ("dsp32alu: dregs = - dregs (.)\n");
2795 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2799 notethat ("dsp32alu: dregs = - dregs (.)\n");
2800 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2804 return yyerror ("Dregs expected");
2807 | REG ASSIGN TILDA REG
2809 if (IS_DREG ($1) && IS_DREG ($4))
2811 notethat ("ALU2op: dregs = ~dregs\n");
2812 $$ = ALU2OP (&$1, &$4, 15);
2815 return yyerror ("Dregs expected");
2818 | REG _GREATER_GREATER_ASSIGN REG
2820 if (IS_DREG ($1) && IS_DREG ($3))
2822 notethat ("ALU2op: dregs >>= dregs\n");
2823 $$ = ALU2OP (&$1, &$3, 1);
2826 return yyerror ("Dregs expected");
2829 | REG _GREATER_GREATER_ASSIGN expr
2831 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2833 notethat ("LOGI2op: dregs >>= uimm5\n");
2834 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2837 return yyerror ("Dregs expected or value error");
2840 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2842 if (IS_DREG ($1) && IS_DREG ($3))
2844 notethat ("ALU2op: dregs >>>= dregs\n");
2845 $$ = ALU2OP (&$1, &$3, 0);
2848 return yyerror ("Dregs expected");
2851 | REG _LESS_LESS_ASSIGN REG
2853 if (IS_DREG ($1) && IS_DREG ($3))
2855 notethat ("ALU2op: dregs <<= dregs\n");
2856 $$ = ALU2OP (&$1, &$3, 2);
2859 return yyerror ("Dregs expected");
2862 | REG _LESS_LESS_ASSIGN expr
2864 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2866 notethat ("LOGI2op: dregs <<= uimm5\n");
2867 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2870 return yyerror ("Dregs expected or const value error");
2874 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2876 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2878 notethat ("LOGI2op: dregs >>>= uimm5\n");
2879 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2882 return yyerror ("Dregs expected");
2885 /* Cache Control. */
2887 | FLUSH LBRACK REG RBRACK
2889 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2891 $$ = CACTRL (&$3, 0, 2);
2893 return yyerror ("Bad register(s) for FLUSH");
2896 | FLUSH reg_with_postinc
2900 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2901 $$ = CACTRL (&$2, 1, 2);
2904 return yyerror ("Bad register(s) for FLUSH");
2907 | FLUSHINV LBRACK REG RBRACK
2911 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2912 $$ = CACTRL (&$3, 0, 1);
2915 return yyerror ("Bad register(s) for FLUSH");
2918 | FLUSHINV reg_with_postinc
2922 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2923 $$ = CACTRL (&$2, 1, 1);
2926 return yyerror ("Bad register(s) for FLUSH");
2929 /* CaCTRL: IFLUSH [pregs]. */
2930 | IFLUSH LBRACK REG RBRACK
2934 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2935 $$ = CACTRL (&$3, 0, 3);
2938 return yyerror ("Bad register(s) for FLUSH");
2941 | IFLUSH reg_with_postinc
2945 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2946 $$ = CACTRL (&$2, 1, 3);
2949 return yyerror ("Bad register(s) for FLUSH");
2952 | PREFETCH LBRACK REG RBRACK
2956 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2957 $$ = CACTRL (&$3, 0, 0);
2960 return yyerror ("Bad register(s) for PREFETCH");
2963 | PREFETCH reg_with_postinc
2967 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2968 $$ = CACTRL (&$2, 1, 0);
2971 return yyerror ("Bad register(s) for PREFETCH");
2975 /* LDST: B [ pregs <post_op> ] = dregs. */
2977 | B LBRACK REG post_op RBRACK ASSIGN REG
2980 return yyerror ("Dreg expected for source operand");
2982 return yyerror ("Preg expected in address");
2984 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2985 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2988 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2989 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2991 Expr_Node *tmp = $5;
2994 return yyerror ("Dreg expected for source operand");
2996 return yyerror ("Preg expected in address");
2999 return yyerror ("Plain symbol used as offset");
3002 tmp = unary (Expr_Op_Type_NEG, tmp);
3004 if (in_range_p (tmp, -32768, 32767, 0))
3006 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
3007 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
3010 return yyerror ("Displacement out of range");
3014 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
3015 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
3017 Expr_Node *tmp = $5;
3020 return yyerror ("Dreg expected for source operand");
3022 return yyerror ("Preg expected in address");
3025 tmp = unary (Expr_Op_Type_NEG, tmp);
3028 return yyerror ("Plain symbol used as offset");
3030 if (in_range_p (tmp, 0, 30, 1))
3032 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
3033 $$ = LDSTII (&$3, &$8, tmp, 1, 1);
3035 else if (in_range_p (tmp, -65536, 65535, 1))
3037 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
3038 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp);
3041 return yyerror ("Displacement out of range");
3044 /* LDST: W [ pregs <post_op> ] = dregs. */
3045 | W LBRACK REG post_op RBRACK ASSIGN REG
3048 return yyerror ("Dreg expected for source operand");
3050 return yyerror ("Preg expected in address");
3052 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
3053 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
3056 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3059 return yyerror ("Dreg expected for source operand");
3062 if (!IS_IREG ($3) && !IS_PREG ($3))
3063 return yyerror ("Ireg or Preg expected in address");
3065 else if (!IS_IREG ($3))
3066 return yyerror ("Ireg expected in address");
3070 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3071 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3075 notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
3076 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3080 /* LDSTiiFP: [ FP - const ] = dpregs. */
3081 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3083 Expr_Node *tmp = $4;
3084 int ispreg = IS_PREG ($7);
3087 return yyerror ("Preg expected in address");
3089 if (!IS_DREG ($7) && !ispreg)
3090 return yyerror ("Preg expected for source operand");
3093 tmp = unary (Expr_Op_Type_NEG, tmp);
3096 return yyerror ("Plain symbol used as offset");
3098 if (in_range_p (tmp, 0, 63, 3))
3100 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3101 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3103 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3105 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3106 tmp = unary (Expr_Op_Type_NEG, tmp);
3107 $$ = LDSTIIFP (tmp, &$7, 1);
3109 else if (in_range_p (tmp, -131072, 131071, 3))
3111 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3112 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp);
3115 return yyerror ("Displacement out of range");
3118 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3120 Expr_Node *tmp = $7;
3122 return yyerror ("Dreg expected for destination operand");
3124 return yyerror ("Preg expected in address");
3127 tmp = unary (Expr_Op_Type_NEG, tmp);
3130 return yyerror ("Plain symbol used as offset");
3132 if (in_range_p (tmp, 0, 30, 1))
3134 notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3135 $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0);
3137 else if (in_range_p (tmp, -65536, 65535, 1))
3139 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3140 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp);
3143 return yyerror ("Displacement out of range");
3146 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3149 return yyerror ("Dreg expected for source operand");
3152 if (!IS_IREG ($5) && !IS_PREG ($5))
3153 return yyerror ("Ireg or Preg expected in address");
3155 else if (!IS_IREG ($5))
3156 return yyerror ("Ireg expected in address");
3160 notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3161 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3165 notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3166 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3171 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3174 return yyerror ("Dreg expected for destination operand");
3176 return yyerror ("Preg expected in address");
3178 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3179 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3182 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3185 return yyerror ("Dreg expected for destination operand");
3186 if (!IS_PREG ($5) || !IS_PREG ($7))
3187 return yyerror ("Preg expected in address");
3189 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3190 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3193 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3196 return yyerror ("Dreg expected for destination operand");
3197 if (!IS_PREG ($5) || !IS_PREG ($7))
3198 return yyerror ("Preg expected in address");
3200 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3201 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3204 | LBRACK REG post_op RBRACK ASSIGN REG
3206 if (!IS_IREG ($2) && !IS_PREG ($2))
3207 return yyerror ("Ireg or Preg expected in address");
3208 else if (IS_IREG ($2) && !IS_DREG ($6))
3209 return yyerror ("Dreg expected for source operand");
3210 else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6))
3211 return yyerror ("Dreg or Preg expected for source operand");
3215 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3216 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3218 else if (IS_DREG ($6))
3220 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3221 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3225 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3226 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3230 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3233 return yyerror ("Dreg expected for source operand");
3235 if (IS_IREG ($2) && IS_MREG ($4))
3237 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3238 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3240 else if (IS_PREG ($2) && IS_PREG ($4))
3242 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3243 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3246 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3249 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3252 return yyerror ("Dreg expected for source operand");
3254 if (IS_PREG ($3) && IS_PREG ($5))
3256 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3257 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3260 return yyerror ("Preg ++ Preg expected in address");
3263 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3265 Expr_Node *tmp = $7;
3267 return yyerror ("Dreg expected for destination operand");
3269 return yyerror ("Preg expected in address");
3272 tmp = unary (Expr_Op_Type_NEG, tmp);
3275 return yyerror ("Plain symbol used as offset");
3277 if (in_range_p (tmp, -32768, 32767, 0))
3279 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3281 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp);
3284 return yyerror ("Displacement out of range");
3287 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3290 return yyerror ("Dreg expected for destination operand");
3292 return yyerror ("Preg expected in address");
3294 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3296 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3299 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3302 return yyerror ("Dreg expected for destination operand");
3304 if (IS_IREG ($4) && IS_MREG ($6))
3306 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3307 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3309 else if (IS_PREG ($4) && IS_PREG ($6))
3311 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3312 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3315 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3318 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3320 Expr_Node *tmp = $6;
3321 int ispreg = IS_PREG ($1);
3322 int isgot = IS_RELOC($6);
3325 return yyerror ("Preg expected in address");
3327 if (!IS_DREG ($1) && !ispreg)
3328 return yyerror ("Dreg or Preg expected for destination operand");
3330 if (tmp->type == Expr_Node_Reloc
3331 && strcmp (tmp->value.s_value,
3332 "_current_shared_library_p5_offset_") != 0)
3333 return yyerror ("Plain symbol used as offset");
3336 tmp = unary (Expr_Op_Type_NEG, tmp);
3340 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3341 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3343 else if (in_range_p (tmp, 0, 63, 3))
3345 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3346 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3348 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3350 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3351 tmp = unary (Expr_Op_Type_NEG, tmp);
3352 $$ = LDSTIIFP (tmp, &$1, 0);
3354 else if (in_range_p (tmp, -131072, 131071, 3))
3356 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3357 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3361 return yyerror ("Displacement out of range");
3364 | REG ASSIGN LBRACK REG post_op RBRACK
3366 if (!IS_IREG ($4) && !IS_PREG ($4))
3367 return yyerror ("Ireg or Preg expected in address");
3368 else if (IS_IREG ($4) && !IS_DREG ($1))
3369 return yyerror ("Dreg expected in destination operand");
3370 else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1)
3371 && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0))
3372 return yyerror ("Dreg or Preg expected in destination operand");
3376 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3377 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3379 else if (IS_DREG ($1))
3381 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3382 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3384 else if (IS_PREG ($1))
3386 if (REG_SAME ($1, $4) && $5.x0 != 2)
3387 return yyerror ("Pregs can't be same");
3389 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3390 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3394 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3395 $$ = PUSHPOPREG (&$1, 0);
3400 /* PushPopMultiple. */
3401 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3403 if ($1.regno != REG_SP)
3404 yyerror ("Stack Pointer expected");
3405 if ($4.regno == REG_R7
3406 && IN_RANGE ($6, 0, 7)
3407 && $8.regno == REG_P5
3408 && IN_RANGE ($10, 0, 5))
3410 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3411 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3414 return yyerror ("Bad register for PushPopMultiple");
3417 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3419 if ($1.regno != REG_SP)
3420 yyerror ("Stack Pointer expected");
3422 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3424 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3425 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3427 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3429 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3430 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3433 return yyerror ("Bad register for PushPopMultiple");
3436 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3438 if ($11.regno != REG_SP)
3439 yyerror ("Stack Pointer expected");
3440 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3441 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3443 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3444 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3447 return yyerror ("Bad register range for PushPopMultiple");
3450 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3452 if ($7.regno != REG_SP)
3453 yyerror ("Stack Pointer expected");
3455 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3457 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3458 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3460 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3462 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3463 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3466 return yyerror ("Bad register range for PushPopMultiple");
3469 | reg_with_predec ASSIGN REG
3471 if ($1.regno != REG_SP)
3472 yyerror ("Stack Pointer expected");
3476 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3477 $$ = PUSHPOPREG (&$3, 1);
3480 return yyerror ("Bad register for PushPopReg");
3487 if (IS_URANGE (16, $2, 0, 4))
3488 $$ = LINKAGE (0, uimm16s4 ($2));
3490 return yyerror ("Bad constant for LINK");
3495 notethat ("linkage: UNLINK\n");
3496 $$ = LINKAGE (1, 0);
3502 | LSETUP LPAREN expr COMMA expr RPAREN REG
3504 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3506 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3507 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3510 return yyerror ("Bad register or values for LSETUP");
3513 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3515 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3516 && IS_PREG ($9) && IS_CREG ($7))
3518 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3519 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3522 return yyerror ("Bad register or values for LSETUP");
3525 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3527 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3528 && IS_PREG ($9) && IS_CREG ($7)
3529 && EXPR_VALUE ($11) == 1)
3531 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3532 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3535 return yyerror ("Bad register or values for LSETUP");
3542 return yyerror ("Invalid expression in loop statement");
3544 return yyerror ("Invalid loop counter register");
3545 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3547 | LOOP expr REG ASSIGN REG
3549 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3551 notethat ("Loop: LOOP expr counters = pregs\n");
3552 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3555 return yyerror ("Bad register or values for LOOP");
3557 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3559 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3561 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3562 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3565 return yyerror ("Bad register or values for LOOP");
3571 Expr_Node_Value val;
3573 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3574 bfin_loop_attempt_create_label (tmp, 1);
3575 if (!IS_RELOC (tmp))
3576 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3577 bfin_loop_beginend (tmp, 1);
3583 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3585 bfin_loop_beginend ($2, 1);
3592 Expr_Node_Value val;
3594 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3595 bfin_loop_attempt_create_label (tmp, 1);
3596 if (!IS_RELOC (tmp))
3597 return yyerror ("Invalid expression in LOOP_END statement");
3598 bfin_loop_beginend (tmp, 0);
3604 return yyerror ("Invalid expression in LOOP_END statement");
3606 bfin_loop_beginend ($2, 0);
3614 notethat ("psedoDEBUG: ABORT\n");
3615 $$ = bfin_gen_pseudodbg (3, 3, 0);
3620 notethat ("pseudoDEBUG: DBG\n");
3621 $$ = bfin_gen_pseudodbg (3, 7, 0);
3625 notethat ("pseudoDEBUG: DBG REG_A\n");
3626 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3630 notethat ("pseudoDEBUG: DBG allregs\n");
3631 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, ($2.regno & CLASS_MASK) >> 4);
3634 | DBGCMPLX LPAREN REG RPAREN
3637 return yyerror ("Dregs expected");
3638 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3639 $$ = bfin_gen_pseudodbg (3, 6, ($3.regno & CODE_MASK) >> 4);
3644 notethat ("psedoDEBUG: DBGHALT\n");
3645 $$ = bfin_gen_pseudodbg (3, 5, 0);
3650 notethat ("psedoDEBUG: HLT\n");
3651 $$ = bfin_gen_pseudodbg (3, 4, 0);
3654 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3656 notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
3657 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3660 | DBGAH LPAREN REG COMMA expr RPAREN
3662 notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
3663 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3666 | DBGAL LPAREN REG COMMA expr RPAREN
3668 notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
3669 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3674 if (!IS_UIMM ($2, 8))
3675 return yyerror ("Constant out of range");
3676 notethat ("psedodbg_assert: OUTC uimm8\n");
3677 $$ = bfin_gen_pseudochr (uimm8 ($2));
3683 return yyerror ("Dregs expected");
3684 notethat ("psedodbg_assert: OUTC dreg\n");
3685 $$ = bfin_gen_pseudodbg (2, $2.regno & CODE_MASK, 0);
3692 /* Register rules. */
3694 REG_A: REG_A_DOUBLE_ZERO
3712 | LPAREN M COMMA MMOD RPAREN
3717 | LPAREN MMOD COMMA M RPAREN
3722 | LPAREN MMOD RPAREN
3734 asr_asl: LPAREN ASL RPAREN
3815 | LPAREN asr_asl_0 RPAREN
3827 | LPAREN asr_asl_0 COMMA sco RPAREN
3833 | LPAREN sco COMMA asr_asl_0 RPAREN
3893 | LPAREN V COMMA S RPAREN
3898 | LPAREN S COMMA V RPAREN
3960 | LPAREN MMOD RPAREN
3963 return yyerror ("Bad modifier");
3967 | LPAREN MMOD COMMA R RPAREN
3970 return yyerror ("Bad modifier");
3974 | LPAREN R COMMA MMOD RPAREN
3977 return yyerror ("Bad modifier");
4004 | LPAREN MMOD RPAREN
4009 return yyerror ("Only (W32) allowed");
4017 | LPAREN MMOD RPAREN
4022 return yyerror ("(IU) expected");
4026 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
4032 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
4084 $$.r0 = 1; /* HL. */
4087 $$.aop = 0; /* aop. */
4092 $$.r0 = 1; /* HL. */
4095 $$.aop = 1; /* aop. */
4098 | LPAREN RNDL RPAREN
4100 $$.r0 = 0; /* HL. */
4103 $$.aop = 0; /* aop. */
4108 $$.r0 = 0; /* HL. */
4114 | LPAREN RNDH COMMA R RPAREN
4116 $$.r0 = 1; /* HL. */
4119 $$.aop = 0; /* aop. */
4121 | LPAREN TH COMMA R RPAREN
4123 $$.r0 = 1; /* HL. */
4126 $$.aop = 1; /* aop. */
4128 | LPAREN RNDL COMMA R RPAREN
4130 $$.r0 = 0; /* HL. */
4133 $$.aop = 0; /* aop. */
4136 | LPAREN TL COMMA R RPAREN
4138 $$.r0 = 0; /* HL. */
4141 $$.aop = 1; /* aop. */
4149 $$.x0 = 0; /* HL. */
4154 $$.x0 = 1; /* HL. */
4156 | LPAREN LO COMMA R RPAREN
4159 $$.x0 = 0; /* HL. */
4161 | LPAREN HI COMMA R RPAREN
4164 $$.x0 = 1; /* HL. */
4182 /* Assignments, Macfuncs. */
4208 if (IS_A1 ($3) && IS_EVEN ($1))
4209 return yyerror ("Cannot move A1 to even register");
4210 else if (!IS_A1 ($3) && !IS_EVEN ($1))
4211 return yyerror ("Cannot move A0 to odd register");
4227 | REG ASSIGN LPAREN a_macfunc RPAREN
4229 if ($4.n && IS_EVEN ($1))
4230 return yyerror ("Cannot move A1 to even register");
4231 else if (!$4.n && !IS_EVEN ($1))
4232 return yyerror ("Cannot move A0 to odd register");
4240 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4242 if ($4.n && !IS_H ($1))
4243 return yyerror ("Cannot move A1 to low half of register");
4244 else if (!$4.n && IS_H ($1))
4245 return yyerror ("Cannot move A0 to high half of register");
4253 | HALF_REG ASSIGN REG_A
4255 if (IS_A1 ($3) && !IS_H ($1))
4256 return yyerror ("Cannot move A1 to low half of register");
4257 else if (!IS_A1 ($3) && IS_H ($1))
4258 return yyerror ("Cannot move A0 to high half of register");
4271 a_assign multiply_halfregs
4278 | a_plusassign multiply_halfregs
4285 | a_minusassign multiply_halfregs
4295 HALF_REG STAR HALF_REG
4297 if (IS_DREG ($1) && IS_DREG ($3))
4303 return yyerror ("Dregs expected");
4327 CCREG cc_op STATUS_REG
4339 | STATUS_REG cc_op CCREG
4353 /* Expressions and Symbols. */
4357 Expr_Node_Value val;
4358 val.s_value = S_GET_NAME($1);
4359 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4365 { $$ = BFD_RELOC_BFIN_GOT; }
4367 { $$ = BFD_RELOC_BFIN_GOT17M4; }
4369 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4372 got: symbol AT any_gotrel
4374 Expr_Node_Value val;
4376 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4399 Expr_Node_Value val;
4401 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4407 | LPAREN expr_1 RPAREN
4413 $$ = unary (Expr_Op_Type_COMP, $2);
4415 | MINUS expr_1 %prec TILDA
4417 $$ = unary (Expr_Op_Type_NEG, $2);
4427 expr_1: expr_1 STAR expr_1
4429 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4431 | expr_1 SLASH expr_1
4433 $$ = binary (Expr_Op_Type_Div, $1, $3);
4435 | expr_1 PERCENT expr_1
4437 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4439 | expr_1 PLUS expr_1
4441 $$ = binary (Expr_Op_Type_Add, $1, $3);
4443 | expr_1 MINUS expr_1
4445 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4447 | expr_1 LESS_LESS expr_1
4449 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4451 | expr_1 GREATER_GREATER expr_1
4453 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4455 | expr_1 AMPERSAND expr_1
4457 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4459 | expr_1 CARET expr_1
4461 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4465 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4477 mkexpr (int x, SYMBOL_T s)
4479 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4486 value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
4488 int umax = (1 << sz) - 1;
4489 int min = -1 << (sz - 1);
4490 int max = (1 << (sz - 1)) - 1;
4492 int v = (EXPR_VALUE (exp)) & 0xffffffff;
4496 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4507 if (v >= min && v <= max) return 1;
4510 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4514 if (v <= umax && v >= 0)
4517 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4522 /* Return the expression structure that allows symbol operations.
4523 If the left and right children are constants, do the operation. */
4525 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4527 Expr_Node_Value val;
4529 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4533 case Expr_Op_Type_Add:
4534 x->value.i_value += y->value.i_value;
4536 case Expr_Op_Type_Sub:
4537 x->value.i_value -= y->value.i_value;
4539 case Expr_Op_Type_Mult:
4540 x->value.i_value *= y->value.i_value;
4542 case Expr_Op_Type_Div:
4543 if (y->value.i_value == 0)
4544 error ("Illegal Expression: Division by zero.");
4546 x->value.i_value /= y->value.i_value;
4548 case Expr_Op_Type_Mod:
4549 x->value.i_value %= y->value.i_value;
4551 case Expr_Op_Type_Lshift:
4552 x->value.i_value <<= y->value.i_value;
4554 case Expr_Op_Type_Rshift:
4555 x->value.i_value >>= y->value.i_value;
4557 case Expr_Op_Type_BAND:
4558 x->value.i_value &= y->value.i_value;
4560 case Expr_Op_Type_BOR:
4561 x->value.i_value |= y->value.i_value;
4563 case Expr_Op_Type_BXOR:
4564 x->value.i_value ^= y->value.i_value;
4566 case Expr_Op_Type_LAND:
4567 x->value.i_value = x->value.i_value && y->value.i_value;
4569 case Expr_Op_Type_LOR:
4570 x->value.i_value = x->value.i_value || y->value.i_value;
4574 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4578 /* Canonicalize order to EXPR OP CONSTANT. */
4579 if (x->type == Expr_Node_Constant)
4585 /* Canonicalize subtraction of const to addition of negated const. */
4586 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4588 op = Expr_Op_Type_Add;
4589 y->value.i_value = -y->value.i_value;
4591 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4592 && x->Right_Child->type == Expr_Node_Constant)
4594 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4596 x->Right_Child->value.i_value += y->value.i_value;
4601 /* Create a new expression structure. */
4603 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4607 unary (Expr_Op_Type op, Expr_Node *x)
4609 if (x->type == Expr_Node_Constant)
4613 case Expr_Op_Type_NEG:
4614 x->value.i_value = -x->value.i_value;
4616 case Expr_Op_Type_COMP:
4617 x->value.i_value = ~x->value.i_value;
4620 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4626 /* Create a new expression structure. */
4627 Expr_Node_Value val;
4629 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4633 int debug_codeselection = 0;
4635 notethat (char *format, ...)
4638 va_start (ap, format);
4639 if (debug_codeselection)
4641 vfprintf (errorf, format, ap);
4647 main (int argc, char **argv)