1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 #include "bfin-aux.h" /* Opcode generating auxiliaries. */
28 #include "elf/common.h"
31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
32 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
35 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
39 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
43 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
46 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
48 #define LDIMMHALF_R(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
52 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
54 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
55 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
57 #define LDST(ptr, reg, aop, sz, z, w) \
58 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
60 #define LDSTII(ptr, reg, offset, w, op) \
61 bfin_gen_ldstii (ptr, reg, offset, w, op)
63 #define DSPLDST(i, m, reg, aop, w) \
64 bfin_gen_dspldst (i, reg, aop, w, m)
66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
67 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
69 #define LDSTIIFP(offset, reg, w) \
70 bfin_gen_ldstiifp (reg, offset, w)
72 #define LOGI2OP(dst, src, opc) \
73 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
75 #define ALU2OP(dst, src, opc) \
76 bfin_gen_alu2op (dst, src, opc)
78 #define BRCC(t, b, offset) \
79 bfin_gen_brcc (t, b, offset)
81 #define UJUMP(offset) \
82 bfin_gen_ujump (offset)
84 #define PROGCTRL(prgfunc, poprnd) \
85 bfin_gen_progctrl (prgfunc, poprnd)
87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
88 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
90 #define PUSHPOPREG(reg, w) \
91 bfin_gen_pushpopreg (reg, w)
93 #define CALLA(addr, s) \
94 bfin_gen_calla (addr, s)
96 #define LINKAGE(r, framesize) \
97 bfin_gen_linkage (r, framesize)
99 #define COMPI2OPD(dst, src, op) \
100 bfin_gen_compi2opd (dst, src, op)
102 #define COMPI2OPP(dst, src, op) \
103 bfin_gen_compi2opp (dst, src, op)
105 #define DAGMODIK(i, op) \
106 bfin_gen_dagmodik (i, op)
108 #define DAGMODIM(i, m, op, br) \
109 bfin_gen_dagmodim (i, m, op, br)
111 #define COMP3OP(dst, src0, src1, opc) \
112 bfin_gen_comp3op (src0, src1, dst, opc)
114 #define PTR2OP(dst, src, opc) \
115 bfin_gen_ptr2op (dst, src, opc)
117 #define CCFLAG(x, y, opc, i, g) \
118 bfin_gen_ccflag (x, y, opc, i, g)
120 #define CCMV(src, dst, t) \
121 bfin_gen_ccmv (src, dst, t)
123 #define CACTRL(reg, a, op) \
124 bfin_gen_cactrl (reg, a, op)
126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
127 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
129 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
130 #define IS_RANGE(bits, expr, sign, mul) \
131 value_match(expr, bits, sign, mul, 1)
132 #define IS_URANGE(bits, expr, sign, mul) \
133 value_match(expr, bits, sign, mul, 0)
134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
136 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
137 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
139 #define IS_PCREL4(expr) \
140 (value_match (expr, 4, 0, 2, 0))
142 #define IS_LPPCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 0))
145 #define IS_PCREL10(expr) \
146 (value_match (expr, 10, 0, 2, 1))
148 #define IS_PCREL12(expr) \
149 (value_match (expr, 12, 0, 2, 1))
151 #define IS_PCREL24(expr) \
152 (value_match (expr, 24, 0, 2, 1))
155 static int value_match (Expr_Node *, int, int, int, int);
160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
161 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
163 static void notethat (char *, ...);
165 char *current_inputline;
167 int yyerror (char *);
169 void error (char *format, ...)
172 static char buffer[2000];
174 va_start (ap, format);
175 vsprintf (buffer, format, ap);
178 as_bad ("%s", buffer);
187 else if (yytext[0] != ';')
188 error ("%s. Input text was %s.", msg, yytext);
196 in_range_p (Expr_Node *exp, int from, int to, unsigned int mask)
198 int val = EXPR_VALUE (exp);
199 if (exp->type != Expr_Node_Constant)
201 if (val < from || val > to)
203 return (val & mask) == 0;
206 extern int yylex (void);
208 #define imm3(x) EXPR_VALUE (x)
209 #define imm4(x) EXPR_VALUE (x)
210 #define uimm4(x) EXPR_VALUE (x)
211 #define imm5(x) EXPR_VALUE (x)
212 #define uimm5(x) EXPR_VALUE (x)
213 #define imm6(x) EXPR_VALUE (x)
214 #define imm7(x) EXPR_VALUE (x)
215 #define uimm8(x) EXPR_VALUE (x)
216 #define imm16(x) EXPR_VALUE (x)
217 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
218 #define uimm16(x) EXPR_VALUE (x)
220 /* Return true if a value is inside a range. */
221 #define IN_RANGE(x, low, high) \
222 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
224 /* Auxiliary functions. */
227 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
229 if (!IS_DREG (*reg1))
231 yyerror ("Dregs expected");
235 if (reg1->regno != 1 && reg1->regno != 3)
237 yyerror ("Bad register pair");
241 if (imm7 (reg2) != reg1->regno - 1)
243 yyerror ("Bad register pair");
252 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
254 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
255 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
256 return yyerror ("Source multiplication register mismatch");
262 /* Check mac option. */
265 check_macfunc_option (Macfunc *a, Opt_mode *opt)
267 /* Default option is always valid. */
271 if ((a->w == 1 && a->P == 1
272 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
273 && opt->mod != M_S2RND && opt->mod != M_ISS2)
274 || (a->w == 1 && a->P == 0
275 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
276 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
277 && opt->mod != M_ISS2 && opt->mod != M_IH)
278 || (a->w == 0 && a->P == 0
279 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
285 /* Check (vector) mac funcs and ops. */
288 check_macfuncs (Macfunc *aa, Opt_mode *opa,
289 Macfunc *ab, Opt_mode *opb)
291 /* Variables for swapping. */
295 /* The option mode should be put at the end of the second instruction
296 of the vector except M, which should follow MAC1 instruction. */
298 return yyerror ("Bad opt mode");
300 /* If a0macfunc comes before a1macfunc, swap them. */
304 /* (M) is not allowed here. */
306 return yyerror ("(M) not allowed with A0MAC");
308 return yyerror ("Vector AxMACs can't be same");
310 mtmp = *aa; *aa = *ab; *ab = mtmp;
311 otmp = *opa; *opa = *opb; *opb = otmp;
316 return yyerror ("(M) not allowed with A0MAC");
318 return yyerror ("Vector AxMACs can't be same");
321 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
322 assignment_or_macfuncs. */
323 if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
324 && (ab->op == 0 || ab->op == 1 || ab->op == 2))
326 if (check_multiply_halfregs (aa, ab) < 0)
331 /* Only one of the assign_macfuncs has a half reg multiply
332 Evil trick: Just 'OR' their source register codes:
333 We can do that, because we know they were initialized to 0
334 in the rules that don't use multiply_halfregs. */
335 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
336 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
339 if (aa->w == ab->w && aa->P != ab->P)
341 return yyerror ("macfuncs must differ");
342 if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
343 return yyerror ("Destination Dregs must differ by one");
346 /* Make sure mod flags get ORed, too. */
347 opb->mod |= opa->mod;
350 if (check_macfunc_option (aa, opb) < 0
351 && check_macfunc_option (ab, opb) < 0)
352 return yyerror ("bad option");
354 /* Make sure first macfunc has got both P flags ORed. */
362 is_group1 (INSTR_T x)
364 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
365 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
372 is_group2 (INSTR_T x)
374 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
375 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
376 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
377 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
378 || (x->value == 0x0000))
389 if ((x->value & 0xf000) == 0x8000)
391 int aop = ((x->value >> 9) & 0x3);
392 int w = ((x->value >> 11) & 0x1);
398 if (((x->value & 0xFF60) == 0x9E60) || /* dagMODim_0 */
399 ((x->value & 0xFFF0) == 0x9F60)) /* dagMODik_0 */
402 /* decode_dspLDST_0 */
403 if ((x->value & 0xFC00) == 0x9C00)
405 int w = ((x->value >> 9) & 0x1);
414 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
416 int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
417 int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
418 int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
420 if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
421 yyerror ("resource conflict in multi-issue instruction");
423 /* Anomaly 05000074 */
424 if (ENABLE_AC_05000074
425 && dsp32 != NULL && dsp16_grp1 != NULL
426 && (dsp32->value & 0xf780) == 0xc680
427 && ((dsp16_grp1->value & 0xfe40) == 0x9240
428 || (dsp16_grp1->value & 0xfe08) == 0xba08
429 || (dsp16_grp1->value & 0xfc00) == 0xbc00))
430 yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
431 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
433 if (is_store (dsp16_grp1) && is_store (dsp16_grp2))
434 yyerror ("Only one instruction in multi-issue instruction can be a store");
436 return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
448 struct { int r0; int s0; int x0; int aop; } modcodes;
449 struct { int r0; } r0;
456 /* Vector Specific. */
457 %token BYTEOP16P BYTEOP16M
458 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
459 %token BYTEUNPACK BYTEPACK
462 %token ALIGN8 ALIGN16 ALIGN24
464 %token EXTRACT DEPOSIT EXPADJ SEARCH
465 %token ONES SIGN SIGNBITS
473 %token CCREG BYTE_DREG
474 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
475 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
480 %token RTI RTS RTX RTN RTE
491 %token JUMP JUMP_DOT_S JUMP_DOT_L
498 %token NOT TILDA BANG
504 %token MINUS PLUS STAR SLASH
508 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
509 %token _MINUS_MINUS _PLUS_PLUS
511 /* Shift/rotate ops. */
512 %token SHIFT LSHIFT ASHIFT BXORSHIFT
513 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
515 %token LESS_LESS GREATER_GREATER
516 %token _GREATER_GREATER_GREATER
517 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
520 /* In place operators. */
521 %token ASSIGN _STAR_ASSIGN
522 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
523 %token _MINUS_ASSIGN _PLUS_ASSIGN
525 /* Assignments, comparisons. */
526 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
531 %token FLUSHINV FLUSH
532 %token IFLUSH PREFETCH
549 %token R RND RNDL RNDH RND12 RND20
554 %token BITTGL BITCLR BITSET BITTST BITMUX
557 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
559 /* Semantic auxiliaries. */
562 %token COLON SEMICOLON
563 %token RPAREN LPAREN LBRACK RBRACK
567 %token GOT GOT17M4 FUNCDESC_GOT17M4
577 %type <modcodes> byteop_mod
579 %type <reg> a_plusassign
580 %type <reg> a_minusassign
581 %type <macfunc> multiply_halfregs
582 %type <macfunc> assign_macfunc
583 %type <macfunc> a_macfunc
587 %type <modcodes> vsmod
588 %type <modcodes> ccstat
591 %type <reg> reg_with_postinc
592 %type <reg> reg_with_predec
596 %type <symbol> SYMBOL
599 %type <reg> BYTE_DREG
600 %type <reg> REG_A_DOUBLE_ZERO
601 %type <reg> REG_A_DOUBLE_ONE
603 %type <reg> STATUS_REG
607 %type <modcodes> smod
608 %type <modcodes> b3_op
609 %type <modcodes> rnd_op
610 %type <modcodes> post_op
612 %type <r0> iu_or_nothing
613 %type <r0> plus_minus
617 %type <modcodes> amod0
618 %type <modcodes> amod1
619 %type <modcodes> amod2
621 %type <r0> w32_or_nothing
625 %type <expr> got_or_expr
627 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
629 /* Precedence rules. */
633 %left LESS_LESS GREATER_GREATER
635 %left STAR SLASH PERCENT
646 if (insn == (INSTR_T) 0)
647 return NO_INSN_GENERATED;
648 else if (insn == (INSTR_T) - 1)
649 return SEMANTIC_ERROR;
651 return INSN_GENERATED;
656 /* Parallel instructions. */
657 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
659 if (($1->value & 0xf800) == 0xc000)
661 if (is_group1 ($3) && is_group2 ($5))
662 $$ = gen_multi_instr_1 ($1, $3, $5);
663 else if (is_group2 ($3) && is_group1 ($5))
664 $$ = gen_multi_instr_1 ($1, $5, $3);
666 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
668 else if (($3->value & 0xf800) == 0xc000)
670 if (is_group1 ($1) && is_group2 ($5))
671 $$ = gen_multi_instr_1 ($3, $1, $5);
672 else if (is_group2 ($1) && is_group1 ($5))
673 $$ = gen_multi_instr_1 ($3, $5, $1);
675 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
677 else if (($5->value & 0xf800) == 0xc000)
679 if (is_group1 ($1) && is_group2 ($3))
680 $$ = gen_multi_instr_1 ($5, $1, $3);
681 else if (is_group2 ($1) && is_group1 ($3))
682 $$ = gen_multi_instr_1 ($5, $3, $1);
684 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
687 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
690 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
692 if (($1->value & 0xf800) == 0xc000)
695 $$ = gen_multi_instr_1 ($1, $3, 0);
696 else if (is_group2 ($3))
697 $$ = gen_multi_instr_1 ($1, 0, $3);
699 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
701 else if (($3->value & 0xf800) == 0xc000)
704 $$ = gen_multi_instr_1 ($3, $1, 0);
705 else if (is_group2 ($1))
706 $$ = gen_multi_instr_1 ($3, 0, $1);
708 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
710 else if (is_group1 ($1) && is_group2 ($3))
711 $$ = gen_multi_instr_1 (0, $1, $3);
712 else if (is_group2 ($1) && is_group1 ($3))
713 $$ = gen_multi_instr_1 (0, $3, $1);
715 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
730 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
732 | assign_macfunc opt_mode
736 int h00, h10, h01, h11;
738 if (check_macfunc_option (&$1, &$2) < 0)
739 return yyerror ("bad option");
744 return yyerror ("(m) not allowed with a0 unit");
763 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
764 &$1.dst, op0, &$1.s0, &$1.s1, w0);
770 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
774 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
776 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
783 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
784 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
785 dst, $4.op, &$1.s0, &$1.s1, $4.w);
792 notethat ("dsp32alu: DISALGNEXCPT\n");
793 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
795 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
797 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
799 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
800 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
803 return yyerror ("Register mismatch");
805 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
807 if (!IS_A1 ($4) && IS_A1 ($5))
809 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
810 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
813 return yyerror ("Register mismatch");
815 | A_ZERO_DOT_H ASSIGN HALF_REG
817 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
818 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
820 | A_ONE_DOT_H ASSIGN HALF_REG
822 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
823 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
825 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
826 COLON expr COMMA REG COLON expr RPAREN aligndir
828 if (!IS_DREG ($2) || !IS_DREG ($4))
829 return yyerror ("Dregs expected");
830 else if (!valid_dreg_pair (&$9, $11))
831 return yyerror ("Bad dreg pair");
832 else if (!valid_dreg_pair (&$13, $15))
833 return yyerror ("Bad dreg pair");
836 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (aligndir)\n");
837 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
841 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
842 REG COLON expr RPAREN aligndir
844 if (!IS_DREG ($2) || !IS_DREG ($4))
845 return yyerror ("Dregs expected");
846 else if (!valid_dreg_pair (&$9, $11))
847 return yyerror ("Bad dreg pair");
848 else if (!valid_dreg_pair (&$13, $15))
849 return yyerror ("Bad dreg pair");
852 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
853 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
857 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
859 if (!IS_DREG ($2) || !IS_DREG ($4))
860 return yyerror ("Dregs expected");
861 else if (!valid_dreg_pair (&$8, $10))
862 return yyerror ("Bad dreg pair");
865 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
866 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
869 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
871 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
873 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
874 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
877 return yyerror ("Register mismatch");
879 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
880 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
882 if (IS_DREG ($1) && IS_DREG ($7))
884 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
885 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
888 return yyerror ("Register mismatch");
892 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
894 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
895 && IS_A1 ($9) && !IS_A1 ($11))
897 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
898 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
901 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
902 && !IS_A1 ($9) && IS_A1 ($11))
904 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
905 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
908 return yyerror ("Register mismatch");
911 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
914 return yyerror ("Operators must differ");
916 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
917 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
919 notethat ("dsp32alu: dregs = dregs + dregs,"
920 "dregs = dregs - dregs (amod1)\n");
921 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
924 return yyerror ("Register mismatch");
927 /* Bar Operations. */
929 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
931 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
932 return yyerror ("Differing source registers");
934 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
935 return yyerror ("Dregs expected");
938 if ($4.r0 == 1 && $10.r0 == 2)
940 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
941 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
943 else if ($4.r0 == 0 && $10.r0 == 3)
945 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
946 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
949 return yyerror ("Bar operand mismatch");
952 | REG ASSIGN ABS REG vmod
956 if (IS_DREG ($1) && IS_DREG ($4))
960 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
965 /* Vector version of ABS. */
966 notethat ("dsp32alu: dregs = ABS dregs\n");
969 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
972 return yyerror ("Dregs expected");
976 notethat ("dsp32alu: Ax = ABS Ax\n");
977 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
979 | A_ZERO_DOT_L ASSIGN HALF_REG
983 notethat ("dsp32alu: A0.l = reg_half\n");
984 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
987 return yyerror ("A0.l = Rx.l expected");
989 | A_ONE_DOT_L ASSIGN HALF_REG
993 notethat ("dsp32alu: A1.l = reg_half\n");
994 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
997 return yyerror ("A1.l = Rx.l expected");
1000 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
1002 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1004 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
1005 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
1008 return yyerror ("Dregs expected");
1011 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
1014 return yyerror ("Dregs expected");
1015 else if (!valid_dreg_pair (&$5, $7))
1016 return yyerror ("Bad dreg pair");
1017 else if (!valid_dreg_pair (&$9, $11))
1018 return yyerror ("Bad dreg pair");
1021 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1022 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
1025 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1028 return yyerror ("Dregs expected");
1029 else if (!valid_dreg_pair (&$5, $7))
1030 return yyerror ("Bad dreg pair");
1031 else if (!valid_dreg_pair (&$9, $11))
1032 return yyerror ("Bad dreg pair");
1035 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1036 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1040 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1044 return yyerror ("Dregs expected");
1045 else if (!valid_dreg_pair (&$5, $7))
1046 return yyerror ("Bad dreg pair");
1047 else if (!valid_dreg_pair (&$9, $11))
1048 return yyerror ("Bad dreg pair");
1051 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1052 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1056 | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1060 return yyerror ("Dregs expected");
1061 else if (!valid_dreg_pair (&$5, $7))
1062 return yyerror ("Bad dreg pair");
1063 else if (!valid_dreg_pair (&$9, $11))
1064 return yyerror ("Bad dreg pair");
1067 notethat ("dsp32alu: dregs = BYTEOP2M (dregs_pair , dregs_pair ) (rnd_op)\n");
1068 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop + 2);
1072 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1076 return yyerror ("Dregs expected");
1077 else if (!valid_dreg_pair (&$5, $7))
1078 return yyerror ("Bad dreg pair");
1079 else if (!valid_dreg_pair (&$9, $11))
1080 return yyerror ("Bad dreg pair");
1083 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1084 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1088 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1090 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1092 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1093 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1096 return yyerror ("Dregs expected");
1099 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1100 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1102 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1104 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1105 "SIGN (dregs_hi) * dregs_hi + "
1106 "SIGN (dregs_lo) * dregs_lo \n");
1108 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1111 return yyerror ("Dregs expected");
1113 | REG ASSIGN REG plus_minus REG amod1
1115 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1119 /* No saturation flag specified, generate the 16 bit variant. */
1120 notethat ("COMP3op: dregs = dregs +- dregs\n");
1121 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1125 /* Saturation flag specified, generate the 32 bit variant. */
1126 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1127 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1131 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1133 notethat ("COMP3op: pregs = pregs + pregs\n");
1134 $$ = COMP3OP (&$1, &$3, &$5, 5);
1137 return yyerror ("Dregs expected");
1139 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1143 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1150 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1151 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1154 return yyerror ("Dregs expected");
1157 | a_assign MINUS REG_A
1159 notethat ("dsp32alu: Ax = - Ax\n");
1160 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1162 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1164 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1165 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1166 $6.s0, $6.x0, HL2 ($3, $5));
1168 | a_assign a_assign expr
1170 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1172 notethat ("dsp32alu: A1 = A0 = 0\n");
1173 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1176 return yyerror ("Bad value, 0 expected");
1180 | a_assign REG_A LPAREN S RPAREN
1182 if (REG_SAME ($1, $2))
1184 notethat ("dsp32alu: Ax = Ax (S)\n");
1185 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1188 return yyerror ("Registers must be equal");
1191 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1195 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1196 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1199 return yyerror ("Dregs expected");
1202 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1204 if (IS_DREG ($3) && IS_DREG ($5))
1206 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1207 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1210 return yyerror ("Dregs expected");
1213 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1215 if (IS_DREG ($3) && IS_DREG ($5))
1217 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1218 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1221 return yyerror ("Dregs expected");
1226 if (!REG_SAME ($1, $2))
1228 notethat ("dsp32alu: An = Am\n");
1229 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1232 return yyerror ("Accu reg arguments must differ");
1239 notethat ("dsp32alu: An = dregs\n");
1240 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1243 return yyerror ("Dregs expected");
1246 | REG ASSIGN HALF_REG xpmod
1250 if ($1.regno == REG_A0x && IS_DREG ($3))
1252 notethat ("dsp32alu: A0.x = dregs_lo\n");
1253 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1255 else if ($1.regno == REG_A1x && IS_DREG ($3))
1257 notethat ("dsp32alu: A1.x = dregs_lo\n");
1258 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1260 else if (IS_DREG ($1) && IS_DREG ($3))
1262 notethat ("ALU2op: dregs = dregs_lo\n");
1263 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1266 return yyerror ("Register mismatch");
1269 return yyerror ("Low reg expected");
1272 | HALF_REG ASSIGN expr
1274 notethat ("LDIMMhalf: pregs_half = imm16\n");
1276 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1277 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1278 return yyerror ("Wrong register for load immediate");
1280 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1281 return yyerror ("Constant out of range");
1283 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1288 notethat ("dsp32alu: An = 0\n");
1291 return yyerror ("0 expected");
1293 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1296 | REG ASSIGN expr xpmod1
1298 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1299 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1300 return yyerror ("Wrong register for load immediate");
1304 /* 7 bit immediate value if possible.
1305 We will check for that constant value for efficiency
1306 If it goes to reloc, it will be 16 bit. */
1307 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1309 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1310 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1312 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1314 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1315 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1319 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1320 return yyerror ("Immediate value out of range");
1322 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1324 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1329 /* (z) There is no 7 bit zero extended instruction.
1330 If the expr is a relocation, generate it. */
1332 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1333 return yyerror ("Immediate value out of range");
1335 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1337 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1341 | HALF_REG ASSIGN REG
1344 return yyerror ("Low reg expected");
1346 if (IS_DREG ($1) && $3.regno == REG_A0x)
1348 notethat ("dsp32alu: dregs_lo = A0.x\n");
1349 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1351 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1353 notethat ("dsp32alu: dregs_lo = A1.x\n");
1354 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1357 return yyerror ("Register mismatch");
1360 | REG ASSIGN REG op_bar_op REG amod0
1362 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1364 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1365 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1368 return yyerror ("Register mismatch");
1371 | REG ASSIGN BYTE_DREG xpmod
1373 if (IS_DREG ($1) && IS_DREG ($3))
1375 notethat ("ALU2op: dregs = dregs_byte\n");
1376 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1379 return yyerror ("Register mismatch");
1382 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1384 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1386 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1387 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1390 return yyerror ("Register mismatch");
1393 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1395 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1397 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1398 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1401 return yyerror ("Register mismatch");
1404 | a_minusassign REG_A w32_or_nothing
1406 if (!IS_A1 ($1) && IS_A1 ($2))
1408 notethat ("dsp32alu: A0 -= A1\n");
1409 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1412 return yyerror ("Register mismatch");
1415 | REG _MINUS_ASSIGN expr
1417 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1419 notethat ("dagMODik: iregs -= 4\n");
1420 $$ = DAGMODIK (&$1, 3);
1422 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1424 notethat ("dagMODik: iregs -= 2\n");
1425 $$ = DAGMODIK (&$1, 1);
1428 return yyerror ("Register or value mismatch");
1431 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1433 if (IS_IREG ($1) && IS_MREG ($3))
1435 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1437 $$ = DAGMODIM (&$1, &$3, 0, 1);
1439 else if (IS_PREG ($1) && IS_PREG ($3))
1441 notethat ("PTR2op: pregs += pregs (BREV )\n");
1442 $$ = PTR2OP (&$1, &$3, 5);
1445 return yyerror ("Register mismatch");
1448 | REG _MINUS_ASSIGN REG
1450 if (IS_IREG ($1) && IS_MREG ($3))
1452 notethat ("dagMODim: iregs -= mregs\n");
1453 $$ = DAGMODIM (&$1, &$3, 1, 0);
1455 else if (IS_PREG ($1) && IS_PREG ($3))
1457 notethat ("PTR2op: pregs -= pregs\n");
1458 $$ = PTR2OP (&$1, &$3, 0);
1461 return yyerror ("Register mismatch");
1464 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1466 if (!IS_A1 ($1) && IS_A1 ($3))
1468 notethat ("dsp32alu: A0 += A1 (W32)\n");
1469 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1472 return yyerror ("Register mismatch");
1475 | REG _PLUS_ASSIGN REG
1477 if (IS_IREG ($1) && IS_MREG ($3))
1479 notethat ("dagMODim: iregs += mregs\n");
1480 $$ = DAGMODIM (&$1, &$3, 0, 0);
1483 return yyerror ("iregs += mregs expected");
1486 | REG _PLUS_ASSIGN expr
1490 if (EXPR_VALUE ($3) == 4)
1492 notethat ("dagMODik: iregs += 4\n");
1493 $$ = DAGMODIK (&$1, 2);
1495 else if (EXPR_VALUE ($3) == 2)
1497 notethat ("dagMODik: iregs += 2\n");
1498 $$ = DAGMODIK (&$1, 0);
1501 return yyerror ("iregs += [ 2 | 4 ");
1503 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1505 notethat ("COMPI2opP: pregs += imm7\n");
1506 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1508 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1510 notethat ("COMPI2opD: dregs += imm7\n");
1511 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1513 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1514 return yyerror ("Immediate value out of range");
1516 return yyerror ("Register mismatch");
1519 | REG _STAR_ASSIGN REG
1521 if (IS_DREG ($1) && IS_DREG ($3))
1523 notethat ("ALU2op: dregs *= dregs\n");
1524 $$ = ALU2OP (&$1, &$3, 3);
1527 return yyerror ("Register mismatch");
1530 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1532 if (!valid_dreg_pair (&$3, $5))
1533 return yyerror ("Bad dreg pair");
1534 else if (!valid_dreg_pair (&$7, $9))
1535 return yyerror ("Bad dreg pair");
1538 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1539 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1543 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1545 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1547 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1548 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1551 return yyerror ("Register mismatch");
1554 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1556 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1557 && REG_SAME ($1, $4))
1559 if (EXPR_VALUE ($9) == 1)
1561 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1562 $$ = ALU2OP (&$1, &$6, 4);
1564 else if (EXPR_VALUE ($9) == 2)
1566 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1567 $$ = ALU2OP (&$1, &$6, 5);
1570 return yyerror ("Bad shift value");
1572 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1573 && REG_SAME ($1, $4))
1575 if (EXPR_VALUE ($9) == 1)
1577 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1578 $$ = PTR2OP (&$1, &$6, 6);
1580 else if (EXPR_VALUE ($9) == 2)
1582 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1583 $$ = PTR2OP (&$1, &$6, 7);
1586 return yyerror ("Bad shift value");
1589 return yyerror ("Register mismatch");
1593 | REG ASSIGN REG BAR REG
1595 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1597 notethat ("COMP3op: dregs = dregs | dregs\n");
1598 $$ = COMP3OP (&$1, &$3, &$5, 3);
1601 return yyerror ("Dregs expected");
1603 | REG ASSIGN REG CARET REG
1605 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1607 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1608 $$ = COMP3OP (&$1, &$3, &$5, 4);
1611 return yyerror ("Dregs expected");
1613 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1615 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1617 if (EXPR_VALUE ($8) == 1)
1619 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1620 $$ = COMP3OP (&$1, &$3, &$6, 6);
1622 else if (EXPR_VALUE ($8) == 2)
1624 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1625 $$ = COMP3OP (&$1, &$3, &$6, 7);
1628 return yyerror ("Bad shift value");
1631 return yyerror ("Dregs expected");
1633 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1635 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1637 notethat ("CCflag: CC = A0 == A1\n");
1638 $$ = CCFLAG (0, 0, 5, 0, 0);
1641 return yyerror ("AREGs are in bad order or same");
1643 | CCREG ASSIGN REG_A LESS_THAN REG_A
1645 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1647 notethat ("CCflag: CC = A0 < A1\n");
1648 $$ = CCFLAG (0, 0, 6, 0, 0);
1651 return yyerror ("AREGs are in bad order or same");
1653 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1655 if ((IS_DREG ($3) && IS_DREG ($5))
1656 || (IS_PREG ($3) && IS_PREG ($5)))
1658 notethat ("CCflag: CC = dpregs < dpregs\n");
1659 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1662 return yyerror ("Bad register in comparison");
1664 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1666 if (!IS_DREG ($3) && !IS_PREG ($3))
1667 return yyerror ("Bad register in comparison");
1669 if (($6.r0 == 1 && IS_IMM ($5, 3))
1670 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1672 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1673 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1676 return yyerror ("Bad constant value");
1678 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1680 if ((IS_DREG ($3) && IS_DREG ($5))
1681 || (IS_PREG ($3) && IS_PREG ($5)))
1683 notethat ("CCflag: CC = dpregs == dpregs\n");
1684 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1687 return yyerror ("Bad register in comparison");
1689 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1691 if (!IS_DREG ($3) && !IS_PREG ($3))
1692 return yyerror ("Bad register in comparison");
1696 notethat ("CCflag: CC = dpregs == imm3\n");
1697 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1700 return yyerror ("Bad constant range");
1702 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1704 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1706 notethat ("CCflag: CC = A0 <= A1\n");
1707 $$ = CCFLAG (0, 0, 7, 0, 0);
1710 return yyerror ("AREGs are in bad order or same");
1712 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1714 if ((IS_DREG ($3) && IS_DREG ($5))
1715 || (IS_PREG ($3) && IS_PREG ($5)))
1717 notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
1718 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1719 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1722 return yyerror ("Bad register in comparison");
1724 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1726 if (!IS_DREG ($3) && !IS_PREG ($3))
1727 return yyerror ("Bad register in comparison");
1729 if (($6.r0 == 1 && IS_IMM ($5, 3))
1730 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1732 notethat ("CCflag: CC = dpregs <= (u)imm3\n");
1733 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1736 return yyerror ("Bad constant value");
1739 | REG ASSIGN REG AMPERSAND REG
1741 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1743 notethat ("COMP3op: dregs = dregs & dregs\n");
1744 $$ = COMP3OP (&$1, &$3, &$5, 2);
1747 return yyerror ("Dregs expected");
1752 notethat ("CC2stat operation\n");
1753 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1758 if ((IS_GENREG ($1) && IS_GENREG ($3))
1759 || (IS_GENREG ($1) && IS_DAGREG ($3))
1760 || (IS_DAGREG ($1) && IS_GENREG ($3))
1761 || (IS_DAGREG ($1) && IS_DAGREG ($3))
1762 || (IS_GENREG ($1) && $3.regno == REG_USP)
1763 || ($1.regno == REG_USP && IS_GENREG ($3))
1764 || ($1.regno == REG_USP && $3.regno == REG_USP)
1765 || (IS_DREG ($1) && IS_SYSREG ($3))
1766 || (IS_PREG ($1) && IS_SYSREG ($3))
1767 || (IS_SYSREG ($1) && IS_GENREG ($3))
1768 || (IS_ALLREG ($1) && IS_EMUDAT ($3))
1769 || (IS_EMUDAT ($1) && IS_ALLREG ($3))
1770 || (IS_SYSREG ($1) && $3.regno == REG_USP))
1772 $$ = bfin_gen_regmv (&$3, &$1);
1775 return yyerror ("Unsupported register move");
1782 notethat ("CC2dreg: CC = dregs\n");
1783 $$ = bfin_gen_cc2dreg (1, &$3);
1786 return yyerror ("Only 'CC = Dreg' supported");
1793 notethat ("CC2dreg: dregs = CC\n");
1794 $$ = bfin_gen_cc2dreg (0, &$1);
1797 return yyerror ("Only 'Dreg = CC' supported");
1800 | CCREG _ASSIGN_BANG CCREG
1802 notethat ("CC2dreg: CC =! CC\n");
1803 $$ = bfin_gen_cc2dreg (3, 0);
1808 | HALF_REG ASSIGN multiply_halfregs opt_mode
1810 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1812 if (!IS_H ($1) && $4.MM)
1813 return yyerror ("(M) not allowed with MAC0");
1815 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1816 && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1817 && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1818 return yyerror ("bad option.");
1822 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1823 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1824 &$1, 0, &$3.s0, &$3.s1, 0);
1828 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1829 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1830 &$1, 0, &$3.s0, &$3.s1, 1);
1834 | REG ASSIGN multiply_halfregs opt_mode
1836 /* Odd registers can use (M). */
1838 return yyerror ("Dreg expected");
1840 if (IS_EVEN ($1) && $4.MM)
1841 return yyerror ("(M) not allowed with MAC0");
1843 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1844 && $4.mod != M_S2RND && $4.mod != M_ISS2)
1845 return yyerror ("bad option");
1849 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1851 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1852 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1853 &$1, 0, &$3.s0, &$3.s1, 0);
1857 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1858 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1859 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1860 &$1, 0, &$3.s0, &$3.s1, 1);
1864 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1865 HALF_REG ASSIGN multiply_halfregs opt_mode
1867 if (!IS_DREG ($1) || !IS_DREG ($6))
1868 return yyerror ("Dregs expected");
1870 if (!IS_HCOMPL($1, $6))
1871 return yyerror ("Dest registers mismatch");
1873 if (check_multiply_halfregs (&$3, &$8) < 0)
1876 if ((!IS_H ($1) && $4.MM)
1877 || (!IS_H ($6) && $9.MM))
1878 return yyerror ("(M) not allowed with MAC0");
1880 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1881 "dregs_lo = multiply_halfregs opt_mode\n");
1884 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1885 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1886 &$1, 0, &$3.s0, &$3.s1, 1);
1888 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1889 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1890 &$1, 0, &$3.s0, &$3.s1, 1);
1893 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1895 if (!IS_DREG ($1) || !IS_DREG ($6))
1896 return yyerror ("Dregs expected");
1898 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1899 || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1900 return yyerror ("Dest registers mismatch");
1902 if (check_multiply_halfregs (&$3, &$8) < 0)
1905 if ((IS_EVEN ($1) && $4.MM)
1906 || (IS_EVEN ($6) && $9.MM))
1907 return yyerror ("(M) not allowed with MAC0");
1909 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1910 "dregs = multiply_halfregs opt_mode\n");
1913 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1914 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1915 &$1, 0, &$3.s0, &$3.s1, 1);
1917 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1918 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1919 &$1, 0, &$3.s0, &$3.s1, 1);
1924 | a_assign ASHIFT REG_A BY HALF_REG
1926 if (!REG_SAME ($1, $3))
1927 return yyerror ("Aregs must be same");
1929 if (IS_DREG ($5) && !IS_H ($5))
1931 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1932 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1935 return yyerror ("Dregs expected");
1938 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1940 if (IS_DREG ($6) && !IS_H ($6))
1942 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1943 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1946 return yyerror ("Dregs expected");
1949 | a_assign REG_A LESS_LESS expr
1951 if (!REG_SAME ($1, $2))
1952 return yyerror ("Aregs must be same");
1954 if (IS_UIMM ($4, 5))
1956 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1957 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1960 return yyerror ("Bad shift value");
1963 | REG ASSIGN REG LESS_LESS expr vsmod
1965 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1970 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1971 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1975 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1976 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1979 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1981 if (EXPR_VALUE ($5) == 2)
1983 notethat ("PTR2op: pregs = pregs << 2\n");
1984 $$ = PTR2OP (&$1, &$3, 1);
1986 else if (EXPR_VALUE ($5) == 1)
1988 notethat ("COMP3op: pregs = pregs << 1\n");
1989 $$ = COMP3OP (&$1, &$3, &$3, 5);
1992 return yyerror ("Bad shift value");
1995 return yyerror ("Bad shift value or register");
1997 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1999 if (IS_UIMM ($5, 4))
2003 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
2004 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
2008 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
2009 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
2013 return yyerror ("Bad shift value");
2015 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
2019 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
2024 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
2025 "dregs_lo (V, .)\n");
2031 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
2033 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
2036 return yyerror ("Dregs expected");
2040 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2042 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2044 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2045 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2048 return yyerror ("Bad shift value or register");
2052 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2054 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2056 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2057 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2059 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2061 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2062 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2065 return yyerror ("Bad shift value or register");
2070 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2072 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2074 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2075 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2078 return yyerror ("Register mismatch");
2081 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2083 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2085 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2086 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2089 return yyerror ("Register mismatch");
2092 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2094 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2096 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2097 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2100 return yyerror ("Register mismatch");
2103 | a_assign REG_A _GREATER_GREATER_GREATER expr
2105 if (!REG_SAME ($1, $2))
2106 return yyerror ("Aregs must be same");
2108 if (IS_UIMM ($4, 5))
2110 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2111 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2114 return yyerror ("Shift value range error");
2116 | a_assign LSHIFT REG_A BY HALF_REG
2118 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2120 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2121 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2124 return yyerror ("Register mismatch");
2127 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2129 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2131 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2132 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2135 return yyerror ("Register mismatch");
2138 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2140 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2142 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2143 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2146 return yyerror ("Register mismatch");
2149 | REG ASSIGN SHIFT REG BY HALF_REG
2151 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2153 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2154 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2157 return yyerror ("Register mismatch");
2160 | a_assign REG_A GREATER_GREATER expr
2162 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2164 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2165 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2168 return yyerror ("Accu register expected");
2171 | REG ASSIGN REG GREATER_GREATER expr vmod
2175 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2177 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2178 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2181 return yyerror ("Register mismatch");
2185 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2187 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2188 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2190 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2192 notethat ("PTR2op: pregs = pregs >> 2\n");
2193 $$ = PTR2OP (&$1, &$3, 3);
2195 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2197 notethat ("PTR2op: pregs = pregs >> 1\n");
2198 $$ = PTR2OP (&$1, &$3, 4);
2201 return yyerror ("Register mismatch");
2204 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2206 if (IS_UIMM ($5, 5))
2208 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2209 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2212 return yyerror ("Register mismatch");
2214 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2216 if (IS_UIMM ($5, 5))
2218 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2219 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2220 $6.s0, HL2 ($1, $3));
2223 return yyerror ("Register or modifier mismatch");
2227 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2229 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2234 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2235 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2239 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2240 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2244 return yyerror ("Register mismatch");
2247 | HALF_REG ASSIGN ONES REG
2249 if (IS_DREG_L ($1) && IS_DREG ($4))
2251 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2252 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2255 return yyerror ("Register mismatch");
2258 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2260 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2262 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2263 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2266 return yyerror ("Register mismatch");
2269 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2272 && $7.regno == REG_A0
2273 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2275 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2276 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2279 return yyerror ("Register mismatch");
2282 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2285 && $7.regno == REG_A0
2286 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2288 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2289 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2292 return yyerror ("Register mismatch");
2295 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2297 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2299 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2300 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2303 return yyerror ("Register mismatch");
2306 | a_assign ROT REG_A BY HALF_REG
2308 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2310 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2311 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2314 return yyerror ("Register mismatch");
2317 | REG ASSIGN ROT REG BY HALF_REG
2319 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2321 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2322 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2325 return yyerror ("Register mismatch");
2328 | a_assign ROT REG_A BY expr
2332 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2333 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2336 return yyerror ("Register mismatch");
2339 | REG ASSIGN ROT REG BY expr
2341 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2343 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2346 return yyerror ("Register mismatch");
2349 | HALF_REG ASSIGN SIGNBITS REG_A
2353 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2354 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2357 return yyerror ("Register mismatch");
2360 | HALF_REG ASSIGN SIGNBITS REG
2362 if (IS_DREG_L ($1) && IS_DREG ($4))
2364 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2365 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2368 return yyerror ("Register mismatch");
2371 | HALF_REG ASSIGN SIGNBITS HALF_REG
2375 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2376 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2379 return yyerror ("Register mismatch");
2382 /* The ASR bit is just inverted here. */
2383 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2385 if (IS_DREG_L ($1) && IS_DREG ($5))
2387 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2388 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2391 return yyerror ("Register mismatch");
2394 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2396 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2398 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2399 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2402 return yyerror ("Register mismatch");
2405 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2407 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2409 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2410 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2413 return yyerror ("Register mismatch");
2416 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2418 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2420 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2421 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2424 return yyerror ("Dregs expected");
2428 /* LOGI2op: BITCLR (dregs, uimm5). */
2429 | BITCLR LPAREN REG COMMA expr RPAREN
2431 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2433 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2434 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2437 return yyerror ("Register mismatch");
2440 /* LOGI2op: BITSET (dregs, uimm5). */
2441 | BITSET LPAREN REG COMMA expr RPAREN
2443 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2445 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2446 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2449 return yyerror ("Register mismatch");
2452 /* LOGI2op: BITTGL (dregs, uimm5). */
2453 | BITTGL LPAREN REG COMMA expr RPAREN
2455 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2457 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2458 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2461 return yyerror ("Register mismatch");
2464 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2466 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2468 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2469 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2472 return yyerror ("Register mismatch or value error");
2475 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2477 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2479 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2480 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2483 return yyerror ("Register mismatch or value error");
2486 | IF BANG CCREG REG ASSIGN REG
2488 if ((IS_DREG ($4) || IS_PREG ($4))
2489 && (IS_DREG ($6) || IS_PREG ($6)))
2491 notethat ("ccMV: IF ! CC gregs = gregs\n");
2492 $$ = CCMV (&$6, &$4, 0);
2495 return yyerror ("Register mismatch");
2498 | IF CCREG REG ASSIGN REG
2500 if ((IS_DREG ($5) || IS_PREG ($5))
2501 && (IS_DREG ($3) || IS_PREG ($3)))
2503 notethat ("ccMV: IF CC gregs = gregs\n");
2504 $$ = CCMV (&$5, &$3, 1);
2507 return yyerror ("Register mismatch");
2510 | IF BANG CCREG JUMP expr
2512 if (IS_PCREL10 ($5))
2514 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2515 $$ = BRCC (0, 0, $5);
2518 return yyerror ("Bad jump offset");
2521 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2523 if (IS_PCREL10 ($5))
2525 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2526 $$ = BRCC (0, 1, $5);
2529 return yyerror ("Bad jump offset");
2532 | IF CCREG JUMP expr
2534 if (IS_PCREL10 ($4))
2536 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2537 $$ = BRCC (1, 0, $4);
2540 return yyerror ("Bad jump offset");
2543 | IF CCREG JUMP expr LPAREN BP RPAREN
2545 if (IS_PCREL10 ($4))
2547 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2548 $$ = BRCC (1, 1, $4);
2551 return yyerror ("Bad jump offset");
2555 notethat ("ProgCtrl: NOP\n");
2556 $$ = PROGCTRL (0, 0);
2561 notethat ("ProgCtrl: RTS\n");
2562 $$ = PROGCTRL (1, 0);
2567 notethat ("ProgCtrl: RTI\n");
2568 $$ = PROGCTRL (1, 1);
2573 notethat ("ProgCtrl: RTX\n");
2574 $$ = PROGCTRL (1, 2);
2579 notethat ("ProgCtrl: RTN\n");
2580 $$ = PROGCTRL (1, 3);
2585 notethat ("ProgCtrl: RTE\n");
2586 $$ = PROGCTRL (1, 4);
2591 notethat ("ProgCtrl: IDLE\n");
2592 $$ = PROGCTRL (2, 0);
2597 notethat ("ProgCtrl: CSYNC\n");
2598 $$ = PROGCTRL (2, 3);
2603 notethat ("ProgCtrl: SSYNC\n");
2604 $$ = PROGCTRL (2, 4);
2609 notethat ("ProgCtrl: EMUEXCPT\n");
2610 $$ = PROGCTRL (2, 5);
2617 notethat ("ProgCtrl: CLI dregs\n");
2618 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2621 return yyerror ("Dreg expected for CLI");
2628 notethat ("ProgCtrl: STI dregs\n");
2629 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2632 return yyerror ("Dreg expected for STI");
2635 | JUMP LPAREN REG RPAREN
2639 notethat ("ProgCtrl: JUMP (pregs )\n");
2640 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2643 return yyerror ("Bad register for indirect jump");
2646 | CALL LPAREN REG RPAREN
2650 notethat ("ProgCtrl: CALL (pregs )\n");
2651 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2654 return yyerror ("Bad register for indirect call");
2657 | CALL LPAREN PC PLUS REG RPAREN
2661 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2662 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2665 return yyerror ("Bad register for indirect call");
2668 | JUMP LPAREN PC PLUS REG RPAREN
2672 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2673 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2676 return yyerror ("Bad register for indirect jump");
2681 if (IS_UIMM ($2, 4))
2683 notethat ("ProgCtrl: RAISE uimm4\n");
2684 $$ = PROGCTRL (9, uimm4 ($2));
2687 return yyerror ("Bad value for RAISE");
2692 notethat ("ProgCtrl: EMUEXCPT\n");
2693 $$ = PROGCTRL (10, uimm4 ($2));
2696 | TESTSET LPAREN REG RPAREN
2700 if ($3.regno == REG_SP || $3.regno == REG_FP)
2701 return yyerror ("Bad register for TESTSET");
2703 notethat ("ProgCtrl: TESTSET (pregs )\n");
2704 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2707 return yyerror ("Preg expected");
2712 if (IS_PCREL12 ($2))
2714 notethat ("UJUMP: JUMP pcrel12\n");
2718 return yyerror ("Bad value for relative jump");
2723 if (IS_PCREL12 ($2))
2725 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2729 return yyerror ("Bad value for relative jump");
2734 if (IS_PCREL24 ($2))
2736 notethat ("CALLa: jump.l pcrel24\n");
2740 return yyerror ("Bad value for long jump");
2745 if (IS_PCREL24 ($2))
2747 notethat ("CALLa: jump.l pcrel24\n");
2751 return yyerror ("Bad value for long jump");
2756 if (IS_PCREL24 ($2))
2758 notethat ("CALLa: CALL pcrel25m2\n");
2762 return yyerror ("Bad call address");
2766 if (IS_PCREL24 ($2))
2768 notethat ("CALLa: CALL pcrel25m2\n");
2772 return yyerror ("Bad call address");
2776 /* ALU2op: DIVQ (dregs, dregs). */
2777 | DIVQ LPAREN REG COMMA REG RPAREN
2779 if (IS_DREG ($3) && IS_DREG ($5))
2780 $$ = ALU2OP (&$3, &$5, 8);
2782 return yyerror ("Bad registers for DIVQ");
2785 | DIVS LPAREN REG COMMA REG RPAREN
2787 if (IS_DREG ($3) && IS_DREG ($5))
2788 $$ = ALU2OP (&$3, &$5, 9);
2790 return yyerror ("Bad registers for DIVS");
2793 | REG ASSIGN MINUS REG vsmod
2795 if (IS_DREG ($1) && IS_DREG ($4))
2797 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2799 notethat ("ALU2op: dregs = - dregs\n");
2800 $$ = ALU2OP (&$1, &$4, 14);
2802 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2804 notethat ("dsp32alu: dregs = - dregs (.)\n");
2805 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2809 notethat ("dsp32alu: dregs = - dregs (.)\n");
2810 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2814 return yyerror ("Dregs expected");
2817 | REG ASSIGN TILDA REG
2819 if (IS_DREG ($1) && IS_DREG ($4))
2821 notethat ("ALU2op: dregs = ~dregs\n");
2822 $$ = ALU2OP (&$1, &$4, 15);
2825 return yyerror ("Dregs expected");
2828 | REG _GREATER_GREATER_ASSIGN REG
2830 if (IS_DREG ($1) && IS_DREG ($3))
2832 notethat ("ALU2op: dregs >>= dregs\n");
2833 $$ = ALU2OP (&$1, &$3, 1);
2836 return yyerror ("Dregs expected");
2839 | REG _GREATER_GREATER_ASSIGN expr
2841 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2843 notethat ("LOGI2op: dregs >>= uimm5\n");
2844 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2847 return yyerror ("Dregs expected or value error");
2850 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2852 if (IS_DREG ($1) && IS_DREG ($3))
2854 notethat ("ALU2op: dregs >>>= dregs\n");
2855 $$ = ALU2OP (&$1, &$3, 0);
2858 return yyerror ("Dregs expected");
2861 | REG _LESS_LESS_ASSIGN REG
2863 if (IS_DREG ($1) && IS_DREG ($3))
2865 notethat ("ALU2op: dregs <<= dregs\n");
2866 $$ = ALU2OP (&$1, &$3, 2);
2869 return yyerror ("Dregs expected");
2872 | REG _LESS_LESS_ASSIGN expr
2874 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2876 notethat ("LOGI2op: dregs <<= uimm5\n");
2877 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2880 return yyerror ("Dregs expected or const value error");
2884 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2886 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2888 notethat ("LOGI2op: dregs >>>= uimm5\n");
2889 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2892 return yyerror ("Dregs expected");
2895 /* Cache Control. */
2897 | FLUSH LBRACK REG RBRACK
2899 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2901 $$ = CACTRL (&$3, 0, 2);
2903 return yyerror ("Bad register(s) for FLUSH");
2906 | FLUSH reg_with_postinc
2910 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2911 $$ = CACTRL (&$2, 1, 2);
2914 return yyerror ("Bad register(s) for FLUSH");
2917 | FLUSHINV LBRACK REG RBRACK
2921 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2922 $$ = CACTRL (&$3, 0, 1);
2925 return yyerror ("Bad register(s) for FLUSH");
2928 | FLUSHINV reg_with_postinc
2932 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2933 $$ = CACTRL (&$2, 1, 1);
2936 return yyerror ("Bad register(s) for FLUSH");
2939 /* CaCTRL: IFLUSH [pregs]. */
2940 | IFLUSH LBRACK REG RBRACK
2944 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2945 $$ = CACTRL (&$3, 0, 3);
2948 return yyerror ("Bad register(s) for FLUSH");
2951 | IFLUSH reg_with_postinc
2955 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2956 $$ = CACTRL (&$2, 1, 3);
2959 return yyerror ("Bad register(s) for FLUSH");
2962 | PREFETCH LBRACK REG RBRACK
2966 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2967 $$ = CACTRL (&$3, 0, 0);
2970 return yyerror ("Bad register(s) for PREFETCH");
2973 | PREFETCH reg_with_postinc
2977 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2978 $$ = CACTRL (&$2, 1, 0);
2981 return yyerror ("Bad register(s) for PREFETCH");
2985 /* LDST: B [ pregs <post_op> ] = dregs. */
2987 | B LBRACK REG post_op RBRACK ASSIGN REG
2990 return yyerror ("Dreg expected for source operand");
2992 return yyerror ("Preg expected in address");
2994 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2995 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2998 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2999 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
3001 Expr_Node *tmp = $5;
3004 return yyerror ("Dreg expected for source operand");
3006 return yyerror ("Preg expected in address");
3009 return yyerror ("Plain symbol used as offset");
3012 tmp = unary (Expr_Op_Type_NEG, tmp);
3014 if (in_range_p (tmp, -32768, 32767, 0))
3016 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
3017 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
3020 return yyerror ("Displacement out of range");
3024 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
3025 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
3027 Expr_Node *tmp = $5;
3030 return yyerror ("Dreg expected for source operand");
3032 return yyerror ("Preg expected in address");
3035 tmp = unary (Expr_Op_Type_NEG, tmp);
3038 return yyerror ("Plain symbol used as offset");
3040 if (in_range_p (tmp, 0, 30, 1))
3042 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
3043 $$ = LDSTII (&$3, &$8, tmp, 1, 1);
3045 else if (in_range_p (tmp, -65536, 65535, 1))
3047 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
3048 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp);
3051 return yyerror ("Displacement out of range");
3054 /* LDST: W [ pregs <post_op> ] = dregs. */
3055 | W LBRACK REG post_op RBRACK ASSIGN REG
3058 return yyerror ("Dreg expected for source operand");
3060 return yyerror ("Preg expected in address");
3062 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
3063 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
3066 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3069 return yyerror ("Dreg expected for source operand");
3072 if (!IS_IREG ($3) && !IS_PREG ($3))
3073 return yyerror ("Ireg or Preg expected in address");
3075 else if (!IS_IREG ($3))
3076 return yyerror ("Ireg expected in address");
3080 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3081 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3085 notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
3086 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3090 /* LDSTiiFP: [ FP - const ] = dpregs. */
3091 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3093 Expr_Node *tmp = $4;
3094 int ispreg = IS_PREG ($7);
3097 return yyerror ("Preg expected in address");
3099 if (!IS_DREG ($7) && !ispreg)
3100 return yyerror ("Preg expected for source operand");
3103 tmp = unary (Expr_Op_Type_NEG, tmp);
3106 return yyerror ("Plain symbol used as offset");
3108 if (in_range_p (tmp, 0, 63, 3))
3110 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3111 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3113 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3115 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3116 tmp = unary (Expr_Op_Type_NEG, tmp);
3117 $$ = LDSTIIFP (tmp, &$7, 1);
3119 else if (in_range_p (tmp, -131072, 131071, 3))
3121 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3122 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp);
3125 return yyerror ("Displacement out of range");
3128 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3130 Expr_Node *tmp = $7;
3132 return yyerror ("Dreg expected for destination operand");
3134 return yyerror ("Preg expected in address");
3137 tmp = unary (Expr_Op_Type_NEG, tmp);
3140 return yyerror ("Plain symbol used as offset");
3142 if (in_range_p (tmp, 0, 30, 1))
3144 notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3145 $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0);
3147 else if (in_range_p (tmp, -65536, 65535, 1))
3149 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3150 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp);
3153 return yyerror ("Displacement out of range");
3156 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3159 return yyerror ("Dreg expected for source operand");
3162 if (!IS_IREG ($5) && !IS_PREG ($5))
3163 return yyerror ("Ireg or Preg expected in address");
3165 else if (!IS_IREG ($5))
3166 return yyerror ("Ireg expected in address");
3170 notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3171 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3175 notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3176 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3181 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3184 return yyerror ("Dreg expected for destination operand");
3186 return yyerror ("Preg expected in address");
3188 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3189 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3192 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3195 return yyerror ("Dreg expected for destination operand");
3196 if (!IS_PREG ($5) || !IS_PREG ($7))
3197 return yyerror ("Preg expected in address");
3199 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3200 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3203 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3206 return yyerror ("Dreg expected for destination operand");
3207 if (!IS_PREG ($5) || !IS_PREG ($7))
3208 return yyerror ("Preg expected in address");
3210 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3211 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3214 | LBRACK REG post_op RBRACK ASSIGN REG
3216 if (!IS_IREG ($2) && !IS_PREG ($2))
3217 return yyerror ("Ireg or Preg expected in address");
3218 else if (IS_IREG ($2) && !IS_DREG ($6))
3219 return yyerror ("Dreg expected for source operand");
3220 else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6))
3221 return yyerror ("Dreg or Preg expected for source operand");
3225 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3226 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3228 else if (IS_DREG ($6))
3230 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3231 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3235 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3236 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3240 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3243 return yyerror ("Dreg expected for source operand");
3245 if (IS_IREG ($2) && IS_MREG ($4))
3247 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3248 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3250 else if (IS_PREG ($2) && IS_PREG ($4))
3252 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3253 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3256 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3259 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3262 return yyerror ("Dreg expected for source operand");
3264 if (IS_PREG ($3) && IS_PREG ($5))
3266 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3267 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3270 return yyerror ("Preg ++ Preg expected in address");
3273 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3275 Expr_Node *tmp = $7;
3277 return yyerror ("Dreg expected for destination operand");
3279 return yyerror ("Preg expected in address");
3282 tmp = unary (Expr_Op_Type_NEG, tmp);
3285 return yyerror ("Plain symbol used as offset");
3287 if (in_range_p (tmp, -32768, 32767, 0))
3289 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3291 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp);
3294 return yyerror ("Displacement out of range");
3297 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3300 return yyerror ("Dreg expected for destination operand");
3302 return yyerror ("Preg expected in address");
3304 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3306 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3309 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3312 return yyerror ("Dreg expected for destination operand");
3314 if (IS_IREG ($4) && IS_MREG ($6))
3316 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3317 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3319 else if (IS_PREG ($4) && IS_PREG ($6))
3321 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3322 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3325 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3328 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3330 Expr_Node *tmp = $6;
3331 int ispreg = IS_PREG ($1);
3332 int isgot = IS_RELOC($6);
3335 return yyerror ("Preg expected in address");
3337 if (!IS_DREG ($1) && !ispreg)
3338 return yyerror ("Dreg or Preg expected for destination operand");
3340 if (tmp->type == Expr_Node_Reloc
3341 && strcmp (tmp->value.s_value,
3342 "_current_shared_library_p5_offset_") != 0)
3343 return yyerror ("Plain symbol used as offset");
3346 tmp = unary (Expr_Op_Type_NEG, tmp);
3350 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3351 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3353 else if (in_range_p (tmp, 0, 63, 3))
3355 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3356 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3358 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3360 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3361 tmp = unary (Expr_Op_Type_NEG, tmp);
3362 $$ = LDSTIIFP (tmp, &$1, 0);
3364 else if (in_range_p (tmp, -131072, 131071, 3))
3366 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3367 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3371 return yyerror ("Displacement out of range");
3374 | REG ASSIGN LBRACK REG post_op RBRACK
3376 if (!IS_IREG ($4) && !IS_PREG ($4))
3377 return yyerror ("Ireg or Preg expected in address");
3378 else if (IS_IREG ($4) && !IS_DREG ($1))
3379 return yyerror ("Dreg expected in destination operand");
3380 else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1)
3381 && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0))
3382 return yyerror ("Dreg or Preg expected in destination operand");
3386 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3387 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3389 else if (IS_DREG ($1))
3391 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3392 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3394 else if (IS_PREG ($1))
3396 if (REG_SAME ($1, $4) && $5.x0 != 2)
3397 return yyerror ("Pregs can't be same");
3399 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3400 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3404 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3405 $$ = PUSHPOPREG (&$1, 0);
3410 /* PushPopMultiple. */
3411 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3413 if ($1.regno != REG_SP)
3414 yyerror ("Stack Pointer expected");
3415 if ($4.regno == REG_R7
3416 && IN_RANGE ($6, 0, 7)
3417 && $8.regno == REG_P5
3418 && IN_RANGE ($10, 0, 5))
3420 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3421 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3424 return yyerror ("Bad register for PushPopMultiple");
3427 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3429 if ($1.regno != REG_SP)
3430 yyerror ("Stack Pointer expected");
3432 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3434 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3435 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3437 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3439 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3440 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3443 return yyerror ("Bad register for PushPopMultiple");
3446 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3448 if ($11.regno != REG_SP)
3449 yyerror ("Stack Pointer expected");
3450 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3451 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3453 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3454 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3457 return yyerror ("Bad register range for PushPopMultiple");
3460 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3462 if ($7.regno != REG_SP)
3463 yyerror ("Stack Pointer expected");
3465 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3467 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3468 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3470 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3472 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3473 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3476 return yyerror ("Bad register range for PushPopMultiple");
3479 | reg_with_predec ASSIGN REG
3481 if ($1.regno != REG_SP)
3482 yyerror ("Stack Pointer expected");
3486 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3487 $$ = PUSHPOPREG (&$3, 1);
3490 return yyerror ("Bad register for PushPopReg");
3497 if (IS_URANGE (16, $2, 0, 4))
3498 $$ = LINKAGE (0, uimm16s4 ($2));
3500 return yyerror ("Bad constant for LINK");
3505 notethat ("linkage: UNLINK\n");
3506 $$ = LINKAGE (1, 0);
3512 | LSETUP LPAREN expr COMMA expr RPAREN REG
3514 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3516 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3517 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3520 return yyerror ("Bad register or values for LSETUP");
3523 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3525 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3526 && IS_PREG ($9) && IS_CREG ($7))
3528 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3529 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3532 return yyerror ("Bad register or values for LSETUP");
3535 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3537 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3538 && IS_PREG ($9) && IS_CREG ($7)
3539 && EXPR_VALUE ($11) == 1)
3541 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3542 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3545 return yyerror ("Bad register or values for LSETUP");
3552 return yyerror ("Invalid expression in loop statement");
3554 return yyerror ("Invalid loop counter register");
3555 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3557 | LOOP expr REG ASSIGN REG
3559 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3561 notethat ("Loop: LOOP expr counters = pregs\n");
3562 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3565 return yyerror ("Bad register or values for LOOP");
3567 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3569 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3571 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3572 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3575 return yyerror ("Bad register or values for LOOP");
3581 Expr_Node_Value val;
3583 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3584 bfin_loop_attempt_create_label (tmp, 1);
3585 if (!IS_RELOC (tmp))
3586 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3587 bfin_loop_beginend (tmp, 1);
3593 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3595 bfin_loop_beginend ($2, 1);
3602 Expr_Node_Value val;
3604 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3605 bfin_loop_attempt_create_label (tmp, 1);
3606 if (!IS_RELOC (tmp))
3607 return yyerror ("Invalid expression in LOOP_END statement");
3608 bfin_loop_beginend (tmp, 0);
3614 return yyerror ("Invalid expression in LOOP_END statement");
3616 bfin_loop_beginend ($2, 0);
3624 notethat ("psedoDEBUG: ABORT\n");
3625 $$ = bfin_gen_pseudodbg (3, 3, 0);
3630 notethat ("pseudoDEBUG: DBG\n");
3631 $$ = bfin_gen_pseudodbg (3, 7, 0);
3635 notethat ("pseudoDEBUG: DBG REG_A\n");
3636 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3640 notethat ("pseudoDEBUG: DBG allregs\n");
3641 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, ($2.regno & CLASS_MASK) >> 4);
3644 | DBGCMPLX LPAREN REG RPAREN
3647 return yyerror ("Dregs expected");
3648 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3649 $$ = bfin_gen_pseudodbg (3, 6, ($3.regno & CODE_MASK) >> 4);
3654 notethat ("psedoDEBUG: DBGHALT\n");
3655 $$ = bfin_gen_pseudodbg (3, 5, 0);
3660 notethat ("psedoDEBUG: HLT\n");
3661 $$ = bfin_gen_pseudodbg (3, 4, 0);
3664 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3666 notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
3667 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3670 | DBGAH LPAREN REG COMMA expr RPAREN
3672 notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
3673 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3676 | DBGAL LPAREN REG COMMA expr RPAREN
3678 notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
3679 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3684 if (!IS_UIMM ($2, 8))
3685 return yyerror ("Constant out of range");
3686 notethat ("psedodbg_assert: OUTC uimm8\n");
3687 $$ = bfin_gen_pseudochr (uimm8 ($2));
3693 return yyerror ("Dregs expected");
3694 notethat ("psedodbg_assert: OUTC dreg\n");
3695 $$ = bfin_gen_pseudodbg (2, $2.regno & CODE_MASK, 0);
3702 /* Register rules. */
3704 REG_A: REG_A_DOUBLE_ZERO
3722 | LPAREN M COMMA MMOD RPAREN
3727 | LPAREN MMOD COMMA M RPAREN
3732 | LPAREN MMOD RPAREN
3744 asr_asl: LPAREN ASL RPAREN
3825 | LPAREN asr_asl_0 RPAREN
3837 | LPAREN asr_asl_0 COMMA sco RPAREN
3843 | LPAREN sco COMMA asr_asl_0 RPAREN
3903 | LPAREN V COMMA S RPAREN
3908 | LPAREN S COMMA V RPAREN
3970 | LPAREN MMOD RPAREN
3973 return yyerror ("Bad modifier");
3977 | LPAREN MMOD COMMA R RPAREN
3980 return yyerror ("Bad modifier");
3984 | LPAREN R COMMA MMOD RPAREN
3987 return yyerror ("Bad modifier");
4014 | LPAREN MMOD RPAREN
4019 return yyerror ("Only (W32) allowed");
4027 | LPAREN MMOD RPAREN
4032 return yyerror ("(IU) expected");
4036 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
4042 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
4094 $$.r0 = 1; /* HL. */
4097 $$.aop = 0; /* aop. */
4102 $$.r0 = 1; /* HL. */
4105 $$.aop = 1; /* aop. */
4108 | LPAREN RNDL RPAREN
4110 $$.r0 = 0; /* HL. */
4113 $$.aop = 0; /* aop. */
4118 $$.r0 = 0; /* HL. */
4124 | LPAREN RNDH COMMA R RPAREN
4126 $$.r0 = 1; /* HL. */
4129 $$.aop = 0; /* aop. */
4131 | LPAREN TH COMMA R RPAREN
4133 $$.r0 = 1; /* HL. */
4136 $$.aop = 1; /* aop. */
4138 | LPAREN RNDL COMMA R RPAREN
4140 $$.r0 = 0; /* HL. */
4143 $$.aop = 0; /* aop. */
4146 | LPAREN TL COMMA R RPAREN
4148 $$.r0 = 0; /* HL. */
4151 $$.aop = 1; /* aop. */
4159 $$.x0 = 0; /* HL. */
4164 $$.x0 = 1; /* HL. */
4166 | LPAREN LO COMMA R RPAREN
4169 $$.x0 = 0; /* HL. */
4171 | LPAREN HI COMMA R RPAREN
4174 $$.x0 = 1; /* HL. */
4192 /* Assignments, Macfuncs. */
4218 if (IS_A1 ($3) && IS_EVEN ($1))
4219 return yyerror ("Cannot move A1 to even register");
4220 else if (!IS_A1 ($3) && !IS_EVEN ($1))
4221 return yyerror ("Cannot move A0 to odd register");
4237 | REG ASSIGN LPAREN a_macfunc RPAREN
4239 if ($4.n && IS_EVEN ($1))
4240 return yyerror ("Cannot move A1 to even register");
4241 else if (!$4.n && !IS_EVEN ($1))
4242 return yyerror ("Cannot move A0 to odd register");
4250 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4252 if ($4.n && !IS_H ($1))
4253 return yyerror ("Cannot move A1 to low half of register");
4254 else if (!$4.n && IS_H ($1))
4255 return yyerror ("Cannot move A0 to high half of register");
4263 | HALF_REG ASSIGN REG_A
4265 if (IS_A1 ($3) && !IS_H ($1))
4266 return yyerror ("Cannot move A1 to low half of register");
4267 else if (!IS_A1 ($3) && IS_H ($1))
4268 return yyerror ("Cannot move A0 to high half of register");
4281 a_assign multiply_halfregs
4288 | a_plusassign multiply_halfregs
4295 | a_minusassign multiply_halfregs
4305 HALF_REG STAR HALF_REG
4307 if (IS_DREG ($1) && IS_DREG ($3))
4313 return yyerror ("Dregs expected");
4337 CCREG cc_op STATUS_REG
4349 | STATUS_REG cc_op CCREG
4363 /* Expressions and Symbols. */
4367 Expr_Node_Value val;
4368 val.s_value = S_GET_NAME($1);
4369 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4375 { $$ = BFD_RELOC_BFIN_GOT; }
4377 { $$ = BFD_RELOC_BFIN_GOT17M4; }
4379 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4382 got: symbol AT any_gotrel
4384 Expr_Node_Value val;
4386 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4409 Expr_Node_Value val;
4411 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4417 | LPAREN expr_1 RPAREN
4423 $$ = unary (Expr_Op_Type_COMP, $2);
4425 | MINUS expr_1 %prec TILDA
4427 $$ = unary (Expr_Op_Type_NEG, $2);
4437 expr_1: expr_1 STAR expr_1
4439 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4441 | expr_1 SLASH expr_1
4443 $$ = binary (Expr_Op_Type_Div, $1, $3);
4445 | expr_1 PERCENT expr_1
4447 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4449 | expr_1 PLUS expr_1
4451 $$ = binary (Expr_Op_Type_Add, $1, $3);
4453 | expr_1 MINUS expr_1
4455 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4457 | expr_1 LESS_LESS expr_1
4459 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4461 | expr_1 GREATER_GREATER expr_1
4463 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4465 | expr_1 AMPERSAND expr_1
4467 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4469 | expr_1 CARET expr_1
4471 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4475 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4487 mkexpr (int x, SYMBOL_T s)
4489 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4496 value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
4498 int umax = (1 << sz) - 1;
4499 int min = -1 << (sz - 1);
4500 int max = (1 << (sz - 1)) - 1;
4502 int v = (EXPR_VALUE (exp)) & 0xffffffff;
4506 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4517 if (v >= min && v <= max) return 1;
4520 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4524 if (v <= umax && v >= 0)
4527 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4532 /* Return the expression structure that allows symbol operations.
4533 If the left and right children are constants, do the operation. */
4535 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4537 Expr_Node_Value val;
4539 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4543 case Expr_Op_Type_Add:
4544 x->value.i_value += y->value.i_value;
4546 case Expr_Op_Type_Sub:
4547 x->value.i_value -= y->value.i_value;
4549 case Expr_Op_Type_Mult:
4550 x->value.i_value *= y->value.i_value;
4552 case Expr_Op_Type_Div:
4553 if (y->value.i_value == 0)
4554 error ("Illegal Expression: Division by zero.");
4556 x->value.i_value /= y->value.i_value;
4558 case Expr_Op_Type_Mod:
4559 x->value.i_value %= y->value.i_value;
4561 case Expr_Op_Type_Lshift:
4562 x->value.i_value <<= y->value.i_value;
4564 case Expr_Op_Type_Rshift:
4565 x->value.i_value >>= y->value.i_value;
4567 case Expr_Op_Type_BAND:
4568 x->value.i_value &= y->value.i_value;
4570 case Expr_Op_Type_BOR:
4571 x->value.i_value |= y->value.i_value;
4573 case Expr_Op_Type_BXOR:
4574 x->value.i_value ^= y->value.i_value;
4576 case Expr_Op_Type_LAND:
4577 x->value.i_value = x->value.i_value && y->value.i_value;
4579 case Expr_Op_Type_LOR:
4580 x->value.i_value = x->value.i_value || y->value.i_value;
4584 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4588 /* Canonicalize order to EXPR OP CONSTANT. */
4589 if (x->type == Expr_Node_Constant)
4595 /* Canonicalize subtraction of const to addition of negated const. */
4596 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4598 op = Expr_Op_Type_Add;
4599 y->value.i_value = -y->value.i_value;
4601 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4602 && x->Right_Child->type == Expr_Node_Constant)
4604 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4606 x->Right_Child->value.i_value += y->value.i_value;
4611 /* Create a new expression structure. */
4613 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4617 unary (Expr_Op_Type op, Expr_Node *x)
4619 if (x->type == Expr_Node_Constant)
4623 case Expr_Op_Type_NEG:
4624 x->value.i_value = -x->value.i_value;
4626 case Expr_Op_Type_COMP:
4627 x->value.i_value = ~x->value.i_value;
4630 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4636 /* Create a new expression structure. */
4637 Expr_Node_Value val;
4639 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4643 int debug_codeselection = 0;
4645 notethat (char *format, ...)
4648 va_start (ap, format);
4649 if (debug_codeselection)
4651 vfprintf (errorf, format, ap);
4657 main (int argc, char **argv)