2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 /* Please note that modifications to all structs defined here are
32 * subject to backwards-compatibility constraints:
33 * 1) Do not use pointers, use uint64_t instead for 32 bit / 64 bit
34 * user/kernel compatibility
35 * 2) Keep fields aligned to their size
36 * 3) Because of how drm_ioctl() works, we can add new fields at
37 * the end of an ioctl if some care is taken: drm_ioctl() will
38 * zero out the new fields at the tail of the ioctl, so a zero
39 * value should have a backwards compatible meaning. And for
40 * output params, userspace won't see the newly added output
41 * fields.. so that has to be somehow ok.
44 #define MSM_PIPE_NONE 0x00
45 #define MSM_PIPE_2D0 0x01
46 #define MSM_PIPE_2D1 0x02
47 #define MSM_PIPE_3D0 0x10
49 /* timeouts are specified in clock-monotonic absolute times (to simplify
50 * restarting interrupted ioctls). The following struct is logically the
51 * same as 'struct timespec' but 32/64b ABI safe.
53 struct drm_msm_timespec {
54 int64_t tv_sec; /* seconds */
55 int64_t tv_nsec; /* nanoseconds */
58 #define MSM_PARAM_GPU_ID 0x01
59 #define MSM_PARAM_GMEM_SIZE 0x02
61 struct drm_msm_param {
62 uint32_t pipe; /* in, MSM_PIPE_x */
63 uint32_t param; /* in, MSM_PARAM_x */
64 uint64_t value; /* out (get_param) or in (set_param) */
71 #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
72 #define MSM_BO_GPU_READONLY 0x00000002
73 #define MSM_BO_CACHE_MASK 0x000f0000
75 #define MSM_BO_CACHED 0x00010000
76 #define MSM_BO_WC 0x00020000
77 #define MSM_BO_UNCACHED 0x00040000
79 struct drm_msm_gem_new {
80 uint64_t size; /* in */
81 uint32_t flags; /* in, mask of MSM_BO_x */
82 uint32_t handle; /* out */
85 struct drm_msm_gem_info {
86 uint32_t handle; /* in */
88 uint64_t offset; /* out, offset to pass to mmap() */
91 #define MSM_PREP_READ 0x01
92 #define MSM_PREP_WRITE 0x02
93 #define MSM_PREP_NOSYNC 0x04
95 struct drm_msm_gem_cpu_prep {
96 uint32_t handle; /* in */
97 uint32_t op; /* in, mask of MSM_PREP_x */
98 struct drm_msm_timespec timeout; /* in */
101 struct drm_msm_gem_cpu_fini {
102 uint32_t handle; /* in */
106 * Cmdstream Submission:
109 /* The value written into the cmdstream is logically:
111 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or
113 * When we have GPU's w/ >32bit ptrs, it should be possible to deal
114 * with this by emit'ing two reloc entries with appropriate shift
115 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
117 * NOTE that reloc's must be sorted by order of increasing submit_offset,
120 struct drm_msm_gem_submit_reloc {
121 uint32_t submit_offset; /* in, offset from submit_bo */
122 uint32_t or; /* in, value OR'd with result */
123 int32_t shift; /* in, amount of left shift (can be negative) */
124 uint32_t reloc_idx; /* in, index of reloc_bo buffer */
125 uint64_t reloc_offset; /* in, offset from start of reloc_bo */
129 * BUF - this cmd buffer is executed normally.
130 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
131 * processed normally, but the kernel does not setup an IB to
132 * this buffer in the first-level ringbuffer
133 * CTX_RESTORE_BUF - only executed if there has been a GPU context
134 * switch since the last SUBMIT ioctl
136 #define MSM_SUBMIT_CMD_BUF 0x0001
137 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
138 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
139 struct drm_msm_gem_submit_cmd {
140 uint32_t type; /* in, one of MSM_SUBMIT_CMD_x */
141 uint32_t submit_idx; /* in, index of submit_bo cmdstream buffer */
142 uint32_t submit_offset; /* in, offset into submit_bo */
143 uint32_t size; /* in, cmdstream size */
145 uint32_t nr_relocs; /* in, number of submit_reloc's */
146 uint64_t __user relocs; /* in, ptr to array of submit_reloc's */
149 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
150 * cmdstream buffer(s) themselves or reloc entries) has one (and only
151 * one) entry in the submit->bos[] table.
153 * As a optimization, the current buffer (gpu virtual address) can be
154 * passed back through the 'presumed' field. If on a subsequent reloc,
155 * userspace passes back a 'presumed' address that is still valid,
156 * then patching the cmdstream for this entry is skipped. This can
157 * avoid kernel needing to map/access the cmdstream bo in the common
160 #define MSM_SUBMIT_BO_READ 0x0001
161 #define MSM_SUBMIT_BO_WRITE 0x0002
162 struct drm_msm_gem_submit_bo {
163 uint32_t flags; /* in, mask of MSM_SUBMIT_BO_x */
164 uint32_t handle; /* in, GEM handle */
165 uint64_t presumed; /* in/out, presumed buffer address */
168 /* Each cmdstream submit consists of a table of buffers involved, and
169 * one or more cmdstream buffers. This allows for conditional execution
170 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
172 struct drm_msm_gem_submit {
173 uint32_t pipe; /* in, MSM_PIPE_x */
174 uint32_t fence; /* out */
175 uint32_t nr_bos; /* in, number of submit_bo's */
176 uint32_t nr_cmds; /* in, number of submit_cmd's */
177 uint64_t __user bos; /* in, ptr to array of submit_bo's */
178 uint64_t __user cmds; /* in, ptr to array of submit_cmd's */
181 /* The normal way to synchronize with the GPU is just to CPU_PREP on
182 * a buffer if you need to access it from the CPU (other cmdstream
183 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
184 * handle the required synchronization under the hood). This ioctl
185 * mainly just exists as a way to implement the gallium pipe_fence
186 * APIs without requiring a dummy bo to synchronize on.
188 struct drm_msm_wait_fence {
189 uint32_t fence; /* in */
191 struct drm_msm_timespec timeout; /* in */
194 #define DRM_MSM_GET_PARAM 0x00
196 #define DRM_MSM_SET_PARAM 0x01
198 #define DRM_MSM_GEM_NEW 0x02
199 #define DRM_MSM_GEM_INFO 0x03
200 #define DRM_MSM_GEM_CPU_PREP 0x04
201 #define DRM_MSM_GEM_CPU_FINI 0x05
202 #define DRM_MSM_GEM_SUBMIT 0x06
203 #define DRM_MSM_WAIT_FENCE 0x07
204 #define DRM_MSM_NUM_IOCTLS 0x08
206 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
207 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
208 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
209 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
210 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
211 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
212 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
214 #endif /* __MSM_DRM_H__ */