3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 * Seung-Woo Kim <sw0312.kim@samsung.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
29 #ifndef _EXYNOS_DRM_H_
30 #define _EXYNOS_DRM_H_
35 * User-desired buffer creation information structure.
37 * @size: user-desired memory allocation size.
38 * - this size value would be page-aligned internally.
39 * @flags: user request for setting memory type or cache attributes.
40 * @handle: returned a handle to created gem object.
41 * - this handle will be set by gem module of kernel side.
43 struct drm_exynos_gem_create {
50 * A structure for getting buffer offset.
52 * @handle: a pointer to gem object created.
53 * @pad: just padding to be 64-bit aligned.
54 * @offset: relatived offset value of the memory region allocated.
55 * - this value should be set by user.
57 struct drm_exynos_gem_map_off {
64 * A structure for mapping buffer.
66 * @handle: a handle to gem object created.
67 * @pad: just padding to be 64-bit aligned.
68 * @size: memory size to be mapped.
69 * @mapped: having user virtual address mmaped.
70 * - this variable would be filled by exynos gem module
71 * of kernel side with user virtual address which is allocated
74 struct drm_exynos_gem_mmap {
82 * A structure to gem information.
84 * @handle: a handle to gem object created.
85 * @flags: flag value including memory type and cache attribute and
86 * this value would be set by driver.
87 * @size: size to memory region allocated by gem and this size would
90 struct drm_exynos_gem_info {
97 * A structure for user connection request of virtual display.
99 * @connection: indicate whether doing connetion or not by user.
100 * @extensions: if this value is 1 then the vidi driver would need additional
101 * 128bytes edid data.
102 * @edid: the edid data pointer from user side.
104 struct drm_exynos_vidi_connection {
105 unsigned int connection;
106 unsigned int extensions;
110 /* memory type definitions. */
111 enum e_drm_exynos_gem_mem_type {
112 /* Physically Continuous memory and used as default. */
113 EXYNOS_BO_CONTIG = 0 << 0,
114 /* Physically Non-Continuous memory. */
115 EXYNOS_BO_NONCONTIG = 1 << 0,
116 /* non-cachable mapping and used as default. */
117 EXYNOS_BO_NONCACHABLE = 0 << 1,
118 /* cachable mapping. */
119 EXYNOS_BO_CACHABLE = 1 << 1,
120 /* write-combine mapping. */
121 EXYNOS_BO_WC = 1 << 2,
122 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
126 struct drm_exynos_g2d_get_ver {
131 struct drm_exynos_g2d_cmd {
136 enum drm_exynos_g2d_buf_type {
137 G2D_BUF_USERPTR = 1 << 31,
140 enum drm_exynos_g2d_event_type {
143 G2D_EVENT_STOP, /* not yet */
146 struct drm_exynos_g2d_userptr {
147 unsigned long userptr;
151 struct drm_exynos_g2d_set_cmdlist {
162 struct drm_exynos_g2d_exec {
166 /* definition of operations types */
167 enum drm_exynos_ops_id {
173 /* definition of size */
174 struct drm_exynos_sz {
179 /* definition of position */
180 struct drm_exynos_pos {
187 /* definition of flip */
188 enum drm_exynos_flip {
189 EXYNOS_DRM_FLIP_NONE = (0 << 0),
190 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
191 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
192 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
193 EXYNOS_DRM_FLIP_HORIZONTAL,
196 /* definition of rotation degree */
197 enum drm_exynos_degree {
199 EXYNOS_DRM_DEGREE_90,
200 EXYNOS_DRM_DEGREE_180,
201 EXYNOS_DRM_DEGREE_270,
204 /* definition of planar */
205 enum drm_exynos_planer {
207 EXYNOS_DRM_PLANAR_CB,
208 EXYNOS_DRM_PLANAR_CR,
209 EXYNOS_DRM_PLANAR_MAX,
213 * A structure for ipp supported property list.
215 * @version: version of this structure.
216 * @ipp_id: id of ipp driver.
217 * @count: count of ipp driver.
218 * @writeback: flag of writeback supporting.
219 * @flip: flag of flip supporting.
220 * @degree: flag of degree information.
221 * @csc: flag of csc supporting.
222 * @crop: flag of crop supporting.
223 * @scale: flag of scale supporting.
224 * @refresh_min: min hz of refresh.
225 * @refresh_max: max hz of refresh.
226 * @crop_min: crop min resolution.
227 * @crop_max: crop max resolution.
228 * @scale_min: scale min resolution.
229 * @scale_max: scale max resolution.
231 struct drm_exynos_ipp_prop_list {
244 struct drm_exynos_sz crop_min;
245 struct drm_exynos_sz crop_max;
246 struct drm_exynos_sz scale_min;
247 struct drm_exynos_sz scale_max;
251 * A structure for ipp config.
253 * @ops_id: property of operation directions.
254 * @flip: property of mirror, flip.
255 * @degree: property of rotation degree.
256 * @fmt: property of image format.
257 * @sz: property of image size.
258 * @pos: property of image position(src-cropped,dst-scaler).
260 struct drm_exynos_ipp_config {
261 enum drm_exynos_ops_id ops_id;
262 enum drm_exynos_flip flip;
263 enum drm_exynos_degree degree;
265 struct drm_exynos_sz sz;
266 struct drm_exynos_pos pos;
269 /* definition of command */
270 enum drm_exynos_ipp_cmd {
278 /* define of color range */
279 enum drm_exynos_color_range {
280 COLOR_RANGE_LIMITED, /* Narrow: Y(16 to 235), Cb/Cr(16 to 240) */
281 COLOR_RANGE_FULL, /* Wide: Y/Cb/Cr(0 to 255), Wide default */
285 * A structure for ipp property.
287 * @config: source, destination config.
288 * @cmd: definition of command.
289 * @ipp_id: id of ipp driver.
290 * @prop_id: id of property.
291 * @refresh_rate: refresh rate.
292 * @range: dynamic range for csc.
293 * @pad: just padding to be 64-bit aligned.
295 struct drm_exynos_ipp_property {
296 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
297 enum drm_exynos_ipp_cmd cmd;
305 /* definition of buffer */
306 enum drm_exynos_ipp_buf_type {
312 * A structure for ipp buffer operations.
314 * @ops_id: operation directions.
315 * @buf_type: definition of buffer.
316 * @prop_id: id of property.
317 * @buf_id: id of buffer.
318 * @handle: Y, Cb, Cr each planar handle.
319 * @user_data: user data.
321 struct drm_exynos_ipp_queue_buf {
322 enum drm_exynos_ops_id ops_id;
323 enum drm_exynos_ipp_buf_type buf_type;
326 __u32 handle[EXYNOS_DRM_PLANAR_MAX];
331 /* definition of control */
332 enum drm_exynos_ipp_ctrl {
341 * A structure for ipp start/stop operations.
343 * @prop_id: id of property.
344 * @ctrl: definition of control.
346 struct drm_exynos_ipp_cmd_ctrl {
348 enum drm_exynos_ipp_ctrl ctrl;
351 #define DRM_EXYNOS_GEM_CREATE 0x00
352 #define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
353 #define DRM_EXYNOS_GEM_MMAP 0x02
354 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
355 #define DRM_EXYNOS_GEM_GET 0x04
356 #define DRM_EXYNOS_VIDI_CONNECTION 0x07
359 #define DRM_EXYNOS_G2D_GET_VER 0x20
360 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
361 #define DRM_EXYNOS_G2D_EXEC 0x22
363 /* IPP - Image Post Processing */
364 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
365 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
366 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
367 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33
369 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
370 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
372 #define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
373 DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off)
375 #define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \
376 DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
378 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
379 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
381 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
382 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
384 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
385 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
386 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
387 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
388 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
389 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
391 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
392 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
393 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
394 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
395 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
396 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
397 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
398 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
400 /* EXYNOS specific events */
401 #define DRM_EXYNOS_G2D_EVENT 0x80000000
402 #define DRM_EXYNOS_IPP_EVENT 0x80000001
404 struct drm_exynos_g2d_event {
405 struct drm_event base;
413 struct drm_exynos_ipp_event {
414 struct drm_event base;
420 __u32 buf_id[EXYNOS_DRM_OPS_MAX];