3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 * Seung-Woo Kim <sw0312.kim@samsung.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
29 #ifndef _EXYNOS_DRM_H_
30 #define _EXYNOS_DRM_H_
35 * User-desired buffer creation information structure.
37 * @size: user-desired memory allocation size.
38 * - this size value would be page-aligned internally.
39 * @flags: user request for setting memory type or cache attributes.
40 * @handle: returned a handle to created gem object.
41 * - this handle will be set by gem module of kernel side.
43 struct drm_exynos_gem_create {
50 * A structure to gem information.
52 * @handle: a handle to gem object created.
53 * @flags: flag value including memory type and cache attribute and
54 * this value would be set by driver.
55 * @size: size to memory region allocated by gem and this size would
58 struct drm_exynos_gem_info {
65 * A structure for user connection request of virtual display.
67 * @connection: indicate whether doing connetion or not by user.
68 * @extensions: if this value is 1 then the vidi driver would need additional
70 * @edid: the edid data pointer from user side.
72 struct drm_exynos_vidi_connection {
73 unsigned int connection;
74 unsigned int extensions;
78 /* memory type definitions. */
79 enum e_drm_exynos_gem_mem_type {
80 /* Physically Continuous memory and used as default. */
81 EXYNOS_BO_CONTIG = 0 << 0,
82 /* Physically Non-Continuous memory. */
83 EXYNOS_BO_NONCONTIG = 1 << 0,
84 /* non-cachable mapping and used as default. */
85 EXYNOS_BO_NONCACHABLE = 0 << 1,
86 /* cachable mapping. */
87 EXYNOS_BO_CACHABLE = 1 << 1,
88 /* write-combine mapping. */
89 EXYNOS_BO_WC = 1 << 2,
90 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
94 struct drm_exynos_g2d_get_ver {
99 struct drm_exynos_g2d_cmd {
104 enum drm_exynos_g2d_buf_type {
105 G2D_BUF_USERPTR = 1 << 31,
108 enum drm_exynos_g2d_event_type {
111 G2D_EVENT_STOP, /* not yet */
114 struct drm_exynos_g2d_userptr {
115 unsigned long userptr;
119 struct drm_exynos_g2d_set_cmdlist {
130 struct drm_exynos_g2d_exec {
134 /* definition of operations types */
135 enum drm_exynos_ops_id {
141 /* definition of size */
142 struct drm_exynos_sz {
147 /* definition of position */
148 struct drm_exynos_pos {
155 /* definition of flip */
156 enum drm_exynos_flip {
157 EXYNOS_DRM_FLIP_NONE = (0 << 0),
158 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
159 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
160 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
161 EXYNOS_DRM_FLIP_HORIZONTAL,
164 /* definition of rotation degree */
165 enum drm_exynos_degree {
167 EXYNOS_DRM_DEGREE_90,
168 EXYNOS_DRM_DEGREE_180,
169 EXYNOS_DRM_DEGREE_270,
172 /* definition of planar */
173 enum drm_exynos_planer {
175 EXYNOS_DRM_PLANAR_CB,
176 EXYNOS_DRM_PLANAR_CR,
177 EXYNOS_DRM_PLANAR_MAX,
180 /* define of blending operation */
181 enum drm_exynos_ipp_blending {
189 /* [Sa + (1 - Sa)*Da, Rc = Sc + (1 - Sa)*Dc] */
190 IPP_BLENDING_SRC_OVER,
191 /* [Sa + (1 - Sa)*Da, Rc = Dc + (1 - Da)*Sc] */
192 IPP_BLENDING_DST_OVER,
193 /* [Sa * Da, Sc * Da] */
195 /* [Sa * Da, Sa * Dc] */
197 /* [Sa * (1 - Da), Sc * (1 - Da)] */
198 IPP_BLENDING_SRC_OUT,
199 /* [Da * (1 - Sa), Dc * (1 - Sa)] */
200 IPP_BLENDING_DST_OUT,
201 /* [Da, Sc * Da + (1 - Sa) * Dc] */
202 IPP_BLENDING_SRC_ATOP,
203 /* [Sa, Sc * (1 - Da) + Sa * Dc ] */
204 IPP_BLENDING_DST_ATOP,
205 /* [-(Sa * Da), Sc * (1 - Da) + (1 - Sa) * Dc] */
207 /* [Sa + Da - Sa*Da, Sc*(1 - Da) + Dc*(1 - Sa) + min(Sc, Dc)] */
209 /* [Sa + Da - Sa*Da, Sc*(1 - Da) + Dc*(1 - Sa) + max(Sc, Dc)] */
210 IPP_BLENDING_LIGHTEN,
211 /* [Sa * Da, Sc * Dc] */
212 IPP_BLENDING_MULTIPLY,
213 /* [Sa + Da - Sa * Da, Sc + Dc - Sc * Dc] */
215 /* Saturate(S + D) */
221 /* define of dithering operation */
222 enum drm_exynos_ipp_dithering {
232 * A structure for ipp supported property list.
234 * @version: version of this structure.
235 * @ipp_id: id of ipp driver.
236 * @count: count of ipp driver.
237 * @writeback: flag of writeback supporting.
238 * @flip: flag of flip supporting.
239 * @degree: flag of degree information.
240 * @csc: flag of csc supporting.
241 * @crop: flag of crop supporting.
242 * @scale: flag of scale supporting.
243 * @blending: flag of blending supporting.
244 * @dithering: flag of dithering supporting.
245 * @colorfill: flag of colorfill supporting.
246 * @refresh_min: min hz of refresh.
247 * @refresh_max: max hz of refresh.
248 * @crop_min: crop min resolution.
249 * @crop_max: crop max resolution.
250 * @scale_min: scale min resolution.
251 * @scale_max: scale max resolution.
253 struct drm_exynos_ipp_prop_list {
268 struct drm_exynos_sz crop_min;
269 struct drm_exynos_sz crop_max;
270 struct drm_exynos_sz scale_min;
271 struct drm_exynos_sz scale_max;
275 * A structure for ipp config.
277 * @ops_id: property of operation directions.
278 * @flip: property of mirror, flip.
279 * @degree: property of rotation degree.
280 * @fmt: property of image format.
281 * @sz: property of image size.
282 * @pos: property of image position(src-cropped,dst-scaler).
284 struct drm_exynos_ipp_config {
285 enum drm_exynos_ops_id ops_id;
286 enum drm_exynos_flip flip;
287 enum drm_exynos_degree degree;
289 struct drm_exynos_sz sz;
290 struct drm_exynos_pos pos;
293 /* definition of command */
294 enum drm_exynos_ipp_cmd {
302 /* define of color range */
303 enum drm_exynos_color_range {
304 COLOR_RANGE_LIMITED, /* Narrow: Y(16 to 235), Cb/Cr(16 to 240) */
305 COLOR_RANGE_FULL, /* Wide: Y/Cb/Cr(0 to 255), Wide default */
309 * A structure for ipp property.
311 * @config: source, destination config.
312 * @cmd: definition of command.
313 * @ipp_id: id of ipp driver.
314 * @prop_id: id of property.
315 * @refresh_rate: refresh rate.
316 * @range: dynamic range for csc.
317 * @blending: blending opeation config.
318 * @dithering: dithering opeation config.
319 * @color_fill: color fill value.
321 struct drm_exynos_ipp_property {
322 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
323 enum drm_exynos_ipp_cmd cmd;
333 /* definition of buffer */
334 enum drm_exynos_ipp_buf_type {
340 * A structure for ipp buffer operations.
342 * @ops_id: operation directions.
343 * @buf_type: definition of buffer.
344 * @prop_id: id of property.
345 * @buf_id: id of buffer.
346 * @handle: Y, Cb, Cr each planar handle.
347 * @user_data: user data.
349 struct drm_exynos_ipp_queue_buf {
350 enum drm_exynos_ops_id ops_id;
351 enum drm_exynos_ipp_buf_type buf_type;
354 __u32 handle[EXYNOS_DRM_PLANAR_MAX];
359 /* definition of control */
360 enum drm_exynos_ipp_ctrl {
369 * A structure for ipp start/stop operations.
371 * @prop_id: id of property.
372 * @ctrl: definition of control.
374 struct drm_exynos_ipp_cmd_ctrl {
376 enum drm_exynos_ipp_ctrl ctrl;
379 #define DRM_EXYNOS_GEM_CREATE 0x00
380 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
381 #define DRM_EXYNOS_GEM_GET 0x04
382 #define DRM_EXYNOS_VIDI_CONNECTION 0x07
385 #define DRM_EXYNOS_G2D_GET_VER 0x20
386 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
387 #define DRM_EXYNOS_G2D_EXEC 0x22
389 /* IPP - Image Post Processing */
390 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
391 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
392 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
393 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33
395 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
396 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
398 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
399 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
401 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
402 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
404 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
405 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
406 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
407 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
408 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
409 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
411 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
412 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
413 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
414 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
415 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
416 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
417 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
418 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
420 /* EXYNOS specific events */
421 #define DRM_EXYNOS_G2D_EVENT 0x80000000
422 #define DRM_EXYNOS_IPP_EVENT 0x80000001
424 struct drm_exynos_g2d_event {
425 struct drm_event base;
433 struct drm_exynos_ipp_event {
434 struct drm_event base;
440 __u32 buf_id[EXYNOS_DRM_OPS_MAX];