3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * The test exercises SDRAM accesses in burst mode
31 #include <asm/processor.h>
36 #include "test_burst.h"
38 /* 8 MB test region of physical RAM */
39 #define TEST_PADDR 0x00800000
40 /* The uncached virtual region */
41 #define TEST_VADDR_NC 0x00800000
42 /* The cached virtual region */
43 #define TEST_VADDR_C 0x01000000
44 /* When an error is detected, the address where the error has been found,
45 and also the current and the expected data will be written to
46 the following flash address
48 #define TEST_FLASH_ADDR 0x40100000
50 static void test_prepare (void);
51 static int test_burst_start (unsigned long size, unsigned long pattern);
52 static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached);
53 static int test_mmu_is_on(void);
54 static void test_desc(unsigned long size);
55 static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern);
56 static void signal_start(void);
57 static void signal_error(void);
58 static void test_usage(void);
60 static unsigned long test_pattern [] = {
68 int test_burst (int argc, char *argv[])
70 unsigned long size = CACHE_LINE_SIZE;
76 for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) {
80 if (size == 0 || *d) {
84 } else if (argc > 2) {
89 size += (CACHE_LINE_SIZE - 1);
90 size &= ~(CACHE_LINE_SIZE - 1);
92 if (!test_mmu_is_on()) {
98 for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]); i++) {
99 res = test_burst_start(size, test_pattern[i]);
108 static void test_prepare (void)
110 volatile immap_t *immr = (immap_t *) CFG_IMMR;
115 disable_interrupts();
118 printf ("Interrupts are disabled\n");
119 printf ("I-Cache is ON\n");
120 printf ("D-Cache is ON\n");
121 printf ("MMU is ON\n");
125 test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0);
126 test_map_8M (TEST_PADDR, TEST_VADDR_C, 1);
128 test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0);
130 /* Configure PD.8 and PD.9 as general purpose output */
131 immr->im_ioport.iop_pdpar &= ~0x00C0;
132 immr->im_ioport.iop_pddir |= 0x00C0;
135 static int test_burst_start (unsigned long size, unsigned long pattern)
137 volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C;
138 volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC;
142 printf ("Test pattern %08x ...", pattern);
146 for (i = 0; i < n; i ++) {
147 vaddr_c [i] = pattern;
150 flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1);
152 for (i = 0; i < n; i ++) {
153 register unsigned long tmp = vaddr_nc [i];
154 if (tmp != pattern) {
155 test_error("2a", vaddr_nc + i, tmp, pattern);
160 for (i = 0; i < n; i ++) {
161 register unsigned long tmp = vaddr_c [i];
162 if (tmp != pattern) {
163 test_error("2b", vaddr_c + i, tmp, pattern);
168 for (i = 0; i < n; i ++) {
169 vaddr_nc [i] = pattern;
172 for (i = 0; i < n; i ++) {
173 register unsigned long tmp = vaddr_nc [i];
174 if (tmp != pattern) {
175 test_error("3a", vaddr_nc + i, tmp, pattern);
181 for (i = 0; i < n; i ++) {
182 register unsigned long tmp = vaddr_c [i];
183 if (tmp != pattern) {
184 test_error("3b", vaddr_c + i, tmp, pattern);
191 printf(" %s\n", res == 0 ? "OK" : "");
196 static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached)
198 mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID);
199 mtspr (MD_TWC, MI_PS8MEG | MI_SVALID);
200 mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2));
201 mtspr (MD_AP, MI_Kp);
204 static int test_mmu_is_on(void)
208 asm volatile("mfmsr %0" : "=r" (msr) :);
213 static void test_desc(unsigned long size)
216 "The following tests will be conducted:\n"
217 "1) Map %d-byte region of physical RAM at 0x%08x\n"
218 " into two virtual regions:\n"
219 " one cached at 0x%08x and\n"
220 " the the other uncached at 0x%08x.\n",
221 size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C);
224 "2) Fill the cached region with a pattern, and flush the cache\n"
225 "2a) Check the uncached region to match the pattern\n"
226 "2b) Check the cached region to match the pattern\n"
227 "3) Fill the uncached region with a pattern\n"
228 "3a) Check the cached region to match the pattern\n"
229 "3b) Check the uncached region to match the pattern\n"
230 "2b) Change the patterns and go to step 2\n"
235 static void test_error(
236 char * step, volatile void * addr, unsigned long val, unsigned long pattern)
238 volatile unsigned long * p = (void *)TEST_FLASH_ADDR;
242 p[0] = (unsigned long)addr;
246 printf ("\nError at step %s, addr %08x: read %08x, pattern %08x",
247 step, addr, val, pattern);
250 static void signal_start(void)
252 volatile immap_t *immr = (immap_t *) CFG_IMMR;
254 if (immr->im_ioport.iop_pddat & 0x0080) {
255 immr->im_ioport.iop_pddat &= ~0x0080;
257 immr->im_ioport.iop_pddat |= 0x0080;
261 static void signal_error(void)
263 volatile immap_t *immr = (immap_t *) CFG_IMMR;
265 if (immr->im_ioport.iop_pddat & 0x0040) {
266 immr->im_ioport.iop_pddat &= ~0x0040;
268 immr->im_ioport.iop_pddat |= 0x0040;
272 static void test_usage(void)
274 printf("Usage: go 0x40004 [size]\n");