2 *-----------------------------------------------------------------------------
5 *-----------------------------------------------------------------------------
6 * Copyright (c) 2002-2010, Intel Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 *-----------------------------------------------------------------------------
28 * This is the register definition file for the Atom E6xx platform. This should
29 * contain device dependent register definitions. Standard register
30 * definitions (VGA, PCI, etc) should not be put in this file. For those
32 *-----------------------------------------------------------------------------
36 * Note: Use _REGS_H_ instead of _TNC_REGS_H_ to insure that no file can
37 * include 2 device dependent register files.
47 /*-----------------------------------------------------------------------------
48 * PCI Register Definitions
49 *---------------------------------------------------------------------------*/
50 #define TNC_PCI_MMADR PCI_BAR_0
51 #define TNC_PCI_IOBAR PCI_BAR_1
52 #define TNC_PCI_GMADR PCI_BAR_2
53 #define TNC_PCI_GTTADR PCI_BAR_3
57 * Device: 2 Offset:50h
58 * [22:20] Graphics mode select
61 #define TNC_PCI_GC 0x52
62 #define TNC_PCI_BSM 0x5C
64 /* Atom E6xx Device 31 GPIO base address offset */
65 #define TNC_PCI_GBA 0x44
67 #define TNC_D2_MMIO_SIZE (1024*1024)
68 #define TNC_D3_MMIO_SIZE (512*1024)
69 #define TNC_ST_SDVO_MMIO_SIZE (10*1024)
71 #define TNC_GTT_SIZE (128*1024)
75 /*-----------------------------------------------------------------------------
76 * General VGA Register Definitions
77 *---------------------------------------------------------------------------*/
78 #define FEATURE_CONT_REG 0x3DA /* Feature Control Register */
79 #define FEATURE_CONT_REG_MONO 0x3BA /* Feature Control Register (Mono) */
80 #define FEATURE_CONT_REG_READ 0x3CA /* Feature Control Register (Read) */
81 #define MSR_PORT 0x3C2 /* Miscellaneous Output Port */
82 #define MSR_PORT_LSB 0xC2 /* Miscellaneous Output Port LSB */
83 #define MSR_READ_PORT 0x3CC /* Miscellaneous Output Reg (Read) */
84 #define STATUS_REG_00 0x3C2 /* Input Status Register 0 */
85 #define STATUS_REG_01 0x3DA /* Input Status Register 1 */
86 #define STATUS_REG_01_MONO 0x3BA /* Input Status Register 1 (Mono) */
88 /* DAC Register Definitions. */
89 #define DAC_PEL_MASK 0x3C6 /* Color Palette Pixel Mask Register */
90 #define DAC_READ_INDEX 0x3C7 /* Color Palette Read-Mode Index Reg */
91 #define DAC_STATE 0x3C7 /* Color Palette State Register */
92 #define DAC_WRITE_INDEX 0x3C8 /* Color Palette Index Register */
93 #define DAC_DATA_REG 0x3C9 /* Color Palette Data Register */
96 /*-----------------------------------------------------------------------------
97 * Attribute Controller Register Definitions
98 *---------------------------------------------------------------------------*/
99 #define AR_PORT_LSB 0xC0 /*Attribute Controller Index Port LSB */
101 #define AR00 0x00 /* Color Data Register */
102 #define AR01 0x01 /* Color Data Register */
103 #define AR02 0x02 /* Color Data Register */
104 #define AR03 0x03 /* Color Data Register */
105 #define AR04 0x04 /* Color Data Register */
106 #define AR05 0x05 /* Color Data Register */
107 #define AR06 0x06 /* Color Data Register */
108 #define AR07 0x07 /* Color Data Register */
109 #define AR08 0x08 /* Color Data Register */
110 #define AR09 0x09 /* Color Data Register */
111 #define AR0A 0x0A /* Color Data Register */
112 #define AR0B 0x0B /* Color Data Register */
113 #define AR0C 0x0C /* Color Data Register */
114 #define AR0D 0x0D /* Color Data Register */
115 #define AR0E 0x0E /* Color Data Register */
116 #define AR0F 0x0F /* Color Data Register */
117 #define AR10 0x10 /* Mode Control Register */
118 #define AR11 0x11 /* Overscan Color Register */
119 #define AR12 0x12 /* Color Plane Enable Register */
120 #define AR13 0x13 /* Horizontal Pixel Panning Register */
121 #define AR14 0x14 /* Pixel Pad Register */
124 /*-----------------------------------------------------------------------------
125 * CRT Controller Register Definitions
126 *---------------------------------------------------------------------------*/
127 #define CR_PORT_LSB 0xD4 /* CRT Controller Index Port LSB */
128 #define CRT_3D4 0x3D4 /* Color CRTC Index Port */
129 #define CRT_3B4 0x3B4 /* Monochrome CRTC Index Port */
131 #define CR00 0x00 /* Horizontal Total Register */
132 #define CR01 0x01 /* Horizontal Display Enable End Reg */
133 #define CR02 0x02 /* Horizontal Blank Start Register */
134 #define CR03 0x03 /* Horizontal Blank End Register */
135 #define CR04 0x04 /* Horizontal Sync Start Register */
136 #define CR05 0x05 /* Horizontal Sync End Register */
137 #define CR06 0x06 /* Vertical Total Register */
138 #define CR07 0x07 /* Overflow Register */
139 #define CR08 0x08 /* Preset Row Scan Register */
140 #define CR09 0x09 /* Maximum Scan Line Register */
141 #define DOUBLE_SCANLINE BIT7 /* Double scan ( 1 = Enable ) */
142 #define LCOMP_BIT9 BIT6 /* Bit 9 of line compare register */
143 #define VBLANK_BIT9 BIT5 /* Bit 9 of vertical blank start */
144 #define CR0A 0x0A /* Cursor Start Scan Line Register */
145 #define CR0B 0x0B /* Cursor End Scan Line Register */
146 #define CR0C 0x0C /* Start Address High Register */
147 #define CR0D 0x0D /* Start Address Low Register */
148 #define CR0E 0x0E /* Cursor Location High Register */
149 #define CR0F 0x0F /* Cursor Location Low Register */
150 #define CR10 0x10 /* Vertical Sync Start Register */
151 #define CR11 0x11 /* Vertical Sync End Register */
152 #define CR12 0x12 /* Vertical Display Enable End Reg */
153 #define CR13 0x13 /* Offset Register */
154 #define CR14 0x14 /* Underline Row Register */
155 #define CR15 0x15 /* Vertical Blank Start Register */
156 #define CR16 0x16 /* Vertical Blank End Register */
157 #define CR17 0x17 /* CRT Mode Control Register */
158 #define CR18 0x18 /* Line Compare Register */
159 #define CR22 0x22 /* Memory Data Latches Register */
160 #define CR24 0x24 /* Attribute Controller Toggle Reg */
163 /*-----------------------------------------------------------------------------
164 * Graphics Controller Register Definitions
165 *---------------------------------------------------------------------------*/
166 #define GR_PORT_LSB 0xCE /* Graphics Controller Index Port LSB */
168 #define GR00 0x00 /* Set/Reset Register */
169 #define GR01 0x01 /* Enable Set/Reset Register */
170 #define GR02 0x02 /* Color Compare Register */
171 #define GR03 0x03 /* Data Rotate Register */
172 #define GR04 0x04 /* Read Map Select Register */
173 #define GR05 0x05 /* Graphics Mode Register */
174 #define GR06 0x06 /* Micsellaneous Register */
175 #define RANGE_MAP_MASK BIT3 + BIT2 /* Address range to map mask */
176 #define A0_BF_RANGE 000h /* Map to A0000h-BFFFFh range */
177 #define GRAF_MODE BIT0 /* 1 = Grahics mode, 0 = Text mode */
178 #define GR07 0x07 /* Color Don't Care Register */
179 #define GR08 0x08 /* Bit Mask Register */
180 #define GR10 0x10 /* Address Mapping */
181 #define PAGING_TARGET BIT2 + BIT1 /* 00 = Local/Stolen, 01 = Mem mapped regs */
182 #define PAGE_MODE BIT0 /* Page Map allow access to all FB mem */
183 #define GR11 0x11 /* Page Selector */
184 #define GR18 0x18 /* Software Flag */
187 /*-----------------------------------------------------------------------------
188 * Sequencer Register Definitions
189 *---------------------------------------------------------------------------*/
190 #define SR_PORT_DATA 0x3C5 /* Sequencer Data Port */
191 #define SR_PORT_LSB 0xC4 /* Sequencer Index Port LSB */
193 #define SR00 0x00 /* Reset Register */
194 #define SR01 0x01 /* Clocking Mode Register */
195 #define DOT_CLOCK_DIVIDE BIT3 /* Divide pixel clock by 2 */
196 #define SR02 0x02 /* Plane/Map Mask Register */
197 #define SR03 0x03 /* Character Font Register */
198 #define SR04 0x04 /* Memory Mode Register */
199 #define SR07 0x07 /* Horizontal Character Counter Reset */
201 /*-----------------------------------------------------------------------------
202 * Platform specific PCI Config Register
203 *---------------------------------------------------------------------------*/
204 #define TNC_OFFSET_VGA_MSAC 0x62
206 /* FIXME: Core Clock should be obtained from the Message Control Register*/
207 #define INTEL_OFFSET_VGA_CORECLK 0xF0
209 /* #define INTEL_OFFSET_BRIDGE_CAPREG 0xE0 Not needed for Atom E6xx */
211 #define PCI_GMS_MASK BIT6 + BIT5 + BIT4 /* GFX Mode Select Bits Mask */
212 #define PCI_LOCAL BIT4 /* Local memory enabled */
213 #define PCI_DVMT_512K BIT5 /* 512KB DVMT */
214 #define PCI_DVMT_1M BIT5 + BIT4 /* 1MB DVMT */
215 #define PCI_DVMT_8M BIT6 /* 8MB DVMT */
217 #define PCI_DRB_REG 0x60 /* DRAM row boundary Register */
218 #define PCI_DRC_REG 0x7C /* DRAM Controller Mode Register */
219 #define PCI_DT_MASK BIT0 + BIT1 /* Select SDRAM types.
220 * = 00: Single data rate SDRAM
221 * = 01: Dual data rate SDRAM
224 #define DT_SDR_SDRAM 00 /* Single data rate SDRAM */
225 #define DT_DDR_SDRAM 01 /* Dual data rate SDRAM */
227 #define PCI_ESMRAMC_REG 0x91 /* Extended System Management RAM Reg */
228 #define PCI_TSEG_SZ BIT1 /* TSEG size bit */
229 #define PCI_TSEG_512K 0 /* 512K TSEG */
230 #define PCI_TSEG_1M BIT1 /* 1MB TSEG */
232 #define PCI_GCLKIO_REG 0xC0 /* GMCH Clock and IO Control Register */
233 #define PCI_AGP_Bit BIT9 /* AGP/DVO Mux Select:
237 #define PCI_GMCHCFG_REG 0xC6 /* GMCH Configuration Register */
238 #define PCI_SMFREQ_MASK BIT10 + BIT11
239 /* System Mem Frequency Select
240 * = 00: Intel Reserved
241 * = 01: System Memory Frequency is 166Mhz (DDR333) - Intel Reserved
242 * = 10: System Memory Frequency is 133Mhz (SDR133, DDR266)
243 * = 11: System Memory Frequency is 100Mhz (DDR200)
245 #define SYS_MEM_FREQ_166 1 /* System Memory Frequency is 166Mhz */
246 #define SYS_MEM_FREQ_133 2 /* System Memory Frequency is 133Mhz */
247 #define SYS_MEM_FREQ_100 3 /* System Memory Frequency is 100Mhz */
248 #define PCI_SMFREQ_POS 10 /* System Memory Frequency position */
250 #define PCI_CONFIG_LMINT 0xE0
251 #define PREALLOCATED_SIZE (8 * 1024 * 1024)
254 /*-----------------------------------------------------------------------------
255 * General VGA Register Definitions
256 *---------------------------------------------------------------------------*/
257 #define FEATURE_CONT_REG 0x3DA /* Feature Control Register */
258 #define FEATURE_CONT_REG_MONO 0x3BA /* Feature Control Register (Mono) */
259 #define FEATURE_CONT_REG_READ 0x3CA /* Feature Control Register (Read) */
260 #define MSR_PORT 0x3C2 /* Miscellaneous Output Port */
261 #define MSR_PORT_LSB 0xC2 /* Miscellaneous Output Port LSB */
262 #define MSR_READ_PORT 0x3CC /* Miscellaneous Output Reg (Read) */
263 #define STATUS_REG_00 0x3C2 /* Input Status Register 0 */
264 #define STATUS_REG_01 0x3DA /* Input Status Register 1 */
265 #define STATUS_REG_01_MONO 0x3BA /* Input Status Register 1 (Mono) */
267 /* DAC Register Definitions. */
268 #define DAC_PEL_MASK 0x3C6 /* Color Palette Pixel Mask Register */
269 #define DAC_READ_INDEX 0x3C7 /* Color Palette Read-Mode Index Reg */
270 #define DAC_STATE 0x3C7 /* Color Palette State Register */
271 #define DAC_WRITE_INDEX 0x3C8 /* Color Palette Index Register */
272 #define DAC_DATA_REG 0x3C9 /* Color Palette Data Register */
275 /*-----------------------------------------------------------------------------
276 * Memory mapped I/O Registers Definitions
277 *---------------------------------------------------------------------------*/
279 /*-----------------------------------------------------------------------------
280 * Instruction and Interrupt Control Registers (01000h - 02FFFh)
281 *---------------------------------------------------------------------------*/
282 #define PGTBL_CTL 0x02020 /* Page Table Control Register */
283 #define HWS_PGA 0x02080 /* Hardware Status Page Address register */
284 #define HWSTAM 0x02098 /* Hardware Status Mask */
285 #define SCPD0 0x0209C /* Scratch Pad 0 (Debug) */
286 #define IER 0x020A0 /* Interrupt Enable */
287 #define IIR 0x020A4 /* Interrupt Identity */
288 #define IMR 0x020A8 /* Interrupt Mask */
289 #define ISR 0x020AC /* Interrupt Status */
290 #define EIR 0x020B0 /* Error Identity */
291 #define EMR 0x020B4 /* Error Mask */
292 #define ESR 0x020B8 /* Error Status */
293 #define FW_BLC_SELF 0x020E0 /* Display FIFO Watermark */
294 #define MI_ARB_STATE 0x020E4 /* Memory Interface Arbitration State */
295 #define G_DEBUG 0x020FC /* G-UNIT Debug enable register */
298 /*-----------------------------------------------------------------------------
299 * FENCE and Per Process GTT Control Registers (02000h - 031FFh)
300 * --------------------------------------------------------------------------*/
301 #define FENCE0 0x02000 /* Fence table registers */
302 #define FENCE1 0x02004
303 #define FENCE2 0x02008
304 #define FENCE3 0x0200C
305 #define FENCE4 0x02010
306 #define FENCE5 0x02014
307 #define FENCE6 0x02018
308 #define FENCE7 0x0201C
309 #define FENCE8 0x03000
310 #define FENCE9 0x03004
311 #define FENCE10 0x03008
312 #define FENCE11 0x0300C
313 #define FENCE12 0x03010
314 #define FENCE13 0x03014
315 #define FENCE14 0x03018
316 #define FENCE15 0x0301C
318 /*-----------------------------------------------------------------------------
319 * FIXME: For TNC, we were not able to find specs detailing the FENCE registers
320 * Use the GN4 FENCE Registers for the time being as a placeholder till we can
321 * nail down the FENCE registers
322 * --------------------------------------------------------------------------*/
323 /*-----------------------------------------------------------------------------
324 * FENCE and Per Process GTT Control Registers (03000h - 031FFh)
326 * The FENCE registers are now 64-bits but we can only read/write 32-bits
327 * at a time. As a result, each register has aliases for the whole 64-bits,
328 * the low DWORD, and the high DWORD.
330 * This is important for restoring the registers, since we must always write
331 * the high DWORD first.
332 * --------------------------------------------------------------------------*/
333 #define FENCE0 0x03000 /* Fence table registers */
334 #define FENCE0l 0x03000
335 #define FENCE0h 0x03004
336 #define FENCE1 0x03008
337 #define FENCE1l 0x03008
338 #define FENCE1h 0x0300C
339 #define FENCE2 0x03010
340 #define FENCE2l 0x03010
341 #define FENCE2h 0x03014
342 #define FENCE3 0x03018
343 #define FENCE3l 0x03018
344 #define FENCE3h 0x0301C
345 #define FENCE4 0x03020
346 #define FENCE4l 0x03020
347 #define FENCE4h 0x03024
348 #define FENCE5 0x03028
349 #define FENCE5l 0x03028
350 #define FENCE5h 0x0302C
351 #define FENCE6 0x03030
352 #define FENCE6l 0x03030
353 #define FENCE6h 0x03034
354 #define FENCE7 0x03038
355 #define FENCE7l 0x03038
356 #define FENCE7h 0x0303C
357 #define FENCE8 0x03040
358 #define FENCE8l 0x03040
359 #define FENCE8h 0x03044
360 #define FENCE9 0x03048
361 #define FENCE9l 0x03048
362 #define FENCE9h 0x0304C
363 #define FENCE10 0x03050
364 #define FENCE10l 0x03050
365 #define FENCE10h 0x03054
366 #define FENCE11 0x03058
367 #define FENCE11l 0x03058
368 #define FENCE11h 0x0305C
369 #define FENCE12 0x03060
370 #define FENCE12l 0x03060
371 #define FENCE12h 0x03064
372 #define FENCE13 0x03068
373 #define FENCE13l 0x03068
374 #define FENCE13h 0x0306C
375 #define FENCE14 0x03070
376 #define FENCE14l 0x03070
377 #define FENCE14h 0x03074
378 #define FENCE15 0x03078
379 #define FENCE15l 0x03078
380 #define FENCE15h 0x0307C
382 /*-----------------------------------------------------------------------------
383 * MISC I/0 Contol Register ( 05000h - 05FFFh )
384 *---------------------------------------------------------------------------*/
385 #define IO_OFF 0x05000 /* Register group offset */
387 #define IO00 0x05000 /* Hsync / Vsync control register */
388 #define GPIO0 0x05010 /* GPIO register 0 (DDC1) */
389 #define DDC1_SCL_PIN GPIO0_SCL_PIN /* DDC1 SCL GPIO pin # */
390 #define DDC1_SDA_PIN GPIO0_SDA_PIN /* DDC1 SDA CPIO pin # */
391 #define GPIO1 0x05014 /* GPIO register 1 (I2C) */
392 #define I2C_SCL_PIN GPIO1_SCL_PIN /* I2C SCL GPIO pin # */
393 #define I2C_SDA_PIN GPIO1_SDA_PIN /* I2C SDA CPIO pin # */
394 #define GPIO2 0x05018 /* GPIO register 2 (DDC2) */
395 #define DDC2_SCL_PIN GPIO2_SCL_PIN /* DDC2 SCL GPIO pin # */
396 #define DDC2_SDA_PIN GPIO2_SDA_PIN /* DDC2 SDA CPIO pin # */
397 #define GPIO3 0x0501C /* GPIO register 3 (AGP mux DVI DDC) */
398 #define GPIO4 0x05020 /* GPIO register 4 (AGP mux I2C) */
399 #define GPIO5 0x05024 /* GPIO register 5 (AGP mux DDC2/I2C) */
401 #define GPIOPIN0 GPIO0
402 #define GPIOPIN1 GPIO0+1
403 #define GPIOPIN2 GPIO1
404 #define GPIOPIN3 GPIO1+1
405 #define GPIOPIN4 GPIO2
406 #define GPIOPIN5 GPIO2+1
407 #define GPIOPIN6 GPIO3
408 #define GPIOPIN7 GPIO3+1
409 #define GPIOPIN8 GPIO4
410 #define GPIOPIN9 GPIO4+1
411 #define GPIOPIN10 GPIO5
412 #define GPIOPIN11 GPIO5+1
413 #define GPIOPINMAX 12
415 #define GMBUS0 0x5100 /* GMBUS clock/device select register */
416 #define GMBUS1 0x5104 /* GMBUS command/status register */
417 #define GMBUS2 0x5108 /* GMBUS status register */
418 #define GMBUS3 0x510c /* GMBUS data buffer register */
419 #define GMBUS4 0x5110 /* GMBUS REQUEST_INUSE register */
420 #define GMBUS5 0x5120 /* GMBUS 2-Byte Index register */
421 #define GMBUS6 0x5124 /* GMBUS Clock divider */
424 #define SW_CLR_INT BIT31
433 #define HW_WAIT BIT14
434 #define HW_TMOUT BIT13
437 #define HW_BUS_ERR BIT10
440 /*-----------------------------------------------------------------------------
441 * Clock Control and PM Register ( 06000h - 06FFFh )
442 *---------------------------------------------------------------------------*/
443 #define VGA0_DIVISOR 0x06000 /* VGA 0 Divisor */
444 #define VGA1_DIVISOR 0x06004 /* VGA 1 Divisor */
445 #define VGA_PD 0x06010 /* VGA Post Divisor Select */
446 #define DPLLAMD 0x0601C /* Display PLL A SDVO Multiplier/Divisor */
447 #define DPLLBMD 0x06020 /* Display PLL B SDVO Multiplier/Divisor */
449 /*-----------------------------------------------------------------------------
450 * DPLL A Control Register ( 0F000h - 0FFFFh )
451 *---------------------------------------------------------------------------*/
452 #define DPLLACNTR 0x0F014 /* Display PLL A Control */
453 #define FPA0 0x0F040 /* DPLL A Divisor 0 */
454 #define FPA1 0x0F044 /* DPLL A Divisor 1 */
455 #define DPLL_TEST 0x0F06C /* DPLLA Test Register */
457 /*-----------------------------------------------------------------------------
458 * DPLL B Control Register ( 06000h - 06FFFh )
459 *---------------------------------------------------------------------------*/
460 #define DPLLBCNTR 0x06018 /* Display PLL B Control */
461 #define FPB0 0x06048 /* DPLL B Divisor 0 */
462 #define FPB1 0x0604C /* DPLL B Divisor 1 */
463 #define TNC_DPLL_TEST 0x0606C /* DPLL A and DPLL B test register */
466 #define TVCLKINBC 0x4000
467 #define CLOCK_2X 0x40000000
469 #define P2D_CG_DIS 0x06200 /* Clock Gating Disable */
470 /* Not available in Atom E6xx */
471 /* #define P3D_CG_DIS 0x06204 */ /* Clock Gating Disable */
474 /*-----------------------------------------------------------------------------
475 * Display Palette Register Definitions (0A000h - 0AFFFh)
476 *---------------------------------------------------------------------------*/
477 #define DPALETTE_A 0x0A000 /* Display Pipe A Palette */
478 #define DPALETTE_B 0x0A800 /* Display Pipe B Palette */
481 /*-----------------------------------------------------------------------------
482 * Display Pipeline / Port Register Definitions (60000h - 6FFFFh)
483 *---------------------------------------------------------------------------*/
484 #define DP_OFFSET 0x60000 /* register group offset */
485 #define PIPEA_TIMINGS 0x60000
486 #define HTOTAL_A 0x60000 /* Pipe A Horizontal Total Register */
487 #define ACTIVE_DISPLAY 0x7FF /* bit [ 10:0 ] */
488 #define HBLANK_A 0x60004 /* Pipe A Horizontal Blank Register */
489 #define HSYNC_A 0x60008 /* Pipe A Horizontal Sync Register */
490 #define VTOTAL_A 0x6000C /* Pipe A Vertical Total Register */
491 #define VBLANK_A 0x60010 /* Pipe A Vertical Blank Register */
492 #define VSYNC_A 0x60014 /* Pipe A Vertical Sync Register */
493 #define PIPEASRC 0x6001C /* Pipe A Source Image Size Register */
494 #define BCLRPAT_A 0x60020 /* Pipe A Border Color Pattern Register */
495 #define CRCCTRLREDA 0x60050 /* Pipe A CRC Red Control Register */
496 #define CRCCTRLGREENA 0x60054 /* Pipe A CRC Green Control Register */
497 #define CRCCTRLBLUEA 0x60058 /* Pipe A CRC Blue Control Register */
498 #define CRCCTRLRESA 0x6005C /* Pipe A CRC Alpha Control Register */
500 /*-----------------------------------------------------------------------------
501 * Pipe B registers are shared between Device 2 and Device 3
502 * Atom E6xx silicon design specifies that both device 2 and device 3
503 * Pipe B registers need to be set sequencially. Device 2, followed by
505 *---------------------------------------------------------------------------*/
506 #define PIPEB_TIMINGS 0x61000
507 #define HTOTAL_B 0x61000 /* Pipe B Horizontal Total Register */
508 #define HBLANK_B 0x61004 /* Pipe B Horizontal Blank Register */
509 #define HSYNC_B 0x61008 /* Pipe B Horizontal Sync Register */
510 #define VTOTAL_B 0x6100C /* Pipe B Vertical Total Register */
511 #define VBLANK_B 0x61010 /* Pipe B Vertical Blank Register */
512 #define VSYNC_B 0x61014 /* Pipe B Vertical Sync Register */
513 #define PIPEBSRC 0x6101C /* Pipe B Source Image Size Register */
514 #define BCLRPAT_B 0x61020 /* Pipe B Border Color Pattern Register */
515 #define VSYNCSHIFT_B 0x61028 /* Pipe B Vertical Sync Shift Register */
516 #define CRCCTRLREDB 0x61050 /* Pipe B CRC Red Control Register */
517 #define CRCCTRLGREENB 0x61054 /* Pipe B CRC Green Control Register */
518 #define CRCCTRLBLUEB 0x61058 /* Pipe B CRC Blue Control Register */
519 #define CRCCTRLRESB 0x6105C /* Pipe B CRC Alpha Control Register */
521 /* These registers are in Device 3 */
522 #define PORT_HPLUG_EN 0x61110 /* Port Hot Plug Enable */
523 #define PORT_HPLUG_STAT 0x61114 /* Port Hot Plug Status */
524 #define SDVOBCNTR 0x61140 /* Digital Display Port B Control */
525 #define LVDSCNTR 0x61180 /* Digital Display Port Control */
526 #define SDVO_BUFF_CTRL_REG 0x61170 /* SDVO Buffer Control */
528 /* Panel Power Sequencing */
529 #define LVDS_PNL_PWR_STS 0x61200 /* LVDS Panel Power Status Register */
530 #define LVDS_PNL_PWR_CTL 0x61204 /* LVDS Panel Power Control Register */
531 #define PP_ON_DELAYS 0x61208 /* Panel Power On Sequencing Delays */
532 #define PP_OFF_DELAYS 0x6120C /* Panel Power Off Sequencing Delays */
533 #define PP_DIVISOR 0x61210 /* Panel Power Cycle Delay and Reference */
536 #define PFIT_CONTROL 0x61230 /* Panel Fitting Control */
537 #define PFIT_PGM_RATIOS 0x61234 /* Programmed Panel Fitting Ratios */
539 /* Backlight control */
540 #define BLC_PWM_CTL2 0x61250 /* Backlight PWM Control 2 */
541 #define BLC_PWM_CTL 0x61254 /* Backlight PWM Control */
542 #define BLM_HIST_CTL 0x61260 /* Image BLM Histogram Control */
544 #define PORT_EN BIT31
545 #define PORT_PIPE_SEL BIT30
546 #define PORT_PIPE_SEL_POS 30
547 #define PORT_PIPE_A 0 /* 0 = Pipe A */
548 #define PORT_PIPE_B BIT30 /* 1 = Pipe B */
549 #define STALL_MASK BIT29 + BIT28
550 #define STALL_ENABLE BIT28
551 #define SYNC_MASK BIT15 + BIT11 + BIT10 + BIT4 + BIT3
552 #define SYNC_POLARITY BIT15 /* 1 = Use VGA register */
553 #define VSYNC_OUTPUT BIT11
554 #define HSYNC_OUTPUT BIT10
555 #define VSYNC_POLARITY BIT4
556 #define HSYNC_POLARITY BIT3
557 #define FP_DATA_ORDER BIT14
558 #define SUBDATA_ORDER BIT6
559 #define BORDER_EN BIT7
560 #define DISPLAY_EN BIT2
561 #define INTERLACED_BIT 0x00100000
562 #define RGBA_BITS 0x00030000
566 /*-----------------------------------------------------------------------------
567 * Display Pipeline A Register ( 70000h - 70024h )
568 *---------------------------------------------------------------------------*/
569 #define PIPEA_SCANLINE_COUNT 0x70000 /* Pipe A Scan Line Count (RO) */
570 #define PIPEA_SCANLINE_COMPARE 0x70004 /* Pipe A SLC Range Compare (RO) */
571 #define PIPEA_CONF 0x70008 /* Pipe A Configuration */
572 #define PIPE_STATUS_OFFSET 0x1C
573 #define PIPEAGCMAXRED 0x70010 /* Pipe A Gamma Correct. Max Red */
574 #define PIPEAGCMAXGRN 0x70014 /* Pipe A Gamma Correct. Max Green */
575 #define PIPEAGCMAXBLU 0x70018 /* Pipe A Gamma Correct. Max Blue */
576 #define PIPEA_STAT 0x70024 /* Pipe A Display Status */
577 #define PIPEA_DISP_ARB_CTRL 0x70030 /* Display Arbitration Control */
581 #define PIPEA_FRAME_HIGH 0x70040 /* Pipe A Frame Count High */
582 #define PIPEA_FRAME_PIXEL 0x70044 /* Pipe A Frame Cnt Low & pixel count */
587 #define PIPE_PIXEL_MASK 0x00ffffff
588 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
589 #define PIPE_FRAME_LOW_MASK 0xff000000
590 #define PIPE_FRAME_LOW_SHIFT 24
593 /*-----------------------------------------------------------------------------
594 * Display Pipeline B Register ( 71000h - 71024h )
595 *---------------------------------------------------------------------------*/
596 #define PIPEB_SCANLINE_COUNT 0x71000 /* Pipe B Disp Scan Line Count Reg */
597 #define PIPEB_SCANLINE_COMPARE 0x71004 /* Pipe B Disp Scan Line Cnt Range Cmp */
598 #define PIPEB_CONF 0x71008 /* Pipe B Pixel Pipeline Config Reg */
599 #define PIPEBGCMAXRED 0x71010 /* Pipe B Gamma Correct. Max Red */
600 #define PIPEBGCMAXGRN 0x71014 /* Pipe B Gamma Correct. Max Green */
601 #define PIPEBGCMAXBLU 0x71018 /* Pipe B Gamma Correct. Max Blue */
602 #define PIPEB_STAT 0x71024 /* Display Status Select Register */
603 #define PROG_STALL 0x6102C /* Programmable cDVO Stall Register */
604 #define PIPEB_FRAME_HIGH 0x71040 /* Pipe B Frame Count High */
605 #define PIPEB_FRAME_PIXEL 0x71044 /* Pipe B Frame Cnt Low and pixel cnt */
608 #define VBLANK_EVN_STS_EN BIT20
609 #define VBLANK_ODD_STS_EN BIT21
610 #define VBLANK_EVN_STS BIT4
611 #define VBLANK_ODD_STS BIT5
614 /* following bit flag defs can be re-used for Pipe-B */
615 #define PIPE_ENABLE BIT31
616 #define PIPE_LOCK BIT29
617 #define GAMMA_MODE BIT24
618 #define HOT_PLUG_EN BIT26
619 /* Setting this bit to a 1 in the PIPE{A|B}_STAT register, enables the
620 * consideration of vertical sync interrupts.
622 #define VSYNC_STS_EN BIT25
623 #define INTERLACE_EN BIT23|BIT22
624 /* Setting this bit to a 1 in the PIPE{A|B}_STAT register, enables the
625 * consideration of vertical blank interrupts.
627 #define VBLANK_STS_EN BIT17
628 #define HOT_PLUG_STS BIT10
629 #define VSYNC_STS BIT9
630 #define VBLANK_STS BIT1
631 /* The following are "sticky" status bits in the PIPE{A|B}_STAT register. They
632 * are cleared by writing a 1 to them. Theres is code that reads a
633 * PIPE{A|B}_STAT register into a variable, then modifies the variable, and
634 * writes it back to the register. These bits should be treated specially, so
635 * as not to inadvertantly clear the status bits, so that other code looking
636 * for those bits to be set won't miss it.
638 #define PIPESTAT_STS_BITS ((unsigned long) BIT31 | BIT13 | BIT12 | BIT11 | \
639 VSYNC_STS | BIT8 | BIT5 | BIT4 | VBLANK_STS | BIT0)
641 /*-----------------------------------------------------------------------------
643 * --------------------------------------------------------------------------*/
644 #define CDVO_CTRL 0x07000 /* cDVO Control Register */
645 #define CDVO_SLEW_RATE 0x07004 /* cDVO Slew Rate Register */
646 #define CDVO_STRENGTH 0x07008 /* cDVO Strength Register */
647 #define CDVO_RCOMP_UPDATE 0x0700C /* cDVO RCOMP update Register */
649 /*-----------------------------------------------------------------------------
650 * TNC_SDVOFAM Registers
651 * --------------------------------------------------------------------------*/
652 #define DPLL_ANACORE_CTRL 0x06300
653 #define DPLL_MISC 0x06304
654 #define DPLL_MONITOR 0x06308
655 #define DPLL_MONITOR2 0x0630C
656 #define DPLL_TEST_COMPARATOR 0x06310
657 #define SDVOB_TX_LSKEW 0x06314
659 /*-----------------------------------------------------------------------------
660 * Hardware Cursor Register Definitions (70080h - 7009Ch)
661 *---------------------------------------------------------------------------*/
662 #define CUR_A_CNTR 0x70080 /*Cursor A Control */
663 #define CUR_B_CNTR 0x700C0
664 #define CUR_BASE_OFFSET 0x4
665 #define CUR_POS_OFFSET 0x8
666 #define CUR_PAL0_OFFSET 0x10
667 #define CUR_PAL1_OFFSET 0x14
668 #define CUR_PAL2_OFFSET 0x18
669 #define CUR_PAL3_OFFSET 0x1C
671 /* Define these for ease of reference */
672 #define CURSOR_A_BASE CUR_A_CNTR + CUR_BASE_OFFSET
673 #define CURSOR_A_POS CUR_A_CNTR + CUR_POS_OFFSET
674 #define CURSOR_A_PAL0 CUR_A_CNTR + CUR_PAL0_OFFSET
675 #define CURSOR_A_PAL1 CUR_A_CNTR + CUR_PAL1_OFFSET
676 #define CURSOR_A_PAL2 CUR_A_CNTR + CUR_PAL2_OFFSET
677 #define CURSOR_A_PAL3 CUR_A_CNTR + CUR_PAL3_OFFSET
678 #define CURSOR_B_BASE CUR_B_CNTR + CUR_BASE_OFFSET
679 #define CURSOR_B_POS CUR_B_CNTR + CUR_POS_OFFSET
680 #define CURSOR_B_PAL0 CUR_B_CNTR + CUR_PAL0_OFFSET
681 #define CURSOR_B_PAL1 CUR_B_CNTR + CUR_PAL1_OFFSET
682 #define CURSOR_B_PAL2 CUR_B_CNTR + CUR_PAL2_OFFSET
683 #define CURSOR_B_PAL3 CUR_B_CNTR + CUR_PAL3_OFFSET
685 /*-----------------------------------------------------------------------------
686 * Display Plane A Register Definitions (70180h - 70188h)
687 *---------------------------------------------------------------------------*/
688 #define DSPAAFLIP 0x7017C
689 #define DSPACNTR 0x70180 /* Display Plane A */
690 #define DSPALINOFF 0x70184 /* Display A Linear Offset */
691 #define DSPASTRIDE 0x70188 /* Display A Stride */
692 #define DSPAKEYVAL 0x70194 /* Sprite color key value */
693 #define DSPAKEYMASK 0x70198 /* Sprite color key mask */
694 #define DSPASURF 0x7019C /* Display A Suface base address */
695 #define DSPATILEOFF 0x701A4 /* Display A Tiled Offset */
697 /*-----------------------------------------------------------------------------
698 * Display Plane B Register Definitions (71180h - 71188h)
699 *---------------------------------------------------------------------------*/
700 #define DSPBFLIP 0x7117C /* Display B Async flip */
701 #define DSPBCNTR 0x71180 /* Display Plane B */
702 #define DSPBLINOFF 0x71184 /* Display B Linear Offset */
703 #define DSPBSTRIDE 0x71188 /* Display B Stride */
704 #define DSPBKEYVAL 0x71194 /* Sprite color key value */
705 #define DSPBKEYMASK 0x71198 /* Sprite color key mask */
706 #define DSPBSURF 0x7119C /* Display B Suface base address */
707 #define DSPBTILEOFF 0x711A4 /* Display B Tiled Offset */
709 /*-----------------------------------------------------------------------------
710 * Source Format Definition for DSPxCNTR
711 *---------------------------------------------------------------------------*/
712 #define DSPxCNTR_ARGB_8888 0x1C000000
713 #define DSPxCNTR_RGB_8888 0x18000000
714 #define DSPxCNTR_RGB_565 0x14000000
715 #define DSPxCNTR_RGB_555 0x10000000
716 #define DSPxCNTR_RGB_8 0x08000000
717 #define DSPxCNTR_SRC_FMT_MASK 0x3C000000 /*mask for above*/
719 /*-----------------------------------------------------------------------------
720 * Display Plane C Register Definitions (72180h - 72188h)
721 *---------------------------------------------------------------------------*/
722 #define DSPCCNTR 0x72180 /* Display Plane C */
723 #define DSPCLINOFF 0x72184 /* Display C Linear Offset */
724 #define DSPCSTRIDE 0x72188 /* Display C Stride */
725 #define DSPCPOS 0x7218C /* Display C Position */
726 #define DSPCSIZE 0x72190 /* Display C Size */
727 #define DSPCKEYMINVAL 0x72194 /* Sprite color key Min */
728 #define DSPCKEYMASK 0x72198 /* Sprite color key mask */
729 #define DSPCSURF 0x7219C /* Display C Suface base address */
730 #define DSPCKEYMAXVAL 0x721A0 /* Display C Sprint color key Max */
731 #define DSPCTILEOFF 0x721A4 /* Display C Tiled Offset */
732 #define DSPCCONTALPHA 0x721A8 /* Display C Constant Alpha */
734 #define DCLRC0 0x721D0 /* Display C Color Correction 0 */
735 #define DCLRC1 0x721D4 /* Display C Color Correction 1 */
736 #define DPYC_GAMC5 0x721E0 /* Display C Gamma Correction 5 */
737 #define DPYC_GAMC4 0x721E4 /* Display C Gamma Correction 4 */
738 #define DPYC_GAMC3 0x721E8 /* Display C Gamma Correction 3 */
739 #define DPYC_GAMC2 0x721EC /* Display C Gamma Correction 2 */
740 #define DPYC_GAMC1 0x721F0 /* Display C Gamma Correction 1 */
741 #define DPYC_GAMC0 0x721F4 /* Display C Gamma Correction 0 */
743 #define PLANE_ENABLE BIT31
744 #define GAMMA_ENABLE BIT30
745 #define BPP_MASK BIT29 + BIT28 + BIT27 + BIT26
747 #define STEREO_ENABLE BIT25
748 #define PIPE_SEL BIT24
749 #define PIPE_SEL_POS 24
750 #define PIXEL_MULTIPLY BIT21 + BIT20
751 #define STEREO_POLARITY BIT18
753 /* Common offsets for all Display Pipeline registers */
754 #define DSP_LINEAR_OFFSET 0x04 /* Offset from the control reg */
755 #define DSP_STRIDE_OFFSET 0x08 /* Offset from the control reg */
756 #define DSP_SIZE_OFFSET 0x10 /* Offset from the control reg */
757 #define DSP_START_OFFSET 0x1c /* Offset from the control reg */
758 #define DSP_TOFF_OFFSET 0x24 /* Offset from the control reg */
760 /*-----------------------------------------------------------------------------
761 * VGA Display Plane Control Register Definitions (71400h)
762 *---------------------------------------------------------------------------*/
764 #define VGACNTRL 0x71400 /* VGA Display Plane Control Register */
765 #define VGA_DOUBLE BIT30
766 #define VGA_PIPE BIT29
767 #define VGA_CENTER_MASK BIT25 + BIT24
768 #define VGA_CENTER_1 BIT25
769 #define VGA_CENTER_0 BIT24
770 #define VGA_PAL_READ BIT23
771 #define VGA_PAL_MASK BIT22 + BIT21
772 #define VGA_PALA_DISABLE BIT22
773 #define VGA_PALB_DISABLE BIT21
774 #define DAC_8_BIT BIT20
775 #define VGA_8_DOT BIT18
777 #define ADD_ID 0x71408 /* ADD Card ID Register*/
779 /*-----------------------------------------------------------------------------
780 * Overlay Plane Control Register Definitions (30000h)
781 *---------------------------------------------------------------------------*/
782 #define OVADD 0x30000 /* Overlay Control */
784 /*-----------------------------------------------------------------------------
785 * VBIOS Software flags 00h - 0Fh
786 *---------------------------------------------------------------------------*/
787 #define DSP_CHICKENBITS 0x70400 /* Chicken Bit */
788 #define SWFABASE 0x70410 /* Software flags A Base Addr */
789 #define SWF00 0x70410
790 #define SWF01 0x70414
791 #define SWF02 0x70418
792 #define SWF03 0x7041C
793 #define SWF04 0x70420
794 #define SWF05 0x70424
795 #define SWF06 0x70428
796 #define SWF07 0x7042C
797 #define SWF08 0x70430
798 #define SWF09 0x70434
799 #define SWF0A 0x70438
800 #define SWF0B 0x7043C
801 #define SWF0C 0x70440
802 #define SWF0D 0x70444
803 #define SWF0E 0x70448
804 #define SWF0F 0x7044C
806 /*-----------------------------------------------------------------------------
807 * VBIOS Software flags 10h - 1Fh
808 *---------------------------------------------------------------------------*/
809 #define SWFBBASE 0x71410 /* Software flags B Base Addr */
810 #define SWF10 0x71410
811 #define SWF11 0x71414
812 #define SWF12 0x71418
813 #define SWF13 0x7141C
814 #define SWF14 0x71420
815 #define SWF15 0x71424
816 #define SWF16 0x71428
817 #define SWF17 0x7142C
818 #define SWF18 0x71430
819 #define SWF19 0x71434
820 #define SWF1A 0x71438
821 #define SWF1B 0x7143C
822 #define SWF1C 0x71440
823 #define SWF1D 0x71444
824 #define SWF1E 0x71448
825 #define SWF1F 0x7144C
827 #define SWF30 0x72414
828 #define SWF31 0x72418
829 #define SWF32 0x7241C
831 /*-----------------------------------------------------------------------------
832 * Software Flag Registers (71410h - 71428h)
833 *---------------------------------------------------------------------------*/
834 /* Map old software flag names to their new Gen4 names */
843 /*-----------------------------------------------------------------------------
844 * GPIO Control Registers(05000h - 05023h)
845 *---------------------------------------------------------------------------*/
846 /* GPIO registers 0x0500 - 0x500C is reserved */
847 #define GPIOCTL_1 0x05014
848 #define GPIOCTL_2 0x05018
849 #define GPIOCTL_4 0x05020
851 /*-----------------------------------------------------------------------------
852 * Scratch register to be used as additional parameter in SMI
853 *---------------------------------------------------------------------------*/
854 #define SCRATCH_SWF6 0x71428
856 /*-----------------------------------------------------------------------------
857 * Miscellaneous registers
858 ----------------------------------------------------------------------------*/
859 #define HW_ST_PAGE_ADDR 0x02080
861 /*-----------------------------------------------------------------------------
862 * GMBUS : I2C Bus Types
863 ----------------------------------------------------------------------------*/
864 //#define GMBUS_ANALOG_DDC 1
866 //#define GMBUS_INT_LVDS_DDC 2
867 #define I2C_INT_LVDS_DDC 2
869 #define GMBUS_DVO_REG 3
871 #define GMBUS_DVOB_DDC 4
872 //#define GMBUS_DVOC_DDC 5
874 /*-----------------------------------------------------------------------------
875 * LPC Register Offsets. Used for LVDS GPIO Bit Bashing. Registers are part
877 ----------------------------------------------------------------------------*/
888 #endif /* _REGS_H_ */
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