2 *-----------------------------------------------------------------------------
5 *-----------------------------------------------------------------------------
6 * Copyright (c) 2002-2010, Intel Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 *-----------------------------------------------------------------------------
28 * These are the defines specific to the SGX engine code.
29 *-----------------------------------------------------------------------------
35 /* ---------------------------------------------------------*/
37 /* ---------------------------------------------------------*/
47 /* ---------------------------------------------------------*/
49 /* ---------------------------------------------------------*/
50 /* PSB SGX Memory buffer types */
51 /* FIXME! - rename 'DRM' prefix to 'SGX'
52 * if we start using this */
53 #define DRM_BO_MEM_LOCAL 0
54 #define DRM_BO_MEM_TT 1
55 #define DRM_BO_MEM_VRAM 2
56 #define DRM_BO_MEM_PRIV0 3
57 #define DRM_BO_MEM_PRIV1 4
58 #define DRM_BO_MEM_PRIV2 5
59 #define DRM_BO_MEM_PRIV3 6
60 #define DRM_BO_MEM_PRIV4 7
61 #define DRM_BO_MEM_TYPES 8
63 #define DRM_BO_LOCK_UNLOCK_BM (1 << 0)
64 #define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1)
66 /* GMM APERTURE FUNCTIONAL SEGMENTATION
67 * - BEWARE!!!! we are not using this kind
68 * of pre-allocated slots in IEGD arch
69 * so this should remain commented!!??
71 #define PSB_VDC_OFFSET 0x00000000
72 #define PSB_VDC_SIZE 0x000080000
73 #define PSB_SGX_SIZE 0x8000
74 #define PSB_SGX_OFFSET 0x00040000
75 #define PSB_MMIO_RESOURCE 0
76 #define PSB_GATT_RESOURCE 2
77 #define PSB_GTT_RESOURCE 3
78 #define PSB_GMCH_CTRL 0x52
80 #define _PSB_GMCH_ENABLED 0x4
81 #define PSB_PGETBL_CTL 0x2020
82 #define _PSB_PGETBL_ENABLED 0x00000001
83 #define PSB_SGX_2D_SLAVE_PORT 0x4000
84 #define PSB_TT_PRIV0_LIMIT (256*1024*1024)
85 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
86 #define PSB_NUM_VALIDATE_BUFFERS 512
87 #define PSB_MEM_KERNEL_START 0x10000000
88 #define PSB_MEM_PDS_START 0x20000000
89 #define PSB_MEM_RASTGEOM_START 0x30000000
90 #define PSB_MEM_MMU_START 0x40000000
93 #define XPSB_LOCAL_SIZE 4096
94 #define XPSB_SPROG_SIZE 1024
95 #define XPSB_GEOM_SIZE 8192
97 #define PSB_HW_COOKIE_SIZE 16
98 #define PSB_HW_FEEDBACK_SIZE 8
100 #define PAGE_SHIFT 12
101 #define PSB_DPM_BUFFER_PAGES ((10*1024*1024) >> PAGE_SHIFT)
102 #define PSB_DPM_TABLE_SIZE 0x40000
103 #define PSB_PARAM_PAGE_SHIFT PAGE_SHIFT
104 #define PSB_PARAM_PAGE_SIZE PAGE_SIZE
105 #define PSB_MIN_NONGLOBAL_PAGES 1024
106 #define PSB_PLM(_val, _base) \
107 (((_val) << (_base ## _SHIFT)) & (_base ## _MASK))
110 * Number of registers in a PDS attribute chunk.
112 #define PSB_PDS_CHUNK_SIZE (32)
113 #define PSB_PDS_CHUNK_SIZE_SHIFT (5)
116 * Number of registers reserved for output registers.
118 #define PSB_USE_NUM_OUTPUT_REGISTERS (384)
121 * Total number of USE registers.
124 #define PSB_USE_NUM_UNIFIED_REGISTERS (2048)
129 #define PSB_USE_DEFAULT_TEMP_REG_COUNT (384)
130 #define PSB_USE_DEFAULT_TEMP_GRAN (4)
131 #define PSB_USE_DEFAULT_TEMP_REG_INIT (24)
132 #define PSB_USE_DEFAULT_ATTRIB_REG_COUNT (2048 - 384 * 2) /* 1280 */
135 /* ---------------------------------------------------------*/
137 /* ---------------------------------------------------------*/
138 struct drm_psb_xhw_arg {
141 unsigned long irq_op;
142 unsigned long issue_irq;
143 unsigned long cookie[PSB_HW_COOKIE_SIZE];
149 unsigned long clear_p_start;
150 unsigned long clear_num_pages;
153 unsigned long fire_flags;
154 unsigned long hw_context;
155 unsigned long offset;
156 unsigned long engine;
158 unsigned long feedback[PSB_HW_FEEDBACK_SIZE];
173 int fix_hw_brn_20267;
174 int fix_hw_brn_20696;
175 int fix_hw_brn_20852;
176 int fix_hw_brn_21024;
177 int fix_hw_brn_21049;
178 int fix_hw_brn_21117;
179 int fix_hw_brn_21158;
180 int fix_hw_brn_21183;
181 int fix_hw_brn_21226;
182 int fix_hw_brn_21227;
183 int fix_hw_brn_21301;
184 int fix_hw_brn_21329;
185 int fix_hw_brn_21351;
186 int fix_hw_brn_21369;
187 int fix_hw_brn_21387;
188 int fix_hw_brn_21246;
189 int fix_hw_brn_21500;
190 int fix_hw_brn_21551;
191 int fix_hw_brn_21592;
192 int fix_hw_brn_21652;
193 int fix_hw_brn_21788;
194 int fix_hw_brn_21826;
195 int fix_hw_brn_21878;
196 int fix_hw_brn_21893;
197 int fix_hw_brn_21934;
198 int fix_hw_brn_21986;
199 int fix_hw_brn_22048;
200 int fix_hw_brn_22107;
201 int fix_hw_brn_22111;
202 int fix_hw_brn_22136;
203 int fix_hw_brn_22162;
204 int fix_hw_brn_22329;
205 int fix_hw_brn_22336;
206 int fix_hw_brn_22364;
207 int fix_hw_brn_22117;
208 int fix_hw_brn_22380;
209 int fix_hw_brn_22391;
210 int fix_hw_brn_22393;
211 int fix_hw_brn_22462;
212 int fix_hw_brn_22563;
213 int fix_hw_brn_22666;
214 int fix_hw_brn_23281;