2 *-----------------------------------------------------------------------------
5 *-----------------------------------------------------------------------------
6 * Copyright (c) 2002-2010, Intel Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 *-----------------------------------------------------------------------------
28 * Contains PCI bus transaction definitions
29 *-----------------------------------------------------------------------------
33 #define PCI_VENDOR_ID_INTEL 0x8086
34 #ifndef PCI_VENDOR_ID_STMICRO
35 #define PCI_VENDOR_ID_STMICRO 0x104A
38 /* PLB Family Chips */
39 #define PCI_DEVICE_ID_BRIDGE_PLB 0x8100
40 #define PCI_DEVICE_ID_VGA_PLB 0x8108
43 #define PCI_DEVICE_ID_BRIDGE_TNC 0x4114
44 #define PCI_DEVICE_ID_VGA_TNC 0x4108
47 #define PCI_DEVICE_ID_BRIDGE_TNC_ULP 0x4115
49 /* Atom E6xx Device 3 */
50 #define PCI_DEVICE_ID_SDVO_TNC 0x8182
52 /* Atom E6xx Device 31 (LPC) */
53 #define PCI_DEVICE_ID_LPC_TNC 0x8186
55 /* Atom E6xx ST Micro SDVO PCI device */
56 #define PCI_DEVICE_ID_SDVO_TNC_ST 0xcc13
58 /* Atom E6xx ST Micro GPIO SDVO PCI device */
59 #define PCI_DEVICE_ID_SDVO_TNC_ST_GPIO 0xcc0c
61 /* Support for MSRT and Pre-Release PCI ID for Atom E6xx
62 * Can be removed in future */
64 /* Atom E6xx A0 Stepping */
65 #define PCI_DEVICE_ID_BRIDGE_TNC_A0 0x4110
66 #define PCI_DEVICE_ID_VGA_TNC_A0 0x4100
69 #define PCI_DEVICE_ID_BRIDGE_LNC 0x4110
70 #define PCI_DEVICE_ID_VGA_LNC 0x4102
73 /* Start: Southbridge specific */
74 #define PCI_DEVICE_ID_LPC_82801AA 0x2410
75 #define PCI_DEVICE_ID_LPC_82801AB 0x2420
76 #define PCI_DEVICE_ID_LPC_82801BA 0x2440
77 #define PCI_DEVICE_ID_LPC_82801BAM 0x244c
78 #define PCI_DEVICE_ID_LPC_82801E 0x2450
79 #define PCI_DEVICE_ID_LPC_82801CA 0x2480
80 #define PCI_DEVICE_ID_LPC_82801DB 0x24c0
81 #define PCI_DEVICE_ID_LPC_82801DBM 0x24cc
82 #define PCI_DEVICE_ID_LPC_82801EB 0x24d0
83 #define PCI_DEVICE_ID_LPC_82801EBM 0x24dc
84 #define PCI_DEVICE_ID_LPC_80001ESB 0x25a1 /* LPC on HanceRapids ICH */
85 #define PCI_DEVICE_ID_LPC_82801FB 0x2640 /* ICH6/ICH6R */
86 #define PCI_DEVICE_ID_LPC_82801FBM 0x2641 /* ICH6M/ICH6MR */
87 #define PCI_DEVICE_ID_LPC_82801FW 0x2642 /* ICH6W/ICH6WR */
88 #define PCI_DEVICE_ID_LPC_82801FWM 0x2643 /* ICH6MW/ICH6MWR */
89 #define PCI_DEVICE_ID_LPC_Q35DES 0x2910 /* ICH9 */
90 #define PCI_DEVICE_ID_LPC_Q35DHES 0x2912 /* ICH9 */
91 #define PCI_DEVICE_ID_LPC_Q35DOES 0x2914 /* ICH9 */
92 #define PCI_DEVICE_ID_LPC_Q35RES 0x2916 /* ICH9 */
93 #define PCI_DEVICE_ID_LPC_Q35BES 0x2918 /* ICH9 */
97 #define INTEL_PTE_ALLIGNMENT 0xFFFFF000