1 /*********************************************************************
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2 ** File Name: sdio_phy.h
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3 ** Author: yanping.xie
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5 ** Copyright: 2004 Spreadtrum, Incoporated. All Rights Reserved.
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6 ** Description: This file describe operation of sdio host.
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7 *********************************************************************
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9 *********************************************************************
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11 ** ------------------------------------------------------------------------- **
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12 ** DATE NAME DESCRIPTION
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13 ** 09/09/2013 ypxie Create.
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14 ********************************************************************/
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15 #ifndef __SDIO_CHIP_H_
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16 #define __SDIO_CHIP_H_
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18 /* sdio register base address */
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19 #define SLOT0_BASE_ADDR CTL_BASE_SDIO0
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20 #define SLOT1_BASE_ADDR (CTL_BASE_SDIO0 + 0x0100)
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21 #define SLOT2_BASE_ADDR 0 /* not support */
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22 #define SLOT3_BASE_ADDR CTL_BASE_SDIO1
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23 #define SLOT4_BASE_ADDR (CTL_BASE_SDIO1 + 0x0100)
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24 #define SLOT5_BASE_ADDR (CTL_BASE_SDIO1 + 0x0200)
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25 #define SLOT6_BASE_ADDR CTL_BASE_SDIO2
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26 #define SLOT7_BASE_ADDR (CTL_BASE_SDIO2 + 0x0100)
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27 #define SLOT8_BASE_ADDR (CTL_BASE_SDIO2 + 0x0200)
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28 #define SLOT9_BASE_ADDR CTL_BASE_EMMC
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29 #define SLOT10_BASE_ADDR (CTL_BASE_SDIO2 + 0x0100)
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30 #define SLOT11_BASE_ADDR 0 /* not support */
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32 /* sdio controller version information */
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36 #define SDIO0_VER SDIO_30
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37 #define SDIO1_VER SDIO_20
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38 #define SDIO2_VER SDIO_20
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39 #define SDIO3_VER SDIO_30
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41 /* sdio slot register */
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42 #define AHB_SDIO_CTRL (SPRD_AHB_PHYS + 0x0018)
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44 #define SLOT0_SEL & (~BIT_16)
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45 #define SLOT1_SEL | BIT_16
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46 #define SLOT2_SEL & 0 /* not support */
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47 #define SLOT3_SEL & (~(BIT_1 | BIT_0))
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48 #define SLOT4_SEL (REG32(AHB_SDIO_CTRL) & (~BIT_1)) | BIT_0
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49 #define SLOT5_SEL (REG32(AHB_SDIO_CTRL) & (~BIT_0)) | BIT_1
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50 #define SLOT6_SEL & (~(BIT_3 | BIT_2))
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51 #define SLOT7_SEL (REG32(AHB_SDIO_CTRL) & (~BIT_3)) | BIT_2
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52 #define SLOT8_SEL (REG32(AHB_SDIO_CTRL) & (~BIT_2)) | BIT_3
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53 #define SLOT9_SEL & (~BIT_17)
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54 #define SLOT10_SEL | BIT_17
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55 #define SLOT11_SEL & 0 /* not support */
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57 /* sdio ahb clock enable : 0x20D00000*/
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60 /* sdio ahb base clock select */
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61 /* REG_AP_CLK_SDIO0_CFG */
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62 /* REG_AP_CLK_SDIO1_CFG */
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63 /* REG_AP_CLK_SDIO2_CFG */
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64 /* REG_AP_CLK_EMMC_CFG */
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65 /* sdio ahb power on or off */
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66 /* sdio ahb power sel */
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75 /* power enable info */
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80 /* power select info */
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84 sel_info_t pwr_sel[4];
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90 /* enable clock reigster info */
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93 /* reset clock reigster info */
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96 /* base clock reigster info */
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100 sel_info_t clk_sel[4];
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102 sdio_pwr_info_t pwr_io;
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103 sdio_pwr_info_t pwr_core;
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104 } sdio_base_info_t;
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106 LOCAL const sdio_base_info_t sdio_resource_detail[]=
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109 {sdio_index, ahb_en, ahb_en_bit, ahb_rst, ahb_rst_bit, clk_reg, clk_mask
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110 , clk_shft, val, step, val, step, val, step, val, step
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111 , pd_set, pd_set_bit
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112 , pd_clr, pd_clr_bit
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113 , pwr_sel_reg, pwr_mask
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114 , pwr_shft, val, step, val, step, val, step, val, step
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115 , pd_set, pd_set_bit
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116 , pd_clr, pd_clr_bit
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117 , pwr_sel, pwr_mask
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118 , pwr_shft, val, step, val, step, val, step, val, step },
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120 {0, AHB_EB, BIT_8, AHB_SOFT_RST, BIT_11,REG_AP_CLK_SDIO0_CFG, (BIT_1 | BIT_0)
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121 , 0, 26000000, 0x00, 192000000, 0x01, 256000000, 0x02, 312000000, 0x03
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122 , ANA_REG_GLB_LDO_PD_CTRL, BIT_1
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124 , ANA_REG_GLB_LDO_V_CTRL1, (BIT_3 | BIT_2)
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125 , 2, 2800, 0x00, 3000, 0x01, 2500, 0x02, 1800, 0x03
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129 , 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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131 {1, AHB_EB, BIT_9, AHB_SOFT_RST, BIT_12,REG_AP_CLK_SDIO1_CFG, (BIT_1 | BIT_0)
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132 , 0, 48000000, 0x00, 76800000, 0x01, 96000000, 0x02, 128000000, 0x03
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133 , ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT_1 /* used vdd18 */
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134 , ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT_1
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135 , ANA_REG_GLB_LDO_V_CTRL0, (BIT_1 | BIT_0)
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136 , 0x00, 1500, 0x00, 1800, 0x01, 1300, 0x02, 1200, 0x03
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140 , 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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141 {2, AHB_EB, BIT_10, AHB_SOFT_RST, BIT_13,REG_AP_CLK_SDIO2_CFG, (BIT_1 | BIT_0)
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142 , 0, 48000000, 0x00, 76800000, 0x01, 96000000, 0x02, 128000000, 0x03
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143 , ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT_1 /* used vdd18 */
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144 , ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT_1
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145 , ANA_REG_GLB_LDO_V_CTRL0, (BIT_1 | BIT_0)
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146 , 0x00, 1500, 0x00, 1800, 0x01, 1300, 0x02, 1200, 0x03
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150 , 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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151 {3, AHB_EB, BIT_11, AHB_SOFT_RST, BIT_14,REG_AP_CLK_EMMC_CFG, (BIT_1 | BIT_0)
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152 , 0, 26000000, 0x00, 192000000, 0x01, 256000000, 0x02, 312000000, 0x03
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153 , ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT_7
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154 , ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT_7
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155 , ANA_REG_GLB_LDO_V_CTRL0, (BIT_13 | BIT_12)
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156 , 12, 1500, 0x00, 1800, 0x01, 1300, 0x02, 1200, 0x03
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157 , ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT_8
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158 , ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT_8
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159 , ANA_REG_GLB_LDO_V_CTRL0, (BIT_15 | BIT_14)
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160 , 14, 2800, 0x00, 3000, 0x01, 2500, 0x02, 1800, 0x03 },
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163 #endif /* __SDIO_CHIP_H_ */