1 /*********************************************************************
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2 ** File Name: sdio_reg.h
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3 ** Author: yanping.xie
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5 ** Copyright: 2004 Spreadtrum, Incoporated. All Rights Reserved.
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6 ** Description: This file describe operation of sdio host.
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7 *********************************************************************
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9 *********************************************************************
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11 ** ------------------------------------------------------------------------- **
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12 ** DATE NAME DESCRIPTION
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13 ** 09/05/2013 ypxie Create.
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14 ********************************************************************/
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15 #ifndef __SDIO_REG_H_
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16 #define __SDIO_REG_H_
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18 /* REG[0x0040], REG[0x0044], REG[0x0048] : capability */
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19 typedef struct sdhost_cap_v20_t_tag
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22 uint32 timeout_clk_freq : 6; ///< [5:0]
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23 uint32 rsrvd0 : 1; ///< [6]
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24 uint32 timeout_lk_uint : 1; ///< [7]
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25 uint32 base_clk_freq : 6; ///< [13:8]
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26 uint32 rsrvd1 : 2; ///< [15:14]
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27 uint32 max_blk_size : 2; ///< [17:16]
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28 uint32 rsrvd2 : 3; ///< [20:18]
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29 uint32 spprt_high_speed : 1; ///< [21]
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30 uint32 spprt_dma : 1; ///< [22]
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31 uint32 spprt_susp_res : 1; ///< [23]
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32 uint32 spprt_volt_33 : 1; ///< [24]
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33 uint32 spprt_volt_30 : 1; ///< [25]
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34 uint32 spprt_volt_18 : 1; ///< [26]
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35 uint32 rsrvd3 : 5; ///< [31:27]
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38 uint32 cap2; ///< reserved
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40 /* MAX_CUR_CAP[0x0048] */
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41 uint32 max_cur_volt_33 : 8; ///< [7:0]
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42 uint32 max_cur_volt_30 : 8; ///< [15:8]
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43 uint32 max_cur_volt_18 : 8; ///< [23:16]
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47 typedef struct sdhost_cap_v30_t_tag
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50 uint32 timeout_clk_freq : 6; ///< [5:0]
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51 uint32 rsrvd0 : 1; ///< [6]
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52 uint32 timeout_lk_uint : 1; ///< [7]
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53 uint32 base_clk_freq : 8; ///< [15:8]
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54 uint32 max_blk_size : 2; ///< [17:16]
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55 uint32 spprt_8bit : 1; ///< [18]
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56 uint32 spprt_adma2 : 1; ///< [19]
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57 uint32 rsrvd1 : 1; ///< [20]
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58 uint32 spprt_high_speed : 1; ///< [21]
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59 uint32 spprt_dma : 1; ///< [22]
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60 uint32 spprt_susp_res : 1; ///< [23]
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61 uint32 spprt_volt_33 : 1; ///< [24]
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62 uint32 spprt_volt_30 : 1; ///< [25]
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63 uint32 spprt_volt_18 : 1; ///< [26]
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64 uint32 rsrvd2 : 1; ///< [27]
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65 uint32 spprt_64bit_sys : 1; ///< [28]
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66 uint32 spprt_async_int : 1; ///< [29]
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67 uint32 rsrvd3 : 2; ///< [31:30]
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70 uint32 spprt_sdr52 : 1; ///< [0]
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71 uint32 spprt_sdr104 : 1; ///< [1]
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72 uint32 spprt_ddr52 : 1; ///< [2]
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73 uint32 rsrvd4 : 29; ///< [31:3]
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75 /* MAX_CUR_CAP[0x0048] */
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76 uint32 max_cur_volt_33 : 8; ///< [7:0]
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77 uint32 max_cur_volt_30 : 8; ///< [15:8]
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78 uint32 max_cur_volt_18 : 8; ///< [23:16]
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81 /* REG[0x000C] : cmd trans mode */
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82 /* [cmd_index] bit[29:24] */
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83 /* [cmd_type] bit[23:22] */
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84 #define SDIO_CMD_TYPE_ABORT ( 3 << 22 )
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85 #define SDIO_CMD_TYPE_RESUME ( 2 << 22 )
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86 #define SDIO_CMD_TYPE_SUSPEND ( 1 << 22 )
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87 #define SDIO_CMD_TYPE_NML ( 0 << 22 )
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89 /* [transmode] bit[6:0], bit[21], bit[31], bit[30] */
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90 #define SDIO_BOOT_ACK BIT_31 ///< v3.0
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91 #define SDIO_CMD_LINE_BOOT BIT_30 ///< v3.0
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92 #define SDIO_DATA_PRE BIT_21
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94 /* v3.0 auto cmd12 is bit[3:2] , v2.0 auto cmd12 is bit[2] */
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95 #define SDIO_TRANS_DIS_AUTO ( 0x00 << 2 ) ///< v3.0
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96 #define SDIO_TRANS_AUTO_CMD12_EN BIT_2 ///< v2.0
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97 #define SDIO_TRANS_AUTO_CMD23_EN ( 0x02 << 2 ) ///< v3.0
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99 #define SDIO_TRANS_COMP_ATA BIT_6
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100 #define SDIO_TRANS_MULTIBLK BIT_5
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101 #define SDIO_TRANS_DIR_READ BIT_4
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102 #define SDIO_TRANS_BLK_CNT_EN BIT_1
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103 #define SDIO_TRANS_DMA_EN BIT_0
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105 /* [response] bit[17:16], bit[20], bit[19]*/
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106 #define SDIO_CMD_INDEX_CHK BIT_20
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107 #define SDIO_CMD_CRC_CHK BIT_19
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109 #define SDIO_CMD_NO_RSP ( 0x00 << 16 )
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110 #define SDIO_CMD_RSP_136 ( 0x01 << 16 )
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111 #define SDIO_CMD_RSP_48 ( 0x02 << 16 )
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112 #define SDIO_CMD_RSP_48_BUSY ( 0x03 << 16 )
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114 #define SDIO_NO_RSP 0x00
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115 #define SDIO_R1 ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
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116 #define SDIO_R2 ( SDIO_CMD_RSP_136 | SDIO_CMD_CRC_CHK )
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117 #define SDIO_R3 SDIO_CMD_RSP_48
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118 #define SDIO_R4 SDIO_CMD_RSP_48
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119 #define SDIO_R5 ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
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120 #define SDIO_R6 ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
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121 #define SDIO_R7 ( SDIO_CMD_RSP_48 | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
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122 #define SDIO_R1B ( SDIO_CMD_RSP_48_BUSY | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
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123 #define SDIO_R5B ( SDIO_CMD_RSP_48_BUSY | SDIO_CMD_INDEX_CHK | SDIO_CMD_CRC_CHK )
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125 /* REG[0x0030], REG[0x0034], REG[0x0038] : interrupt */
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126 #define INT_CMD_CMPLT BIT_0
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127 #define INT_TR_CMPLT BIT_1
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128 #define INT_CAP_EVENT BIT_2
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129 #define INT_DMA_INT BIT_3
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130 #define INT_BUF_WR_RDY BIT_4
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131 #define INT_BUF_RD_RDY BIT_5
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132 #define INT_CARD_INT BIT_8
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134 #define INT_ERR_INT BIT_15
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136 #define INT_CMD_TIMEOUT BIT_16
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137 #define INT_CMD_CRC BIT_17
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138 #define INT_CMD_END_BIT BIT_18
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139 #define INT_CMD_IND BIT_19
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140 #define INT_DATA_TIMEOUT BIT_20
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141 #define INT_DATA_CRC BIT_21
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142 #define INT_DATA_END_BIT BIT_22
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143 #define INT_CUR_LMT BIT_23
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144 #define INT_AUTO_CMD12 BIT_24
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145 #define INT_TRGT_RESP BIT_28
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146 #define INT_VNDR_ERR_ST (BIT_29 | BIT_30 | BIT_31)
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148 #define INT_ALL (BIT_15 | BIT_8 | 0xFF)
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150 typedef struct sdio_reg_v20_t_tag
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152 volatile uint32 dma_addr; ///< 0x0000
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153 volatile uint32 blk_size_cnt; ///< 0x0004
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154 volatile uint32 cmd_argu; ///< 0x0008
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155 volatile uint32 tr_mode; ///< 0x000C
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156 volatile uint32 resp0; ///< 0x0010
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157 volatile uint32 resp1; ///< 0x0014
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158 volatile uint32 resp2; ///< 0x0018
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159 volatile uint32 resp3; ///< 0x001C
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160 volatile uint32 buf_port; ///< 0x0020
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161 volatile uint32 pres_state; ///< 0x0024
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162 volatile uint32 sd_ctrl1; ///< 0x0028
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163 volatile uint32 sd_ctrl2; ///< 0x002C
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164 volatile uint32 int_st; ///< 0x0030
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165 volatile uint32 int_st_en; ///< 0x0034
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166 volatile uint32 int_sig_en; ///< 0x0038
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167 volatile uint32 cmd12_st; ///< 0x003C
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168 volatile uint32 cap1; ///< 0x0040
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169 volatile uint32 cap2; ///< 0x0044
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170 volatile uint32 cur_cap1; ///< 0x0048
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171 volatile uint32 cur_cap2; ///< 0x004C
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172 } sdio_reg_v20_t, *sdio_reg_ptr;
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174 typedef struct sdio_reg_v30_t_tag
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176 volatile uint32 dma_addr; ///< 0x0000
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177 volatile uint32 blk_size_cnt; ///< 0x0004
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178 volatile uint32 cmd_argu; ///< 0x0008
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179 volatile uint32 tr_mode; ///< 0x000C
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180 volatile uint32 resp0; ///< 0x0010
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181 volatile uint32 resp1; ///< 0x0014
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182 volatile uint32 resp2; ///< 0x0018
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183 volatile uint32 resp3; ///< 0x001C
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184 volatile uint32 buf_port; ///< 0x0020
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185 volatile uint32 pres_state; ///< 0x0024
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186 volatile uint32 sd_ctrl1; ///< 0x0028
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187 volatile uint32 sd_ctrl2; ///< 0x002C
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188 volatile uint32 int_st; ///< 0x0030
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189 volatile uint32 int_st_en; ///< 0x0034
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190 volatile uint32 int_sig_en; ///< 0x0038
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191 volatile uint32 sd_ctrl3; ///< 0x003C
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192 volatile uint32 cap1; ///< 0x0040
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193 volatile uint32 cap2; ///< 0x0044
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194 volatile uint32 cur_cap1; ///< 0x0048
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195 volatile uint32 cur_cap2; ///< 0x004C
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196 volatile uint32 force_evt; ///< 0x0050
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197 volatile uint32 reserved0; ///< 0x0054
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198 volatile uint32 reserved1; ///< 0x0058
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199 volatile uint32 reserved2; ///< 0x005C
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200 volatile uint32 pre_val_def; ///< 0x0060
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201 volatile uint32 pre_val_high; ///< 0x0064
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202 volatile uint32 pre_val_sdr52; ///< 0x0068
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203 volatile uint32 pre_val_ddr52; ///< 0x006C
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204 volatile uint32 reserved3; ///< 0x0070
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205 volatile uint32 reserved4; ///< 0x0074
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206 volatile uint32 reserved5; ///< 0x0078
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207 volatile uint32 reserved6; ///< 0x007C
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208 volatile uint32 wr_dly; ///< 0x0080
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209 volatile uint32 rd_pos_dly; ///< 0x0080
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210 volatile uint32 rd_neg_dly; ///< 0x0088
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211 /* slt_int_st ... 0x00FC is slot interrupt status */
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212 } sdio_reg_v30_t, *sdio_reg_v30_ptr;
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214 typedef struct sdio_reg_slave_t_tag
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216 volatile uint32 dma_addr; ///< 0x0000
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217 volatile uint32 rst_dma_set; ///< 0x0004
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218 volatile uint32 reserved0; ///< 0x0008
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219 volatile uint32 blk_size_cnt; ///< 0x000C
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220 volatile uint32 tr_mode; ///< 0x0010
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221 volatile uint32 cur_st; ///< 0x0014
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222 volatile uint32 cmd_argu; ///< 0x0018
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223 volatile uint32 rsp_argu; ///< 0x001C
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224 volatile uint32 buf_port; ///< 0x0020
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225 volatile uint32 reserved1; ///< 0x0024
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226 volatile uint32 reserved2; ///< 0x0028
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227 volatile uint32 reserved3; ///< 0x002C
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228 volatile uint32 int_en; ///< 0x0030
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229 volatile uint32 int_clr; ///< 0x0034
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230 volatile uint32 int_raw_st; ///< 0x0038
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231 volatile uint32 int_mask; ///< 0x003C
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232 volatile uint32 supt_ocr; ///< 0x0040
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233 volatile uint32 cur_ocr; ///< 0x0044
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234 } sdio_reg_slave_t, *sdio_reg_slave_ptr;
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236 #endif /* __SDIO_REG_H_ */