1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx AXI platforms watchdog timer driver.
5 * Author(s): Michal Simek <michal.simek@xilinx.com>
6 * Shreenidhi Shedi <yesshedi@gmail.com>
8 * Copyright (c) 2011-2018 Xilinx Inc.
15 #include <linux/err.h>
18 #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */
19 #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
20 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
21 #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */
23 struct watchdog_regs {
29 struct xlnx_wdt_platdata {
31 struct watchdog_regs *regs;
34 static int xlnx_wdt_reset(struct udevice *dev)
37 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
39 debug("%s ", __func__);
41 /* Read the current contents of TCSR0 */
42 reg = readl(&platdata->regs->twcsr0);
44 /* Clear the watchdog WDS bit */
45 if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
46 writel(reg | XWT_CSR0_WDS_MASK, &platdata->regs->twcsr0);
51 static int xlnx_wdt_stop(struct udevice *dev)
54 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
56 if (platdata->enable_once) {
57 debug("Can't stop Xilinx watchdog.\n");
61 /* Read the current contents of TCSR0 */
62 reg = readl(&platdata->regs->twcsr0);
64 writel(reg & ~XWT_CSR0_EWDT1_MASK, &platdata->regs->twcsr0);
65 writel(~XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
67 debug("Watchdog disabled!\n");
72 static int xlnx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
74 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
76 debug("%s:\n", __func__);
78 writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
79 &platdata->regs->twcsr0);
81 writel(XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
86 static int xlnx_wdt_probe(struct udevice *dev)
88 debug("%s: Probing wdt%u\n", __func__, dev->seq);
93 static int xlnx_wdt_ofdata_to_platdata(struct udevice *dev)
95 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
97 platdata->regs = (struct watchdog_regs *)dev_read_addr(dev);
98 if (IS_ERR(platdata->regs))
99 return PTR_ERR(platdata->regs);
101 platdata->enable_once = dev_read_u32_default(dev,
102 "xlnx,wdt-enable-once", 0);
104 debug("%s: wdt-enable-once %d\n", __func__, platdata->enable_once);
109 static const struct wdt_ops xlnx_wdt_ops = {
110 .start = xlnx_wdt_start,
111 .reset = xlnx_wdt_reset,
112 .stop = xlnx_wdt_stop,
115 static const struct udevice_id xlnx_wdt_ids[] = {
116 { .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
117 { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
121 U_BOOT_DRIVER(xlnx_wdt) = {
124 .of_match = xlnx_wdt_ids,
125 .probe = xlnx_wdt_probe,
126 .platdata_auto_alloc_size = sizeof(struct xlnx_wdt_platdata),
127 .ofdata_to_platdata = xlnx_wdt_ofdata_to_platdata,
128 .ops = &xlnx_wdt_ops,