1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx AXI platforms watchdog timer driver.
5 * Author(s): Michal Simek <michal.simek@xilinx.com>
6 * Shreenidhi Shedi <yesshedi@gmail.com>
8 * Copyright (c) 2011-2018 Xilinx Inc.
16 #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */
17 #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
18 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
19 #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */
21 struct watchdog_regs {
27 struct xlnx_wdt_platdata {
29 struct watchdog_regs *regs;
32 static int xlnx_wdt_reset(struct udevice *dev)
35 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
37 debug("%s ", __func__);
39 /* Read the current contents of TCSR0 */
40 reg = readl(&platdata->regs->twcsr0);
42 /* Clear the watchdog WDS bit */
43 if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
44 writel(reg | XWT_CSR0_WDS_MASK, &platdata->regs->twcsr0);
49 static int xlnx_wdt_stop(struct udevice *dev)
52 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
54 if (platdata->enable_once) {
55 debug("Can't stop Xilinx watchdog.\n");
59 /* Read the current contents of TCSR0 */
60 reg = readl(&platdata->regs->twcsr0);
62 writel(reg & ~XWT_CSR0_EWDT1_MASK, &platdata->regs->twcsr0);
63 writel(~XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
65 debug("Watchdog disabled!\n");
70 static int xlnx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
72 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
74 debug("%s:\n", __func__);
76 writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
77 &platdata->regs->twcsr0);
79 writel(XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
84 static int xlnx_wdt_probe(struct udevice *dev)
86 debug("%s: Probing wdt%u\n", __func__, dev->seq);
91 static int xlnx_wdt_ofdata_to_platdata(struct udevice *dev)
93 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
95 platdata->regs = (struct watchdog_regs *)dev_read_addr(dev);
96 if (IS_ERR(platdata->regs))
97 return PTR_ERR(platdata->regs);
99 platdata->enable_once = dev_read_u32_default(dev,
100 "xlnx,wdt-enable-once", 0);
102 debug("%s: wdt-enable-once %d\n", __func__, platdata->enable_once);
107 static const struct wdt_ops xlnx_wdt_ops = {
108 .start = xlnx_wdt_start,
109 .reset = xlnx_wdt_reset,
110 .stop = xlnx_wdt_stop,
113 static const struct udevice_id xlnx_wdt_ids[] = {
114 { .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
115 { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
119 U_BOOT_DRIVER(xlnx_wdt) = {
122 .of_match = xlnx_wdt_ids,
123 .probe = xlnx_wdt_probe,
124 .platdata_auto_alloc_size = sizeof(struct xlnx_wdt_platdata),
125 .ofdata_to_platdata = xlnx_wdt_ofdata_to_platdata,
126 .ops = &xlnx_wdt_ops,