1 // SPDX-License-Identifier: GPL-2.0+
3 * Watchdog driver for SP805 on some Layerscape SoC
9 #include <asm/global_data.h>
13 #include <dm/device.h>
14 #include <dm/fdtaddr.h>
16 #include <linux/bitops.h>
19 #include <linux/err.h>
22 #define WDTCONTROL 0x008
23 #define WDTINTCLR 0x00C
26 #define TIME_OUT_MIN_MSECS 1
27 #define TIME_OUT_MAX_MSECS 120000
28 #define SYS_FSL_WDT_CLK_DIV 16
29 #define INT_ENABLE BIT(0)
30 #define RESET_ENABLE BIT(1)
32 #define UNLOCK 0x1ACCE551
33 #define LOCK 0x00000001
34 #define INT_MASK BIT(0)
36 DECLARE_GLOBAL_DATA_PTR;
38 struct sp805_wdt_priv {
40 unsigned long clk_rate;
43 static int sp805_wdt_reset(struct udevice *dev)
45 struct sp805_wdt_priv *priv = dev_get_priv(dev);
47 writel(UNLOCK, priv->reg + WDTLOCK);
48 writel(INT_MASK, priv->reg + WDTINTCLR);
49 writel(LOCK, priv->reg + WDTLOCK);
50 readl(priv->reg + WDTLOCK);
55 static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
59 struct sp805_wdt_priv *priv = dev_get_priv(dev);
61 load_time = (u32)timeout;
62 if (timeout < TIME_OUT_MIN_MSECS)
63 load_time = TIME_OUT_MIN_MSECS;
64 else if (timeout > TIME_OUT_MAX_MSECS)
65 load_time = TIME_OUT_MAX_MSECS;
66 /* sp805 runs counter with given value twice, so when the max timeout is
67 * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
71 load_value = (gd->bus_clk) /
72 (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
74 /* platform provide clk */
75 load_value = (timeout / 2) * (priv->clk_rate / 1000);
78 writel(UNLOCK, priv->reg + WDTLOCK);
79 writel(load_value, priv->reg + WDTLOAD);
80 writel(INT_MASK, priv->reg + WDTINTCLR);
81 writel(INT_ENABLE | RESET_ENABLE, priv->reg + WDTCONTROL);
82 writel(LOCK, priv->reg + WDTLOCK);
83 readl(priv->reg + WDTLOCK);
88 static int sp805_wdt_stop(struct udevice *dev)
90 struct sp805_wdt_priv *priv = dev_get_priv(dev);
92 writel(UNLOCK, priv->reg + WDTLOCK);
93 writel(DISABLE, priv->reg + WDTCONTROL);
94 writel(LOCK, priv->reg + WDTLOCK);
95 readl(priv->reg + WDTLOCK);
100 static int sp805_wdt_expire_now(struct udevice *dev, ulong flags)
102 sp805_wdt_start(dev, 0, flags);
107 static int sp805_wdt_probe(struct udevice *dev)
109 debug("%s: Probing wdt%u (sp805-wdt)\n", __func__, dev_seq(dev));
114 static int sp805_wdt_of_to_plat(struct udevice *dev)
116 struct sp805_wdt_priv *priv = dev_get_priv(dev);
119 priv->reg = (void __iomem *)dev_read_addr(dev);
120 if (IS_ERR(priv->reg))
121 return PTR_ERR(priv->reg);
123 if (!clk_get_by_index(dev, 0, &clk))
124 priv->clk_rate = clk_get_rate(&clk);
129 static const struct wdt_ops sp805_wdt_ops = {
130 .start = sp805_wdt_start,
131 .reset = sp805_wdt_reset,
132 .stop = sp805_wdt_stop,
133 .expire_now = sp805_wdt_expire_now,
136 static const struct udevice_id sp805_wdt_ids[] = {
137 { .compatible = "arm,sp805" },
141 U_BOOT_DRIVER(sp805_wdt) = {
144 .of_match = sp805_wdt_ids,
145 .probe = sp805_wdt_probe,
146 .priv_auto = sizeof(struct sp805_wdt_priv),
147 .of_to_plat = sp805_wdt_of_to_plat,
148 .ops = &sp805_wdt_ops,