drivers/watchdog/sp5100_tco.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *      sp5100_tco :    TCO timer driver for sp5100 chipsets
   4  *
   5  *      (c) Copyright 2009 Google Inc., All Rights Reserved.
   6  *
   7  *      Based on i8xx_tco.c:
   8  *      (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
   9  *      Reserved.
  10  *                              https://www.kernelconcepts.de
  11  *
  12  *      See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
  13  *          AMD Publication 45482 "AMD SB800-Series Southbridges Register
  14  *                                                            Reference Guide"
  15  *          AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
  16  *                              for AMD Family 16h Models 00h-0Fh Processors"
  17  *          AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
  18  *          AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
  19  *                              for AMD Family 16h Models 30h-3Fh Processors"
  20  *          AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
  21  *                              for AMD Family 17h Model 18h, Revision B1
  22  *                              Processors (PUB)
  23  *          AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
  24  *                              for AMD Family 17h Model 20h, Revision A1
  25  *                              Processors (PUB)
  26  */
  27
  28 /*
  29  *      Includes, defines, variables, module parameters, ...
  30  */
  31
  32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33
  34 #include <linux/init.h>
  35 #include <linux/io.h>
  36 #include <linux/ioport.h>
  37 #include <linux/module.h>
  38 #include <linux/moduleparam.h>
  39 #include <linux/pci.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/types.h>
  42 #include <linux/watchdog.h>
  43
  44 #include "sp5100_tco.h"
  45
  46 #define TCO_DRIVER_NAME "sp5100-tco"
  47
  48 /* internal variables */
  49
  50 enum tco_reg_layout {
  51         sp5100, sb800, efch, efch_mmio
  52 };
  53
  54 struct sp5100_tco {
  55         struct watchdog_device wdd;
  56         void __iomem *tcobase;
  57         enum tco_reg_layout tco_reg_layout;
  58 };
  59
  60 /* the watchdog platform device */
  61 static struct platform_device *sp5100_tco_platform_device;
  62 /* the associated PCI device */
  63 static struct pci_dev *sp5100_tco_pci;
  64
  65 /* module parameters */
  66
  67 #define WATCHDOG_HEARTBEAT 60   /* 60 sec default heartbeat. */
  68 static int heartbeat = WATCHDOG_HEARTBEAT;  /* in seconds */
  69 module_param(heartbeat, int, 0);
  70 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
  71                  __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
  72
  73 static bool nowayout = WATCHDOG_NOWAYOUT;
  74 module_param(nowayout, bool, 0);
  75 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
  76                 " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  77
  78 /*
  79  * Some TCO specific functions
  80  */
  81
  82 static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
  83 {
  84         if (dev->vendor == PCI_VENDOR_ID_ATI &&
  85             dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
  86             dev->revision < 0x40) {
  87                 return sp5100;
  88         } else if (dev->vendor == PCI_VENDOR_ID_AMD &&
  89             sp5100_tco_pci->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
  90             sp5100_tco_pci->revision >= AMD_ZEN_SMBUS_PCI_REV) {
  91                 return efch_mmio;
  92         } else if (dev->vendor == PCI_VENDOR_ID_AMD &&
  93             ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
  94              dev->revision >= 0x41) ||
  95             (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
  96              dev->revision >= 0x49))) {
  97                 return efch;
  98         }
  99         return sb800;
 100 }
 101
 102 static int tco_timer_start(struct watchdog_device *wdd)
 103 {
 104         struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 105         u32 val;
 106
 107         val = readl(SP5100_WDT_CONTROL(tco->tcobase));
 108         val |= SP5100_WDT_START_STOP_BIT;
 109         writel(val, SP5100_WDT_CONTROL(tco->tcobase));
 110
 111         return 0;
 112 }
 113
 114 static int tco_timer_stop(struct watchdog_device *wdd)
 115 {
 116         struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 117         u32 val;
 118
 119         val = readl(SP5100_WDT_CONTROL(tco->tcobase));
 120         val &= ~SP5100_WDT_START_STOP_BIT;
 121         writel(val, SP5100_WDT_CONTROL(tco->tcobase));
 122
 123         return 0;
 124 }
 125
 126 static int tco_timer_ping(struct watchdog_device *wdd)
 127 {
 128         struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 129         u32 val;
 130
 131         val = readl(SP5100_WDT_CONTROL(tco->tcobase));
 132         val |= SP5100_WDT_TRIGGER_BIT;
 133         writel(val, SP5100_WDT_CONTROL(tco->tcobase));
 134
 135         return 0;
 136 }
 137
 138 static int tco_timer_set_timeout(struct watchdog_device *wdd,
 139                                  unsigned int t)
 140 {
 141         struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 142
 143         /* Write new heartbeat to watchdog */
 144         writel(t, SP5100_WDT_COUNT(tco->tcobase));
 145
 146         wdd->timeout = t;
 147
 148         return 0;
 149 }
 150
 151 static u8 sp5100_tco_read_pm_reg8(u8 index)
 152 {
 153         outb(index, SP5100_IO_PM_INDEX_REG);
 154         return inb(SP5100_IO_PM_DATA_REG);
 155 }
 156
 157 static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
 158 {
 159         u8 val;
 160
 161         outb(index, SP5100_IO_PM_INDEX_REG);
 162         val = inb(SP5100_IO_PM_DATA_REG);
 163         val &= reset;
 164         val |= set;
 165         outb(val, SP5100_IO_PM_DATA_REG);
 166 }
 167
 168 static void tco_timer_enable(struct sp5100_tco *tco)
 169 {
 170         u32 val;
 171
 172         switch (tco->tco_reg_layout) {
 173         case sb800:
 174                 /* For SB800 or later */
 175                 /* Set the Watchdog timer resolution to 1 sec */
 176                 sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
 177                                           0xff, SB800_PM_WATCHDOG_SECOND_RES);
 178
 179                 /* Enable watchdog decode bit and watchdog timer */
 180                 sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
 181                                           ~SB800_PM_WATCHDOG_DISABLE,
 182                                           SB800_PCI_WATCHDOG_DECODE_EN);
 183                 break;
 184         case sp5100:
 185                 /* For SP5100 or SB7x0 */
 186                 /* Enable watchdog decode bit */
 187                 pci_read_config_dword(sp5100_tco_pci,
 188                                       SP5100_PCI_WATCHDOG_MISC_REG,
 189                                       &val);
 190
 191                 val |= SP5100_PCI_WATCHDOG_DECODE_EN;
 192
 193                 pci_write_config_dword(sp5100_tco_pci,
 194                                        SP5100_PCI_WATCHDOG_MISC_REG,
 195                                        val);
 196
 197                 /* Enable Watchdog timer and set the resolution to 1 sec */
 198                 sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
 199                                           ~SP5100_PM_WATCHDOG_DISABLE,
 200                                           SP5100_PM_WATCHDOG_SECOND_RES);
 201                 break;
 202         case efch:
 203                 /* Set the Watchdog timer resolution to 1 sec and enable */
 204                 sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
 205                                           ~EFCH_PM_WATCHDOG_DISABLE,
 206                                           EFCH_PM_DECODEEN_SECOND_RES);
 207                 break;
 208         default:
 209                 break;
 210         }
 211 }
 212
 213 static u32 sp5100_tco_read_pm_reg32(u8 index)
 214 {
 215         u32 val = 0;
 216         int i;
 217
 218         for (i = 3; i >= 0; i--)
 219                 val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
 220
 221         return val;
 222 }
 223
 224 static u32 sp5100_tco_request_region(struct device *dev,
 225                                      u32 mmio_addr,
 226                                      const char *dev_name)
 227 {
 228         if (!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
 229                                      dev_name)) {
 230                 dev_dbg(dev, "MMIO address 0x%08x already in use\n", mmio_addr);
 231                 return 0;
 232         }
 233
 234         return mmio_addr;
 235 }
 236
 237 static u32 sp5100_tco_prepare_base(struct sp5100_tco *tco,
 238                                    u32 mmio_addr,
 239                                    u32 alt_mmio_addr,
 240                                    const char *dev_name)
 241 {
 242         struct device *dev = tco->wdd.parent;
 243
 244         dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n", mmio_addr);
 245
 246         if (!mmio_addr && !alt_mmio_addr)
 247                 return -ENODEV;
 248
 249         /* Check for MMIO address and alternate MMIO address conflicts */
 250         if (mmio_addr)
 251                 mmio_addr = sp5100_tco_request_region(dev, mmio_addr, dev_name);
 252
 253         if (!mmio_addr && alt_mmio_addr)
 254                 mmio_addr = sp5100_tco_request_region(dev, alt_mmio_addr, dev_name);
 255
 256         if (!mmio_addr) {
 257                 dev_err(dev, "Failed to reserve MMIO or alternate MMIO region\n");
 258                 return -EBUSY;
 259         }
 260
 261         tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
 262         if (!tco->tcobase) {
 263                 dev_err(dev, "MMIO address 0x%08x failed mapping\n", mmio_addr);
 264                 devm_release_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
 265                 return -ENOMEM;
 266         }
 267
 268         dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
 269
 270         return 0;
 271 }
 272
 273 static int sp5100_tco_timer_init(struct sp5100_tco *tco)
 274 {
 275         struct watchdog_device *wdd = &tco->wdd;
 276         struct device *dev = wdd->parent;
 277         u32 val;
 278
 279         val = readl(SP5100_WDT_CONTROL(tco->tcobase));
 280         if (val & SP5100_WDT_DISABLED) {
 281                 dev_err(dev, "Watchdog hardware is disabled\n");
 282                 return -ENODEV;
 283         }
 284
 285         /*
 286          * Save WatchDogFired status, because WatchDogFired flag is
 287          * cleared here.
 288          */
 289         if (val & SP5100_WDT_FIRED)
 290                 wdd->bootstatus = WDIOF_CARDRESET;
 291
 292         /* Set watchdog action to reset the system */
 293         val &= ~SP5100_WDT_ACTION_RESET;
 294         writel(val, SP5100_WDT_CONTROL(tco->tcobase));
 295
 296         /* Set a reasonable heartbeat before we stop the timer */
 297         tco_timer_set_timeout(wdd, wdd->timeout);
 298
 299         /*
 300          * Stop the TCO before we change anything so we don't race with
 301          * a zeroed timer.
 302          */
 303         tco_timer_stop(wdd);
 304
 305         return 0;
 306 }
 307
 308 static u8 efch_read_pm_reg8(void __iomem *addr, u8 index)
 309 {
 310         return readb(addr + index);
 311 }
 312
 313 static void efch_update_pm_reg8(void __iomem *addr, u8 index, u8 reset, u8 set)
 314 {
 315         u8 val;
 316
 317         val = readb(addr + index);
 318         val &= reset;
 319         val |= set;
 320         writeb(val, addr + index);
 321 }
 322
 323 static void tco_timer_enable_mmio(void __iomem *addr)
 324 {
 325         efch_update_pm_reg8(addr, EFCH_PM_DECODEEN3,
 326                             ~EFCH_PM_WATCHDOG_DISABLE,
 327                             EFCH_PM_DECODEEN_SECOND_RES);
 328 }
 329
 330 static int sp5100_tco_setupdevice_mmio(struct device *dev,
 331                                        struct watchdog_device *wdd)
 332 {
 333         struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 334         const char *dev_name = SB800_DEVNAME;
 335         u32 mmio_addr = 0, alt_mmio_addr = 0;
 336         struct resource *res;
 337         void __iomem *addr;
 338         int ret;
 339         u32 val;
 340
 341         res = request_mem_region_muxed(EFCH_PM_ACPI_MMIO_PM_ADDR,
 342                                        EFCH_PM_ACPI_MMIO_PM_SIZE,
 343                                        "sp5100_tco");
 344
 345         if (!res) {
 346                 dev_err(dev,
 347                         "Memory region 0x%08x already in use\n",
 348                         EFCH_PM_ACPI_MMIO_PM_ADDR);
 349                 return -EBUSY;
 350         }
 351
 352         addr = ioremap(EFCH_PM_ACPI_MMIO_PM_ADDR, EFCH_PM_ACPI_MMIO_PM_SIZE);
 353         if (!addr) {
 354                 dev_err(dev, "Address mapping failed\n");
 355                 ret = -ENOMEM;
 356                 goto out;
 357         }
 358
 359         /*
 360          * EFCH_PM_DECODEEN_WDT_TMREN is dual purpose. This bitfield
 361          * enables sp5100_tco register MMIO space decoding. The bitfield
 362          * also starts the timer operation. Enable if not already enabled.
 363          */
 364         val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
 365         if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
 366                 efch_update_pm_reg8(addr, EFCH_PM_DECODEEN, 0xff,
 367                                     EFCH_PM_DECODEEN_WDT_TMREN);
 368         }
 369
 370         /* Error if the timer could not be enabled */
 371         val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
 372         if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
 373                 dev_err(dev, "Failed to enable the timer\n");
 374                 ret = -EFAULT;
 375                 goto out;
 376         }
 377
 378         mmio_addr = EFCH_PM_WDT_ADDR;
 379
 380         /* Determine alternate MMIO base address */
 381         val = efch_read_pm_reg8(addr, EFCH_PM_ISACONTROL);
 382         if (val & EFCH_PM_ISACONTROL_MMIOEN)
 383                 alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
 384                         EFCH_PM_ACPI_MMIO_WDT_OFFSET;
 385
 386         ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
 387         if (!ret) {
 388                 tco_timer_enable_mmio(addr);
 389                 ret = sp5100_tco_timer_init(tco);
 390         }
 391
 392 out:
 393         if (addr)
 394                 iounmap(addr);
 395
 396         release_resource(res);
 397         kfree(res);
 398
 399         return ret;
 400 }
 401
 402 static int sp5100_tco_setupdevice(struct device *dev,
 403                                   struct watchdog_device *wdd)
 404 {
 405         struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 406         const char *dev_name;
 407         u32 mmio_addr = 0, val;
 408         u32 alt_mmio_addr = 0;
 409         int ret;
 410
 411         if (tco->tco_reg_layout == efch_mmio)
 412                 return sp5100_tco_setupdevice_mmio(dev, wdd);
 413
 414         /* Request the IO ports used by this driver */
 415         if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
 416                                   SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
 417                 dev_err(dev, "I/O address 0x%04x already in use\n",
 418                         SP5100_IO_PM_INDEX_REG);
 419                 return -EBUSY;
 420         }
 421
 422         /*
 423          * Determine type of southbridge chipset.
 424          */
 425         switch (tco->tco_reg_layout) {
 426         case sp5100:
 427                 dev_name = SP5100_DEVNAME;
 428                 mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
 429                                                                 0xfffffff8;
 430
 431                 /*
 432                  * Secondly, find the watchdog timer MMIO address
 433                  * from SBResource_MMIO register.
 434                  */
 435
 436                 /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
 437                 pci_read_config_dword(sp5100_tco_pci,
 438                                       SP5100_SB_RESOURCE_MMIO_BASE,
 439                                       &val);
 440
 441                 /* Verify MMIO is enabled and using bar0 */
 442                 if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
 443                         alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
 444                 break;
 445         case sb800:
 446                 dev_name = SB800_DEVNAME;
 447                 mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
 448                                                                 0xfffffff8;
 449
 450                 /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
 451                 val = sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
 452
 453                 /* Verify MMIO is enabled and using bar0 */
 454                 if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
 455                         alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
 456                 break;
 457         case efch:
 458                 dev_name = SB800_DEVNAME;
 459                 val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
 460                 if (val & EFCH_PM_DECODEEN_WDT_TMREN)
 461                         mmio_addr = EFCH_PM_WDT_ADDR;
 462
 463                 val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
 464                 if (val & EFCH_PM_ISACONTROL_MMIOEN)
 465                         alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
 466                                 EFCH_PM_ACPI_MMIO_WDT_OFFSET;
 467                 break;
 468         default:
 469                 return -ENODEV;
 470         }
 471
 472         ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
 473         if (!ret) {
 474                 /* Setup the watchdog timer */
 475                 tco_timer_enable(tco);
 476                 ret = sp5100_tco_timer_init(tco);
 477         }
 478
 479         release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
 480         return ret;
 481 }
 482
 483 static struct watchdog_info sp5100_tco_wdt_info = {
 484         .identity = "SP5100 TCO timer",
 485         .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
 486 };
 487
 488 static const struct watchdog_ops sp5100_tco_wdt_ops = {
 489         .owner = THIS_MODULE,
 490         .start = tco_timer_start,
 491         .stop = tco_timer_stop,
 492         .ping = tco_timer_ping,
 493         .set_timeout = tco_timer_set_timeout,
 494 };
 495
 496 static int sp5100_tco_probe(struct platform_device *pdev)
 497 {
 498         struct device *dev = &pdev->dev;
 499         struct watchdog_device *wdd;
 500         struct sp5100_tco *tco;
 501         int ret;
 502
 503         tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
 504         if (!tco)
 505                 return -ENOMEM;
 506
 507         tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
 508
 509         wdd = &tco->wdd;
 510         wdd->parent = dev;
 511         wdd->info = &sp5100_tco_wdt_info;
 512         wdd->ops = &sp5100_tco_wdt_ops;
 513         wdd->timeout = WATCHDOG_HEARTBEAT;
 514         wdd->min_timeout = 1;
 515         wdd->max_timeout = 0xffff;
 516
 517         watchdog_init_timeout(wdd, heartbeat, NULL);
 518         watchdog_set_nowayout(wdd, nowayout);
 519         watchdog_stop_on_reboot(wdd);
 520         watchdog_stop_on_unregister(wdd);
 521         watchdog_set_drvdata(wdd, tco);
 522
 523         ret = sp5100_tco_setupdevice(dev, wdd);
 524         if (ret)
 525                 return ret;
 526
 527         ret = devm_watchdog_register_device(dev, wdd);
 528         if (ret)
 529                 return ret;
 530
 531         /* Show module parameters */
 532         dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
 533                  wdd->timeout, nowayout);
 534
 535         return 0;
 536 }
 537
 538 static struct platform_driver sp5100_tco_driver = {
 539         .probe          = sp5100_tco_probe,
 540         .driver         = {
 541                 .name   = TCO_DRIVER_NAME,
 542         },
 543 };
 544
 545 /*
 546  * Data for PCI driver interface
 547  *
 548  * This data only exists for exporting the supported
 549  * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 550  * register a pci_driver, because someone else might
 551  * want to register another driver on the same PCI id.
 552  */
 553 static const struct pci_device_id sp5100_tco_pci_tbl[] = {
 554         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
 555           PCI_ANY_ID, },
 556         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
 557           PCI_ANY_ID, },
 558         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
 559           PCI_ANY_ID, },
 560         { 0, },                 /* End of list */
 561 };
 562 MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
 563
 564 static int __init sp5100_tco_init(void)
 565 {
 566         struct pci_dev *dev = NULL;
 567         int err;
 568
 569         /* Match the PCI device */
 570         for_each_pci_dev(dev) {
 571                 if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
 572                         sp5100_tco_pci = dev;
 573                         break;
 574                 }
 575         }
 576
 577         if (!sp5100_tco_pci)
 578                 return -ENODEV;
 579
 580         pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
 581
 582         err = platform_driver_register(&sp5100_tco_driver);
 583         if (err)
 584                 return err;
 585
 586         sp5100_tco_platform_device =
 587                 platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
 588         if (IS_ERR(sp5100_tco_platform_device)) {
 589                 err = PTR_ERR(sp5100_tco_platform_device);
 590                 goto unreg_platform_driver;
 591         }
 592
 593         return 0;
 594
 595 unreg_platform_driver:
 596         platform_driver_unregister(&sp5100_tco_driver);
 597         return err;
 598 }
 599
 600 static void __exit sp5100_tco_exit(void)
 601 {
 602         platform_device_unregister(sp5100_tco_platform_device);
 603         platform_driver_unregister(&sp5100_tco_driver);
 604 }
 605
 606 module_init(sp5100_tco_init);
 607 module_exit(sp5100_tco_exit);
 608
 609 MODULE_AUTHOR("Priyanka Gupta");
 610 MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
 611 MODULE_LICENSE("GPL");