drivers/watchdog/s3c2410_wdt.c

   1 /* linux/drivers/char/watchdog/s3c2410_wdt.c
   2  *
   3  * Copyright (c) 2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 Watchdog Timer Support
   7  *
   8  * Based on, softdog.c by Alan Cox,
   9  *     (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24 */
  25
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/types.h>
  29 #include <linux/timer.h>
  30 #include <linux/watchdog.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/clk.h>
  34 #include <linux/uaccess.h>
  35 #include <linux/io.h>
  36 #include <linux/cpufreq.h>
  37 #include <linux/slab.h>
  38 #include <linux/err.h>
  39 #include <linux/of.h>
  40 #include <linux/mfd/syscon.h>
  41 #include <linux/regmap.h>
  42 #include <linux/delay.h>
  43
  44 #define S3C2410_WTCON           0x00
  45 #define S3C2410_WTDAT           0x04
  46 #define S3C2410_WTCNT           0x08
  47 #define S3C2410_WTCLRINT        0x0c
  48
  49 #define S3C2410_WTCNT_MAXCNT    0xffff
  50
  51 #define S3C2410_WTCON_RSTEN     (1 << 0)
  52 #define S3C2410_WTCON_INTEN     (1 << 2)
  53 #define S3C2410_WTCON_ENABLE    (1 << 5)
  54
  55 #define S3C2410_WTCON_DIV16     (0 << 3)
  56 #define S3C2410_WTCON_DIV32     (1 << 3)
  57 #define S3C2410_WTCON_DIV64     (2 << 3)
  58 #define S3C2410_WTCON_DIV128    (3 << 3)
  59
  60 #define S3C2410_WTCON_MAXDIV    0x80
  61
  62 #define S3C2410_WTCON_PRESCALE(x)       ((x) << 8)
  63 #define S3C2410_WTCON_PRESCALE_MASK     (0xff << 8)
  64 #define S3C2410_WTCON_PRESCALE_MAX      0xff
  65
  66 #define S3C2410_WATCHDOG_ATBOOT         (0)
  67 #define S3C2410_WATCHDOG_DEFAULT_TIME   (15)
  68
  69 #define EXYNOS5_RST_STAT_REG_OFFSET             0x0404
  70 #define EXYNOS5_WDT_DISABLE_REG_OFFSET          0x0408
  71 #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET       0x040c
  72 #define QUIRK_HAS_PMU_CONFIG                    (1 << 0)
  73 #define QUIRK_HAS_RST_STAT                      (1 << 1)
  74 #define QUIRK_HAS_WTCLRINT_REG                  (1 << 2)
  75
  76 /* These quirks require that we have a PMU register map */
  77 #define QUIRKS_HAVE_PMUREG                      (QUIRK_HAS_PMU_CONFIG | \
  78                                                  QUIRK_HAS_RST_STAT)
  79
  80 static bool nowayout    = WATCHDOG_NOWAYOUT;
  81 static int tmr_margin;
  82 static int tmr_atboot   = S3C2410_WATCHDOG_ATBOOT;
  83 static int soft_noboot;
  84
  85 module_param(tmr_margin,  int, 0);
  86 module_param(tmr_atboot,  int, 0);
  87 module_param(nowayout,   bool, 0);
  88 module_param(soft_noboot, int, 0);
  89
  90 MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
  91                 __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  92 MODULE_PARM_DESC(tmr_atboot,
  93                 "Watchdog is started at boot time if set to 1, default="
  94                         __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT));
  95 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  96                         __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  97 MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  98                         "0 to reboot (default 0)");
  99
 100 /**
 101  * struct s3c2410_wdt_variant - Per-variant config data
 102  *
 103  * @disable_reg: Offset in pmureg for the register that disables the watchdog
 104  * timer reset functionality.
 105  * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
 106  * timer reset functionality.
 107  * @mask_bit: Bit number for the watchdog timer in the disable register and the
 108  * mask reset register.
 109  * @rst_stat_reg: Offset in pmureg for the register that has the reset status.
 110  * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
 111  * reset.
 112  * @quirks: A bitfield of quirks.
 113  */
 114
 115 struct s3c2410_wdt_variant {
 116         int disable_reg;
 117         int mask_reset_reg;
 118         int mask_bit;
 119         int rst_stat_reg;
 120         int rst_stat_bit;
 121         u32 quirks;
 122 };
 123
 124 struct s3c2410_wdt {
 125         struct device           *dev;
 126         struct clk              *clock;
 127         void __iomem            *reg_base;
 128         unsigned int            count;
 129         spinlock_t              lock;
 130         unsigned long           wtcon_save;
 131         unsigned long           wtdat_save;
 132         struct watchdog_device  wdt_device;
 133         struct notifier_block   freq_transition;
 134         struct s3c2410_wdt_variant *drv_data;
 135         struct regmap *pmureg;
 136 };
 137
 138 static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
 139         .quirks = 0
 140 };
 141
 142 #ifdef CONFIG_OF
 143 static const struct s3c2410_wdt_variant drv_data_s3c6410 = {
 144         .quirks = QUIRK_HAS_WTCLRINT_REG,
 145 };
 146
 147 static const struct s3c2410_wdt_variant drv_data_exynos5250  = {
 148         .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
 149         .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
 150         .mask_bit = 20,
 151         .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
 152         .rst_stat_bit = 20,
 153         .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
 154                   | QUIRK_HAS_WTCLRINT_REG,
 155 };
 156
 157 static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
 158         .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
 159         .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
 160         .mask_bit = 0,
 161         .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
 162         .rst_stat_bit = 9,
 163         .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
 164                   | QUIRK_HAS_WTCLRINT_REG,
 165 };
 166
 167 static const struct s3c2410_wdt_variant drv_data_exynos7 = {
 168         .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
 169         .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
 170         .mask_bit = 23,
 171         .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
 172         .rst_stat_bit = 23,     /* A57 WDTRESET */
 173         .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
 174                   | QUIRK_HAS_WTCLRINT_REG,
 175 };
 176
 177 static const struct of_device_id s3c2410_wdt_match[] = {
 178         { .compatible = "samsung,s3c2410-wdt",
 179           .data = &drv_data_s3c2410 },
 180         { .compatible = "samsung,s3c6410-wdt",
 181           .data = &drv_data_s3c6410 },
 182         { .compatible = "samsung,exynos5250-wdt",
 183           .data = &drv_data_exynos5250 },
 184         { .compatible = "samsung,exynos5420-wdt",
 185           .data = &drv_data_exynos5420 },
 186         { .compatible = "samsung,exynos7-wdt",
 187           .data = &drv_data_exynos7 },
 188         {},
 189 };
 190 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
 191 #endif
 192
 193 static const struct platform_device_id s3c2410_wdt_ids[] = {
 194         {
 195                 .name = "s3c2410-wdt",
 196                 .driver_data = (unsigned long)&drv_data_s3c2410,
 197         },
 198         {}
 199 };
 200 MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
 201
 202 /* functions */
 203
 204 static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock)
 205 {
 206         unsigned long freq = clk_get_rate(clock);
 207
 208         return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1)
 209                                        / S3C2410_WTCON_MAXDIV);
 210 }
 211
 212 static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
 213 {
 214         return container_of(nb, struct s3c2410_wdt, freq_transition);
 215 }
 216
 217 static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
 218 {
 219         int ret;
 220         u32 mask_val = 1 << wdt->drv_data->mask_bit;
 221         u32 val = 0;
 222
 223         /* No need to do anything if no PMU CONFIG needed */
 224         if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
 225                 return 0;
 226
 227         if (mask)
 228                 val = mask_val;
 229
 230         ret = regmap_update_bits(wdt->pmureg,
 231                         wdt->drv_data->disable_reg,
 232                         mask_val, val);
 233         if (ret < 0)
 234                 goto error;
 235
 236         ret = regmap_update_bits(wdt->pmureg,
 237                         wdt->drv_data->mask_reset_reg,
 238                         mask_val, val);
 239  error:
 240         if (ret < 0)
 241                 dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
 242
 243         return ret;
 244 }
 245
 246 static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
 247 {
 248         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 249
 250         spin_lock(&wdt->lock);
 251         writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
 252         spin_unlock(&wdt->lock);
 253
 254         return 0;
 255 }
 256
 257 static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
 258 {
 259         unsigned long wtcon;
 260
 261         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 262         wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
 263         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
 264 }
 265
 266 static int s3c2410wdt_stop(struct watchdog_device *wdd)
 267 {
 268         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 269
 270         spin_lock(&wdt->lock);
 271         __s3c2410wdt_stop(wdt);
 272         spin_unlock(&wdt->lock);
 273
 274         return 0;
 275 }
 276
 277 static int s3c2410wdt_start(struct watchdog_device *wdd)
 278 {
 279         unsigned long wtcon;
 280         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 281
 282         spin_lock(&wdt->lock);
 283
 284         __s3c2410wdt_stop(wdt);
 285
 286         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 287         wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
 288
 289         if (soft_noboot) {
 290                 wtcon |= S3C2410_WTCON_INTEN;
 291                 wtcon &= ~S3C2410_WTCON_RSTEN;
 292         } else {
 293                 wtcon &= ~S3C2410_WTCON_INTEN;
 294                 wtcon |= S3C2410_WTCON_RSTEN;
 295         }
 296
 297         dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
 298                 wdt->count, wtcon);
 299
 300         writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
 301         writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
 302         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
 303         spin_unlock(&wdt->lock);
 304
 305         return 0;
 306 }
 307
 308 static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
 309 {
 310         return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
 311 }
 312
 313 static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
 314 {
 315         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 316         unsigned long freq = clk_get_rate(wdt->clock);
 317         unsigned int count;
 318         unsigned int divisor = 1;
 319         unsigned long wtcon;
 320
 321         if (timeout < 1)
 322                 return -EINVAL;
 323
 324         freq = DIV_ROUND_UP(freq, 128);
 325         count = timeout * freq;
 326
 327         dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
 328                 count, timeout, freq);
 329
 330         /* if the count is bigger than the watchdog register,
 331            then work out what we need to do (and if) we can
 332            actually make this value
 333         */
 334
 335         if (count >= 0x10000) {
 336                 divisor = DIV_ROUND_UP(count, 0xffff);
 337
 338                 if (divisor > 0x100) {
 339                         dev_err(wdt->dev, "timeout %d too big\n", timeout);
 340                         return -EINVAL;
 341                 }
 342         }
 343
 344         dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
 345                 timeout, divisor, count, DIV_ROUND_UP(count, divisor));
 346
 347         count = DIV_ROUND_UP(count, divisor);
 348         wdt->count = count;
 349
 350         /* update the pre-scaler */
 351         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 352         wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
 353         wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
 354
 355         writel(count, wdt->reg_base + S3C2410_WTDAT);
 356         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
 357
 358         wdd->timeout = (count * divisor) / freq;
 359
 360         return 0;
 361 }
 362
 363 static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
 364                               void *data)
 365 {
 366         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 367         void __iomem *wdt_base = wdt->reg_base;
 368
 369         /* disable watchdog, to be safe  */
 370         writel(0, wdt_base + S3C2410_WTCON);
 371
 372         /* put initial values into count and data */
 373         writel(0x80, wdt_base + S3C2410_WTCNT);
 374         writel(0x80, wdt_base + S3C2410_WTDAT);
 375
 376         /* set the watchdog to go and reset... */
 377         writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
 378                 S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
 379                 wdt_base + S3C2410_WTCON);
 380
 381         /* wait for reset to assert... */
 382         mdelay(500);
 383
 384         return 0;
 385 }
 386
 387 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
 388
 389 static const struct watchdog_info s3c2410_wdt_ident = {
 390         .options          =     OPTIONS,
 391         .firmware_version =     0,
 392         .identity         =     "S3C2410 Watchdog",
 393 };
 394
 395 static const struct watchdog_ops s3c2410wdt_ops = {
 396         .owner = THIS_MODULE,
 397         .start = s3c2410wdt_start,
 398         .stop = s3c2410wdt_stop,
 399         .ping = s3c2410wdt_keepalive,
 400         .set_timeout = s3c2410wdt_set_heartbeat,
 401         .restart = s3c2410wdt_restart,
 402 };
 403
 404 static struct watchdog_device s3c2410_wdd = {
 405         .info = &s3c2410_wdt_ident,
 406         .ops = &s3c2410wdt_ops,
 407         .timeout = S3C2410_WATCHDOG_DEFAULT_TIME,
 408 };
 409
 410 /* interrupt handler code */
 411
 412 static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
 413 {
 414         struct s3c2410_wdt *wdt = platform_get_drvdata(param);
 415
 416         dev_info(wdt->dev, "watchdog timer expired (irq)\n");
 417
 418         s3c2410wdt_keepalive(&wdt->wdt_device);
 419
 420         if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
 421                 writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
 422
 423         return IRQ_HANDLED;
 424 }
 425
 426 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 427
 428 static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
 429                                           unsigned long val, void *data)
 430 {
 431         int ret;
 432         struct s3c2410_wdt *wdt = freq_to_wdt(nb);
 433
 434         if (!s3c2410wdt_is_running(wdt))
 435                 goto done;
 436
 437         if (val == CPUFREQ_PRECHANGE) {
 438                 /* To ensure that over the change we don't cause the
 439                  * watchdog to trigger, we perform an keep-alive if
 440                  * the watchdog is running.
 441                  */
 442
 443                 s3c2410wdt_keepalive(&wdt->wdt_device);
 444         } else if (val == CPUFREQ_POSTCHANGE) {
 445                 s3c2410wdt_stop(&wdt->wdt_device);
 446
 447                 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
 448                                                 wdt->wdt_device.timeout);
 449
 450                 if (ret >= 0)
 451                         s3c2410wdt_start(&wdt->wdt_device);
 452                 else
 453                         goto err;
 454         }
 455
 456 done:
 457         return 0;
 458
 459  err:
 460         dev_err(wdt->dev, "cannot set new value for timeout %d\n",
 461                                 wdt->wdt_device.timeout);
 462         return ret;
 463 }
 464
 465 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
 466 {
 467         wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
 468
 469         return cpufreq_register_notifier(&wdt->freq_transition,
 470                                          CPUFREQ_TRANSITION_NOTIFIER);
 471 }
 472
 473 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
 474 {
 475         wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
 476
 477         cpufreq_unregister_notifier(&wdt->freq_transition,
 478                                     CPUFREQ_TRANSITION_NOTIFIER);
 479 }
 480
 481 #else
 482
 483 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
 484 {
 485         return 0;
 486 }
 487
 488 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
 489 {
 490 }
 491 #endif
 492
 493 static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
 494 {
 495         unsigned int rst_stat;
 496         int ret;
 497
 498         if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
 499                 return 0;
 500
 501         ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
 502         if (ret)
 503                 dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
 504         else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
 505                 return WDIOF_CARDRESET;
 506
 507         return 0;
 508 }
 509
 510 static inline struct s3c2410_wdt_variant *
 511 s3c2410_get_wdt_drv_data(struct platform_device *pdev)
 512 {
 513         if (pdev->dev.of_node) {
 514                 const struct of_device_id *match;
 515                 match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node);
 516                 return (struct s3c2410_wdt_variant *)match->data;
 517         } else {
 518                 return (struct s3c2410_wdt_variant *)
 519                         platform_get_device_id(pdev)->driver_data;
 520         }
 521 }
 522
 523 static int s3c2410wdt_probe(struct platform_device *pdev)
 524 {
 525         struct device *dev;
 526         struct s3c2410_wdt *wdt;
 527         struct resource *wdt_mem;
 528         struct resource *wdt_irq;
 529         unsigned int wtcon;
 530         int started = 0;
 531         int ret;
 532
 533         dev = &pdev->dev;
 534
 535         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 536         if (!wdt)
 537                 return -ENOMEM;
 538
 539         wdt->dev = &pdev->dev;
 540         spin_lock_init(&wdt->lock);
 541         wdt->wdt_device = s3c2410_wdd;
 542
 543         wdt->drv_data = s3c2410_get_wdt_drv_data(pdev);
 544         if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
 545                 wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
 546                                                 "samsung,syscon-phandle");
 547                 if (IS_ERR(wdt->pmureg)) {
 548                         dev_err(dev, "syscon regmap lookup failed.\n");
 549                         return PTR_ERR(wdt->pmureg);
 550                 }
 551         }
 552
 553         wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 554         if (wdt_irq == NULL) {
 555                 dev_err(dev, "no irq resource specified\n");
 556                 ret = -ENOENT;
 557                 goto err;
 558         }
 559
 560         /* get the memory region for the watchdog timer */
 561         wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 562         wdt->reg_base = devm_ioremap_resource(dev, wdt_mem);
 563         if (IS_ERR(wdt->reg_base)) {
 564                 ret = PTR_ERR(wdt->reg_base);
 565                 goto err;
 566         }
 567
 568         wdt->clock = devm_clk_get(dev, "watchdog");
 569         if (IS_ERR(wdt->clock)) {
 570                 dev_err(dev, "failed to find watchdog clock source\n");
 571                 ret = PTR_ERR(wdt->clock);
 572                 goto err;
 573         }
 574
 575         ret = clk_prepare_enable(wdt->clock);
 576         if (ret < 0) {
 577                 dev_err(dev, "failed to enable clock\n");
 578                 return ret;
 579         }
 580
 581         wdt->wdt_device.min_timeout = 1;
 582         wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock);
 583
 584         ret = s3c2410wdt_cpufreq_register(wdt);
 585         if (ret < 0) {
 586                 dev_err(dev, "failed to register cpufreq\n");
 587                 goto err_clk;
 588         }
 589
 590         watchdog_set_drvdata(&wdt->wdt_device, wdt);
 591
 592         /* see if we can actually set the requested timer margin, and if
 593          * not, try the default value */
 594
 595         watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev);
 596         ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
 597                                         wdt->wdt_device.timeout);
 598         if (ret) {
 599                 started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
 600                                         S3C2410_WATCHDOG_DEFAULT_TIME);
 601
 602                 if (started == 0)
 603                         dev_info(dev,
 604                            "tmr_margin value out of range, default %d used\n",
 605                                S3C2410_WATCHDOG_DEFAULT_TIME);
 606                 else
 607                         dev_info(dev, "default timer value is out of range, "
 608                                                         "cannot start\n");
 609         }
 610
 611         ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
 612                                 pdev->name, pdev);
 613         if (ret != 0) {
 614                 dev_err(dev, "failed to install irq (%d)\n", ret);
 615                 goto err_cpufreq;
 616         }
 617
 618         watchdog_set_nowayout(&wdt->wdt_device, nowayout);
 619         watchdog_set_restart_priority(&wdt->wdt_device, 128);
 620
 621         wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
 622         wdt->wdt_device.parent = &pdev->dev;
 623
 624         ret = watchdog_register_device(&wdt->wdt_device);
 625         if (ret) {
 626                 dev_err(dev, "cannot register watchdog (%d)\n", ret);
 627                 goto err_cpufreq;
 628         }
 629
 630         ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
 631         if (ret < 0)
 632                 goto err_unregister;
 633
 634         if (tmr_atboot && started == 0) {
 635                 dev_info(dev, "starting watchdog timer\n");
 636                 s3c2410wdt_start(&wdt->wdt_device);
 637         } else if (!tmr_atboot) {
 638                 /* if we're not enabling the watchdog, then ensure it is
 639                  * disabled if it has been left running from the bootloader
 640                  * or other source */
 641
 642                 s3c2410wdt_stop(&wdt->wdt_device);
 643         }
 644
 645         platform_set_drvdata(pdev, wdt);
 646
 647         /* print out a statement of readiness */
 648
 649         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 650
 651         dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
 652                  (wtcon & S3C2410_WTCON_ENABLE) ?  "" : "in",
 653                  (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
 654                  (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
 655
 656         return 0;
 657
 658  err_unregister:
 659         watchdog_unregister_device(&wdt->wdt_device);
 660
 661  err_cpufreq:
 662         s3c2410wdt_cpufreq_deregister(wdt);
 663
 664  err_clk:
 665         clk_disable_unprepare(wdt->clock);
 666
 667  err:
 668         return ret;
 669 }
 670
 671 static int s3c2410wdt_remove(struct platform_device *dev)
 672 {
 673         int ret;
 674         struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
 675
 676         ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
 677         if (ret < 0)
 678                 return ret;
 679
 680         watchdog_unregister_device(&wdt->wdt_device);
 681
 682         s3c2410wdt_cpufreq_deregister(wdt);
 683
 684         clk_disable_unprepare(wdt->clock);
 685
 686         return 0;
 687 }
 688
 689 static void s3c2410wdt_shutdown(struct platform_device *dev)
 690 {
 691         struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
 692
 693         s3c2410wdt_mask_and_disable_reset(wdt, true);
 694
 695         s3c2410wdt_stop(&wdt->wdt_device);
 696 }
 697
 698 #ifdef CONFIG_PM_SLEEP
 699
 700 static int s3c2410wdt_suspend(struct device *dev)
 701 {
 702         int ret;
 703         struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
 704
 705         /* Save watchdog state, and turn it off. */
 706         wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
 707         wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
 708
 709         ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
 710         if (ret < 0)
 711                 return ret;
 712
 713         /* Note that WTCNT doesn't need to be saved. */
 714         s3c2410wdt_stop(&wdt->wdt_device);
 715
 716         return 0;
 717 }
 718
 719 static int s3c2410wdt_resume(struct device *dev)
 720 {
 721         int ret;
 722         struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
 723
 724         /* Restore watchdog state. */
 725         writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
 726         writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
 727         writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
 728
 729         ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
 730         if (ret < 0)
 731                 return ret;
 732
 733         dev_info(dev, "watchdog %sabled\n",
 734                 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
 735
 736         return 0;
 737 }
 738 #endif
 739
 740 static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
 741                         s3c2410wdt_resume);
 742
 743 static struct platform_driver s3c2410wdt_driver = {
 744         .probe          = s3c2410wdt_probe,
 745         .remove         = s3c2410wdt_remove,
 746         .shutdown       = s3c2410wdt_shutdown,
 747         .id_table       = s3c2410_wdt_ids,
 748         .driver         = {
 749                 .name   = "s3c2410-wdt",
 750                 .pm     = &s3c2410wdt_pm_ops,
 751                 .of_match_table = of_match_ptr(s3c2410_wdt_match),
 752         },
 753 };
 754
 755 module_platform_driver(s3c2410wdt_driver);
 756
 757 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
 758               "Dimitry Andric <dimitry.andric@tomtom.com>");
 759 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
 760 MODULE_LICENSE("GPL");