1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Marvell International Ltd.
5 * https://spdx.org/licenses
13 #include <linux/bitfield.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define CORE0_WDOG_OFFSET 0x40000
18 #define CORE0_POKE_OFFSET 0x50000
19 #define CORE0_POKE_OFFSET_MASK 0xfffffULL
21 #define WDOG_MODE GENMASK_ULL(1, 0)
22 #define WDOG_LEN GENMASK_ULL(19, 4)
23 #define WDOG_CNT GENMASK_ULL(43, 20)
30 static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
32 struct octeontx_wdt *priv = dev_get_priv(dev);
36 clk_rate = clk_get_rate(&priv->clk);
37 if (IS_ERR_VALUE(clk_rate))
40 /* Watchdog counts in 1024 cycle steps */
41 tout_wdog = (clk_rate * timeout_ms / 1000) >> 10;
44 * We can only specify the upper 16 bits of a 24 bit value.
47 tout_wdog = (tout_wdog + 0xff) >> 8;
49 /* If the timeout overflows the hardware limit, set max */
50 if (tout_wdog >= 0x10000)
53 val = FIELD_PREP(WDOG_MODE, 0x3) |
54 FIELD_PREP(WDOG_LEN, tout_wdog) |
55 FIELD_PREP(WDOG_CNT, tout_wdog << 8);
56 writeq(val, priv->reg + CORE0_WDOG_OFFSET);
61 static int octeontx_wdt_stop(struct udevice *dev)
63 struct octeontx_wdt *priv = dev_get_priv(dev);
65 writeq(0, priv->reg + CORE0_WDOG_OFFSET);
70 static int octeontx_wdt_expire_now(struct udevice *dev, ulong flags)
72 octeontx_wdt_stop(dev);
74 /* Start with 100ms timeout to expire immediately */
75 octeontx_wdt_start(dev, 100, flags);
80 static int octeontx_wdt_reset(struct udevice *dev)
82 struct octeontx_wdt *priv = dev_get_priv(dev);
84 writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET);
89 static int octeontx_wdt_remove(struct udevice *dev)
91 octeontx_wdt_stop(dev);
96 static int octeontx_wdt_probe(struct udevice *dev)
98 struct octeontx_wdt *priv = dev_get_priv(dev);
101 priv->reg = dev_remap_addr(dev);
106 * Save base register address in reg masking lower 20 bits
107 * as 0xa0000 appears when extracted from the DT
109 priv->reg = (void __iomem *)(((u64)priv->reg &
110 ~CORE0_POKE_OFFSET_MASK));
112 ret = clk_get_by_index(dev, 0, &priv->clk);
116 ret = clk_enable(&priv->clk);
123 static const struct wdt_ops octeontx_wdt_ops = {
124 .reset = octeontx_wdt_reset,
125 .start = octeontx_wdt_start,
126 .stop = octeontx_wdt_stop,
127 .expire_now = octeontx_wdt_expire_now,
130 static const struct udevice_id octeontx_wdt_ids[] = {
131 { .compatible = "arm,sbsa-gwdt" },
135 U_BOOT_DRIVER(wdt_octeontx) = {
136 .name = "wdt_octeontx",
138 .of_match = octeontx_wdt_ids,
139 .ops = &octeontx_wdt_ops,
140 .priv_auto = sizeof(struct octeontx_wdt),
141 .probe = octeontx_wdt_probe,
142 .remove = octeontx_wdt_remove,
143 .flags = DM_FLAG_OS_PREPARE,