1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018 Nuvoton Technology corporation.
3 // Copyright (c) 2018 IBM Corp.
5 #include <linux/bitops.h>
7 #include <linux/delay.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_irq.h>
12 #include <linux/platform_device.h>
13 #include <linux/slab.h>
14 #include <linux/watchdog.h>
16 #define NPCM_WTCR 0x1C
18 #define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */
19 #define NPCM_WTE BIT(7) /* Enable */
20 #define NPCM_WTIE BIT(6) /* Enable irq */
21 #define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */
22 #define NPCM_WTIF BIT(3) /* Interrupt flag*/
23 #define NPCM_WTRF BIT(2) /* Reset flag */
24 #define NPCM_WTRE BIT(1) /* Reset enable */
25 #define NPCM_WTR BIT(0) /* Reset counter */
30 * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400
31 * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410
32 * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800
33 * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420
34 * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810
35 * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430
36 * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820
37 * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00
38 * 85600 msec: WTCLK=10 WTIS=11 VAL= 0x830
39 * 172000 msec: WTCLK=11 WTIS=01 VAL= 0xC10
40 * 687000 msec: WTCLK=11 WTIS=10 VAL= 0xC20
41 * 2750000 msec: WTCLK=11 WTIS=11 VAL= 0xC30
45 struct watchdog_device wdd;
50 static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd)
52 return container_of(wdd, struct npcm_wdt, wdd);
55 static int npcm_wdt_ping(struct watchdog_device *wdd)
57 struct npcm_wdt *wdt = to_npcm_wdt(wdd);
60 val = readl(wdt->reg);
61 writel(val | NPCM_WTR, wdt->reg);
66 static int npcm_wdt_start(struct watchdog_device *wdd)
68 struct npcm_wdt *wdt = to_npcm_wdt(wdd);
72 clk_prepare_enable(wdt->clk);
76 else if (wdd->timeout < 3)
78 else if (wdd->timeout < 6)
80 else if (wdd->timeout < 11)
82 else if (wdd->timeout < 22)
84 else if (wdd->timeout < 44)
86 else if (wdd->timeout < 87)
88 else if (wdd->timeout < 173)
90 else if (wdd->timeout < 688)
95 val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE;
97 writel(val, wdt->reg);
102 static int npcm_wdt_stop(struct watchdog_device *wdd)
104 struct npcm_wdt *wdt = to_npcm_wdt(wdd);
109 clk_disable_unprepare(wdt->clk);
114 static int npcm_wdt_set_timeout(struct watchdog_device *wdd,
115 unsigned int timeout)
119 else if (timeout < 3)
121 else if (timeout < 6)
123 else if (timeout < 11)
125 else if (timeout < 22)
127 else if (timeout < 44)
129 else if (timeout < 87)
131 else if (timeout < 173)
133 else if (timeout < 688)
138 if (watchdog_active(wdd))
144 static irqreturn_t npcm_wdt_interrupt(int irq, void *data)
146 struct npcm_wdt *wdt = data;
148 watchdog_notify_pretimeout(&wdt->wdd);
153 static int npcm_wdt_restart(struct watchdog_device *wdd,
154 unsigned long action, void *data)
156 struct npcm_wdt *wdt = to_npcm_wdt(wdd);
158 /* For reset, we start the WDT clock and leave it running. */
160 clk_prepare_enable(wdt->clk);
162 writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg);
168 static bool npcm_is_running(struct watchdog_device *wdd)
170 struct npcm_wdt *wdt = to_npcm_wdt(wdd);
172 return readl(wdt->reg) & NPCM_WTE;
175 static const struct watchdog_info npcm_wdt_info = {
176 .identity = KBUILD_MODNAME,
177 .options = WDIOF_SETTIMEOUT
178 | WDIOF_KEEPALIVEPING
182 static const struct watchdog_ops npcm_wdt_ops = {
183 .owner = THIS_MODULE,
184 .start = npcm_wdt_start,
185 .stop = npcm_wdt_stop,
186 .ping = npcm_wdt_ping,
187 .set_timeout = npcm_wdt_set_timeout,
188 .restart = npcm_wdt_restart,
191 static int npcm_wdt_probe(struct platform_device *pdev)
193 struct device *dev = &pdev->dev;
194 struct npcm_wdt *wdt;
198 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
202 wdt->reg = devm_platform_ioremap_resource(pdev, 0);
203 if (IS_ERR(wdt->reg))
204 return PTR_ERR(wdt->reg);
206 wdt->clk = devm_clk_get_optional(&pdev->dev, NULL);
207 if (IS_ERR(wdt->clk))
208 return PTR_ERR(wdt->clk);
210 irq = platform_get_irq(pdev, 0);
214 wdt->wdd.info = &npcm_wdt_info;
215 wdt->wdd.ops = &npcm_wdt_ops;
216 wdt->wdd.min_timeout = 1;
217 wdt->wdd.max_timeout = 2750;
218 wdt->wdd.parent = dev;
220 wdt->wdd.timeout = 86;
221 watchdog_init_timeout(&wdt->wdd, 0, dev);
223 /* Ensure timeout is able to be represented by the hardware */
224 npcm_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
226 if (npcm_is_running(&wdt->wdd)) {
227 /* Restart with the default or device-tree specified timeout */
228 npcm_wdt_start(&wdt->wdd);
229 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
232 ret = devm_request_irq(dev, irq, npcm_wdt_interrupt, 0, "watchdog",
237 ret = devm_watchdog_register_device(dev, &wdt->wdd);
241 dev_info(dev, "NPCM watchdog driver enabled\n");
247 static const struct of_device_id npcm_wdt_match[] = {
248 {.compatible = "nuvoton,wpcm450-wdt"},
249 {.compatible = "nuvoton,npcm750-wdt"},
252 MODULE_DEVICE_TABLE(of, npcm_wdt_match);
255 static struct platform_driver npcm_wdt_driver = {
256 .probe = npcm_wdt_probe,
259 .of_match_table = of_match_ptr(npcm_wdt_match),
262 module_platform_driver(npcm_wdt_driver);
264 MODULE_AUTHOR("Joel Stanley");
265 MODULE_DESCRIPTION("Watchdog driver for NPCM");
266 MODULE_LICENSE("GPL v2");