1 // SPDX-License-Identifier: GPL-2.0
3 * Watchdog driver for MediaTek SoCs
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
14 #define MTK_WDT_MODE 0x00
15 #define MTK_WDT_LENGTH 0x04
16 #define MTK_WDT_RESTART 0x08
17 #define MTK_WDT_STATUS 0x0c
18 #define MTK_WDT_INTERVAL 0x10
19 #define MTK_WDT_SWRST 0x14
20 #define MTK_WDT_REQ_MODE 0x30
21 #define MTK_WDT_DEBUG_CTL 0x40
23 #define WDT_MODE_KEY (0x22 << 24)
24 #define WDT_MODE_EN BIT(0)
25 #define WDT_MODE_EXTPOL BIT(1)
26 #define WDT_MODE_EXTEN BIT(2)
27 #define WDT_MODE_IRQ_EN BIT(3)
28 #define WDT_MODE_DUAL_EN BIT(6)
30 #define WDT_LENGTH_KEY 0x8
31 #define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
33 #define WDT_RESTART_KEY 0x1971
34 #define WDT_SWRST_KEY 0x1209
40 static int mtk_wdt_reset(struct udevice *dev)
42 struct mtk_wdt_priv *priv = dev_get_priv(dev);
44 /* Reload watchdog duration */
45 writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
50 static int mtk_wdt_stop(struct udevice *dev)
52 struct mtk_wdt_priv *priv = dev_get_priv(dev);
54 clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
59 static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
61 struct mtk_wdt_priv *priv = dev_get_priv(dev);
63 /* Kick watchdog to prevent counter == 0 */
64 writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
67 writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
73 static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout)
75 struct mtk_wdt_priv *priv = dev_get_priv(dev);
78 * One bit is the value of 512 ticks
79 * The clock has 32 KHz
81 timeout = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
82 writel(timeout, priv->base + MTK_WDT_LENGTH);
87 static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
89 struct mtk_wdt_priv *priv = dev_get_priv(dev);
91 mtk_wdt_set_timeout(dev, timeout);
93 /* Enable watchdog reset signal */
94 setbits_le32(priv->base + MTK_WDT_MODE,
95 WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
100 static int mtk_wdt_probe(struct udevice *dev)
102 struct mtk_wdt_priv *priv = dev_get_priv(dev);
104 priv->base = dev_read_addr_ptr(dev);
109 clrsetbits_le32(priv->base + MTK_WDT_MODE,
110 WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
112 return mtk_wdt_stop(dev);
115 static const struct wdt_ops mtk_wdt_ops = {
116 .start = mtk_wdt_start,
117 .reset = mtk_wdt_reset,
118 .stop = mtk_wdt_stop,
119 .expire_now = mtk_wdt_expire_now,
122 static const struct udevice_id mtk_wdt_ids[] = {
123 { .compatible = "mediatek,wdt"},
127 U_BOOT_DRIVER(mtk_wdt) = {
130 .of_match = mtk_wdt_ids,
131 .priv_auto_alloc_size = sizeof(struct mtk_wdt_priv),
132 .probe = mtk_wdt_probe,
134 .flags = DM_FLAG_PRE_RELOC,