1 // SPDX-License-Identifier: GPL-2.0+
3 * Ralink / Mediatek RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
5 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
7 * Based on the Linux driver version which is:
8 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
15 #include <asm/global_data.h>
16 #include <linux/bitops.h>
19 DECLARE_GLOBAL_DATA_PTR;
25 #define TIMER_REG_TMRSTAT 0x00
26 #define TIMER_REG_TMR1CTL 0x20
27 #define TIMER_REG_TMR1LOAD 0x24
29 #define TMR1CTL_ENABLE BIT(7)
30 #define TMR1CTL_RESTART BIT(9)
31 #define TMR1CTL_PRESCALE_SHIFT 16
33 static int mt762x_wdt_ping(struct mt762x_wdt *priv)
35 writel(TMR1CTL_RESTART, priv->regs + TIMER_REG_TMRSTAT);
40 static int mt762x_wdt_start(struct udevice *dev, u64 ms, ulong flags)
42 struct mt762x_wdt *priv = dev_get_priv(dev);
44 /* set the prescaler to 1ms == 1000us */
45 writel(1000 << TMR1CTL_PRESCALE_SHIFT, priv->regs + TIMER_REG_TMR1CTL);
46 writel(ms, priv->regs + TIMER_REG_TMR1LOAD);
48 setbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE);
53 static int mt762x_wdt_stop(struct udevice *dev)
55 struct mt762x_wdt *priv = dev_get_priv(dev);
57 mt762x_wdt_ping(priv);
59 clrbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE);
64 static int mt762x_wdt_reset(struct udevice *dev)
66 struct mt762x_wdt *priv = dev_get_priv(dev);
68 mt762x_wdt_ping(priv);
73 static int mt762x_wdt_probe(struct udevice *dev)
75 struct mt762x_wdt *priv = dev_get_priv(dev);
77 priv->regs = dev_remap_addr(dev);
86 static const struct wdt_ops mt762x_wdt_ops = {
87 .start = mt762x_wdt_start,
88 .reset = mt762x_wdt_reset,
89 .stop = mt762x_wdt_stop,
92 static const struct udevice_id mt762x_wdt_ids[] = {
93 { .compatible = "mediatek,mt7621-wdt" },
97 U_BOOT_DRIVER(mt762x_wdt) = {
100 .of_match = mt762x_wdt_ids,
101 .probe = mt762x_wdt_probe,
102 .priv_auto = sizeof(struct mt762x_wdt),
103 .ops = &mt762x_wdt_ops,