1 // SPDX-License-Identifier: GPL-2.0+
3 * Ralink / Mediatek RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
5 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
7 * Based on the Linux driver version which is:
8 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
15 #include <linux/bitops.h>
18 DECLARE_GLOBAL_DATA_PTR;
24 #define TIMER_REG_TMRSTAT 0x00
25 #define TIMER_REG_TMR1CTL 0x20
26 #define TIMER_REG_TMR1LOAD 0x24
28 #define TMR1CTL_ENABLE BIT(7)
29 #define TMR1CTL_RESTART BIT(9)
30 #define TMR1CTL_PRESCALE_SHIFT 16
32 static int mt762x_wdt_ping(struct mt762x_wdt *priv)
34 writel(TMR1CTL_RESTART, priv->regs + TIMER_REG_TMRSTAT);
39 static int mt762x_wdt_start(struct udevice *dev, u64 ms, ulong flags)
41 struct mt762x_wdt *priv = dev_get_priv(dev);
43 /* set the prescaler to 1ms == 1000us */
44 writel(1000 << TMR1CTL_PRESCALE_SHIFT, priv->regs + TIMER_REG_TMR1CTL);
45 writel(ms, priv->regs + TIMER_REG_TMR1LOAD);
47 setbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE);
52 static int mt762x_wdt_stop(struct udevice *dev)
54 struct mt762x_wdt *priv = dev_get_priv(dev);
56 mt762x_wdt_ping(priv);
58 clrbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE);
63 static int mt762x_wdt_reset(struct udevice *dev)
65 struct mt762x_wdt *priv = dev_get_priv(dev);
67 mt762x_wdt_ping(priv);
72 static int mt762x_wdt_probe(struct udevice *dev)
74 struct mt762x_wdt *priv = dev_get_priv(dev);
76 priv->regs = dev_remap_addr(dev);
85 static const struct wdt_ops mt762x_wdt_ops = {
86 .start = mt762x_wdt_start,
87 .reset = mt762x_wdt_reset,
88 .stop = mt762x_wdt_stop,
91 static const struct udevice_id mt762x_wdt_ids[] = {
92 { .compatible = "mediatek,mt7621-wdt" },
96 U_BOOT_DRIVER(mt762x_wdt) = {
99 .of_match = mt762x_wdt_ids,
100 .probe = mt762x_wdt_probe,
101 .priv_auto_alloc_size = sizeof(struct mt762x_wdt),
102 .ops = &mt762x_wdt_ops,