1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 MediaTek Inc.
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
7 * Watchdog timer for MT7620 and earlier SoCs
14 #include <linux/bitops.h>
22 #define TIMER_FREQ 40000000
23 #define TIMER_MASK 0xffff
24 #define TIMER_PRESCALE 65536
26 #define TIMER_LOAD 0x00
27 #define TIMER_CTL 0x08
29 #define TIMER_ENABLE BIT(7)
30 #define TIMER_MODE_SHIFT 4
31 #define TIMER_MODE_WDT 3
32 #define TIMER_PRESCALE_SHIFT 0
33 #define TIMER_PRESCALE_65536 15
35 static void mt7620_wdt_ping(struct mt7620_wdt *priv)
39 val = (TIMER_FREQ / TIMER_PRESCALE) * priv->timeout;
45 writel(val, priv->regs + TIMER_LOAD);
48 static int mt7620_wdt_start(struct udevice *dev, u64 ms, ulong flags)
50 struct mt7620_wdt *priv = dev_get_priv(dev);
53 mt7620_wdt_ping(priv);
55 writel(TIMER_ENABLE | (TIMER_MODE_WDT << TIMER_MODE_SHIFT) |
56 (TIMER_PRESCALE_65536 << TIMER_PRESCALE_SHIFT),
57 priv->regs + TIMER_CTL);
62 static int mt7620_wdt_stop(struct udevice *dev)
64 struct mt7620_wdt *priv = dev_get_priv(dev);
66 mt7620_wdt_ping(priv);
68 clrbits_32(priv->regs + TIMER_CTL, TIMER_ENABLE);
73 static int mt7620_wdt_reset(struct udevice *dev)
75 struct mt7620_wdt *priv = dev_get_priv(dev);
77 mt7620_wdt_ping(priv);
82 static int mt7620_wdt_expire_now(struct udevice *dev, ulong flags)
84 struct mt7620_wdt *priv = dev_get_priv(dev);
86 mt7620_wdt_start(dev, 1, flags);
89 * 0 will disable the timer directly, a positive number must be used
90 * instead. Since the timer is a countdown timer, 1 (tick) is used.
92 * For a timer with input clock = 40MHz, 1 timer tick is short
93 * enough to trigger a timeout immediately.
95 * Restore prescale to 1, and load timer with 1 to trigger timeout.
97 writel(TIMER_ENABLE | (TIMER_MODE_WDT << TIMER_MODE_SHIFT),
98 priv->regs + TIMER_CTL);
99 writel(1, priv->regs + TIMER_LOAD);
104 static int mt7620_wdt_probe(struct udevice *dev)
106 struct mt7620_wdt *priv = dev_get_priv(dev);
107 struct reset_ctl reset_wdt;
110 ret = reset_get_by_index(dev, 0, &reset_wdt);
112 reset_deassert(&reset_wdt);
114 priv->regs = dev_remap_addr(dev);
118 mt7620_wdt_stop(dev);
123 static const struct wdt_ops mt7620_wdt_ops = {
124 .start = mt7620_wdt_start,
125 .reset = mt7620_wdt_reset,
126 .stop = mt7620_wdt_stop,
127 .expire_now = mt7620_wdt_expire_now,
130 static const struct udevice_id mt7620_wdt_ids[] = {
131 { .compatible = "mediatek,mt7620-wdt" },
135 U_BOOT_DRIVER(mt7620_wdt) = {
136 .name = "mt7620_wdt",
138 .of_match = mt7620_wdt_ids,
139 .probe = mt7620_wdt_probe,
140 .priv_auto = sizeof(struct mt7620_wdt),
141 .ops = &mt7620_wdt_ops,