drivers/watchdog/mpc8xxx_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
   4  *
   5  * Authors: Dave Updegraff <dave@cray.org>
   6  *          Kumar Gala <galak@kernel.crashing.org>
   7  *              Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org>
   8  *                              ..and from sc520_wdt
   9  * Copyright (c) 2008  MontaVista Software, Inc.
  10  *                     Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * Note: it appears that you can only actually ENABLE or DISABLE the thing
  13  * once after POR. Once enabled, you cannot disable, and vice versa.
  14  */
  15
  16 #include <linux/fs.h>
  17 #include <linux/init.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/module.h>
  22 #include <linux/watchdog.h>
  23 #include <linux/io.h>
  24 #include <linux/uaccess.h>
  25 #include <sysdev/fsl_soc.h>
  26
  27 #define WATCHDOG_TIMEOUT 10
  28
  29 struct mpc8xxx_wdt {
  30         __be32 res0;
  31         __be32 swcrr; /* System watchdog control register */
  32 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
  33 #define SWCRR_SWF  0x00000008 /* Software Watchdog Freeze (mpc8xx). */
  34 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
  35 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
  36 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
  37         __be32 swcnr; /* System watchdog count register */
  38         u8 res1[2];
  39         __be16 swsrr; /* System watchdog service register */
  40         u8 res2[0xF0];
  41 };
  42
  43 struct mpc8xxx_wdt_type {
  44         int prescaler;
  45         bool hw_enabled;
  46         u32 rsr_mask;
  47 };
  48
  49 struct mpc8xxx_wdt_ddata {
  50         struct mpc8xxx_wdt __iomem *base;
  51         struct watchdog_device wdd;
  52         spinlock_t lock;
  53         u16 swtc;
  54 };
  55
  56 static u16 timeout;
  57 module_param(timeout, ushort, 0);
  58 MODULE_PARM_DESC(timeout,
  59         "Watchdog timeout in seconds. (1<timeout<65535, default="
  60         __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
  61
  62 static bool reset = 1;
  63 module_param(reset, bool, 0);
  64 MODULE_PARM_DESC(reset,
  65         "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset");
  66
  67 static bool nowayout = WATCHDOG_NOWAYOUT;
  68 module_param(nowayout, bool, 0);
  69 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  70                  "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  71
  72 static void mpc8xxx_wdt_keepalive(struct mpc8xxx_wdt_ddata *ddata)
  73 {
  74         /* Ping the WDT */
  75         spin_lock(&ddata->lock);
  76         out_be16(&ddata->base->swsrr, 0x556c);
  77         out_be16(&ddata->base->swsrr, 0xaa39);
  78         spin_unlock(&ddata->lock);
  79 }
  80
  81 static int mpc8xxx_wdt_start(struct watchdog_device *w)
  82 {
  83         struct mpc8xxx_wdt_ddata *ddata =
  84                 container_of(w, struct mpc8xxx_wdt_ddata, wdd);
  85         u32 tmp = in_be32(&ddata->base->swcrr);
  86
  87         /* Good, fire up the show */
  88         tmp &= ~(SWCRR_SWTC | SWCRR_SWF | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR);
  89         tmp |= SWCRR_SWEN | SWCRR_SWPR | (ddata->swtc << 16);
  90
  91         if (reset)
  92                 tmp |= SWCRR_SWRI;
  93
  94         out_be32(&ddata->base->swcrr, tmp);
  95
  96         tmp = in_be32(&ddata->base->swcrr);
  97         if (!(tmp & SWCRR_SWEN))
  98                 return -EOPNOTSUPP;
  99
 100         ddata->swtc = tmp >> 16;
 101         set_bit(WDOG_HW_RUNNING, &ddata->wdd.status);
 102
 103         return 0;
 104 }
 105
 106 static int mpc8xxx_wdt_ping(struct watchdog_device *w)
 107 {
 108         struct mpc8xxx_wdt_ddata *ddata =
 109                 container_of(w, struct mpc8xxx_wdt_ddata, wdd);
 110
 111         mpc8xxx_wdt_keepalive(ddata);
 112         return 0;
 113 }
 114
 115 static struct watchdog_info mpc8xxx_wdt_info = {
 116         .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT,
 117         .firmware_version = 1,
 118         .identity = "MPC8xxx",
 119 };
 120
 121 static const struct watchdog_ops mpc8xxx_wdt_ops = {
 122         .owner = THIS_MODULE,
 123         .start = mpc8xxx_wdt_start,
 124         .ping = mpc8xxx_wdt_ping,
 125 };
 126
 127 static int mpc8xxx_wdt_probe(struct platform_device *ofdev)
 128 {
 129         int ret;
 130         struct resource *res;
 131         const struct mpc8xxx_wdt_type *wdt_type;
 132         struct mpc8xxx_wdt_ddata *ddata;
 133         u32 freq = fsl_get_sys_freq();
 134         bool enabled;
 135         struct device *dev = &ofdev->dev;
 136
 137         wdt_type = of_device_get_match_data(dev);
 138         if (!wdt_type)
 139                 return -EINVAL;
 140
 141         if (!freq || freq == -1)
 142                 return -EINVAL;
 143
 144         ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
 145         if (!ddata)
 146                 return -ENOMEM;
 147
 148         ddata->base = devm_platform_ioremap_resource(ofdev, 0);
 149         if (IS_ERR(ddata->base))
 150                 return PTR_ERR(ddata->base);
 151
 152         enabled = in_be32(&ddata->base->swcrr) & SWCRR_SWEN;
 153         if (!enabled && wdt_type->hw_enabled) {
 154                 dev_info(dev, "could not be enabled in software\n");
 155                 return -ENODEV;
 156         }
 157
 158         res = platform_get_resource(ofdev, IORESOURCE_MEM, 1);
 159         if (res) {
 160                 bool status;
 161                 u32 __iomem *rsr = ioremap(res->start, resource_size(res));
 162
 163                 if (!rsr)
 164                         return -ENOMEM;
 165
 166                 status = in_be32(rsr) & wdt_type->rsr_mask;
 167                 ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0;
 168                  /* clear reset status bits related to watchdog timer */
 169                 out_be32(rsr, wdt_type->rsr_mask);
 170                 iounmap(rsr);
 171
 172                 dev_info(dev, "Last boot was %scaused by watchdog\n",
 173                          status ? "" : "not ");
 174         }
 175
 176         spin_lock_init(&ddata->lock);
 177
 178         ddata->wdd.info = &mpc8xxx_wdt_info;
 179         ddata->wdd.ops = &mpc8xxx_wdt_ops;
 180
 181         ddata->wdd.timeout = WATCHDOG_TIMEOUT;
 182         watchdog_init_timeout(&ddata->wdd, timeout, dev);
 183
 184         watchdog_set_nowayout(&ddata->wdd, nowayout);
 185
 186         ddata->swtc = min(ddata->wdd.timeout * freq / wdt_type->prescaler,
 187                           0xffffU);
 188
 189         /*
 190          * If the watchdog was previously enabled or we're running on
 191          * MPC8xxx, we should ping the wdt from the kernel until the
 192          * userspace handles it.
 193          */
 194         if (enabled)
 195                 mpc8xxx_wdt_start(&ddata->wdd);
 196
 197         ddata->wdd.max_hw_heartbeat_ms = (ddata->swtc * wdt_type->prescaler) /
 198                                          (freq / 1000);
 199         ddata->wdd.min_timeout = ddata->wdd.max_hw_heartbeat_ms / 1000;
 200         if (ddata->wdd.timeout < ddata->wdd.min_timeout)
 201                 ddata->wdd.timeout = ddata->wdd.min_timeout;
 202
 203         ret = devm_watchdog_register_device(dev, &ddata->wdd);
 204         if (ret)
 205                 return ret;
 206
 207         dev_info(dev,
 208                  "WDT driver for MPC8xxx initialized. mode:%s timeout=%d sec\n",
 209                  reset ? "reset" : "interrupt", ddata->wdd.timeout);
 210
 211         platform_set_drvdata(ofdev, ddata);
 212         return 0;
 213 }
 214
 215 static const struct of_device_id mpc8xxx_wdt_match[] = {
 216         {
 217                 .compatible = "mpc83xx_wdt",
 218                 .data = &(struct mpc8xxx_wdt_type) {
 219                         .prescaler = 0x10000,
 220                         .rsr_mask = BIT(3), /* RSR Bit SWRS */
 221                 },
 222         },
 223         {
 224                 .compatible = "fsl,mpc8610-wdt",
 225                 .data = &(struct mpc8xxx_wdt_type) {
 226                         .prescaler = 0x10000,
 227                         .hw_enabled = true,
 228                         .rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */
 229                 },
 230         },
 231         {
 232                 .compatible = "fsl,mpc823-wdt",
 233                 .data = &(struct mpc8xxx_wdt_type) {
 234                         .prescaler = 0x800,
 235                         .hw_enabled = true,
 236                         .rsr_mask = BIT(28), /* RSR Bit SWRS */
 237                 },
 238         },
 239         {},
 240 };
 241 MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match);
 242
 243 static struct platform_driver mpc8xxx_wdt_driver = {
 244         .probe          = mpc8xxx_wdt_probe,
 245         .driver = {
 246                 .name = "mpc8xxx_wdt",
 247                 .of_match_table = mpc8xxx_wdt_match,
 248         },
 249 };
 250
 251 static int __init mpc8xxx_wdt_init(void)
 252 {
 253         return platform_driver_register(&mpc8xxx_wdt_driver);
 254 }
 255 arch_initcall(mpc8xxx_wdt_init);
 256
 257 static void __exit mpc8xxx_wdt_exit(void)
 258 {
 259         platform_driver_unregister(&mpc8xxx_wdt_driver);
 260 }
 261 module_exit(mpc8xxx_wdt_exit);
 262
 263 MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
 264 MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx "
 265                    "uProcessors");
 266 MODULE_LICENSE("GPL");