2 * watchdog.c - driver for i.mx on-chip watchdog
4 * Licensed under the GPL-2 or later.
10 #include <asm/arch/imx-regs.h>
12 struct watchdog_regs {
13 u16 wcr; /* Control */
14 u16 wsr; /* Service */
15 u16 wrsr; /* Reset Status */
18 #define WCR_WDZST 0x01
20 #define WCR_WDE 0x04 /* WDOG enable */
24 #define SET_WCR_WT(x) (x << 8)
26 #ifdef CONFIG_IMX_WATCHDOG
27 void hw_watchdog_reset(void)
29 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
31 writew(0x5555, &wdog->wsr);
32 writew(0xaaaa, &wdog->wsr);
35 void hw_watchdog_init(void)
37 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
41 * The timer watchdog can be set between
42 * 0.5 and 128 Seconds. If not defined
43 * in configuration file, sets 128 Seconds
45 #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
46 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
48 timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
49 writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
50 WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr);
55 void reset_cpu(ulong addr)
57 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
59 writew(WCR_WDE, &wdog->wcr);
60 writew(0x5555, &wdog->wsr);
61 writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
64 * spin for .5 seconds before reset