2 * watchdog.c - driver for i.mx on-chip watchdog
4 * Licensed under the GPL-2 or later.
14 #include <asm/arch/imx-regs.h>
15 #ifdef CONFIG_FSL_LSCH2
16 #include <asm/arch/immap_lsch2.h>
21 #define TIMEOUT_MAX 128000
22 #define TIMEOUT_MIN 500
24 static void imx_watchdog_expire_now(struct watchdog_regs *wdog, bool ext_reset)
29 wcr |= WCR_SRS; /* do not assert internal reset */
31 wcr |= WCR_WDA; /* do not assert external reset */
33 /* Write 3 times to ensure it works, due to IMX6Q errata ERR004346 */
34 writew(wcr, &wdog->wcr);
35 writew(wcr, &wdog->wcr);
36 writew(wcr, &wdog->wcr);
45 #if !defined(CONFIG_IMX_WATCHDOG) || \
46 (defined(CONFIG_IMX_WATCHDOG) && !CONFIG_IS_ENABLED(WDT))
47 void __attribute__((weak)) reset_cpu(ulong addr)
49 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
51 imx_watchdog_expire_now(wdog, true);
55 #if defined(CONFIG_IMX_WATCHDOG)
56 static void imx_watchdog_reset(struct watchdog_regs *wdog)
58 #ifndef CONFIG_WATCHDOG_RESET_DISABLE
59 writew(0x5555, &wdog->wsr);
60 writew(0xaaaa, &wdog->wsr);
61 #endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
64 static void imx_watchdog_init(struct watchdog_regs *wdog, bool ext_reset,
70 * The timer watchdog can be set between
71 * 0.5 and 128 Seconds. If not defined
72 * in configuration file, sets 128 Seconds
74 #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
75 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
78 timeout = max_t(u64, timeout, TIMEOUT_MIN);
79 timeout = min_t(u64, timeout, TIMEOUT_MAX);
80 timeout = lldiv(timeout, 500) - 1;
82 #ifdef CONFIG_FSL_LSCH2
83 wcr = (WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout;
85 wcr = WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_SRS |
86 WCR_WDA | SET_WCR_WT(timeout);
89 #endif /* CONFIG_FSL_LSCH2*/
90 writew(wcr, &wdog->wcr);
91 imx_watchdog_reset(wdog);
94 #if !CONFIG_IS_ENABLED(WDT)
95 void hw_watchdog_reset(void)
97 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
99 imx_watchdog_reset(wdog);
102 void hw_watchdog_init(void)
104 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
106 imx_watchdog_init(wdog, true, CONFIG_WATCHDOG_TIMEOUT_MSECS);
109 struct imx_wdt_priv {
114 static int imx_wdt_reset(struct udevice *dev)
116 struct imx_wdt_priv *priv = dev_get_priv(dev);
118 imx_watchdog_reset(priv->base);
123 static int imx_wdt_expire_now(struct udevice *dev, ulong flags)
125 struct imx_wdt_priv *priv = dev_get_priv(dev);
127 imx_watchdog_expire_now(priv->base, priv->ext_reset);
133 static int imx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
135 struct imx_wdt_priv *priv = dev_get_priv(dev);
137 imx_watchdog_init(priv->base, priv->ext_reset, timeout);
142 static int imx_wdt_probe(struct udevice *dev)
144 struct imx_wdt_priv *priv = dev_get_priv(dev);
146 priv->base = dev_read_addr_ptr(dev);
150 priv->ext_reset = dev_read_bool(dev, "fsl,ext-reset-output");
155 static const struct wdt_ops imx_wdt_ops = {
156 .start = imx_wdt_start,
157 .reset = imx_wdt_reset,
158 .expire_now = imx_wdt_expire_now,
161 static const struct udevice_id imx_wdt_ids[] = {
162 { .compatible = "fsl,imx21-wdt" },
166 U_BOOT_DRIVER(imx_wdt) = {
169 .of_match = imx_wdt_ids,
170 .probe = imx_wdt_probe,
172 .priv_auto_alloc_size = sizeof(struct imx_wdt_priv),
173 .flags = DM_FLAG_PRE_RELOC,