drivers/watchdog/designware_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <clk.h>
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <reset.h>
  10 #include <wdt.h>
  11 #include <asm/io.h>
  12 #include <linux/bitops.h>
  13
  14 #define DW_WDT_CR       0x00
  15 #define DW_WDT_TORR     0x04
  16 #define DW_WDT_CRR      0x0C
  17
  18 #define DW_WDT_CR_EN_OFFSET     0x00
  19 #define DW_WDT_CR_RMOD_OFFSET   0x01
  20 #define DW_WDT_CRR_RESTART_VAL  0x76
  21
  22 struct designware_wdt_priv {
  23         void __iomem    *base;
  24         unsigned int    clk_khz;
  25         struct reset_ctl_bulk resets;
  26 };
  27
  28 /*
  29  * Set the watchdog time interval.
  30  * Counter is 32 bit.
  31  */
  32 static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
  33                                      unsigned int timeout)
  34 {
  35         signed int i;
  36
  37         /* calculate the timeout range value */
  38         i = fls(timeout * clk_khz - 1) - 16;
  39         i = clamp(i, 0, 15);
  40
  41         writel(i | (i << 4), base + DW_WDT_TORR);
  42
  43         return 0;
  44 }
  45
  46 static void designware_wdt_enable(void __iomem *base)
  47 {
  48         writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR);
  49 }
  50
  51 static unsigned int designware_wdt_is_enabled(void __iomem *base)
  52 {
  53         return readl(base + DW_WDT_CR) & BIT(0);
  54 }
  55
  56 static void designware_wdt_reset_common(void __iomem *base)
  57 {
  58         if (designware_wdt_is_enabled(base))
  59                 /* restart the watchdog counter */
  60                 writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
  61 }
  62
  63 #if !CONFIG_IS_ENABLED(WDT)
  64 void hw_watchdog_reset(void)
  65 {
  66         designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
  67 }
  68
  69 void hw_watchdog_init(void)
  70 {
  71         /* reset to disable the watchdog */
  72         hw_watchdog_reset();
  73         /* set timer in miliseconds */
  74         designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
  75                                   CONFIG_DW_WDT_CLOCK_KHZ,
  76                                   CONFIG_WATCHDOG_TIMEOUT_MSECS);
  77         /* enable the watchdog */
  78         designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
  79         /* reset the watchdog */
  80         hw_watchdog_reset();
  81 }
  82 #else
  83 static int designware_wdt_reset(struct udevice *dev)
  84 {
  85         struct designware_wdt_priv *priv = dev_get_priv(dev);
  86
  87         designware_wdt_reset_common(priv->base);
  88
  89         return 0;
  90 }
  91
  92 static int designware_wdt_stop(struct udevice *dev)
  93 {
  94         struct designware_wdt_priv *priv = dev_get_priv(dev);
  95
  96         designware_wdt_reset(dev);
  97         writel(0, priv->base + DW_WDT_CR);
  98
  99         if (CONFIG_IS_ENABLED(DM_RESET)) {
 100                 int ret;
 101
 102                 ret = reset_assert_bulk(&priv->resets);
 103                 if (ret)
 104                         return ret;
 105
 106                 ret = reset_deassert_bulk(&priv->resets);
 107                 if (ret)
 108                         return ret;
 109         }
 110
 111         return 0;
 112 }
 113
 114 static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
 115 {
 116         struct designware_wdt_priv *priv = dev_get_priv(dev);
 117
 118         designware_wdt_stop(dev);
 119
 120         /* set timer in miliseconds */
 121         designware_wdt_settimeout(priv->base, priv->clk_khz, timeout);
 122
 123         designware_wdt_enable(priv->base);
 124
 125         /* reset the watchdog */
 126         return designware_wdt_reset(dev);
 127 }
 128
 129 static int designware_wdt_probe(struct udevice *dev)
 130 {
 131         struct designware_wdt_priv *priv = dev_get_priv(dev);
 132         __maybe_unused int ret;
 133
 134         priv->base = dev_remap_addr(dev);
 135         if (!priv->base)
 136                 return -EINVAL;
 137
 138 #if CONFIG_IS_ENABLED(CLK)
 139         struct clk clk;
 140
 141         ret = clk_get_by_index(dev, 0, &clk);
 142         if (ret)
 143                 return ret;
 144
 145         ret = clk_enable(&clk);
 146         if (ret)
 147                 goto err;
 148
 149         priv->clk_khz = clk_get_rate(&clk) / 1000;
 150         if (!priv->clk_khz) {
 151                 ret = -EINVAL;
 152                 goto err;
 153         }
 154 #else
 155         priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
 156 #endif
 157
 158         if (CONFIG_IS_ENABLED(DM_RESET)) {
 159                 ret = reset_get_bulk(dev, &priv->resets);
 160                 if (ret)
 161                         goto err;
 162
 163                 ret = reset_deassert_bulk(&priv->resets);
 164                 if (ret)
 165                         goto err;
 166         }
 167
 168         /* reset to disable the watchdog */
 169         return designware_wdt_stop(dev);
 170
 171 err:
 172 #if CONFIG_IS_ENABLED(CLK)
 173         clk_free(&clk);
 174 #endif
 175         return ret;
 176 }
 177
 178 static const struct wdt_ops designware_wdt_ops = {
 179         .start = designware_wdt_start,
 180         .reset = designware_wdt_reset,
 181         .stop = designware_wdt_stop,
 182 };
 183
 184 static const struct udevice_id designware_wdt_ids[] = {
 185         { .compatible = "snps,dw-wdt"},
 186         {}
 187 };
 188
 189 U_BOOT_DRIVER(designware_wdt) = {
 190         .name = "designware_wdt",
 191         .id = UCLASS_WDT,
 192         .of_match = designware_wdt_ids,
 193         .priv_auto      = sizeof(struct designware_wdt_priv),
 194         .probe = designware_wdt_probe,
 195         .ops = &designware_wdt_ops,
 196         .flags = DM_FLAG_PRE_RELOC,
 197 };
 198 #endif