1 /* cpwd.c - driver implementation for hardware watchdog
2 * timers found on Sun Microsystems CP1400 and CP1500 boards.
4 * This device supports both the generic Linux watchdog
5 * interface and Solaris-compatible ioctls as best it is
8 * NOTE: CP1400 systems appear to have a defective intr_mask
9 * register on the PLD, preventing the disabling of
10 * timer interrupts. We use a timer to periodically
11 * reset 'stopped' watchdogs on affected platforms.
13 * Copyright (c) 2000 Eric Brower (ebrower@usa.net)
14 * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/errno.h>
23 #include <linux/major.h>
24 #include <linux/init.h>
25 #include <linux/miscdevice.h>
26 #include <linux/interrupt.h>
27 #include <linux/ioport.h>
28 #include <linux/timer.h>
29 #include <linux/slab.h>
30 #include <linux/mutex.h>
33 #include <linux/of_device.h>
34 #include <linux/uaccess.h>
37 #include <asm/watchdog.h>
39 #define DRIVER_NAME "cpwd"
41 #define WD_OBPNAME "watchdog"
42 #define WD_BADMODEL "SUNW,501-5336"
43 #define WD_BTIMEOUT (jiffies + (HZ * 1000))
44 #define WD_BLIMIT 0xFFFF
50 /* Internal driver definitions. */
59 #define WD_STAT_INIT 0x01 /* Watchdog timer is initialized */
60 #define WD_STAT_BSTOP 0x02 /* Watchdog timer is brokenstopped */
61 #define WD_STAT_SVCD 0x04 /* Watchdog interrupt occurred */
63 /* Register value definitions
65 #define WD0_INTR_MASK 0x01 /* Watchdog device interrupt masks */
66 #define WD1_INTR_MASK 0x02
67 #define WD2_INTR_MASK 0x04
69 #define WD_S_RUNNING 0x01 /* Watchdog device status running */
70 #define WD_S_EXPIRED 0x02 /* Watchdog device status expired */
78 unsigned long timeout;
85 struct miscdevice misc;
93 static DEFINE_MUTEX(cpwd_mutex);
94 static struct cpwd *cpwd_device;
96 /* Sun uses Altera PLD EPF8820ATC144-4
97 * providing three hardware watchdogs:
99 * 1) RIC - sends an interrupt when triggered
100 * 2) XIR - asserts XIR_B_RESET when triggered, resets CPU
101 * 3) POR - asserts POR_B_RESET when triggered, resets CPU, backplane, board
103 *** Timer register block definition (struct wd_timer_regblk)
105 * dcntr and limit registers (halfword access):
106 * -------------------
107 * | 15 | ...| 1 | 0 |
108 * -------------------
110 * -------------------
111 * dcntr - Current 16-bit downcounter value.
112 * When downcounter reaches '0' watchdog expires.
113 * Reading this register resets downcounter with
115 * limit - 16-bit countdown value in 1/10th second increments.
116 * Writing this register begins countdown with input value.
117 * Reading from this register does not affect counter.
118 * NOTES: After watchdog reset, dcntr and limit contain '1'
120 * status register (byte access):
121 * ---------------------------
122 * | 7 | ... | 2 | 1 | 0 |
123 * --------------+------------
124 * |- UNUSED -| EXP | RUN |
125 * ---------------------------
126 * status- Bit 0 - Watchdog is running
127 * Bit 1 - Watchdog has expired
129 *** PLD register block definition (struct wd_pld_regblk)
131 * intr_mask register (byte access):
132 * ---------------------------------
133 * | 7 | ... | 3 | 2 | 1 | 0 |
134 * +-------------+------------------
135 * |- UNUSED -| WD3 | WD2 | WD1 |
136 * ---------------------------------
137 * WD3 - 1 == Interrupt disabled for watchdog 3
138 * WD2 - 1 == Interrupt disabled for watchdog 2
139 * WD1 - 1 == Interrupt disabled for watchdog 1
141 * pld_status register (byte access):
142 * UNKNOWN, MAGICAL MYSTERY REGISTER
145 #define WD_TIMER_REGSZ 16
147 #define WD1_OFF (WD_TIMER_REGSZ * 1)
148 #define WD2_OFF (WD_TIMER_REGSZ * 2)
149 #define PLD_OFF (WD_TIMER_REGSZ * 3)
151 #define WD_DCNTR 0x00
152 #define WD_LIMIT 0x04
153 #define WD_STATUS 0x08
155 #define PLD_IMASK (PLD_OFF + 0x00)
156 #define PLD_STATUS (PLD_OFF + 0x04)
158 static struct timer_list cpwd_timer;
160 static int wd0_timeout;
161 static int wd1_timeout;
162 static int wd2_timeout;
164 module_param(wd0_timeout, int, 0);
165 MODULE_PARM_DESC(wd0_timeout, "Default watchdog0 timeout in 1/10secs");
166 module_param(wd1_timeout, int, 0);
167 MODULE_PARM_DESC(wd1_timeout, "Default watchdog1 timeout in 1/10secs");
168 module_param(wd2_timeout, int, 0);
169 MODULE_PARM_DESC(wd2_timeout, "Default watchdog2 timeout in 1/10secs");
171 MODULE_AUTHOR("Eric Brower <ebrower@usa.net>");
172 MODULE_DESCRIPTION("Hardware watchdog driver for Sun Microsystems CP1400/1500");
173 MODULE_LICENSE("GPL");
174 MODULE_SUPPORTED_DEVICE("watchdog");
176 static void cpwd_writew(u16 val, void __iomem *addr)
178 writew(cpu_to_le16(val), addr);
180 static u16 cpwd_readw(void __iomem *addr)
182 u16 val = readw(addr);
184 return le16_to_cpu(val);
187 static void cpwd_writeb(u8 val, void __iomem *addr)
192 static u8 cpwd_readb(void __iomem *addr)
197 /* Enable or disable watchdog interrupts
198 * Because of the CP1400 defect this should only be
199 * called during initialzation or by wd_[start|stop]timer()
201 * index - sub-device index, or -1 for 'all'
202 * enable - non-zero to enable interrupts, zero to disable
204 static void cpwd_toggleintr(struct cpwd *p, int index, int enable)
206 unsigned char curregs = cpwd_readb(p->regs + PLD_IMASK);
207 unsigned char setregs =
209 (WD0_INTR_MASK | WD1_INTR_MASK | WD2_INTR_MASK) :
210 (p->devs[index].intr_mask);
212 if (enable == WD_INTR_ON)
217 cpwd_writeb(curregs, p->regs + PLD_IMASK);
220 /* Restarts timer with maximum limit value and
221 * does not unset 'brokenstop' value.
223 static void cpwd_resetbrokentimer(struct cpwd *p, int index)
225 cpwd_toggleintr(p, index, WD_INTR_ON);
226 cpwd_writew(WD_BLIMIT, p->devs[index].regs + WD_LIMIT);
229 /* Timer method called to reset stopped watchdogs--
230 * because of the PLD bug on CP1400, we cannot mask
231 * interrupts within the PLD so me must continually
232 * reset the timers ad infinitum.
234 static void cpwd_brokentimer(unsigned long data)
236 struct cpwd *p = (struct cpwd *) data;
239 /* kill a running timer instance, in case we
240 * were called directly instead of by kernel timer
242 if (timer_pending(&cpwd_timer))
243 del_timer(&cpwd_timer);
245 for (id = 0; id < WD_NUMDEVS; id++) {
246 if (p->devs[id].runstatus & WD_STAT_BSTOP) {
248 cpwd_resetbrokentimer(p, id);
253 /* there is at least one timer brokenstopped-- reschedule */
254 cpwd_timer.expires = WD_BTIMEOUT;
255 add_timer(&cpwd_timer);
259 /* Reset countdown timer with 'limit' value and continue countdown.
260 * This will not start a stopped timer.
262 static void cpwd_pingtimer(struct cpwd *p, int index)
264 if (cpwd_readb(p->devs[index].regs + WD_STATUS) & WD_S_RUNNING)
265 cpwd_readw(p->devs[index].regs + WD_DCNTR);
268 /* Stop a running watchdog timer-- the timer actually keeps
269 * running, but the interrupt is masked so that no action is
270 * taken upon expiration.
272 static void cpwd_stoptimer(struct cpwd *p, int index)
274 if (cpwd_readb(p->devs[index].regs + WD_STATUS) & WD_S_RUNNING) {
275 cpwd_toggleintr(p, index, WD_INTR_OFF);
278 p->devs[index].runstatus |= WD_STAT_BSTOP;
279 cpwd_brokentimer((unsigned long) p);
284 /* Start a watchdog timer with the specified limit value
285 * If the watchdog is running, it will be restarted with
286 * the provided limit value.
288 * This function will enable interrupts on the specified
291 static void cpwd_starttimer(struct cpwd *p, int index)
294 p->devs[index].runstatus &= ~WD_STAT_BSTOP;
296 p->devs[index].runstatus &= ~WD_STAT_SVCD;
298 cpwd_writew(p->devs[index].timeout, p->devs[index].regs + WD_LIMIT);
299 cpwd_toggleintr(p, index, WD_INTR_ON);
302 static int cpwd_getstatus(struct cpwd *p, int index)
304 unsigned char stat = cpwd_readb(p->devs[index].regs + WD_STATUS);
305 unsigned char intr = cpwd_readb(p->devs[index].regs + PLD_IMASK);
306 unsigned char ret = WD_STOPPED;
308 /* determine STOPPED */
312 /* determine EXPIRED vs FREERUN vs RUNNING */
313 else if (WD_S_EXPIRED & stat) {
315 } else if (WD_S_RUNNING & stat) {
316 if (intr & p->devs[index].intr_mask) {
319 /* Fudge WD_EXPIRED status for defective CP1400--
320 * IF timer is running
321 * AND brokenstop is set
322 * AND an interrupt has been serviced
325 * IF timer is running
326 * AND brokenstop is set
327 * AND no interrupt has been serviced
331 (p->devs[index].runstatus & WD_STAT_BSTOP)) {
332 if (p->devs[index].runstatus & WD_STAT_SVCD) {
335 /* we could as well pretend
345 /* determine SERVICED */
346 if (p->devs[index].runstatus & WD_STAT_SVCD)
352 static irqreturn_t cpwd_interrupt(int irq, void *dev_id)
354 struct cpwd *p = dev_id;
356 /* Only WD0 will interrupt-- others are NMI and we won't
359 spin_lock_irq(&p->lock);
361 cpwd_stoptimer(p, WD0_ID);
362 p->devs[WD0_ID].runstatus |= WD_STAT_SVCD;
364 spin_unlock_irq(&p->lock);
369 static int cpwd_open(struct inode *inode, struct file *f)
371 struct cpwd *p = cpwd_device;
373 mutex_lock(&cpwd_mutex);
374 switch (iminor(inode)) {
381 mutex_unlock(&cpwd_mutex);
385 /* Register IRQ on first open of device */
386 if (!p->initialized) {
387 if (request_irq(p->irq, &cpwd_interrupt,
388 IRQF_SHARED, DRIVER_NAME, p)) {
389 pr_err("Cannot register IRQ %d\n", p->irq);
390 mutex_unlock(&cpwd_mutex);
393 p->initialized = true;
396 mutex_unlock(&cpwd_mutex);
398 return nonseekable_open(inode, f);
401 static int cpwd_release(struct inode *inode, struct file *file)
406 static long cpwd_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
408 static const struct watchdog_info info = {
409 .options = WDIOF_SETTIMEOUT,
410 .firmware_version = 1,
411 .identity = DRIVER_NAME,
413 void __user *argp = (void __user *)arg;
414 struct inode *inode = file->f_path.dentry->d_inode;
415 int index = iminor(inode) - WD0_MINOR;
416 struct cpwd *p = cpwd_device;
420 /* Generic Linux IOCTLs */
421 case WDIOC_GETSUPPORT:
422 if (copy_to_user(argp, &info, sizeof(struct watchdog_info)))
426 case WDIOC_GETSTATUS:
427 case WDIOC_GETBOOTSTATUS:
428 if (put_user(0, (int __user *)argp))
432 case WDIOC_KEEPALIVE:
433 cpwd_pingtimer(p, index);
436 case WDIOC_SETOPTIONS:
437 if (copy_from_user(&setopt, argp, sizeof(unsigned int)))
440 if (setopt & WDIOS_DISABLECARD) {
443 cpwd_stoptimer(p, index);
444 } else if (setopt & WDIOS_ENABLECARD) {
445 cpwd_starttimer(p, index);
451 /* Solaris-compatible IOCTLs */
453 setopt = cpwd_getstatus(p, index);
454 if (copy_to_user(argp, &setopt, sizeof(unsigned int)))
459 cpwd_starttimer(p, index);
466 cpwd_stoptimer(p, index);
476 static long cpwd_compat_ioctl(struct file *file, unsigned int cmd,
479 int rval = -ENOIOCTLCMD;
482 /* solaris ioctls are specific to this driver */
486 mutex_lock(&cpwd_mutex);
487 rval = cpwd_ioctl(file, cmd, arg);
488 mutex_unlock(&cpwd_mutex);
491 /* everything else is handled by the generic compat layer */
499 static ssize_t cpwd_write(struct file *file, const char __user *buf,
500 size_t count, loff_t *ppos)
502 struct inode *inode = file->f_path.dentry->d_inode;
503 struct cpwd *p = cpwd_device;
504 int index = iminor(inode);
507 cpwd_pingtimer(p, index);
514 static ssize_t cpwd_read(struct file *file, char __user *buffer,
515 size_t count, loff_t *ppos)
520 static const struct file_operations cpwd_fops = {
521 .owner = THIS_MODULE,
522 .unlocked_ioctl = cpwd_ioctl,
523 .compat_ioctl = cpwd_compat_ioctl,
527 .release = cpwd_release,
531 static int __devinit cpwd_probe(struct platform_device *op)
533 struct device_node *options;
534 const char *str_prop;
535 const void *prop_val;
536 int i, err = -EINVAL;
542 p = kzalloc(sizeof(*p), GFP_KERNEL);
545 pr_err("Unable to allocate struct cpwd\n");
549 p->irq = op->archdata.irqs[0];
551 spin_lock_init(&p->lock);
553 p->regs = of_ioremap(&op->resource[0], 0,
554 4 * WD_TIMER_REGSZ, DRIVER_NAME);
556 pr_err("Unable to map registers\n");
560 options = of_find_node_by_path("/options");
563 pr_err("Unable to find /options node\n");
567 prop_val = of_get_property(options, "watchdog-enable?", NULL);
568 p->enabled = (prop_val ? true : false);
570 prop_val = of_get_property(options, "watchdog-reboot?", NULL);
571 p->reboot = (prop_val ? true : false);
573 str_prop = of_get_property(options, "watchdog-timeout", NULL);
575 p->timeout = simple_strtoul(str_prop, NULL, 10);
577 /* CP1400s seem to have broken PLD implementations-- the
578 * interrupt_mask register cannot be written, so no timer
579 * interrupts can be masked within the PLD.
581 str_prop = of_get_property(op->dev.of_node, "model", NULL);
582 p->broken = (str_prop && !strcmp(str_prop, WD_BADMODEL));
585 cpwd_toggleintr(p, -1, WD_INTR_OFF);
587 for (i = 0; i < WD_NUMDEVS; i++) {
588 static const char *cpwd_names[] = { "RIC", "XIR", "POR" };
589 static int *parms[] = { &wd0_timeout,
592 struct miscdevice *mp = &p->devs[i].misc;
594 mp->minor = WD0_MINOR + i;
595 mp->name = cpwd_names[i];
596 mp->fops = &cpwd_fops;
598 p->devs[i].regs = p->regs + (i * WD_TIMER_REGSZ);
599 p->devs[i].intr_mask = (WD0_INTR_MASK << i);
600 p->devs[i].runstatus &= ~WD_STAT_BSTOP;
601 p->devs[i].runstatus |= WD_STAT_INIT;
602 p->devs[i].timeout = p->timeout;
604 p->devs[i].timeout = *parms[i];
606 err = misc_register(&p->devs[i].misc);
608 pr_err("Could not register misc device for dev %d\n",
615 init_timer(&cpwd_timer);
616 cpwd_timer.function = cpwd_brokentimer;
617 cpwd_timer.data = (unsigned long) p;
618 cpwd_timer.expires = WD_BTIMEOUT;
620 pr_info("PLD defect workaround enabled for model %s\n",
624 dev_set_drvdata(&op->dev, p);
632 for (i--; i >= 0; i--)
633 misc_deregister(&p->devs[i].misc);
636 of_iounmap(&op->resource[0], p->regs, 4 * WD_TIMER_REGSZ);
643 static int __devexit cpwd_remove(struct platform_device *op)
645 struct cpwd *p = dev_get_drvdata(&op->dev);
648 for (i = 0; i < WD_NUMDEVS; i++) {
649 misc_deregister(&p->devs[i].misc);
652 cpwd_stoptimer(p, i);
653 if (p->devs[i].runstatus & WD_STAT_BSTOP)
654 cpwd_resetbrokentimer(p, i);
659 del_timer_sync(&cpwd_timer);
664 of_iounmap(&op->resource[0], p->regs, 4 * WD_TIMER_REGSZ);
672 static const struct of_device_id cpwd_match[] = {
678 MODULE_DEVICE_TABLE(of, cpwd_match);
680 static struct platform_driver cpwd_driver = {
683 .owner = THIS_MODULE,
684 .of_match_table = cpwd_match,
687 .remove = __devexit_p(cpwd_remove),
690 module_platform_driver(cpwd_driver);